[thirdparty/gcc.git] / gcc / config / i386 / driver-i386.c

/* Subroutines for the gcc driver.
   Copyright (C) 2006, 2007 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <stdlib.h>

const char *host_detect_local_cpu (int argc, const char **argv);

#ifdef __GNUC__
#include "cpuid.h"

/* Returns parameters that describe L1_ASSOC associative cache of size
   L1_SIZEKB with lines of size L1_LINE.  */

static char *
describe_cache (unsigned l1_sizekb, unsigned l1_line,
		unsigned l1_assoc ATTRIBUTE_UNUSED, unsigned l2_sizekb)
{
  char size[100], line[100], size2[100];

  /* At the moment, gcc middle-end does not use the information about the
     associativity of the cache.  */

  sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
  sprintf (line, "--param l1-cache-line-size=%u", l1_line);
  sprintf (size2, "--param l2-cache-size=%u", l2_sizekb);

  return concat (size, " ", line, " ", size2, " ", NULL);
}

static void
decode_l2_cache (unsigned *l2_size, unsigned *l2_line, unsigned *l2_assoc)
{
  unsigned eax, ebx, ecx, edx, assoc;

  __cpuid (0x80000006, eax, ebx, ecx, edx);

  *l2_size = (ecx >> 16) & 0xffff;
  *l2_line = ecx & 0xff;
  assoc = (ecx >> 12) & 0xf;
  if (assoc == 6)
    assoc = 8;
  else if (assoc == 8)
    assoc = 16;
  else if (assoc >= 0xa && assoc <= 0xc)
    assoc = 32 + (assoc - 0xa) * 16;
  else if (assoc >= 0xd && assoc <= 0xe)
    assoc = 96 + (assoc - 0xd) * 32;
  *l2_assoc = assoc;
}

/* Returns the description of caches for an AMD processor.  */

static char *
detect_caches_amd (unsigned max_ext_level)
{
  unsigned eax, ebx, ecx, edx;
  unsigned l1_sizekb, l1_line, l1_assoc;
  unsigned l2_sizekb, l2_line, l2_assoc;

  if (max_ext_level < 0x80000005)
    return (char *) "";

  __cpuid (0x80000005, eax, ebx, ecx, edx);

  l1_line = ecx & 0xff;
  l1_sizekb = (ecx >> 24) & 0xff;
  l1_assoc = (ecx >> 16) & 0xff;

  if (max_ext_level >= 0x80000006)
    decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);

  return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
}

/* Stores the size of the L1/2 cache and cache line, and the associativity
   of the cache according to REG to L1_SIZEKB, L1_LINE, L1_ASSOC and
   L2_SIZEKB. */

static void
decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
		     unsigned *l1_assoc, unsigned *l2_sizekb,
		     unsigned *l2_line, unsigned *l2_assoc)
{
  unsigned i, val;

  if (((reg >> 31) & 1) != 0)
    return;

  for (i = 0; i < 4; i++)
    {
      val = reg & 0xff;
      reg >>= 8;

      switch (val)
	{
	case 0xa:
	  *l1_sizekb = 8;
	  *l1_line = 32;
	  *l1_assoc = 2;
	  break;
	case 0xc:
	  *l1_sizekb = 16;
	  *l1_line = 32;
	  *l1_assoc = 4;
	  break;
	case 0x2c:
	  *l1_sizekb = 32;
	  *l1_line = 64;
	  *l1_assoc = 8;
	  break;
	case 0x39:
	  *l2_sizekb = 128;
	  *l2_line = 64;
	  *l2_assoc = 4;
	  break;
	case 0x3a:
	  *l2_sizekb = 192;
	  *l2_line = 64;
	  *l2_assoc = 6;
	  break;
	case 0x3b:
	  *l2_sizekb = 128;
	  *l2_line = 64;
	  *l2_assoc = 2;
	  break;
	case 0x3c:
	  *l2_sizekb = 256;
	  *l2_line = 64;
	  *l2_assoc = 4;
	  break;
	case 0x3d:
	  *l2_sizekb = 384;
	  *l2_line = 64;
	  *l2_assoc = 6;
	  break;
	case 0x3e:
	  *l2_sizekb = 512;
	  *l2_line = 64;
	  *l2_assoc = 4;
	  break;
	case 0x41:
	  *l2_sizekb = 128;
	  *l2_line = 32;
	  *l2_assoc = 4;
	  break;
	case 0x42:
	  *l2_sizekb = 256;
	  *l2_line = 32;
	  *l2_assoc = 4;
	  break;
	case 0x43:
	  *l2_sizekb = 512;
	  *l2_line = 32;
	  *l2_assoc = 4;
	  break;
	case 0x44:
	  *l2_sizekb = 1024;
	  *l2_line = 32;
	  *l2_assoc = 4;
	  break;
	case 0x45:
	  *l2_sizekb = 2048;
	  *l2_line = 32;
	  *l2_assoc = 4;
	  break;
	case 0x49:
	  *l2_sizekb = 4096;
	  *l2_line = 64;
	  *l2_assoc = 16;
	  break;
	case 0x60:
	  *l1_sizekb = 16;
	  *l1_line = 64;
	  *l1_assoc = 8;
	  break;
	case 0x66:
	  *l1_sizekb = 8;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;
	case 0x67:
	  *l1_sizekb = 16;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;
	case 0x68:
	  *l1_sizekb = 32;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;
	case 0x78:
	  *l2_sizekb = 1024;
	  *l2_line = 64;
	  *l2_assoc = 4;
	  break;
	case 0x79:
	  *l2_sizekb = 128;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;
	case 0x7a:
	  *l2_sizekb = 256;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;
	case 0x7b:
	  *l2_sizekb = 512;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;
	case 0x7c:
	  *l2_sizekb = 1024;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;
	case 0x7d:
	  *l2_sizekb = 2048;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;
	case 0x7f:
	  *l2_sizekb = 512;
	  *l2_line = 64;
	  *l2_assoc = 2;
	  break;
	case 0x82:
	  *l2_sizekb = 256;
	  *l2_line = 32;
	  *l2_assoc = 8;
	  break;
	case 0x83:
	  *l2_sizekb = 512;
	  *l2_line = 32;
	  *l2_assoc = 8;
	  break;
	case 0x84:
	  *l2_sizekb = 1024;
	  *l2_line = 32;
	  *l2_assoc = 8;
	  break;
	case 0x85:
	  *l2_sizekb = 2048;
	  *l2_line = 32;
	  *l2_assoc = 8;
	  break;
	case 0x86:
	  *l2_sizekb = 512;
	  *l2_line = 64;
	  *l2_assoc = 4;
	  break;
	case 0x87:
	  *l2_sizekb = 1024;
	  *l2_line = 64;
	  *l2_assoc = 8;
	  break;

	default:
	  break;
	}
    }
}

/* Returns the description of caches for an intel processor.  */

static char *
detect_caches_intel (unsigned max_level, unsigned max_ext_level)
{
  unsigned eax, ebx, ecx, edx;
  unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
  unsigned l2_sizekb = 0, l2_line = 0, l2_assoc = 0;

  if (max_level < 2)
    return (char *) "";

  __cpuid (2, eax, ebx, ecx, edx);

  decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc,
      &l2_sizekb, &l2_line, &l2_assoc);
  decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc,
      &l2_sizekb, &l2_line, &l2_assoc);
  decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc,
      &l2_sizekb, &l2_line, &l2_assoc);
  decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc,
      &l2_sizekb, &l2_line, &l2_assoc);

  if (!l1_sizekb)
    return (char *) "";

  /* Newer Intel CPUs are equipped with AMD style L2 cache info */
  if (max_ext_level >= 0x80000006)
    decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);

  return describe_cache (l1_sizekb, l1_line, assoc, l2_sizekb);
}

/* This will be called by the spec parser in gcc.c when it sees
   a %:local_cpu_detect(args) construct.  Currently it will be called
   with either "arch" or "tune" as argument depending on if -march=native
   or -mtune=native is to be substituted.

   It returns a string containing new command line parameters to be
   put at the place of the above two options, depending on what CPU
   this is executed.  E.g. "-march=k8" on an AMD64 machine
   for -march=native.

   ARGC and ARGV are set depending on the actual arguments given
   in the spec.  */

const char *host_detect_local_cpu (int argc, const char **argv)
{
  enum processor_type processor = PROCESSOR_I386;
  const char *cpu = "i386";

  const char *cache = "";
  const char *options = "";

 unsigned int eax, ebx, ecx, edx;

  unsigned int max_level, ext_level;
  unsigned int vendor;
  unsigned int family;

  unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
  unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;

  /* Extended features */
  unsigned int has_lahf_lm = 0, has_sse4a = 0;
  unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;

  bool arch;

  if (argc < 1)
    return NULL;

  arch = !strcmp (argv[0], "arch");

  if (!arch && strcmp (argv[0], "tune"))
    return NULL;

  max_level = __get_cpuid_max (0, &vendor);
  if (max_level < 1)
    goto done;

  __cpuid (1, eax, ebx, ecx, edx);

  /* We don't care for extended family.  */
  family = (eax >> 8) & 0x0f;

  has_sse3 = ecx & bit_SSE3;
  has_ssse3 = ecx & bit_SSSE3;
  has_cmpxchg16b = ecx & bit_CMPXCHG16B;

  has_cmpxchg8b = edx & bit_CMPXCHG8B;
  has_cmov = edx & bit_CMOV;
  has_mmx = edx & bit_MMX;
  has_sse = edx & bit_SSE;
  has_sse2 = edx & bit_SSE2;

  /* Check cpuid level of extended features.  */
  __cpuid (0x80000000, ext_level, ebx, ecx, edx);

  if (ext_level > 0x80000000)
    {
      __cpuid (0x80000001, eax, ebx, ecx, edx);

      has_lahf_lm = ecx & bit_LAHF_LM;
      has_sse4a = ecx & bit_SSE4a;

      has_longmode = edx & bit_LM;
      has_3dnowp = edx & bit_3DNOWP;
      has_3dnow = edx & bit_3DNOW;
    }

  if (!arch)
    {
      if (vendor == *(unsigned int*) "Auth")
	cache = detect_caches_amd (ext_level);
      else if (vendor == *(unsigned int*) "Genu")
	cache = detect_caches_intel (max_level, ext_level);
    }

  if (vendor == *(unsigned int*) "Auth")
    {
      processor = PROCESSOR_PENTIUM;

      if (has_mmx)
	processor = PROCESSOR_K6;
      if (has_3dnowp)
	processor = PROCESSOR_ATHLON;
      if (has_sse2 || has_longmode)
	processor = PROCESSOR_K8;
      if (has_sse4a)
	processor = PROCESSOR_AMDFAM10;
    }
  else if (vendor == *(unsigned int*) "Geod")
    processor = PROCESSOR_GEODE;
  else
    {
      switch (family)
	{
	case 4:
	  processor = PROCESSOR_I486;
	  break;
	case 5:
	  processor = PROCESSOR_PENTIUM;
	  break;
	case 6:
	  processor = PROCESSOR_PENTIUMPRO;
	  break;
	case 15:
	  processor = PROCESSOR_PENTIUM4;
	  break;
	default:
	  /* We have no idea.  */
	  processor = PROCESSOR_GENERIC32;
	}
    }

  switch (processor)
    {
    case PROCESSOR_I386:
      /* Default.  */
      break;
    case PROCESSOR_I486:
      cpu = "i486";
      break;
    case PROCESSOR_PENTIUM:
      if (arch && has_mmx)
	cpu = "pentium-mmx";
      else
	cpu = "pentium";
      break;
    case PROCESSOR_PENTIUMPRO:
      if (has_longmode)
	/* It is Core 2 Duo.  */
	cpu = "core2";
      else if (arch)
	{
	  if (has_sse3)
	    /* It is Core Duo.  */
	    cpu = "prescott";
	  else if (has_sse2)
	    /* It is Pentium M.  */
	    cpu = "pentium-m";
	  else if (has_sse)
	    /* It is Pentium III.  */
	    cpu = "pentium3";
	  else if (has_mmx)
	    /* It is Pentium II.  */
	    cpu = "pentium2";
	  else
	    /* Default to Pentium Pro.  */
	    cpu = "pentiumpro";
	}
      else
	/* For -mtune, we default to -mtune=generic.  */
	cpu = "generic";
      break;
    case PROCESSOR_PENTIUM4:
      if (has_sse3)
	{
	  if (has_longmode)
	    cpu = "nocona";
	  else
	    cpu = "prescott";
	}
      else
	cpu = "pentium4";
      break;
    case PROCESSOR_GEODE:
      cpu = "geode";
      break;
    case PROCESSOR_K6:
      if (arch && has_3dnow)
	cpu = "k6-3";
      else
	cpu = "k6";
      break;
    case PROCESSOR_ATHLON:
      if (arch && has_sse)
	cpu = "athlon-4";
      else
	cpu = "athlon";
      break;
    case PROCESSOR_K8:
      if (arch && has_sse3)
	cpu = "k8-sse3";
      else
	cpu = "k8";
      break;
    case PROCESSOR_AMDFAM10:
      cpu = "amdfam10";
      break;

    default:
      /* Use something reasonable.  */
      if (arch)
	{
	  if (has_ssse3)
	    cpu = "core2";
	  else if (has_sse3)
	    {
	      if (has_longmode)
		cpu = "nocona";
	      else
		cpu = "prescott";
	    }
	  else if (has_sse2)
	    cpu = "pentium4";
	  else if (has_cmov)
	    cpu = "pentiumpro";
	  else if (has_mmx)
	    cpu = "pentium-mmx";
	  else if (has_cmpxchg8b)
	    cpu = "pentium";
	}
      else
	cpu = "generic";
    }

  if (arch)
    {
      if (has_cmpxchg16b)
	options = concat (options, "-mcx16 ", NULL);
      if (has_lahf_lm)
	options = concat (options, "-msahf ", NULL);
    }

done:
  return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
}
#else

/* If we aren't compiling with GCC we just provide a minimal
   default value.  */

const char *host_detect_local_cpu (int argc, const char **argv)
{
  const char *cpu;
  bool arch;

  if (argc < 1)
    return NULL;

  arch = !strcmp (argv[0], "arch");

  if (!arch && strcmp (argv[0], "tune"))
    return NULL;
  
  if (arch)
    {
      /* FIXME: i386 is wrong for 64bit compiler.  How can we tell if
	 we are generating 64bit or 32bit code?  */
      cpu = "i386";
    }
  else
    cpu = "generic";

  return concat ("-m", argv[0], "=", cpu, NULL);
}
#endif /* __GNUC__ */
Commit	Line	Data
fa959ce4	1	/* Subroutines for the gcc driver.
35a63f21	2	Copyright (C) 2006, 2007 Free Software Foundation, Inc.
fa959ce4 MM	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
2f83c7d6	8	the Free Software Foundation; either version 3, or (at your option)
fa959ce4 MM	9	any later version.
	10
	11	GCC is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	<http://www.gnu.org/licenses/>. */
fa959ce4 MM	19
	20	#include "config.h"
	21	#include "system.h"
edccdcb1 L	22	#include "coretypes.h"
edccdcb1 L	23	#include "tm.h"
fa959ce4 MM	24	#include <stdlib.h>
fa959ce4 MM	25
895016f6 UB	26	const char host_detect_local_cpu (int argc, const char *argv);
895016f6 UB	27
a6ecb05c	28	#ifdef __GNUC__
b3172cab	29	#include "cpuid.h"
fa959ce4	30
2711355f ZD	31	/* Returns parameters that describe L1_ASSOC associative cache of size
	32	L1_SIZEKB with lines of size L1_LINE. */
	33
	34	static char *
	35	describe_cache (unsigned l1_sizekb, unsigned l1_line,
f4a1dd0d	36	unsigned l1_assoc ATTRIBUTE_UNUSED, unsigned l2_sizekb)
2711355f	37	{
f4a1dd0d	38	char size[100], line[100], size2[100];
2711355f ZD	39
	40	/* At the moment, gcc middle-end does not use the information about the
	41	associativity of the cache. */
	42
46cb0441	43	sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
2711355f	44	sprintf (line, "--param l1-cache-line-size=%u", l1_line);
f4a1dd0d	45	sprintf (size2, "--param l2-cache-size=%u", l2_sizekb);
2711355f	46
f4a1dd0d ZM	47	return concat (size, " ", line, " ", size2, " ", NULL);
	48	}
	49
	50	static void
	51	decode_l2_cache (unsigned l2_size, unsigned l2_line, unsigned *l2_assoc)
	52	{
	53	unsigned eax, ebx, ecx, edx, assoc;
	54
	55	__cpuid (0x80000006, eax, ebx, ecx, edx);
	56
	57	*l2_size = (ecx >> 16) & 0xffff;
	58	*l2_line = ecx & 0xff;
	59	assoc = (ecx >> 12) & 0xf;
	60	if (assoc == 6)
	61	assoc = 8;
	62	else if (assoc == 8)
	63	assoc = 16;
	64	else if (assoc >= 0xa && assoc <= 0xc)
	65	assoc = 32 + (assoc - 0xa) * 16;
	66	else if (assoc >= 0xd && assoc <= 0xe)
	67	assoc = 96 + (assoc - 0xd) * 32;
	68	*l2_assoc = assoc;
2711355f ZD	69	}
	70
	71	/* Returns the description of caches for an AMD processor. */
	72
	73	static char *
	74	detect_caches_amd (unsigned max_ext_level)
	75	{
	76	unsigned eax, ebx, ecx, edx;
	77	unsigned l1_sizekb, l1_line, l1_assoc;
f4a1dd0d	78	unsigned l2_sizekb, l2_line, l2_assoc;
2711355f ZD	79
2711355f ZD	80	if (max_ext_level < 0x80000005)
b3172cab	81	return (char *) "";
2711355f	82
b3172cab	83	__cpuid (0x80000005, eax, ebx, ecx, edx);
2711355f ZD	84
	85	l1_line = ecx & 0xff;
	86	l1_sizekb = (ecx >> 24) & 0xff;
	87	l1_assoc = (ecx >> 16) & 0xff;
	88
f4a1dd0d ZM	89	if (max_ext_level >= 0x80000006)
	90	decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
	91
	92	return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
2711355f ZD	93	}
2711355f ZD	94
f4a1dd0d ZM	95	/* Stores the size of the L1/2 cache and cache line, and the associativity
	96	of the cache according to REG to L1_SIZEKB, L1_LINE, L1_ASSOC and
	97	L2_SIZEKB. */
2711355f ZD	98
	99	static void
	100	decode_caches_intel (unsigned reg, unsigned l1_sizekb, unsigned l1_line,
f4a1dd0d ZM	101	unsigned l1_assoc, unsigned l2_sizekb,
f4a1dd0d ZM	102	unsigned l2_line, unsigned l2_assoc)
2711355f ZD	103	{
	104	unsigned i, val;
	105
	106	if (((reg >> 31) & 1) != 0)
	107	return;
	108
	109	for (i = 0; i < 4; i++)
	110	{
	111	val = reg & 0xff;
	112	reg >>= 8;
	113
	114	switch (val)
	115	{
	116	case 0xa:
	117	*l1_sizekb = 8;
	118	*l1_line = 32;
	119	*l1_assoc = 2;
	120	break;
	121	case 0xc:
	122	*l1_sizekb = 16;
	123	*l1_line = 32;
	124	*l1_assoc = 4;
	125	break;
	126	case 0x2c:
	127	*l1_sizekb = 32;
	128	*l1_line = 64;
	129	*l1_assoc = 8;
	130	break;
f4a1dd0d ZM	131	case 0x39:
	132	*l2_sizekb = 128;
	133	*l2_line = 64;
	134	*l2_assoc = 4;
	135	break;
	136	case 0x3a:
	137	*l2_sizekb = 192;
	138	*l2_line = 64;
	139	*l2_assoc = 6;
	140	break;
	141	case 0x3b:
	142	*l2_sizekb = 128;
	143	*l2_line = 64;
	144	*l2_assoc = 2;
	145	break;
	146	case 0x3c:
	147	*l2_sizekb = 256;
	148	*l2_line = 64;
	149	*l2_assoc = 4;
	150	break;
	151	case 0x3d:
	152	*l2_sizekb = 384;
	153	*l2_line = 64;
	154	*l2_assoc = 6;
	155	break;
	156	case 0x3e:
	157	*l2_sizekb = 512;
	158	*l2_line = 64;
	159	*l2_assoc = 4;
	160	break;
	161	case 0x41:
	162	*l2_sizekb = 128;
	163	*l2_line = 32;
	164	*l2_assoc = 4;
	165	break;
	166	case 0x42:
	167	*l2_sizekb = 256;
	168	*l2_line = 32;
	169	*l2_assoc = 4;
	170	break;
	171	case 0x43:
	172	*l2_sizekb = 512;
	173	*l2_line = 32;
	174	*l2_assoc = 4;
	175	break;
	176	case 0x44:
	177	*l2_sizekb = 1024;
	178	*l2_line = 32;
	179	*l2_assoc = 4;
	180	break;
	181	case 0x45:
	182	*l2_sizekb = 2048;
	183	*l2_line = 32;
	184	*l2_assoc = 4;
	185	break;
	186	case 0x49:
	187	*l2_sizekb = 4096;
	188	*l2_line = 64;
	189	*l2_assoc = 16;
	190	break;
2711355f ZD	191	case 0x60:
	192	*l1_sizekb = 16;
	193	*l1_line = 64;
	194	*l1_assoc = 8;
	195	break;
	196	case 0x66:
	197	*l1_sizekb = 8;
	198	*l1_line = 64;
	199	*l1_assoc = 4;
	200	break;
	201	case 0x67:
	202	*l1_sizekb = 16;
	203	*l1_line = 64;
	204	*l1_assoc = 4;
	205	break;
	206	case 0x68:
	207	*l1_sizekb = 32;
	208	*l1_line = 64;
	209	*l1_assoc = 4;
	210	break;
f4a1dd0d ZM	211	case 0x78:
	212	*l2_sizekb = 1024;
	213	*l2_line = 64;
	214	*l2_assoc = 4;
	215	break;
	216	case 0x79:
	217	*l2_sizekb = 128;
	218	*l2_line = 64;
	219	*l2_assoc = 8;
	220	break;
	221	case 0x7a:
	222	*l2_sizekb = 256;
	223	*l2_line = 64;
	224	*l2_assoc = 8;
	225	break;
	226	case 0x7b:
	227	*l2_sizekb = 512;
	228	*l2_line = 64;
	229	*l2_assoc = 8;
	230	break;
	231	case 0x7c:
	232	*l2_sizekb = 1024;
	233	*l2_line = 64;
	234	*l2_assoc = 8;
	235	break;
	236	case 0x7d:
	237	*l2_sizekb = 2048;
	238	*l2_line = 64;
	239	*l2_assoc = 8;
	240	break;
	241	case 0x7f:
	242	*l2_sizekb = 512;
	243	*l2_line = 64;
	244	*l2_assoc = 2;
	245	break;
	246	case 0x82:
	247	*l2_sizekb = 256;
	248	*l2_line = 32;
	249	*l2_assoc = 8;
	250	break;
	251	case 0x83:
	252	*l2_sizekb = 512;
	253	*l2_line = 32;
	254	*l2_assoc = 8;
	255	break;
	256	case 0x84:
	257	*l2_sizekb = 1024;
	258	*l2_line = 32;
	259	*l2_assoc = 8;
	260	break;
	261	case 0x85:
	262	*l2_sizekb = 2048;
	263	*l2_line = 32;
	264	*l2_assoc = 8;
	265	break;
	266	case 0x86:
	267	*l2_sizekb = 512;
	268	*l2_line = 64;
	269	*l2_assoc = 4;
	270	break;
	271	case 0x87:
	272	*l2_sizekb = 1024;
	273	*l2_line = 64;
	274	*l2_assoc = 8;
275	break;
2711355f ZD	276
	277	default:
	278	break;
	279	}
	280	}
	281	}
	282
	283	/* Returns the description of caches for an intel processor. */
	284
	285	static char *
f4a1dd0d	286	detect_caches_intel (unsigned max_level, unsigned max_ext_level)
2711355f ZD	287	{
	288	unsigned eax, ebx, ecx, edx;
	289	unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
f4a1dd0d	290	unsigned l2_sizekb = 0, l2_line = 0, l2_assoc = 0;
2711355f ZD	291
2711355f ZD	292	if (max_level < 2)
b3172cab	293	return (char *) "";
2711355f	294
b3172cab	295	__cpuid (2, eax, ebx, ecx, edx);
2711355f	296
f4a1dd0d ZM	297	decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc,
	298	&l2_sizekb, &l2_line, &l2_assoc);
	299	decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc,
	300	&l2_sizekb, &l2_line, &l2_assoc);
	301	decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc,
	302	&l2_sizekb, &l2_line, &l2_assoc);
	303	decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc,
	304	&l2_sizekb, &l2_line, &l2_assoc);
b3172cab	305
2711355f ZD	306	if (!l1_sizekb)
	307	return (char *) "";
	308
f4a1dd0d ZM	309	/* Newer Intel CPUs are equipped with AMD style L2 cache info */
	310	if (max_ext_level >= 0x80000006)
	311	decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
	312
	313	return describe_cache (l1_sizekb, l1_line, assoc, l2_sizekb);
2711355f ZD	314	}
2711355f ZD	315
fa959ce4 MM	316	/* This will be called by the spec parser in gcc.c when it sees
	317	a %:local_cpu_detect(args) construct. Currently it will be called
	318	with either "arch" or "tune" as argument depending on if -march=native
	319	or -mtune=native is to be substituted.
	320
	321	It returns a string containing new command line parameters to be
	322	put at the place of the above two options, depending on what CPU
	323	this is executed. E.g. "-march=k8" on an AMD64 machine
	324	for -march=native.
	325
	326	ARGC and ARGV are set depending on the actual arguments given
	327	in the spec. */
b3172cab	328
fa959ce4 MM	329	const char host_detect_local_cpu (int argc, const char *argv)
fa959ce4 MM	330	{
b3172cab UB	331	enum processor_type processor = PROCESSOR_I386;
	332	const char *cpu = "i386";
	333
2711355f	334	const char *cache = "";
5be6cb59	335	const char *options = "";
b3172cab UB	336
	337	unsigned int eax, ebx, ecx, edx;
	338
	339	unsigned int max_level, ext_level;
fa959ce4	340	unsigned int vendor;
b3172cab UB	341	unsigned int family;
	342
	343	unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
	344	unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
	345
	346	/* Extended features */
	347	unsigned int has_lahf_lm = 0, has_sse4a = 0;
	348	unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
	349
edccdcb1 L	350	bool arch;
	351
	352	if (argc < 1)
	353	return NULL;
	354
b3172cab UB	355	arch = !strcmp (argv[0], "arch");
b3172cab UB	356
edccdcb1	357	if (!arch && strcmp (argv[0], "tune"))
fa959ce4 MM	358	return NULL;
fa959ce4 MM	359
b3172cab UB	360	max_level = __get_cpuid_max (0, &vendor);
b3172cab UB	361	if (max_level < 1)
fa959ce4	362	goto done;
fa959ce4	363
b3172cab	364	__cpuid (1, eax, ebx, ecx, edx);
fa959ce4	365
fa959ce4	366	/* We don't care for extended family. */
b3172cab UB	367	family = (eax >> 8) & 0x0f;
	368
	369	has_sse3 = ecx & bit_SSE3;
	370	has_ssse3 = ecx & bit_SSSE3;
	371	has_cmpxchg16b = ecx & bit_CMPXCHG16B;
fa959ce4	372
b3172cab UB	373	has_cmpxchg8b = edx & bit_CMPXCHG8B;
	374	has_cmov = edx & bit_CMOV;
	375	has_mmx = edx & bit_MMX;
	376	has_sse = edx & bit_SSE;
	377	has_sse2 = edx & bit_SSE2;
	378
	379	/* Check cpuid level of extended features. */
	380	__cpuid (0x80000000, ext_level, ebx, ecx, edx);
	381
	382	if (ext_level > 0x80000000)
fa959ce4	383	{
b3172cab	384	__cpuid (0x80000001, eax, ebx, ecx, edx);
fa959ce4	385
b3172cab UB	386	has_lahf_lm = ecx & bit_LAHF_LM;
	387	has_sse4a = ecx & bit_SSE4a;
	388
	389	has_longmode = edx & bit_LM;
	390	has_3dnowp = edx & bit_3DNOWP;
	391	has_3dnow = edx & bit_3DNOW;
	392	}
fa959ce4	393
2711355f ZD	394	if (!arch)
2711355f ZD	395	{
b3172cab	396	if (vendor == (unsigned int) "Auth")
2711355f	397	cache = detect_caches_amd (ext_level);
b3172cab	398	else if (vendor == (unsigned int) "Genu")
f4a1dd0d	399	cache = detect_caches_intel (max_level, ext_level);
2711355f ZD	400	}
2711355f ZD	401
b3172cab	402	if (vendor == (unsigned int) "Auth")
fa959ce4	403	{
b3172cab UB	404	processor = PROCESSOR_PENTIUM;
b3172cab UB	405
fa959ce4	406	if (has_mmx)
edccdcb1	407	processor = PROCESSOR_K6;
fa959ce4	408	if (has_3dnowp)
edccdcb1	409	processor = PROCESSOR_ATHLON;
fa959ce4	410	if (has_sse2 \|\| has_longmode)
edccdcb1	411	processor = PROCESSOR_K8;
35a63f21 DR	412	if (has_sse4a)
35a63f21 DR	413	processor = PROCESSOR_AMDFAM10;
fa959ce4	414	}
b3172cab UB	415	else if (vendor == (unsigned int) "Geod")
b3172cab UB	416	processor = PROCESSOR_GEODE;
fa959ce4 MM	417	else
fa959ce4 MM	418	{
edccdcb1 L	419	switch (family)
edccdcb1 L	420	{
b3172cab UB	421	case 4:
	422	processor = PROCESSOR_I486;
	423	break;
edccdcb1	424	case 5:
b3172cab	425	processor = PROCESSOR_PENTIUM;
edccdcb1 L	426	break;
	427	case 6:
	428	processor = PROCESSOR_PENTIUMPRO;
	429	break;
	430	case 15:
	431	processor = PROCESSOR_PENTIUM4;
	432	break;
	433	default:
b3172cab UB	434	/* We have no idea. */
b3172cab UB	435	processor = PROCESSOR_GENERIC32;
edccdcb1 L	436	}
	437	}
	438
	439	switch (processor)
	440	{
	441	case PROCESSOR_I386:
b3172cab	442	/* Default. */
edccdcb1 L	443	break;
	444	case PROCESSOR_I486:
	445	cpu = "i486";
	446	break;
	447	case PROCESSOR_PENTIUM:
b3172cab	448	if (arch && has_mmx)
edccdcb1 L	449	cpu = "pentium-mmx";
	450	else
	451	cpu = "pentium";
	452	break;
	453	case PROCESSOR_PENTIUMPRO:
	454	if (has_longmode)
b3172cab UB	455	/* It is Core 2 Duo. */
	456	cpu = "core2";
	457	else if (arch)
edccdcb1	458	{
b3172cab UB	459	if (has_sse3)
	460	/* It is Core Duo. */
	461	cpu = "prescott";
	462	else if (has_sse2)
	463	/* It is Pentium M. */
	464	cpu = "pentium-m";
	465	else if (has_sse)
	466	/* It is Pentium III. */
	467	cpu = "pentium3";
	468	else if (has_mmx)
	469	/* It is Pentium II. */
	470	cpu = "pentium2";
	471	else
	472	/* Default to Pentium Pro. */
	473	cpu = "pentiumpro";
fa959ce4	474	}
edccdcb1	475	else
b3172cab UB	476	/* For -mtune, we default to -mtune=generic. */
	477	cpu = "generic";
	478	break;
	479	case PROCESSOR_PENTIUM4:
	480	if (has_sse3)
fa959ce4	481	{
b3172cab UB	482	if (has_longmode)
b3172cab UB	483	cpu = "nocona";
fa959ce4	484	else
b3172cab	485	cpu = "prescott";
fa959ce4	486	}
b3172cab UB	487	else
b3172cab UB	488	cpu = "pentium4";
edccdcb1 L	489	break;
	490	case PROCESSOR_GEODE:
	491	cpu = "geode";
	492	break;
	493	case PROCESSOR_K6:
b3172cab UB	494	if (arch && has_3dnow)
b3172cab UB	495	cpu = "k6-3";
edccdcb1 L	496	else
	497	cpu = "k6";
	498	break;
	499	case PROCESSOR_ATHLON:
b3172cab	500	if (arch && has_sse)
edccdcb1 L	501	cpu = "athlon-4";
	502	else
	503	cpu = "athlon";
	504	break;
edccdcb1	505	case PROCESSOR_K8:
b3172cab UB	506	if (arch && has_sse3)
	507	cpu = "k8-sse3";
	508	else
	509	cpu = "k8";
edccdcb1	510	break;
35a63f21 DR	511	case PROCESSOR_AMDFAM10:
	512	cpu = "amdfam10";
	513	break;
b3172cab	514
edccdcb1	515	default:
b3172cab UB	516	/* Use something reasonable. */
	517	if (arch)
	518	{
	519	if (has_ssse3)
	520	cpu = "core2";
	521	else if (has_sse3)
	522	{
	523	if (has_longmode)
	524	cpu = "nocona";
	525	else
	526	cpu = "prescott";
	527	}
	528	else if (has_sse2)
	529	cpu = "pentium4";
	530	else if (has_cmov)
	531	cpu = "pentiumpro";
	532	else if (has_mmx)
	533	cpu = "pentium-mmx";
	534	else if (has_cmpxchg8b)
	535	cpu = "pentium";
	536	}
	537	else
	538	cpu = "generic";
fa959ce4 MM	539	}
fa959ce4 MM	540
5be6cb59 UB	541	if (arch)
	542	{
	543	if (has_cmpxchg16b)
	544	options = concat (options, "-mcx16 ", NULL);
	545	if (has_lahf_lm)
	546	options = concat (options, "-msahf ", NULL);
	547	}
	548
fa959ce4	549	done:
5be6cb59	550	return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
fa959ce4 MM	551	}
fa959ce4 MM	552	#else
b3172cab	553
fa959ce4 MM	554	/* If we aren't compiling with GCC we just provide a minimal
fa959ce4 MM	555	default value. */
b3172cab	556
fa959ce4 MM	557	const char host_detect_local_cpu (int argc, const char *argv)
fa959ce4 MM	558	{
edccdcb1 L	559	const char *cpu;
	560	bool arch;
	561
	562	if (argc < 1)
	563	return NULL;
	564
b3172cab UB	565	arch = !strcmp (argv[0], "arch");
b3172cab UB	566
edccdcb1 L	567	if (!arch && strcmp (argv[0], "tune"))
	568	return NULL;
	569
	570	if (arch)
	571	{
	572	/* FIXME: i386 is wrong for 64bit compiler. How can we tell if
	573	we are generating 64bit or 32bit code? */
	574	cpu = "i386";
	575	}
	576	else
	577	cpu = "generic";
	578
	579	return concat ("-m", argv[0], "=", cpu, NULL);
fa959ce4	580	}
a6ecb05c	581	#endif /* __GNUC__ */