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fa959ce4 | 1 | /* Subroutines for the gcc driver. |
cb0dee88 | 2 | Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc. |
fa959ce4 MM |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
fa959ce4 MM |
9 | any later version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
fa959ce4 MM |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
edccdcb1 L |
22 | #include "coretypes.h" |
23 | #include "tm.h" | |
fa959ce4 MM |
24 | #include <stdlib.h> |
25 | ||
895016f6 UB |
26 | const char *host_detect_local_cpu (int argc, const char **argv); |
27 | ||
a6ecb05c | 28 | #ifdef __GNUC__ |
b3172cab | 29 | #include "cpuid.h" |
fa959ce4 | 30 | |
cb0dee88 UB |
31 | struct cache_desc |
32 | { | |
33 | unsigned sizekb; | |
34 | unsigned assoc; | |
35 | unsigned line; | |
36 | }; | |
37 | ||
38 | /* Returns command line parameters that describe size and | |
39 | cache line size of the processor caches. */ | |
2711355f ZD |
40 | |
41 | static char * | |
cb0dee88 | 42 | describe_cache (struct cache_desc level1, struct cache_desc level2) |
2711355f | 43 | { |
f4a1dd0d | 44 | char size[100], line[100], size2[100]; |
2711355f | 45 | |
cb0dee88 UB |
46 | /* At the moment, gcc does not use the information |
47 | about the associativity of the cache. */ | |
48 | ||
49 | sprintf (size, "--param l1-cache-size=%u", level1.sizekb); | |
50 | sprintf (line, "--param l1-cache-line-size=%u", level1.line); | |
2711355f | 51 | |
cb0dee88 | 52 | sprintf (size2, "--param l2-cache-size=%u", level2.sizekb); |
2711355f | 53 | |
f4a1dd0d ZM |
54 | return concat (size, " ", line, " ", size2, " ", NULL); |
55 | } | |
56 | ||
cb0dee88 UB |
57 | /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ |
58 | ||
f4a1dd0d | 59 | static void |
cb0dee88 | 60 | detect_l2_cache (struct cache_desc *level2) |
f4a1dd0d | 61 | { |
cb0dee88 UB |
62 | unsigned eax, ebx, ecx, edx; |
63 | unsigned assoc; | |
f4a1dd0d ZM |
64 | |
65 | __cpuid (0x80000006, eax, ebx, ecx, edx); | |
66 | ||
cb0dee88 UB |
67 | level2->sizekb = (ecx >> 16) & 0xffff; |
68 | level2->line = ecx & 0xff; | |
69 | ||
f4a1dd0d ZM |
70 | assoc = (ecx >> 12) & 0xf; |
71 | if (assoc == 6) | |
72 | assoc = 8; | |
73 | else if (assoc == 8) | |
74 | assoc = 16; | |
75 | else if (assoc >= 0xa && assoc <= 0xc) | |
76 | assoc = 32 + (assoc - 0xa) * 16; | |
77 | else if (assoc >= 0xd && assoc <= 0xe) | |
78 | assoc = 96 + (assoc - 0xd) * 32; | |
cb0dee88 UB |
79 | |
80 | level2->assoc = assoc; | |
2711355f ZD |
81 | } |
82 | ||
83 | /* Returns the description of caches for an AMD processor. */ | |
84 | ||
d3bfe4de | 85 | static const char * |
2711355f ZD |
86 | detect_caches_amd (unsigned max_ext_level) |
87 | { | |
88 | unsigned eax, ebx, ecx, edx; | |
cb0dee88 UB |
89 | |
90 | struct cache_desc level1, level2 = {0, 0, 0}; | |
2711355f ZD |
91 | |
92 | if (max_ext_level < 0x80000005) | |
d3bfe4de | 93 | return ""; |
2711355f | 94 | |
b3172cab | 95 | __cpuid (0x80000005, eax, ebx, ecx, edx); |
2711355f | 96 | |
cb0dee88 UB |
97 | level1.sizekb = (ecx >> 24) & 0xff; |
98 | level1.assoc = (ecx >> 16) & 0xff; | |
99 | level1.line = ecx & 0xff; | |
2711355f | 100 | |
f4a1dd0d | 101 | if (max_ext_level >= 0x80000006) |
cb0dee88 | 102 | detect_l2_cache (&level2); |
f4a1dd0d | 103 | |
cb0dee88 | 104 | return describe_cache (level1, level2); |
2711355f ZD |
105 | } |
106 | ||
cb0dee88 UB |
107 | /* Decodes the size, the associativity and the cache line size of |
108 | L1/L2 caches of an Intel processor. Values are based on | |
109 | "Intel Processor Identification and the CPUID Instruction" | |
110 | [Application Note 485], revision -032, December 2007. */ | |
2711355f ZD |
111 | |
112 | static void | |
cb0dee88 UB |
113 | decode_caches_intel (unsigned reg, bool xeon_mp, |
114 | struct cache_desc *level1, struct cache_desc *level2) | |
2711355f | 115 | { |
cb0dee88 UB |
116 | int i; |
117 | ||
118 | for (i = 24; i >= 0; i -= 8) | |
119 | switch ((reg >> i) & 0xff) | |
120 | { | |
121 | case 0x0a: | |
122 | level1->sizekb = 8; level1->assoc = 2; level1->line = 32; | |
123 | break; | |
124 | case 0x0c: | |
125 | level1->sizekb = 16; level1->assoc = 4; level1->line = 32; | |
126 | break; | |
127 | case 0x2c: | |
128 | level1->sizekb = 32; level1->assoc = 8; level1->line = 64; | |
129 | break; | |
130 | case 0x39: | |
131 | level2->sizekb = 128; level2->assoc = 4; level2->line = 64; | |
132 | break; | |
133 | case 0x3a: | |
134 | level2->sizekb = 192; level2->assoc = 6; level2->line = 64; | |
135 | break; | |
136 | case 0x3b: | |
137 | level2->sizekb = 128; level2->assoc = 2; level2->line = 64; | |
138 | break; | |
139 | case 0x3c: | |
140 | level2->sizekb = 256; level2->assoc = 4; level2->line = 64; | |
141 | break; | |
142 | case 0x3d: | |
143 | level2->sizekb = 384; level2->assoc = 6; level2->line = 64; | |
144 | break; | |
145 | case 0x3e: | |
146 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
147 | break; | |
148 | case 0x41: | |
149 | level2->sizekb = 128; level2->assoc = 4; level2->line = 32; | |
150 | break; | |
151 | case 0x42: | |
152 | level2->sizekb = 256; level2->assoc = 4; level2->line = 32; | |
153 | break; | |
154 | case 0x43: | |
155 | level2->sizekb = 512; level2->assoc = 4; level2->line = 32; | |
156 | break; | |
157 | case 0x44: | |
158 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; | |
159 | break; | |
160 | case 0x45: | |
161 | level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; | |
162 | break; | |
163 | case 0x49: | |
164 | if (xeon_mp) | |
165 | break; | |
166 | level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; | |
167 | break; | |
168 | case 0x4e: | |
169 | level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; | |
170 | break; | |
171 | case 0x60: | |
172 | level1->sizekb = 16; level1->assoc = 8; level1->line = 64; | |
173 | break; | |
174 | case 0x66: | |
175 | level1->sizekb = 8; level1->assoc = 4; level1->line = 64; | |
176 | break; | |
177 | case 0x67: | |
178 | level1->sizekb = 16; level1->assoc = 4; level1->line = 64; | |
179 | break; | |
180 | case 0x68: | |
181 | level1->sizekb = 32; level1->assoc = 4; level1->line = 64; | |
182 | break; | |
183 | case 0x78: | |
184 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; | |
185 | break; | |
186 | case 0x79: | |
187 | level2->sizekb = 128; level2->assoc = 8; level2->line = 64; | |
188 | break; | |
189 | case 0x7a: | |
190 | level2->sizekb = 256; level2->assoc = 8; level2->line = 64; | |
191 | break; | |
192 | case 0x7b: | |
193 | level2->sizekb = 512; level2->assoc = 8; level2->line = 64; | |
194 | break; | |
195 | case 0x7c: | |
196 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
197 | break; | |
198 | case 0x7d: | |
199 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; | |
200 | break; | |
201 | case 0x7f: | |
202 | level2->sizekb = 512; level2->assoc = 2; level2->line = 64; | |
203 | break; | |
204 | case 0x82: | |
205 | level2->sizekb = 256; level2->assoc = 8; level2->line = 32; | |
206 | break; | |
207 | case 0x83: | |
208 | level2->sizekb = 512; level2->assoc = 8; level2->line = 32; | |
209 | break; | |
210 | case 0x84: | |
211 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; | |
212 | break; | |
213 | case 0x85: | |
214 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; | |
215 | break; | |
216 | case 0x86: | |
217 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
218 | break; | |
219 | case 0x87: | |
220 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
221 | ||
222 | default: | |
223 | break; | |
224 | } | |
225 | } | |
2711355f | 226 | |
cb0dee88 | 227 | /* Detect cache parameters using CPUID function 2. */ |
2711355f | 228 | |
cb0dee88 UB |
229 | static void |
230 | detect_caches_cpuid2 (bool xeon_mp, | |
231 | struct cache_desc *level1, struct cache_desc *level2) | |
232 | { | |
dc8bd8d9 UB |
233 | unsigned regs[4]; |
234 | int nreps, i; | |
cb0dee88 | 235 | |
dc8bd8d9 | 236 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 | 237 | |
dc8bd8d9 UB |
238 | nreps = regs[0] & 0x0f; |
239 | regs[0] &= ~0x0f; | |
cb0dee88 UB |
240 | |
241 | while (--nreps >= 0) | |
2711355f | 242 | { |
dc8bd8d9 UB |
243 | for (i = 0; i < 4; i++) |
244 | if (regs[i] && !((regs[i] >> 31) & 1)) | |
245 | decode_caches_intel (regs[i], xeon_mp, level1, level2); | |
cb0dee88 UB |
246 | |
247 | if (nreps) | |
dc8bd8d9 | 248 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 UB |
249 | } |
250 | } | |
2711355f | 251 | |
cb0dee88 UB |
252 | /* Detect cache parameters using CPUID function 4. This |
253 | method doesn't require hardcoded tables. */ | |
2711355f | 254 | |
cb0dee88 UB |
255 | enum cache_type |
256 | { | |
257 | CACHE_END = 0, | |
258 | CACHE_DATA = 1, | |
259 | CACHE_INST = 2, | |
260 | CACHE_UNIFIED = 3 | |
261 | }; | |
262 | ||
263 | static void | |
264 | detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2) | |
265 | { | |
266 | struct cache_desc *cache; | |
267 | ||
268 | unsigned eax, ebx, ecx, edx; | |
269 | int count; | |
270 | ||
271 | for (count = 0;; count++) | |
272 | { | |
273 | __cpuid_count(4, count, eax, ebx, ecx, edx); | |
274 | switch (eax & 0x1f) | |
275 | { | |
276 | case CACHE_END: | |
277 | return; | |
278 | case CACHE_DATA: | |
279 | case CACHE_UNIFIED: | |
280 | { | |
281 | switch ((eax >> 5) & 0x07) | |
282 | { | |
283 | case 1: | |
284 | cache = level1; | |
285 | break; | |
286 | case 2: | |
287 | cache = level2; | |
288 | break; | |
289 | default: | |
290 | cache = NULL; | |
291 | } | |
292 | ||
293 | if (cache) | |
294 | { | |
295 | unsigned sets = ecx + 1; | |
dc8bd8d9 | 296 | unsigned part = ((ebx >> 12) & 0x03ff) + 1; |
cb0dee88 | 297 | |
dc8bd8d9 | 298 | cache->assoc = ((ebx >> 22) & 0x03ff) + 1; |
cb0dee88 | 299 | cache->line = (ebx & 0x0fff) + 1; |
cb0dee88 UB |
300 | |
301 | cache->sizekb = (cache->assoc * part | |
302 | * cache->line * sets) / 1024; | |
303 | } | |
304 | } | |
2711355f ZD |
305 | default: |
306 | break; | |
307 | } | |
308 | } | |
309 | } | |
310 | ||
cb0dee88 | 311 | /* Returns the description of caches for an Intel processor. */ |
2711355f | 312 | |
d3bfe4de | 313 | static const char * |
cb0dee88 | 314 | detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level) |
2711355f | 315 | { |
cb0dee88 | 316 | struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}; |
2711355f | 317 | |
cb0dee88 UB |
318 | if (max_level >= 4) |
319 | detect_caches_cpuid4 (&level1, &level2); | |
320 | else if (max_level >= 2) | |
321 | detect_caches_cpuid2 (xeon_mp, &level1, &level2); | |
322 | else | |
d3bfe4de | 323 | return ""; |
2711355f | 324 | |
cb0dee88 | 325 | if (level1.sizekb == 0) |
d3bfe4de | 326 | return ""; |
2711355f | 327 | |
cb0dee88 UB |
328 | /* Intel CPUs are equipped with AMD style L2 cache info. Try this |
329 | method if other methods fail to provide L2 cache parameters. */ | |
330 | if (level2.sizekb == 0 && max_ext_level >= 0x80000006) | |
331 | detect_l2_cache (&level2); | |
f4a1dd0d | 332 | |
cb0dee88 | 333 | return describe_cache (level1, level2); |
2711355f ZD |
334 | } |
335 | ||
4d947823 UB |
336 | enum vendor_signatures |
337 | { | |
338 | SIG_INTEL = 0x756e6547 /* Genu */, | |
fbdf817d UB |
339 | SIG_AMD = 0x68747541 /* Auth */ |
340 | }; | |
341 | ||
342 | enum processor_signatures | |
343 | { | |
4d947823 UB |
344 | SIG_GEODE = 0x646f6547 /* Geod */ |
345 | }; | |
346 | ||
fa959ce4 MM |
347 | /* This will be called by the spec parser in gcc.c when it sees |
348 | a %:local_cpu_detect(args) construct. Currently it will be called | |
349 | with either "arch" or "tune" as argument depending on if -march=native | |
350 | or -mtune=native is to be substituted. | |
351 | ||
352 | It returns a string containing new command line parameters to be | |
353 | put at the place of the above two options, depending on what CPU | |
354 | this is executed. E.g. "-march=k8" on an AMD64 machine | |
355 | for -march=native. | |
356 | ||
357 | ARGC and ARGV are set depending on the actual arguments given | |
358 | in the spec. */ | |
b3172cab | 359 | |
fa959ce4 MM |
360 | const char *host_detect_local_cpu (int argc, const char **argv) |
361 | { | |
b3172cab UB |
362 | enum processor_type processor = PROCESSOR_I386; |
363 | const char *cpu = "i386"; | |
364 | ||
2711355f | 365 | const char *cache = ""; |
5be6cb59 | 366 | const char *options = ""; |
b3172cab | 367 | |
cb0dee88 | 368 | unsigned int eax, ebx, ecx, edx; |
b3172cab UB |
369 | |
370 | unsigned int max_level, ext_level; | |
cb0dee88 | 371 | |
fa959ce4 | 372 | unsigned int vendor; |
cb0dee88 | 373 | unsigned int model, family; |
b3172cab UB |
374 | |
375 | unsigned int has_sse3, has_ssse3, has_cmpxchg16b; | |
376 | unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; | |
377 | ||
378 | /* Extended features */ | |
379 | unsigned int has_lahf_lm = 0, has_sse4a = 0; | |
380 | unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; | |
381 | ||
edccdcb1 L |
382 | bool arch; |
383 | ||
384 | if (argc < 1) | |
385 | return NULL; | |
386 | ||
b3172cab UB |
387 | arch = !strcmp (argv[0], "arch"); |
388 | ||
edccdcb1 | 389 | if (!arch && strcmp (argv[0], "tune")) |
fa959ce4 MM |
390 | return NULL; |
391 | ||
b3172cab UB |
392 | max_level = __get_cpuid_max (0, &vendor); |
393 | if (max_level < 1) | |
fa959ce4 | 394 | goto done; |
fa959ce4 | 395 | |
b3172cab | 396 | __cpuid (1, eax, ebx, ecx, edx); |
fa959ce4 | 397 | |
cb0dee88 | 398 | model = (eax >> 4) & 0x0f; |
b3172cab | 399 | family = (eax >> 8) & 0x0f; |
37c50435 L |
400 | if (vendor == SIG_INTEL) |
401 | { | |
402 | unsigned int extended_model, extended_family; | |
403 | ||
404 | extended_model = (eax >> 12) & 0xf0; | |
405 | extended_family = (eax >> 20) & 0xff; | |
406 | if (family == 0x0f) | |
407 | { | |
408 | family += extended_family; | |
409 | model += extended_model; | |
410 | } | |
411 | else if (family == 0x06) | |
412 | model += extended_model; | |
413 | } | |
b3172cab UB |
414 | |
415 | has_sse3 = ecx & bit_SSE3; | |
416 | has_ssse3 = ecx & bit_SSSE3; | |
417 | has_cmpxchg16b = ecx & bit_CMPXCHG16B; | |
fa959ce4 | 418 | |
b3172cab UB |
419 | has_cmpxchg8b = edx & bit_CMPXCHG8B; |
420 | has_cmov = edx & bit_CMOV; | |
421 | has_mmx = edx & bit_MMX; | |
422 | has_sse = edx & bit_SSE; | |
423 | has_sse2 = edx & bit_SSE2; | |
424 | ||
425 | /* Check cpuid level of extended features. */ | |
426 | __cpuid (0x80000000, ext_level, ebx, ecx, edx); | |
427 | ||
428 | if (ext_level > 0x80000000) | |
fa959ce4 | 429 | { |
b3172cab | 430 | __cpuid (0x80000001, eax, ebx, ecx, edx); |
fa959ce4 | 431 | |
b3172cab UB |
432 | has_lahf_lm = ecx & bit_LAHF_LM; |
433 | has_sse4a = ecx & bit_SSE4a; | |
434 | ||
435 | has_longmode = edx & bit_LM; | |
436 | has_3dnowp = edx & bit_3DNOWP; | |
437 | has_3dnow = edx & bit_3DNOW; | |
438 | } | |
fa959ce4 | 439 | |
2711355f ZD |
440 | if (!arch) |
441 | { | |
4d947823 | 442 | if (vendor == SIG_AMD) |
2711355f | 443 | cache = detect_caches_amd (ext_level); |
4d947823 | 444 | else if (vendor == SIG_INTEL) |
cb0dee88 UB |
445 | { |
446 | bool xeon_mp = (family == 15 && model == 6); | |
447 | cache = detect_caches_intel (xeon_mp, max_level, ext_level); | |
448 | } | |
2711355f ZD |
449 | } |
450 | ||
4d947823 | 451 | if (vendor == SIG_AMD) |
fa959ce4 | 452 | { |
fbdf817d | 453 | unsigned int name; |
b3172cab | 454 | |
fbdf817d UB |
455 | /* Detect geode processor by its processor signature. */ |
456 | if (ext_level > 0x80000001) | |
457 | __cpuid (0x80000002, name, ebx, ecx, edx); | |
458 | else | |
459 | name = 0; | |
460 | ||
461 | if (name == SIG_GEODE) | |
462 | processor = PROCESSOR_GEODE; | |
463 | else if (has_sse4a) | |
35a63f21 | 464 | processor = PROCESSOR_AMDFAM10; |
fbdf817d UB |
465 | else if (has_sse2 || has_longmode) |
466 | processor = PROCESSOR_K8; | |
467 | else if (has_3dnowp) | |
468 | processor = PROCESSOR_ATHLON; | |
469 | else if (has_mmx) | |
470 | processor = PROCESSOR_K6; | |
471 | else | |
472 | processor = PROCESSOR_PENTIUM; | |
fa959ce4 MM |
473 | } |
474 | else | |
475 | { | |
edccdcb1 L |
476 | switch (family) |
477 | { | |
b3172cab UB |
478 | case 4: |
479 | processor = PROCESSOR_I486; | |
480 | break; | |
edccdcb1 | 481 | case 5: |
b3172cab | 482 | processor = PROCESSOR_PENTIUM; |
edccdcb1 L |
483 | break; |
484 | case 6: | |
485 | processor = PROCESSOR_PENTIUMPRO; | |
486 | break; | |
487 | case 15: | |
488 | processor = PROCESSOR_PENTIUM4; | |
489 | break; | |
490 | default: | |
b3172cab UB |
491 | /* We have no idea. */ |
492 | processor = PROCESSOR_GENERIC32; | |
edccdcb1 L |
493 | } |
494 | } | |
495 | ||
496 | switch (processor) | |
497 | { | |
498 | case PROCESSOR_I386: | |
b3172cab | 499 | /* Default. */ |
edccdcb1 L |
500 | break; |
501 | case PROCESSOR_I486: | |
502 | cpu = "i486"; | |
503 | break; | |
504 | case PROCESSOR_PENTIUM: | |
b3172cab | 505 | if (arch && has_mmx) |
edccdcb1 L |
506 | cpu = "pentium-mmx"; |
507 | else | |
508 | cpu = "pentium"; | |
509 | break; | |
510 | case PROCESSOR_PENTIUMPRO: | |
511 | if (has_longmode) | |
37c50435 L |
512 | /* It is Core 2 or Atom. */ |
513 | cpu = (model == 28) ? "atom" : "core2"; | |
b3172cab | 514 | else if (arch) |
edccdcb1 | 515 | { |
b3172cab UB |
516 | if (has_sse3) |
517 | /* It is Core Duo. */ | |
518 | cpu = "prescott"; | |
519 | else if (has_sse2) | |
520 | /* It is Pentium M. */ | |
521 | cpu = "pentium-m"; | |
522 | else if (has_sse) | |
523 | /* It is Pentium III. */ | |
524 | cpu = "pentium3"; | |
525 | else if (has_mmx) | |
526 | /* It is Pentium II. */ | |
527 | cpu = "pentium2"; | |
528 | else | |
529 | /* Default to Pentium Pro. */ | |
530 | cpu = "pentiumpro"; | |
fa959ce4 | 531 | } |
edccdcb1 | 532 | else |
b3172cab UB |
533 | /* For -mtune, we default to -mtune=generic. */ |
534 | cpu = "generic"; | |
535 | break; | |
536 | case PROCESSOR_PENTIUM4: | |
537 | if (has_sse3) | |
fa959ce4 | 538 | { |
b3172cab UB |
539 | if (has_longmode) |
540 | cpu = "nocona"; | |
fa959ce4 | 541 | else |
b3172cab | 542 | cpu = "prescott"; |
fa959ce4 | 543 | } |
b3172cab UB |
544 | else |
545 | cpu = "pentium4"; | |
edccdcb1 L |
546 | break; |
547 | case PROCESSOR_GEODE: | |
548 | cpu = "geode"; | |
549 | break; | |
550 | case PROCESSOR_K6: | |
b3172cab UB |
551 | if (arch && has_3dnow) |
552 | cpu = "k6-3"; | |
edccdcb1 L |
553 | else |
554 | cpu = "k6"; | |
555 | break; | |
556 | case PROCESSOR_ATHLON: | |
b3172cab | 557 | if (arch && has_sse) |
edccdcb1 L |
558 | cpu = "athlon-4"; |
559 | else | |
560 | cpu = "athlon"; | |
561 | break; | |
edccdcb1 | 562 | case PROCESSOR_K8: |
b3172cab UB |
563 | if (arch && has_sse3) |
564 | cpu = "k8-sse3"; | |
565 | else | |
566 | cpu = "k8"; | |
edccdcb1 | 567 | break; |
35a63f21 DR |
568 | case PROCESSOR_AMDFAM10: |
569 | cpu = "amdfam10"; | |
570 | break; | |
b3172cab | 571 | |
edccdcb1 | 572 | default: |
b3172cab UB |
573 | /* Use something reasonable. */ |
574 | if (arch) | |
575 | { | |
576 | if (has_ssse3) | |
577 | cpu = "core2"; | |
578 | else if (has_sse3) | |
579 | { | |
580 | if (has_longmode) | |
581 | cpu = "nocona"; | |
582 | else | |
583 | cpu = "prescott"; | |
584 | } | |
585 | else if (has_sse2) | |
586 | cpu = "pentium4"; | |
587 | else if (has_cmov) | |
588 | cpu = "pentiumpro"; | |
589 | else if (has_mmx) | |
590 | cpu = "pentium-mmx"; | |
591 | else if (has_cmpxchg8b) | |
592 | cpu = "pentium"; | |
593 | } | |
594 | else | |
595 | cpu = "generic"; | |
fa959ce4 MM |
596 | } |
597 | ||
5be6cb59 UB |
598 | if (arch) |
599 | { | |
600 | if (has_cmpxchg16b) | |
601 | options = concat (options, "-mcx16 ", NULL); | |
602 | if (has_lahf_lm) | |
603 | options = concat (options, "-msahf ", NULL); | |
604 | } | |
605 | ||
fa959ce4 | 606 | done: |
5be6cb59 | 607 | return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL); |
fa959ce4 MM |
608 | } |
609 | #else | |
b3172cab | 610 | |
fa959ce4 MM |
611 | /* If we aren't compiling with GCC we just provide a minimal |
612 | default value. */ | |
b3172cab | 613 | |
fa959ce4 MM |
614 | const char *host_detect_local_cpu (int argc, const char **argv) |
615 | { | |
edccdcb1 L |
616 | const char *cpu; |
617 | bool arch; | |
618 | ||
619 | if (argc < 1) | |
620 | return NULL; | |
621 | ||
b3172cab UB |
622 | arch = !strcmp (argv[0], "arch"); |
623 | ||
edccdcb1 L |
624 | if (!arch && strcmp (argv[0], "tune")) |
625 | return NULL; | |
626 | ||
627 | if (arch) | |
628 | { | |
629 | /* FIXME: i386 is wrong for 64bit compiler. How can we tell if | |
630 | we are generating 64bit or 32bit code? */ | |
631 | cpu = "i386"; | |
632 | } | |
633 | else | |
634 | cpu = "generic"; | |
635 | ||
636 | return concat ("-m", argv[0], "=", cpu, NULL); | |
fa959ce4 | 637 | } |
a6ecb05c | 638 | #endif /* __GNUC__ */ |