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fa959ce4 | 1 | /* Subroutines for the gcc driver. |
d652f226 | 2 | Copyright (C) 2006, 2007, 2008, 2010 Free Software Foundation, Inc. |
fa959ce4 MM |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
fa959ce4 MM |
9 | any later version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
fa959ce4 MM |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
edccdcb1 L |
22 | #include "coretypes.h" |
23 | #include "tm.h" | |
fa959ce4 | 24 | |
895016f6 UB |
25 | const char *host_detect_local_cpu (int argc, const char **argv); |
26 | ||
a6ecb05c | 27 | #ifdef __GNUC__ |
b3172cab | 28 | #include "cpuid.h" |
fa959ce4 | 29 | |
cb0dee88 UB |
30 | struct cache_desc |
31 | { | |
32 | unsigned sizekb; | |
33 | unsigned assoc; | |
34 | unsigned line; | |
35 | }; | |
36 | ||
37 | /* Returns command line parameters that describe size and | |
38 | cache line size of the processor caches. */ | |
2711355f ZD |
39 | |
40 | static char * | |
cb0dee88 | 41 | describe_cache (struct cache_desc level1, struct cache_desc level2) |
2711355f | 42 | { |
f4a1dd0d | 43 | char size[100], line[100], size2[100]; |
2711355f | 44 | |
cb0dee88 UB |
45 | /* At the moment, gcc does not use the information |
46 | about the associativity of the cache. */ | |
47 | ||
f3afc8a7 UB |
48 | snprintf (size, sizeof (size), |
49 | "--param l1-cache-size=%u ", level1.sizekb); | |
50 | snprintf (line, sizeof (line), | |
51 | "--param l1-cache-line-size=%u ", level1.line); | |
2711355f | 52 | |
f3afc8a7 UB |
53 | snprintf (size2, sizeof (size2), |
54 | "--param l2-cache-size=%u ", level2.sizekb); | |
2711355f | 55 | |
f3afc8a7 | 56 | return concat (size, line, size2, NULL); |
f4a1dd0d ZM |
57 | } |
58 | ||
cb0dee88 UB |
59 | /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ |
60 | ||
f4a1dd0d | 61 | static void |
cb0dee88 | 62 | detect_l2_cache (struct cache_desc *level2) |
f4a1dd0d | 63 | { |
cb0dee88 UB |
64 | unsigned eax, ebx, ecx, edx; |
65 | unsigned assoc; | |
f4a1dd0d ZM |
66 | |
67 | __cpuid (0x80000006, eax, ebx, ecx, edx); | |
68 | ||
cb0dee88 UB |
69 | level2->sizekb = (ecx >> 16) & 0xffff; |
70 | level2->line = ecx & 0xff; | |
71 | ||
f4a1dd0d ZM |
72 | assoc = (ecx >> 12) & 0xf; |
73 | if (assoc == 6) | |
74 | assoc = 8; | |
75 | else if (assoc == 8) | |
76 | assoc = 16; | |
77 | else if (assoc >= 0xa && assoc <= 0xc) | |
78 | assoc = 32 + (assoc - 0xa) * 16; | |
79 | else if (assoc >= 0xd && assoc <= 0xe) | |
80 | assoc = 96 + (assoc - 0xd) * 32; | |
cb0dee88 UB |
81 | |
82 | level2->assoc = assoc; | |
2711355f ZD |
83 | } |
84 | ||
85 | /* Returns the description of caches for an AMD processor. */ | |
86 | ||
d3bfe4de | 87 | static const char * |
2711355f ZD |
88 | detect_caches_amd (unsigned max_ext_level) |
89 | { | |
90 | unsigned eax, ebx, ecx, edx; | |
cb0dee88 UB |
91 | |
92 | struct cache_desc level1, level2 = {0, 0, 0}; | |
2711355f ZD |
93 | |
94 | if (max_ext_level < 0x80000005) | |
d3bfe4de | 95 | return ""; |
2711355f | 96 | |
b3172cab | 97 | __cpuid (0x80000005, eax, ebx, ecx, edx); |
2711355f | 98 | |
cb0dee88 UB |
99 | level1.sizekb = (ecx >> 24) & 0xff; |
100 | level1.assoc = (ecx >> 16) & 0xff; | |
101 | level1.line = ecx & 0xff; | |
2711355f | 102 | |
f4a1dd0d | 103 | if (max_ext_level >= 0x80000006) |
cb0dee88 | 104 | detect_l2_cache (&level2); |
f4a1dd0d | 105 | |
cb0dee88 | 106 | return describe_cache (level1, level2); |
2711355f ZD |
107 | } |
108 | ||
cb0dee88 UB |
109 | /* Decodes the size, the associativity and the cache line size of |
110 | L1/L2 caches of an Intel processor. Values are based on | |
111 | "Intel Processor Identification and the CPUID Instruction" | |
112 | [Application Note 485], revision -032, December 2007. */ | |
2711355f ZD |
113 | |
114 | static void | |
cb0dee88 UB |
115 | decode_caches_intel (unsigned reg, bool xeon_mp, |
116 | struct cache_desc *level1, struct cache_desc *level2) | |
2711355f | 117 | { |
cb0dee88 UB |
118 | int i; |
119 | ||
120 | for (i = 24; i >= 0; i -= 8) | |
121 | switch ((reg >> i) & 0xff) | |
122 | { | |
123 | case 0x0a: | |
124 | level1->sizekb = 8; level1->assoc = 2; level1->line = 32; | |
125 | break; | |
126 | case 0x0c: | |
127 | level1->sizekb = 16; level1->assoc = 4; level1->line = 32; | |
128 | break; | |
129 | case 0x2c: | |
130 | level1->sizekb = 32; level1->assoc = 8; level1->line = 64; | |
131 | break; | |
132 | case 0x39: | |
133 | level2->sizekb = 128; level2->assoc = 4; level2->line = 64; | |
134 | break; | |
135 | case 0x3a: | |
136 | level2->sizekb = 192; level2->assoc = 6; level2->line = 64; | |
137 | break; | |
138 | case 0x3b: | |
139 | level2->sizekb = 128; level2->assoc = 2; level2->line = 64; | |
140 | break; | |
141 | case 0x3c: | |
142 | level2->sizekb = 256; level2->assoc = 4; level2->line = 64; | |
143 | break; | |
144 | case 0x3d: | |
145 | level2->sizekb = 384; level2->assoc = 6; level2->line = 64; | |
146 | break; | |
147 | case 0x3e: | |
148 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
149 | break; | |
150 | case 0x41: | |
151 | level2->sizekb = 128; level2->assoc = 4; level2->line = 32; | |
152 | break; | |
153 | case 0x42: | |
154 | level2->sizekb = 256; level2->assoc = 4; level2->line = 32; | |
155 | break; | |
156 | case 0x43: | |
157 | level2->sizekb = 512; level2->assoc = 4; level2->line = 32; | |
158 | break; | |
159 | case 0x44: | |
160 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; | |
161 | break; | |
162 | case 0x45: | |
163 | level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; | |
164 | break; | |
165 | case 0x49: | |
166 | if (xeon_mp) | |
167 | break; | |
168 | level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; | |
169 | break; | |
170 | case 0x4e: | |
171 | level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; | |
172 | break; | |
173 | case 0x60: | |
174 | level1->sizekb = 16; level1->assoc = 8; level1->line = 64; | |
175 | break; | |
176 | case 0x66: | |
177 | level1->sizekb = 8; level1->assoc = 4; level1->line = 64; | |
178 | break; | |
179 | case 0x67: | |
180 | level1->sizekb = 16; level1->assoc = 4; level1->line = 64; | |
181 | break; | |
182 | case 0x68: | |
183 | level1->sizekb = 32; level1->assoc = 4; level1->line = 64; | |
184 | break; | |
185 | case 0x78: | |
186 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; | |
187 | break; | |
188 | case 0x79: | |
189 | level2->sizekb = 128; level2->assoc = 8; level2->line = 64; | |
190 | break; | |
191 | case 0x7a: | |
192 | level2->sizekb = 256; level2->assoc = 8; level2->line = 64; | |
193 | break; | |
194 | case 0x7b: | |
195 | level2->sizekb = 512; level2->assoc = 8; level2->line = 64; | |
196 | break; | |
197 | case 0x7c: | |
198 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
199 | break; | |
200 | case 0x7d: | |
201 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; | |
202 | break; | |
203 | case 0x7f: | |
204 | level2->sizekb = 512; level2->assoc = 2; level2->line = 64; | |
205 | break; | |
206 | case 0x82: | |
207 | level2->sizekb = 256; level2->assoc = 8; level2->line = 32; | |
208 | break; | |
209 | case 0x83: | |
210 | level2->sizekb = 512; level2->assoc = 8; level2->line = 32; | |
211 | break; | |
212 | case 0x84: | |
213 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; | |
214 | break; | |
215 | case 0x85: | |
216 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; | |
217 | break; | |
218 | case 0x86: | |
219 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
220 | break; | |
221 | case 0x87: | |
222 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
223 | ||
224 | default: | |
225 | break; | |
226 | } | |
227 | } | |
2711355f | 228 | |
cb0dee88 | 229 | /* Detect cache parameters using CPUID function 2. */ |
2711355f | 230 | |
cb0dee88 UB |
231 | static void |
232 | detect_caches_cpuid2 (bool xeon_mp, | |
233 | struct cache_desc *level1, struct cache_desc *level2) | |
234 | { | |
dc8bd8d9 UB |
235 | unsigned regs[4]; |
236 | int nreps, i; | |
cb0dee88 | 237 | |
dc8bd8d9 | 238 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 | 239 | |
dc8bd8d9 UB |
240 | nreps = regs[0] & 0x0f; |
241 | regs[0] &= ~0x0f; | |
cb0dee88 UB |
242 | |
243 | while (--nreps >= 0) | |
2711355f | 244 | { |
dc8bd8d9 UB |
245 | for (i = 0; i < 4; i++) |
246 | if (regs[i] && !((regs[i] >> 31) & 1)) | |
247 | decode_caches_intel (regs[i], xeon_mp, level1, level2); | |
cb0dee88 UB |
248 | |
249 | if (nreps) | |
dc8bd8d9 | 250 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 UB |
251 | } |
252 | } | |
2711355f | 253 | |
cb0dee88 UB |
254 | /* Detect cache parameters using CPUID function 4. This |
255 | method doesn't require hardcoded tables. */ | |
2711355f | 256 | |
cb0dee88 UB |
257 | enum cache_type |
258 | { | |
259 | CACHE_END = 0, | |
260 | CACHE_DATA = 1, | |
261 | CACHE_INST = 2, | |
262 | CACHE_UNIFIED = 3 | |
263 | }; | |
264 | ||
265 | static void | |
a0463099 AK |
266 | detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, |
267 | struct cache_desc *level3) | |
cb0dee88 UB |
268 | { |
269 | struct cache_desc *cache; | |
270 | ||
271 | unsigned eax, ebx, ecx, edx; | |
272 | int count; | |
273 | ||
274 | for (count = 0;; count++) | |
275 | { | |
276 | __cpuid_count(4, count, eax, ebx, ecx, edx); | |
277 | switch (eax & 0x1f) | |
278 | { | |
279 | case CACHE_END: | |
280 | return; | |
281 | case CACHE_DATA: | |
282 | case CACHE_UNIFIED: | |
283 | { | |
284 | switch ((eax >> 5) & 0x07) | |
285 | { | |
286 | case 1: | |
287 | cache = level1; | |
288 | break; | |
289 | case 2: | |
290 | cache = level2; | |
291 | break; | |
a0463099 AK |
292 | case 3: |
293 | cache = level3; | |
294 | break; | |
cb0dee88 UB |
295 | default: |
296 | cache = NULL; | |
297 | } | |
298 | ||
299 | if (cache) | |
300 | { | |
301 | unsigned sets = ecx + 1; | |
dc8bd8d9 | 302 | unsigned part = ((ebx >> 12) & 0x03ff) + 1; |
cb0dee88 | 303 | |
dc8bd8d9 | 304 | cache->assoc = ((ebx >> 22) & 0x03ff) + 1; |
cb0dee88 | 305 | cache->line = (ebx & 0x0fff) + 1; |
cb0dee88 UB |
306 | |
307 | cache->sizekb = (cache->assoc * part | |
308 | * cache->line * sets) / 1024; | |
a0463099 | 309 | } |
cb0dee88 | 310 | } |
2711355f ZD |
311 | default: |
312 | break; | |
313 | } | |
314 | } | |
315 | } | |
316 | ||
cb0dee88 | 317 | /* Returns the description of caches for an Intel processor. */ |
2711355f | 318 | |
d3bfe4de | 319 | static const char * |
a0463099 AK |
320 | detect_caches_intel (bool xeon_mp, unsigned max_level, |
321 | unsigned max_ext_level, unsigned *l2sizekb) | |
2711355f | 322 | { |
a0463099 | 323 | struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0}; |
2711355f | 324 | |
cb0dee88 | 325 | if (max_level >= 4) |
a0463099 | 326 | detect_caches_cpuid4 (&level1, &level2, &level3); |
cb0dee88 UB |
327 | else if (max_level >= 2) |
328 | detect_caches_cpuid2 (xeon_mp, &level1, &level2); | |
329 | else | |
d3bfe4de | 330 | return ""; |
2711355f | 331 | |
cb0dee88 | 332 | if (level1.sizekb == 0) |
d3bfe4de | 333 | return ""; |
2711355f | 334 | |
a0463099 AK |
335 | /* Let the L3 replace the L2. This assumes inclusive caches |
336 | and single threaded program for now. */ | |
337 | if (level3.sizekb) | |
338 | level2 = level3; | |
339 | ||
cb0dee88 UB |
340 | /* Intel CPUs are equipped with AMD style L2 cache info. Try this |
341 | method if other methods fail to provide L2 cache parameters. */ | |
342 | if (level2.sizekb == 0 && max_ext_level >= 0x80000006) | |
343 | detect_l2_cache (&level2); | |
f4a1dd0d | 344 | |
a0463099 AK |
345 | *l2sizekb = level2.sizekb; |
346 | ||
cb0dee88 | 347 | return describe_cache (level1, level2); |
2711355f ZD |
348 | } |
349 | ||
4d947823 UB |
350 | enum vendor_signatures |
351 | { | |
352 | SIG_INTEL = 0x756e6547 /* Genu */, | |
fbdf817d UB |
353 | SIG_AMD = 0x68747541 /* Auth */ |
354 | }; | |
355 | ||
356 | enum processor_signatures | |
357 | { | |
4d947823 UB |
358 | SIG_GEODE = 0x646f6547 /* Geod */ |
359 | }; | |
360 | ||
fa959ce4 MM |
361 | /* This will be called by the spec parser in gcc.c when it sees |
362 | a %:local_cpu_detect(args) construct. Currently it will be called | |
363 | with either "arch" or "tune" as argument depending on if -march=native | |
364 | or -mtune=native is to be substituted. | |
365 | ||
366 | It returns a string containing new command line parameters to be | |
367 | put at the place of the above two options, depending on what CPU | |
368 | this is executed. E.g. "-march=k8" on an AMD64 machine | |
369 | for -march=native. | |
370 | ||
371 | ARGC and ARGV are set depending on the actual arguments given | |
372 | in the spec. */ | |
b3172cab | 373 | |
fa959ce4 MM |
374 | const char *host_detect_local_cpu (int argc, const char **argv) |
375 | { | |
b3172cab UB |
376 | enum processor_type processor = PROCESSOR_I386; |
377 | const char *cpu = "i386"; | |
378 | ||
2711355f | 379 | const char *cache = ""; |
5be6cb59 | 380 | const char *options = ""; |
b3172cab | 381 | |
cb0dee88 | 382 | unsigned int eax, ebx, ecx, edx; |
b3172cab UB |
383 | |
384 | unsigned int max_level, ext_level; | |
cb0dee88 | 385 | |
fa959ce4 | 386 | unsigned int vendor; |
cb0dee88 | 387 | unsigned int model, family; |
b3172cab UB |
388 | |
389 | unsigned int has_sse3, has_ssse3, has_cmpxchg16b; | |
390 | unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; | |
391 | ||
392 | /* Extended features */ | |
393 | unsigned int has_lahf_lm = 0, has_sse4a = 0; | |
394 | unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; | |
634fa334 L |
395 | unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; |
396 | unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0; | |
8ad9d49e | 397 | unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; |
1133125e | 398 | unsigned int has_fma4 = 0, has_xop = 0; |
94d13ad1 | 399 | unsigned int has_bmi = 0, has_tbm = 0; |
b3172cab | 400 | |
edccdcb1 L |
401 | bool arch; |
402 | ||
a0463099 AK |
403 | unsigned int l2sizekb = 0; |
404 | ||
edccdcb1 L |
405 | if (argc < 1) |
406 | return NULL; | |
407 | ||
b3172cab UB |
408 | arch = !strcmp (argv[0], "arch"); |
409 | ||
edccdcb1 | 410 | if (!arch && strcmp (argv[0], "tune")) |
fa959ce4 MM |
411 | return NULL; |
412 | ||
b3172cab UB |
413 | max_level = __get_cpuid_max (0, &vendor); |
414 | if (max_level < 1) | |
fa959ce4 | 415 | goto done; |
fa959ce4 | 416 | |
b3172cab | 417 | __cpuid (1, eax, ebx, ecx, edx); |
fa959ce4 | 418 | |
cb0dee88 | 419 | model = (eax >> 4) & 0x0f; |
b3172cab | 420 | family = (eax >> 8) & 0x0f; |
37c50435 L |
421 | if (vendor == SIG_INTEL) |
422 | { | |
423 | unsigned int extended_model, extended_family; | |
424 | ||
425 | extended_model = (eax >> 12) & 0xf0; | |
426 | extended_family = (eax >> 20) & 0xff; | |
427 | if (family == 0x0f) | |
428 | { | |
429 | family += extended_family; | |
430 | model += extended_model; | |
431 | } | |
432 | else if (family == 0x06) | |
433 | model += extended_model; | |
434 | } | |
b3172cab UB |
435 | |
436 | has_sse3 = ecx & bit_SSE3; | |
437 | has_ssse3 = ecx & bit_SSSE3; | |
634fa334 L |
438 | has_sse4_1 = ecx & bit_SSE4_1; |
439 | has_sse4_2 = ecx & bit_SSE4_2; | |
440 | has_avx = ecx & bit_AVX; | |
b3172cab | 441 | has_cmpxchg16b = ecx & bit_CMPXCHG16B; |
cabf85c3 | 442 | has_movbe = ecx & bit_MOVBE; |
634fa334 L |
443 | has_popcnt = ecx & bit_POPCNT; |
444 | has_aes = ecx & bit_AES; | |
445 | has_pclmul = ecx & bit_PCLMUL; | |
fa959ce4 | 446 | |
b3172cab UB |
447 | has_cmpxchg8b = edx & bit_CMPXCHG8B; |
448 | has_cmov = edx & bit_CMOV; | |
449 | has_mmx = edx & bit_MMX; | |
450 | has_sse = edx & bit_SSE; | |
451 | has_sse2 = edx & bit_SSE2; | |
452 | ||
453 | /* Check cpuid level of extended features. */ | |
454 | __cpuid (0x80000000, ext_level, ebx, ecx, edx); | |
455 | ||
456 | if (ext_level > 0x80000000) | |
fa959ce4 | 457 | { |
b3172cab | 458 | __cpuid (0x80000001, eax, ebx, ecx, edx); |
fa959ce4 | 459 | |
b3172cab UB |
460 | has_lahf_lm = ecx & bit_LAHF_LM; |
461 | has_sse4a = ecx & bit_SSE4a; | |
c3d34a78 | 462 | has_abm = ecx & bit_ABM; |
8ad9d49e | 463 | has_lwp = ecx & bit_LWP; |
1133125e HJ |
464 | has_fma4 = ecx & bit_FMA4; |
465 | has_xop = ecx & bit_XOP; | |
94d13ad1 | 466 | has_tbm = ecx & bit_TBM; |
b3172cab UB |
467 | |
468 | has_longmode = edx & bit_LM; | |
469 | has_3dnowp = edx & bit_3DNOWP; | |
470 | has_3dnow = edx & bit_3DNOW; | |
91afcfa3 QN |
471 | |
472 | __cpuid (0x7, eax, ebx, ecx, edx); | |
473 | ||
474 | has_bmi = ebx & bit_BMI; | |
b3172cab | 475 | } |
fa959ce4 | 476 | |
2711355f ZD |
477 | if (!arch) |
478 | { | |
4d947823 | 479 | if (vendor == SIG_AMD) |
2711355f | 480 | cache = detect_caches_amd (ext_level); |
4d947823 | 481 | else if (vendor == SIG_INTEL) |
cb0dee88 UB |
482 | { |
483 | bool xeon_mp = (family == 15 && model == 6); | |
a0463099 AK |
484 | cache = detect_caches_intel (xeon_mp, max_level, |
485 | ext_level, &l2sizekb); | |
cb0dee88 | 486 | } |
2711355f ZD |
487 | } |
488 | ||
4d947823 | 489 | if (vendor == SIG_AMD) |
fa959ce4 | 490 | { |
fbdf817d | 491 | unsigned int name; |
b3172cab | 492 | |
fbdf817d UB |
493 | /* Detect geode processor by its processor signature. */ |
494 | if (ext_level > 0x80000001) | |
495 | __cpuid (0x80000002, name, ebx, ecx, edx); | |
496 | else | |
497 | name = 0; | |
498 | ||
499 | if (name == SIG_GEODE) | |
500 | processor = PROCESSOR_GEODE; | |
1133125e HJ |
501 | else if (has_xop) |
502 | processor = PROCESSOR_BDVER1; | |
fbdf817d | 503 | else if (has_sse4a) |
35a63f21 | 504 | processor = PROCESSOR_AMDFAM10; |
fbdf817d UB |
505 | else if (has_sse2 || has_longmode) |
506 | processor = PROCESSOR_K8; | |
507 | else if (has_3dnowp) | |
508 | processor = PROCESSOR_ATHLON; | |
509 | else if (has_mmx) | |
510 | processor = PROCESSOR_K6; | |
511 | else | |
512 | processor = PROCESSOR_PENTIUM; | |
fa959ce4 MM |
513 | } |
514 | else | |
515 | { | |
edccdcb1 L |
516 | switch (family) |
517 | { | |
b3172cab UB |
518 | case 4: |
519 | processor = PROCESSOR_I486; | |
520 | break; | |
edccdcb1 | 521 | case 5: |
b3172cab | 522 | processor = PROCESSOR_PENTIUM; |
edccdcb1 L |
523 | break; |
524 | case 6: | |
525 | processor = PROCESSOR_PENTIUMPRO; | |
526 | break; | |
527 | case 15: | |
528 | processor = PROCESSOR_PENTIUM4; | |
529 | break; | |
530 | default: | |
b3172cab UB |
531 | /* We have no idea. */ |
532 | processor = PROCESSOR_GENERIC32; | |
edccdcb1 L |
533 | } |
534 | } | |
535 | ||
536 | switch (processor) | |
537 | { | |
538 | case PROCESSOR_I386: | |
b3172cab | 539 | /* Default. */ |
edccdcb1 L |
540 | break; |
541 | case PROCESSOR_I486: | |
542 | cpu = "i486"; | |
543 | break; | |
544 | case PROCESSOR_PENTIUM: | |
b3172cab | 545 | if (arch && has_mmx) |
edccdcb1 L |
546 | cpu = "pentium-mmx"; |
547 | else | |
548 | cpu = "pentium"; | |
549 | break; | |
550 | case PROCESSOR_PENTIUMPRO: | |
44f276c6 | 551 | switch (model) |
edccdcb1 | 552 | { |
44f276c6 L |
553 | case 0x1c: |
554 | case 0x26: | |
555 | /* Atom. */ | |
556 | cpu = "atom"; | |
557 | break; | |
558 | case 0x1a: | |
559 | case 0x1e: | |
560 | case 0x1f: | |
561 | case 0x2e: | |
eefe143b L |
562 | /* Nehalem. */ |
563 | cpu = "corei7"; | |
44f276c6 L |
564 | break; |
565 | case 0x25: | |
12bbb78f | 566 | case 0x2c: |
44f276c6 | 567 | case 0x2f: |
eefe143b L |
568 | /* Westmere. */ |
569 | cpu = "corei7"; | |
44f276c6 | 570 | break; |
35758e5b L |
571 | case 0x2a: |
572 | /* Sandy Bridge. */ | |
573 | cpu = "corei7-avx"; | |
574 | break; | |
44f276c6 L |
575 | case 0x17: |
576 | case 0x1d: | |
eefe143b | 577 | /* Penryn. */ |
44f276c6 L |
578 | cpu = "core2"; |
579 | break; | |
580 | case 0x0f: | |
eefe143b | 581 | /* Merom. */ |
44f276c6 L |
582 | cpu = "core2"; |
583 | break; | |
584 | default: | |
585 | if (arch) | |
586 | { | |
587 | if (has_ssse3) | |
588 | /* If it is an unknown CPU with SSSE3, assume Core 2. */ | |
589 | cpu = "core2"; | |
590 | else if (has_sse3) | |
591 | /* It is Core Duo. */ | |
592 | cpu = "pentium-m"; | |
593 | else if (has_sse2) | |
594 | /* It is Pentium M. */ | |
595 | cpu = "pentium-m"; | |
596 | else if (has_sse) | |
597 | /* It is Pentium III. */ | |
598 | cpu = "pentium3"; | |
599 | else if (has_mmx) | |
600 | /* It is Pentium II. */ | |
601 | cpu = "pentium2"; | |
602 | else | |
603 | /* Default to Pentium Pro. */ | |
604 | cpu = "pentiumpro"; | |
605 | } | |
b3172cab | 606 | else |
44f276c6 L |
607 | /* For -mtune, we default to -mtune=generic. */ |
608 | cpu = "generic"; | |
609 | break; | |
fa959ce4 | 610 | } |
b3172cab UB |
611 | break; |
612 | case PROCESSOR_PENTIUM4: | |
613 | if (has_sse3) | |
fa959ce4 | 614 | { |
b3172cab UB |
615 | if (has_longmode) |
616 | cpu = "nocona"; | |
fa959ce4 | 617 | else |
b3172cab | 618 | cpu = "prescott"; |
fa959ce4 | 619 | } |
b3172cab UB |
620 | else |
621 | cpu = "pentium4"; | |
edccdcb1 L |
622 | break; |
623 | case PROCESSOR_GEODE: | |
624 | cpu = "geode"; | |
625 | break; | |
626 | case PROCESSOR_K6: | |
b3172cab UB |
627 | if (arch && has_3dnow) |
628 | cpu = "k6-3"; | |
edccdcb1 L |
629 | else |
630 | cpu = "k6"; | |
631 | break; | |
632 | case PROCESSOR_ATHLON: | |
b3172cab | 633 | if (arch && has_sse) |
edccdcb1 L |
634 | cpu = "athlon-4"; |
635 | else | |
636 | cpu = "athlon"; | |
637 | break; | |
edccdcb1 | 638 | case PROCESSOR_K8: |
b3172cab UB |
639 | if (arch && has_sse3) |
640 | cpu = "k8-sse3"; | |
641 | else | |
642 | cpu = "k8"; | |
edccdcb1 | 643 | break; |
35a63f21 DR |
644 | case PROCESSOR_AMDFAM10: |
645 | cpu = "amdfam10"; | |
646 | break; | |
1133125e HJ |
647 | case PROCESSOR_BDVER1: |
648 | cpu = "bdver1"; | |
649 | break; | |
b3172cab | 650 | |
edccdcb1 | 651 | default: |
b3172cab UB |
652 | /* Use something reasonable. */ |
653 | if (arch) | |
654 | { | |
655 | if (has_ssse3) | |
656 | cpu = "core2"; | |
657 | else if (has_sse3) | |
658 | { | |
659 | if (has_longmode) | |
660 | cpu = "nocona"; | |
661 | else | |
662 | cpu = "prescott"; | |
663 | } | |
664 | else if (has_sse2) | |
665 | cpu = "pentium4"; | |
666 | else if (has_cmov) | |
667 | cpu = "pentiumpro"; | |
668 | else if (has_mmx) | |
669 | cpu = "pentium-mmx"; | |
670 | else if (has_cmpxchg8b) | |
671 | cpu = "pentium"; | |
672 | } | |
673 | else | |
674 | cpu = "generic"; | |
fa959ce4 MM |
675 | } |
676 | ||
5be6cb59 UB |
677 | if (arch) |
678 | { | |
679 | if (has_cmpxchg16b) | |
f3afc8a7 | 680 | options = concat (options, " -mcx16", NULL); |
5be6cb59 | 681 | if (has_lahf_lm) |
f3afc8a7 | 682 | options = concat (options, " -msahf", NULL); |
cabf85c3 | 683 | if (has_movbe) |
f3afc8a7 | 684 | options = concat (options, " -mmovbe", NULL); |
634fa334 | 685 | if (has_aes) |
f3afc8a7 | 686 | options = concat (options, " -maes", NULL); |
634fa334 | 687 | if (has_pclmul) |
f3afc8a7 | 688 | options = concat (options, " -mpclmul", NULL); |
634fa334 | 689 | if (has_popcnt) |
f3afc8a7 | 690 | options = concat (options, " -mpopcnt", NULL); |
c3d34a78 SP |
691 | if (has_abm) |
692 | options = concat (options, " -mabm", NULL); | |
8ad9d49e SP |
693 | if (has_lwp) |
694 | options = concat (options, " -mlwp", NULL); | |
1133125e HJ |
695 | if (has_fma4) |
696 | options = concat (options, " -mfma4", NULL); | |
697 | if (has_xop) | |
698 | options = concat (options, " -mxop", NULL); | |
91afcfa3 QN |
699 | if (has_bmi) |
700 | options = concat (options, " -mbmi", NULL); | |
94d13ad1 QN |
701 | if (has_tbm) |
702 | options = concat (options, " -mtbm", NULL); | |
f3afc8a7 | 703 | |
634fa334 | 704 | if (has_avx) |
f3afc8a7 | 705 | options = concat (options, " -mavx", NULL); |
634fa334 | 706 | else if (has_sse4_2) |
f3afc8a7 | 707 | options = concat (options, " -msse4.2", NULL); |
634fa334 | 708 | else if (has_sse4_1) |
f3afc8a7 | 709 | options = concat (options, " -msse4.1", NULL); |
5be6cb59 UB |
710 | } |
711 | ||
fa959ce4 | 712 | done: |
f3afc8a7 | 713 | return concat (cache, "-m", argv[0], "=", cpu, options, NULL); |
fa959ce4 MM |
714 | } |
715 | #else | |
b3172cab | 716 | |
f3afc8a7 UB |
717 | /* If we aren't compiling with GCC then the driver will just ignore |
718 | -march and -mtune "native" target and will leave to the newly | |
719 | built compiler to generate code for its default target. */ | |
b3172cab | 720 | |
f3afc8a7 UB |
721 | const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED, |
722 | const char **argv ATTRIBUTE_UNUSED) | |
fa959ce4 | 723 | { |
f3afc8a7 | 724 | return NULL; |
fa959ce4 | 725 | } |
a6ecb05c | 726 | #endif /* __GNUC__ */ |