[thirdparty/gcc.git] / gcc / config / i386 / driver-i386.c

/* Subroutines for the gcc driver.
   Copyright (C) 2006, 2007 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <stdlib.h>

const char *host_detect_local_cpu (int argc, const char **argv);

#ifdef GCC_VERSION
#include "cpuid.h"

/* Returns parameters that describe L1_ASSOC associative cache of size
   L1_SIZEKB with lines of size L1_LINE.  */

static char *
describe_cache (unsigned l1_sizekb, unsigned l1_line,
		unsigned l1_assoc ATTRIBUTE_UNUSED)
{
  char size[100], line[100];

  /* At the moment, gcc middle-end does not use the information about the
     associativity of the cache.  */

  sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
  sprintf (line, "--param l1-cache-line-size=%u", l1_line);

  return concat (size, " ", line, " ", NULL);
}

/* Returns the description of caches for an AMD processor.  */

static char *
detect_caches_amd (unsigned max_ext_level)
{
  unsigned eax, ebx, ecx, edx;
  unsigned l1_sizekb, l1_line, l1_assoc;

  if (max_ext_level < 0x80000005)
    return (char *) "";

  __cpuid (0x80000005, eax, ebx, ecx, edx);

  l1_line = ecx & 0xff;
  l1_sizekb = (ecx >> 24) & 0xff;
  l1_assoc = (ecx >> 16) & 0xff;

  return describe_cache (l1_sizekb, l1_line, l1_assoc);
}

/* Stores the size of the L1 cache and cache line, and the associativity
   of the cache according to REG to L1_SIZEKB, L1_LINE and L1_ASSOC.  */

static void
decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
		     unsigned *l1_assoc)
{
  unsigned i, val;

  if (((reg >> 31) & 1) != 0)
    return;

  for (i = 0; i < 4; i++)
    {
      val = reg & 0xff;
      reg >>= 8;

      switch (val)
	{
	case 0xa:
	  *l1_sizekb = 8;
	  *l1_line = 32;
	  *l1_assoc = 2;
	  break;
	case 0xc:
	  *l1_sizekb = 16;
	  *l1_line = 32;
	  *l1_assoc = 4;
	  break;
	case 0x2c:
	  *l1_sizekb = 32;
	  *l1_line = 64;
	  *l1_assoc = 8;
	  break;
	case 0x60:
	  *l1_sizekb = 16;
	  *l1_line = 64;
	  *l1_assoc = 8;
	  break;
	case 0x66:
	  *l1_sizekb = 8;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;
	case 0x67:
	  *l1_sizekb = 16;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;
	case 0x68:
	  *l1_sizekb = 32;
	  *l1_line = 64;
	  *l1_assoc = 4;
	  break;

	default:
	  break;
	}
    }
}

/* Returns the description of caches for an intel processor.  */

static char *
detect_caches_intel (unsigned max_level)
{
  unsigned eax, ebx, ecx, edx;
  unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;

  if (max_level < 2)
    return (char *) "";

  __cpuid (2, eax, ebx, ecx, edx);

  decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc);
  decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc);
  decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc);
  decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc);

  if (!l1_sizekb)
    return (char *) "";

  return describe_cache (l1_sizekb, l1_line, assoc);
}

/* This will be called by the spec parser in gcc.c when it sees
   a %:local_cpu_detect(args) construct.  Currently it will be called
   with either "arch" or "tune" as argument depending on if -march=native
   or -mtune=native is to be substituted.

   It returns a string containing new command line parameters to be
   put at the place of the above two options, depending on what CPU
   this is executed.  E.g. "-march=k8" on an AMD64 machine
   for -march=native.

   ARGC and ARGV are set depending on the actual arguments given
   in the spec.  */

const char *host_detect_local_cpu (int argc, const char **argv)
{
  enum processor_type processor = PROCESSOR_I386;
  const char *cpu = "i386";

  const char *cache = "";
  const char *options = "";

 unsigned int eax, ebx, ecx, edx;

  unsigned int max_level, ext_level;
  unsigned int vendor;
  unsigned int family;

  unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
  unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;

  /* Extended features */
  unsigned int has_lahf_lm = 0, has_sse4a = 0;
  unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;

  bool arch;

  if (argc < 1)
    return NULL;

  arch = !strcmp (argv[0], "arch");

  if (!arch && strcmp (argv[0], "tune"))
    return NULL;

  max_level = __get_cpuid_max (0, &vendor);
  if (max_level < 1)
    goto done;

  __cpuid (1, eax, ebx, ecx, edx);

  /* We don't care for extended family.  */
  family = (eax >> 8) & 0x0f;

  has_sse3 = ecx & bit_SSE3;
  has_ssse3 = ecx & bit_SSSE3;
  has_cmpxchg16b = ecx & bit_CMPXCHG16B;

  has_cmpxchg8b = edx & bit_CMPXCHG8B;
  has_cmov = edx & bit_CMOV;
  has_mmx = edx & bit_MMX;
  has_sse = edx & bit_SSE;
  has_sse2 = edx & bit_SSE2;

  /* Check cpuid level of extended features.  */
  __cpuid (0x80000000, ext_level, ebx, ecx, edx);

  if (ext_level > 0x80000000)
    {
      __cpuid (0x80000001, eax, ebx, ecx, edx);

      has_lahf_lm = ecx & bit_LAHF_LM;
      has_sse4a = ecx & bit_SSE4a;

      has_longmode = edx & bit_LM;
      has_3dnowp = edx & bit_3DNOWP;
      has_3dnow = edx & bit_3DNOW;
    }

  if (!arch)
    {
      if (vendor == *(unsigned int*) "Auth")
	cache = detect_caches_amd (ext_level);
      else if (vendor == *(unsigned int*) "Genu")
	cache = detect_caches_intel (max_level);
    }

  if (vendor == *(unsigned int*) "Auth")
    {
      processor = PROCESSOR_PENTIUM;

      if (has_mmx)
	processor = PROCESSOR_K6;
      if (has_3dnowp)
	processor = PROCESSOR_ATHLON;
      if (has_sse2 || has_longmode)
	processor = PROCESSOR_K8;
      if (has_sse4a)
	processor = PROCESSOR_AMDFAM10;
    }
  else if (vendor == *(unsigned int*) "Geod")
    processor = PROCESSOR_GEODE;
  else
    {
      switch (family)
	{
	case 4:
	  processor = PROCESSOR_I486;
	  break;
	case 5:
	  processor = PROCESSOR_PENTIUM;
	  break;
	case 6:
	  processor = PROCESSOR_PENTIUMPRO;
	  break;
	case 15:
	  processor = PROCESSOR_PENTIUM4;
	  break;
	default:
	  /* We have no idea.  */
	  processor = PROCESSOR_GENERIC32;
	}
    }

  switch (processor)
    {
    case PROCESSOR_I386:
      /* Default.  */
      break;
    case PROCESSOR_I486:
      cpu = "i486";
      break;
    case PROCESSOR_PENTIUM:
      if (arch && has_mmx)
	cpu = "pentium-mmx";
      else
	cpu = "pentium";
      break;
    case PROCESSOR_PENTIUMPRO:
      if (has_longmode)
	/* It is Core 2 Duo.  */
	cpu = "core2";
      else if (arch)
	{
	  if (has_sse3)
	    /* It is Core Duo.  */
	    cpu = "prescott";
	  else if (has_sse2)
	    /* It is Pentium M.  */
	    cpu = "pentium-m";
	  else if (has_sse)
	    /* It is Pentium III.  */
	    cpu = "pentium3";
	  else if (has_mmx)
	    /* It is Pentium II.  */
	    cpu = "pentium2";
	  else
	    /* Default to Pentium Pro.  */
	    cpu = "pentiumpro";
	}
      else
	/* For -mtune, we default to -mtune=generic.  */
	cpu = "generic";
      break;
    case PROCESSOR_PENTIUM4:
      if (has_sse3)
	{
	  if (has_longmode)
	    cpu = "nocona";
	  else
	    cpu = "prescott";
	}
      else
	cpu = "pentium4";
      break;
    case PROCESSOR_GEODE:
      cpu = "geode";
      break;
    case PROCESSOR_K6:
      if (arch && has_3dnow)
	cpu = "k6-3";
      else
	cpu = "k6";
      break;
    case PROCESSOR_ATHLON:
      if (arch && has_sse)
	cpu = "athlon-4";
      else
	cpu = "athlon";
      break;
    case PROCESSOR_K8:
      if (arch && has_sse3)
	cpu = "k8-sse3";
      else
	cpu = "k8";
      break;
    case PROCESSOR_AMDFAM10:
      cpu = "amdfam10";
      break;

    default:
      /* Use something reasonable.  */
      if (arch)
	{
	  if (has_ssse3)
	    cpu = "core2";
	  else if (has_sse3)
	    {
	      if (has_longmode)
		cpu = "nocona";
	      else
		cpu = "prescott";
	    }
	  else if (has_sse2)
	    cpu = "pentium4";
	  else if (has_cmov)
	    cpu = "pentiumpro";
	  else if (has_mmx)
	    cpu = "pentium-mmx";
	  else if (has_cmpxchg8b)
	    cpu = "pentium";
	}
      else
	cpu = "generic";
    }

  if (arch)
    {
      if (has_cmpxchg16b)
	options = concat (options, "-mcx16 ", NULL);
      if (has_lahf_lm)
	options = concat (options, "-msahf ", NULL);
    }

done:
  return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
}
#else

/* If we aren't compiling with GCC we just provide a minimal
   default value.  */

const char *host_detect_local_cpu (int argc, const char **argv)
{
  const char *cpu;
  bool arch;

  if (argc < 1)
    return NULL;

  arch = !strcmp (argv[0], "arch");

  if (!arch && strcmp (argv[0], "tune"))
    return NULL;
  
  if (arch)
    {
      /* FIXME: i386 is wrong for 64bit compiler.  How can we tell if
	 we are generating 64bit or 32bit code?  */
      cpu = "i386";
    }
  else
    cpu = "generic";

  return concat ("-m", argv[0], "=", cpu, NULL);
}
#endif /* GCC_VERSION */
Commit	Line	Data
fa959ce4	1	/* Subroutines for the gcc driver.
35a63f21	2	Copyright (C) 2006, 2007 Free Software Foundation, Inc.
fa959ce4 MM	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
2f83c7d6	8	the Free Software Foundation; either version 3, or (at your option)
fa959ce4 MM	9	any later version.
	10
	11	GCC is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	<http://www.gnu.org/licenses/>. */
fa959ce4 MM	19
	20	#include "config.h"
	21	#include "system.h"
edccdcb1 L	22	#include "coretypes.h"
edccdcb1 L	23	#include "tm.h"
fa959ce4 MM	24	#include <stdlib.h>
fa959ce4 MM	25
895016f6 UB	26	const char host_detect_local_cpu (int argc, const char *argv);
895016f6 UB	27
fa959ce4	28	#ifdef GCC_VERSION
b3172cab	29	#include "cpuid.h"
fa959ce4	30
2711355f ZD	31	/* Returns parameters that describe L1_ASSOC associative cache of size
	32	L1_SIZEKB with lines of size L1_LINE. */
	33
	34	static char *
	35	describe_cache (unsigned l1_sizekb, unsigned l1_line,
	36	unsigned l1_assoc ATTRIBUTE_UNUSED)
	37	{
b3172cab	38	char size[100], line[100];
2711355f ZD	39
	40	/* At the moment, gcc middle-end does not use the information about the
	41	associativity of the cache. */
	42
46cb0441	43	sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
2711355f ZD	44	sprintf (line, "--param l1-cache-line-size=%u", l1_line);
	45
	46	return concat (size, " ", line, " ", NULL);
	47	}
	48
	49	/* Returns the description of caches for an AMD processor. */
	50
	51	static char *
	52	detect_caches_amd (unsigned max_ext_level)
	53	{
	54	unsigned eax, ebx, ecx, edx;
	55	unsigned l1_sizekb, l1_line, l1_assoc;
	56
	57	if (max_ext_level < 0x80000005)
b3172cab	58	return (char *) "";
2711355f	59
b3172cab	60	__cpuid (0x80000005, eax, ebx, ecx, edx);
2711355f ZD	61
	62	l1_line = ecx & 0xff;
	63	l1_sizekb = (ecx >> 24) & 0xff;
	64	l1_assoc = (ecx >> 16) & 0xff;
	65
	66	return describe_cache (l1_sizekb, l1_line, l1_assoc);
	67	}
	68
	69	/* Stores the size of the L1 cache and cache line, and the associativity
	70	of the cache according to REG to L1_SIZEKB, L1_LINE and L1_ASSOC. */
	71
	72	static void
	73	decode_caches_intel (unsigned reg, unsigned l1_sizekb, unsigned l1_line,
	74	unsigned *l1_assoc)
	75	{
	76	unsigned i, val;
	77
	78	if (((reg >> 31) & 1) != 0)
	79	return;
	80
	81	for (i = 0; i < 4; i++)
	82	{
	83	val = reg & 0xff;
	84	reg >>= 8;
	85
	86	switch (val)
	87	{
	88	case 0xa:
	89	*l1_sizekb = 8;
	90	*l1_line = 32;
	91	*l1_assoc = 2;
	92	break;
	93	case 0xc:
	94	*l1_sizekb = 16;
	95	*l1_line = 32;
	96	*l1_assoc = 4;
	97	break;
	98	case 0x2c:
	99	*l1_sizekb = 32;
	100	*l1_line = 64;
	101	*l1_assoc = 8;
	102	break;
	103	case 0x60:
	104	*l1_sizekb = 16;
	105	*l1_line = 64;
	106	*l1_assoc = 8;
	107	break;
	108	case 0x66:
	109	*l1_sizekb = 8;
	110	*l1_line = 64;
	111	*l1_assoc = 4;
	112	break;
	113	case 0x67:
	114	*l1_sizekb = 16;
	115	*l1_line = 64;
	116	*l1_assoc = 4;
	117	break;
	118	case 0x68:
	119	*l1_sizekb = 32;
	120	*l1_line = 64;
	121	*l1_assoc = 4;
	122	break;
	123
	124	default:
125	break;
126	}
127	}
128	}
129
130	/* Returns the description of caches for an intel processor. */
131
132	static char *
133	detect_caches_intel (unsigned max_level)
134	{
135	unsigned eax, ebx, ecx, edx;
136	unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
137
138	if (max_level < 2)
b3172cab	139	return (char *) "";
2711355f	140
b3172cab	141	__cpuid (2, eax, ebx, ecx, edx);
2711355f ZD	142
	143	decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc);
	144	decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc);
	145	decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc);
	146	decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc);
b3172cab	147
2711355f ZD	148	if (!l1_sizekb)
	149	return (char *) "";
	150
	151	return describe_cache (l1_sizekb, l1_line, assoc);
	152	}
	153
fa959ce4 MM	154	/* This will be called by the spec parser in gcc.c when it sees
	155	a %:local_cpu_detect(args) construct. Currently it will be called
	156	with either "arch" or "tune" as argument depending on if -march=native
	157	or -mtune=native is to be substituted.
	158
	159	It returns a string containing new command line parameters to be
	160	put at the place of the above two options, depending on what CPU
	161	this is executed. E.g. "-march=k8" on an AMD64 machine
	162	for -march=native.
	163
	164	ARGC and ARGV are set depending on the actual arguments given
	165	in the spec. */
b3172cab	166
fa959ce4 MM	167	const char host_detect_local_cpu (int argc, const char *argv)
fa959ce4 MM	168	{
b3172cab UB	169	enum processor_type processor = PROCESSOR_I386;
	170	const char *cpu = "i386";
	171
2711355f	172	const char *cache = "";
5be6cb59	173	const char *options = "";
b3172cab UB	174
	175	unsigned int eax, ebx, ecx, edx;
	176
	177	unsigned int max_level, ext_level;
fa959ce4	178	unsigned int vendor;
b3172cab UB	179	unsigned int family;
	180
	181	unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
	182	unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
	183
	184	/* Extended features */
	185	unsigned int has_lahf_lm = 0, has_sse4a = 0;
	186	unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
	187
edccdcb1 L	188	bool arch;
	189
	190	if (argc < 1)
	191	return NULL;
	192
b3172cab UB	193	arch = !strcmp (argv[0], "arch");
b3172cab UB	194
edccdcb1	195	if (!arch && strcmp (argv[0], "tune"))
fa959ce4 MM	196	return NULL;
fa959ce4 MM	197
b3172cab UB	198	max_level = __get_cpuid_max (0, &vendor);
b3172cab UB	199	if (max_level < 1)
fa959ce4	200	goto done;
fa959ce4	201
b3172cab	202	__cpuid (1, eax, ebx, ecx, edx);
fa959ce4	203
fa959ce4	204	/* We don't care for extended family. */
b3172cab UB	205	family = (eax >> 8) & 0x0f;
	206
	207	has_sse3 = ecx & bit_SSE3;
	208	has_ssse3 = ecx & bit_SSSE3;
	209	has_cmpxchg16b = ecx & bit_CMPXCHG16B;
fa959ce4	210
b3172cab UB	211	has_cmpxchg8b = edx & bit_CMPXCHG8B;
	212	has_cmov = edx & bit_CMOV;
	213	has_mmx = edx & bit_MMX;
	214	has_sse = edx & bit_SSE;
	215	has_sse2 = edx & bit_SSE2;
	216
	217	/* Check cpuid level of extended features. */
	218	__cpuid (0x80000000, ext_level, ebx, ecx, edx);
	219
	220	if (ext_level > 0x80000000)
fa959ce4	221	{
b3172cab	222	__cpuid (0x80000001, eax, ebx, ecx, edx);
fa959ce4	223
b3172cab UB	224	has_lahf_lm = ecx & bit_LAHF_LM;
	225	has_sse4a = ecx & bit_SSE4a;
	226
	227	has_longmode = edx & bit_LM;
	228	has_3dnowp = edx & bit_3DNOWP;
	229	has_3dnow = edx & bit_3DNOW;
	230	}
fa959ce4	231
2711355f ZD	232	if (!arch)
2711355f ZD	233	{
b3172cab	234	if (vendor == (unsigned int) "Auth")
2711355f	235	cache = detect_caches_amd (ext_level);
b3172cab	236	else if (vendor == (unsigned int) "Genu")
2711355f ZD	237	cache = detect_caches_intel (max_level);
	238	}
	239
b3172cab	240	if (vendor == (unsigned int) "Auth")
fa959ce4	241	{
b3172cab UB	242	processor = PROCESSOR_PENTIUM;
b3172cab UB	243
fa959ce4	244	if (has_mmx)
edccdcb1	245	processor = PROCESSOR_K6;
fa959ce4	246	if (has_3dnowp)
edccdcb1	247	processor = PROCESSOR_ATHLON;
fa959ce4	248	if (has_sse2 \|\| has_longmode)
edccdcb1	249	processor = PROCESSOR_K8;
35a63f21 DR	250	if (has_sse4a)
35a63f21 DR	251	processor = PROCESSOR_AMDFAM10;
fa959ce4	252	}
b3172cab UB	253	else if (vendor == (unsigned int) "Geod")
b3172cab UB	254	processor = PROCESSOR_GEODE;
fa959ce4 MM	255	else
fa959ce4 MM	256	{
edccdcb1 L	257	switch (family)
edccdcb1 L	258	{
b3172cab UB	259	case 4:
	260	processor = PROCESSOR_I486;
	261	break;
edccdcb1	262	case 5:
b3172cab	263	processor = PROCESSOR_PENTIUM;
edccdcb1 L	264	break;
	265	case 6:
	266	processor = PROCESSOR_PENTIUMPRO;
	267	break;
	268	case 15:
	269	processor = PROCESSOR_PENTIUM4;
	270	break;
	271	default:
b3172cab UB	272	/* We have no idea. */
b3172cab UB	273	processor = PROCESSOR_GENERIC32;
edccdcb1 L	274	}
	275	}
	276
	277	switch (processor)
	278	{
	279	case PROCESSOR_I386:
b3172cab	280	/* Default. */
edccdcb1 L	281	break;
	282	case PROCESSOR_I486:
	283	cpu = "i486";
	284	break;
	285	case PROCESSOR_PENTIUM:
b3172cab	286	if (arch && has_mmx)
edccdcb1 L	287	cpu = "pentium-mmx";
	288	else
	289	cpu = "pentium";
	290	break;
	291	case PROCESSOR_PENTIUMPRO:
	292	if (has_longmode)
b3172cab UB	293	/* It is Core 2 Duo. */
	294	cpu = "core2";
	295	else if (arch)
edccdcb1	296	{
b3172cab UB	297	if (has_sse3)
	298	/* It is Core Duo. */
	299	cpu = "prescott";
	300	else if (has_sse2)
	301	/* It is Pentium M. */
	302	cpu = "pentium-m";
	303	else if (has_sse)
	304	/* It is Pentium III. */
	305	cpu = "pentium3";
	306	else if (has_mmx)
	307	/* It is Pentium II. */
	308	cpu = "pentium2";
	309	else
	310	/* Default to Pentium Pro. */
	311	cpu = "pentiumpro";
fa959ce4	312	}
edccdcb1	313	else
b3172cab UB	314	/* For -mtune, we default to -mtune=generic. */
	315	cpu = "generic";
	316	break;
	317	case PROCESSOR_PENTIUM4:
	318	if (has_sse3)
fa959ce4	319	{
b3172cab UB	320	if (has_longmode)
b3172cab UB	321	cpu = "nocona";
fa959ce4	322	else
b3172cab	323	cpu = "prescott";
fa959ce4	324	}
b3172cab UB	325	else
b3172cab UB	326	cpu = "pentium4";
edccdcb1 L	327	break;
	328	case PROCESSOR_GEODE:
	329	cpu = "geode";
	330	break;
	331	case PROCESSOR_K6:
b3172cab UB	332	if (arch && has_3dnow)
b3172cab UB	333	cpu = "k6-3";
edccdcb1 L	334	else
	335	cpu = "k6";
	336	break;
	337	case PROCESSOR_ATHLON:
b3172cab	338	if (arch && has_sse)
edccdcb1 L	339	cpu = "athlon-4";
	340	else
	341	cpu = "athlon";
	342	break;
edccdcb1	343	case PROCESSOR_K8:
b3172cab UB	344	if (arch && has_sse3)
	345	cpu = "k8-sse3";
	346	else
	347	cpu = "k8";
edccdcb1	348	break;
35a63f21 DR	349	case PROCESSOR_AMDFAM10:
	350	cpu = "amdfam10";
	351	break;
b3172cab	352
edccdcb1	353	default:
b3172cab UB	354	/* Use something reasonable. */
	355	if (arch)
	356	{
	357	if (has_ssse3)
	358	cpu = "core2";
	359	else if (has_sse3)
	360	{
	361	if (has_longmode)
	362	cpu = "nocona";
	363	else
	364	cpu = "prescott";
	365	}
	366	else if (has_sse2)
	367	cpu = "pentium4";
	368	else if (has_cmov)
	369	cpu = "pentiumpro";
	370	else if (has_mmx)
	371	cpu = "pentium-mmx";
	372	else if (has_cmpxchg8b)
	373	cpu = "pentium";
	374	}
	375	else
	376	cpu = "generic";
fa959ce4 MM	377	}
fa959ce4 MM	378
5be6cb59 UB	379	if (arch)
	380	{
	381	if (has_cmpxchg16b)
	382	options = concat (options, "-mcx16 ", NULL);
	383	if (has_lahf_lm)
	384	options = concat (options, "-msahf ", NULL);
	385	}
	386
fa959ce4	387	done:
5be6cb59	388	return concat (cache, "-m", argv[0], "=", cpu, " ", options, NULL);
fa959ce4 MM	389	}
fa959ce4 MM	390	#else
b3172cab	391
fa959ce4 MM	392	/* If we aren't compiling with GCC we just provide a minimal
fa959ce4 MM	393	default value. */
b3172cab	394
fa959ce4 MM	395	const char host_detect_local_cpu (int argc, const char *argv)
fa959ce4 MM	396	{
edccdcb1 L	397	const char *cpu;
	398	bool arch;
	399
	400	if (argc < 1)
	401	return NULL;
	402
b3172cab UB	403	arch = !strcmp (argv[0], "arch");
b3172cab UB	404
edccdcb1 L	405	if (!arch && strcmp (argv[0], "tune"))
	406	return NULL;
	407
	408	if (arch)
	409	{
	410	/* FIXME: i386 is wrong for 64bit compiler. How can we tell if
	411	we are generating 64bit or 32bit code? */
	412	cpu = "i386";
	413	}
	414	else
	415	cpu = "generic";
	416
	417	return concat ("-m", argv[0], "=", cpu, NULL);
fa959ce4	418	}
682cd442	419	#endif /* GCC_VERSION */