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fa959ce4 | 1 | /* Subroutines for the gcc driver. |
d1e082c2 | 2 | Copyright (C) 2006-2013 Free Software Foundation, Inc. |
fa959ce4 MM |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
fa959ce4 MM |
9 | any later version. |
10 | ||
11 | GCC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
fa959ce4 MM |
19 | |
20 | #include "config.h" | |
21 | #include "system.h" | |
edccdcb1 L |
22 | #include "coretypes.h" |
23 | #include "tm.h" | |
fa959ce4 | 24 | |
895016f6 UB |
25 | const char *host_detect_local_cpu (int argc, const char **argv); |
26 | ||
a6ecb05c | 27 | #ifdef __GNUC__ |
b3172cab | 28 | #include "cpuid.h" |
fa959ce4 | 29 | |
cb0dee88 UB |
30 | struct cache_desc |
31 | { | |
32 | unsigned sizekb; | |
33 | unsigned assoc; | |
34 | unsigned line; | |
35 | }; | |
36 | ||
37 | /* Returns command line parameters that describe size and | |
38 | cache line size of the processor caches. */ | |
2711355f ZD |
39 | |
40 | static char * | |
cb0dee88 | 41 | describe_cache (struct cache_desc level1, struct cache_desc level2) |
2711355f | 42 | { |
f4a1dd0d | 43 | char size[100], line[100], size2[100]; |
2711355f | 44 | |
cb0dee88 UB |
45 | /* At the moment, gcc does not use the information |
46 | about the associativity of the cache. */ | |
47 | ||
f3afc8a7 UB |
48 | snprintf (size, sizeof (size), |
49 | "--param l1-cache-size=%u ", level1.sizekb); | |
50 | snprintf (line, sizeof (line), | |
51 | "--param l1-cache-line-size=%u ", level1.line); | |
2711355f | 52 | |
f3afc8a7 UB |
53 | snprintf (size2, sizeof (size2), |
54 | "--param l2-cache-size=%u ", level2.sizekb); | |
2711355f | 55 | |
f3afc8a7 | 56 | return concat (size, line, size2, NULL); |
f4a1dd0d ZM |
57 | } |
58 | ||
cb0dee88 UB |
59 | /* Detect L2 cache parameters using CPUID extended function 0x80000006. */ |
60 | ||
f4a1dd0d | 61 | static void |
cb0dee88 | 62 | detect_l2_cache (struct cache_desc *level2) |
f4a1dd0d | 63 | { |
cb0dee88 UB |
64 | unsigned eax, ebx, ecx, edx; |
65 | unsigned assoc; | |
f4a1dd0d ZM |
66 | |
67 | __cpuid (0x80000006, eax, ebx, ecx, edx); | |
68 | ||
cb0dee88 UB |
69 | level2->sizekb = (ecx >> 16) & 0xffff; |
70 | level2->line = ecx & 0xff; | |
71 | ||
f4a1dd0d ZM |
72 | assoc = (ecx >> 12) & 0xf; |
73 | if (assoc == 6) | |
74 | assoc = 8; | |
75 | else if (assoc == 8) | |
76 | assoc = 16; | |
77 | else if (assoc >= 0xa && assoc <= 0xc) | |
78 | assoc = 32 + (assoc - 0xa) * 16; | |
79 | else if (assoc >= 0xd && assoc <= 0xe) | |
80 | assoc = 96 + (assoc - 0xd) * 32; | |
cb0dee88 UB |
81 | |
82 | level2->assoc = assoc; | |
2711355f ZD |
83 | } |
84 | ||
85 | /* Returns the description of caches for an AMD processor. */ | |
86 | ||
d3bfe4de | 87 | static const char * |
2711355f ZD |
88 | detect_caches_amd (unsigned max_ext_level) |
89 | { | |
90 | unsigned eax, ebx, ecx, edx; | |
cb0dee88 UB |
91 | |
92 | struct cache_desc level1, level2 = {0, 0, 0}; | |
2711355f ZD |
93 | |
94 | if (max_ext_level < 0x80000005) | |
d3bfe4de | 95 | return ""; |
2711355f | 96 | |
b3172cab | 97 | __cpuid (0x80000005, eax, ebx, ecx, edx); |
2711355f | 98 | |
cb0dee88 UB |
99 | level1.sizekb = (ecx >> 24) & 0xff; |
100 | level1.assoc = (ecx >> 16) & 0xff; | |
101 | level1.line = ecx & 0xff; | |
2711355f | 102 | |
f4a1dd0d | 103 | if (max_ext_level >= 0x80000006) |
cb0dee88 | 104 | detect_l2_cache (&level2); |
f4a1dd0d | 105 | |
cb0dee88 | 106 | return describe_cache (level1, level2); |
2711355f ZD |
107 | } |
108 | ||
cb0dee88 UB |
109 | /* Decodes the size, the associativity and the cache line size of |
110 | L1/L2 caches of an Intel processor. Values are based on | |
111 | "Intel Processor Identification and the CPUID Instruction" | |
112 | [Application Note 485], revision -032, December 2007. */ | |
2711355f ZD |
113 | |
114 | static void | |
cb0dee88 UB |
115 | decode_caches_intel (unsigned reg, bool xeon_mp, |
116 | struct cache_desc *level1, struct cache_desc *level2) | |
2711355f | 117 | { |
cb0dee88 UB |
118 | int i; |
119 | ||
120 | for (i = 24; i >= 0; i -= 8) | |
121 | switch ((reg >> i) & 0xff) | |
122 | { | |
123 | case 0x0a: | |
124 | level1->sizekb = 8; level1->assoc = 2; level1->line = 32; | |
125 | break; | |
126 | case 0x0c: | |
127 | level1->sizekb = 16; level1->assoc = 4; level1->line = 32; | |
128 | break; | |
129 | case 0x2c: | |
130 | level1->sizekb = 32; level1->assoc = 8; level1->line = 64; | |
131 | break; | |
132 | case 0x39: | |
133 | level2->sizekb = 128; level2->assoc = 4; level2->line = 64; | |
134 | break; | |
135 | case 0x3a: | |
136 | level2->sizekb = 192; level2->assoc = 6; level2->line = 64; | |
137 | break; | |
138 | case 0x3b: | |
139 | level2->sizekb = 128; level2->assoc = 2; level2->line = 64; | |
140 | break; | |
141 | case 0x3c: | |
142 | level2->sizekb = 256; level2->assoc = 4; level2->line = 64; | |
143 | break; | |
144 | case 0x3d: | |
145 | level2->sizekb = 384; level2->assoc = 6; level2->line = 64; | |
146 | break; | |
147 | case 0x3e: | |
148 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
149 | break; | |
150 | case 0x41: | |
151 | level2->sizekb = 128; level2->assoc = 4; level2->line = 32; | |
152 | break; | |
153 | case 0x42: | |
154 | level2->sizekb = 256; level2->assoc = 4; level2->line = 32; | |
155 | break; | |
156 | case 0x43: | |
157 | level2->sizekb = 512; level2->assoc = 4; level2->line = 32; | |
158 | break; | |
159 | case 0x44: | |
160 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 32; | |
161 | break; | |
162 | case 0x45: | |
163 | level2->sizekb = 2048; level2->assoc = 4; level2->line = 32; | |
164 | break; | |
165 | case 0x49: | |
166 | if (xeon_mp) | |
167 | break; | |
168 | level2->sizekb = 4096; level2->assoc = 16; level2->line = 64; | |
169 | break; | |
170 | case 0x4e: | |
171 | level2->sizekb = 6144; level2->assoc = 24; level2->line = 64; | |
172 | break; | |
173 | case 0x60: | |
174 | level1->sizekb = 16; level1->assoc = 8; level1->line = 64; | |
175 | break; | |
176 | case 0x66: | |
177 | level1->sizekb = 8; level1->assoc = 4; level1->line = 64; | |
178 | break; | |
179 | case 0x67: | |
180 | level1->sizekb = 16; level1->assoc = 4; level1->line = 64; | |
181 | break; | |
182 | case 0x68: | |
183 | level1->sizekb = 32; level1->assoc = 4; level1->line = 64; | |
184 | break; | |
185 | case 0x78: | |
186 | level2->sizekb = 1024; level2->assoc = 4; level2->line = 64; | |
187 | break; | |
188 | case 0x79: | |
189 | level2->sizekb = 128; level2->assoc = 8; level2->line = 64; | |
190 | break; | |
191 | case 0x7a: | |
192 | level2->sizekb = 256; level2->assoc = 8; level2->line = 64; | |
193 | break; | |
194 | case 0x7b: | |
195 | level2->sizekb = 512; level2->assoc = 8; level2->line = 64; | |
196 | break; | |
197 | case 0x7c: | |
198 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
199 | break; | |
200 | case 0x7d: | |
201 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 64; | |
202 | break; | |
203 | case 0x7f: | |
204 | level2->sizekb = 512; level2->assoc = 2; level2->line = 64; | |
205 | break; | |
206 | case 0x82: | |
207 | level2->sizekb = 256; level2->assoc = 8; level2->line = 32; | |
208 | break; | |
209 | case 0x83: | |
210 | level2->sizekb = 512; level2->assoc = 8; level2->line = 32; | |
211 | break; | |
212 | case 0x84: | |
213 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 32; | |
214 | break; | |
215 | case 0x85: | |
216 | level2->sizekb = 2048; level2->assoc = 8; level2->line = 32; | |
217 | break; | |
218 | case 0x86: | |
219 | level2->sizekb = 512; level2->assoc = 4; level2->line = 64; | |
220 | break; | |
221 | case 0x87: | |
222 | level2->sizekb = 1024; level2->assoc = 8; level2->line = 64; | |
223 | ||
224 | default: | |
225 | break; | |
226 | } | |
227 | } | |
2711355f | 228 | |
cb0dee88 | 229 | /* Detect cache parameters using CPUID function 2. */ |
2711355f | 230 | |
cb0dee88 UB |
231 | static void |
232 | detect_caches_cpuid2 (bool xeon_mp, | |
233 | struct cache_desc *level1, struct cache_desc *level2) | |
234 | { | |
dc8bd8d9 UB |
235 | unsigned regs[4]; |
236 | int nreps, i; | |
cb0dee88 | 237 | |
dc8bd8d9 | 238 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 | 239 | |
dc8bd8d9 UB |
240 | nreps = regs[0] & 0x0f; |
241 | regs[0] &= ~0x0f; | |
cb0dee88 UB |
242 | |
243 | while (--nreps >= 0) | |
2711355f | 244 | { |
dc8bd8d9 UB |
245 | for (i = 0; i < 4; i++) |
246 | if (regs[i] && !((regs[i] >> 31) & 1)) | |
247 | decode_caches_intel (regs[i], xeon_mp, level1, level2); | |
cb0dee88 UB |
248 | |
249 | if (nreps) | |
dc8bd8d9 | 250 | __cpuid (2, regs[0], regs[1], regs[2], regs[3]); |
cb0dee88 UB |
251 | } |
252 | } | |
2711355f | 253 | |
cb0dee88 UB |
254 | /* Detect cache parameters using CPUID function 4. This |
255 | method doesn't require hardcoded tables. */ | |
2711355f | 256 | |
cb0dee88 UB |
257 | enum cache_type |
258 | { | |
259 | CACHE_END = 0, | |
260 | CACHE_DATA = 1, | |
261 | CACHE_INST = 2, | |
262 | CACHE_UNIFIED = 3 | |
263 | }; | |
264 | ||
265 | static void | |
a0463099 AK |
266 | detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2, |
267 | struct cache_desc *level3) | |
cb0dee88 UB |
268 | { |
269 | struct cache_desc *cache; | |
270 | ||
271 | unsigned eax, ebx, ecx, edx; | |
272 | int count; | |
273 | ||
274 | for (count = 0;; count++) | |
275 | { | |
276 | __cpuid_count(4, count, eax, ebx, ecx, edx); | |
277 | switch (eax & 0x1f) | |
278 | { | |
279 | case CACHE_END: | |
280 | return; | |
281 | case CACHE_DATA: | |
282 | case CACHE_UNIFIED: | |
283 | { | |
284 | switch ((eax >> 5) & 0x07) | |
285 | { | |
286 | case 1: | |
287 | cache = level1; | |
288 | break; | |
289 | case 2: | |
290 | cache = level2; | |
291 | break; | |
a0463099 AK |
292 | case 3: |
293 | cache = level3; | |
294 | break; | |
cb0dee88 UB |
295 | default: |
296 | cache = NULL; | |
297 | } | |
298 | ||
299 | if (cache) | |
300 | { | |
301 | unsigned sets = ecx + 1; | |
dc8bd8d9 | 302 | unsigned part = ((ebx >> 12) & 0x03ff) + 1; |
cb0dee88 | 303 | |
dc8bd8d9 | 304 | cache->assoc = ((ebx >> 22) & 0x03ff) + 1; |
cb0dee88 | 305 | cache->line = (ebx & 0x0fff) + 1; |
cb0dee88 UB |
306 | |
307 | cache->sizekb = (cache->assoc * part | |
308 | * cache->line * sets) / 1024; | |
a0463099 | 309 | } |
cb0dee88 | 310 | } |
2711355f ZD |
311 | default: |
312 | break; | |
313 | } | |
314 | } | |
315 | } | |
316 | ||
cb0dee88 | 317 | /* Returns the description of caches for an Intel processor. */ |
2711355f | 318 | |
d3bfe4de | 319 | static const char * |
a0463099 AK |
320 | detect_caches_intel (bool xeon_mp, unsigned max_level, |
321 | unsigned max_ext_level, unsigned *l2sizekb) | |
2711355f | 322 | { |
a0463099 | 323 | struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0}; |
2711355f | 324 | |
cb0dee88 | 325 | if (max_level >= 4) |
a0463099 | 326 | detect_caches_cpuid4 (&level1, &level2, &level3); |
cb0dee88 UB |
327 | else if (max_level >= 2) |
328 | detect_caches_cpuid2 (xeon_mp, &level1, &level2); | |
329 | else | |
d3bfe4de | 330 | return ""; |
2711355f | 331 | |
cb0dee88 | 332 | if (level1.sizekb == 0) |
d3bfe4de | 333 | return ""; |
2711355f | 334 | |
a0463099 AK |
335 | /* Let the L3 replace the L2. This assumes inclusive caches |
336 | and single threaded program for now. */ | |
337 | if (level3.sizekb) | |
338 | level2 = level3; | |
339 | ||
cb0dee88 UB |
340 | /* Intel CPUs are equipped with AMD style L2 cache info. Try this |
341 | method if other methods fail to provide L2 cache parameters. */ | |
342 | if (level2.sizekb == 0 && max_ext_level >= 0x80000006) | |
343 | detect_l2_cache (&level2); | |
f4a1dd0d | 344 | |
a0463099 AK |
345 | *l2sizekb = level2.sizekb; |
346 | ||
cb0dee88 | 347 | return describe_cache (level1, level2); |
2711355f ZD |
348 | } |
349 | ||
fa959ce4 MM |
350 | /* This will be called by the spec parser in gcc.c when it sees |
351 | a %:local_cpu_detect(args) construct. Currently it will be called | |
352 | with either "arch" or "tune" as argument depending on if -march=native | |
353 | or -mtune=native is to be substituted. | |
354 | ||
355 | It returns a string containing new command line parameters to be | |
356 | put at the place of the above two options, depending on what CPU | |
357 | this is executed. E.g. "-march=k8" on an AMD64 machine | |
358 | for -march=native. | |
359 | ||
360 | ARGC and ARGV are set depending on the actual arguments given | |
361 | in the spec. */ | |
b3172cab | 362 | |
fa959ce4 MM |
363 | const char *host_detect_local_cpu (int argc, const char **argv) |
364 | { | |
b3172cab UB |
365 | enum processor_type processor = PROCESSOR_I386; |
366 | const char *cpu = "i386"; | |
367 | ||
2711355f | 368 | const char *cache = ""; |
5be6cb59 | 369 | const char *options = ""; |
b3172cab | 370 | |
cb0dee88 | 371 | unsigned int eax, ebx, ecx, edx; |
b3172cab UB |
372 | |
373 | unsigned int max_level, ext_level; | |
cb0dee88 | 374 | |
fa959ce4 | 375 | unsigned int vendor; |
cb0dee88 | 376 | unsigned int model, family; |
b3172cab UB |
377 | |
378 | unsigned int has_sse3, has_ssse3, has_cmpxchg16b; | |
379 | unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2; | |
380 | ||
381 | /* Extended features */ | |
382 | unsigned int has_lahf_lm = 0, has_sse4a = 0; | |
383 | unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0; | |
634fa334 | 384 | unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0; |
7afac110 | 385 | unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0; |
8ad9d49e | 386 | unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; |
5eed4f27 | 387 | unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0; |
82feeb8d | 388 | unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0; |
76a02e42 | 389 | unsigned int has_hle = 0, has_rtm = 0; |
d1925759 | 390 | unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; |
d05e383b | 391 | unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; |
3a0d99bb | 392 | unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0; |
3f97cb0b AI |
393 | unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0; |
394 | unsigned int has_avx512f = 0; | |
b3172cab | 395 | |
edccdcb1 L |
396 | bool arch; |
397 | ||
a0463099 AK |
398 | unsigned int l2sizekb = 0; |
399 | ||
edccdcb1 L |
400 | if (argc < 1) |
401 | return NULL; | |
402 | ||
b3172cab UB |
403 | arch = !strcmp (argv[0], "arch"); |
404 | ||
edccdcb1 | 405 | if (!arch && strcmp (argv[0], "tune")) |
fa959ce4 MM |
406 | return NULL; |
407 | ||
b3172cab UB |
408 | max_level = __get_cpuid_max (0, &vendor); |
409 | if (max_level < 1) | |
fa959ce4 | 410 | goto done; |
fa959ce4 | 411 | |
b3172cab | 412 | __cpuid (1, eax, ebx, ecx, edx); |
fa959ce4 | 413 | |
cb0dee88 | 414 | model = (eax >> 4) & 0x0f; |
b3172cab | 415 | family = (eax >> 8) & 0x0f; |
ef64d158 | 416 | if (vendor == signature_INTEL_ebx) |
37c50435 L |
417 | { |
418 | unsigned int extended_model, extended_family; | |
419 | ||
420 | extended_model = (eax >> 12) & 0xf0; | |
421 | extended_family = (eax >> 20) & 0xff; | |
422 | if (family == 0x0f) | |
423 | { | |
424 | family += extended_family; | |
425 | model += extended_model; | |
426 | } | |
427 | else if (family == 0x06) | |
428 | model += extended_model; | |
429 | } | |
b3172cab UB |
430 | |
431 | has_sse3 = ecx & bit_SSE3; | |
432 | has_ssse3 = ecx & bit_SSSE3; | |
634fa334 L |
433 | has_sse4_1 = ecx & bit_SSE4_1; |
434 | has_sse4_2 = ecx & bit_SSE4_2; | |
435 | has_avx = ecx & bit_AVX; | |
a91529c4 | 436 | has_osxsave = ecx & bit_OSXSAVE; |
b3172cab | 437 | has_cmpxchg16b = ecx & bit_CMPXCHG16B; |
cabf85c3 | 438 | has_movbe = ecx & bit_MOVBE; |
634fa334 L |
439 | has_popcnt = ecx & bit_POPCNT; |
440 | has_aes = ecx & bit_AES; | |
441 | has_pclmul = ecx & bit_PCLMUL; | |
5eed4f27 | 442 | has_fma = ecx & bit_FMA; |
d1925759 L |
443 | has_f16c = ecx & bit_F16C; |
444 | has_rdrnd = ecx & bit_RDRND; | |
3a0d99bb | 445 | has_xsave = ecx & bit_XSAVE; |
fa959ce4 | 446 | |
b3172cab UB |
447 | has_cmpxchg8b = edx & bit_CMPXCHG8B; |
448 | has_cmov = edx & bit_CMOV; | |
449 | has_mmx = edx & bit_MMX; | |
3a0d99bb | 450 | has_fxsr = edx & bit_FXSAVE; |
b3172cab UB |
451 | has_sse = edx & bit_SSE; |
452 | has_sse2 = edx & bit_SSE2; | |
453 | ||
2c9b39ef L |
454 | if (max_level >= 7) |
455 | { | |
456 | __cpuid_count (7, 0, eax, ebx, ecx, edx); | |
457 | ||
458 | has_bmi = ebx & bit_BMI; | |
5dcfdccd | 459 | has_hle = ebx & bit_HLE; |
76a02e42 | 460 | has_rtm = ebx & bit_RTM; |
2c9b39ef L |
461 | has_avx2 = ebx & bit_AVX2; |
462 | has_bmi2 = ebx & bit_BMI2; | |
d1925759 | 463 | has_fsgsbase = ebx & bit_FSGSBASE; |
4c340b5d | 464 | has_rdseed = ebx & bit_RDSEED; |
d05e383b | 465 | has_adx = ebx & bit_ADX; |
3f97cb0b AI |
466 | has_avx512f = ebx & bit_AVX512F; |
467 | has_avx512er = ebx & bit_AVX512ER; | |
468 | has_avx512pf = ebx & bit_AVX512PF; | |
469 | has_avx512cd = ebx & bit_AVX512CD; | |
2c9b39ef L |
470 | } |
471 | ||
3a0d99bb AI |
472 | if (max_level >= 13) |
473 | { | |
474 | __cpuid_count (13, 1, eax, ebx, ecx, edx); | |
475 | ||
476 | has_xsaveopt = eax & bit_XSAVEOPT; | |
477 | } | |
478 | ||
a91529c4 L |
479 | /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ |
480 | #define XCR_XFEATURE_ENABLED_MASK 0x0 | |
481 | #define XSTATE_FP 0x1 | |
482 | #define XSTATE_SSE 0x2 | |
483 | #define XSTATE_YMM 0x4 | |
484 | if (has_osxsave) | |
485 | asm (".byte 0x0f; .byte 0x01; .byte 0xd0" | |
486 | : "=a" (eax), "=d" (edx) | |
487 | : "c" (XCR_XFEATURE_ENABLED_MASK)); | |
488 | ||
489 | /* Check if SSE and YMM states are supported. */ | |
953ac966 AN |
490 | if (!has_osxsave |
491 | || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) | |
a91529c4 L |
492 | { |
493 | has_avx = 0; | |
494 | has_avx2 = 0; | |
495 | has_fma = 0; | |
496 | has_fma4 = 0; | |
497 | has_xop = 0; | |
3a0d99bb AI |
498 | has_xsave = 0; |
499 | has_xsaveopt = 0; | |
a91529c4 L |
500 | } |
501 | ||
b3172cab UB |
502 | /* Check cpuid level of extended features. */ |
503 | __cpuid (0x80000000, ext_level, ebx, ecx, edx); | |
504 | ||
505 | if (ext_level > 0x80000000) | |
fa959ce4 | 506 | { |
b3172cab | 507 | __cpuid (0x80000001, eax, ebx, ecx, edx); |
fa959ce4 | 508 | |
b3172cab UB |
509 | has_lahf_lm = ecx & bit_LAHF_LM; |
510 | has_sse4a = ecx & bit_SSE4a; | |
c3d34a78 | 511 | has_abm = ecx & bit_ABM; |
8ad9d49e | 512 | has_lwp = ecx & bit_LWP; |
1133125e HJ |
513 | has_fma4 = ecx & bit_FMA4; |
514 | has_xop = ecx & bit_XOP; | |
94d13ad1 | 515 | has_tbm = ecx & bit_TBM; |
5fcafa60 | 516 | has_lzcnt = ecx & bit_LZCNT; |
9006f7f3 | 517 | has_prfchw = ecx & bit_PRFCHW; |
b3172cab UB |
518 | |
519 | has_longmode = edx & bit_LM; | |
520 | has_3dnowp = edx & bit_3DNOWP; | |
521 | has_3dnow = edx & bit_3DNOW; | |
522 | } | |
fa959ce4 | 523 | |
2711355f ZD |
524 | if (!arch) |
525 | { | |
19db293a | 526 | if (vendor == signature_AMD_ebx |
af0e415b UB |
527 | || vendor == signature_CENTAUR_ebx |
528 | || vendor == signature_CYRIX_ebx | |
7b9d1bd8 | 529 | || vendor == signature_NSC_ebx) |
2711355f | 530 | cache = detect_caches_amd (ext_level); |
ef64d158 | 531 | else if (vendor == signature_INTEL_ebx) |
cb0dee88 UB |
532 | { |
533 | bool xeon_mp = (family == 15 && model == 6); | |
a0463099 AK |
534 | cache = detect_caches_intel (xeon_mp, max_level, |
535 | ext_level, &l2sizekb); | |
cb0dee88 | 536 | } |
2711355f ZD |
537 | } |
538 | ||
ef64d158 | 539 | if (vendor == signature_AMD_ebx) |
fa959ce4 | 540 | { |
fbdf817d | 541 | unsigned int name; |
b3172cab | 542 | |
fbdf817d UB |
543 | /* Detect geode processor by its processor signature. */ |
544 | if (ext_level > 0x80000001) | |
545 | __cpuid (0x80000002, name, ebx, ecx, edx); | |
546 | else | |
547 | name = 0; | |
548 | ||
ef64d158 | 549 | if (name == signature_NSC_ebx) |
fbdf817d | 550 | processor = PROCESSOR_GEODE; |
e32bfc16 VK |
551 | else if (has_movbe) |
552 | processor = PROCESSOR_BTVER2; | |
ed97ad47 GG |
553 | else if (has_avx2) |
554 | processor = PROCESSOR_BDVER4; | |
eb2f2b44 GG |
555 | else if (has_xsaveopt) |
556 | processor = PROCESSOR_BDVER3; | |
4d652a18 HJ |
557 | else if (has_bmi) |
558 | processor = PROCESSOR_BDVER2; | |
1133125e HJ |
559 | else if (has_xop) |
560 | processor = PROCESSOR_BDVER1; | |
14b52538 CF |
561 | else if (has_sse4a && has_ssse3) |
562 | processor = PROCESSOR_BTVER1; | |
fbdf817d | 563 | else if (has_sse4a) |
35a63f21 | 564 | processor = PROCESSOR_AMDFAM10; |
fbdf817d UB |
565 | else if (has_sse2 || has_longmode) |
566 | processor = PROCESSOR_K8; | |
f7593cb4 | 567 | else if (has_3dnowp && family == 6) |
fbdf817d UB |
568 | processor = PROCESSOR_ATHLON; |
569 | else if (has_mmx) | |
570 | processor = PROCESSOR_K6; | |
571 | else | |
572 | processor = PROCESSOR_PENTIUM; | |
fa959ce4 | 573 | } |
19db293a UB |
574 | else if (vendor == signature_CENTAUR_ebx) |
575 | { | |
576 | if (arch) | |
577 | { | |
af0e415b | 578 | switch (family) |
19db293a | 579 | { |
af0e415b | 580 | case 6: |
19db293a UB |
581 | if (model > 9) |
582 | /* Use the default detection procedure. */ | |
9d532162 | 583 | processor = PROCESSOR_GENERIC; |
19db293a UB |
584 | else if (model == 9) |
585 | cpu = "c3-2"; | |
586 | else if (model >= 6) | |
587 | cpu = "c3"; | |
588 | else | |
9d532162 | 589 | processor = PROCESSOR_GENERIC; |
af0e415b UB |
590 | break; |
591 | case 5: | |
592 | if (has_3dnow) | |
593 | cpu = "winchip2"; | |
594 | else if (has_mmx) | |
595 | cpu = "winchip2-c6"; | |
596 | else | |
9d532162 | 597 | processor = PROCESSOR_GENERIC; |
af0e415b UB |
598 | break; |
599 | default: | |
600 | /* We have no idea. */ | |
9d532162 | 601 | processor = PROCESSOR_GENERIC; |
19db293a | 602 | } |
19db293a UB |
603 | } |
604 | } | |
fa959ce4 MM |
605 | else |
606 | { | |
edccdcb1 L |
607 | switch (family) |
608 | { | |
b3172cab UB |
609 | case 4: |
610 | processor = PROCESSOR_I486; | |
611 | break; | |
edccdcb1 | 612 | case 5: |
b3172cab | 613 | processor = PROCESSOR_PENTIUM; |
edccdcb1 L |
614 | break; |
615 | case 6: | |
616 | processor = PROCESSOR_PENTIUMPRO; | |
617 | break; | |
618 | case 15: | |
619 | processor = PROCESSOR_PENTIUM4; | |
620 | break; | |
621 | default: | |
b3172cab | 622 | /* We have no idea. */ |
9d532162 | 623 | processor = PROCESSOR_GENERIC; |
edccdcb1 L |
624 | } |
625 | } | |
626 | ||
627 | switch (processor) | |
628 | { | |
629 | case PROCESSOR_I386: | |
b3172cab | 630 | /* Default. */ |
edccdcb1 L |
631 | break; |
632 | case PROCESSOR_I486: | |
633 | cpu = "i486"; | |
634 | break; | |
635 | case PROCESSOR_PENTIUM: | |
b3172cab | 636 | if (arch && has_mmx) |
edccdcb1 L |
637 | cpu = "pentium-mmx"; |
638 | else | |
639 | cpu = "pentium"; | |
640 | break; | |
641 | case PROCESSOR_PENTIUMPRO: | |
44f276c6 | 642 | switch (model) |
edccdcb1 | 643 | { |
44f276c6 L |
644 | case 0x1c: |
645 | case 0x26: | |
d3c11974 L |
646 | /* Bonnell. */ |
647 | cpu = "bonnell"; | |
44f276c6 | 648 | break; |
e5287671 YR |
649 | case 0x37: |
650 | case 0x4d: | |
651 | /* Silvermont. */ | |
d3c11974 | 652 | cpu = "silvermont"; |
e5287671 | 653 | break; |
992592ec CW |
654 | case 0x0f: |
655 | /* Merom. */ | |
656 | case 0x17: | |
657 | case 0x1d: | |
658 | /* Penryn. */ | |
659 | cpu = "core2"; | |
660 | break; | |
44f276c6 L |
661 | case 0x1a: |
662 | case 0x1e: | |
663 | case 0x1f: | |
664 | case 0x2e: | |
eefe143b | 665 | /* Nehalem. */ |
d3c11974 L |
666 | cpu = "nehalem"; |
667 | break; | |
44f276c6 | 668 | case 0x25: |
12bbb78f | 669 | case 0x2c: |
44f276c6 | 670 | case 0x2f: |
eefe143b | 671 | /* Westmere. */ |
d3c11974 | 672 | cpu = "westmere"; |
44f276c6 | 673 | break; |
35758e5b | 674 | case 0x2a: |
815cecbe | 675 | case 0x2d: |
35758e5b | 676 | /* Sandy Bridge. */ |
d3c11974 | 677 | cpu = "sandybridge"; |
35758e5b | 678 | break; |
992592ec CW |
679 | case 0x3a: |
680 | case 0x3e: | |
681 | /* Ivy Bridge. */ | |
d3c11974 | 682 | cpu = "ivybridge"; |
44f276c6 | 683 | break; |
992592ec | 684 | case 0x3c: |
d0cf4e84 L |
685 | case 0x45: |
686 | case 0x46: | |
992592ec | 687 | /* Haswell. */ |
d3c11974 | 688 | cpu = "haswell"; |
44f276c6 L |
689 | break; |
690 | default: | |
691 | if (arch) | |
692 | { | |
4ffae7ff | 693 | /* This is unknown family 0x6 CPU. */ |
19ac6899 TI |
694 | if (has_adx) |
695 | cpu = "broadwell"; | |
696 | else if (has_avx2) | |
992592ec | 697 | /* Assume Haswell. */ |
d3c11974 | 698 | cpu = "haswell"; |
992592ec | 699 | else if (has_avx) |
4ffae7ff | 700 | /* Assume Sandy Bridge. */ |
d3c11974 | 701 | cpu = "sandybridge"; |
4ffae7ff | 702 | else if (has_sse4_2) |
0b871ccf YR |
703 | { |
704 | if (has_movbe) | |
d3c11974 L |
705 | /* Assume Silvermont. */ |
706 | cpu = "silvermont"; | |
0b871ccf | 707 | else |
d3c11974 L |
708 | /* Assume Nehalem. */ |
709 | cpu = "nehalem"; | |
0b871ccf | 710 | } |
4ffae7ff L |
711 | else if (has_ssse3) |
712 | { | |
713 | if (has_movbe) | |
d3c11974 L |
714 | /* Assume Bonnell. */ |
715 | cpu = "bonnell"; | |
4ffae7ff L |
716 | else |
717 | /* Assume Core 2. */ | |
718 | cpu = "core2"; | |
719 | } | |
44f276c6 L |
720 | else if (has_sse3) |
721 | /* It is Core Duo. */ | |
722 | cpu = "pentium-m"; | |
723 | else if (has_sse2) | |
724 | /* It is Pentium M. */ | |
725 | cpu = "pentium-m"; | |
726 | else if (has_sse) | |
727 | /* It is Pentium III. */ | |
728 | cpu = "pentium3"; | |
729 | else if (has_mmx) | |
730 | /* It is Pentium II. */ | |
731 | cpu = "pentium2"; | |
732 | else | |
733 | /* Default to Pentium Pro. */ | |
734 | cpu = "pentiumpro"; | |
735 | } | |
b3172cab | 736 | else |
44f276c6 L |
737 | /* For -mtune, we default to -mtune=generic. */ |
738 | cpu = "generic"; | |
739 | break; | |
fa959ce4 | 740 | } |
b3172cab UB |
741 | break; |
742 | case PROCESSOR_PENTIUM4: | |
743 | if (has_sse3) | |
fa959ce4 | 744 | { |
b3172cab UB |
745 | if (has_longmode) |
746 | cpu = "nocona"; | |
fa959ce4 | 747 | else |
b3172cab | 748 | cpu = "prescott"; |
fa959ce4 | 749 | } |
b3172cab UB |
750 | else |
751 | cpu = "pentium4"; | |
edccdcb1 L |
752 | break; |
753 | case PROCESSOR_GEODE: | |
754 | cpu = "geode"; | |
755 | break; | |
756 | case PROCESSOR_K6: | |
b3172cab UB |
757 | if (arch && has_3dnow) |
758 | cpu = "k6-3"; | |
edccdcb1 L |
759 | else |
760 | cpu = "k6"; | |
761 | break; | |
762 | case PROCESSOR_ATHLON: | |
b3172cab | 763 | if (arch && has_sse) |
edccdcb1 L |
764 | cpu = "athlon-4"; |
765 | else | |
766 | cpu = "athlon"; | |
767 | break; | |
edccdcb1 | 768 | case PROCESSOR_K8: |
b3172cab UB |
769 | if (arch && has_sse3) |
770 | cpu = "k8-sse3"; | |
771 | else | |
772 | cpu = "k8"; | |
edccdcb1 | 773 | break; |
35a63f21 DR |
774 | case PROCESSOR_AMDFAM10: |
775 | cpu = "amdfam10"; | |
776 | break; | |
1133125e HJ |
777 | case PROCESSOR_BDVER1: |
778 | cpu = "bdver1"; | |
779 | break; | |
4d652a18 HJ |
780 | case PROCESSOR_BDVER2: |
781 | cpu = "bdver2"; | |
782 | break; | |
eb2f2b44 GG |
783 | case PROCESSOR_BDVER3: |
784 | cpu = "bdver3"; | |
785 | break; | |
ed97ad47 GG |
786 | case PROCESSOR_BDVER4: |
787 | cpu = "bdver4"; | |
788 | break; | |
14b52538 CF |
789 | case PROCESSOR_BTVER1: |
790 | cpu = "btver1"; | |
791 | break; | |
e32bfc16 VK |
792 | case PROCESSOR_BTVER2: |
793 | cpu = "btver2"; | |
794 | break; | |
b3172cab | 795 | |
edccdcb1 | 796 | default: |
b3172cab UB |
797 | /* Use something reasonable. */ |
798 | if (arch) | |
799 | { | |
800 | if (has_ssse3) | |
801 | cpu = "core2"; | |
802 | else if (has_sse3) | |
803 | { | |
804 | if (has_longmode) | |
805 | cpu = "nocona"; | |
806 | else | |
807 | cpu = "prescott"; | |
808 | } | |
809 | else if (has_sse2) | |
810 | cpu = "pentium4"; | |
811 | else if (has_cmov) | |
812 | cpu = "pentiumpro"; | |
813 | else if (has_mmx) | |
814 | cpu = "pentium-mmx"; | |
815 | else if (has_cmpxchg8b) | |
816 | cpu = "pentium"; | |
817 | } | |
818 | else | |
819 | cpu = "generic"; | |
fa959ce4 MM |
820 | } |
821 | ||
5be6cb59 UB |
822 | if (arch) |
823 | { | |
11c2aa39 UB |
824 | const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx"; |
825 | const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow"; | |
826 | const char *sse = has_sse ? " -msse" : " -mno-sse"; | |
827 | const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2"; | |
828 | const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3"; | |
829 | const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3"; | |
830 | const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a"; | |
5eed4f27 L |
831 | const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16"; |
832 | const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf"; | |
833 | const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe"; | |
11c2aa39 | 834 | const char *aes = has_aes ? " -maes" : " -mno-aes"; |
5eed4f27 L |
835 | const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul"; |
836 | const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt"; | |
837 | const char *abm = has_abm ? " -mabm" : " -mno-abm"; | |
838 | const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp"; | |
839 | const char *fma = has_fma ? " -mfma" : " -mno-fma"; | |
840 | const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4"; | |
841 | const char *xop = has_xop ? " -mxop" : " -mno-xop"; | |
842 | const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi"; | |
82feeb8d | 843 | const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2"; |
5eed4f27 L |
844 | const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm"; |
845 | const char *avx = has_avx ? " -mavx" : " -mno-avx"; | |
7afac110 | 846 | const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2"; |
642a011d | 847 | const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2"; |
5eed4f27 | 848 | const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1"; |
3ed2c643 | 849 | const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt"; |
38d7f26e | 850 | const char *hle = has_hle ? " -mhle" : " -mno-hle"; |
76a02e42 | 851 | const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm"; |
d1925759 L |
852 | const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd"; |
853 | const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c"; | |
854 | const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase"; | |
4c340b5d | 855 | const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed"; |
e61c94dd | 856 | const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw"; |
d05e383b | 857 | const char *adx = has_adx ? " -madx" : " -mno-adx"; |
3a0d99bb AI |
858 | const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr"; |
859 | const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave"; | |
860 | const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt"; | |
3f97cb0b AI |
861 | const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f"; |
862 | const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er"; | |
863 | const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd"; | |
864 | const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf"; | |
5eed4f27 | 865 | |
11c2aa39 UB |
866 | options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, |
867 | sse4a, cx16, sahf, movbe, aes, pclmul, | |
82feeb8d | 868 | popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, |
76a02e42 | 869 | tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm, |
3a0d99bb | 870 | hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, |
3f97cb0b AI |
871 | fxsr, xsave, xsaveopt, avx512f, avx512er, |
872 | avx512cd, avx512pf, NULL); | |
5be6cb59 UB |
873 | } |
874 | ||
fa959ce4 | 875 | done: |
f3afc8a7 | 876 | return concat (cache, "-m", argv[0], "=", cpu, options, NULL); |
fa959ce4 MM |
877 | } |
878 | #else | |
b3172cab | 879 | |
f3afc8a7 UB |
880 | /* If we aren't compiling with GCC then the driver will just ignore |
881 | -march and -mtune "native" target and will leave to the newly | |
882 | built compiler to generate code for its default target. */ | |
b3172cab | 883 | |
f3afc8a7 UB |
884 | const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED, |
885 | const char **argv ATTRIBUTE_UNUSED) | |
fa959ce4 | 886 | { |
f3afc8a7 | 887 | return NULL; |
fa959ce4 | 888 | } |
a6ecb05c | 889 | #endif /* __GNUC__ */ |