[thirdparty/gcc.git] / gcc / config / i386 / driver-i386.c

/* Subroutines for the gcc driver.
   Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3.  If not see
<http://www.gnu.org/licenses/>.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include <stdlib.h>

const char *host_detect_local_cpu (int argc, const char **argv);

#ifdef __GNUC__
#include "cpuid.h"

struct cache_desc
{
  unsigned sizekb;
  unsigned assoc;
  unsigned line;
};

/* Returns command line parameters that describe size and
   cache line size of the processor caches.  */

static char *
describe_cache (struct cache_desc level1, struct cache_desc level2)
{
  char size[100], line[100], size2[100];

  /* At the moment, gcc does not use the information
     about the associativity of the cache.  */

  snprintf (size, sizeof (size),
	    "--param l1-cache-size=%u ", level1.sizekb);
  snprintf (line, sizeof (line),
	    "--param l1-cache-line-size=%u ", level1.line);

  snprintf (size2, sizeof (size2),
	    "--param l2-cache-size=%u ", level2.sizekb);

  return concat (size, line, size2, NULL);
}

/* Detect L2 cache parameters using CPUID extended function 0x80000006.  */

static void
detect_l2_cache (struct cache_desc *level2)
{
  unsigned eax, ebx, ecx, edx;
  unsigned assoc;

  __cpuid (0x80000006, eax, ebx, ecx, edx);

  level2->sizekb = (ecx >> 16) & 0xffff;
  level2->line = ecx & 0xff;

  assoc = (ecx >> 12) & 0xf;
  if (assoc == 6)
    assoc = 8;
  else if (assoc == 8)
    assoc = 16;
  else if (assoc >= 0xa && assoc <= 0xc)
    assoc = 32 + (assoc - 0xa) * 16;
  else if (assoc >= 0xd && assoc <= 0xe)
    assoc = 96 + (assoc - 0xd) * 32;

  level2->assoc = assoc;
}

/* Returns the description of caches for an AMD processor.  */

static const char *
detect_caches_amd (unsigned max_ext_level)
{
  unsigned eax, ebx, ecx, edx;

  struct cache_desc level1, level2 = {0, 0, 0};

  if (max_ext_level < 0x80000005)
    return "";

  __cpuid (0x80000005, eax, ebx, ecx, edx);

  level1.sizekb = (ecx >> 24) & 0xff;
  level1.assoc = (ecx >> 16) & 0xff;
  level1.line = ecx & 0xff;

  if (max_ext_level >= 0x80000006)
    detect_l2_cache (&level2);

  return describe_cache (level1, level2);
}

/* Decodes the size, the associativity and the cache line size of
   L1/L2 caches of an Intel processor.  Values are based on
   "Intel Processor Identification and the CPUID Instruction"
   [Application Note 485], revision -032, December 2007.  */

static void
decode_caches_intel (unsigned reg, bool xeon_mp,
		     struct cache_desc *level1, struct cache_desc *level2)
{
  int i;

  for (i = 24; i >= 0; i -= 8)
    switch ((reg >> i) & 0xff)
      {
      case 0x0a:
	level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
	break;
      case 0x0c:
	level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
	break;
      case 0x2c:
	level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
	break;
      case 0x39:
	level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
	break;
      case 0x3a:
	level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
	break;
      case 0x3b:
	level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
	break;
      case 0x3c:
	level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
	break;
      case 0x3d:
	level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
	break;
      case 0x3e:
	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
	break;
      case 0x41:
	level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
	break;
      case 0x42:
	level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
	break;
      case 0x43:
	level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
	break;
      case 0x44:
	level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
	break;
      case 0x45:
	level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
	break;
      case 0x49:
	if (xeon_mp)
	  break;
	level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
	break;
      case 0x4e:
	level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
	break;
      case 0x60:
	level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
	break;
      case 0x66:
	level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
	break;
      case 0x67:
	level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
	break;
      case 0x68:
	level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
	break;
      case 0x78:
	level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
	break;
      case 0x79:
	level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
	break;
      case 0x7a:
	level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
	break;
      case 0x7b:
	level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
	break;
      case 0x7c:
	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
	break;
      case 0x7d:
	level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
	break;
      case 0x7f:
	level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
	break;
      case 0x82:
	level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
	break;
      case 0x83:
	level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
	break;
      case 0x84:
	level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
	break;
      case 0x85:
	level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
	break;
      case 0x86:
	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
	break;
      case 0x87:
	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;

      default:
	break;
      }
}

/* Detect cache parameters using CPUID function 2.  */

static void
detect_caches_cpuid2 (bool xeon_mp, 
		      struct cache_desc *level1, struct cache_desc *level2)
{
  unsigned regs[4];
  int nreps, i;

  __cpuid (2, regs[0], regs[1], regs[2], regs[3]);

  nreps = regs[0] & 0x0f;
  regs[0] &= ~0x0f;

  while (--nreps >= 0)
    {
      for (i = 0; i < 4; i++)
	if (regs[i] && !((regs[i] >> 31) & 1))
	  decode_caches_intel (regs[i], xeon_mp, level1, level2);

      if (nreps)
	__cpuid (2, regs[0], regs[1], regs[2], regs[3]);
    }
}

/* Detect cache parameters using CPUID function 4. This
   method doesn't require hardcoded tables.  */

enum cache_type
{
  CACHE_END = 0,
  CACHE_DATA = 1,
  CACHE_INST = 2,
  CACHE_UNIFIED = 3
};

static void
detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2)
{
  struct cache_desc *cache;

  unsigned eax, ebx, ecx, edx;
  int count;

  for (count = 0;; count++)
    { 
      __cpuid_count(4, count, eax, ebx, ecx, edx);
      switch (eax & 0x1f)
	{
	case CACHE_END:
	  return;
	case CACHE_DATA:
	case CACHE_UNIFIED:
	  {
	    switch ((eax >> 5) & 0x07)
	      {
	      case 1:
		cache = level1;
		break;
	      case 2:
		cache = level2;
		break;
	      default:
		cache = NULL;
	      }

	    if (cache)
	      {
		unsigned sets = ecx + 1;
		unsigned part = ((ebx >> 12) & 0x03ff) + 1;

		cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
		cache->line = (ebx & 0x0fff) + 1;

		cache->sizekb = (cache->assoc * part
				 * cache->line * sets) / 1024;
	      }	       
	  }
	default:
	  break;
	}
    }
}

/* Returns the description of caches for an Intel processor.  */

static const char *
detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level)
{
  struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0};

  if (max_level >= 4)
    detect_caches_cpuid4 (&level1, &level2);
  else if (max_level >= 2)
    detect_caches_cpuid2 (xeon_mp, &level1, &level2);
  else
    return "";

  if (level1.sizekb == 0)
    return "";

  /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
     method if other methods fail to provide L2 cache parameters.  */
  if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
    detect_l2_cache (&level2);

  return describe_cache (level1, level2);
}

enum vendor_signatures
{
  SIG_INTEL =	0x756e6547 /* Genu */,
  SIG_AMD =	0x68747541 /* Auth */
};

enum processor_signatures
{
  SIG_GEODE =	0x646f6547 /* Geod */
};

/* This will be called by the spec parser in gcc.c when it sees
   a %:local_cpu_detect(args) construct.  Currently it will be called
   with either "arch" or "tune" as argument depending on if -march=native
   or -mtune=native is to be substituted.

   It returns a string containing new command line parameters to be
   put at the place of the above two options, depending on what CPU
   this is executed.  E.g. "-march=k8" on an AMD64 machine
   for -march=native.

   ARGC and ARGV are set depending on the actual arguments given
   in the spec.  */

const char *host_detect_local_cpu (int argc, const char **argv)
{
  enum processor_type processor = PROCESSOR_I386;
  const char *cpu = "i386";

  const char *cache = "";
  const char *options = "";

  unsigned int eax, ebx, ecx, edx;

  unsigned int max_level, ext_level;

  unsigned int vendor;
  unsigned int model, family;

  unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
  unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;

  /* Extended features */
  unsigned int has_lahf_lm = 0, has_sse4a = 0;
  unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
  unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
  unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
  unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;

  bool arch;

  if (argc < 1)
    return NULL;

  arch = !strcmp (argv[0], "arch");

  if (!arch && strcmp (argv[0], "tune"))
    return NULL;

  max_level = __get_cpuid_max (0, &vendor);
  if (max_level < 1)
    goto done;

  __cpuid (1, eax, ebx, ecx, edx);

  model = (eax >> 4) & 0x0f;
  family = (eax >> 8) & 0x0f;
  if (vendor == SIG_INTEL)
    {
      unsigned int extended_model, extended_family;

      extended_model = (eax >> 12) & 0xf0;
      extended_family = (eax >> 20) & 0xff;
      if (family == 0x0f)
	{
	  family += extended_family;
	  model += extended_model;
	}
      else if (family == 0x06)
	model += extended_model;
    }

  has_sse3 = ecx & bit_SSE3;
  has_ssse3 = ecx & bit_SSSE3;
  has_sse4_1 = ecx & bit_SSE4_1;
  has_sse4_2 = ecx & bit_SSE4_2;
  has_avx = ecx & bit_AVX;
  has_cmpxchg16b = ecx & bit_CMPXCHG16B;
  has_movbe = ecx & bit_MOVBE;
  has_popcnt = ecx & bit_POPCNT;
  has_aes = ecx & bit_AES;
  has_pclmul = ecx & bit_PCLMUL;

  has_cmpxchg8b = edx & bit_CMPXCHG8B;
  has_cmov = edx & bit_CMOV;
  has_mmx = edx & bit_MMX;
  has_sse = edx & bit_SSE;
  has_sse2 = edx & bit_SSE2;

  /* Check cpuid level of extended features.  */
  __cpuid (0x80000000, ext_level, ebx, ecx, edx);

  if (ext_level > 0x80000000)
    {
      __cpuid (0x80000001, eax, ebx, ecx, edx);

      has_lahf_lm = ecx & bit_LAHF_LM;
      has_sse4a = ecx & bit_SSE4a;
      has_abm = ecx & bit_ABM;
      has_lwp = ecx & bit_LWP;

      has_longmode = edx & bit_LM;
      has_3dnowp = edx & bit_3DNOWP;
      has_3dnow = edx & bit_3DNOW;
    }

  if (!arch)
    {
      if (vendor == SIG_AMD)
	cache = detect_caches_amd (ext_level);
      else if (vendor == SIG_INTEL)
	{
	  bool xeon_mp = (family == 15 && model == 6);
	  cache = detect_caches_intel (xeon_mp, max_level, ext_level);
	}
    }

  if (vendor == SIG_AMD)
    {
      unsigned int name;

      /* Detect geode processor by its processor signature.  */
      if (ext_level > 0x80000001)
	__cpuid (0x80000002, name, ebx, ecx, edx);
      else
	name = 0;

      if (name == SIG_GEODE)
	processor = PROCESSOR_GEODE;
      else if (has_sse4a)
	processor = PROCESSOR_AMDFAM10;
      else if (has_sse2 || has_longmode)
	processor = PROCESSOR_K8;
      else if (has_3dnowp)
	processor = PROCESSOR_ATHLON;
      else if (has_mmx)
	processor = PROCESSOR_K6;
      else
	processor = PROCESSOR_PENTIUM;
    }
  else
    {
      switch (family)
	{
	case 4:
	  processor = PROCESSOR_I486;
	  break;
	case 5:
	  processor = PROCESSOR_PENTIUM;
	  break;
	case 6:
	  processor = PROCESSOR_PENTIUMPRO;
	  break;
	case 15:
	  processor = PROCESSOR_PENTIUM4;
	  break;
	default:
	  /* We have no idea.  */
	  processor = PROCESSOR_GENERIC32;
	}
    }

  switch (processor)
    {
    case PROCESSOR_I386:
      /* Default.  */
      break;
    case PROCESSOR_I486:
      cpu = "i486";
      break;
    case PROCESSOR_PENTIUM:
      if (arch && has_mmx)
	cpu = "pentium-mmx";
      else
	cpu = "pentium";
      break;
    case PROCESSOR_PENTIUMPRO:
      if (has_longmode)
	/* It is Core 2 or Atom.  */
	cpu = (model == 28) ? "atom" : "core2";
      else if (arch)
	{
	  if (has_sse3)
	    /* It is Core Duo.  */
	    cpu = "prescott";
	  else if (has_sse2)
	    /* It is Pentium M.  */
	    cpu = "pentium-m";
	  else if (has_sse)
	    /* It is Pentium III.  */
	    cpu = "pentium3";
	  else if (has_mmx)
	    /* It is Pentium II.  */
	    cpu = "pentium2";
	  else
	    /* Default to Pentium Pro.  */
	    cpu = "pentiumpro";
	}
      else
	/* For -mtune, we default to -mtune=generic.  */
	cpu = "generic";
      break;
    case PROCESSOR_PENTIUM4:
      if (has_sse3)
	{
	  if (has_longmode)
	    cpu = "nocona";
	  else
	    cpu = "prescott";
	}
      else
	cpu = "pentium4";
      break;
    case PROCESSOR_GEODE:
      cpu = "geode";
      break;
    case PROCESSOR_K6:
      if (arch && has_3dnow)
	cpu = "k6-3";
      else
	cpu = "k6";
      break;
    case PROCESSOR_ATHLON:
      if (arch && has_sse)
	cpu = "athlon-4";
      else
	cpu = "athlon";
      break;
    case PROCESSOR_K8:
      if (arch && has_sse3)
	cpu = "k8-sse3";
      else
	cpu = "k8";
      break;
    case PROCESSOR_AMDFAM10:
      cpu = "amdfam10";
      break;

    default:
      /* Use something reasonable.  */
      if (arch)
	{
	  if (has_ssse3)
	    cpu = "core2";
	  else if (has_sse3)
	    {
	      if (has_longmode)
		cpu = "nocona";
	      else
		cpu = "prescott";
	    }
	  else if (has_sse2)
	    cpu = "pentium4";
	  else if (has_cmov)
	    cpu = "pentiumpro";
	  else if (has_mmx)
	    cpu = "pentium-mmx";
	  else if (has_cmpxchg8b)
	    cpu = "pentium";
	}
      else
	cpu = "generic";
    }

  if (arch)
    {
      if (has_cmpxchg16b)
	options = concat (options, " -mcx16", NULL);
      if (has_lahf_lm)
	options = concat (options, " -msahf", NULL);
      if (has_movbe)
	options = concat (options, " -mmovbe", NULL);
      if (has_aes)
	options = concat (options, " -maes", NULL);
      if (has_pclmul)
	options = concat (options, " -mpclmul", NULL);
      if (has_popcnt)
	options = concat (options, " -mpopcnt", NULL);
      if (has_abm)
	options = concat (options, " -mabm", NULL);
      if (has_lwp)
	options = concat (options, " -mlwp", NULL);

      if (has_avx)
	options = concat (options, " -mavx", NULL);
      else if (has_sse4_2)
	options = concat (options, " -msse4.2", NULL);
      else if (has_sse4_1)
	options = concat (options, " -msse4.1", NULL);
    }

done:
  return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
}
#else

/* If we aren't compiling with GCC then the driver will just ignore
   -march and -mtune "native" target and will leave to the newly
   built compiler to generate code for its default target.  */

const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
				   const char **argv ATTRIBUTE_UNUSED)
{
  return NULL;
}
#endif /* __GNUC__ */
Commit	Line	Data
fa959ce4	1	/* Subroutines for the gcc driver.
cb0dee88	2	Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
fa959ce4 MM	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
2f83c7d6	8	the Free Software Foundation; either version 3, or (at your option)
fa959ce4 MM	9	any later version.
	10
	11	GCC is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	<http://www.gnu.org/licenses/>. */
fa959ce4 MM	19
	20	#include "config.h"
	21	#include "system.h"
edccdcb1 L	22	#include "coretypes.h"
edccdcb1 L	23	#include "tm.h"
fa959ce4 MM	24	#include <stdlib.h>
fa959ce4 MM	25
895016f6 UB	26	const char host_detect_local_cpu (int argc, const char *argv);
895016f6 UB	27
a6ecb05c	28	#ifdef __GNUC__
b3172cab	29	#include "cpuid.h"
fa959ce4	30
cb0dee88 UB	31	struct cache_desc
	32	{
	33	unsigned sizekb;
	34	unsigned assoc;
	35	unsigned line;
	36	};
	37
	38	/* Returns command line parameters that describe size and
	39	cache line size of the processor caches. */
2711355f ZD	40
2711355f ZD	41	static char *
cb0dee88	42	describe_cache (struct cache_desc level1, struct cache_desc level2)
2711355f	43	{
f4a1dd0d	44	char size[100], line[100], size2[100];
2711355f	45
cb0dee88 UB	46	/* At the moment, gcc does not use the information
	47	about the associativity of the cache. */
	48
f3afc8a7 UB	49	snprintf (size, sizeof (size),
	50	"--param l1-cache-size=%u ", level1.sizekb);
	51	snprintf (line, sizeof (line),
	52	"--param l1-cache-line-size=%u ", level1.line);
2711355f	53
f3afc8a7 UB	54	snprintf (size2, sizeof (size2),
f3afc8a7 UB	55	"--param l2-cache-size=%u ", level2.sizekb);
2711355f	56
f3afc8a7	57	return concat (size, line, size2, NULL);
f4a1dd0d ZM	58	}
f4a1dd0d ZM	59
cb0dee88 UB	60	/* Detect L2 cache parameters using CPUID extended function 0x80000006. */
cb0dee88 UB	61
f4a1dd0d	62	static void
cb0dee88	63	detect_l2_cache (struct cache_desc *level2)
f4a1dd0d	64	{
cb0dee88 UB	65	unsigned eax, ebx, ecx, edx;
cb0dee88 UB	66	unsigned assoc;
f4a1dd0d ZM	67
	68	__cpuid (0x80000006, eax, ebx, ecx, edx);
	69
cb0dee88 UB	70	level2->sizekb = (ecx >> 16) & 0xffff;
	71	level2->line = ecx & 0xff;
	72
f4a1dd0d ZM	73	assoc = (ecx >> 12) & 0xf;
	74	if (assoc == 6)
	75	assoc = 8;
	76	else if (assoc == 8)
	77	assoc = 16;
	78	else if (assoc >= 0xa && assoc <= 0xc)
	79	assoc = 32 + (assoc - 0xa) * 16;
	80	else if (assoc >= 0xd && assoc <= 0xe)
	81	assoc = 96 + (assoc - 0xd) * 32;
cb0dee88 UB	82
cb0dee88 UB	83	level2->assoc = assoc;
2711355f ZD	84	}
	85
	86	/* Returns the description of caches for an AMD processor. */
	87
d3bfe4de	88	static const char *
2711355f ZD	89	detect_caches_amd (unsigned max_ext_level)
	90	{
	91	unsigned eax, ebx, ecx, edx;
cb0dee88 UB	92
cb0dee88 UB	93	struct cache_desc level1, level2 = {0, 0, 0};
2711355f ZD	94
2711355f ZD	95	if (max_ext_level < 0x80000005)
d3bfe4de	96	return "";
2711355f	97
b3172cab	98	__cpuid (0x80000005, eax, ebx, ecx, edx);
2711355f	99
cb0dee88 UB	100	level1.sizekb = (ecx >> 24) & 0xff;
	101	level1.assoc = (ecx >> 16) & 0xff;
	102	level1.line = ecx & 0xff;
2711355f	103
f4a1dd0d	104	if (max_ext_level >= 0x80000006)
cb0dee88	105	detect_l2_cache (&level2);
f4a1dd0d	106
cb0dee88	107	return describe_cache (level1, level2);
2711355f ZD	108	}
2711355f ZD	109
cb0dee88 UB	110	/* Decodes the size, the associativity and the cache line size of
	111	L1/L2 caches of an Intel processor. Values are based on
	112	"Intel Processor Identification and the CPUID Instruction"
	113	[Application Note 485], revision -032, December 2007. */
2711355f ZD	114
2711355f ZD	115	static void
cb0dee88 UB	116	decode_caches_intel (unsigned reg, bool xeon_mp,
cb0dee88 UB	117	struct cache_desc level1, struct cache_desc level2)
2711355f	118	{
cb0dee88 UB	119	int i;
	120
	121	for (i = 24; i >= 0; i -= 8)
	122	switch ((reg >> i) & 0xff)
	123	{
	124	case 0x0a:
	125	level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
	126	break;
	127	case 0x0c:
	128	level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
	129	break;
	130	case 0x2c:
	131	level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
	132	break;
	133	case 0x39:
	134	level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
	135	break;
	136	case 0x3a:
	137	level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
	138	break;
	139	case 0x3b:
	140	level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
	141	break;
	142	case 0x3c:
	143	level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
	144	break;
	145	case 0x3d:
	146	level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
	147	break;
	148	case 0x3e:
	149	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
	150	break;
	151	case 0x41:
	152	level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
	153	break;
	154	case 0x42:
	155	level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
	156	break;
	157	case 0x43:
	158	level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
	159	break;
	160	case 0x44:
	161	level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
	162	break;
	163	case 0x45:
	164	level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
	165	break;
	166	case 0x49:
	167	if (xeon_mp)
	168	break;
	169	level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
	170	break;
	171	case 0x4e:
	172	level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
	173	break;
	174	case 0x60:
	175	level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
	176	break;
	177	case 0x66:
	178	level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
	179	break;
	180	case 0x67:
	181	level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
	182	break;
183	case 0x68:
184	level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
185	break;
186	case 0x78:
187	level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
188	break;
189	case 0x79:
190	level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
191	break;
192	case 0x7a:
193	level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
194	break;
195	case 0x7b:
196	level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
197	break;
198	case 0x7c:
199	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
200	break;
201	case 0x7d:
202	level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
203	break;
204	case 0x7f:
205	level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
206	break;
207	case 0x82:
208	level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
209	break;
210	case 0x83:
211	level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
212	break;
213	case 0x84:
214	level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
215	break;
216	case 0x85:
217	level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
218	break;
219	case 0x86:
220	level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
221	break;
222	case 0x87:
223	level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
224
225	default:
226	break;
227	}
228	}
2711355f	229
cb0dee88	230	/* Detect cache parameters using CPUID function 2. */
2711355f	231
cb0dee88 UB	232	static void
	233	detect_caches_cpuid2 (bool xeon_mp,
	234	struct cache_desc level1, struct cache_desc level2)
	235	{
dc8bd8d9 UB	236	unsigned regs[4];
dc8bd8d9 UB	237	int nreps, i;
cb0dee88	238
dc8bd8d9	239	__cpuid (2, regs[0], regs[1], regs[2], regs[3]);
cb0dee88	240
dc8bd8d9 UB	241	nreps = regs[0] & 0x0f;
dc8bd8d9 UB	242	regs[0] &= ~0x0f;
cb0dee88 UB	243
cb0dee88 UB	244	while (--nreps >= 0)
2711355f	245	{
dc8bd8d9 UB	246	for (i = 0; i < 4; i++)
	247	if (regs[i] && !((regs[i] >> 31) & 1))
	248	decode_caches_intel (regs[i], xeon_mp, level1, level2);
cb0dee88 UB	249
cb0dee88 UB	250	if (nreps)
dc8bd8d9	251	__cpuid (2, regs[0], regs[1], regs[2], regs[3]);
cb0dee88 UB	252	}
cb0dee88 UB	253	}
2711355f	254
cb0dee88 UB	255	/* Detect cache parameters using CPUID function 4. This
cb0dee88 UB	256	method doesn't require hardcoded tables. */
2711355f	257
cb0dee88 UB	258	enum cache_type
	259	{
	260	CACHE_END = 0,
	261	CACHE_DATA = 1,
	262	CACHE_INST = 2,
	263	CACHE_UNIFIED = 3
	264	};
	265
	266	static void
	267	detect_caches_cpuid4 (struct cache_desc level1, struct cache_desc level2)
	268	{
	269	struct cache_desc *cache;
	270
	271	unsigned eax, ebx, ecx, edx;
	272	int count;
	273
	274	for (count = 0;; count++)
	275	{
	276	__cpuid_count(4, count, eax, ebx, ecx, edx);
	277	switch (eax & 0x1f)
	278	{
	279	case CACHE_END:
	280	return;
	281	case CACHE_DATA:
	282	case CACHE_UNIFIED:
	283	{
	284	switch ((eax >> 5) & 0x07)
	285	{
	286	case 1:
	287	cache = level1;
	288	break;
	289	case 2:
	290	cache = level2;
	291	break;
	292	default:
	293	cache = NULL;
	294	}
	295
	296	if (cache)
	297	{
	298	unsigned sets = ecx + 1;
dc8bd8d9	299	unsigned part = ((ebx >> 12) & 0x03ff) + 1;
cb0dee88	300
dc8bd8d9	301	cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
cb0dee88	302	cache->line = (ebx & 0x0fff) + 1;
cb0dee88 UB	303
	304	cache->sizekb = (cache->assoc * part
	305	* cache->line * sets) / 1024;
	306	}
	307	}
2711355f ZD	308	default:
	309	break;
	310	}
	311	}
	312	}
	313
cb0dee88	314	/* Returns the description of caches for an Intel processor. */
2711355f	315
d3bfe4de	316	static const char *
cb0dee88	317	detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level)
2711355f	318	{
cb0dee88	319	struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0};
2711355f	320
cb0dee88 UB	321	if (max_level >= 4)
	322	detect_caches_cpuid4 (&level1, &level2);
	323	else if (max_level >= 2)
	324	detect_caches_cpuid2 (xeon_mp, &level1, &level2);
	325	else
d3bfe4de	326	return "";
2711355f	327
cb0dee88	328	if (level1.sizekb == 0)
d3bfe4de	329	return "";
2711355f	330
cb0dee88 UB	331	/* Intel CPUs are equipped with AMD style L2 cache info. Try this
	332	method if other methods fail to provide L2 cache parameters. */
	333	if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
	334	detect_l2_cache (&level2);
f4a1dd0d	335
cb0dee88	336	return describe_cache (level1, level2);
2711355f ZD	337	}
2711355f ZD	338
4d947823 UB	339	enum vendor_signatures
	340	{
	341	SIG_INTEL = 0x756e6547 /* Genu */,
fbdf817d UB	342	SIG_AMD = 0x68747541 /* Auth */
	343	};
	344
	345	enum processor_signatures
	346	{
4d947823 UB	347	SIG_GEODE = 0x646f6547 /* Geod */
	348	};
	349
fa959ce4 MM	350	/* This will be called by the spec parser in gcc.c when it sees
	351	a %:local_cpu_detect(args) construct. Currently it will be called
	352	with either "arch" or "tune" as argument depending on if -march=native
	353	or -mtune=native is to be substituted.
	354
	355	It returns a string containing new command line parameters to be
	356	put at the place of the above two options, depending on what CPU
	357	this is executed. E.g. "-march=k8" on an AMD64 machine
	358	for -march=native.
	359
	360	ARGC and ARGV are set depending on the actual arguments given
	361	in the spec. */
b3172cab	362
fa959ce4 MM	363	const char host_detect_local_cpu (int argc, const char *argv)
fa959ce4 MM	364	{
b3172cab UB	365	enum processor_type processor = PROCESSOR_I386;
	366	const char *cpu = "i386";
	367
2711355f	368	const char *cache = "";
5be6cb59	369	const char *options = "";
b3172cab	370
cb0dee88	371	unsigned int eax, ebx, ecx, edx;
b3172cab UB	372
b3172cab UB	373	unsigned int max_level, ext_level;
cb0dee88	374
fa959ce4	375	unsigned int vendor;
cb0dee88	376	unsigned int model, family;
b3172cab UB	377
	378	unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
	379	unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
	380
	381	/* Extended features */
	382	unsigned int has_lahf_lm = 0, has_sse4a = 0;
	383	unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
634fa334 L	384	unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
634fa334 L	385	unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
8ad9d49e	386	unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
b3172cab	387
edccdcb1 L	388	bool arch;
	389
	390	if (argc < 1)
	391	return NULL;
	392
b3172cab UB	393	arch = !strcmp (argv[0], "arch");
b3172cab UB	394
edccdcb1	395	if (!arch && strcmp (argv[0], "tune"))
fa959ce4 MM	396	return NULL;
fa959ce4 MM	397
b3172cab UB	398	max_level = __get_cpuid_max (0, &vendor);
b3172cab UB	399	if (max_level < 1)
fa959ce4	400	goto done;
fa959ce4	401
b3172cab	402	__cpuid (1, eax, ebx, ecx, edx);
fa959ce4	403
cb0dee88	404	model = (eax >> 4) & 0x0f;
b3172cab	405	family = (eax >> 8) & 0x0f;
37c50435 L	406	if (vendor == SIG_INTEL)
	407	{
	408	unsigned int extended_model, extended_family;
	409
	410	extended_model = (eax >> 12) & 0xf0;
	411	extended_family = (eax >> 20) & 0xff;
	412	if (family == 0x0f)
	413	{
	414	family += extended_family;
	415	model += extended_model;
	416	}
	417	else if (family == 0x06)
	418	model += extended_model;
	419	}
b3172cab UB	420
	421	has_sse3 = ecx & bit_SSE3;
	422	has_ssse3 = ecx & bit_SSSE3;
634fa334 L	423	has_sse4_1 = ecx & bit_SSE4_1;
	424	has_sse4_2 = ecx & bit_SSE4_2;
	425	has_avx = ecx & bit_AVX;
b3172cab	426	has_cmpxchg16b = ecx & bit_CMPXCHG16B;
cabf85c3	427	has_movbe = ecx & bit_MOVBE;
634fa334 L	428	has_popcnt = ecx & bit_POPCNT;
	429	has_aes = ecx & bit_AES;
	430	has_pclmul = ecx & bit_PCLMUL;
fa959ce4	431
b3172cab UB	432	has_cmpxchg8b = edx & bit_CMPXCHG8B;
	433	has_cmov = edx & bit_CMOV;
	434	has_mmx = edx & bit_MMX;
	435	has_sse = edx & bit_SSE;
	436	has_sse2 = edx & bit_SSE2;
	437
	438	/* Check cpuid level of extended features. */
	439	__cpuid (0x80000000, ext_level, ebx, ecx, edx);
	440
	441	if (ext_level > 0x80000000)
fa959ce4	442	{
b3172cab	443	__cpuid (0x80000001, eax, ebx, ecx, edx);
fa959ce4	444
b3172cab UB	445	has_lahf_lm = ecx & bit_LAHF_LM;
b3172cab UB	446	has_sse4a = ecx & bit_SSE4a;
c3d34a78	447	has_abm = ecx & bit_ABM;
8ad9d49e	448	has_lwp = ecx & bit_LWP;
b3172cab UB	449
	450	has_longmode = edx & bit_LM;
	451	has_3dnowp = edx & bit_3DNOWP;
	452	has_3dnow = edx & bit_3DNOW;
	453	}
fa959ce4	454
2711355f ZD	455	if (!arch)
2711355f ZD	456	{
4d947823	457	if (vendor == SIG_AMD)
2711355f	458	cache = detect_caches_amd (ext_level);
4d947823	459	else if (vendor == SIG_INTEL)
cb0dee88 UB	460	{
	461	bool xeon_mp = (family == 15 && model == 6);
	462	cache = detect_caches_intel (xeon_mp, max_level, ext_level);
	463	}
2711355f ZD	464	}
2711355f ZD	465
4d947823	466	if (vendor == SIG_AMD)
fa959ce4	467	{
fbdf817d	468	unsigned int name;
b3172cab	469
fbdf817d UB	470	/* Detect geode processor by its processor signature. */
	471	if (ext_level > 0x80000001)
	472	__cpuid (0x80000002, name, ebx, ecx, edx);
	473	else
	474	name = 0;
	475
	476	if (name == SIG_GEODE)
	477	processor = PROCESSOR_GEODE;
	478	else if (has_sse4a)
35a63f21	479	processor = PROCESSOR_AMDFAM10;
fbdf817d UB	480	else if (has_sse2 \|\| has_longmode)
	481	processor = PROCESSOR_K8;
	482	else if (has_3dnowp)
	483	processor = PROCESSOR_ATHLON;
	484	else if (has_mmx)
	485	processor = PROCESSOR_K6;
	486	else
	487	processor = PROCESSOR_PENTIUM;
fa959ce4 MM	488	}
	489	else
	490	{
edccdcb1 L	491	switch (family)
edccdcb1 L	492	{
b3172cab UB	493	case 4:
	494	processor = PROCESSOR_I486;
	495	break;
edccdcb1	496	case 5:
b3172cab	497	processor = PROCESSOR_PENTIUM;
edccdcb1 L	498	break;
	499	case 6:
	500	processor = PROCESSOR_PENTIUMPRO;
	501	break;
	502	case 15:
	503	processor = PROCESSOR_PENTIUM4;
	504	break;
	505	default:
b3172cab UB	506	/* We have no idea. */
b3172cab UB	507	processor = PROCESSOR_GENERIC32;
edccdcb1 L	508	}
	509	}
	510
	511	switch (processor)
	512	{
	513	case PROCESSOR_I386:
b3172cab	514	/* Default. */
edccdcb1 L	515	break;
	516	case PROCESSOR_I486:
	517	cpu = "i486";
	518	break;
	519	case PROCESSOR_PENTIUM:
b3172cab	520	if (arch && has_mmx)
edccdcb1 L	521	cpu = "pentium-mmx";
	522	else
	523	cpu = "pentium";
	524	break;
	525	case PROCESSOR_PENTIUMPRO:
	526	if (has_longmode)
37c50435 L	527	/* It is Core 2 or Atom. */
37c50435 L	528	cpu = (model == 28) ? "atom" : "core2";
b3172cab	529	else if (arch)
edccdcb1	530	{
b3172cab UB	531	if (has_sse3)
	532	/* It is Core Duo. */
	533	cpu = "prescott";
	534	else if (has_sse2)
	535	/* It is Pentium M. */
	536	cpu = "pentium-m";
	537	else if (has_sse)
	538	/* It is Pentium III. */
	539	cpu = "pentium3";
	540	else if (has_mmx)
	541	/* It is Pentium II. */
	542	cpu = "pentium2";
	543	else
	544	/* Default to Pentium Pro. */
	545	cpu = "pentiumpro";
fa959ce4	546	}
edccdcb1	547	else
b3172cab UB	548	/* For -mtune, we default to -mtune=generic. */
	549	cpu = "generic";
	550	break;
	551	case PROCESSOR_PENTIUM4:
	552	if (has_sse3)
fa959ce4	553	{
b3172cab UB	554	if (has_longmode)
b3172cab UB	555	cpu = "nocona";
fa959ce4	556	else
b3172cab	557	cpu = "prescott";
fa959ce4	558	}
b3172cab UB	559	else
b3172cab UB	560	cpu = "pentium4";
edccdcb1 L	561	break;
	562	case PROCESSOR_GEODE:
	563	cpu = "geode";
	564	break;
	565	case PROCESSOR_K6:
b3172cab UB	566	if (arch && has_3dnow)
b3172cab UB	567	cpu = "k6-3";
edccdcb1 L	568	else
	569	cpu = "k6";
	570	break;
	571	case PROCESSOR_ATHLON:
b3172cab	572	if (arch && has_sse)
edccdcb1 L	573	cpu = "athlon-4";
	574	else
	575	cpu = "athlon";
	576	break;
edccdcb1	577	case PROCESSOR_K8:
b3172cab UB	578	if (arch && has_sse3)
	579	cpu = "k8-sse3";
	580	else
	581	cpu = "k8";
edccdcb1	582	break;
35a63f21 DR	583	case PROCESSOR_AMDFAM10:
	584	cpu = "amdfam10";
	585	break;
b3172cab	586
edccdcb1	587	default:
b3172cab UB	588	/* Use something reasonable. */
	589	if (arch)
	590	{
	591	if (has_ssse3)
	592	cpu = "core2";
	593	else if (has_sse3)
	594	{
	595	if (has_longmode)
	596	cpu = "nocona";
	597	else
	598	cpu = "prescott";
	599	}
	600	else if (has_sse2)
	601	cpu = "pentium4";
	602	else if (has_cmov)
	603	cpu = "pentiumpro";
	604	else if (has_mmx)
	605	cpu = "pentium-mmx";
	606	else if (has_cmpxchg8b)
	607	cpu = "pentium";
	608	}
	609	else
	610	cpu = "generic";
fa959ce4 MM	611	}
fa959ce4 MM	612
5be6cb59 UB	613	if (arch)
	614	{
	615	if (has_cmpxchg16b)
f3afc8a7	616	options = concat (options, " -mcx16", NULL);
5be6cb59	617	if (has_lahf_lm)
f3afc8a7	618	options = concat (options, " -msahf", NULL);
cabf85c3	619	if (has_movbe)
f3afc8a7	620	options = concat (options, " -mmovbe", NULL);
634fa334	621	if (has_aes)
f3afc8a7	622	options = concat (options, " -maes", NULL);
634fa334	623	if (has_pclmul)
f3afc8a7	624	options = concat (options, " -mpclmul", NULL);
634fa334	625	if (has_popcnt)
f3afc8a7	626	options = concat (options, " -mpopcnt", NULL);
c3d34a78 SP	627	if (has_abm)
c3d34a78 SP	628	options = concat (options, " -mabm", NULL);
8ad9d49e SP	629	if (has_lwp)
8ad9d49e SP	630	options = concat (options, " -mlwp", NULL);
f3afc8a7	631
634fa334	632	if (has_avx)
f3afc8a7	633	options = concat (options, " -mavx", NULL);
634fa334	634	else if (has_sse4_2)
f3afc8a7	635	options = concat (options, " -msse4.2", NULL);
634fa334	636	else if (has_sse4_1)
f3afc8a7	637	options = concat (options, " -msse4.1", NULL);
5be6cb59 UB	638	}
5be6cb59 UB	639
fa959ce4	640	done:
f3afc8a7	641	return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
fa959ce4 MM	642	}
fa959ce4 MM	643	#else
b3172cab	644
f3afc8a7 UB	645	/* If we aren't compiling with GCC then the driver will just ignore
	646	-march and -mtune "native" target and will leave to the newly
	647	built compiler to generate code for its default target. */
b3172cab	648
f3afc8a7 UB	649	const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
f3afc8a7 UB	650	const char **argv ATTRIBUTE_UNUSED)
fa959ce4	651	{
f3afc8a7	652	return NULL;
fa959ce4	653	}
a6ecb05c	654	#endif /* __GNUC__ */