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X86_64: Enable support for next generation AMD Zen3 CPU.
[thirdparty/gcc.git] / gcc / config / i386 / i386-c.c
CommitLineData
ab442df7 1/* Subroutines used for macro/preprocessor support on the ia-32.
8d9254fc 2 Copyright (C) 2008-2020 Free Software Foundation, Inc.
ab442df7
MM		 3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
8fcc61f8
RS		 20#define IN_TARGET_CODE 1
21
ab442df7
MM		 22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
ab442df7 25#include "target.h"
e11c4407 26#include "c-family/c-common.h"
4d0cdd0c 27#include "memmodel.h"
e11c4407 28#include "tm_p.h"
39dabefd 29#include "c-family/c-pragma.h"
ab442df7 30
5779e713 31static bool ix86_pragma_target_parse (tree, tree);
ab442df7 32static void ix86_target_macros_internal
5fbb13a7 33 (HOST_WIDE_INT, HOST_WIDE_INT, enum processor_type, enum processor_type, enum fpmath_unit,
ab442df7
MM		 34 void (*def_or_undef) (cpp_reader *, const char *));
35
ab442df7
MM		 36/* Internal function to either define or undef the appropriate system
37 macros. */
38static void
df385b9c 39ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
5fbb13a7 40 HOST_WIDE_INT isa_flag2,
ab442df7
MM		 41 enum processor_type arch,
42 enum processor_type tune,
43 enum fpmath_unit fpmath,
44 void (*def_or_undef) (cpp_reader *,
45 const char *))
46{
073a8998 47 /* For some of the k6/pentium varients there weren't separate ISA bits to
ab442df7
MM		 48 identify which tune/arch flag was passed, so figure it out here. */
49 size_t arch_len = strlen (ix86_arch_string);
50 size_t tune_len = strlen (ix86_tune_string);
51 int last_arch_char = ix86_arch_string[arch_len - 1];
52 int last_tune_char = ix86_tune_string[tune_len - 1];
53
54 /* Built-ins based on -march=. */
55 switch (arch)
56 {
57 case PROCESSOR_I386:
58 break;
59 case PROCESSOR_I486:
60 def_or_undef (parse_in, "__i486");
61 def_or_undef (parse_in, "__i486__");
62 break;
2d6b2e28 63 case PROCESSOR_LAKEMONT:
45cef0e9 64 /* Intel MCU is based on Intel Pentium CPU. */
ab442df7
MM		 65 case PROCESSOR_PENTIUM:
66 def_or_undef (parse_in, "__i586");
67 def_or_undef (parse_in, "__i586__");
68 def_or_undef (parse_in, "__pentium");
69 def_or_undef (parse_in, "__pentium__");
70 if (isa_flag & OPTION_MASK_ISA_MMX)
71 def_or_undef (parse_in, "__pentium_mmx__");
72 break;
73 case PROCESSOR_PENTIUMPRO:
74 def_or_undef (parse_in, "__i686");
75 def_or_undef (parse_in, "__i686__");
76 def_or_undef (parse_in, "__pentiumpro");
77 def_or_undef (parse_in, "__pentiumpro__");
78 break;
79 case PROCESSOR_GEODE:
80 def_or_undef (parse_in, "__geode");
81 def_or_undef (parse_in, "__geode__");
82 break;
83 case PROCESSOR_K6:
84 def_or_undef (parse_in, "__k6");
85 def_or_undef (parse_in, "__k6__");
86 if (last_arch_char == '2')
87 def_or_undef (parse_in, "__k6_2__");
88 else if (last_arch_char == '3')
89 def_or_undef (parse_in, "__k6_3__");
90 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
91 def_or_undef (parse_in, "__k6_3__");
92 break;
93 case PROCESSOR_ATHLON:
94 def_or_undef (parse_in, "__athlon");
95 def_or_undef (parse_in, "__athlon__");
96 if (isa_flag & OPTION_MASK_ISA_SSE)
97 def_or_undef (parse_in, "__athlon_sse__");
98 break;
99 case PROCESSOR_K8:
100 def_or_undef (parse_in, "__k8");
101 def_or_undef (parse_in, "__k8__");
102 break;
103 case PROCESSOR_AMDFAM10:
104 def_or_undef (parse_in, "__amdfam10");
105 def_or_undef (parse_in, "__amdfam10__");
106 break;
1133125e
HJ		 107 case PROCESSOR_BDVER1:
108 def_or_undef (parse_in, "__bdver1");
109 def_or_undef (parse_in, "__bdver1__");
110 break;
4d652a18
HJ		 111 case PROCESSOR_BDVER2:
112 def_or_undef (parse_in, "__bdver2");
113 def_or_undef (parse_in, "__bdver2__");
114 break;
eb2f2b44
GG		 115 case PROCESSOR_BDVER3:
116 def_or_undef (parse_in, "__bdver3");
117 def_or_undef (parse_in, "__bdver3__");
118 break;
ed97ad47
GG		 119 case PROCESSOR_BDVER4:
120 def_or_undef (parse_in, "__bdver4");
121 def_or_undef (parse_in, "__bdver4__");
122 break;
9ce29eb0
VK		 123 case PROCESSOR_ZNVER1:
124 def_or_undef (parse_in, "__znver1");
125 def_or_undef (parse_in, "__znver1__");
126 break;
2901f42f
VK		 127 case PROCESSOR_ZNVER2:
128 def_or_undef (parse_in, "__znver2");
129 def_or_undef (parse_in, "__znver2__");
130 break;
3e2ae3ee
VK		 131 case PROCESSOR_ZNVER3:
132 def_or_undef (parse_in, "__znver3");
133 def_or_undef (parse_in, "__znver3__");
134 break;
14b52538
CF		 135 case PROCESSOR_BTVER1:
136 def_or_undef (parse_in, "__btver1");
137 def_or_undef (parse_in, "__btver1__");
138 break;
e32bfc16
VK		 139 case PROCESSOR_BTVER2:
140 def_or_undef (parse_in, "__btver2");
141 def_or_undef (parse_in, "__btver2__");
142 break;
ab442df7
MM		 143 case PROCESSOR_PENTIUM4:
144 def_or_undef (parse_in, "__pentium4");
145 def_or_undef (parse_in, "__pentium4__");
146 break;
147 case PROCESSOR_NOCONA:
148 def_or_undef (parse_in, "__nocona");
149 def_or_undef (parse_in, "__nocona__");
150 break;
340ef734 151 case PROCESSOR_CORE2:
ab442df7
MM		 152 def_or_undef (parse_in, "__core2");
153 def_or_undef (parse_in, "__core2__");
154 break;
d3c11974 155 case PROCESSOR_NEHALEM:
b2b01543
BS		 156 def_or_undef (parse_in, "__corei7");
157 def_or_undef (parse_in, "__corei7__");
d3c11974
L		 158 def_or_undef (parse_in, "__nehalem");
159 def_or_undef (parse_in, "__nehalem__");
b2b01543 160 break;
d3c11974 161 case PROCESSOR_SANDYBRIDGE:
fd5564d3
WM		 162 def_or_undef (parse_in, "__corei7_avx");
163 def_or_undef (parse_in, "__corei7_avx__");
d3c11974
L		 164 def_or_undef (parse_in, "__sandybridge");
165 def_or_undef (parse_in, "__sandybridge__");
fd5564d3 166 break;
3a579e09
VY		 167 case PROCESSOR_HASWELL:
168 def_or_undef (parse_in, "__core_avx2");
169 def_or_undef (parse_in, "__core_avx2__");
d3c11974
L		 170 def_or_undef (parse_in, "__haswell");
171 def_or_undef (parse_in, "__haswell__");
3a579e09 172 break;
d3c11974 173 case PROCESSOR_BONNELL:
b6837b94
JY		 174 def_or_undef (parse_in, "__atom");
175 def_or_undef (parse_in, "__atom__");
d3c11974
L		 176 def_or_undef (parse_in, "__bonnell");
177 def_or_undef (parse_in, "__bonnell__");
b6837b94 178 break;
d3c11974 179 case PROCESSOR_SILVERMONT:
0b871ccf
YR		 180 def_or_undef (parse_in, "__slm");
181 def_or_undef (parse_in, "__slm__");
d3c11974
L		 182 def_or_undef (parse_in, "__silvermont");
183 def_or_undef (parse_in, "__silvermont__");
0b871ccf 184 break;
50e461df
OM		 185 case PROCESSOR_GOLDMONT:
186 def_or_undef (parse_in, "__goldmont");
187 def_or_undef (parse_in, "__goldmont__");
188 break;
74b2bb19
OM		 189 case PROCESSOR_GOLDMONT_PLUS:
190 def_or_undef (parse_in, "__goldmont_plus");
191 def_or_undef (parse_in, "__goldmont_plus__");
192 break;
a548a5a1
OM		 193 case PROCESSOR_TREMONT:
194 def_or_undef (parse_in, "__tremont");
195 def_or_undef (parse_in, "__tremont__");
196 break;
52747219
IT		 197 case PROCESSOR_KNL:
198 def_or_undef (parse_in, "__knl");
199 def_or_undef (parse_in, "__knl__");
200 break;
cace2309
SP		 201 case PROCESSOR_KNM:
202 def_or_undef (parse_in, "__knm");
203 def_or_undef (parse_in, "__knm__");
204 break;
176a3386
OM		 205 case PROCESSOR_SKYLAKE:
206 def_or_undef (parse_in, "__skylake");
207 def_or_undef (parse_in, "__skylake__");
208 break;
06caf59d
KY		 209 case PROCESSOR_SKYLAKE_AVX512:
210 def_or_undef (parse_in, "__skylake_avx512");
211 def_or_undef (parse_in, "__skylake_avx512__");
212 break;
c234d831
UB		 213 case PROCESSOR_CANNONLAKE:
214 def_or_undef (parse_in, "__cannonlake");
215 def_or_undef (parse_in, "__cannonlake__");
216 break;
79ab5364
JK		 217 case PROCESSOR_ICELAKE_CLIENT:
218 def_or_undef (parse_in, "__icelake_client");
219 def_or_undef (parse_in, "__icelake_client__");
220 break;
221 case PROCESSOR_ICELAKE_SERVER:
222 def_or_undef (parse_in, "__icelake_server");
223 def_or_undef (parse_in, "__icelake_server__");
02da1e9c 224 break;
7cab07f0
WX		 225 case PROCESSOR_CASCADELAKE:
226 def_or_undef (parse_in, "__cascadelake");
227 def_or_undef (parse_in, "__cascadelake__");
228 break;
a9fcfec3
HL		 229 case PROCESSOR_TIGERLAKE:
230 def_or_undef (parse_in, "__tigerlake");
231 def_or_undef (parse_in, "__tigerlake__");
232 break;
233 case PROCESSOR_COOPERLAKE:
234 def_or_undef (parse_in, "__cooperlake");
235 def_or_undef (parse_in, "__cooperlake__");
ba9c87d3
CL		 236 break;
237 case PROCESSOR_SAPPHIRERAPIDS:
238 def_or_undef (parse_in, "__sapphirerapids");
239 def_or_undef (parse_in, "__sapphirerapids__");
240 break;
241 case PROCESSOR_ALDERLAKE:
242 def_or_undef (parse_in, "__alderlake");
243 def_or_undef (parse_in, "__alderlake__");
244 break;
ab442df7
MM		 245 /* use PROCESSOR_max to not set/unset the arch macro. */
246 case PROCESSOR_max:
247 break;
9a7f94d7 248 case PROCESSOR_INTEL:
9d532162 249 case PROCESSOR_GENERIC:
ab442df7
MM		 250 gcc_unreachable ();
251 }
252
253 /* Built-ins based on -mtune=. */
254 switch (tune)
255 {
256 case PROCESSOR_I386:
257 def_or_undef (parse_in, "__tune_i386__");
258 break;
259 case PROCESSOR_I486:
260 def_or_undef (parse_in, "__tune_i486__");
261 break;
262 case PROCESSOR_PENTIUM:
263 def_or_undef (parse_in, "__tune_i586__");
264 def_or_undef (parse_in, "__tune_pentium__");
265 if (last_tune_char == 'x')
266 def_or_undef (parse_in, "__tune_pentium_mmx__");
267 break;
268 case PROCESSOR_PENTIUMPRO:
269 def_or_undef (parse_in, "__tune_i686__");
270 def_or_undef (parse_in, "__tune_pentiumpro__");
271 switch (last_tune_char)
272 {
273 case '3':
274 def_or_undef (parse_in, "__tune_pentium3__");
275 /* FALLTHRU */
276 case '2':
277 def_or_undef (parse_in, "__tune_pentium2__");
278 break;
279 }
280 break;
281 case PROCESSOR_GEODE:
282 def_or_undef (parse_in, "__tune_geode__");
283 break;
284 case PROCESSOR_K6:
285 def_or_undef (parse_in, "__tune_k6__");
286 if (last_tune_char == '2')
287 def_or_undef (parse_in, "__tune_k6_2__");
288 else if (last_tune_char == '3')
289 def_or_undef (parse_in, "__tune_k6_3__");
290 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
291 def_or_undef (parse_in, "__tune_k6_3__");
292 break;
293 case PROCESSOR_ATHLON:
294 def_or_undef (parse_in, "__tune_athlon__");
295 if (isa_flag & OPTION_MASK_ISA_SSE)
296 def_or_undef (parse_in, "__tune_athlon_sse__");
297 break;
298 case PROCESSOR_K8:
299 def_or_undef (parse_in, "__tune_k8__");
300 break;
301 case PROCESSOR_AMDFAM10:
302 def_or_undef (parse_in, "__tune_amdfam10__");
303 break;
1133125e
HJ		 304 case PROCESSOR_BDVER1:
305 def_or_undef (parse_in, "__tune_bdver1__");
306 break;
4d652a18
HJ		 307 case PROCESSOR_BDVER2:
308 def_or_undef (parse_in, "__tune_bdver2__");
309 break;
eb2f2b44
GG		 310 case PROCESSOR_BDVER3:
311 def_or_undef (parse_in, "__tune_bdver3__");
ed97ad47
GG		 312 break;
313 case PROCESSOR_BDVER4:
314 def_or_undef (parse_in, "__tune_bdver4__");
eb2f2b44 315 break;
9ce29eb0
VK		 316 case PROCESSOR_ZNVER1:
317 def_or_undef (parse_in, "__tune_znver1__");
318 break;
2901f42f
VK		 319 case PROCESSOR_ZNVER2:
320 def_or_undef (parse_in, "__tune_znver2__");
321 break;
3e2ae3ee
VK		 322 case PROCESSOR_ZNVER3:
323 def_or_undef (parse_in, "__tune_znver3__");
324 break;
eb2f2b44 325 case PROCESSOR_BTVER1:
14b52538
CF		 326 def_or_undef (parse_in, "__tune_btver1__");
327 break;
e32bfc16
VK		 328 case PROCESSOR_BTVER2:
329 def_or_undef (parse_in, "__tune_btver2__");
330 break;
ab442df7
MM		 331 case PROCESSOR_PENTIUM4:
332 def_or_undef (parse_in, "__tune_pentium4__");
333 break;
334 case PROCESSOR_NOCONA:
335 def_or_undef (parse_in, "__tune_nocona__");
336 break;
340ef734 337 case PROCESSOR_CORE2:
ab442df7
MM		 338 def_or_undef (parse_in, "__tune_core2__");
339 break;
d3c11974 340 case PROCESSOR_NEHALEM:
b2b01543 341 def_or_undef (parse_in, "__tune_corei7__");
d3c11974 342 def_or_undef (parse_in, "__tune_nehalem__");
b2b01543 343 break;
d3c11974 344 case PROCESSOR_SANDYBRIDGE:
fd5564d3 345 def_or_undef (parse_in, "__tune_corei7_avx__");
d3c11974 346 def_or_undef (parse_in, "__tune_sandybridge__");
fd5564d3 347 break;
3a579e09
VY		 348 case PROCESSOR_HASWELL:
349 def_or_undef (parse_in, "__tune_core_avx2__");
d3c11974 350 def_or_undef (parse_in, "__tune_haswell__");
3a579e09 351 break;
d3c11974 352 case PROCESSOR_BONNELL:
b6837b94 353 def_or_undef (parse_in, "__tune_atom__");
d3c11974 354 def_or_undef (parse_in, "__tune_bonnell__");
b6837b94 355 break;
d3c11974 356 case PROCESSOR_SILVERMONT:
0b871ccf 357 def_or_undef (parse_in, "__tune_slm__");
d3c11974 358 def_or_undef (parse_in, "__tune_silvermont__");
0b871ccf 359 break;
50e461df
OM		 360 case PROCESSOR_GOLDMONT:
361 def_or_undef (parse_in, "__tune_goldmont__");
362 break;
74b2bb19
OM		 363 case PROCESSOR_GOLDMONT_PLUS:
364 def_or_undef (parse_in, "__tune_goldmont_plus__");
365 break;
a548a5a1
OM		 366 case PROCESSOR_TREMONT:
367 def_or_undef (parse_in, "__tune_tremont__");
368 break;
52747219
IT		 369 case PROCESSOR_KNL:
370 def_or_undef (parse_in, "__tune_knl__");
371 break;
cace2309
SP		 372 case PROCESSOR_KNM:
373 def_or_undef (parse_in, "__tune_knm__");
374 break;
176a3386
OM		 375 case PROCESSOR_SKYLAKE:
376 def_or_undef (parse_in, "__tune_skylake__");
377 break;
06caf59d
KY		 378 case PROCESSOR_SKYLAKE_AVX512:
379 def_or_undef (parse_in, "__tune_skylake_avx512__");
380 break;
c234d831
UB		 381 case PROCESSOR_CANNONLAKE:
382 def_or_undef (parse_in, "__tune_cannonlake__");
383 break;
79ab5364
JK		 384 case PROCESSOR_ICELAKE_CLIENT:
385 def_or_undef (parse_in, "__tune_icelake_client__");
386 break;
387 case PROCESSOR_ICELAKE_SERVER:
388 def_or_undef (parse_in, "__tune_icelake_server__");
02da1e9c 389 break;
2d6b2e28
L		 390 case PROCESSOR_LAKEMONT:
391 def_or_undef (parse_in, "__tune_lakemont__");
45cef0e9 392 break;
7cab07f0
WX		 393 case PROCESSOR_CASCADELAKE:
394 def_or_undef (parse_in, "__tune_cascadelake__");
395 break;
a9fcfec3
HL		 396 case PROCESSOR_TIGERLAKE:
397 def_or_undef (parse_in, "__tune_tigerlake__");
398 break;
399 case PROCESSOR_COOPERLAKE:
400 def_or_undef (parse_in, "__tune_cooperlake__");
401 break;
ba9c87d3
CL		 402 case PROCESSOR_SAPPHIRERAPIDS:
403 def_or_undef (parse_in, "__tune_sapphirerapids__");
404 break;
405 case PROCESSOR_ALDERLAKE:
406 def_or_undef (parse_in, "__tune_alderlake__");
407 break;
9a7f94d7 408 case PROCESSOR_INTEL:
9d532162 409 case PROCESSOR_GENERIC:
ab442df7
MM		 410 break;
411 /* use PROCESSOR_max to not set/unset the tune macro. */
412 case PROCESSOR_max:
413 break;
414 }
415
bb664f09
UB		 416 switch (ix86_cmodel)
417 {
418 case CM_SMALL:
419 case CM_SMALL_PIC:
420 def_or_undef (parse_in, "__code_model_small__");
421 break;
422 case CM_MEDIUM:
423 case CM_MEDIUM_PIC:
424 def_or_undef (parse_in, "__code_model_medium__");
425 break;
426 case CM_LARGE:
427 case CM_LARGE_PIC:
428 def_or_undef (parse_in, "__code_model_large__");
429 break;
430 case CM_32:
431 def_or_undef (parse_in, "__code_model_32__");
432 break;
433 case CM_KERNEL:
434 def_or_undef (parse_in, "__code_model_kernel__");
435 break;
436 default:
437 ;
438 }
439
8cf86e14 440 if (isa_flag2 & OPTION_MASK_ISA2_WBNOINVD)
13b93d4b 441 def_or_undef (parse_in, "__WBNOINVD__");
8cf86e14 442 if (isa_flag2 & OPTION_MASK_ISA2_AVX512VP2INTERSECT)
e21b52af 443 def_or_undef (parse_in, "__AVX512VP2INTERSECT__");
ab442df7
MM		 444 if (isa_flag & OPTION_MASK_ISA_MMX)
445 def_or_undef (parse_in, "__MMX__");
446 if (isa_flag & OPTION_MASK_ISA_3DNOW)
447 def_or_undef (parse_in, "__3dNOW__");
448 if (isa_flag & OPTION_MASK_ISA_3DNOW_A)
449 def_or_undef (parse_in, "__3dNOW_A__");
450 if (isa_flag & OPTION_MASK_ISA_SSE)
451 def_or_undef (parse_in, "__SSE__");
452 if (isa_flag & OPTION_MASK_ISA_SSE2)
453 def_or_undef (parse_in, "__SSE2__");
454 if (isa_flag & OPTION_MASK_ISA_SSE3)
455 def_or_undef (parse_in, "__SSE3__");
456 if (isa_flag & OPTION_MASK_ISA_SSSE3)
457 def_or_undef (parse_in, "__SSSE3__");
458 if (isa_flag & OPTION_MASK_ISA_SSE4_1)
459 def_or_undef (parse_in, "__SSE4_1__");
460 if (isa_flag & OPTION_MASK_ISA_SSE4_2)
461 def_or_undef (parse_in, "__SSE4_2__");
462 if (isa_flag & OPTION_MASK_ISA_AES)
463 def_or_undef (parse_in, "__AES__");
c1618f82
AI		 464 if (isa_flag & OPTION_MASK_ISA_SHA)
465 def_or_undef (parse_in, "__SHA__");
ab442df7
MM		 466 if (isa_flag & OPTION_MASK_ISA_PCLMUL)
467 def_or_undef (parse_in, "__PCLMUL__");
95879c72
L		 468 if (isa_flag & OPTION_MASK_ISA_AVX)
469 def_or_undef (parse_in, "__AVX__");
7afac110
KY		 470 if (isa_flag & OPTION_MASK_ISA_AVX2)
471 def_or_undef (parse_in, "__AVX2__");
3f97cb0b
AI		 472 if (isa_flag & OPTION_MASK_ISA_AVX512F)
473 def_or_undef (parse_in, "__AVX512F__");
474 if (isa_flag & OPTION_MASK_ISA_AVX512ER)
475 def_or_undef (parse_in, "__AVX512ER__");
476 if (isa_flag & OPTION_MASK_ISA_AVX512CD)
477 def_or_undef (parse_in, "__AVX512CD__");
478 if (isa_flag & OPTION_MASK_ISA_AVX512PF)
479 def_or_undef (parse_in, "__AVX512PF__");
07165dd7
AI		 480 if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
481 def_or_undef (parse_in, "__AVX512DQ__");
b525d943
AI		 482 if (isa_flag & OPTION_MASK_ISA_AVX512BW)
483 def_or_undef (parse_in, "__AVX512BW__");
f4af595f
AI		 484 if (isa_flag & OPTION_MASK_ISA_AVX512VL)
485 def_or_undef (parse_in, "__AVX512VL__");
3dcc8af5
IT		 486 if (isa_flag & OPTION_MASK_ISA_AVX512VBMI)
487 def_or_undef (parse_in, "__AVX512VBMI__");
4190ea38
IT		 488 if (isa_flag & OPTION_MASK_ISA_AVX512IFMA)
489 def_or_undef (parse_in, "__AVX512IFMA__");
8cf86e14 490 if (isa_flag2 & OPTION_MASK_ISA2_AVX5124VNNIW)
5fbb13a7 491 def_or_undef (parse_in, "__AVX5124VNNIW__");
b1ccd09a 492 if (isa_flag & OPTION_MASK_ISA_AVX512VBMI2)
fca51879 493 def_or_undef (parse_in, "__AVX512VBMI2__");
fefab953 494 if (isa_flag & OPTION_MASK_ISA_AVX512VNNI)
98966963 495 def_or_undef (parse_in, "__AVX512VNNI__");
8cf86e14 496 if (isa_flag2 & OPTION_MASK_ISA2_PCONFIG)
13b93d4b 497 def_or_undef (parse_in, "__PCONFIG__");
8cf86e14 498 if (isa_flag2 & OPTION_MASK_ISA2_SGX)
73e32c47 499 def_or_undef (parse_in, "__SGX__");
8cf86e14 500 if (isa_flag2 & OPTION_MASK_ISA2_AVX5124FMAPS)
5fbb13a7 501 def_or_undef (parse_in, "__AVX5124FMAPS__");
2e34b5bc 502 if (isa_flag & OPTION_MASK_ISA_AVX512BITALG)
e2a29465 503 def_or_undef (parse_in, "__AVX512BITALG__");
2e34b5bc 504 if (isa_flag & OPTION_MASK_ISA_AVX512VPOPCNTDQ)
79fc8ffe 505 def_or_undef (parse_in, "__AVX512VPOPCNTDQ__");
95879c72
L		 506 if (isa_flag & OPTION_MASK_ISA_FMA)
507 def_or_undef (parse_in, "__FMA__");
bf2eaa3f
KY		 508 if (isa_flag & OPTION_MASK_ISA_RTM)
509 def_or_undef (parse_in, "__RTM__");
ab442df7
MM		 510 if (isa_flag & OPTION_MASK_ISA_SSE4A)
511 def_or_undef (parse_in, "__SSE4A__");
cbf2e4d4
HJ		 512 if (isa_flag & OPTION_MASK_ISA_FMA4)
513 def_or_undef (parse_in, "__FMA4__");
43a8b705
HJ		 514 if (isa_flag & OPTION_MASK_ISA_XOP)
515 def_or_undef (parse_in, "__XOP__");
3e901069
HJ		 516 if (isa_flag & OPTION_MASK_ISA_LWP)
517 def_or_undef (parse_in, "__LWP__");
13c0eb43
SP		 518 if (isa_flag & OPTION_MASK_ISA_ABM)
519 def_or_undef (parse_in, "__ABM__");
91afcfa3
QN		 520 if (isa_flag & OPTION_MASK_ISA_BMI)
521 def_or_undef (parse_in, "__BMI__");
82feeb8d
L		 522 if (isa_flag & OPTION_MASK_ISA_BMI2)
523 def_or_undef (parse_in, "__BMI2__");
5fcafa60
KY		 524 if (isa_flag & OPTION_MASK_ISA_LZCNT)
525 def_or_undef (parse_in, "__LZCNT__");
94d13ad1
QN		 526 if (isa_flag & OPTION_MASK_ISA_TBM)
527 def_or_undef (parse_in, "__TBM__");
3bccee03
SP		 528 if (isa_flag & OPTION_MASK_ISA_POPCNT)
529 def_or_undef (parse_in, "__POPCNT__");
4ee89d5f
L		 530 if (isa_flag & OPTION_MASK_ISA_FSGSBASE)
531 def_or_undef (parse_in, "__FSGSBASE__");
532 if (isa_flag & OPTION_MASK_ISA_RDRND)
533 def_or_undef (parse_in, "__RDRND__");
534 if (isa_flag & OPTION_MASK_ISA_F16C)
535 def_or_undef (parse_in, "__F16C__");
4c340b5d
KY		 536 if (isa_flag & OPTION_MASK_ISA_RDSEED)
537 def_or_undef (parse_in, "__RDSEED__");
e61c94dd
KY		 538 if (isa_flag & OPTION_MASK_ISA_PRFCHW)
539 def_or_undef (parse_in, "__PRFCHW__");
d05e383b
MZ		 540 if (isa_flag & OPTION_MASK_ISA_ADX)
541 def_or_undef (parse_in, "__ADX__");
3a0d99bb
AI		 542 if (isa_flag & OPTION_MASK_ISA_FXSR)
543 def_or_undef (parse_in, "__FXSR__");
544 if (isa_flag & OPTION_MASK_ISA_XSAVE)
545 def_or_undef (parse_in, "__XSAVE__");
546 if (isa_flag & OPTION_MASK_ISA_XSAVEOPT)
547 def_or_undef (parse_in, "__XSAVEOPT__");
43b3f52f
IT		 548 if (isa_flag & OPTION_MASK_ISA_PREFETCHWT1)
549 def_or_undef (parse_in, "__PREFETCHWT1__");
ab442df7
MM		 550 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
551 def_or_undef (parse_in, "__SSE_MATH__");
552 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
553 def_or_undef (parse_in, "__SSE2_MATH__");
9cdea277
IT		 554 if (isa_flag & OPTION_MASK_ISA_CLFLUSHOPT)
555 def_or_undef (parse_in, "__CLFLUSHOPT__");
8cf86e14 556 if (isa_flag2 & OPTION_MASK_ISA2_CLZERO)
9ce29eb0 557 def_or_undef (parse_in, "__CLZERO__");
9cdea277
IT		 558 if (isa_flag & OPTION_MASK_ISA_XSAVEC)
559 def_or_undef (parse_in, "__XSAVEC__");
560 if (isa_flag & OPTION_MASK_ISA_XSAVES)
561 def_or_undef (parse_in, "__XSAVES__");
9c3bca11
IT		 562 if (isa_flag & OPTION_MASK_ISA_CLWB)
563 def_or_undef (parse_in, "__CLWB__");
8cf86e14 564 if (isa_flag2 & OPTION_MASK_ISA2_MWAITX)
500a08b2 565 def_or_undef (parse_in, "__MWAITX__");
41a4ef22
KY		 566 if (isa_flag & OPTION_MASK_ISA_PKU)
567 def_or_undef (parse_in, "__PKU__");
8cf86e14 568 if (isa_flag2 & OPTION_MASK_ISA2_RDPID)
1d516992 569 def_or_undef (parse_in, "__RDPID__");
d4bc3829 570 if (isa_flag & OPTION_MASK_ISA_GFNI)
b8cca31c 571 def_or_undef (parse_in, "__GFNI__");
e95dda95
L		 572 if ((isa_flag & OPTION_MASK_ISA_SHSTK))
573 def_or_undef (parse_in, "__SHSTK__");
8cf86e14 574 if (isa_flag2 & OPTION_MASK_ISA2_VAES)
b7b0a4fa 575 def_or_undef (parse_in, "__VAES__");
6557be99
JK		 576 if (isa_flag & OPTION_MASK_ISA_VPCLMULQDQ)
577 def_or_undef (parse_in, "__VPCLMULQDQ__");
37d51c75
SP		 578 if (isa_flag & OPTION_MASK_ISA_MOVDIRI)
579 def_or_undef (parse_in, "__MOVDIRI__");
8cf86e14 580 if (isa_flag2 & OPTION_MASK_ISA2_MOVDIR64B)
37d51c75 581 def_or_undef (parse_in, "__MOVDIR64B__");
8cf86e14 582 if (isa_flag2 & OPTION_MASK_ISA2_WAITPKG)
55f31ed1 583 def_or_undef (parse_in, "__WAITPKG__");
8cf86e14 584 if (isa_flag2 & OPTION_MASK_ISA2_CLDEMOTE)
f8d9957e 585 def_or_undef (parse_in, "__CLDEMOTE__");
366386c7 586 if (isa_flag2 & OPTION_MASK_ISA2_SERIALIZE)
587 def_or_undef (parse_in, "__SERIALIZE__");
8cf86e14 588 if (isa_flag2 & OPTION_MASK_ISA2_PTWRITE)
41f8d1fc 589 def_or_undef (parse_in, "__PTWRITE__");
8cf86e14 590 if (isa_flag2 & OPTION_MASK_ISA2_AVX512BF16)
4f0e90fa 591 def_or_undef (parse_in, "__AVX512BF16__");
dfa61b9e
L		 592 if (TARGET_MMX_WITH_SSE)
593 def_or_undef (parse_in, "__MMX_WITH_SSE__");
8cf86e14 594 if (isa_flag2 & OPTION_MASK_ISA2_ENQCMD)
6a10feda 595 def_or_undef (parse_in, "__ENQCMD__");
1e47cb35 596 if (isa_flag2 & OPTION_MASK_ISA2_TSXLDTRK)
597 def_or_undef (parse_in, "__TSXLDTRK__");
5c609842 598 if (isa_flag2 & OPTION_MASK_ISA2_AMX_TILE)
599 def_or_undef (parse_in, "__AMX_TILE__");
600 if (isa_flag2 & OPTION_MASK_ISA2_AMX_INT8)
601 def_or_undef (parse_in, "__AMX_INT8__");
602 if (isa_flag2 & OPTION_MASK_ISA2_AMX_BF16)
603 def_or_undef (parse_in, "__AMX_BF16__");
92e652d8
FW		 604 if (isa_flag & OPTION_MASK_ISA_SAHF)
605 def_or_undef (parse_in, "__LAHF_SAHF__");
606 if (isa_flag2 & OPTION_MASK_ISA2_MOVBE)
607 def_or_undef (parse_in, "__MOVBE__");
299a53d7 608 if (isa_flag2 & OPTION_MASK_ISA2_UINTR)
609 def_or_undef (parse_in, "__UINTR__");
83927c63
HW		 610 if (isa_flag2 & OPTION_MASK_ISA2_HRESET)
611 def_or_undef (parse_in, "__HRESET__");
632a2f50 612 if (isa_flag2 & OPTION_MASK_ISA2_KL)
613 def_or_undef (parse_in, "__KL__");
614 if (isa_flag2 & OPTION_MASK_ISA2_WIDEKL)
615 def_or_undef (parse_in, "__WIDEKL__");
ca813880 616 if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNI)
617 def_or_undef (parse_in, "__AVXVNNI__");
d9063947
L		 618 if (TARGET_IAMCU)
619 {
620 def_or_undef (parse_in, "__iamcu");
621 def_or_undef (parse_in, "__iamcu__");
622 }
ab442df7
MM		 623}
624
625\f
5779e713
MM		 626/* Hook to validate the current #pragma GCC target and set the state, and
627 update the macros based on what was changed. If ARGS is NULL, then
628 POP_TARGET is used to reset the options. */
ab442df7
MM		 629
630static bool
5779e713 631ix86_pragma_target_parse (tree args, tree pop_target)
ab442df7 632{
ba948b37
JJ		 633 tree prev_tree
634 = build_target_option_node (&global_options, &global_options_set);
ab442df7
MM		 635 tree cur_tree;
636 struct cl_target_option *prev_opt;
637 struct cl_target_option *cur_opt;
df385b9c
L		 638 HOST_WIDE_INT prev_isa;
639 HOST_WIDE_INT cur_isa;
640 HOST_WIDE_INT diff_isa;
5fbb13a7
KY		 641 HOST_WIDE_INT prev_isa2;
642 HOST_WIDE_INT cur_isa2;
643 HOST_WIDE_INT diff_isa2;
ab442df7
MM		 644 enum processor_type prev_arch;
645 enum processor_type prev_tune;
646 enum processor_type cur_arch;
647 enum processor_type cur_tune;
648
649 if (! args)
650 {
97db2bf7 651 cur_tree = (pop_target ? pop_target : target_option_default_node);
ba948b37 652 cl_target_option_restore (&global_options, &global_options_set,
46625112 653 TREE_TARGET_OPTION (cur_tree));
ab442df7
MM		 654 }
655 else
656 {
cc2a672a
ML		 657 cur_tree = ix86_valid_target_attribute_tree (NULL_TREE, args,
658 &global_options,
659 &global_options_set, 0);
97db2bf7
ST		 660 if (!cur_tree || cur_tree == error_mark_node)
661 {
ba948b37 662 cl_target_option_restore (&global_options, &global_options_set,
97db2bf7
ST		 663 TREE_TARGET_OPTION (prev_tree));
664 return false;
665 }
ab442df7
MM		 666 }
667
668 target_option_current_node = cur_tree;
97db2bf7 669 ix86_reset_previous_fndecl ();
ab442df7
MM		 670
671 /* Figure out the previous/current isa, arch, tune and the differences. */
672 prev_opt = TREE_TARGET_OPTION (prev_tree);
673 cur_opt = TREE_TARGET_OPTION (cur_tree);
e3339d0f
JM		 674 prev_isa = prev_opt->x_ix86_isa_flags;
675 cur_isa = cur_opt->x_ix86_isa_flags;
ab442df7 676 diff_isa = (prev_isa ^ cur_isa);
5fbb13a7
KY		 677 prev_isa2 = prev_opt->x_ix86_isa_flags2;
678 cur_isa2 = cur_opt->x_ix86_isa_flags2;
679 diff_isa2 = (prev_isa2 ^ cur_isa2);
32e8bb8e
ILT		 680 prev_arch = (enum processor_type) prev_opt->arch;
681 prev_tune = (enum processor_type) prev_opt->tune;
682 cur_arch = (enum processor_type) cur_opt->arch;
683 cur_tune = (enum processor_type) cur_opt->tune;
ab442df7
MM		 684
685 /* If the same processor is used for both previous and current options, don't
686 change the macros. */
687 if (cur_arch == prev_arch)
688 cur_arch = prev_arch = PROCESSOR_max;
689
690 if (cur_tune == prev_tune)
691 cur_tune = prev_tune = PROCESSOR_max;
692
693 /* Undef all of the macros for that are no longer current. */
694 ix86_target_macros_internal (prev_isa & diff_isa,
5fbb13a7 695 prev_isa2 & diff_isa2,
ab442df7
MM		 696 prev_arch,
697 prev_tune,
8023568e 698 (enum fpmath_unit) prev_opt->x_ix86_fpmath,
ab442df7
MM		 699 cpp_undef);
700
fa5d6c75
JJ		 701 /* For the definitions, ensure all newly defined macros are considered
702 as used for -Wunused-macros. There is no point warning about the
703 compiler predefined macros. */
704 cpp_options *cpp_opts = cpp_get_options (parse_in);
705 unsigned char saved_warn_unused_macros = cpp_opts->warn_unused_macros;
706 cpp_opts->warn_unused_macros = 0;
707
ab442df7
MM		 708 /* Define all of the macros for new options that were just turned on. */
709 ix86_target_macros_internal (cur_isa & diff_isa,
5fbb13a7 710 cur_isa2 & diff_isa2,
ab442df7
MM		 711 cur_arch,
712 cur_tune,
8023568e 713 (enum fpmath_unit) cur_opt->x_ix86_fpmath,
ab442df7
MM		 714 cpp_define);
715
fa5d6c75
JJ		 716 cpp_opts->warn_unused_macros = saved_warn_unused_macros;
717
ab442df7
MM		 718 return true;
719}
720\f
721/* Function to tell the preprocessor about the defines for the current target. */
722
723void
724ix86_target_macros (void)
725{
726 /* 32/64-bit won't change with target specific options, so do the assert and
727 builtin_define_std calls here. */
728 if (TARGET_64BIT)
729 {
730 cpp_assert (parse_in, "cpu=x86_64");
731 cpp_assert (parse_in, "machine=x86_64");
732 cpp_define (parse_in, "__amd64");
733 cpp_define (parse_in, "__amd64__");
734 cpp_define (parse_in, "__x86_64");
735 cpp_define (parse_in, "__x86_64__");
6573c644
L		 736 if (TARGET_X32)
737 {
738 cpp_define (parse_in, "_ILP32");
739 cpp_define (parse_in, "__ILP32__");
740 }
ab442df7
MM		 741 }
742 else
743 {
744 cpp_assert (parse_in, "cpu=i386");
745 cpp_assert (parse_in, "machine=i386");
746 builtin_define_std ("i386");
13a46321
GP		 747 cpp_define (parse_in, "_ILP32");
748 cpp_define (parse_in, "__ILP32__");
ab442df7
MM		 749 }
750
02ac9503
UB		 751 if (!TARGET_80387)
752 cpp_define (parse_in, "_SOFT_FLOAT");
753
c637141a
L		 754 if (TARGET_LONG_DOUBLE_64)
755 cpp_define (parse_in, "__LONG_DOUBLE_64__");
756
a2a1ddb5
L		 757 if (TARGET_LONG_DOUBLE_128)
758 cpp_define (parse_in, "__LONG_DOUBLE_128__");
759
30c0a59a
MG		 760 if (TARGET_128BIT_LONG_DOUBLE)
761 cpp_define (parse_in, "__SIZEOF_FLOAT80__=16");
762 else
763 cpp_define (parse_in, "__SIZEOF_FLOAT80__=12");
764
765 cpp_define (parse_in, "__SIZEOF_FLOAT128__=16");
766
d5becc11
JJ		 767 cpp_define_formatted (parse_in, "__ATOMIC_HLE_ACQUIRE=%d", IX86_HLE_ACQUIRE);
768 cpp_define_formatted (parse_in, "__ATOMIC_HLE_RELEASE=%d", IX86_HLE_RELEASE);
769
f767f583
RH		 770 cpp_define (parse_in, "__GCC_ASM_FLAG_OUTPUTS__");
771
ab442df7 772 ix86_target_macros_internal (ix86_isa_flags,
5fbb13a7 773 ix86_isa_flags2,
ab442df7
MM		 774 ix86_arch,
775 ix86_tune,
776 ix86_fpmath,
777 cpp_define);
00402c94
RH		 778
779 cpp_define (parse_in, "__SEG_FS");
780 cpp_define (parse_in, "__SEG_GS");
e95dda95
L		 781
782 if (flag_cf_protection != CF_NONE)
783 cpp_define_formatted (parse_in, "__CET__=%d",
784 flag_cf_protection & ~CF_SET);
ab442df7
MM		 785}
786
787\f
788/* Register target pragmas. We need to add the hook for parsing #pragma GCC
789 option here rather than in i386.c since it will pull in various preprocessor
790 functions, and those are not present in languages like fortran without a
791 preprocessor. */
792
793void
794ix86_register_pragmas (void)
795{
5779e713
MM		 796 /* Update pragma hook to allow parsing #pragma GCC target. */
797 targetm.target_option.pragma_parse = ix86_pragma_target_parse;
ab442df7 798
00402c94
RH		 799 c_register_addr_space ("__seg_fs", ADDR_SPACE_SEG_FS);
800 c_register_addr_space ("__seg_gs", ADDR_SPACE_SEG_GS);
00402c94 801
ab442df7
MM		 802#ifdef REGISTER_SUBTARGET_PRAGMAS
803 REGISTER_SUBTARGET_PRAGMAS ();
804#endif
805}
Mirror of https://gcc.gnu.org/git/gcc.git