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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
23a5b65a | 2 | Copyright (C) 2002-2014 Free Software Foundation, Inc. |
a5381466 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
a5381466 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
a5381466 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
a5381466 ZW |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
a5381466 ZW |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
a5381466 | 19 | |
968a7562 | 20 | /* The x86_64 ABI specifies both XF and TF modes. |
f8a1ebc6 | 21 | XFmode is __float80 is IEEE extended; TFmode is __float128 |
968a7562 | 22 | is IEEE quad. */ |
f8a1ebc6 | 23 | |
968a7562 ZW |
24 | FRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format); |
25 | FLOAT_MODE (TF, 16, ieee_quad_format); | |
94134f42 | 26 | |
968a7562 ZW |
27 | /* In ILP32 mode, XFmode has size 12 and alignment 4. |
28 | In LP64 mode, XFmode has size and alignment 16. */ | |
ac3ef3f5 JH |
29 | ADJUST_FLOAT_FORMAT (XF, (TARGET_128BIT_LONG_DOUBLE |
30 | ? &ieee_extended_intel_128_format | |
cc69336f RH |
31 | : TARGET_96_ROUND_53_LONG_DOUBLE |
32 | ? &ieee_extended_intel_96_round_53_format | |
ac3ef3f5 | 33 | : &ieee_extended_intel_96_format)); |
f8a1ebc6 JH |
34 | ADJUST_BYTESIZE (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 12); |
35 | ADJUST_ALIGNMENT (XF, TARGET_128BIT_LONG_DOUBLE ? 16 : 4); | |
94134f42 | 36 | |
a5381466 ZW |
37 | /* Add any extra modes needed to represent the condition code. |
38 | ||
39 | For the i386, we need separate modes when floating-point | |
40 | equality comparisons are being done. | |
41 | ||
42 | Add CCNO to indicate comparisons against zero that requires | |
43 | Overflow flag to be unset. Sign bit test is used instead and | |
44 | thus can be used to form "a&b>0" type of tests. | |
45 | ||
4aae8a9a | 46 | Add CCGC to indicate comparisons against zero that allows |
a5381466 ZW |
47 | unspecified garbage in the Carry flag. This mode is used |
48 | by inc/dec instructions. | |
49 | ||
4aae8a9a | 50 | Add CCGOC to indicate comparisons against zero that allows |
a5381466 ZW |
51 | unspecified garbage in the Carry and Overflow flag. This |
52 | mode is used to simulate comparisons of (a-b) and (a+b) | |
53 | against zero using sub/cmp/add operations. | |
54 | ||
06f4e35d L |
55 | Add CCA to indicate that only the Above flag is valid. |
56 | Add CCC to indicate that only the Carry flag is valid. | |
57 | Add CCO to indicate that only the Overflow flag is valid. | |
58 | Add CCS to indicate that only the Sign flag is valid. | |
a5381466 ZW |
59 | Add CCZ to indicate that only the Zero flag is valid. */ |
60 | ||
94134f42 ZW |
61 | CC_MODE (CCGC); |
62 | CC_MODE (CCGOC); | |
63 | CC_MODE (CCNO); | |
06f4e35d L |
64 | CC_MODE (CCA); |
65 | CC_MODE (CCC); | |
66 | CC_MODE (CCO); | |
67 | CC_MODE (CCS); | |
94134f42 ZW |
68 | CC_MODE (CCZ); |
69 | CC_MODE (CCFP); | |
70 | CC_MODE (CCFPU); | |
49e76be8 | 71 | |
0fac5151 RH |
72 | /* Vector modes. Note that VEC_CONCAT patterns require vector |
73 | sizes twice as big as implemented in hardware. */ | |
74 | VECTOR_MODES (INT, 4); /* V4QI V2HI */ | |
75 | VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ | |
76 | VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ | |
77 | VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ | |
78 | VECTOR_MODES (INT, 64); /* V64QI V32HI V16SI V8DI */ | |
3f97cb0b | 79 | VECTOR_MODES (INT, 128); /* V128QI V64HI V32SI V16DI */ |
0fac5151 RH |
80 | VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */ |
81 | VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ | |
82 | VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ | |
83 | VECTOR_MODES (FLOAT, 64); /* V32HF V16SF V8DF */ | |
3f97cb0b | 84 | VECTOR_MODES (FLOAT, 128); /* V64HF V32SF V16DF */ |
fe6ae2da | 85 | VECTOR_MODE (INT, TI, 1); /* V1TI */ |
0fac5151 RH |
86 | VECTOR_MODE (INT, DI, 1); /* V1DI */ |
87 | VECTOR_MODE (INT, SI, 1); /* V1SI */ | |
88 | VECTOR_MODE (INT, QI, 2); /* V2QI */ | |
4a90ee35 AI |
89 | VECTOR_MODE (INT, QI, 12); /* V12QI */ |
90 | VECTOR_MODE (INT, QI, 14); /* V14QI */ | |
91 | VECTOR_MODE (INT, HI, 6); /* V6HI */ | |
95879c72 | 92 | |
d5e254e1 IE |
93 | POINTER_BOUNDS_MODE (BND32, 8); |
94 | POINTER_BOUNDS_MODE (BND64, 16); | |
95 | ||
95879c72 | 96 | INT_MODE (OI, 32); |
3f97cb0b | 97 | INT_MODE (XI, 64); |
49e76be8 | 98 | |
8fd05f4d KZ |
99 | /* Keep the OI and XI modes from confusing the compiler into thinking |
100 | that these modes could actually be used for computation. They are | |
101 | only holders for vectors during data movement. */ | |
102 | #define MAX_BITSIZE_MODE_ANY_INT (128) | |
103 | ||
49e76be8 PB |
104 | /* The symbol Pmode stands for one of the above machine modes (usually SImode). |
105 | The tm.h file specifies which one. It is not a distinct mode. */ |