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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
66647d44 | 3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
2f83c7d6 | 4 | Free Software Foundation, Inc. |
c98f8742 | 5 | |
188fc5b5 | 6 | This file is part of GCC. |
c98f8742 | 7 | |
188fc5b5 | 8 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
11 | any later version. |
12 | ||
188fc5b5 | 13 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c98f8742 | 21 | |
ccf8e764 RH |
22 | /* The purpose of this file is to define the characteristics of the i386, |
23 | independent of assembler syntax or operating system. | |
24 | ||
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
36 | ||
0a1c5e55 UB |
37 | /* Redefines for option macros. */ |
38 | ||
39 | #define TARGET_64BIT OPTION_ISA_64BIT | |
40 | #define TARGET_MMX OPTION_ISA_MMX | |
41 | #define TARGET_3DNOW OPTION_ISA_3DNOW | |
42 | #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A | |
43 | #define TARGET_SSE OPTION_ISA_SSE | |
44 | #define TARGET_SSE2 OPTION_ISA_SSE2 | |
45 | #define TARGET_SSE3 OPTION_ISA_SSE3 | |
46 | #define TARGET_SSSE3 OPTION_ISA_SSSE3 | |
47 | #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 | |
3b8dd071 | 48 | #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 |
95879c72 L |
49 | #define TARGET_AVX OPTION_ISA_AVX |
50 | #define TARGET_FMA OPTION_ISA_FMA | |
0a1c5e55 | 51 | #define TARGET_SSE4A OPTION_ISA_SSE4A |
04e1d06b MM |
52 | #define TARGET_SSE5 OPTION_ISA_SSE5 |
53 | #define TARGET_ROUND OPTION_ISA_ROUND | |
ab442df7 MM |
54 | #define TARGET_ABM OPTION_ISA_ABM |
55 | #define TARGET_POPCNT OPTION_ISA_POPCNT | |
56 | #define TARGET_SAHF OPTION_ISA_SAHF | |
57 | #define TARGET_AES OPTION_ISA_AES | |
58 | #define TARGET_PCLMUL OPTION_ISA_PCLMUL | |
59 | #define TARGET_CMPXCHG16B OPTION_ISA_CX16 | |
60 | ||
04e1d06b MM |
61 | |
62 | /* SSE5 and SSE4.1 define the same round instructions */ | |
63 | #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5) | |
64 | #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) | |
0a1c5e55 | 65 | |
26b5109f RS |
66 | #include "config/vxworks-dummy.h" |
67 | ||
8c996513 JH |
68 | /* Algorithm to expand string function with. */ |
69 | enum stringop_alg | |
70 | { | |
71 | no_stringop, | |
72 | libcall, | |
73 | rep_prefix_1_byte, | |
74 | rep_prefix_4_byte, | |
75 | rep_prefix_8_byte, | |
76 | loop_1_byte, | |
77 | loop, | |
78 | unrolled_loop | |
79 | }; | |
ccf8e764 | 80 | |
8c996513 | 81 | #define NAX_STRINGOP_ALGS 4 |
ccf8e764 | 82 | |
8c996513 JH |
83 | /* Specify what algorithm to use for stringops on known size. |
84 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
85 | known at compile time or estimated via feedback, the SIZE array | |
86 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 87 | means infinity). Corresponding ALG is used then. |
8c996513 | 88 | For example initializer: |
4f3f76e6 | 89 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 90 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 91 | be used otherwise. */ |
8c996513 JH |
92 | struct stringop_algs |
93 | { | |
94 | const enum stringop_alg unknown_size; | |
95 | const struct stringop_strategy { | |
96 | const int max; | |
97 | const enum stringop_alg alg; | |
98 | } size [NAX_STRINGOP_ALGS]; | |
99 | }; | |
100 | ||
d4ba09c0 SC |
101 | /* Define the specific costs for a given cpu */ |
102 | ||
103 | struct processor_costs { | |
8b60264b KG |
104 | const int add; /* cost of an add instruction */ |
105 | const int lea; /* cost of a lea instruction */ | |
106 | const int shift_var; /* variable shift costs */ | |
107 | const int shift_const; /* constant shift costs */ | |
f676971a | 108 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 109 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 110 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 111 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 112 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
113 | int movsx; /* The cost of movsx operation. */ |
114 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
115 | const int large_insn; /* insns larger than this cost more */ |
116 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 117 | memory-to-memory move insns. */ |
8b60264b KG |
118 | const int movzbl_load; /* cost of loading using movzbl */ |
119 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
120 | in QImode, HImode and SImode relative |
121 | to reg-reg move (2). */ | |
8b60264b | 122 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 123 | in QImode, HImode and SImode */ |
8b60264b KG |
124 | const int fp_move; /* cost of reg,reg fld/fst */ |
125 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 126 | in SFmode, DFmode and XFmode */ |
8b60264b | 127 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 128 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
129 | const int mmx_move; /* cost of moving MMX register. */ |
130 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 131 | in SImode and DImode */ |
8b60264b | 132 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 133 | in SImode and DImode */ |
8b60264b KG |
134 | const int sse_move; /* cost of moving SSE register. */ |
135 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 136 | in SImode, DImode and TImode*/ |
8b60264b | 137 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 138 | in SImode, DImode and TImode*/ |
8b60264b | 139 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 140 | integer and vice versa. */ |
46cb0441 ZD |
141 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
142 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
143 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
144 | const int simultaneous_prefetches; /* number of parallel prefetch | |
145 | operations. */ | |
4977bab6 | 146 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
147 | const int fadd; /* cost of FADD and FSUB instructions. */ |
148 | const int fmul; /* cost of FMUL instruction. */ | |
149 | const int fdiv; /* cost of FDIV instruction. */ | |
150 | const int fabs; /* cost of FABS instruction. */ | |
151 | const int fchs; /* cost of FCHS instruction. */ | |
152 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 JH |
153 | /* Specify what algorithm |
154 | to use for stringops on unknown size. */ | |
155 | struct stringop_algs memcpy[2], memset[2]; | |
e70444a8 HJ |
156 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
157 | load and store. */ | |
158 | const int scalar_load_cost; /* Cost of scalar load. */ | |
159 | const int scalar_store_cost; /* Cost of scalar store. */ | |
160 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
161 | load, store, vector-to-scalar and | |
162 | scalar-to-vector operation. */ | |
163 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
164 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 165 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
166 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
167 | const int vec_store_cost; /* Cost of vector store. */ | |
168 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
169 | cost model. */ | |
170 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
171 | vectorizer cost model. */ | |
d4ba09c0 SC |
172 | }; |
173 | ||
8b60264b | 174 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
175 | extern const struct processor_costs ix86_size_cost; |
176 | ||
177 | #define ix86_cur_cost() \ | |
178 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 179 | |
c98f8742 JVA |
180 | /* Macros used in the machine description to test the flags. */ |
181 | ||
ddd5a7c1 | 182 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 183 | |
35b528be | 184 | #ifndef TARGET_CPU_DEFAULT |
d326eaf0 | 185 | #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic |
10e9fecc | 186 | #endif |
35b528be | 187 | |
004d3859 GK |
188 | #ifndef TARGET_FPMATH_DEFAULT |
189 | #define TARGET_FPMATH_DEFAULT \ | |
190 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
191 | #endif | |
192 | ||
6ac49599 | 193 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
b08de47e | 194 | |
5791cc29 JT |
195 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
196 | compile-time constant. */ | |
197 | #ifdef IN_LIBGCC2 | |
6ac49599 | 198 | #undef TARGET_64BIT |
5791cc29 JT |
199 | #ifdef __x86_64__ |
200 | #define TARGET_64BIT 1 | |
201 | #else | |
202 | #define TARGET_64BIT 0 | |
203 | #endif | |
204 | #else | |
6ac49599 RS |
205 | #ifndef TARGET_BI_ARCH |
206 | #undef TARGET_64BIT | |
67adf6a9 | 207 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
208 | #define TARGET_64BIT 1 |
209 | #else | |
210 | #define TARGET_64BIT 0 | |
211 | #endif | |
212 | #endif | |
5791cc29 | 213 | #endif |
25f94bb5 | 214 | |
750054a2 CT |
215 | #define HAS_LONG_COND_BRANCH 1 |
216 | #define HAS_LONG_UNCOND_BRANCH 1 | |
217 | ||
9e555526 RH |
218 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
219 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
220 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
221 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 222 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
223 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
224 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
225 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
226 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 227 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 228 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
05f85dbb | 229 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d326eaf0 JH |
230 | #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) |
231 | #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
232 | #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
21efb4d4 | 233 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
a269a03c | 234 | |
80fd744f RH |
235 | /* Feature tests against the various tunings. */ |
236 | enum ix86_tune_indices { | |
237 | X86_TUNE_USE_LEAVE, | |
238 | X86_TUNE_PUSH_MEMORY, | |
239 | X86_TUNE_ZERO_EXTEND_WITH_AND, | |
80fd744f RH |
240 | X86_TUNE_UNROLL_STRLEN, |
241 | X86_TUNE_DEEP_BRANCH_PREDICTION, | |
242 | X86_TUNE_BRANCH_PREDICTION_HINTS, | |
243 | X86_TUNE_DOUBLE_WITH_ADD, | |
3c2d980c | 244 | X86_TUNE_USE_SAHF, |
80fd744f RH |
245 | X86_TUNE_MOVX, |
246 | X86_TUNE_PARTIAL_REG_STALL, | |
247 | X86_TUNE_PARTIAL_FLAG_REG_STALL, | |
248 | X86_TUNE_USE_HIMODE_FIOP, | |
249 | X86_TUNE_USE_SIMODE_FIOP, | |
250 | X86_TUNE_USE_MOV0, | |
251 | X86_TUNE_USE_CLTD, | |
252 | X86_TUNE_USE_XCHGB, | |
253 | X86_TUNE_SPLIT_LONG_MOVES, | |
254 | X86_TUNE_READ_MODIFY_WRITE, | |
255 | X86_TUNE_READ_MODIFY, | |
256 | X86_TUNE_PROMOTE_QIMODE, | |
257 | X86_TUNE_FAST_PREFIX, | |
258 | X86_TUNE_SINGLE_STRINGOP, | |
259 | X86_TUNE_QIMODE_MATH, | |
260 | X86_TUNE_HIMODE_MATH, | |
261 | X86_TUNE_PROMOTE_QI_REGS, | |
262 | X86_TUNE_PROMOTE_HI_REGS, | |
263 | X86_TUNE_ADD_ESP_4, | |
264 | X86_TUNE_ADD_ESP_8, | |
265 | X86_TUNE_SUB_ESP_4, | |
266 | X86_TUNE_SUB_ESP_8, | |
267 | X86_TUNE_INTEGER_DFMODE_MOVES, | |
268 | X86_TUNE_PARTIAL_REG_DEPENDENCY, | |
269 | X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, | |
270 | X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, | |
271 | X86_TUNE_SSE_SPLIT_REGS, | |
272 | X86_TUNE_SSE_TYPELESS_STORES, | |
273 | X86_TUNE_SSE_LOAD0_BY_PXOR, | |
274 | X86_TUNE_MEMORY_MISMATCH_STALL, | |
275 | X86_TUNE_PROLOGUE_USING_MOVE, | |
276 | X86_TUNE_EPILOGUE_USING_MOVE, | |
277 | X86_TUNE_SHIFT1, | |
278 | X86_TUNE_USE_FFREEP, | |
279 | X86_TUNE_INTER_UNIT_MOVES, | |
630ecd8d | 280 | X86_TUNE_INTER_UNIT_CONVERSIONS, |
80fd744f RH |
281 | X86_TUNE_FOUR_JUMP_LIMIT, |
282 | X86_TUNE_SCHEDULE, | |
283 | X86_TUNE_USE_BT, | |
284 | X86_TUNE_USE_INCDEC, | |
285 | X86_TUNE_PAD_RETURNS, | |
286 | X86_TUNE_EXT_80387_CONSTANTS, | |
ddff69b9 MM |
287 | X86_TUNE_SHORTEN_X87_SSE, |
288 | X86_TUNE_AVOID_VECTOR_DECODE, | |
a646aded | 289 | X86_TUNE_PROMOTE_HIMODE_IMUL, |
ddff69b9 MM |
290 | X86_TUNE_SLOW_IMUL_IMM32_MEM, |
291 | X86_TUNE_SLOW_IMUL_IMM8, | |
292 | X86_TUNE_MOVE_M1_VIA_OR, | |
293 | X86_TUNE_NOT_UNPAIRABLE, | |
294 | X86_TUNE_NOT_VECTORMODE, | |
54723b46 | 295 | X86_TUNE_USE_VECTOR_FP_CONVERTS, |
4e9d897d | 296 | X86_TUNE_USE_VECTOR_CONVERTS, |
354f84af | 297 | X86_TUNE_FUSE_CMP_AND_BRANCH, |
80fd744f RH |
298 | |
299 | X86_TUNE_LAST | |
300 | }; | |
301 | ||
ab442df7 | 302 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
303 | |
304 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
305 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
306 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
307 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f RH |
308 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
309 | #define TARGET_DEEP_BRANCH_PREDICTION \ | |
310 | ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] | |
311 | #define TARGET_BRANCH_PREDICTION_HINTS \ | |
312 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
313 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
314 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
315 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
316 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
317 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
318 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
319 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] | |
320 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
321 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
322 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
323 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
324 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
325 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
326 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
327 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
328 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
329 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
330 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] | |
331 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
332 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
333 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
334 | #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] | |
335 | #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] | |
336 | #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] | |
337 | #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] | |
338 | #define TARGET_INTEGER_DFMODE_MOVES \ | |
339 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
340 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
341 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
342 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
343 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
344 | #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ | |
345 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] | |
346 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] | |
347 | #define TARGET_SSE_TYPELESS_STORES \ | |
348 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
349 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
350 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
351 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
352 | #define TARGET_PROLOGUE_USING_MOVE \ | |
353 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
354 | #define TARGET_EPILOGUE_USING_MOVE \ | |
355 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
356 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
357 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
358 | #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] | |
630ecd8d JH |
359 | #define TARGET_INTER_UNIT_CONVERSIONS\ |
360 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] | |
80fd744f RH |
361 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
362 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
363 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
364 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
365 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
366 | #define TARGET_EXT_80387_CONSTANTS \ | |
367 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
368 | #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] |
369 | #define TARGET_AVOID_VECTOR_DECODE \ | |
370 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
371 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
372 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
373 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
374 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
375 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
376 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
377 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
378 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
379 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
380 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
381 | #define TARGET_USE_VECTOR_CONVERTS \ |
382 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
383 | #define TARGET_FUSE_CMP_AND_BRANCH \ | |
384 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] | |
80fd744f RH |
385 | |
386 | /* Feature tests against the various architecture variations. */ | |
387 | enum ix86_arch_indices { | |
388 | X86_ARCH_CMOVE, /* || TARGET_SSE */ | |
389 | X86_ARCH_CMPXCHG, | |
390 | X86_ARCH_CMPXCHG8B, | |
391 | X86_ARCH_XADD, | |
392 | X86_ARCH_BSWAP, | |
393 | ||
394 | X86_ARCH_LAST | |
395 | }; | |
4f3f76e6 | 396 | |
ab442df7 | 397 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f RH |
398 | |
399 | #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] | |
400 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] | |
401 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
402 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
403 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
404 | ||
405 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) | |
406 | ||
407 | extern int x86_prefetch_sse; | |
0a1c5e55 | 408 | |
80fd744f RH |
409 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
410 | ||
80fd744f RH |
411 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
412 | ||
413 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
414 | #define TARGET_MIX_SSE_I387 \ | |
415 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
416 | ||
417 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
418 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
419 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
420 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
1ef45b77 | 421 | |
0a1c5e55 UB |
422 | extern int ix86_isa_flags; |
423 | ||
67adf6a9 RH |
424 | #ifndef TARGET_64BIT_DEFAULT |
425 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 426 | #endif |
74dc3e94 RH |
427 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
428 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
429 | #endif | |
25f94bb5 | 430 | |
79f5e442 ZD |
431 | /* Fence to use after loop using storent. */ |
432 | ||
433 | extern tree x86_mfence; | |
434 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
435 | ||
0ed4a390 JL |
436 | /* Once GDB has been enhanced to deal with functions without frame |
437 | pointers, we can change this to allow for elimination of | |
438 | the frame pointer in leaf functions. */ | |
439 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 440 | |
0a1c5e55 UB |
441 | /* Extra bits to force. */ |
442 | #define TARGET_SUBTARGET_DEFAULT 0 | |
443 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
444 | ||
445 | /* Extra bits to force on w/ 32-bit mode. */ | |
446 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
447 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
448 | ||
ccf8e764 RH |
449 | /* Extra bits to force on w/ 64-bit mode. */ |
450 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 451 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 452 | |
b069de3b SS |
453 | /* This is not really a target flag, but is done this way so that |
454 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
455 | redefines this to 1. */ | |
456 | #define TARGET_MACHO 0 | |
457 | ||
ccf8e764 | 458 | /* Likewise, for the Windows 64-bit ABI. */ |
7c800926 KT |
459 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
460 | ||
461 | /* Available call abi. */ | |
35cbb299 | 462 | enum calling_abi |
7c800926 KT |
463 | { |
464 | SYSV_ABI = 0, | |
465 | MS_ABI = 1 | |
466 | }; | |
467 | ||
51212b32 L |
468 | /* The abi used by target. */ |
469 | extern enum calling_abi ix86_abi; | |
470 | ||
471 | /* The default abi used by target. */ | |
7c800926 | 472 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 473 | |
cc69336f RH |
474 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
475 | with the rounding mode forced to 53 bits. */ | |
476 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
477 | ||
f5316dfe MM |
478 | /* Sometimes certain combinations of command options do not make |
479 | sense on a particular target machine. You can define a macro | |
480 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
481 | defined, is executed once just after all the command options have | |
482 | been parsed. | |
483 | ||
484 | Don't use this macro to turn on various extra optimizations for | |
485 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
486 | ||
ab442df7 | 487 | #define OVERRIDE_OPTIONS override_options (true) |
f5316dfe | 488 | |
d4ba09c0 | 489 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
490 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
491 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 492 | |
682cd442 GK |
493 | /* -march=native handling only makes sense with compiler running on |
494 | an x86 or x86_64 chip. If changing this condition, also change | |
495 | the condition in driver-i386.c. */ | |
496 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
497 | /* In driver-i386.c. */ |
498 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
499 | #define EXTRA_SPEC_FUNCTIONS \ | |
500 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 501 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
502 | #endif |
503 | ||
8981c15b JM |
504 | #if TARGET_64BIT_DEFAULT |
505 | #define OPT_ARCH64 "!m32" | |
506 | #define OPT_ARCH32 "m32" | |
507 | #else | |
508 | #define OPT_ARCH64 "m64" | |
509 | #define OPT_ARCH32 "!m64" | |
510 | #endif | |
511 | ||
1cba2b96 EC |
512 | /* Support for configure-time defaults of some command line options. |
513 | The order here is important so that -march doesn't squash the | |
514 | tune or cpu values. */ | |
ce998900 | 515 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 516 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
517 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
518 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 519 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
520 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
521 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
522 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
523 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
524 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 525 | |
241e1a89 SC |
526 | /* Specs for the compiler proper */ |
527 | ||
628714d8 | 528 | #ifndef CC1_CPU_SPEC |
fa959ce4 | 529 | #define CC1_CPU_SPEC_1 "\ |
9d913bbf | 530 | %{mcpu=*:-mtune=%* \ |
d347d4c7 | 531 | %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ |
9d913bbf | 532 | %<mcpu=* \ |
c93e80a5 JH |
533 | %{mintel-syntax:-masm=intel \ |
534 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
535 | %{mno-intel-syntax:-masm=att \ | |
536 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
fa959ce4 | 537 | |
682cd442 | 538 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
539 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
540 | #else | |
541 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
edccdcb1 L |
542 | "%{march=native:%<march=native %:local_cpu_detect(arch) \ |
543 | %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ | |
fa959ce4 MM |
544 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" |
545 | #endif | |
241e1a89 | 546 | #endif |
c98f8742 | 547 | \f |
30efe578 | 548 | /* Target CPU builtins. */ |
ab442df7 MM |
549 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
550 | ||
551 | /* Target Pragmas. */ | |
552 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 553 | |
c2f17e19 UB |
554 | enum target_cpu_default |
555 | { | |
556 | TARGET_CPU_DEFAULT_generic = 0, | |
557 | ||
558 | TARGET_CPU_DEFAULT_i386, | |
559 | TARGET_CPU_DEFAULT_i486, | |
560 | TARGET_CPU_DEFAULT_pentium, | |
561 | TARGET_CPU_DEFAULT_pentium_mmx, | |
562 | TARGET_CPU_DEFAULT_pentiumpro, | |
563 | TARGET_CPU_DEFAULT_pentium2, | |
564 | TARGET_CPU_DEFAULT_pentium3, | |
565 | TARGET_CPU_DEFAULT_pentium4, | |
566 | TARGET_CPU_DEFAULT_pentium_m, | |
567 | TARGET_CPU_DEFAULT_prescott, | |
568 | TARGET_CPU_DEFAULT_nocona, | |
569 | TARGET_CPU_DEFAULT_core2, | |
570 | ||
571 | TARGET_CPU_DEFAULT_geode, | |
572 | TARGET_CPU_DEFAULT_k6, | |
573 | TARGET_CPU_DEFAULT_k6_2, | |
574 | TARGET_CPU_DEFAULT_k6_3, | |
575 | TARGET_CPU_DEFAULT_athlon, | |
576 | TARGET_CPU_DEFAULT_athlon_sse, | |
577 | TARGET_CPU_DEFAULT_k8, | |
578 | TARGET_CPU_DEFAULT_amdfam10, | |
579 | ||
580 | TARGET_CPU_DEFAULT_max | |
581 | }; | |
0c2dc519 | 582 | |
628714d8 | 583 | #ifndef CC1_SPEC |
8015b78d | 584 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
585 | #endif |
586 | ||
587 | /* This macro defines names of additional specifications to put in the | |
588 | specs that can be used in various specifications like CC1_SPEC. Its | |
589 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
590 | |
591 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 592 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
593 | program. |
594 | ||
595 | Do not define this macro if it does not need to do anything. */ | |
596 | ||
597 | #ifndef SUBTARGET_EXTRA_SPECS | |
598 | #define SUBTARGET_EXTRA_SPECS | |
599 | #endif | |
600 | ||
601 | #define EXTRA_SPECS \ | |
628714d8 | 602 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
603 | SUBTARGET_EXTRA_SPECS |
604 | \f | |
ce998900 | 605 | |
d57a4b98 RH |
606 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
607 | FPU, assume that the fpcw is set to extended precision; when using | |
608 | only SSE, rounding is correct; when using both SSE and the FPU, | |
609 | the rounding precision is indeterminate, since either may be chosen | |
610 | apparently at random. */ | |
611 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 612 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 613 | |
979c67a5 UB |
614 | /* target machine storage layout */ |
615 | ||
65d9c0ab JH |
616 | #define SHORT_TYPE_SIZE 16 |
617 | #define INT_TYPE_SIZE 32 | |
618 | #define FLOAT_TYPE_SIZE 32 | |
619 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
65d9c0ab JH |
620 | #define DOUBLE_TYPE_SIZE 64 |
621 | #define LONG_LONG_TYPE_SIZE 64 | |
979c67a5 UB |
622 | #define LONG_DOUBLE_TYPE_SIZE 80 |
623 | ||
624 | #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE | |
65d9c0ab | 625 | |
67adf6a9 | 626 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 627 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
628 | #else |
629 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
630 | #endif |
631 | ||
c98f8742 JVA |
632 | /* Define this if most significant byte of a word is the lowest numbered. */ |
633 | /* That is true on the 80386. */ | |
634 | ||
635 | #define BITS_BIG_ENDIAN 0 | |
636 | ||
637 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
638 | /* That is not true on the 80386. */ | |
639 | #define BYTES_BIG_ENDIAN 0 | |
640 | ||
641 | /* Define this if most significant word of a multiword number is the lowest | |
642 | numbered. */ | |
643 | /* Not true for 80386 */ | |
644 | #define WORDS_BIG_ENDIAN 0 | |
645 | ||
c98f8742 | 646 | /* Width of a word, in units (bytes). */ |
4ae8027b | 647 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
2e64c636 JH |
648 | #ifdef IN_LIBGCC2 |
649 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
650 | #else | |
651 | #define MIN_UNITS_PER_WORD 4 | |
652 | #endif | |
c98f8742 | 653 | |
c98f8742 | 654 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 655 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 656 | |
e075ae69 | 657 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
4ae8027b | 658 | #define STACK_BOUNDARY \ |
51212b32 | 659 | (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 660 | |
2e3f842f L |
661 | /* Stack boundary of the main function guaranteed by OS. */ |
662 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
663 | ||
de1132d1 L |
664 | /* Minimum stack boundary. */ |
665 | #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
2e3f842f | 666 | |
d1f87653 | 667 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 668 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 669 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 670 | |
de1132d1 | 671 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
672 | both 32bit and 64bit, to support codes that need 128 bit stack |
673 | alignment for SSE instructions, but can't realign the stack. */ | |
674 | #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
675 | ||
676 | /* 1 if -mstackrealign should be turned on by default. It will | |
677 | generate an alternate prologue and epilogue that realigns the | |
678 | runtime stack if nessary. This supports mixing codes that keep a | |
679 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
680 | need a 16-byte aligned stack, as required by SSE instructions. If | |
681 | STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is | |
682 | 128, stacks for all functions may be realigned. */ | |
683 | #define STACK_REALIGN_DEFAULT 0 | |
684 | ||
685 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
686 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 687 | |
ebff937c SH |
688 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
689 | mandatory for the 64-bit ABI, and may or may not be true for other | |
690 | operating systems. */ | |
691 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
692 | ||
f963b5d9 RS |
693 | /* Minimum allocation boundary for the code of a function. */ |
694 | #define FUNCTION_BOUNDARY 8 | |
695 | ||
696 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
697 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 698 | |
892a2d68 | 699 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 700 | |
65d9c0ab | 701 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
702 | |
703 | /* Minimum size in bits of the largest boundary to which any | |
704 | and all fundamental data types supported by the hardware | |
705 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 706 | rounder than this. |
fce5a9f2 | 707 | |
d1f87653 | 708 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
709 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
710 | ||
95879c72 | 711 | #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128) |
17f24ff0 | 712 | |
2e3f842f L |
713 | /* Maximum stack alignment. */ |
714 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
715 | ||
6e4f1168 L |
716 | /* Alignment value for attribute ((aligned)). It is a constant since |
717 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
718 | #define ATTRIBUTE_ALIGNED_VALUE 128 | |
719 | ||
822eda12 | 720 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 721 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 722 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 723 | |
17f24ff0 | 724 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 725 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 726 | -malign-double is set. */ |
e932b21b | 727 | |
e83f3cff RH |
728 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
729 | supports no vector modes, cut out the complexity and fall back | |
730 | on BIGGEST_FIELD_ALIGNMENT. */ | |
731 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
732 | #ifdef __x86_64__ |
733 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
734 | #else | |
e83f3cff | 735 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 736 | #endif |
e83f3cff | 737 | #else |
e932b21b JH |
738 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
739 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 740 | #endif |
c98f8742 | 741 | |
e5e8a8bf | 742 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 743 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
744 | and ALIGN is the alignment that the object would ordinarily have. |
745 | The value of this macro is used instead of that alignment to align | |
746 | the object. | |
747 | ||
748 | If this macro is not defined, then ALIGN is used. | |
749 | ||
750 | The typical use of this macro is to increase alignment for string | |
751 | constants to be word aligned so that `strcpy' calls that copy | |
752 | constants can be done inline. */ | |
753 | ||
d9a5f180 | 754 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 755 | |
8a022443 JW |
756 | /* If defined, a C expression to compute the alignment for a static |
757 | variable. TYPE is the data type, and ALIGN is the alignment that | |
758 | the object would ordinarily have. The value of this macro is used | |
759 | instead of that alignment to align the object. | |
760 | ||
761 | If this macro is not defined, then ALIGN is used. | |
762 | ||
763 | One use of this macro is to increase alignment of medium-size | |
764 | data to make it all fit in fewer cache lines. Another is to | |
765 | cause character arrays to be word-aligned so that `strcpy' calls | |
766 | that copy constants to character arrays can be done inline. */ | |
767 | ||
d9a5f180 | 768 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
769 | |
770 | /* If defined, a C expression to compute the alignment for a local | |
771 | variable. TYPE is the data type, and ALIGN is the alignment that | |
772 | the object would ordinarily have. The value of this macro is used | |
773 | instead of that alignment to align the object. | |
774 | ||
775 | If this macro is not defined, then ALIGN is used. | |
776 | ||
777 | One use of this macro is to increase alignment of medium-size | |
778 | data to make it all fit in fewer cache lines. */ | |
779 | ||
76fe54f0 L |
780 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
781 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
782 | ||
783 | /* If defined, a C expression to compute the alignment for stack slot. | |
784 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
785 | is the alignment that the slot would ordinarily have. The value of | |
786 | this macro is used instead of that alignment to align the slot. | |
787 | ||
788 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
789 | Otherwise, LOCAL_ALIGNMENT will be used. | |
790 | ||
791 | One use of this macro is to set alignment of stack slot to the | |
792 | maximum alignment of all possible modes which the slot may have. */ | |
793 | ||
794 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
795 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 796 | |
9bfaf89d JJ |
797 | /* If defined, a C expression to compute the alignment for a local |
798 | variable DECL. | |
799 | ||
800 | If this macro is not defined, then | |
801 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
802 | ||
803 | One use of this macro is to increase alignment of medium-size | |
804 | data to make it all fit in fewer cache lines. */ | |
805 | ||
806 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
807 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
808 | ||
809 | ||
53c17031 JH |
810 | /* If defined, a C expression that gives the alignment boundary, in |
811 | bits, of an argument with the specified mode and type. If it is | |
812 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
813 | ||
d9a5f180 GS |
814 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
815 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 816 | |
9cd10576 | 817 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 818 | when given unaligned data. */ |
b4ac57ab | 819 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
820 | |
821 | /* If bit field type is int, don't let it cross an int, | |
822 | and give entire struct the alignment of an int. */ | |
43a88a8c | 823 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 824 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
825 | \f |
826 | /* Standard register usage. */ | |
827 | ||
828 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 829 | for details. */ |
c98f8742 JVA |
830 | |
831 | #define STACK_REGS | |
ce998900 | 832 | |
d9a5f180 | 833 | #define IS_STACK_MODE(MODE) \ |
b5c82fa1 PB |
834 | (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ |
835 | || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
836 | || (MODE) == XFmode) | |
c98f8742 JVA |
837 | |
838 | /* Number of actual hardware registers. | |
839 | The hardware registers are assigned numbers for the compiler | |
840 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
841 | All registers that the compiler knows about must be given numbers, | |
842 | even those that are not normally considered general registers. | |
843 | ||
844 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
845 | We number the floating point registers 8-15. | |
846 | Note that registers 0-7 can be accessed as a short or int, | |
847 | while only 0-3 may be used with byte `mov' instructions. | |
848 | ||
849 | Reg 16 does not correspond to any hardware register, but instead | |
850 | appears in the RTL as an argument pointer prior to reload, and is | |
851 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 852 | pointer. */ |
c98f8742 | 853 | |
b0d95de8 | 854 | #define FIRST_PSEUDO_REGISTER 53 |
c98f8742 | 855 | |
3073d01c ML |
856 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
857 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
858 | ||
859 | #define DWARF_FRAME_REGISTERS 17 | |
860 | ||
c98f8742 JVA |
861 | /* 1 for registers that have pervasive standard uses |
862 | and are not available for the register allocator. | |
3f3f2124 | 863 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 864 | |
3a4416fb RS |
865 | The value is zero if the register is not fixed on either 32 or |
866 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
867 | bit targets, two if it is only fixed on 32bit targets and three | |
868 | if its only fixed on 64bit targets. | |
869 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
3f3f2124 | 870 | */ |
a7180f70 BS |
871 | #define FIXED_REGISTERS \ |
872 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 873 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
874 | /*arg,flags,fpsr,fpcr,frame*/ \ |
875 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
876 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
877 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 878 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
879 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
880 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
3a4416fb | 881 | 2, 2, 2, 2, 2, 2, 2, 2, \ |
3f3f2124 | 882 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
ce998900 | 883 | 2, 2, 2, 2, 2, 2, 2, 2 } |
fce5a9f2 | 884 | |
c98f8742 JVA |
885 | |
886 | /* 1 for registers not available across function calls. | |
887 | These must include the FIXED_REGISTERS and also any | |
888 | registers that can be used without being saved. | |
889 | The latter must include the registers where values are returned | |
890 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
891 | Aside from that, you can include as many other registers as you like. |
892 | ||
9d72d996 JJ |
893 | The value is zero if the register is not call used on either 32 or |
894 | 64 bit targets, one if the register if call used on both 32 and 64 | |
895 | bit targets, two if it is only call used on 32bit targets and three | |
896 | if its only call used on 64bit targets. | |
3a4416fb | 897 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. |
3f3f2124 | 898 | */ |
a7180f70 BS |
899 | #define CALL_USED_REGISTERS \ |
900 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 901 | { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
902 | /*arg,flags,fpsr,fpcr,frame*/ \ |
903 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 904 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
03c259ad | 905 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
78168632 | 906 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 907 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 908 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 909 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 910 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
ce998900 | 911 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 912 | |
3b3c6a3f MM |
913 | /* Order in which to allocate registers. Each register must be |
914 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
915 | late and fixed registers last. Note that, in general, we prefer | |
916 | registers listed in CALL_USED_REGISTERS, keeping the others | |
917 | available for storage of persistent values. | |
918 | ||
162f023b JH |
919 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
920 | so this is just empty initializer for array. */ | |
3b3c6a3f | 921 | |
162f023b JH |
922 | #define REG_ALLOC_ORDER \ |
923 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
924 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
925 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
b0d95de8 | 926 | 48, 49, 50, 51, 52 } |
3b3c6a3f | 927 | |
162f023b JH |
928 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
929 | to be rearranged based on a particular function. When using sse math, | |
03c259ad | 930 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 931 | |
162f023b | 932 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 933 | |
f5316dfe | 934 | |
7c800926 KT |
935 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
936 | ||
c98f8742 | 937 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 938 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 939 | do { \ |
3f3f2124 | 940 | int i; \ |
b0fede98 | 941 | unsigned int j; \ |
3f3f2124 JH |
942 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
943 | { \ | |
3a4416fb RS |
944 | if (fixed_regs[i] > 1) \ |
945 | fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ | |
946 | if (call_used_regs[i] > 1) \ | |
947 | call_used_regs[i] = (call_used_regs[i] \ | |
948 | == (TARGET_64BIT ? 3 : 2)); \ | |
3f3f2124 | 949 | } \ |
b0fede98 | 950 | j = PIC_OFFSET_TABLE_REGNUM; \ |
7706ca5d | 951 | if (j != INVALID_REGNUM) \ |
962aae34 | 952 | fixed_regs[j] = call_used_regs[j] = 1; \ |
0705d3f4 | 953 | if (TARGET_64BIT \ |
6b5629db | 954 | && ((cfun && cfun->machine->call_abi == MS_ABI) \ |
51212b32 | 955 | || (!cfun && ix86_abi == MS_ABI))) \ |
0705d3f4 | 956 | { \ |
6c6094f1 UB |
957 | call_used_regs[SI_REG] = 0; \ |
958 | call_used_regs[DI_REG] = 0; \ | |
959 | call_used_regs[XMM6_REG] = 0; \ | |
960 | call_used_regs[XMM7_REG] = 0; \ | |
434426d2 UB |
961 | for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ |
962 | call_used_regs[i] = 0; \ | |
0705d3f4 | 963 | } \ |
a7180f70 | 964 | if (! TARGET_MMX) \ |
6b5629db UB |
965 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
966 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
967 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ | |
a7180f70 | 968 | if (! TARGET_SSE) \ |
6b5629db UB |
969 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
970 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
971 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ | |
972 | if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387)) \ | |
962aae34 UB |
973 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
974 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i)) \ | |
975 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ | |
33270999 AO |
976 | if (! TARGET_64BIT) \ |
977 | { \ | |
33270999 AO |
978 | for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ |
979 | reg_names[i] = ""; \ | |
980 | for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ | |
981 | reg_names[i] = ""; \ | |
a7180f70 | 982 | } \ |
d9a5f180 | 983 | } while (0) |
c98f8742 JVA |
984 | |
985 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
986 | to hold something of mode MODE. | |
987 | This is ordinarily the length in words of a value of mode MODE | |
988 | but can be less for certain modes in special long registers. | |
989 | ||
fce5a9f2 | 990 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
991 | registers. And only registers 0-3 may have mov byte instructions |
992 | applied to them. | |
993 | */ | |
994 | ||
ce998900 | 995 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
92d0fb09 JH |
996 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
997 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 | 998 | : ((MODE) == XFmode \ |
92d0fb09 | 999 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1000 | : (MODE) == XCmode \ |
92d0fb09 | 1001 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1002 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1003 | |
8521c414 JM |
1004 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
1005 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
1006 | ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
1007 | ? 0 \ | |
1008 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
1009 | : 0) | |
1010 | ||
1011 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1012 | ||
95879c72 L |
1013 | #define VALID_AVX256_REG_MODE(MODE) \ |
1014 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
1015 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) | |
1016 | ||
ce998900 UB |
1017 | #define VALID_SSE2_REG_MODE(MODE) \ |
1018 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1019 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1020 | |
d9a5f180 | 1021 | #define VALID_SSE_REG_MODE(MODE) \ |
ce998900 UB |
1022 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ |
1023 | || (MODE) == SFmode || (MODE) == TFmode) | |
a7180f70 | 1024 | |
47f339cf | 1025 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1026 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1027 | |
d9a5f180 | 1028 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1029 | ((MODE == V1DImode) || (MODE) == DImode \ |
1030 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1031 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1032 | |
accde4cf | 1033 | /* ??? No autovectorization into MMX or 3DNOW until we can reliably |
95879c72 L |
1034 | place emms and femms instructions. |
1035 | FIXME: AVX has 32byte floating point vector operations and 16byte | |
1036 | integer vector operations. But vectorizer doesn't support | |
1037 | different sizes for integer and floating point vectors. We limit | |
1038 | vector size to 16byte. */ | |
1039 | #define UNITS_PER_SIMD_WORD(MODE) \ | |
1040 | (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \ | |
1041 | : (TARGET_SSE ? 16 : UNITS_PER_WORD)) | |
0bf43309 | 1042 | |
ce998900 UB |
1043 | #define VALID_DFP_MODE_P(MODE) \ |
1044 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1045 | |
d9a5f180 | 1046 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1047 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1048 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1049 | |
d9a5f180 | 1050 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1051 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1052 | || (MODE) == DImode \ | |
1053 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1054 | || (MODE) == CDImode \ | |
1055 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1056 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1057 | |
822eda12 | 1058 | /* Return true for modes passed in SSE registers. */ |
ce998900 UB |
1059 | #define SSE_REG_MODE_P(MODE) \ |
1060 | ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ | |
822eda12 | 1061 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ |
95879c72 L |
1062 | || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \ |
1063 | || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \ | |
1064 | || (MODE) == V8SFmode || (MODE) == V4DFmode) | |
822eda12 | 1065 | |
e075ae69 | 1066 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1067 | |
a946dd00 | 1068 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1069 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1070 | |
1071 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1072 | when one has mode MODE1 and one has mode MODE2. | |
1073 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1074 | for any hard reg, then this must be 0 for correct output. */ | |
1075 | ||
c1c5b5e3 | 1076 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 1077 | |
ff25ef99 ZD |
1078 | /* It is possible to write patterns to move flags; but until someone |
1079 | does it, */ | |
1080 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1081 | |
e075ae69 | 1082 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1083 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1084 | |
787dc842 JH |
1085 | Kill any attempts to combine saving of modes. */ |
1086 | ||
d9a5f180 GS |
1087 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1088 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1089 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1090 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
d9a5f180 | 1091 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ |
6c6094f1 | 1092 | : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ |
d2836273 | 1093 | : (MODE)) |
ce998900 | 1094 | |
c98f8742 JVA |
1095 | /* Specify the registers used for certain standard purposes. |
1096 | The values of these macros are register numbers. */ | |
1097 | ||
1098 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1099 | register. The ordinary mov instructions won't work */ | |
1100 | /* #define PC_REGNUM */ | |
1101 | ||
1102 | /* Register to use for pushing function arguments. */ | |
1103 | #define STACK_POINTER_REGNUM 7 | |
1104 | ||
1105 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1106 | #define HARD_FRAME_POINTER_REGNUM 6 |
1107 | ||
1108 | /* Base register for access to local variables of the function. */ | |
b0d95de8 | 1109 | #define FRAME_POINTER_REGNUM 20 |
c98f8742 JVA |
1110 | |
1111 | /* First floating point reg */ | |
1112 | #define FIRST_FLOAT_REG 8 | |
1113 | ||
1114 | /* First & last stack-like regs */ | |
1115 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1116 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1117 | ||
a7180f70 BS |
1118 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1119 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1120 | |
a7180f70 BS |
1121 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1122 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1123 | ||
3f3f2124 JH |
1124 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1125 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1126 | ||
1127 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1128 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1129 | ||
c98f8742 JVA |
1130 | /* Value should be nonzero if functions must have frame pointers. |
1131 | Zero means the frame pointer need not be set up (and parms | |
1132 | may be accessed via the stack pointer) in functions that seem suitable. | |
1133 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
1134 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1135 | ||
aabcd309 | 1136 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1137 | requiring a frame pointer. */ |
1138 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1139 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1140 | #endif | |
1141 | ||
1142 | /* Make sure we can access arbitrary call frames. */ | |
1143 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1144 | |
1145 | /* Base register for access to arguments of the function. */ | |
1146 | #define ARG_POINTER_REGNUM 16 | |
1147 | ||
d2836273 JH |
1148 | /* Register in which static-chain is passed to a function. |
1149 | We do use ECX as static chain register for 32 bit ABI. On the | |
1150 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
2ff8644d | 1151 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG) |
c98f8742 JVA |
1152 | |
1153 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1154 | code access to data items. We don't use PIC pointer for 64bit |
1155 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1156 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1157 | |
1158 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1159 | the pic register when possible. The change is visible after the | |
1160 | prologue has been emitted. */ | |
1161 | ||
2e3f842f | 1162 | #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG |
bd09bdeb RH |
1163 | |
1164 | #define PIC_OFFSET_TABLE_REGNUM \ | |
7dcbf659 JH |
1165 | ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ |
1166 | || !flag_pic ? INVALID_REGNUM \ | |
bd09bdeb RH |
1167 | : reload_completed ? REGNO (pic_offset_table_rtx) \ |
1168 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1169 | |
5fc0e5df KW |
1170 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1171 | ||
c51e6d85 | 1172 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1173 | #define MS_AGGREGATE_RETURN 0 |
1174 | ||
61fec9ff JB |
1175 | /* This is overridden by <netware.h>. */ |
1176 | #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
c98f8742 JVA |
1177 | \f |
1178 | /* Define the classes of registers for register constraints in the | |
1179 | machine description. Also define ranges of constants. | |
1180 | ||
1181 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1182 | If there is more than one class, another class must be named NO_REGS | |
1183 | and contain no registers. | |
1184 | ||
1185 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1186 | another name such as ALL_REGS). This is the class of registers | |
1187 | that is allowed by "g" or "r" in a register constraint. | |
1188 | Also, registers outside this class are allocated only when | |
1189 | instructions express preferences for them. | |
1190 | ||
1191 | The classes must be numbered in nondecreasing order; that is, | |
1192 | a larger-numbered class must never be contained completely | |
1193 | in a smaller-numbered class. | |
1194 | ||
1195 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1196 | class that represents their union. |
1197 | ||
1198 | It might seem that class BREG is unnecessary, since no useful 386 | |
1199 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1200 | and the "b" register constraint is useful in asms for syscalls. |
1201 | ||
03c259ad | 1202 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1203 | |
1204 | enum reg_class | |
1205 | { | |
1206 | NO_REGS, | |
e075ae69 | 1207 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1208 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1209 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1210 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1211 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1212 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1213 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1214 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1215 | FLOAT_REGS, | |
06f4e35d | 1216 | SSE_FIRST_REG, |
a7180f70 BS |
1217 | SSE_REGS, |
1218 | MMX_REGS, | |
446988df JH |
1219 | FP_TOP_SSE_REGS, |
1220 | FP_SECOND_SSE_REGS, | |
1221 | FLOAT_SSE_REGS, | |
1222 | FLOAT_INT_REGS, | |
1223 | INT_SSE_REGS, | |
1224 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1225 | ALL_REGS, LIM_REG_CLASSES |
1226 | }; | |
1227 | ||
d9a5f180 GS |
1228 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1229 | ||
1230 | #define INTEGER_CLASS_P(CLASS) \ | |
1231 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1232 | #define FLOAT_CLASS_P(CLASS) \ | |
1233 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1234 | #define SSE_CLASS_P(CLASS) \ | |
06f4e35d | 1235 | reg_class_subset_p ((CLASS), SSE_REGS) |
d9a5f180 | 1236 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1237 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1238 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1239 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1240 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1241 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1242 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1243 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1244 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1245 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1246 | ||
1247 | #define Q_CLASS_P(CLASS) \ | |
1248 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1249 | |
43f3a59d | 1250 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1251 | |
1252 | #define REG_CLASS_NAMES \ | |
1253 | { "NO_REGS", \ | |
ab408a86 | 1254 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1255 | "SIREG", "DIREG", \ |
e075ae69 RH |
1256 | "AD_REGS", \ |
1257 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1258 | "INDEX_REGS", \ |
3f3f2124 | 1259 | "LEGACY_REGS", \ |
c98f8742 JVA |
1260 | "GENERAL_REGS", \ |
1261 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1262 | "FLOAT_REGS", \ | |
cb482895 | 1263 | "SSE_FIRST_REG", \ |
a7180f70 BS |
1264 | "SSE_REGS", \ |
1265 | "MMX_REGS", \ | |
446988df JH |
1266 | "FP_TOP_SSE_REGS", \ |
1267 | "FP_SECOND_SSE_REGS", \ | |
1268 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1269 | "FLOAT_INT_REGS", \ |
446988df JH |
1270 | "INT_SSE_REGS", \ |
1271 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1272 | "ALL_REGS" } |
1273 | ||
1274 | /* Define which registers fit in which classes. | |
1275 | This is an initializer for a vector of HARD_REG_SET | |
1276 | of length N_REG_CLASSES. */ | |
1277 | ||
a7180f70 | 1278 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1279 | { { 0x00, 0x0 }, \ |
1280 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1281 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1282 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1283 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1284 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
b0d95de8 UB |
1285 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ |
1286 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1287 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1288 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
3f3f2124 JH |
1289 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ |
1290 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
cb482895 | 1291 | { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ |
b0d95de8 UB |
1292 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ |
1293 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1294 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1295 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1296 | { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \ | |
1297 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1298 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1299 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1300 | { 0xffffffff,0x1fffff } \ | |
e075ae69 | 1301 | } |
c98f8742 | 1302 | |
058e97ec VM |
1303 | /* The following macro defines cover classes for Integrated Register |
1304 | Allocator. Cover classes is a set of non-intersected register | |
1305 | classes covering all hard registers used for register allocation | |
1306 | purpose. Any move between two registers of a cover class should be | |
1307 | cheaper than load or store of the registers. The macro value is | |
1308 | array of register classes with LIM_REG_CLASSES used as the end | |
1309 | marker. */ | |
1310 | ||
1311 | #define IRA_COVER_CLASSES \ | |
1312 | { \ | |
1313 | GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \ | |
1314 | } | |
1315 | ||
c98f8742 JVA |
1316 | /* The same information, inverted: |
1317 | Return the class number of the smallest class containing | |
1318 | reg number REGNO. This could be a conditional expression | |
1319 | or could index an array. */ | |
1320 | ||
c98f8742 JVA |
1321 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1322 | ||
1323 | /* When defined, the compiler allows registers explicitly used in the | |
1324 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1325 | extending the lifetime of these registers. */ |
c98f8742 | 1326 | |
2922fe9e | 1327 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 | 1328 | |
6c6094f1 | 1329 | #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) |
3f3f2124 | 1330 | |
d9a5f180 | 1331 | #define GENERAL_REGNO_P(N) \ |
fb84c7a0 | 1332 | ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) |
3f3f2124 JH |
1333 | |
1334 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1335 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1336 | |
1337 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1338 | ||
fb84c7a0 UB |
1339 | #define REX_INT_REGNO_P(N) \ |
1340 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 JH |
1341 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1342 | ||
c98f8742 | 1343 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
fb84c7a0 | 1344 | #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
446988df | 1345 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1346 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1347 | |
54a88090 | 1348 | #define X87_FLOAT_MODE_P(MODE) \ |
27ac40e2 | 1349 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) |
54a88090 | 1350 | |
fb84c7a0 UB |
1351 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) |
1352 | #define SSE_REGNO_P(N) \ | |
1353 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
1354 | || REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1355 | |
4977bab6 | 1356 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1357 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1358 | |
d9a5f180 GS |
1359 | #define SSE_REGNO(N) \ |
1360 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
446988df | 1361 | |
d9a5f180 | 1362 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1363 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1364 | |
d6023b50 UB |
1365 | #define SSE_VEC_FLOAT_MODE_P(MODE) \ |
1366 | ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) | |
1367 | ||
95879c72 L |
1368 | #define AVX_FLOAT_MODE_P(MODE) \ |
1369 | (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode)) | |
1370 | ||
1371 | #define AVX128_VEC_FLOAT_MODE_P(MODE) \ | |
1372 | (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode)) | |
1373 | ||
1374 | #define AVX256_VEC_FLOAT_MODE_P(MODE) \ | |
1375 | (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1376 | ||
1377 | #define AVX_VEC_FLOAT_MODE_P(MODE) \ | |
1378 | (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1379 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1380 | ||
d9a5f180 | 1381 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) |
fb84c7a0 | 1382 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1383 | |
fb84c7a0 | 1384 | #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) |
fb84c7a0 | 1385 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
c98f8742 | 1386 | |
d9a5f180 | 1387 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1388 | |
e075ae69 RH |
1389 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1390 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1391 | ||
c98f8742 JVA |
1392 | /* The class value for index registers, and the one for base regs. */ |
1393 | ||
1394 | #define INDEX_REG_CLASS INDEX_REGS | |
1395 | #define BASE_REG_CLASS GENERAL_REGS | |
1396 | ||
c98f8742 | 1397 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1398 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1399 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1400 | |
d2836273 JH |
1401 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1402 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1403 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1404 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1405 | ? Q_REGS : (CLASS)) |
1406 | ||
1407 | /* Given an rtx X being reloaded into a reg required to be | |
1408 | in class CLASS, return the class of reg to actually use. | |
1409 | In general this is just CLASS; but on some machines | |
1410 | in some cases it is preferable to use a more restrictive class. | |
1411 | On the 80386 series, we prevent floating constants from being | |
1412 | reloaded into floating registers (since no move-insn can do that) | |
1413 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1414 | ||
d398b3b1 | 1415 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1416 | QImode must go into class Q_REGS. |
d398b3b1 | 1417 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1418 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1419 | |
d9a5f180 GS |
1420 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1421 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e | 1422 | |
b5c82fa1 PB |
1423 | /* Discourage putting floating-point values in SSE registers unless |
1424 | SSE math is being used, and likewise for the 387 registers. */ | |
1425 | ||
1426 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
1427 | ix86_preferred_output_reload_class ((X), (CLASS)) | |
1428 | ||
85ff473e | 1429 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1430 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1431 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1432 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 | 1433 | |
c62b3659 UB |
1434 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1435 | There is no need to emit full 64 bit move on 64 bit targets | |
1436 | for integral modes that can be moved using 32 bit move. */ | |
1437 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1438 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1439 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1440 | : MODE) | |
1441 | ||
c98f8742 JVA |
1442 | /* Return the maximum number of consecutive registers |
1443 | needed to represent mode MODE in a register of class CLASS. */ | |
1444 | /* On the 80386, this is the size of MODE in words, | |
f8a1ebc6 | 1445 | except in the FP regs, where a single reg is always enough. */ |
a7180f70 | 1446 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1447 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1448 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 JH |
1449 | : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ |
1450 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1451 | |
1452 | /* A C expression whose value is nonzero if pseudos that have been | |
1453 | assigned to registers of class CLASS would likely be spilled | |
1454 | because registers of CLASS are needed for spill registers. | |
1455 | ||
1456 | The default value of this macro returns 1 if CLASS has exactly one | |
1457 | register and zero otherwise. On most machines, this default | |
1458 | should be used. Only define this macro to some other expression | |
1459 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1460 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1461 | macro returns nonzero for those classes, those pseudos will only |
1462 | be allocated by `global.c', which knows how to reallocate the | |
1463 | pseudo to another register. If there would not be another | |
1464 | register available for reallocation, you should not change the | |
1465 | definition of this macro since the only effect of such a | |
1466 | definition would be to slow down register allocation. */ | |
1467 | ||
1468 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1469 | (((CLASS) == AREG) \ | |
1470 | || ((CLASS) == DREG) \ | |
1471 | || ((CLASS) == CREG) \ | |
1472 | || ((CLASS) == BREG) \ | |
1473 | || ((CLASS) == AD_REGS) \ | |
1474 | || ((CLASS) == SIREG) \ | |
b0af5c03 JH |
1475 | || ((CLASS) == DIREG) \ |
1476 | || ((CLASS) == FP_TOP_REG) \ | |
1477 | || ((CLASS) == FP_SECOND_REG)) | |
f5316dfe | 1478 | |
1272914c RH |
1479 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1480 | ||
1481 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1482 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1483 | \f |
1484 | /* Stack layout; function entry, exit and calling. */ | |
1485 | ||
1486 | /* Define this if pushing a word on the stack | |
1487 | makes the stack pointer a smaller address. */ | |
1488 | #define STACK_GROWS_DOWNWARD | |
1489 | ||
a4d05547 | 1490 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1491 | is at the high-address end of the local variables; |
1492 | that is, each additional local variable allocated | |
1493 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1494 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1495 | |
1496 | /* Offset within stack frame to start allocating local variables at. | |
1497 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1498 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1499 | of the first local allocated. */ | |
1500 | #define STARTING_FRAME_OFFSET 0 | |
1501 | ||
1502 | /* If we generate an insn to push BYTES bytes, | |
1503 | this says how many the stack pointer really advances by. | |
6541fe75 JJ |
1504 | On 386, we have pushw instruction that decrements by exactly 2 no |
1505 | matter what the position was, there is no pushb. | |
1506 | But as CIE data alignment factor on this arch is -4, we need to make | |
1507 | sure all stack pointer adjustments are in multiple of 4. | |
fce5a9f2 | 1508 | |
d2836273 JH |
1509 | For 64bit ABI we round up to 8 bytes. |
1510 | */ | |
c98f8742 | 1511 | |
d2836273 JH |
1512 | #define PUSH_ROUNDING(BYTES) \ |
1513 | (TARGET_64BIT \ | |
1514 | ? (((BYTES) + 7) & (-8)) \ | |
6541fe75 | 1515 | : (((BYTES) + 3) & (-4))) |
c98f8742 | 1516 | |
f73ad30e JH |
1517 | /* If defined, the maximum amount of space required for outgoing arguments will |
1518 | be computed and placed into the variable | |
38173d38 | 1519 | `crtl->outgoing_args_size'. No space will be pushed onto the |
f73ad30e | 1520 | stack for each call; instead, the function prologue should increase the stack |
9aa5c1b2 JH |
1521 | frame size by this amount. |
1522 | ||
1523 | MS ABI seem to require 16 byte alignment everywhere except for function | |
1524 | prologue and apilogue. This is not possible without | |
1525 | ACCUMULATE_OUTGOING_ARGS. */ | |
f73ad30e | 1526 | |
6c6094f1 UB |
1527 | #define ACCUMULATE_OUTGOING_ARGS \ |
1528 | (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) | |
f73ad30e JH |
1529 | |
1530 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1531 | instructions to pass outgoing arguments. */ | |
1532 | ||
1533 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1534 | ||
2da4124d L |
1535 | /* We want the stack and args grow in opposite directions, even if |
1536 | PUSH_ARGS is 0. */ | |
1537 | #define PUSH_ARGS_REVERSED 1 | |
1538 | ||
c98f8742 JVA |
1539 | /* Offset of first parameter from the argument pointer register value. */ |
1540 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1541 | ||
a7180f70 BS |
1542 | /* Define this macro if functions should assume that stack space has been |
1543 | allocated for arguments even when their values are passed in registers. | |
1544 | ||
1545 | The value of this macro is the size, in bytes, of the area reserved for | |
1546 | arguments passed in registers for the function represented by FNDECL. | |
1547 | ||
1548 | This space can be allocated by the caller, or be a part of the | |
1549 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1550 | which. */ | |
7c800926 KT |
1551 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1552 | ||
4ae8027b UB |
1553 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
1554 | (ix86_function_type_abi (FNTYPE) == MS_ABI) | |
7c800926 | 1555 | |
c98f8742 JVA |
1556 | /* Value is the number of bytes of arguments automatically |
1557 | popped when returning from a subroutine call. | |
8b109b37 | 1558 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1559 | FUNTYPE is the data type of the function (as a tree), |
1560 | or for a library call it is an identifier node for the subroutine name. | |
1561 | SIZE is the number of bytes of arguments passed on the stack. | |
1562 | ||
1563 | On the 80386, the RTD insn may be used to pop them if the number | |
1564 | of args is fixed, but if the number is variable then the caller | |
1565 | must pop them all. RTD can't be used for library calls now | |
1566 | because the library is compiled with the Unix compiler. | |
1567 | Use of RTD is a selectable option, since it is incompatible with | |
1568 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1569 | the caller must always pop the args. |
1570 | ||
1571 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1572 | |
d9a5f180 GS |
1573 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1574 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1575 | |
4ae8027b | 1576 | #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N) |
c98f8742 JVA |
1577 | |
1578 | /* Define how to find the value returned by a library function | |
1579 | assuming the value has mode MODE. */ | |
1580 | ||
4ae8027b | 1581 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1582 | |
e9125c09 TW |
1583 | /* Define the size of the result block used for communication between |
1584 | untyped_call and untyped_return. The block contains a DImode value | |
1585 | followed by the block used by fnsave and frstor. */ | |
1586 | ||
1587 | #define APPLY_RESULT_SIZE (8+108) | |
1588 | ||
b08de47e | 1589 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1590 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1591 | |
1592 | /* Define a data type for recording info about an argument list | |
1593 | during the scan of that argument list. This data type should | |
1594 | hold all necessary information about the function itself | |
1595 | and about the args processed so far, enough to enable macros | |
b08de47e | 1596 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1597 | |
e075ae69 | 1598 | typedef struct ix86_args { |
fa283935 | 1599 | int words; /* # words passed so far */ |
b08de47e MM |
1600 | int nregs; /* # registers available for passing */ |
1601 | int regno; /* next available register number */ | |
9d72d996 | 1602 | int fastcall; /* fastcall calling convention is used */ |
fa283935 | 1603 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1604 | int sse_nregs; /* # sse registers available for passing */ |
95879c72 | 1605 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1606 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1607 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1608 | int sse_regno; /* next available sse register number */ | |
1609 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1610 | int mmx_nregs; /* # mmx registers available for passing */ |
1611 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1612 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2f84b963 RG |
1613 | int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should |
1614 | be passed in SSE registers. Otherwise 0. */ | |
51212b32 | 1615 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1616 | MS_ABI for ms abi. */ |
b08de47e | 1617 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1618 | |
1619 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1620 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1621 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1622 | |
0f6937fe | 1623 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
dafc5b82 | 1624 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
c98f8742 JVA |
1625 | |
1626 | /* Update the data in CUM to advance over an argument | |
1627 | of mode MODE and data type TYPE. | |
1628 | (TYPE is null for libcalls where that information may not be available.) */ | |
1629 | ||
d9a5f180 GS |
1630 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1631 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1632 | |
1633 | /* Define where to put the arguments to a function. | |
1634 | Value is zero to push the argument on the stack, | |
1635 | or a hard register in which to store the argument. | |
1636 | ||
1637 | MODE is the argument's machine mode. | |
1638 | TYPE is the data type of the argument (as a tree). | |
1639 | This is null for libcalls where that information may | |
1640 | not be available. | |
1641 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1642 | the preceding args and about the function being called. | |
1643 | NAMED is nonzero if this argument is a named parameter | |
1644 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1645 | ||
c98f8742 | 1646 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1647 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 | 1648 | |
a5fe455b ZW |
1649 | #define TARGET_ASM_FILE_END ix86_file_end |
1650 | #define NEED_INDICATE_EXEC_STACK 0 | |
3a0433fd | 1651 | |
c98f8742 JVA |
1652 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1653 | for profiling a function entry. */ | |
1654 | ||
a5fa1ecd JH |
1655 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1656 | ||
1657 | #define MCOUNT_NAME "_mcount" | |
1658 | ||
1659 | #define PROFILE_COUNT_REGISTER "edx" | |
c98f8742 JVA |
1660 | |
1661 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1662 | the stack pointer does not matter. The value is tested only in | |
1663 | functions that have frame pointers. | |
1664 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1665 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1666 | we have to restore it ourselves from the frame pointer, in order to |
1667 | use pop */ | |
1668 | ||
1669 | #define EXIT_IGNORE_STACK 1 | |
1670 | ||
c98f8742 JVA |
1671 | /* Output assembler code for a block containing the constant parts |
1672 | of a trampoline, leaving space for the variable parts. */ | |
1673 | ||
a269a03c | 1674 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1675 | mov #STATIC,ecx |
a269a03c JC |
1676 | jmp FUNCTION |
1677 | The trampoline is generated entirely at runtime. The operand of JMP | |
1678 | is the address of FUNCTION relative to the instruction following the | |
1679 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1680 | |
1681 | /* Length in units of the trampoline for entering a nested function. */ | |
1682 | ||
39d04363 | 1683 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1684 | |
1685 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1686 | FNADDR is an RTX for the address of the function's pure code. | |
1687 | CXT is an RTX for the static chain value for the function. */ | |
1688 | ||
d9a5f180 GS |
1689 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1690 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1691 | \f |
1692 | /* Definitions for register eliminations. | |
1693 | ||
1694 | This is an array of structures. Each structure initializes one pair | |
1695 | of eliminable registers. The "from" register number is given first, | |
1696 | followed by "to". Eliminations of the same "from" register are listed | |
1697 | in order of preference. | |
1698 | ||
afc2cd05 NC |
1699 | There are two registers that can always be eliminated on the i386. |
1700 | The frame pointer and the arg pointer can be replaced by either the | |
1701 | hard frame pointer or to the stack pointer, depending upon the | |
1702 | circumstances. The hard frame pointer is not used before reload and | |
1703 | so it is not eligible for elimination. */ | |
c98f8742 | 1704 | |
564d80f4 JH |
1705 | #define ELIMINABLE_REGS \ |
1706 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1707 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1708 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1709 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1710 | |
2c5a510c | 1711 | /* Given FROM and TO register numbers, say whether this elimination is |
2e3f842f | 1712 | allowed. */ |
c98f8742 | 1713 | |
2e3f842f | 1714 | #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO)) |
c98f8742 JVA |
1715 | |
1716 | /* Define the offset between two registers, one to be eliminated, and the other | |
1717 | its replacement, at the start of a routine. */ | |
1718 | ||
d9a5f180 GS |
1719 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1720 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1721 | \f |
1722 | /* Addressing modes, and classification of registers for them. */ | |
1723 | ||
c98f8742 JVA |
1724 | /* Macros to check register numbers against specific register classes. */ |
1725 | ||
1726 | /* These assume that REGNO is a hard or pseudo reg number. | |
1727 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1728 | or a pseudo reg currently allocated to a suitable hard reg. | |
1729 | Since they use reg_renumber, they are safe only once reg_renumber | |
1730 | has been allocated, which happens in local-alloc.c. */ | |
1731 | ||
3f3f2124 JH |
1732 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1733 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1734 | || REX_INT_REGNO_P (REGNO) \ |
1735 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1736 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1737 | |
3f3f2124 | 1738 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1739 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1740 | || (REGNO) == ARG_POINTER_REGNUM \ |
1741 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1742 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1743 | |
c98f8742 JVA |
1744 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1745 | and check its validity for a certain class. | |
1746 | We have two alternate definitions for each of them. | |
1747 | The usual definition accepts all pseudo regs; the other rejects | |
1748 | them unless they have been allocated suitable hard regs. | |
1749 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1750 | ||
1751 | Most source files want to accept pseudo regs in the hope that | |
1752 | they will get allocated to the class that the insn wants them to be in. | |
1753 | Source files for reload pass need to be strict. | |
1754 | After reload, it makes no difference, since pseudo regs have | |
1755 | been eliminated by then. */ | |
1756 | ||
c98f8742 | 1757 | |
ff482c8d | 1758 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1759 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1760 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1761 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1762 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1763 | ||
3b3c6a3f | 1764 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1765 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1766 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1767 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1768 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1769 | |
3b3c6a3f MM |
1770 | /* Strict versions, hard registers only */ |
1771 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1772 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1773 | |
3b3c6a3f | 1774 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1775 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1776 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1777 | |
1778 | #else | |
d9a5f180 GS |
1779 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1780 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1781 | #endif |
1782 | ||
1783 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1784 | that is a valid memory address for an instruction. | |
1785 | The MODE argument is the machine mode for the MEM expression | |
1786 | that wants to use this address. | |
1787 | ||
1788 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1789 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1790 | ||
1791 | See legitimize_pic_address in i386.c for details as to what | |
1792 | constitutes a legitimate address when -fpic is used. */ | |
1793 | ||
1794 | #define MAX_REGS_PER_ADDRESS 2 | |
1795 | ||
f996902d | 1796 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1797 | |
1798 | /* Nonzero if the constant value X is a legitimate general operand. | |
1799 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1800 | ||
f996902d | 1801 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1802 | |
3b3c6a3f MM |
1803 | #ifdef REG_OK_STRICT |
1804 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1805 | do { \ |
1806 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1807 | goto ADDR; \ |
d9a5f180 | 1808 | } while (0) |
c98f8742 | 1809 | |
3b3c6a3f MM |
1810 | #else |
1811 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1812 | do { \ |
1813 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1814 | goto ADDR; \ |
d9a5f180 | 1815 | } while (0) |
c98f8742 | 1816 | |
3b3c6a3f MM |
1817 | #endif |
1818 | ||
b949ea8b JW |
1819 | /* If defined, a C expression to determine the base term of address X. |
1820 | This macro is used in only one place: `find_base_term' in alias.c. | |
1821 | ||
1822 | It is always safe for this macro to not be defined. It exists so | |
1823 | that alias analysis can understand machine-dependent addresses. | |
1824 | ||
1825 | The typical use of this macro is to handle addresses containing | |
1826 | a label_ref or symbol_ref within an UNSPEC. */ | |
1827 | ||
d9a5f180 | 1828 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1829 | |
c98f8742 JVA |
1830 | /* Try machine-dependent ways of modifying an illegitimate address |
1831 | to be legitimate. If we find one, return the new, valid address. | |
1832 | This macro is used in only one place: `memory_address' in explow.c. | |
1833 | ||
1834 | OLDX is the address as it was before break_out_memory_refs was called. | |
1835 | In some cases it is useful to look at this to decide what needs to be done. | |
1836 | ||
1837 | MODE and WIN are passed so that this macro can use | |
1838 | GO_IF_LEGITIMATE_ADDRESS. | |
1839 | ||
1840 | It is always safe for this macro to do nothing. It exists to recognize | |
1841 | opportunities to optimize the output. | |
1842 | ||
1843 | For the 80386, we handle X+REG by loading X into a register R and | |
1844 | using R+REG. R will go in a general reg and indexing will be used. | |
1845 | However, if REG is a broken-out memory address or multiplication, | |
1846 | nothing needs to be done because REG can certainly go in a general reg. | |
1847 | ||
1848 | When -fpic is used, special handling is needed for symbolic references. | |
1849 | See comments by legitimize_pic_address in i386.c for details. */ | |
1850 | ||
3b3c6a3f | 1851 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
1852 | do { \ |
1853 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1854 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 1855 | goto WIN; \ |
d9a5f180 | 1856 | } while (0) |
c98f8742 JVA |
1857 | |
1858 | /* Nonzero if the constant value X is a legitimate general operand | |
fce5a9f2 | 1859 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1860 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1861 | ||
f996902d | 1862 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1863 | |
1864 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1865 | (GET_CODE (X) == SYMBOL_REF \ |
1866 | || GET_CODE (X) == LABEL_REF \ | |
1867 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
1868 | |
1869 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1870 | has an effect that depends on the machine mode it is used for. | |
1871 | On the 80386, only postdecrement and postincrement address depend thus | |
b9a76028 MS |
1872 | (the amount of decrement or increment being the length of the operand). |
1873 | These are now caught in recog.c. */ | |
1874 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
c98f8742 | 1875 | \f |
b08de47e MM |
1876 | /* Max number of args passed in registers. If this is more than 3, we will |
1877 | have problems with ebx (register #4), since it is a caller save register and | |
1878 | is also used as the pic register in ELF. So for now, don't allow more than | |
1879 | 3 registers to be passed in registers. */ | |
1880 | ||
7c800926 KT |
1881 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1882 | #define X86_64_REGPARM_MAX 6 | |
1883 | #define X64_REGPARM_MAX 4 | |
1884 | #define X86_32_REGPARM_MAX 3 | |
1885 | ||
1886 | #define X86_64_SSE_REGPARM_MAX 8 | |
1887 | #define X64_SSE_REGPARM_MAX 4 | |
1888 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0) | |
1889 | ||
4ae8027b UB |
1890 | #define REGPARM_MAX \ |
1891 | (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \ | |
1892 | : X86_64_REGPARM_MAX) \ | |
1893 | : X86_32_REGPARM_MAX) | |
d2836273 | 1894 | |
4ae8027b UB |
1895 | #define SSE_REGPARM_MAX \ |
1896 | (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \ | |
1897 | : X86_64_SSE_REGPARM_MAX) \ | |
1898 | : X86_32_SSE_REGPARM_MAX) | |
bcf17554 JH |
1899 | |
1900 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
b08de47e | 1901 | |
c98f8742 JVA |
1902 | \f |
1903 | /* Specify the machine mode that this machine uses | |
1904 | for the index in the tablejump instruction. */ | |
dc4d7240 JH |
1905 | #define CASE_VECTOR_MODE \ |
1906 | (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) | |
c98f8742 | 1907 | |
c98f8742 JVA |
1908 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1909 | #define DEFAULT_SIGNED_CHAR 1 | |
1910 | ||
1911 | /* Max number of bytes we can move from memory to memory | |
1912 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1913 | #define MOVE_MAX 16 |
1914 | ||
1915 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1916 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1917 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 1918 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 1919 | |
7e24ffc9 | 1920 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1921 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1922 | Increasing the value will always make code faster, but eventually |
1923 | incurs high cost in increased code size. | |
c98f8742 | 1924 | |
e2e52e1b | 1925 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1926 | |
e04ad03d | 1927 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1928 | |
45d78e7f JJ |
1929 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1930 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1931 | ||
e04ad03d | 1932 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1933 | |
c98f8742 JVA |
1934 | /* Define if shifts truncate the shift count |
1935 | which implies one can omit a sign-extension or zero-extension | |
1936 | of a shift count. */ | |
892a2d68 | 1937 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
1938 | |
1939 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1940 | ||
1941 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1942 | is done just by pretending it is already truncated. */ | |
1943 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1944 | ||
d9f32422 JH |
1945 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1946 | TYPE and which has the specified mode and signedness is to be | |
1947 | stored in a register. This macro is only called when TYPE is a | |
1948 | scalar type. | |
1949 | ||
f710504c | 1950 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1951 | quantities to SImode. The choice depends on target type. */ |
1952 | ||
1953 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1954 | do { \ |
d9f32422 JH |
1955 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1956 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1957 | (MODE) = SImode; \ |
1958 | } while (0) | |
d9f32422 | 1959 | |
c98f8742 JVA |
1960 | /* Specify the machine mode that pointers have. |
1961 | After generation of rtl, the compiler makes no further distinction | |
1962 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 1963 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
1964 | |
1965 | /* A function address in a call instruction | |
1966 | is a byte address (for indexing purposes) | |
1967 | so give the MEM rtx a byte's mode. */ | |
1968 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1969 | \f |
96e7ae40 JH |
1970 | /* A C expression for the cost of moving data from a register in class FROM to |
1971 | one in class TO. The classes are expressed using the enumeration values | |
1972 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
1973 | interpreted relative to that. | |
d4ba09c0 | 1974 | |
96e7ae40 JH |
1975 | It is not required that the cost always equal 2 when FROM is the same as TO; |
1976 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 1977 | general registers. */ |
d4ba09c0 | 1978 | |
f84aa48a | 1979 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 1980 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
1981 | |
1982 | /* A C expression for the cost of moving data of mode M between a | |
1983 | register and memory. A value of 2 is the default; this cost is | |
1984 | relative to those in `REGISTER_MOVE_COST'. | |
1985 | ||
1986 | If moving between registers and memory is more expensive than | |
1987 | between two registers, you should define this macro to express the | |
fa79946e | 1988 | relative cost. */ |
d4ba09c0 | 1989 | |
d9a5f180 GS |
1990 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
1991 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
1992 | |
1993 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1994 | is the default; other values are interpreted relative to that. */ | |
1995 | ||
3a4fd356 JH |
1996 | #define BRANCH_COST(speed_p, predictable_p) \ |
1997 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 SC |
1998 | |
1999 | /* Define this macro as a C expression which is nonzero if accessing | |
2000 | less than a word of memory (i.e. a `char' or a `short') is no | |
2001 | faster than accessing a word of memory, i.e., if such access | |
2002 | require more than one instruction or if there is no difference in | |
2003 | cost between byte and (aligned) word loads. | |
2004 | ||
2005 | When this macro is not defined, the compiler will access a field by | |
2006 | finding the smallest containing object; when it is defined, a | |
2007 | fullword load will be used if alignment permits. Unless bytes | |
2008 | accesses are faster than word accesses, using word accesses is | |
2009 | preferable since it may eliminate subsequent memory access if | |
2010 | subsequent accesses occur to other fields in the same word of the | |
2011 | structure, but to different bytes. */ | |
2012 | ||
2013 | #define SLOW_BYTE_ACCESS 0 | |
2014 | ||
2015 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2016 | #define SLOW_SHORT_ACCESS 0 | |
2017 | ||
d4ba09c0 SC |
2018 | /* Define this macro to be the value 1 if unaligned accesses have a |
2019 | cost many times greater than aligned accesses, for example if they | |
2020 | are emulated in a trap handler. | |
2021 | ||
9cd10576 KH |
2022 | When this macro is nonzero, the compiler will act as if |
2023 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2024 | moves. This can cause significantly more instructions to be |
9cd10576 | 2025 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2026 | accesses only add a cycle or two to the time for a memory access. |
2027 | ||
2028 | If the value of this macro is always zero, it need not be defined. */ | |
2029 | ||
e1565e65 | 2030 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 2031 | |
d4ba09c0 SC |
2032 | /* Define this macro if it is as good or better to call a constant |
2033 | function address than to call an address kept in a register. | |
2034 | ||
2035 | Desirable on the 386 because a CALL with a constant address is | |
2036 | faster than one with a register address. */ | |
2037 | ||
2038 | #define NO_FUNCTION_CSE | |
c98f8742 | 2039 | \f |
c572e5ba JVA |
2040 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2041 | return the mode to be used for the comparison. | |
2042 | ||
2043 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2044 | VOIDmode should be used in all other cases. |
c572e5ba | 2045 | |
16189740 | 2046 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2047 | possible, to allow for more combinations. */ |
c98f8742 | 2048 | |
d9a5f180 | 2049 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2050 | |
9cd10576 | 2051 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2052 | reversed. */ |
2053 | ||
2054 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2055 | ||
2056 | /* A C expression whose value is reversed condition code of the CODE for | |
2057 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2058 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2059 | |
c98f8742 JVA |
2060 | \f |
2061 | /* Control the assembler format that we output, to the extent | |
2062 | this does not vary between assemblers. */ | |
2063 | ||
2064 | /* How to refer to registers in assembler output. | |
892a2d68 | 2065 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2066 | |
a7b376ee | 2067 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2068 | For non floating point regs, the following are the HImode names. |
2069 | ||
2070 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
a55f4481 | 2071 | instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ |
c98f8742 | 2072 | |
a7180f70 BS |
2073 | #define HI_REGISTER_NAMES \ |
2074 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2075 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2076 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2077 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2078 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 JH |
2079 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
2080 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 2081 | |
c98f8742 JVA |
2082 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2083 | ||
2084 | /* Table of additional register names to use in user input. */ | |
2085 | ||
2086 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
2087 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2088 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
2089 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
2090 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 2091 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
21bf822e | 2092 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } |
c98f8742 JVA |
2093 | |
2094 | /* Note we are omitting these since currently I don't know how | |
2095 | to get gcc to use these, since they want the same but different | |
2096 | number as al, and ax. | |
2097 | */ | |
2098 | ||
c98f8742 | 2099 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2100 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2101 | |
2102 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2103 | of regs 0 through 3. */ |
c98f8742 JVA |
2104 | |
2105 | #define QI_HIGH_REGISTER_NAMES \ | |
2106 | {"ah", "dh", "ch", "bh", } | |
2107 | ||
2108 | /* How to renumber registers for dbx and gdb. */ | |
2109 | ||
d9a5f180 GS |
2110 | #define DBX_REGISTER_NUMBER(N) \ |
2111 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2112 | |
9a82e702 MS |
2113 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2114 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2115 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2116 | |
469ac993 JM |
2117 | /* Before the prologue, RA is at 0(%esp). */ |
2118 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2119 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2120 | |
e414ab29 | 2121 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2122 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2123 | ((COUNT) == 0 \ | |
2124 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2125 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2126 | |
892a2d68 | 2127 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2128 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2129 | |
a6ab3aad | 2130 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2131 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2132 | |
1020a5ab RH |
2133 | /* Describe how we implement __builtin_eh_return. */ |
2134 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2135 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2136 | ||
ad919812 | 2137 | |
e4c4ebeb RH |
2138 | /* Select a format to encode pointers in exception handling data. CODE |
2139 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2140 | true if the symbol may be affected by dynamic relocations. | |
2141 | ||
2142 | ??? All x86 object file formats are capable of representing this. | |
2143 | After all, the relocation needed is the same as for the call insn. | |
2144 | Whether or not a particular assembler allows us to enter such, I | |
2145 | guess we'll have to see. */ | |
d9a5f180 | 2146 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2147 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2148 | |
c98f8742 JVA |
2149 | /* This is how to output an insn to push a register on the stack. |
2150 | It need not be very fast code. */ | |
2151 | ||
d9a5f180 | 2152 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2153 | do { \ |
2154 | if (TARGET_64BIT) \ | |
2155 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2156 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2157 | else \ | |
2158 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2159 | } while (0) | |
c98f8742 JVA |
2160 | |
2161 | /* This is how to output an insn to pop a register from the stack. | |
2162 | It need not be very fast code. */ | |
2163 | ||
d9a5f180 | 2164 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2165 | do { \ |
2166 | if (TARGET_64BIT) \ | |
2167 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2168 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2169 | else \ | |
2170 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2171 | } while (0) | |
c98f8742 | 2172 | |
f88c65f7 | 2173 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2174 | |
2175 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2176 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2177 | |
f88c65f7 | 2178 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2179 | |
33f7f353 | 2180 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2181 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2182 | |
95879c72 L |
2183 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is |
2184 | true. */ | |
2185 | ||
2186 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2187 | { \ | |
2188 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
2189 | { \ | |
2190 | if (TARGET_AVX) \ | |
2191 | (PTR) += 1; \ | |
2192 | else \ | |
2193 | (PTR) += 2; \ | |
2194 | } \ | |
2195 | } | |
2196 | ||
2197 | /* A C statement or statements which output an assembler instruction | |
2198 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2199 | variable of type `char *' which points to the opcode name in | |
2200 | its "internal" form--the form that is written in the machine | |
2201 | description. */ | |
2202 | ||
2203 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2204 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2205 | ||
f7288899 EC |
2206 | /* Under some conditions we need jump tables in the text section, |
2207 | because the assembler cannot handle label differences between | |
2208 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2209 | |
2210 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2211 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2212 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2213 | |
cea3bd3e RH |
2214 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2215 | and switch back. For x86 we do this only to save a few bytes that | |
2216 | would otherwise be unused in the text section. */ | |
2217 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2218 | asm (SECTION_OP "\n\t" \ | |
2219 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2220 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 2221 | \f |
c98f8742 JVA |
2222 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2223 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
2224 | Effect of various CODE letters is described in i386.c near |
2225 | print_operand function. */ | |
c98f8742 | 2226 | |
d9a5f180 | 2227 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
c9d259cb | 2228 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') |
c98f8742 JVA |
2229 | |
2230 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
d9a5f180 | 2231 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
2232 | |
2233 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 2234 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 2235 | |
f996902d RH |
2236 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
2237 | do { \ | |
2238 | if (! output_addr_const_extra (FILE, (X))) \ | |
2239 | goto FAIL; \ | |
2240 | } while (0); | |
d4ba09c0 | 2241 | \f |
5bf0ebab RH |
2242 | /* Which processor to schedule for. The cpu attribute defines a list that |
2243 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
2244 | ||
2245 | enum processor_type | |
2246 | { | |
8383d43c | 2247 | PROCESSOR_I386 = 0, /* 80386 */ |
5bf0ebab RH |
2248 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2249 | PROCESSOR_PENTIUM, | |
2250 | PROCESSOR_PENTIUMPRO, | |
cfe1b18f | 2251 | PROCESSOR_GEODE, |
5bf0ebab RH |
2252 | PROCESSOR_K6, |
2253 | PROCESSOR_ATHLON, | |
2254 | PROCESSOR_PENTIUM4, | |
4977bab6 | 2255 | PROCESSOR_K8, |
89c43c0a | 2256 | PROCESSOR_NOCONA, |
05f85dbb | 2257 | PROCESSOR_CORE2, |
d326eaf0 JH |
2258 | PROCESSOR_GENERIC32, |
2259 | PROCESSOR_GENERIC64, | |
21efb4d4 | 2260 | PROCESSOR_AMDFAM10, |
5bf0ebab RH |
2261 | PROCESSOR_max |
2262 | }; | |
2263 | ||
9e555526 | 2264 | extern enum processor_type ix86_tune; |
5bf0ebab | 2265 | extern enum processor_type ix86_arch; |
5bf0ebab RH |
2266 | |
2267 | enum fpmath_unit | |
2268 | { | |
2269 | FPMATH_387 = 1, | |
2270 | FPMATH_SSE = 2 | |
2271 | }; | |
2272 | ||
2273 | extern enum fpmath_unit ix86_fpmath; | |
5bf0ebab | 2274 | |
f996902d RH |
2275 | enum tls_dialect |
2276 | { | |
2277 | TLS_DIALECT_GNU, | |
5bf5a10b | 2278 | TLS_DIALECT_GNU2, |
f996902d RH |
2279 | TLS_DIALECT_SUN |
2280 | }; | |
2281 | ||
2282 | extern enum tls_dialect ix86_tls_dialect; | |
f996902d | 2283 | |
6189a572 | 2284 | enum cmodel { |
5bf0ebab RH |
2285 | CM_32, /* The traditional 32-bit ABI. */ |
2286 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2287 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2288 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2289 | CM_LARGE, /* No assumptions. */ | |
7dcbf659 | 2290 | CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ |
dc4d7240 JH |
2291 | CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ |
2292 | CM_LARGE_PIC /* No assumptions. */ | |
6189a572 JH |
2293 | }; |
2294 | ||
5bf0ebab | 2295 | extern enum cmodel ix86_cmodel; |
5bf0ebab | 2296 | |
8362f420 JH |
2297 | /* Size of the RED_ZONE area. */ |
2298 | #define RED_ZONE_SIZE 128 | |
2299 | /* Reserved area of the red zone for temporaries. */ | |
2300 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
2301 | |
2302 | enum asm_dialect { | |
2303 | ASM_ATT, | |
2304 | ASM_INTEL | |
2305 | }; | |
5bf0ebab | 2306 | |
80f33d06 | 2307 | extern enum asm_dialect ix86_asm_dialect; |
95899b34 | 2308 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2309 | extern unsigned int ix86_incoming_stack_boundary; |
7dcbf659 | 2310 | extern int ix86_branch_cost, ix86_section_threshold; |
5bf0ebab RH |
2311 | |
2312 | /* Smallest class containing REGNO. */ | |
2313 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2314 | ||
d9a5f180 GS |
2315 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
2316 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
1ef45b77 | 2317 | extern rtx ix86_compare_emitted; |
22fb740d JH |
2318 | \f |
2319 | /* To properly truncate FP values into integers, we need to set i387 control | |
2320 | word. We can't emit proper mode switching code before reload, as spills | |
2321 | generated by reload may truncate values incorrectly, but we still can avoid | |
2322 | redundant computation of new control word by the mode switching pass. | |
2323 | The fldcw instructions are still emitted redundantly, but this is probably | |
2324 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2325 | the sequence. |
22fb740d JH |
2326 | |
2327 | The machinery is to emit simple truncation instructions and split them | |
2328 | before reload to instructions having USEs of two memory locations that | |
2329 | are filled by this code to old and new control word. | |
fce5a9f2 | 2330 | |
22fb740d JH |
2331 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2332 | needed. */ | |
2333 | ||
ff680eb1 UB |
2334 | enum ix86_entity |
2335 | { | |
2336 | I387_TRUNC = 0, | |
2337 | I387_FLOOR, | |
2338 | I387_CEIL, | |
2339 | I387_MASK_PM, | |
2340 | MAX_386_ENTITIES | |
2341 | }; | |
2342 | ||
1cba2b96 | 2343 | enum ix86_stack_slot |
ff680eb1 | 2344 | { |
80dcd3aa UB |
2345 | SLOT_VIRTUAL = 0, |
2346 | SLOT_TEMP, | |
ff680eb1 UB |
2347 | SLOT_CW_STORED, |
2348 | SLOT_CW_TRUNC, | |
2349 | SLOT_CW_FLOOR, | |
2350 | SLOT_CW_CEIL, | |
2351 | SLOT_CW_MASK_PM, | |
2352 | MAX_386_STACK_LOCALS | |
2353 | }; | |
22fb740d JH |
2354 | |
2355 | /* Define this macro if the port needs extra instructions inserted | |
2356 | for mode switching in an optimizing compilation. */ | |
2357 | ||
ff680eb1 UB |
2358 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2359 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2360 | |
2361 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2362 | initializer for an array of integers. Each initializer element N | |
2363 | refers to an entity that needs mode switching, and specifies the | |
2364 | number of different modes that might need to be set for this | |
2365 | entity. The position of the initializer in the initializer - | |
2366 | starting counting at zero - determines the integer that is used to | |
2367 | refer to the mode-switched entity in question. */ | |
2368 | ||
ff680eb1 UB |
2369 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2370 | { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
22fb740d JH |
2371 | |
2372 | /* ENTITY is an integer specifying a mode-switched entity. If | |
2373 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2374 | return an integer value not larger than the corresponding element | |
2375 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
ff680eb1 UB |
2376 | must be switched into prior to the execution of INSN. */ |
2377 | ||
2378 | #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
22fb740d JH |
2379 | |
2380 | /* This macro specifies the order in which modes for ENTITY are | |
2381 | processed. 0 is the highest priority. */ | |
2382 | ||
d9a5f180 | 2383 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
2384 | |
2385 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2386 | is the set of hard registers live at the point where the insn(s) | |
2387 | are to be inserted. */ | |
2388 | ||
2389 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
1d1df0df | 2390 | ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ |
ff680eb1 | 2391 | ? emit_i387_cw_initialization (MODE), 0 \ |
22fb740d | 2392 | : 0) |
ff680eb1 | 2393 | |
0f0138b6 JH |
2394 | \f |
2395 | /* Avoid renaming of stack registers, as doing so in combination with | |
2396 | scheduling just increases amount of live registers at time and in | |
2397 | the turn amount of fxch instructions needed. | |
2398 | ||
43f3a59d | 2399 | ??? Maybe Pentium chips benefits from renaming, someone can try.... */ |
0f0138b6 | 2400 | |
d9a5f180 | 2401 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
fb84c7a0 | 2402 | (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) |
22fb740d | 2403 | |
3b3c6a3f | 2404 | \f |
e91f04de | 2405 | #define FASTCALL_PREFIX '@' |
fa1a0d02 JH |
2406 | \f |
2407 | struct machine_function GTY(()) | |
2408 | { | |
2409 | struct stack_local_entry *stack_locals; | |
2410 | const char *some_ld_name; | |
4aab97f9 L |
2411 | int varargs_gpr_size; |
2412 | int varargs_fpr_size; | |
fa1a0d02 | 2413 | int accesses_prev_frame; |
ff680eb1 | 2414 | int optimize_mode_switching[MAX_386_ENTITIES]; |
922e3e33 UB |
2415 | int needs_cld; |
2416 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue | |
2417 | expander to determine the style used. */ | |
d9b40e8d | 2418 | int use_fast_prologue_epilogue; |
d7394366 JH |
2419 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed |
2420 | for. */ | |
2421 | int use_fast_prologue_epilogue_nregs; | |
5bf5a10b AO |
2422 | /* If true, the current function needs the default PIC register, not |
2423 | an alternate register (on x86) and must not use the red zone (on | |
2424 | x86_64), even if it's a leaf function. We don't want the | |
2425 | function to be regarded as non-leaf because TLS calls need not | |
2426 | affect register allocation. This flag is set when a TLS call | |
2427 | instruction is expanded within a function, and never reset, even | |
2428 | if all such instructions are optimized away. Use the | |
2429 | ix86_current_function_calls_tls_descriptor macro for a better | |
2430 | approximation. */ | |
2431 | int tls_descriptor_call_expanded_p; | |
7c800926 KT |
2432 | /* This value is used for amd64 targets and specifies the current abi |
2433 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
51212b32 | 2434 | enum calling_abi call_abi; |
fa1a0d02 JH |
2435 | }; |
2436 | ||
2437 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2438 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2439 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2440 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
922e3e33 | 2441 | #define ix86_current_function_needs_cld (cfun->machine->needs_cld) |
5bf5a10b AO |
2442 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2443 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2444 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2445 | calls are optimized away, we try to detect cases in which it was | |
2446 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2447 | verify whether there's any such instruction live by testing that | |
2448 | REG_SP is live. */ | |
2449 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2450 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
249e6b63 | 2451 | |
1bc7c5b6 ZW |
2452 | /* Control behavior of x86_file_start. */ |
2453 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2454 | #define X86_FILE_START_FLTUSED false | |
2455 | ||
7dcbf659 JH |
2456 | /* Flag to mark data that is in the large address area. */ |
2457 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2458 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2459 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2460 | |
2461 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2462 | have defined always, to avoid ifdefing. */ | |
2463 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2464 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2465 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2466 | ||
2467 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2468 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2469 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2470 | ||
e70444a8 HJ |
2471 | /* Model costs for vectorizer. */ |
2472 | ||
2473 | /* Cost of conditional branch. */ | |
2474 | #undef TARG_COND_BRANCH_COST | |
2475 | #define TARG_COND_BRANCH_COST ix86_cost->branch_cost | |
2476 | ||
4ae8027b UB |
2477 | /* Enum through the target specific extra va_list types. |
2478 | Please, do not iterate the base va_list type name. */ | |
35cbb299 | 2479 | #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ |
4ae8027b | 2480 | (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0) |
35cbb299 | 2481 | |
e70444a8 HJ |
2482 | /* Cost of any scalar operation, excluding load and store. */ |
2483 | #undef TARG_SCALAR_STMT_COST | |
2484 | #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost | |
2485 | ||
2486 | /* Cost of scalar load. */ | |
2487 | #undef TARG_SCALAR_LOAD_COST | |
2488 | #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost | |
2489 | ||
2490 | /* Cost of scalar store. */ | |
2491 | #undef TARG_SCALAR_STORE_COST | |
2492 | #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost | |
2493 | ||
2494 | /* Cost of any vector operation, excluding load, store or vector to scalar | |
4f3f76e6 | 2495 | operation. */ |
e70444a8 HJ |
2496 | #undef TARG_VEC_STMT_COST |
2497 | #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost | |
2498 | ||
2499 | /* Cost of vector to scalar operation. */ | |
2500 | #undef TARG_VEC_TO_SCALAR_COST | |
2501 | #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost | |
2502 | ||
2503 | /* Cost of scalar to vector operation. */ | |
2504 | #undef TARG_SCALAR_TO_VEC_COST | |
2505 | #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost | |
2506 | ||
2507 | /* Cost of aligned vector load. */ | |
2508 | #undef TARG_VEC_LOAD_COST | |
2509 | #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost | |
2510 | ||
2511 | /* Cost of misaligned vector load. */ | |
2512 | #undef TARG_VEC_UNALIGNED_LOAD_COST | |
2513 | #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost | |
2514 | ||
2515 | /* Cost of vector store. */ | |
2516 | #undef TARG_VEC_STORE_COST | |
2517 | #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost | |
2518 | ||
2519 | /* Cost of conditional taken branch for vectorizer cost model. */ | |
2520 | #undef TARG_COND_TAKEN_BRANCH_COST | |
2521 | #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost | |
2522 | ||
2523 | /* Cost of conditional not taken branch for vectorizer cost model. */ | |
2524 | #undef TARG_COND_NOT_TAKEN_BRANCH_COST | |
2525 | #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost | |
2526 | ||
c98f8742 JVA |
2527 | /* |
2528 | Local variables: | |
2529 | version-control: t | |
2530 | End: | |
2531 | */ |