]>
Commit | Line | Data |
---|---|---|
e075ae69 | 1 | /* Definitions of target machine for GNU compiler for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
d9a5f180 | 3 | 2001, 2002 Free Software Foundation, Inc. |
c98f8742 JVA |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
892a2d68 | 20 | Boston, MA 02111-1307, USA. */ |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
e075ae69 RH |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
c98f8742 | 36 | |
d4ba09c0 SC |
37 | /* Define the specific costs for a given cpu */ |
38 | ||
39 | struct processor_costs { | |
8b60264b KG |
40 | const int add; /* cost of an add instruction */ |
41 | const int lea; /* cost of a lea instruction */ | |
42 | const int shift_var; /* variable shift costs */ | |
43 | const int shift_const; /* constant shift costs */ | |
44 | const int mult_init; /* cost of starting a multiply */ | |
45 | const int mult_bit; /* cost of multiply per each bit set */ | |
46 | const int divide; /* cost of a divide/mod */ | |
44cf5b6a JH |
47 | int movsx; /* The cost of movsx operation. */ |
48 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
49 | const int large_insn; /* insns larger than this cost more */ |
50 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 51 | memory-to-memory move insns. */ |
8b60264b KG |
52 | const int movzbl_load; /* cost of loading using movzbl */ |
53 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
54 | in QImode, HImode and SImode relative |
55 | to reg-reg move (2). */ | |
8b60264b | 56 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 57 | in QImode, HImode and SImode */ |
8b60264b KG |
58 | const int fp_move; /* cost of reg,reg fld/fst */ |
59 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 60 | in SFmode, DFmode and XFmode */ |
8b60264b | 61 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 62 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
63 | const int mmx_move; /* cost of moving MMX register. */ |
64 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 65 | in SImode and DImode */ |
8b60264b | 66 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 67 | in SImode and DImode */ |
8b60264b KG |
68 | const int sse_move; /* cost of moving SSE register. */ |
69 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 70 | in SImode, DImode and TImode*/ |
8b60264b | 71 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 72 | in SImode, DImode and TImode*/ |
8b60264b | 73 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 74 | integer and vice versa. */ |
f4365627 JH |
75 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
76 | const int simultaneous_prefetches; /* number of parallel prefetch | |
77 | operations. */ | |
d4ba09c0 SC |
78 | }; |
79 | ||
8b60264b | 80 | extern const struct processor_costs *ix86_cost; |
d4ba09c0 | 81 | |
c98f8742 JVA |
82 | /* Run-time compilation parameters selecting different hardware subsets. */ |
83 | ||
84 | extern int target_flags; | |
85 | ||
86 | /* Macros used in the machine description to test the flags. */ | |
87 | ||
ddd5a7c1 | 88 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 89 | |
35b528be RS |
90 | #ifndef TARGET_CPU_DEFAULT |
91 | #define TARGET_CPU_DEFAULT 0 | |
92 | #endif | |
93 | ||
3b3c6a3f | 94 | /* Masks for the -m switches */ |
e075ae69 RH |
95 | #define MASK_80387 0x00000001 /* Hardware floating point */ |
96 | #define MASK_RTD 0x00000002 /* Use ret that pops args */ | |
97 | #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ | |
98 | #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ | |
99 | #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ | |
100 | #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ | |
101 | #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ | |
102 | #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ | |
103 | #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ | |
0dd0e980 JH |
104 | #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ |
105 | #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ | |
106 | #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ | |
107 | #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ | |
9ef1b13a RH |
108 | #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ |
109 | #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ | |
110 | #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ | |
111 | #define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */ | |
112 | #define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */ | |
113 | #define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */ | |
114 | #define MASK_64BIT 0x00080000 /* Produce 64bit code */ | |
115 | ||
116 | /* Unused: 0x03f0000 */ | |
117 | ||
c93e80a5 JH |
118 | /* ... overlap with subtarget options starts by 0x04000000. */ |
119 | #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ | |
3b3c6a3f MM |
120 | |
121 | /* Use the floating point instructions */ | |
122 | #define TARGET_80387 (target_flags & MASK_80387) | |
123 | ||
c98f8742 JVA |
124 | /* Compile using ret insn that pops args. |
125 | This will not work unless you use prototypes at least | |
fce5a9f2 | 126 | for all functions that can take varying numbers of args. */ |
3b3c6a3f MM |
127 | #define TARGET_RTD (target_flags & MASK_RTD) |
128 | ||
b08de47e MM |
129 | /* Align doubles to a two word boundary. This breaks compatibility with |
130 | the published ABI's for structures containing doubles, but produces | |
131 | faster code on the pentium. */ | |
132 | #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) | |
c98f8742 | 133 | |
f73ad30e JH |
134 | /* Use push instructions to save outgoing args. */ |
135 | #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) | |
136 | ||
137 | /* Accumulate stack adjustments to prologue/epilogue. */ | |
138 | #define TARGET_ACCUMULATE_OUTGOING_ARGS \ | |
139 | (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) | |
140 | ||
d7cd15e9 RS |
141 | /* Put uninitialized locals into bss, not data. |
142 | Meaningful only on svr3. */ | |
3b3c6a3f | 143 | #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) |
d7cd15e9 | 144 | |
c572e5ba JVA |
145 | /* Use IEEE floating point comparisons. These handle correctly the cases |
146 | where the result of a comparison is unordered. Normally SIGFPE is | |
147 | generated in such cases, in which case this isn't needed. */ | |
3b3c6a3f | 148 | #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) |
c572e5ba | 149 | |
8c2bf92a JVA |
150 | /* Functions that return a floating point value may return that value |
151 | in the 387 FPU or in 386 integer registers. If set, this flag causes | |
892a2d68 | 152 | the 387 to be used, which is compatible with most calling conventions. */ |
3b3c6a3f | 153 | #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) |
8c2bf92a | 154 | |
2b589241 | 155 | /* Long double is 128bit instead of 96bit, even when only 80bits are used. |
f5143c46 | 156 | This mode wastes cache, but avoid misaligned data accesses and simplifies |
2b589241 JH |
157 | address calculations. */ |
158 | #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) | |
159 | ||
099800e3 RK |
160 | /* Disable generation of FP sin, cos and sqrt operations for 387. |
161 | This is because FreeBSD lacks these in the math-emulator-code */ | |
3b3c6a3f MM |
162 | #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) |
163 | ||
2f2fa5b1 | 164 | /* Don't create frame pointers for leaf functions */ |
e075ae69 RH |
165 | #define TARGET_OMIT_LEAF_FRAME_POINTER \ |
166 | (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) | |
f6f58ba3 | 167 | |
3b3c6a3f | 168 | /* Debug GO_IF_LEGITIMATE_ADDRESS */ |
c93e80a5 | 169 | #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) |
3b3c6a3f | 170 | |
b08de47e | 171 | /* Debug FUNCTION_ARG macros */ |
c93e80a5 | 172 | #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) |
b08de47e | 173 | |
25f94bb5 | 174 | /* 64bit Sledgehammer mode */ |
0c2dc519 | 175 | #ifdef TARGET_BI_ARCH |
25f94bb5 | 176 | #define TARGET_64BIT (target_flags & MASK_64BIT) |
0c2dc519 | 177 | #else |
67adf6a9 | 178 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
179 | #define TARGET_64BIT 1 |
180 | #else | |
181 | #define TARGET_64BIT 0 | |
182 | #endif | |
183 | #endif | |
25f94bb5 | 184 | |
f7746310 SC |
185 | #define TARGET_386 (ix86_cpu == PROCESSOR_I386) |
186 | #define TARGET_486 (ix86_cpu == PROCESSOR_I486) | |
187 | #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) | |
3a0433fd | 188 | #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) |
a269a03c | 189 | #define TARGET_K6 (ix86_cpu == PROCESSOR_K6) |
309ada50 | 190 | #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) |
b4e89e2d | 191 | #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) |
a269a03c JC |
192 | |
193 | #define CPUMASK (1 << ix86_cpu) | |
194 | extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; | |
195 | extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; | |
ef6257cd | 196 | extern const int x86_branch_hints, x86_unroll_strlen; |
e075ae69 RH |
197 | extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; |
198 | extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; | |
199 | extern const int x86_use_cltd, x86_read_modify_write; | |
200 | extern const int x86_read_modify, x86_split_long_moves; | |
285464d0 | 201 | extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; |
d9f32422 | 202 | extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; |
0b5107cf | 203 | extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; |
bdeb029c | 204 | extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; |
0b5107cf | 205 | extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; |
c6036a37 | 206 | extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; |
b972dd02 | 207 | extern const int x86_epilogue_using_move, x86_decompose_lea; |
495333a6 | 208 | extern const int x86_arch_always_fancy_math_387, x86_shift1; |
f4365627 | 209 | extern int x86_prefetch_sse; |
a269a03c JC |
210 | |
211 | #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) | |
212 | #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) | |
213 | #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) | |
214 | #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) | |
215 | #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) | |
0644b628 JH |
216 | /* For sane SSE instruction set generation we need fcomi instruction. It is |
217 | safe to enable all CMOVE instructions. */ | |
218 | #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) | |
a269a03c | 219 | #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) |
ef6257cd | 220 | #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) |
a269a03c | 221 | #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) |
0d7d98ee | 222 | #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) |
e075ae69 RH |
223 | #define TARGET_MOVX (x86_movx & CPUMASK) |
224 | #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) | |
225 | #define TARGET_USE_LOOP (x86_use_loop & CPUMASK) | |
226 | #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) | |
227 | #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) | |
228 | #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) | |
229 | #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) | |
230 | #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) | |
231 | #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) | |
e9e80858 | 232 | #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) |
285464d0 | 233 | #define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK) |
f90800f8 | 234 | #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) |
d9f32422 JH |
235 | #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) |
236 | #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) | |
237 | #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) | |
238 | #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) | |
bdeb029c JH |
239 | #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) |
240 | #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) | |
241 | #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) | |
242 | #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) | |
0b5107cf JH |
243 | #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) |
244 | #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) | |
245 | #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) | |
c6036a37 JH |
246 | #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) |
247 | #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) | |
b972dd02 | 248 | #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) |
f4365627 | 249 | #define TARGET_PREFETCH_SSE (x86_prefetch_sse) |
495333a6 | 250 | #define TARGET_SHIFT1 (x86_shift1 & CPUMASK) |
a269a03c | 251 | |
8c9be447 | 252 | #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) |
3b3c6a3f | 253 | |
79f05c19 JH |
254 | #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) |
255 | #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) | |
256 | ||
c93e80a5 | 257 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
e075ae69 | 258 | |
446988df JH |
259 | #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) |
260 | #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) | |
965f5423 JH |
261 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) |
262 | #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ | |
263 | && (ix86_fpmath & FPMATH_387)) | |
a7180f70 | 264 | #define TARGET_MMX ((target_flags & MASK_MMX) != 0) |
47f339cf BS |
265 | #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) |
266 | #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) | |
a7180f70 | 267 | |
8362f420 JH |
268 | #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) |
269 | ||
f996902d RH |
270 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
271 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
272 | ||
a5d17ff3 PT |
273 | /* WARNING: Do not mark empty strings for translation, as calling |
274 | gettext on an empty string does NOT return an empty | |
275 | string. */ | |
276 | ||
277 | ||
e075ae69 | 278 | #define TARGET_SWITCHES \ |
047142d3 PT |
279 | { { "80387", MASK_80387, N_("Use hardware fp") }, \ |
280 | { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ | |
281 | { "hard-float", MASK_80387, N_("Use hardware fp") }, \ | |
282 | { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ | |
283 | { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ | |
a5d17ff3 PT |
284 | { "386", 0, "" /*Deprecated.*/}, \ |
285 | { "486", 0, "" /*Deprecated.*/}, \ | |
286 | { "pentium", 0, "" /*Deprecated.*/}, \ | |
287 | { "pentiumpro", 0, "" /*Deprecated.*/}, \ | |
288 | { "intel-syntax", 0, "" /*Deprecated.*/}, \ | |
289 | { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ | |
047142d3 PT |
290 | { "rtd", MASK_RTD, \ |
291 | N_("Alternate calling convention") }, \ | |
292 | { "no-rtd", -MASK_RTD, \ | |
293 | N_("Use normal calling convention") }, \ | |
e075ae69 | 294 | { "align-double", MASK_ALIGN_DOUBLE, \ |
047142d3 | 295 | N_("Align some doubles on dword boundary") }, \ |
e075ae69 | 296 | { "no-align-double", -MASK_ALIGN_DOUBLE, \ |
047142d3 | 297 | N_("Align doubles on word boundary") }, \ |
e075ae69 | 298 | { "svr3-shlib", MASK_SVR3_SHLIB, \ |
047142d3 | 299 | N_("Uninitialized locals in .bss") }, \ |
e075ae69 | 300 | { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ |
047142d3 | 301 | N_("Uninitialized locals in .data") }, \ |
e075ae69 | 302 | { "ieee-fp", MASK_IEEE_FP, \ |
047142d3 | 303 | N_("Use IEEE math for fp comparisons") }, \ |
e075ae69 | 304 | { "no-ieee-fp", -MASK_IEEE_FP, \ |
047142d3 | 305 | N_("Do not use IEEE math for fp comparisons") }, \ |
e075ae69 | 306 | { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ |
047142d3 | 307 | N_("Return values of functions in FPU registers") }, \ |
e075ae69 | 308 | { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ |
047142d3 | 309 | N_("Do not return values of functions in FPU registers")}, \ |
e075ae69 | 310 | { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ |
047142d3 | 311 | N_("Do not generate sin, cos, sqrt for FPU") }, \ |
e075ae69 | 312 | { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ |
047142d3 | 313 | N_("Generate sin, cos, sqrt for FPU")}, \ |
e075ae69 | 314 | { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ |
047142d3 | 315 | N_("Omit the frame pointer in leaf functions") }, \ |
e075ae69 | 316 | { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ |
047142d3 PT |
317 | { "stack-arg-probe", MASK_STACK_PROBE, \ |
318 | N_("Enable stack probing") }, \ | |
e075ae69 RH |
319 | { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ |
320 | { "windows", 0, 0 /* undocumented */ }, \ | |
321 | { "dll", 0, 0 /* undocumented */ }, \ | |
79f05c19 | 322 | { "align-stringops", -MASK_NO_ALIGN_STROPS, \ |
047142d3 | 323 | N_("Align destination of the string operations") }, \ |
79f05c19 | 324 | { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ |
047142d3 | 325 | N_("Do not align destination of the string operations") }, \ |
4be2e5d9 | 326 | { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ |
047142d3 | 327 | N_("Inline all known string operations") }, \ |
79f05c19 | 328 | { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ |
047142d3 | 329 | N_("Do not inline all known string operations") }, \ |
f73ad30e | 330 | { "push-args", -MASK_NO_PUSH_ARGS, \ |
047142d3 | 331 | N_("Use push instructions to save outgoing arguments") }, \ |
053f1126 | 332 | { "no-push-args", MASK_NO_PUSH_ARGS, \ |
047142d3 | 333 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 334 | { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 335 | N_("Use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 336 | { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 337 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 338 | { "mmx", MASK_MMX, \ |
b0287a90 | 339 | N_("Support MMX built-in functions") }, \ |
0dd0e980 | 340 | { "no-mmx", -MASK_MMX, \ |
b0287a90 | 341 | N_("Do not support MMX built-in functions") }, \ |
9ef1b13a | 342 | { "3dnow", MASK_3DNOW, \ |
b0287a90 | 343 | N_("Support 3DNow! built-in functions") }, \ |
9ef1b13a | 344 | { "no-3dnow", -MASK_3DNOW, \ |
b0287a90 | 345 | N_("Do not support 3DNow! built-in functions") }, \ |
9ef1b13a | 346 | { "sse", MASK_SSE, \ |
b0287a90 | 347 | N_("Support MMX and SSE built-in functions and code generation") }, \ |
9ef1b13a | 348 | { "no-sse", -MASK_SSE, \ |
b0287a90 | 349 | N_("Do not support MMX and SSE built-in functions and code generation") },\ |
9ef1b13a | 350 | { "sse2", MASK_SSE2, \ |
b0287a90 | 351 | N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
9ef1b13a | 352 | { "no-sse2", -MASK_SSE2, \ |
b0287a90 | 353 | N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
2b589241 | 354 | { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 355 | N_("sizeof(long double) is 16") }, \ |
2b589241 | 356 | { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 357 | N_("sizeof(long double) is 12") }, \ |
25f94bb5 JH |
358 | { "64", MASK_64BIT, \ |
359 | N_("Generate 64bit x86-64 code") }, \ | |
360 | { "32", -MASK_64BIT, \ | |
361 | N_("Generate 32bit i386 code") }, \ | |
8362f420 JH |
362 | { "red-zone", -MASK_NO_RED_ZONE, \ |
363 | N_("Use red-zone in the x86-64 code") }, \ | |
364 | { "no-red-zone", MASK_NO_RED_ZONE, \ | |
4cba3b67 | 365 | N_("Do not use red-zone in the x86-64 code") }, \ |
e075ae69 | 366 | SUBTARGET_SWITCHES \ |
67adf6a9 | 367 | { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }} |
241e1a89 | 368 | |
67adf6a9 RH |
369 | #ifndef TARGET_64BIT_DEFAULT |
370 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 JH |
371 | #endif |
372 | ||
0ed4a390 JL |
373 | /* Once GDB has been enhanced to deal with functions without frame |
374 | pointers, we can change this to allow for elimination of | |
375 | the frame pointer in leaf functions. */ | |
376 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 377 | |
b069de3b SS |
378 | /* This is not really a target flag, but is done this way so that |
379 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
380 | redefines this to 1. */ | |
381 | #define TARGET_MACHO 0 | |
382 | ||
f5316dfe MM |
383 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
384 | command options that have values. Its definition is an | |
385 | initializer with a subgrouping for each command option. | |
386 | ||
387 | Each subgrouping contains a string constant, that defines the | |
388 | fixed part of the option name, and the address of a variable. The | |
389 | variable, type `char *', is set to the variable part of the given | |
390 | option if the fixed part matches. The actual option name is made | |
391 | by appending `-m' to the specified name. */ | |
e075ae69 RH |
392 | #define TARGET_OPTIONS \ |
393 | { { "cpu=", &ix86_cpu_string, \ | |
047142d3 | 394 | N_("Schedule code for given CPU")}, \ |
965f5423 JH |
395 | { "fpmath=", &ix86_fpmath_string, \ |
396 | N_("Generate floating point mathematics using given instruction set")},\ | |
e075ae69 | 397 | { "arch=", &ix86_arch_string, \ |
047142d3 | 398 | N_("Generate code for given CPU")}, \ |
e075ae69 | 399 | { "regparm=", &ix86_regparm_string, \ |
047142d3 | 400 | N_("Number of registers used to pass integer arguments") }, \ |
e075ae69 | 401 | { "align-loops=", &ix86_align_loops_string, \ |
047142d3 | 402 | N_("Loop code aligned to this power of 2") }, \ |
e075ae69 | 403 | { "align-jumps=", &ix86_align_jumps_string, \ |
047142d3 | 404 | N_("Jump targets are aligned to this power of 2") }, \ |
e075ae69 | 405 | { "align-functions=", &ix86_align_funcs_string, \ |
047142d3 | 406 | N_("Function starts are aligned to this power of 2") }, \ |
e075ae69 RH |
407 | { "preferred-stack-boundary=", \ |
408 | &ix86_preferred_stack_boundary_string, \ | |
047142d3 | 409 | N_("Attempt to keep stack aligned to this power of 2") }, \ |
e075ae69 | 410 | { "branch-cost=", &ix86_branch_cost_string, \ |
047142d3 | 411 | N_("Branches are this expensive (1-5, arbitrary units)") }, \ |
6189a572 JH |
412 | { "cmodel=", &ix86_cmodel_string, \ |
413 | N_("Use given x86-64 code model") }, \ | |
c93e80a5 | 414 | { "debug-arg", &ix86_debug_arg_string, \ |
a5d17ff3 | 415 | "" /* Undocumented. */ }, \ |
c93e80a5 | 416 | { "debug-addr", &ix86_debug_addr_string, \ |
a5d17ff3 | 417 | "" /* Undocumented. */ }, \ |
c93e80a5 JH |
418 | { "asm=", &ix86_asm_string, \ |
419 | N_("Use given assembler dialect") }, \ | |
f996902d RH |
420 | { "tls-dialect=", &ix86_tls_dialect_string, \ |
421 | N_("Use given thread-local storage dialect") }, \ | |
e075ae69 | 422 | SUBTARGET_OPTIONS \ |
b08de47e | 423 | } |
f5316dfe MM |
424 | |
425 | /* Sometimes certain combinations of command options do not make | |
426 | sense on a particular target machine. You can define a macro | |
427 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
428 | defined, is executed once just after all the command options have | |
429 | been parsed. | |
430 | ||
431 | Don't use this macro to turn on various extra optimizations for | |
432 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
433 | ||
434 | #define OVERRIDE_OPTIONS override_options () | |
435 | ||
436 | /* These are meant to be redefined in the host dependent files */ | |
95393dfd | 437 | #define SUBTARGET_SWITCHES |
f5316dfe | 438 | #define SUBTARGET_OPTIONS |
95393dfd | 439 | |
d4ba09c0 | 440 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
441 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
442 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 443 | |
241e1a89 SC |
444 | /* Specs for the compiler proper */ |
445 | ||
628714d8 RK |
446 | #ifndef CC1_CPU_SPEC |
447 | #define CC1_CPU_SPEC "\ | |
241e1a89 | 448 | %{!mcpu*: \ |
4a88a060 | 449 | %{m386:-mcpu=i386 \ |
3f0e0fa2 | 450 | %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ |
4a88a060 | 451 | %{m486:-mcpu=i486 \ |
3f0e0fa2 | 452 | %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ |
4a88a060 | 453 | %{mpentium:-mcpu=pentium \ |
3f0e0fa2 | 454 | %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ |
4a88a060 | 455 | %{mpentiumpro:-mcpu=pentiumpro \ |
c93e80a5 JH |
456 | %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ |
457 | %{mintel-syntax:-masm=intel \ | |
458 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
459 | %{mno-intel-syntax:-masm=att \ | |
460 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
241e1a89 | 461 | #endif |
c98f8742 | 462 | \f |
30efe578 | 463 | /* Target CPU builtins. */ |
1ba7b414 NB |
464 | #define TARGET_CPU_CPP_BUILTINS() \ |
465 | do \ | |
466 | { \ | |
467 | size_t arch_len = strlen (ix86_arch_string); \ | |
468 | size_t cpu_len = strlen (ix86_cpu_string); \ | |
469 | int last_arch_char = ix86_arch_string[arch_len - 1]; \ | |
470 | int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \ | |
471 | \ | |
472 | if (TARGET_64BIT) \ | |
473 | { \ | |
474 | builtin_assert ("cpu=x86_64"); \ | |
475 | builtin_assert ("machine=x86_64"); \ | |
476 | builtin_define ("__x86_64"); \ | |
477 | builtin_define ("__x86_64__"); \ | |
478 | } \ | |
479 | else \ | |
480 | { \ | |
481 | builtin_assert ("cpu=i386"); \ | |
482 | builtin_assert ("machine=i386"); \ | |
483 | builtin_define_std ("i386"); \ | |
484 | } \ | |
485 | \ | |
486 | /* Built-ins based on -mcpu= (or -march= if no \ | |
487 | CPU given). */ \ | |
488 | if (TARGET_386) \ | |
489 | builtin_define ("__tune_i386__"); \ | |
490 | else if (TARGET_486) \ | |
491 | builtin_define ("__tune_i486__"); \ | |
492 | else if (TARGET_PENTIUM) \ | |
493 | { \ | |
494 | builtin_define ("__tune_i586__"); \ | |
495 | builtin_define ("__tune_pentium__"); \ | |
496 | if (last_cpu_char == 'x') \ | |
497 | builtin_define ("__tune_pentium_mmx__"); \ | |
498 | } \ | |
499 | else if (TARGET_PENTIUMPRO) \ | |
500 | { \ | |
501 | builtin_define ("__tune_i686__"); \ | |
502 | builtin_define ("__tune_pentiumpro__"); \ | |
503 | } \ | |
504 | else if (TARGET_K6) \ | |
505 | { \ | |
506 | builtin_define ("__tune_k6__"); \ | |
507 | if (last_cpu_char == '2') \ | |
508 | builtin_define ("__tune_k6_2__"); \ | |
509 | else if (last_cpu_char == '3') \ | |
510 | builtin_define ("__tune_k6_3__"); \ | |
511 | } \ | |
512 | else if (TARGET_ATHLON) \ | |
513 | { \ | |
514 | builtin_define ("__tune_athlon__"); \ | |
515 | /* Only plain "athlon" lacks SSE. */ \ | |
516 | if (last_cpu_char != 'n') \ | |
517 | builtin_define ("__tune_athlon_sse__"); \ | |
518 | } \ | |
519 | else if (TARGET_PENTIUM4) \ | |
520 | builtin_define ("__tune_pentium4__"); \ | |
521 | \ | |
522 | if (TARGET_MMX) \ | |
523 | builtin_define ("__MMX__"); \ | |
524 | if (TARGET_3DNOW) \ | |
525 | builtin_define ("__3dNOW__"); \ | |
526 | if (TARGET_3DNOW_A) \ | |
527 | builtin_define ("__3dNOW_A__"); \ | |
528 | if (TARGET_SSE) \ | |
529 | builtin_define ("__SSE__"); \ | |
530 | if (TARGET_SSE2) \ | |
531 | builtin_define ("__SSE2__"); \ | |
48ddd46c JH |
532 | if (TARGET_SSE_MATH && TARGET_SSE) \ |
533 | builtin_define ("__SSE_MATH__"); \ | |
534 | if (TARGET_SSE_MATH && TARGET_SSE2) \ | |
535 | builtin_define ("__SSE2_MATH__"); \ | |
1ba7b414 NB |
536 | \ |
537 | /* Built-ins based on -march=. */ \ | |
538 | if (ix86_arch == PROCESSOR_I486) \ | |
539 | { \ | |
540 | builtin_define ("__i486"); \ | |
541 | builtin_define ("__i486__"); \ | |
542 | } \ | |
543 | else if (ix86_arch == PROCESSOR_PENTIUM) \ | |
544 | { \ | |
545 | builtin_define ("__i586"); \ | |
546 | builtin_define ("__i586__"); \ | |
547 | builtin_define ("__pentium"); \ | |
548 | builtin_define ("__pentium__"); \ | |
549 | if (last_arch_char == 'x') \ | |
550 | builtin_define ("__pentium_mmx__"); \ | |
551 | } \ | |
552 | else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ | |
553 | { \ | |
554 | builtin_define ("__i686"); \ | |
555 | builtin_define ("__i686__"); \ | |
556 | builtin_define ("__pentiumpro"); \ | |
557 | builtin_define ("__pentiumpro__"); \ | |
558 | } \ | |
559 | else if (ix86_arch == PROCESSOR_K6) \ | |
560 | { \ | |
561 | \ | |
562 | builtin_define ("__k6"); \ | |
563 | builtin_define ("__k6__"); \ | |
564 | if (last_arch_char == '2') \ | |
565 | builtin_define ("__k6_2__"); \ | |
566 | else if (last_arch_char == '3') \ | |
567 | builtin_define ("__k6_3__"); \ | |
568 | } \ | |
569 | else if (ix86_arch == PROCESSOR_ATHLON) \ | |
570 | { \ | |
571 | builtin_define ("__athlon"); \ | |
572 | builtin_define ("__athlon__"); \ | |
573 | /* Only plain "athlon" lacks SSE. */ \ | |
574 | if (last_arch_char != 'n') \ | |
575 | builtin_define ("__athlon_sse__"); \ | |
576 | } \ | |
577 | else if (ix86_arch == PROCESSOR_PENTIUM4) \ | |
578 | { \ | |
579 | builtin_define ("__pentium4"); \ | |
580 | builtin_define ("__pentium4__"); \ | |
581 | } \ | |
582 | } \ | |
30efe578 NB |
583 | while (0) |
584 | ||
f4365627 JH |
585 | #define TARGET_CPU_DEFAULT_i386 0 |
586 | #define TARGET_CPU_DEFAULT_i486 1 | |
587 | #define TARGET_CPU_DEFAULT_pentium 2 | |
91d2f4ba JH |
588 | #define TARGET_CPU_DEFAULT_pentium_mmx 3 |
589 | #define TARGET_CPU_DEFAULT_pentiumpro 4 | |
590 | #define TARGET_CPU_DEFAULT_pentium2 5 | |
591 | #define TARGET_CPU_DEFAULT_pentium3 6 | |
592 | #define TARGET_CPU_DEFAULT_pentium4 7 | |
593 | #define TARGET_CPU_DEFAULT_k6 8 | |
594 | #define TARGET_CPU_DEFAULT_k6_2 9 | |
595 | #define TARGET_CPU_DEFAULT_k6_3 10 | |
596 | #define TARGET_CPU_DEFAULT_athlon 11 | |
597 | #define TARGET_CPU_DEFAULT_athlon_sse 12 | |
f4365627 JH |
598 | |
599 | #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ | |
600 | "pentiumpro", "pentium2", "pentium3", \ | |
601 | "pentium4", "k6", "k6-2", "k6-3",\ | |
602 | "athlon", "athlon-4"} | |
0c2dc519 | 603 | |
628714d8 | 604 | #ifndef CC1_SPEC |
8015b78d | 605 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
606 | #endif |
607 | ||
608 | /* This macro defines names of additional specifications to put in the | |
609 | specs that can be used in various specifications like CC1_SPEC. Its | |
610 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
611 | |
612 | Each subgrouping contains a string constant, that defines the | |
613 | specification name, and a string constant that used by the GNU CC driver | |
614 | program. | |
615 | ||
616 | Do not define this macro if it does not need to do anything. */ | |
617 | ||
618 | #ifndef SUBTARGET_EXTRA_SPECS | |
619 | #define SUBTARGET_EXTRA_SPECS | |
620 | #endif | |
621 | ||
622 | #define EXTRA_SPECS \ | |
628714d8 | 623 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
624 | SUBTARGET_EXTRA_SPECS |
625 | \f | |
c98f8742 JVA |
626 | /* target machine storage layout */ |
627 | ||
2b589241 | 628 | /* Define for XFmode or TFmode extended real floating point support. |
2b589241 | 629 | The XFmode is specified by i386 ABI, while TFmode may be faster |
3dc85dfb | 630 | due to alignment and simplifications in the address calculations. */ |
2b589241 JH |
631 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) |
632 | #define MAX_LONG_DOUBLE_TYPE_SIZE 128 | |
65d9c0ab JH |
633 | #ifdef __x86_64__ |
634 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
635 | #else | |
636 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 | |
637 | #endif | |
2b589241 | 638 | |
d57a4b98 RH |
639 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
640 | FPU, assume that the fpcw is set to extended precision; when using | |
641 | only SSE, rounding is correct; when using both SSE and the FPU, | |
642 | the rounding precision is indeterminate, since either may be chosen | |
643 | apparently at random. */ | |
644 | #define TARGET_FLT_EVAL_METHOD \ | |
645 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2) | |
0038aea6 | 646 | |
65d9c0ab JH |
647 | #define SHORT_TYPE_SIZE 16 |
648 | #define INT_TYPE_SIZE 32 | |
649 | #define FLOAT_TYPE_SIZE 32 | |
650 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
2faf6b96 | 651 | #define MAX_WCHAR_TYPE_SIZE 32 |
65d9c0ab JH |
652 | #define DOUBLE_TYPE_SIZE 64 |
653 | #define LONG_LONG_TYPE_SIZE 64 | |
654 | ||
67adf6a9 | 655 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 JH |
656 | #define MAX_BITS_PER_WORD 64 |
657 | #define MAX_LONG_TYPE_SIZE 64 | |
658 | #else | |
659 | #define MAX_BITS_PER_WORD 32 | |
660 | #define MAX_LONG_TYPE_SIZE 32 | |
661 | #endif | |
662 | ||
c98f8742 JVA |
663 | /* Define this if most significant byte of a word is the lowest numbered. */ |
664 | /* That is true on the 80386. */ | |
665 | ||
666 | #define BITS_BIG_ENDIAN 0 | |
667 | ||
668 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
669 | /* That is not true on the 80386. */ | |
670 | #define BYTES_BIG_ENDIAN 0 | |
671 | ||
672 | /* Define this if most significant word of a multiword number is the lowest | |
673 | numbered. */ | |
674 | /* Not true for 80386 */ | |
675 | #define WORDS_BIG_ENDIAN 0 | |
676 | ||
c98f8742 | 677 | /* Width of a word, in units (bytes). */ |
65d9c0ab JH |
678 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
679 | #define MIN_UNITS_PER_WORD 4 | |
c98f8742 | 680 | |
c98f8742 | 681 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 682 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 683 | |
e075ae69 | 684 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
65d9c0ab | 685 | #define STACK_BOUNDARY BITS_PER_WORD |
c98f8742 | 686 | |
3af4bd89 JH |
687 | /* Boundary (in *bits*) on which the stack pointer preferrs to be |
688 | aligned; the compiler cannot rely on having this alignment. */ | |
e075ae69 | 689 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 690 | |
1d482056 RH |
691 | /* As of July 2001, many runtimes to not align the stack properly when |
692 | entering main. This causes expand_main_function to forcably align | |
693 | the stack, which results in aligned frames for functions called from | |
694 | main, though it does nothing for the alignment of main itself. */ | |
695 | #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ | |
14f73b5a | 696 | (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) |
1d482056 | 697 | |
892a2d68 | 698 | /* Allocation boundary for the code of a function. */ |
3e18fdf6 | 699 | #define FUNCTION_BOUNDARY 16 |
c98f8742 | 700 | |
892a2d68 | 701 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 702 | |
65d9c0ab | 703 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
704 | |
705 | /* Minimum size in bits of the largest boundary to which any | |
706 | and all fundamental data types supported by the hardware | |
707 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 708 | rounder than this. |
fce5a9f2 | 709 | |
3e18fdf6 | 710 | Pentium+ preferrs DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
711 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
712 | ||
713 | #define BIGGEST_ALIGNMENT 128 | |
714 | ||
a7180f70 BS |
715 | /* Decide whether a variable of mode MODE must be 128 bit aligned. */ |
716 | #define ALIGN_MODE_128(MODE) \ | |
2b589241 JH |
717 | ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \ |
718 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
a7180f70 | 719 | |
17f24ff0 | 720 | /* The published ABIs say that doubles should be aligned on word |
6fc605d8 ZW |
721 | boundaries, so lower the aligment for structure fields unless |
722 | -malign-double is set. */ | |
e932b21b | 723 | |
e83f3cff RH |
724 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
725 | supports no vector modes, cut out the complexity and fall back | |
726 | on BIGGEST_FIELD_ALIGNMENT. */ | |
727 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
728 | #ifdef __x86_64__ |
729 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
730 | #else | |
e83f3cff | 731 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 732 | #endif |
e83f3cff | 733 | #else |
e932b21b JH |
734 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
735 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 736 | #endif |
c98f8742 | 737 | |
e5e8a8bf | 738 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 739 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
740 | and ALIGN is the alignment that the object would ordinarily have. |
741 | The value of this macro is used instead of that alignment to align | |
742 | the object. | |
743 | ||
744 | If this macro is not defined, then ALIGN is used. | |
745 | ||
746 | The typical use of this macro is to increase alignment for string | |
747 | constants to be word aligned so that `strcpy' calls that copy | |
748 | constants can be done inline. */ | |
749 | ||
d9a5f180 | 750 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 751 | |
8a022443 JW |
752 | /* If defined, a C expression to compute the alignment for a static |
753 | variable. TYPE is the data type, and ALIGN is the alignment that | |
754 | the object would ordinarily have. The value of this macro is used | |
755 | instead of that alignment to align the object. | |
756 | ||
757 | If this macro is not defined, then ALIGN is used. | |
758 | ||
759 | One use of this macro is to increase alignment of medium-size | |
760 | data to make it all fit in fewer cache lines. Another is to | |
761 | cause character arrays to be word-aligned so that `strcpy' calls | |
762 | that copy constants to character arrays can be done inline. */ | |
763 | ||
d9a5f180 | 764 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
765 | |
766 | /* If defined, a C expression to compute the alignment for a local | |
767 | variable. TYPE is the data type, and ALIGN is the alignment that | |
768 | the object would ordinarily have. The value of this macro is used | |
769 | instead of that alignment to align the object. | |
770 | ||
771 | If this macro is not defined, then ALIGN is used. | |
772 | ||
773 | One use of this macro is to increase alignment of medium-size | |
774 | data to make it all fit in fewer cache lines. */ | |
775 | ||
d9a5f180 | 776 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) |
8a022443 | 777 | |
53c17031 JH |
778 | /* If defined, a C expression that gives the alignment boundary, in |
779 | bits, of an argument with the specified mode and type. If it is | |
780 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
781 | ||
d9a5f180 GS |
782 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
783 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 784 | |
9cd10576 | 785 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 786 | when given unaligned data. */ |
b4ac57ab | 787 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
788 | |
789 | /* If bit field type is int, don't let it cross an int, | |
790 | and give entire struct the alignment of an int. */ | |
43a88a8c | 791 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 792 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
793 | \f |
794 | /* Standard register usage. */ | |
795 | ||
796 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 797 | for details. */ |
c98f8742 JVA |
798 | |
799 | #define STACK_REGS | |
d9a5f180 GS |
800 | #define IS_STACK_MODE(MODE) \ |
801 | ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ | |
802 | || (MODE) == TFmode) | |
c98f8742 JVA |
803 | |
804 | /* Number of actual hardware registers. | |
805 | The hardware registers are assigned numbers for the compiler | |
806 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
807 | All registers that the compiler knows about must be given numbers, | |
808 | even those that are not normally considered general registers. | |
809 | ||
810 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
811 | We number the floating point registers 8-15. | |
812 | Note that registers 0-7 can be accessed as a short or int, | |
813 | while only 0-3 may be used with byte `mov' instructions. | |
814 | ||
815 | Reg 16 does not correspond to any hardware register, but instead | |
816 | appears in the RTL as an argument pointer prior to reload, and is | |
817 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 818 | pointer. */ |
c98f8742 | 819 | |
3f3f2124 | 820 | #define FIRST_PSEUDO_REGISTER 53 |
c98f8742 | 821 | |
3073d01c ML |
822 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
823 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
824 | ||
825 | #define DWARF_FRAME_REGISTERS 17 | |
826 | ||
c98f8742 JVA |
827 | /* 1 for registers that have pervasive standard uses |
828 | and are not available for the register allocator. | |
3f3f2124 | 829 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 830 | |
3f3f2124 JH |
831 | The value is an mask - bit 1 is set for fixed registers |
832 | for 32bit target, while 2 is set for fixed registers for 64bit. | |
833 | Proper value is computed in the CONDITIONAL_REGISTER_USAGE. | |
834 | */ | |
a7180f70 BS |
835 | #define FIXED_REGISTERS \ |
836 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3f3f2124 | 837 | { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ |
a7180f70 | 838 | /*arg,flags,fpsr,dir,frame*/ \ |
3f3f2124 | 839 | 3, 3, 3, 3, 3, \ |
a7180f70 BS |
840 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
841 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
842 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
3f3f2124 JH |
843 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
844 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
845 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
846 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
847 | 1, 1, 1, 1, 1, 1, 1, 1} | |
fce5a9f2 | 848 | |
c98f8742 JVA |
849 | |
850 | /* 1 for registers not available across function calls. | |
851 | These must include the FIXED_REGISTERS and also any | |
852 | registers that can be used without being saved. | |
853 | The latter must include the registers where values are returned | |
854 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
855 | Aside from that, you can include as many other registers as you like. |
856 | ||
3f3f2124 JH |
857 | The value is an mask - bit 1 is set for call used |
858 | for 32bit target, while 2 is set for call used for 64bit. | |
859 | Proper value is computed in the CONDITIONAL_REGISTER_USAGE. | |
860 | */ | |
a7180f70 BS |
861 | #define CALL_USED_REGISTERS \ |
862 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3f3f2124 | 863 | { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ |
a7180f70 | 864 | /*arg,flags,fpsr,dir,frame*/ \ |
3f3f2124 | 865 | 3, 3, 3, 3, 3, \ |
a7180f70 | 866 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
3f3f2124 | 867 | 3, 3, 3, 3, 3, 3, 3, 3, \ |
a7180f70 | 868 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
3f3f2124 JH |
869 | 3, 3, 3, 3, 3, 3, 3, 3, \ |
870 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
871 | 3, 3, 3, 3, 1, 1, 1, 1, \ | |
872 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
873 | 3, 3, 3, 3, 3, 3, 3, 3} \ | |
c98f8742 | 874 | |
3b3c6a3f MM |
875 | /* Order in which to allocate registers. Each register must be |
876 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
877 | late and fixed registers last. Note that, in general, we prefer | |
878 | registers listed in CALL_USED_REGISTERS, keeping the others | |
879 | available for storage of persistent values. | |
880 | ||
162f023b JH |
881 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
882 | so this is just empty initializer for array. */ | |
3b3c6a3f | 883 | |
162f023b JH |
884 | #define REG_ALLOC_ORDER \ |
885 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
886 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
887 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
888 | 48, 49, 50, 51, 52 } | |
3b3c6a3f | 889 | |
162f023b JH |
890 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
891 | to be rearranged based on a particular function. When using sse math, | |
892 | we want to allocase SSE before x87 registers and vice vera. */ | |
3b3c6a3f | 893 | |
162f023b | 894 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 895 | |
f5316dfe | 896 | |
c98f8742 | 897 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 898 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 899 | do { \ |
3f3f2124 JH |
900 | int i; \ |
901 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
902 | { \ | |
903 | fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ | |
904 | call_used_regs[i] = (call_used_regs[i] \ | |
905 | & (TARGET_64BIT ? 2 : 1)) != 0; \ | |
906 | } \ | |
5b43fed1 | 907 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
a7180f70 BS |
908 | { \ |
909 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
910 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
911 | } \ | |
912 | if (! TARGET_MMX) \ | |
913 | { \ | |
914 | int i; \ | |
915 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
916 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
917 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
918 | } \ | |
919 | if (! TARGET_SSE) \ | |
920 | { \ | |
921 | int i; \ | |
922 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
923 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
924 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
925 | } \ | |
926 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
927 | { \ | |
928 | int i; \ | |
929 | HARD_REG_SET x; \ | |
930 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
931 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
932 | if (TEST_HARD_REG_BIT (x, i)) \ | |
933 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
934 | } \ | |
d9a5f180 | 935 | } while (0) |
c98f8742 JVA |
936 | |
937 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
938 | to hold something of mode MODE. | |
939 | This is ordinarily the length in words of a value of mode MODE | |
940 | but can be less for certain modes in special long registers. | |
941 | ||
fce5a9f2 | 942 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
943 | registers. And only registers 0-3 may have mov byte instructions |
944 | applied to them. | |
945 | */ | |
946 | ||
947 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
92d0fb09 JH |
948 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
949 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
d9a5f180 | 950 | : ((MODE) == TFmode \ |
92d0fb09 | 951 | ? (TARGET_64BIT ? 2 : 3) \ |
d9a5f180 | 952 | : (MODE) == TCmode \ |
92d0fb09 | 953 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 954 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 955 | |
fbe5eb6d BS |
956 | #define VALID_SSE2_REG_MODE(MODE) \ |
957 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
958 | || (MODE) == V2DImode) | |
959 | ||
d9a5f180 GS |
960 | #define VALID_SSE_REG_MODE(MODE) \ |
961 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
962 | || (MODE) == SFmode \ | |
fbe5eb6d BS |
963 | /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ |
964 | || VALID_SSE2_REG_MODE (MODE) \ | |
141e454b | 965 | || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) |
a7180f70 | 966 | |
47f339cf BS |
967 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
968 | ((MODE) == V2SFmode || (MODE) == SFmode) | |
969 | ||
d9a5f180 GS |
970 | #define VALID_MMX_REG_MODE(MODE) \ |
971 | ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ | |
a7180f70 BS |
972 | || (MODE) == V2SImode || (MODE) == SImode) |
973 | ||
974 | #define VECTOR_MODE_SUPPORTED_P(MODE) \ | |
975 | (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ | |
47f339cf BS |
976 | : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ |
977 | : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) | |
a7180f70 | 978 | |
d9a5f180 GS |
979 | #define VALID_FP_MODE_P(MODE) \ |
980 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ | |
981 | || (!TARGET_64BIT && (MODE) == XFmode) \ | |
982 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ | |
983 | || (!TARGET_64BIT && (MODE) == XCmode)) | |
a946dd00 | 984 | |
d9a5f180 GS |
985 | #define VALID_INT_MODE_P(MODE) \ |
986 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
987 | || (MODE) == DImode \ | |
988 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
989 | || (MODE) == CDImode \ | |
990 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) | |
a946dd00 | 991 | |
e075ae69 | 992 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 993 | |
a946dd00 | 994 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 995 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
996 | |
997 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
998 | when one has mode MODE1 and one has mode MODE2. | |
999 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1000 | for any hard reg, then this must be 0 for correct output. */ | |
1001 | ||
95912252 RH |
1002 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
1003 | ((MODE1) == (MODE2) \ | |
d2836273 JH |
1004 | || (((MODE1) == HImode || (MODE1) == SImode \ |
1005 | || ((MODE1) == QImode \ | |
1006 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ | |
1007 | || ((MODE1) == DImode && TARGET_64BIT)) \ | |
1008 | && ((MODE2) == HImode || (MODE2) == SImode \ | |
1009 | || ((MODE1) == QImode \ | |
1010 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ | |
1011 | || ((MODE2) == DImode && TARGET_64BIT)))) | |
1012 | ||
c98f8742 | 1013 | |
e075ae69 | 1014 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1015 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1016 | |
787dc842 JH |
1017 | Kill any attempts to combine saving of modes. */ |
1018 | ||
d9a5f180 GS |
1019 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1020 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1021 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
1022 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ | |
1023 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ | |
1024 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
d2836273 | 1025 | : (MODE)) |
c98f8742 JVA |
1026 | /* Specify the registers used for certain standard purposes. |
1027 | The values of these macros are register numbers. */ | |
1028 | ||
1029 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1030 | register. The ordinary mov instructions won't work */ | |
1031 | /* #define PC_REGNUM */ | |
1032 | ||
1033 | /* Register to use for pushing function arguments. */ | |
1034 | #define STACK_POINTER_REGNUM 7 | |
1035 | ||
1036 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1037 | #define HARD_FRAME_POINTER_REGNUM 6 |
1038 | ||
1039 | /* Base register for access to local variables of the function. */ | |
1040 | #define FRAME_POINTER_REGNUM 20 | |
c98f8742 JVA |
1041 | |
1042 | /* First floating point reg */ | |
1043 | #define FIRST_FLOAT_REG 8 | |
1044 | ||
1045 | /* First & last stack-like regs */ | |
1046 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1047 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1048 | ||
e075ae69 RH |
1049 | #define FLAGS_REG 17 |
1050 | #define FPSR_REG 18 | |
7c7ef435 | 1051 | #define DIRFLAG_REG 19 |
e075ae69 | 1052 | |
a7180f70 BS |
1053 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1054 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1055 | |
a7180f70 BS |
1056 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1057 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1058 | ||
3f3f2124 JH |
1059 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1060 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1061 | ||
1062 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1063 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1064 | ||
c98f8742 JVA |
1065 | /* Value should be nonzero if functions must have frame pointers. |
1066 | Zero means the frame pointer need not be set up (and parms | |
1067 | may be accessed via the stack pointer) in functions that seem suitable. | |
1068 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
1069 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1070 | ||
1071 | /* Override this in other tm.h files to cope with various OS losage | |
1072 | requiring a frame pointer. */ | |
1073 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1074 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1075 | #endif | |
1076 | ||
1077 | /* Make sure we can access arbitrary call frames. */ | |
1078 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1079 | |
1080 | /* Base register for access to arguments of the function. */ | |
1081 | #define ARG_POINTER_REGNUM 16 | |
1082 | ||
d2836273 JH |
1083 | /* Register in which static-chain is passed to a function. |
1084 | We do use ECX as static chain register for 32 bit ABI. On the | |
1085 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
1086 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) | |
c98f8742 JVA |
1087 | |
1088 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1089 | code access to data items. We don't use PIC pointer for 64bit |
1090 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1091 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1092 | |
1093 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1094 | the pic register when possible. The change is visible after the | |
1095 | prologue has been emitted. */ | |
1096 | ||
1097 | #define REAL_PIC_OFFSET_TABLE_REGNUM 3 | |
1098 | ||
1099 | #define PIC_OFFSET_TABLE_REGNUM \ | |
1100 | (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ | |
1101 | : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
1102 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1103 | |
5fc0e5df KW |
1104 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1105 | ||
c98f8742 JVA |
1106 | /* Register in which address to store a structure value |
1107 | arrives in the function. On the 386, the prologue | |
1108 | copies this from the stack to register %eax. */ | |
1109 | #define STRUCT_VALUE_INCOMING 0 | |
1110 | ||
1111 | /* Place in which caller passes the structure value address. | |
1112 | 0 means push the value on the stack like an argument. */ | |
1113 | #define STRUCT_VALUE 0 | |
713225d4 MM |
1114 | |
1115 | /* A C expression which can inhibit the returning of certain function | |
1116 | values in registers, based on the type of value. A nonzero value | |
1117 | says to return the function value in memory, just as large | |
1118 | structures are always returned. Here TYPE will be a C expression | |
1119 | of type `tree', representing the data type of the value. | |
1120 | ||
1121 | Note that values of mode `BLKmode' must be explicitly handled by | |
1122 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
1123 | regardless of this macro. On most systems, it is possible to | |
1124 | leave the macro undefined; this causes a default definition to be | |
1125 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
1126 | otherwise. | |
1127 | ||
1128 | Do not use this macro to indicate that structures and unions | |
1129 | should always be returned in memory. You should instead use | |
1130 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
1131 | ||
d9a5f180 | 1132 | #define RETURN_IN_MEMORY(TYPE) \ |
53c17031 | 1133 | ix86_return_in_memory (TYPE) |
713225d4 | 1134 | |
c98f8742 JVA |
1135 | \f |
1136 | /* Define the classes of registers for register constraints in the | |
1137 | machine description. Also define ranges of constants. | |
1138 | ||
1139 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1140 | If there is more than one class, another class must be named NO_REGS | |
1141 | and contain no registers. | |
1142 | ||
1143 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1144 | another name such as ALL_REGS). This is the class of registers | |
1145 | that is allowed by "g" or "r" in a register constraint. | |
1146 | Also, registers outside this class are allocated only when | |
1147 | instructions express preferences for them. | |
1148 | ||
1149 | The classes must be numbered in nondecreasing order; that is, | |
1150 | a larger-numbered class must never be contained completely | |
1151 | in a smaller-numbered class. | |
1152 | ||
1153 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1154 | class that represents their union. |
1155 | ||
1156 | It might seem that class BREG is unnecessary, since no useful 386 | |
1157 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1158 | and the "b" register constraint is useful in asms for syscalls. |
1159 | ||
1160 | The flags and fpsr registers are in no class. */ | |
c98f8742 JVA |
1161 | |
1162 | enum reg_class | |
1163 | { | |
1164 | NO_REGS, | |
e075ae69 | 1165 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1166 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1167 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1168 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1169 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1170 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1171 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1172 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1173 | FLOAT_REGS, | |
a7180f70 BS |
1174 | SSE_REGS, |
1175 | MMX_REGS, | |
446988df JH |
1176 | FP_TOP_SSE_REGS, |
1177 | FP_SECOND_SSE_REGS, | |
1178 | FLOAT_SSE_REGS, | |
1179 | FLOAT_INT_REGS, | |
1180 | INT_SSE_REGS, | |
1181 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1182 | ALL_REGS, LIM_REG_CLASSES |
1183 | }; | |
1184 | ||
d9a5f180 GS |
1185 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1186 | ||
1187 | #define INTEGER_CLASS_P(CLASS) \ | |
1188 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1189 | #define FLOAT_CLASS_P(CLASS) \ | |
1190 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1191 | #define SSE_CLASS_P(CLASS) \ | |
1192 | reg_class_subset_p ((CLASS), SSE_REGS) | |
1193 | #define MMX_CLASS_P(CLASS) \ | |
1194 | reg_class_subset_p ((CLASS), MMX_REGS) | |
1195 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ | |
1196 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1197 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1198 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1199 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1200 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1201 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1202 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1203 | ||
1204 | #define Q_CLASS_P(CLASS) \ | |
1205 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1206 | |
c98f8742 JVA |
1207 | /* Give names of register classes as strings for dump file. */ |
1208 | ||
1209 | #define REG_CLASS_NAMES \ | |
1210 | { "NO_REGS", \ | |
ab408a86 | 1211 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1212 | "SIREG", "DIREG", \ |
e075ae69 RH |
1213 | "AD_REGS", \ |
1214 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1215 | "INDEX_REGS", \ |
3f3f2124 | 1216 | "LEGACY_REGS", \ |
c98f8742 JVA |
1217 | "GENERAL_REGS", \ |
1218 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1219 | "FLOAT_REGS", \ | |
a7180f70 BS |
1220 | "SSE_REGS", \ |
1221 | "MMX_REGS", \ | |
446988df JH |
1222 | "FP_TOP_SSE_REGS", \ |
1223 | "FP_SECOND_SSE_REGS", \ | |
1224 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1225 | "FLOAT_INT_REGS", \ |
446988df JH |
1226 | "INT_SSE_REGS", \ |
1227 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1228 | "ALL_REGS" } |
1229 | ||
1230 | /* Define which registers fit in which classes. | |
1231 | This is an initializer for a vector of HARD_REG_SET | |
1232 | of length N_REG_CLASSES. */ | |
1233 | ||
a7180f70 | 1234 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1235 | { { 0x00, 0x0 }, \ |
1236 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1237 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1238 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1239 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1240 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
1241 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ | |
1242 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1243 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1244 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
1245 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ | |
1246 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
1247 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ | |
1248 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1249 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1250 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1251 | { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ | |
1252 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1253 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1254 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1255 | { 0xffffffff,0x1fffff } \ | |
e075ae69 | 1256 | } |
c98f8742 JVA |
1257 | |
1258 | /* The same information, inverted: | |
1259 | Return the class number of the smallest class containing | |
1260 | reg number REGNO. This could be a conditional expression | |
1261 | or could index an array. */ | |
1262 | ||
c98f8742 JVA |
1263 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1264 | ||
1265 | /* When defined, the compiler allows registers explicitly used in the | |
1266 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1267 | extending the lifetime of these registers. */ |
c98f8742 | 1268 | |
2922fe9e | 1269 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 JVA |
1270 | |
1271 | #define QI_REG_P(X) \ | |
1272 | (REG_P (X) && REGNO (X) < 4) | |
3f3f2124 | 1273 | |
d9a5f180 GS |
1274 | #define GENERAL_REGNO_P(N) \ |
1275 | ((N) < 8 || REX_INT_REGNO_P (N)) | |
3f3f2124 JH |
1276 | |
1277 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1278 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1279 | |
1280 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1281 | ||
c98f8742 JVA |
1282 | #define NON_QI_REG_P(X) \ |
1283 | (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) | |
1284 | ||
d9a5f180 | 1285 | #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) |
3f3f2124 JH |
1286 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1287 | ||
c98f8742 | 1288 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1289 | #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) |
446988df | 1290 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1291 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1292 | |
d9a5f180 GS |
1293 | #define SSE_REGNO_P(N) \ |
1294 | (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ | |
1295 | || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) | |
3f3f2124 | 1296 | |
d9a5f180 GS |
1297 | #define SSE_REGNO(N) \ |
1298 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
1299 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) | |
446988df | 1300 | |
d9a5f180 | 1301 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1302 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1303 | |
d9a5f180 GS |
1304 | #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) |
1305 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) | |
fce5a9f2 | 1306 | |
d9a5f180 GS |
1307 | #define STACK_REG_P(XOP) \ |
1308 | (REG_P (XOP) && \ | |
1309 | REGNO (XOP) >= FIRST_STACK_REG && \ | |
1310 | REGNO (XOP) <= LAST_STACK_REG) | |
c98f8742 | 1311 | |
d9a5f180 | 1312 | #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) |
c98f8742 | 1313 | |
d9a5f180 | 1314 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1315 | |
e075ae69 RH |
1316 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1317 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1318 | ||
cdbca172 JO |
1319 | /* Indicate whether hard register numbered REG_NO should be converted |
1320 | to SSA form. */ | |
1321 | #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ | |
d9a5f180 | 1322 | ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) |
cdbca172 | 1323 | |
c98f8742 JVA |
1324 | /* The class value for index registers, and the one for base regs. */ |
1325 | ||
1326 | #define INDEX_REG_CLASS INDEX_REGS | |
1327 | #define BASE_REG_CLASS GENERAL_REGS | |
1328 | ||
1329 | /* Get reg_class from a letter such as appears in the machine description. */ | |
1330 | ||
1331 | #define REG_CLASS_FROM_LETTER(C) \ | |
8c2bf92a | 1332 | ((C) == 'r' ? GENERAL_REGS : \ |
3f3f2124 JH |
1333 | (C) == 'R' ? LEGACY_REGS : \ |
1334 | (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ | |
1335 | (C) == 'Q' ? Q_REGS : \ | |
8c2bf92a JVA |
1336 | (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ |
1337 | ? FLOAT_REGS \ | |
1338 | : NO_REGS) : \ | |
1339 | (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1340 | ? FP_TOP_REG \ | |
1341 | : NO_REGS) : \ | |
1342 | (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1343 | ? FP_SECOND_REG \ | |
1344 | : NO_REGS) : \ | |
1345 | (C) == 'a' ? AREG : \ | |
1346 | (C) == 'b' ? BREG : \ | |
1347 | (C) == 'c' ? CREG : \ | |
1348 | (C) == 'd' ? DREG : \ | |
446988df JH |
1349 | (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ |
1350 | (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ | |
1351 | (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ | |
4b71cd6e | 1352 | (C) == 'A' ? AD_REGS : \ |
8c2bf92a | 1353 | (C) == 'D' ? DIREG : \ |
c98f8742 JVA |
1354 | (C) == 'S' ? SIREG : NO_REGS) |
1355 | ||
1356 | /* The letters I, J, K, L and M in a register constraint string | |
1357 | can be used to stand for particular ranges of immediate operands. | |
1358 | This macro defines what the ranges are. | |
1359 | C is the letter, and VALUE is a constant value. | |
1360 | Return 1 if VALUE is in the range specified by C. | |
1361 | ||
1362 | I is for non-DImode shifts. | |
1363 | J is for DImode shifts. | |
e075ae69 RH |
1364 | K is for signed imm8 operands. |
1365 | L is for andsi as zero-extending move. | |
c98f8742 | 1366 | M is for shifts that can be executed by the "lea" opcode. |
1aa9fd24 | 1367 | N is for immedaite operands for out/in instructions (0-255) |
c98f8742 JVA |
1368 | */ |
1369 | ||
e075ae69 RH |
1370 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1371 | ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ | |
1372 | : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ | |
1373 | : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ | |
1374 | : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ | |
1375 | : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ | |
1aa9fd24 | 1376 | : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ |
e075ae69 | 1377 | : 0) |
c98f8742 JVA |
1378 | |
1379 | /* Similar, but for floating constants, and defining letters G and H. | |
b4ac57ab RS |
1380 | Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if |
1381 | TARGET_387 isn't set, because the stack register converter may need to | |
c47f5ea5 | 1382 | load 0.0 into the function value register. */ |
c98f8742 JVA |
1383 | |
1384 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
2b04e52b JH |
1385 | ((C) == 'G' ? standard_80387_constant_p (VALUE) \ |
1386 | : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0)) | |
c98f8742 | 1387 | |
6189a572 JH |
1388 | /* A C expression that defines the optional machine-dependent |
1389 | constraint letters that can be used to segregate specific types of | |
1390 | operands, usually memory references, for the target machine. Any | |
1391 | letter that is not elsewhere defined and not matched by | |
1392 | `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not | |
1393 | be defined. | |
1394 | ||
1395 | If it is required for a particular target machine, it should | |
1396 | return 1 if VALUE corresponds to the operand type represented by | |
1397 | the constraint letter C. If C is not defined as an extra | |
1398 | constraint, the value returned should be 0 regardless of VALUE. */ | |
1399 | ||
1400 | #define EXTRA_CONSTRAINT(VALUE, C) \ | |
1401 | ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \ | |
1402 | : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \ | |
1403 | : 0) | |
1404 | ||
c98f8742 | 1405 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1406 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1407 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1408 | |
d2836273 JH |
1409 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1410 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1411 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1412 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1413 | ? Q_REGS : (CLASS)) |
1414 | ||
1415 | /* Given an rtx X being reloaded into a reg required to be | |
1416 | in class CLASS, return the class of reg to actually use. | |
1417 | In general this is just CLASS; but on some machines | |
1418 | in some cases it is preferable to use a more restrictive class. | |
1419 | On the 80386 series, we prevent floating constants from being | |
1420 | reloaded into floating registers (since no move-insn can do that) | |
1421 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1422 | ||
d398b3b1 | 1423 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1424 | QImode must go into class Q_REGS. |
d398b3b1 | 1425 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1426 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1427 | |
d9a5f180 GS |
1428 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1429 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e JVA |
1430 | |
1431 | /* If we are copying between general and FP registers, we need a memory | |
f84aa48a | 1432 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1433 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1434 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 RH |
1435 | |
1436 | /* QImode spills from non-QI registers need a scratch. This does not | |
fce5a9f2 | 1437 | happen often -- the only example so far requires an uninitialized |
e075ae69 RH |
1438 | pseudo. */ |
1439 | ||
d9a5f180 | 1440 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ |
3b8d200e JJ |
1441 | (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ |
1442 | || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ | |
d2836273 | 1443 | ? Q_REGS : NO_REGS) |
c98f8742 JVA |
1444 | |
1445 | /* Return the maximum number of consecutive registers | |
1446 | needed to represent mode MODE in a register of class CLASS. */ | |
1447 | /* On the 80386, this is the size of MODE in words, | |
92d0fb09 JH |
1448 | except in the FP regs, where a single reg is always enough. |
1449 | The TFmodes are really just 80bit values, so we use only 3 registers | |
1450 | to hold them, instead of 4, as the size would suggest. | |
1451 | */ | |
a7180f70 | 1452 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1453 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1454 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
1455 | : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ | |
1456 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1457 | |
1458 | /* A C expression whose value is nonzero if pseudos that have been | |
1459 | assigned to registers of class CLASS would likely be spilled | |
1460 | because registers of CLASS are needed for spill registers. | |
1461 | ||
1462 | The default value of this macro returns 1 if CLASS has exactly one | |
1463 | register and zero otherwise. On most machines, this default | |
1464 | should be used. Only define this macro to some other expression | |
1465 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1466 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1467 | macro returns nonzero for those classes, those pseudos will only |
1468 | be allocated by `global.c', which knows how to reallocate the | |
1469 | pseudo to another register. If there would not be another | |
1470 | register available for reallocation, you should not change the | |
1471 | definition of this macro since the only effect of such a | |
1472 | definition would be to slow down register allocation. */ | |
1473 | ||
1474 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1475 | (((CLASS) == AREG) \ | |
1476 | || ((CLASS) == DREG) \ | |
1477 | || ((CLASS) == CREG) \ | |
1478 | || ((CLASS) == BREG) \ | |
1479 | || ((CLASS) == AD_REGS) \ | |
1480 | || ((CLASS) == SIREG) \ | |
1481 | || ((CLASS) == DIREG)) | |
1482 | ||
e075ae69 | 1483 | /* A C statement that adds to CLOBBERS any hard regs the port wishes |
fce5a9f2 | 1484 | to automatically clobber for all asms. |
e075ae69 RH |
1485 | |
1486 | We do this in the new i386 backend to maintain source compatibility | |
1487 | with the old cc0-based compiler. */ | |
1488 | ||
d9a5f180 GS |
1489 | #define MD_ASM_CLOBBERS(CLOBBERS) \ |
1490 | do { \ | |
1491 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ | |
1492 | (CLOBBERS)); \ | |
1493 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ | |
1494 | (CLOBBERS)); \ | |
1495 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ | |
1496 | (CLOBBERS)); \ | |
e075ae69 | 1497 | } while (0) |
c98f8742 JVA |
1498 | \f |
1499 | /* Stack layout; function entry, exit and calling. */ | |
1500 | ||
1501 | /* Define this if pushing a word on the stack | |
1502 | makes the stack pointer a smaller address. */ | |
1503 | #define STACK_GROWS_DOWNWARD | |
1504 | ||
1505 | /* Define this if the nominal address of the stack frame | |
1506 | is at the high-address end of the local variables; | |
1507 | that is, each additional local variable allocated | |
1508 | goes at a more negative offset in the frame. */ | |
1509 | #define FRAME_GROWS_DOWNWARD | |
1510 | ||
1511 | /* Offset within stack frame to start allocating local variables at. | |
1512 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1513 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1514 | of the first local allocated. */ | |
1515 | #define STARTING_FRAME_OFFSET 0 | |
1516 | ||
1517 | /* If we generate an insn to push BYTES bytes, | |
1518 | this says how many the stack pointer really advances by. | |
1519 | On 386 pushw decrements by exactly 2 no matter what the position was. | |
1520 | On the 386 there is no pushb; we use pushw instead, and this | |
d2836273 | 1521 | has the effect of rounding up to 2. |
fce5a9f2 | 1522 | |
d2836273 JH |
1523 | For 64bit ABI we round up to 8 bytes. |
1524 | */ | |
c98f8742 | 1525 | |
d2836273 JH |
1526 | #define PUSH_ROUNDING(BYTES) \ |
1527 | (TARGET_64BIT \ | |
1528 | ? (((BYTES) + 7) & (-8)) \ | |
1529 | : (((BYTES) + 1) & (-2))) | |
c98f8742 | 1530 | |
f73ad30e JH |
1531 | /* If defined, the maximum amount of space required for outgoing arguments will |
1532 | be computed and placed into the variable | |
1533 | `current_function_outgoing_args_size'. No space will be pushed onto the | |
1534 | stack for each call; instead, the function prologue should increase the stack | |
1535 | frame size by this amount. */ | |
1536 | ||
1537 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1538 | ||
1539 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1540 | instructions to pass outgoing arguments. */ | |
1541 | ||
1542 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1543 | ||
c98f8742 JVA |
1544 | /* Offset of first parameter from the argument pointer register value. */ |
1545 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1546 | ||
a7180f70 BS |
1547 | /* Define this macro if functions should assume that stack space has been |
1548 | allocated for arguments even when their values are passed in registers. | |
1549 | ||
1550 | The value of this macro is the size, in bytes, of the area reserved for | |
1551 | arguments passed in registers for the function represented by FNDECL. | |
1552 | ||
1553 | This space can be allocated by the caller, or be a part of the | |
1554 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1555 | which. */ | |
1556 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
1557 | ||
1558 | /* Define as a C expression that evaluates to nonzero if we do not know how | |
1559 | to pass TYPE solely in registers. The file expr.h defines a | |
1560 | definition that is usually appropriate, refer to expr.h for additional | |
1561 | documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be | |
1562 | computed in the stack and then loaded into a register. */ | |
d9a5f180 GS |
1563 | #define MUST_PASS_IN_STACK(MODE, TYPE) \ |
1564 | ((TYPE) != 0 \ | |
1565 | && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ | |
1566 | || TREE_ADDRESSABLE (TYPE) \ | |
1567 | || ((MODE) == TImode) \ | |
1568 | || ((MODE) == BLKmode \ | |
1569 | && ! ((TYPE) != 0 \ | |
1570 | && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ | |
1571 | && 0 == (int_size_in_bytes (TYPE) \ | |
1572 | % (PARM_BOUNDARY / BITS_PER_UNIT))) \ | |
1573 | && (FUNCTION_ARG_PADDING (MODE, TYPE) \ | |
a7180f70 BS |
1574 | == (BYTES_BIG_ENDIAN ? upward : downward))))) |
1575 | ||
c98f8742 JVA |
1576 | /* Value is the number of bytes of arguments automatically |
1577 | popped when returning from a subroutine call. | |
8b109b37 | 1578 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1579 | FUNTYPE is the data type of the function (as a tree), |
1580 | or for a library call it is an identifier node for the subroutine name. | |
1581 | SIZE is the number of bytes of arguments passed on the stack. | |
1582 | ||
1583 | On the 80386, the RTD insn may be used to pop them if the number | |
1584 | of args is fixed, but if the number is variable then the caller | |
1585 | must pop them all. RTD can't be used for library calls now | |
1586 | because the library is compiled with the Unix compiler. | |
1587 | Use of RTD is a selectable option, since it is incompatible with | |
1588 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1589 | the caller must always pop the args. |
1590 | ||
1591 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1592 | |
d9a5f180 GS |
1593 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1594 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1595 | |
8c2bf92a JVA |
1596 | /* Define how to find the value returned by a function. |
1597 | VALTYPE is the data type of the value (as a tree). | |
1598 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1599 | otherwise, FUNC is 0. */ | |
c98f8742 | 1600 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
53c17031 JH |
1601 | ix86_function_value (VALTYPE) |
1602 | ||
1603 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
1604 | ix86_function_value_regno_p (N) | |
c98f8742 JVA |
1605 | |
1606 | /* Define how to find the value returned by a library function | |
1607 | assuming the value has mode MODE. */ | |
1608 | ||
1609 | #define LIBCALL_VALUE(MODE) \ | |
53c17031 | 1610 | ix86_libcall_value (MODE) |
c98f8742 | 1611 | |
e9125c09 TW |
1612 | /* Define the size of the result block used for communication between |
1613 | untyped_call and untyped_return. The block contains a DImode value | |
1614 | followed by the block used by fnsave and frstor. */ | |
1615 | ||
1616 | #define APPLY_RESULT_SIZE (8+108) | |
1617 | ||
b08de47e | 1618 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1619 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1620 | |
1621 | /* Define a data type for recording info about an argument list | |
1622 | during the scan of that argument list. This data type should | |
1623 | hold all necessary information about the function itself | |
1624 | and about the args processed so far, enough to enable macros | |
b08de47e | 1625 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1626 | |
e075ae69 | 1627 | typedef struct ix86_args { |
b08de47e MM |
1628 | int words; /* # words passed so far */ |
1629 | int nregs; /* # registers available for passing */ | |
1630 | int regno; /* next available register number */ | |
a7180f70 BS |
1631 | int sse_words; /* # sse words passed so far */ |
1632 | int sse_nregs; /* # sse registers available for passing */ | |
1633 | int sse_regno; /* next available sse register number */ | |
892a2d68 | 1634 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
b08de47e | 1635 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1636 | |
1637 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1638 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1639 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1640 | |
d9a5f180 GS |
1641 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1642 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) | |
c98f8742 JVA |
1643 | |
1644 | /* Update the data in CUM to advance over an argument | |
1645 | of mode MODE and data type TYPE. | |
1646 | (TYPE is null for libcalls where that information may not be available.) */ | |
1647 | ||
d9a5f180 GS |
1648 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1649 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1650 | |
1651 | /* Define where to put the arguments to a function. | |
1652 | Value is zero to push the argument on the stack, | |
1653 | or a hard register in which to store the argument. | |
1654 | ||
1655 | MODE is the argument's machine mode. | |
1656 | TYPE is the data type of the argument (as a tree). | |
1657 | This is null for libcalls where that information may | |
1658 | not be available. | |
1659 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1660 | the preceding args and about the function being called. | |
1661 | NAMED is nonzero if this argument is a named parameter | |
1662 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1663 | ||
c98f8742 | 1664 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1665 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 JVA |
1666 | |
1667 | /* For an arg passed partly in registers and partly in memory, | |
1668 | this is the number of registers used. | |
1669 | For args passed entirely in registers or entirely in memory, zero. */ | |
1670 | ||
e075ae69 | 1671 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
c98f8742 | 1672 | |
26f2c02a ZW |
1673 | /* If PIC, we cannot make sibling calls to global functions |
1674 | because the PLT requires %ebx live. | |
1675 | If we are returning floats on the register stack, we cannot make | |
1676 | sibling calls to functions that return floats. (The stack adjust | |
1677 | instruction will wind up after the sibcall jump, and not be executed.) */ | |
d9a5f180 GS |
1678 | #define FUNCTION_OK_FOR_SIBCALL(DECL) \ |
1679 | ((DECL) \ | |
1680 | && (! flag_pic || ! TREE_PUBLIC (DECL)) \ | |
1681 | && (! TARGET_FLOAT_RETURNS_IN_80387 \ | |
1682 | || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \ | |
26f2c02a | 1683 | || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl)))))) |
cbbf65e0 | 1684 | |
ad919812 JH |
1685 | /* Perform any needed actions needed for a function that is receiving a |
1686 | variable number of arguments. | |
1687 | ||
1688 | CUM is as above. | |
1689 | ||
1690 | MODE and TYPE are the mode and type of the current parameter. | |
1691 | ||
1692 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1693 | that must be pushed by the prolog to pretend that our caller pushed | |
1694 | it. | |
1695 | ||
1696 | Normally, this macro will push all remaining incoming registers on the | |
1697 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1698 | ||
d9a5f180 GS |
1699 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
1700 | ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ | |
1701 | (NO_RTL)) | |
ad919812 JH |
1702 | |
1703 | /* Define the `__builtin_va_list' type for the ABI. */ | |
1704 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
d9a5f180 | 1705 | ((VALIST) = ix86_build_va_list ()) |
ad919812 JH |
1706 | |
1707 | /* Implement `va_start' for varargs and stdarg. */ | |
e5faf155 ZW |
1708 | #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ |
1709 | ix86_va_start (VALIST, NEXTARG) | |
ad919812 JH |
1710 | |
1711 | /* Implement `va_arg'. */ | |
d9a5f180 GS |
1712 | #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ |
1713 | ix86_va_arg ((VALIST), (TYPE)) | |
ad919812 | 1714 | |
4cf12e7e RH |
1715 | /* This macro is invoked at the end of compilation. It is used here to |
1716 | output code for -fpic that will load the return address into %ebx. */ | |
3a0433fd | 1717 | |
4cf12e7e RH |
1718 | #undef ASM_FILE_END |
1719 | #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) | |
3a0433fd | 1720 | |
c98f8742 JVA |
1721 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1722 | for profiling a function entry. */ | |
1723 | ||
d9a5f180 GS |
1724 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1725 | do { \ | |
c98f8742 JVA |
1726 | if (flag_pic) \ |
1727 | { \ | |
d9a5f180 | 1728 | fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ |
c98f8742 | 1729 | LPREFIX, (LABELNO)); \ |
d9a5f180 | 1730 | fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \ |
c98f8742 JVA |
1731 | } \ |
1732 | else \ | |
1733 | { \ | |
d9a5f180 GS |
1734 | fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ |
1735 | fprintf ((FILE), "\tcall\t_mcount\n"); \ | |
c98f8742 | 1736 | } \ |
d9a5f180 | 1737 | } while (0) |
c98f8742 JVA |
1738 | |
1739 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1740 | the stack pointer does not matter. The value is tested only in | |
1741 | functions that have frame pointers. | |
1742 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1743 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1744 | we have to restore it ourselves from the frame pointer, in order to |
1745 | use pop */ | |
1746 | ||
1747 | #define EXIT_IGNORE_STACK 1 | |
1748 | ||
c98f8742 JVA |
1749 | /* Output assembler code for a block containing the constant parts |
1750 | of a trampoline, leaving space for the variable parts. */ | |
1751 | ||
a269a03c | 1752 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1753 | mov #STATIC,ecx |
a269a03c JC |
1754 | jmp FUNCTION |
1755 | The trampoline is generated entirely at runtime. The operand of JMP | |
1756 | is the address of FUNCTION relative to the instruction following the | |
1757 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1758 | |
1759 | /* Length in units of the trampoline for entering a nested function. */ | |
1760 | ||
39d04363 | 1761 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1762 | |
1763 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1764 | FNADDR is an RTX for the address of the function's pure code. | |
1765 | CXT is an RTX for the static chain value for the function. */ | |
1766 | ||
d9a5f180 GS |
1767 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1768 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1769 | \f |
1770 | /* Definitions for register eliminations. | |
1771 | ||
1772 | This is an array of structures. Each structure initializes one pair | |
1773 | of eliminable registers. The "from" register number is given first, | |
1774 | followed by "to". Eliminations of the same "from" register are listed | |
1775 | in order of preference. | |
1776 | ||
afc2cd05 NC |
1777 | There are two registers that can always be eliminated on the i386. |
1778 | The frame pointer and the arg pointer can be replaced by either the | |
1779 | hard frame pointer or to the stack pointer, depending upon the | |
1780 | circumstances. The hard frame pointer is not used before reload and | |
1781 | so it is not eligible for elimination. */ | |
c98f8742 | 1782 | |
564d80f4 JH |
1783 | #define ELIMINABLE_REGS \ |
1784 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1785 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1786 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1787 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1788 | |
2c5a510c RH |
1789 | /* Given FROM and TO register numbers, say whether this elimination is |
1790 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1791 | |
1792 | All other eliminations are valid. */ | |
1793 | ||
2c5a510c RH |
1794 | #define CAN_ELIMINATE(FROM, TO) \ |
1795 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
c98f8742 JVA |
1796 | |
1797 | /* Define the offset between two registers, one to be eliminated, and the other | |
1798 | its replacement, at the start of a routine. */ | |
1799 | ||
d9a5f180 GS |
1800 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1801 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1802 | \f |
1803 | /* Addressing modes, and classification of registers for them. */ | |
1804 | ||
940da324 JL |
1805 | /* #define HAVE_POST_INCREMENT 0 */ |
1806 | /* #define HAVE_POST_DECREMENT 0 */ | |
c98f8742 | 1807 | |
940da324 JL |
1808 | /* #define HAVE_PRE_DECREMENT 0 */ |
1809 | /* #define HAVE_PRE_INCREMENT 0 */ | |
c98f8742 JVA |
1810 | |
1811 | /* Macros to check register numbers against specific register classes. */ | |
1812 | ||
1813 | /* These assume that REGNO is a hard or pseudo reg number. | |
1814 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1815 | or a pseudo reg currently allocated to a suitable hard reg. | |
1816 | Since they use reg_renumber, they are safe only once reg_renumber | |
1817 | has been allocated, which happens in local-alloc.c. */ | |
1818 | ||
3f3f2124 JH |
1819 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1820 | ((REGNO) < STACK_POINTER_REGNUM \ | |
1821 | || (REGNO >= FIRST_REX_INT_REG \ | |
1822 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1823 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1824 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1825 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) | |
c98f8742 | 1826 | |
3f3f2124 JH |
1827 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1828 | ((REGNO) <= STACK_POINTER_REGNUM \ | |
1829 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1830 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1831 | || (REGNO >= FIRST_REX_INT_REG \ | |
1832 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1833 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1834 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1835 | || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) | |
c98f8742 | 1836 | |
d9a5f180 GS |
1837 | #define REGNO_OK_FOR_SIREG_P(REGNO) \ |
1838 | ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) | |
1839 | #define REGNO_OK_FOR_DIREG_P(REGNO) \ | |
1840 | ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) | |
c98f8742 JVA |
1841 | |
1842 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1843 | and check its validity for a certain class. | |
1844 | We have two alternate definitions for each of them. | |
1845 | The usual definition accepts all pseudo regs; the other rejects | |
1846 | them unless they have been allocated suitable hard regs. | |
1847 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1848 | ||
1849 | Most source files want to accept pseudo regs in the hope that | |
1850 | they will get allocated to the class that the insn wants them to be in. | |
1851 | Source files for reload pass need to be strict. | |
1852 | After reload, it makes no difference, since pseudo regs have | |
1853 | been eliminated by then. */ | |
1854 | ||
c98f8742 | 1855 | |
3b3c6a3f MM |
1856 | /* Non strict versions, pseudos are ok */ |
1857 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
1858 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
3f3f2124 JH |
1859 | || (REGNO (X) >= FIRST_REX_INT_REG \ |
1860 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
c98f8742 JVA |
1861 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1862 | ||
3b3c6a3f MM |
1863 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
1864 | (REGNO (X) <= STACK_POINTER_REGNUM \ | |
1865 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
3f3f2124 JH |
1866 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
1867 | || (REGNO (X) >= FIRST_REX_INT_REG \ | |
1868 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
3b3c6a3f | 1869 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1870 | |
3b3c6a3f MM |
1871 | /* Strict versions, hard registers only */ |
1872 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1873 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1874 | |
3b3c6a3f | 1875 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1876 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1877 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1878 | |
1879 | #else | |
d9a5f180 GS |
1880 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1881 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1882 | #endif |
1883 | ||
1884 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1885 | that is a valid memory address for an instruction. | |
1886 | The MODE argument is the machine mode for the MEM expression | |
1887 | that wants to use this address. | |
1888 | ||
1889 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1890 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1891 | ||
1892 | See legitimize_pic_address in i386.c for details as to what | |
1893 | constitutes a legitimate address when -fpic is used. */ | |
1894 | ||
1895 | #define MAX_REGS_PER_ADDRESS 2 | |
1896 | ||
f996902d | 1897 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1898 | |
1899 | /* Nonzero if the constant value X is a legitimate general operand. | |
1900 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1901 | ||
f996902d | 1902 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1903 | |
3b3c6a3f MM |
1904 | #ifdef REG_OK_STRICT |
1905 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1906 | do { \ |
1907 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1908 | goto ADDR; \ |
d9a5f180 | 1909 | } while (0) |
c98f8742 | 1910 | |
3b3c6a3f MM |
1911 | #else |
1912 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1913 | do { \ |
1914 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1915 | goto ADDR; \ |
d9a5f180 | 1916 | } while (0) |
c98f8742 | 1917 | |
3b3c6a3f MM |
1918 | #endif |
1919 | ||
b949ea8b JW |
1920 | /* If defined, a C expression to determine the base term of address X. |
1921 | This macro is used in only one place: `find_base_term' in alias.c. | |
1922 | ||
1923 | It is always safe for this macro to not be defined. It exists so | |
1924 | that alias analysis can understand machine-dependent addresses. | |
1925 | ||
1926 | The typical use of this macro is to handle addresses containing | |
1927 | a label_ref or symbol_ref within an UNSPEC. */ | |
1928 | ||
d9a5f180 | 1929 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1930 | |
c98f8742 JVA |
1931 | /* Try machine-dependent ways of modifying an illegitimate address |
1932 | to be legitimate. If we find one, return the new, valid address. | |
1933 | This macro is used in only one place: `memory_address' in explow.c. | |
1934 | ||
1935 | OLDX is the address as it was before break_out_memory_refs was called. | |
1936 | In some cases it is useful to look at this to decide what needs to be done. | |
1937 | ||
1938 | MODE and WIN are passed so that this macro can use | |
1939 | GO_IF_LEGITIMATE_ADDRESS. | |
1940 | ||
1941 | It is always safe for this macro to do nothing. It exists to recognize | |
1942 | opportunities to optimize the output. | |
1943 | ||
1944 | For the 80386, we handle X+REG by loading X into a register R and | |
1945 | using R+REG. R will go in a general reg and indexing will be used. | |
1946 | However, if REG is a broken-out memory address or multiplication, | |
1947 | nothing needs to be done because REG can certainly go in a general reg. | |
1948 | ||
1949 | When -fpic is used, special handling is needed for symbolic references. | |
1950 | See comments by legitimize_pic_address in i386.c for details. */ | |
1951 | ||
3b3c6a3f | 1952 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
1953 | do { \ |
1954 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1955 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 1956 | goto WIN; \ |
d9a5f180 | 1957 | } while (0) |
c98f8742 | 1958 | |
d9a5f180 | 1959 | #define REWRITE_ADDRESS(X) rewrite_address (X) |
d4ba09c0 | 1960 | |
c98f8742 | 1961 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1962 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1963 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1964 | ||
f996902d | 1965 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1966 | |
1967 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1968 | (GET_CODE (X) == SYMBOL_REF \ |
1969 | || GET_CODE (X) == LABEL_REF \ | |
1970 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
1971 | |
1972 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1973 | has an effect that depends on the machine mode it is used for. | |
1974 | On the 80386, only postdecrement and postincrement address depend thus | |
1975 | (the amount of decrement or increment being the length of the operand). */ | |
d9a5f180 GS |
1976 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
1977 | do { \ | |
1978 | if (GET_CODE (ADDR) == POST_INC \ | |
1979 | || GET_CODE (ADDR) == POST_DEC) \ | |
1980 | goto LABEL; \ | |
1981 | } while (0) | |
c98f8742 | 1982 | \f |
bd793c65 BS |
1983 | /* Codes for all the SSE/MMX builtins. */ |
1984 | enum ix86_builtins | |
1985 | { | |
1986 | IX86_BUILTIN_ADDPS, | |
1987 | IX86_BUILTIN_ADDSS, | |
1988 | IX86_BUILTIN_DIVPS, | |
1989 | IX86_BUILTIN_DIVSS, | |
1990 | IX86_BUILTIN_MULPS, | |
1991 | IX86_BUILTIN_MULSS, | |
1992 | IX86_BUILTIN_SUBPS, | |
1993 | IX86_BUILTIN_SUBSS, | |
1994 | ||
1995 | IX86_BUILTIN_CMPEQPS, | |
1996 | IX86_BUILTIN_CMPLTPS, | |
1997 | IX86_BUILTIN_CMPLEPS, | |
1998 | IX86_BUILTIN_CMPGTPS, | |
1999 | IX86_BUILTIN_CMPGEPS, | |
2000 | IX86_BUILTIN_CMPNEQPS, | |
2001 | IX86_BUILTIN_CMPNLTPS, | |
2002 | IX86_BUILTIN_CMPNLEPS, | |
2003 | IX86_BUILTIN_CMPNGTPS, | |
2004 | IX86_BUILTIN_CMPNGEPS, | |
2005 | IX86_BUILTIN_CMPORDPS, | |
2006 | IX86_BUILTIN_CMPUNORDPS, | |
2007 | IX86_BUILTIN_CMPNEPS, | |
2008 | IX86_BUILTIN_CMPEQSS, | |
2009 | IX86_BUILTIN_CMPLTSS, | |
2010 | IX86_BUILTIN_CMPLESS, | |
2011 | IX86_BUILTIN_CMPGTSS, | |
2012 | IX86_BUILTIN_CMPGESS, | |
2013 | IX86_BUILTIN_CMPNEQSS, | |
2014 | IX86_BUILTIN_CMPNLTSS, | |
2015 | IX86_BUILTIN_CMPNLESS, | |
2016 | IX86_BUILTIN_CMPNGTSS, | |
2017 | IX86_BUILTIN_CMPNGESS, | |
2018 | IX86_BUILTIN_CMPORDSS, | |
2019 | IX86_BUILTIN_CMPUNORDSS, | |
2020 | IX86_BUILTIN_CMPNESS, | |
2021 | ||
2022 | IX86_BUILTIN_COMIEQSS, | |
2023 | IX86_BUILTIN_COMILTSS, | |
2024 | IX86_BUILTIN_COMILESS, | |
2025 | IX86_BUILTIN_COMIGTSS, | |
2026 | IX86_BUILTIN_COMIGESS, | |
2027 | IX86_BUILTIN_COMINEQSS, | |
2028 | IX86_BUILTIN_UCOMIEQSS, | |
2029 | IX86_BUILTIN_UCOMILTSS, | |
2030 | IX86_BUILTIN_UCOMILESS, | |
2031 | IX86_BUILTIN_UCOMIGTSS, | |
2032 | IX86_BUILTIN_UCOMIGESS, | |
2033 | IX86_BUILTIN_UCOMINEQSS, | |
2034 | ||
2035 | IX86_BUILTIN_CVTPI2PS, | |
2036 | IX86_BUILTIN_CVTPS2PI, | |
2037 | IX86_BUILTIN_CVTSI2SS, | |
2038 | IX86_BUILTIN_CVTSS2SI, | |
2039 | IX86_BUILTIN_CVTTPS2PI, | |
2040 | IX86_BUILTIN_CVTTSS2SI, | |
bd793c65 BS |
2041 | |
2042 | IX86_BUILTIN_MAXPS, | |
2043 | IX86_BUILTIN_MAXSS, | |
2044 | IX86_BUILTIN_MINPS, | |
2045 | IX86_BUILTIN_MINSS, | |
2046 | ||
2047 | IX86_BUILTIN_LOADAPS, | |
2048 | IX86_BUILTIN_LOADUPS, | |
2049 | IX86_BUILTIN_STOREAPS, | |
2050 | IX86_BUILTIN_STOREUPS, | |
2051 | IX86_BUILTIN_LOADSS, | |
2052 | IX86_BUILTIN_STORESS, | |
2053 | IX86_BUILTIN_MOVSS, | |
2054 | ||
2055 | IX86_BUILTIN_MOVHLPS, | |
2056 | IX86_BUILTIN_MOVLHPS, | |
2057 | IX86_BUILTIN_LOADHPS, | |
2058 | IX86_BUILTIN_LOADLPS, | |
2059 | IX86_BUILTIN_STOREHPS, | |
2060 | IX86_BUILTIN_STORELPS, | |
2061 | ||
2062 | IX86_BUILTIN_MASKMOVQ, | |
2063 | IX86_BUILTIN_MOVMSKPS, | |
2064 | IX86_BUILTIN_PMOVMSKB, | |
2065 | ||
2066 | IX86_BUILTIN_MOVNTPS, | |
2067 | IX86_BUILTIN_MOVNTQ, | |
2068 | ||
2069 | IX86_BUILTIN_PACKSSWB, | |
2070 | IX86_BUILTIN_PACKSSDW, | |
2071 | IX86_BUILTIN_PACKUSWB, | |
2072 | ||
2073 | IX86_BUILTIN_PADDB, | |
2074 | IX86_BUILTIN_PADDW, | |
2075 | IX86_BUILTIN_PADDD, | |
2076 | IX86_BUILTIN_PADDSB, | |
2077 | IX86_BUILTIN_PADDSW, | |
2078 | IX86_BUILTIN_PADDUSB, | |
2079 | IX86_BUILTIN_PADDUSW, | |
2080 | IX86_BUILTIN_PSUBB, | |
2081 | IX86_BUILTIN_PSUBW, | |
2082 | IX86_BUILTIN_PSUBD, | |
2083 | IX86_BUILTIN_PSUBSB, | |
2084 | IX86_BUILTIN_PSUBSW, | |
2085 | IX86_BUILTIN_PSUBUSB, | |
2086 | IX86_BUILTIN_PSUBUSW, | |
2087 | ||
2088 | IX86_BUILTIN_PAND, | |
2089 | IX86_BUILTIN_PANDN, | |
2090 | IX86_BUILTIN_POR, | |
2091 | IX86_BUILTIN_PXOR, | |
2092 | ||
2093 | IX86_BUILTIN_PAVGB, | |
2094 | IX86_BUILTIN_PAVGW, | |
2095 | ||
2096 | IX86_BUILTIN_PCMPEQB, | |
2097 | IX86_BUILTIN_PCMPEQW, | |
2098 | IX86_BUILTIN_PCMPEQD, | |
2099 | IX86_BUILTIN_PCMPGTB, | |
2100 | IX86_BUILTIN_PCMPGTW, | |
2101 | IX86_BUILTIN_PCMPGTD, | |
2102 | ||
2103 | IX86_BUILTIN_PEXTRW, | |
2104 | IX86_BUILTIN_PINSRW, | |
2105 | ||
2106 | IX86_BUILTIN_PMADDWD, | |
2107 | ||
2108 | IX86_BUILTIN_PMAXSW, | |
2109 | IX86_BUILTIN_PMAXUB, | |
2110 | IX86_BUILTIN_PMINSW, | |
2111 | IX86_BUILTIN_PMINUB, | |
2112 | ||
2113 | IX86_BUILTIN_PMULHUW, | |
2114 | IX86_BUILTIN_PMULHW, | |
2115 | IX86_BUILTIN_PMULLW, | |
2116 | ||
2117 | IX86_BUILTIN_PSADBW, | |
2118 | IX86_BUILTIN_PSHUFW, | |
2119 | ||
2120 | IX86_BUILTIN_PSLLW, | |
2121 | IX86_BUILTIN_PSLLD, | |
2122 | IX86_BUILTIN_PSLLQ, | |
2123 | IX86_BUILTIN_PSRAW, | |
2124 | IX86_BUILTIN_PSRAD, | |
2125 | IX86_BUILTIN_PSRLW, | |
2126 | IX86_BUILTIN_PSRLD, | |
2127 | IX86_BUILTIN_PSRLQ, | |
2128 | IX86_BUILTIN_PSLLWI, | |
2129 | IX86_BUILTIN_PSLLDI, | |
2130 | IX86_BUILTIN_PSLLQI, | |
2131 | IX86_BUILTIN_PSRAWI, | |
2132 | IX86_BUILTIN_PSRADI, | |
2133 | IX86_BUILTIN_PSRLWI, | |
2134 | IX86_BUILTIN_PSRLDI, | |
2135 | IX86_BUILTIN_PSRLQI, | |
2136 | ||
2137 | IX86_BUILTIN_PUNPCKHBW, | |
2138 | IX86_BUILTIN_PUNPCKHWD, | |
2139 | IX86_BUILTIN_PUNPCKHDQ, | |
2140 | IX86_BUILTIN_PUNPCKLBW, | |
2141 | IX86_BUILTIN_PUNPCKLWD, | |
2142 | IX86_BUILTIN_PUNPCKLDQ, | |
2143 | ||
2144 | IX86_BUILTIN_SHUFPS, | |
2145 | ||
2146 | IX86_BUILTIN_RCPPS, | |
2147 | IX86_BUILTIN_RCPSS, | |
2148 | IX86_BUILTIN_RSQRTPS, | |
2149 | IX86_BUILTIN_RSQRTSS, | |
2150 | IX86_BUILTIN_SQRTPS, | |
2151 | IX86_BUILTIN_SQRTSS, | |
fce5a9f2 | 2152 | |
bd793c65 BS |
2153 | IX86_BUILTIN_UNPCKHPS, |
2154 | IX86_BUILTIN_UNPCKLPS, | |
2155 | ||
2156 | IX86_BUILTIN_ANDPS, | |
2157 | IX86_BUILTIN_ANDNPS, | |
2158 | IX86_BUILTIN_ORPS, | |
2159 | IX86_BUILTIN_XORPS, | |
2160 | ||
2161 | IX86_BUILTIN_EMMS, | |
2162 | IX86_BUILTIN_LDMXCSR, | |
2163 | IX86_BUILTIN_STMXCSR, | |
2164 | IX86_BUILTIN_SFENCE, | |
bd793c65 | 2165 | |
47f339cf BS |
2166 | /* 3DNow! Original */ |
2167 | IX86_BUILTIN_FEMMS, | |
2168 | IX86_BUILTIN_PAVGUSB, | |
2169 | IX86_BUILTIN_PF2ID, | |
2170 | IX86_BUILTIN_PFACC, | |
2171 | IX86_BUILTIN_PFADD, | |
2172 | IX86_BUILTIN_PFCMPEQ, | |
2173 | IX86_BUILTIN_PFCMPGE, | |
2174 | IX86_BUILTIN_PFCMPGT, | |
2175 | IX86_BUILTIN_PFMAX, | |
2176 | IX86_BUILTIN_PFMIN, | |
2177 | IX86_BUILTIN_PFMUL, | |
2178 | IX86_BUILTIN_PFRCP, | |
2179 | IX86_BUILTIN_PFRCPIT1, | |
2180 | IX86_BUILTIN_PFRCPIT2, | |
2181 | IX86_BUILTIN_PFRSQIT1, | |
2182 | IX86_BUILTIN_PFRSQRT, | |
2183 | IX86_BUILTIN_PFSUB, | |
2184 | IX86_BUILTIN_PFSUBR, | |
2185 | IX86_BUILTIN_PI2FD, | |
2186 | IX86_BUILTIN_PMULHRW, | |
47f339cf BS |
2187 | |
2188 | /* 3DNow! Athlon Extensions */ | |
2189 | IX86_BUILTIN_PF2IW, | |
2190 | IX86_BUILTIN_PFNACC, | |
2191 | IX86_BUILTIN_PFPNACC, | |
2192 | IX86_BUILTIN_PI2FW, | |
2193 | IX86_BUILTIN_PSWAPDSI, | |
2194 | IX86_BUILTIN_PSWAPDSF, | |
2195 | ||
e37af218 | 2196 | IX86_BUILTIN_SSE_ZERO, |
bd793c65 BS |
2197 | IX86_BUILTIN_MMX_ZERO, |
2198 | ||
fbe5eb6d BS |
2199 | /* SSE2 */ |
2200 | IX86_BUILTIN_ADDPD, | |
2201 | IX86_BUILTIN_ADDSD, | |
2202 | IX86_BUILTIN_DIVPD, | |
2203 | IX86_BUILTIN_DIVSD, | |
2204 | IX86_BUILTIN_MULPD, | |
2205 | IX86_BUILTIN_MULSD, | |
2206 | IX86_BUILTIN_SUBPD, | |
2207 | IX86_BUILTIN_SUBSD, | |
2208 | ||
2209 | IX86_BUILTIN_CMPEQPD, | |
2210 | IX86_BUILTIN_CMPLTPD, | |
2211 | IX86_BUILTIN_CMPLEPD, | |
2212 | IX86_BUILTIN_CMPGTPD, | |
2213 | IX86_BUILTIN_CMPGEPD, | |
2214 | IX86_BUILTIN_CMPNEQPD, | |
2215 | IX86_BUILTIN_CMPNLTPD, | |
2216 | IX86_BUILTIN_CMPNLEPD, | |
2217 | IX86_BUILTIN_CMPNGTPD, | |
2218 | IX86_BUILTIN_CMPNGEPD, | |
2219 | IX86_BUILTIN_CMPORDPD, | |
2220 | IX86_BUILTIN_CMPUNORDPD, | |
2221 | IX86_BUILTIN_CMPNEPD, | |
2222 | IX86_BUILTIN_CMPEQSD, | |
2223 | IX86_BUILTIN_CMPLTSD, | |
2224 | IX86_BUILTIN_CMPLESD, | |
2225 | IX86_BUILTIN_CMPGTSD, | |
2226 | IX86_BUILTIN_CMPGESD, | |
2227 | IX86_BUILTIN_CMPNEQSD, | |
2228 | IX86_BUILTIN_CMPNLTSD, | |
2229 | IX86_BUILTIN_CMPNLESD, | |
2230 | IX86_BUILTIN_CMPNGTSD, | |
2231 | IX86_BUILTIN_CMPNGESD, | |
2232 | IX86_BUILTIN_CMPORDSD, | |
2233 | IX86_BUILTIN_CMPUNORDSD, | |
2234 | IX86_BUILTIN_CMPNESD, | |
2235 | ||
2236 | IX86_BUILTIN_COMIEQSD, | |
2237 | IX86_BUILTIN_COMILTSD, | |
2238 | IX86_BUILTIN_COMILESD, | |
2239 | IX86_BUILTIN_COMIGTSD, | |
2240 | IX86_BUILTIN_COMIGESD, | |
2241 | IX86_BUILTIN_COMINEQSD, | |
2242 | IX86_BUILTIN_UCOMIEQSD, | |
2243 | IX86_BUILTIN_UCOMILTSD, | |
2244 | IX86_BUILTIN_UCOMILESD, | |
2245 | IX86_BUILTIN_UCOMIGTSD, | |
2246 | IX86_BUILTIN_UCOMIGESD, | |
2247 | IX86_BUILTIN_UCOMINEQSD, | |
2248 | ||
2249 | IX86_BUILTIN_MAXPD, | |
2250 | IX86_BUILTIN_MAXSD, | |
2251 | IX86_BUILTIN_MINPD, | |
2252 | IX86_BUILTIN_MINSD, | |
2253 | ||
2254 | IX86_BUILTIN_ANDPD, | |
2255 | IX86_BUILTIN_ANDNPD, | |
2256 | IX86_BUILTIN_ORPD, | |
2257 | IX86_BUILTIN_XORPD, | |
2258 | ||
2259 | IX86_BUILTIN_SQRTPD, | |
2260 | IX86_BUILTIN_SQRTSD, | |
2261 | ||
2262 | IX86_BUILTIN_UNPCKHPD, | |
2263 | IX86_BUILTIN_UNPCKLPD, | |
2264 | ||
2265 | IX86_BUILTIN_SHUFPD, | |
2266 | ||
2267 | IX86_BUILTIN_LOADAPD, | |
2268 | IX86_BUILTIN_LOADUPD, | |
2269 | IX86_BUILTIN_STOREAPD, | |
2270 | IX86_BUILTIN_STOREUPD, | |
2271 | IX86_BUILTIN_LOADSD, | |
2272 | IX86_BUILTIN_STORESD, | |
2273 | IX86_BUILTIN_MOVSD, | |
2274 | ||
2275 | IX86_BUILTIN_LOADHPD, | |
2276 | IX86_BUILTIN_LOADLPD, | |
2277 | IX86_BUILTIN_STOREHPD, | |
2278 | IX86_BUILTIN_STORELPD, | |
2279 | ||
2280 | IX86_BUILTIN_CVTDQ2PD, | |
2281 | IX86_BUILTIN_CVTDQ2PS, | |
2282 | ||
2283 | IX86_BUILTIN_CVTPD2DQ, | |
2284 | IX86_BUILTIN_CVTPD2PI, | |
2285 | IX86_BUILTIN_CVTPD2PS, | |
2286 | IX86_BUILTIN_CVTTPD2DQ, | |
2287 | IX86_BUILTIN_CVTTPD2PI, | |
2288 | ||
2289 | IX86_BUILTIN_CVTPI2PD, | |
2290 | IX86_BUILTIN_CVTSI2SD, | |
2291 | ||
2292 | IX86_BUILTIN_CVTSD2SI, | |
2293 | IX86_BUILTIN_CVTSD2SS, | |
2294 | IX86_BUILTIN_CVTSS2SD, | |
2295 | IX86_BUILTIN_CVTTSD2SI, | |
2296 | ||
2297 | IX86_BUILTIN_CVTPS2DQ, | |
2298 | IX86_BUILTIN_CVTPS2PD, | |
2299 | IX86_BUILTIN_CVTTPS2DQ, | |
2300 | ||
2301 | IX86_BUILTIN_MOVNTI, | |
2302 | IX86_BUILTIN_MOVNTPD, | |
2303 | IX86_BUILTIN_MOVNTDQ, | |
2304 | ||
2305 | IX86_BUILTIN_SETPD1, | |
2306 | IX86_BUILTIN_SETPD, | |
2307 | IX86_BUILTIN_CLRPD, | |
2308 | IX86_BUILTIN_SETRPD, | |
2309 | IX86_BUILTIN_LOADPD1, | |
2310 | IX86_BUILTIN_LOADRPD, | |
2311 | IX86_BUILTIN_STOREPD1, | |
2312 | IX86_BUILTIN_STORERPD, | |
2313 | ||
2314 | /* SSE2 MMX */ | |
2315 | IX86_BUILTIN_MASKMOVDQU, | |
2316 | IX86_BUILTIN_MOVMSKPD, | |
2317 | IX86_BUILTIN_PMOVMSKB128, | |
2318 | IX86_BUILTIN_MOVQ2DQ, | |
2319 | ||
2320 | IX86_BUILTIN_PACKSSWB128, | |
2321 | IX86_BUILTIN_PACKSSDW128, | |
2322 | IX86_BUILTIN_PACKUSWB128, | |
2323 | ||
2324 | IX86_BUILTIN_PADDB128, | |
2325 | IX86_BUILTIN_PADDW128, | |
2326 | IX86_BUILTIN_PADDD128, | |
2327 | IX86_BUILTIN_PADDQ128, | |
2328 | IX86_BUILTIN_PADDSB128, | |
2329 | IX86_BUILTIN_PADDSW128, | |
2330 | IX86_BUILTIN_PADDUSB128, | |
2331 | IX86_BUILTIN_PADDUSW128, | |
2332 | IX86_BUILTIN_PSUBB128, | |
2333 | IX86_BUILTIN_PSUBW128, | |
2334 | IX86_BUILTIN_PSUBD128, | |
2335 | IX86_BUILTIN_PSUBQ128, | |
2336 | IX86_BUILTIN_PSUBSB128, | |
2337 | IX86_BUILTIN_PSUBSW128, | |
2338 | IX86_BUILTIN_PSUBUSB128, | |
2339 | IX86_BUILTIN_PSUBUSW128, | |
2340 | ||
2341 | IX86_BUILTIN_PAND128, | |
2342 | IX86_BUILTIN_PANDN128, | |
2343 | IX86_BUILTIN_POR128, | |
2344 | IX86_BUILTIN_PXOR128, | |
2345 | ||
2346 | IX86_BUILTIN_PAVGB128, | |
2347 | IX86_BUILTIN_PAVGW128, | |
2348 | ||
2349 | IX86_BUILTIN_PCMPEQB128, | |
2350 | IX86_BUILTIN_PCMPEQW128, | |
2351 | IX86_BUILTIN_PCMPEQD128, | |
2352 | IX86_BUILTIN_PCMPGTB128, | |
2353 | IX86_BUILTIN_PCMPGTW128, | |
2354 | IX86_BUILTIN_PCMPGTD128, | |
2355 | ||
2356 | IX86_BUILTIN_PEXTRW128, | |
2357 | IX86_BUILTIN_PINSRW128, | |
2358 | ||
2359 | IX86_BUILTIN_PMADDWD128, | |
2360 | ||
2361 | IX86_BUILTIN_PMAXSW128, | |
2362 | IX86_BUILTIN_PMAXUB128, | |
2363 | IX86_BUILTIN_PMINSW128, | |
2364 | IX86_BUILTIN_PMINUB128, | |
2365 | ||
2366 | IX86_BUILTIN_PMULUDQ, | |
2367 | IX86_BUILTIN_PMULUDQ128, | |
2368 | IX86_BUILTIN_PMULHUW128, | |
2369 | IX86_BUILTIN_PMULHW128, | |
2370 | IX86_BUILTIN_PMULLW128, | |
2371 | ||
2372 | IX86_BUILTIN_PSADBW128, | |
2373 | IX86_BUILTIN_PSHUFHW, | |
2374 | IX86_BUILTIN_PSHUFLW, | |
2375 | IX86_BUILTIN_PSHUFD, | |
2376 | ||
2377 | IX86_BUILTIN_PSLLW128, | |
2378 | IX86_BUILTIN_PSLLD128, | |
2379 | IX86_BUILTIN_PSLLQ128, | |
2380 | IX86_BUILTIN_PSRAW128, | |
2381 | IX86_BUILTIN_PSRAD128, | |
2382 | IX86_BUILTIN_PSRLW128, | |
2383 | IX86_BUILTIN_PSRLD128, | |
2384 | IX86_BUILTIN_PSRLQ128, | |
2385 | IX86_BUILTIN_PSLLWI128, | |
2386 | IX86_BUILTIN_PSLLDI128, | |
2387 | IX86_BUILTIN_PSLLQI128, | |
2388 | IX86_BUILTIN_PSRAWI128, | |
2389 | IX86_BUILTIN_PSRADI128, | |
2390 | IX86_BUILTIN_PSRLWI128, | |
2391 | IX86_BUILTIN_PSRLDI128, | |
2392 | IX86_BUILTIN_PSRLQI128, | |
2393 | ||
2394 | IX86_BUILTIN_PUNPCKHBW128, | |
2395 | IX86_BUILTIN_PUNPCKHWD128, | |
2396 | IX86_BUILTIN_PUNPCKHDQ128, | |
2397 | IX86_BUILTIN_PUNPCKLBW128, | |
2398 | IX86_BUILTIN_PUNPCKLWD128, | |
2399 | IX86_BUILTIN_PUNPCKLDQ128, | |
2400 | ||
2401 | IX86_BUILTIN_CLFLUSH, | |
2402 | IX86_BUILTIN_MFENCE, | |
2403 | IX86_BUILTIN_LFENCE, | |
2404 | ||
bd793c65 BS |
2405 | IX86_BUILTIN_MAX |
2406 | }; | |
bd793c65 | 2407 | \f |
f996902d RH |
2408 | #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info |
2409 | #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding | |
2410 | ||
2411 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
2412 | do { \ | |
2413 | const char *xname = (NAME); \ | |
2414 | if (xname[0] == '%') \ | |
2415 | xname += 2; \ | |
2416 | if (xname[0] == '*') \ | |
2417 | xname += 1; \ | |
2418 | else \ | |
2419 | fputs (user_label_prefix, FILE); \ | |
2420 | fputs (xname, FILE); \ | |
2421 | } while (0) | |
b08de47e | 2422 | \f |
b08de47e MM |
2423 | /* Max number of args passed in registers. If this is more than 3, we will |
2424 | have problems with ebx (register #4), since it is a caller save register and | |
2425 | is also used as the pic register in ELF. So for now, don't allow more than | |
2426 | 3 registers to be passed in registers. */ | |
2427 | ||
d2836273 JH |
2428 | #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) |
2429 | ||
df4e780e | 2430 | #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) |
b08de47e | 2431 | |
c98f8742 JVA |
2432 | \f |
2433 | /* Specify the machine mode that this machine uses | |
2434 | for the index in the tablejump instruction. */ | |
6eb791fc | 2435 | #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) |
c98f8742 | 2436 | |
18543a22 ILT |
2437 | /* Define as C expression which evaluates to nonzero if the tablejump |
2438 | instruction expects the table to contain offsets from the address of the | |
2439 | table. | |
892a2d68 | 2440 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2441 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ |
c98f8742 | 2442 | |
c98f8742 JVA |
2443 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2444 | #define DEFAULT_SIGNED_CHAR 1 | |
2445 | ||
f4365627 JH |
2446 | /* Number of bytes moved into a data cache for a single prefetch operation. */ |
2447 | #define PREFETCH_BLOCK ix86_cost->prefetch_block | |
2448 | ||
2449 | /* Number of prefetch operations that can be done in parallel. */ | |
2450 | #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches | |
2451 | ||
c98f8742 JVA |
2452 | /* Max number of bytes we can move from memory to memory |
2453 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
2454 | #define MOVE_MAX 16 |
2455 | ||
2456 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
2457 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 2458 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 2459 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 2460 | |
7e24ffc9 HPN |
2461 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
2462 | move-instruction pairs, we will do a movstr or libcall instead. | |
2463 | Increasing the value will always make code faster, but eventually | |
2464 | incurs high cost in increased code size. | |
c98f8742 | 2465 | |
e2e52e1b | 2466 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 2467 | |
e2e52e1b | 2468 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 JVA |
2469 | |
2470 | /* Define if shifts truncate the shift count | |
2471 | which implies one can omit a sign-extension or zero-extension | |
2472 | of a shift count. */ | |
892a2d68 | 2473 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
2474 | |
2475 | /* #define SHIFT_COUNT_TRUNCATED */ | |
2476 | ||
2477 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2478 | is done just by pretending it is already truncated. */ | |
2479 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2480 | ||
2481 | /* We assume that the store-condition-codes instructions store 0 for false | |
2482 | and some other value for true. This is the value stored for true. */ | |
2483 | ||
2484 | #define STORE_FLAG_VALUE 1 | |
2485 | ||
2486 | /* When a prototype says `char' or `short', really pass an `int'. | |
2487 | (The 386 can't easily push less than an int.) */ | |
2488 | ||
cb560352 | 2489 | #define PROMOTE_PROTOTYPES 1 |
c98f8742 | 2490 | |
d9f32422 JH |
2491 | /* A macro to update M and UNSIGNEDP when an object whose type is |
2492 | TYPE and which has the specified mode and signedness is to be | |
2493 | stored in a register. This macro is only called when TYPE is a | |
2494 | scalar type. | |
2495 | ||
f710504c | 2496 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
2497 | quantities to SImode. The choice depends on target type. */ |
2498 | ||
2499 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 2500 | do { \ |
d9f32422 JH |
2501 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
2502 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
2503 | (MODE) = SImode; \ |
2504 | } while (0) | |
d9f32422 | 2505 | |
c98f8742 JVA |
2506 | /* Specify the machine mode that pointers have. |
2507 | After generation of rtl, the compiler makes no further distinction | |
2508 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 2509 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
2510 | |
2511 | /* A function address in a call instruction | |
2512 | is a byte address (for indexing purposes) | |
2513 | so give the MEM rtx a byte's mode. */ | |
2514 | #define FUNCTION_MODE QImode | |
d4ba09c0 SC |
2515 | \f |
2516 | /* A part of a C `switch' statement that describes the relative costs | |
2517 | of constant RTL expressions. It must contain `case' labels for | |
2518 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
2519 | and `const_double'. Each case must ultimately reach a `return' | |
2520 | statement to return the relative cost of the use of that kind of | |
2521 | constant value in an expression. The cost may depend on the | |
2522 | precise value of the constant, which is available for examination | |
2523 | in X, and the rtx code of the expression in which it is contained, | |
2524 | found in OUTER_CODE. | |
fce5a9f2 | 2525 | |
d4ba09c0 SC |
2526 | CODE is the expression code--redundant, since it can be obtained |
2527 | with `GET_CODE (X)'. */ | |
c98f8742 | 2528 | |
d9a5f180 | 2529 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
c98f8742 JVA |
2530 | case CONST_INT: \ |
2531 | case CONST: \ | |
2532 | case LABEL_REF: \ | |
2533 | case SYMBOL_REF: \ | |
44cf5b6a JH |
2534 | if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ |
2535 | return 3; \ | |
2536 | if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ | |
2537 | return 2; \ | |
1acc845e | 2538 | return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ |
d4ba09c0 | 2539 | \ |
c98f8742 | 2540 | case CONST_DOUBLE: \ |
51286de6 RH |
2541 | if (GET_MODE (RTX) == VOIDmode) \ |
2542 | return 0; \ | |
2543 | switch (standard_80387_constant_p (RTX)) \ | |
2544 | { \ | |
2545 | case 1: /* 0.0 */ \ | |
2546 | return 1; \ | |
2547 | case 2: /* 1.0 */ \ | |
2548 | return 2; \ | |
2549 | default: \ | |
2550 | /* Start with (MEM (SYMBOL_REF)), since that's where \ | |
2551 | it'll probably end up. Add a penalty for size. */ \ | |
2552 | return (COSTS_N_INSNS (1) + (flag_pic != 0) \ | |
2553 | + (GET_MODE (RTX) == SFmode ? 0 \ | |
2554 | : GET_MODE (RTX) == DFmode ? 1 : 2)); \ | |
2555 | } | |
c98f8742 | 2556 | |
76565a24 | 2557 | /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ |
e075ae69 RH |
2558 | #define TOPLEVEL_COSTS_N_INSNS(N) \ |
2559 | do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) | |
76565a24 | 2560 | |
d4ba09c0 SC |
2561 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. |
2562 | This can be used, for example, to indicate how costly a multiply | |
2563 | instruction is. In writing this macro, you can use the construct | |
2564 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
2565 | instructions. OUTER_CODE is the code of the expression in which X | |
2566 | is contained. | |
2567 | ||
2568 | This macro is optional; do not define it if the default cost | |
2569 | assumptions are adequate for the target machine. */ | |
2570 | ||
d9a5f180 | 2571 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ |
44cf5b6a JH |
2572 | case ZERO_EXTEND: \ |
2573 | /* The zero extensions is often completely free on x86_64, so make \ | |
2574 | it as cheap as possible. */ \ | |
2575 | if (TARGET_64BIT && GET_MODE (X) == DImode \ | |
2576 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
2577 | { \ | |
2578 | total = 1; goto egress_rtx_costs; \ | |
2579 | } \ | |
2580 | else \ | |
2581 | TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ | |
2582 | ix86_cost->add : ix86_cost->movzx); \ | |
2583 | break; \ | |
2584 | case SIGN_EXTEND: \ | |
2585 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ | |
2586 | break; \ | |
d4ba09c0 SC |
2587 | case ASHIFT: \ |
2588 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
44cf5b6a | 2589 | && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ |
d4ba09c0 SC |
2590 | { \ |
2591 | HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
d4ba09c0 | 2592 | if (value == 1) \ |
e075ae69 | 2593 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ |
b972dd02 JH |
2594 | if ((value == 2 || value == 3) \ |
2595 | && !TARGET_DECOMPOSE_LEA \ | |
2596 | && ix86_cost->lea <= ix86_cost->shift_const) \ | |
e075ae69 | 2597 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ |
d4ba09c0 SC |
2598 | } \ |
2599 | /* fall through */ \ | |
2600 | \ | |
2601 | case ROTATE: \ | |
2602 | case ASHIFTRT: \ | |
2603 | case LSHIFTRT: \ | |
2604 | case ROTATERT: \ | |
44cf5b6a | 2605 | if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ |
76565a24 SC |
2606 | { \ |
2607 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
54d26233 MH |
2608 | { \ |
2609 | if (INTVAL (XEXP (X, 1)) > 32) \ | |
e075ae69 RH |
2610 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ |
2611 | else \ | |
2612 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ | |
2613 | } \ | |
2614 | else \ | |
2615 | { \ | |
2616 | if (GET_CODE (XEXP (X, 1)) == AND) \ | |
2617 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ | |
2618 | else \ | |
2619 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ | |
54d26233 | 2620 | } \ |
76565a24 | 2621 | } \ |
e075ae69 RH |
2622 | else \ |
2623 | { \ | |
2624 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2625 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ | |
2626 | else \ | |
2627 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ | |
2628 | } \ | |
2629 | break; \ | |
d4ba09c0 SC |
2630 | \ |
2631 | case MULT: \ | |
2632 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2633 | { \ | |
2634 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
2635 | int nbits = 0; \ | |
2636 | \ | |
2637 | while (value != 0) \ | |
2638 | { \ | |
2639 | nbits++; \ | |
2640 | value >>= 1; \ | |
2641 | } \ | |
2642 | \ | |
630c79be BS |
2643 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
2644 | + nbits * ix86_cost->mult_bit); \ | |
d4ba09c0 | 2645 | } \ |
d4ba09c0 | 2646 | else /* This is arbitrary */ \ |
76565a24 SC |
2647 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
2648 | + 7 * ix86_cost->mult_bit); \ | |
d4ba09c0 SC |
2649 | \ |
2650 | case DIV: \ | |
2651 | case UDIV: \ | |
2652 | case MOD: \ | |
2653 | case UMOD: \ | |
76565a24 | 2654 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ |
d4ba09c0 SC |
2655 | \ |
2656 | case PLUS: \ | |
b972dd02 JH |
2657 | if (!TARGET_DECOMPOSE_LEA \ |
2658 | && INTEGRAL_MODE_P (GET_MODE (X)) \ | |
2659 | && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ | |
e075ae69 | 2660 | { \ |
b972dd02 JH |
2661 | if (GET_CODE (XEXP (X, 0)) == PLUS \ |
2662 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ | |
2663 | && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ | |
2664 | && CONSTANT_P (XEXP (X, 1))) \ | |
e075ae69 | 2665 | { \ |
b972dd02 JH |
2666 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ |
2667 | if (val == 2 || val == 4 || val == 8) \ | |
2668 | { \ | |
2669 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2670 | + rtx_cost (XEXP (XEXP (X, 0), 1), \ |
2671 | (OUTER_CODE)) \ | |
2672 | + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ | |
2673 | (OUTER_CODE)) \ | |
2674 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
b972dd02 | 2675 | } \ |
e075ae69 | 2676 | } \ |
b972dd02 JH |
2677 | else if (GET_CODE (XEXP (X, 0)) == MULT \ |
2678 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
2679 | { \ | |
2680 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
2681 | if (val == 2 || val == 4 || val == 8) \ | |
2682 | { \ | |
2683 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2684 | + rtx_cost (XEXP (XEXP (X, 0), 0), \ |
2685 | (OUTER_CODE)) \ | |
2686 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
b972dd02 JH |
2687 | } \ |
2688 | } \ | |
2689 | else if (GET_CODE (XEXP (X, 0)) == PLUS) \ | |
e075ae69 RH |
2690 | { \ |
2691 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2692 | + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ |
2693 | + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ | |
2694 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
e075ae69 | 2695 | } \ |
e075ae69 | 2696 | } \ |
d4ba09c0 SC |
2697 | \ |
2698 | /* fall through */ \ | |
2699 | case AND: \ | |
2700 | case IOR: \ | |
2701 | case XOR: \ | |
2702 | case MINUS: \ | |
44cf5b6a | 2703 | if (!TARGET_64BIT && GET_MODE (X) == DImode) \ |
e075ae69 | 2704 | return (COSTS_N_INSNS (ix86_cost->add) * 2 \ |
d9a5f180 | 2705 | + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ |
e075ae69 | 2706 | << (GET_MODE (XEXP (X, 0)) != DImode)) \ |
d9a5f180 | 2707 | + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ |
e075ae69 RH |
2708 | << (GET_MODE (XEXP (X, 1)) != DImode))); \ |
2709 | \ | |
2710 | /* fall through */ \ | |
d4ba09c0 SC |
2711 | case NEG: \ |
2712 | case NOT: \ | |
44cf5b6a | 2713 | if (!TARGET_64BIT && GET_MODE (X) == DImode) \ |
e075ae69 RH |
2714 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ |
2715 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ | |
2716 | \ | |
51286de6 | 2717 | case FLOAT_EXTEND: \ |
285464d0 JH |
2718 | if (!TARGET_SSE_MATH \ |
2719 | || !VALID_SSE_REG_MODE (GET_MODE (X))) \ | |
2720 | TOPLEVEL_COSTS_N_INSNS (0); \ | |
2721 | break; \ | |
51286de6 | 2722 | \ |
e075ae69 RH |
2723 | egress_rtx_costs: \ |
2724 | break; | |
d4ba09c0 SC |
2725 | |
2726 | ||
2727 | /* An expression giving the cost of an addressing mode that contains | |
2728 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
2729 | expression and the `CONST_COSTS' values. | |
2730 | ||
2731 | For most CISC machines, the default cost is a good approximation | |
2732 | of the true cost of the addressing mode. However, on RISC | |
2733 | machines, all instructions normally have the same length and | |
2734 | execution time. Hence all addresses will have equal costs. | |
2735 | ||
2736 | In cases where more than one form of an address is known, the form | |
2737 | with the lowest cost will be used. If multiple forms have the | |
2738 | same, lowest, cost, the one that is the most complex will be used. | |
2739 | ||
2740 | For example, suppose an address that is equal to the sum of a | |
2741 | register and a constant is used twice in the same basic block. | |
2742 | When this macro is not defined, the address will be computed in a | |
2743 | register and memory references will be indirect through that | |
2744 | register. On machines where the cost of the addressing mode | |
2745 | containing the sum is no higher than that of a simple indirect | |
2746 | reference, this will produce an additional instruction and | |
2747 | possibly require an additional register. Proper specification of | |
2748 | this macro eliminates this overhead for such machines. | |
2749 | ||
2750 | Similar use of this macro is made in strength reduction of loops. | |
2751 | ||
2752 | ADDRESS need not be valid as an address. In such a case, the cost | |
2753 | is not relevant and can be any value; invalid addresses need not be | |
2754 | assigned a different cost. | |
2755 | ||
2756 | On machines where an address involving more than one register is as | |
2757 | cheap as an address computation involving only one register, | |
2758 | defining `ADDRESS_COST' to reflect this can cause two registers to | |
2759 | be live over a region of code where only one would have been if | |
2760 | `ADDRESS_COST' were not defined in that manner. This effect should | |
2761 | be considered in the definition of this macro. Equivalent costs | |
2762 | should probably only be given to addresses with different numbers | |
2763 | of registers on machines with lots of registers. | |
2764 | ||
2765 | This macro will normally either not be defined or be defined as a | |
2766 | constant. | |
c98f8742 JVA |
2767 | |
2768 | For i386, it is better to use a complex address than let gcc copy | |
2769 | the address into a reg and make a new pseudo. But not if the address | |
2770 | requires to two regs - that would mean more pseudos with longer | |
2771 | lifetimes. */ | |
2772 | ||
2773 | #define ADDRESS_COST(RTX) \ | |
0806f95f | 2774 | ix86_address_cost (RTX) |
d4ba09c0 | 2775 | |
96e7ae40 JH |
2776 | /* A C expression for the cost of moving data from a register in class FROM to |
2777 | one in class TO. The classes are expressed using the enumeration values | |
2778 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
2779 | interpreted relative to that. | |
d4ba09c0 | 2780 | |
96e7ae40 JH |
2781 | It is not required that the cost always equal 2 when FROM is the same as TO; |
2782 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 2783 | general registers. */ |
d4ba09c0 | 2784 | |
f84aa48a | 2785 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 2786 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
2787 | |
2788 | /* A C expression for the cost of moving data of mode M between a | |
2789 | register and memory. A value of 2 is the default; this cost is | |
2790 | relative to those in `REGISTER_MOVE_COST'. | |
2791 | ||
2792 | If moving between registers and memory is more expensive than | |
2793 | between two registers, you should define this macro to express the | |
fa79946e | 2794 | relative cost. */ |
d4ba09c0 | 2795 | |
d9a5f180 GS |
2796 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
2797 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
2798 | |
2799 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2800 | is the default; other values are interpreted relative to that. */ | |
2801 | ||
e075ae69 | 2802 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
2803 | |
2804 | /* Define this macro as a C expression which is nonzero if accessing | |
2805 | less than a word of memory (i.e. a `char' or a `short') is no | |
2806 | faster than accessing a word of memory, i.e., if such access | |
2807 | require more than one instruction or if there is no difference in | |
2808 | cost between byte and (aligned) word loads. | |
2809 | ||
2810 | When this macro is not defined, the compiler will access a field by | |
2811 | finding the smallest containing object; when it is defined, a | |
2812 | fullword load will be used if alignment permits. Unless bytes | |
2813 | accesses are faster than word accesses, using word accesses is | |
2814 | preferable since it may eliminate subsequent memory access if | |
2815 | subsequent accesses occur to other fields in the same word of the | |
2816 | structure, but to different bytes. */ | |
2817 | ||
2818 | #define SLOW_BYTE_ACCESS 0 | |
2819 | ||
2820 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2821 | #define SLOW_SHORT_ACCESS 0 | |
2822 | ||
d4ba09c0 SC |
2823 | /* Define this macro to be the value 1 if unaligned accesses have a |
2824 | cost many times greater than aligned accesses, for example if they | |
2825 | are emulated in a trap handler. | |
2826 | ||
9cd10576 KH |
2827 | When this macro is nonzero, the compiler will act as if |
2828 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2829 | moves. This can cause significantly more instructions to be |
9cd10576 | 2830 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2831 | accesses only add a cycle or two to the time for a memory access. |
2832 | ||
2833 | If the value of this macro is always zero, it need not be defined. */ | |
2834 | ||
e1565e65 | 2835 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 SC |
2836 | |
2837 | /* Define this macro to inhibit strength reduction of memory | |
2838 | addresses. (On some machines, such strength reduction seems to do | |
2839 | harm rather than good.) */ | |
2840 | ||
2841 | /* #define DONT_REDUCE_ADDR */ | |
2842 | ||
2843 | /* Define this macro if it is as good or better to call a constant | |
2844 | function address than to call an address kept in a register. | |
2845 | ||
2846 | Desirable on the 386 because a CALL with a constant address is | |
2847 | faster than one with a register address. */ | |
2848 | ||
2849 | #define NO_FUNCTION_CSE | |
2850 | ||
2851 | /* Define this macro if it is as good or better for a function to call | |
2852 | itself with an explicit address than to call an address kept in a | |
2853 | register. */ | |
2854 | ||
2855 | #define NO_RECURSIVE_FUNCTION_CSE | |
c98f8742 | 2856 | \f |
c572e5ba JVA |
2857 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2858 | return the mode to be used for the comparison. | |
2859 | ||
2860 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2861 | VOIDmode should be used in all other cases. |
c572e5ba | 2862 | |
16189740 | 2863 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2864 | possible, to allow for more combinations. */ |
c98f8742 | 2865 | |
d9a5f180 | 2866 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2867 | |
9cd10576 | 2868 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2869 | reversed. */ |
2870 | ||
2871 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2872 | ||
2873 | /* A C expression whose value is reversed condition code of the CODE for | |
2874 | comparison done in CC_MODE mode. */ | |
2875 | #define REVERSE_CONDITION(CODE, MODE) \ | |
2876 | ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ | |
2877 | : reverse_condition_maybe_unordered (CODE)) | |
2878 | ||
c98f8742 JVA |
2879 | \f |
2880 | /* Control the assembler format that we output, to the extent | |
2881 | this does not vary between assemblers. */ | |
2882 | ||
2883 | /* How to refer to registers in assembler output. | |
892a2d68 | 2884 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 JVA |
2885 | |
2886 | /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" | |
2887 | For non floating point regs, the following are the HImode names. | |
2888 | ||
2889 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
9e06e321 | 2890 | instead of just "%st". PRINT_REG handles this with the "y" code. */ |
c98f8742 | 2891 | |
fce5a9f2 | 2892 | #undef HI_REGISTER_NAMES |
a7180f70 BS |
2893 | #define HI_REGISTER_NAMES \ |
2894 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
2895 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ | |
2896 | "flags","fpsr", "dirflag", "frame", \ | |
2897 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ | |
3f3f2124 JH |
2898 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ |
2899 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2900 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 2901 | |
c98f8742 JVA |
2902 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2903 | ||
2904 | /* Table of additional register names to use in user input. */ | |
2905 | ||
2906 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
2907 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2908 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
2909 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
2910 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 2911 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
a7180f70 BS |
2912 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ |
2913 | { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ | |
2914 | { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } | |
c98f8742 JVA |
2915 | |
2916 | /* Note we are omitting these since currently I don't know how | |
2917 | to get gcc to use these, since they want the same but different | |
2918 | number as al, and ax. | |
2919 | */ | |
2920 | ||
c98f8742 | 2921 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2922 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2923 | |
2924 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2925 | of regs 0 through 3. */ |
c98f8742 JVA |
2926 | |
2927 | #define QI_HIGH_REGISTER_NAMES \ | |
2928 | {"ah", "dh", "ch", "bh", } | |
2929 | ||
2930 | /* How to renumber registers for dbx and gdb. */ | |
2931 | ||
d9a5f180 GS |
2932 | #define DBX_REGISTER_NUMBER(N) \ |
2933 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 RH |
2934 | |
2935 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
0f7fa3d0 | 2936 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; |
83774849 | 2937 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; |
c98f8742 | 2938 | |
469ac993 JM |
2939 | /* Before the prologue, RA is at 0(%esp). */ |
2940 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2941 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2942 | |
e414ab29 | 2943 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2944 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2945 | ((COUNT) == 0 \ | |
2946 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2947 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2948 | |
892a2d68 | 2949 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2950 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2951 | |
a6ab3aad | 2952 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2953 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2954 | |
1020a5ab RH |
2955 | /* Describe how we implement __builtin_eh_return. */ |
2956 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2957 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2958 | ||
ad919812 | 2959 | |
e4c4ebeb RH |
2960 | /* Select a format to encode pointers in exception handling data. CODE |
2961 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2962 | true if the symbol may be affected by dynamic relocations. | |
2963 | ||
2964 | ??? All x86 object file formats are capable of representing this. | |
2965 | After all, the relocation needed is the same as for the call insn. | |
2966 | Whether or not a particular assembler allows us to enter such, I | |
2967 | guess we'll have to see. */ | |
d9a5f180 | 2968 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
b932f770 | 2969 | (flag_pic \ |
d9a5f180 | 2970 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ |
e4c4ebeb RH |
2971 | : DW_EH_PE_absptr) |
2972 | ||
c98f8742 JVA |
2973 | /* Store in OUTPUT a string (made with alloca) containing |
2974 | an assembler-name for a local static variable named NAME. | |
2975 | LABELNO is an integer which is different for each call. */ | |
2976 | ||
2977 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2978 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2979 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2980 | ||
c98f8742 JVA |
2981 | /* This is how to output an insn to push a register on the stack. |
2982 | It need not be very fast code. */ | |
2983 | ||
d9a5f180 GS |
2984 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
2985 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]) | |
c98f8742 JVA |
2986 | |
2987 | /* This is how to output an insn to pop a register from the stack. | |
2988 | It need not be very fast code. */ | |
2989 | ||
d9a5f180 GS |
2990 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
2991 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]) | |
c98f8742 | 2992 | |
f88c65f7 | 2993 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2994 | |
2995 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2996 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2997 | |
f88c65f7 | 2998 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2999 | |
33f7f353 | 3000 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 3001 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 RH |
3002 | |
3003 | /* Under some conditions we need jump tables in the text section, because | |
3004 | the assembler cannot handle label differences between sections. */ | |
3005 | ||
3006 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
3007 | (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) | |
c98f8742 | 3008 | |
fce5a9f2 | 3009 | /* A C statement that outputs an address constant appropriate to |
1865dbb5 JM |
3010 | for DWARF debugging. */ |
3011 | ||
d9a5f180 GS |
3012 | #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ |
3013 | i386_dwarf_output_addr_const ((FILE), (X)) | |
1865dbb5 JM |
3014 | |
3015 | /* Either simplify a location expression, or return the original. */ | |
3016 | ||
3017 | #define ASM_SIMPLIFY_DWARF_ADDR(X) \ | |
d9a5f180 | 3018 | i386_simplify_dwarf_addr (X) |
cea3bd3e | 3019 | |
b9203463 RH |
3020 | /* Emit a dtp-relative reference to a TLS variable. */ |
3021 | ||
3022 | #ifdef HAVE_AS_TLS | |
3023 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
3024 | i386_output_dwarf_dtprel (FILE, SIZE, X) | |
3025 | #endif | |
3026 | ||
cea3bd3e RH |
3027 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
3028 | and switch back. For x86 we do this only to save a few bytes that | |
3029 | would otherwise be unused in the text section. */ | |
3030 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
3031 | asm (SECTION_OP "\n\t" \ | |
3032 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
3033 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 3034 | \f |
c98f8742 JVA |
3035 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
3036 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
3037 | Effect of various CODE letters is described in i386.c near |
3038 | print_operand function. */ | |
c98f8742 | 3039 | |
d9a5f180 | 3040 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
f996902d | 3041 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') |
c98f8742 | 3042 | |
74b42c8b RS |
3043 | /* Print the name of a register based on its machine mode and number. |
3044 | If CODE is 'w', pretend the mode is HImode. | |
3045 | If CODE is 'b', pretend the mode is QImode. | |
3046 | If CODE is 'k', pretend the mode is SImode. | |
ef6257cd | 3047 | If CODE is 'q', pretend the mode is DImode. |
74b42c8b | 3048 | If CODE is 'h', pretend the reg is the `high' byte register. |
ef6257cd | 3049 | If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ |
74b42c8b | 3050 | |
e075ae69 | 3051 | #define PRINT_REG(X, CODE, FILE) \ |
d9a5f180 | 3052 | print_reg ((X), (CODE), (FILE)) |
74b42c8b | 3053 | |
c98f8742 | 3054 | #define PRINT_OPERAND(FILE, X, CODE) \ |
d9a5f180 | 3055 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
3056 | |
3057 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 3058 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 3059 | |
f996902d RH |
3060 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
3061 | do { \ | |
3062 | if (! output_addr_const_extra (FILE, (X))) \ | |
3063 | goto FAIL; \ | |
3064 | } while (0); | |
3065 | ||
aa3e8d2a JVA |
3066 | /* Print the name of a register for based on its machine mode and number. |
3067 | This macro is used to print debugging output. | |
3068 | This macro is different from PRINT_REG in that it may be used in | |
3069 | programs that are not linked with aux-output.o. */ | |
3070 | ||
e075ae69 | 3071 | #define DEBUG_PRINT_REG(X, CODE, FILE) \ |
69ddee61 KG |
3072 | do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ |
3073 | static const char * const qi_name[] = QI_REGISTER_NAMES; \ | |
d9a5f180 | 3074 | fprintf ((FILE), "%d ", REGNO (X)); \ |
e075ae69 | 3075 | if (REGNO (X) == FLAGS_REG) \ |
d9a5f180 | 3076 | { fputs ("flags", (FILE)); break; } \ |
7c7ef435 | 3077 | if (REGNO (X) == DIRFLAG_REG) \ |
d9a5f180 | 3078 | { fputs ("dirflag", (FILE)); break; } \ |
e075ae69 | 3079 | if (REGNO (X) == FPSR_REG) \ |
d9a5f180 | 3080 | { fputs ("fpsr", (FILE)); break; } \ |
aa3e8d2a | 3081 | if (REGNO (X) == ARG_POINTER_REGNUM) \ |
d9a5f180 | 3082 | { fputs ("argp", (FILE)); break; } \ |
564d80f4 | 3083 | if (REGNO (X) == FRAME_POINTER_REGNUM) \ |
d9a5f180 | 3084 | { fputs ("frame", (FILE)); break; } \ |
aa3e8d2a | 3085 | if (STACK_TOP_P (X)) \ |
d9a5f180 | 3086 | { fputs ("st(0)", (FILE)); break; } \ |
b0ceea8c | 3087 | if (FP_REG_P (X)) \ |
d9a5f180 | 3088 | { fputs (hi_name[REGNO(X)], (FILE)); break; } \ |
3f3f2124 JH |
3089 | if (REX_INT_REG_P (X)) \ |
3090 | { \ | |
3091 | switch (GET_MODE_SIZE (GET_MODE (X))) \ | |
3092 | { \ | |
3093 | default: \ | |
3094 | case 8: \ | |
d9a5f180 | 3095 | fprintf ((FILE), "r%i", REGNO (X) \ |
3f3f2124 JH |
3096 | - FIRST_REX_INT_REG + 8); \ |
3097 | break; \ | |
3098 | case 4: \ | |
d9a5f180 | 3099 | fprintf ((FILE), "r%id", REGNO (X) \ |
3f3f2124 JH |
3100 | - FIRST_REX_INT_REG + 8); \ |
3101 | break; \ | |
3102 | case 2: \ | |
d9a5f180 | 3103 | fprintf ((FILE), "r%iw", REGNO (X) \ |
3f3f2124 JH |
3104 | - FIRST_REX_INT_REG + 8); \ |
3105 | break; \ | |
3106 | case 1: \ | |
d9a5f180 | 3107 | fprintf ((FILE), "r%ib", REGNO (X) \ |
3f3f2124 JH |
3108 | - FIRST_REX_INT_REG + 8); \ |
3109 | break; \ | |
3110 | } \ | |
3111 | break; \ | |
3112 | } \ | |
aa3e8d2a JVA |
3113 | switch (GET_MODE_SIZE (GET_MODE (X))) \ |
3114 | { \ | |
3f3f2124 | 3115 | case 8: \ |
d9a5f180 GS |
3116 | fputs ("r", (FILE)); \ |
3117 | fputs (hi_name[REGNO (X)], (FILE)); \ | |
3f3f2124 | 3118 | break; \ |
b0ceea8c | 3119 | default: \ |
d9a5f180 | 3120 | fputs ("e", (FILE)); \ |
aa3e8d2a | 3121 | case 2: \ |
d9a5f180 | 3122 | fputs (hi_name[REGNO (X)], (FILE)); \ |
aa3e8d2a JVA |
3123 | break; \ |
3124 | case 1: \ | |
d9a5f180 | 3125 | fputs (qi_name[REGNO (X)], (FILE)); \ |
aa3e8d2a JVA |
3126 | break; \ |
3127 | } \ | |
3128 | } while (0) | |
3129 | ||
c98f8742 JVA |
3130 | /* a letter which is not needed by the normal asm syntax, which |
3131 | we can use for operand syntax in the extended asm */ | |
3132 | ||
3133 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 3134 | #define RET return "" |
d9a5f180 | 3135 | #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) |
d4ba09c0 | 3136 | \f |
e075ae69 RH |
3137 | /* Define the codes that are matched by predicates in i386.c. */ |
3138 | ||
3139 | #define PREDICATE_CODES \ | |
7dd4b4a3 JH |
3140 | {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ |
3141 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3142 | {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ | |
3143 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3144 | {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ | |
3145 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3146 | {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ | |
3147 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3148 | {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ | |
3149 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3150 | {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ | |
3151 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3152 | {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ | |
3153 | SYMBOL_REF, LABEL_REF}}, \ | |
371bc54b | 3154 | {"shiftdi_operand", {SUBREG, REG, MEM}}, \ |
8bad7136 | 3155 | {"const_int_1_operand", {CONST_INT}}, \ |
794a292d | 3156 | {"const_int_1_31_operand", {CONST_INT}}, \ |
e075ae69 | 3157 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ |
2247f6ed JH |
3158 | {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
3159 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
e075ae69 | 3160 | {"pic_symbolic_operand", {CONST}}, \ |
e1ff012c | 3161 | {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ |
eaf19aba | 3162 | {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ |
e075ae69 RH |
3163 | {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ |
3164 | {"const1_operand", {CONST_INT}}, \ | |
3165 | {"const248_operand", {CONST_INT}}, \ | |
3166 | {"incdec_operand", {CONST_INT}}, \ | |
915119a5 | 3167 | {"mmx_reg_operand", {REG}}, \ |
e075ae69 | 3168 | {"reg_no_sp_operand", {SUBREG, REG}}, \ |
2c5a510c RH |
3169 | {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ |
3170 | SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ | |
3171 | {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ | |
7ec70495 | 3172 | {"index_register_operand", {SUBREG, REG}}, \ |
e075ae69 RH |
3173 | {"q_regs_operand", {SUBREG, REG}}, \ |
3174 | {"non_q_regs_operand", {SUBREG, REG}}, \ | |
9e7adcb3 JH |
3175 | {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ |
3176 | ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ | |
3177 | GE, UNGE, LTGT, UNEQ}}, \ | |
bf71a4f8 JH |
3178 | {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ |
3179 | ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ | |
3180 | }}, \ | |
9076b9c1 | 3181 | {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ |
9e7adcb3 JH |
3182 | GTU, UNORDERED, ORDERED, UNLE, UNLT, \ |
3183 | UNGE, UNGT, LTGT, UNEQ }}, \ | |
e075ae69 RH |
3184 | {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ |
3185 | {"ext_register_operand", {SUBREG, REG}}, \ | |
3186 | {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ | |
3187 | {"mult_operator", {MULT}}, \ | |
3188 | {"div_operator", {DIV}}, \ | |
3189 | {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ | |
3190 | UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ | |
3191 | UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ | |
3192 | LSHIFTRT, ROTATERT}}, \ | |
e9e80858 | 3193 | {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ |
e075ae69 RH |
3194 | {"memory_displacement_operand", {MEM}}, \ |
3195 | {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
6343a50e | 3196 | LABEL_REF, SUBREG, REG, MEM, AND}}, \ |
f996902d RH |
3197 | {"long_memory_operand", {MEM}}, \ |
3198 | {"tls_symbolic_operand", {SYMBOL_REF}}, \ | |
3199 | {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ | |
3200 | {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ | |
3201 | {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ | |
c3c637e3 GS |
3202 | {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ |
3203 | {"any_fp_register_operand", {REG}}, \ | |
3204 | {"register_and_not_any_fp_reg_operand", {REG}}, \ | |
3205 | {"fp_register_operand", {REG}}, \ | |
3206 | {"register_and_not_fp_reg_operand", {REG}}, \ | |
c76aab11 RH |
3207 | |
3208 | /* A list of predicates that do special things with modes, and so | |
3209 | should not elicit warnings for VOIDmode match_operand. */ | |
3210 | ||
3211 | #define SPECIAL_MODE_PREDICATES \ | |
3212 | "ext_register_operand", | |
c98f8742 | 3213 | \f |
5bf0ebab RH |
3214 | /* Which processor to schedule for. The cpu attribute defines a list that |
3215 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
3216 | ||
3217 | enum processor_type | |
3218 | { | |
3219 | PROCESSOR_I386, /* 80386 */ | |
3220 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
3221 | PROCESSOR_PENTIUM, | |
3222 | PROCESSOR_PENTIUMPRO, | |
3223 | PROCESSOR_K6, | |
3224 | PROCESSOR_ATHLON, | |
3225 | PROCESSOR_PENTIUM4, | |
3226 | PROCESSOR_max | |
3227 | }; | |
3228 | ||
3229 | extern enum processor_type ix86_cpu; | |
3230 | extern const char *ix86_cpu_string; | |
3231 | ||
3232 | extern enum processor_type ix86_arch; | |
3233 | extern const char *ix86_arch_string; | |
3234 | ||
3235 | enum fpmath_unit | |
3236 | { | |
3237 | FPMATH_387 = 1, | |
3238 | FPMATH_SSE = 2 | |
3239 | }; | |
3240 | ||
3241 | extern enum fpmath_unit ix86_fpmath; | |
3242 | extern const char *ix86_fpmath_string; | |
3243 | ||
f996902d RH |
3244 | enum tls_dialect |
3245 | { | |
3246 | TLS_DIALECT_GNU, | |
3247 | TLS_DIALECT_SUN | |
3248 | }; | |
3249 | ||
3250 | extern enum tls_dialect ix86_tls_dialect; | |
3251 | extern const char *ix86_tls_dialect_string; | |
3252 | ||
6189a572 | 3253 | enum cmodel { |
5bf0ebab RH |
3254 | CM_32, /* The traditional 32-bit ABI. */ |
3255 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
3256 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
3257 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
3258 | CM_LARGE, /* No assumptions. */ | |
3259 | CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ | |
6189a572 JH |
3260 | }; |
3261 | ||
5bf0ebab RH |
3262 | extern enum cmodel ix86_cmodel; |
3263 | extern const char *ix86_cmodel_string; | |
3264 | ||
8362f420 JH |
3265 | /* Size of the RED_ZONE area. */ |
3266 | #define RED_ZONE_SIZE 128 | |
3267 | /* Reserved area of the red zone for temporaries. */ | |
3268 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
3269 | |
3270 | enum asm_dialect { | |
3271 | ASM_ATT, | |
3272 | ASM_INTEL | |
3273 | }; | |
5bf0ebab | 3274 | |
c93e80a5 | 3275 | extern const char *ix86_asm_string; |
80f33d06 | 3276 | extern enum asm_dialect ix86_asm_dialect; |
5bf0ebab RH |
3277 | |
3278 | extern int ix86_regparm; | |
fce5a9f2 | 3279 | extern const char *ix86_regparm_string; |
5bf0ebab RH |
3280 | |
3281 | extern int ix86_preferred_stack_boundary; | |
3282 | extern const char *ix86_preferred_stack_boundary_string; | |
3283 | ||
3284 | extern int ix86_branch_cost; | |
3285 | extern const char *ix86_branch_cost_string; | |
3286 | ||
3287 | extern const char *ix86_debug_arg_string; | |
3288 | extern const char *ix86_debug_addr_string; | |
3289 | ||
3290 | /* Obsoleted by -f options. Remove before 3.2 ships. */ | |
3291 | extern const char *ix86_align_loops_string; | |
3292 | extern const char *ix86_align_jumps_string; | |
3293 | extern const char *ix86_align_funcs_string; | |
3294 | ||
3295 | /* Smallest class containing REGNO. */ | |
3296 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
3297 | ||
d9a5f180 GS |
3298 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
3299 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
22fb740d JH |
3300 | \f |
3301 | /* To properly truncate FP values into integers, we need to set i387 control | |
3302 | word. We can't emit proper mode switching code before reload, as spills | |
3303 | generated by reload may truncate values incorrectly, but we still can avoid | |
3304 | redundant computation of new control word by the mode switching pass. | |
3305 | The fldcw instructions are still emitted redundantly, but this is probably | |
3306 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 3307 | the sequence. |
22fb740d JH |
3308 | |
3309 | The machinery is to emit simple truncation instructions and split them | |
3310 | before reload to instructions having USEs of two memory locations that | |
3311 | are filled by this code to old and new control word. | |
fce5a9f2 | 3312 | |
22fb740d JH |
3313 | Post-reload pass may be later used to eliminate the redundant fildcw if |
3314 | needed. */ | |
3315 | ||
3316 | enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; | |
3317 | ||
3318 | /* Define this macro if the port needs extra instructions inserted | |
3319 | for mode switching in an optimizing compilation. */ | |
3320 | ||
3321 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 | |
3322 | ||
3323 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
3324 | initializer for an array of integers. Each initializer element N | |
3325 | refers to an entity that needs mode switching, and specifies the | |
3326 | number of different modes that might need to be set for this | |
3327 | entity. The position of the initializer in the initializer - | |
3328 | starting counting at zero - determines the integer that is used to | |
3329 | refer to the mode-switched entity in question. */ | |
3330 | ||
3331 | #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } | |
3332 | ||
3333 | /* ENTITY is an integer specifying a mode-switched entity. If | |
3334 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
3335 | return an integer value not larger than the corresponding element | |
3336 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
3337 | must be switched into prior to the execution of INSN. */ | |
3338 | ||
3339 | #define MODE_NEEDED(ENTITY, I) \ | |
3340 | (GET_CODE (I) == CALL_INSN \ | |
3341 | || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ | |
3342 | || GET_CODE (PATTERN (I)) == ASM_INPUT))\ | |
3343 | ? FP_CW_UNINITIALIZED \ | |
3344 | : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ | |
3345 | ? FP_CW_ANY \ | |
3346 | : FP_CW_STORED) | |
3347 | ||
3348 | /* This macro specifies the order in which modes for ENTITY are | |
3349 | processed. 0 is the highest priority. */ | |
3350 | ||
d9a5f180 | 3351 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
3352 | |
3353 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
3354 | is the set of hard registers live at the point where the insn(s) | |
3355 | are to be inserted. */ | |
3356 | ||
3357 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
d9a5f180 | 3358 | ((MODE) == FP_CW_STORED \ |
22fb740d JH |
3359 | ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ |
3360 | assign_386_stack_local (HImode, 2)), 0\ | |
3361 | : 0) | |
0f0138b6 JH |
3362 | \f |
3363 | /* Avoid renaming of stack registers, as doing so in combination with | |
3364 | scheduling just increases amount of live registers at time and in | |
3365 | the turn amount of fxch instructions needed. | |
3366 | ||
3367 | ??? Maybe Pentium chips benefits from renaming, someone can try... */ | |
3368 | ||
d9a5f180 GS |
3369 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
3370 | ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) | |
22fb740d | 3371 | |
3b3c6a3f | 3372 | \f |
2a500b9e | 3373 | #define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X) |
c98f8742 JVA |
3374 | /* |
3375 | Local variables: | |
3376 | version-control: t | |
3377 | End: | |
3378 | */ |