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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
23a5b65a | 2 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
90922d36 | 42 | #define TARGET_64BIT TARGET_ISA_64BIT |
bf7b5747 | 43 | #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) |
90922d36 | 44 | #define TARGET_MMX TARGET_ISA_MMX |
bf7b5747 | 45 | #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) |
90922d36 | 46 | #define TARGET_3DNOW TARGET_ISA_3DNOW |
bf7b5747 | 47 | #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) |
90922d36 | 48 | #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A |
bf7b5747 | 49 | #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) |
90922d36 | 50 | #define TARGET_SSE TARGET_ISA_SSE |
bf7b5747 | 51 | #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) |
90922d36 | 52 | #define TARGET_SSE2 TARGET_ISA_SSE2 |
bf7b5747 | 53 | #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) |
90922d36 | 54 | #define TARGET_SSE3 TARGET_ISA_SSE3 |
bf7b5747 | 55 | #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) |
90922d36 | 56 | #define TARGET_SSSE3 TARGET_ISA_SSSE3 |
bf7b5747 | 57 | #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) |
90922d36 | 58 | #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 |
bf7b5747 | 59 | #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) |
90922d36 | 60 | #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 |
bf7b5747 | 61 | #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) |
90922d36 | 62 | #define TARGET_AVX TARGET_ISA_AVX |
bf7b5747 | 63 | #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) |
90922d36 | 64 | #define TARGET_AVX2 TARGET_ISA_AVX2 |
bf7b5747 | 65 | #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) |
cb610367 UB |
66 | #define TARGET_AVX512F TARGET_ISA_AVX512F |
67 | #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
68 | #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
69 | #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
70 | #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
71 | #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
72 | #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
73 | #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
07165dd7 AI |
74 | #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ |
75 | #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
b525d943 AI |
76 | #define TARGET_AVX512BW TARGET_ISA_AVX512BW |
77 | #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
f4af595f AI |
78 | #define TARGET_AVX512VL TARGET_ISA_AVX512VL |
79 | #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
90922d36 | 80 | #define TARGET_FMA TARGET_ISA_FMA |
bf7b5747 | 81 | #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) |
90922d36 | 82 | #define TARGET_SSE4A TARGET_ISA_SSE4A |
bf7b5747 | 83 | #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) |
90922d36 | 84 | #define TARGET_FMA4 TARGET_ISA_FMA4 |
bf7b5747 | 85 | #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) |
90922d36 | 86 | #define TARGET_XOP TARGET_ISA_XOP |
bf7b5747 | 87 | #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) |
90922d36 | 88 | #define TARGET_LWP TARGET_ISA_LWP |
bf7b5747 | 89 | #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) |
90922d36 MM |
90 | #define TARGET_ROUND TARGET_ISA_ROUND |
91 | #define TARGET_ABM TARGET_ISA_ABM | |
bf7b5747 | 92 | #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) |
90922d36 | 93 | #define TARGET_BMI TARGET_ISA_BMI |
bf7b5747 | 94 | #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) |
90922d36 | 95 | #define TARGET_BMI2 TARGET_ISA_BMI2 |
bf7b5747 | 96 | #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) |
90922d36 | 97 | #define TARGET_LZCNT TARGET_ISA_LZCNT |
bf7b5747 | 98 | #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) |
90922d36 | 99 | #define TARGET_TBM TARGET_ISA_TBM |
bf7b5747 | 100 | #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) |
90922d36 | 101 | #define TARGET_POPCNT TARGET_ISA_POPCNT |
bf7b5747 | 102 | #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) |
90922d36 | 103 | #define TARGET_SAHF TARGET_ISA_SAHF |
bf7b5747 | 104 | #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) |
90922d36 | 105 | #define TARGET_MOVBE TARGET_ISA_MOVBE |
bf7b5747 | 106 | #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) |
90922d36 | 107 | #define TARGET_CRC32 TARGET_ISA_CRC32 |
bf7b5747 | 108 | #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) |
90922d36 | 109 | #define TARGET_AES TARGET_ISA_AES |
bf7b5747 | 110 | #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) |
c1618f82 AI |
111 | #define TARGET_SHA TARGET_ISA_SHA |
112 | #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
9cdea277 IT |
113 | #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT |
114 | #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
115 | #define TARGET_XSAVEC TARGET_ISA_XSAVEC | |
116 | #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
117 | #define TARGET_XSAVES TARGET_ISA_XSAVES | |
118 | #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
90922d36 | 119 | #define TARGET_PCLMUL TARGET_ISA_PCLMUL |
bf7b5747 | 120 | #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) |
cb610367 UB |
121 | #define TARGET_CMPXCHG16B TARGET_ISA_CX16 |
122 | #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) | |
90922d36 | 123 | #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
bf7b5747 | 124 | #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) |
90922d36 | 125 | #define TARGET_RDRND TARGET_ISA_RDRND |
bf7b5747 | 126 | #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) |
90922d36 | 127 | #define TARGET_F16C TARGET_ISA_F16C |
bf7b5747 | 128 | #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) |
cb610367 UB |
129 | #define TARGET_RTM TARGET_ISA_RTM |
130 | #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
90922d36 | 131 | #define TARGET_HLE TARGET_ISA_HLE |
bf7b5747 | 132 | #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) |
90922d36 | 133 | #define TARGET_RDSEED TARGET_ISA_RDSEED |
bf7b5747 | 134 | #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) |
90922d36 | 135 | #define TARGET_PRFCHW TARGET_ISA_PRFCHW |
bf7b5747 | 136 | #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) |
90922d36 | 137 | #define TARGET_ADX TARGET_ISA_ADX |
bf7b5747 | 138 | #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) |
3a0d99bb | 139 | #define TARGET_FXSR TARGET_ISA_FXSR |
bf7b5747 | 140 | #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) |
3a0d99bb | 141 | #define TARGET_XSAVE TARGET_ISA_XSAVE |
bf7b5747 | 142 | #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) |
3a0d99bb | 143 | #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT |
bf7b5747 | 144 | #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) |
43b3f52f IT |
145 | #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 |
146 | #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
ab442df7 | 147 | |
90922d36 | 148 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 149 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
90922d36 | 150 | #define TARGET_X32 TARGET_ABI_X32 |
bf7b5747 | 151 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) |
d5d618b5 L |
152 | #define TARGET_16BIT TARGET_CODE16 |
153 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
04e1d06b | 154 | |
cbf2e4d4 HJ |
155 | /* SSE4.1 defines round instructions */ |
156 | #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 | |
90922d36 | 157 | #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) |
0a1c5e55 | 158 | |
26b5109f RS |
159 | #include "config/vxworks-dummy.h" |
160 | ||
7eb68c06 | 161 | #include "config/i386/i386-opts.h" |
ccf8e764 | 162 | |
c69fa2d4 | 163 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 164 | |
8c996513 JH |
165 | /* Specify what algorithm to use for stringops on known size. |
166 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
167 | known at compile time or estimated via feedback, the SIZE array | |
168 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 169 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
170 | When NOALIGN is true the code guaranting the alignment of the memory |
171 | block is skipped. | |
172 | ||
8c996513 | 173 | For example initializer: |
4f3f76e6 | 174 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 175 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 176 | be used otherwise. */ |
8c996513 JH |
177 | struct stringop_algs |
178 | { | |
179 | const enum stringop_alg unknown_size; | |
180 | const struct stringop_strategy { | |
181 | const int max; | |
182 | const enum stringop_alg alg; | |
340ef734 | 183 | int noalign; |
c69fa2d4 | 184 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
185 | }; |
186 | ||
d4ba09c0 SC |
187 | /* Define the specific costs for a given cpu */ |
188 | ||
189 | struct processor_costs { | |
8b60264b KG |
190 | const int add; /* cost of an add instruction */ |
191 | const int lea; /* cost of a lea instruction */ | |
192 | const int shift_var; /* variable shift costs */ | |
193 | const int shift_const; /* constant shift costs */ | |
f676971a | 194 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 195 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 196 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 197 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 198 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
199 | int movsx; /* The cost of movsx operation. */ |
200 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
201 | const int large_insn; /* insns larger than this cost more */ |
202 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 203 | memory-to-memory move insns. */ |
8b60264b KG |
204 | const int movzbl_load; /* cost of loading using movzbl */ |
205 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
206 | in QImode, HImode and SImode relative |
207 | to reg-reg move (2). */ | |
8b60264b | 208 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 209 | in QImode, HImode and SImode */ |
8b60264b KG |
210 | const int fp_move; /* cost of reg,reg fld/fst */ |
211 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 212 | in SFmode, DFmode and XFmode */ |
8b60264b | 213 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 214 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
215 | const int mmx_move; /* cost of moving MMX register. */ |
216 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 217 | in SImode and DImode */ |
8b60264b | 218 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 219 | in SImode and DImode */ |
8b60264b KG |
220 | const int sse_move; /* cost of moving SSE register. */ |
221 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 222 | in SImode, DImode and TImode*/ |
8b60264b | 223 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 224 | in SImode, DImode and TImode*/ |
8b60264b | 225 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 226 | integer and vice versa. */ |
46cb0441 ZD |
227 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
228 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
229 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
230 | const int simultaneous_prefetches; /* number of parallel prefetch | |
231 | operations. */ | |
4977bab6 | 232 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
233 | const int fadd; /* cost of FADD and FSUB instructions. */ |
234 | const int fmul; /* cost of FMUL instruction. */ | |
235 | const int fdiv; /* cost of FDIV instruction. */ | |
236 | const int fabs; /* cost of FABS instruction. */ | |
237 | const int fchs; /* cost of FCHS instruction. */ | |
238 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 239 | /* Specify what algorithm |
bee51209 | 240 | to use for stringops on unknown size. */ |
ad83025e | 241 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
242 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
243 | load and store. */ | |
244 | const int scalar_load_cost; /* Cost of scalar load. */ | |
245 | const int scalar_store_cost; /* Cost of scalar store. */ | |
246 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
247 | load, store, vector-to-scalar and | |
248 | scalar-to-vector operation. */ | |
249 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
250 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 251 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
252 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
253 | const int vec_store_cost; /* Cost of vector store. */ | |
254 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
255 | cost model. */ | |
256 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
257 | vectorizer cost model. */ | |
d4ba09c0 SC |
258 | }; |
259 | ||
8b60264b | 260 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
261 | extern const struct processor_costs ix86_size_cost; |
262 | ||
263 | #define ix86_cur_cost() \ | |
264 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 265 | |
c98f8742 JVA |
266 | /* Macros used in the machine description to test the flags. */ |
267 | ||
b97de419 | 268 | /* configure can arrange to change it. */ |
e075ae69 | 269 | |
35b528be | 270 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 271 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 272 | #endif |
35b528be | 273 | |
004d3859 GK |
274 | #ifndef TARGET_FPMATH_DEFAULT |
275 | #define TARGET_FPMATH_DEFAULT \ | |
276 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
277 | #endif | |
278 | ||
bf7b5747 ST |
279 | #ifndef TARGET_FPMATH_DEFAULT_P |
280 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
281 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
282 | #endif | |
283 | ||
6ac49599 | 284 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
bf7b5747 | 285 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x) |
b08de47e | 286 | |
5791cc29 JT |
287 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
288 | compile-time constant. */ | |
289 | #ifdef IN_LIBGCC2 | |
6ac49599 | 290 | #undef TARGET_64BIT |
5791cc29 JT |
291 | #ifdef __x86_64__ |
292 | #define TARGET_64BIT 1 | |
293 | #else | |
294 | #define TARGET_64BIT 0 | |
295 | #endif | |
296 | #else | |
6ac49599 RS |
297 | #ifndef TARGET_BI_ARCH |
298 | #undef TARGET_64BIT | |
e49080ec | 299 | #undef TARGET_64BIT_P |
67adf6a9 | 300 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 301 | #define TARGET_64BIT 1 |
e49080ec | 302 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
303 | #else |
304 | #define TARGET_64BIT 0 | |
e49080ec | 305 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
306 | #endif |
307 | #endif | |
5791cc29 | 308 | #endif |
25f94bb5 | 309 | |
750054a2 CT |
310 | #define HAS_LONG_COND_BRANCH 1 |
311 | #define HAS_LONG_UNCOND_BRANCH 1 | |
312 | ||
9e555526 RH |
313 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
314 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
315 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
316 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 317 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
318 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
319 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
320 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
321 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 322 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 323 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
340ef734 | 324 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d3c11974 L |
325 | #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) |
326 | #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
3a579e09 | 327 | #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) |
d3c11974 L |
328 | #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) |
329 | #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
9a7f94d7 | 330 | #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
9d532162 | 331 | #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) |
21efb4d4 | 332 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
1133125e | 333 | #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
4d652a18 | 334 | #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
eb2f2b44 | 335 | #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) |
ed97ad47 | 336 | #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) |
14b52538 | 337 | #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
e32bfc16 | 338 | #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
a269a03c | 339 | |
80fd744f RH |
340 | /* Feature tests against the various tunings. */ |
341 | enum ix86_tune_indices { | |
4b8bc035 | 342 | #undef DEF_TUNE |
3ad20bd4 | 343 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
344 | #include "x86-tune.def" |
345 | #undef DEF_TUNE | |
346 | X86_TUNE_LAST | |
80fd744f RH |
347 | }; |
348 | ||
ab442df7 | 349 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
350 | |
351 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
352 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
353 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
354 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 355 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
356 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
357 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
358 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
359 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
360 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
361 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
362 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
363 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
364 | #define TARGET_LCP_STALL \ |
365 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
366 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
367 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
368 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
369 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
370 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
371 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
372 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
373 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
374 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
375 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
376 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
5783ad0e UB |
377 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
378 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
379 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
380 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
381 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
382 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
383 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
384 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
385 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
386 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
387 | #define TARGET_INTEGER_DFMODE_MOVES \ |
388 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
389 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
390 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
391 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
392 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
1133125e HJ |
393 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
394 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
395 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
396 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
397 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
398 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
399 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
400 | #define TARGET_SSE_TYPELESS_STORES \ | |
401 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
402 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
403 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
404 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
405 | #define TARGET_PROLOGUE_USING_MOVE \ | |
406 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
407 | #define TARGET_EPILOGUE_USING_MOVE \ | |
408 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
409 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
410 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
411 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
412 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
413 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
414 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
415 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 416 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
417 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
418 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
419 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
420 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
421 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
422 | #define TARGET_PAD_SHORT_FUNCTION \ |
423 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
424 | #define TARGET_EXT_80387_CONSTANTS \ |
425 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
426 | #define TARGET_AVOID_VECTOR_DECODE \ |
427 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
428 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
429 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
430 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
431 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
432 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
433 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
434 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
435 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
436 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
437 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
438 | #define TARGET_USE_VECTOR_CONVERTS \ |
439 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
440 | #define TARGET_SLOW_PSHUFB \ |
441 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
f7917029 ES |
442 | #define TARGET_VECTOR_PARALLEL_EXECUTION \ |
443 | ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION] | |
0dc41f28 WM |
444 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
445 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
446 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
447 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 448 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
449 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
450 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
451 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
452 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
453 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
454 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 455 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
456 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
457 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
e72eba85 L |
458 | #define TARGET_VECTORIZE_DOUBLE \ |
459 | ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] | |
5d0878e7 JH |
460 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
461 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
5c0d88e6 CF |
462 | #define TARGET_AVX128_OPTIMAL \ |
463 | ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] | |
df7b0cc4 EI |
464 | #define TARGET_REASSOC_INT_TO_PARALLEL \ |
465 | ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] | |
466 | #define TARGET_REASSOC_FP_TO_PARALLEL \ | |
467 | ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] | |
55a2c322 VM |
468 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
469 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
470 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
471 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 472 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 473 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
474 | #define TARGET_ADJUST_UNROLL \ |
475 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
374f5bf8 UB |
476 | #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ |
477 | ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
df7b0cc4 | 478 | |
80fd744f RH |
479 | /* Feature tests against the various architecture variations. */ |
480 | enum ix86_arch_indices { | |
cef31f9c | 481 | X86_ARCH_CMOV, |
80fd744f RH |
482 | X86_ARCH_CMPXCHG, |
483 | X86_ARCH_CMPXCHG8B, | |
484 | X86_ARCH_XADD, | |
485 | X86_ARCH_BSWAP, | |
486 | ||
487 | X86_ARCH_LAST | |
488 | }; | |
4f3f76e6 | 489 | |
ab442df7 | 490 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 491 | |
cef31f9c | 492 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
493 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
494 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
495 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
496 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
497 | ||
cef31f9c UB |
498 | /* For sane SSE instruction set generation we need fcomi instruction. |
499 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
500 | expands to a sequence that includes conditional move. */ | |
501 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
502 | ||
80fd744f RH |
503 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
504 | ||
cb261eb7 | 505 | extern unsigned char x86_prefetch_sse; |
80fd744f RH |
506 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
507 | ||
80fd744f RH |
508 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
509 | ||
510 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
511 | #define TARGET_MIX_SSE_I387 \ | |
512 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
513 | ||
514 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
515 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
516 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 517 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 518 | |
67adf6a9 RH |
519 | #ifndef TARGET_64BIT_DEFAULT |
520 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 521 | #endif |
74dc3e94 RH |
522 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
523 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
524 | #endif | |
25f94bb5 | 525 | |
e0ea8797 AH |
526 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
527 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
528 | ||
79f5e442 ZD |
529 | /* Fence to use after loop using storent. */ |
530 | ||
531 | extern tree x86_mfence; | |
532 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
533 | ||
0ed4a390 JL |
534 | /* Once GDB has been enhanced to deal with functions without frame |
535 | pointers, we can change this to allow for elimination of | |
536 | the frame pointer in leaf functions. */ | |
537 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 538 | |
0a1c5e55 UB |
539 | /* Extra bits to force. */ |
540 | #define TARGET_SUBTARGET_DEFAULT 0 | |
541 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
542 | ||
543 | /* Extra bits to force on w/ 32-bit mode. */ | |
544 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
545 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
546 | ||
ccf8e764 RH |
547 | /* Extra bits to force on w/ 64-bit mode. */ |
548 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 549 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 550 | |
fee3eacd IS |
551 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
552 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 553 | #define TARGET_MACHO 0 |
9005471b | 554 | #define TARGET_MACHO_BRANCH_ISLANDS 0 |
fee3eacd IS |
555 | #define MACHOPIC_ATT_STUB 0 |
556 | /* (b) Macros defined in config/darwin.h */ | |
557 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
558 | #define MACHOPIC_INDIRECT 0 | |
559 | #define MACHOPIC_PURE 0 | |
9005471b | 560 | |
5a579c3b LE |
561 | /* For the RDOS */ |
562 | #define TARGET_RDOS 0 | |
563 | ||
9005471b | 564 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
565 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
566 | ||
6510e8bb KT |
567 | /* For the Windows 32-bit ABI. */ |
568 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
569 | ||
f81c9774 RH |
570 | /* This is re-defined by cygming.h. */ |
571 | #define TARGET_SEH 0 | |
572 | ||
a3d7ab92 KT |
573 | /* This is re-defined by cygming.h. */ |
574 | #define TARGET_PECOFF 0 | |
575 | ||
51212b32 | 576 | /* The default abi used by target. */ |
7c800926 | 577 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 578 | |
b8b3f0ca LE |
579 | /* The default TLS segment register used by target. */ |
580 | #define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS) | |
581 | ||
cc69336f RH |
582 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
583 | with the rounding mode forced to 53 bits. */ | |
584 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
585 | ||
682cd442 GK |
586 | /* -march=native handling only makes sense with compiler running on |
587 | an x86 or x86_64 chip. If changing this condition, also change | |
588 | the condition in driver-i386.c. */ | |
589 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
590 | /* In driver-i386.c. */ |
591 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
592 | #define EXTRA_SPEC_FUNCTIONS \ | |
593 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 594 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
595 | #endif |
596 | ||
8981c15b JM |
597 | #if TARGET_64BIT_DEFAULT |
598 | #define OPT_ARCH64 "!m32" | |
599 | #define OPT_ARCH32 "m32" | |
600 | #else | |
f0ea7581 L |
601 | #define OPT_ARCH64 "m64|mx32" |
602 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
603 | #endif |
604 | ||
1cba2b96 EC |
605 | /* Support for configure-time defaults of some command line options. |
606 | The order here is important so that -march doesn't squash the | |
607 | tune or cpu values. */ | |
ce998900 | 608 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 609 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
610 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
611 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 612 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
613 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
614 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
615 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
616 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
617 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 618 | |
241e1a89 SC |
619 | /* Specs for the compiler proper */ |
620 | ||
628714d8 | 621 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 622 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 623 | |
682cd442 | 624 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
625 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
626 | #else | |
627 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
96f5b137 L |
628 | "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
629 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ | |
630 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" | |
fa959ce4 | 631 | #endif |
241e1a89 | 632 | #endif |
c98f8742 | 633 | \f |
30efe578 | 634 | /* Target CPU builtins. */ |
ab442df7 MM |
635 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
636 | ||
637 | /* Target Pragmas. */ | |
638 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 639 | |
628714d8 | 640 | #ifndef CC1_SPEC |
8015b78d | 641 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
642 | #endif |
643 | ||
644 | /* This macro defines names of additional specifications to put in the | |
645 | specs that can be used in various specifications like CC1_SPEC. Its | |
646 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
647 | |
648 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 649 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
650 | program. |
651 | ||
652 | Do not define this macro if it does not need to do anything. */ | |
653 | ||
654 | #ifndef SUBTARGET_EXTRA_SPECS | |
655 | #define SUBTARGET_EXTRA_SPECS | |
656 | #endif | |
657 | ||
658 | #define EXTRA_SPECS \ | |
628714d8 | 659 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
660 | SUBTARGET_EXTRA_SPECS |
661 | \f | |
ce998900 | 662 | |
d57a4b98 RH |
663 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
664 | FPU, assume that the fpcw is set to extended precision; when using | |
665 | only SSE, rounding is correct; when using both SSE and the FPU, | |
666 | the rounding precision is indeterminate, since either may be chosen | |
667 | apparently at random. */ | |
668 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 669 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 670 | |
8ce94e44 JM |
671 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
672 | SFmode, DFmode and XFmode) in the current excess precision | |
673 | configuration. */ | |
674 | #define X87_ENABLE_ARITH(MODE) \ | |
675 | (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) | |
676 | ||
677 | /* Likewise, whether to allow direct conversions from integer mode | |
678 | IMODE (HImode, SImode or DImode) to MODE. */ | |
679 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
680 | (flag_excess_precision == EXCESS_PRECISION_FAST \ | |
681 | || (MODE) == XFmode \ | |
682 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
683 | || (IMODE) == HImode) | |
684 | ||
979c67a5 UB |
685 | /* target machine storage layout */ |
686 | ||
65d9c0ab JH |
687 | #define SHORT_TYPE_SIZE 16 |
688 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
689 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
690 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 691 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 692 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 693 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
694 | #define LONG_DOUBLE_TYPE_SIZE \ |
695 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 696 | |
c637141a | 697 | #define WIDEST_HARDWARE_FP_SIZE 80 |
65d9c0ab | 698 | |
67adf6a9 | 699 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 700 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
701 | #else |
702 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
703 | #endif |
704 | ||
c98f8742 JVA |
705 | /* Define this if most significant byte of a word is the lowest numbered. */ |
706 | /* That is true on the 80386. */ | |
707 | ||
708 | #define BITS_BIG_ENDIAN 0 | |
709 | ||
710 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
711 | /* That is not true on the 80386. */ | |
712 | #define BYTES_BIG_ENDIAN 0 | |
713 | ||
714 | /* Define this if most significant word of a multiword number is the lowest | |
715 | numbered. */ | |
716 | /* Not true for 80386 */ | |
717 | #define WORDS_BIG_ENDIAN 0 | |
718 | ||
c98f8742 | 719 | /* Width of a word, in units (bytes). */ |
4ae8027b | 720 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
721 | |
722 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
723 | #define MIN_UNITS_PER_WORD 4 |
724 | #endif | |
c98f8742 | 725 | |
c98f8742 | 726 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 727 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 728 | |
e075ae69 | 729 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
4ae8027b | 730 | #define STACK_BOUNDARY \ |
51212b32 | 731 | (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 732 | |
2e3f842f L |
733 | /* Stack boundary of the main function guaranteed by OS. */ |
734 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
735 | ||
de1132d1 | 736 | /* Minimum stack boundary. */ |
5bfb2af2 | 737 | #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32) |
2e3f842f | 738 | |
d1f87653 | 739 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 740 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 741 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 742 | |
de1132d1 | 743 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
744 | both 32bit and 64bit, to support codes that need 128 bit stack |
745 | alignment for SSE instructions, but can't realign the stack. */ | |
746 | #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
747 | ||
748 | /* 1 if -mstackrealign should be turned on by default. It will | |
749 | generate an alternate prologue and epilogue that realigns the | |
750 | runtime stack if nessary. This supports mixing codes that keep a | |
751 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 752 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
753 | #define STACK_REALIGN_DEFAULT 0 |
754 | ||
755 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
756 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 757 | |
a2851b75 TG |
758 | /* According to Windows x64 software convention, the maximum stack allocatable |
759 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
760 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
761 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
762 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
763 | prologue. | |
764 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 765 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
766 | regs, then save them, and then allocate the remaining. There is no SEH |
767 | unwind info for this later allocation. */ | |
768 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
769 | ||
ebff937c SH |
770 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
771 | mandatory for the 64-bit ABI, and may or may not be true for other | |
772 | operating systems. */ | |
773 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
774 | ||
f963b5d9 RS |
775 | /* Minimum allocation boundary for the code of a function. */ |
776 | #define FUNCTION_BOUNDARY 8 | |
777 | ||
778 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
779 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 780 | |
c98f8742 JVA |
781 | /* Minimum size in bits of the largest boundary to which any |
782 | and all fundamental data types supported by the hardware | |
783 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 784 | rounder than this. |
fce5a9f2 | 785 | |
d1f87653 | 786 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
787 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
788 | ||
3f97cb0b AI |
789 | #define BIGGEST_ALIGNMENT \ |
790 | (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)) | |
17f24ff0 | 791 | |
2e3f842f L |
792 | /* Maximum stack alignment. */ |
793 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
794 | ||
6e4f1168 L |
795 | /* Alignment value for attribute ((aligned)). It is a constant since |
796 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
797 | #define ATTRIBUTE_ALIGNED_VALUE 128 | |
798 | ||
822eda12 | 799 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 800 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 801 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 802 | |
17f24ff0 | 803 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 804 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 805 | -malign-double is set. */ |
e932b21b | 806 | |
e83f3cff RH |
807 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
808 | supports no vector modes, cut out the complexity and fall back | |
809 | on BIGGEST_FIELD_ALIGNMENT. */ | |
810 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
811 | #ifdef __x86_64__ |
812 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
813 | #else | |
e83f3cff | 814 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 815 | #endif |
e83f3cff | 816 | #else |
e932b21b JH |
817 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
818 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 819 | #endif |
c98f8742 | 820 | |
e5e8a8bf | 821 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 822 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
823 | and ALIGN is the alignment that the object would ordinarily have. |
824 | The value of this macro is used instead of that alignment to align | |
825 | the object. | |
826 | ||
827 | If this macro is not defined, then ALIGN is used. | |
828 | ||
829 | The typical use of this macro is to increase alignment for string | |
830 | constants to be word aligned so that `strcpy' calls that copy | |
831 | constants can be done inline. */ | |
832 | ||
d9a5f180 | 833 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 834 | |
8a022443 JW |
835 | /* If defined, a C expression to compute the alignment for a static |
836 | variable. TYPE is the data type, and ALIGN is the alignment that | |
837 | the object would ordinarily have. The value of this macro is used | |
838 | instead of that alignment to align the object. | |
839 | ||
840 | If this macro is not defined, then ALIGN is used. | |
841 | ||
842 | One use of this macro is to increase alignment of medium-size | |
843 | data to make it all fit in fewer cache lines. Another is to | |
844 | cause character arrays to be word-aligned so that `strcpy' calls | |
845 | that copy constants to character arrays can be done inline. */ | |
846 | ||
df8a1d28 JJ |
847 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
848 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
849 | ||
850 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
851 | some alignment increase, instead of optimization only purposes. E.g. | |
852 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
853 | must be aligned to 16 byte boundaries. | |
854 | ||
855 | If this macro is not defined, then ALIGN is used. */ | |
856 | ||
857 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
858 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
859 | |
860 | /* If defined, a C expression to compute the alignment for a local | |
861 | variable. TYPE is the data type, and ALIGN is the alignment that | |
862 | the object would ordinarily have. The value of this macro is used | |
863 | instead of that alignment to align the object. | |
864 | ||
865 | If this macro is not defined, then ALIGN is used. | |
866 | ||
867 | One use of this macro is to increase alignment of medium-size | |
868 | data to make it all fit in fewer cache lines. */ | |
869 | ||
76fe54f0 L |
870 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
871 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
872 | ||
873 | /* If defined, a C expression to compute the alignment for stack slot. | |
874 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
875 | is the alignment that the slot would ordinarily have. The value of | |
876 | this macro is used instead of that alignment to align the slot. | |
877 | ||
878 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
879 | Otherwise, LOCAL_ALIGNMENT will be used. | |
880 | ||
881 | One use of this macro is to set alignment of stack slot to the | |
882 | maximum alignment of all possible modes which the slot may have. */ | |
883 | ||
884 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
885 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 886 | |
9bfaf89d JJ |
887 | /* If defined, a C expression to compute the alignment for a local |
888 | variable DECL. | |
889 | ||
890 | If this macro is not defined, then | |
891 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
892 | ||
893 | One use of this macro is to increase alignment of medium-size | |
894 | data to make it all fit in fewer cache lines. */ | |
895 | ||
896 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
897 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
898 | ||
ae58e548 JJ |
899 | /* If defined, a C expression to compute the minimum required alignment |
900 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
901 | MODE, assuming normal alignment ALIGN. | |
902 | ||
903 | If this macro is not defined, then (ALIGN) will be used. */ | |
904 | ||
905 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
906 | ix86_minimum_alignment (EXP, MODE, ALIGN) | |
907 | ||
9bfaf89d | 908 | |
9cd10576 | 909 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 910 | when given unaligned data. */ |
b4ac57ab | 911 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
912 | |
913 | /* If bit field type is int, don't let it cross an int, | |
914 | and give entire struct the alignment of an int. */ | |
43a88a8c | 915 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 916 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
917 | \f |
918 | /* Standard register usage. */ | |
919 | ||
920 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 921 | for details. */ |
c98f8742 JVA |
922 | |
923 | #define STACK_REGS | |
ce998900 | 924 | |
d9a5f180 | 925 | #define IS_STACK_MODE(MODE) \ |
63001560 UB |
926 | (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ |
927 | || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ | |
b5c82fa1 | 928 | || (MODE) == XFmode) |
c98f8742 JVA |
929 | |
930 | /* Number of actual hardware registers. | |
931 | The hardware registers are assigned numbers for the compiler | |
932 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
933 | All registers that the compiler knows about must be given numbers, | |
934 | even those that are not normally considered general registers. | |
935 | ||
936 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
937 | We number the floating point registers 8-15. | |
938 | Note that registers 0-7 can be accessed as a short or int, | |
939 | while only 0-3 may be used with byte `mov' instructions. | |
940 | ||
941 | Reg 16 does not correspond to any hardware register, but instead | |
942 | appears in the RTL as an argument pointer prior to reload, and is | |
943 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 944 | pointer. */ |
c98f8742 | 945 | |
089d1227 | 946 | #define FIRST_PSEUDO_REGISTER 77 |
c98f8742 | 947 | |
3073d01c ML |
948 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
949 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
950 | ||
951 | #define DWARF_FRAME_REGISTERS 17 | |
952 | ||
c98f8742 JVA |
953 | /* 1 for registers that have pervasive standard uses |
954 | and are not available for the register allocator. | |
3f3f2124 | 955 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 956 | |
621bc046 UB |
957 | REX registers are disabled for 32bit targets in |
958 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
959 | ||
a7180f70 BS |
960 | #define FIXED_REGISTERS \ |
961 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 962 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
963 | /*arg,flags,fpsr,fpcr,frame*/ \ |
964 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
965 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
966 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 967 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
968 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
969 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 970 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 971 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
972 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
973 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
974 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
975 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
976 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
977 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
089d1227 | 978 | 0, 0, 0, 0, 0, 0, 0, 0 } |
c98f8742 JVA |
979 | |
980 | /* 1 for registers not available across function calls. | |
981 | These must include the FIXED_REGISTERS and also any | |
982 | registers that can be used without being saved. | |
983 | The latter must include the registers where values are returned | |
984 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
985 | Aside from that, you can include as many other registers as you like. |
986 | ||
621bc046 UB |
987 | Value is set to 1 if the register is call used unconditionally. |
988 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
989 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
990 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
991 | ||
992 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
993 | ||
a7180f70 BS |
994 | #define CALL_USED_REGISTERS \ |
995 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 996 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
997 | /*arg,flags,fpsr,fpcr,frame*/ \ |
998 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 999 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 1000 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 1001 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 1002 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1003 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1004 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1005 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1006 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1007 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1008 | 6, 6, 6, 6, 6, 6, 6, 6, \ | |
1009 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1010 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1011 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
089d1227 | 1012 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 1013 | |
3b3c6a3f MM |
1014 | /* Order in which to allocate registers. Each register must be |
1015 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1016 | late and fixed registers last. Note that, in general, we prefer | |
1017 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1018 | available for storage of persistent values. | |
1019 | ||
5a733826 | 1020 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
162f023b | 1021 | so this is just empty initializer for array. */ |
3b3c6a3f | 1022 | |
162f023b JH |
1023 | #define REG_ALLOC_ORDER \ |
1024 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1025 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1026 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
3f97cb0b | 1027 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
089d1227 | 1028 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76 } |
3b3c6a3f | 1029 | |
5a733826 | 1030 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 1031 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 1032 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1033 | |
5a733826 | 1034 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1035 | |
f5316dfe | 1036 | |
7c800926 KT |
1037 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1038 | ||
c98f8742 JVA |
1039 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1040 | to hold something of mode MODE. | |
1041 | This is ordinarily the length in words of a value of mode MODE | |
1042 | but can be less for certain modes in special long registers. | |
1043 | ||
fce5a9f2 | 1044 | Actually there are no two word move instructions for consecutive |
c98f8742 | 1045 | registers. And only registers 0-3 may have mov byte instructions |
63001560 | 1046 | applied to them. */ |
c98f8742 | 1047 | |
ce998900 | 1048 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
9e4a4dd6 AI |
1049 | (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) \ |
1050 | || MMX_REGNO_P (REGNO) || MASK_REGNO_P (REGNO) \ | |
92d0fb09 | 1051 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ |
f8a1ebc6 | 1052 | : ((MODE) == XFmode \ |
92d0fb09 | 1053 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1054 | : (MODE) == XCmode \ |
92d0fb09 | 1055 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1056 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1057 | |
8521c414 JM |
1058 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
1059 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
66aaf16f | 1060 | ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
8521c414 JM |
1061 | ? 0 \ |
1062 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
1063 | : 0) | |
1064 | ||
1065 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1066 | ||
95879c72 L |
1067 | #define VALID_AVX256_REG_MODE(MODE) \ |
1068 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb JJ |
1069 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
1070 | || (MODE) == V4DFmode) | |
95879c72 | 1071 | |
4ac005ba | 1072 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
ff97910d VY |
1073 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) |
1074 | ||
3f97cb0b AI |
1075 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
1076 | ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
1077 | || (MODE) == SFmode) | |
1078 | ||
1079 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1080 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 AI |
1081 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
1082 | || (MODE) == V4TImode) | |
1083 | ||
1084 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ | |
1085 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ | |
1086 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode) | |
3f97cb0b | 1087 | |
ce998900 UB |
1088 | #define VALID_SSE2_REG_MODE(MODE) \ |
1089 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1090 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1091 | |
d9a5f180 | 1092 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1093 | ((MODE) == V1TImode || (MODE) == TImode \ |
1094 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
ce998900 | 1095 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1096 | |
47f339cf | 1097 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1098 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1099 | |
d9a5f180 | 1100 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1101 | ((MODE == V1DImode) || (MODE) == DImode \ |
1102 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1103 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1104 | |
ce998900 UB |
1105 | #define VALID_DFP_MODE_P(MODE) \ |
1106 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1107 | |
d9a5f180 | 1108 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1109 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1110 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1111 | |
d9a5f180 | 1112 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1113 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1114 | || (MODE) == DImode \ | |
1115 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1116 | || (MODE) == CDImode \ | |
1117 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1118 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1119 | |
822eda12 | 1120 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1121 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1122 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1123 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1124 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1125 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1126 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1127 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1128 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
1129 | || (MODE) == V16SFmode) | |
822eda12 | 1130 | |
85a77221 AI |
1131 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1132 | ||
9e4a4dd6 AI |
1133 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) |
1134 | ||
e075ae69 | 1135 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1136 | |
a946dd00 | 1137 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1138 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1139 | |
1140 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1141 | when one has mode MODE1 and one has mode MODE2. | |
1142 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1143 | for any hard reg, then this must be 0 for correct output. */ | |
1144 | ||
c1c5b5e3 | 1145 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 1146 | |
ff25ef99 ZD |
1147 | /* It is possible to write patterns to move flags; but until someone |
1148 | does it, */ | |
1149 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1150 | |
e075ae69 | 1151 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1152 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1153 | |
787dc842 JH |
1154 | Kill any attempts to combine saving of modes. */ |
1155 | ||
d9a5f180 GS |
1156 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1157 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1158 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1159 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
85a77221 AI |
1160 | : (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \ |
1161 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
1162 | : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \ | |
1163 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
d2836273 | 1164 | : (MODE)) |
ce998900 | 1165 | |
51ba747a RH |
1166 | /* The only ABI that saves SSE registers across calls is Win64 (thus no |
1167 | need to check the current ABI here), and with AVX enabled Win64 only | |
1168 | guarantees that the low 16 bytes are saved. */ | |
1169 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
1170 | (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) | |
1171 | ||
c98f8742 JVA |
1172 | /* Specify the registers used for certain standard purposes. |
1173 | The values of these macros are register numbers. */ | |
1174 | ||
1175 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1176 | register. The ordinary mov instructions won't work */ | |
1177 | /* #define PC_REGNUM */ | |
1178 | ||
1179 | /* Register to use for pushing function arguments. */ | |
1180 | #define STACK_POINTER_REGNUM 7 | |
1181 | ||
1182 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1183 | #define HARD_FRAME_POINTER_REGNUM 6 |
1184 | ||
1185 | /* Base register for access to local variables of the function. */ | |
b0d95de8 | 1186 | #define FRAME_POINTER_REGNUM 20 |
c98f8742 JVA |
1187 | |
1188 | /* First floating point reg */ | |
1189 | #define FIRST_FLOAT_REG 8 | |
1190 | ||
1191 | /* First & last stack-like regs */ | |
1192 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1193 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1194 | ||
a7180f70 BS |
1195 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1196 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1197 | |
3f97cb0b | 1198 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/ |
a7180f70 BS |
1199 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) |
1200 | ||
3f97cb0b | 1201 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/ |
3f3f2124 JH |
1202 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) |
1203 | ||
3f97cb0b | 1204 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/ |
3f3f2124 JH |
1205 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) |
1206 | ||
3f97cb0b AI |
1207 | #define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/ |
1208 | #define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/ | |
1209 | ||
85a77221 AI |
1210 | #define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/ |
1211 | #define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/ | |
1212 | ||
aabcd309 | 1213 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1214 | requiring a frame pointer. */ |
1215 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1216 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1217 | #endif | |
1218 | ||
1219 | /* Make sure we can access arbitrary call frames. */ | |
1220 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1221 | |
1222 | /* Base register for access to arguments of the function. */ | |
1223 | #define ARG_POINTER_REGNUM 16 | |
1224 | ||
c98f8742 | 1225 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1226 | code access to data items. We don't use PIC pointer for 64bit |
1227 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1228 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1229 | |
1230 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1231 | the pic register when possible. The change is visible after the | |
1232 | prologue has been emitted. */ | |
1233 | ||
2e3f842f | 1234 | #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG |
bd09bdeb | 1235 | |
bcb21886 KY |
1236 | #define PIC_OFFSET_TABLE_REGNUM \ |
1237 | ((TARGET_64BIT && (ix86_cmodel == CM_SMALL_PIC \ | |
1238 | || TARGET_PECOFF)) \ | |
1239 | || !flag_pic \ | |
1240 | ? INVALID_REGNUM \ | |
1241 | : pic_offset_table_rtx \ | |
1242 | ? INVALID_REGNUM \ | |
1243 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1244 | |
5fc0e5df KW |
1245 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1246 | ||
c51e6d85 | 1247 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1248 | #define MS_AGGREGATE_RETURN 0 |
1249 | ||
61fec9ff | 1250 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1251 | \f |
1252 | /* Define the classes of registers for register constraints in the | |
1253 | machine description. Also define ranges of constants. | |
1254 | ||
1255 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1256 | If there is more than one class, another class must be named NO_REGS | |
1257 | and contain no registers. | |
1258 | ||
1259 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1260 | another name such as ALL_REGS). This is the class of registers | |
1261 | that is allowed by "g" or "r" in a register constraint. | |
1262 | Also, registers outside this class are allocated only when | |
1263 | instructions express preferences for them. | |
1264 | ||
1265 | The classes must be numbered in nondecreasing order; that is, | |
1266 | a larger-numbered class must never be contained completely | |
1267 | in a smaller-numbered class. | |
1268 | ||
1269 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1270 | class that represents their union. |
1271 | ||
1272 | It might seem that class BREG is unnecessary, since no useful 386 | |
1273 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1274 | and the "b" register constraint is useful in asms for syscalls. |
1275 | ||
03c259ad | 1276 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1277 | |
1278 | enum reg_class | |
1279 | { | |
1280 | NO_REGS, | |
e075ae69 | 1281 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1282 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1283 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1284 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1285 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1286 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
621bc046 | 1287 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
63001560 UB |
1288 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1289 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1290 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1291 | FLOAT_REGS, | |
06f4e35d | 1292 | SSE_FIRST_REG, |
a7180f70 | 1293 | SSE_REGS, |
3f97cb0b AI |
1294 | EVEX_SSE_REGS, |
1295 | ALL_SSE_REGS, | |
a7180f70 | 1296 | MMX_REGS, |
446988df JH |
1297 | FP_TOP_SSE_REGS, |
1298 | FP_SECOND_SSE_REGS, | |
1299 | FLOAT_SSE_REGS, | |
1300 | FLOAT_INT_REGS, | |
1301 | INT_SSE_REGS, | |
1302 | FLOAT_INT_SSE_REGS, | |
85a77221 AI |
1303 | MASK_EVEX_REGS, |
1304 | MASK_REGS, | |
c98f8742 JVA |
1305 | ALL_REGS, LIM_REG_CLASSES |
1306 | }; | |
1307 | ||
d9a5f180 GS |
1308 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1309 | ||
1310 | #define INTEGER_CLASS_P(CLASS) \ | |
1311 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1312 | #define FLOAT_CLASS_P(CLASS) \ | |
1313 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1314 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1315 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1316 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1317 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1318 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1319 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1320 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1321 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1322 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1323 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1324 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1325 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 AI |
1326 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
1327 | reg_classes_intersect_p ((CLASS), MASK_REGS) | |
d9a5f180 GS |
1328 | |
1329 | #define Q_CLASS_P(CLASS) \ | |
1330 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1331 | |
0bd72901 UB |
1332 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1333 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1334 | ||
43f3a59d | 1335 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1336 | |
1337 | #define REG_CLASS_NAMES \ | |
1338 | { "NO_REGS", \ | |
ab408a86 | 1339 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1340 | "SIREG", "DIREG", \ |
e075ae69 RH |
1341 | "AD_REGS", \ |
1342 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1343 | "INDEX_REGS", \ |
3f3f2124 | 1344 | "LEGACY_REGS", \ |
621bc046 | 1345 | "CLOBBERED_REGS", \ |
c98f8742 JVA |
1346 | "GENERAL_REGS", \ |
1347 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1348 | "FLOAT_REGS", \ | |
cb482895 | 1349 | "SSE_FIRST_REG", \ |
a7180f70 | 1350 | "SSE_REGS", \ |
3f97cb0b AI |
1351 | "EVEX_SSE_REGS", \ |
1352 | "ALL_SSE_REGS", \ | |
a7180f70 | 1353 | "MMX_REGS", \ |
446988df JH |
1354 | "FP_TOP_SSE_REGS", \ |
1355 | "FP_SECOND_SSE_REGS", \ | |
1356 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1357 | "FLOAT_INT_REGS", \ |
446988df JH |
1358 | "INT_SSE_REGS", \ |
1359 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 AI |
1360 | "MASK_EVEX_REGS", \ |
1361 | "MASK_REGS", \ | |
c98f8742 JVA |
1362 | "ALL_REGS" } |
1363 | ||
ac2e563f RH |
1364 | /* Define which registers fit in which classes. This is an initializer |
1365 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1366 | ||
621bc046 UB |
1367 | Note that CLOBBERED_REGS are calculated by |
1368 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1369 | |
3f97cb0b | 1370 | #define REG_CLASS_CONTENTS \ |
089d1227 IE |
1371 | { { 0x00, 0x0, 0x0 }, \ |
1372 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1373 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1374 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1375 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1376 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1377 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1378 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
1379 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ | |
1380 | { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ | |
1381 | { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ | |
1382 | { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
1383 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ | |
1384 | { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ | |
1385 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1386 | { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1387 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1388 | { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
1389 | { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ | |
1390 | { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ | |
1391 | { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ | |
1392 | { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ | |
1393 | { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ | |
1394 | { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ | |
1395 | { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ | |
1396 | { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1397 | { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ | |
1398 | { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ | |
1399 | { 0x0, 0x0,0x1fc0 }, /* MASK_EVEX_REGS */ \ | |
1400 | { 0x0, 0x0,0x1fe0 }, /* MASK_REGS */ \ | |
1401 | { 0xffffffff,0xffffffff,0x1fff } \ | |
e075ae69 | 1402 | } |
c98f8742 JVA |
1403 | |
1404 | /* The same information, inverted: | |
1405 | Return the class number of the smallest class containing | |
1406 | reg number REGNO. This could be a conditional expression | |
1407 | or could index an array. */ | |
1408 | ||
c98f8742 JVA |
1409 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1410 | ||
42db504c SB |
1411 | /* When this hook returns true for MODE, the compiler allows |
1412 | registers explicitly used in the rtl to be used as spill registers | |
1413 | but prevents the compiler from extending the lifetime of these | |
1414 | registers. */ | |
1415 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1416 | |
fc27f749 UB |
1417 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
1418 | #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG) | |
3f3f2124 JH |
1419 | |
1420 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1421 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 UB |
1422 | #define GENERAL_REGNO_P(N) \ |
1423 | (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N)) | |
3f3f2124 | 1424 | |
fc27f749 UB |
1425 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1426 | #define ANY_QI_REGNO_P(N) \ | |
1427 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1428 | |
fc27f749 | 1429 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1430 | #define REX_INT_REGNO_P(N) \ |
1431 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1432 | |
66aaf16f UB |
1433 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1434 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1435 | |
446988df | 1436 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
66aaf16f | 1437 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1438 | |
54a88090 | 1439 | #define X87_FLOAT_MODE_P(MODE) \ |
27ac40e2 | 1440 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) |
54a88090 | 1441 | |
fc27f749 | 1442 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1443 | #define SSE_REGNO_P(N) \ |
1444 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
3f97cb0b AI |
1445 | || REX_SSE_REGNO_P (N) \ |
1446 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1447 | |
4977bab6 | 1448 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1449 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1450 | |
3f97cb0b AI |
1451 | #define EXT_REX_SSE_REGNO_P(N) \ |
1452 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1453 | ||
d9a5f180 | 1454 | #define SSE_REGNO(N) \ |
3f97cb0b AI |
1455 | ((N) < 8 ? FIRST_SSE_REG + (N) \ |
1456 | : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ | |
1457 | : (FIRST_EXT_REX_SSE_REG + (N) - 16)) | |
1458 | ||
9e4a4dd6 | 1459 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 AI |
1460 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
1461 | #define ANY_MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) | |
446988df | 1462 | |
d9a5f180 | 1463 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1464 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1465 | |
cbf2e4d4 HJ |
1466 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ |
1467 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1468 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1469 | ||
fc27f749 | 1470 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1471 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1472 | |
fc27f749 | 1473 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG) |
c98f8742 | 1474 | |
e075ae69 RH |
1475 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1476 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1477 | ||
c98f8742 JVA |
1478 | /* The class value for index registers, and the one for base regs. */ |
1479 | ||
1480 | #define INDEX_REG_CLASS INDEX_REGS | |
1481 | #define BASE_REG_CLASS GENERAL_REGS | |
1482 | ||
c98f8742 | 1483 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1484 | is necessary to be able to hold a value of mode MODE in a reload |
b197fc48 UB |
1485 | register for which class CLASS would ordinarily be used. |
1486 | ||
1487 | We avoid classes containing registers from multiple units due to | |
1488 | the limitation in ix86_secondary_memory_needed. We limit these | |
1489 | classes to their "natural mode" single unit register class, depending | |
1490 | on the unit availability. | |
1491 | ||
1492 | Please note that reg_class_subset_p is not commutative, so these | |
1493 | conditions mean "... if (CLASS) includes ALL registers from the | |
1494 | register set." */ | |
1495 | ||
1496 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
1497 | (((MODE) == QImode && !TARGET_64BIT \ | |
1498 | && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ | |
1499 | : (((MODE) == SImode || (MODE) == DImode) \ | |
1500 | && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ | |
1501 | : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ | |
1502 | && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ | |
1503 | : (X87_FLOAT_MODE_P (MODE) \ | |
1504 | && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ | |
1505 | : (CLASS)) | |
c98f8742 | 1506 | |
85ff473e | 1507 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1508 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1509 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1510 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 | 1511 | |
c62b3659 UB |
1512 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1513 | There is no need to emit full 64 bit move on 64 bit targets | |
1514 | for integral modes that can be moved using 32 bit move. */ | |
1515 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1516 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1517 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1518 | : MODE) | |
1519 | ||
1272914c RH |
1520 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1521 | ||
1522 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1523 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1524 | \f |
1525 | /* Stack layout; function entry, exit and calling. */ | |
1526 | ||
1527 | /* Define this if pushing a word on the stack | |
1528 | makes the stack pointer a smaller address. */ | |
1529 | #define STACK_GROWS_DOWNWARD | |
1530 | ||
a4d05547 | 1531 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1532 | is at the high-address end of the local variables; |
1533 | that is, each additional local variable allocated | |
1534 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1535 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1536 | |
1537 | /* Offset within stack frame to start allocating local variables at. | |
1538 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1539 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1540 | of the first local allocated. */ | |
1541 | #define STARTING_FRAME_OFFSET 0 | |
1542 | ||
8c2b2fae UB |
1543 | /* If we generate an insn to push BYTES bytes, this says how many the stack |
1544 | pointer really advances by. On 386, we have pushw instruction that | |
1545 | decrements by exactly 2 no matter what the position was, there is no pushb. | |
1546 | ||
1547 | But as CIE data alignment factor on this arch is -4 for 32bit targets | |
1548 | and -8 for 64bit targets, we need to make sure all stack pointer adjustments | |
1549 | are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ | |
c98f8742 | 1550 | |
d2836273 | 1551 | #define PUSH_ROUNDING(BYTES) \ |
8c2b2fae UB |
1552 | (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) |
1553 | ||
1554 | /* If defined, the maximum amount of space required for outgoing arguments | |
1555 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1556 | No space will be pushed onto the stack for each call; instead, the | |
1557 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1558 | |
1559 | In 32bit mode enabling argument accumulation results in about 5% code size | |
1560 | growth becuase move instructions are less compact than push. In 64bit | |
1561 | mode the difference is less drastic but visible. | |
1562 | ||
1563 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1564 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1565 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1566 | |
1567 | With the 64-bit MS ABI, we can generate correct code with or without | |
1568 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1569 | generated without accumulated args is terrible. | |
41ee845b JH |
1570 | |
1571 | If stack probes are required, the space used for large function | |
1572 | arguments on the stack must also be probed, so enable | |
1573 | -maccumulate-outgoing-args so this happens in the prologue. */ | |
f73ad30e | 1574 | |
6c6094f1 | 1575 | #define ACCUMULATE_OUTGOING_ARGS \ |
41ee845b JH |
1576 | ((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \ |
1577 | || TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI) | |
f73ad30e JH |
1578 | |
1579 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1580 | instructions to pass outgoing arguments. */ | |
1581 | ||
1582 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1583 | ||
2da4124d L |
1584 | /* We want the stack and args grow in opposite directions, even if |
1585 | PUSH_ARGS is 0. */ | |
1586 | #define PUSH_ARGS_REVERSED 1 | |
1587 | ||
c98f8742 JVA |
1588 | /* Offset of first parameter from the argument pointer register value. */ |
1589 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1590 | ||
a7180f70 BS |
1591 | /* Define this macro if functions should assume that stack space has been |
1592 | allocated for arguments even when their values are passed in registers. | |
1593 | ||
1594 | The value of this macro is the size, in bytes, of the area reserved for | |
1595 | arguments passed in registers for the function represented by FNDECL. | |
1596 | ||
1597 | This space can be allocated by the caller, or be a part of the | |
1598 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1599 | which. */ | |
7c800926 KT |
1600 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1601 | ||
4ae8027b | 1602 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1603 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1604 | |
c98f8742 JVA |
1605 | /* Define how to find the value returned by a library function |
1606 | assuming the value has mode MODE. */ | |
1607 | ||
4ae8027b | 1608 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1609 | |
e9125c09 TW |
1610 | /* Define the size of the result block used for communication between |
1611 | untyped_call and untyped_return. The block contains a DImode value | |
1612 | followed by the block used by fnsave and frstor. */ | |
1613 | ||
1614 | #define APPLY_RESULT_SIZE (8+108) | |
1615 | ||
b08de47e | 1616 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1617 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1618 | |
1619 | /* Define a data type for recording info about an argument list | |
1620 | during the scan of that argument list. This data type should | |
1621 | hold all necessary information about the function itself | |
1622 | and about the args processed so far, enough to enable macros | |
b08de47e | 1623 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1624 | |
e075ae69 | 1625 | typedef struct ix86_args { |
fa283935 | 1626 | int words; /* # words passed so far */ |
b08de47e MM |
1627 | int nregs; /* # registers available for passing */ |
1628 | int regno; /* next available register number */ | |
3e65f251 KT |
1629 | int fastcall; /* fastcall or thiscall calling convention |
1630 | is used */ | |
fa283935 | 1631 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1632 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1633 | int warn_avx512f; /* True when we want to warn |
1634 | about AVX512F ABI. */ | |
95879c72 | 1635 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1636 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1637 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1638 | int sse_regno; /* next available sse register number */ | |
1639 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1640 | int mmx_nregs; /* # mmx registers available for passing */ |
1641 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1642 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1643 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1644 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1645 | SFmode/DFmode arguments should be passed | |
1646 | in SSE registers. Otherwise 0. */ | |
51212b32 | 1647 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1648 | MS_ABI for ms abi. */ |
b08de47e | 1649 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1650 | |
1651 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1652 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1653 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1654 | |
0f6937fe | 1655 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1656 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1657 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1658 | |
c98f8742 JVA |
1659 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1660 | for profiling a function entry. */ | |
1661 | ||
a5fa1ecd JH |
1662 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1663 | ||
1664 | #define MCOUNT_NAME "_mcount" | |
1665 | ||
3c5273a9 KT |
1666 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1667 | ||
a5fa1ecd | 1668 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1669 | |
1670 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1671 | the stack pointer does not matter. The value is tested only in | |
1672 | functions that have frame pointers. | |
1673 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1674 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1675 | we have to restore it ourselves from the frame pointer, in order to |
1676 | use pop */ | |
1677 | ||
1678 | #define EXIT_IGNORE_STACK 1 | |
1679 | ||
c98f8742 JVA |
1680 | /* Output assembler code for a block containing the constant parts |
1681 | of a trampoline, leaving space for the variable parts. */ | |
1682 | ||
a269a03c | 1683 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1684 | mov #STATIC,ecx |
a269a03c JC |
1685 | jmp FUNCTION |
1686 | The trampoline is generated entirely at runtime. The operand of JMP | |
1687 | is the address of FUNCTION relative to the instruction following the | |
1688 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1689 | |
1690 | /* Length in units of the trampoline for entering a nested function. */ | |
1691 | ||
3452586b | 1692 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) |
c98f8742 JVA |
1693 | \f |
1694 | /* Definitions for register eliminations. | |
1695 | ||
1696 | This is an array of structures. Each structure initializes one pair | |
1697 | of eliminable registers. The "from" register number is given first, | |
1698 | followed by "to". Eliminations of the same "from" register are listed | |
1699 | in order of preference. | |
1700 | ||
afc2cd05 NC |
1701 | There are two registers that can always be eliminated on the i386. |
1702 | The frame pointer and the arg pointer can be replaced by either the | |
1703 | hard frame pointer or to the stack pointer, depending upon the | |
1704 | circumstances. The hard frame pointer is not used before reload and | |
1705 | so it is not eligible for elimination. */ | |
c98f8742 | 1706 | |
564d80f4 JH |
1707 | #define ELIMINABLE_REGS \ |
1708 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1709 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1710 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1711 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1712 | |
c98f8742 JVA |
1713 | /* Define the offset between two registers, one to be eliminated, and the other |
1714 | its replacement, at the start of a routine. */ | |
1715 | ||
d9a5f180 GS |
1716 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1717 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1718 | \f |
1719 | /* Addressing modes, and classification of registers for them. */ | |
1720 | ||
c98f8742 JVA |
1721 | /* Macros to check register numbers against specific register classes. */ |
1722 | ||
1723 | /* These assume that REGNO is a hard or pseudo reg number. | |
1724 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1725 | or a pseudo reg currently allocated to a suitable hard reg. | |
1726 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1727 | has been allocated, which happens in reginfo.c during register |
1728 | allocation. */ | |
c98f8742 | 1729 | |
3f3f2124 JH |
1730 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1731 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1732 | || REX_INT_REGNO_P (REGNO) \ |
1733 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1734 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1735 | |
3f3f2124 | 1736 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1737 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1738 | || (REGNO) == ARG_POINTER_REGNUM \ |
1739 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1740 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1741 | |
c98f8742 JVA |
1742 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1743 | and check its validity for a certain class. | |
1744 | We have two alternate definitions for each of them. | |
1745 | The usual definition accepts all pseudo regs; the other rejects | |
1746 | them unless they have been allocated suitable hard regs. | |
1747 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1748 | ||
1749 | Most source files want to accept pseudo regs in the hope that | |
1750 | they will get allocated to the class that the insn wants them to be in. | |
1751 | Source files for reload pass need to be strict. | |
1752 | After reload, it makes no difference, since pseudo regs have | |
1753 | been eliminated by then. */ | |
1754 | ||
c98f8742 | 1755 | |
ff482c8d | 1756 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1757 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1758 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1759 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1760 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1761 | ||
3b3c6a3f | 1762 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1763 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1764 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1765 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1766 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1767 | |
3b3c6a3f MM |
1768 | /* Strict versions, hard registers only */ |
1769 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1770 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1771 | |
3b3c6a3f | 1772 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1773 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1774 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1775 | |
1776 | #else | |
d9a5f180 GS |
1777 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1778 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1779 | #endif |
1780 | ||
331d9186 | 1781 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1782 | that is a valid memory address for an instruction. |
1783 | The MODE argument is the machine mode for the MEM expression | |
1784 | that wants to use this address. | |
1785 | ||
331d9186 | 1786 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1787 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1788 | ||
1789 | See legitimize_pic_address in i386.c for details as to what | |
1790 | constitutes a legitimate address when -fpic is used. */ | |
1791 | ||
1792 | #define MAX_REGS_PER_ADDRESS 2 | |
1793 | ||
f996902d | 1794 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1795 | |
ae1547cc UB |
1796 | /* Try a machine-dependent way of reloading an illegitimate address |
1797 | operand. If we find one, push the reload and jump to WIN. This | |
1798 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
1799 | ||
1800 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ | |
1801 | do { \ | |
1802 | if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
1803 | (int)(TYPE), (INDL))) \ | |
1804 | goto WIN; \ | |
1805 | } while (0) | |
1806 | ||
b949ea8b JW |
1807 | /* If defined, a C expression to determine the base term of address X. |
1808 | This macro is used in only one place: `find_base_term' in alias.c. | |
1809 | ||
1810 | It is always safe for this macro to not be defined. It exists so | |
1811 | that alias analysis can understand machine-dependent addresses. | |
1812 | ||
1813 | The typical use of this macro is to handle addresses containing | |
1814 | a label_ref or symbol_ref within an UNSPEC. */ | |
1815 | ||
d9a5f180 | 1816 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1817 | |
c98f8742 | 1818 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1819 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1820 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1821 | ||
f996902d | 1822 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1823 | |
1824 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1825 | (GET_CODE (X) == SYMBOL_REF \ |
1826 | || GET_CODE (X) == LABEL_REF \ | |
1827 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1828 | \f |
b08de47e MM |
1829 | /* Max number of args passed in registers. If this is more than 3, we will |
1830 | have problems with ebx (register #4), since it is a caller save register and | |
1831 | is also used as the pic register in ELF. So for now, don't allow more than | |
1832 | 3 registers to be passed in registers. */ | |
1833 | ||
7c800926 KT |
1834 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1835 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1836 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1837 | |
72fa3605 | 1838 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1839 | |
4ae8027b | 1840 | #define REGPARM_MAX \ |
2824d6e5 UB |
1841 | (TARGET_64BIT \ |
1842 | ? (TARGET_64BIT_MS_ABI \ | |
1843 | ? X86_64_MS_REGPARM_MAX \ | |
1844 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1845 | : X86_32_REGPARM_MAX) |
d2836273 | 1846 | |
72fa3605 UB |
1847 | #define X86_64_SSE_REGPARM_MAX 8 |
1848 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1849 | ||
b6010cab | 1850 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1851 | |
4ae8027b | 1852 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1853 | (TARGET_64BIT \ |
1854 | ? (TARGET_64BIT_MS_ABI \ | |
1855 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1856 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1857 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 JH |
1858 | |
1859 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
c98f8742 JVA |
1860 | \f |
1861 | /* Specify the machine mode that this machine uses | |
1862 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1863 | #define CASE_VECTOR_MODE \ |
6025b127 | 1864 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1865 | |
c98f8742 JVA |
1866 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1867 | #define DEFAULT_SIGNED_CHAR 1 | |
1868 | ||
1869 | /* Max number of bytes we can move from memory to memory | |
1870 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1871 | #define MOVE_MAX 16 |
1872 | ||
1873 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1874 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1875 | number of bytes we can move with a single instruction. */ |
63001560 | 1876 | #define MOVE_MAX_PIECES UNITS_PER_WORD |
c98f8742 | 1877 | |
7e24ffc9 | 1878 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1879 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1880 | Increasing the value will always make code faster, but eventually |
1881 | incurs high cost in increased code size. | |
c98f8742 | 1882 | |
e2e52e1b | 1883 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1884 | |
e04ad03d | 1885 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1886 | |
45d78e7f JJ |
1887 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1888 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1889 | ||
e04ad03d | 1890 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1891 | |
53f00dde UB |
1892 | /* Define if shifts truncate the shift count which implies one can |
1893 | omit a sign-extension or zero-extension of a shift count. | |
1894 | ||
1895 | On i386, shifts do truncate the count. But bit test instructions | |
1896 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1897 | |
1898 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1899 | ||
1900 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1901 | is done just by pretending it is already truncated. */ | |
1902 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1903 | ||
d9f32422 JH |
1904 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1905 | TYPE and which has the specified mode and signedness is to be | |
1906 | stored in a register. This macro is only called when TYPE is a | |
1907 | scalar type. | |
1908 | ||
f710504c | 1909 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1910 | quantities to SImode. The choice depends on target type. */ |
1911 | ||
1912 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1913 | do { \ |
d9f32422 JH |
1914 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1915 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1916 | (MODE) = SImode; \ |
1917 | } while (0) | |
d9f32422 | 1918 | |
c98f8742 JVA |
1919 | /* Specify the machine mode that pointers have. |
1920 | After generation of rtl, the compiler makes no further distinction | |
1921 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1922 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1923 | |
f0ea7581 L |
1924 | /* A C expression whose value is zero if pointers that need to be extended |
1925 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1926 | greater then zero if they are zero-extended and less then zero if the | |
1927 | ptr_extend instruction should be used. */ | |
1928 | ||
1929 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1930 | ||
c98f8742 JVA |
1931 | /* A function address in a call instruction |
1932 | is a byte address (for indexing purposes) | |
1933 | so give the MEM rtx a byte's mode. */ | |
1934 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1935 | \f |
d4ba09c0 | 1936 | |
d4ba09c0 SC |
1937 | /* A C expression for the cost of a branch instruction. A value of 1 |
1938 | is the default; other values are interpreted relative to that. */ | |
1939 | ||
3a4fd356 JH |
1940 | #define BRANCH_COST(speed_p, predictable_p) \ |
1941 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1942 | |
e327d1a3 L |
1943 | /* An integer expression for the size in bits of the largest integer machine |
1944 | mode that should actually be used. We allow pairs of registers. */ | |
1945 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1946 | ||
d4ba09c0 SC |
1947 | /* Define this macro as a C expression which is nonzero if accessing |
1948 | less than a word of memory (i.e. a `char' or a `short') is no | |
1949 | faster than accessing a word of memory, i.e., if such access | |
1950 | require more than one instruction or if there is no difference in | |
1951 | cost between byte and (aligned) word loads. | |
1952 | ||
1953 | When this macro is not defined, the compiler will access a field by | |
1954 | finding the smallest containing object; when it is defined, a | |
1955 | fullword load will be used if alignment permits. Unless bytes | |
1956 | accesses are faster than word accesses, using word accesses is | |
1957 | preferable since it may eliminate subsequent memory access if | |
1958 | subsequent accesses occur to other fields in the same word of the | |
1959 | structure, but to different bytes. */ | |
1960 | ||
1961 | #define SLOW_BYTE_ACCESS 0 | |
1962 | ||
1963 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1964 | #define SLOW_SHORT_ACCESS 0 | |
1965 | ||
d4ba09c0 SC |
1966 | /* Define this macro to be the value 1 if unaligned accesses have a |
1967 | cost many times greater than aligned accesses, for example if they | |
1968 | are emulated in a trap handler. | |
1969 | ||
9cd10576 KH |
1970 | When this macro is nonzero, the compiler will act as if |
1971 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 1972 | moves. This can cause significantly more instructions to be |
9cd10576 | 1973 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
1974 | accesses only add a cycle or two to the time for a memory access. |
1975 | ||
1976 | If the value of this macro is always zero, it need not be defined. */ | |
1977 | ||
e1565e65 | 1978 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 1979 | |
d4ba09c0 SC |
1980 | /* Define this macro if it is as good or better to call a constant |
1981 | function address than to call an address kept in a register. | |
1982 | ||
1983 | Desirable on the 386 because a CALL with a constant address is | |
1984 | faster than one with a register address. */ | |
1985 | ||
1986 | #define NO_FUNCTION_CSE | |
c98f8742 | 1987 | \f |
c572e5ba JVA |
1988 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1989 | return the mode to be used for the comparison. | |
1990 | ||
1991 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 1992 | VOIDmode should be used in all other cases. |
c572e5ba | 1993 | |
16189740 | 1994 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 1995 | possible, to allow for more combinations. */ |
c98f8742 | 1996 | |
d9a5f180 | 1997 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 1998 | |
9cd10576 | 1999 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2000 | reversed. */ |
2001 | ||
2002 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2003 | ||
2004 | /* A C expression whose value is reversed condition code of the CODE for | |
2005 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2006 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2007 | |
c98f8742 JVA |
2008 | \f |
2009 | /* Control the assembler format that we output, to the extent | |
2010 | this does not vary between assemblers. */ | |
2011 | ||
2012 | /* How to refer to registers in assembler output. | |
892a2d68 | 2013 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2014 | |
a7b376ee | 2015 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2016 | For non floating point regs, the following are the HImode names. |
2017 | ||
2018 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
2019 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
2020 | "y" code. */ | |
c98f8742 | 2021 | |
a7180f70 BS |
2022 | #define HI_REGISTER_NAMES \ |
2023 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2024 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2025 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2026 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2027 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 2028 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
2029 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
2030 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
2031 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
2032 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 2033 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
089d1227 | 2034 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } |
a7180f70 | 2035 | |
c98f8742 JVA |
2036 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2037 | ||
2038 | /* Table of additional register names to use in user input. */ | |
2039 | ||
2040 | #define ADDITIONAL_REGISTER_NAMES \ | |
7c831c4d KY |
2041 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2042 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2043 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
2044 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
2045 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2046 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ | |
2047 | { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ | |
2048 | { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ | |
2049 | { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ | |
2050 | { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ | |
2051 | { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ | |
2052 | { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ | |
2053 | { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ | |
2054 | { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ | |
2055 | { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ | |
2056 | { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ | |
2057 | { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ | |
2058 | { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ | |
2059 | { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ | |
2060 | { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ | |
2061 | { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ | |
2062 | { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } | |
c98f8742 JVA |
2063 | |
2064 | /* Note we are omitting these since currently I don't know how | |
2065 | to get gcc to use these, since they want the same but different | |
2066 | number as al, and ax. | |
2067 | */ | |
2068 | ||
c98f8742 | 2069 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2070 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2071 | |
2072 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2073 | of regs 0 through 3. */ |
c98f8742 JVA |
2074 | |
2075 | #define QI_HIGH_REGISTER_NAMES \ | |
2076 | {"ah", "dh", "ch", "bh", } | |
2077 | ||
2078 | /* How to renumber registers for dbx and gdb. */ | |
2079 | ||
d9a5f180 GS |
2080 | #define DBX_REGISTER_NUMBER(N) \ |
2081 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2082 | |
9a82e702 MS |
2083 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2084 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2085 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2086 | |
780a5b71 UB |
2087 | extern int const x86_64_ms_sysv_extra_clobbered_registers[12]; |
2088 | ||
469ac993 JM |
2089 | /* Before the prologue, RA is at 0(%esp). */ |
2090 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2091 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2092 | |
e414ab29 | 2093 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2094 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2095 | ((COUNT) == 0 \ | |
0a81f074 RS |
2096 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ |
2097 | -UNITS_PER_WORD)) \ | |
2098 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2099 | |
892a2d68 | 2100 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2101 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2102 | |
a6ab3aad | 2103 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2104 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2105 | |
1020a5ab | 2106 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2107 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2108 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2109 | |
ad919812 | 2110 | |
e4c4ebeb RH |
2111 | /* Select a format to encode pointers in exception handling data. CODE |
2112 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2113 | true if the symbol may be affected by dynamic relocations. | |
2114 | ||
2115 | ??? All x86 object file formats are capable of representing this. | |
2116 | After all, the relocation needed is the same as for the call insn. | |
2117 | Whether or not a particular assembler allows us to enter such, I | |
2118 | guess we'll have to see. */ | |
d9a5f180 | 2119 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2120 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2121 | |
c98f8742 JVA |
2122 | /* This is how to output an insn to push a register on the stack. |
2123 | It need not be very fast code. */ | |
2124 | ||
d9a5f180 | 2125 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2126 | do { \ |
2127 | if (TARGET_64BIT) \ | |
2128 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2129 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2130 | else \ | |
2131 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2132 | } while (0) | |
c98f8742 JVA |
2133 | |
2134 | /* This is how to output an insn to pop a register from the stack. | |
2135 | It need not be very fast code. */ | |
2136 | ||
d9a5f180 | 2137 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2138 | do { \ |
2139 | if (TARGET_64BIT) \ | |
2140 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2141 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2142 | else \ | |
2143 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2144 | } while (0) | |
c98f8742 | 2145 | |
f88c65f7 | 2146 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2147 | |
2148 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2149 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2150 | |
f88c65f7 | 2151 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2152 | |
33f7f353 | 2153 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2154 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2155 | |
63001560 | 2156 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2157 | |
2158 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2159 | { \ | |
2160 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2161 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2162 | } |
2163 | ||
2164 | /* A C statement or statements which output an assembler instruction | |
2165 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2166 | variable of type `char *' which points to the opcode name in | |
2167 | its "internal" form--the form that is written in the machine | |
2168 | description. */ | |
2169 | ||
2170 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2171 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2172 | ||
6a90d232 L |
2173 | /* A C statement to output to the stdio stream FILE an assembler |
2174 | command to pad the location counter to a multiple of 1<<LOG | |
2175 | bytes if it is within MAX_SKIP bytes. */ | |
2176 | ||
2177 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
2178 | #undef ASM_OUTPUT_MAX_SKIP_PAD | |
2179 | #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ | |
2180 | if ((LOG) != 0) \ | |
2181 | { \ | |
2182 | if ((MAX_SKIP) == 0) \ | |
2183 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2184 | else \ | |
2185 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ | |
2186 | } | |
2187 | #endif | |
2188 | ||
135a687e KT |
2189 | /* Write the extra assembler code needed to declare a function |
2190 | properly. */ | |
2191 | ||
2192 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2193 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
2194 | ix86_asm_output_function_label (FILE, NAME, DECL) | |
2195 | ||
f7288899 EC |
2196 | /* Under some conditions we need jump tables in the text section, |
2197 | because the assembler cannot handle label differences between | |
2198 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2199 | |
2200 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2201 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2202 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2203 | |
cea3bd3e RH |
2204 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2205 | and switch back. For x86 we do this only to save a few bytes that | |
2206 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2207 | #define CRT_MKSTR2(VAL) #VAL |
2208 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2209 | ||
2210 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2211 | asm (SECTION_OP "\n\t" \ | |
2212 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2213 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2214 | |
2215 | /* Default threshold for putting data in large sections | |
2216 | with x86-64 medium memory model */ | |
2217 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
74b42c8b | 2218 | \f |
b97de419 L |
2219 | /* Which processor to tune code generation for. These must be in sync |
2220 | with processor_target_table in i386.c. */ | |
5bf0ebab RH |
2221 | |
2222 | enum processor_type | |
2223 | { | |
b97de419 L |
2224 | PROCESSOR_GENERIC = 0, |
2225 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2226 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2227 | PROCESSOR_PENTIUM, | |
2228 | PROCESSOR_PENTIUMPRO, | |
5bf0ebab | 2229 | PROCESSOR_PENTIUM4, |
89c43c0a | 2230 | PROCESSOR_NOCONA, |
340ef734 | 2231 | PROCESSOR_CORE2, |
d3c11974 L |
2232 | PROCESSOR_NEHALEM, |
2233 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2234 | PROCESSOR_HASWELL, |
d3c11974 L |
2235 | PROCESSOR_BONNELL, |
2236 | PROCESSOR_SILVERMONT, | |
9a7f94d7 | 2237 | PROCESSOR_INTEL, |
b97de419 L |
2238 | PROCESSOR_GEODE, |
2239 | PROCESSOR_K6, | |
2240 | PROCESSOR_ATHLON, | |
2241 | PROCESSOR_K8, | |
21efb4d4 | 2242 | PROCESSOR_AMDFAM10, |
1133125e | 2243 | PROCESSOR_BDVER1, |
4d652a18 | 2244 | PROCESSOR_BDVER2, |
eb2f2b44 | 2245 | PROCESSOR_BDVER3, |
ed97ad47 | 2246 | PROCESSOR_BDVER4, |
14b52538 | 2247 | PROCESSOR_BTVER1, |
e32bfc16 | 2248 | PROCESSOR_BTVER2, |
5bf0ebab RH |
2249 | PROCESSOR_max |
2250 | }; | |
2251 | ||
9e555526 | 2252 | extern enum processor_type ix86_tune; |
5bf0ebab | 2253 | extern enum processor_type ix86_arch; |
5bf0ebab | 2254 | |
8362f420 JH |
2255 | /* Size of the RED_ZONE area. */ |
2256 | #define RED_ZONE_SIZE 128 | |
2257 | /* Reserved area of the red zone for temporaries. */ | |
2258 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2259 | |
95899b34 | 2260 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2261 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2262 | |
2263 | /* Smallest class containing REGNO. */ | |
2264 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2265 | ||
0948ccb2 PB |
2266 | enum ix86_fpcmp_strategy { |
2267 | IX86_FPCMP_SAHF, | |
2268 | IX86_FPCMP_COMI, | |
2269 | IX86_FPCMP_ARITH | |
2270 | }; | |
22fb740d JH |
2271 | \f |
2272 | /* To properly truncate FP values into integers, we need to set i387 control | |
2273 | word. We can't emit proper mode switching code before reload, as spills | |
2274 | generated by reload may truncate values incorrectly, but we still can avoid | |
2275 | redundant computation of new control word by the mode switching pass. | |
2276 | The fldcw instructions are still emitted redundantly, but this is probably | |
2277 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2278 | the sequence. |
22fb740d JH |
2279 | |
2280 | The machinery is to emit simple truncation instructions and split them | |
2281 | before reload to instructions having USEs of two memory locations that | |
2282 | are filled by this code to old and new control word. | |
fce5a9f2 | 2283 | |
22fb740d JH |
2284 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2285 | needed. */ | |
2286 | ||
ff680eb1 UB |
2287 | enum ix86_entity |
2288 | { | |
ff97910d VY |
2289 | AVX_U128 = 0, |
2290 | I387_TRUNC, | |
ff680eb1 UB |
2291 | I387_FLOOR, |
2292 | I387_CEIL, | |
2293 | I387_MASK_PM, | |
2294 | MAX_386_ENTITIES | |
2295 | }; | |
2296 | ||
1cba2b96 | 2297 | enum ix86_stack_slot |
ff680eb1 | 2298 | { |
443ca5fc | 2299 | SLOT_TEMP = 0, |
ff680eb1 UB |
2300 | SLOT_CW_STORED, |
2301 | SLOT_CW_TRUNC, | |
2302 | SLOT_CW_FLOOR, | |
2303 | SLOT_CW_CEIL, | |
2304 | SLOT_CW_MASK_PM, | |
2305 | MAX_386_STACK_LOCALS | |
2306 | }; | |
22fb740d | 2307 | |
ff97910d VY |
2308 | enum avx_u128_state |
2309 | { | |
2310 | AVX_U128_CLEAN, | |
2311 | AVX_U128_DIRTY, | |
2312 | AVX_U128_ANY | |
2313 | }; | |
2314 | ||
22fb740d JH |
2315 | /* Define this macro if the port needs extra instructions inserted |
2316 | for mode switching in an optimizing compilation. */ | |
2317 | ||
ff680eb1 UB |
2318 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2319 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2320 | |
2321 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2322 | initializer for an array of integers. Each initializer element N | |
2323 | refers to an entity that needs mode switching, and specifies the | |
2324 | number of different modes that might need to be set for this | |
2325 | entity. The position of the initializer in the initializer - | |
2326 | starting counting at zero - determines the integer that is used to | |
2327 | refer to the mode-switched entity in question. */ | |
2328 | ||
ff680eb1 | 2329 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
ff97910d | 2330 | { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
22fb740d | 2331 | |
0f0138b6 JH |
2332 | \f |
2333 | /* Avoid renaming of stack registers, as doing so in combination with | |
2334 | scheduling just increases amount of live registers at time and in | |
2335 | the turn amount of fxch instructions needed. | |
2336 | ||
3f97cb0b AI |
2337 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2338 | ||
2339 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2340 | |
3f97cb0b AI |
2341 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \ |
2342 | (EXT_REX_SSE_REGNO_P (SRC) == \ | |
2343 | EXT_REX_SSE_REGNO_P (TARGET))) | |
22fb740d | 2344 | |
3b3c6a3f | 2345 | \f |
e91f04de | 2346 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2347 | \f |
ec7ded37 | 2348 | /* Machine specific frame tracking during prologue/epilogue generation. */ |
cd9c1ca8 | 2349 | |
604a6be9 | 2350 | #ifndef USED_FOR_TARGET |
ec7ded37 | 2351 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2352 | { |
ec7ded37 RH |
2353 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2354 | is drap_reg, we don't bother trying to record here the real CFA when | |
2355 | it might really be a DW_CFA_def_cfa_expression. */ | |
2356 | rtx cfa_reg; | |
2357 | HOST_WIDE_INT cfa_offset; | |
2358 | ||
2359 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2360 | When stack frame re-alignment is active, these may not be relative | |
2361 | to the CFA. However, in all cases they are relative to the offsets | |
2362 | of the saved registers stored in ix86_frame. */ | |
2363 | HOST_WIDE_INT sp_offset; | |
2364 | HOST_WIDE_INT fp_offset; | |
2365 | ||
2366 | /* The size of the red-zone that may be assumed for the purposes of | |
2367 | eliding register restore notes in the epilogue. This may be zero | |
2368 | if no red-zone is in effect, or may be reduced from the real | |
2369 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2370 | int red_zone_offset; | |
2371 | ||
2372 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2373 | value within the frame. If false then the offset above should be | |
2374 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2375 | thus has an offset of zero. */ | |
2376 | BOOL_BITFIELD sp_valid : 1; | |
2377 | BOOL_BITFIELD fp_valid : 1; | |
2378 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2379 | |
2380 | /* Indicate whether the local stack frame has been re-aligned. When | |
2381 | set, the SP/FP offsets above are relative to the aligned frame | |
2382 | and not the CFA. */ | |
2383 | BOOL_BITFIELD realigned : 1; | |
cd9c1ca8 RH |
2384 | }; |
2385 | ||
f81c9774 RH |
2386 | /* Private to winnt.c. */ |
2387 | struct seh_frame_state; | |
2388 | ||
d1b38208 | 2389 | struct GTY(()) machine_function { |
fa1a0d02 JH |
2390 | struct stack_local_entry *stack_locals; |
2391 | const char *some_ld_name; | |
4aab97f9 L |
2392 | int varargs_gpr_size; |
2393 | int varargs_fpr_size; | |
ff680eb1 | 2394 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b RH |
2395 | |
2396 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE | |
2397 | has been computed for. */ | |
2398 | int use_fast_prologue_epilogue_nregs; | |
2399 | ||
7458026b ILT |
2400 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2401 | the stack arguments for a function with a variable number of | |
2402 | arguments. This is set at the start of the function and is used | |
2403 | to initialize the overflow_arg_area field of the va_list | |
2404 | structure. */ | |
2405 | rtx split_stack_varargs_pointer; | |
2406 | ||
3452586b RH |
2407 | /* This value is used for amd64 targets and specifies the current abi |
2408 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2409 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2410 | |
2411 | /* Nonzero if the function accesses a previous frame. */ | |
2412 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2413 | ||
2414 | /* Nonzero if the function requires a CLD in the prologue. */ | |
2415 | BOOL_BITFIELD needs_cld : 1; | |
2416 | ||
922e3e33 UB |
2417 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2418 | expander to determine the style used. */ | |
3452586b RH |
2419 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2420 | ||
5bf5a10b AO |
2421 | /* If true, the current function needs the default PIC register, not |
2422 | an alternate register (on x86) and must not use the red zone (on | |
2423 | x86_64), even if it's a leaf function. We don't want the | |
2424 | function to be regarded as non-leaf because TLS calls need not | |
2425 | affect register allocation. This flag is set when a TLS call | |
2426 | instruction is expanded within a function, and never reset, even | |
2427 | if all such instructions are optimized away. Use the | |
2428 | ix86_current_function_calls_tls_descriptor macro for a better | |
2429 | approximation. */ | |
3452586b RH |
2430 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2431 | ||
2432 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2433 | stack below the return address. */ | |
2434 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2435 | |
529a6471 JJ |
2436 | /* If true, it is safe to not save/restore DRAP register. */ |
2437 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2438 | ||
ec7ded37 RH |
2439 | /* During prologue/epilogue generation, the current frame state. |
2440 | Otherwise, the frame state at the end of the prologue. */ | |
2441 | struct machine_frame_state fs; | |
f81c9774 RH |
2442 | |
2443 | /* During SEH output, this is non-null. */ | |
2444 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2445 | }; |
cd9c1ca8 | 2446 | #endif |
fa1a0d02 JH |
2447 | |
2448 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2449 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2450 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2451 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
922e3e33 | 2452 | #define ix86_current_function_needs_cld (cfun->machine->needs_cld) |
5bf5a10b AO |
2453 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2454 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2455 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2456 | calls are optimized away, we try to detect cases in which it was | |
2457 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2458 | verify whether there's any such instruction live by testing that | |
2459 | REG_SP is live. */ | |
2460 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2461 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2462 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
249e6b63 | 2463 | |
1bc7c5b6 ZW |
2464 | /* Control behavior of x86_file_start. */ |
2465 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2466 | #define X86_FILE_START_FLTUSED false | |
2467 | ||
7dcbf659 JH |
2468 | /* Flag to mark data that is in the large address area. */ |
2469 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2470 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2471 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2472 | |
2473 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2474 | have defined always, to avoid ifdefing. */ | |
2475 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2476 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2477 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2478 | ||
2479 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2480 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2481 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2482 | ||
82c0e1a0 KT |
2483 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2484 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2485 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2486 | ||
7942e47e RY |
2487 | extern void debug_ready_dispatch (void); |
2488 | extern void debug_dispatch_window (int); | |
2489 | ||
91afcfa3 QN |
2490 | /* The value at zero is only defined for the BMI instructions |
2491 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2492 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1068ced5 | 2493 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) |
91afcfa3 | 2494 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
1068ced5 | 2495 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) |
91afcfa3 QN |
2496 | |
2497 | ||
b8ce4e94 KT |
2498 | /* Flags returned by ix86_get_callcvt (). */ |
2499 | #define IX86_CALLCVT_CDECL 0x1 | |
2500 | #define IX86_CALLCVT_STDCALL 0x2 | |
2501 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2502 | #define IX86_CALLCVT_THISCALL 0x8 | |
2503 | #define IX86_CALLCVT_REGPARM 0x10 | |
2504 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2505 | ||
2506 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2507 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2508 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2509 | ||
b86b9f44 MM |
2510 | #define RECIP_MASK_NONE 0x00 |
2511 | #define RECIP_MASK_DIV 0x01 | |
2512 | #define RECIP_MASK_SQRT 0x02 | |
2513 | #define RECIP_MASK_VEC_DIV 0x04 | |
2514 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2515 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2516 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2517 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2518 | |
2519 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2520 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2521 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2522 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2523 | ||
5dcfdccd KY |
2524 | #define IX86_HLE_ACQUIRE (1 << 16) |
2525 | #define IX86_HLE_RELEASE (1 << 17) | |
2526 | ||
e83b8e2e JJ |
2527 | /* For switching between functions with different target attributes. */ |
2528 | #define SWITCHABLE_TARGET 1 | |
2529 | ||
c98f8742 JVA |
2530 | /* |
2531 | Local variables: | |
2532 | version-control: t | |
2533 | End: | |
2534 | */ |