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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
a5544970 | 2 | Copyright (C) 1988-2019 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
90922d36 | 42 | #define TARGET_64BIT TARGET_ISA_64BIT |
bf7b5747 | 43 | #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) |
90922d36 | 44 | #define TARGET_MMX TARGET_ISA_MMX |
bf7b5747 | 45 | #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) |
90922d36 | 46 | #define TARGET_3DNOW TARGET_ISA_3DNOW |
bf7b5747 | 47 | #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) |
90922d36 | 48 | #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A |
bf7b5747 | 49 | #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) |
90922d36 | 50 | #define TARGET_SSE TARGET_ISA_SSE |
bf7b5747 | 51 | #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) |
90922d36 | 52 | #define TARGET_SSE2 TARGET_ISA_SSE2 |
bf7b5747 | 53 | #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) |
90922d36 | 54 | #define TARGET_SSE3 TARGET_ISA_SSE3 |
bf7b5747 | 55 | #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) |
90922d36 | 56 | #define TARGET_SSSE3 TARGET_ISA_SSSE3 |
bf7b5747 | 57 | #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) |
90922d36 | 58 | #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 |
bf7b5747 | 59 | #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) |
90922d36 | 60 | #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 |
bf7b5747 | 61 | #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) |
90922d36 | 62 | #define TARGET_AVX TARGET_ISA_AVX |
bf7b5747 | 63 | #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) |
90922d36 | 64 | #define TARGET_AVX2 TARGET_ISA_AVX2 |
bf7b5747 | 65 | #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) |
cb610367 UB |
66 | #define TARGET_AVX512F TARGET_ISA_AVX512F |
67 | #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
68 | #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
69 | #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
70 | #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
71 | #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
72 | #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
73 | #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
07165dd7 AI |
74 | #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ |
75 | #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
b525d943 AI |
76 | #define TARGET_AVX512BW TARGET_ISA_AVX512BW |
77 | #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
f4af595f AI |
78 | #define TARGET_AVX512VL TARGET_ISA_AVX512VL |
79 | #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
3dcc8af5 IT |
80 | #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI |
81 | #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) | |
4190ea38 IT |
82 | #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA |
83 | #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) | |
5fbb13a7 KY |
84 | #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS |
85 | #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) | |
86 | #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW | |
87 | #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) | |
fca51879 JK |
88 | #define TARGET_AVX512VBMI2 TARGET_ISA_AVX512VBMI2 |
89 | #define TARGET_AVX512VBMI2_P(x) TARGET_ISA_AVX512VBMI2_P(x) | |
79fc8ffe AS |
90 | #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ |
91 | #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) | |
98966963 JK |
92 | #define TARGET_AVX512VNNI TARGET_ISA_AVX512VNNI |
93 | #define TARGET_AVX512VNNI_P(x) TARGET_ISA_AVX512VNNI_P(x) | |
e2a29465 JK |
94 | #define TARGET_AVX512BITALG TARGET_ISA_AVX512BITALG |
95 | #define TARGET_AVX512BITALG_P(x) TARGET_ISA_AVX512BITALG_P(x) | |
90922d36 | 96 | #define TARGET_FMA TARGET_ISA_FMA |
bf7b5747 | 97 | #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) |
90922d36 | 98 | #define TARGET_SSE4A TARGET_ISA_SSE4A |
bf7b5747 | 99 | #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) |
90922d36 | 100 | #define TARGET_FMA4 TARGET_ISA_FMA4 |
bf7b5747 | 101 | #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) |
90922d36 | 102 | #define TARGET_XOP TARGET_ISA_XOP |
bf7b5747 | 103 | #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) |
90922d36 | 104 | #define TARGET_LWP TARGET_ISA_LWP |
bf7b5747 | 105 | #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) |
90922d36 | 106 | #define TARGET_ABM TARGET_ISA_ABM |
bf7b5747 | 107 | #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) |
13b93d4b OM |
108 | #define TARGET_PCONFIG TARGET_ISA_PCONFIG |
109 | #define TARGET_PCONFIG_P(x) TARGET_ISA_PCONFIG_P(x) | |
110 | #define TARGET_WBNOINVD TARGET_ISA_WBNOINVD | |
111 | #define TARGET_WBNOINVD_P(x) TARGET_ISA_WBNOINVD_P(x) | |
73e32c47 JK |
112 | #define TARGET_SGX TARGET_ISA_SGX |
113 | #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) | |
1d516992 JK |
114 | #define TARGET_RDPID TARGET_ISA_RDPID |
115 | #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) | |
b8cca31c JK |
116 | #define TARGET_GFNI TARGET_ISA_GFNI |
117 | #define TARGET_GFNI_P(x) TARGET_ISA_GFNI_P(x) | |
b7b0a4fa JK |
118 | #define TARGET_VAES TARGET_ISA_VAES |
119 | #define TARGET_VAES_P(x) TARGET_ISA_VAES_P(x) | |
6557be99 JK |
120 | #define TARGET_VPCLMULQDQ TARGET_ISA_VPCLMULQDQ |
121 | #define TARGET_VPCLMULQDQ_P(x) TARGET_ISA_VPCLMULQDQ_P(x) | |
90922d36 | 122 | #define TARGET_BMI TARGET_ISA_BMI |
bf7b5747 | 123 | #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) |
90922d36 | 124 | #define TARGET_BMI2 TARGET_ISA_BMI2 |
bf7b5747 | 125 | #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) |
90922d36 | 126 | #define TARGET_LZCNT TARGET_ISA_LZCNT |
bf7b5747 | 127 | #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) |
90922d36 | 128 | #define TARGET_TBM TARGET_ISA_TBM |
bf7b5747 | 129 | #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) |
90922d36 | 130 | #define TARGET_POPCNT TARGET_ISA_POPCNT |
bf7b5747 | 131 | #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) |
90922d36 | 132 | #define TARGET_SAHF TARGET_ISA_SAHF |
bf7b5747 | 133 | #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) |
90922d36 | 134 | #define TARGET_MOVBE TARGET_ISA_MOVBE |
bf7b5747 | 135 | #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) |
90922d36 | 136 | #define TARGET_CRC32 TARGET_ISA_CRC32 |
bf7b5747 | 137 | #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) |
90922d36 | 138 | #define TARGET_AES TARGET_ISA_AES |
bf7b5747 | 139 | #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) |
c1618f82 AI |
140 | #define TARGET_SHA TARGET_ISA_SHA |
141 | #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
9cdea277 IT |
142 | #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT |
143 | #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
9ce29eb0 VK |
144 | #define TARGET_CLZERO TARGET_ISA_CLZERO |
145 | #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) | |
9cdea277 IT |
146 | #define TARGET_XSAVEC TARGET_ISA_XSAVEC |
147 | #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
148 | #define TARGET_XSAVES TARGET_ISA_XSAVES | |
149 | #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
90922d36 | 150 | #define TARGET_PCLMUL TARGET_ISA_PCLMUL |
bf7b5747 | 151 | #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) |
cb610367 UB |
152 | #define TARGET_CMPXCHG16B TARGET_ISA_CX16 |
153 | #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) | |
90922d36 | 154 | #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
bf7b5747 | 155 | #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) |
90922d36 | 156 | #define TARGET_RDRND TARGET_ISA_RDRND |
bf7b5747 | 157 | #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) |
90922d36 | 158 | #define TARGET_F16C TARGET_ISA_F16C |
bf7b5747 | 159 | #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) |
cb610367 UB |
160 | #define TARGET_RTM TARGET_ISA_RTM |
161 | #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
90922d36 | 162 | #define TARGET_HLE TARGET_ISA_HLE |
bf7b5747 | 163 | #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) |
90922d36 | 164 | #define TARGET_RDSEED TARGET_ISA_RDSEED |
bf7b5747 | 165 | #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) |
90922d36 | 166 | #define TARGET_PRFCHW TARGET_ISA_PRFCHW |
bf7b5747 | 167 | #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) |
90922d36 | 168 | #define TARGET_ADX TARGET_ISA_ADX |
bf7b5747 | 169 | #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) |
3a0d99bb | 170 | #define TARGET_FXSR TARGET_ISA_FXSR |
bf7b5747 | 171 | #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) |
3a0d99bb | 172 | #define TARGET_XSAVE TARGET_ISA_XSAVE |
bf7b5747 | 173 | #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) |
3a0d99bb | 174 | #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT |
bf7b5747 | 175 | #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) |
43b3f52f IT |
176 | #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 |
177 | #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
9c3bca11 IT |
178 | #define TARGET_CLWB TARGET_ISA_CLWB |
179 | #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) | |
500a08b2 VK |
180 | #define TARGET_MWAITX TARGET_ISA_MWAITX |
181 | #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) | |
41a4ef22 KY |
182 | #define TARGET_PKU TARGET_ISA_PKU |
183 | #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) | |
2a25448c IT |
184 | #define TARGET_SHSTK TARGET_ISA_SHSTK |
185 | #define TARGET_SHSTK_P(x) TARGET_ISA_SHSTK_P(x) | |
37d51c75 SP |
186 | #define TARGET_MOVDIRI TARGET_ISA_MOVDIRI |
187 | #define TARGET_MOVDIRI_P(x) TARGET_ISA_MOVDIRI_P(x) | |
188 | #define TARGET_MOVDIR64B TARGET_ISA_MOVDIR64B | |
189 | #define TARGET_MOVDIR64B_P(x) TARGET_ISA_MOVDIR64B_P(x) | |
55f31ed1 SP |
190 | #define TARGET_WAITPKG TARGET_ISA_WAITPKG |
191 | #define TARGET_WAITPKG_P(x) TARGET_ISA_WAITPKG_P(x) | |
f8d9957e SP |
192 | #define TARGET_CLDEMOTE TARGET_ISA_CLDEMOTE |
193 | #define TARGET_CLDEMOTE_P(x) TARGET_ISA_CLDEMOTE_P(x) | |
41f8d1fc AK |
194 | #define TARGET_PTWRITE TARGET_ISA_PTWRITE |
195 | #define TARGET_PTWRITE_P(x) TARGET_ISA_PTWRITE_P(x) | |
4f0e90fa HL |
196 | #define TARGET_AVX512BF16 TARGET_ISA_AVX512BF16 |
197 | #define TARGET_AVX512BF16_P(x) TARGET_ISA_AVX512BF16_P(x) | |
41a4ef22 | 198 | |
90922d36 | 199 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 200 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
90922d36 | 201 | #define TARGET_X32 TARGET_ABI_X32 |
bf7b5747 | 202 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) |
d5d618b5 L |
203 | #define TARGET_16BIT TARGET_CODE16 |
204 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
04e1d06b | 205 | |
dfa61b9e L |
206 | #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) |
207 | ||
26b5109f RS |
208 | #include "config/vxworks-dummy.h" |
209 | ||
7eb68c06 | 210 | #include "config/i386/i386-opts.h" |
ccf8e764 | 211 | |
c69fa2d4 | 212 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 213 | |
8c996513 JH |
214 | /* Specify what algorithm to use for stringops on known size. |
215 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
216 | known at compile time or estimated via feedback, the SIZE array | |
217 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 218 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
219 | When NOALIGN is true the code guaranting the alignment of the memory |
220 | block is skipped. | |
221 | ||
8c996513 | 222 | For example initializer: |
4f3f76e6 | 223 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 224 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 225 | be used otherwise. */ |
8c996513 JH |
226 | struct stringop_algs |
227 | { | |
228 | const enum stringop_alg unknown_size; | |
229 | const struct stringop_strategy { | |
230 | const int max; | |
231 | const enum stringop_alg alg; | |
340ef734 | 232 | int noalign; |
c69fa2d4 | 233 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
234 | }; |
235 | ||
d4ba09c0 SC |
236 | /* Define the specific costs for a given cpu */ |
237 | ||
238 | struct processor_costs { | |
8b60264b KG |
239 | const int add; /* cost of an add instruction */ |
240 | const int lea; /* cost of a lea instruction */ | |
241 | const int shift_var; /* variable shift costs */ | |
242 | const int shift_const; /* constant shift costs */ | |
f676971a | 243 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 244 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 245 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 246 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 247 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
248 | int movsx; /* The cost of movsx operation. */ |
249 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
250 | const int large_insn; /* insns larger than this cost more */ |
251 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 252 | memory-to-memory move insns. */ |
8b60264b KG |
253 | const int movzbl_load; /* cost of loading using movzbl */ |
254 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
255 | in QImode, HImode and SImode relative |
256 | to reg-reg move (2). */ | |
8b60264b | 257 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 258 | in QImode, HImode and SImode */ |
8b60264b KG |
259 | const int fp_move; /* cost of reg,reg fld/fst */ |
260 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 261 | in SFmode, DFmode and XFmode */ |
8b60264b | 262 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 263 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
264 | const int mmx_move; /* cost of moving MMX register. */ |
265 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 266 | in SImode and DImode */ |
8b60264b | 267 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 268 | in SImode and DImode */ |
df41dbaf JH |
269 | const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ |
270 | zmm_move; | |
271 | const int sse_load[5]; /* cost of loading SSE register | |
272 | in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
273 | const int sse_unaligned_load[5];/* cost of unaligned load. */ | |
274 | const int sse_store[5]; /* cost of storing SSE register | |
275 | in SImode, DImode and TImode. */ | |
276 | const int sse_unaligned_store[5];/* cost of unaligned store. */ | |
8b60264b | 277 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
df41dbaf JH |
278 | integer. */ |
279 | const int ssemmx_to_integer; /* cost of moving integer to mmxsse register. */ | |
a4fe6139 JH |
280 | const int gather_static, gather_per_elt; /* Cost of gather load is computed |
281 | as static + per_item * nelts. */ | |
282 | const int scatter_static, scatter_per_elt; /* Cost of gather store is | |
283 | computed as static + per_item * nelts. */ | |
46cb0441 ZD |
284 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
285 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
286 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
287 | const int simultaneous_prefetches; /* number of parallel prefetch | |
288 | operations. */ | |
4977bab6 | 289 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
290 | const int fadd; /* cost of FADD and FSUB instructions. */ |
291 | const int fmul; /* cost of FMUL instruction. */ | |
292 | const int fdiv; /* cost of FDIV instruction. */ | |
293 | const int fabs; /* cost of FABS instruction. */ | |
294 | const int fchs; /* cost of FCHS instruction. */ | |
295 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 296 | /* Specify what algorithm |
bee51209 | 297 | to use for stringops on unknown size. */ |
c53c148c | 298 | const int sse_op; /* cost of cheap SSE instruction. */ |
6065f444 JH |
299 | const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ |
300 | const int mulss; /* cost of MULSS instructions. */ | |
301 | const int mulsd; /* cost of MULSD instructions. */ | |
c53c148c JH |
302 | const int fmass; /* cost of FMASS instructions. */ |
303 | const int fmasd; /* cost of FMASD instructions. */ | |
6065f444 JH |
304 | const int divss; /* cost of DIVSS instructions. */ |
305 | const int divsd; /* cost of DIVSD instructions. */ | |
306 | const int sqrtss; /* cost of SQRTSS instructions. */ | |
307 | const int sqrtsd; /* cost of SQRTSD instructions. */ | |
a813c280 JH |
308 | const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; |
309 | /* Specify reassociation width for integer, | |
310 | fp, vector integer and vector fp | |
311 | operations. Generally should correspond | |
312 | to number of instructions executed in | |
313 | parallel. See also | |
314 | ix86_reassociation_width. */ | |
ad83025e | 315 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
316 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer |
317 | cost model. */ | |
318 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
319 | vectorizer cost model. */ | |
7dc58b50 ML |
320 | |
321 | /* The "0:0:8" label alignment specified for some processors generates | |
322 | secondary 8-byte alignment only for those label/jump/loop targets | |
323 | which have primary alignment. */ | |
324 | const char *const align_loop; /* Loop alignment. */ | |
325 | const char *const align_jump; /* Jump alignment. */ | |
326 | const char *const align_label; /* Label alignment. */ | |
327 | const char *const align_func; /* Function alignment. */ | |
d4ba09c0 SC |
328 | }; |
329 | ||
8b60264b | 330 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
331 | extern const struct processor_costs ix86_size_cost; |
332 | ||
333 | #define ix86_cur_cost() \ | |
334 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 335 | |
c98f8742 JVA |
336 | /* Macros used in the machine description to test the flags. */ |
337 | ||
b97de419 | 338 | /* configure can arrange to change it. */ |
e075ae69 | 339 | |
35b528be | 340 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 341 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 342 | #endif |
35b528be | 343 | |
004d3859 GK |
344 | #ifndef TARGET_FPMATH_DEFAULT |
345 | #define TARGET_FPMATH_DEFAULT \ | |
346 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
347 | #endif | |
348 | ||
bf7b5747 ST |
349 | #ifndef TARGET_FPMATH_DEFAULT_P |
350 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
351 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
352 | #endif | |
353 | ||
c207fd99 L |
354 | /* If the i387 is disabled or -miamcu is used , then do not return |
355 | values in it. */ | |
356 | #define TARGET_FLOAT_RETURNS_IN_80387 \ | |
357 | (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) | |
358 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ | |
359 | (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) | |
b08de47e | 360 | |
5791cc29 JT |
361 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
362 | compile-time constant. */ | |
363 | #ifdef IN_LIBGCC2 | |
6ac49599 | 364 | #undef TARGET_64BIT |
5791cc29 JT |
365 | #ifdef __x86_64__ |
366 | #define TARGET_64BIT 1 | |
367 | #else | |
368 | #define TARGET_64BIT 0 | |
369 | #endif | |
370 | #else | |
6ac49599 RS |
371 | #ifndef TARGET_BI_ARCH |
372 | #undef TARGET_64BIT | |
e49080ec | 373 | #undef TARGET_64BIT_P |
67adf6a9 | 374 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 375 | #define TARGET_64BIT 1 |
e49080ec | 376 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
377 | #else |
378 | #define TARGET_64BIT 0 | |
e49080ec | 379 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
380 | #endif |
381 | #endif | |
5791cc29 | 382 | #endif |
25f94bb5 | 383 | |
750054a2 CT |
384 | #define HAS_LONG_COND_BRANCH 1 |
385 | #define HAS_LONG_UNCOND_BRANCH 1 | |
386 | ||
9e555526 RH |
387 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
388 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
389 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
390 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 391 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
392 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
393 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
394 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
395 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 396 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 397 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
340ef734 | 398 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d3c11974 L |
399 | #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) |
400 | #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
3a579e09 | 401 | #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) |
d3c11974 L |
402 | #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) |
403 | #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
50e461df | 404 | #define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT) |
74b2bb19 | 405 | #define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS) |
a548a5a1 | 406 | #define TARGET_TREMONT (ix86_tune == PROCESSOR_TREMONT) |
52747219 | 407 | #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) |
cace2309 | 408 | #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) |
176a3386 | 409 | #define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE) |
06caf59d | 410 | #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) |
c234d831 | 411 | #define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE) |
79ab5364 JK |
412 | #define TARGET_ICELAKE_CLIENT (ix86_tune == PROCESSOR_ICELAKE_CLIENT) |
413 | #define TARGET_ICELAKE_SERVER (ix86_tune == PROCESSOR_ICELAKE_SERVER) | |
7cab07f0 | 414 | #define TARGET_CASCADELAKE (ix86_tune == PROCESSOR_CASCADELAKE) |
9a7f94d7 | 415 | #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
9d532162 | 416 | #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) |
21efb4d4 | 417 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
1133125e | 418 | #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
4d652a18 | 419 | #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
eb2f2b44 | 420 | #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) |
ed97ad47 | 421 | #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) |
14b52538 | 422 | #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
e32bfc16 | 423 | #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
9ce29eb0 | 424 | #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) |
2901f42f | 425 | #define TARGET_ZNVER2 (ix86_tune == PROCESSOR_ZNVER2) |
a269a03c | 426 | |
80fd744f RH |
427 | /* Feature tests against the various tunings. */ |
428 | enum ix86_tune_indices { | |
4b8bc035 | 429 | #undef DEF_TUNE |
3ad20bd4 | 430 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
431 | #include "x86-tune.def" |
432 | #undef DEF_TUNE | |
433 | X86_TUNE_LAST | |
80fd744f RH |
434 | }; |
435 | ||
ab442df7 | 436 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
437 | |
438 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
439 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
440 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
441 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 442 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
443 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
444 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
445 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
446 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
447 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
448 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
449 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
450 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
451 | #define TARGET_LCP_STALL \ |
452 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
453 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
454 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
455 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
456 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
457 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
458 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
459 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
460 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
461 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
462 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
463 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
5783ad0e UB |
464 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
465 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
466 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
467 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
468 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
469 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
470 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
471 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
472 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
473 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
474 | #define TARGET_INTEGER_DFMODE_MOVES \ |
475 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
476 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
477 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
478 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
479 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
1133125e HJ |
480 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
481 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
482 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
483 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
484 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
485 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
486 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
487 | #define TARGET_SSE_TYPELESS_STORES \ | |
488 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
489 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
490 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
491 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
492 | #define TARGET_PROLOGUE_USING_MOVE \ | |
493 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
494 | #define TARGET_EPILOGUE_USING_MOVE \ | |
495 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
496 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
497 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
498 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
499 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
500 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
501 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
502 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 503 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
504 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
505 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
506 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
507 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
508 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
509 | #define TARGET_PAD_SHORT_FUNCTION \ |
510 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
511 | #define TARGET_EXT_80387_CONSTANTS \ |
512 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
513 | #define TARGET_AVOID_VECTOR_DECODE \ |
514 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
515 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
516 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
517 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
518 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
519 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
520 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
521 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
522 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
523 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
524 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
525 | #define TARGET_USE_VECTOR_CONVERTS \ |
526 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
527 | #define TARGET_SLOW_PSHUFB \ |
528 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
8e0dc054 JJ |
529 | #define TARGET_AVOID_4BYTE_PREFIXES \ |
530 | ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] | |
f6aa5171 JH |
531 | #define TARGET_USE_GATHER \ |
532 | ix86_tune_features[X86_TUNE_USE_GATHER] | |
0dc41f28 WM |
533 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
534 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
535 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
536 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 537 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
538 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
539 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
540 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
541 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
542 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
543 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 544 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
545 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
546 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
5d0878e7 JH |
547 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
548 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
5c0d88e6 CF |
549 | #define TARGET_AVX128_OPTIMAL \ |
550 | ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] | |
55a2c322 VM |
551 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
552 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
553 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
554 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 555 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 556 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
557 | #define TARGET_ADJUST_UNROLL \ |
558 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
374f5bf8 UB |
559 | #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ |
560 | ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
ca90b1ed YR |
561 | #define TARGET_ONE_IF_CONV_INSN \ |
562 | ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] | |
348188bf L |
563 | #define TARGET_EMIT_VZEROUPPER \ |
564 | ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] | |
df7b0cc4 | 565 | |
80fd744f RH |
566 | /* Feature tests against the various architecture variations. */ |
567 | enum ix86_arch_indices { | |
cef31f9c | 568 | X86_ARCH_CMOV, |
80fd744f RH |
569 | X86_ARCH_CMPXCHG, |
570 | X86_ARCH_CMPXCHG8B, | |
571 | X86_ARCH_XADD, | |
572 | X86_ARCH_BSWAP, | |
573 | ||
574 | X86_ARCH_LAST | |
575 | }; | |
4f3f76e6 | 576 | |
ab442df7 | 577 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 578 | |
cef31f9c | 579 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
580 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
581 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
582 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
583 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
584 | ||
cef31f9c UB |
585 | /* For sane SSE instruction set generation we need fcomi instruction. |
586 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
587 | expands to a sequence that includes conditional move. */ | |
588 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
589 | ||
80fd744f RH |
590 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
591 | ||
cb261eb7 | 592 | extern unsigned char x86_prefetch_sse; |
80fd744f RH |
593 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
594 | ||
80fd744f RH |
595 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
596 | ||
597 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
598 | #define TARGET_MIX_SSE_I387 \ | |
599 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
600 | ||
5fa578f0 UB |
601 | #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) |
602 | #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) | |
603 | #define TARGET_HARD_XF_REGS (TARGET_80387) | |
604 | ||
80fd744f RH |
605 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
606 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
607 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 608 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 609 | |
67adf6a9 RH |
610 | #ifndef TARGET_64BIT_DEFAULT |
611 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 612 | #endif |
74dc3e94 RH |
613 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
614 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
615 | #endif | |
25f94bb5 | 616 | |
e0ea8797 AH |
617 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
618 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
619 | ||
79f5e442 ZD |
620 | /* Fence to use after loop using storent. */ |
621 | ||
622 | extern tree x86_mfence; | |
623 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
624 | ||
0ed4a390 JL |
625 | /* Once GDB has been enhanced to deal with functions without frame |
626 | pointers, we can change this to allow for elimination of | |
627 | the frame pointer in leaf functions. */ | |
628 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 629 | |
0a1c5e55 UB |
630 | /* Extra bits to force. */ |
631 | #define TARGET_SUBTARGET_DEFAULT 0 | |
632 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
633 | ||
634 | /* Extra bits to force on w/ 32-bit mode. */ | |
635 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
636 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
637 | ||
ccf8e764 RH |
638 | /* Extra bits to force on w/ 64-bit mode. */ |
639 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
8b131a8a UB |
640 | /* Enable MMX, SSE and SSE2 by default. */ |
641 | #define TARGET_SUBTARGET64_ISA_DEFAULT \ | |
642 | (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) | |
ccf8e764 | 643 | |
fee3eacd IS |
644 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
645 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 646 | #define TARGET_MACHO 0 |
9005471b | 647 | #define TARGET_MACHO_BRANCH_ISLANDS 0 |
fee3eacd IS |
648 | #define MACHOPIC_ATT_STUB 0 |
649 | /* (b) Macros defined in config/darwin.h */ | |
650 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
651 | #define MACHOPIC_INDIRECT 0 | |
652 | #define MACHOPIC_PURE 0 | |
9005471b | 653 | |
5a579c3b LE |
654 | /* For the RDOS */ |
655 | #define TARGET_RDOS 0 | |
656 | ||
9005471b | 657 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
658 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
659 | ||
6510e8bb KT |
660 | /* For the Windows 32-bit ABI. */ |
661 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
662 | ||
f81c9774 RH |
663 | /* This is re-defined by cygming.h. */ |
664 | #define TARGET_SEH 0 | |
665 | ||
51212b32 | 666 | /* The default abi used by target. */ |
7c800926 | 667 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 668 | |
b8b3f0ca | 669 | /* The default TLS segment register used by target. */ |
00402c94 RH |
670 | #define DEFAULT_TLS_SEG_REG \ |
671 | (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) | |
b8b3f0ca | 672 | |
cc69336f RH |
673 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
674 | with the rounding mode forced to 53 bits. */ | |
675 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
676 | ||
682cd442 GK |
677 | /* -march=native handling only makes sense with compiler running on |
678 | an x86 or x86_64 chip. If changing this condition, also change | |
679 | the condition in driver-i386.c. */ | |
680 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
681 | /* In driver-i386.c. */ |
682 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
683 | #define EXTRA_SPEC_FUNCTIONS \ | |
684 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 685 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
686 | #endif |
687 | ||
8981c15b JM |
688 | #if TARGET_64BIT_DEFAULT |
689 | #define OPT_ARCH64 "!m32" | |
690 | #define OPT_ARCH32 "m32" | |
691 | #else | |
f0ea7581 L |
692 | #define OPT_ARCH64 "m64|mx32" |
693 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
694 | #endif |
695 | ||
1cba2b96 EC |
696 | /* Support for configure-time defaults of some command line options. |
697 | The order here is important so that -march doesn't squash the | |
698 | tune or cpu values. */ | |
ce998900 | 699 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 700 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
701 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
702 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 703 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
704 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
705 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
706 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
707 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
708 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 709 | |
241e1a89 SC |
710 | /* Specs for the compiler proper */ |
711 | ||
628714d8 | 712 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 713 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 714 | |
682cd442 | 715 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
716 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
717 | #else | |
718 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
96f5b137 L |
719 | "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
720 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ | |
721 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" | |
fa959ce4 | 722 | #endif |
241e1a89 | 723 | #endif |
c98f8742 | 724 | \f |
30efe578 | 725 | /* Target CPU builtins. */ |
ab442df7 MM |
726 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
727 | ||
728 | /* Target Pragmas. */ | |
729 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 730 | |
b4c522fa IB |
731 | /* Target CPU versions for D. */ |
732 | #define TARGET_D_CPU_VERSIONS ix86_d_target_versions | |
733 | ||
628714d8 | 734 | #ifndef CC1_SPEC |
8015b78d | 735 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
736 | #endif |
737 | ||
738 | /* This macro defines names of additional specifications to put in the | |
739 | specs that can be used in various specifications like CC1_SPEC. Its | |
740 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
741 | |
742 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 743 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
744 | program. |
745 | ||
746 | Do not define this macro if it does not need to do anything. */ | |
747 | ||
748 | #ifndef SUBTARGET_EXTRA_SPECS | |
749 | #define SUBTARGET_EXTRA_SPECS | |
750 | #endif | |
751 | ||
752 | #define EXTRA_SPECS \ | |
628714d8 | 753 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
754 | SUBTARGET_EXTRA_SPECS |
755 | \f | |
ce998900 | 756 | |
8ce94e44 JM |
757 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
758 | SFmode, DFmode and XFmode) in the current excess precision | |
759 | configuration. */ | |
b8cab8a5 UB |
760 | #define X87_ENABLE_ARITH(MODE) \ |
761 | (flag_unsafe_math_optimizations \ | |
762 | || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
763 | || (MODE) == XFmode) | |
8ce94e44 JM |
764 | |
765 | /* Likewise, whether to allow direct conversions from integer mode | |
766 | IMODE (HImode, SImode or DImode) to MODE. */ | |
767 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
b8cab8a5 UB |
768 | (flag_unsafe_math_optimizations \ |
769 | || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
8ce94e44 JM |
770 | || (MODE) == XFmode \ |
771 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
772 | || (IMODE) == HImode) | |
773 | ||
979c67a5 UB |
774 | /* target machine storage layout */ |
775 | ||
65d9c0ab JH |
776 | #define SHORT_TYPE_SIZE 16 |
777 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
778 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
779 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 780 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 781 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 782 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
783 | #define LONG_DOUBLE_TYPE_SIZE \ |
784 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 785 | |
c637141a | 786 | #define WIDEST_HARDWARE_FP_SIZE 80 |
65d9c0ab | 787 | |
67adf6a9 | 788 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 789 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
790 | #else |
791 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
792 | #endif |
793 | ||
c98f8742 JVA |
794 | /* Define this if most significant byte of a word is the lowest numbered. */ |
795 | /* That is true on the 80386. */ | |
796 | ||
797 | #define BITS_BIG_ENDIAN 0 | |
798 | ||
799 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
800 | /* That is not true on the 80386. */ | |
801 | #define BYTES_BIG_ENDIAN 0 | |
802 | ||
803 | /* Define this if most significant word of a multiword number is the lowest | |
804 | numbered. */ | |
805 | /* Not true for 80386 */ | |
806 | #define WORDS_BIG_ENDIAN 0 | |
807 | ||
c98f8742 | 808 | /* Width of a word, in units (bytes). */ |
4ae8027b | 809 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
810 | |
811 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
812 | #define MIN_UNITS_PER_WORD 4 |
813 | #endif | |
c98f8742 | 814 | |
c98f8742 | 815 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 816 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 817 | |
e075ae69 | 818 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
bd5d3961 | 819 | #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 820 | |
2e3f842f L |
821 | /* Stack boundary of the main function guaranteed by OS. */ |
822 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
823 | ||
de1132d1 | 824 | /* Minimum stack boundary. */ |
cba9c789 | 825 | #define MIN_STACK_BOUNDARY BITS_PER_WORD |
2e3f842f | 826 | |
d1f87653 | 827 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 828 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 829 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 830 | |
de1132d1 | 831 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
832 | both 32bit and 64bit, to support codes that need 128 bit stack |
833 | alignment for SSE instructions, but can't realign the stack. */ | |
d9063947 L |
834 | #define PREFERRED_STACK_BOUNDARY_DEFAULT \ |
835 | (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) | |
2e3f842f L |
836 | |
837 | /* 1 if -mstackrealign should be turned on by default. It will | |
838 | generate an alternate prologue and epilogue that realigns the | |
839 | runtime stack if nessary. This supports mixing codes that keep a | |
840 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 841 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
842 | #define STACK_REALIGN_DEFAULT 0 |
843 | ||
844 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
845 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 846 | |
a2851b75 TG |
847 | /* According to Windows x64 software convention, the maximum stack allocatable |
848 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
849 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
850 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
851 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
852 | prologue. | |
853 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 854 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
855 | regs, then save them, and then allocate the remaining. There is no SEH |
856 | unwind info for this later allocation. */ | |
857 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
858 | ||
ebff937c SH |
859 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
860 | mandatory for the 64-bit ABI, and may or may not be true for other | |
861 | operating systems. */ | |
862 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
863 | ||
f963b5d9 RS |
864 | /* Minimum allocation boundary for the code of a function. */ |
865 | #define FUNCTION_BOUNDARY 8 | |
866 | ||
867 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
868 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 869 | |
c98f8742 JVA |
870 | /* Minimum size in bits of the largest boundary to which any |
871 | and all fundamental data types supported by the hardware | |
872 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 873 | rounder than this. |
fce5a9f2 | 874 | |
d1f87653 | 875 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
6d2b7199 BS |
876 | and Pentium Pro XFmode values at 128 bit boundaries. |
877 | ||
878 | When increasing the maximum, also update | |
879 | TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ | |
17f24ff0 | 880 | |
3f97cb0b | 881 | #define BIGGEST_ALIGNMENT \ |
0076c82f | 882 | (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) |
17f24ff0 | 883 | |
2e3f842f L |
884 | /* Maximum stack alignment. */ |
885 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
886 | ||
6e4f1168 L |
887 | /* Alignment value for attribute ((aligned)). It is a constant since |
888 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
e9c9e772 | 889 | #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) |
6e4f1168 | 890 | |
822eda12 | 891 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 892 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 893 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 894 | |
17f24ff0 | 895 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 896 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 897 | -malign-double is set. */ |
e932b21b | 898 | |
e83f3cff RH |
899 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
900 | supports no vector modes, cut out the complexity and fall back | |
901 | on BIGGEST_FIELD_ALIGNMENT. */ | |
902 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
903 | #ifdef __x86_64__ |
904 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
905 | #else | |
e83f3cff | 906 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 907 | #endif |
e83f3cff | 908 | #else |
a4cf4b64 RB |
909 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
910 | x86_field_alignment ((TYPE), (COMPUTED)) | |
e83f3cff | 911 | #endif |
c98f8742 | 912 | |
8a022443 JW |
913 | /* If defined, a C expression to compute the alignment for a static |
914 | variable. TYPE is the data type, and ALIGN is the alignment that | |
915 | the object would ordinarily have. The value of this macro is used | |
916 | instead of that alignment to align the object. | |
917 | ||
918 | If this macro is not defined, then ALIGN is used. | |
919 | ||
920 | One use of this macro is to increase alignment of medium-size | |
921 | data to make it all fit in fewer cache lines. Another is to | |
922 | cause character arrays to be word-aligned so that `strcpy' calls | |
923 | that copy constants to character arrays can be done inline. */ | |
924 | ||
df8a1d28 JJ |
925 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
926 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
927 | ||
928 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
929 | some alignment increase, instead of optimization only purposes. E.g. | |
930 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
931 | must be aligned to 16 byte boundaries. | |
932 | ||
933 | If this macro is not defined, then ALIGN is used. */ | |
934 | ||
935 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
936 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
937 | |
938 | /* If defined, a C expression to compute the alignment for a local | |
939 | variable. TYPE is the data type, and ALIGN is the alignment that | |
940 | the object would ordinarily have. The value of this macro is used | |
941 | instead of that alignment to align the object. | |
942 | ||
943 | If this macro is not defined, then ALIGN is used. | |
944 | ||
945 | One use of this macro is to increase alignment of medium-size | |
946 | data to make it all fit in fewer cache lines. */ | |
947 | ||
76fe54f0 L |
948 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
949 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
950 | ||
951 | /* If defined, a C expression to compute the alignment for stack slot. | |
952 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
953 | is the alignment that the slot would ordinarily have. The value of | |
954 | this macro is used instead of that alignment to align the slot. | |
955 | ||
956 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
957 | Otherwise, LOCAL_ALIGNMENT will be used. | |
958 | ||
959 | One use of this macro is to set alignment of stack slot to the | |
960 | maximum alignment of all possible modes which the slot may have. */ | |
961 | ||
962 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
963 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 964 | |
9bfaf89d JJ |
965 | /* If defined, a C expression to compute the alignment for a local |
966 | variable DECL. | |
967 | ||
968 | If this macro is not defined, then | |
969 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
970 | ||
971 | One use of this macro is to increase alignment of medium-size | |
972 | data to make it all fit in fewer cache lines. */ | |
973 | ||
974 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
975 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
976 | ||
ae58e548 JJ |
977 | /* If defined, a C expression to compute the minimum required alignment |
978 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
979 | MODE, assuming normal alignment ALIGN. | |
980 | ||
981 | If this macro is not defined, then (ALIGN) will be used. */ | |
982 | ||
983 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
1a6e82b8 | 984 | ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) |
ae58e548 | 985 | |
9bfaf89d | 986 | |
9cd10576 | 987 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 988 | when given unaligned data. */ |
b4ac57ab | 989 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
990 | |
991 | /* If bit field type is int, don't let it cross an int, | |
992 | and give entire struct the alignment of an int. */ | |
43a88a8c | 993 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 994 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
995 | \f |
996 | /* Standard register usage. */ | |
997 | ||
998 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 999 | for details. */ |
c98f8742 JVA |
1000 | |
1001 | #define STACK_REGS | |
ce998900 | 1002 | |
f48b4284 UB |
1003 | #define IS_STACK_MODE(MODE) \ |
1004 | (X87_FLOAT_MODE_P (MODE) \ | |
1005 | && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ | |
1006 | || TARGET_MIX_SSE_I387)) | |
c98f8742 JVA |
1007 | |
1008 | /* Number of actual hardware registers. | |
1009 | The hardware registers are assigned numbers for the compiler | |
1010 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
1011 | All registers that the compiler knows about must be given numbers, | |
1012 | even those that are not normally considered general registers. | |
1013 | ||
1014 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
1015 | We number the floating point registers 8-15. | |
1016 | Note that registers 0-7 can be accessed as a short or int, | |
1017 | while only 0-3 may be used with byte `mov' instructions. | |
1018 | ||
1019 | Reg 16 does not correspond to any hardware register, but instead | |
1020 | appears in the RTL as an argument pointer prior to reload, and is | |
1021 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 1022 | pointer. */ |
c98f8742 | 1023 | |
05416670 | 1024 | #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG |
c98f8742 | 1025 | |
3073d01c ML |
1026 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
1027 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
1028 | ||
1029 | #define DWARF_FRAME_REGISTERS 17 | |
1030 | ||
c98f8742 JVA |
1031 | /* 1 for registers that have pervasive standard uses |
1032 | and are not available for the register allocator. | |
3f3f2124 | 1033 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 1034 | |
621bc046 UB |
1035 | REX registers are disabled for 32bit targets in |
1036 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
1037 | ||
a7180f70 BS |
1038 | #define FIXED_REGISTERS \ |
1039 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 1040 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
eaa17c21 UB |
1041 | /*arg,flags,fpsr,frame*/ \ |
1042 | 1, 1, 1, 1, \ | |
a7180f70 BS |
1043 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
1044 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 1045 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
1046 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1047 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 1048 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 1049 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1050 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1051 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1052 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1053 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1054 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1055 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
eafa30ef | 1056 | 0, 0, 0, 0, 0, 0, 0, 0 } |
c98f8742 JVA |
1057 | |
1058 | /* 1 for registers not available across function calls. | |
1059 | These must include the FIXED_REGISTERS and also any | |
1060 | registers that can be used without being saved. | |
1061 | The latter must include the registers where values are returned | |
1062 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
1063 | Aside from that, you can include as many other registers as you like. |
1064 | ||
621bc046 UB |
1065 | Value is set to 1 if the register is call used unconditionally. |
1066 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
1067 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
1068 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
1069 | ||
1070 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
1071 | ||
1f3ccbc8 L |
1072 | #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ |
1073 | ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) | |
1074 | ||
a7180f70 BS |
1075 | #define CALL_USED_REGISTERS \ |
1076 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 1077 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
eaa17c21 UB |
1078 | /*arg,flags,fpsr,frame*/ \ |
1079 | 1, 1, 1, 1, \ | |
a7180f70 | 1080 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 1081 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 1082 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 1083 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1084 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1085 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1086 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1087 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1088 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1089 | 6, 6, 6, 6, 6, 6, 6, 6, \ | |
1090 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1091 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1092 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
eafa30ef | 1093 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 1094 | |
3b3c6a3f MM |
1095 | /* Order in which to allocate registers. Each register must be |
1096 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1097 | late and fixed registers last. Note that, in general, we prefer | |
1098 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1099 | available for storage of persistent values. | |
1100 | ||
5a733826 | 1101 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
162f023b | 1102 | so this is just empty initializer for array. */ |
3b3c6a3f | 1103 | |
eaa17c21 UB |
1104 | #define REG_ALLOC_ORDER \ |
1105 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
1106 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
1107 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
1108 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
1109 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 } | |
3b3c6a3f | 1110 | |
5a733826 | 1111 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 1112 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 1113 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1114 | |
5a733826 | 1115 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1116 | |
f5316dfe | 1117 | |
7c800926 KT |
1118 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1119 | ||
8521c414 | 1120 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
7bf65250 UB |
1121 | (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ |
1122 | && GENERAL_REGNO_P (REGNO) \ | |
1123 | && ((MODE) == XFmode || (MODE) == XCmode)) | |
8521c414 JM |
1124 | |
1125 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1126 | ||
95879c72 L |
1127 | #define VALID_AVX256_REG_MODE(MODE) \ |
1128 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb JJ |
1129 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
1130 | || (MODE) == V4DFmode) | |
95879c72 | 1131 | |
4ac005ba | 1132 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
ff97910d VY |
1133 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) |
1134 | ||
3f97cb0b AI |
1135 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
1136 | ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
1137 | || (MODE) == SFmode) | |
1138 | ||
1139 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1140 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 AI |
1141 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
1142 | || (MODE) == V4TImode) | |
1143 | ||
e6f146d2 SP |
1144 | #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ |
1145 | (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) | |
1146 | ||
05416670 | 1147 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ |
9e4a4dd6 | 1148 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ |
40bd4bf9 JJ |
1149 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ |
1150 | || (MODE) == TFmode || (MODE) == V1TImode) | |
3f97cb0b | 1151 | |
ce998900 UB |
1152 | #define VALID_SSE2_REG_MODE(MODE) \ |
1153 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1154 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1155 | |
d9a5f180 | 1156 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1157 | ((MODE) == V1TImode || (MODE) == TImode \ |
1158 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
ce998900 | 1159 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1160 | |
47f339cf | 1161 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1162 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1163 | |
d9a5f180 | 1164 | #define VALID_MMX_REG_MODE(MODE) \ |
879f9d0b | 1165 | ((MODE) == V1DImode || (MODE) == DImode \ |
10a97ae6 UB |
1166 | || (MODE) == V2SImode || (MODE) == SImode \ |
1167 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1168 | |
05416670 UB |
1169 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1170 | ||
1171 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) | |
1172 | ||
ce998900 UB |
1173 | #define VALID_DFP_MODE_P(MODE) \ |
1174 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1175 | |
d9a5f180 | 1176 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1177 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1178 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1179 | |
d9a5f180 | 1180 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1181 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1182 | || (MODE) == DImode \ | |
1183 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1184 | || (MODE) == CDImode \ | |
1185 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1186 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1187 | |
822eda12 | 1188 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1189 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1190 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1191 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1192 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1193 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1194 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1195 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1196 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
1197 | || (MODE) == V16SFmode) | |
822eda12 | 1198 | |
05416670 UB |
1199 | #define X87_FLOAT_MODE_P(MODE) \ |
1200 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
85a77221 | 1201 | |
05416670 UB |
1202 | #define SSE_FLOAT_MODE_P(MODE) \ |
1203 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
1204 | ||
1205 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ | |
1206 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1207 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
9e4a4dd6 | 1208 | |
ff25ef99 ZD |
1209 | /* It is possible to write patterns to move flags; but until someone |
1210 | does it, */ | |
1211 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1212 | |
e075ae69 | 1213 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1214 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1215 | |
787dc842 JH |
1216 | Kill any attempts to combine saving of modes. */ |
1217 | ||
d9a5f180 GS |
1218 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1219 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1220 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1221 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
a60c3351 UB |
1222 | : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ |
1223 | && TARGET_PARTIAL_REG_STALL) \ | |
85a77221 | 1224 | || MASK_REGNO_P (REGNO)) ? SImode \ |
a60c3351 | 1225 | : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ |
85a77221 | 1226 | || MASK_REGNO_P (REGNO)) ? SImode \ |
d2836273 | 1227 | : (MODE)) |
ce998900 | 1228 | |
c98f8742 JVA |
1229 | /* Specify the registers used for certain standard purposes. |
1230 | The values of these macros are register numbers. */ | |
1231 | ||
1232 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1233 | register. The ordinary mov instructions won't work */ | |
1234 | /* #define PC_REGNUM */ | |
1235 | ||
05416670 UB |
1236 | /* Base register for access to arguments of the function. */ |
1237 | #define ARG_POINTER_REGNUM ARGP_REG | |
1238 | ||
c98f8742 | 1239 | /* Register to use for pushing function arguments. */ |
05416670 | 1240 | #define STACK_POINTER_REGNUM SP_REG |
c98f8742 JVA |
1241 | |
1242 | /* Base register for access to local variables of the function. */ | |
05416670 UB |
1243 | #define FRAME_POINTER_REGNUM FRAME_REG |
1244 | #define HARD_FRAME_POINTER_REGNUM BP_REG | |
564d80f4 | 1245 | |
05416670 UB |
1246 | #define FIRST_INT_REG AX_REG |
1247 | #define LAST_INT_REG SP_REG | |
c98f8742 | 1248 | |
05416670 UB |
1249 | #define FIRST_QI_REG AX_REG |
1250 | #define LAST_QI_REG BX_REG | |
c98f8742 JVA |
1251 | |
1252 | /* First & last stack-like regs */ | |
05416670 UB |
1253 | #define FIRST_STACK_REG ST0_REG |
1254 | #define LAST_STACK_REG ST7_REG | |
c98f8742 | 1255 | |
05416670 UB |
1256 | #define FIRST_SSE_REG XMM0_REG |
1257 | #define LAST_SSE_REG XMM7_REG | |
fce5a9f2 | 1258 | |
05416670 UB |
1259 | #define FIRST_MMX_REG MM0_REG |
1260 | #define LAST_MMX_REG MM7_REG | |
a7180f70 | 1261 | |
05416670 UB |
1262 | #define FIRST_REX_INT_REG R8_REG |
1263 | #define LAST_REX_INT_REG R15_REG | |
3f3f2124 | 1264 | |
05416670 UB |
1265 | #define FIRST_REX_SSE_REG XMM8_REG |
1266 | #define LAST_REX_SSE_REG XMM15_REG | |
3f3f2124 | 1267 | |
05416670 UB |
1268 | #define FIRST_EXT_REX_SSE_REG XMM16_REG |
1269 | #define LAST_EXT_REX_SSE_REG XMM31_REG | |
3f97cb0b | 1270 | |
05416670 UB |
1271 | #define FIRST_MASK_REG MASK0_REG |
1272 | #define LAST_MASK_REG MASK7_REG | |
85a77221 | 1273 | |
aabcd309 | 1274 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1275 | requiring a frame pointer. */ |
1276 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1277 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1278 | #endif | |
1279 | ||
1280 | /* Make sure we can access arbitrary call frames. */ | |
1281 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 | 1282 | |
c98f8742 | 1283 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1284 | code access to data items. We don't use PIC pointer for 64bit |
1285 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1286 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1287 | |
1288 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1289 | the pic register when possible. The change is visible after the | |
1290 | prologue has been emitted. */ | |
1291 | ||
e8b5eb25 | 1292 | #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) |
bd09bdeb | 1293 | |
bcb21886 | 1294 | #define PIC_OFFSET_TABLE_REGNUM \ |
d290bb1d IE |
1295 | (ix86_use_pseudo_pic_reg () \ |
1296 | ? (pic_offset_table_rtx \ | |
1297 | ? INVALID_REGNUM \ | |
1298 | : REAL_PIC_OFFSET_TABLE_REGNUM) \ | |
1299 | : INVALID_REGNUM) | |
c98f8742 | 1300 | |
5fc0e5df KW |
1301 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1302 | ||
c51e6d85 | 1303 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1304 | #define MS_AGGREGATE_RETURN 0 |
1305 | ||
61fec9ff | 1306 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1307 | \f |
1308 | /* Define the classes of registers for register constraints in the | |
1309 | machine description. Also define ranges of constants. | |
1310 | ||
1311 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1312 | If there is more than one class, another class must be named NO_REGS | |
1313 | and contain no registers. | |
1314 | ||
1315 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1316 | another name such as ALL_REGS). This is the class of registers | |
1317 | that is allowed by "g" or "r" in a register constraint. | |
1318 | Also, registers outside this class are allocated only when | |
1319 | instructions express preferences for them. | |
1320 | ||
1321 | The classes must be numbered in nondecreasing order; that is, | |
1322 | a larger-numbered class must never be contained completely | |
2e24efd3 AM |
1323 | in a smaller-numbered class. This is why CLOBBERED_REGS class |
1324 | is listed early, even though in 64-bit mode it contains more | |
1325 | registers than just %eax, %ecx, %edx. | |
c98f8742 JVA |
1326 | |
1327 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1328 | class that represents their union. |
1329 | ||
eaa17c21 | 1330 | The flags and fpsr registers are in no class. */ |
c98f8742 JVA |
1331 | |
1332 | enum reg_class | |
1333 | { | |
1334 | NO_REGS, | |
e075ae69 | 1335 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1336 | AD_REGS, /* %eax/%edx for DImode */ |
2e24efd3 | 1337 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
c98f8742 | 1338 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1339 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
de86ff8f | 1340 | TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ |
c98f8742 | 1341 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1342 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
63001560 UB |
1343 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1344 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1345 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1346 | FLOAT_REGS, | |
06f4e35d | 1347 | SSE_FIRST_REG, |
45392c76 | 1348 | NO_REX_SSE_REGS, |
a7180f70 | 1349 | SSE_REGS, |
3f97cb0b | 1350 | ALL_SSE_REGS, |
a7180f70 | 1351 | MMX_REGS, |
446988df JH |
1352 | FLOAT_SSE_REGS, |
1353 | FLOAT_INT_REGS, | |
1354 | INT_SSE_REGS, | |
1355 | FLOAT_INT_SSE_REGS, | |
85a77221 | 1356 | MASK_REGS, |
d18cbbf6 UB |
1357 | ALL_MASK_REGS, |
1358 | ALL_REGS, | |
1359 | LIM_REG_CLASSES | |
c98f8742 JVA |
1360 | }; |
1361 | ||
d9a5f180 GS |
1362 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1363 | ||
1364 | #define INTEGER_CLASS_P(CLASS) \ | |
1365 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1366 | #define FLOAT_CLASS_P(CLASS) \ | |
1367 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1368 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1369 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1370 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1371 | ((CLASS) == MMX_REGS) |
4ed04e93 | 1372 | #define MASK_CLASS_P(CLASS) \ |
d18cbbf6 | 1373 | reg_class_subset_p ((CLASS), ALL_MASK_REGS) |
d9a5f180 GS |
1374 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1375 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1376 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1377 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1378 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1379 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1380 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1381 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 | 1382 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
d18cbbf6 | 1383 | reg_classes_intersect_p ((CLASS), ALL_MASK_REGS) |
d9a5f180 GS |
1384 | |
1385 | #define Q_CLASS_P(CLASS) \ | |
1386 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1387 | |
0bd72901 UB |
1388 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1389 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1390 | ||
43f3a59d | 1391 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1392 | |
1393 | #define REG_CLASS_NAMES \ | |
1394 | { "NO_REGS", \ | |
ab408a86 | 1395 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1396 | "SIREG", "DIREG", \ |
e075ae69 | 1397 | "AD_REGS", \ |
2e24efd3 | 1398 | "CLOBBERED_REGS", \ |
e075ae69 | 1399 | "Q_REGS", "NON_Q_REGS", \ |
de86ff8f | 1400 | "TLS_GOTBASE_REGS", \ |
c98f8742 | 1401 | "INDEX_REGS", \ |
3f3f2124 | 1402 | "LEGACY_REGS", \ |
c98f8742 JVA |
1403 | "GENERAL_REGS", \ |
1404 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1405 | "FLOAT_REGS", \ | |
cb482895 | 1406 | "SSE_FIRST_REG", \ |
45392c76 | 1407 | "NO_REX_SSE_REGS", \ |
a7180f70 | 1408 | "SSE_REGS", \ |
3f97cb0b | 1409 | "ALL_SSE_REGS", \ |
a7180f70 | 1410 | "MMX_REGS", \ |
446988df | 1411 | "FLOAT_SSE_REGS", \ |
8fcaaa80 | 1412 | "FLOAT_INT_REGS", \ |
446988df JH |
1413 | "INT_SSE_REGS", \ |
1414 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 | 1415 | "MASK_REGS", \ |
d18cbbf6 | 1416 | "ALL_MASK_REGS", \ |
c98f8742 JVA |
1417 | "ALL_REGS" } |
1418 | ||
ac2e563f RH |
1419 | /* Define which registers fit in which classes. This is an initializer |
1420 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1421 | ||
621bc046 UB |
1422 | Note that CLOBBERED_REGS are calculated by |
1423 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1424 | |
d18cbbf6 | 1425 | #define REG_CLASS_CONTENTS \ |
eaa17c21 UB |
1426 | { { 0x0, 0x0, 0x0 }, /* NO_REGS */ \ |
1427 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1428 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1429 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1430 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1431 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1432 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1433 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
1434 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ | |
1435 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ | |
1436 | { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ | |
1437 | { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ | |
1438 | { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ | |
1439 | { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
1440 | { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \ | |
1441 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1442 | { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1443 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1444 | { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
1445 | { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \ | |
1446 | { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \ | |
1447 | { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \ | |
1448 | { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \ | |
1449 | { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \ | |
1450 | { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1451 | { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \ | |
1452 | { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \ | |
1453 | { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ | |
1454 | { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ | |
1455 | { 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \ | |
e075ae69 | 1456 | } |
c98f8742 JVA |
1457 | |
1458 | /* The same information, inverted: | |
1459 | Return the class number of the smallest class containing | |
1460 | reg number REGNO. This could be a conditional expression | |
1461 | or could index an array. */ | |
1462 | ||
1a6e82b8 | 1463 | #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) |
c98f8742 | 1464 | |
42db504c SB |
1465 | /* When this hook returns true for MODE, the compiler allows |
1466 | registers explicitly used in the rtl to be used as spill registers | |
1467 | but prevents the compiler from extending the lifetime of these | |
1468 | registers. */ | |
1469 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1470 | |
fc27f749 | 1471 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
05416670 UB |
1472 | #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) |
1473 | ||
1474 | #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) | |
1475 | #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) | |
1476 | ||
1477 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
1478 | #define REX_INT_REGNO_P(N) \ | |
1479 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1480 | |
58b0b34c | 1481 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 | 1482 | #define GENERAL_REGNO_P(N) \ |
58b0b34c | 1483 | (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) |
3f3f2124 | 1484 | |
fc27f749 UB |
1485 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1486 | #define ANY_QI_REGNO_P(N) \ | |
1487 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1488 | |
66aaf16f UB |
1489 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1490 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1491 | |
fc27f749 | 1492 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1493 | #define SSE_REGNO_P(N) \ |
1494 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
3f97cb0b AI |
1495 | || REX_SSE_REGNO_P (N) \ |
1496 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1497 | |
4977bab6 | 1498 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1499 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1500 | |
0a48088a IT |
1501 | #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) |
1502 | ||
3f97cb0b AI |
1503 | #define EXT_REX_SSE_REGNO_P(N) \ |
1504 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1505 | ||
05416670 UB |
1506 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
1507 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) | |
3f97cb0b | 1508 | |
9e4a4dd6 | 1509 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 | 1510 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
446988df | 1511 | |
fc27f749 | 1512 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1513 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1514 | |
e075ae69 | 1515 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
adb67ffb | 1516 | #define CC_REGNO_P(X) ((X) == FLAGS_REG) |
e075ae69 | 1517 | |
5fbb13a7 KY |
1518 | #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) |
1519 | #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ | |
1520 | || (N) == XMM4_REG \ | |
1521 | || (N) == XMM8_REG \ | |
1522 | || (N) == XMM12_REG \ | |
1523 | || (N) == XMM16_REG \ | |
1524 | || (N) == XMM20_REG \ | |
1525 | || (N) == XMM24_REG \ | |
1526 | || (N) == XMM28_REG) | |
1527 | ||
05416670 UB |
1528 | /* First floating point reg */ |
1529 | #define FIRST_FLOAT_REG FIRST_STACK_REG | |
1530 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) | |
1531 | ||
02469d3a UB |
1532 | #define GET_SSE_REGNO(N) \ |
1533 | ((N) < 8 ? FIRST_SSE_REG + (N) \ | |
1534 | : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ | |
1535 | : FIRST_EXT_REX_SSE_REG + (N) - 16) | |
05416670 | 1536 | |
c98f8742 JVA |
1537 | /* The class value for index registers, and the one for base regs. */ |
1538 | ||
1539 | #define INDEX_REG_CLASS INDEX_REGS | |
1540 | #define BASE_REG_CLASS GENERAL_REGS | |
c98f8742 JVA |
1541 | \f |
1542 | /* Stack layout; function entry, exit and calling. */ | |
1543 | ||
1544 | /* Define this if pushing a word on the stack | |
1545 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1546 | #define STACK_GROWS_DOWNWARD 1 |
c98f8742 | 1547 | |
a4d05547 | 1548 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1549 | is at the high-address end of the local variables; |
1550 | that is, each additional local variable allocated | |
1551 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1552 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 | 1553 | |
7b4df2bf | 1554 | #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) |
8c2b2fae UB |
1555 | |
1556 | /* If defined, the maximum amount of space required for outgoing arguments | |
1557 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1558 | No space will be pushed onto the stack for each call; instead, the | |
1559 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1560 | |
1561 | In 32bit mode enabling argument accumulation results in about 5% code size | |
56aae4b7 | 1562 | growth because move instructions are less compact than push. In 64bit |
41ee845b JH |
1563 | mode the difference is less drastic but visible. |
1564 | ||
1565 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1566 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1567 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1568 | |
1569 | With the 64-bit MS ABI, we can generate correct code with or without | |
1570 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1571 | generated without accumulated args is terrible. | |
41ee845b JH |
1572 | |
1573 | If stack probes are required, the space used for large function | |
1574 | arguments on the stack must also be probed, so enable | |
f8071c05 L |
1575 | -maccumulate-outgoing-args so this happens in the prologue. |
1576 | ||
1577 | We must use argument accumulation in interrupt function if stack | |
1578 | may be realigned to avoid DRAP. */ | |
f73ad30e | 1579 | |
6c6094f1 | 1580 | #define ACCUMULATE_OUTGOING_ARGS \ |
f8071c05 L |
1581 | ((TARGET_ACCUMULATE_OUTGOING_ARGS \ |
1582 | && optimize_function_for_speed_p (cfun)) \ | |
1583 | || (cfun->machine->func_type != TYPE_NORMAL \ | |
1584 | && crtl->stack_realign_needed) \ | |
1585 | || TARGET_STACK_PROBE \ | |
1586 | || TARGET_64BIT_MS_ABI \ | |
ff734e26 | 1587 | || (TARGET_MACHO && crtl->profile)) |
f73ad30e JH |
1588 | |
1589 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1590 | instructions to pass outgoing arguments. */ | |
1591 | ||
1592 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1593 | ||
2da4124d L |
1594 | /* We want the stack and args grow in opposite directions, even if |
1595 | PUSH_ARGS is 0. */ | |
1596 | #define PUSH_ARGS_REVERSED 1 | |
1597 | ||
c98f8742 JVA |
1598 | /* Offset of first parameter from the argument pointer register value. */ |
1599 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1600 | ||
a7180f70 BS |
1601 | /* Define this macro if functions should assume that stack space has been |
1602 | allocated for arguments even when their values are passed in registers. | |
1603 | ||
1604 | The value of this macro is the size, in bytes, of the area reserved for | |
1605 | arguments passed in registers for the function represented by FNDECL. | |
1606 | ||
1607 | This space can be allocated by the caller, or be a part of the | |
1608 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1609 | which. */ | |
7c800926 KT |
1610 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1611 | ||
4ae8027b | 1612 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1613 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1614 | |
c98f8742 JVA |
1615 | /* Define how to find the value returned by a library function |
1616 | assuming the value has mode MODE. */ | |
1617 | ||
4ae8027b | 1618 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1619 | |
e9125c09 TW |
1620 | /* Define the size of the result block used for communication between |
1621 | untyped_call and untyped_return. The block contains a DImode value | |
1622 | followed by the block used by fnsave and frstor. */ | |
1623 | ||
1624 | #define APPLY_RESULT_SIZE (8+108) | |
1625 | ||
b08de47e | 1626 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1627 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1628 | |
1629 | /* Define a data type for recording info about an argument list | |
1630 | during the scan of that argument list. This data type should | |
1631 | hold all necessary information about the function itself | |
1632 | and about the args processed so far, enough to enable macros | |
b08de47e | 1633 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1634 | |
e075ae69 | 1635 | typedef struct ix86_args { |
fa283935 | 1636 | int words; /* # words passed so far */ |
b08de47e MM |
1637 | int nregs; /* # registers available for passing */ |
1638 | int regno; /* next available register number */ | |
3e65f251 KT |
1639 | int fastcall; /* fastcall or thiscall calling convention |
1640 | is used */ | |
fa283935 | 1641 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1642 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1643 | int warn_avx512f; /* True when we want to warn |
1644 | about AVX512F ABI. */ | |
95879c72 | 1645 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1646 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 | 1647 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
974aedcc MP |
1648 | int warn_empty; /* True when we want to warn about empty classes |
1649 | passing ABI change. */ | |
fa283935 UB |
1650 | int sse_regno; /* next available sse register number */ |
1651 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1652 | int mmx_nregs; /* # mmx registers available for passing */ |
1653 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1654 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1655 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1656 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1657 | SFmode/DFmode arguments should be passed | |
1658 | in SSE registers. Otherwise 0. */ | |
d5e254e1 | 1659 | int stdarg; /* Set to 1 if function is stdarg. */ |
51212b32 | 1660 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1661 | MS_ABI for ms abi. */ |
e66fc623 | 1662 | tree decl; /* Callee decl. */ |
b08de47e | 1663 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1664 | |
1665 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1666 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1667 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1668 | |
0f6937fe | 1669 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1670 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1671 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1672 | |
c98f8742 JVA |
1673 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1674 | for profiling a function entry. */ | |
1675 | ||
1a6e82b8 UB |
1676 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1677 | x86_function_profiler ((FILE), (LABELNO)) | |
a5fa1ecd JH |
1678 | |
1679 | #define MCOUNT_NAME "_mcount" | |
1680 | ||
3c5273a9 KT |
1681 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1682 | ||
a5fa1ecd | 1683 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1684 | |
1685 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1686 | the stack pointer does not matter. The value is tested only in | |
1687 | functions that have frame pointers. | |
1688 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1689 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1690 | we have to restore it ourselves from the frame pointer, in order to |
1691 | use pop */ | |
1692 | ||
1693 | #define EXIT_IGNORE_STACK 1 | |
1694 | ||
f8071c05 L |
1695 | /* Define this macro as a C expression that is nonzero for registers |
1696 | used by the epilogue or the `return' pattern. */ | |
1697 | ||
1698 | #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) | |
1699 | ||
c98f8742 JVA |
1700 | /* Output assembler code for a block containing the constant parts |
1701 | of a trampoline, leaving space for the variable parts. */ | |
1702 | ||
a269a03c | 1703 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1704 | mov #STATIC,ecx |
a269a03c JC |
1705 | jmp FUNCTION |
1706 | The trampoline is generated entirely at runtime. The operand of JMP | |
1707 | is the address of FUNCTION relative to the instruction following the | |
1708 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1709 | |
1710 | /* Length in units of the trampoline for entering a nested function. */ | |
1711 | ||
6514899f | 1712 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) |
c98f8742 JVA |
1713 | \f |
1714 | /* Definitions for register eliminations. | |
1715 | ||
1716 | This is an array of structures. Each structure initializes one pair | |
1717 | of eliminable registers. The "from" register number is given first, | |
1718 | followed by "to". Eliminations of the same "from" register are listed | |
1719 | in order of preference. | |
1720 | ||
afc2cd05 NC |
1721 | There are two registers that can always be eliminated on the i386. |
1722 | The frame pointer and the arg pointer can be replaced by either the | |
1723 | hard frame pointer or to the stack pointer, depending upon the | |
1724 | circumstances. The hard frame pointer is not used before reload and | |
1725 | so it is not eligible for elimination. */ | |
c98f8742 | 1726 | |
564d80f4 JH |
1727 | #define ELIMINABLE_REGS \ |
1728 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1729 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1730 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1731 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1732 | |
c98f8742 JVA |
1733 | /* Define the offset between two registers, one to be eliminated, and the other |
1734 | its replacement, at the start of a routine. */ | |
1735 | ||
d9a5f180 GS |
1736 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1737 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1738 | \f |
1739 | /* Addressing modes, and classification of registers for them. */ | |
1740 | ||
c98f8742 JVA |
1741 | /* Macros to check register numbers against specific register classes. */ |
1742 | ||
1743 | /* These assume that REGNO is a hard or pseudo reg number. | |
1744 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1745 | or a pseudo reg currently allocated to a suitable hard reg. | |
1746 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1747 | has been allocated, which happens in reginfo.c during register |
1748 | allocation. */ | |
c98f8742 | 1749 | |
3f3f2124 JH |
1750 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1751 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1752 | || REX_INT_REGNO_P (REGNO) \ |
1753 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1754 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1755 | |
3f3f2124 | 1756 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1757 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1758 | || (REGNO) == ARG_POINTER_REGNUM \ |
1759 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1760 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1761 | |
c98f8742 JVA |
1762 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1763 | and check its validity for a certain class. | |
1764 | We have two alternate definitions for each of them. | |
1765 | The usual definition accepts all pseudo regs; the other rejects | |
1766 | them unless they have been allocated suitable hard regs. | |
1767 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1768 | ||
1769 | Most source files want to accept pseudo regs in the hope that | |
1770 | they will get allocated to the class that the insn wants them to be in. | |
1771 | Source files for reload pass need to be strict. | |
1772 | After reload, it makes no difference, since pseudo regs have | |
1773 | been eliminated by then. */ | |
1774 | ||
c98f8742 | 1775 | |
ff482c8d | 1776 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1777 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1778 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1779 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1780 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1781 | ||
3b3c6a3f | 1782 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1783 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1784 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1785 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1786 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1787 | |
3b3c6a3f MM |
1788 | /* Strict versions, hard registers only */ |
1789 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1790 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1791 | |
3b3c6a3f | 1792 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1793 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1794 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1795 | |
1796 | #else | |
d9a5f180 GS |
1797 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1798 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1799 | #endif |
1800 | ||
331d9186 | 1801 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1802 | that is a valid memory address for an instruction. |
1803 | The MODE argument is the machine mode for the MEM expression | |
1804 | that wants to use this address. | |
1805 | ||
331d9186 | 1806 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1807 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1808 | ||
1809 | See legitimize_pic_address in i386.c for details as to what | |
1810 | constitutes a legitimate address when -fpic is used. */ | |
1811 | ||
1812 | #define MAX_REGS_PER_ADDRESS 2 | |
1813 | ||
f996902d | 1814 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1815 | |
b949ea8b JW |
1816 | /* If defined, a C expression to determine the base term of address X. |
1817 | This macro is used in only one place: `find_base_term' in alias.c. | |
1818 | ||
1819 | It is always safe for this macro to not be defined. It exists so | |
1820 | that alias analysis can understand machine-dependent addresses. | |
1821 | ||
1822 | The typical use of this macro is to handle addresses containing | |
1823 | a label_ref or symbol_ref within an UNSPEC. */ | |
1824 | ||
d9a5f180 | 1825 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1826 | |
c98f8742 | 1827 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1828 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1829 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1830 | ||
f996902d | 1831 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1832 | |
1833 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1834 | (GET_CODE (X) == SYMBOL_REF \ |
1835 | || GET_CODE (X) == LABEL_REF \ | |
1836 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1837 | \f |
b08de47e MM |
1838 | /* Max number of args passed in registers. If this is more than 3, we will |
1839 | have problems with ebx (register #4), since it is a caller save register and | |
1840 | is also used as the pic register in ELF. So for now, don't allow more than | |
1841 | 3 registers to be passed in registers. */ | |
1842 | ||
7c800926 KT |
1843 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1844 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1845 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1846 | |
72fa3605 | 1847 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1848 | |
4ae8027b | 1849 | #define REGPARM_MAX \ |
2824d6e5 UB |
1850 | (TARGET_64BIT \ |
1851 | ? (TARGET_64BIT_MS_ABI \ | |
1852 | ? X86_64_MS_REGPARM_MAX \ | |
1853 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1854 | : X86_32_REGPARM_MAX) |
d2836273 | 1855 | |
72fa3605 UB |
1856 | #define X86_64_SSE_REGPARM_MAX 8 |
1857 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1858 | ||
b6010cab | 1859 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1860 | |
4ae8027b | 1861 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1862 | (TARGET_64BIT \ |
1863 | ? (TARGET_64BIT_MS_ABI \ | |
1864 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1865 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1866 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 JH |
1867 | |
1868 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
c98f8742 JVA |
1869 | \f |
1870 | /* Specify the machine mode that this machine uses | |
1871 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1872 | #define CASE_VECTOR_MODE \ |
6025b127 | 1873 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1874 | |
c98f8742 JVA |
1875 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1876 | #define DEFAULT_SIGNED_CHAR 1 | |
1877 | ||
1878 | /* Max number of bytes we can move from memory to memory | |
1879 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1880 | #define MOVE_MAX 16 |
1881 | ||
1882 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1883 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
df7ec09f L |
1884 | number of bytes we can move with a single instruction. |
1885 | ||
1886 | ??? We should use TImode in 32-bit mode and use OImode or XImode | |
1887 | if they are available. But since by_pieces_ninsns determines the | |
1888 | widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in | |
1889 | 64-bit mode. */ | |
1890 | #define MOVE_MAX_PIECES \ | |
1891 | ((TARGET_64BIT \ | |
1892 | && TARGET_SSE2 \ | |
1893 | && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ | |
1894 | && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ | |
1895 | ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) | |
c98f8742 | 1896 | |
7e24ffc9 | 1897 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1898 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1899 | Increasing the value will always make code faster, but eventually |
1900 | incurs high cost in increased code size. | |
c98f8742 | 1901 | |
e2e52e1b | 1902 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1903 | |
e04ad03d | 1904 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1905 | |
45d78e7f JJ |
1906 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1907 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1908 | ||
e04ad03d | 1909 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1910 | |
53f00dde UB |
1911 | /* Define if shifts truncate the shift count which implies one can |
1912 | omit a sign-extension or zero-extension of a shift count. | |
1913 | ||
1914 | On i386, shifts do truncate the count. But bit test instructions | |
1915 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1916 | |
1917 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1918 | ||
d9f32422 JH |
1919 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1920 | TYPE and which has the specified mode and signedness is to be | |
1921 | stored in a register. This macro is only called when TYPE is a | |
1922 | scalar type. | |
1923 | ||
f710504c | 1924 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1925 | quantities to SImode. The choice depends on target type. */ |
1926 | ||
1927 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1928 | do { \ |
d9f32422 JH |
1929 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1930 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1931 | (MODE) = SImode; \ |
1932 | } while (0) | |
d9f32422 | 1933 | |
c98f8742 JVA |
1934 | /* Specify the machine mode that pointers have. |
1935 | After generation of rtl, the compiler makes no further distinction | |
1936 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1937 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1938 | |
5e1e91c4 L |
1939 | /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. |
1940 | NONLOCAL needs space to save both shadow stack and stack pointers. | |
1941 | ||
1942 | FIXME: We only need to save and restore stack pointer in ptr_mode. | |
1943 | But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode | |
1944 | to save and restore stack pointer. See | |
1945 | https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 | |
1946 | */ | |
1947 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
1948 | ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) | |
1949 | ||
f0ea7581 L |
1950 | /* A C expression whose value is zero if pointers that need to be extended |
1951 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1952 | greater then zero if they are zero-extended and less then zero if the | |
1953 | ptr_extend instruction should be used. */ | |
1954 | ||
1955 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1956 | ||
c98f8742 JVA |
1957 | /* A function address in a call instruction |
1958 | is a byte address (for indexing purposes) | |
1959 | so give the MEM rtx a byte's mode. */ | |
1960 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1961 | \f |
d4ba09c0 | 1962 | |
d4ba09c0 SC |
1963 | /* A C expression for the cost of a branch instruction. A value of 1 |
1964 | is the default; other values are interpreted relative to that. */ | |
1965 | ||
3a4fd356 JH |
1966 | #define BRANCH_COST(speed_p, predictable_p) \ |
1967 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1968 | |
e327d1a3 L |
1969 | /* An integer expression for the size in bits of the largest integer machine |
1970 | mode that should actually be used. We allow pairs of registers. */ | |
1971 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1972 | ||
d4ba09c0 SC |
1973 | /* Define this macro as a C expression which is nonzero if accessing |
1974 | less than a word of memory (i.e. a `char' or a `short') is no | |
1975 | faster than accessing a word of memory, i.e., if such access | |
1976 | require more than one instruction or if there is no difference in | |
1977 | cost between byte and (aligned) word loads. | |
1978 | ||
1979 | When this macro is not defined, the compiler will access a field by | |
1980 | finding the smallest containing object; when it is defined, a | |
1981 | fullword load will be used if alignment permits. Unless bytes | |
1982 | accesses are faster than word accesses, using word accesses is | |
1983 | preferable since it may eliminate subsequent memory access if | |
1984 | subsequent accesses occur to other fields in the same word of the | |
1985 | structure, but to different bytes. */ | |
1986 | ||
1987 | #define SLOW_BYTE_ACCESS 0 | |
1988 | ||
1989 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1990 | #define SLOW_SHORT_ACCESS 0 | |
1991 | ||
d4ba09c0 SC |
1992 | /* Define this macro if it is as good or better to call a constant |
1993 | function address than to call an address kept in a register. | |
1994 | ||
1995 | Desirable on the 386 because a CALL with a constant address is | |
1996 | faster than one with a register address. */ | |
1997 | ||
1e8552c2 | 1998 | #define NO_FUNCTION_CSE 1 |
c98f8742 | 1999 | \f |
c572e5ba JVA |
2000 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2001 | return the mode to be used for the comparison. | |
2002 | ||
2003 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2004 | VOIDmode should be used in all other cases. |
c572e5ba | 2005 | |
16189740 | 2006 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2007 | possible, to allow for more combinations. */ |
c98f8742 | 2008 | |
d9a5f180 | 2009 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2010 | |
9cd10576 | 2011 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2012 | reversed. */ |
2013 | ||
2014 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2015 | ||
2016 | /* A C expression whose value is reversed condition code of the CODE for | |
2017 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2018 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2019 | |
c98f8742 JVA |
2020 | \f |
2021 | /* Control the assembler format that we output, to the extent | |
2022 | this does not vary between assemblers. */ | |
2023 | ||
2024 | /* How to refer to registers in assembler output. | |
892a2d68 | 2025 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2026 | |
a7b376ee | 2027 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2028 | For non floating point regs, the following are the HImode names. |
2029 | ||
2030 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
2031 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
2032 | "y" code. */ | |
c98f8742 | 2033 | |
a7180f70 BS |
2034 | #define HI_REGISTER_NAMES \ |
2035 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2036 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
eaa17c21 | 2037 | "argp", "flags", "fpsr", "frame", \ |
a7180f70 | 2038 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2039 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 2040 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
2041 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
2042 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
2043 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
2044 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 2045 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
eafa30ef | 2046 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } |
a7180f70 | 2047 | |
c98f8742 JVA |
2048 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2049 | ||
50bec228 UB |
2050 | #define QI_REGISTER_NAMES \ |
2051 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"} | |
2052 | ||
2053 | #define QI_HIGH_REGISTER_NAMES \ | |
2054 | {"ah", "dh", "ch", "bh"} | |
2055 | ||
c98f8742 JVA |
2056 | /* Table of additional register names to use in user input. */ |
2057 | ||
eaa17c21 UB |
2058 | #define ADDITIONAL_REGISTER_NAMES \ |
2059 | { \ | |
2060 | { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \ | |
2061 | { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \ | |
2062 | { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \ | |
2063 | { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \ | |
2064 | { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \ | |
50bec228 | 2065 | { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \ |
eaa17c21 UB |
2066 | { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \ |
2067 | { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \ | |
2068 | { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \ | |
2069 | { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \ | |
2070 | { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \ | |
2071 | { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \ | |
2072 | { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \ | |
2073 | { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \ | |
2074 | { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \ | |
2075 | { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \ | |
2076 | { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \ | |
2077 | { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \ | |
2078 | { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \ | |
2079 | { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \ | |
2080 | { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \ | |
2081 | { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \ | |
2082 | { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \ | |
2083 | } | |
c98f8742 | 2084 | |
c98f8742 JVA |
2085 | /* How to renumber registers for dbx and gdb. */ |
2086 | ||
d9a5f180 GS |
2087 | #define DBX_REGISTER_NUMBER(N) \ |
2088 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2089 | |
9a82e702 MS |
2090 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2091 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2092 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2093 | |
469ac993 JM |
2094 | /* Before the prologue, RA is at 0(%esp). */ |
2095 | #define INCOMING_RETURN_ADDR_RTX \ | |
2efb4214 | 2096 | gen_rtx_MEM (Pmode, stack_pointer_rtx) |
fce5a9f2 | 2097 | |
e414ab29 | 2098 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1a6e82b8 UB |
2099 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2100 | ((COUNT) == 0 \ | |
2101 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ | |
2102 | -UNITS_PER_WORD)) \ | |
2103 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) | |
e414ab29 | 2104 | |
892a2d68 | 2105 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2106 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2107 | |
a10b3cf1 L |
2108 | /* Before the prologue, there are return address and error code for |
2109 | exception handler on the top of the frame. */ | |
2110 | #define INCOMING_FRAME_SP_OFFSET \ | |
2111 | (cfun->machine->func_type == TYPE_EXCEPTION \ | |
2112 | ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) | |
a6ab3aad | 2113 | |
26fc730d JJ |
2114 | /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in |
2115 | .cfi_startproc. */ | |
2116 | #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD | |
2117 | ||
1020a5ab | 2118 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2119 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2120 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2121 | |
ad919812 | 2122 | |
e4c4ebeb RH |
2123 | /* Select a format to encode pointers in exception handling data. CODE |
2124 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2125 | true if the symbol may be affected by dynamic relocations. | |
2126 | ||
2127 | ??? All x86 object file formats are capable of representing this. | |
2128 | After all, the relocation needed is the same as for the call insn. | |
2129 | Whether or not a particular assembler allows us to enter such, I | |
2130 | guess we'll have to see. */ | |
d9a5f180 | 2131 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2132 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2133 | |
ec1895c1 UB |
2134 | /* These are a couple of extensions to the formats accepted |
2135 | by asm_fprintf: | |
2136 | %z prints out opcode suffix for word-mode instruction | |
2137 | %r prints out word-mode name for reg_names[arg] */ | |
2138 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
2139 | case 'z': \ | |
2140 | fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ | |
2141 | break; \ | |
2142 | \ | |
2143 | case 'r': \ | |
2144 | { \ | |
2145 | unsigned int regno = va_arg ((ARGS), int); \ | |
2146 | if (LEGACY_INT_REGNO_P (regno)) \ | |
2147 | fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ | |
2148 | fputs (reg_names[regno], (FILE)); \ | |
2149 | break; \ | |
2150 | } | |
2151 | ||
2152 | /* This is how to output an insn to push a register on the stack. */ | |
2153 | ||
2154 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
2155 | asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) | |
2156 | ||
2157 | /* This is how to output an insn to pop a register from the stack. */ | |
c98f8742 | 2158 | |
d9a5f180 | 2159 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
ec1895c1 | 2160 | asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) |
c98f8742 | 2161 | |
f88c65f7 | 2162 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2163 | |
2164 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2165 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2166 | |
f88c65f7 | 2167 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2168 | |
33f7f353 | 2169 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2170 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2171 | |
63001560 | 2172 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2173 | |
2174 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2175 | { \ | |
2176 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2177 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2178 | } |
2179 | ||
2180 | /* A C statement or statements which output an assembler instruction | |
2181 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2182 | variable of type `char *' which points to the opcode name in | |
2183 | its "internal" form--the form that is written in the machine | |
2184 | description. */ | |
2185 | ||
2186 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2187 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2188 | ||
6a90d232 L |
2189 | /* A C statement to output to the stdio stream FILE an assembler |
2190 | command to pad the location counter to a multiple of 1<<LOG | |
2191 | bytes if it is within MAX_SKIP bytes. */ | |
2192 | ||
2193 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
2194 | #undef ASM_OUTPUT_MAX_SKIP_PAD | |
2195 | #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ | |
2196 | if ((LOG) != 0) \ | |
2197 | { \ | |
dd047c67 | 2198 | if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \ |
6a90d232 L |
2199 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ |
2200 | else \ | |
2201 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ | |
2202 | } | |
2203 | #endif | |
2204 | ||
135a687e KT |
2205 | /* Write the extra assembler code needed to declare a function |
2206 | properly. */ | |
2207 | ||
2208 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2209 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
1a6e82b8 | 2210 | ix86_asm_output_function_label ((FILE), (NAME), (DECL)) |
135a687e | 2211 | |
f7288899 EC |
2212 | /* Under some conditions we need jump tables in the text section, |
2213 | because the assembler cannot handle label differences between | |
2214 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2215 | |
2216 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2217 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2218 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2219 | |
cea3bd3e RH |
2220 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2221 | and switch back. For x86 we do this only to save a few bytes that | |
2222 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2223 | #define CRT_MKSTR2(VAL) #VAL |
2224 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2225 | ||
2226 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2227 | asm (SECTION_OP "\n\t" \ | |
2228 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2229 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2230 | |
2231 | /* Default threshold for putting data in large sections | |
2232 | with x86-64 medium memory model */ | |
2233 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
74b42c8b | 2234 | \f |
b97de419 L |
2235 | /* Which processor to tune code generation for. These must be in sync |
2236 | with processor_target_table in i386.c. */ | |
5bf0ebab RH |
2237 | |
2238 | enum processor_type | |
2239 | { | |
b97de419 L |
2240 | PROCESSOR_GENERIC = 0, |
2241 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2242 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2243 | PROCESSOR_PENTIUM, | |
2d6b2e28 | 2244 | PROCESSOR_LAKEMONT, |
5bf0ebab | 2245 | PROCESSOR_PENTIUMPRO, |
5bf0ebab | 2246 | PROCESSOR_PENTIUM4, |
89c43c0a | 2247 | PROCESSOR_NOCONA, |
340ef734 | 2248 | PROCESSOR_CORE2, |
d3c11974 L |
2249 | PROCESSOR_NEHALEM, |
2250 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2251 | PROCESSOR_HASWELL, |
d3c11974 L |
2252 | PROCESSOR_BONNELL, |
2253 | PROCESSOR_SILVERMONT, | |
50e461df | 2254 | PROCESSOR_GOLDMONT, |
74b2bb19 | 2255 | PROCESSOR_GOLDMONT_PLUS, |
a548a5a1 | 2256 | PROCESSOR_TREMONT, |
52747219 | 2257 | PROCESSOR_KNL, |
cace2309 | 2258 | PROCESSOR_KNM, |
176a3386 | 2259 | PROCESSOR_SKYLAKE, |
06caf59d | 2260 | PROCESSOR_SKYLAKE_AVX512, |
c234d831 | 2261 | PROCESSOR_CANNONLAKE, |
79ab5364 JK |
2262 | PROCESSOR_ICELAKE_CLIENT, |
2263 | PROCESSOR_ICELAKE_SERVER, | |
7cab07f0 | 2264 | PROCESSOR_CASCADELAKE, |
9a7f94d7 | 2265 | PROCESSOR_INTEL, |
b97de419 L |
2266 | PROCESSOR_GEODE, |
2267 | PROCESSOR_K6, | |
2268 | PROCESSOR_ATHLON, | |
2269 | PROCESSOR_K8, | |
21efb4d4 | 2270 | PROCESSOR_AMDFAM10, |
1133125e | 2271 | PROCESSOR_BDVER1, |
4d652a18 | 2272 | PROCESSOR_BDVER2, |
eb2f2b44 | 2273 | PROCESSOR_BDVER3, |
ed97ad47 | 2274 | PROCESSOR_BDVER4, |
14b52538 | 2275 | PROCESSOR_BTVER1, |
e32bfc16 | 2276 | PROCESSOR_BTVER2, |
9ce29eb0 | 2277 | PROCESSOR_ZNVER1, |
2901f42f | 2278 | PROCESSOR_ZNVER2, |
5bf0ebab RH |
2279 | PROCESSOR_max |
2280 | }; | |
2281 | ||
c98c2430 | 2282 | #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) |
2559ef9f | 2283 | extern const char *const processor_names[]; |
c98c2430 ML |
2284 | |
2285 | #include "wide-int-bitmask.h" | |
2286 | ||
2287 | const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0); | |
2288 | const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1); | |
2289 | const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2); | |
2290 | const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3); | |
2291 | const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4); | |
2292 | const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5); | |
2293 | const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6); | |
2294 | const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7); | |
2295 | const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8); | |
2296 | const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9); | |
2297 | const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10); | |
2298 | const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11); | |
2299 | const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12); | |
2300 | const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13); | |
2301 | const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14); | |
2302 | const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15); | |
2303 | const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16); | |
2304 | const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17); | |
2305 | const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18); | |
2306 | const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19); | |
2307 | const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20); | |
2308 | const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21); | |
2309 | const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22); | |
2310 | const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23); | |
2311 | const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24); | |
2312 | const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25); | |
2313 | const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26); | |
2314 | const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27); | |
2315 | const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28); | |
2316 | const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29); | |
2317 | const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30); | |
2318 | const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31); | |
2319 | const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32); | |
2320 | const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33); | |
2321 | const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34); | |
2322 | const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35); | |
2323 | const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36); | |
2324 | const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37); | |
2325 | const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38); | |
2326 | const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39); | |
2327 | const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40); | |
2328 | const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41); | |
2329 | const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42); | |
2330 | const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43); | |
2331 | /* Hole after PTA_MPX was removed. */ | |
2332 | const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45); | |
2333 | const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46); | |
2334 | const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47); | |
2335 | const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48); | |
2336 | const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49); | |
2337 | const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50); | |
2338 | const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51); | |
2339 | const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52); | |
2340 | const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53); | |
2341 | const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54); | |
2342 | const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55); | |
2343 | const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56); | |
2344 | const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57); | |
2345 | const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58); | |
2346 | const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59); | |
2347 | const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60); | |
2348 | const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61); | |
2349 | const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62); | |
2350 | const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63); | |
2351 | const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U); | |
2352 | const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1); | |
2353 | const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2); | |
2354 | const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3); | |
2355 | const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4); | |
2356 | const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5); | |
2357 | const wide_int_bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6); | |
2358 | const wide_int_bitmask PTA_PCONFIG (0, HOST_WIDE_INT_1U << 7); | |
2359 | const wide_int_bitmask PTA_WBNOINVD (0, HOST_WIDE_INT_1U << 8); | |
2360 | const wide_int_bitmask PTA_WAITPKG (0, HOST_WIDE_INT_1U << 9); | |
41f8d1fc | 2361 | const wide_int_bitmask PTA_PTWRITE (0, HOST_WIDE_INT_1U << 10); |
4f0e90fa | 2362 | const wide_int_bitmask PTA_AVX512BF16 (0, HOST_WIDE_INT_1U << 11); |
c98c2430 ML |
2363 | |
2364 | const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | |
2365 | | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; | |
2366 | const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | |
2367 | | PTA_POPCNT; | |
c9450033 | 2368 | const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; |
c98c2430 ML |
2369 | const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE |
2370 | | PTA_XSAVEOPT; | |
2371 | const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | |
2372 | | PTA_RDRND | PTA_F16C; | |
2373 | const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | |
2374 | | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; | |
2375 | const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW | |
2376 | | PTA_RDSEED; | |
c9450033 | 2377 | const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT |
c98c2430 ML |
2378 | | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; |
2379 | const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | |
2380 | | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | |
2381 | | PTA_CLWB; | |
7cab07f0 | 2382 | const wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VNNI; |
c98c2430 ML |
2383 | const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F |
2384 | | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | |
2385 | | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; | |
2386 | const wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | |
2387 | | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | |
2388 | | PTA_RDPID | PTA_CLWB; | |
2389 | const wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT | PTA_PCONFIG | |
2390 | | PTA_WBNOINVD; | |
2391 | const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | |
2392 | | PTA_AVX512F | PTA_AVX512CD; | |
2393 | const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; | |
2394 | const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND; | |
c9450033 | 2395 | const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE |
c98c2430 ML |
2396 | | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT |
2397 | | PTA_FSGSBASE; | |
2398 | const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID | |
41f8d1fc | 2399 | | PTA_SGX | PTA_PTWRITE; |
c98c2430 ML |
2400 | const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB |
2401 | | PTA_GFNI; | |
2402 | const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | |
2403 | | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; | |
2404 | ||
2405 | #ifndef GENERATOR_FILE | |
2406 | ||
2407 | #include "insn-attr-common.h" | |
2408 | ||
2409 | struct pta | |
2410 | { | |
2411 | const char *const name; /* processor name or nickname. */ | |
2412 | const enum processor_type processor; | |
2413 | const enum attr_cpu schedule; | |
2414 | const wide_int_bitmask flags; | |
2415 | }; | |
2416 | ||
2417 | extern const pta processor_alias_table[]; | |
2418 | extern int const pta_size; | |
2419 | #endif | |
2420 | ||
2421 | #endif | |
2422 | ||
9e555526 | 2423 | extern enum processor_type ix86_tune; |
5bf0ebab | 2424 | extern enum processor_type ix86_arch; |
5bf0ebab | 2425 | |
8362f420 JH |
2426 | /* Size of the RED_ZONE area. */ |
2427 | #define RED_ZONE_SIZE 128 | |
2428 | /* Reserved area of the red zone for temporaries. */ | |
2429 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2430 | |
95899b34 | 2431 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2432 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2433 | |
2434 | /* Smallest class containing REGNO. */ | |
2435 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2436 | ||
0948ccb2 PB |
2437 | enum ix86_fpcmp_strategy { |
2438 | IX86_FPCMP_SAHF, | |
2439 | IX86_FPCMP_COMI, | |
2440 | IX86_FPCMP_ARITH | |
2441 | }; | |
22fb740d JH |
2442 | \f |
2443 | /* To properly truncate FP values into integers, we need to set i387 control | |
2444 | word. We can't emit proper mode switching code before reload, as spills | |
2445 | generated by reload may truncate values incorrectly, but we still can avoid | |
2446 | redundant computation of new control word by the mode switching pass. | |
2447 | The fldcw instructions are still emitted redundantly, but this is probably | |
2448 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2449 | the sequence. |
22fb740d JH |
2450 | |
2451 | The machinery is to emit simple truncation instructions and split them | |
2452 | before reload to instructions having USEs of two memory locations that | |
2453 | are filled by this code to old and new control word. | |
fce5a9f2 | 2454 | |
22fb740d JH |
2455 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2456 | needed. */ | |
2457 | ||
c7ca8ef8 UB |
2458 | enum ix86_stack_slot |
2459 | { | |
2460 | SLOT_TEMP = 0, | |
2461 | SLOT_CW_STORED, | |
2462 | SLOT_CW_TRUNC, | |
2463 | SLOT_CW_FLOOR, | |
2464 | SLOT_CW_CEIL, | |
80008279 | 2465 | SLOT_STV_TEMP, |
c7ca8ef8 UB |
2466 | MAX_386_STACK_LOCALS |
2467 | }; | |
2468 | ||
ff680eb1 UB |
2469 | enum ix86_entity |
2470 | { | |
c7ca8ef8 UB |
2471 | X86_DIRFLAG = 0, |
2472 | AVX_U128, | |
ff97910d | 2473 | I387_TRUNC, |
ff680eb1 UB |
2474 | I387_FLOOR, |
2475 | I387_CEIL, | |
ff680eb1 UB |
2476 | MAX_386_ENTITIES |
2477 | }; | |
2478 | ||
c7ca8ef8 | 2479 | enum x86_dirflag_state |
ff680eb1 | 2480 | { |
c7ca8ef8 UB |
2481 | X86_DIRFLAG_RESET, |
2482 | X86_DIRFLAG_ANY | |
ff680eb1 | 2483 | }; |
22fb740d | 2484 | |
ff97910d VY |
2485 | enum avx_u128_state |
2486 | { | |
2487 | AVX_U128_CLEAN, | |
2488 | AVX_U128_DIRTY, | |
2489 | AVX_U128_ANY | |
2490 | }; | |
2491 | ||
22fb740d JH |
2492 | /* Define this macro if the port needs extra instructions inserted |
2493 | for mode switching in an optimizing compilation. */ | |
2494 | ||
ff680eb1 UB |
2495 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2496 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2497 | |
2498 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2499 | initializer for an array of integers. Each initializer element N | |
2500 | refers to an entity that needs mode switching, and specifies the | |
2501 | number of different modes that might need to be set for this | |
2502 | entity. The position of the initializer in the initializer - | |
2503 | starting counting at zero - determines the integer that is used to | |
2504 | refer to the mode-switched entity in question. */ | |
2505 | ||
c7ca8ef8 UB |
2506 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2507 | { X86_DIRFLAG_ANY, AVX_U128_ANY, \ | |
8c097065 | 2508 | I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
22fb740d | 2509 | |
0f0138b6 JH |
2510 | \f |
2511 | /* Avoid renaming of stack registers, as doing so in combination with | |
2512 | scheduling just increases amount of live registers at time and in | |
2513 | the turn amount of fxch instructions needed. | |
2514 | ||
3f97cb0b AI |
2515 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2516 | ||
2517 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2518 | |
1a6e82b8 UB |
2519 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
2520 | (!STACK_REGNO_P (SRC) \ | |
2521 | && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) | |
22fb740d | 2522 | |
3b3c6a3f | 2523 | \f |
e91f04de | 2524 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2525 | \f |
77560086 BE |
2526 | #ifndef USED_FOR_TARGET |
2527 | /* Structure describing stack frame layout. | |
2528 | Stack grows downward: | |
2529 | ||
2530 | [arguments] | |
2531 | <- ARG_POINTER | |
2532 | saved pc | |
2533 | ||
2534 | saved static chain if ix86_static_chain_on_stack | |
2535 | ||
2536 | saved frame pointer if frame_pointer_needed | |
2537 | <- HARD_FRAME_POINTER | |
2538 | [saved regs] | |
2539 | <- reg_save_offset | |
2540 | [padding0] | |
2541 | <- stack_realign_offset | |
2542 | [saved SSE regs] | |
2543 | OR | |
2544 | [stub-saved registers for ms x64 --> sysv clobbers | |
2545 | <- Start of out-of-line, stub-saved/restored regs | |
2546 | (see libgcc/config/i386/(sav|res)ms64*.S) | |
2547 | [XMM6-15] | |
2548 | [RSI] | |
2549 | [RDI] | |
2550 | [?RBX] only if RBX is clobbered | |
2551 | [?RBP] only if RBP and RBX are clobbered | |
2552 | [?R12] only if R12 and all previous regs are clobbered | |
2553 | [?R13] only if R13 and all previous regs are clobbered | |
2554 | [?R14] only if R14 and all previous regs are clobbered | |
2555 | [?R15] only if R15 and all previous regs are clobbered | |
2556 | <- end of stub-saved/restored regs | |
2557 | [padding1] | |
2558 | ] | |
5d9d834d | 2559 | <- sse_reg_save_offset |
77560086 BE |
2560 | [padding2] |
2561 | | <- FRAME_POINTER | |
2562 | [va_arg registers] | | |
2563 | | | |
2564 | [frame] | | |
2565 | | | |
2566 | [padding2] | = to_allocate | |
2567 | <- STACK_POINTER | |
2568 | */ | |
2569 | struct GTY(()) ix86_frame | |
2570 | { | |
2571 | int nsseregs; | |
2572 | int nregs; | |
2573 | int va_arg_size; | |
2574 | int red_zone_size; | |
2575 | int outgoing_arguments_size; | |
2576 | ||
2577 | /* The offsets relative to ARG_POINTER. */ | |
2578 | HOST_WIDE_INT frame_pointer_offset; | |
2579 | HOST_WIDE_INT hard_frame_pointer_offset; | |
2580 | HOST_WIDE_INT stack_pointer_offset; | |
2581 | HOST_WIDE_INT hfp_save_offset; | |
2582 | HOST_WIDE_INT reg_save_offset; | |
122f9da1 | 2583 | HOST_WIDE_INT stack_realign_allocate; |
77560086 | 2584 | HOST_WIDE_INT stack_realign_offset; |
77560086 BE |
2585 | HOST_WIDE_INT sse_reg_save_offset; |
2586 | ||
2587 | /* When save_regs_using_mov is set, emit prologue using | |
2588 | move instead of push instructions. */ | |
2589 | bool save_regs_using_mov; | |
2590 | }; | |
2591 | ||
122f9da1 DS |
2592 | /* Machine specific frame tracking during prologue/epilogue generation. All |
2593 | values are positive, but since the x86 stack grows downward, are subtratced | |
2594 | from the CFA to produce a valid address. */ | |
cd9c1ca8 | 2595 | |
ec7ded37 | 2596 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2597 | { |
ec7ded37 RH |
2598 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2599 | is drap_reg, we don't bother trying to record here the real CFA when | |
2600 | it might really be a DW_CFA_def_cfa_expression. */ | |
2601 | rtx cfa_reg; | |
2602 | HOST_WIDE_INT cfa_offset; | |
2603 | ||
2604 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2605 | When stack frame re-alignment is active, these may not be relative | |
2606 | to the CFA. However, in all cases they are relative to the offsets | |
2607 | of the saved registers stored in ix86_frame. */ | |
2608 | HOST_WIDE_INT sp_offset; | |
2609 | HOST_WIDE_INT fp_offset; | |
2610 | ||
2611 | /* The size of the red-zone that may be assumed for the purposes of | |
2612 | eliding register restore notes in the epilogue. This may be zero | |
2613 | if no red-zone is in effect, or may be reduced from the real | |
2614 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2615 | int red_zone_offset; | |
2616 | ||
2617 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2618 | value within the frame. If false then the offset above should be | |
2619 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2620 | thus has an offset of zero. */ | |
2621 | BOOL_BITFIELD sp_valid : 1; | |
2622 | BOOL_BITFIELD fp_valid : 1; | |
2623 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2624 | |
2625 | /* Indicate whether the local stack frame has been re-aligned. When | |
2626 | set, the SP/FP offsets above are relative to the aligned frame | |
2627 | and not the CFA. */ | |
2628 | BOOL_BITFIELD realigned : 1; | |
d6d4d770 DS |
2629 | |
2630 | /* Indicates whether the stack pointer has been re-aligned. When set, | |
2631 | SP/FP continue to be relative to the CFA, but the stack pointer | |
122f9da1 DS |
2632 | should only be used for offsets > sp_realigned_offset, while |
2633 | the frame pointer should be used for offsets <= sp_realigned_fp_last. | |
d6d4d770 DS |
2634 | The flags realigned and sp_realigned are mutually exclusive. */ |
2635 | BOOL_BITFIELD sp_realigned : 1; | |
2636 | ||
122f9da1 DS |
2637 | /* If sp_realigned is set, this is the last valid offset from the CFA |
2638 | that can be used for access with the frame pointer. */ | |
2639 | HOST_WIDE_INT sp_realigned_fp_last; | |
2640 | ||
2641 | /* If sp_realigned is set, this is the offset from the CFA that the stack | |
2642 | pointer was realigned, and may or may not be equal to sp_realigned_fp_last. | |
2643 | Access via the stack pointer is only valid for offsets that are greater than | |
2644 | this value. */ | |
d6d4d770 | 2645 | HOST_WIDE_INT sp_realigned_offset; |
cd9c1ca8 RH |
2646 | }; |
2647 | ||
f81c9774 RH |
2648 | /* Private to winnt.c. */ |
2649 | struct seh_frame_state; | |
2650 | ||
f8071c05 L |
2651 | enum function_type |
2652 | { | |
2653 | TYPE_UNKNOWN = 0, | |
2654 | TYPE_NORMAL, | |
2655 | /* The current function is an interrupt service routine with a | |
2656 | pointer argument as specified by the "interrupt" attribute. */ | |
2657 | TYPE_INTERRUPT, | |
2658 | /* The current function is an interrupt service routine with a | |
2659 | pointer argument and an integer argument as specified by the | |
2660 | "interrupt" attribute. */ | |
2661 | TYPE_EXCEPTION | |
2662 | }; | |
2663 | ||
d1b38208 | 2664 | struct GTY(()) machine_function { |
fa1a0d02 | 2665 | struct stack_local_entry *stack_locals; |
4aab97f9 L |
2666 | int varargs_gpr_size; |
2667 | int varargs_fpr_size; | |
ff680eb1 | 2668 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b | 2669 | |
77560086 BE |
2670 | /* Cached initial frame layout for the current function. */ |
2671 | struct ix86_frame frame; | |
3452586b | 2672 | |
7458026b ILT |
2673 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2674 | the stack arguments for a function with a variable number of | |
2675 | arguments. This is set at the start of the function and is used | |
2676 | to initialize the overflow_arg_area field of the va_list | |
2677 | structure. */ | |
2678 | rtx split_stack_varargs_pointer; | |
2679 | ||
3452586b RH |
2680 | /* This value is used for amd64 targets and specifies the current abi |
2681 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2682 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2683 | |
2684 | /* Nonzero if the function accesses a previous frame. */ | |
2685 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2686 | ||
922e3e33 UB |
2687 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2688 | expander to determine the style used. */ | |
3452586b RH |
2689 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2690 | ||
1e4490dc UB |
2691 | /* Nonzero if the current function calls pc thunk and |
2692 | must not use the red zone. */ | |
2693 | BOOL_BITFIELD pc_thunk_call_expanded : 1; | |
2694 | ||
5bf5a10b AO |
2695 | /* If true, the current function needs the default PIC register, not |
2696 | an alternate register (on x86) and must not use the red zone (on | |
2697 | x86_64), even if it's a leaf function. We don't want the | |
2698 | function to be regarded as non-leaf because TLS calls need not | |
2699 | affect register allocation. This flag is set when a TLS call | |
2700 | instruction is expanded within a function, and never reset, even | |
2701 | if all such instructions are optimized away. Use the | |
2702 | ix86_current_function_calls_tls_descriptor macro for a better | |
2703 | approximation. */ | |
3452586b RH |
2704 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2705 | ||
2706 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2707 | stack below the return address. */ | |
2708 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2709 | |
529a6471 JJ |
2710 | /* If true, it is safe to not save/restore DRAP register. */ |
2711 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2712 | ||
f8071c05 L |
2713 | /* Function type. */ |
2714 | ENUM_BITFIELD(function_type) func_type : 2; | |
2715 | ||
da99fd4a L |
2716 | /* How to generate indirec branch. */ |
2717 | ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; | |
2718 | ||
2719 | /* If true, the current function has local indirect jumps, like | |
2720 | "indirect_jump" or "tablejump". */ | |
2721 | BOOL_BITFIELD has_local_indirect_jump : 1; | |
2722 | ||
45e14019 L |
2723 | /* How to generate function return. */ |
2724 | ENUM_BITFIELD(indirect_branch) function_return_type : 3; | |
2725 | ||
f8071c05 L |
2726 | /* If true, the current function is a function specified with |
2727 | the "interrupt" or "no_caller_saved_registers" attribute. */ | |
2728 | BOOL_BITFIELD no_caller_saved_registers : 1; | |
2729 | ||
a0ff7835 L |
2730 | /* If true, there is register available for argument passing. This |
2731 | is used only in ix86_function_ok_for_sibcall by 32-bit to determine | |
2732 | if there is scratch register available for indirect sibcall. In | |
2733 | 64-bit, rax, r10 and r11 are scratch registers which aren't used to | |
2734 | pass arguments and can be used for indirect sibcall. */ | |
2735 | BOOL_BITFIELD arg_reg_available : 1; | |
2736 | ||
d6d4d770 | 2737 | /* If true, we're out-of-lining reg save/restore for regs clobbered |
5d9d834d | 2738 | by 64-bit ms_abi functions calling a sysv_abi function. */ |
d6d4d770 DS |
2739 | BOOL_BITFIELD call_ms2sysv : 1; |
2740 | ||
2741 | /* If true, the incoming 16-byte aligned stack has an offset (of 8) and | |
5d9d834d | 2742 | needs padding prior to out-of-line stub save/restore area. */ |
d6d4d770 DS |
2743 | BOOL_BITFIELD call_ms2sysv_pad_in : 1; |
2744 | ||
d6d4d770 DS |
2745 | /* This is the number of extra registers saved by stub (valid range is |
2746 | 0-6). Each additional register is only saved/restored by the stubs | |
2747 | if all successive ones are. (Will always be zero when using a hard | |
2748 | frame pointer.) */ | |
2749 | unsigned int call_ms2sysv_extra_regs:3; | |
2750 | ||
35c95658 L |
2751 | /* Nonzero if the function places outgoing arguments on stack. */ |
2752 | BOOL_BITFIELD outgoing_args_on_stack : 1; | |
2753 | ||
708c728d L |
2754 | /* If true, ENDBR is queued at function entrance. */ |
2755 | BOOL_BITFIELD endbr_queued_at_entrance : 1; | |
2756 | ||
cd3410cc L |
2757 | /* The largest alignment, in bytes, of stack slot actually used. */ |
2758 | unsigned int max_used_stack_alignment; | |
2759 | ||
ec7ded37 RH |
2760 | /* During prologue/epilogue generation, the current frame state. |
2761 | Otherwise, the frame state at the end of the prologue. */ | |
2762 | struct machine_frame_state fs; | |
f81c9774 RH |
2763 | |
2764 | /* During SEH output, this is non-null. */ | |
2765 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2766 | }; |
2bf6d935 ML |
2767 | |
2768 | extern GTY(()) tree sysv_va_list_type_node; | |
2769 | extern GTY(()) tree ms_va_list_type_node; | |
cd9c1ca8 | 2770 | #endif |
fa1a0d02 JH |
2771 | |
2772 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2773 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2774 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2775 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
1e4490dc | 2776 | #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) |
5bf5a10b AO |
2777 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2778 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2779 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2780 | calls are optimized away, we try to detect cases in which it was | |
2781 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2782 | verify whether there's any such instruction live by testing that | |
2783 | REG_SP is live. */ | |
2784 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2785 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2786 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
2ecf9ac7 | 2787 | #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) |
249e6b63 | 2788 | |
1bc7c5b6 ZW |
2789 | /* Control behavior of x86_file_start. */ |
2790 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2791 | #define X86_FILE_START_FLTUSED false | |
2792 | ||
7dcbf659 JH |
2793 | /* Flag to mark data that is in the large address area. */ |
2794 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2795 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2796 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2797 | |
2798 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2799 | have defined always, to avoid ifdefing. */ | |
2800 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2801 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2802 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2803 | ||
2804 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2805 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2806 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2807 | ||
82c0e1a0 KT |
2808 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2809 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2810 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2811 | ||
7942e47e RY |
2812 | extern void debug_ready_dispatch (void); |
2813 | extern void debug_dispatch_window (int); | |
2814 | ||
91afcfa3 QN |
2815 | /* The value at zero is only defined for the BMI instructions |
2816 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2817 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1068ced5 | 2818 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) |
91afcfa3 | 2819 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
1068ced5 | 2820 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) |
91afcfa3 QN |
2821 | |
2822 | ||
b8ce4e94 KT |
2823 | /* Flags returned by ix86_get_callcvt (). */ |
2824 | #define IX86_CALLCVT_CDECL 0x1 | |
2825 | #define IX86_CALLCVT_STDCALL 0x2 | |
2826 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2827 | #define IX86_CALLCVT_THISCALL 0x8 | |
2828 | #define IX86_CALLCVT_REGPARM 0x10 | |
2829 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2830 | ||
2831 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2832 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2833 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2834 | ||
b86b9f44 MM |
2835 | #define RECIP_MASK_NONE 0x00 |
2836 | #define RECIP_MASK_DIV 0x01 | |
2837 | #define RECIP_MASK_SQRT 0x02 | |
2838 | #define RECIP_MASK_VEC_DIV 0x04 | |
2839 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2840 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2841 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2842 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2843 | |
2844 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2845 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2846 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2847 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2848 | ||
ab2c4ec8 SS |
2849 | /* Use 128-bit AVX instructions in the auto-vectorizer. */ |
2850 | #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) | |
2851 | /* Use 256-bit AVX instructions in the auto-vectorizer. */ | |
02a70367 SS |
2852 | #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ |
2853 | || prefer_vector_width_type == PVW_AVX256) | |
ab2c4ec8 | 2854 | |
c2c601b2 L |
2855 | #define TARGET_INDIRECT_BRANCH_REGISTER \ |
2856 | (ix86_indirect_branch_register \ | |
2857 | || cfun->machine->indirect_branch_type != indirect_branch_keep) | |
2858 | ||
5dcfdccd KY |
2859 | #define IX86_HLE_ACQUIRE (1 << 16) |
2860 | #define IX86_HLE_RELEASE (1 << 17) | |
2861 | ||
e83b8e2e JJ |
2862 | /* For switching between functions with different target attributes. */ |
2863 | #define SWITCHABLE_TARGET 1 | |
2864 | ||
44d0de8d UB |
2865 | #define TARGET_SUPPORTS_WIDE_INT 1 |
2866 | ||
2bf6d935 ML |
2867 | #if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2) |
2868 | extern enum attr_cpu ix86_schedule; | |
2869 | ||
2870 | #define NUM_X86_64_MS_CLOBBERED_REGS 12 | |
2871 | #endif | |
2872 | ||
c98f8742 JVA |
2873 | /* |
2874 | Local variables: | |
2875 | version-control: t | |
2876 | End: | |
2877 | */ |