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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
cbe34bb5 | 2 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
90922d36 | 42 | #define TARGET_64BIT TARGET_ISA_64BIT |
bf7b5747 | 43 | #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) |
90922d36 | 44 | #define TARGET_MMX TARGET_ISA_MMX |
bf7b5747 | 45 | #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) |
90922d36 | 46 | #define TARGET_3DNOW TARGET_ISA_3DNOW |
bf7b5747 | 47 | #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) |
90922d36 | 48 | #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A |
bf7b5747 | 49 | #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) |
90922d36 | 50 | #define TARGET_SSE TARGET_ISA_SSE |
bf7b5747 | 51 | #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) |
90922d36 | 52 | #define TARGET_SSE2 TARGET_ISA_SSE2 |
bf7b5747 | 53 | #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) |
90922d36 | 54 | #define TARGET_SSE3 TARGET_ISA_SSE3 |
bf7b5747 | 55 | #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) |
90922d36 | 56 | #define TARGET_SSSE3 TARGET_ISA_SSSE3 |
bf7b5747 | 57 | #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) |
90922d36 | 58 | #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 |
bf7b5747 | 59 | #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) |
90922d36 | 60 | #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 |
bf7b5747 | 61 | #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) |
90922d36 | 62 | #define TARGET_AVX TARGET_ISA_AVX |
bf7b5747 | 63 | #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) |
90922d36 | 64 | #define TARGET_AVX2 TARGET_ISA_AVX2 |
bf7b5747 | 65 | #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) |
cb610367 UB |
66 | #define TARGET_AVX512F TARGET_ISA_AVX512F |
67 | #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
68 | #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
69 | #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
70 | #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
71 | #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
72 | #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
73 | #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
07165dd7 AI |
74 | #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ |
75 | #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
b525d943 AI |
76 | #define TARGET_AVX512BW TARGET_ISA_AVX512BW |
77 | #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
f4af595f AI |
78 | #define TARGET_AVX512VL TARGET_ISA_AVX512VL |
79 | #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
3dcc8af5 IT |
80 | #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI |
81 | #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) | |
4190ea38 IT |
82 | #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA |
83 | #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) | |
5fbb13a7 KY |
84 | #define TARGET_AVX5124FMAPS TARGET_ISA_AVX5124FMAPS |
85 | #define TARGET_AVX5124FMAPS_P(x) TARGET_ISA_AVX5124FMAPS_P(x) | |
86 | #define TARGET_AVX5124VNNIW TARGET_ISA_AVX5124VNNIW | |
87 | #define TARGET_AVX5124VNNIW_P(x) TARGET_ISA_AVX5124VNNIW_P(x) | |
79fc8ffe AS |
88 | #define TARGET_AVX512VPOPCNTDQ TARGET_ISA_AVX512VPOPCNTDQ |
89 | #define TARGET_AVX512VPOPCNTDQ_P(x) TARGET_ISA_AVX512VPOPCNTDQ_P(x) | |
90922d36 | 90 | #define TARGET_FMA TARGET_ISA_FMA |
bf7b5747 | 91 | #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) |
90922d36 | 92 | #define TARGET_SSE4A TARGET_ISA_SSE4A |
bf7b5747 | 93 | #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) |
90922d36 | 94 | #define TARGET_FMA4 TARGET_ISA_FMA4 |
bf7b5747 | 95 | #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) |
90922d36 | 96 | #define TARGET_XOP TARGET_ISA_XOP |
bf7b5747 | 97 | #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) |
90922d36 | 98 | #define TARGET_LWP TARGET_ISA_LWP |
bf7b5747 | 99 | #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) |
90922d36 | 100 | #define TARGET_ABM TARGET_ISA_ABM |
bf7b5747 | 101 | #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) |
73e32c47 JK |
102 | #define TARGET_SGX TARGET_ISA_SGX |
103 | #define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) | |
1d516992 JK |
104 | #define TARGET_RDPID TARGET_ISA_RDPID |
105 | #define TARGET_RDPID_P(x) TARGET_ISA_RDPID_P(x) | |
90922d36 | 106 | #define TARGET_BMI TARGET_ISA_BMI |
bf7b5747 | 107 | #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) |
90922d36 | 108 | #define TARGET_BMI2 TARGET_ISA_BMI2 |
bf7b5747 | 109 | #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) |
90922d36 | 110 | #define TARGET_LZCNT TARGET_ISA_LZCNT |
bf7b5747 | 111 | #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) |
90922d36 | 112 | #define TARGET_TBM TARGET_ISA_TBM |
bf7b5747 | 113 | #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) |
90922d36 | 114 | #define TARGET_POPCNT TARGET_ISA_POPCNT |
bf7b5747 | 115 | #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) |
90922d36 | 116 | #define TARGET_SAHF TARGET_ISA_SAHF |
bf7b5747 | 117 | #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) |
90922d36 | 118 | #define TARGET_MOVBE TARGET_ISA_MOVBE |
bf7b5747 | 119 | #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) |
90922d36 | 120 | #define TARGET_CRC32 TARGET_ISA_CRC32 |
bf7b5747 | 121 | #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) |
90922d36 | 122 | #define TARGET_AES TARGET_ISA_AES |
bf7b5747 | 123 | #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) |
c1618f82 AI |
124 | #define TARGET_SHA TARGET_ISA_SHA |
125 | #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
9cdea277 IT |
126 | #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT |
127 | #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
9ce29eb0 VK |
128 | #define TARGET_CLZERO TARGET_ISA_CLZERO |
129 | #define TARGET_CLZERO_P(x) TARGET_ISA_CLZERO_P(x) | |
9cdea277 IT |
130 | #define TARGET_XSAVEC TARGET_ISA_XSAVEC |
131 | #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
132 | #define TARGET_XSAVES TARGET_ISA_XSAVES | |
133 | #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
90922d36 | 134 | #define TARGET_PCLMUL TARGET_ISA_PCLMUL |
bf7b5747 | 135 | #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) |
cb610367 UB |
136 | #define TARGET_CMPXCHG16B TARGET_ISA_CX16 |
137 | #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) | |
90922d36 | 138 | #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
bf7b5747 | 139 | #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) |
90922d36 | 140 | #define TARGET_RDRND TARGET_ISA_RDRND |
bf7b5747 | 141 | #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) |
90922d36 | 142 | #define TARGET_F16C TARGET_ISA_F16C |
bf7b5747 | 143 | #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) |
cb610367 UB |
144 | #define TARGET_RTM TARGET_ISA_RTM |
145 | #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
90922d36 | 146 | #define TARGET_HLE TARGET_ISA_HLE |
bf7b5747 | 147 | #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) |
90922d36 | 148 | #define TARGET_RDSEED TARGET_ISA_RDSEED |
bf7b5747 | 149 | #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) |
90922d36 | 150 | #define TARGET_PRFCHW TARGET_ISA_PRFCHW |
bf7b5747 | 151 | #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) |
90922d36 | 152 | #define TARGET_ADX TARGET_ISA_ADX |
bf7b5747 | 153 | #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) |
3a0d99bb | 154 | #define TARGET_FXSR TARGET_ISA_FXSR |
bf7b5747 | 155 | #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) |
3a0d99bb | 156 | #define TARGET_XSAVE TARGET_ISA_XSAVE |
bf7b5747 | 157 | #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) |
3a0d99bb | 158 | #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT |
bf7b5747 | 159 | #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) |
43b3f52f IT |
160 | #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 |
161 | #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
d5e254e1 IE |
162 | #define TARGET_MPX TARGET_ISA_MPX |
163 | #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) | |
9c3bca11 IT |
164 | #define TARGET_CLWB TARGET_ISA_CLWB |
165 | #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) | |
500a08b2 VK |
166 | #define TARGET_MWAITX TARGET_ISA_MWAITX |
167 | #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) | |
41a4ef22 KY |
168 | #define TARGET_PKU TARGET_ISA_PKU |
169 | #define TARGET_PKU_P(x) TARGET_ISA_PKU_P(x) | |
170 | ||
90922d36 | 171 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 172 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
90922d36 | 173 | #define TARGET_X32 TARGET_ABI_X32 |
bf7b5747 | 174 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) |
d5d618b5 L |
175 | #define TARGET_16BIT TARGET_CODE16 |
176 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
04e1d06b | 177 | |
26b5109f RS |
178 | #include "config/vxworks-dummy.h" |
179 | ||
7eb68c06 | 180 | #include "config/i386/i386-opts.h" |
ccf8e764 | 181 | |
c69fa2d4 | 182 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 183 | |
8c996513 JH |
184 | /* Specify what algorithm to use for stringops on known size. |
185 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
186 | known at compile time or estimated via feedback, the SIZE array | |
187 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 188 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
189 | When NOALIGN is true the code guaranting the alignment of the memory |
190 | block is skipped. | |
191 | ||
8c996513 | 192 | For example initializer: |
4f3f76e6 | 193 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 194 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 195 | be used otherwise. */ |
8c996513 JH |
196 | struct stringop_algs |
197 | { | |
198 | const enum stringop_alg unknown_size; | |
199 | const struct stringop_strategy { | |
200 | const int max; | |
201 | const enum stringop_alg alg; | |
340ef734 | 202 | int noalign; |
c69fa2d4 | 203 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
204 | }; |
205 | ||
d4ba09c0 SC |
206 | /* Define the specific costs for a given cpu */ |
207 | ||
208 | struct processor_costs { | |
8b60264b KG |
209 | const int add; /* cost of an add instruction */ |
210 | const int lea; /* cost of a lea instruction */ | |
211 | const int shift_var; /* variable shift costs */ | |
212 | const int shift_const; /* constant shift costs */ | |
f676971a | 213 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 214 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 215 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 216 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 217 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
218 | int movsx; /* The cost of movsx operation. */ |
219 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
220 | const int large_insn; /* insns larger than this cost more */ |
221 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 222 | memory-to-memory move insns. */ |
8b60264b KG |
223 | const int movzbl_load; /* cost of loading using movzbl */ |
224 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
225 | in QImode, HImode and SImode relative |
226 | to reg-reg move (2). */ | |
8b60264b | 227 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 228 | in QImode, HImode and SImode */ |
8b60264b KG |
229 | const int fp_move; /* cost of reg,reg fld/fst */ |
230 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 231 | in SFmode, DFmode and XFmode */ |
8b60264b | 232 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 233 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
234 | const int mmx_move; /* cost of moving MMX register. */ |
235 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 236 | in SImode and DImode */ |
8b60264b | 237 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 238 | in SImode and DImode */ |
8b60264b KG |
239 | const int sse_move; /* cost of moving SSE register. */ |
240 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 241 | in SImode, DImode and TImode*/ |
8b60264b | 242 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 243 | in SImode, DImode and TImode*/ |
8b60264b | 244 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 245 | integer and vice versa. */ |
46cb0441 ZD |
246 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
247 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
248 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
249 | const int simultaneous_prefetches; /* number of parallel prefetch | |
250 | operations. */ | |
4977bab6 | 251 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
252 | const int fadd; /* cost of FADD and FSUB instructions. */ |
253 | const int fmul; /* cost of FMUL instruction. */ | |
254 | const int fdiv; /* cost of FDIV instruction. */ | |
255 | const int fabs; /* cost of FABS instruction. */ | |
256 | const int fchs; /* cost of FCHS instruction. */ | |
257 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 258 | /* Specify what algorithm |
bee51209 | 259 | to use for stringops on unknown size. */ |
6065f444 JH |
260 | const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ |
261 | const int mulss; /* cost of MULSS instructions. */ | |
262 | const int mulsd; /* cost of MULSD instructions. */ | |
263 | const int divss; /* cost of DIVSS instructions. */ | |
264 | const int divsd; /* cost of DIVSD instructions. */ | |
265 | const int sqrtss; /* cost of SQRTSS instructions. */ | |
266 | const int sqrtsd; /* cost of SQRTSD instructions. */ | |
a813c280 JH |
267 | const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; |
268 | /* Specify reassociation width for integer, | |
269 | fp, vector integer and vector fp | |
270 | operations. Generally should correspond | |
271 | to number of instructions executed in | |
272 | parallel. See also | |
273 | ix86_reassociation_width. */ | |
ad83025e | 274 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
275 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
276 | load and store. */ | |
277 | const int scalar_load_cost; /* Cost of scalar load. */ | |
278 | const int scalar_store_cost; /* Cost of scalar store. */ | |
279 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
280 | load, store, vector-to-scalar and | |
281 | scalar-to-vector operation. */ | |
282 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
283 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 284 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
285 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
286 | const int vec_store_cost; /* Cost of vector store. */ | |
287 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
288 | cost model. */ | |
289 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
290 | vectorizer cost model. */ | |
d4ba09c0 SC |
291 | }; |
292 | ||
8b60264b | 293 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
294 | extern const struct processor_costs ix86_size_cost; |
295 | ||
296 | #define ix86_cur_cost() \ | |
297 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 298 | |
c98f8742 JVA |
299 | /* Macros used in the machine description to test the flags. */ |
300 | ||
b97de419 | 301 | /* configure can arrange to change it. */ |
e075ae69 | 302 | |
35b528be | 303 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 304 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 305 | #endif |
35b528be | 306 | |
004d3859 GK |
307 | #ifndef TARGET_FPMATH_DEFAULT |
308 | #define TARGET_FPMATH_DEFAULT \ | |
309 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
310 | #endif | |
311 | ||
bf7b5747 ST |
312 | #ifndef TARGET_FPMATH_DEFAULT_P |
313 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
314 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
315 | #endif | |
316 | ||
c207fd99 L |
317 | /* If the i387 is disabled or -miamcu is used , then do not return |
318 | values in it. */ | |
319 | #define TARGET_FLOAT_RETURNS_IN_80387 \ | |
320 | (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) | |
321 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ | |
322 | (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) | |
b08de47e | 323 | |
5791cc29 JT |
324 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
325 | compile-time constant. */ | |
326 | #ifdef IN_LIBGCC2 | |
6ac49599 | 327 | #undef TARGET_64BIT |
5791cc29 JT |
328 | #ifdef __x86_64__ |
329 | #define TARGET_64BIT 1 | |
330 | #else | |
331 | #define TARGET_64BIT 0 | |
332 | #endif | |
333 | #else | |
6ac49599 RS |
334 | #ifndef TARGET_BI_ARCH |
335 | #undef TARGET_64BIT | |
e49080ec | 336 | #undef TARGET_64BIT_P |
67adf6a9 | 337 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 338 | #define TARGET_64BIT 1 |
e49080ec | 339 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
340 | #else |
341 | #define TARGET_64BIT 0 | |
e49080ec | 342 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
343 | #endif |
344 | #endif | |
5791cc29 | 345 | #endif |
25f94bb5 | 346 | |
750054a2 CT |
347 | #define HAS_LONG_COND_BRANCH 1 |
348 | #define HAS_LONG_UNCOND_BRANCH 1 | |
349 | ||
9e555526 RH |
350 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
351 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
352 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
353 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 354 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
355 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
356 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
357 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
358 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 359 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 360 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
340ef734 | 361 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d3c11974 L |
362 | #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) |
363 | #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
3a579e09 | 364 | #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) |
d3c11974 L |
365 | #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) |
366 | #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
52747219 | 367 | #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) |
cace2309 | 368 | #define TARGET_KNM (ix86_tune == PROCESSOR_KNM) |
06caf59d | 369 | #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) |
9a7f94d7 | 370 | #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
9d532162 | 371 | #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) |
21efb4d4 | 372 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
1133125e | 373 | #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
4d652a18 | 374 | #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
eb2f2b44 | 375 | #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) |
ed97ad47 | 376 | #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) |
14b52538 | 377 | #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
e32bfc16 | 378 | #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
9ce29eb0 | 379 | #define TARGET_ZNVER1 (ix86_tune == PROCESSOR_ZNVER1) |
a269a03c | 380 | |
80fd744f RH |
381 | /* Feature tests against the various tunings. */ |
382 | enum ix86_tune_indices { | |
4b8bc035 | 383 | #undef DEF_TUNE |
3ad20bd4 | 384 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
385 | #include "x86-tune.def" |
386 | #undef DEF_TUNE | |
387 | X86_TUNE_LAST | |
80fd744f RH |
388 | }; |
389 | ||
ab442df7 | 390 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
391 | |
392 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
393 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
394 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
395 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 396 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
397 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
398 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
399 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
400 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
401 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
402 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
403 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
404 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
405 | #define TARGET_LCP_STALL \ |
406 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
407 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
408 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
409 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
410 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
411 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
412 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
413 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
414 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
415 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
416 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
417 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
5783ad0e UB |
418 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
419 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
420 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
421 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
422 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
423 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
424 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
425 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
426 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
427 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
428 | #define TARGET_INTEGER_DFMODE_MOVES \ |
429 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
430 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
431 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
432 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
433 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
1133125e HJ |
434 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
435 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
436 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
437 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
438 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
439 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
440 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
441 | #define TARGET_SSE_TYPELESS_STORES \ | |
442 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
443 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
444 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
445 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
446 | #define TARGET_PROLOGUE_USING_MOVE \ | |
447 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
448 | #define TARGET_EPILOGUE_USING_MOVE \ | |
449 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
450 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
451 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
452 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
453 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
454 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
455 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
456 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 457 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
458 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
459 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
460 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
461 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
462 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
463 | #define TARGET_PAD_SHORT_FUNCTION \ |
464 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
465 | #define TARGET_EXT_80387_CONSTANTS \ |
466 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
467 | #define TARGET_AVOID_VECTOR_DECODE \ |
468 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
469 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
470 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
471 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
472 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
473 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
474 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
475 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
476 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
477 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
478 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
479 | #define TARGET_USE_VECTOR_CONVERTS \ |
480 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
481 | #define TARGET_SLOW_PSHUFB \ |
482 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
8e0dc054 JJ |
483 | #define TARGET_AVOID_4BYTE_PREFIXES \ |
484 | ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] | |
0dc41f28 WM |
485 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
486 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
487 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
488 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 489 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
490 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
491 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
492 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
493 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
494 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
495 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 496 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
497 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
498 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
5d0878e7 JH |
499 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
500 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
5c0d88e6 CF |
501 | #define TARGET_AVX128_OPTIMAL \ |
502 | ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] | |
55a2c322 VM |
503 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
504 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
505 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
506 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 507 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 508 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
509 | #define TARGET_ADJUST_UNROLL \ |
510 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
374f5bf8 UB |
511 | #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ |
512 | ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
ca90b1ed YR |
513 | #define TARGET_ONE_IF_CONV_INSN \ |
514 | ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] | |
df7b0cc4 | 515 | |
80fd744f RH |
516 | /* Feature tests against the various architecture variations. */ |
517 | enum ix86_arch_indices { | |
cef31f9c | 518 | X86_ARCH_CMOV, |
80fd744f RH |
519 | X86_ARCH_CMPXCHG, |
520 | X86_ARCH_CMPXCHG8B, | |
521 | X86_ARCH_XADD, | |
522 | X86_ARCH_BSWAP, | |
523 | ||
524 | X86_ARCH_LAST | |
525 | }; | |
4f3f76e6 | 526 | |
ab442df7 | 527 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 528 | |
cef31f9c | 529 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
530 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
531 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
532 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
533 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
534 | ||
cef31f9c UB |
535 | /* For sane SSE instruction set generation we need fcomi instruction. |
536 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
537 | expands to a sequence that includes conditional move. */ | |
538 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
539 | ||
80fd744f RH |
540 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
541 | ||
cb261eb7 | 542 | extern unsigned char x86_prefetch_sse; |
80fd744f RH |
543 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
544 | ||
80fd744f RH |
545 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
546 | ||
547 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
548 | #define TARGET_MIX_SSE_I387 \ | |
549 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
550 | ||
5fa578f0 UB |
551 | #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) |
552 | #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) | |
553 | #define TARGET_HARD_XF_REGS (TARGET_80387) | |
554 | ||
80fd744f RH |
555 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
556 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
557 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 558 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 559 | |
67adf6a9 RH |
560 | #ifndef TARGET_64BIT_DEFAULT |
561 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 562 | #endif |
74dc3e94 RH |
563 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
564 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
565 | #endif | |
25f94bb5 | 566 | |
e0ea8797 AH |
567 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
568 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
569 | ||
79f5e442 ZD |
570 | /* Fence to use after loop using storent. */ |
571 | ||
572 | extern tree x86_mfence; | |
573 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
574 | ||
0ed4a390 JL |
575 | /* Once GDB has been enhanced to deal with functions without frame |
576 | pointers, we can change this to allow for elimination of | |
577 | the frame pointer in leaf functions. */ | |
578 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 579 | |
0a1c5e55 UB |
580 | /* Extra bits to force. */ |
581 | #define TARGET_SUBTARGET_DEFAULT 0 | |
582 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
583 | ||
584 | /* Extra bits to force on w/ 32-bit mode. */ | |
585 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
586 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
587 | ||
ccf8e764 RH |
588 | /* Extra bits to force on w/ 64-bit mode. */ |
589 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 590 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 591 | |
fee3eacd IS |
592 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
593 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 594 | #define TARGET_MACHO 0 |
9005471b | 595 | #define TARGET_MACHO_BRANCH_ISLANDS 0 |
fee3eacd IS |
596 | #define MACHOPIC_ATT_STUB 0 |
597 | /* (b) Macros defined in config/darwin.h */ | |
598 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
599 | #define MACHOPIC_INDIRECT 0 | |
600 | #define MACHOPIC_PURE 0 | |
9005471b | 601 | |
5a579c3b LE |
602 | /* For the RDOS */ |
603 | #define TARGET_RDOS 0 | |
604 | ||
9005471b | 605 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
606 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
607 | ||
6510e8bb KT |
608 | /* For the Windows 32-bit ABI. */ |
609 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
610 | ||
f81c9774 RH |
611 | /* This is re-defined by cygming.h. */ |
612 | #define TARGET_SEH 0 | |
613 | ||
51212b32 | 614 | /* The default abi used by target. */ |
7c800926 | 615 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 616 | |
b8b3f0ca | 617 | /* The default TLS segment register used by target. */ |
00402c94 RH |
618 | #define DEFAULT_TLS_SEG_REG \ |
619 | (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) | |
b8b3f0ca | 620 | |
cc69336f RH |
621 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
622 | with the rounding mode forced to 53 bits. */ | |
623 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
624 | ||
682cd442 GK |
625 | /* -march=native handling only makes sense with compiler running on |
626 | an x86 or x86_64 chip. If changing this condition, also change | |
627 | the condition in driver-i386.c. */ | |
628 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
629 | /* In driver-i386.c. */ |
630 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
631 | #define EXTRA_SPEC_FUNCTIONS \ | |
632 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 633 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
634 | #endif |
635 | ||
8981c15b JM |
636 | #if TARGET_64BIT_DEFAULT |
637 | #define OPT_ARCH64 "!m32" | |
638 | #define OPT_ARCH32 "m32" | |
639 | #else | |
f0ea7581 L |
640 | #define OPT_ARCH64 "m64|mx32" |
641 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
642 | #endif |
643 | ||
1cba2b96 EC |
644 | /* Support for configure-time defaults of some command line options. |
645 | The order here is important so that -march doesn't squash the | |
646 | tune or cpu values. */ | |
ce998900 | 647 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 648 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
649 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
650 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 651 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
652 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
653 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
654 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
655 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
656 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 657 | |
241e1a89 SC |
658 | /* Specs for the compiler proper */ |
659 | ||
628714d8 | 660 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 661 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 662 | |
682cd442 | 663 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
664 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
665 | #else | |
666 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
96f5b137 L |
667 | "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
668 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ | |
669 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" | |
fa959ce4 | 670 | #endif |
241e1a89 | 671 | #endif |
c98f8742 | 672 | \f |
30efe578 | 673 | /* Target CPU builtins. */ |
ab442df7 MM |
674 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
675 | ||
676 | /* Target Pragmas. */ | |
677 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 678 | |
628714d8 | 679 | #ifndef CC1_SPEC |
8015b78d | 680 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
681 | #endif |
682 | ||
683 | /* This macro defines names of additional specifications to put in the | |
684 | specs that can be used in various specifications like CC1_SPEC. Its | |
685 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
686 | |
687 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 688 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
689 | program. |
690 | ||
691 | Do not define this macro if it does not need to do anything. */ | |
692 | ||
693 | #ifndef SUBTARGET_EXTRA_SPECS | |
694 | #define SUBTARGET_EXTRA_SPECS | |
695 | #endif | |
696 | ||
697 | #define EXTRA_SPECS \ | |
628714d8 | 698 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
699 | SUBTARGET_EXTRA_SPECS |
700 | \f | |
ce998900 | 701 | |
8ce94e44 JM |
702 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
703 | SFmode, DFmode and XFmode) in the current excess precision | |
704 | configuration. */ | |
b8cab8a5 UB |
705 | #define X87_ENABLE_ARITH(MODE) \ |
706 | (flag_unsafe_math_optimizations \ | |
707 | || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
708 | || (MODE) == XFmode) | |
8ce94e44 JM |
709 | |
710 | /* Likewise, whether to allow direct conversions from integer mode | |
711 | IMODE (HImode, SImode or DImode) to MODE. */ | |
712 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
b8cab8a5 UB |
713 | (flag_unsafe_math_optimizations \ |
714 | || flag_excess_precision == EXCESS_PRECISION_FAST \ | |
8ce94e44 JM |
715 | || (MODE) == XFmode \ |
716 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
717 | || (IMODE) == HImode) | |
718 | ||
979c67a5 UB |
719 | /* target machine storage layout */ |
720 | ||
65d9c0ab JH |
721 | #define SHORT_TYPE_SIZE 16 |
722 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
723 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
724 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 725 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 726 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 727 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
728 | #define LONG_DOUBLE_TYPE_SIZE \ |
729 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 730 | |
c637141a | 731 | #define WIDEST_HARDWARE_FP_SIZE 80 |
65d9c0ab | 732 | |
67adf6a9 | 733 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 734 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
735 | #else |
736 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
737 | #endif |
738 | ||
c98f8742 JVA |
739 | /* Define this if most significant byte of a word is the lowest numbered. */ |
740 | /* That is true on the 80386. */ | |
741 | ||
742 | #define BITS_BIG_ENDIAN 0 | |
743 | ||
744 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
745 | /* That is not true on the 80386. */ | |
746 | #define BYTES_BIG_ENDIAN 0 | |
747 | ||
748 | /* Define this if most significant word of a multiword number is the lowest | |
749 | numbered. */ | |
750 | /* Not true for 80386 */ | |
751 | #define WORDS_BIG_ENDIAN 0 | |
752 | ||
c98f8742 | 753 | /* Width of a word, in units (bytes). */ |
4ae8027b | 754 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
755 | |
756 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
757 | #define MIN_UNITS_PER_WORD 4 |
758 | #endif | |
c98f8742 | 759 | |
c98f8742 | 760 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 761 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 762 | |
e075ae69 | 763 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
4ae8027b | 764 | #define STACK_BOUNDARY \ |
51212b32 | 765 | (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 766 | |
2e3f842f L |
767 | /* Stack boundary of the main function guaranteed by OS. */ |
768 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
769 | ||
de1132d1 | 770 | /* Minimum stack boundary. */ |
cba9c789 | 771 | #define MIN_STACK_BOUNDARY BITS_PER_WORD |
2e3f842f | 772 | |
d1f87653 | 773 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 774 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 775 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 776 | |
de1132d1 | 777 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
778 | both 32bit and 64bit, to support codes that need 128 bit stack |
779 | alignment for SSE instructions, but can't realign the stack. */ | |
d9063947 L |
780 | #define PREFERRED_STACK_BOUNDARY_DEFAULT \ |
781 | (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) | |
2e3f842f L |
782 | |
783 | /* 1 if -mstackrealign should be turned on by default. It will | |
784 | generate an alternate prologue and epilogue that realigns the | |
785 | runtime stack if nessary. This supports mixing codes that keep a | |
786 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 787 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
788 | #define STACK_REALIGN_DEFAULT 0 |
789 | ||
790 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
791 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 792 | |
a2851b75 TG |
793 | /* According to Windows x64 software convention, the maximum stack allocatable |
794 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
795 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
796 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
797 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
798 | prologue. | |
799 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 800 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
801 | regs, then save them, and then allocate the remaining. There is no SEH |
802 | unwind info for this later allocation. */ | |
803 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
804 | ||
ebff937c SH |
805 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
806 | mandatory for the 64-bit ABI, and may or may not be true for other | |
807 | operating systems. */ | |
808 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
809 | ||
f963b5d9 RS |
810 | /* Minimum allocation boundary for the code of a function. */ |
811 | #define FUNCTION_BOUNDARY 8 | |
812 | ||
813 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
814 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 815 | |
c98f8742 JVA |
816 | /* Minimum size in bits of the largest boundary to which any |
817 | and all fundamental data types supported by the hardware | |
818 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 819 | rounder than this. |
fce5a9f2 | 820 | |
d1f87653 | 821 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
6d2b7199 BS |
822 | and Pentium Pro XFmode values at 128 bit boundaries. |
823 | ||
824 | When increasing the maximum, also update | |
825 | TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ | |
17f24ff0 | 826 | |
3f97cb0b | 827 | #define BIGGEST_ALIGNMENT \ |
0076c82f | 828 | (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) |
17f24ff0 | 829 | |
2e3f842f L |
830 | /* Maximum stack alignment. */ |
831 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
832 | ||
6e4f1168 L |
833 | /* Alignment value for attribute ((aligned)). It is a constant since |
834 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
e9c9e772 | 835 | #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) |
6e4f1168 | 836 | |
822eda12 | 837 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 838 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 839 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 840 | |
17f24ff0 | 841 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 842 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 843 | -malign-double is set. */ |
e932b21b | 844 | |
e83f3cff RH |
845 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
846 | supports no vector modes, cut out the complexity and fall back | |
847 | on BIGGEST_FIELD_ALIGNMENT. */ | |
848 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
849 | #ifdef __x86_64__ |
850 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
851 | #else | |
e83f3cff | 852 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 853 | #endif |
e83f3cff | 854 | #else |
a4cf4b64 RB |
855 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
856 | x86_field_alignment ((TYPE), (COMPUTED)) | |
e83f3cff | 857 | #endif |
c98f8742 | 858 | |
8a022443 JW |
859 | /* If defined, a C expression to compute the alignment for a static |
860 | variable. TYPE is the data type, and ALIGN is the alignment that | |
861 | the object would ordinarily have. The value of this macro is used | |
862 | instead of that alignment to align the object. | |
863 | ||
864 | If this macro is not defined, then ALIGN is used. | |
865 | ||
866 | One use of this macro is to increase alignment of medium-size | |
867 | data to make it all fit in fewer cache lines. Another is to | |
868 | cause character arrays to be word-aligned so that `strcpy' calls | |
869 | that copy constants to character arrays can be done inline. */ | |
870 | ||
df8a1d28 JJ |
871 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
872 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
873 | ||
874 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
875 | some alignment increase, instead of optimization only purposes. E.g. | |
876 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
877 | must be aligned to 16 byte boundaries. | |
878 | ||
879 | If this macro is not defined, then ALIGN is used. */ | |
880 | ||
881 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
882 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
883 | |
884 | /* If defined, a C expression to compute the alignment for a local | |
885 | variable. TYPE is the data type, and ALIGN is the alignment that | |
886 | the object would ordinarily have. The value of this macro is used | |
887 | instead of that alignment to align the object. | |
888 | ||
889 | If this macro is not defined, then ALIGN is used. | |
890 | ||
891 | One use of this macro is to increase alignment of medium-size | |
892 | data to make it all fit in fewer cache lines. */ | |
893 | ||
76fe54f0 L |
894 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
895 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
896 | ||
897 | /* If defined, a C expression to compute the alignment for stack slot. | |
898 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
899 | is the alignment that the slot would ordinarily have. The value of | |
900 | this macro is used instead of that alignment to align the slot. | |
901 | ||
902 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
903 | Otherwise, LOCAL_ALIGNMENT will be used. | |
904 | ||
905 | One use of this macro is to set alignment of stack slot to the | |
906 | maximum alignment of all possible modes which the slot may have. */ | |
907 | ||
908 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
909 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 910 | |
9bfaf89d JJ |
911 | /* If defined, a C expression to compute the alignment for a local |
912 | variable DECL. | |
913 | ||
914 | If this macro is not defined, then | |
915 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
916 | ||
917 | One use of this macro is to increase alignment of medium-size | |
918 | data to make it all fit in fewer cache lines. */ | |
919 | ||
920 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
921 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
922 | ||
ae58e548 JJ |
923 | /* If defined, a C expression to compute the minimum required alignment |
924 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
925 | MODE, assuming normal alignment ALIGN. | |
926 | ||
927 | If this macro is not defined, then (ALIGN) will be used. */ | |
928 | ||
929 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
1a6e82b8 | 930 | ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) |
ae58e548 | 931 | |
9bfaf89d | 932 | |
9cd10576 | 933 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 934 | when given unaligned data. */ |
b4ac57ab | 935 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
936 | |
937 | /* If bit field type is int, don't let it cross an int, | |
938 | and give entire struct the alignment of an int. */ | |
43a88a8c | 939 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 940 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
941 | \f |
942 | /* Standard register usage. */ | |
943 | ||
944 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 945 | for details. */ |
c98f8742 JVA |
946 | |
947 | #define STACK_REGS | |
ce998900 | 948 | |
f48b4284 UB |
949 | #define IS_STACK_MODE(MODE) \ |
950 | (X87_FLOAT_MODE_P (MODE) \ | |
951 | && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ | |
952 | || TARGET_MIX_SSE_I387)) | |
c98f8742 JVA |
953 | |
954 | /* Number of actual hardware registers. | |
955 | The hardware registers are assigned numbers for the compiler | |
956 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
957 | All registers that the compiler knows about must be given numbers, | |
958 | even those that are not normally considered general registers. | |
959 | ||
960 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
961 | We number the floating point registers 8-15. | |
962 | Note that registers 0-7 can be accessed as a short or int, | |
963 | while only 0-3 may be used with byte `mov' instructions. | |
964 | ||
965 | Reg 16 does not correspond to any hardware register, but instead | |
966 | appears in the RTL as an argument pointer prior to reload, and is | |
967 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 968 | pointer. */ |
c98f8742 | 969 | |
05416670 | 970 | #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG |
c98f8742 | 971 | |
3073d01c ML |
972 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
973 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
974 | ||
975 | #define DWARF_FRAME_REGISTERS 17 | |
976 | ||
c98f8742 JVA |
977 | /* 1 for registers that have pervasive standard uses |
978 | and are not available for the register allocator. | |
3f3f2124 | 979 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 980 | |
621bc046 UB |
981 | REX registers are disabled for 32bit targets in |
982 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
983 | ||
a7180f70 BS |
984 | #define FIXED_REGISTERS \ |
985 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 986 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
987 | /*arg,flags,fpsr,fpcr,frame*/ \ |
988 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
989 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
990 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 991 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
992 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
993 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 994 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 995 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
996 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
997 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
998 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
999 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1000 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1001 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
d5e254e1 IE |
1002 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1003 | /* b0, b1, b2, b3*/ \ | |
1004 | 0, 0, 0, 0 } | |
c98f8742 JVA |
1005 | |
1006 | /* 1 for registers not available across function calls. | |
1007 | These must include the FIXED_REGISTERS and also any | |
1008 | registers that can be used without being saved. | |
1009 | The latter must include the registers where values are returned | |
1010 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
1011 | Aside from that, you can include as many other registers as you like. |
1012 | ||
621bc046 UB |
1013 | Value is set to 1 if the register is call used unconditionally. |
1014 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
1015 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
1016 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
1017 | ||
1018 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
1019 | ||
1f3ccbc8 L |
1020 | #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ |
1021 | ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) | |
1022 | ||
a7180f70 BS |
1023 | #define CALL_USED_REGISTERS \ |
1024 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 1025 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
1026 | /*arg,flags,fpsr,fpcr,frame*/ \ |
1027 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 1028 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 1029 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 1030 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 1031 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1032 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1033 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1034 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1035 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1036 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1037 | 6, 6, 6, 6, 6, 6, 6, 6, \ | |
1038 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1039 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1040 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
d5e254e1 IE |
1041 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
1042 | /* b0, b1, b2, b3*/ \ | |
1043 | 1, 1, 1, 1 } | |
c98f8742 | 1044 | |
3b3c6a3f MM |
1045 | /* Order in which to allocate registers. Each register must be |
1046 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1047 | late and fixed registers last. Note that, in general, we prefer | |
1048 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1049 | available for storage of persistent values. | |
1050 | ||
5a733826 | 1051 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
162f023b | 1052 | so this is just empty initializer for array. */ |
3b3c6a3f | 1053 | |
162f023b JH |
1054 | #define REG_ALLOC_ORDER \ |
1055 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1056 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1057 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
3f97cb0b | 1058 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
d5e254e1 IE |
1059 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ |
1060 | 78, 79, 80 } | |
3b3c6a3f | 1061 | |
5a733826 | 1062 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 1063 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 1064 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1065 | |
5a733826 | 1066 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1067 | |
f5316dfe | 1068 | |
7c800926 KT |
1069 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1070 | ||
8521c414 | 1071 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
7bf65250 UB |
1072 | (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ |
1073 | && GENERAL_REGNO_P (REGNO) \ | |
1074 | && ((MODE) == XFmode || (MODE) == XCmode)) | |
8521c414 JM |
1075 | |
1076 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1077 | ||
95879c72 L |
1078 | #define VALID_AVX256_REG_MODE(MODE) \ |
1079 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb JJ |
1080 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
1081 | || (MODE) == V4DFmode) | |
95879c72 | 1082 | |
4ac005ba | 1083 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
ff97910d VY |
1084 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) |
1085 | ||
3f97cb0b AI |
1086 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
1087 | ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
1088 | || (MODE) == SFmode) | |
1089 | ||
1090 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1091 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 AI |
1092 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
1093 | || (MODE) == V4TImode) | |
1094 | ||
05416670 | 1095 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ |
9e4a4dd6 | 1096 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ |
40bd4bf9 JJ |
1097 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ |
1098 | || (MODE) == TFmode || (MODE) == V1TImode) | |
3f97cb0b | 1099 | |
ce998900 UB |
1100 | #define VALID_SSE2_REG_MODE(MODE) \ |
1101 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1102 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1103 | |
d9a5f180 | 1104 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1105 | ((MODE) == V1TImode || (MODE) == TImode \ |
1106 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
ce998900 | 1107 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1108 | |
47f339cf | 1109 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1110 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1111 | |
d9a5f180 | 1112 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1113 | ((MODE == V1DImode) || (MODE) == DImode \ |
1114 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1115 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1116 | |
05416670 UB |
1117 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1118 | ||
1119 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) | |
1120 | ||
d5e254e1 IE |
1121 | #define VALID_BND_REG_MODE(MODE) \ |
1122 | (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) | |
1123 | ||
ce998900 UB |
1124 | #define VALID_DFP_MODE_P(MODE) \ |
1125 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1126 | |
d9a5f180 | 1127 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1128 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1129 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1130 | |
d9a5f180 | 1131 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1132 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1133 | || (MODE) == DImode \ | |
1134 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1135 | || (MODE) == CDImode \ | |
1136 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1137 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1138 | |
822eda12 | 1139 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1140 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1141 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1142 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1143 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1144 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1145 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1146 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1147 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
1148 | || (MODE) == V16SFmode) | |
822eda12 | 1149 | |
05416670 UB |
1150 | #define X87_FLOAT_MODE_P(MODE) \ |
1151 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
85a77221 | 1152 | |
05416670 UB |
1153 | #define SSE_FLOAT_MODE_P(MODE) \ |
1154 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
1155 | ||
1156 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ | |
1157 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1158 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
9e4a4dd6 | 1159 | |
ff25ef99 ZD |
1160 | /* It is possible to write patterns to move flags; but until someone |
1161 | does it, */ | |
1162 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1163 | |
e075ae69 | 1164 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1165 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1166 | |
787dc842 JH |
1167 | Kill any attempts to combine saving of modes. */ |
1168 | ||
d9a5f180 GS |
1169 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1170 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1171 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1172 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
a60c3351 UB |
1173 | : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ |
1174 | && TARGET_PARTIAL_REG_STALL) \ | |
85a77221 | 1175 | || MASK_REGNO_P (REGNO)) ? SImode \ |
a60c3351 | 1176 | : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ |
85a77221 | 1177 | || MASK_REGNO_P (REGNO)) ? SImode \ |
d2836273 | 1178 | : (MODE)) |
ce998900 | 1179 | |
c98f8742 JVA |
1180 | /* Specify the registers used for certain standard purposes. |
1181 | The values of these macros are register numbers. */ | |
1182 | ||
1183 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1184 | register. The ordinary mov instructions won't work */ | |
1185 | /* #define PC_REGNUM */ | |
1186 | ||
05416670 UB |
1187 | /* Base register for access to arguments of the function. */ |
1188 | #define ARG_POINTER_REGNUM ARGP_REG | |
1189 | ||
c98f8742 | 1190 | /* Register to use for pushing function arguments. */ |
05416670 | 1191 | #define STACK_POINTER_REGNUM SP_REG |
c98f8742 JVA |
1192 | |
1193 | /* Base register for access to local variables of the function. */ | |
05416670 UB |
1194 | #define FRAME_POINTER_REGNUM FRAME_REG |
1195 | #define HARD_FRAME_POINTER_REGNUM BP_REG | |
564d80f4 | 1196 | |
05416670 UB |
1197 | #define FIRST_INT_REG AX_REG |
1198 | #define LAST_INT_REG SP_REG | |
c98f8742 | 1199 | |
05416670 UB |
1200 | #define FIRST_QI_REG AX_REG |
1201 | #define LAST_QI_REG BX_REG | |
c98f8742 JVA |
1202 | |
1203 | /* First & last stack-like regs */ | |
05416670 UB |
1204 | #define FIRST_STACK_REG ST0_REG |
1205 | #define LAST_STACK_REG ST7_REG | |
c98f8742 | 1206 | |
05416670 UB |
1207 | #define FIRST_SSE_REG XMM0_REG |
1208 | #define LAST_SSE_REG XMM7_REG | |
fce5a9f2 | 1209 | |
05416670 UB |
1210 | #define FIRST_MMX_REG MM0_REG |
1211 | #define LAST_MMX_REG MM7_REG | |
a7180f70 | 1212 | |
05416670 UB |
1213 | #define FIRST_REX_INT_REG R8_REG |
1214 | #define LAST_REX_INT_REG R15_REG | |
3f3f2124 | 1215 | |
05416670 UB |
1216 | #define FIRST_REX_SSE_REG XMM8_REG |
1217 | #define LAST_REX_SSE_REG XMM15_REG | |
3f3f2124 | 1218 | |
05416670 UB |
1219 | #define FIRST_EXT_REX_SSE_REG XMM16_REG |
1220 | #define LAST_EXT_REX_SSE_REG XMM31_REG | |
3f97cb0b | 1221 | |
05416670 UB |
1222 | #define FIRST_MASK_REG MASK0_REG |
1223 | #define LAST_MASK_REG MASK7_REG | |
85a77221 | 1224 | |
05416670 UB |
1225 | #define FIRST_BND_REG BND0_REG |
1226 | #define LAST_BND_REG BND3_REG | |
d5e254e1 | 1227 | |
aabcd309 | 1228 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1229 | requiring a frame pointer. */ |
1230 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1231 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1232 | #endif | |
1233 | ||
1234 | /* Make sure we can access arbitrary call frames. */ | |
1235 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 | 1236 | |
c98f8742 | 1237 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1238 | code access to data items. We don't use PIC pointer for 64bit |
1239 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1240 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1241 | |
1242 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1243 | the pic register when possible. The change is visible after the | |
1244 | prologue has been emitted. */ | |
1245 | ||
e8b5eb25 | 1246 | #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) |
bd09bdeb | 1247 | |
bcb21886 | 1248 | #define PIC_OFFSET_TABLE_REGNUM \ |
d290bb1d IE |
1249 | (ix86_use_pseudo_pic_reg () \ |
1250 | ? (pic_offset_table_rtx \ | |
1251 | ? INVALID_REGNUM \ | |
1252 | : REAL_PIC_OFFSET_TABLE_REGNUM) \ | |
1253 | : INVALID_REGNUM) | |
c98f8742 | 1254 | |
5fc0e5df KW |
1255 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1256 | ||
c51e6d85 | 1257 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1258 | #define MS_AGGREGATE_RETURN 0 |
1259 | ||
61fec9ff | 1260 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1261 | \f |
1262 | /* Define the classes of registers for register constraints in the | |
1263 | machine description. Also define ranges of constants. | |
1264 | ||
1265 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1266 | If there is more than one class, another class must be named NO_REGS | |
1267 | and contain no registers. | |
1268 | ||
1269 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1270 | another name such as ALL_REGS). This is the class of registers | |
1271 | that is allowed by "g" or "r" in a register constraint. | |
1272 | Also, registers outside this class are allocated only when | |
1273 | instructions express preferences for them. | |
1274 | ||
1275 | The classes must be numbered in nondecreasing order; that is, | |
1276 | a larger-numbered class must never be contained completely | |
2e24efd3 AM |
1277 | in a smaller-numbered class. This is why CLOBBERED_REGS class |
1278 | is listed early, even though in 64-bit mode it contains more | |
1279 | registers than just %eax, %ecx, %edx. | |
c98f8742 JVA |
1280 | |
1281 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1282 | class that represents their union. |
1283 | ||
1284 | It might seem that class BREG is unnecessary, since no useful 386 | |
1285 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1286 | and the "b" register constraint is useful in asms for syscalls. |
1287 | ||
03c259ad | 1288 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1289 | |
1290 | enum reg_class | |
1291 | { | |
1292 | NO_REGS, | |
e075ae69 | 1293 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1294 | AD_REGS, /* %eax/%edx for DImode */ |
2e24efd3 | 1295 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
c98f8742 | 1296 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1297 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
de86ff8f | 1298 | TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ |
c98f8742 | 1299 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1300 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
63001560 UB |
1301 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1302 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1303 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1304 | FLOAT_REGS, | |
06f4e35d | 1305 | SSE_FIRST_REG, |
45392c76 | 1306 | NO_REX_SSE_REGS, |
a7180f70 | 1307 | SSE_REGS, |
3f97cb0b | 1308 | EVEX_SSE_REGS, |
d5e254e1 | 1309 | BND_REGS, |
3f97cb0b | 1310 | ALL_SSE_REGS, |
a7180f70 | 1311 | MMX_REGS, |
446988df JH |
1312 | FP_TOP_SSE_REGS, |
1313 | FP_SECOND_SSE_REGS, | |
1314 | FLOAT_SSE_REGS, | |
1315 | FLOAT_INT_REGS, | |
1316 | INT_SSE_REGS, | |
1317 | FLOAT_INT_SSE_REGS, | |
85a77221 AI |
1318 | MASK_EVEX_REGS, |
1319 | MASK_REGS, | |
5fbb13a7 | 1320 | MOD4_SSE_REGS, |
c98f8742 JVA |
1321 | ALL_REGS, LIM_REG_CLASSES |
1322 | }; | |
1323 | ||
d9a5f180 GS |
1324 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1325 | ||
1326 | #define INTEGER_CLASS_P(CLASS) \ | |
1327 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1328 | #define FLOAT_CLASS_P(CLASS) \ | |
1329 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1330 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1331 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1332 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1333 | ((CLASS) == MMX_REGS) |
4ed04e93 UB |
1334 | #define MASK_CLASS_P(CLASS) \ |
1335 | reg_class_subset_p ((CLASS), MASK_REGS) | |
d9a5f180 GS |
1336 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1337 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1338 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1339 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1340 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1341 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1342 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1343 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 AI |
1344 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
1345 | reg_classes_intersect_p ((CLASS), MASK_REGS) | |
d9a5f180 GS |
1346 | |
1347 | #define Q_CLASS_P(CLASS) \ | |
1348 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1349 | |
0bd72901 UB |
1350 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1351 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1352 | ||
43f3a59d | 1353 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1354 | |
1355 | #define REG_CLASS_NAMES \ | |
1356 | { "NO_REGS", \ | |
ab408a86 | 1357 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1358 | "SIREG", "DIREG", \ |
e075ae69 | 1359 | "AD_REGS", \ |
2e24efd3 | 1360 | "CLOBBERED_REGS", \ |
e075ae69 | 1361 | "Q_REGS", "NON_Q_REGS", \ |
de86ff8f | 1362 | "TLS_GOTBASE_REGS", \ |
c98f8742 | 1363 | "INDEX_REGS", \ |
3f3f2124 | 1364 | "LEGACY_REGS", \ |
c98f8742 JVA |
1365 | "GENERAL_REGS", \ |
1366 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1367 | "FLOAT_REGS", \ | |
cb482895 | 1368 | "SSE_FIRST_REG", \ |
45392c76 | 1369 | "NO_REX_SSE_REGS", \ |
a7180f70 | 1370 | "SSE_REGS", \ |
3f97cb0b | 1371 | "EVEX_SSE_REGS", \ |
d5e254e1 | 1372 | "BND_REGS", \ |
3f97cb0b | 1373 | "ALL_SSE_REGS", \ |
a7180f70 | 1374 | "MMX_REGS", \ |
446988df JH |
1375 | "FP_TOP_SSE_REGS", \ |
1376 | "FP_SECOND_SSE_REGS", \ | |
1377 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1378 | "FLOAT_INT_REGS", \ |
446988df JH |
1379 | "INT_SSE_REGS", \ |
1380 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 AI |
1381 | "MASK_EVEX_REGS", \ |
1382 | "MASK_REGS", \ | |
cae67b80 | 1383 | "MOD4_SSE_REGS", \ |
c98f8742 JVA |
1384 | "ALL_REGS" } |
1385 | ||
ac2e563f RH |
1386 | /* Define which registers fit in which classes. This is an initializer |
1387 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1388 | ||
621bc046 UB |
1389 | Note that CLOBBERED_REGS are calculated by |
1390 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1391 | |
3f97cb0b | 1392 | #define REG_CLASS_CONTENTS \ |
d5e254e1 IE |
1393 | { { 0x00, 0x0, 0x0 }, \ |
1394 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1395 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1396 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1397 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1398 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1399 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1400 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
2e24efd3 | 1401 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ |
d5e254e1 IE |
1402 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ |
1403 | { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ | |
de86ff8f | 1404 | { 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \ |
d5e254e1 IE |
1405 | { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ |
1406 | { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
d5e254e1 IE |
1407 | { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ |
1408 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1409 | { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1410 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1411 | { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
45392c76 | 1412 | { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ |
d5e254e1 IE |
1413 | { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ |
1414 | { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ | |
1415 | { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ | |
1416 | { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ | |
1417 | { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ | |
1418 | { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ | |
1419 | { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ | |
1420 | { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ | |
1421 | { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1422 | { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ | |
1423 | { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ | |
5fbb13a7 | 1424 | { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ |
d5e254e1 | 1425 | { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ |
5fbb13a7 KY |
1426 | { 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \ |
1427 | { 0xffffffff,0xffffffff,0x1ffff } \ | |
e075ae69 | 1428 | } |
c98f8742 JVA |
1429 | |
1430 | /* The same information, inverted: | |
1431 | Return the class number of the smallest class containing | |
1432 | reg number REGNO. This could be a conditional expression | |
1433 | or could index an array. */ | |
1434 | ||
1a6e82b8 | 1435 | #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) |
c98f8742 | 1436 | |
42db504c SB |
1437 | /* When this hook returns true for MODE, the compiler allows |
1438 | registers explicitly used in the rtl to be used as spill registers | |
1439 | but prevents the compiler from extending the lifetime of these | |
1440 | registers. */ | |
1441 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1442 | |
fc27f749 | 1443 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
05416670 UB |
1444 | #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) |
1445 | ||
1446 | #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) | |
1447 | #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) | |
1448 | ||
1449 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
1450 | #define REX_INT_REGNO_P(N) \ | |
1451 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1452 | |
58b0b34c | 1453 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 | 1454 | #define GENERAL_REGNO_P(N) \ |
58b0b34c | 1455 | (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) |
3f3f2124 | 1456 | |
fc27f749 UB |
1457 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1458 | #define ANY_QI_REGNO_P(N) \ | |
1459 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1460 | |
66aaf16f UB |
1461 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1462 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1463 | |
fc27f749 | 1464 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1465 | #define SSE_REGNO_P(N) \ |
1466 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
3f97cb0b AI |
1467 | || REX_SSE_REGNO_P (N) \ |
1468 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1469 | |
4977bab6 | 1470 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1471 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1472 | |
0a48088a IT |
1473 | #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) |
1474 | ||
3f97cb0b AI |
1475 | #define EXT_REX_SSE_REGNO_P(N) \ |
1476 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1477 | ||
05416670 UB |
1478 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
1479 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) | |
3f97cb0b | 1480 | |
9e4a4dd6 | 1481 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 | 1482 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
446988df | 1483 | |
fc27f749 | 1484 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1485 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1486 | |
e075ae69 RH |
1487 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1488 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1489 | ||
58b0b34c | 1490 | #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) |
d5e254e1 | 1491 | #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) |
d5e254e1 | 1492 | |
5fbb13a7 KY |
1493 | #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) |
1494 | #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ | |
1495 | || (N) == XMM4_REG \ | |
1496 | || (N) == XMM8_REG \ | |
1497 | || (N) == XMM12_REG \ | |
1498 | || (N) == XMM16_REG \ | |
1499 | || (N) == XMM20_REG \ | |
1500 | || (N) == XMM24_REG \ | |
1501 | || (N) == XMM28_REG) | |
1502 | ||
05416670 UB |
1503 | /* First floating point reg */ |
1504 | #define FIRST_FLOAT_REG FIRST_STACK_REG | |
1505 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) | |
1506 | ||
1507 | #define SSE_REGNO(N) \ | |
1508 | ((N) < 8 ? FIRST_SSE_REG + (N) \ | |
1509 | : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ | |
1510 | : (FIRST_EXT_REX_SSE_REG + (N) - 16)) | |
1511 | ||
c98f8742 JVA |
1512 | /* The class value for index registers, and the one for base regs. */ |
1513 | ||
1514 | #define INDEX_REG_CLASS INDEX_REGS | |
1515 | #define BASE_REG_CLASS GENERAL_REGS | |
c98f8742 JVA |
1516 | \f |
1517 | /* Stack layout; function entry, exit and calling. */ | |
1518 | ||
1519 | /* Define this if pushing a word on the stack | |
1520 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1521 | #define STACK_GROWS_DOWNWARD 1 |
c98f8742 | 1522 | |
a4d05547 | 1523 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1524 | is at the high-address end of the local variables; |
1525 | that is, each additional local variable allocated | |
1526 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1527 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1528 | |
1529 | /* Offset within stack frame to start allocating local variables at. | |
1530 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1531 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1532 | of the first local allocated. */ | |
1533 | #define STARTING_FRAME_OFFSET 0 | |
1534 | ||
8c2b2fae UB |
1535 | /* If we generate an insn to push BYTES bytes, this says how many the stack |
1536 | pointer really advances by. On 386, we have pushw instruction that | |
1537 | decrements by exactly 2 no matter what the position was, there is no pushb. | |
1538 | ||
1539 | But as CIE data alignment factor on this arch is -4 for 32bit targets | |
1540 | and -8 for 64bit targets, we need to make sure all stack pointer adjustments | |
1541 | are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ | |
c98f8742 | 1542 | |
1a6e82b8 | 1543 | #define PUSH_ROUNDING(BYTES) ROUND_UP ((BYTES), UNITS_PER_WORD) |
8c2b2fae UB |
1544 | |
1545 | /* If defined, the maximum amount of space required for outgoing arguments | |
1546 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1547 | No space will be pushed onto the stack for each call; instead, the | |
1548 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1549 | |
1550 | In 32bit mode enabling argument accumulation results in about 5% code size | |
56aae4b7 | 1551 | growth because move instructions are less compact than push. In 64bit |
41ee845b JH |
1552 | mode the difference is less drastic but visible. |
1553 | ||
1554 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1555 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1556 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1557 | |
1558 | With the 64-bit MS ABI, we can generate correct code with or without | |
1559 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1560 | generated without accumulated args is terrible. | |
41ee845b JH |
1561 | |
1562 | If stack probes are required, the space used for large function | |
1563 | arguments on the stack must also be probed, so enable | |
f8071c05 L |
1564 | -maccumulate-outgoing-args so this happens in the prologue. |
1565 | ||
1566 | We must use argument accumulation in interrupt function if stack | |
1567 | may be realigned to avoid DRAP. */ | |
f73ad30e | 1568 | |
6c6094f1 | 1569 | #define ACCUMULATE_OUTGOING_ARGS \ |
f8071c05 L |
1570 | ((TARGET_ACCUMULATE_OUTGOING_ARGS \ |
1571 | && optimize_function_for_speed_p (cfun)) \ | |
1572 | || (cfun->machine->func_type != TYPE_NORMAL \ | |
1573 | && crtl->stack_realign_needed) \ | |
1574 | || TARGET_STACK_PROBE \ | |
1575 | || TARGET_64BIT_MS_ABI \ | |
ff734e26 | 1576 | || (TARGET_MACHO && crtl->profile)) |
f73ad30e JH |
1577 | |
1578 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1579 | instructions to pass outgoing arguments. */ | |
1580 | ||
1581 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1582 | ||
2da4124d L |
1583 | /* We want the stack and args grow in opposite directions, even if |
1584 | PUSH_ARGS is 0. */ | |
1585 | #define PUSH_ARGS_REVERSED 1 | |
1586 | ||
c98f8742 JVA |
1587 | /* Offset of first parameter from the argument pointer register value. */ |
1588 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1589 | ||
a7180f70 BS |
1590 | /* Define this macro if functions should assume that stack space has been |
1591 | allocated for arguments even when their values are passed in registers. | |
1592 | ||
1593 | The value of this macro is the size, in bytes, of the area reserved for | |
1594 | arguments passed in registers for the function represented by FNDECL. | |
1595 | ||
1596 | This space can be allocated by the caller, or be a part of the | |
1597 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1598 | which. */ | |
7c800926 KT |
1599 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1600 | ||
4ae8027b | 1601 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1602 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1603 | |
c98f8742 JVA |
1604 | /* Define how to find the value returned by a library function |
1605 | assuming the value has mode MODE. */ | |
1606 | ||
4ae8027b | 1607 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1608 | |
e9125c09 TW |
1609 | /* Define the size of the result block used for communication between |
1610 | untyped_call and untyped_return. The block contains a DImode value | |
1611 | followed by the block used by fnsave and frstor. */ | |
1612 | ||
1613 | #define APPLY_RESULT_SIZE (8+108) | |
1614 | ||
b08de47e | 1615 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1616 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1617 | |
1618 | /* Define a data type for recording info about an argument list | |
1619 | during the scan of that argument list. This data type should | |
1620 | hold all necessary information about the function itself | |
1621 | and about the args processed so far, enough to enable macros | |
b08de47e | 1622 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1623 | |
e075ae69 | 1624 | typedef struct ix86_args { |
fa283935 | 1625 | int words; /* # words passed so far */ |
b08de47e MM |
1626 | int nregs; /* # registers available for passing */ |
1627 | int regno; /* next available register number */ | |
3e65f251 KT |
1628 | int fastcall; /* fastcall or thiscall calling convention |
1629 | is used */ | |
fa283935 | 1630 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1631 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1632 | int warn_avx512f; /* True when we want to warn |
1633 | about AVX512F ABI. */ | |
95879c72 | 1634 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1635 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1636 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1637 | int sse_regno; /* next available sse register number */ | |
1638 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1639 | int mmx_nregs; /* # mmx registers available for passing */ |
1640 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1641 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1642 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1643 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1644 | SFmode/DFmode arguments should be passed | |
1645 | in SSE registers. Otherwise 0. */ | |
d5e254e1 IE |
1646 | int bnd_regno; /* next available bnd register number */ |
1647 | int bnds_in_bt; /* number of bounds expected in BT. */ | |
1648 | int force_bnd_pass; /* number of bounds expected for stdarg arg. */ | |
1649 | int stdarg; /* Set to 1 if function is stdarg. */ | |
51212b32 | 1650 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1651 | MS_ABI for ms abi. */ |
e66fc623 | 1652 | tree decl; /* Callee decl. */ |
b08de47e | 1653 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1654 | |
1655 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1656 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1657 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1658 | |
0f6937fe | 1659 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1660 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1661 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1662 | |
c98f8742 JVA |
1663 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1664 | for profiling a function entry. */ | |
1665 | ||
1a6e82b8 UB |
1666 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1667 | x86_function_profiler ((FILE), (LABELNO)) | |
a5fa1ecd JH |
1668 | |
1669 | #define MCOUNT_NAME "_mcount" | |
1670 | ||
3c5273a9 KT |
1671 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1672 | ||
a5fa1ecd | 1673 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1674 | |
1675 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1676 | the stack pointer does not matter. The value is tested only in | |
1677 | functions that have frame pointers. | |
1678 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1679 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1680 | we have to restore it ourselves from the frame pointer, in order to |
1681 | use pop */ | |
1682 | ||
1683 | #define EXIT_IGNORE_STACK 1 | |
1684 | ||
f8071c05 L |
1685 | /* Define this macro as a C expression that is nonzero for registers |
1686 | used by the epilogue or the `return' pattern. */ | |
1687 | ||
1688 | #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) | |
1689 | ||
c98f8742 JVA |
1690 | /* Output assembler code for a block containing the constant parts |
1691 | of a trampoline, leaving space for the variable parts. */ | |
1692 | ||
a269a03c | 1693 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1694 | mov #STATIC,ecx |
a269a03c JC |
1695 | jmp FUNCTION |
1696 | The trampoline is generated entirely at runtime. The operand of JMP | |
1697 | is the address of FUNCTION relative to the instruction following the | |
1698 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1699 | |
1700 | /* Length in units of the trampoline for entering a nested function. */ | |
1701 | ||
3452586b | 1702 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) |
c98f8742 JVA |
1703 | \f |
1704 | /* Definitions for register eliminations. | |
1705 | ||
1706 | This is an array of structures. Each structure initializes one pair | |
1707 | of eliminable registers. The "from" register number is given first, | |
1708 | followed by "to". Eliminations of the same "from" register are listed | |
1709 | in order of preference. | |
1710 | ||
afc2cd05 NC |
1711 | There are two registers that can always be eliminated on the i386. |
1712 | The frame pointer and the arg pointer can be replaced by either the | |
1713 | hard frame pointer or to the stack pointer, depending upon the | |
1714 | circumstances. The hard frame pointer is not used before reload and | |
1715 | so it is not eligible for elimination. */ | |
c98f8742 | 1716 | |
564d80f4 JH |
1717 | #define ELIMINABLE_REGS \ |
1718 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1719 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1720 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1721 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1722 | |
c98f8742 JVA |
1723 | /* Define the offset between two registers, one to be eliminated, and the other |
1724 | its replacement, at the start of a routine. */ | |
1725 | ||
d9a5f180 GS |
1726 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1727 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1728 | \f |
1729 | /* Addressing modes, and classification of registers for them. */ | |
1730 | ||
c98f8742 JVA |
1731 | /* Macros to check register numbers against specific register classes. */ |
1732 | ||
1733 | /* These assume that REGNO is a hard or pseudo reg number. | |
1734 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1735 | or a pseudo reg currently allocated to a suitable hard reg. | |
1736 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1737 | has been allocated, which happens in reginfo.c during register |
1738 | allocation. */ | |
c98f8742 | 1739 | |
3f3f2124 JH |
1740 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1741 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1742 | || REX_INT_REGNO_P (REGNO) \ |
1743 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1744 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1745 | |
3f3f2124 | 1746 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1747 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1748 | || (REGNO) == ARG_POINTER_REGNUM \ |
1749 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1750 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1751 | |
c98f8742 JVA |
1752 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1753 | and check its validity for a certain class. | |
1754 | We have two alternate definitions for each of them. | |
1755 | The usual definition accepts all pseudo regs; the other rejects | |
1756 | them unless they have been allocated suitable hard regs. | |
1757 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1758 | ||
1759 | Most source files want to accept pseudo regs in the hope that | |
1760 | they will get allocated to the class that the insn wants them to be in. | |
1761 | Source files for reload pass need to be strict. | |
1762 | After reload, it makes no difference, since pseudo regs have | |
1763 | been eliminated by then. */ | |
1764 | ||
c98f8742 | 1765 | |
ff482c8d | 1766 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1767 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1768 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1769 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1770 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1771 | ||
3b3c6a3f | 1772 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1773 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1774 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1775 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1776 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1777 | |
3b3c6a3f MM |
1778 | /* Strict versions, hard registers only */ |
1779 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1780 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1781 | |
3b3c6a3f | 1782 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1783 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1784 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1785 | |
1786 | #else | |
d9a5f180 GS |
1787 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1788 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1789 | #endif |
1790 | ||
331d9186 | 1791 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1792 | that is a valid memory address for an instruction. |
1793 | The MODE argument is the machine mode for the MEM expression | |
1794 | that wants to use this address. | |
1795 | ||
331d9186 | 1796 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1797 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1798 | ||
1799 | See legitimize_pic_address in i386.c for details as to what | |
1800 | constitutes a legitimate address when -fpic is used. */ | |
1801 | ||
1802 | #define MAX_REGS_PER_ADDRESS 2 | |
1803 | ||
f996902d | 1804 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1805 | |
b949ea8b JW |
1806 | /* If defined, a C expression to determine the base term of address X. |
1807 | This macro is used in only one place: `find_base_term' in alias.c. | |
1808 | ||
1809 | It is always safe for this macro to not be defined. It exists so | |
1810 | that alias analysis can understand machine-dependent addresses. | |
1811 | ||
1812 | The typical use of this macro is to handle addresses containing | |
1813 | a label_ref or symbol_ref within an UNSPEC. */ | |
1814 | ||
d9a5f180 | 1815 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1816 | |
c98f8742 | 1817 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1818 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1819 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1820 | ||
f996902d | 1821 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1822 | |
1823 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1824 | (GET_CODE (X) == SYMBOL_REF \ |
1825 | || GET_CODE (X) == LABEL_REF \ | |
1826 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1827 | \f |
b08de47e MM |
1828 | /* Max number of args passed in registers. If this is more than 3, we will |
1829 | have problems with ebx (register #4), since it is a caller save register and | |
1830 | is also used as the pic register in ELF. So for now, don't allow more than | |
1831 | 3 registers to be passed in registers. */ | |
1832 | ||
7c800926 KT |
1833 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1834 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1835 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1836 | |
72fa3605 | 1837 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1838 | |
4ae8027b | 1839 | #define REGPARM_MAX \ |
2824d6e5 UB |
1840 | (TARGET_64BIT \ |
1841 | ? (TARGET_64BIT_MS_ABI \ | |
1842 | ? X86_64_MS_REGPARM_MAX \ | |
1843 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1844 | : X86_32_REGPARM_MAX) |
d2836273 | 1845 | |
72fa3605 UB |
1846 | #define X86_64_SSE_REGPARM_MAX 8 |
1847 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1848 | ||
b6010cab | 1849 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1850 | |
4ae8027b | 1851 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1852 | (TARGET_64BIT \ |
1853 | ? (TARGET_64BIT_MS_ABI \ | |
1854 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1855 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1856 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 JH |
1857 | |
1858 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
c98f8742 JVA |
1859 | \f |
1860 | /* Specify the machine mode that this machine uses | |
1861 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1862 | #define CASE_VECTOR_MODE \ |
6025b127 | 1863 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1864 | |
c98f8742 JVA |
1865 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1866 | #define DEFAULT_SIGNED_CHAR 1 | |
1867 | ||
1868 | /* Max number of bytes we can move from memory to memory | |
1869 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1870 | #define MOVE_MAX 16 |
1871 | ||
1872 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1873 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
df7ec09f L |
1874 | number of bytes we can move with a single instruction. |
1875 | ||
1876 | ??? We should use TImode in 32-bit mode and use OImode or XImode | |
1877 | if they are available. But since by_pieces_ninsns determines the | |
1878 | widest mode with MAX_FIXED_MODE_SIZE, we can only use TImode in | |
1879 | 64-bit mode. */ | |
1880 | #define MOVE_MAX_PIECES \ | |
1881 | ((TARGET_64BIT \ | |
1882 | && TARGET_SSE2 \ | |
1883 | && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ | |
1884 | && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ | |
1885 | ? GET_MODE_SIZE (TImode) : UNITS_PER_WORD) | |
c98f8742 | 1886 | |
7e24ffc9 | 1887 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1888 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1889 | Increasing the value will always make code faster, but eventually |
1890 | incurs high cost in increased code size. | |
c98f8742 | 1891 | |
e2e52e1b | 1892 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1893 | |
e04ad03d | 1894 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1895 | |
45d78e7f JJ |
1896 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1897 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1898 | ||
e04ad03d | 1899 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1900 | |
53f00dde UB |
1901 | /* Define if shifts truncate the shift count which implies one can |
1902 | omit a sign-extension or zero-extension of a shift count. | |
1903 | ||
1904 | On i386, shifts do truncate the count. But bit test instructions | |
1905 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1906 | |
1907 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1908 | ||
d9f32422 JH |
1909 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1910 | TYPE and which has the specified mode and signedness is to be | |
1911 | stored in a register. This macro is only called when TYPE is a | |
1912 | scalar type. | |
1913 | ||
f710504c | 1914 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1915 | quantities to SImode. The choice depends on target type. */ |
1916 | ||
1917 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1918 | do { \ |
d9f32422 JH |
1919 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1920 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1921 | (MODE) = SImode; \ |
1922 | } while (0) | |
d9f32422 | 1923 | |
c98f8742 JVA |
1924 | /* Specify the machine mode that pointers have. |
1925 | After generation of rtl, the compiler makes no further distinction | |
1926 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1927 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1928 | |
d5e254e1 IE |
1929 | /* Specify the machine mode that bounds have. */ |
1930 | #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) | |
1931 | ||
f0ea7581 L |
1932 | /* A C expression whose value is zero if pointers that need to be extended |
1933 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1934 | greater then zero if they are zero-extended and less then zero if the | |
1935 | ptr_extend instruction should be used. */ | |
1936 | ||
1937 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1938 | ||
c98f8742 JVA |
1939 | /* A function address in a call instruction |
1940 | is a byte address (for indexing purposes) | |
1941 | so give the MEM rtx a byte's mode. */ | |
1942 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1943 | \f |
d4ba09c0 | 1944 | |
d4ba09c0 SC |
1945 | /* A C expression for the cost of a branch instruction. A value of 1 |
1946 | is the default; other values are interpreted relative to that. */ | |
1947 | ||
3a4fd356 JH |
1948 | #define BRANCH_COST(speed_p, predictable_p) \ |
1949 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1950 | |
e327d1a3 L |
1951 | /* An integer expression for the size in bits of the largest integer machine |
1952 | mode that should actually be used. We allow pairs of registers. */ | |
1953 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1954 | ||
d4ba09c0 SC |
1955 | /* Define this macro as a C expression which is nonzero if accessing |
1956 | less than a word of memory (i.e. a `char' or a `short') is no | |
1957 | faster than accessing a word of memory, i.e., if such access | |
1958 | require more than one instruction or if there is no difference in | |
1959 | cost between byte and (aligned) word loads. | |
1960 | ||
1961 | When this macro is not defined, the compiler will access a field by | |
1962 | finding the smallest containing object; when it is defined, a | |
1963 | fullword load will be used if alignment permits. Unless bytes | |
1964 | accesses are faster than word accesses, using word accesses is | |
1965 | preferable since it may eliminate subsequent memory access if | |
1966 | subsequent accesses occur to other fields in the same word of the | |
1967 | structure, but to different bytes. */ | |
1968 | ||
1969 | #define SLOW_BYTE_ACCESS 0 | |
1970 | ||
1971 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1972 | #define SLOW_SHORT_ACCESS 0 | |
1973 | ||
d4ba09c0 SC |
1974 | /* Define this macro if it is as good or better to call a constant |
1975 | function address than to call an address kept in a register. | |
1976 | ||
1977 | Desirable on the 386 because a CALL with a constant address is | |
1978 | faster than one with a register address. */ | |
1979 | ||
1e8552c2 | 1980 | #define NO_FUNCTION_CSE 1 |
c98f8742 | 1981 | \f |
c572e5ba JVA |
1982 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1983 | return the mode to be used for the comparison. | |
1984 | ||
1985 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 1986 | VOIDmode should be used in all other cases. |
c572e5ba | 1987 | |
16189740 | 1988 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 1989 | possible, to allow for more combinations. */ |
c98f8742 | 1990 | |
d9a5f180 | 1991 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 1992 | |
9cd10576 | 1993 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
1994 | reversed. */ |
1995 | ||
1996 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1997 | ||
1998 | /* A C expression whose value is reversed condition code of the CODE for | |
1999 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2000 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2001 | |
c98f8742 JVA |
2002 | \f |
2003 | /* Control the assembler format that we output, to the extent | |
2004 | this does not vary between assemblers. */ | |
2005 | ||
2006 | /* How to refer to registers in assembler output. | |
892a2d68 | 2007 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2008 | |
a7b376ee | 2009 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2010 | For non floating point regs, the following are the HImode names. |
2011 | ||
2012 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
2013 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
2014 | "y" code. */ | |
c98f8742 | 2015 | |
a7180f70 BS |
2016 | #define HI_REGISTER_NAMES \ |
2017 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2018 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2019 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2020 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2021 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 2022 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
2023 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
2024 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
2025 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
2026 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 2027 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
d5e254e1 IE |
2028 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ |
2029 | "bnd0", "bnd1", "bnd2", "bnd3" } | |
a7180f70 | 2030 | |
c98f8742 JVA |
2031 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2032 | ||
2033 | /* Table of additional register names to use in user input. */ | |
2034 | ||
2035 | #define ADDITIONAL_REGISTER_NAMES \ | |
7c831c4d KY |
2036 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2037 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2038 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
2039 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
2040 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2041 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ | |
2042 | { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ | |
2043 | { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ | |
2044 | { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ | |
2045 | { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ | |
2046 | { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ | |
2047 | { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ | |
2048 | { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ | |
2049 | { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ | |
2050 | { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ | |
2051 | { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ | |
2052 | { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ | |
2053 | { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ | |
2054 | { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ | |
2055 | { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ | |
2056 | { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ | |
2057 | { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } | |
c98f8742 JVA |
2058 | |
2059 | /* Note we are omitting these since currently I don't know how | |
2060 | to get gcc to use these, since they want the same but different | |
2061 | number as al, and ax. | |
2062 | */ | |
2063 | ||
c98f8742 | 2064 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2065 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2066 | |
2067 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2068 | of regs 0 through 3. */ |
c98f8742 JVA |
2069 | |
2070 | #define QI_HIGH_REGISTER_NAMES \ | |
2071 | {"ah", "dh", "ch", "bh", } | |
2072 | ||
2073 | /* How to renumber registers for dbx and gdb. */ | |
2074 | ||
d9a5f180 GS |
2075 | #define DBX_REGISTER_NUMBER(N) \ |
2076 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2077 | |
9a82e702 MS |
2078 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2079 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2080 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2081 | |
469ac993 JM |
2082 | /* Before the prologue, RA is at 0(%esp). */ |
2083 | #define INCOMING_RETURN_ADDR_RTX \ | |
2efb4214 | 2084 | gen_rtx_MEM (Pmode, stack_pointer_rtx) |
fce5a9f2 | 2085 | |
e414ab29 | 2086 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1a6e82b8 UB |
2087 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2088 | ((COUNT) == 0 \ | |
2089 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ | |
2090 | -UNITS_PER_WORD)) \ | |
2091 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) | |
e414ab29 | 2092 | |
892a2d68 | 2093 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2094 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2095 | |
a10b3cf1 L |
2096 | /* Before the prologue, there are return address and error code for |
2097 | exception handler on the top of the frame. */ | |
2098 | #define INCOMING_FRAME_SP_OFFSET \ | |
2099 | (cfun->machine->func_type == TYPE_EXCEPTION \ | |
2100 | ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) | |
a6ab3aad | 2101 | |
1020a5ab | 2102 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2103 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2104 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2105 | |
ad919812 | 2106 | |
e4c4ebeb RH |
2107 | /* Select a format to encode pointers in exception handling data. CODE |
2108 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2109 | true if the symbol may be affected by dynamic relocations. | |
2110 | ||
2111 | ??? All x86 object file formats are capable of representing this. | |
2112 | After all, the relocation needed is the same as for the call insn. | |
2113 | Whether or not a particular assembler allows us to enter such, I | |
2114 | guess we'll have to see. */ | |
d9a5f180 | 2115 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2116 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2117 | |
ec1895c1 UB |
2118 | /* These are a couple of extensions to the formats accepted |
2119 | by asm_fprintf: | |
2120 | %z prints out opcode suffix for word-mode instruction | |
2121 | %r prints out word-mode name for reg_names[arg] */ | |
2122 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
2123 | case 'z': \ | |
2124 | fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ | |
2125 | break; \ | |
2126 | \ | |
2127 | case 'r': \ | |
2128 | { \ | |
2129 | unsigned int regno = va_arg ((ARGS), int); \ | |
2130 | if (LEGACY_INT_REGNO_P (regno)) \ | |
2131 | fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ | |
2132 | fputs (reg_names[regno], (FILE)); \ | |
2133 | break; \ | |
2134 | } | |
2135 | ||
2136 | /* This is how to output an insn to push a register on the stack. */ | |
2137 | ||
2138 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
2139 | asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) | |
2140 | ||
2141 | /* This is how to output an insn to pop a register from the stack. */ | |
c98f8742 | 2142 | |
d9a5f180 | 2143 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
ec1895c1 | 2144 | asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) |
c98f8742 | 2145 | |
f88c65f7 | 2146 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2147 | |
2148 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2149 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2150 | |
f88c65f7 | 2151 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2152 | |
33f7f353 | 2153 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2154 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2155 | |
63001560 | 2156 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2157 | |
2158 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2159 | { \ | |
2160 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2161 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2162 | } |
2163 | ||
2164 | /* A C statement or statements which output an assembler instruction | |
2165 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2166 | variable of type `char *' which points to the opcode name in | |
2167 | its "internal" form--the form that is written in the machine | |
2168 | description. */ | |
2169 | ||
2170 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2171 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2172 | ||
6a90d232 L |
2173 | /* A C statement to output to the stdio stream FILE an assembler |
2174 | command to pad the location counter to a multiple of 1<<LOG | |
2175 | bytes if it is within MAX_SKIP bytes. */ | |
2176 | ||
2177 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
2178 | #undef ASM_OUTPUT_MAX_SKIP_PAD | |
2179 | #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ | |
2180 | if ((LOG) != 0) \ | |
2181 | { \ | |
2182 | if ((MAX_SKIP) == 0) \ | |
2183 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2184 | else \ | |
2185 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ | |
2186 | } | |
2187 | #endif | |
2188 | ||
135a687e KT |
2189 | /* Write the extra assembler code needed to declare a function |
2190 | properly. */ | |
2191 | ||
2192 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2193 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
1a6e82b8 | 2194 | ix86_asm_output_function_label ((FILE), (NAME), (DECL)) |
135a687e | 2195 | |
f7288899 EC |
2196 | /* Under some conditions we need jump tables in the text section, |
2197 | because the assembler cannot handle label differences between | |
2198 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2199 | |
2200 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2201 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2202 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2203 | |
cea3bd3e RH |
2204 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2205 | and switch back. For x86 we do this only to save a few bytes that | |
2206 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2207 | #define CRT_MKSTR2(VAL) #VAL |
2208 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2209 | ||
2210 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2211 | asm (SECTION_OP "\n\t" \ | |
2212 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2213 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2214 | |
2215 | /* Default threshold for putting data in large sections | |
2216 | with x86-64 medium memory model */ | |
2217 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
776280c4 UB |
2218 | |
2219 | /* Adjust the length of the insn with the length of BND prefix. */ | |
0453025d UB |
2220 | |
2221 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2222 | do { \ | |
2223 | if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \ | |
2224 | && get_attr_maybe_prefix_bnd (INSN)) \ | |
2225 | LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ | |
776280c4 | 2226 | } while (0) |
74b42c8b | 2227 | \f |
b97de419 L |
2228 | /* Which processor to tune code generation for. These must be in sync |
2229 | with processor_target_table in i386.c. */ | |
5bf0ebab RH |
2230 | |
2231 | enum processor_type | |
2232 | { | |
b97de419 L |
2233 | PROCESSOR_GENERIC = 0, |
2234 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2235 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2236 | PROCESSOR_PENTIUM, | |
2d6b2e28 | 2237 | PROCESSOR_LAKEMONT, |
5bf0ebab | 2238 | PROCESSOR_PENTIUMPRO, |
5bf0ebab | 2239 | PROCESSOR_PENTIUM4, |
89c43c0a | 2240 | PROCESSOR_NOCONA, |
340ef734 | 2241 | PROCESSOR_CORE2, |
d3c11974 L |
2242 | PROCESSOR_NEHALEM, |
2243 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2244 | PROCESSOR_HASWELL, |
d3c11974 L |
2245 | PROCESSOR_BONNELL, |
2246 | PROCESSOR_SILVERMONT, | |
52747219 | 2247 | PROCESSOR_KNL, |
cace2309 | 2248 | PROCESSOR_KNM, |
06caf59d | 2249 | PROCESSOR_SKYLAKE_AVX512, |
9a7f94d7 | 2250 | PROCESSOR_INTEL, |
b97de419 L |
2251 | PROCESSOR_GEODE, |
2252 | PROCESSOR_K6, | |
2253 | PROCESSOR_ATHLON, | |
2254 | PROCESSOR_K8, | |
21efb4d4 | 2255 | PROCESSOR_AMDFAM10, |
1133125e | 2256 | PROCESSOR_BDVER1, |
4d652a18 | 2257 | PROCESSOR_BDVER2, |
eb2f2b44 | 2258 | PROCESSOR_BDVER3, |
ed97ad47 | 2259 | PROCESSOR_BDVER4, |
14b52538 | 2260 | PROCESSOR_BTVER1, |
e32bfc16 | 2261 | PROCESSOR_BTVER2, |
9ce29eb0 | 2262 | PROCESSOR_ZNVER1, |
5bf0ebab RH |
2263 | PROCESSOR_max |
2264 | }; | |
2265 | ||
9e555526 | 2266 | extern enum processor_type ix86_tune; |
5bf0ebab | 2267 | extern enum processor_type ix86_arch; |
5bf0ebab | 2268 | |
8362f420 JH |
2269 | /* Size of the RED_ZONE area. */ |
2270 | #define RED_ZONE_SIZE 128 | |
2271 | /* Reserved area of the red zone for temporaries. */ | |
2272 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2273 | |
95899b34 | 2274 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2275 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2276 | |
2277 | /* Smallest class containing REGNO. */ | |
2278 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2279 | ||
0948ccb2 PB |
2280 | enum ix86_fpcmp_strategy { |
2281 | IX86_FPCMP_SAHF, | |
2282 | IX86_FPCMP_COMI, | |
2283 | IX86_FPCMP_ARITH | |
2284 | }; | |
22fb740d JH |
2285 | \f |
2286 | /* To properly truncate FP values into integers, we need to set i387 control | |
2287 | word. We can't emit proper mode switching code before reload, as spills | |
2288 | generated by reload may truncate values incorrectly, but we still can avoid | |
2289 | redundant computation of new control word by the mode switching pass. | |
2290 | The fldcw instructions are still emitted redundantly, but this is probably | |
2291 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2292 | the sequence. |
22fb740d JH |
2293 | |
2294 | The machinery is to emit simple truncation instructions and split them | |
2295 | before reload to instructions having USEs of two memory locations that | |
2296 | are filled by this code to old and new control word. | |
fce5a9f2 | 2297 | |
22fb740d JH |
2298 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2299 | needed. */ | |
2300 | ||
c7ca8ef8 UB |
2301 | enum ix86_stack_slot |
2302 | { | |
2303 | SLOT_TEMP = 0, | |
2304 | SLOT_CW_STORED, | |
2305 | SLOT_CW_TRUNC, | |
2306 | SLOT_CW_FLOOR, | |
2307 | SLOT_CW_CEIL, | |
2308 | SLOT_CW_MASK_PM, | |
80008279 | 2309 | SLOT_STV_TEMP, |
c7ca8ef8 UB |
2310 | MAX_386_STACK_LOCALS |
2311 | }; | |
2312 | ||
ff680eb1 UB |
2313 | enum ix86_entity |
2314 | { | |
c7ca8ef8 UB |
2315 | X86_DIRFLAG = 0, |
2316 | AVX_U128, | |
ff97910d | 2317 | I387_TRUNC, |
ff680eb1 UB |
2318 | I387_FLOOR, |
2319 | I387_CEIL, | |
2320 | I387_MASK_PM, | |
2321 | MAX_386_ENTITIES | |
2322 | }; | |
2323 | ||
c7ca8ef8 | 2324 | enum x86_dirflag_state |
ff680eb1 | 2325 | { |
c7ca8ef8 UB |
2326 | X86_DIRFLAG_RESET, |
2327 | X86_DIRFLAG_ANY | |
ff680eb1 | 2328 | }; |
22fb740d | 2329 | |
ff97910d VY |
2330 | enum avx_u128_state |
2331 | { | |
2332 | AVX_U128_CLEAN, | |
2333 | AVX_U128_DIRTY, | |
2334 | AVX_U128_ANY | |
2335 | }; | |
2336 | ||
22fb740d JH |
2337 | /* Define this macro if the port needs extra instructions inserted |
2338 | for mode switching in an optimizing compilation. */ | |
2339 | ||
ff680eb1 UB |
2340 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2341 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2342 | |
2343 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2344 | initializer for an array of integers. Each initializer element N | |
2345 | refers to an entity that needs mode switching, and specifies the | |
2346 | number of different modes that might need to be set for this | |
2347 | entity. The position of the initializer in the initializer - | |
2348 | starting counting at zero - determines the integer that is used to | |
2349 | refer to the mode-switched entity in question. */ | |
2350 | ||
c7ca8ef8 UB |
2351 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2352 | { X86_DIRFLAG_ANY, AVX_U128_ANY, \ | |
2353 | I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
22fb740d | 2354 | |
0f0138b6 JH |
2355 | \f |
2356 | /* Avoid renaming of stack registers, as doing so in combination with | |
2357 | scheduling just increases amount of live registers at time and in | |
2358 | the turn amount of fxch instructions needed. | |
2359 | ||
3f97cb0b AI |
2360 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2361 | ||
2362 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2363 | |
1a6e82b8 UB |
2364 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
2365 | (!STACK_REGNO_P (SRC) \ | |
2366 | && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) | |
22fb740d | 2367 | |
3b3c6a3f | 2368 | \f |
e91f04de | 2369 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2370 | \f |
77560086 BE |
2371 | #ifndef USED_FOR_TARGET |
2372 | /* Structure describing stack frame layout. | |
2373 | Stack grows downward: | |
2374 | ||
2375 | [arguments] | |
2376 | <- ARG_POINTER | |
2377 | saved pc | |
2378 | ||
2379 | saved static chain if ix86_static_chain_on_stack | |
2380 | ||
2381 | saved frame pointer if frame_pointer_needed | |
2382 | <- HARD_FRAME_POINTER | |
2383 | [saved regs] | |
2384 | <- reg_save_offset | |
2385 | [padding0] | |
2386 | <- stack_realign_offset | |
2387 | [saved SSE regs] | |
2388 | OR | |
2389 | [stub-saved registers for ms x64 --> sysv clobbers | |
2390 | <- Start of out-of-line, stub-saved/restored regs | |
2391 | (see libgcc/config/i386/(sav|res)ms64*.S) | |
2392 | [XMM6-15] | |
2393 | [RSI] | |
2394 | [RDI] | |
2395 | [?RBX] only if RBX is clobbered | |
2396 | [?RBP] only if RBP and RBX are clobbered | |
2397 | [?R12] only if R12 and all previous regs are clobbered | |
2398 | [?R13] only if R13 and all previous regs are clobbered | |
2399 | [?R14] only if R14 and all previous regs are clobbered | |
2400 | [?R15] only if R15 and all previous regs are clobbered | |
2401 | <- end of stub-saved/restored regs | |
2402 | [padding1] | |
2403 | ] | |
5d9d834d | 2404 | <- sse_reg_save_offset |
77560086 BE |
2405 | [padding2] |
2406 | | <- FRAME_POINTER | |
2407 | [va_arg registers] | | |
2408 | | | |
2409 | [frame] | | |
2410 | | | |
2411 | [padding2] | = to_allocate | |
2412 | <- STACK_POINTER | |
2413 | */ | |
2414 | struct GTY(()) ix86_frame | |
2415 | { | |
2416 | int nsseregs; | |
2417 | int nregs; | |
2418 | int va_arg_size; | |
2419 | int red_zone_size; | |
2420 | int outgoing_arguments_size; | |
2421 | ||
2422 | /* The offsets relative to ARG_POINTER. */ | |
2423 | HOST_WIDE_INT frame_pointer_offset; | |
2424 | HOST_WIDE_INT hard_frame_pointer_offset; | |
2425 | HOST_WIDE_INT stack_pointer_offset; | |
2426 | HOST_WIDE_INT hfp_save_offset; | |
2427 | HOST_WIDE_INT reg_save_offset; | |
122f9da1 | 2428 | HOST_WIDE_INT stack_realign_allocate; |
77560086 | 2429 | HOST_WIDE_INT stack_realign_offset; |
77560086 BE |
2430 | HOST_WIDE_INT sse_reg_save_offset; |
2431 | ||
2432 | /* When save_regs_using_mov is set, emit prologue using | |
2433 | move instead of push instructions. */ | |
2434 | bool save_regs_using_mov; | |
2435 | }; | |
2436 | ||
122f9da1 DS |
2437 | /* Machine specific frame tracking during prologue/epilogue generation. All |
2438 | values are positive, but since the x86 stack grows downward, are subtratced | |
2439 | from the CFA to produce a valid address. */ | |
cd9c1ca8 | 2440 | |
ec7ded37 | 2441 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2442 | { |
ec7ded37 RH |
2443 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2444 | is drap_reg, we don't bother trying to record here the real CFA when | |
2445 | it might really be a DW_CFA_def_cfa_expression. */ | |
2446 | rtx cfa_reg; | |
2447 | HOST_WIDE_INT cfa_offset; | |
2448 | ||
2449 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2450 | When stack frame re-alignment is active, these may not be relative | |
2451 | to the CFA. However, in all cases they are relative to the offsets | |
2452 | of the saved registers stored in ix86_frame. */ | |
2453 | HOST_WIDE_INT sp_offset; | |
2454 | HOST_WIDE_INT fp_offset; | |
2455 | ||
2456 | /* The size of the red-zone that may be assumed for the purposes of | |
2457 | eliding register restore notes in the epilogue. This may be zero | |
2458 | if no red-zone is in effect, or may be reduced from the real | |
2459 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2460 | int red_zone_offset; | |
2461 | ||
2462 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2463 | value within the frame. If false then the offset above should be | |
2464 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2465 | thus has an offset of zero. */ | |
2466 | BOOL_BITFIELD sp_valid : 1; | |
2467 | BOOL_BITFIELD fp_valid : 1; | |
2468 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2469 | |
2470 | /* Indicate whether the local stack frame has been re-aligned. When | |
2471 | set, the SP/FP offsets above are relative to the aligned frame | |
2472 | and not the CFA. */ | |
2473 | BOOL_BITFIELD realigned : 1; | |
d6d4d770 DS |
2474 | |
2475 | /* Indicates whether the stack pointer has been re-aligned. When set, | |
2476 | SP/FP continue to be relative to the CFA, but the stack pointer | |
122f9da1 DS |
2477 | should only be used for offsets > sp_realigned_offset, while |
2478 | the frame pointer should be used for offsets <= sp_realigned_fp_last. | |
d6d4d770 DS |
2479 | The flags realigned and sp_realigned are mutually exclusive. */ |
2480 | BOOL_BITFIELD sp_realigned : 1; | |
2481 | ||
122f9da1 DS |
2482 | /* If sp_realigned is set, this is the last valid offset from the CFA |
2483 | that can be used for access with the frame pointer. */ | |
2484 | HOST_WIDE_INT sp_realigned_fp_last; | |
2485 | ||
2486 | /* If sp_realigned is set, this is the offset from the CFA that the stack | |
2487 | pointer was realigned, and may or may not be equal to sp_realigned_fp_last. | |
2488 | Access via the stack pointer is only valid for offsets that are greater than | |
2489 | this value. */ | |
d6d4d770 | 2490 | HOST_WIDE_INT sp_realigned_offset; |
cd9c1ca8 RH |
2491 | }; |
2492 | ||
f81c9774 RH |
2493 | /* Private to winnt.c. */ |
2494 | struct seh_frame_state; | |
2495 | ||
f8071c05 L |
2496 | enum function_type |
2497 | { | |
2498 | TYPE_UNKNOWN = 0, | |
2499 | TYPE_NORMAL, | |
2500 | /* The current function is an interrupt service routine with a | |
2501 | pointer argument as specified by the "interrupt" attribute. */ | |
2502 | TYPE_INTERRUPT, | |
2503 | /* The current function is an interrupt service routine with a | |
2504 | pointer argument and an integer argument as specified by the | |
2505 | "interrupt" attribute. */ | |
2506 | TYPE_EXCEPTION | |
2507 | }; | |
2508 | ||
d1b38208 | 2509 | struct GTY(()) machine_function { |
fa1a0d02 | 2510 | struct stack_local_entry *stack_locals; |
4aab97f9 L |
2511 | int varargs_gpr_size; |
2512 | int varargs_fpr_size; | |
ff680eb1 | 2513 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b | 2514 | |
77560086 BE |
2515 | /* Cached initial frame layout for the current function. */ |
2516 | struct ix86_frame frame; | |
3452586b | 2517 | |
7458026b ILT |
2518 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2519 | the stack arguments for a function with a variable number of | |
2520 | arguments. This is set at the start of the function and is used | |
2521 | to initialize the overflow_arg_area field of the va_list | |
2522 | structure. */ | |
2523 | rtx split_stack_varargs_pointer; | |
2524 | ||
3452586b RH |
2525 | /* This value is used for amd64 targets and specifies the current abi |
2526 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2527 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2528 | |
2529 | /* Nonzero if the function accesses a previous frame. */ | |
2530 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2531 | ||
922e3e33 UB |
2532 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2533 | expander to determine the style used. */ | |
3452586b RH |
2534 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2535 | ||
1e4490dc UB |
2536 | /* Nonzero if the current function calls pc thunk and |
2537 | must not use the red zone. */ | |
2538 | BOOL_BITFIELD pc_thunk_call_expanded : 1; | |
2539 | ||
5bf5a10b AO |
2540 | /* If true, the current function needs the default PIC register, not |
2541 | an alternate register (on x86) and must not use the red zone (on | |
2542 | x86_64), even if it's a leaf function. We don't want the | |
2543 | function to be regarded as non-leaf because TLS calls need not | |
2544 | affect register allocation. This flag is set when a TLS call | |
2545 | instruction is expanded within a function, and never reset, even | |
2546 | if all such instructions are optimized away. Use the | |
2547 | ix86_current_function_calls_tls_descriptor macro for a better | |
2548 | approximation. */ | |
3452586b RH |
2549 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2550 | ||
2551 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2552 | stack below the return address. */ | |
2553 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2554 | |
529a6471 JJ |
2555 | /* If true, it is safe to not save/restore DRAP register. */ |
2556 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2557 | ||
f8071c05 L |
2558 | /* Function type. */ |
2559 | ENUM_BITFIELD(function_type) func_type : 2; | |
2560 | ||
2561 | /* If true, the current function is a function specified with | |
2562 | the "interrupt" or "no_caller_saved_registers" attribute. */ | |
2563 | BOOL_BITFIELD no_caller_saved_registers : 1; | |
2564 | ||
a0ff7835 L |
2565 | /* If true, there is register available for argument passing. This |
2566 | is used only in ix86_function_ok_for_sibcall by 32-bit to determine | |
2567 | if there is scratch register available for indirect sibcall. In | |
2568 | 64-bit, rax, r10 and r11 are scratch registers which aren't used to | |
2569 | pass arguments and can be used for indirect sibcall. */ | |
2570 | BOOL_BITFIELD arg_reg_available : 1; | |
2571 | ||
d6d4d770 | 2572 | /* If true, we're out-of-lining reg save/restore for regs clobbered |
5d9d834d | 2573 | by 64-bit ms_abi functions calling a sysv_abi function. */ |
d6d4d770 DS |
2574 | BOOL_BITFIELD call_ms2sysv : 1; |
2575 | ||
2576 | /* If true, the incoming 16-byte aligned stack has an offset (of 8) and | |
5d9d834d | 2577 | needs padding prior to out-of-line stub save/restore area. */ |
d6d4d770 DS |
2578 | BOOL_BITFIELD call_ms2sysv_pad_in : 1; |
2579 | ||
d6d4d770 DS |
2580 | /* This is the number of extra registers saved by stub (valid range is |
2581 | 0-6). Each additional register is only saved/restored by the stubs | |
2582 | if all successive ones are. (Will always be zero when using a hard | |
2583 | frame pointer.) */ | |
2584 | unsigned int call_ms2sysv_extra_regs:3; | |
2585 | ||
35c95658 L |
2586 | /* Nonzero if the function places outgoing arguments on stack. */ |
2587 | BOOL_BITFIELD outgoing_args_on_stack : 1; | |
2588 | ||
ec7ded37 RH |
2589 | /* During prologue/epilogue generation, the current frame state. |
2590 | Otherwise, the frame state at the end of the prologue. */ | |
2591 | struct machine_frame_state fs; | |
f81c9774 RH |
2592 | |
2593 | /* During SEH output, this is non-null. */ | |
2594 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2595 | }; |
cd9c1ca8 | 2596 | #endif |
fa1a0d02 JH |
2597 | |
2598 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2599 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2600 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2601 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
1e4490dc | 2602 | #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) |
5bf5a10b AO |
2603 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2604 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2605 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2606 | calls are optimized away, we try to detect cases in which it was | |
2607 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2608 | verify whether there's any such instruction live by testing that | |
2609 | REG_SP is live. */ | |
2610 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2611 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2612 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
2ecf9ac7 | 2613 | #define ix86_red_zone_size (cfun->machine->frame.red_zone_size) |
249e6b63 | 2614 | |
1bc7c5b6 ZW |
2615 | /* Control behavior of x86_file_start. */ |
2616 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2617 | #define X86_FILE_START_FLTUSED false | |
2618 | ||
7dcbf659 JH |
2619 | /* Flag to mark data that is in the large address area. */ |
2620 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2621 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2622 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2623 | |
2624 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2625 | have defined always, to avoid ifdefing. */ | |
2626 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2627 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2628 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2629 | ||
2630 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2631 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2632 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2633 | ||
82c0e1a0 KT |
2634 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2635 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2636 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2637 | ||
7942e47e RY |
2638 | extern void debug_ready_dispatch (void); |
2639 | extern void debug_dispatch_window (int); | |
2640 | ||
91afcfa3 QN |
2641 | /* The value at zero is only defined for the BMI instructions |
2642 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2643 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1068ced5 | 2644 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) |
91afcfa3 | 2645 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
1068ced5 | 2646 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) |
91afcfa3 QN |
2647 | |
2648 | ||
b8ce4e94 KT |
2649 | /* Flags returned by ix86_get_callcvt (). */ |
2650 | #define IX86_CALLCVT_CDECL 0x1 | |
2651 | #define IX86_CALLCVT_STDCALL 0x2 | |
2652 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2653 | #define IX86_CALLCVT_THISCALL 0x8 | |
2654 | #define IX86_CALLCVT_REGPARM 0x10 | |
2655 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2656 | ||
2657 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2658 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2659 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2660 | ||
b86b9f44 MM |
2661 | #define RECIP_MASK_NONE 0x00 |
2662 | #define RECIP_MASK_DIV 0x01 | |
2663 | #define RECIP_MASK_SQRT 0x02 | |
2664 | #define RECIP_MASK_VEC_DIV 0x04 | |
2665 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2666 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2667 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2668 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2669 | |
2670 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2671 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2672 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2673 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2674 | ||
5dcfdccd KY |
2675 | #define IX86_HLE_ACQUIRE (1 << 16) |
2676 | #define IX86_HLE_RELEASE (1 << 17) | |
2677 | ||
e83b8e2e JJ |
2678 | /* For switching between functions with different target attributes. */ |
2679 | #define SWITCHABLE_TARGET 1 | |
2680 | ||
44d0de8d UB |
2681 | #define TARGET_SUPPORTS_WIDE_INT 1 |
2682 | ||
c98f8742 JVA |
2683 | /* |
2684 | Local variables: | |
2685 | version-control: t | |
2686 | End: | |
2687 | */ |