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e075ae69 | 1 | /* Definitions of target machine for GNU compiler for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
d9a5f180 | 3 | 2001, 2002 Free Software Foundation, Inc. |
c98f8742 JVA |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
892a2d68 | 20 | Boston, MA 02111-1307, USA. */ |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
e075ae69 RH |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
c98f8742 | 36 | |
d4ba09c0 SC |
37 | /* Define the specific costs for a given cpu */ |
38 | ||
39 | struct processor_costs { | |
8b60264b KG |
40 | const int add; /* cost of an add instruction */ |
41 | const int lea; /* cost of a lea instruction */ | |
42 | const int shift_var; /* variable shift costs */ | |
43 | const int shift_const; /* constant shift costs */ | |
4977bab6 ZW |
44 | const int mult_init[5]; /* cost of starting a multiply |
45 | in QImode, HImode, SImode, DImode, TImode*/ | |
8b60264b | 46 | const int mult_bit; /* cost of multiply per each bit set */ |
4977bab6 ZW |
47 | const int divide[5]; /* cost of a divide/mod |
48 | in QImode, HImode, SImode, DImode, TImode*/ | |
44cf5b6a JH |
49 | int movsx; /* The cost of movsx operation. */ |
50 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
51 | const int large_insn; /* insns larger than this cost more */ |
52 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 53 | memory-to-memory move insns. */ |
8b60264b KG |
54 | const int movzbl_load; /* cost of loading using movzbl */ |
55 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
56 | in QImode, HImode and SImode relative |
57 | to reg-reg move (2). */ | |
8b60264b | 58 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 59 | in QImode, HImode and SImode */ |
8b60264b KG |
60 | const int fp_move; /* cost of reg,reg fld/fst */ |
61 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 62 | in SFmode, DFmode and XFmode */ |
8b60264b | 63 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 64 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
65 | const int mmx_move; /* cost of moving MMX register. */ |
66 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 67 | in SImode and DImode */ |
8b60264b | 68 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 69 | in SImode and DImode */ |
8b60264b KG |
70 | const int sse_move; /* cost of moving SSE register. */ |
71 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 72 | in SImode, DImode and TImode*/ |
8b60264b | 73 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 74 | in SImode, DImode and TImode*/ |
8b60264b | 75 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 76 | integer and vice versa. */ |
f4365627 JH |
77 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
78 | const int simultaneous_prefetches; /* number of parallel prefetch | |
79 | operations. */ | |
4977bab6 | 80 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
81 | const int fadd; /* cost of FADD and FSUB instructions. */ |
82 | const int fmul; /* cost of FMUL instruction. */ | |
83 | const int fdiv; /* cost of FDIV instruction. */ | |
84 | const int fabs; /* cost of FABS instruction. */ | |
85 | const int fchs; /* cost of FCHS instruction. */ | |
86 | const int fsqrt; /* cost of FSQRT instruction. */ | |
d4ba09c0 SC |
87 | }; |
88 | ||
8b60264b | 89 | extern const struct processor_costs *ix86_cost; |
d4ba09c0 | 90 | |
c98f8742 JVA |
91 | /* Run-time compilation parameters selecting different hardware subsets. */ |
92 | ||
93 | extern int target_flags; | |
94 | ||
95 | /* Macros used in the machine description to test the flags. */ | |
96 | ||
ddd5a7c1 | 97 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 98 | |
35b528be RS |
99 | #ifndef TARGET_CPU_DEFAULT |
100 | #define TARGET_CPU_DEFAULT 0 | |
101 | #endif | |
102 | ||
3b3c6a3f | 103 | /* Masks for the -m switches */ |
e075ae69 RH |
104 | #define MASK_80387 0x00000001 /* Hardware floating point */ |
105 | #define MASK_RTD 0x00000002 /* Use ret that pops args */ | |
106 | #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ | |
107 | #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ | |
108 | #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ | |
109 | #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ | |
110 | #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ | |
111 | #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ | |
112 | #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ | |
0dd0e980 JH |
113 | #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */ |
114 | #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */ | |
115 | #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */ | |
116 | #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */ | |
9ef1b13a RH |
117 | #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */ |
118 | #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */ | |
119 | #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */ | |
120 | #define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */ | |
121 | #define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */ | |
122 | #define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */ | |
123 | #define MASK_64BIT 0x00080000 /* Produce 64bit code */ | |
4977bab6 | 124 | #define MASK_MS_BITFIELD_LAYOUT 0x00100000 /* Use native (MS) bitfield layout */ |
9ef1b13a | 125 | |
4977bab6 | 126 | /* Unused: 0x03e0000 */ |
9ef1b13a | 127 | |
c93e80a5 JH |
128 | /* ... overlap with subtarget options starts by 0x04000000. */ |
129 | #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */ | |
3b3c6a3f MM |
130 | |
131 | /* Use the floating point instructions */ | |
132 | #define TARGET_80387 (target_flags & MASK_80387) | |
133 | ||
c98f8742 JVA |
134 | /* Compile using ret insn that pops args. |
135 | This will not work unless you use prototypes at least | |
fce5a9f2 | 136 | for all functions that can take varying numbers of args. */ |
3b3c6a3f MM |
137 | #define TARGET_RTD (target_flags & MASK_RTD) |
138 | ||
b08de47e MM |
139 | /* Align doubles to a two word boundary. This breaks compatibility with |
140 | the published ABI's for structures containing doubles, but produces | |
141 | faster code on the pentium. */ | |
142 | #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) | |
c98f8742 | 143 | |
f73ad30e JH |
144 | /* Use push instructions to save outgoing args. */ |
145 | #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS)) | |
146 | ||
147 | /* Accumulate stack adjustments to prologue/epilogue. */ | |
148 | #define TARGET_ACCUMULATE_OUTGOING_ARGS \ | |
149 | (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS) | |
150 | ||
d7cd15e9 RS |
151 | /* Put uninitialized locals into bss, not data. |
152 | Meaningful only on svr3. */ | |
3b3c6a3f | 153 | #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) |
d7cd15e9 | 154 | |
c572e5ba JVA |
155 | /* Use IEEE floating point comparisons. These handle correctly the cases |
156 | where the result of a comparison is unordered. Normally SIGFPE is | |
157 | generated in such cases, in which case this isn't needed. */ | |
3b3c6a3f | 158 | #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) |
c572e5ba | 159 | |
8c2bf92a JVA |
160 | /* Functions that return a floating point value may return that value |
161 | in the 387 FPU or in 386 integer registers. If set, this flag causes | |
892a2d68 | 162 | the 387 to be used, which is compatible with most calling conventions. */ |
3b3c6a3f | 163 | #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) |
8c2bf92a | 164 | |
2b589241 | 165 | /* Long double is 128bit instead of 96bit, even when only 80bits are used. |
f5143c46 | 166 | This mode wastes cache, but avoid misaligned data accesses and simplifies |
2b589241 JH |
167 | address calculations. */ |
168 | #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE) | |
169 | ||
099800e3 RK |
170 | /* Disable generation of FP sin, cos and sqrt operations for 387. |
171 | This is because FreeBSD lacks these in the math-emulator-code */ | |
3b3c6a3f MM |
172 | #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) |
173 | ||
2f2fa5b1 | 174 | /* Don't create frame pointers for leaf functions */ |
e075ae69 RH |
175 | #define TARGET_OMIT_LEAF_FRAME_POINTER \ |
176 | (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) | |
f6f58ba3 | 177 | |
3b3c6a3f | 178 | /* Debug GO_IF_LEGITIMATE_ADDRESS */ |
c93e80a5 | 179 | #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0) |
3b3c6a3f | 180 | |
b08de47e | 181 | /* Debug FUNCTION_ARG macros */ |
c93e80a5 | 182 | #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0) |
b08de47e | 183 | |
5791cc29 JT |
184 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
185 | compile-time constant. */ | |
186 | #ifdef IN_LIBGCC2 | |
187 | #ifdef __x86_64__ | |
188 | #define TARGET_64BIT 1 | |
189 | #else | |
190 | #define TARGET_64BIT 0 | |
191 | #endif | |
192 | #else | |
0c2dc519 | 193 | #ifdef TARGET_BI_ARCH |
25f94bb5 | 194 | #define TARGET_64BIT (target_flags & MASK_64BIT) |
0c2dc519 | 195 | #else |
67adf6a9 | 196 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
197 | #define TARGET_64BIT 1 |
198 | #else | |
199 | #define TARGET_64BIT 0 | |
200 | #endif | |
201 | #endif | |
5791cc29 | 202 | #endif |
25f94bb5 | 203 | |
f7746310 SC |
204 | #define TARGET_386 (ix86_cpu == PROCESSOR_I386) |
205 | #define TARGET_486 (ix86_cpu == PROCESSOR_I486) | |
206 | #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) | |
3a0433fd | 207 | #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) |
a269a03c | 208 | #define TARGET_K6 (ix86_cpu == PROCESSOR_K6) |
309ada50 | 209 | #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) |
b4e89e2d | 210 | #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4) |
4977bab6 ZW |
211 | #define TARGET_K8 (ix86_cpu == PROCESSOR_K8) |
212 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) | |
a269a03c JC |
213 | |
214 | #define CPUMASK (1 << ix86_cpu) | |
215 | extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; | |
216 | extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; | |
ef6257cd | 217 | extern const int x86_branch_hints, x86_unroll_strlen; |
e075ae69 RH |
218 | extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; |
219 | extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; | |
220 | extern const int x86_use_cltd, x86_read_modify_write; | |
221 | extern const int x86_read_modify, x86_split_long_moves; | |
285464d0 | 222 | extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; |
d9f32422 | 223 | extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; |
0b5107cf | 224 | extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; |
bdeb029c | 225 | extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; |
0b5107cf | 226 | extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; |
c6036a37 | 227 | extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; |
b972dd02 | 228 | extern const int x86_epilogue_using_move, x86_decompose_lea; |
495333a6 | 229 | extern const int x86_arch_always_fancy_math_387, x86_shift1; |
4977bab6 ZW |
230 | extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs; |
231 | extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; | |
232 | extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss; | |
f4365627 | 233 | extern int x86_prefetch_sse; |
a269a03c JC |
234 | |
235 | #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) | |
236 | #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) | |
237 | #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) | |
238 | #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) | |
239 | #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) | |
0644b628 JH |
240 | /* For sane SSE instruction set generation we need fcomi instruction. It is |
241 | safe to enable all CMOVE instructions. */ | |
242 | #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) | |
a269a03c | 243 | #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) |
ef6257cd | 244 | #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK) |
a269a03c | 245 | #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) |
0d7d98ee | 246 | #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT) |
e075ae69 RH |
247 | #define TARGET_MOVX (x86_movx & CPUMASK) |
248 | #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) | |
249 | #define TARGET_USE_LOOP (x86_use_loop & CPUMASK) | |
250 | #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) | |
251 | #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) | |
252 | #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) | |
253 | #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) | |
254 | #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) | |
255 | #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) | |
e9e80858 | 256 | #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) |
285464d0 | 257 | #define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK) |
f90800f8 | 258 | #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) |
d9f32422 JH |
259 | #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) |
260 | #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) | |
261 | #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) | |
262 | #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) | |
bdeb029c JH |
263 | #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK) |
264 | #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK) | |
265 | #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK) | |
266 | #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK) | |
0b5107cf JH |
267 | #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK) |
268 | #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK) | |
4977bab6 ZW |
269 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ |
270 | (x86_sse_partial_reg_dependency & CPUMASK) | |
271 | #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & CPUMASK) | |
272 | #define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \ | |
273 | (x86_sse_partial_regs_for_cvtsd2ss & CPUMASK) | |
274 | #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & CPUMASK) | |
275 | #define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & CPUMASK) | |
276 | #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & CPUMASK) | |
0b5107cf | 277 | #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK) |
c6036a37 JH |
278 | #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK) |
279 | #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK) | |
b972dd02 | 280 | #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK) |
f4365627 | 281 | #define TARGET_PREFETCH_SSE (x86_prefetch_sse) |
495333a6 | 282 | #define TARGET_SHIFT1 (x86_shift1 & CPUMASK) |
4977bab6 ZW |
283 | #define TARGET_USE_FFREEP (x86_use_ffreep & CPUMASK) |
284 | #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & CPUMASK) | |
a269a03c | 285 | |
8c9be447 | 286 | #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) |
3b3c6a3f | 287 | |
79f05c19 JH |
288 | #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) |
289 | #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) | |
290 | ||
c93e80a5 | 291 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
e075ae69 | 292 | |
446988df JH |
293 | #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0) |
294 | #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0) | |
965f5423 JH |
295 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) |
296 | #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ | |
297 | && (ix86_fpmath & FPMATH_387)) | |
a7180f70 | 298 | #define TARGET_MMX ((target_flags & MASK_MMX) != 0) |
47f339cf BS |
299 | #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0) |
300 | #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0) | |
a7180f70 | 301 | |
8362f420 JH |
302 | #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE)) |
303 | ||
4977bab6 ZW |
304 | #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT) |
305 | ||
f996902d RH |
306 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
307 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
308 | ||
a5d17ff3 PT |
309 | /* WARNING: Do not mark empty strings for translation, as calling |
310 | gettext on an empty string does NOT return an empty | |
311 | string. */ | |
312 | ||
313 | ||
e075ae69 | 314 | #define TARGET_SWITCHES \ |
047142d3 PT |
315 | { { "80387", MASK_80387, N_("Use hardware fp") }, \ |
316 | { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \ | |
317 | { "hard-float", MASK_80387, N_("Use hardware fp") }, \ | |
318 | { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \ | |
319 | { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \ | |
a5d17ff3 PT |
320 | { "386", 0, "" /*Deprecated.*/}, \ |
321 | { "486", 0, "" /*Deprecated.*/}, \ | |
322 | { "pentium", 0, "" /*Deprecated.*/}, \ | |
323 | { "pentiumpro", 0, "" /*Deprecated.*/}, \ | |
324 | { "intel-syntax", 0, "" /*Deprecated.*/}, \ | |
325 | { "no-intel-syntax", 0, "" /*Deprecated.*/}, \ | |
047142d3 PT |
326 | { "rtd", MASK_RTD, \ |
327 | N_("Alternate calling convention") }, \ | |
328 | { "no-rtd", -MASK_RTD, \ | |
329 | N_("Use normal calling convention") }, \ | |
e075ae69 | 330 | { "align-double", MASK_ALIGN_DOUBLE, \ |
047142d3 | 331 | N_("Align some doubles on dword boundary") }, \ |
e075ae69 | 332 | { "no-align-double", -MASK_ALIGN_DOUBLE, \ |
047142d3 | 333 | N_("Align doubles on word boundary") }, \ |
e075ae69 | 334 | { "svr3-shlib", MASK_SVR3_SHLIB, \ |
047142d3 | 335 | N_("Uninitialized locals in .bss") }, \ |
e075ae69 | 336 | { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ |
047142d3 | 337 | N_("Uninitialized locals in .data") }, \ |
e075ae69 | 338 | { "ieee-fp", MASK_IEEE_FP, \ |
047142d3 | 339 | N_("Use IEEE math for fp comparisons") }, \ |
e075ae69 | 340 | { "no-ieee-fp", -MASK_IEEE_FP, \ |
047142d3 | 341 | N_("Do not use IEEE math for fp comparisons") }, \ |
e075ae69 | 342 | { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ |
047142d3 | 343 | N_("Return values of functions in FPU registers") }, \ |
e075ae69 | 344 | { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ |
047142d3 | 345 | N_("Do not return values of functions in FPU registers")}, \ |
e075ae69 | 346 | { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ |
047142d3 | 347 | N_("Do not generate sin, cos, sqrt for FPU") }, \ |
e075ae69 | 348 | { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ |
047142d3 | 349 | N_("Generate sin, cos, sqrt for FPU")}, \ |
e075ae69 | 350 | { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ |
047142d3 | 351 | N_("Omit the frame pointer in leaf functions") }, \ |
e075ae69 | 352 | { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ |
047142d3 PT |
353 | { "stack-arg-probe", MASK_STACK_PROBE, \ |
354 | N_("Enable stack probing") }, \ | |
e075ae69 RH |
355 | { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ |
356 | { "windows", 0, 0 /* undocumented */ }, \ | |
357 | { "dll", 0, 0 /* undocumented */ }, \ | |
79f05c19 | 358 | { "align-stringops", -MASK_NO_ALIGN_STROPS, \ |
047142d3 | 359 | N_("Align destination of the string operations") }, \ |
79f05c19 | 360 | { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ |
047142d3 | 361 | N_("Do not align destination of the string operations") }, \ |
4be2e5d9 | 362 | { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ |
047142d3 | 363 | N_("Inline all known string operations") }, \ |
79f05c19 | 364 | { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ |
047142d3 | 365 | N_("Do not inline all known string operations") }, \ |
f73ad30e | 366 | { "push-args", -MASK_NO_PUSH_ARGS, \ |
047142d3 | 367 | N_("Use push instructions to save outgoing arguments") }, \ |
053f1126 | 368 | { "no-push-args", MASK_NO_PUSH_ARGS, \ |
047142d3 | 369 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 370 | { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 371 | N_("Use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 372 | { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \ |
047142d3 | 373 | N_("Do not use push instructions to save outgoing arguments") }, \ |
9ef1b13a | 374 | { "mmx", MASK_MMX, \ |
b0287a90 | 375 | N_("Support MMX built-in functions") }, \ |
0dd0e980 | 376 | { "no-mmx", -MASK_MMX, \ |
b0287a90 | 377 | N_("Do not support MMX built-in functions") }, \ |
9ef1b13a | 378 | { "3dnow", MASK_3DNOW, \ |
b0287a90 | 379 | N_("Support 3DNow! built-in functions") }, \ |
9ef1b13a | 380 | { "no-3dnow", -MASK_3DNOW, \ |
b0287a90 | 381 | N_("Do not support 3DNow! built-in functions") }, \ |
9ef1b13a | 382 | { "sse", MASK_SSE, \ |
b0287a90 | 383 | N_("Support MMX and SSE built-in functions and code generation") }, \ |
9ef1b13a | 384 | { "no-sse", -MASK_SSE, \ |
b0287a90 | 385 | N_("Do not support MMX and SSE built-in functions and code generation") },\ |
9ef1b13a | 386 | { "sse2", MASK_SSE2, \ |
b0287a90 | 387 | N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
9ef1b13a | 388 | { "no-sse2", -MASK_SSE2, \ |
b0287a90 | 389 | N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \ |
2b589241 | 390 | { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 391 | N_("sizeof(long double) is 16") }, \ |
2b589241 | 392 | { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \ |
c725bd79 | 393 | N_("sizeof(long double) is 12") }, \ |
25f94bb5 JH |
394 | { "64", MASK_64BIT, \ |
395 | N_("Generate 64bit x86-64 code") }, \ | |
396 | { "32", -MASK_64BIT, \ | |
397 | N_("Generate 32bit i386 code") }, \ | |
4977bab6 ZW |
398 | { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \ |
399 | N_("Use native (MS) bitfield layout") }, \ | |
400 | { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \ | |
401 | N_("Use gcc default bitfield layout") }, \ | |
8362f420 JH |
402 | { "red-zone", -MASK_NO_RED_ZONE, \ |
403 | N_("Use red-zone in the x86-64 code") }, \ | |
404 | { "no-red-zone", MASK_NO_RED_ZONE, \ | |
4cba3b67 | 405 | N_("Do not use red-zone in the x86-64 code") }, \ |
e075ae69 | 406 | SUBTARGET_SWITCHES \ |
67adf6a9 | 407 | { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }} |
241e1a89 | 408 | |
67adf6a9 RH |
409 | #ifndef TARGET_64BIT_DEFAULT |
410 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 JH |
411 | #endif |
412 | ||
0ed4a390 JL |
413 | /* Once GDB has been enhanced to deal with functions without frame |
414 | pointers, we can change this to allow for elimination of | |
415 | the frame pointer in leaf functions. */ | |
416 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 417 | |
b069de3b SS |
418 | /* This is not really a target flag, but is done this way so that |
419 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
420 | redefines this to 1. */ | |
421 | #define TARGET_MACHO 0 | |
422 | ||
f5316dfe MM |
423 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
424 | command options that have values. Its definition is an | |
425 | initializer with a subgrouping for each command option. | |
426 | ||
427 | Each subgrouping contains a string constant, that defines the | |
428 | fixed part of the option name, and the address of a variable. The | |
429 | variable, type `char *', is set to the variable part of the given | |
430 | option if the fixed part matches. The actual option name is made | |
431 | by appending `-m' to the specified name. */ | |
e075ae69 RH |
432 | #define TARGET_OPTIONS \ |
433 | { { "cpu=", &ix86_cpu_string, \ | |
047142d3 | 434 | N_("Schedule code for given CPU")}, \ |
965f5423 JH |
435 | { "fpmath=", &ix86_fpmath_string, \ |
436 | N_("Generate floating point mathematics using given instruction set")},\ | |
e075ae69 | 437 | { "arch=", &ix86_arch_string, \ |
047142d3 | 438 | N_("Generate code for given CPU")}, \ |
e075ae69 | 439 | { "regparm=", &ix86_regparm_string, \ |
047142d3 | 440 | N_("Number of registers used to pass integer arguments") }, \ |
e075ae69 | 441 | { "align-loops=", &ix86_align_loops_string, \ |
047142d3 | 442 | N_("Loop code aligned to this power of 2") }, \ |
e075ae69 | 443 | { "align-jumps=", &ix86_align_jumps_string, \ |
047142d3 | 444 | N_("Jump targets are aligned to this power of 2") }, \ |
e075ae69 | 445 | { "align-functions=", &ix86_align_funcs_string, \ |
047142d3 | 446 | N_("Function starts are aligned to this power of 2") }, \ |
e075ae69 RH |
447 | { "preferred-stack-boundary=", \ |
448 | &ix86_preferred_stack_boundary_string, \ | |
047142d3 | 449 | N_("Attempt to keep stack aligned to this power of 2") }, \ |
e075ae69 | 450 | { "branch-cost=", &ix86_branch_cost_string, \ |
047142d3 | 451 | N_("Branches are this expensive (1-5, arbitrary units)") }, \ |
6189a572 JH |
452 | { "cmodel=", &ix86_cmodel_string, \ |
453 | N_("Use given x86-64 code model") }, \ | |
c93e80a5 | 454 | { "debug-arg", &ix86_debug_arg_string, \ |
a5d17ff3 | 455 | "" /* Undocumented. */ }, \ |
c93e80a5 | 456 | { "debug-addr", &ix86_debug_addr_string, \ |
a5d17ff3 | 457 | "" /* Undocumented. */ }, \ |
c93e80a5 JH |
458 | { "asm=", &ix86_asm_string, \ |
459 | N_("Use given assembler dialect") }, \ | |
f996902d RH |
460 | { "tls-dialect=", &ix86_tls_dialect_string, \ |
461 | N_("Use given thread-local storage dialect") }, \ | |
e075ae69 | 462 | SUBTARGET_OPTIONS \ |
b08de47e | 463 | } |
f5316dfe MM |
464 | |
465 | /* Sometimes certain combinations of command options do not make | |
466 | sense on a particular target machine. You can define a macro | |
467 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
468 | defined, is executed once just after all the command options have | |
469 | been parsed. | |
470 | ||
471 | Don't use this macro to turn on various extra optimizations for | |
472 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
473 | ||
474 | #define OVERRIDE_OPTIONS override_options () | |
475 | ||
476 | /* These are meant to be redefined in the host dependent files */ | |
95393dfd | 477 | #define SUBTARGET_SWITCHES |
f5316dfe | 478 | #define SUBTARGET_OPTIONS |
95393dfd | 479 | |
d4ba09c0 | 480 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
481 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
482 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 483 | |
241e1a89 SC |
484 | /* Specs for the compiler proper */ |
485 | ||
628714d8 RK |
486 | #ifndef CC1_CPU_SPEC |
487 | #define CC1_CPU_SPEC "\ | |
241e1a89 | 488 | %{!mcpu*: \ |
4a88a060 | 489 | %{m386:-mcpu=i386 \ |
3f0e0fa2 | 490 | %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \ |
4a88a060 | 491 | %{m486:-mcpu=i486 \ |
3f0e0fa2 | 492 | %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \ |
4a88a060 | 493 | %{mpentium:-mcpu=pentium \ |
3f0e0fa2 | 494 | %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \ |
4a88a060 | 495 | %{mpentiumpro:-mcpu=pentiumpro \ |
c93e80a5 JH |
496 | %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \ |
497 | %{mintel-syntax:-masm=intel \ | |
498 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
499 | %{mno-intel-syntax:-masm=att \ | |
500 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
241e1a89 | 501 | #endif |
c98f8742 | 502 | \f |
30efe578 | 503 | /* Target CPU builtins. */ |
1ba7b414 NB |
504 | #define TARGET_CPU_CPP_BUILTINS() \ |
505 | do \ | |
506 | { \ | |
507 | size_t arch_len = strlen (ix86_arch_string); \ | |
508 | size_t cpu_len = strlen (ix86_cpu_string); \ | |
509 | int last_arch_char = ix86_arch_string[arch_len - 1]; \ | |
510 | int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \ | |
511 | \ | |
512 | if (TARGET_64BIT) \ | |
513 | { \ | |
514 | builtin_assert ("cpu=x86_64"); \ | |
515 | builtin_assert ("machine=x86_64"); \ | |
516 | builtin_define ("__x86_64"); \ | |
517 | builtin_define ("__x86_64__"); \ | |
518 | } \ | |
519 | else \ | |
520 | { \ | |
521 | builtin_assert ("cpu=i386"); \ | |
522 | builtin_assert ("machine=i386"); \ | |
523 | builtin_define_std ("i386"); \ | |
524 | } \ | |
525 | \ | |
526 | /* Built-ins based on -mcpu= (or -march= if no \ | |
527 | CPU given). */ \ | |
528 | if (TARGET_386) \ | |
529 | builtin_define ("__tune_i386__"); \ | |
530 | else if (TARGET_486) \ | |
531 | builtin_define ("__tune_i486__"); \ | |
532 | else if (TARGET_PENTIUM) \ | |
533 | { \ | |
534 | builtin_define ("__tune_i586__"); \ | |
535 | builtin_define ("__tune_pentium__"); \ | |
536 | if (last_cpu_char == 'x') \ | |
537 | builtin_define ("__tune_pentium_mmx__"); \ | |
538 | } \ | |
539 | else if (TARGET_PENTIUMPRO) \ | |
540 | { \ | |
541 | builtin_define ("__tune_i686__"); \ | |
542 | builtin_define ("__tune_pentiumpro__"); \ | |
2e37b0ce RH |
543 | switch (last_cpu_char) \ |
544 | { \ | |
545 | case '3': \ | |
546 | builtin_define ("__tune_pentium3__"); \ | |
547 | /* FALLTHRU */ \ | |
548 | case '2': \ | |
549 | builtin_define ("__tune_pentium2__"); \ | |
550 | break; \ | |
551 | } \ | |
1ba7b414 NB |
552 | } \ |
553 | else if (TARGET_K6) \ | |
554 | { \ | |
555 | builtin_define ("__tune_k6__"); \ | |
556 | if (last_cpu_char == '2') \ | |
557 | builtin_define ("__tune_k6_2__"); \ | |
558 | else if (last_cpu_char == '3') \ | |
559 | builtin_define ("__tune_k6_3__"); \ | |
560 | } \ | |
561 | else if (TARGET_ATHLON) \ | |
562 | { \ | |
563 | builtin_define ("__tune_athlon__"); \ | |
564 | /* Only plain "athlon" lacks SSE. */ \ | |
565 | if (last_cpu_char != 'n') \ | |
566 | builtin_define ("__tune_athlon_sse__"); \ | |
567 | } \ | |
4977bab6 ZW |
568 | else if (TARGET_K8) \ |
569 | builtin_define ("__tune_k8__"); \ | |
1ba7b414 NB |
570 | else if (TARGET_PENTIUM4) \ |
571 | builtin_define ("__tune_pentium4__"); \ | |
572 | \ | |
573 | if (TARGET_MMX) \ | |
574 | builtin_define ("__MMX__"); \ | |
575 | if (TARGET_3DNOW) \ | |
576 | builtin_define ("__3dNOW__"); \ | |
577 | if (TARGET_3DNOW_A) \ | |
578 | builtin_define ("__3dNOW_A__"); \ | |
579 | if (TARGET_SSE) \ | |
580 | builtin_define ("__SSE__"); \ | |
581 | if (TARGET_SSE2) \ | |
582 | builtin_define ("__SSE2__"); \ | |
48ddd46c JH |
583 | if (TARGET_SSE_MATH && TARGET_SSE) \ |
584 | builtin_define ("__SSE_MATH__"); \ | |
585 | if (TARGET_SSE_MATH && TARGET_SSE2) \ | |
586 | builtin_define ("__SSE2_MATH__"); \ | |
1ba7b414 NB |
587 | \ |
588 | /* Built-ins based on -march=. */ \ | |
589 | if (ix86_arch == PROCESSOR_I486) \ | |
590 | { \ | |
591 | builtin_define ("__i486"); \ | |
592 | builtin_define ("__i486__"); \ | |
593 | } \ | |
594 | else if (ix86_arch == PROCESSOR_PENTIUM) \ | |
595 | { \ | |
596 | builtin_define ("__i586"); \ | |
597 | builtin_define ("__i586__"); \ | |
598 | builtin_define ("__pentium"); \ | |
599 | builtin_define ("__pentium__"); \ | |
600 | if (last_arch_char == 'x') \ | |
601 | builtin_define ("__pentium_mmx__"); \ | |
602 | } \ | |
603 | else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ | |
604 | { \ | |
605 | builtin_define ("__i686"); \ | |
606 | builtin_define ("__i686__"); \ | |
607 | builtin_define ("__pentiumpro"); \ | |
608 | builtin_define ("__pentiumpro__"); \ | |
609 | } \ | |
610 | else if (ix86_arch == PROCESSOR_K6) \ | |
611 | { \ | |
612 | \ | |
613 | builtin_define ("__k6"); \ | |
614 | builtin_define ("__k6__"); \ | |
615 | if (last_arch_char == '2') \ | |
616 | builtin_define ("__k6_2__"); \ | |
617 | else if (last_arch_char == '3') \ | |
618 | builtin_define ("__k6_3__"); \ | |
619 | } \ | |
620 | else if (ix86_arch == PROCESSOR_ATHLON) \ | |
621 | { \ | |
622 | builtin_define ("__athlon"); \ | |
623 | builtin_define ("__athlon__"); \ | |
624 | /* Only plain "athlon" lacks SSE. */ \ | |
625 | if (last_arch_char != 'n') \ | |
626 | builtin_define ("__athlon_sse__"); \ | |
627 | } \ | |
4977bab6 ZW |
628 | else if (ix86_arch == PROCESSOR_K8) \ |
629 | { \ | |
630 | builtin_define ("__k8"); \ | |
631 | builtin_define ("__k8__"); \ | |
632 | } \ | |
1ba7b414 NB |
633 | else if (ix86_arch == PROCESSOR_PENTIUM4) \ |
634 | { \ | |
635 | builtin_define ("__pentium4"); \ | |
636 | builtin_define ("__pentium4__"); \ | |
637 | } \ | |
638 | } \ | |
30efe578 NB |
639 | while (0) |
640 | ||
f4365627 JH |
641 | #define TARGET_CPU_DEFAULT_i386 0 |
642 | #define TARGET_CPU_DEFAULT_i486 1 | |
643 | #define TARGET_CPU_DEFAULT_pentium 2 | |
91d2f4ba JH |
644 | #define TARGET_CPU_DEFAULT_pentium_mmx 3 |
645 | #define TARGET_CPU_DEFAULT_pentiumpro 4 | |
646 | #define TARGET_CPU_DEFAULT_pentium2 5 | |
647 | #define TARGET_CPU_DEFAULT_pentium3 6 | |
648 | #define TARGET_CPU_DEFAULT_pentium4 7 | |
649 | #define TARGET_CPU_DEFAULT_k6 8 | |
650 | #define TARGET_CPU_DEFAULT_k6_2 9 | |
651 | #define TARGET_CPU_DEFAULT_k6_3 10 | |
652 | #define TARGET_CPU_DEFAULT_athlon 11 | |
653 | #define TARGET_CPU_DEFAULT_athlon_sse 12 | |
4977bab6 | 654 | #define TARGET_CPU_DEFAULT_k8 13 |
f4365627 JH |
655 | |
656 | #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ | |
657 | "pentiumpro", "pentium2", "pentium3", \ | |
658 | "pentium4", "k6", "k6-2", "k6-3",\ | |
4977bab6 | 659 | "athlon", "athlon-4", "k8"} |
0c2dc519 | 660 | |
628714d8 | 661 | #ifndef CC1_SPEC |
8015b78d | 662 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
663 | #endif |
664 | ||
665 | /* This macro defines names of additional specifications to put in the | |
666 | specs that can be used in various specifications like CC1_SPEC. Its | |
667 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
668 | |
669 | Each subgrouping contains a string constant, that defines the | |
670 | specification name, and a string constant that used by the GNU CC driver | |
671 | program. | |
672 | ||
673 | Do not define this macro if it does not need to do anything. */ | |
674 | ||
675 | #ifndef SUBTARGET_EXTRA_SPECS | |
676 | #define SUBTARGET_EXTRA_SPECS | |
677 | #endif | |
678 | ||
679 | #define EXTRA_SPECS \ | |
628714d8 | 680 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
681 | SUBTARGET_EXTRA_SPECS |
682 | \f | |
c98f8742 JVA |
683 | /* target machine storage layout */ |
684 | ||
2b589241 | 685 | /* Define for XFmode or TFmode extended real floating point support. |
2b589241 | 686 | The XFmode is specified by i386 ABI, while TFmode may be faster |
3dc85dfb | 687 | due to alignment and simplifications in the address calculations. */ |
2b589241 JH |
688 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96) |
689 | #define MAX_LONG_DOUBLE_TYPE_SIZE 128 | |
65d9c0ab JH |
690 | #ifdef __x86_64__ |
691 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
692 | #else | |
693 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 | |
694 | #endif | |
2b589241 | 695 | |
d57a4b98 RH |
696 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
697 | FPU, assume that the fpcw is set to extended precision; when using | |
698 | only SSE, rounding is correct; when using both SSE and the FPU, | |
699 | the rounding precision is indeterminate, since either may be chosen | |
700 | apparently at random. */ | |
701 | #define TARGET_FLT_EVAL_METHOD \ | |
702 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2) | |
0038aea6 | 703 | |
65d9c0ab JH |
704 | #define SHORT_TYPE_SIZE 16 |
705 | #define INT_TYPE_SIZE 32 | |
706 | #define FLOAT_TYPE_SIZE 32 | |
707 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
2faf6b96 | 708 | #define MAX_WCHAR_TYPE_SIZE 32 |
65d9c0ab JH |
709 | #define DOUBLE_TYPE_SIZE 64 |
710 | #define LONG_LONG_TYPE_SIZE 64 | |
711 | ||
67adf6a9 | 712 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 JH |
713 | #define MAX_BITS_PER_WORD 64 |
714 | #define MAX_LONG_TYPE_SIZE 64 | |
715 | #else | |
716 | #define MAX_BITS_PER_WORD 32 | |
717 | #define MAX_LONG_TYPE_SIZE 32 | |
718 | #endif | |
719 | ||
c98f8742 JVA |
720 | /* Define this if most significant byte of a word is the lowest numbered. */ |
721 | /* That is true on the 80386. */ | |
722 | ||
723 | #define BITS_BIG_ENDIAN 0 | |
724 | ||
725 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
726 | /* That is not true on the 80386. */ | |
727 | #define BYTES_BIG_ENDIAN 0 | |
728 | ||
729 | /* Define this if most significant word of a multiword number is the lowest | |
730 | numbered. */ | |
731 | /* Not true for 80386 */ | |
732 | #define WORDS_BIG_ENDIAN 0 | |
733 | ||
c98f8742 | 734 | /* Width of a word, in units (bytes). */ |
65d9c0ab | 735 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
2e64c636 JH |
736 | #ifdef IN_LIBGCC2 |
737 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
738 | #else | |
739 | #define MIN_UNITS_PER_WORD 4 | |
740 | #endif | |
c98f8742 | 741 | |
c98f8742 | 742 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 743 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 744 | |
e075ae69 | 745 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
65d9c0ab | 746 | #define STACK_BOUNDARY BITS_PER_WORD |
c98f8742 | 747 | |
3af4bd89 JH |
748 | /* Boundary (in *bits*) on which the stack pointer preferrs to be |
749 | aligned; the compiler cannot rely on having this alignment. */ | |
e075ae69 | 750 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 751 | |
1d482056 RH |
752 | /* As of July 2001, many runtimes to not align the stack properly when |
753 | entering main. This causes expand_main_function to forcably align | |
754 | the stack, which results in aligned frames for functions called from | |
755 | main, though it does nothing for the alignment of main itself. */ | |
756 | #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ | |
14f73b5a | 757 | (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) |
1d482056 | 758 | |
f963b5d9 RS |
759 | /* Minimum allocation boundary for the code of a function. */ |
760 | #define FUNCTION_BOUNDARY 8 | |
761 | ||
762 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
763 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 764 | |
892a2d68 | 765 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 766 | |
65d9c0ab | 767 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
768 | |
769 | /* Minimum size in bits of the largest boundary to which any | |
770 | and all fundamental data types supported by the hardware | |
771 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 772 | rounder than this. |
fce5a9f2 | 773 | |
3e18fdf6 | 774 | Pentium+ preferrs DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
775 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
776 | ||
777 | #define BIGGEST_ALIGNMENT 128 | |
778 | ||
822eda12 | 779 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 780 | #define ALIGN_MODE_128(MODE) \ |
822eda12 | 781 | ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 782 | |
17f24ff0 | 783 | /* The published ABIs say that doubles should be aligned on word |
6fc605d8 ZW |
784 | boundaries, so lower the aligment for structure fields unless |
785 | -malign-double is set. */ | |
e932b21b | 786 | |
e83f3cff RH |
787 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
788 | supports no vector modes, cut out the complexity and fall back | |
789 | on BIGGEST_FIELD_ALIGNMENT. */ | |
790 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
791 | #ifdef __x86_64__ |
792 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
793 | #else | |
e83f3cff | 794 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 795 | #endif |
e83f3cff | 796 | #else |
e932b21b JH |
797 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
798 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 799 | #endif |
c98f8742 | 800 | |
e5e8a8bf | 801 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 802 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
803 | and ALIGN is the alignment that the object would ordinarily have. |
804 | The value of this macro is used instead of that alignment to align | |
805 | the object. | |
806 | ||
807 | If this macro is not defined, then ALIGN is used. | |
808 | ||
809 | The typical use of this macro is to increase alignment for string | |
810 | constants to be word aligned so that `strcpy' calls that copy | |
811 | constants can be done inline. */ | |
812 | ||
d9a5f180 | 813 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 814 | |
8a022443 JW |
815 | /* If defined, a C expression to compute the alignment for a static |
816 | variable. TYPE is the data type, and ALIGN is the alignment that | |
817 | the object would ordinarily have. The value of this macro is used | |
818 | instead of that alignment to align the object. | |
819 | ||
820 | If this macro is not defined, then ALIGN is used. | |
821 | ||
822 | One use of this macro is to increase alignment of medium-size | |
823 | data to make it all fit in fewer cache lines. Another is to | |
824 | cause character arrays to be word-aligned so that `strcpy' calls | |
825 | that copy constants to character arrays can be done inline. */ | |
826 | ||
d9a5f180 | 827 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
828 | |
829 | /* If defined, a C expression to compute the alignment for a local | |
830 | variable. TYPE is the data type, and ALIGN is the alignment that | |
831 | the object would ordinarily have. The value of this macro is used | |
832 | instead of that alignment to align the object. | |
833 | ||
834 | If this macro is not defined, then ALIGN is used. | |
835 | ||
836 | One use of this macro is to increase alignment of medium-size | |
837 | data to make it all fit in fewer cache lines. */ | |
838 | ||
d9a5f180 | 839 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) |
8a022443 | 840 | |
53c17031 JH |
841 | /* If defined, a C expression that gives the alignment boundary, in |
842 | bits, of an argument with the specified mode and type. If it is | |
843 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
844 | ||
d9a5f180 GS |
845 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
846 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 847 | |
9cd10576 | 848 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 849 | when given unaligned data. */ |
b4ac57ab | 850 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
851 | |
852 | /* If bit field type is int, don't let it cross an int, | |
853 | and give entire struct the alignment of an int. */ | |
43a88a8c | 854 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 855 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
856 | \f |
857 | /* Standard register usage. */ | |
858 | ||
859 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 860 | for details. */ |
c98f8742 JVA |
861 | |
862 | #define STACK_REGS | |
d9a5f180 GS |
863 | #define IS_STACK_MODE(MODE) \ |
864 | ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \ | |
865 | || (MODE) == TFmode) | |
c98f8742 JVA |
866 | |
867 | /* Number of actual hardware registers. | |
868 | The hardware registers are assigned numbers for the compiler | |
869 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
870 | All registers that the compiler knows about must be given numbers, | |
871 | even those that are not normally considered general registers. | |
872 | ||
873 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
874 | We number the floating point registers 8-15. | |
875 | Note that registers 0-7 can be accessed as a short or int, | |
876 | while only 0-3 may be used with byte `mov' instructions. | |
877 | ||
878 | Reg 16 does not correspond to any hardware register, but instead | |
879 | appears in the RTL as an argument pointer prior to reload, and is | |
880 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 881 | pointer. */ |
c98f8742 | 882 | |
3f3f2124 | 883 | #define FIRST_PSEUDO_REGISTER 53 |
c98f8742 | 884 | |
3073d01c ML |
885 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
886 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
887 | ||
888 | #define DWARF_FRAME_REGISTERS 17 | |
889 | ||
c98f8742 JVA |
890 | /* 1 for registers that have pervasive standard uses |
891 | and are not available for the register allocator. | |
3f3f2124 | 892 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 893 | |
3f3f2124 JH |
894 | The value is an mask - bit 1 is set for fixed registers |
895 | for 32bit target, while 2 is set for fixed registers for 64bit. | |
896 | Proper value is computed in the CONDITIONAL_REGISTER_USAGE. | |
897 | */ | |
a7180f70 BS |
898 | #define FIXED_REGISTERS \ |
899 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3f3f2124 | 900 | { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \ |
a7180f70 | 901 | /*arg,flags,fpsr,dir,frame*/ \ |
3f3f2124 | 902 | 3, 3, 3, 3, 3, \ |
a7180f70 BS |
903 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
904 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
905 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
3f3f2124 JH |
906 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
907 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
908 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
909 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
910 | 1, 1, 1, 1, 1, 1, 1, 1} | |
fce5a9f2 | 911 | |
c98f8742 JVA |
912 | |
913 | /* 1 for registers not available across function calls. | |
914 | These must include the FIXED_REGISTERS and also any | |
915 | registers that can be used without being saved. | |
916 | The latter must include the registers where values are returned | |
917 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
918 | Aside from that, you can include as many other registers as you like. |
919 | ||
3f3f2124 JH |
920 | The value is an mask - bit 1 is set for call used |
921 | for 32bit target, while 2 is set for call used for 64bit. | |
922 | Proper value is computed in the CONDITIONAL_REGISTER_USAGE. | |
923 | */ | |
a7180f70 BS |
924 | #define CALL_USED_REGISTERS \ |
925 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3f3f2124 | 926 | { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \ |
a7180f70 | 927 | /*arg,flags,fpsr,dir,frame*/ \ |
3f3f2124 | 928 | 3, 3, 3, 3, 3, \ |
a7180f70 | 929 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
3f3f2124 | 930 | 3, 3, 3, 3, 3, 3, 3, 3, \ |
a7180f70 | 931 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
3f3f2124 JH |
932 | 3, 3, 3, 3, 3, 3, 3, 3, \ |
933 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
934 | 3, 3, 3, 3, 1, 1, 1, 1, \ | |
935 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
936 | 3, 3, 3, 3, 3, 3, 3, 3} \ | |
c98f8742 | 937 | |
3b3c6a3f MM |
938 | /* Order in which to allocate registers. Each register must be |
939 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
940 | late and fixed registers last. Note that, in general, we prefer | |
941 | registers listed in CALL_USED_REGISTERS, keeping the others | |
942 | available for storage of persistent values. | |
943 | ||
162f023b JH |
944 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
945 | so this is just empty initializer for array. */ | |
3b3c6a3f | 946 | |
162f023b JH |
947 | #define REG_ALLOC_ORDER \ |
948 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
949 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
950 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
951 | 48, 49, 50, 51, 52 } | |
3b3c6a3f | 952 | |
162f023b JH |
953 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
954 | to be rearranged based on a particular function. When using sse math, | |
955 | we want to allocase SSE before x87 registers and vice vera. */ | |
3b3c6a3f | 956 | |
162f023b | 957 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 958 | |
f5316dfe | 959 | |
c98f8742 | 960 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 961 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 962 | do { \ |
3f3f2124 JH |
963 | int i; \ |
964 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
965 | { \ | |
966 | fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \ | |
967 | call_used_regs[i] = (call_used_regs[i] \ | |
968 | & (TARGET_64BIT ? 2 : 1)) != 0; \ | |
969 | } \ | |
5b43fed1 | 970 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
a7180f70 BS |
971 | { \ |
972 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
973 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
974 | } \ | |
975 | if (! TARGET_MMX) \ | |
976 | { \ | |
977 | int i; \ | |
978 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
979 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
980 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
981 | } \ | |
982 | if (! TARGET_SSE) \ | |
983 | { \ | |
984 | int i; \ | |
985 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
986 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
987 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
988 | } \ | |
989 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
990 | { \ | |
991 | int i; \ | |
992 | HARD_REG_SET x; \ | |
993 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
994 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
995 | if (TEST_HARD_REG_BIT (x, i)) \ | |
996 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
997 | } \ | |
d9a5f180 | 998 | } while (0) |
c98f8742 JVA |
999 | |
1000 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
1001 | to hold something of mode MODE. | |
1002 | This is ordinarily the length in words of a value of mode MODE | |
1003 | but can be less for certain modes in special long registers. | |
1004 | ||
fce5a9f2 | 1005 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
1006 | registers. And only registers 0-3 may have mov byte instructions |
1007 | applied to them. | |
1008 | */ | |
1009 | ||
1010 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
92d0fb09 JH |
1011 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
1012 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
d9a5f180 | 1013 | : ((MODE) == TFmode \ |
92d0fb09 | 1014 | ? (TARGET_64BIT ? 2 : 3) \ |
d9a5f180 | 1015 | : (MODE) == TCmode \ |
92d0fb09 | 1016 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1017 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1018 | |
fbe5eb6d BS |
1019 | #define VALID_SSE2_REG_MODE(MODE) \ |
1020 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1021 | || (MODE) == V2DImode) | |
1022 | ||
d9a5f180 GS |
1023 | #define VALID_SSE_REG_MODE(MODE) \ |
1024 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1025 | || (MODE) == SFmode \ | |
fbe5eb6d BS |
1026 | /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \ |
1027 | || VALID_SSE2_REG_MODE (MODE) \ | |
141e454b | 1028 | || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE)))) |
a7180f70 | 1029 | |
47f339cf BS |
1030 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
1031 | ((MODE) == V2SFmode || (MODE) == SFmode) | |
1032 | ||
d9a5f180 GS |
1033 | #define VALID_MMX_REG_MODE(MODE) \ |
1034 | ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ | |
a7180f70 BS |
1035 | || (MODE) == V2SImode || (MODE) == SImode) |
1036 | ||
1037 | #define VECTOR_MODE_SUPPORTED_P(MODE) \ | |
1038 | (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \ | |
47f339cf BS |
1039 | : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \ |
1040 | : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0) | |
a7180f70 | 1041 | |
d9a5f180 GS |
1042 | #define VALID_FP_MODE_P(MODE) \ |
1043 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ | |
1044 | || (!TARGET_64BIT && (MODE) == XFmode) \ | |
1045 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \ | |
1046 | || (!TARGET_64BIT && (MODE) == XCmode)) | |
a946dd00 | 1047 | |
d9a5f180 GS |
1048 | #define VALID_INT_MODE_P(MODE) \ |
1049 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
1050 | || (MODE) == DImode \ | |
1051 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1052 | || (MODE) == CDImode \ | |
1053 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode))) | |
a946dd00 | 1054 | |
822eda12 JH |
1055 | /* Return true for modes passed in SSE registers. */ |
1056 | #define SSE_REG_MODE_P(MODE) \ | |
1057 | ((MODE) == TImode || (MODE) == V16QImode \ | |
1058 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ | |
1059 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
1060 | ||
1061 | /* Return true for modes passed in MMX registers. */ | |
1062 | #define MMX_REG_MODE_P(MODE) \ | |
1063 | ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \ | |
1064 | || (MODE) == V2SFmode) | |
1065 | ||
e075ae69 | 1066 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1067 | |
a946dd00 | 1068 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1069 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1070 | |
1071 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1072 | when one has mode MODE1 and one has mode MODE2. | |
1073 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1074 | for any hard reg, then this must be 0 for correct output. */ | |
1075 | ||
95912252 RH |
1076 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
1077 | ((MODE1) == (MODE2) \ | |
d2836273 JH |
1078 | || (((MODE1) == HImode || (MODE1) == SImode \ |
1079 | || ((MODE1) == QImode \ | |
1080 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ | |
1081 | || ((MODE1) == DImode && TARGET_64BIT)) \ | |
1082 | && ((MODE2) == HImode || (MODE2) == SImode \ | |
1083 | || ((MODE1) == QImode \ | |
1084 | && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \ | |
1085 | || ((MODE2) == DImode && TARGET_64BIT)))) | |
1086 | ||
c98f8742 | 1087 | |
e075ae69 | 1088 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1089 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1090 | |
787dc842 JH |
1091 | Kill any attempts to combine saving of modes. */ |
1092 | ||
d9a5f180 GS |
1093 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1094 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1095 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
1096 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \ | |
1097 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ | |
1098 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
d2836273 | 1099 | : (MODE)) |
c98f8742 JVA |
1100 | /* Specify the registers used for certain standard purposes. |
1101 | The values of these macros are register numbers. */ | |
1102 | ||
1103 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1104 | register. The ordinary mov instructions won't work */ | |
1105 | /* #define PC_REGNUM */ | |
1106 | ||
1107 | /* Register to use for pushing function arguments. */ | |
1108 | #define STACK_POINTER_REGNUM 7 | |
1109 | ||
1110 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1111 | #define HARD_FRAME_POINTER_REGNUM 6 |
1112 | ||
1113 | /* Base register for access to local variables of the function. */ | |
1114 | #define FRAME_POINTER_REGNUM 20 | |
c98f8742 JVA |
1115 | |
1116 | /* First floating point reg */ | |
1117 | #define FIRST_FLOAT_REG 8 | |
1118 | ||
1119 | /* First & last stack-like regs */ | |
1120 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1121 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1122 | ||
e075ae69 RH |
1123 | #define FLAGS_REG 17 |
1124 | #define FPSR_REG 18 | |
7c7ef435 | 1125 | #define DIRFLAG_REG 19 |
e075ae69 | 1126 | |
a7180f70 BS |
1127 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1128 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1129 | |
a7180f70 BS |
1130 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1131 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1132 | ||
3f3f2124 JH |
1133 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1134 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1135 | ||
1136 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1137 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1138 | ||
c98f8742 JVA |
1139 | /* Value should be nonzero if functions must have frame pointers. |
1140 | Zero means the frame pointer need not be set up (and parms | |
1141 | may be accessed via the stack pointer) in functions that seem suitable. | |
1142 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
1143 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1144 | ||
1145 | /* Override this in other tm.h files to cope with various OS losage | |
1146 | requiring a frame pointer. */ | |
1147 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1148 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1149 | #endif | |
1150 | ||
1151 | /* Make sure we can access arbitrary call frames. */ | |
1152 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1153 | |
1154 | /* Base register for access to arguments of the function. */ | |
1155 | #define ARG_POINTER_REGNUM 16 | |
1156 | ||
d2836273 JH |
1157 | /* Register in which static-chain is passed to a function. |
1158 | We do use ECX as static chain register for 32 bit ABI. On the | |
1159 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
1160 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) | |
c98f8742 JVA |
1161 | |
1162 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1163 | code access to data items. We don't use PIC pointer for 64bit |
1164 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1165 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1166 | |
1167 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1168 | the pic register when possible. The change is visible after the | |
1169 | prologue has been emitted. */ | |
1170 | ||
1171 | #define REAL_PIC_OFFSET_TABLE_REGNUM 3 | |
1172 | ||
1173 | #define PIC_OFFSET_TABLE_REGNUM \ | |
1174 | (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \ | |
1175 | : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
1176 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1177 | |
5fc0e5df KW |
1178 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1179 | ||
c98f8742 JVA |
1180 | /* Register in which address to store a structure value |
1181 | arrives in the function. On the 386, the prologue | |
1182 | copies this from the stack to register %eax. */ | |
1183 | #define STRUCT_VALUE_INCOMING 0 | |
1184 | ||
1185 | /* Place in which caller passes the structure value address. | |
1186 | 0 means push the value on the stack like an argument. */ | |
1187 | #define STRUCT_VALUE 0 | |
713225d4 MM |
1188 | |
1189 | /* A C expression which can inhibit the returning of certain function | |
1190 | values in registers, based on the type of value. A nonzero value | |
1191 | says to return the function value in memory, just as large | |
1192 | structures are always returned. Here TYPE will be a C expression | |
1193 | of type `tree', representing the data type of the value. | |
1194 | ||
1195 | Note that values of mode `BLKmode' must be explicitly handled by | |
1196 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
1197 | regardless of this macro. On most systems, it is possible to | |
1198 | leave the macro undefined; this causes a default definition to be | |
1199 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
1200 | otherwise. | |
1201 | ||
1202 | Do not use this macro to indicate that structures and unions | |
1203 | should always be returned in memory. You should instead use | |
1204 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
1205 | ||
d9a5f180 | 1206 | #define RETURN_IN_MEMORY(TYPE) \ |
53c17031 | 1207 | ix86_return_in_memory (TYPE) |
713225d4 | 1208 | |
c98f8742 JVA |
1209 | \f |
1210 | /* Define the classes of registers for register constraints in the | |
1211 | machine description. Also define ranges of constants. | |
1212 | ||
1213 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1214 | If there is more than one class, another class must be named NO_REGS | |
1215 | and contain no registers. | |
1216 | ||
1217 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1218 | another name such as ALL_REGS). This is the class of registers | |
1219 | that is allowed by "g" or "r" in a register constraint. | |
1220 | Also, registers outside this class are allocated only when | |
1221 | instructions express preferences for them. | |
1222 | ||
1223 | The classes must be numbered in nondecreasing order; that is, | |
1224 | a larger-numbered class must never be contained completely | |
1225 | in a smaller-numbered class. | |
1226 | ||
1227 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1228 | class that represents their union. |
1229 | ||
1230 | It might seem that class BREG is unnecessary, since no useful 386 | |
1231 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1232 | and the "b" register constraint is useful in asms for syscalls. |
1233 | ||
1234 | The flags and fpsr registers are in no class. */ | |
c98f8742 JVA |
1235 | |
1236 | enum reg_class | |
1237 | { | |
1238 | NO_REGS, | |
e075ae69 | 1239 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1240 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1241 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1242 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1243 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1244 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1245 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1246 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1247 | FLOAT_REGS, | |
a7180f70 BS |
1248 | SSE_REGS, |
1249 | MMX_REGS, | |
446988df JH |
1250 | FP_TOP_SSE_REGS, |
1251 | FP_SECOND_SSE_REGS, | |
1252 | FLOAT_SSE_REGS, | |
1253 | FLOAT_INT_REGS, | |
1254 | INT_SSE_REGS, | |
1255 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1256 | ALL_REGS, LIM_REG_CLASSES |
1257 | }; | |
1258 | ||
d9a5f180 GS |
1259 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1260 | ||
1261 | #define INTEGER_CLASS_P(CLASS) \ | |
1262 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1263 | #define FLOAT_CLASS_P(CLASS) \ | |
1264 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1265 | #define SSE_CLASS_P(CLASS) \ | |
1266 | reg_class_subset_p ((CLASS), SSE_REGS) | |
1267 | #define MMX_CLASS_P(CLASS) \ | |
1268 | reg_class_subset_p ((CLASS), MMX_REGS) | |
1269 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ | |
1270 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1271 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1272 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1273 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1274 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1275 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1276 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1277 | ||
1278 | #define Q_CLASS_P(CLASS) \ | |
1279 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1280 | |
c98f8742 JVA |
1281 | /* Give names of register classes as strings for dump file. */ |
1282 | ||
1283 | #define REG_CLASS_NAMES \ | |
1284 | { "NO_REGS", \ | |
ab408a86 | 1285 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1286 | "SIREG", "DIREG", \ |
e075ae69 RH |
1287 | "AD_REGS", \ |
1288 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1289 | "INDEX_REGS", \ |
3f3f2124 | 1290 | "LEGACY_REGS", \ |
c98f8742 JVA |
1291 | "GENERAL_REGS", \ |
1292 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1293 | "FLOAT_REGS", \ | |
a7180f70 BS |
1294 | "SSE_REGS", \ |
1295 | "MMX_REGS", \ | |
446988df JH |
1296 | "FP_TOP_SSE_REGS", \ |
1297 | "FP_SECOND_SSE_REGS", \ | |
1298 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1299 | "FLOAT_INT_REGS", \ |
446988df JH |
1300 | "INT_SSE_REGS", \ |
1301 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1302 | "ALL_REGS" } |
1303 | ||
1304 | /* Define which registers fit in which classes. | |
1305 | This is an initializer for a vector of HARD_REG_SET | |
1306 | of length N_REG_CLASSES. */ | |
1307 | ||
a7180f70 | 1308 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1309 | { { 0x00, 0x0 }, \ |
1310 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1311 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1312 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1313 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1314 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
1315 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ | |
1316 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1317 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1318 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
1319 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ | |
1320 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
1321 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ | |
1322 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1323 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1324 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1325 | { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ | |
1326 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1327 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1328 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1329 | { 0xffffffff,0x1fffff } \ | |
e075ae69 | 1330 | } |
c98f8742 JVA |
1331 | |
1332 | /* The same information, inverted: | |
1333 | Return the class number of the smallest class containing | |
1334 | reg number REGNO. This could be a conditional expression | |
1335 | or could index an array. */ | |
1336 | ||
c98f8742 JVA |
1337 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1338 | ||
1339 | /* When defined, the compiler allows registers explicitly used in the | |
1340 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1341 | extending the lifetime of these registers. */ |
c98f8742 | 1342 | |
2922fe9e | 1343 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 JVA |
1344 | |
1345 | #define QI_REG_P(X) \ | |
1346 | (REG_P (X) && REGNO (X) < 4) | |
3f3f2124 | 1347 | |
d9a5f180 GS |
1348 | #define GENERAL_REGNO_P(N) \ |
1349 | ((N) < 8 || REX_INT_REGNO_P (N)) | |
3f3f2124 JH |
1350 | |
1351 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1352 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1353 | |
1354 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1355 | ||
c98f8742 JVA |
1356 | #define NON_QI_REG_P(X) \ |
1357 | (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) | |
1358 | ||
d9a5f180 | 1359 | #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG) |
3f3f2124 JH |
1360 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1361 | ||
c98f8742 | 1362 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1363 | #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG) |
446988df | 1364 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1365 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1366 | |
d9a5f180 GS |
1367 | #define SSE_REGNO_P(N) \ |
1368 | (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \ | |
1369 | || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)) | |
3f3f2124 | 1370 | |
4977bab6 ZW |
1371 | #define REX_SSE_REGNO_P(N) \ |
1372 | ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG) | |
1373 | ||
d9a5f180 GS |
1374 | #define SSE_REGNO(N) \ |
1375 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
1376 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) | |
446988df | 1377 | |
d9a5f180 | 1378 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1379 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1380 | |
d9a5f180 GS |
1381 | #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG) |
1382 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) | |
fce5a9f2 | 1383 | |
d9a5f180 GS |
1384 | #define STACK_REG_P(XOP) \ |
1385 | (REG_P (XOP) && \ | |
1386 | REGNO (XOP) >= FIRST_STACK_REG && \ | |
1387 | REGNO (XOP) <= LAST_STACK_REG) | |
c98f8742 | 1388 | |
d9a5f180 | 1389 | #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP)) |
c98f8742 | 1390 | |
d9a5f180 | 1391 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1392 | |
e075ae69 RH |
1393 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1394 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1395 | ||
cdbca172 JO |
1396 | /* Indicate whether hard register numbered REG_NO should be converted |
1397 | to SSA form. */ | |
1398 | #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \ | |
d9a5f180 | 1399 | ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM) |
cdbca172 | 1400 | |
c98f8742 JVA |
1401 | /* The class value for index registers, and the one for base regs. */ |
1402 | ||
1403 | #define INDEX_REG_CLASS INDEX_REGS | |
1404 | #define BASE_REG_CLASS GENERAL_REGS | |
1405 | ||
1406 | /* Get reg_class from a letter such as appears in the machine description. */ | |
1407 | ||
1408 | #define REG_CLASS_FROM_LETTER(C) \ | |
8c2bf92a | 1409 | ((C) == 'r' ? GENERAL_REGS : \ |
3f3f2124 JH |
1410 | (C) == 'R' ? LEGACY_REGS : \ |
1411 | (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \ | |
1412 | (C) == 'Q' ? Q_REGS : \ | |
8c2bf92a JVA |
1413 | (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ |
1414 | ? FLOAT_REGS \ | |
1415 | : NO_REGS) : \ | |
1416 | (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1417 | ? FP_TOP_REG \ | |
1418 | : NO_REGS) : \ | |
1419 | (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
1420 | ? FP_SECOND_REG \ | |
1421 | : NO_REGS) : \ | |
1422 | (C) == 'a' ? AREG : \ | |
1423 | (C) == 'b' ? BREG : \ | |
1424 | (C) == 'c' ? CREG : \ | |
1425 | (C) == 'd' ? DREG : \ | |
446988df JH |
1426 | (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \ |
1427 | (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \ | |
1428 | (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \ | |
4b71cd6e | 1429 | (C) == 'A' ? AD_REGS : \ |
8c2bf92a | 1430 | (C) == 'D' ? DIREG : \ |
c98f8742 JVA |
1431 | (C) == 'S' ? SIREG : NO_REGS) |
1432 | ||
1433 | /* The letters I, J, K, L and M in a register constraint string | |
1434 | can be used to stand for particular ranges of immediate operands. | |
1435 | This macro defines what the ranges are. | |
1436 | C is the letter, and VALUE is a constant value. | |
1437 | Return 1 if VALUE is in the range specified by C. | |
1438 | ||
1439 | I is for non-DImode shifts. | |
1440 | J is for DImode shifts. | |
e075ae69 RH |
1441 | K is for signed imm8 operands. |
1442 | L is for andsi as zero-extending move. | |
c98f8742 | 1443 | M is for shifts that can be executed by the "lea" opcode. |
1aa9fd24 | 1444 | N is for immedaite operands for out/in instructions (0-255) |
c98f8742 JVA |
1445 | */ |
1446 | ||
e075ae69 RH |
1447 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1448 | ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ | |
1449 | : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ | |
1450 | : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ | |
1451 | : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ | |
1452 | : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ | |
1aa9fd24 | 1453 | : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \ |
e075ae69 | 1454 | : 0) |
c98f8742 JVA |
1455 | |
1456 | /* Similar, but for floating constants, and defining letters G and H. | |
b4ac57ab RS |
1457 | Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if |
1458 | TARGET_387 isn't set, because the stack register converter may need to | |
c47f5ea5 | 1459 | load 0.0 into the function value register. */ |
c98f8742 JVA |
1460 | |
1461 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
2b04e52b | 1462 | ((C) == 'G' ? standard_80387_constant_p (VALUE) \ |
f8ca7923 | 1463 | : 0) |
c98f8742 | 1464 | |
6189a572 JH |
1465 | /* A C expression that defines the optional machine-dependent |
1466 | constraint letters that can be used to segregate specific types of | |
1467 | operands, usually memory references, for the target machine. Any | |
1468 | letter that is not elsewhere defined and not matched by | |
1469 | `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not | |
1470 | be defined. | |
1471 | ||
1472 | If it is required for a particular target machine, it should | |
1473 | return 1 if VALUE corresponds to the operand type represented by | |
1474 | the constraint letter C. If C is not defined as an extra | |
1475 | constraint, the value returned should be 0 regardless of VALUE. */ | |
1476 | ||
0e67d460 | 1477 | #define EXTRA_CONSTRAINT(VALUE, D) \ |
c05dbe81 | 1478 | ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \ |
0e67d460 JH |
1479 | : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \ |
1480 | : (D) == 'C' ? standard_sse_constant_p (VALUE) \ | |
6189a572 JH |
1481 | : 0) |
1482 | ||
c98f8742 | 1483 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1484 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1485 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1486 | |
d2836273 JH |
1487 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1488 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1489 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1490 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1491 | ? Q_REGS : (CLASS)) |
1492 | ||
1493 | /* Given an rtx X being reloaded into a reg required to be | |
1494 | in class CLASS, return the class of reg to actually use. | |
1495 | In general this is just CLASS; but on some machines | |
1496 | in some cases it is preferable to use a more restrictive class. | |
1497 | On the 80386 series, we prevent floating constants from being | |
1498 | reloaded into floating registers (since no move-insn can do that) | |
1499 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1500 | ||
d398b3b1 | 1501 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1502 | QImode must go into class Q_REGS. |
d398b3b1 | 1503 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1504 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1505 | |
d9a5f180 GS |
1506 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1507 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e JVA |
1508 | |
1509 | /* If we are copying between general and FP registers, we need a memory | |
f84aa48a | 1510 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1511 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1512 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 RH |
1513 | |
1514 | /* QImode spills from non-QI registers need a scratch. This does not | |
fce5a9f2 | 1515 | happen often -- the only example so far requires an uninitialized |
e075ae69 RH |
1516 | pseudo. */ |
1517 | ||
d9a5f180 | 1518 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ |
3b8d200e JJ |
1519 | (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ |
1520 | || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ | |
d2836273 | 1521 | ? Q_REGS : NO_REGS) |
c98f8742 JVA |
1522 | |
1523 | /* Return the maximum number of consecutive registers | |
1524 | needed to represent mode MODE in a register of class CLASS. */ | |
1525 | /* On the 80386, this is the size of MODE in words, | |
92d0fb09 JH |
1526 | except in the FP regs, where a single reg is always enough. |
1527 | The TFmodes are really just 80bit values, so we use only 3 registers | |
1528 | to hold them, instead of 4, as the size would suggest. | |
1529 | */ | |
a7180f70 | 1530 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1531 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1532 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
1533 | : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \ | |
1534 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1535 | |
1536 | /* A C expression whose value is nonzero if pseudos that have been | |
1537 | assigned to registers of class CLASS would likely be spilled | |
1538 | because registers of CLASS are needed for spill registers. | |
1539 | ||
1540 | The default value of this macro returns 1 if CLASS has exactly one | |
1541 | register and zero otherwise. On most machines, this default | |
1542 | should be used. Only define this macro to some other expression | |
1543 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1544 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1545 | macro returns nonzero for those classes, those pseudos will only |
1546 | be allocated by `global.c', which knows how to reallocate the | |
1547 | pseudo to another register. If there would not be another | |
1548 | register available for reallocation, you should not change the | |
1549 | definition of this macro since the only effect of such a | |
1550 | definition would be to slow down register allocation. */ | |
1551 | ||
1552 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1553 | (((CLASS) == AREG) \ | |
1554 | || ((CLASS) == DREG) \ | |
1555 | || ((CLASS) == CREG) \ | |
1556 | || ((CLASS) == BREG) \ | |
1557 | || ((CLASS) == AD_REGS) \ | |
1558 | || ((CLASS) == SIREG) \ | |
1559 | || ((CLASS) == DIREG)) | |
1560 | ||
e075ae69 | 1561 | /* A C statement that adds to CLOBBERS any hard regs the port wishes |
fce5a9f2 | 1562 | to automatically clobber for all asms. |
e075ae69 RH |
1563 | |
1564 | We do this in the new i386 backend to maintain source compatibility | |
1565 | with the old cc0-based compiler. */ | |
1566 | ||
d9a5f180 GS |
1567 | #define MD_ASM_CLOBBERS(CLOBBERS) \ |
1568 | do { \ | |
1569 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \ | |
1570 | (CLOBBERS)); \ | |
1571 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \ | |
1572 | (CLOBBERS)); \ | |
1573 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \ | |
1574 | (CLOBBERS)); \ | |
e075ae69 | 1575 | } while (0) |
c98f8742 JVA |
1576 | \f |
1577 | /* Stack layout; function entry, exit and calling. */ | |
1578 | ||
1579 | /* Define this if pushing a word on the stack | |
1580 | makes the stack pointer a smaller address. */ | |
1581 | #define STACK_GROWS_DOWNWARD | |
1582 | ||
1583 | /* Define this if the nominal address of the stack frame | |
1584 | is at the high-address end of the local variables; | |
1585 | that is, each additional local variable allocated | |
1586 | goes at a more negative offset in the frame. */ | |
1587 | #define FRAME_GROWS_DOWNWARD | |
1588 | ||
1589 | /* Offset within stack frame to start allocating local variables at. | |
1590 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1591 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1592 | of the first local allocated. */ | |
1593 | #define STARTING_FRAME_OFFSET 0 | |
1594 | ||
1595 | /* If we generate an insn to push BYTES bytes, | |
1596 | this says how many the stack pointer really advances by. | |
1597 | On 386 pushw decrements by exactly 2 no matter what the position was. | |
1598 | On the 386 there is no pushb; we use pushw instead, and this | |
d2836273 | 1599 | has the effect of rounding up to 2. |
fce5a9f2 | 1600 | |
d2836273 JH |
1601 | For 64bit ABI we round up to 8 bytes. |
1602 | */ | |
c98f8742 | 1603 | |
d2836273 JH |
1604 | #define PUSH_ROUNDING(BYTES) \ |
1605 | (TARGET_64BIT \ | |
1606 | ? (((BYTES) + 7) & (-8)) \ | |
1607 | : (((BYTES) + 1) & (-2))) | |
c98f8742 | 1608 | |
f73ad30e JH |
1609 | /* If defined, the maximum amount of space required for outgoing arguments will |
1610 | be computed and placed into the variable | |
1611 | `current_function_outgoing_args_size'. No space will be pushed onto the | |
1612 | stack for each call; instead, the function prologue should increase the stack | |
1613 | frame size by this amount. */ | |
1614 | ||
1615 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1616 | ||
1617 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1618 | instructions to pass outgoing arguments. */ | |
1619 | ||
1620 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1621 | ||
2da4124d L |
1622 | /* We want the stack and args grow in opposite directions, even if |
1623 | PUSH_ARGS is 0. */ | |
1624 | #define PUSH_ARGS_REVERSED 1 | |
1625 | ||
c98f8742 JVA |
1626 | /* Offset of first parameter from the argument pointer register value. */ |
1627 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1628 | ||
a7180f70 BS |
1629 | /* Define this macro if functions should assume that stack space has been |
1630 | allocated for arguments even when their values are passed in registers. | |
1631 | ||
1632 | The value of this macro is the size, in bytes, of the area reserved for | |
1633 | arguments passed in registers for the function represented by FNDECL. | |
1634 | ||
1635 | This space can be allocated by the caller, or be a part of the | |
1636 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1637 | which. */ | |
1638 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
1639 | ||
1640 | /* Define as a C expression that evaluates to nonzero if we do not know how | |
1641 | to pass TYPE solely in registers. The file expr.h defines a | |
1642 | definition that is usually appropriate, refer to expr.h for additional | |
1643 | documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be | |
1644 | computed in the stack and then loaded into a register. */ | |
d9a5f180 GS |
1645 | #define MUST_PASS_IN_STACK(MODE, TYPE) \ |
1646 | ((TYPE) != 0 \ | |
1647 | && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ | |
1648 | || TREE_ADDRESSABLE (TYPE) \ | |
1649 | || ((MODE) == TImode) \ | |
1650 | || ((MODE) == BLKmode \ | |
1651 | && ! ((TYPE) != 0 \ | |
1652 | && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ | |
1653 | && 0 == (int_size_in_bytes (TYPE) \ | |
1654 | % (PARM_BOUNDARY / BITS_PER_UNIT))) \ | |
1655 | && (FUNCTION_ARG_PADDING (MODE, TYPE) \ | |
a7180f70 BS |
1656 | == (BYTES_BIG_ENDIAN ? upward : downward))))) |
1657 | ||
c98f8742 JVA |
1658 | /* Value is the number of bytes of arguments automatically |
1659 | popped when returning from a subroutine call. | |
8b109b37 | 1660 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1661 | FUNTYPE is the data type of the function (as a tree), |
1662 | or for a library call it is an identifier node for the subroutine name. | |
1663 | SIZE is the number of bytes of arguments passed on the stack. | |
1664 | ||
1665 | On the 80386, the RTD insn may be used to pop them if the number | |
1666 | of args is fixed, but if the number is variable then the caller | |
1667 | must pop them all. RTD can't be used for library calls now | |
1668 | because the library is compiled with the Unix compiler. | |
1669 | Use of RTD is a selectable option, since it is incompatible with | |
1670 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1671 | the caller must always pop the args. |
1672 | ||
1673 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1674 | |
d9a5f180 GS |
1675 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1676 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1677 | |
8c2bf92a JVA |
1678 | /* Define how to find the value returned by a function. |
1679 | VALTYPE is the data type of the value (as a tree). | |
1680 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1681 | otherwise, FUNC is 0. */ | |
c98f8742 | 1682 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
53c17031 JH |
1683 | ix86_function_value (VALTYPE) |
1684 | ||
1685 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
1686 | ix86_function_value_regno_p (N) | |
c98f8742 JVA |
1687 | |
1688 | /* Define how to find the value returned by a library function | |
1689 | assuming the value has mode MODE. */ | |
1690 | ||
1691 | #define LIBCALL_VALUE(MODE) \ | |
53c17031 | 1692 | ix86_libcall_value (MODE) |
c98f8742 | 1693 | |
e9125c09 TW |
1694 | /* Define the size of the result block used for communication between |
1695 | untyped_call and untyped_return. The block contains a DImode value | |
1696 | followed by the block used by fnsave and frstor. */ | |
1697 | ||
1698 | #define APPLY_RESULT_SIZE (8+108) | |
1699 | ||
b08de47e | 1700 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1701 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1702 | |
1703 | /* Define a data type for recording info about an argument list | |
1704 | during the scan of that argument list. This data type should | |
1705 | hold all necessary information about the function itself | |
1706 | and about the args processed so far, enough to enable macros | |
b08de47e | 1707 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1708 | |
e075ae69 | 1709 | typedef struct ix86_args { |
b08de47e MM |
1710 | int words; /* # words passed so far */ |
1711 | int nregs; /* # registers available for passing */ | |
1712 | int regno; /* next available register number */ | |
a7180f70 BS |
1713 | int sse_words; /* # sse words passed so far */ |
1714 | int sse_nregs; /* # sse registers available for passing */ | |
1715 | int sse_regno; /* next available sse register number */ | |
892a2d68 | 1716 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
b08de47e | 1717 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1718 | |
1719 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1720 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1721 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1722 | |
d9a5f180 GS |
1723 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ |
1724 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME)) | |
c98f8742 JVA |
1725 | |
1726 | /* Update the data in CUM to advance over an argument | |
1727 | of mode MODE and data type TYPE. | |
1728 | (TYPE is null for libcalls where that information may not be available.) */ | |
1729 | ||
d9a5f180 GS |
1730 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1731 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1732 | |
1733 | /* Define where to put the arguments to a function. | |
1734 | Value is zero to push the argument on the stack, | |
1735 | or a hard register in which to store the argument. | |
1736 | ||
1737 | MODE is the argument's machine mode. | |
1738 | TYPE is the data type of the argument (as a tree). | |
1739 | This is null for libcalls where that information may | |
1740 | not be available. | |
1741 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1742 | the preceding args and about the function being called. | |
1743 | NAMED is nonzero if this argument is a named parameter | |
1744 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1745 | ||
c98f8742 | 1746 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1747 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 JVA |
1748 | |
1749 | /* For an arg passed partly in registers and partly in memory, | |
1750 | this is the number of registers used. | |
1751 | For args passed entirely in registers or entirely in memory, zero. */ | |
1752 | ||
e075ae69 | 1753 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
c98f8742 | 1754 | |
ad919812 JH |
1755 | /* Perform any needed actions needed for a function that is receiving a |
1756 | variable number of arguments. | |
1757 | ||
1758 | CUM is as above. | |
1759 | ||
1760 | MODE and TYPE are the mode and type of the current parameter. | |
1761 | ||
1762 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1763 | that must be pushed by the prolog to pretend that our caller pushed | |
1764 | it. | |
1765 | ||
1766 | Normally, this macro will push all remaining incoming registers on the | |
1767 | stack and set PRETEND_SIZE to the length of the registers pushed. */ | |
1768 | ||
d9a5f180 GS |
1769 | #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ |
1770 | ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \ | |
1771 | (NO_RTL)) | |
ad919812 JH |
1772 | |
1773 | /* Define the `__builtin_va_list' type for the ABI. */ | |
1774 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
d9a5f180 | 1775 | ((VALIST) = ix86_build_va_list ()) |
ad919812 JH |
1776 | |
1777 | /* Implement `va_start' for varargs and stdarg. */ | |
e5faf155 ZW |
1778 | #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ |
1779 | ix86_va_start (VALIST, NEXTARG) | |
ad919812 JH |
1780 | |
1781 | /* Implement `va_arg'. */ | |
d9a5f180 GS |
1782 | #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \ |
1783 | ix86_va_arg ((VALIST), (TYPE)) | |
ad919812 | 1784 | |
4cf12e7e RH |
1785 | /* This macro is invoked at the end of compilation. It is used here to |
1786 | output code for -fpic that will load the return address into %ebx. */ | |
3a0433fd | 1787 | |
4cf12e7e RH |
1788 | #undef ASM_FILE_END |
1789 | #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE) | |
3a0433fd | 1790 | |
c98f8742 JVA |
1791 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1792 | for profiling a function entry. */ | |
1793 | ||
a5fa1ecd JH |
1794 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1795 | ||
1796 | #define MCOUNT_NAME "_mcount" | |
1797 | ||
1798 | #define PROFILE_COUNT_REGISTER "edx" | |
c98f8742 JVA |
1799 | |
1800 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1801 | the stack pointer does not matter. The value is tested only in | |
1802 | functions that have frame pointers. | |
1803 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1804 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1805 | we have to restore it ourselves from the frame pointer, in order to |
1806 | use pop */ | |
1807 | ||
1808 | #define EXIT_IGNORE_STACK 1 | |
1809 | ||
c98f8742 JVA |
1810 | /* Output assembler code for a block containing the constant parts |
1811 | of a trampoline, leaving space for the variable parts. */ | |
1812 | ||
a269a03c | 1813 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1814 | mov #STATIC,ecx |
a269a03c JC |
1815 | jmp FUNCTION |
1816 | The trampoline is generated entirely at runtime. The operand of JMP | |
1817 | is the address of FUNCTION relative to the instruction following the | |
1818 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1819 | |
1820 | /* Length in units of the trampoline for entering a nested function. */ | |
1821 | ||
39d04363 | 1822 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1823 | |
1824 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1825 | FNADDR is an RTX for the address of the function's pure code. | |
1826 | CXT is an RTX for the static chain value for the function. */ | |
1827 | ||
d9a5f180 GS |
1828 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1829 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1830 | \f |
1831 | /* Definitions for register eliminations. | |
1832 | ||
1833 | This is an array of structures. Each structure initializes one pair | |
1834 | of eliminable registers. The "from" register number is given first, | |
1835 | followed by "to". Eliminations of the same "from" register are listed | |
1836 | in order of preference. | |
1837 | ||
afc2cd05 NC |
1838 | There are two registers that can always be eliminated on the i386. |
1839 | The frame pointer and the arg pointer can be replaced by either the | |
1840 | hard frame pointer or to the stack pointer, depending upon the | |
1841 | circumstances. The hard frame pointer is not used before reload and | |
1842 | so it is not eligible for elimination. */ | |
c98f8742 | 1843 | |
564d80f4 JH |
1844 | #define ELIMINABLE_REGS \ |
1845 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1846 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1847 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1848 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1849 | |
2c5a510c RH |
1850 | /* Given FROM and TO register numbers, say whether this elimination is |
1851 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1852 | |
1853 | All other eliminations are valid. */ | |
1854 | ||
2c5a510c RH |
1855 | #define CAN_ELIMINATE(FROM, TO) \ |
1856 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
c98f8742 JVA |
1857 | |
1858 | /* Define the offset between two registers, one to be eliminated, and the other | |
1859 | its replacement, at the start of a routine. */ | |
1860 | ||
d9a5f180 GS |
1861 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1862 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1863 | \f |
1864 | /* Addressing modes, and classification of registers for them. */ | |
1865 | ||
c98f8742 JVA |
1866 | /* Macros to check register numbers against specific register classes. */ |
1867 | ||
1868 | /* These assume that REGNO is a hard or pseudo reg number. | |
1869 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1870 | or a pseudo reg currently allocated to a suitable hard reg. | |
1871 | Since they use reg_renumber, they are safe only once reg_renumber | |
1872 | has been allocated, which happens in local-alloc.c. */ | |
1873 | ||
3f3f2124 JH |
1874 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1875 | ((REGNO) < STACK_POINTER_REGNUM \ | |
1876 | || (REGNO >= FIRST_REX_INT_REG \ | |
1877 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1878 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1879 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1880 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM) | |
c98f8742 | 1881 | |
3f3f2124 JH |
1882 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
1883 | ((REGNO) <= STACK_POINTER_REGNUM \ | |
1884 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1885 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1886 | || (REGNO >= FIRST_REX_INT_REG \ | |
1887 | && (REGNO) <= LAST_REX_INT_REG) \ | |
d9a5f180 GS |
1888 | || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \ |
1889 | && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \ | |
1890 | || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM) | |
c98f8742 | 1891 | |
d9a5f180 GS |
1892 | #define REGNO_OK_FOR_SIREG_P(REGNO) \ |
1893 | ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) | |
1894 | #define REGNO_OK_FOR_DIREG_P(REGNO) \ | |
1895 | ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) | |
c98f8742 JVA |
1896 | |
1897 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1898 | and check its validity for a certain class. | |
1899 | We have two alternate definitions for each of them. | |
1900 | The usual definition accepts all pseudo regs; the other rejects | |
1901 | them unless they have been allocated suitable hard regs. | |
1902 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1903 | ||
1904 | Most source files want to accept pseudo regs in the hope that | |
1905 | they will get allocated to the class that the insn wants them to be in. | |
1906 | Source files for reload pass need to be strict. | |
1907 | After reload, it makes no difference, since pseudo regs have | |
1908 | been eliminated by then. */ | |
1909 | ||
c98f8742 | 1910 | |
3b3c6a3f MM |
1911 | /* Non strict versions, pseudos are ok */ |
1912 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
1913 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
3f3f2124 JH |
1914 | || (REGNO (X) >= FIRST_REX_INT_REG \ |
1915 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
c98f8742 JVA |
1916 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1917 | ||
3b3c6a3f MM |
1918 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
1919 | (REGNO (X) <= STACK_POINTER_REGNUM \ | |
1920 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
3f3f2124 JH |
1921 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
1922 | || (REGNO (X) >= FIRST_REX_INT_REG \ | |
1923 | && REGNO (X) <= LAST_REX_INT_REG) \ | |
3b3c6a3f | 1924 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1925 | |
3b3c6a3f MM |
1926 | /* Strict versions, hard registers only */ |
1927 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1928 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1929 | |
3b3c6a3f | 1930 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1931 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1932 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1933 | |
1934 | #else | |
d9a5f180 GS |
1935 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1936 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1937 | #endif |
1938 | ||
1939 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1940 | that is a valid memory address for an instruction. | |
1941 | The MODE argument is the machine mode for the MEM expression | |
1942 | that wants to use this address. | |
1943 | ||
1944 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1945 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1946 | ||
1947 | See legitimize_pic_address in i386.c for details as to what | |
1948 | constitutes a legitimate address when -fpic is used. */ | |
1949 | ||
1950 | #define MAX_REGS_PER_ADDRESS 2 | |
1951 | ||
f996902d | 1952 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1953 | |
1954 | /* Nonzero if the constant value X is a legitimate general operand. | |
1955 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1956 | ||
f996902d | 1957 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1958 | |
3b3c6a3f MM |
1959 | #ifdef REG_OK_STRICT |
1960 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1961 | do { \ |
1962 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1963 | goto ADDR; \ |
d9a5f180 | 1964 | } while (0) |
c98f8742 | 1965 | |
3b3c6a3f MM |
1966 | #else |
1967 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1968 | do { \ |
1969 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1970 | goto ADDR; \ |
d9a5f180 | 1971 | } while (0) |
c98f8742 | 1972 | |
3b3c6a3f MM |
1973 | #endif |
1974 | ||
b949ea8b JW |
1975 | /* If defined, a C expression to determine the base term of address X. |
1976 | This macro is used in only one place: `find_base_term' in alias.c. | |
1977 | ||
1978 | It is always safe for this macro to not be defined. It exists so | |
1979 | that alias analysis can understand machine-dependent addresses. | |
1980 | ||
1981 | The typical use of this macro is to handle addresses containing | |
1982 | a label_ref or symbol_ref within an UNSPEC. */ | |
1983 | ||
d9a5f180 | 1984 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1985 | |
c98f8742 JVA |
1986 | /* Try machine-dependent ways of modifying an illegitimate address |
1987 | to be legitimate. If we find one, return the new, valid address. | |
1988 | This macro is used in only one place: `memory_address' in explow.c. | |
1989 | ||
1990 | OLDX is the address as it was before break_out_memory_refs was called. | |
1991 | In some cases it is useful to look at this to decide what needs to be done. | |
1992 | ||
1993 | MODE and WIN are passed so that this macro can use | |
1994 | GO_IF_LEGITIMATE_ADDRESS. | |
1995 | ||
1996 | It is always safe for this macro to do nothing. It exists to recognize | |
1997 | opportunities to optimize the output. | |
1998 | ||
1999 | For the 80386, we handle X+REG by loading X into a register R and | |
2000 | using R+REG. R will go in a general reg and indexing will be used. | |
2001 | However, if REG is a broken-out memory address or multiplication, | |
2002 | nothing needs to be done because REG can certainly go in a general reg. | |
2003 | ||
2004 | When -fpic is used, special handling is needed for symbolic references. | |
2005 | See comments by legitimize_pic_address in i386.c for details. */ | |
2006 | ||
3b3c6a3f | 2007 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
2008 | do { \ |
2009 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
2010 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 2011 | goto WIN; \ |
d9a5f180 | 2012 | } while (0) |
c98f8742 | 2013 | |
d9a5f180 | 2014 | #define REWRITE_ADDRESS(X) rewrite_address (X) |
d4ba09c0 | 2015 | |
c98f8742 | 2016 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 2017 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
2018 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
2019 | ||
f996902d | 2020 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
2021 | |
2022 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
2023 | (GET_CODE (X) == SYMBOL_REF \ |
2024 | || GET_CODE (X) == LABEL_REF \ | |
2025 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
2026 | |
2027 | /* Go to LABEL if ADDR (a legitimate address expression) | |
2028 | has an effect that depends on the machine mode it is used for. | |
2029 | On the 80386, only postdecrement and postincrement address depend thus | |
2030 | (the amount of decrement or increment being the length of the operand). */ | |
d9a5f180 GS |
2031 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
2032 | do { \ | |
2033 | if (GET_CODE (ADDR) == POST_INC \ | |
2034 | || GET_CODE (ADDR) == POST_DEC) \ | |
2035 | goto LABEL; \ | |
2036 | } while (0) | |
c98f8742 | 2037 | \f |
bd793c65 BS |
2038 | /* Codes for all the SSE/MMX builtins. */ |
2039 | enum ix86_builtins | |
2040 | { | |
2041 | IX86_BUILTIN_ADDPS, | |
2042 | IX86_BUILTIN_ADDSS, | |
2043 | IX86_BUILTIN_DIVPS, | |
2044 | IX86_BUILTIN_DIVSS, | |
2045 | IX86_BUILTIN_MULPS, | |
2046 | IX86_BUILTIN_MULSS, | |
2047 | IX86_BUILTIN_SUBPS, | |
2048 | IX86_BUILTIN_SUBSS, | |
2049 | ||
2050 | IX86_BUILTIN_CMPEQPS, | |
2051 | IX86_BUILTIN_CMPLTPS, | |
2052 | IX86_BUILTIN_CMPLEPS, | |
2053 | IX86_BUILTIN_CMPGTPS, | |
2054 | IX86_BUILTIN_CMPGEPS, | |
2055 | IX86_BUILTIN_CMPNEQPS, | |
2056 | IX86_BUILTIN_CMPNLTPS, | |
2057 | IX86_BUILTIN_CMPNLEPS, | |
2058 | IX86_BUILTIN_CMPNGTPS, | |
2059 | IX86_BUILTIN_CMPNGEPS, | |
2060 | IX86_BUILTIN_CMPORDPS, | |
2061 | IX86_BUILTIN_CMPUNORDPS, | |
2062 | IX86_BUILTIN_CMPNEPS, | |
2063 | IX86_BUILTIN_CMPEQSS, | |
2064 | IX86_BUILTIN_CMPLTSS, | |
2065 | IX86_BUILTIN_CMPLESS, | |
bd793c65 BS |
2066 | IX86_BUILTIN_CMPNEQSS, |
2067 | IX86_BUILTIN_CMPNLTSS, | |
2068 | IX86_BUILTIN_CMPNLESS, | |
bd793c65 BS |
2069 | IX86_BUILTIN_CMPORDSS, |
2070 | IX86_BUILTIN_CMPUNORDSS, | |
2071 | IX86_BUILTIN_CMPNESS, | |
2072 | ||
2073 | IX86_BUILTIN_COMIEQSS, | |
2074 | IX86_BUILTIN_COMILTSS, | |
2075 | IX86_BUILTIN_COMILESS, | |
2076 | IX86_BUILTIN_COMIGTSS, | |
2077 | IX86_BUILTIN_COMIGESS, | |
2078 | IX86_BUILTIN_COMINEQSS, | |
2079 | IX86_BUILTIN_UCOMIEQSS, | |
2080 | IX86_BUILTIN_UCOMILTSS, | |
2081 | IX86_BUILTIN_UCOMILESS, | |
2082 | IX86_BUILTIN_UCOMIGTSS, | |
2083 | IX86_BUILTIN_UCOMIGESS, | |
2084 | IX86_BUILTIN_UCOMINEQSS, | |
2085 | ||
2086 | IX86_BUILTIN_CVTPI2PS, | |
2087 | IX86_BUILTIN_CVTPS2PI, | |
2088 | IX86_BUILTIN_CVTSI2SS, | |
2089 | IX86_BUILTIN_CVTSS2SI, | |
2090 | IX86_BUILTIN_CVTTPS2PI, | |
2091 | IX86_BUILTIN_CVTTSS2SI, | |
bd793c65 BS |
2092 | |
2093 | IX86_BUILTIN_MAXPS, | |
2094 | IX86_BUILTIN_MAXSS, | |
2095 | IX86_BUILTIN_MINPS, | |
2096 | IX86_BUILTIN_MINSS, | |
2097 | ||
2098 | IX86_BUILTIN_LOADAPS, | |
2099 | IX86_BUILTIN_LOADUPS, | |
2100 | IX86_BUILTIN_STOREAPS, | |
2101 | IX86_BUILTIN_STOREUPS, | |
2102 | IX86_BUILTIN_LOADSS, | |
2103 | IX86_BUILTIN_STORESS, | |
2104 | IX86_BUILTIN_MOVSS, | |
2105 | ||
2106 | IX86_BUILTIN_MOVHLPS, | |
2107 | IX86_BUILTIN_MOVLHPS, | |
2108 | IX86_BUILTIN_LOADHPS, | |
2109 | IX86_BUILTIN_LOADLPS, | |
2110 | IX86_BUILTIN_STOREHPS, | |
2111 | IX86_BUILTIN_STORELPS, | |
2112 | ||
2113 | IX86_BUILTIN_MASKMOVQ, | |
2114 | IX86_BUILTIN_MOVMSKPS, | |
2115 | IX86_BUILTIN_PMOVMSKB, | |
2116 | ||
2117 | IX86_BUILTIN_MOVNTPS, | |
2118 | IX86_BUILTIN_MOVNTQ, | |
2119 | ||
f02e1358 JH |
2120 | IX86_BUILTIN_LOADDQA, |
2121 | IX86_BUILTIN_LOADDQU, | |
2122 | IX86_BUILTIN_STOREDQA, | |
2123 | IX86_BUILTIN_STOREDQU, | |
2124 | IX86_BUILTIN_MOVQ, | |
2125 | IX86_BUILTIN_LOADD, | |
2126 | IX86_BUILTIN_STORED, | |
2127 | ||
2128 | IX86_BUILTIN_CLRTI, | |
2129 | ||
bd793c65 BS |
2130 | IX86_BUILTIN_PACKSSWB, |
2131 | IX86_BUILTIN_PACKSSDW, | |
2132 | IX86_BUILTIN_PACKUSWB, | |
2133 | ||
2134 | IX86_BUILTIN_PADDB, | |
2135 | IX86_BUILTIN_PADDW, | |
2136 | IX86_BUILTIN_PADDD, | |
2137 | IX86_BUILTIN_PADDSB, | |
2138 | IX86_BUILTIN_PADDSW, | |
2139 | IX86_BUILTIN_PADDUSB, | |
2140 | IX86_BUILTIN_PADDUSW, | |
2141 | IX86_BUILTIN_PSUBB, | |
2142 | IX86_BUILTIN_PSUBW, | |
2143 | IX86_BUILTIN_PSUBD, | |
2144 | IX86_BUILTIN_PSUBSB, | |
2145 | IX86_BUILTIN_PSUBSW, | |
2146 | IX86_BUILTIN_PSUBUSB, | |
2147 | IX86_BUILTIN_PSUBUSW, | |
2148 | ||
2149 | IX86_BUILTIN_PAND, | |
2150 | IX86_BUILTIN_PANDN, | |
2151 | IX86_BUILTIN_POR, | |
2152 | IX86_BUILTIN_PXOR, | |
2153 | ||
2154 | IX86_BUILTIN_PAVGB, | |
2155 | IX86_BUILTIN_PAVGW, | |
2156 | ||
2157 | IX86_BUILTIN_PCMPEQB, | |
2158 | IX86_BUILTIN_PCMPEQW, | |
2159 | IX86_BUILTIN_PCMPEQD, | |
2160 | IX86_BUILTIN_PCMPGTB, | |
2161 | IX86_BUILTIN_PCMPGTW, | |
2162 | IX86_BUILTIN_PCMPGTD, | |
2163 | ||
2164 | IX86_BUILTIN_PEXTRW, | |
2165 | IX86_BUILTIN_PINSRW, | |
2166 | ||
2167 | IX86_BUILTIN_PMADDWD, | |
2168 | ||
2169 | IX86_BUILTIN_PMAXSW, | |
2170 | IX86_BUILTIN_PMAXUB, | |
2171 | IX86_BUILTIN_PMINSW, | |
2172 | IX86_BUILTIN_PMINUB, | |
2173 | ||
2174 | IX86_BUILTIN_PMULHUW, | |
2175 | IX86_BUILTIN_PMULHW, | |
2176 | IX86_BUILTIN_PMULLW, | |
2177 | ||
2178 | IX86_BUILTIN_PSADBW, | |
2179 | IX86_BUILTIN_PSHUFW, | |
2180 | ||
2181 | IX86_BUILTIN_PSLLW, | |
2182 | IX86_BUILTIN_PSLLD, | |
2183 | IX86_BUILTIN_PSLLQ, | |
2184 | IX86_BUILTIN_PSRAW, | |
2185 | IX86_BUILTIN_PSRAD, | |
2186 | IX86_BUILTIN_PSRLW, | |
2187 | IX86_BUILTIN_PSRLD, | |
2188 | IX86_BUILTIN_PSRLQ, | |
2189 | IX86_BUILTIN_PSLLWI, | |
2190 | IX86_BUILTIN_PSLLDI, | |
2191 | IX86_BUILTIN_PSLLQI, | |
2192 | IX86_BUILTIN_PSRAWI, | |
2193 | IX86_BUILTIN_PSRADI, | |
2194 | IX86_BUILTIN_PSRLWI, | |
2195 | IX86_BUILTIN_PSRLDI, | |
2196 | IX86_BUILTIN_PSRLQI, | |
2197 | ||
2198 | IX86_BUILTIN_PUNPCKHBW, | |
2199 | IX86_BUILTIN_PUNPCKHWD, | |
2200 | IX86_BUILTIN_PUNPCKHDQ, | |
2201 | IX86_BUILTIN_PUNPCKLBW, | |
2202 | IX86_BUILTIN_PUNPCKLWD, | |
2203 | IX86_BUILTIN_PUNPCKLDQ, | |
2204 | ||
2205 | IX86_BUILTIN_SHUFPS, | |
2206 | ||
2207 | IX86_BUILTIN_RCPPS, | |
2208 | IX86_BUILTIN_RCPSS, | |
2209 | IX86_BUILTIN_RSQRTPS, | |
2210 | IX86_BUILTIN_RSQRTSS, | |
2211 | IX86_BUILTIN_SQRTPS, | |
2212 | IX86_BUILTIN_SQRTSS, | |
fce5a9f2 | 2213 | |
bd793c65 BS |
2214 | IX86_BUILTIN_UNPCKHPS, |
2215 | IX86_BUILTIN_UNPCKLPS, | |
2216 | ||
2217 | IX86_BUILTIN_ANDPS, | |
2218 | IX86_BUILTIN_ANDNPS, | |
2219 | IX86_BUILTIN_ORPS, | |
2220 | IX86_BUILTIN_XORPS, | |
2221 | ||
2222 | IX86_BUILTIN_EMMS, | |
2223 | IX86_BUILTIN_LDMXCSR, | |
2224 | IX86_BUILTIN_STMXCSR, | |
2225 | IX86_BUILTIN_SFENCE, | |
bd793c65 | 2226 | |
47f339cf BS |
2227 | /* 3DNow! Original */ |
2228 | IX86_BUILTIN_FEMMS, | |
2229 | IX86_BUILTIN_PAVGUSB, | |
2230 | IX86_BUILTIN_PF2ID, | |
2231 | IX86_BUILTIN_PFACC, | |
2232 | IX86_BUILTIN_PFADD, | |
2233 | IX86_BUILTIN_PFCMPEQ, | |
2234 | IX86_BUILTIN_PFCMPGE, | |
2235 | IX86_BUILTIN_PFCMPGT, | |
2236 | IX86_BUILTIN_PFMAX, | |
2237 | IX86_BUILTIN_PFMIN, | |
2238 | IX86_BUILTIN_PFMUL, | |
2239 | IX86_BUILTIN_PFRCP, | |
2240 | IX86_BUILTIN_PFRCPIT1, | |
2241 | IX86_BUILTIN_PFRCPIT2, | |
2242 | IX86_BUILTIN_PFRSQIT1, | |
2243 | IX86_BUILTIN_PFRSQRT, | |
2244 | IX86_BUILTIN_PFSUB, | |
2245 | IX86_BUILTIN_PFSUBR, | |
2246 | IX86_BUILTIN_PI2FD, | |
2247 | IX86_BUILTIN_PMULHRW, | |
47f339cf BS |
2248 | |
2249 | /* 3DNow! Athlon Extensions */ | |
2250 | IX86_BUILTIN_PF2IW, | |
2251 | IX86_BUILTIN_PFNACC, | |
2252 | IX86_BUILTIN_PFPNACC, | |
2253 | IX86_BUILTIN_PI2FW, | |
2254 | IX86_BUILTIN_PSWAPDSI, | |
2255 | IX86_BUILTIN_PSWAPDSF, | |
2256 | ||
e37af218 | 2257 | IX86_BUILTIN_SSE_ZERO, |
bd793c65 BS |
2258 | IX86_BUILTIN_MMX_ZERO, |
2259 | ||
fbe5eb6d BS |
2260 | /* SSE2 */ |
2261 | IX86_BUILTIN_ADDPD, | |
2262 | IX86_BUILTIN_ADDSD, | |
2263 | IX86_BUILTIN_DIVPD, | |
2264 | IX86_BUILTIN_DIVSD, | |
2265 | IX86_BUILTIN_MULPD, | |
2266 | IX86_BUILTIN_MULSD, | |
2267 | IX86_BUILTIN_SUBPD, | |
2268 | IX86_BUILTIN_SUBSD, | |
2269 | ||
2270 | IX86_BUILTIN_CMPEQPD, | |
2271 | IX86_BUILTIN_CMPLTPD, | |
2272 | IX86_BUILTIN_CMPLEPD, | |
2273 | IX86_BUILTIN_CMPGTPD, | |
2274 | IX86_BUILTIN_CMPGEPD, | |
2275 | IX86_BUILTIN_CMPNEQPD, | |
2276 | IX86_BUILTIN_CMPNLTPD, | |
2277 | IX86_BUILTIN_CMPNLEPD, | |
2278 | IX86_BUILTIN_CMPNGTPD, | |
2279 | IX86_BUILTIN_CMPNGEPD, | |
2280 | IX86_BUILTIN_CMPORDPD, | |
2281 | IX86_BUILTIN_CMPUNORDPD, | |
2282 | IX86_BUILTIN_CMPNEPD, | |
2283 | IX86_BUILTIN_CMPEQSD, | |
2284 | IX86_BUILTIN_CMPLTSD, | |
2285 | IX86_BUILTIN_CMPLESD, | |
fbe5eb6d BS |
2286 | IX86_BUILTIN_CMPNEQSD, |
2287 | IX86_BUILTIN_CMPNLTSD, | |
2288 | IX86_BUILTIN_CMPNLESD, | |
fbe5eb6d BS |
2289 | IX86_BUILTIN_CMPORDSD, |
2290 | IX86_BUILTIN_CMPUNORDSD, | |
2291 | IX86_BUILTIN_CMPNESD, | |
2292 | ||
2293 | IX86_BUILTIN_COMIEQSD, | |
2294 | IX86_BUILTIN_COMILTSD, | |
2295 | IX86_BUILTIN_COMILESD, | |
2296 | IX86_BUILTIN_COMIGTSD, | |
2297 | IX86_BUILTIN_COMIGESD, | |
2298 | IX86_BUILTIN_COMINEQSD, | |
2299 | IX86_BUILTIN_UCOMIEQSD, | |
2300 | IX86_BUILTIN_UCOMILTSD, | |
2301 | IX86_BUILTIN_UCOMILESD, | |
2302 | IX86_BUILTIN_UCOMIGTSD, | |
2303 | IX86_BUILTIN_UCOMIGESD, | |
2304 | IX86_BUILTIN_UCOMINEQSD, | |
2305 | ||
2306 | IX86_BUILTIN_MAXPD, | |
2307 | IX86_BUILTIN_MAXSD, | |
2308 | IX86_BUILTIN_MINPD, | |
2309 | IX86_BUILTIN_MINSD, | |
2310 | ||
2311 | IX86_BUILTIN_ANDPD, | |
2312 | IX86_BUILTIN_ANDNPD, | |
2313 | IX86_BUILTIN_ORPD, | |
2314 | IX86_BUILTIN_XORPD, | |
2315 | ||
2316 | IX86_BUILTIN_SQRTPD, | |
2317 | IX86_BUILTIN_SQRTSD, | |
2318 | ||
2319 | IX86_BUILTIN_UNPCKHPD, | |
2320 | IX86_BUILTIN_UNPCKLPD, | |
2321 | ||
2322 | IX86_BUILTIN_SHUFPD, | |
2323 | ||
2324 | IX86_BUILTIN_LOADAPD, | |
2325 | IX86_BUILTIN_LOADUPD, | |
2326 | IX86_BUILTIN_STOREAPD, | |
2327 | IX86_BUILTIN_STOREUPD, | |
2328 | IX86_BUILTIN_LOADSD, | |
2329 | IX86_BUILTIN_STORESD, | |
2330 | IX86_BUILTIN_MOVSD, | |
2331 | ||
2332 | IX86_BUILTIN_LOADHPD, | |
2333 | IX86_BUILTIN_LOADLPD, | |
2334 | IX86_BUILTIN_STOREHPD, | |
2335 | IX86_BUILTIN_STORELPD, | |
2336 | ||
2337 | IX86_BUILTIN_CVTDQ2PD, | |
2338 | IX86_BUILTIN_CVTDQ2PS, | |
2339 | ||
2340 | IX86_BUILTIN_CVTPD2DQ, | |
2341 | IX86_BUILTIN_CVTPD2PI, | |
2342 | IX86_BUILTIN_CVTPD2PS, | |
2343 | IX86_BUILTIN_CVTTPD2DQ, | |
2344 | IX86_BUILTIN_CVTTPD2PI, | |
2345 | ||
2346 | IX86_BUILTIN_CVTPI2PD, | |
2347 | IX86_BUILTIN_CVTSI2SD, | |
2348 | ||
2349 | IX86_BUILTIN_CVTSD2SI, | |
2350 | IX86_BUILTIN_CVTSD2SS, | |
2351 | IX86_BUILTIN_CVTSS2SD, | |
2352 | IX86_BUILTIN_CVTTSD2SI, | |
2353 | ||
2354 | IX86_BUILTIN_CVTPS2DQ, | |
2355 | IX86_BUILTIN_CVTPS2PD, | |
2356 | IX86_BUILTIN_CVTTPS2DQ, | |
2357 | ||
2358 | IX86_BUILTIN_MOVNTI, | |
2359 | IX86_BUILTIN_MOVNTPD, | |
2360 | IX86_BUILTIN_MOVNTDQ, | |
2361 | ||
2362 | IX86_BUILTIN_SETPD1, | |
2363 | IX86_BUILTIN_SETPD, | |
2364 | IX86_BUILTIN_CLRPD, | |
2365 | IX86_BUILTIN_SETRPD, | |
2366 | IX86_BUILTIN_LOADPD1, | |
2367 | IX86_BUILTIN_LOADRPD, | |
2368 | IX86_BUILTIN_STOREPD1, | |
2369 | IX86_BUILTIN_STORERPD, | |
2370 | ||
2371 | /* SSE2 MMX */ | |
2372 | IX86_BUILTIN_MASKMOVDQU, | |
2373 | IX86_BUILTIN_MOVMSKPD, | |
2374 | IX86_BUILTIN_PMOVMSKB128, | |
2375 | IX86_BUILTIN_MOVQ2DQ, | |
f02e1358 | 2376 | IX86_BUILTIN_MOVDQ2Q, |
fbe5eb6d BS |
2377 | |
2378 | IX86_BUILTIN_PACKSSWB128, | |
2379 | IX86_BUILTIN_PACKSSDW128, | |
2380 | IX86_BUILTIN_PACKUSWB128, | |
2381 | ||
2382 | IX86_BUILTIN_PADDB128, | |
2383 | IX86_BUILTIN_PADDW128, | |
2384 | IX86_BUILTIN_PADDD128, | |
2385 | IX86_BUILTIN_PADDQ128, | |
2386 | IX86_BUILTIN_PADDSB128, | |
2387 | IX86_BUILTIN_PADDSW128, | |
2388 | IX86_BUILTIN_PADDUSB128, | |
2389 | IX86_BUILTIN_PADDUSW128, | |
2390 | IX86_BUILTIN_PSUBB128, | |
2391 | IX86_BUILTIN_PSUBW128, | |
2392 | IX86_BUILTIN_PSUBD128, | |
2393 | IX86_BUILTIN_PSUBQ128, | |
2394 | IX86_BUILTIN_PSUBSB128, | |
2395 | IX86_BUILTIN_PSUBSW128, | |
2396 | IX86_BUILTIN_PSUBUSB128, | |
2397 | IX86_BUILTIN_PSUBUSW128, | |
2398 | ||
2399 | IX86_BUILTIN_PAND128, | |
2400 | IX86_BUILTIN_PANDN128, | |
2401 | IX86_BUILTIN_POR128, | |
2402 | IX86_BUILTIN_PXOR128, | |
2403 | ||
2404 | IX86_BUILTIN_PAVGB128, | |
2405 | IX86_BUILTIN_PAVGW128, | |
2406 | ||
2407 | IX86_BUILTIN_PCMPEQB128, | |
2408 | IX86_BUILTIN_PCMPEQW128, | |
2409 | IX86_BUILTIN_PCMPEQD128, | |
2410 | IX86_BUILTIN_PCMPGTB128, | |
2411 | IX86_BUILTIN_PCMPGTW128, | |
2412 | IX86_BUILTIN_PCMPGTD128, | |
2413 | ||
2414 | IX86_BUILTIN_PEXTRW128, | |
2415 | IX86_BUILTIN_PINSRW128, | |
2416 | ||
2417 | IX86_BUILTIN_PMADDWD128, | |
2418 | ||
2419 | IX86_BUILTIN_PMAXSW128, | |
2420 | IX86_BUILTIN_PMAXUB128, | |
2421 | IX86_BUILTIN_PMINSW128, | |
2422 | IX86_BUILTIN_PMINUB128, | |
2423 | ||
2424 | IX86_BUILTIN_PMULUDQ, | |
2425 | IX86_BUILTIN_PMULUDQ128, | |
2426 | IX86_BUILTIN_PMULHUW128, | |
2427 | IX86_BUILTIN_PMULHW128, | |
2428 | IX86_BUILTIN_PMULLW128, | |
2429 | ||
2430 | IX86_BUILTIN_PSADBW128, | |
2431 | IX86_BUILTIN_PSHUFHW, | |
2432 | IX86_BUILTIN_PSHUFLW, | |
2433 | IX86_BUILTIN_PSHUFD, | |
2434 | ||
2435 | IX86_BUILTIN_PSLLW128, | |
2436 | IX86_BUILTIN_PSLLD128, | |
2437 | IX86_BUILTIN_PSLLQ128, | |
2438 | IX86_BUILTIN_PSRAW128, | |
2439 | IX86_BUILTIN_PSRAD128, | |
2440 | IX86_BUILTIN_PSRLW128, | |
2441 | IX86_BUILTIN_PSRLD128, | |
2442 | IX86_BUILTIN_PSRLQ128, | |
ab3146fd | 2443 | IX86_BUILTIN_PSLLDQI128, |
fbe5eb6d BS |
2444 | IX86_BUILTIN_PSLLWI128, |
2445 | IX86_BUILTIN_PSLLDI128, | |
2446 | IX86_BUILTIN_PSLLQI128, | |
2447 | IX86_BUILTIN_PSRAWI128, | |
2448 | IX86_BUILTIN_PSRADI128, | |
ab3146fd | 2449 | IX86_BUILTIN_PSRLDQI128, |
fbe5eb6d BS |
2450 | IX86_BUILTIN_PSRLWI128, |
2451 | IX86_BUILTIN_PSRLDI128, | |
2452 | IX86_BUILTIN_PSRLQI128, | |
2453 | ||
2454 | IX86_BUILTIN_PUNPCKHBW128, | |
2455 | IX86_BUILTIN_PUNPCKHWD128, | |
2456 | IX86_BUILTIN_PUNPCKHDQ128, | |
077084dd | 2457 | IX86_BUILTIN_PUNPCKHQDQ128, |
fbe5eb6d BS |
2458 | IX86_BUILTIN_PUNPCKLBW128, |
2459 | IX86_BUILTIN_PUNPCKLWD128, | |
2460 | IX86_BUILTIN_PUNPCKLDQ128, | |
f02e1358 | 2461 | IX86_BUILTIN_PUNPCKLQDQ128, |
fbe5eb6d BS |
2462 | |
2463 | IX86_BUILTIN_CLFLUSH, | |
2464 | IX86_BUILTIN_MFENCE, | |
2465 | IX86_BUILTIN_LFENCE, | |
2466 | ||
bd793c65 BS |
2467 | IX86_BUILTIN_MAX |
2468 | }; | |
bd793c65 | 2469 | \f |
f996902d RH |
2470 | #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info |
2471 | #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding | |
2472 | ||
2473 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ | |
2474 | do { \ | |
2475 | const char *xname = (NAME); \ | |
2476 | if (xname[0] == '%') \ | |
2477 | xname += 2; \ | |
2478 | if (xname[0] == '*') \ | |
2479 | xname += 1; \ | |
2480 | else \ | |
2481 | fputs (user_label_prefix, FILE); \ | |
2482 | fputs (xname, FILE); \ | |
2483 | } while (0) | |
b08de47e | 2484 | \f |
b08de47e MM |
2485 | /* Max number of args passed in registers. If this is more than 3, we will |
2486 | have problems with ebx (register #4), since it is a caller save register and | |
2487 | is also used as the pic register in ELF. So for now, don't allow more than | |
2488 | 3 registers to be passed in registers. */ | |
2489 | ||
d2836273 JH |
2490 | #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) |
2491 | ||
df4e780e | 2492 | #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0) |
b08de47e | 2493 | |
c98f8742 JVA |
2494 | \f |
2495 | /* Specify the machine mode that this machine uses | |
2496 | for the index in the tablejump instruction. */ | |
6eb791fc | 2497 | #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) |
c98f8742 | 2498 | |
18543a22 ILT |
2499 | /* Define as C expression which evaluates to nonzero if the tablejump |
2500 | instruction expects the table to contain offsets from the address of the | |
2501 | table. | |
892a2d68 | 2502 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 2503 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ |
c98f8742 | 2504 | |
c98f8742 JVA |
2505 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
2506 | #define DEFAULT_SIGNED_CHAR 1 | |
2507 | ||
f4365627 JH |
2508 | /* Number of bytes moved into a data cache for a single prefetch operation. */ |
2509 | #define PREFETCH_BLOCK ix86_cost->prefetch_block | |
2510 | ||
2511 | /* Number of prefetch operations that can be done in parallel. */ | |
2512 | #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches | |
2513 | ||
c98f8742 JVA |
2514 | /* Max number of bytes we can move from memory to memory |
2515 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
2516 | #define MOVE_MAX 16 |
2517 | ||
2518 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
2519 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 2520 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 2521 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 2522 | |
7e24ffc9 HPN |
2523 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
2524 | move-instruction pairs, we will do a movstr or libcall instead. | |
2525 | Increasing the value will always make code faster, but eventually | |
2526 | incurs high cost in increased code size. | |
c98f8742 | 2527 | |
e2e52e1b | 2528 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 2529 | |
e2e52e1b | 2530 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 JVA |
2531 | |
2532 | /* Define if shifts truncate the shift count | |
2533 | which implies one can omit a sign-extension or zero-extension | |
2534 | of a shift count. */ | |
892a2d68 | 2535 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
2536 | |
2537 | /* #define SHIFT_COUNT_TRUNCATED */ | |
2538 | ||
2539 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
2540 | is done just by pretending it is already truncated. */ | |
2541 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2542 | ||
2543 | /* We assume that the store-condition-codes instructions store 0 for false | |
2544 | and some other value for true. This is the value stored for true. */ | |
2545 | ||
2546 | #define STORE_FLAG_VALUE 1 | |
2547 | ||
2548 | /* When a prototype says `char' or `short', really pass an `int'. | |
2549 | (The 386 can't easily push less than an int.) */ | |
2550 | ||
cb560352 | 2551 | #define PROMOTE_PROTOTYPES 1 |
c98f8742 | 2552 | |
d9f32422 JH |
2553 | /* A macro to update M and UNSIGNEDP when an object whose type is |
2554 | TYPE and which has the specified mode and signedness is to be | |
2555 | stored in a register. This macro is only called when TYPE is a | |
2556 | scalar type. | |
2557 | ||
f710504c | 2558 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
2559 | quantities to SImode. The choice depends on target type. */ |
2560 | ||
2561 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 2562 | do { \ |
d9f32422 JH |
2563 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
2564 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
2565 | (MODE) = SImode; \ |
2566 | } while (0) | |
d9f32422 | 2567 | |
c98f8742 JVA |
2568 | /* Specify the machine mode that pointers have. |
2569 | After generation of rtl, the compiler makes no further distinction | |
2570 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 2571 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
2572 | |
2573 | /* A function address in a call instruction | |
2574 | is a byte address (for indexing purposes) | |
2575 | so give the MEM rtx a byte's mode. */ | |
2576 | #define FUNCTION_MODE QImode | |
d4ba09c0 SC |
2577 | \f |
2578 | /* A part of a C `switch' statement that describes the relative costs | |
2579 | of constant RTL expressions. It must contain `case' labels for | |
2580 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
2581 | and `const_double'. Each case must ultimately reach a `return' | |
2582 | statement to return the relative cost of the use of that kind of | |
2583 | constant value in an expression. The cost may depend on the | |
2584 | precise value of the constant, which is available for examination | |
2585 | in X, and the rtx code of the expression in which it is contained, | |
2586 | found in OUTER_CODE. | |
fce5a9f2 | 2587 | |
d4ba09c0 SC |
2588 | CODE is the expression code--redundant, since it can be obtained |
2589 | with `GET_CODE (X)'. */ | |
c98f8742 | 2590 | |
d9a5f180 | 2591 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
c98f8742 JVA |
2592 | case CONST_INT: \ |
2593 | case CONST: \ | |
2594 | case LABEL_REF: \ | |
2595 | case SYMBOL_REF: \ | |
c05dbe81 | 2596 | if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \ |
44cf5b6a JH |
2597 | return 3; \ |
2598 | if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \ | |
2599 | return 2; \ | |
1acc845e | 2600 | return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \ |
d4ba09c0 | 2601 | \ |
c98f8742 | 2602 | case CONST_DOUBLE: \ |
51286de6 RH |
2603 | if (GET_MODE (RTX) == VOIDmode) \ |
2604 | return 0; \ | |
2605 | switch (standard_80387_constant_p (RTX)) \ | |
2606 | { \ | |
2607 | case 1: /* 0.0 */ \ | |
2608 | return 1; \ | |
2609 | case 2: /* 1.0 */ \ | |
2610 | return 2; \ | |
2611 | default: \ | |
2612 | /* Start with (MEM (SYMBOL_REF)), since that's where \ | |
2613 | it'll probably end up. Add a penalty for size. */ \ | |
2614 | return (COSTS_N_INSNS (1) + (flag_pic != 0) \ | |
2615 | + (GET_MODE (RTX) == SFmode ? 0 \ | |
2616 | : GET_MODE (RTX) == DFmode ? 1 : 2)); \ | |
2617 | } | |
c98f8742 | 2618 | |
76565a24 | 2619 | /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ |
e075ae69 RH |
2620 | #define TOPLEVEL_COSTS_N_INSNS(N) \ |
2621 | do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) | |
76565a24 | 2622 | |
4977bab6 ZW |
2623 | /* Return index of given mode in mult and division cost tables. */ |
2624 | #define MODE_INDEX(mode) \ | |
2625 | ((mode) == QImode ? 0 \ | |
2626 | : (mode) == HImode ? 1 \ | |
2627 | : (mode) == SImode ? 2 \ | |
2628 | : (mode) == DImode ? 3 \ | |
2629 | : 4) | |
2630 | ||
d4ba09c0 SC |
2631 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. |
2632 | This can be used, for example, to indicate how costly a multiply | |
2633 | instruction is. In writing this macro, you can use the construct | |
2634 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
2635 | instructions. OUTER_CODE is the code of the expression in which X | |
2636 | is contained. | |
2637 | ||
2638 | This macro is optional; do not define it if the default cost | |
2639 | assumptions are adequate for the target machine. */ | |
2640 | ||
d9a5f180 | 2641 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ |
44cf5b6a JH |
2642 | case ZERO_EXTEND: \ |
2643 | /* The zero extensions is often completely free on x86_64, so make \ | |
2644 | it as cheap as possible. */ \ | |
2645 | if (TARGET_64BIT && GET_MODE (X) == DImode \ | |
2646 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
2647 | { \ | |
2648 | total = 1; goto egress_rtx_costs; \ | |
2649 | } \ | |
2650 | else \ | |
2651 | TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \ | |
2652 | ix86_cost->add : ix86_cost->movzx); \ | |
2653 | break; \ | |
2654 | case SIGN_EXTEND: \ | |
2655 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \ | |
2656 | break; \ | |
d4ba09c0 SC |
2657 | case ASHIFT: \ |
2658 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
44cf5b6a | 2659 | && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \ |
d4ba09c0 SC |
2660 | { \ |
2661 | HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
d4ba09c0 | 2662 | if (value == 1) \ |
e075ae69 | 2663 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ |
b972dd02 JH |
2664 | if ((value == 2 || value == 3) \ |
2665 | && !TARGET_DECOMPOSE_LEA \ | |
2666 | && ix86_cost->lea <= ix86_cost->shift_const) \ | |
e075ae69 | 2667 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ |
d4ba09c0 SC |
2668 | } \ |
2669 | /* fall through */ \ | |
2670 | \ | |
2671 | case ROTATE: \ | |
2672 | case ASHIFTRT: \ | |
2673 | case LSHIFTRT: \ | |
2674 | case ROTATERT: \ | |
44cf5b6a | 2675 | if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \ |
76565a24 SC |
2676 | { \ |
2677 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
54d26233 MH |
2678 | { \ |
2679 | if (INTVAL (XEXP (X, 1)) > 32) \ | |
e075ae69 RH |
2680 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ |
2681 | else \ | |
2682 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ | |
2683 | } \ | |
2684 | else \ | |
2685 | { \ | |
2686 | if (GET_CODE (XEXP (X, 1)) == AND) \ | |
2687 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ | |
2688 | else \ | |
2689 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ | |
54d26233 | 2690 | } \ |
76565a24 | 2691 | } \ |
e075ae69 RH |
2692 | else \ |
2693 | { \ | |
2694 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
2695 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ | |
2696 | else \ | |
2697 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ | |
2698 | } \ | |
2699 | break; \ | |
d4ba09c0 SC |
2700 | \ |
2701 | case MULT: \ | |
229b303a RS |
2702 | if (FLOAT_MODE_P (GET_MODE (X))) \ |
2703 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fmul); \ | |
2704 | else if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
d4ba09c0 SC |
2705 | { \ |
2706 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
2707 | int nbits = 0; \ | |
2708 | \ | |
2709 | while (value != 0) \ | |
2710 | { \ | |
2711 | nbits++; \ | |
2712 | value >>= 1; \ | |
2713 | } \ | |
2714 | \ | |
630c79be | 2715 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
4977bab6 | 2716 | [MODE_INDEX (GET_MODE (X))] \ |
630c79be | 2717 | + nbits * ix86_cost->mult_bit); \ |
d4ba09c0 | 2718 | } \ |
d4ba09c0 | 2719 | else /* This is arbitrary */ \ |
76565a24 | 2720 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
4977bab6 | 2721 | [MODE_INDEX (GET_MODE (X))] \ |
76565a24 | 2722 | + 7 * ix86_cost->mult_bit); \ |
d4ba09c0 SC |
2723 | \ |
2724 | case DIV: \ | |
2725 | case UDIV: \ | |
2726 | case MOD: \ | |
2727 | case UMOD: \ | |
229b303a RS |
2728 | if (FLOAT_MODE_P (GET_MODE (X))) \ |
2729 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fdiv); \ | |
2730 | else \ | |
4977bab6 ZW |
2731 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide \ |
2732 | [MODE_INDEX (GET_MODE (X))]); \ | |
229b303a | 2733 | break; \ |
d4ba09c0 SC |
2734 | \ |
2735 | case PLUS: \ | |
229b303a RS |
2736 | if (FLOAT_MODE_P (GET_MODE (X))) \ |
2737 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ | |
2738 | else if (!TARGET_DECOMPOSE_LEA \ | |
b972dd02 JH |
2739 | && INTEGRAL_MODE_P (GET_MODE (X)) \ |
2740 | && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \ | |
e075ae69 | 2741 | { \ |
b972dd02 JH |
2742 | if (GET_CODE (XEXP (X, 0)) == PLUS \ |
2743 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ | |
2744 | && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ | |
2745 | && CONSTANT_P (XEXP (X, 1))) \ | |
e075ae69 | 2746 | { \ |
b972dd02 JH |
2747 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\ |
2748 | if (val == 2 || val == 4 || val == 8) \ | |
2749 | { \ | |
2750 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2751 | + rtx_cost (XEXP (XEXP (X, 0), 1), \ |
2752 | (OUTER_CODE)) \ | |
2753 | + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \ | |
2754 | (OUTER_CODE)) \ | |
2755 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
b972dd02 | 2756 | } \ |
e075ae69 | 2757 | } \ |
b972dd02 JH |
2758 | else if (GET_CODE (XEXP (X, 0)) == MULT \ |
2759 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
2760 | { \ | |
2761 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
2762 | if (val == 2 || val == 4 || val == 8) \ | |
2763 | { \ | |
2764 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2765 | + rtx_cost (XEXP (XEXP (X, 0), 0), \ |
2766 | (OUTER_CODE)) \ | |
2767 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
b972dd02 JH |
2768 | } \ |
2769 | } \ | |
2770 | else if (GET_CODE (XEXP (X, 0)) == PLUS) \ | |
e075ae69 RH |
2771 | { \ |
2772 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
d9a5f180 GS |
2773 | + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \ |
2774 | + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \ | |
2775 | + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \ | |
e075ae69 | 2776 | } \ |
e075ae69 | 2777 | } \ |
229b303a | 2778 | /* fall through */ \ |
d4ba09c0 | 2779 | \ |
229b303a RS |
2780 | case MINUS: \ |
2781 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
2782 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \ | |
d4ba09c0 | 2783 | /* fall through */ \ |
229b303a | 2784 | \ |
d4ba09c0 SC |
2785 | case AND: \ |
2786 | case IOR: \ | |
2787 | case XOR: \ | |
44cf5b6a | 2788 | if (!TARGET_64BIT && GET_MODE (X) == DImode) \ |
e075ae69 | 2789 | return (COSTS_N_INSNS (ix86_cost->add) * 2 \ |
d9a5f180 | 2790 | + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \ |
e075ae69 | 2791 | << (GET_MODE (XEXP (X, 0)) != DImode)) \ |
d9a5f180 | 2792 | + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \ |
e075ae69 | 2793 | << (GET_MODE (XEXP (X, 1)) != DImode))); \ |
e075ae69 | 2794 | /* fall through */ \ |
229b303a | 2795 | \ |
d4ba09c0 | 2796 | case NEG: \ |
229b303a RS |
2797 | if (FLOAT_MODE_P (GET_MODE (X))) \ |
2798 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fchs); \ | |
2799 | /* fall through */ \ | |
2800 | \ | |
d4ba09c0 | 2801 | case NOT: \ |
44cf5b6a | 2802 | if (!TARGET_64BIT && GET_MODE (X) == DImode) \ |
e075ae69 RH |
2803 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ |
2804 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ | |
2805 | \ | |
51286de6 | 2806 | case FLOAT_EXTEND: \ |
285464d0 JH |
2807 | if (!TARGET_SSE_MATH \ |
2808 | || !VALID_SSE_REG_MODE (GET_MODE (X))) \ | |
2809 | TOPLEVEL_COSTS_N_INSNS (0); \ | |
2810 | break; \ | |
51286de6 | 2811 | \ |
229b303a RS |
2812 | case ABS: \ |
2813 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
2814 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fabs); \ | |
2815 | break; \ | |
2816 | \ | |
2817 | case SQRT: \ | |
2818 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
2819 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->fsqrt); \ | |
2820 | break; \ | |
2821 | \ | |
e075ae69 RH |
2822 | egress_rtx_costs: \ |
2823 | break; | |
d4ba09c0 SC |
2824 | |
2825 | ||
2826 | /* An expression giving the cost of an addressing mode that contains | |
2827 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
2828 | expression and the `CONST_COSTS' values. | |
2829 | ||
2830 | For most CISC machines, the default cost is a good approximation | |
2831 | of the true cost of the addressing mode. However, on RISC | |
2832 | machines, all instructions normally have the same length and | |
2833 | execution time. Hence all addresses will have equal costs. | |
2834 | ||
2835 | In cases where more than one form of an address is known, the form | |
2836 | with the lowest cost will be used. If multiple forms have the | |
2837 | same, lowest, cost, the one that is the most complex will be used. | |
2838 | ||
2839 | For example, suppose an address that is equal to the sum of a | |
2840 | register and a constant is used twice in the same basic block. | |
2841 | When this macro is not defined, the address will be computed in a | |
2842 | register and memory references will be indirect through that | |
2843 | register. On machines where the cost of the addressing mode | |
2844 | containing the sum is no higher than that of a simple indirect | |
2845 | reference, this will produce an additional instruction and | |
2846 | possibly require an additional register. Proper specification of | |
2847 | this macro eliminates this overhead for such machines. | |
2848 | ||
2849 | Similar use of this macro is made in strength reduction of loops. | |
2850 | ||
2851 | ADDRESS need not be valid as an address. In such a case, the cost | |
2852 | is not relevant and can be any value; invalid addresses need not be | |
2853 | assigned a different cost. | |
2854 | ||
2855 | On machines where an address involving more than one register is as | |
2856 | cheap as an address computation involving only one register, | |
2857 | defining `ADDRESS_COST' to reflect this can cause two registers to | |
2858 | be live over a region of code where only one would have been if | |
2859 | `ADDRESS_COST' were not defined in that manner. This effect should | |
2860 | be considered in the definition of this macro. Equivalent costs | |
2861 | should probably only be given to addresses with different numbers | |
2862 | of registers on machines with lots of registers. | |
2863 | ||
2864 | This macro will normally either not be defined or be defined as a | |
2865 | constant. | |
c98f8742 JVA |
2866 | |
2867 | For i386, it is better to use a complex address than let gcc copy | |
2868 | the address into a reg and make a new pseudo. But not if the address | |
2869 | requires to two regs - that would mean more pseudos with longer | |
2870 | lifetimes. */ | |
2871 | ||
2872 | #define ADDRESS_COST(RTX) \ | |
0806f95f | 2873 | ix86_address_cost (RTX) |
d4ba09c0 | 2874 | |
96e7ae40 JH |
2875 | /* A C expression for the cost of moving data from a register in class FROM to |
2876 | one in class TO. The classes are expressed using the enumeration values | |
2877 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
2878 | interpreted relative to that. | |
d4ba09c0 | 2879 | |
96e7ae40 JH |
2880 | It is not required that the cost always equal 2 when FROM is the same as TO; |
2881 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 2882 | general registers. */ |
d4ba09c0 | 2883 | |
f84aa48a | 2884 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 2885 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
2886 | |
2887 | /* A C expression for the cost of moving data of mode M between a | |
2888 | register and memory. A value of 2 is the default; this cost is | |
2889 | relative to those in `REGISTER_MOVE_COST'. | |
2890 | ||
2891 | If moving between registers and memory is more expensive than | |
2892 | between two registers, you should define this macro to express the | |
fa79946e | 2893 | relative cost. */ |
d4ba09c0 | 2894 | |
d9a5f180 GS |
2895 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
2896 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
2897 | |
2898 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2899 | is the default; other values are interpreted relative to that. */ | |
2900 | ||
e075ae69 | 2901 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
2902 | |
2903 | /* Define this macro as a C expression which is nonzero if accessing | |
2904 | less than a word of memory (i.e. a `char' or a `short') is no | |
2905 | faster than accessing a word of memory, i.e., if such access | |
2906 | require more than one instruction or if there is no difference in | |
2907 | cost between byte and (aligned) word loads. | |
2908 | ||
2909 | When this macro is not defined, the compiler will access a field by | |
2910 | finding the smallest containing object; when it is defined, a | |
2911 | fullword load will be used if alignment permits. Unless bytes | |
2912 | accesses are faster than word accesses, using word accesses is | |
2913 | preferable since it may eliminate subsequent memory access if | |
2914 | subsequent accesses occur to other fields in the same word of the | |
2915 | structure, but to different bytes. */ | |
2916 | ||
2917 | #define SLOW_BYTE_ACCESS 0 | |
2918 | ||
2919 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2920 | #define SLOW_SHORT_ACCESS 0 | |
2921 | ||
d4ba09c0 SC |
2922 | /* Define this macro to be the value 1 if unaligned accesses have a |
2923 | cost many times greater than aligned accesses, for example if they | |
2924 | are emulated in a trap handler. | |
2925 | ||
9cd10576 KH |
2926 | When this macro is nonzero, the compiler will act as if |
2927 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2928 | moves. This can cause significantly more instructions to be |
9cd10576 | 2929 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2930 | accesses only add a cycle or two to the time for a memory access. |
2931 | ||
2932 | If the value of this macro is always zero, it need not be defined. */ | |
2933 | ||
e1565e65 | 2934 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 SC |
2935 | |
2936 | /* Define this macro to inhibit strength reduction of memory | |
2937 | addresses. (On some machines, such strength reduction seems to do | |
2938 | harm rather than good.) */ | |
2939 | ||
2940 | /* #define DONT_REDUCE_ADDR */ | |
2941 | ||
2942 | /* Define this macro if it is as good or better to call a constant | |
2943 | function address than to call an address kept in a register. | |
2944 | ||
2945 | Desirable on the 386 because a CALL with a constant address is | |
2946 | faster than one with a register address. */ | |
2947 | ||
2948 | #define NO_FUNCTION_CSE | |
2949 | ||
2950 | /* Define this macro if it is as good or better for a function to call | |
2951 | itself with an explicit address than to call an address kept in a | |
2952 | register. */ | |
2953 | ||
2954 | #define NO_RECURSIVE_FUNCTION_CSE | |
c98f8742 | 2955 | \f |
c572e5ba JVA |
2956 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2957 | return the mode to be used for the comparison. | |
2958 | ||
2959 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2960 | VOIDmode should be used in all other cases. |
c572e5ba | 2961 | |
16189740 | 2962 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2963 | possible, to allow for more combinations. */ |
c98f8742 | 2964 | |
d9a5f180 | 2965 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2966 | |
9cd10576 | 2967 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2968 | reversed. */ |
2969 | ||
2970 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2971 | ||
2972 | /* A C expression whose value is reversed condition code of the CODE for | |
2973 | comparison done in CC_MODE mode. */ | |
2974 | #define REVERSE_CONDITION(CODE, MODE) \ | |
2975 | ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \ | |
2976 | : reverse_condition_maybe_unordered (CODE)) | |
2977 | ||
c98f8742 JVA |
2978 | \f |
2979 | /* Control the assembler format that we output, to the extent | |
2980 | this does not vary between assemblers. */ | |
2981 | ||
2982 | /* How to refer to registers in assembler output. | |
892a2d68 | 2983 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 JVA |
2984 | |
2985 | /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" | |
2986 | For non floating point regs, the following are the HImode names. | |
2987 | ||
2988 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
9e06e321 | 2989 | instead of just "%st". PRINT_REG handles this with the "y" code. */ |
c98f8742 | 2990 | |
fce5a9f2 | 2991 | #undef HI_REGISTER_NAMES |
a7180f70 BS |
2992 | #define HI_REGISTER_NAMES \ |
2993 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
2994 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ | |
2995 | "flags","fpsr", "dirflag", "frame", \ | |
2996 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ | |
3f3f2124 JH |
2997 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \ |
2998 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2999 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 3000 | |
c98f8742 JVA |
3001 | #define REGISTER_NAMES HI_REGISTER_NAMES |
3002 | ||
3003 | /* Table of additional register names to use in user input. */ | |
3004 | ||
3005 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
3006 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
3007 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
3008 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
3009 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 3010 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
a7180f70 BS |
3011 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ |
3012 | { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \ | |
3013 | { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} } | |
c98f8742 JVA |
3014 | |
3015 | /* Note we are omitting these since currently I don't know how | |
3016 | to get gcc to use these, since they want the same but different | |
3017 | number as al, and ax. | |
3018 | */ | |
3019 | ||
c98f8742 | 3020 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 3021 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
3022 | |
3023 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 3024 | of regs 0 through 3. */ |
c98f8742 JVA |
3025 | |
3026 | #define QI_HIGH_REGISTER_NAMES \ | |
3027 | {"ah", "dh", "ch", "bh", } | |
3028 | ||
3029 | /* How to renumber registers for dbx and gdb. */ | |
3030 | ||
d9a5f180 GS |
3031 | #define DBX_REGISTER_NUMBER(N) \ |
3032 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 RH |
3033 | |
3034 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
0f7fa3d0 | 3035 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; |
83774849 | 3036 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; |
c98f8742 | 3037 | |
469ac993 JM |
3038 | /* Before the prologue, RA is at 0(%esp). */ |
3039 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 3040 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 3041 | |
e414ab29 | 3042 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
3043 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
3044 | ((COUNT) == 0 \ | |
3045 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
3046 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 3047 | |
892a2d68 | 3048 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 3049 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 3050 | |
a6ab3aad | 3051 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 3052 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 3053 | |
1020a5ab RH |
3054 | /* Describe how we implement __builtin_eh_return. */ |
3055 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
3056 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
3057 | ||
ad919812 | 3058 | |
e4c4ebeb RH |
3059 | /* Select a format to encode pointers in exception handling data. CODE |
3060 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
3061 | true if the symbol may be affected by dynamic relocations. | |
3062 | ||
3063 | ??? All x86 object file formats are capable of representing this. | |
3064 | After all, the relocation needed is the same as for the call insn. | |
3065 | Whether or not a particular assembler allows us to enter such, I | |
3066 | guess we'll have to see. */ | |
d9a5f180 | 3067 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
b932f770 | 3068 | (flag_pic \ |
d9a5f180 | 3069 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ |
e4c4ebeb RH |
3070 | : DW_EH_PE_absptr) |
3071 | ||
c98f8742 JVA |
3072 | /* This is how to output an insn to push a register on the stack. |
3073 | It need not be very fast code. */ | |
3074 | ||
d9a5f180 | 3075 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
3076 | do { \ |
3077 | if (TARGET_64BIT) \ | |
3078 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
3079 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
3080 | else \ | |
3081 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
3082 | } while (0) | |
c98f8742 JVA |
3083 | |
3084 | /* This is how to output an insn to pop a register from the stack. | |
3085 | It need not be very fast code. */ | |
3086 | ||
d9a5f180 | 3087 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
3088 | do { \ |
3089 | if (TARGET_64BIT) \ | |
3090 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
3091 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
3092 | else \ | |
3093 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
3094 | } while (0) | |
c98f8742 | 3095 | |
f88c65f7 | 3096 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
3097 | |
3098 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 3099 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 3100 | |
f88c65f7 | 3101 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 3102 | |
33f7f353 | 3103 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 3104 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 RH |
3105 | |
3106 | /* Under some conditions we need jump tables in the text section, because | |
3107 | the assembler cannot handle label differences between sections. */ | |
3108 | ||
3109 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
3110 | (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA) | |
c98f8742 | 3111 | |
fce5a9f2 | 3112 | /* A C statement that outputs an address constant appropriate to |
1865dbb5 JM |
3113 | for DWARF debugging. */ |
3114 | ||
d9a5f180 GS |
3115 | #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \ |
3116 | i386_dwarf_output_addr_const ((FILE), (X)) | |
1865dbb5 JM |
3117 | |
3118 | /* Either simplify a location expression, or return the original. */ | |
3119 | ||
3120 | #define ASM_SIMPLIFY_DWARF_ADDR(X) \ | |
d9a5f180 | 3121 | i386_simplify_dwarf_addr (X) |
cea3bd3e | 3122 | |
b9203463 RH |
3123 | /* Emit a dtp-relative reference to a TLS variable. */ |
3124 | ||
3125 | #ifdef HAVE_AS_TLS | |
3126 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
3127 | i386_output_dwarf_dtprel (FILE, SIZE, X) | |
3128 | #endif | |
3129 | ||
cea3bd3e RH |
3130 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
3131 | and switch back. For x86 we do this only to save a few bytes that | |
3132 | would otherwise be unused in the text section. */ | |
3133 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
3134 | asm (SECTION_OP "\n\t" \ | |
3135 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
3136 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 3137 | \f |
c98f8742 JVA |
3138 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
3139 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
3140 | Effect of various CODE letters is described in i386.c near |
3141 | print_operand function. */ | |
c98f8742 | 3142 | |
d9a5f180 | 3143 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
f996902d | 3144 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') |
c98f8742 | 3145 | |
74b42c8b RS |
3146 | /* Print the name of a register based on its machine mode and number. |
3147 | If CODE is 'w', pretend the mode is HImode. | |
3148 | If CODE is 'b', pretend the mode is QImode. | |
3149 | If CODE is 'k', pretend the mode is SImode. | |
ef6257cd | 3150 | If CODE is 'q', pretend the mode is DImode. |
74b42c8b | 3151 | If CODE is 'h', pretend the reg is the `high' byte register. |
ef6257cd | 3152 | If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ |
74b42c8b | 3153 | |
e075ae69 | 3154 | #define PRINT_REG(X, CODE, FILE) \ |
d9a5f180 | 3155 | print_reg ((X), (CODE), (FILE)) |
74b42c8b | 3156 | |
c98f8742 | 3157 | #define PRINT_OPERAND(FILE, X, CODE) \ |
d9a5f180 | 3158 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
3159 | |
3160 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 3161 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 3162 | |
f996902d RH |
3163 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
3164 | do { \ | |
3165 | if (! output_addr_const_extra (FILE, (X))) \ | |
3166 | goto FAIL; \ | |
3167 | } while (0); | |
3168 | ||
aa3e8d2a JVA |
3169 | /* Print the name of a register for based on its machine mode and number. |
3170 | This macro is used to print debugging output. | |
3171 | This macro is different from PRINT_REG in that it may be used in | |
3172 | programs that are not linked with aux-output.o. */ | |
3173 | ||
e075ae69 | 3174 | #define DEBUG_PRINT_REG(X, CODE, FILE) \ |
69ddee61 KG |
3175 | do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ |
3176 | static const char * const qi_name[] = QI_REGISTER_NAMES; \ | |
d9a5f180 | 3177 | fprintf ((FILE), "%d ", REGNO (X)); \ |
e075ae69 | 3178 | if (REGNO (X) == FLAGS_REG) \ |
d9a5f180 | 3179 | { fputs ("flags", (FILE)); break; } \ |
7c7ef435 | 3180 | if (REGNO (X) == DIRFLAG_REG) \ |
d9a5f180 | 3181 | { fputs ("dirflag", (FILE)); break; } \ |
e075ae69 | 3182 | if (REGNO (X) == FPSR_REG) \ |
d9a5f180 | 3183 | { fputs ("fpsr", (FILE)); break; } \ |
aa3e8d2a | 3184 | if (REGNO (X) == ARG_POINTER_REGNUM) \ |
d9a5f180 | 3185 | { fputs ("argp", (FILE)); break; } \ |
564d80f4 | 3186 | if (REGNO (X) == FRAME_POINTER_REGNUM) \ |
d9a5f180 | 3187 | { fputs ("frame", (FILE)); break; } \ |
aa3e8d2a | 3188 | if (STACK_TOP_P (X)) \ |
d9a5f180 | 3189 | { fputs ("st(0)", (FILE)); break; } \ |
b0ceea8c | 3190 | if (FP_REG_P (X)) \ |
d9a5f180 | 3191 | { fputs (hi_name[REGNO(X)], (FILE)); break; } \ |
3f3f2124 JH |
3192 | if (REX_INT_REG_P (X)) \ |
3193 | { \ | |
3194 | switch (GET_MODE_SIZE (GET_MODE (X))) \ | |
3195 | { \ | |
3196 | default: \ | |
3197 | case 8: \ | |
d9a5f180 | 3198 | fprintf ((FILE), "r%i", REGNO (X) \ |
3f3f2124 JH |
3199 | - FIRST_REX_INT_REG + 8); \ |
3200 | break; \ | |
3201 | case 4: \ | |
d9a5f180 | 3202 | fprintf ((FILE), "r%id", REGNO (X) \ |
3f3f2124 JH |
3203 | - FIRST_REX_INT_REG + 8); \ |
3204 | break; \ | |
3205 | case 2: \ | |
d9a5f180 | 3206 | fprintf ((FILE), "r%iw", REGNO (X) \ |
3f3f2124 JH |
3207 | - FIRST_REX_INT_REG + 8); \ |
3208 | break; \ | |
3209 | case 1: \ | |
d9a5f180 | 3210 | fprintf ((FILE), "r%ib", REGNO (X) \ |
3f3f2124 JH |
3211 | - FIRST_REX_INT_REG + 8); \ |
3212 | break; \ | |
3213 | } \ | |
3214 | break; \ | |
3215 | } \ | |
aa3e8d2a JVA |
3216 | switch (GET_MODE_SIZE (GET_MODE (X))) \ |
3217 | { \ | |
3f3f2124 | 3218 | case 8: \ |
d9a5f180 GS |
3219 | fputs ("r", (FILE)); \ |
3220 | fputs (hi_name[REGNO (X)], (FILE)); \ | |
3f3f2124 | 3221 | break; \ |
b0ceea8c | 3222 | default: \ |
d9a5f180 | 3223 | fputs ("e", (FILE)); \ |
aa3e8d2a | 3224 | case 2: \ |
d9a5f180 | 3225 | fputs (hi_name[REGNO (X)], (FILE)); \ |
aa3e8d2a JVA |
3226 | break; \ |
3227 | case 1: \ | |
d9a5f180 | 3228 | fputs (qi_name[REGNO (X)], (FILE)); \ |
aa3e8d2a JVA |
3229 | break; \ |
3230 | } \ | |
3231 | } while (0) | |
3232 | ||
c98f8742 JVA |
3233 | /* a letter which is not needed by the normal asm syntax, which |
3234 | we can use for operand syntax in the extended asm */ | |
3235 | ||
3236 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 3237 | #define RET return "" |
d9a5f180 | 3238 | #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) |
d4ba09c0 | 3239 | \f |
e075ae69 RH |
3240 | /* Define the codes that are matched by predicates in i386.c. */ |
3241 | ||
3242 | #define PREDICATE_CODES \ | |
7dd4b4a3 JH |
3243 | {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \ |
3244 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3245 | {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \ | |
3246 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3247 | {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \ | |
3248 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3249 | {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \ | |
3250 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3251 | {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \ | |
3252 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3253 | {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \ | |
3254 | SYMBOL_REF, LABEL_REF, CONST}}, \ | |
3255 | {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \ | |
3256 | SYMBOL_REF, LABEL_REF}}, \ | |
371bc54b | 3257 | {"shiftdi_operand", {SUBREG, REG, MEM}}, \ |
8bad7136 | 3258 | {"const_int_1_operand", {CONST_INT}}, \ |
794a292d | 3259 | {"const_int_1_31_operand", {CONST_INT}}, \ |
e075ae69 | 3260 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ |
2247f6ed JH |
3261 | {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
3262 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
e075ae69 | 3263 | {"pic_symbolic_operand", {CONST}}, \ |
e1ff012c | 3264 | {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \ |
4977bab6 | 3265 | {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \ |
eaf19aba | 3266 | {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \ |
e075ae69 RH |
3267 | {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ |
3268 | {"const1_operand", {CONST_INT}}, \ | |
3269 | {"const248_operand", {CONST_INT}}, \ | |
3270 | {"incdec_operand", {CONST_INT}}, \ | |
915119a5 | 3271 | {"mmx_reg_operand", {REG}}, \ |
e075ae69 | 3272 | {"reg_no_sp_operand", {SUBREG, REG}}, \ |
2c5a510c RH |
3273 | {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ |
3274 | SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ | |
3275 | {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ | |
7ec70495 | 3276 | {"index_register_operand", {SUBREG, REG}}, \ |
4977bab6 | 3277 | {"flags_reg_operand", {REG}}, \ |
e075ae69 RH |
3278 | {"q_regs_operand", {SUBREG, REG}}, \ |
3279 | {"non_q_regs_operand", {SUBREG, REG}}, \ | |
9e7adcb3 JH |
3280 | {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \ |
3281 | ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \ | |
3282 | GE, UNGE, LTGT, UNEQ}}, \ | |
bf71a4f8 JH |
3283 | {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \ |
3284 | ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \ | |
3285 | }}, \ | |
9076b9c1 | 3286 | {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \ |
9e7adcb3 JH |
3287 | GTU, UNORDERED, ORDERED, UNLE, UNLT, \ |
3288 | UNGE, UNGT, LTGT, UNEQ }}, \ | |
e075ae69 RH |
3289 | {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ |
3290 | {"ext_register_operand", {SUBREG, REG}}, \ | |
3291 | {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ | |
3292 | {"mult_operator", {MULT}}, \ | |
3293 | {"div_operator", {DIV}}, \ | |
3294 | {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ | |
3295 | UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ | |
3296 | UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ | |
3297 | LSHIFTRT, ROTATERT}}, \ | |
e9e80858 | 3298 | {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ |
e075ae69 RH |
3299 | {"memory_displacement_operand", {MEM}}, \ |
3300 | {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
6343a50e | 3301 | LABEL_REF, SUBREG, REG, MEM, AND}}, \ |
f996902d RH |
3302 | {"long_memory_operand", {MEM}}, \ |
3303 | {"tls_symbolic_operand", {SYMBOL_REF}}, \ | |
3304 | {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \ | |
3305 | {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \ | |
3306 | {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \ | |
c3c637e3 GS |
3307 | {"local_exec_symbolic_operand", {SYMBOL_REF}}, \ |
3308 | {"any_fp_register_operand", {REG}}, \ | |
3309 | {"register_and_not_any_fp_reg_operand", {REG}}, \ | |
3310 | {"fp_register_operand", {REG}}, \ | |
3311 | {"register_and_not_fp_reg_operand", {REG}}, \ | |
4977bab6 | 3312 | {"zero_extended_scalar_load_operand", {MEM}}, \ |
c76aab11 RH |
3313 | |
3314 | /* A list of predicates that do special things with modes, and so | |
3315 | should not elicit warnings for VOIDmode match_operand. */ | |
3316 | ||
3317 | #define SPECIAL_MODE_PREDICATES \ | |
3318 | "ext_register_operand", | |
c98f8742 | 3319 | \f |
5bf0ebab RH |
3320 | /* Which processor to schedule for. The cpu attribute defines a list that |
3321 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
3322 | ||
3323 | enum processor_type | |
3324 | { | |
3325 | PROCESSOR_I386, /* 80386 */ | |
3326 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
3327 | PROCESSOR_PENTIUM, | |
3328 | PROCESSOR_PENTIUMPRO, | |
3329 | PROCESSOR_K6, | |
3330 | PROCESSOR_ATHLON, | |
3331 | PROCESSOR_PENTIUM4, | |
4977bab6 | 3332 | PROCESSOR_K8, |
5bf0ebab RH |
3333 | PROCESSOR_max |
3334 | }; | |
3335 | ||
3336 | extern enum processor_type ix86_cpu; | |
3337 | extern const char *ix86_cpu_string; | |
3338 | ||
3339 | extern enum processor_type ix86_arch; | |
3340 | extern const char *ix86_arch_string; | |
3341 | ||
3342 | enum fpmath_unit | |
3343 | { | |
3344 | FPMATH_387 = 1, | |
3345 | FPMATH_SSE = 2 | |
3346 | }; | |
3347 | ||
3348 | extern enum fpmath_unit ix86_fpmath; | |
3349 | extern const char *ix86_fpmath_string; | |
3350 | ||
f996902d RH |
3351 | enum tls_dialect |
3352 | { | |
3353 | TLS_DIALECT_GNU, | |
3354 | TLS_DIALECT_SUN | |
3355 | }; | |
3356 | ||
3357 | extern enum tls_dialect ix86_tls_dialect; | |
3358 | extern const char *ix86_tls_dialect_string; | |
3359 | ||
6189a572 | 3360 | enum cmodel { |
5bf0ebab RH |
3361 | CM_32, /* The traditional 32-bit ABI. */ |
3362 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
3363 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
3364 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
3365 | CM_LARGE, /* No assumptions. */ | |
3366 | CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */ | |
6189a572 JH |
3367 | }; |
3368 | ||
5bf0ebab RH |
3369 | extern enum cmodel ix86_cmodel; |
3370 | extern const char *ix86_cmodel_string; | |
3371 | ||
8362f420 JH |
3372 | /* Size of the RED_ZONE area. */ |
3373 | #define RED_ZONE_SIZE 128 | |
3374 | /* Reserved area of the red zone for temporaries. */ | |
3375 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
3376 | |
3377 | enum asm_dialect { | |
3378 | ASM_ATT, | |
3379 | ASM_INTEL | |
3380 | }; | |
5bf0ebab | 3381 | |
c93e80a5 | 3382 | extern const char *ix86_asm_string; |
80f33d06 | 3383 | extern enum asm_dialect ix86_asm_dialect; |
5bf0ebab RH |
3384 | |
3385 | extern int ix86_regparm; | |
fce5a9f2 | 3386 | extern const char *ix86_regparm_string; |
5bf0ebab RH |
3387 | |
3388 | extern int ix86_preferred_stack_boundary; | |
3389 | extern const char *ix86_preferred_stack_boundary_string; | |
3390 | ||
3391 | extern int ix86_branch_cost; | |
3392 | extern const char *ix86_branch_cost_string; | |
3393 | ||
3394 | extern const char *ix86_debug_arg_string; | |
3395 | extern const char *ix86_debug_addr_string; | |
3396 | ||
3397 | /* Obsoleted by -f options. Remove before 3.2 ships. */ | |
3398 | extern const char *ix86_align_loops_string; | |
3399 | extern const char *ix86_align_jumps_string; | |
3400 | extern const char *ix86_align_funcs_string; | |
3401 | ||
3402 | /* Smallest class containing REGNO. */ | |
3403 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
3404 | ||
d9a5f180 GS |
3405 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
3406 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
22fb740d JH |
3407 | \f |
3408 | /* To properly truncate FP values into integers, we need to set i387 control | |
3409 | word. We can't emit proper mode switching code before reload, as spills | |
3410 | generated by reload may truncate values incorrectly, but we still can avoid | |
3411 | redundant computation of new control word by the mode switching pass. | |
3412 | The fldcw instructions are still emitted redundantly, but this is probably | |
3413 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 3414 | the sequence. |
22fb740d JH |
3415 | |
3416 | The machinery is to emit simple truncation instructions and split them | |
3417 | before reload to instructions having USEs of two memory locations that | |
3418 | are filled by this code to old and new control word. | |
fce5a9f2 | 3419 | |
22fb740d JH |
3420 | Post-reload pass may be later used to eliminate the redundant fildcw if |
3421 | needed. */ | |
3422 | ||
3423 | enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY}; | |
3424 | ||
3425 | /* Define this macro if the port needs extra instructions inserted | |
3426 | for mode switching in an optimizing compilation. */ | |
3427 | ||
3428 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1 | |
3429 | ||
3430 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
3431 | initializer for an array of integers. Each initializer element N | |
3432 | refers to an entity that needs mode switching, and specifies the | |
3433 | number of different modes that might need to be set for this | |
3434 | entity. The position of the initializer in the initializer - | |
3435 | starting counting at zero - determines the integer that is used to | |
3436 | refer to the mode-switched entity in question. */ | |
3437 | ||
3438 | #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY } | |
3439 | ||
3440 | /* ENTITY is an integer specifying a mode-switched entity. If | |
3441 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
3442 | return an integer value not larger than the corresponding element | |
3443 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
3444 | must be switched into prior to the execution of INSN. */ | |
3445 | ||
3446 | #define MODE_NEEDED(ENTITY, I) \ | |
3447 | (GET_CODE (I) == CALL_INSN \ | |
3448 | || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \ | |
3449 | || GET_CODE (PATTERN (I)) == ASM_INPUT))\ | |
3450 | ? FP_CW_UNINITIALIZED \ | |
3451 | : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \ | |
3452 | ? FP_CW_ANY \ | |
3453 | : FP_CW_STORED) | |
3454 | ||
3455 | /* This macro specifies the order in which modes for ENTITY are | |
3456 | processed. 0 is the highest priority. */ | |
3457 | ||
d9a5f180 | 3458 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
3459 | |
3460 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
3461 | is the set of hard registers live at the point where the insn(s) | |
3462 | are to be inserted. */ | |
3463 | ||
3464 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
d9a5f180 | 3465 | ((MODE) == FP_CW_STORED \ |
22fb740d JH |
3466 | ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \ |
3467 | assign_386_stack_local (HImode, 2)), 0\ | |
3468 | : 0) | |
0f0138b6 JH |
3469 | \f |
3470 | /* Avoid renaming of stack registers, as doing so in combination with | |
3471 | scheduling just increases amount of live registers at time and in | |
3472 | the turn amount of fxch instructions needed. | |
3473 | ||
3474 | ??? Maybe Pentium chips benefits from renaming, someone can try... */ | |
3475 | ||
d9a5f180 GS |
3476 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
3477 | ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG) | |
22fb740d | 3478 | |
3b3c6a3f | 3479 | \f |
2a500b9e | 3480 | #define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X) |
249e6b63 CH |
3481 | |
3482 | #define DLL_IMPORT_EXPORT_PREFIX '@' | |
3483 | ||
c98f8742 JVA |
3484 | /* |
3485 | Local variables: | |
3486 | version-control: t | |
3487 | End: | |
3488 | */ |