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8b109b37 RK |
1 | /* Definitions of target machine for GNU compiler for Intel X86 |
2 | (386, 486, Pentium). | |
c6aded7c | 3 | Copyright (C) 1988, 92, 94-97, 1998 Free Software Foundation, Inc. |
c98f8742 JVA |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
d4ba09c0 | 20 | Boston, MA 02111-1307, USA. */ |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
33 | assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE, | |
34 | PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, | |
35 | PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ | |
36 | ||
37 | /* Names to predefine in the preprocessor for this target machine. */ | |
38 | ||
39 | #define I386 1 | |
40 | ||
95393dfd CH |
41 | /* Stubs for half-pic support if not OSF/1 reference platform. */ |
42 | ||
43 | #ifndef HALF_PIC_P | |
44 | #define HALF_PIC_P() 0 | |
45 | #define HALF_PIC_NUMBER_PTRS 0 | |
46 | #define HALF_PIC_NUMBER_REFS 0 | |
47 | #define HALF_PIC_ENCODE(DECL) | |
48 | #define HALF_PIC_DECLARE(NAME) | |
49 | #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") | |
50 | #define HALF_PIC_ADDRESS_P(X) 0 | |
51 | #define HALF_PIC_PTR(X) X | |
52 | #define HALF_PIC_FINISH(STREAM) | |
53 | #endif | |
54 | ||
d4ba09c0 SC |
55 | /* Define the specific costs for a given cpu */ |
56 | ||
57 | struct processor_costs { | |
58 | int add; /* cost of an add instruction */ | |
59 | int lea; /* cost of a lea instruction */ | |
60 | int shift_var; /* variable shift costs */ | |
61 | int shift_const; /* constant shift costs */ | |
62 | int mult_init; /* cost of starting a multiply */ | |
63 | int mult_bit; /* cost of multiply per each bit set */ | |
64 | int divide; /* cost of a divide/mod */ | |
65 | }; | |
66 | ||
67 | extern struct processor_costs *ix86_cost; | |
68 | ||
c98f8742 JVA |
69 | /* Run-time compilation parameters selecting different hardware subsets. */ |
70 | ||
71 | extern int target_flags; | |
72 | ||
73 | /* Macros used in the machine description to test the flags. */ | |
74 | ||
ddd5a7c1 | 75 | /* configure can arrange to make this 2, to force a 486. */ |
35b528be RS |
76 | #ifndef TARGET_CPU_DEFAULT |
77 | #define TARGET_CPU_DEFAULT 0 | |
78 | #endif | |
79 | ||
3b3c6a3f MM |
80 | /* Masks for the -m switches */ |
81 | #define MASK_80387 000000000001 /* Hardware floating point */ | |
33c1d53a SC |
82 | #define MASK_NOTUSED1 000000000002 /* bit not currently used */ |
83 | #define MASK_NOTUSED2 000000000004 /* bit not currently used */ | |
3b3c6a3f | 84 | #define MASK_RTD 000000000010 /* Use ret that pops args */ |
b08de47e | 85 | #define MASK_ALIGN_DOUBLE 000000000020 /* align doubles to 2 word boundary */ |
3b3c6a3f MM |
86 | #define MASK_SVR3_SHLIB 000000000040 /* Uninit locals into bss */ |
87 | #define MASK_IEEE_FP 000000000100 /* IEEE fp comparisons */ | |
88 | #define MASK_FLOAT_RETURNS 000000000200 /* Return float in st(0) */ | |
89 | #define MASK_NO_FANCY_MATH_387 000000000400 /* Disable sin, cos, sqrt */ | |
2f2fa5b1 | 90 | #define MASK_OMIT_LEAF_FRAME_POINTER 0x00000800 /* omit leaf frame pointers */ |
3b3c6a3f MM |
91 | /* Temporary codegen switches */ |
92 | #define MASK_DEBUG_ADDR 000001000000 /* Debug GO_IF_LEGITIMATE_ADDRESS */ | |
93 | #define MASK_NO_WIDE_MULTIPLY 000002000000 /* Disable 32x32->64 multiplies */ | |
94 | #define MASK_NO_MOVE 000004000000 /* Don't generate mem->mem */ | |
d4ba09c0 SC |
95 | #define MASK_NO_PSEUDO 000010000000 /* Move op's args -> pseudos */ |
96 | #define MASK_DEBUG_ARG 000020000000 /* Debug function_arg */ | |
f6f58ba3 | 97 | #define MASK_SCHEDULE_PROLOGUE 000040000000 /* Emit prologue as rtl */ |
8c9be447 | 98 | #define MASK_STACK_PROBE 000100000000 /* Enable stack probing */ |
3b3c6a3f MM |
99 | |
100 | /* Use the floating point instructions */ | |
101 | #define TARGET_80387 (target_flags & MASK_80387) | |
102 | ||
c98f8742 JVA |
103 | /* Compile using ret insn that pops args. |
104 | This will not work unless you use prototypes at least | |
105 | for all functions that can take varying numbers of args. */ | |
3b3c6a3f MM |
106 | #define TARGET_RTD (target_flags & MASK_RTD) |
107 | ||
b08de47e MM |
108 | /* Align doubles to a two word boundary. This breaks compatibility with |
109 | the published ABI's for structures containing doubles, but produces | |
110 | faster code on the pentium. */ | |
111 | #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) | |
c98f8742 | 112 | |
d7cd15e9 RS |
113 | /* Put uninitialized locals into bss, not data. |
114 | Meaningful only on svr3. */ | |
3b3c6a3f | 115 | #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) |
d7cd15e9 | 116 | |
c572e5ba JVA |
117 | /* Use IEEE floating point comparisons. These handle correctly the cases |
118 | where the result of a comparison is unordered. Normally SIGFPE is | |
119 | generated in such cases, in which case this isn't needed. */ | |
3b3c6a3f | 120 | #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) |
c572e5ba | 121 | |
8c2bf92a JVA |
122 | /* Functions that return a floating point value may return that value |
123 | in the 387 FPU or in 386 integer registers. If set, this flag causes | |
124 | the 387 to be used, which is compatible with most calling conventions. */ | |
3b3c6a3f | 125 | #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) |
8c2bf92a | 126 | |
099800e3 RK |
127 | /* Disable generation of FP sin, cos and sqrt operations for 387. |
128 | This is because FreeBSD lacks these in the math-emulator-code */ | |
3b3c6a3f MM |
129 | #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) |
130 | ||
2f2fa5b1 SC |
131 | /* Don't create frame pointers for leaf functions */ |
132 | #define TARGET_OMIT_LEAF_FRAME_POINTER (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) | |
133 | ||
3b3c6a3f MM |
134 | /* Temporary switches for tuning code generation */ |
135 | ||
136 | /* Disable 32x32->64 bit multiplies that are used for long long multiplies | |
137 | and division by constants, but sometimes cause reload problems. */ | |
138 | #define TARGET_NO_WIDE_MULTIPLY (target_flags & MASK_NO_WIDE_MULTIPLY) | |
139 | #define TARGET_WIDE_MULTIPLY (!TARGET_NO_WIDE_MULTIPLY) | |
140 | ||
f6f58ba3 SC |
141 | /* Emit/Don't emit prologue as rtl */ |
142 | #define TARGET_SCHEDULE_PROLOGUE (target_flags & MASK_SCHEDULE_PROLOGUE) | |
143 | ||
3b3c6a3f MM |
144 | /* Debug GO_IF_LEGITIMATE_ADDRESS */ |
145 | #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR) | |
146 | ||
b08de47e MM |
147 | /* Debug FUNCTION_ARG macros */ |
148 | #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG) | |
149 | ||
3b3c6a3f MM |
150 | /* Hack macros for tuning code generation */ |
151 | #define TARGET_MOVE ((target_flags & MASK_NO_MOVE) == 0) /* Don't generate memory->memory */ | |
d4ba09c0 SC |
152 | #define TARGET_PSEUDO ((target_flags & MASK_NO_PSEUDO) == 0) /* Move op's args into pseudos */ |
153 | ||
f7746310 SC |
154 | #define TARGET_386 (ix86_cpu == PROCESSOR_I386) |
155 | #define TARGET_486 (ix86_cpu == PROCESSOR_I486) | |
156 | #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) | |
3a0433fd | 157 | #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) |
f7746310 | 158 | #define TARGET_USE_LEAVE (ix86_cpu == PROCESSOR_I386) |
241e1a89 | 159 | #define TARGET_PUSH_MEMORY (ix86_cpu == PROCESSOR_I386) |
5bc7cd8e SC |
160 | #define TARGET_ZERO_EXTEND_WITH_AND (ix86_cpu != PROCESSOR_I386 \ |
161 | && ix86_cpu != PROCESSOR_PENTIUMPRO) | |
241e1a89 | 162 | #define TARGET_DOUBLE_WITH_ADD (ix86_cpu != PROCESSOR_I386) |
f7746310 SC |
163 | #define TARGET_USE_BIT_TEST (ix86_cpu == PROCESSOR_I386) |
164 | #define TARGET_UNROLL_STRLEN (ix86_cpu != PROCESSOR_I386) | |
3c67a76b SC |
165 | #define TARGET_USE_Q_REG (ix86_cpu == PROCESSOR_PENTIUM \ |
166 | || ix86_cpu == PROCESSOR_PENTIUMPRO) | |
f7746310 | 167 | #define TARGET_USE_ANY_REG (ix86_cpu == PROCESSOR_I486) |
bcd86433 | 168 | #define TARGET_CMOVE (ix86_arch == PROCESSOR_PENTIUMPRO) |
2f2fa5b1 | 169 | #define TARGET_DEEP_BRANCH_PREDICTION (ix86_cpu == PROCESSOR_PENTIUMPRO) |
8c9be447 | 170 | #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) |
3b3c6a3f MM |
171 | |
172 | #define TARGET_SWITCHES \ | |
173 | { { "80387", MASK_80387 }, \ | |
174 | { "no-80387", -MASK_80387 }, \ | |
175 | { "hard-float", MASK_80387 }, \ | |
176 | { "soft-float", -MASK_80387 }, \ | |
177 | { "no-soft-float", MASK_80387 }, \ | |
241e1a89 SC |
178 | { "386", 0 }, \ |
179 | { "no-386", 0 }, \ | |
180 | { "486", 0 }, \ | |
181 | { "no-486", 0 }, \ | |
182 | { "pentium", 0 }, \ | |
183 | { "pentiumpro", 0 }, \ | |
3b3c6a3f MM |
184 | { "rtd", MASK_RTD }, \ |
185 | { "no-rtd", -MASK_RTD }, \ | |
b08de47e MM |
186 | { "align-double", MASK_ALIGN_DOUBLE }, \ |
187 | { "no-align-double", -MASK_ALIGN_DOUBLE }, \ | |
3b3c6a3f MM |
188 | { "svr3-shlib", MASK_SVR3_SHLIB }, \ |
189 | { "no-svr3-shlib", -MASK_SVR3_SHLIB }, \ | |
190 | { "ieee-fp", MASK_IEEE_FP }, \ | |
191 | { "no-ieee-fp", -MASK_IEEE_FP }, \ | |
192 | { "fp-ret-in-387", MASK_FLOAT_RETURNS }, \ | |
193 | { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS }, \ | |
194 | { "no-fancy-math-387", MASK_NO_FANCY_MATH_387 }, \ | |
195 | { "fancy-math-387", -MASK_NO_FANCY_MATH_387 }, \ | |
2f2fa5b1 SC |
196 | { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER }, \ |
197 | { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER }, \ | |
3b3c6a3f MM |
198 | { "no-wide-multiply", MASK_NO_WIDE_MULTIPLY }, \ |
199 | { "wide-multiply", -MASK_NO_WIDE_MULTIPLY }, \ | |
f6f58ba3 SC |
200 | { "schedule-prologue", MASK_SCHEDULE_PROLOGUE }, \ |
201 | { "no-schedule-prologue", -MASK_SCHEDULE_PROLOGUE }, \ | |
3b3c6a3f MM |
202 | { "debug-addr", MASK_DEBUG_ADDR }, \ |
203 | { "no-debug-addr", -MASK_DEBUG_ADDR }, \ | |
204 | { "move", -MASK_NO_MOVE }, \ | |
205 | { "no-move", MASK_NO_MOVE }, \ | |
b08de47e MM |
206 | { "debug-arg", MASK_DEBUG_ARG }, \ |
207 | { "no-debug-arg", -MASK_DEBUG_ARG }, \ | |
8c9be447 RK |
208 | { "stack-arg-probe", MASK_STACK_PROBE }, \ |
209 | { "no-stack-arg-probe", -MASK_STACK_PROBE }, \ | |
956d6950 JL |
210 | { "windows", 0 }, \ |
211 | { "dll", 0 }, \ | |
3b3c6a3f | 212 | SUBTARGET_SWITCHES \ |
f6f58ba3 | 213 | { "", MASK_SCHEDULE_PROLOGUE | TARGET_DEFAULT}} |
241e1a89 | 214 | |
d4ba09c0 SC |
215 | /* Which processor to schedule for. The cpu attribute defines a list that |
216 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
217 | ||
241e1a89 SC |
218 | enum processor_type |
219 | {PROCESSOR_I386, /* 80386 */ | |
220 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
221 | PROCESSOR_PENTIUM, | |
222 | PROCESSOR_PENTIUMPRO}; | |
223 | ||
224 | #define PROCESSOR_I386_STRING "i386" | |
225 | #define PROCESSOR_I486_STRING "i486" | |
226 | #define PROCESSOR_I586_STRING "i586" | |
227 | #define PROCESSOR_PENTIUM_STRING "pentium" | |
228 | #define PROCESSOR_I686_STRING "i686" | |
229 | #define PROCESSOR_PENTIUMPRO_STRING "pentiumpro" | |
230 | ||
231 | extern enum processor_type ix86_cpu; | |
232 | ||
bcd86433 | 233 | extern int ix86_arch; |
241e1a89 SC |
234 | |
235 | /* Define the default processor. This is overridden by other tm.h files. */ | |
236 | #define PROCESSOR_DEFAULT \ | |
237 | ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_I486) \ | |
238 | ? PROCESSOR_I486 \ | |
239 | : ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_PENTIUM) \ | |
240 | ? PROCESSOR_PENTIUM \ | |
241 | : ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_PENTIUMPRO) \ | |
242 | ? PROCESSOR_PENTIUMPRO \ | |
243 | : PROCESSOR_I386 | |
244 | #define PROCESSOR_DEFAULT_STRING \ | |
245 | ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_I486) \ | |
246 | ? PROCESSOR_I486_STRING \ | |
247 | : ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_PENTIUM) \ | |
248 | ? PROCESSOR_PENTIUM_STRING \ | |
249 | : ((enum processor_type) TARGET_CPU_DEFAULT == PROCESSOR_PENTIUMPRO) \ | |
250 | ? PROCESSOR_PENTIUMPRO_STRING \ | |
251 | : PROCESSOR_I386_STRING | |
95393dfd | 252 | |
f5316dfe MM |
253 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
254 | command options that have values. Its definition is an | |
255 | initializer with a subgrouping for each command option. | |
256 | ||
257 | Each subgrouping contains a string constant, that defines the | |
258 | fixed part of the option name, and the address of a variable. The | |
259 | variable, type `char *', is set to the variable part of the given | |
260 | option if the fixed part matches. The actual option name is made | |
261 | by appending `-m' to the specified name. */ | |
262 | #define TARGET_OPTIONS \ | |
241e1a89 | 263 | { { "cpu=", &ix86_cpu_string}, \ |
bcd86433 | 264 | { "arch=", &ix86_arch_string}, \ |
241e1a89 | 265 | { "reg-alloc=", &i386_reg_alloc_order }, \ |
b08de47e MM |
266 | { "regparm=", &i386_regparm_string }, \ |
267 | { "align-loops=", &i386_align_loops_string }, \ | |
268 | { "align-jumps=", &i386_align_jumps_string }, \ | |
269 | { "align-functions=", &i386_align_funcs_string }, \ | |
e2a606cb | 270 | { "branch-cost=", &i386_branch_cost_string }, \ |
b08de47e MM |
271 | SUBTARGET_OPTIONS \ |
272 | } | |
f5316dfe MM |
273 | |
274 | /* Sometimes certain combinations of command options do not make | |
275 | sense on a particular target machine. You can define a macro | |
276 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
277 | defined, is executed once just after all the command options have | |
278 | been parsed. | |
279 | ||
280 | Don't use this macro to turn on various extra optimizations for | |
281 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
282 | ||
283 | #define OVERRIDE_OPTIONS override_options () | |
284 | ||
285 | /* These are meant to be redefined in the host dependent files */ | |
95393dfd | 286 | #define SUBTARGET_SWITCHES |
f5316dfe | 287 | #define SUBTARGET_OPTIONS |
95393dfd | 288 | |
d4ba09c0 | 289 | /* Define this to change the optimizations performed by default. */ |
c6aded7c | 290 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) |
d4ba09c0 | 291 | |
241e1a89 SC |
292 | /* Specs for the compiler proper */ |
293 | ||
628714d8 RK |
294 | #ifndef CC1_CPU_SPEC |
295 | #define CC1_CPU_SPEC "\ | |
241e1a89 | 296 | %{!mcpu*: \ |
2f2fa5b1 SC |
297 | %{m386:-mcpu=i386 -march=i386} \ |
298 | %{mno-486:-mcpu=i386 -march=i386} \ | |
299 | %{m486:-mcpu=i486 -march=i486} \ | |
300 | %{mno-386:-mcpu=i486 -march=i486} \ | |
301 | %{mno-pentium:-mcpu=i486 -march=i486} \ | |
241e1a89 | 302 | %{mpentium:-mcpu=pentium} \ |
2f2fa5b1 | 303 | %{mno-pentiumpro:-mcpu=pentium} \ |
241e1a89 SC |
304 | %{mpentiumpro:-mcpu=pentiumpro}}" |
305 | #endif | |
c98f8742 | 306 | \f |
bcd86433 | 307 | #ifndef CPP_CPU_SPEC |
33c1d53a | 308 | #ifdef __STDC__ |
d5c65c96 | 309 | #if TARGET_CPU_DEFAULT == 1 |
33c1d53a | 310 | #define CPP_CPU_DEFAULT "-Di486" |
da594c94 JL |
311 | #else |
312 | #if TARGET_CPU_DEFAULT == 2 | |
33c1d53a | 313 | #define CPP_CPU_DEFAULT "-Di586" |
da594c94 JL |
314 | #else |
315 | #if TARGET_CPU_DEFAULT == 3 | |
33c1d53a | 316 | #define CPP_CPU_DEFAULT "-Di686" |
d5c65c96 SC |
317 | #else |
318 | #define CPP_CPU_DEFAULT "" | |
da594c94 JL |
319 | #endif |
320 | #endif | |
33c1d53a SC |
321 | #endif /* TARGET_CPU_DEFAULT */ |
322 | ||
323 | #define CPP_CPU_SPEC "\ | |
324 | -Di386 " CPP_CPU_DEFAULT " -Asystem(unix) -Acpu(i386) -Amachine(i386) \ | |
325 | %{mcpu=i486:-Di486} %{m486:-Di486} \ | |
326 | %{mpentium:-Dpentium -Di586} %{mcpu=pentium:-Dpentium -Di586} \ | |
327 | %{mpentiumpro:-Dpentiumpro -Di686} %{mcpu=pentiumpro:-Dpentiumpro -Di686}" | |
328 | ||
329 | #else | |
bcd86433 SC |
330 | #define CPP_CPU_SPEC "\ |
331 | -Di386 -Asystem(unix) -Acpu(i386) -Amachine(i386) \ | |
332 | %{mcpu=i486:-Di486} %{m486:-Di486} \ | |
333 | %{mpentium:-Dpentium -Di586} %{mcpu=pentium:-Dpentium -Di586} \ | |
334 | %{mpentiumpro:-Dpentiumpro -Di686} %{mcpu=pentiumpro:-Dpentiumpro -Di686}" | |
33c1d53a SC |
335 | #endif /* __STDC__ */ |
336 | #endif /* CPP_CPU_SPEC */ | |
bcd86433 | 337 | |
628714d8 RK |
338 | #ifndef CC1_SPEC |
339 | #define CC1_SPEC "%(cc1_spec) " | |
340 | #endif | |
341 | ||
342 | /* This macro defines names of additional specifications to put in the | |
343 | specs that can be used in various specifications like CC1_SPEC. Its | |
344 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
345 | |
346 | Each subgrouping contains a string constant, that defines the | |
347 | specification name, and a string constant that used by the GNU CC driver | |
348 | program. | |
349 | ||
350 | Do not define this macro if it does not need to do anything. */ | |
351 | ||
352 | #ifndef SUBTARGET_EXTRA_SPECS | |
353 | #define SUBTARGET_EXTRA_SPECS | |
354 | #endif | |
355 | ||
356 | #define EXTRA_SPECS \ | |
357 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
628714d8 | 358 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
359 | SUBTARGET_EXTRA_SPECS |
360 | \f | |
c98f8742 JVA |
361 | /* target machine storage layout */ |
362 | ||
0038aea6 JVA |
363 | /* Define for XFmode extended real floating point support. |
364 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
365 | #define LONG_DOUBLE_TYPE_SIZE 96 | |
366 | ||
367 | /* Define if you don't want extended real, but do want to use the | |
368 | software floating point emulator for REAL_ARITHMETIC and | |
369 | decimal <-> binary conversion. */ | |
370 | /* #define REAL_ARITHMETIC */ | |
371 | ||
c98f8742 JVA |
372 | /* Define this if most significant byte of a word is the lowest numbered. */ |
373 | /* That is true on the 80386. */ | |
374 | ||
375 | #define BITS_BIG_ENDIAN 0 | |
376 | ||
377 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
378 | /* That is not true on the 80386. */ | |
379 | #define BYTES_BIG_ENDIAN 0 | |
380 | ||
381 | /* Define this if most significant word of a multiword number is the lowest | |
382 | numbered. */ | |
383 | /* Not true for 80386 */ | |
384 | #define WORDS_BIG_ENDIAN 0 | |
385 | ||
b4ac57ab | 386 | /* number of bits in an addressable storage unit */ |
c98f8742 JVA |
387 | #define BITS_PER_UNIT 8 |
388 | ||
389 | /* Width in bits of a "word", which is the contents of a machine register. | |
390 | Note that this is not necessarily the width of data type `int'; | |
391 | if using 16-bit ints on a 80386, this would still be 32. | |
392 | But on a machine with 16-bit registers, this would be 16. */ | |
393 | #define BITS_PER_WORD 32 | |
394 | ||
395 | /* Width of a word, in units (bytes). */ | |
396 | #define UNITS_PER_WORD 4 | |
397 | ||
398 | /* Width in bits of a pointer. | |
399 | See also the macro `Pmode' defined below. */ | |
400 | #define POINTER_SIZE 32 | |
401 | ||
402 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
403 | #define PARM_BOUNDARY 32 | |
404 | ||
405 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
d5c65c96 | 406 | #define STACK_BOUNDARY 32 |
c98f8742 JVA |
407 | |
408 | /* Allocation boundary (in *bits*) for the code of a function. | |
409 | For i486, we get better performance by aligning to a cache | |
410 | line (i.e. 16 byte) boundary. */ | |
b08de47e | 411 | #define FUNCTION_BOUNDARY (1 << (i386_align_funcs + 3)) |
c98f8742 JVA |
412 | |
413 | /* Alignment of field after `int : 0' in a structure. */ | |
414 | ||
415 | #define EMPTY_FIELD_BOUNDARY 32 | |
416 | ||
417 | /* Minimum size in bits of the largest boundary to which any | |
418 | and all fundamental data types supported by the hardware | |
419 | might need to be aligned. No data type wants to be aligned | |
420 | rounder than this. The i386 supports 64-bit floating point | |
b08de47e MM |
421 | quantities, but these can be aligned on any 32-bit boundary. |
422 | The published ABIs say that doubles should be aligned on word | |
423 | boundaries, but the Pentium gets better performance with them | |
424 | aligned on 64 bit boundaries. */ | |
425 | #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) | |
c98f8742 | 426 | |
d4ba09c0 SC |
427 | /* align DFmode constants and nonaggregates */ |
428 | #define ALIGN_DFmode (!TARGET_386) | |
429 | ||
b4ac57ab | 430 | /* Set this non-zero if move instructions will actually fail to work |
c98f8742 | 431 | when given unaligned data. */ |
b4ac57ab | 432 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
433 | |
434 | /* If bit field type is int, don't let it cross an int, | |
435 | and give entire struct the alignment of an int. */ | |
436 | /* Required on the 386 since it doesn't have bitfield insns. */ | |
437 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
438 | ||
4bc679ad SC |
439 | /* An integer expression for the size in bits of the largest integer |
440 | machine mode that should actually be used. All integer machine modes of | |
441 | this size or smaller can be used for structures and unions with the | |
442 | appropriate sizes. */ | |
443 | #define MAX_FIXED_MODE_SIZE 32 | |
444 | ||
b08de47e MM |
445 | /* Maximum power of 2 that code can be aligned to. */ |
446 | #define MAX_CODE_ALIGN 6 /* 64 byte alignment */ | |
447 | ||
c98f8742 | 448 | /* Align loop starts for optimal branching. */ |
b08de47e | 449 | #define ASM_OUTPUT_LOOP_ALIGN(FILE) ASM_OUTPUT_ALIGN (FILE, i386_align_loops) |
c98f8742 JVA |
450 | |
451 | /* This is how to align an instruction for optimal branching. | |
452 | On i486 we'll get better performance by aligning on a | |
453 | cache line (i.e. 16 byte) boundary. */ | |
b08de47e MM |
454 | #define ASM_OUTPUT_ALIGN_CODE(FILE) ASM_OUTPUT_ALIGN ((FILE), i386_align_jumps) |
455 | ||
c98f8742 JVA |
456 | \f |
457 | /* Standard register usage. */ | |
458 | ||
459 | /* This processor has special stack-like registers. See reg-stack.c | |
460 | for details. */ | |
461 | ||
462 | #define STACK_REGS | |
d4ba09c0 | 463 | #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode || mode==XFmode) |
c98f8742 JVA |
464 | |
465 | /* Number of actual hardware registers. | |
466 | The hardware registers are assigned numbers for the compiler | |
467 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
468 | All registers that the compiler knows about must be given numbers, | |
469 | even those that are not normally considered general registers. | |
470 | ||
471 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
472 | We number the floating point registers 8-15. | |
473 | Note that registers 0-7 can be accessed as a short or int, | |
474 | while only 0-3 may be used with byte `mov' instructions. | |
475 | ||
476 | Reg 16 does not correspond to any hardware register, but instead | |
477 | appears in the RTL as an argument pointer prior to reload, and is | |
478 | eliminated during reloading in favor of either the stack or frame | |
479 | pointer. */ | |
480 | ||
481 | #define FIRST_PSEUDO_REGISTER 17 | |
482 | ||
483 | /* 1 for registers that have pervasive standard uses | |
484 | and are not available for the register allocator. | |
485 | On the 80386, the stack pointer is such, as is the arg pointer. */ | |
486 | #define FIXED_REGISTERS \ | |
487 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ | |
488 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
489 | ||
490 | /* 1 for registers not available across function calls. | |
491 | These must include the FIXED_REGISTERS and also any | |
492 | registers that can be used without being saved. | |
493 | The latter must include the registers where values are returned | |
494 | and the register where structure-value addresses are passed. | |
495 | Aside from that, you can include as many other registers as you like. */ | |
496 | ||
497 | #define CALL_USED_REGISTERS \ | |
498 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ | |
499 | { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
500 | ||
3b3c6a3f MM |
501 | /* Order in which to allocate registers. Each register must be |
502 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
503 | late and fixed registers last. Note that, in general, we prefer | |
504 | registers listed in CALL_USED_REGISTERS, keeping the others | |
505 | available for storage of persistent values. | |
506 | ||
507 | Three different versions of REG_ALLOC_ORDER have been tried: | |
508 | ||
509 | If the order is edx, ecx, eax, ... it produces a slightly faster compiler, | |
510 | but slower code on simple functions returning values in eax. | |
511 | ||
512 | If the order is eax, ecx, edx, ... it causes reload to abort when compiling | |
513 | perl 4.036 due to not being able to create a DImode register (to hold a 2 | |
514 | word union). | |
515 | ||
516 | If the order is eax, edx, ecx, ... it produces better code for simple | |
517 | functions, and a slightly slower compiler. Users complained about the code | |
518 | generated by allocating edx first, so restore the 'natural' order of things. */ | |
519 | ||
184ff798 | 520 | #define REG_ALLOC_ORDER \ |
f5316dfe MM |
521 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ |
522 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 } | |
523 | ||
524 | /* A C statement (sans semicolon) to choose the order in which to | |
525 | allocate hard registers for pseudo-registers local to a basic | |
526 | block. | |
527 | ||
528 | Store the desired register order in the array `reg_alloc_order'. | |
529 | Element 0 should be the register to allocate first; element 1, the | |
530 | next register; and so on. | |
531 | ||
532 | The macro body should not assume anything about the contents of | |
533 | `reg_alloc_order' before execution of the macro. | |
534 | ||
535 | On most machines, it is not necessary to define this macro. */ | |
536 | ||
537 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
184ff798 | 538 | |
c98f8742 JVA |
539 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
540 | #define CONDITIONAL_REGISTER_USAGE \ | |
541 | { \ | |
542 | if (flag_pic) \ | |
543 | { \ | |
544 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
545 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
546 | } \ | |
8c2bf92a JVA |
547 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ |
548 | { \ | |
549 | int i; \ | |
550 | HARD_REG_SET x; \ | |
551 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
552 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
553 | if (TEST_HARD_REG_BIT (x, i)) \ | |
554 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
555 | } \ | |
c98f8742 JVA |
556 | } |
557 | ||
558 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
559 | to hold something of mode MODE. | |
560 | This is ordinarily the length in words of a value of mode MODE | |
561 | but can be less for certain modes in special long registers. | |
562 | ||
563 | Actually there are no two word move instructions for consecutive | |
564 | registers. And only registers 0-3 may have mov byte instructions | |
565 | applied to them. | |
566 | */ | |
567 | ||
568 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
569 | (FP_REGNO_P (REGNO) ? 1 \ | |
570 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
571 | ||
572 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
573 | On the 80386, the first 4 cpu registers can hold any mode | |
574 | while the floating point registers may hold only floating point. | |
575 | Make it clear that the fp regs could not hold a 16-byte float. */ | |
576 | ||
48227a2c RS |
577 | /* The casts to int placate a compiler on a microvax, |
578 | for cross-compiler testing. */ | |
579 | ||
c98f8742 | 580 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
1bbe49a6 JVA |
581 | ((REGNO) < 2 ? 1 \ |
582 | : (REGNO) < 4 ? 1 \ | |
0038aea6 | 583 | : FP_REGNO_P (REGNO) \ |
48227a2c RS |
584 | ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \ |
585 | || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \ | |
62acf5fd | 586 | && GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\ |
b73c3f2a SC |
587 | : (int) (MODE) != (int) QImode ? 1 \ |
588 | : (reload_in_progress | reload_completed) == 1) | |
c98f8742 JVA |
589 | |
590 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
591 | when one has mode MODE1 and one has mode MODE2. | |
592 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
593 | for any hard reg, then this must be 0 for correct output. */ | |
594 | ||
595 | #define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) | |
596 | ||
c98f8742 JVA |
597 | /* Specify the registers used for certain standard purposes. |
598 | The values of these macros are register numbers. */ | |
599 | ||
600 | /* on the 386 the pc register is %eip, and is not usable as a general | |
601 | register. The ordinary mov instructions won't work */ | |
602 | /* #define PC_REGNUM */ | |
603 | ||
604 | /* Register to use for pushing function arguments. */ | |
605 | #define STACK_POINTER_REGNUM 7 | |
606 | ||
607 | /* Base register for access to local variables of the function. */ | |
608 | #define FRAME_POINTER_REGNUM 6 | |
609 | ||
610 | /* First floating point reg */ | |
611 | #define FIRST_FLOAT_REG 8 | |
612 | ||
613 | /* First & last stack-like regs */ | |
614 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
615 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
616 | ||
617 | /* Value should be nonzero if functions must have frame pointers. | |
618 | Zero means the frame pointer need not be set up (and parms | |
619 | may be accessed via the stack pointer) in functions that seem suitable. | |
620 | This is computed in `reload', in reload1.c. */ | |
2f2fa5b1 | 621 | #define FRAME_POINTER_REQUIRED (TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ()) |
c98f8742 JVA |
622 | |
623 | /* Base register for access to arguments of the function. */ | |
624 | #define ARG_POINTER_REGNUM 16 | |
625 | ||
626 | /* Register in which static-chain is passed to a function. */ | |
627 | #define STATIC_CHAIN_REGNUM 2 | |
628 | ||
629 | /* Register to hold the addressing base for position independent | |
630 | code access to data items. */ | |
631 | #define PIC_OFFSET_TABLE_REGNUM 3 | |
632 | ||
633 | /* Register in which address to store a structure value | |
634 | arrives in the function. On the 386, the prologue | |
635 | copies this from the stack to register %eax. */ | |
636 | #define STRUCT_VALUE_INCOMING 0 | |
637 | ||
638 | /* Place in which caller passes the structure value address. | |
639 | 0 means push the value on the stack like an argument. */ | |
640 | #define STRUCT_VALUE 0 | |
713225d4 MM |
641 | |
642 | /* A C expression which can inhibit the returning of certain function | |
643 | values in registers, based on the type of value. A nonzero value | |
644 | says to return the function value in memory, just as large | |
645 | structures are always returned. Here TYPE will be a C expression | |
646 | of type `tree', representing the data type of the value. | |
647 | ||
648 | Note that values of mode `BLKmode' must be explicitly handled by | |
649 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
650 | regardless of this macro. On most systems, it is possible to | |
651 | leave the macro undefined; this causes a default definition to be | |
652 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
653 | otherwise. | |
654 | ||
655 | Do not use this macro to indicate that structures and unions | |
656 | should always be returned in memory. You should instead use | |
657 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
658 | ||
659 | #define RETURN_IN_MEMORY(TYPE) \ | |
660 | ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12) | |
661 | ||
c98f8742 JVA |
662 | \f |
663 | /* Define the classes of registers for register constraints in the | |
664 | machine description. Also define ranges of constants. | |
665 | ||
666 | One of the classes must always be named ALL_REGS and include all hard regs. | |
667 | If there is more than one class, another class must be named NO_REGS | |
668 | and contain no registers. | |
669 | ||
670 | The name GENERAL_REGS must be the name of a class (or an alias for | |
671 | another name such as ALL_REGS). This is the class of registers | |
672 | that is allowed by "g" or "r" in a register constraint. | |
673 | Also, registers outside this class are allocated only when | |
674 | instructions express preferences for them. | |
675 | ||
676 | The classes must be numbered in nondecreasing order; that is, | |
677 | a larger-numbered class must never be contained completely | |
678 | in a smaller-numbered class. | |
679 | ||
680 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
681 | class that represents their union. |
682 | ||
683 | It might seem that class BREG is unnecessary, since no useful 386 | |
684 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
685 | and the "b" register constraint is useful in asms for syscalls. */ | |
c98f8742 JVA |
686 | |
687 | enum reg_class | |
688 | { | |
689 | NO_REGS, | |
ab408a86 | 690 | AREG, DREG, CREG, BREG, |
4b71cd6e | 691 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 JVA |
692 | Q_REGS, /* %eax %ebx %ecx %edx */ |
693 | SIREG, DIREG, | |
694 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ | |
695 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ | |
696 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ | |
697 | FLOAT_REGS, | |
698 | ALL_REGS, LIM_REG_CLASSES | |
699 | }; | |
700 | ||
701 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
702 | ||
4cbb525c JVA |
703 | #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) |
704 | ||
c98f8742 JVA |
705 | /* Give names of register classes as strings for dump file. */ |
706 | ||
707 | #define REG_CLASS_NAMES \ | |
708 | { "NO_REGS", \ | |
ab408a86 | 709 | "AREG", "DREG", "CREG", "BREG", \ |
4b71cd6e | 710 | "AD_REGS", \ |
c98f8742 JVA |
711 | "Q_REGS", \ |
712 | "SIREG", "DIREG", \ | |
713 | "INDEX_REGS", \ | |
714 | "GENERAL_REGS", \ | |
715 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
716 | "FLOAT_REGS", \ | |
717 | "ALL_REGS" } | |
718 | ||
719 | /* Define which registers fit in which classes. | |
720 | This is an initializer for a vector of HARD_REG_SET | |
721 | of length N_REG_CLASSES. */ | |
722 | ||
723 | #define REG_CLASS_CONTENTS \ | |
724 | { 0, \ | |
ab408a86 | 725 | 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ |
4b71cd6e | 726 | 0x3, /* AD_REGS */ \ |
c98f8742 JVA |
727 | 0xf, /* Q_REGS */ \ |
728 | 0x10, 0x20, /* SIREG, DIREG */ \ | |
d4ba09c0 | 729 | 0x7f, /* INDEX_REGS */ \ |
c98f8742 JVA |
730 | 0x100ff, /* GENERAL_REGS */ \ |
731 | 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ | |
732 | 0xff00, /* FLOAT_REGS */ \ | |
733 | 0x1ffff } | |
734 | ||
735 | /* The same information, inverted: | |
736 | Return the class number of the smallest class containing | |
737 | reg number REGNO. This could be a conditional expression | |
738 | or could index an array. */ | |
739 | ||
c98f8742 JVA |
740 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
741 | ||
742 | /* When defined, the compiler allows registers explicitly used in the | |
743 | rtl to be used as spill registers but prevents the compiler from | |
744 | extending the lifetime of these registers. */ | |
745 | ||
2922fe9e | 746 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 JVA |
747 | |
748 | #define QI_REG_P(X) \ | |
749 | (REG_P (X) && REGNO (X) < 4) | |
750 | #define NON_QI_REG_P(X) \ | |
751 | (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) | |
752 | ||
753 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
754 | #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) | |
755 | ||
756 | #define STACK_REG_P(xop) (REG_P (xop) && \ | |
757 | REGNO (xop) >= FIRST_STACK_REG && \ | |
758 | REGNO (xop) <= LAST_STACK_REG) | |
759 | ||
760 | #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) | |
761 | ||
762 | #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) | |
763 | ||
764 | /* Try to maintain the accuracy of the death notes for regs satisfying the | |
765 | following. Important for stack like regs, to know when to pop. */ | |
766 | ||
767 | /* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */ | |
768 | ||
769 | /* 1 if register REGNO can magically overlap other regs. | |
770 | Note that nonzero values work only in very special circumstances. */ | |
771 | ||
772 | /* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */ | |
773 | ||
774 | /* The class value for index registers, and the one for base regs. */ | |
775 | ||
776 | #define INDEX_REG_CLASS INDEX_REGS | |
777 | #define BASE_REG_CLASS GENERAL_REGS | |
778 | ||
779 | /* Get reg_class from a letter such as appears in the machine description. */ | |
780 | ||
781 | #define REG_CLASS_FROM_LETTER(C) \ | |
8c2bf92a JVA |
782 | ((C) == 'r' ? GENERAL_REGS : \ |
783 | (C) == 'q' ? Q_REGS : \ | |
784 | (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
785 | ? FLOAT_REGS \ | |
786 | : NO_REGS) : \ | |
787 | (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
788 | ? FP_TOP_REG \ | |
789 | : NO_REGS) : \ | |
790 | (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
791 | ? FP_SECOND_REG \ | |
792 | : NO_REGS) : \ | |
793 | (C) == 'a' ? AREG : \ | |
794 | (C) == 'b' ? BREG : \ | |
795 | (C) == 'c' ? CREG : \ | |
796 | (C) == 'd' ? DREG : \ | |
4b71cd6e | 797 | (C) == 'A' ? AD_REGS : \ |
8c2bf92a | 798 | (C) == 'D' ? DIREG : \ |
c98f8742 JVA |
799 | (C) == 'S' ? SIREG : NO_REGS) |
800 | ||
801 | /* The letters I, J, K, L and M in a register constraint string | |
802 | can be used to stand for particular ranges of immediate operands. | |
803 | This macro defines what the ranges are. | |
804 | C is the letter, and VALUE is a constant value. | |
805 | Return 1 if VALUE is in the range specified by C. | |
806 | ||
807 | I is for non-DImode shifts. | |
808 | J is for DImode shifts. | |
809 | K and L are for an `andsi' optimization. | |
810 | M is for shifts that can be executed by the "lea" opcode. | |
811 | */ | |
812 | ||
813 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
814 | ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \ | |
815 | (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \ | |
816 | (C) == 'K' ? (VALUE) == 0xff : \ | |
817 | (C) == 'L' ? (VALUE) == 0xffff : \ | |
818 | (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ | |
b4232589 | 819 | (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 :\ |
d4ba09c0 | 820 | (C) == 'O' ? (VALUE) >= 0 && (VALUE) <= 32 : \ |
c98f8742 JVA |
821 | 0) |
822 | ||
823 | /* Similar, but for floating constants, and defining letters G and H. | |
b4ac57ab RS |
824 | Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if |
825 | TARGET_387 isn't set, because the stack register converter may need to | |
826 | load 0.0 into the function value register. */ | |
c98f8742 JVA |
827 | |
828 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
b4ac57ab | 829 | ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) |
c98f8742 JVA |
830 | |
831 | /* Place additional restrictions on the register class to use when it | |
4cbb525c JVA |
832 | is necessary to be able to hold a value of mode MODE in a reload |
833 | register for which class CLASS would ordinarily be used. */ | |
c98f8742 JVA |
834 | |
835 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
836 | ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ | |
837 | ? Q_REGS : (CLASS)) | |
838 | ||
839 | /* Given an rtx X being reloaded into a reg required to be | |
840 | in class CLASS, return the class of reg to actually use. | |
841 | In general this is just CLASS; but on some machines | |
842 | in some cases it is preferable to use a more restrictive class. | |
843 | On the 80386 series, we prevent floating constants from being | |
844 | reloaded into floating registers (since no move-insn can do that) | |
845 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
846 | ||
d398b3b1 | 847 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 848 | QImode must go into class Q_REGS. |
d398b3b1 JVA |
849 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
850 | movdf to do mem-to-mem moves through integer regs. */ | |
c98f8742 | 851 | |
7488be4e | 852 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
85ff473e JVA |
853 | (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \ |
854 | : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ | |
d398b3b1 JVA |
855 | : ((CLASS) == ALL_REGS \ |
856 | && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \ | |
85ff473e JVA |
857 | : (CLASS)) |
858 | ||
859 | /* If we are copying between general and FP registers, we need a memory | |
860 | location. */ | |
861 | ||
862 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
4cbb525c JVA |
863 | ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ |
864 | || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) | |
c98f8742 JVA |
865 | |
866 | /* Return the maximum number of consecutive registers | |
867 | needed to represent mode MODE in a register of class CLASS. */ | |
868 | /* On the 80386, this is the size of MODE in words, | |
869 | except in the FP regs, where a single reg is always enough. */ | |
870 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
4cbb525c JVA |
871 | (FLOAT_CLASS_P (CLASS) ? 1 : \ |
872 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
873 | |
874 | /* A C expression whose value is nonzero if pseudos that have been | |
875 | assigned to registers of class CLASS would likely be spilled | |
876 | because registers of CLASS are needed for spill registers. | |
877 | ||
878 | The default value of this macro returns 1 if CLASS has exactly one | |
879 | register and zero otherwise. On most machines, this default | |
880 | should be used. Only define this macro to some other expression | |
881 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 882 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
883 | macro returns nonzero for those classes, those pseudos will only |
884 | be allocated by `global.c', which knows how to reallocate the | |
885 | pseudo to another register. If there would not be another | |
886 | register available for reallocation, you should not change the | |
887 | definition of this macro since the only effect of such a | |
888 | definition would be to slow down register allocation. */ | |
889 | ||
890 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
891 | (((CLASS) == AREG) \ | |
892 | || ((CLASS) == DREG) \ | |
893 | || ((CLASS) == CREG) \ | |
894 | || ((CLASS) == BREG) \ | |
895 | || ((CLASS) == AD_REGS) \ | |
896 | || ((CLASS) == SIREG) \ | |
897 | || ((CLASS) == DIREG)) | |
898 | ||
c98f8742 JVA |
899 | \f |
900 | /* Stack layout; function entry, exit and calling. */ | |
901 | ||
902 | /* Define this if pushing a word on the stack | |
903 | makes the stack pointer a smaller address. */ | |
904 | #define STACK_GROWS_DOWNWARD | |
905 | ||
906 | /* Define this if the nominal address of the stack frame | |
907 | is at the high-address end of the local variables; | |
908 | that is, each additional local variable allocated | |
909 | goes at a more negative offset in the frame. */ | |
910 | #define FRAME_GROWS_DOWNWARD | |
911 | ||
912 | /* Offset within stack frame to start allocating local variables at. | |
913 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
914 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
915 | of the first local allocated. */ | |
916 | #define STARTING_FRAME_OFFSET 0 | |
917 | ||
918 | /* If we generate an insn to push BYTES bytes, | |
919 | this says how many the stack pointer really advances by. | |
920 | On 386 pushw decrements by exactly 2 no matter what the position was. | |
921 | On the 386 there is no pushb; we use pushw instead, and this | |
922 | has the effect of rounding up to 2. */ | |
923 | ||
924 | #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) | |
925 | ||
926 | /* Offset of first parameter from the argument pointer register value. */ | |
927 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
928 | ||
929 | /* Value is the number of bytes of arguments automatically | |
930 | popped when returning from a subroutine call. | |
8b109b37 | 931 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
932 | FUNTYPE is the data type of the function (as a tree), |
933 | or for a library call it is an identifier node for the subroutine name. | |
934 | SIZE is the number of bytes of arguments passed on the stack. | |
935 | ||
936 | On the 80386, the RTD insn may be used to pop them if the number | |
937 | of args is fixed, but if the number is variable then the caller | |
938 | must pop them all. RTD can't be used for library calls now | |
939 | because the library is compiled with the Unix compiler. | |
940 | Use of RTD is a selectable option, since it is incompatible with | |
941 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
942 | the caller must always pop the args. |
943 | ||
944 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 945 | |
b08de47e MM |
946 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
947 | (i386_return_pops_args (FUNDECL, FUNTYPE, SIZE)) | |
c98f8742 | 948 | |
8c2bf92a JVA |
949 | /* Define how to find the value returned by a function. |
950 | VALTYPE is the data type of the value (as a tree). | |
951 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
952 | otherwise, FUNC is 0. */ | |
c98f8742 | 953 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
f64cecad | 954 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ |
c98f8742 JVA |
955 | VALUE_REGNO (TYPE_MODE (VALTYPE))) |
956 | ||
957 | /* Define how to find the value returned by a library function | |
958 | assuming the value has mode MODE. */ | |
959 | ||
960 | #define LIBCALL_VALUE(MODE) \ | |
f64cecad | 961 | gen_rtx_REG (MODE, VALUE_REGNO (MODE)) |
c98f8742 | 962 | |
e9125c09 TW |
963 | /* Define the size of the result block used for communication between |
964 | untyped_call and untyped_return. The block contains a DImode value | |
965 | followed by the block used by fnsave and frstor. */ | |
966 | ||
967 | #define APPLY_RESULT_SIZE (8+108) | |
968 | ||
b08de47e MM |
969 | /* 1 if N is a possible register number for function argument passing. */ |
970 | #define FUNCTION_ARG_REGNO_P(N) ((N) >= 0 && (N) < REGPARM_MAX) | |
c98f8742 JVA |
971 | |
972 | /* Define a data type for recording info about an argument list | |
973 | during the scan of that argument list. This data type should | |
974 | hold all necessary information about the function itself | |
975 | and about the args processed so far, enough to enable macros | |
b08de47e | 976 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 977 | |
b08de47e MM |
978 | typedef struct i386_args { |
979 | int words; /* # words passed so far */ | |
980 | int nregs; /* # registers available for passing */ | |
981 | int regno; /* next available register number */ | |
982 | } CUMULATIVE_ARGS; | |
c98f8742 JVA |
983 | |
984 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
985 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 986 | For a library call, FNTYPE is 0. */ |
c98f8742 | 987 | |
2c7ee1a6 | 988 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
b08de47e | 989 | (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) |
c98f8742 JVA |
990 | |
991 | /* Update the data in CUM to advance over an argument | |
992 | of mode MODE and data type TYPE. | |
993 | (TYPE is null for libcalls where that information may not be available.) */ | |
994 | ||
995 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
b08de47e | 996 | (function_arg_advance (&CUM, MODE, TYPE, NAMED)) |
c98f8742 JVA |
997 | |
998 | /* Define where to put the arguments to a function. | |
999 | Value is zero to push the argument on the stack, | |
1000 | or a hard register in which to store the argument. | |
1001 | ||
1002 | MODE is the argument's machine mode. | |
1003 | TYPE is the data type of the argument (as a tree). | |
1004 | This is null for libcalls where that information may | |
1005 | not be available. | |
1006 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1007 | the preceding args and about the function being called. | |
1008 | NAMED is nonzero if this argument is a named parameter | |
1009 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1010 | ||
c98f8742 | 1011 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
b08de47e | 1012 | (function_arg (&CUM, MODE, TYPE, NAMED)) |
c98f8742 JVA |
1013 | |
1014 | /* For an arg passed partly in registers and partly in memory, | |
1015 | this is the number of registers used. | |
1016 | For args passed entirely in registers or entirely in memory, zero. */ | |
1017 | ||
c98f8742 | 1018 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ |
b08de47e | 1019 | (function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)) |
c98f8742 | 1020 | |
3a0433fd SC |
1021 | /* This macro is invoked just before the start of a function. |
1022 | It is used here to output code for -fpic that will load the | |
1023 | return address into %ebx. */ | |
1024 | ||
1025 | #undef ASM_OUTPUT_FUNCTION_PREFIX | |
1026 | #define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \ | |
1027 | asm_output_function_prefix (FILE, FNNAME) | |
1028 | ||
c98f8742 JVA |
1029 | /* This macro generates the assembly code for function entry. |
1030 | FILE is a stdio stream to output the code to. | |
1031 | SIZE is an int: how many units of temporary storage to allocate. | |
1032 | Refer to the array `regs_ever_live' to determine which registers | |
1033 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1034 | is ever used in the function. This macro is responsible for | |
1035 | knowing which registers should not be saved even if used. */ | |
1036 | ||
1037 | #define FUNCTION_PROLOGUE(FILE, SIZE) \ | |
1038 | function_prologue (FILE, SIZE) | |
1039 | ||
1040 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
1041 | for profiling a function entry. */ | |
1042 | ||
1043 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1044 | { \ | |
1045 | if (flag_pic) \ | |
1046 | { \ | |
1047 | fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ | |
1048 | LPREFIX, (LABELNO)); \ | |
1049 | fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \ | |
1050 | } \ | |
1051 | else \ | |
1052 | { \ | |
1053 | fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ | |
1054 | fprintf (FILE, "\tcall _mcount\n"); \ | |
1055 | } \ | |
1056 | } | |
1057 | ||
1cf5eda8 | 1058 | |
6e753900 RK |
1059 | /* There are three profiling modes for basic blocks available. |
1060 | The modes are selected at compile time by using the options | |
1061 | -a or -ax of the gnu compiler. | |
1062 | The variable `profile_block_flag' will be set according to the | |
1063 | selected option. | |
1cf5eda8 | 1064 | |
6e753900 | 1065 | profile_block_flag == 0, no option used: |
1cf5eda8 | 1066 | |
6e753900 | 1067 | No profiling done. |
1cf5eda8 | 1068 | |
6e753900 RK |
1069 | profile_block_flag == 1, -a option used. |
1070 | ||
1071 | Count frequency of execution of every basic block. | |
1072 | ||
1073 | profile_block_flag == 2, -ax option used. | |
1074 | ||
1075 | Generate code to allow several different profiling modes at run time. | |
1076 | Available modes are: | |
1077 | Produce a trace of all basic blocks. | |
1078 | Count frequency of jump instructions executed. | |
1079 | In every mode it is possible to start profiling upon entering | |
1080 | certain functions and to disable profiling of some other functions. | |
1081 | ||
1082 | The result of basic-block profiling will be written to a file `bb.out'. | |
1083 | If the -ax option is used parameters for the profiling will be read | |
1084 | from file `bb.in'. | |
1085 | ||
1086 | */ | |
1087 | ||
1088 | /* The following macro shall output assembler code to FILE | |
1089 | to initialize basic-block profiling. | |
1090 | ||
1091 | If profile_block_flag == 2 | |
1092 | ||
1093 | Output code to call the subroutine `__bb_init_trace_func' | |
1094 | and pass two parameters to it. The first parameter is | |
1095 | the address of a block allocated in the object module. | |
1096 | The second parameter is the number of the first basic block | |
1097 | of the function. | |
1098 | ||
1099 | The name of the block is a local symbol made with this statement: | |
1100 | ||
1101 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
1102 | ||
1103 | Of course, since you are writing the definition of | |
1104 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1105 | can take a short cut in the definition of this macro and use the | |
1106 | name that you know will result. | |
1107 | ||
1108 | The number of the first basic block of the function is | |
1109 | passed to the macro in BLOCK_OR_LABEL. | |
1110 | ||
1111 | If described in a virtual assembler language the code to be | |
1112 | output looks like: | |
1113 | ||
1114 | parameter1 <- LPBX0 | |
1115 | parameter2 <- BLOCK_OR_LABEL | |
1116 | call __bb_init_trace_func | |
1117 | ||
1118 | else if profile_block_flag != 0 | |
1119 | ||
1120 | Output code to call the subroutine `__bb_init_func' | |
1121 | and pass one single parameter to it, which is the same | |
1122 | as the first parameter to `__bb_init_trace_func'. | |
1123 | ||
1124 | The first word of this parameter is a flag which will be nonzero if | |
1125 | the object module has already been initialized. So test this word | |
1126 | first, and do not call `__bb_init_func' if the flag is nonzero. | |
1127 | Note: When profile_block_flag == 2 the test need not be done | |
1128 | but `__bb_init_trace_func' *must* be called. | |
1129 | ||
1130 | BLOCK_OR_LABEL may be used to generate a label number as a | |
1131 | branch destination in case `__bb_init_func' will not be called. | |
1132 | ||
1133 | If described in a virtual assembler language the code to be | |
1134 | output looks like: | |
1135 | ||
1136 | cmp (LPBX0),0 | |
1137 | jne local_label | |
1138 | parameter1 <- LPBX0 | |
1139 | call __bb_init_func | |
1140 | local_label: | |
1141 | ||
1142 | */ | |
1cf5eda8 MM |
1143 | |
1144 | #undef FUNCTION_BLOCK_PROFILER | |
6e753900 | 1145 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ |
1cf5eda8 MM |
1146 | do \ |
1147 | { \ | |
1148 | static int num_func = 0; \ | |
8ecf187a | 1149 | rtx xops[8]; \ |
1cf5eda8 MM |
1150 | char block_table[80], false_label[80]; \ |
1151 | \ | |
1152 | ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); \ | |
1cf5eda8 | 1153 | \ |
f64cecad | 1154 | xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table); \ |
1cf5eda8 | 1155 | xops[5] = stack_pointer_rtx; \ |
f64cecad | 1156 | xops[7] = gen_rtx_REG (Pmode, 0); /* eax */ \ |
1cf5eda8 MM |
1157 | \ |
1158 | CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; \ | |
1cf5eda8 | 1159 | \ |
6e753900 | 1160 | switch (profile_block_flag) \ |
1cf5eda8 | 1161 | { \ |
1cf5eda8 | 1162 | \ |
6e753900 RK |
1163 | case 2: \ |
1164 | \ | |
1165 | xops[2] = GEN_INT ((BLOCK_OR_LABEL)); \ | |
f64cecad | 1166 | xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_trace_func")); \ |
6e753900 RK |
1167 | xops[6] = GEN_INT (8); \ |
1168 | \ | |
1169 | output_asm_insn (AS1(push%L2,%2), xops); \ | |
1170 | if (!flag_pic) \ | |
1171 | output_asm_insn (AS1(push%L1,%1), xops); \ | |
1172 | else \ | |
1173 | { \ | |
1174 | output_asm_insn (AS2 (lea%L7,%a1,%7), xops); \ | |
1175 | output_asm_insn (AS1 (push%L7,%7), xops); \ | |
1176 | } \ | |
1177 | \ | |
1178 | output_asm_insn (AS1(call,%P3), xops); \ | |
1179 | output_asm_insn (AS2(add%L0,%6,%5), xops); \ | |
1180 | \ | |
1181 | break; \ | |
1182 | \ | |
1183 | default: \ | |
1184 | \ | |
1185 | ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func); \ | |
1186 | \ | |
1187 | xops[0] = const0_rtx; \ | |
f64cecad JC |
1188 | xops[2] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, false_label)); \ |
1189 | xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_init_func")); \ | |
1190 | xops[4] = gen_rtx_MEM (Pmode, xops[1]); \ | |
6e753900 RK |
1191 | xops[6] = GEN_INT (4); \ |
1192 | \ | |
1193 | CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE; \ | |
1194 | \ | |
1195 | output_asm_insn (AS2(cmp%L4,%0,%4), xops); \ | |
1196 | output_asm_insn (AS1(jne,%2), xops); \ | |
1197 | \ | |
1198 | if (!flag_pic) \ | |
1199 | output_asm_insn (AS1(push%L1,%1), xops); \ | |
1200 | else \ | |
1201 | { \ | |
1202 | output_asm_insn (AS2 (lea%L7,%a1,%7), xops); \ | |
1203 | output_asm_insn (AS1 (push%L7,%7), xops); \ | |
1204 | } \ | |
1205 | \ | |
1206 | output_asm_insn (AS1(call,%P3), xops); \ | |
1207 | output_asm_insn (AS2(add%L0,%6,%5), xops); \ | |
1208 | ASM_OUTPUT_INTERNAL_LABEL (FILE, "LPBZ", num_func); \ | |
1209 | num_func++; \ | |
1210 | \ | |
1211 | break; \ | |
1212 | \ | |
1213 | } \ | |
1cf5eda8 MM |
1214 | } \ |
1215 | while (0) | |
1216 | ||
6e753900 RK |
1217 | /* The following macro shall output assembler code to FILE |
1218 | to increment a counter associated with basic block number BLOCKNO. | |
1219 | ||
1220 | If profile_block_flag == 2 | |
1221 | ||
1222 | Output code to initialize the global structure `__bb' and | |
1223 | call the function `__bb_trace_func' which will increment the | |
1224 | counter. | |
1225 | ||
1226 | `__bb' consists of two words. In the first word the number | |
1227 | of the basic block has to be stored. In the second word | |
1228 | the address of a block allocated in the object module | |
1229 | has to be stored. | |
1230 | ||
1231 | The basic block number is given by BLOCKNO. | |
1232 | ||
1233 | The address of the block is given by the label created with | |
1234 | ||
1235 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); | |
1236 | ||
1237 | by FUNCTION_BLOCK_PROFILER. | |
1cf5eda8 | 1238 | |
6e753900 RK |
1239 | Of course, since you are writing the definition of |
1240 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1241 | can take a short cut in the definition of this macro and use the | |
1242 | name that you know will result. | |
1cf5eda8 | 1243 | |
6e753900 RK |
1244 | If described in a virtual assembler language the code to be |
1245 | output looks like: | |
1cf5eda8 | 1246 | |
6e753900 RK |
1247 | move BLOCKNO -> (__bb) |
1248 | move LPBX0 -> (__bb+4) | |
1249 | call __bb_trace_func | |
1cf5eda8 | 1250 | |
6e753900 RK |
1251 | Note that function `__bb_trace_func' must not change the |
1252 | machine state, especially the flag register. To grant | |
1253 | this, you must output code to save and restore registers | |
1254 | either in this macro or in the macros MACHINE_STATE_SAVE | |
1255 | and MACHINE_STATE_RESTORE. The last two macros will be | |
1256 | used in the function `__bb_trace_func', so you must make | |
1257 | sure that the function prologue does not change any | |
1258 | register prior to saving it with MACHINE_STATE_SAVE. | |
1259 | ||
1260 | else if profile_block_flag != 0 | |
1261 | ||
1262 | Output code to increment the counter directly. | |
1263 | Basic blocks are numbered separately from zero within each | |
1264 | compiled object module. The count associated with block number | |
1265 | BLOCKNO is at index BLOCKNO in an array of words; the name of | |
1266 | this array is a local symbol made with this statement: | |
1267 | ||
1268 | ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); | |
1269 | ||
1270 | Of course, since you are writing the definition of | |
1271 | `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you | |
1272 | can take a short cut in the definition of this macro and use the | |
1273 | name that you know will result. | |
1274 | ||
1275 | If described in a virtual assembler language the code to be | |
1276 | output looks like: | |
1277 | ||
1278 | inc (LPBX2+4*BLOCKNO) | |
1279 | ||
1280 | */ | |
1281 | ||
1282 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1cf5eda8 MM |
1283 | do \ |
1284 | { \ | |
6e753900 | 1285 | rtx xops[8], cnt_rtx; \ |
1cf5eda8 | 1286 | char counts[80]; \ |
6e753900 RK |
1287 | char *block_table = counts; \ |
1288 | \ | |
1289 | switch (profile_block_flag) \ | |
1290 | { \ | |
1291 | \ | |
1292 | case 2: \ | |
1293 | \ | |
1294 | ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); \ | |
1295 | \ | |
f64cecad | 1296 | xops[1] = gen_rtx_SYMBOL_REF (VOIDmode, block_table); \ |
6e753900 | 1297 | xops[2] = GEN_INT ((BLOCKNO)); \ |
f64cecad JC |
1298 | xops[3] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_func")); \ |
1299 | xops[4] = gen_rtx_SYMBOL_REF (VOIDmode, "__bb"); \ | |
6e753900 | 1300 | xops[5] = plus_constant (xops[4], 4); \ |
f64cecad JC |
1301 | xops[0] = gen_rtx_MEM (SImode, xops[4]); \ |
1302 | xops[6] = gen_rtx_MEM (SImode, xops[5]); \ | |
6e753900 RK |
1303 | \ |
1304 | CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; \ | |
1305 | \ | |
1306 | fprintf(FILE, "\tpushf\n"); \ | |
1307 | output_asm_insn (AS2(mov%L0,%2,%0), xops); \ | |
1308 | if (flag_pic) \ | |
1309 | { \ | |
f64cecad | 1310 | xops[7] = gen_rtx_REG (Pmode, 0); /* eax */ \ |
6e753900 RK |
1311 | output_asm_insn (AS1(push%L7,%7), xops); \ |
1312 | output_asm_insn (AS2(lea%L7,%a1,%7), xops); \ | |
1313 | output_asm_insn (AS2(mov%L6,%7,%6), xops); \ | |
1314 | output_asm_insn (AS1(pop%L7,%7), xops); \ | |
1315 | } \ | |
1316 | else \ | |
1317 | output_asm_insn (AS2(mov%L6,%1,%6), xops); \ | |
1318 | output_asm_insn (AS1(call,%P3), xops); \ | |
1319 | fprintf(FILE, "\tpopf\n"); \ | |
1320 | \ | |
1321 | break; \ | |
1322 | \ | |
1323 | default: \ | |
1324 | \ | |
1325 | ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2); \ | |
f64cecad | 1326 | cnt_rtx = gen_rtx_SYMBOL_REF (VOIDmode, counts); \ |
6e753900 | 1327 | SYMBOL_REF_FLAG (cnt_rtx) = TRUE; \ |
1cf5eda8 | 1328 | \ |
6e753900 RK |
1329 | if (BLOCKNO) \ |
1330 | cnt_rtx = plus_constant (cnt_rtx, (BLOCKNO)*4); \ | |
1cf5eda8 | 1331 | \ |
6e753900 | 1332 | if (flag_pic) \ |
f64cecad | 1333 | cnt_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, cnt_rtx); \ |
05ca35c7 | 1334 | \ |
f64cecad | 1335 | xops[0] = gen_rtx_MEM (SImode, cnt_rtx); \ |
6e753900 | 1336 | output_asm_insn (AS1(inc%L0,%0), xops); \ |
05ca35c7 | 1337 | \ |
6e753900 RK |
1338 | break; \ |
1339 | \ | |
1340 | } \ | |
1cf5eda8 MM |
1341 | } \ |
1342 | while (0) | |
1343 | ||
6e753900 RK |
1344 | /* The following macro shall output assembler code to FILE |
1345 | to indicate a return from function during basic-block profiling. | |
1346 | ||
1347 | If profiling_block_flag == 2: | |
1348 | ||
1349 | Output assembler code to call function `__bb_trace_ret'. | |
1350 | ||
1351 | Note that function `__bb_trace_ret' must not change the | |
1352 | machine state, especially the flag register. To grant | |
1353 | this, you must output code to save and restore registers | |
1354 | either in this macro or in the macros MACHINE_STATE_SAVE_RET | |
1355 | and MACHINE_STATE_RESTORE_RET. The last two macros will be | |
1356 | used in the function `__bb_trace_ret', so you must make | |
1357 | sure that the function prologue does not change any | |
1358 | register prior to saving it with MACHINE_STATE_SAVE_RET. | |
1359 | ||
1360 | else if profiling_block_flag != 0: | |
1361 | ||
1362 | The macro will not be used, so it need not distinguish | |
1363 | these cases. | |
1364 | */ | |
1365 | ||
1366 | #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \ | |
1367 | do \ | |
1368 | { \ | |
1369 | rtx xops[1]; \ | |
1370 | \ | |
f64cecad | 1371 | xops[0] = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")); \ |
6e753900 RK |
1372 | \ |
1373 | output_asm_insn (AS1(call,%P0), xops); \ | |
1374 | \ | |
1375 | } \ | |
1376 | while (0) | |
1377 | ||
1378 | /* The function `__bb_trace_func' is called in every basic block | |
1379 | and is not allowed to change the machine state. Saving (restoring) | |
1380 | the state can either be done in the BLOCK_PROFILER macro, | |
1381 | before calling function (rsp. after returning from function) | |
1382 | `__bb_trace_func', or it can be done inside the function by | |
1383 | defining the macros: | |
1384 | ||
1385 | MACHINE_STATE_SAVE(ID) | |
1386 | MACHINE_STATE_RESTORE(ID) | |
1387 | ||
1388 | In the latter case care must be taken, that the prologue code | |
1389 | of function `__bb_trace_func' does not already change the | |
1390 | state prior to saving it with MACHINE_STATE_SAVE. | |
1391 | ||
1392 | The parameter `ID' is a string identifying a unique macro use. | |
1393 | ||
1394 | On the i386 the initialization code at the begin of | |
1395 | function `__bb_trace_func' contains a `sub' instruction | |
1396 | therefore we handle save and restore of the flag register | |
1397 | in the BLOCK_PROFILER macro. */ | |
1398 | ||
1399 | #define MACHINE_STATE_SAVE(ID) \ | |
1400 | asm (" pushl %eax"); \ | |
1401 | asm (" pushl %ecx"); \ | |
1402 | asm (" pushl %edx"); \ | |
1403 | asm (" pushl %esi"); | |
1404 | ||
1405 | #define MACHINE_STATE_RESTORE(ID) \ | |
1406 | asm (" popl %esi"); \ | |
1407 | asm (" popl %edx"); \ | |
1408 | asm (" popl %ecx"); \ | |
1409 | asm (" popl %eax"); | |
1410 | ||
c98f8742 JVA |
1411 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1412 | the stack pointer does not matter. The value is tested only in | |
1413 | functions that have frame pointers. | |
1414 | No definition is equivalent to always zero. */ | |
1415 | /* Note on the 386 it might be more efficient not to define this since | |
1416 | we have to restore it ourselves from the frame pointer, in order to | |
1417 | use pop */ | |
1418 | ||
1419 | #define EXIT_IGNORE_STACK 1 | |
1420 | ||
1421 | /* This macro generates the assembly code for function exit, | |
1422 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
1423 | then individual return instructions are generated for each | |
1424 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
1425 | ||
1426 | The function epilogue should not depend on the current stack pointer! | |
1427 | It should use the frame pointer only. This is mandatory because | |
1428 | of alloca; we also take advantage of it to omit stack adjustments | |
1429 | before returning. | |
1430 | ||
1431 | If the last non-note insn in the function is a BARRIER, then there | |
1432 | is no need to emit a function prologue, because control does not fall | |
1433 | off the end. This happens if the function ends in an "exit" call, or | |
1434 | if a `return' insn is emitted directly into the function. */ | |
1435 | ||
2f2fa5b1 SC |
1436 | #if 0 |
1437 | #define FUNCTION_BEGIN_EPILOGUE(FILE) \ | |
c98f8742 JVA |
1438 | do { \ |
1439 | rtx last = get_last_insn (); \ | |
1440 | if (last && GET_CODE (last) == NOTE) \ | |
1441 | last = prev_nonnote_insn (last); \ | |
2f2fa5b1 SC |
1442 | /* if (! last || GET_CODE (last) != BARRIER) \ |
1443 | function_epilogue (FILE, SIZE);*/ \ | |
c98f8742 | 1444 | } while (0) |
2f2fa5b1 SC |
1445 | #endif |
1446 | ||
1447 | #define FUNCTION_EPILOGUE(FILE, SIZE) \ | |
1448 | function_epilogue (FILE, SIZE) | |
c98f8742 JVA |
1449 | |
1450 | /* Output assembler code for a block containing the constant parts | |
1451 | of a trampoline, leaving space for the variable parts. */ | |
1452 | ||
1453 | /* On the 386, the trampoline contains three instructions: | |
1454 | mov #STATIC,ecx | |
1455 | mov #FUNCTION,eax | |
1456 | jmp @eax */ | |
8c2bf92a JVA |
1457 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
1458 | { \ | |
1459 | ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \ | |
1460 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
1461 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
1462 | ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \ | |
1463 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
1464 | ASM_OUTPUT_SHORT (FILE, const0_rtx); \ | |
1465 | ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \ | |
1466 | ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \ | |
c98f8742 JVA |
1467 | } |
1468 | ||
1469 | /* Length in units of the trampoline for entering a nested function. */ | |
1470 | ||
1471 | #define TRAMPOLINE_SIZE 12 | |
1472 | ||
1473 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1474 | FNADDR is an RTX for the address of the function's pure code. | |
1475 | CXT is an RTX for the static chain value for the function. */ | |
1476 | ||
1477 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1478 | { \ | |
f64cecad JC |
1479 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \ |
1480 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), FNADDR); \ | |
c98f8742 JVA |
1481 | } |
1482 | \f | |
1483 | /* Definitions for register eliminations. | |
1484 | ||
1485 | This is an array of structures. Each structure initializes one pair | |
1486 | of eliminable registers. The "from" register number is given first, | |
1487 | followed by "to". Eliminations of the same "from" register are listed | |
1488 | in order of preference. | |
1489 | ||
1490 | We have two registers that can be eliminated on the i386. First, the | |
1491 | frame pointer register can often be eliminated in favor of the stack | |
1492 | pointer register. Secondly, the argument pointer register can always be | |
1493 | eliminated; it is replaced with either the stack or frame pointer. */ | |
1494 | ||
1495 | #define ELIMINABLE_REGS \ | |
1496 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1497 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
1498 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
1499 | ||
1500 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
1501 | Frame pointer elimination is automatically handled. | |
1502 | ||
1503 | For the i386, if frame pointer elimination is being done, we would like to | |
1504 | convert ap into sp, not fp. | |
1505 | ||
1506 | All other eliminations are valid. */ | |
1507 | ||
1508 | #define CAN_ELIMINATE(FROM, TO) \ | |
1509 | ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ | |
1510 | ? ! frame_pointer_needed \ | |
1511 | : 1) | |
1512 | ||
1513 | /* Define the offset between two registers, one to be eliminated, and the other | |
1514 | its replacement, at the start of a routine. */ | |
1515 | ||
1516 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1517 | { \ | |
1518 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ | |
1519 | (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \ | |
1520 | else \ | |
1521 | { \ | |
1522 | int regno; \ | |
1523 | int offset = 0; \ | |
1524 | \ | |
1525 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ | |
1526 | if ((regs_ever_live[regno] && ! call_used_regs[regno]) \ | |
6d8ccdbb JL |
1527 | || ((current_function_uses_pic_offset_table \ |
1528 | || current_function_uses_const_pool) \ | |
1529 | && flag_pic && regno == PIC_OFFSET_TABLE_REGNUM)) \ | |
c98f8742 JVA |
1530 | offset += 4; \ |
1531 | \ | |
1532 | (OFFSET) = offset + get_frame_size (); \ | |
1533 | \ | |
1534 | if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
1535 | (OFFSET) += 4; /* Skip saved PC */ \ | |
1536 | } \ | |
1537 | } | |
1538 | \f | |
1539 | /* Addressing modes, and classification of registers for them. */ | |
1540 | ||
1541 | /* #define HAVE_POST_INCREMENT */ | |
1542 | /* #define HAVE_POST_DECREMENT */ | |
1543 | ||
1544 | /* #define HAVE_PRE_DECREMENT */ | |
1545 | /* #define HAVE_PRE_INCREMENT */ | |
1546 | ||
1547 | /* Macros to check register numbers against specific register classes. */ | |
1548 | ||
1549 | /* These assume that REGNO is a hard or pseudo reg number. | |
1550 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1551 | or a pseudo reg currently allocated to a suitable hard reg. | |
1552 | Since they use reg_renumber, they are safe only once reg_renumber | |
1553 | has been allocated, which happens in local-alloc.c. */ | |
1554 | ||
1555 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1556 | ((REGNO) < STACK_POINTER_REGNUM \ | |
1557 | || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) | |
1558 | ||
1559 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1560 | ((REGNO) <= STACK_POINTER_REGNUM \ | |
1561 | || (REGNO) == ARG_POINTER_REGNUM \ | |
1562 | || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) | |
1563 | ||
1564 | #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) | |
1565 | #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) | |
1566 | ||
1567 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1568 | and check its validity for a certain class. | |
1569 | We have two alternate definitions for each of them. | |
1570 | The usual definition accepts all pseudo regs; the other rejects | |
1571 | them unless they have been allocated suitable hard regs. | |
1572 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1573 | ||
1574 | Most source files want to accept pseudo regs in the hope that | |
1575 | they will get allocated to the class that the insn wants them to be in. | |
1576 | Source files for reload pass need to be strict. | |
1577 | After reload, it makes no difference, since pseudo regs have | |
1578 | been eliminated by then. */ | |
1579 | ||
c98f8742 | 1580 | |
3b3c6a3f MM |
1581 | /* Non strict versions, pseudos are ok */ |
1582 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
1583 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
c98f8742 JVA |
1584 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1585 | ||
3b3c6a3f MM |
1586 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
1587 | (REGNO (X) <= STACK_POINTER_REGNUM \ | |
1588 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
1589 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
c98f8742 | 1590 | |
3b3c6a3f | 1591 | #define REG_OK_FOR_STRREG_NONSTRICT_P(X) \ |
c98f8742 JVA |
1592 | (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1593 | ||
3b3c6a3f MM |
1594 | /* Strict versions, hard registers only */ |
1595 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1596 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1597 | #define REG_OK_FOR_STRREG_STRICT_P(X) \ | |
c98f8742 JVA |
1598 | (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) |
1599 | ||
3b3c6a3f MM |
1600 | #ifndef REG_OK_STRICT |
1601 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
1602 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
1603 | #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X) | |
1604 | ||
1605 | #else | |
1606 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
1607 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
1608 | #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X) | |
c98f8742 JVA |
1609 | #endif |
1610 | ||
1611 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1612 | that is a valid memory address for an instruction. | |
1613 | The MODE argument is the machine mode for the MEM expression | |
1614 | that wants to use this address. | |
1615 | ||
1616 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1617 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1618 | ||
1619 | See legitimize_pic_address in i386.c for details as to what | |
1620 | constitutes a legitimate address when -fpic is used. */ | |
1621 | ||
1622 | #define MAX_REGS_PER_ADDRESS 2 | |
1623 | ||
6eff269e BK |
1624 | #define CONSTANT_ADDRESS_P(X) \ |
1625 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1626 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1627 | || GET_CODE (X) == HIGH) | |
c98f8742 JVA |
1628 | |
1629 | /* Nonzero if the constant value X is a legitimate general operand. | |
1630 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1631 | ||
1632 | #define LEGITIMATE_CONSTANT_P(X) 1 | |
1633 | ||
3b3c6a3f MM |
1634 | #ifdef REG_OK_STRICT |
1635 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1636 | { \ | |
1637 | if (legitimate_address_p (MODE, X, 1)) \ | |
1638 | goto ADDR; \ | |
1639 | } | |
c98f8742 | 1640 | |
3b3c6a3f MM |
1641 | #else |
1642 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
c98f8742 | 1643 | { \ |
3b3c6a3f | 1644 | if (legitimate_address_p (MODE, X, 0)) \ |
c98f8742 | 1645 | goto ADDR; \ |
c98f8742 JVA |
1646 | } |
1647 | ||
3b3c6a3f MM |
1648 | #endif |
1649 | ||
c98f8742 JVA |
1650 | /* Try machine-dependent ways of modifying an illegitimate address |
1651 | to be legitimate. If we find one, return the new, valid address. | |
1652 | This macro is used in only one place: `memory_address' in explow.c. | |
1653 | ||
1654 | OLDX is the address as it was before break_out_memory_refs was called. | |
1655 | In some cases it is useful to look at this to decide what needs to be done. | |
1656 | ||
1657 | MODE and WIN are passed so that this macro can use | |
1658 | GO_IF_LEGITIMATE_ADDRESS. | |
1659 | ||
1660 | It is always safe for this macro to do nothing. It exists to recognize | |
1661 | opportunities to optimize the output. | |
1662 | ||
1663 | For the 80386, we handle X+REG by loading X into a register R and | |
1664 | using R+REG. R will go in a general reg and indexing will be used. | |
1665 | However, if REG is a broken-out memory address or multiplication, | |
1666 | nothing needs to be done because REG can certainly go in a general reg. | |
1667 | ||
1668 | When -fpic is used, special handling is needed for symbolic references. | |
1669 | See comments by legitimize_pic_address in i386.c for details. */ | |
1670 | ||
3b3c6a3f MM |
1671 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1672 | { \ | |
1673 | rtx orig_x = (X); \ | |
1674 | (X) = legitimize_address (X, OLDX, MODE); \ | |
1675 | if (memory_address_p (MODE, X)) \ | |
1676 | goto WIN; \ | |
1677 | } | |
c98f8742 | 1678 | |
d4ba09c0 SC |
1679 | #define REWRITE_ADDRESS(x) rewrite_address(x) |
1680 | ||
c98f8742 JVA |
1681 | /* Nonzero if the constant value X is a legitimate general operand |
1682 | when generating PIC code. It is given that flag_pic is on and | |
1683 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1684 | ||
1685 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
1686 | (! SYMBOLIC_CONST (X) \ | |
1687 | || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))) | |
1688 | ||
1689 | #define SYMBOLIC_CONST(X) \ | |
1690 | (GET_CODE (X) == SYMBOL_REF \ | |
1691 | || GET_CODE (X) == LABEL_REF \ | |
1692 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
1693 | ||
1694 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1695 | has an effect that depends on the machine mode it is used for. | |
1696 | On the 80386, only postdecrement and postincrement address depend thus | |
1697 | (the amount of decrement or increment being the length of the operand). */ | |
1698 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1699 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL | |
1700 | \f | |
1701 | /* Define this macro if references to a symbol must be treated | |
1702 | differently depending on something about the variable or | |
1703 | function named by the symbol (such as what section it is in). | |
1704 | ||
b4ac57ab | 1705 | On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol |
c98f8742 JVA |
1706 | so that we may access it directly in the GOT. */ |
1707 | ||
1708 | #define ENCODE_SECTION_INFO(DECL) \ | |
1709 | do \ | |
1710 | { \ | |
1711 | if (flag_pic) \ | |
1712 | { \ | |
b4ac57ab RS |
1713 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ |
1714 | ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ | |
d4ba09c0 SC |
1715 | \ |
1716 | if (TARGET_DEBUG_ADDR \ | |
1717 | && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ | |
1718 | { \ | |
69d4ca36 | 1719 | fprintf (stderr, "Encode %s, public = %d\n", \ |
d4ba09c0 SC |
1720 | IDENTIFIER_POINTER (DECL_NAME (DECL)), \ |
1721 | TREE_PUBLIC (DECL)); \ | |
1722 | } \ | |
1723 | \ | |
b4ac57ab RS |
1724 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ |
1725 | = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ | |
1726 | || ! TREE_PUBLIC (DECL)); \ | |
c98f8742 JVA |
1727 | } \ |
1728 | } \ | |
1729 | while (0) | |
d398b3b1 JVA |
1730 | |
1731 | /* Initialize data used by insn expanders. This is called from | |
1732 | init_emit, once for each function, before code is generated. | |
1733 | For 386, clear stack slot assignments remembered from previous | |
1734 | functions. */ | |
1735 | ||
1736 | #define INIT_EXPANDERS clear_386_stack_locals () | |
638b724c MM |
1737 | |
1738 | /* The `FINALIZE_PIC' macro serves as a hook to emit these special | |
1739 | codes once the function is being compiled into assembly code, but | |
1740 | not before. (It is not done before, because in the case of | |
1741 | compiling an inline function, it would lead to multiple PIC | |
1742 | prologues being included in functions which used inline functions | |
1743 | and were compiled to assembly language.) */ | |
1744 | ||
1745 | #define FINALIZE_PIC \ | |
1746 | do \ | |
1747 | { \ | |
1748 | extern int current_function_uses_pic_offset_table; \ | |
1749 | \ | |
1750 | current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \ | |
1751 | } \ | |
1752 | while (0) | |
1753 | ||
b08de47e MM |
1754 | \f |
1755 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
1756 | with arguments ARGS is a valid machine specific attribute for DECL. | |
1757 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
1758 | ||
7db4b149 RK |
1759 | #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \ |
1760 | (i386_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS)) | |
b08de47e MM |
1761 | |
1762 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
1763 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
1764 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
1765 | ||
7db4b149 RK |
1766 | #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ |
1767 | (i386_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) | |
b08de47e MM |
1768 | |
1769 | /* If defined, a C expression whose value is zero if the attributes on | |
1770 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
1771 | two if they are nearly compatible (which causes a warning to be | |
1772 | generated). */ | |
1773 | ||
1774 | #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ | |
1775 | (i386_comp_type_attributes (TYPE1, TYPE2)) | |
1776 | ||
1777 | /* If defined, a C statement that assigns default attributes to newly | |
1778 | defined TYPE. */ | |
1779 | ||
1780 | /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */ | |
1781 | ||
1782 | /* Max number of args passed in registers. If this is more than 3, we will | |
1783 | have problems with ebx (register #4), since it is a caller save register and | |
1784 | is also used as the pic register in ELF. So for now, don't allow more than | |
1785 | 3 registers to be passed in registers. */ | |
1786 | ||
1787 | #define REGPARM_MAX 3 | |
1788 | ||
c98f8742 JVA |
1789 | \f |
1790 | /* Specify the machine mode that this machine uses | |
1791 | for the index in the tablejump instruction. */ | |
1792 | #define CASE_VECTOR_MODE Pmode | |
1793 | ||
18543a22 ILT |
1794 | /* Define as C expression which evaluates to nonzero if the tablejump |
1795 | instruction expects the table to contain offsets from the address of the | |
1796 | table. | |
1797 | Do not define this if the table should contain absolute addresses. */ | |
1798 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
c98f8742 JVA |
1799 | |
1800 | /* Specify the tree operation to be used to convert reals to integers. | |
1801 | This should be changed to take advantage of fist --wfs ?? | |
1802 | */ | |
1803 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1804 | ||
1805 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1806 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1807 | ||
1808 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1809 | #define DEFAULT_SIGNED_CHAR 1 | |
1810 | ||
1811 | /* Max number of bytes we can move from memory to memory | |
1812 | in one reasonably fast instruction. */ | |
1813 | #define MOVE_MAX 4 | |
1814 | ||
d4ba09c0 SC |
1815 | /* The number of scalar move insns which should be generated instead |
1816 | of a string move insn or a library call. Increasing the value | |
1817 | will always make code faster, but eventually incurs high cost in | |
1818 | increased code size. | |
c98f8742 | 1819 | |
d4ba09c0 | 1820 | If you don't define this, a reasonable default is used. |
c98f8742 | 1821 | |
d4ba09c0 SC |
1822 | Make this large on i386, since the block move is very inefficient with small |
1823 | blocks, and the hard register needs of the block move require much reload | |
1824 | work. */ | |
1825 | ||
1826 | #define MOVE_RATIO 5 | |
c98f8742 JVA |
1827 | |
1828 | /* Define if shifts truncate the shift count | |
1829 | which implies one can omit a sign-extension or zero-extension | |
1830 | of a shift count. */ | |
241e1a89 | 1831 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
1832 | |
1833 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1834 | ||
1835 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1836 | is done just by pretending it is already truncated. */ | |
1837 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1838 | ||
1839 | /* We assume that the store-condition-codes instructions store 0 for false | |
1840 | and some other value for true. This is the value stored for true. */ | |
1841 | ||
1842 | #define STORE_FLAG_VALUE 1 | |
1843 | ||
1844 | /* When a prototype says `char' or `short', really pass an `int'. | |
1845 | (The 386 can't easily push less than an int.) */ | |
1846 | ||
1847 | #define PROMOTE_PROTOTYPES | |
1848 | ||
1849 | /* Specify the machine mode that pointers have. | |
1850 | After generation of rtl, the compiler makes no further distinction | |
1851 | between pointers and any other objects of this machine mode. */ | |
1852 | #define Pmode SImode | |
1853 | ||
1854 | /* A function address in a call instruction | |
1855 | is a byte address (for indexing purposes) | |
1856 | so give the MEM rtx a byte's mode. */ | |
1857 | #define FUNCTION_MODE QImode | |
d4ba09c0 SC |
1858 | \f |
1859 | /* A part of a C `switch' statement that describes the relative costs | |
1860 | of constant RTL expressions. It must contain `case' labels for | |
1861 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
1862 | and `const_double'. Each case must ultimately reach a `return' | |
1863 | statement to return the relative cost of the use of that kind of | |
1864 | constant value in an expression. The cost may depend on the | |
1865 | precise value of the constant, which is available for examination | |
1866 | in X, and the rtx code of the expression in which it is contained, | |
1867 | found in OUTER_CODE. | |
1868 | ||
1869 | CODE is the expression code--redundant, since it can be obtained | |
1870 | with `GET_CODE (X)'. */ | |
c98f8742 | 1871 | |
3bb22aee | 1872 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
c98f8742 JVA |
1873 | case CONST_INT: \ |
1874 | case CONST: \ | |
1875 | case LABEL_REF: \ | |
1876 | case SYMBOL_REF: \ | |
76565a24 | 1877 | return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1; \ |
d4ba09c0 | 1878 | \ |
c98f8742 JVA |
1879 | case CONST_DOUBLE: \ |
1880 | { \ | |
7488be4e JVA |
1881 | int code; \ |
1882 | if (GET_MODE (RTX) == VOIDmode) \ | |
1883 | return 2; \ | |
d4ba09c0 | 1884 | \ |
7488be4e | 1885 | code = standard_80387_constant_p (RTX); \ |
c98f8742 JVA |
1886 | return code == 1 ? 0 : \ |
1887 | code == 2 ? 1 : \ | |
1888 | 2; \ | |
3bb22aee | 1889 | } |
c98f8742 | 1890 | |
76565a24 SC |
1891 | /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ |
1892 | #define TOPLEVEL_COSTS_N_INSNS(N) {total = COSTS_N_INSNS (N); break;} | |
1893 | ||
d4ba09c0 SC |
1894 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. |
1895 | This can be used, for example, to indicate how costly a multiply | |
1896 | instruction is. In writing this macro, you can use the construct | |
1897 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
1898 | instructions. OUTER_CODE is the code of the expression in which X | |
1899 | is contained. | |
1900 | ||
1901 | This macro is optional; do not define it if the default cost | |
1902 | assumptions are adequate for the target machine. */ | |
1903 | ||
1904 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
1905 | case ASHIFT: \ | |
1906 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1907 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
1908 | { \ | |
1909 | HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
1910 | \ | |
1911 | if (value == 1) \ | |
66050251 SC |
1912 | return COSTS_N_INSNS (ix86_cost->add) \ |
1913 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ | |
d4ba09c0 SC |
1914 | \ |
1915 | if (value == 2 || value == 3) \ | |
66050251 SC |
1916 | return COSTS_N_INSNS (ix86_cost->lea) \ |
1917 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ | |
d4ba09c0 SC |
1918 | } \ |
1919 | /* fall through */ \ | |
1920 | \ | |
1921 | case ROTATE: \ | |
1922 | case ASHIFTRT: \ | |
1923 | case LSHIFTRT: \ | |
1924 | case ROTATERT: \ | |
76565a24 SC |
1925 | if (GET_MODE (XEXP (X, 0)) == DImode) \ |
1926 | { \ | |
1927 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1928 | if (INTVAL (XEXP (X, 1)) > 32) \ | |
1929 | return COSTS_N_INSNS(ix86_cost->shift_const + 2); \ | |
1930 | else \ | |
1931 | return COSTS_N_INSNS(ix86_cost->shift_const * 2); \ | |
1932 | return ((GET_CODE (XEXP (X, 1)) == AND \ | |
1933 | ? COSTS_N_INSNS(ix86_cost->shift_var * 2) \ | |
1934 | : COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2)) \ | |
66050251 | 1935 | + rtx_cost(XEXP (X, 0), OUTER_CODE)); \ |
76565a24 SC |
1936 | } \ |
1937 | return COSTS_N_INSNS (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1938 | ? ix86_cost->shift_const \ | |
1939 | : ix86_cost->shift_var) \ | |
66050251 | 1940 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ |
d4ba09c0 SC |
1941 | \ |
1942 | case MULT: \ | |
1943 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1944 | { \ | |
1945 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
1946 | int nbits = 0; \ | |
1947 | \ | |
76565a24 | 1948 | if (value == 2) \ |
66050251 SC |
1949 | return COSTS_N_INSNS (ix86_cost->add) \ |
1950 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ | |
76565a24 | 1951 | if (value == 4 || value == 8) \ |
66050251 SC |
1952 | return COSTS_N_INSNS (ix86_cost->lea) \ |
1953 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ | |
76565a24 | 1954 | \ |
d4ba09c0 SC |
1955 | while (value != 0) \ |
1956 | { \ | |
1957 | nbits++; \ | |
1958 | value >>= 1; \ | |
1959 | } \ | |
1960 | \ | |
76565a24 SC |
1961 | if (nbits == 1) \ |
1962 | return COSTS_N_INSNS (ix86_cost->shift_const) \ | |
66050251 | 1963 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ |
76565a24 | 1964 | \ |
d4ba09c0 | 1965 | return COSTS_N_INSNS (ix86_cost->mult_init \ |
76565a24 | 1966 | + nbits * ix86_cost->mult_bit) \ |
66050251 | 1967 | + rtx_cost(XEXP (X, 0), OUTER_CODE); \ |
d4ba09c0 SC |
1968 | } \ |
1969 | \ | |
1970 | else /* This is arbitrary */ \ | |
76565a24 SC |
1971 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
1972 | + 7 * ix86_cost->mult_bit); \ | |
d4ba09c0 SC |
1973 | \ |
1974 | case DIV: \ | |
1975 | case UDIV: \ | |
1976 | case MOD: \ | |
1977 | case UMOD: \ | |
76565a24 | 1978 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ |
d4ba09c0 SC |
1979 | \ |
1980 | case PLUS: \ | |
1981 | if (GET_CODE (XEXP (X, 0)) == REG \ | |
1982 | && GET_MODE (XEXP (X, 0)) == SImode \ | |
1983 | && GET_CODE (XEXP (X, 1)) == PLUS) \ | |
1984 | return COSTS_N_INSNS (ix86_cost->lea); \ | |
1985 | \ | |
1986 | /* fall through */ \ | |
1987 | case AND: \ | |
1988 | case IOR: \ | |
1989 | case XOR: \ | |
1990 | case MINUS: \ | |
76565a24 SC |
1991 | if (GET_MODE (X) == DImode) \ |
1992 | return COSTS_N_INSNS (ix86_cost->add) * 2 \ | |
66050251 SC |
1993 | + (rtx_cost (XEXP (X, 0), OUTER_CODE) \ |
1994 | << (GET_MODE (XEXP (X, 0)) != DImode)) \ | |
1995 | + (rtx_cost (XEXP (X, 1), OUTER_CODE) \ | |
1996 | << (GET_MODE (XEXP (X, 1)) != DImode)); \ | |
d4ba09c0 SC |
1997 | case NEG: \ |
1998 | case NOT: \ | |
76565a24 SC |
1999 | if (GET_MODE (X) == DImode) \ |
2000 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2) \ | |
2001 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add) | |
d4ba09c0 SC |
2002 | |
2003 | ||
2004 | /* An expression giving the cost of an addressing mode that contains | |
2005 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
2006 | expression and the `CONST_COSTS' values. | |
2007 | ||
2008 | For most CISC machines, the default cost is a good approximation | |
2009 | of the true cost of the addressing mode. However, on RISC | |
2010 | machines, all instructions normally have the same length and | |
2011 | execution time. Hence all addresses will have equal costs. | |
2012 | ||
2013 | In cases where more than one form of an address is known, the form | |
2014 | with the lowest cost will be used. If multiple forms have the | |
2015 | same, lowest, cost, the one that is the most complex will be used. | |
2016 | ||
2017 | For example, suppose an address that is equal to the sum of a | |
2018 | register and a constant is used twice in the same basic block. | |
2019 | When this macro is not defined, the address will be computed in a | |
2020 | register and memory references will be indirect through that | |
2021 | register. On machines where the cost of the addressing mode | |
2022 | containing the sum is no higher than that of a simple indirect | |
2023 | reference, this will produce an additional instruction and | |
2024 | possibly require an additional register. Proper specification of | |
2025 | this macro eliminates this overhead for such machines. | |
2026 | ||
2027 | Similar use of this macro is made in strength reduction of loops. | |
2028 | ||
2029 | ADDRESS need not be valid as an address. In such a case, the cost | |
2030 | is not relevant and can be any value; invalid addresses need not be | |
2031 | assigned a different cost. | |
2032 | ||
2033 | On machines where an address involving more than one register is as | |
2034 | cheap as an address computation involving only one register, | |
2035 | defining `ADDRESS_COST' to reflect this can cause two registers to | |
2036 | be live over a region of code where only one would have been if | |
2037 | `ADDRESS_COST' were not defined in that manner. This effect should | |
2038 | be considered in the definition of this macro. Equivalent costs | |
2039 | should probably only be given to addresses with different numbers | |
2040 | of registers on machines with lots of registers. | |
2041 | ||
2042 | This macro will normally either not be defined or be defined as a | |
2043 | constant. | |
c98f8742 JVA |
2044 | |
2045 | For i386, it is better to use a complex address than let gcc copy | |
2046 | the address into a reg and make a new pseudo. But not if the address | |
2047 | requires to two regs - that would mean more pseudos with longer | |
2048 | lifetimes. */ | |
2049 | ||
2050 | #define ADDRESS_COST(RTX) \ | |
2051 | ((CONSTANT_P (RTX) \ | |
2052 | || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ | |
2053 | && REG_P (XEXP (RTX, 0)))) ? 0 \ | |
2054 | : REG_P (RTX) ? 1 \ | |
2055 | : 2) | |
d4ba09c0 SC |
2056 | |
2057 | /* A C expression for the cost of moving data of mode M between a | |
2058 | register and memory. A value of 2 is the default; this cost is | |
2059 | relative to those in `REGISTER_MOVE_COST'. | |
2060 | ||
2061 | If moving between registers and memory is more expensive than | |
2062 | between two registers, you should define this macro to express the | |
2063 | relative cost. | |
2064 | ||
2065 | On the i386, copying between floating-point and fixed-point | |
2066 | registers is expensive. */ | |
2067 | ||
2068 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
2069 | (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ | |
2070 | || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \ | |
2071 | : 2) | |
2072 | ||
2073 | ||
2074 | /* A C expression for the cost of moving data of mode M between a | |
2075 | register and memory. A value of 2 is the default; this cost is | |
2076 | relative to those in `REGISTER_MOVE_COST'. | |
2077 | ||
2078 | If moving between registers and memory is more expensive than | |
2079 | between two registers, you should define this macro to express the | |
2080 | relative cost. */ | |
2081 | ||
2082 | /* #define MEMORY_MOVE_COST(M) 2 */ | |
2083 | ||
2084 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2085 | is the default; other values are interpreted relative to that. */ | |
2086 | ||
e2a606cb | 2087 | #define BRANCH_COST i386_branch_cost |
d4ba09c0 SC |
2088 | |
2089 | /* Define this macro as a C expression which is nonzero if accessing | |
2090 | less than a word of memory (i.e. a `char' or a `short') is no | |
2091 | faster than accessing a word of memory, i.e., if such access | |
2092 | require more than one instruction or if there is no difference in | |
2093 | cost between byte and (aligned) word loads. | |
2094 | ||
2095 | When this macro is not defined, the compiler will access a field by | |
2096 | finding the smallest containing object; when it is defined, a | |
2097 | fullword load will be used if alignment permits. Unless bytes | |
2098 | accesses are faster than word accesses, using word accesses is | |
2099 | preferable since it may eliminate subsequent memory access if | |
2100 | subsequent accesses occur to other fields in the same word of the | |
2101 | structure, but to different bytes. */ | |
2102 | ||
2103 | #define SLOW_BYTE_ACCESS 0 | |
2104 | ||
2105 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2106 | #define SLOW_SHORT_ACCESS 0 | |
2107 | ||
2108 | /* Define this macro if zero-extension (of a `char' or `short' to an | |
2109 | `int') can be done faster if the destination is a register that is | |
2110 | known to be zero. | |
2111 | ||
2112 | If you define this macro, you must have instruction patterns that | |
2113 | recognize RTL structures like this: | |
2114 | ||
2115 | (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...) | |
2116 | ||
2117 | and likewise for `HImode'. */ | |
2118 | ||
2119 | /* #define SLOW_ZERO_EXTEND */ | |
2120 | ||
2121 | /* Define this macro to be the value 1 if unaligned accesses have a | |
2122 | cost many times greater than aligned accesses, for example if they | |
2123 | are emulated in a trap handler. | |
2124 | ||
2125 | When this macro is non-zero, the compiler will act as if | |
2126 | `STRICT_ALIGNMENT' were non-zero when generating code for block | |
2127 | moves. This can cause significantly more instructions to be | |
2128 | produced. Therefore, do not set this macro non-zero if unaligned | |
2129 | accesses only add a cycle or two to the time for a memory access. | |
2130 | ||
2131 | If the value of this macro is always zero, it need not be defined. */ | |
2132 | ||
2133 | /* #define SLOW_UNALIGNED_ACCESS 0 */ | |
2134 | ||
2135 | /* Define this macro to inhibit strength reduction of memory | |
2136 | addresses. (On some machines, such strength reduction seems to do | |
2137 | harm rather than good.) */ | |
2138 | ||
2139 | /* #define DONT_REDUCE_ADDR */ | |
2140 | ||
2141 | /* Define this macro if it is as good or better to call a constant | |
2142 | function address than to call an address kept in a register. | |
2143 | ||
2144 | Desirable on the 386 because a CALL with a constant address is | |
2145 | faster than one with a register address. */ | |
2146 | ||
2147 | #define NO_FUNCTION_CSE | |
2148 | ||
2149 | /* Define this macro if it is as good or better for a function to call | |
2150 | itself with an explicit address than to call an address kept in a | |
2151 | register. */ | |
2152 | ||
2153 | #define NO_RECURSIVE_FUNCTION_CSE | |
2154 | ||
2155 | /* A C statement (sans semicolon) to update the integer variable COST | |
2156 | based on the relationship between INSN that is dependent on | |
2157 | DEP_INSN through the dependence LINK. The default is to make no | |
2158 | adjustment to COST. This can be used for example to specify to | |
2159 | the scheduler that an output- or anti-dependence does not incur | |
2160 | the same cost as a data-dependence. */ | |
2161 | ||
2162 | #define ADJUST_COST(insn,link,dep_insn,cost) \ | |
2163 | { \ | |
2164 | rtx next_inst; \ | |
2165 | if (GET_CODE (dep_insn) == CALL_INSN) \ | |
2166 | (cost) = 0; \ | |
2167 | \ | |
2168 | else if (GET_CODE (dep_insn) == INSN \ | |
2169 | && GET_CODE (PATTERN (dep_insn)) == SET \ | |
2170 | && GET_CODE (SET_DEST (PATTERN (dep_insn))) == REG \ | |
2171 | && GET_CODE (insn) == INSN \ | |
2172 | && GET_CODE (PATTERN (insn)) == SET \ | |
2173 | && !reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)), \ | |
2174 | SET_SRC (PATTERN (insn)))) \ | |
2175 | { \ | |
2176 | (cost) = 0; \ | |
2177 | } \ | |
2178 | \ | |
2179 | else if (GET_CODE (insn) == JUMP_INSN) \ | |
2180 | { \ | |
2181 | (cost) = 0; \ | |
2182 | } \ | |
2183 | \ | |
2184 | if (TARGET_PENTIUM) \ | |
2185 | { \ | |
2186 | if (cost !=0 && is_fp_insn (insn) && is_fp_insn (dep_insn) \ | |
2187 | && !is_fp_dest (dep_insn)) \ | |
2188 | { \ | |
2189 | (cost) = 0; \ | |
2190 | } \ | |
2191 | \ | |
2192 | if (agi_dependent (insn, dep_insn)) \ | |
2193 | { \ | |
2194 | (cost) = 3; \ | |
2195 | } \ | |
2196 | else if (GET_CODE (insn) == INSN \ | |
2197 | && GET_CODE (PATTERN (insn)) == SET \ | |
2198 | && SET_DEST (PATTERN (insn)) == cc0_rtx \ | |
2199 | && (next_inst = next_nonnote_insn (insn)) \ | |
2200 | && GET_CODE (next_inst) == JUMP_INSN) \ | |
2201 | { /* compare probably paired with jump */ \ | |
2202 | (cost) = 0; \ | |
2203 | } \ | |
2204 | } \ | |
2205 | else \ | |
2206 | if (!is_fp_dest (dep_insn)) \ | |
2207 | { \ | |
2208 | if(!agi_dependent (insn, dep_insn)) \ | |
2209 | (cost) = 0; \ | |
2210 | else if (TARGET_486) \ | |
2211 | (cost) = 2; \ | |
2212 | } \ | |
2213 | else \ | |
2214 | if (is_fp_store (insn) && is_fp_insn (dep_insn) \ | |
2215 | && NEXT_INSN (insn) && NEXT_INSN (NEXT_INSN (insn)) \ | |
2216 | && NEXT_INSN (NEXT_INSN (NEXT_INSN (insn))) \ | |
2217 | && (GET_CODE (NEXT_INSN (insn)) == INSN) \ | |
2218 | && (GET_CODE (NEXT_INSN (NEXT_INSN (insn))) == JUMP_INSN) \ | |
2219 | && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) == NOTE) \ | |
2220 | && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (insn)))) \ | |
2221 | == NOTE_INSN_LOOP_END)) \ | |
2222 | { \ | |
2223 | (cost) = 3; \ | |
2224 | } \ | |
2225 | } | |
2226 | ||
2227 | ||
2228 | #define ADJUST_BLOCKAGE(last_insn,insn,blockage) \ | |
2229 | { \ | |
2230 | if (is_fp_store (last_insn) && is_fp_insn (insn) \ | |
2231 | && NEXT_INSN (last_insn) && NEXT_INSN (NEXT_INSN (last_insn)) \ | |
2232 | && NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn))) \ | |
2233 | && (GET_CODE (NEXT_INSN (last_insn)) == INSN) \ | |
2234 | && (GET_CODE (NEXT_INSN (NEXT_INSN (last_insn))) == JUMP_INSN) \ | |
2235 | && (GET_CODE (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) == NOTE) \ | |
2236 | && (NOTE_LINE_NUMBER (NEXT_INSN (NEXT_INSN (NEXT_INSN (last_insn)))) \ | |
2237 | == NOTE_INSN_LOOP_END)) \ | |
2238 | { \ | |
2239 | (blockage) = 3; \ | |
2240 | } \ | |
2241 | } | |
2242 | ||
c98f8742 | 2243 | \f |
c572e5ba JVA |
2244 | /* Add any extra modes needed to represent the condition code. |
2245 | ||
2246 | For the i386, we need separate modes when floating-point equality | |
2247 | comparisons are being done. */ | |
2248 | ||
2249 | #define EXTRA_CC_MODES CCFPEQmode | |
2250 | ||
2251 | /* Define the names for the modes specified above. */ | |
2252 | #define EXTRA_CC_NAMES "CCFPEQ" | |
2253 | ||
2254 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2255 | return the mode to be used for the comparison. | |
2256 | ||
2257 | For floating-point equality comparisons, CCFPEQmode should be used. | |
2258 | VOIDmode should be used in all other cases. */ | |
2259 | ||
b565a316 | 2260 | #define SELECT_CC_MODE(OP,X,Y) \ |
c572e5ba | 2261 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ |
4cbb525c | 2262 | && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode) |
c572e5ba JVA |
2263 | |
2264 | /* Define the information needed to generate branch and scc insns. This is | |
2265 | stored from the compare operation. Note that we can't use "rtx" here | |
2266 | since it hasn't been defined! */ | |
2267 | ||
c572e5ba JVA |
2268 | extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); |
2269 | ||
c98f8742 JVA |
2270 | /* Tell final.c how to eliminate redundant test instructions. */ |
2271 | ||
2272 | /* Here we define machine-dependent flags and fields in cc_status | |
2273 | (see `conditions.h'). */ | |
2274 | ||
62acf5fd | 2275 | /* Set if the cc value was actually from the 80387 and |
d4ba09c0 SC |
2276 | we are testing eax directly (i.e. no sahf) */ |
2277 | #define CC_TEST_AX 020000 | |
2278 | ||
c98f8742 JVA |
2279 | /* Set if the cc value is actually in the 80387, so a floating point |
2280 | conditional branch must be output. */ | |
2281 | #define CC_IN_80387 04000 | |
2282 | ||
2283 | /* Set if the CC value was stored in a nonstandard way, so that | |
2284 | the state of equality is indicated by zero in the carry bit. */ | |
2285 | #define CC_Z_IN_NOT_C 010000 | |
2286 | ||
62acf5fd SC |
2287 | /* Set if the CC value was actually from the 80387 and loaded directly |
2288 | into the eflags instead of via eax/sahf. */ | |
2289 | #define CC_FCOMI 040000 | |
2290 | ||
c98f8742 JVA |
2291 | /* Store in cc_status the expressions |
2292 | that the condition codes will describe | |
2293 | after execution of an instruction whose pattern is EXP. | |
2294 | Do not alter them if the instruction would not alter the cc's. */ | |
2295 | ||
2296 | #define NOTICE_UPDATE_CC(EXP, INSN) \ | |
2297 | notice_update_cc((EXP)) | |
2298 | ||
2299 | /* Output a signed jump insn. Use template NORMAL ordinarily, or | |
2300 | FLOAT following a floating point comparison. | |
2301 | Use NO_OV following an arithmetic insn that set the cc's | |
2302 | before a test insn that was deleted. | |
2303 | NO_OV may be zero, meaning final should reinsert the test insn | |
2304 | because the jump cannot be handled properly without it. */ | |
2305 | ||
2306 | #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ | |
2307 | { \ | |
2308 | if (cc_prev_status.flags & CC_IN_80387) \ | |
2309 | return FLOAT; \ | |
2310 | if (cc_prev_status.flags & CC_NO_OVERFLOW) \ | |
2311 | return NO_OV; \ | |
2312 | return NORMAL; \ | |
2313 | } | |
2314 | \f | |
2315 | /* Control the assembler format that we output, to the extent | |
2316 | this does not vary between assemblers. */ | |
2317 | ||
2318 | /* How to refer to registers in assembler output. | |
2319 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2320 | ||
2321 | /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" | |
2322 | For non floating point regs, the following are the HImode names. | |
2323 | ||
2324 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
9e06e321 | 2325 | instead of just "%st". PRINT_REG handles this with the "y" code. */ |
c98f8742 JVA |
2326 | |
2327 | #define HI_REGISTER_NAMES \ | |
2328 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
2329 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" } | |
2330 | ||
2331 | #define REGISTER_NAMES HI_REGISTER_NAMES | |
2332 | ||
2333 | /* Table of additional register names to use in user input. */ | |
2334 | ||
2335 | #define ADDITIONAL_REGISTER_NAMES \ | |
2336 | { "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \ | |
2337 | "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \ | |
2338 | "al", 0, "dl", 1, "cl", 2, "bl", 3, \ | |
2339 | "ah", 0, "dh", 1, "ch", 2, "bh", 3 } | |
2340 | ||
2341 | /* Note we are omitting these since currently I don't know how | |
2342 | to get gcc to use these, since they want the same but different | |
2343 | number as al, and ax. | |
2344 | */ | |
2345 | ||
b4ac57ab | 2346 | /* note the last four are not really qi_registers, but |
c98f8742 JVA |
2347 | the md will have to never output movb into one of them |
2348 | only a movw . There is no movb into the last four regs */ | |
2349 | ||
2350 | #define QI_REGISTER_NAMES \ | |
2351 | {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} | |
2352 | ||
2353 | /* These parallel the array above, and can be used to access bits 8:15 | |
2354 | of regs 0 through 3. */ | |
2355 | ||
2356 | #define QI_HIGH_REGISTER_NAMES \ | |
2357 | {"ah", "dh", "ch", "bh", } | |
2358 | ||
2359 | /* How to renumber registers for dbx and gdb. */ | |
2360 | ||
2361 | /* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */ | |
2362 | #define DBX_REGISTER_NUMBER(n) \ | |
2363 | ((n) == 0 ? 0 : \ | |
2364 | (n) == 1 ? 2 : \ | |
2365 | (n) == 2 ? 1 : \ | |
2366 | (n) == 3 ? 3 : \ | |
2367 | (n) == 4 ? 6 : \ | |
2368 | (n) == 5 ? 7 : \ | |
2369 | (n) == 6 ? 4 : \ | |
2370 | (n) == 7 ? 5 : \ | |
2371 | (n) + 4) | |
2372 | ||
469ac993 JM |
2373 | /* Before the prologue, RA is at 0(%esp). */ |
2374 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2375 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
469ac993 | 2376 | |
e414ab29 RH |
2377 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
2378 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
2379 | ((COUNT) == 0 \ | |
f64cecad JC |
2380 | ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT(-4)))\ |
2381 | : gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, (FRAME), GEN_INT(4)))) | |
e414ab29 | 2382 | |
469ac993 JM |
2383 | /* PC is dbx register 8; let's use that column for RA. */ |
2384 | #define DWARF_FRAME_RETURN_COLUMN 8 | |
2385 | ||
a6ab3aad JM |
2386 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
2387 | #define INCOMING_FRAME_SP_OFFSET 4 | |
2388 | ||
c98f8742 JVA |
2389 | /* This is how to output the definition of a user-level label named NAME, |
2390 | such as the label on a static function or variable NAME. */ | |
2391 | ||
2392 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2393 | (assemble_name (FILE, NAME), fputs (":\n", FILE)) | |
2394 | ||
2395 | /* This is how to output an assembler line defining a `double' constant. */ | |
2396 | ||
0038aea6 JVA |
2397 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
2398 | do { long l[2]; \ | |
2399 | REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ | |
f64cecad | 2400 | fprintf (FILE, "%s 0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \ |
0038aea6 | 2401 | } while (0) |
c98f8742 | 2402 | |
0038aea6 JVA |
2403 | /* This is how to output a `long double' extended real constant. */ |
2404 | ||
2405 | #undef ASM_OUTPUT_LONG_DOUBLE | |
2406 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
2407 | do { long l[3]; \ | |
2408 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ | |
f64cecad | 2409 | fprintf (FILE, "%s 0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \ |
0038aea6 | 2410 | } while (0) |
c98f8742 JVA |
2411 | |
2412 | /* This is how to output an assembler line defining a `float' constant. */ | |
2413 | ||
0038aea6 JVA |
2414 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
2415 | do { long l; \ | |
2416 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
f64cecad | 2417 | fprintf ((FILE), "%s 0x%lx\n", ASM_LONG, l); \ |
c98f8742 JVA |
2418 | } while (0) |
2419 | ||
c98f8742 JVA |
2420 | /* Store in OUTPUT a string (made with alloca) containing |
2421 | an assembler-name for a local static variable named NAME. | |
2422 | LABELNO is an integer which is different for each call. */ | |
2423 | ||
2424 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2425 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2426 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2427 | ||
2428 | ||
2429 | ||
2430 | /* This is how to output an assembler line defining an `int' constant. */ | |
2431 | ||
2432 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
2433 | ( fprintf (FILE, "%s ", ASM_LONG), \ | |
2434 | output_addr_const (FILE,(VALUE)), \ | |
2435 | putc('\n',FILE)) | |
2436 | ||
2437 | /* Likewise for `char' and `short' constants. */ | |
2438 | /* is this supposed to do align too?? */ | |
2439 | ||
2440 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
2441 | ( fprintf (FILE, "%s ", ASM_SHORT), \ | |
2442 | output_addr_const (FILE,(VALUE)), \ | |
2443 | putc('\n',FILE)) | |
2444 | ||
2445 | /* | |
2446 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
2447 | ( fprintf (FILE, "%s ", ASM_BYTE_OP), \ | |
2448 | output_addr_const (FILE,(VALUE)), \ | |
2449 | fputs (",", FILE), \ | |
2450 | output_addr_const (FILE,(VALUE)), \ | |
2451 | fputs (" >> 8\n",FILE)) | |
2452 | */ | |
2453 | ||
2454 | ||
2455 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
2456 | ( fprintf (FILE, "%s ", ASM_BYTE_OP), \ | |
2457 | output_addr_const (FILE, (VALUE)), \ | |
2458 | putc ('\n', FILE)) | |
2459 | ||
2460 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2461 | ||
2462 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
2463 | fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE)) | |
2464 | ||
2465 | /* This is how to output an insn to push a register on the stack. | |
2466 | It need not be very fast code. */ | |
2467 | ||
2468 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
b078c5c6 | 2469 | fprintf (FILE, "\tpushl %%e%s\n", reg_names[REGNO]) |
c98f8742 JVA |
2470 | |
2471 | /* This is how to output an insn to pop a register from the stack. | |
2472 | It need not be very fast code. */ | |
2473 | ||
2474 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
b078c5c6 | 2475 | fprintf (FILE, "\tpopl %%e%s\n", reg_names[REGNO]) |
c98f8742 JVA |
2476 | |
2477 | /* This is how to output an element of a case-vector that is absolute. | |
2478 | */ | |
2479 | ||
2480 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
2481 | fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) | |
2482 | ||
2483 | /* This is how to output an element of a case-vector that is relative. | |
2484 | We don't use these on the 386 yet, because the ATT assembler can't do | |
2485 | forward reference the differences. | |
2486 | */ | |
2487 | ||
2488 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ | |
2489 | fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL) | |
2490 | ||
2491 | /* Define the parentheses used to group arithmetic operations | |
2492 | in assembler code. */ | |
2493 | ||
2494 | #define ASM_OPEN_PAREN "" | |
2495 | #define ASM_CLOSE_PAREN "" | |
2496 | ||
2497 | /* Define results of standard character escape sequences. */ | |
2498 | #define TARGET_BELL 007 | |
2499 | #define TARGET_BS 010 | |
2500 | #define TARGET_TAB 011 | |
2501 | #define TARGET_NEWLINE 012 | |
2502 | #define TARGET_VT 013 | |
2503 | #define TARGET_FF 014 | |
2504 | #define TARGET_CR 015 | |
74b42c8b | 2505 | \f |
c98f8742 JVA |
2506 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2507 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2508 | The CODE z takes the size of operand from the following digit, and | |
2509 | outputs b,w,or l respectively. | |
2510 | ||
2511 | On the 80386, we use several such letters: | |
2512 | f -- float insn (print a CONST_DOUBLE as a float rather than in hex). | |
0038aea6 | 2513 | L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. |
c98f8742 JVA |
2514 | R -- print the prefix for register names. |
2515 | z -- print the opcode suffix for the size of the current operand. | |
2516 | * -- print a star (in certain assembler syntax) | |
2517 | w -- print the operand as if it's a "word" (HImode) even if it isn't. | |
2518 | b -- print the operand as if it's a byte (QImode) even if it isn't. | |
2519 | c -- don't print special prefixes before constant operands. */ | |
2520 | ||
2521 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
2522 | ((CODE) == '*') | |
2523 | ||
74b42c8b RS |
2524 | /* Print the name of a register based on its machine mode and number. |
2525 | If CODE is 'w', pretend the mode is HImode. | |
2526 | If CODE is 'b', pretend the mode is QImode. | |
2527 | If CODE is 'k', pretend the mode is SImode. | |
2528 | If CODE is 'h', pretend the reg is the `high' byte register. | |
2529 | If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ | |
2530 | ||
aa3e8d2a JVA |
2531 | extern char *hi_reg_name[]; |
2532 | extern char *qi_reg_name[]; | |
2533 | extern char *qi_high_reg_name[]; | |
2534 | ||
74b42c8b | 2535 | #define PRINT_REG(X, CODE, FILE) \ |
aa3e8d2a JVA |
2536 | do { if (REGNO (X) == ARG_POINTER_REGNUM) \ |
2537 | abort (); \ | |
74b42c8b RS |
2538 | fprintf (FILE, "%s", RP); \ |
2539 | switch ((CODE == 'w' ? 2 \ | |
2540 | : CODE == 'b' ? 1 \ | |
2541 | : CODE == 'k' ? 4 \ | |
2542 | : CODE == 'y' ? 3 \ | |
2543 | : CODE == 'h' ? 0 \ | |
2544 | : GET_MODE_SIZE (GET_MODE (X)))) \ | |
2545 | { \ | |
2546 | case 3: \ | |
2547 | if (STACK_TOP_P (X)) \ | |
aa3e8d2a JVA |
2548 | { \ |
2549 | fputs ("st(0)", FILE); \ | |
2550 | break; \ | |
2551 | } \ | |
2552 | case 4: \ | |
2553 | case 8: \ | |
0038aea6 | 2554 | case 12: \ |
9e06e321 | 2555 | if (! FP_REG_P (X)) fputs ("e", FILE); \ |
74b42c8b RS |
2556 | case 2: \ |
2557 | fputs (hi_reg_name[REGNO (X)], FILE); \ | |
2558 | break; \ | |
2559 | case 1: \ | |
2560 | fputs (qi_reg_name[REGNO (X)], FILE); \ | |
2561 | break; \ | |
2562 | case 0: \ | |
2563 | fputs (qi_high_reg_name[REGNO (X)], FILE); \ | |
2564 | break; \ | |
2565 | } \ | |
2566 | } while (0) | |
2567 | ||
c98f8742 JVA |
2568 | #define PRINT_OPERAND(FILE, X, CODE) \ |
2569 | print_operand (FILE, X, CODE) | |
c98f8742 JVA |
2570 | |
2571 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2572 | print_operand_address (FILE, ADDR) | |
2573 | ||
aa3e8d2a JVA |
2574 | /* Print the name of a register for based on its machine mode and number. |
2575 | This macro is used to print debugging output. | |
2576 | This macro is different from PRINT_REG in that it may be used in | |
2577 | programs that are not linked with aux-output.o. */ | |
2578 | ||
2579 | #define DEBUG_PRINT_REG(X, CODE, FILE) \ | |
2580 | do { static char *hi_name[] = HI_REGISTER_NAMES; \ | |
2581 | static char *qi_name[] = QI_REGISTER_NAMES; \ | |
7488be4e | 2582 | fprintf (FILE, "%d %s", REGNO (X), RP); \ |
aa3e8d2a JVA |
2583 | if (REGNO (X) == ARG_POINTER_REGNUM) \ |
2584 | { fputs ("argp", FILE); break; } \ | |
2585 | if (STACK_TOP_P (X)) \ | |
2586 | { fputs ("st(0)", FILE); break; } \ | |
b0ceea8c RK |
2587 | if (FP_REG_P (X)) \ |
2588 | { fputs (hi_name[REGNO(X)], FILE); break; } \ | |
aa3e8d2a JVA |
2589 | switch (GET_MODE_SIZE (GET_MODE (X))) \ |
2590 | { \ | |
b0ceea8c RK |
2591 | default: \ |
2592 | fputs ("e", FILE); \ | |
aa3e8d2a JVA |
2593 | case 2: \ |
2594 | fputs (hi_name[REGNO (X)], FILE); \ | |
2595 | break; \ | |
2596 | case 1: \ | |
2597 | fputs (qi_name[REGNO (X)], FILE); \ | |
2598 | break; \ | |
2599 | } \ | |
2600 | } while (0) | |
2601 | ||
c98f8742 JVA |
2602 | /* Output the prefix for an immediate operand, or for an offset operand. */ |
2603 | #define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE)) | |
2604 | #define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE)) | |
2605 | ||
2606 | /* Routines in libgcc that return floats must return them in an fp reg, | |
2607 | just as other functions do which return such values. | |
2608 | These macros make that happen. */ | |
2609 | ||
2610 | #define FLOAT_VALUE_TYPE float | |
2611 | #define INTIFY(FLOATVAL) FLOATVAL | |
2612 | ||
2613 | /* Nonzero if INSN magically clobbers register REGNO. */ | |
2614 | ||
2615 | /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \ | |
2616 | (FP_REGNO_P (REGNO) \ | |
2617 | && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER)) | |
2618 | */ | |
2619 | ||
2620 | /* a letter which is not needed by the normal asm syntax, which | |
2621 | we can use for operand syntax in the extended asm */ | |
2622 | ||
2623 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 2624 | #define RET return "" |
f64cecad | 2625 | #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx)) |
d4ba09c0 SC |
2626 | \f |
2627 | /* Helper macros to expand a binary/unary operator if needed */ | |
2628 | #define IX86_EXPAND_BINARY_OPERATOR(OP, MODE, OPERANDS) \ | |
2629 | do { \ | |
2630 | if (!ix86_expand_binary_operator (OP, MODE, OPERANDS)) \ | |
2631 | FAIL; \ | |
2632 | } while (0) | |
2633 | ||
2634 | #define IX86_EXPAND_UNARY_OPERATOR(OP, MODE, OPERANDS) \ | |
2635 | do { \ | |
2636 | if (!ix86_expand_unary_operator (OP, MODE, OPERANDS,)) \ | |
2637 | FAIL; \ | |
2638 | } while (0) | |
2639 | ||
c98f8742 | 2640 | \f |
3b3c6a3f | 2641 | /* Functions in i386.c */ |
f5316dfe MM |
2642 | extern void override_options (); |
2643 | extern void order_regs_for_local_alloc (); | |
d4ba09c0 | 2644 | extern char *output_strlen_unroll (); |
5bc7cd8e SC |
2645 | extern struct rtx_def *i386_sext16_if_const (); |
2646 | extern int i386_aligned_p (); | |
2647 | extern int i386_cc_probably_useless_p (); | |
b08de47e MM |
2648 | extern int i386_valid_decl_attribute_p (); |
2649 | extern int i386_valid_type_attribute_p (); | |
2650 | extern int i386_return_pops_args (); | |
2651 | extern int i386_comp_type_attributes (); | |
2652 | extern void init_cumulative_args (); | |
2653 | extern void function_arg_advance (); | |
2654 | extern struct rtx_def *function_arg (); | |
2655 | extern int function_arg_partial_nregs (); | |
f7746310 | 2656 | extern char *output_strlen_unroll (); |
3b3c6a3f MM |
2657 | extern void output_op_from_reg (); |
2658 | extern void output_to_reg (); | |
2659 | extern char *singlemove_string (); | |
2660 | extern char *output_move_double (); | |
b840bfb0 MM |
2661 | extern char *output_move_memory (); |
2662 | extern char *output_move_pushmem (); | |
3b3c6a3f MM |
2663 | extern int standard_80387_constant_p (); |
2664 | extern char *output_move_const_single (); | |
2665 | extern int symbolic_operand (); | |
2666 | extern int call_insn_operand (); | |
2667 | extern int expander_call_insn_operand (); | |
2668 | extern int symbolic_reference_mentioned_p (); | |
d4ba09c0 SC |
2669 | extern int ix86_expand_binary_operator (); |
2670 | extern int ix86_binary_operator_ok (); | |
2671 | extern int ix86_expand_unary_operator (); | |
2672 | extern int ix86_unary_operator_ok (); | |
3b3c6a3f MM |
2673 | extern void emit_pic_move (); |
2674 | extern void function_prologue (); | |
2675 | extern int simple_386_epilogue (); | |
2676 | extern void function_epilogue (); | |
2677 | extern int legitimate_address_p (); | |
2678 | extern struct rtx_def *legitimize_pic_address (); | |
2679 | extern struct rtx_def *legitimize_address (); | |
2680 | extern void print_operand (); | |
2681 | extern void print_operand_address (); | |
2682 | extern void notice_update_cc (); | |
2683 | extern void split_di (); | |
2684 | extern int binary_387_op (); | |
2685 | extern int shift_op (); | |
2686 | extern int VOIDmode_compare_op (); | |
2687 | extern char *output_387_binary_op (); | |
2688 | extern char *output_fix_trunc (); | |
2689 | extern char *output_float_compare (); | |
2690 | extern char *output_fp_cc0_set (); | |
2691 | extern void save_386_machine_status (); | |
2692 | extern void restore_386_machine_status (); | |
2693 | extern void clear_386_stack_locals (); | |
2694 | extern struct rtx_def *assign_386_stack_local (); | |
d4ba09c0 SC |
2695 | extern int is_mul (); |
2696 | extern int is_div (); | |
2697 | extern int last_to_set_cc (); | |
2698 | extern int doesnt_set_condition_code (); | |
2699 | extern int sets_condition_code (); | |
2700 | extern int str_immediate_operand (); | |
2701 | extern int is_fp_insn (); | |
2702 | extern int is_fp_dest (); | |
2703 | extern int is_fp_store (); | |
2704 | extern int agi_dependent (); | |
2705 | extern int reg_mentioned_in_mem (); | |
2706 | ||
2707 | #ifdef NOTYET | |
2708 | extern struct rtx_def *copy_all_rtx (); | |
2709 | extern void rewrite_address (); | |
2710 | #endif | |
3b3c6a3f | 2711 | |
f5316dfe | 2712 | /* Variables in i386.c */ |
241e1a89 | 2713 | extern char *ix86_cpu_string; /* for -mcpu=<xxx> */ |
bcd86433 | 2714 | extern char *ix86_arch_string; /* for -march=<xxx> */ |
f5316dfe | 2715 | extern char *i386_reg_alloc_order; /* register allocation order */ |
b08de47e MM |
2716 | extern char *i386_regparm_string; /* # registers to use to pass args */ |
2717 | extern char *i386_align_loops_string; /* power of two alignment for loops */ | |
2718 | extern char *i386_align_jumps_string; /* power of two alignment for non-loop jumps */ | |
2719 | extern char *i386_align_funcs_string; /* power of two alignment for functions */ | |
e2a606cb | 2720 | extern char *i386_branch_cost_string; /* values 1-5: see jump.c */ |
b08de47e MM |
2721 | extern int i386_regparm; /* i386_regparm_string as a number */ |
2722 | extern int i386_align_loops; /* power of two alignment for loops */ | |
2723 | extern int i386_align_jumps; /* power of two alignment for non-loop jumps */ | |
2724 | extern int i386_align_funcs; /* power of two alignment for functions */ | |
e2a606cb | 2725 | extern int i386_branch_cost; /* values 1-5: see jump.c */ |
f5316dfe MM |
2726 | extern char *hi_reg_name[]; /* names for 16 bit regs */ |
2727 | extern char *qi_reg_name[]; /* names for 8 bit regs (low) */ | |
2728 | extern char *qi_high_reg_name[]; /* names for 8 bit regs (high) */ | |
2729 | extern enum reg_class regclass_map[]; /* smalled class containing REGNO */ | |
2730 | extern struct rtx_def *i386_compare_op0; /* operand 0 for comparisons */ | |
2731 | extern struct rtx_def *i386_compare_op1; /* operand 1 for comparisons */ | |
2732 | ||
3b3c6a3f | 2733 | /* External variables used */ |
d4ba09c0 SC |
2734 | extern int optimize; /* optimization level */ |
2735 | extern int obey_regdecls; /* TRUE if stupid register allocation */ | |
3b3c6a3f MM |
2736 | |
2737 | /* External functions used */ | |
2738 | extern struct rtx_def *force_operand (); | |
d4ba09c0 | 2739 | |
3b3c6a3f | 2740 | \f |
c98f8742 JVA |
2741 | /* |
2742 | Local variables: | |
2743 | version-control: t | |
2744 | End: | |
2745 | */ |