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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
2f83c7d6 NC |
3 | 2001, 2002, 2003, 2004, 2005, 2006, 2007 |
4 | Free Software Foundation, Inc. | |
c98f8742 | 5 | |
188fc5b5 | 6 | This file is part of GCC. |
c98f8742 | 7 | |
188fc5b5 | 8 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
11 | any later version. |
12 | ||
188fc5b5 | 13 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c98f8742 | 21 | |
ccf8e764 RH |
22 | /* The purpose of this file is to define the characteristics of the i386, |
23 | independent of assembler syntax or operating system. | |
24 | ||
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
36 | ||
0a1c5e55 UB |
37 | /* Redefines for option macros. */ |
38 | ||
39 | #define TARGET_64BIT OPTION_ISA_64BIT | |
40 | #define TARGET_MMX OPTION_ISA_MMX | |
41 | #define TARGET_3DNOW OPTION_ISA_3DNOW | |
42 | #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A | |
43 | #define TARGET_SSE OPTION_ISA_SSE | |
44 | #define TARGET_SSE2 OPTION_ISA_SSE2 | |
45 | #define TARGET_SSE3 OPTION_ISA_SSE3 | |
46 | #define TARGET_SSSE3 OPTION_ISA_SSSE3 | |
47 | #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 | |
3b8dd071 | 48 | #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 |
0a1c5e55 | 49 | #define TARGET_SSE4A OPTION_ISA_SSE4A |
04e1d06b MM |
50 | #define TARGET_SSE5 OPTION_ISA_SSE5 |
51 | #define TARGET_ROUND OPTION_ISA_ROUND | |
52 | ||
53 | /* SSE5 and SSE4.1 define the same round instructions */ | |
54 | #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5) | |
55 | #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) | |
0a1c5e55 | 56 | |
26b5109f RS |
57 | #include "config/vxworks-dummy.h" |
58 | ||
8c996513 JH |
59 | /* Algorithm to expand string function with. */ |
60 | enum stringop_alg | |
61 | { | |
62 | no_stringop, | |
63 | libcall, | |
64 | rep_prefix_1_byte, | |
65 | rep_prefix_4_byte, | |
66 | rep_prefix_8_byte, | |
67 | loop_1_byte, | |
68 | loop, | |
69 | unrolled_loop | |
70 | }; | |
ccf8e764 | 71 | |
8c996513 | 72 | #define NAX_STRINGOP_ALGS 4 |
ccf8e764 | 73 | |
8c996513 JH |
74 | /* Specify what algorithm to use for stringops on known size. |
75 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
76 | known at compile time or estimated via feedback, the SIZE array | |
77 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 78 | means infinity). Corresponding ALG is used then. |
8c996513 | 79 | For example initializer: |
4f3f76e6 | 80 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 81 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 82 | be used otherwise. */ |
8c996513 JH |
83 | struct stringop_algs |
84 | { | |
85 | const enum stringop_alg unknown_size; | |
86 | const struct stringop_strategy { | |
87 | const int max; | |
88 | const enum stringop_alg alg; | |
89 | } size [NAX_STRINGOP_ALGS]; | |
90 | }; | |
91 | ||
d4ba09c0 SC |
92 | /* Define the specific costs for a given cpu */ |
93 | ||
94 | struct processor_costs { | |
8b60264b KG |
95 | const int add; /* cost of an add instruction */ |
96 | const int lea; /* cost of a lea instruction */ | |
97 | const int shift_var; /* variable shift costs */ | |
98 | const int shift_const; /* constant shift costs */ | |
f676971a | 99 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 100 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 101 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 102 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 103 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
104 | int movsx; /* The cost of movsx operation. */ |
105 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
106 | const int large_insn; /* insns larger than this cost more */ |
107 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 108 | memory-to-memory move insns. */ |
8b60264b KG |
109 | const int movzbl_load; /* cost of loading using movzbl */ |
110 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
111 | in QImode, HImode and SImode relative |
112 | to reg-reg move (2). */ | |
8b60264b | 113 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 114 | in QImode, HImode and SImode */ |
8b60264b KG |
115 | const int fp_move; /* cost of reg,reg fld/fst */ |
116 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 117 | in SFmode, DFmode and XFmode */ |
8b60264b | 118 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 119 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
120 | const int mmx_move; /* cost of moving MMX register. */ |
121 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 122 | in SImode and DImode */ |
8b60264b | 123 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 124 | in SImode and DImode */ |
8b60264b KG |
125 | const int sse_move; /* cost of moving SSE register. */ |
126 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 127 | in SImode, DImode and TImode*/ |
8b60264b | 128 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 129 | in SImode, DImode and TImode*/ |
8b60264b | 130 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 131 | integer and vice versa. */ |
46cb0441 ZD |
132 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
133 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
134 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
135 | const int simultaneous_prefetches; /* number of parallel prefetch | |
136 | operations. */ | |
4977bab6 | 137 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
138 | const int fadd; /* cost of FADD and FSUB instructions. */ |
139 | const int fmul; /* cost of FMUL instruction. */ | |
140 | const int fdiv; /* cost of FDIV instruction. */ | |
141 | const int fabs; /* cost of FABS instruction. */ | |
142 | const int fchs; /* cost of FCHS instruction. */ | |
143 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 JH |
144 | /* Specify what algorithm |
145 | to use for stringops on unknown size. */ | |
146 | struct stringop_algs memcpy[2], memset[2]; | |
e70444a8 HJ |
147 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
148 | load and store. */ | |
149 | const int scalar_load_cost; /* Cost of scalar load. */ | |
150 | const int scalar_store_cost; /* Cost of scalar store. */ | |
151 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
152 | load, store, vector-to-scalar and | |
153 | scalar-to-vector operation. */ | |
154 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
155 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 156 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
157 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
158 | const int vec_store_cost; /* Cost of vector store. */ | |
159 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
160 | cost model. */ | |
161 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
162 | vectorizer cost model. */ | |
d4ba09c0 SC |
163 | }; |
164 | ||
8b60264b | 165 | extern const struct processor_costs *ix86_cost; |
d4ba09c0 | 166 | |
c98f8742 JVA |
167 | /* Macros used in the machine description to test the flags. */ |
168 | ||
ddd5a7c1 | 169 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 170 | |
35b528be | 171 | #ifndef TARGET_CPU_DEFAULT |
d326eaf0 | 172 | #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic |
10e9fecc | 173 | #endif |
35b528be | 174 | |
004d3859 GK |
175 | #ifndef TARGET_FPMATH_DEFAULT |
176 | #define TARGET_FPMATH_DEFAULT \ | |
177 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
178 | #endif | |
179 | ||
6ac49599 | 180 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
b08de47e | 181 | |
5791cc29 JT |
182 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
183 | compile-time constant. */ | |
184 | #ifdef IN_LIBGCC2 | |
6ac49599 | 185 | #undef TARGET_64BIT |
5791cc29 JT |
186 | #ifdef __x86_64__ |
187 | #define TARGET_64BIT 1 | |
188 | #else | |
189 | #define TARGET_64BIT 0 | |
190 | #endif | |
191 | #else | |
6ac49599 RS |
192 | #ifndef TARGET_BI_ARCH |
193 | #undef TARGET_64BIT | |
67adf6a9 | 194 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
195 | #define TARGET_64BIT 1 |
196 | #else | |
197 | #define TARGET_64BIT 0 | |
198 | #endif | |
199 | #endif | |
5791cc29 | 200 | #endif |
25f94bb5 | 201 | |
750054a2 CT |
202 | #define HAS_LONG_COND_BRANCH 1 |
203 | #define HAS_LONG_UNCOND_BRANCH 1 | |
204 | ||
9e555526 RH |
205 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
206 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
207 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
208 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 209 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
210 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
211 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
212 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
213 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 214 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 215 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
05f85dbb | 216 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d326eaf0 JH |
217 | #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) |
218 | #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
219 | #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
21efb4d4 | 220 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
a269a03c | 221 | |
80fd744f RH |
222 | /* Feature tests against the various tunings. */ |
223 | enum ix86_tune_indices { | |
224 | X86_TUNE_USE_LEAVE, | |
225 | X86_TUNE_PUSH_MEMORY, | |
226 | X86_TUNE_ZERO_EXTEND_WITH_AND, | |
227 | X86_TUNE_USE_BIT_TEST, | |
228 | X86_TUNE_UNROLL_STRLEN, | |
229 | X86_TUNE_DEEP_BRANCH_PREDICTION, | |
230 | X86_TUNE_BRANCH_PREDICTION_HINTS, | |
231 | X86_TUNE_DOUBLE_WITH_ADD, | |
3c2d980c | 232 | X86_TUNE_USE_SAHF, |
80fd744f RH |
233 | X86_TUNE_MOVX, |
234 | X86_TUNE_PARTIAL_REG_STALL, | |
235 | X86_TUNE_PARTIAL_FLAG_REG_STALL, | |
236 | X86_TUNE_USE_HIMODE_FIOP, | |
237 | X86_TUNE_USE_SIMODE_FIOP, | |
238 | X86_TUNE_USE_MOV0, | |
239 | X86_TUNE_USE_CLTD, | |
240 | X86_TUNE_USE_XCHGB, | |
241 | X86_TUNE_SPLIT_LONG_MOVES, | |
242 | X86_TUNE_READ_MODIFY_WRITE, | |
243 | X86_TUNE_READ_MODIFY, | |
244 | X86_TUNE_PROMOTE_QIMODE, | |
245 | X86_TUNE_FAST_PREFIX, | |
246 | X86_TUNE_SINGLE_STRINGOP, | |
247 | X86_TUNE_QIMODE_MATH, | |
248 | X86_TUNE_HIMODE_MATH, | |
249 | X86_TUNE_PROMOTE_QI_REGS, | |
250 | X86_TUNE_PROMOTE_HI_REGS, | |
251 | X86_TUNE_ADD_ESP_4, | |
252 | X86_TUNE_ADD_ESP_8, | |
253 | X86_TUNE_SUB_ESP_4, | |
254 | X86_TUNE_SUB_ESP_8, | |
255 | X86_TUNE_INTEGER_DFMODE_MOVES, | |
256 | X86_TUNE_PARTIAL_REG_DEPENDENCY, | |
257 | X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, | |
258 | X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, | |
259 | X86_TUNE_SSE_SPLIT_REGS, | |
260 | X86_TUNE_SSE_TYPELESS_STORES, | |
261 | X86_TUNE_SSE_LOAD0_BY_PXOR, | |
262 | X86_TUNE_MEMORY_MISMATCH_STALL, | |
263 | X86_TUNE_PROLOGUE_USING_MOVE, | |
264 | X86_TUNE_EPILOGUE_USING_MOVE, | |
265 | X86_TUNE_SHIFT1, | |
266 | X86_TUNE_USE_FFREEP, | |
267 | X86_TUNE_INTER_UNIT_MOVES, | |
630ecd8d | 268 | X86_TUNE_INTER_UNIT_CONVERSIONS, |
80fd744f RH |
269 | X86_TUNE_FOUR_JUMP_LIMIT, |
270 | X86_TUNE_SCHEDULE, | |
271 | X86_TUNE_USE_BT, | |
272 | X86_TUNE_USE_INCDEC, | |
273 | X86_TUNE_PAD_RETURNS, | |
274 | X86_TUNE_EXT_80387_CONSTANTS, | |
ddff69b9 MM |
275 | X86_TUNE_SHORTEN_X87_SSE, |
276 | X86_TUNE_AVOID_VECTOR_DECODE, | |
a646aded | 277 | X86_TUNE_PROMOTE_HIMODE_IMUL, |
ddff69b9 MM |
278 | X86_TUNE_SLOW_IMUL_IMM32_MEM, |
279 | X86_TUNE_SLOW_IMUL_IMM8, | |
280 | X86_TUNE_MOVE_M1_VIA_OR, | |
281 | X86_TUNE_NOT_UNPAIRABLE, | |
282 | X86_TUNE_NOT_VECTORMODE, | |
4e9d897d | 283 | X86_TUNE_USE_VECTOR_CONVERTS, |
80fd744f RH |
284 | |
285 | X86_TUNE_LAST | |
286 | }; | |
287 | ||
288 | extern unsigned int ix86_tune_features[X86_TUNE_LAST]; | |
289 | ||
290 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
291 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
292 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
293 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
294 | #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST] | |
295 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] | |
296 | #define TARGET_DEEP_BRANCH_PREDICTION \ | |
297 | ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] | |
298 | #define TARGET_BRANCH_PREDICTION_HINTS \ | |
299 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
300 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
301 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
302 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
303 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
304 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
305 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
306 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] | |
307 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
308 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
309 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
310 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
311 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
312 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
313 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
314 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
315 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
316 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
317 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] | |
318 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
319 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
320 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
321 | #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] | |
322 | #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] | |
323 | #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] | |
324 | #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] | |
325 | #define TARGET_INTEGER_DFMODE_MOVES \ | |
326 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
327 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
328 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
329 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
330 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
331 | #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ | |
332 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] | |
333 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] | |
334 | #define TARGET_SSE_TYPELESS_STORES \ | |
335 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
336 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
337 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
338 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
339 | #define TARGET_PROLOGUE_USING_MOVE \ | |
340 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
341 | #define TARGET_EPILOGUE_USING_MOVE \ | |
342 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
343 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
344 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
345 | #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] | |
630ecd8d JH |
346 | #define TARGET_INTER_UNIT_CONVERSIONS\ |
347 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] | |
80fd744f RH |
348 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
349 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
350 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
351 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
352 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
353 | #define TARGET_EXT_80387_CONSTANTS \ | |
354 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
355 | #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] |
356 | #define TARGET_AVOID_VECTOR_DECODE \ | |
357 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
358 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
359 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
360 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
361 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
362 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
363 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
364 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
365 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
4e9d897d | 366 | #define TARGET_USE_VECTOR_CONVERTS ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] |
80fd744f RH |
367 | |
368 | /* Feature tests against the various architecture variations. */ | |
369 | enum ix86_arch_indices { | |
370 | X86_ARCH_CMOVE, /* || TARGET_SSE */ | |
371 | X86_ARCH_CMPXCHG, | |
372 | X86_ARCH_CMPXCHG8B, | |
373 | X86_ARCH_XADD, | |
374 | X86_ARCH_BSWAP, | |
375 | ||
376 | X86_ARCH_LAST | |
377 | }; | |
4f3f76e6 | 378 | |
80fd744f RH |
379 | extern unsigned int ix86_arch_features[X86_ARCH_LAST]; |
380 | ||
381 | #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] | |
382 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] | |
383 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
384 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
385 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
386 | ||
387 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) | |
388 | ||
389 | extern int x86_prefetch_sse; | |
0a1c5e55 UB |
390 | |
391 | #define TARGET_ABM x86_abm | |
392 | #define TARGET_CMPXCHG16B x86_cmpxchg16b | |
393 | #define TARGET_POPCNT x86_popcnt | |
80fd744f | 394 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
0a1c5e55 | 395 | #define TARGET_SAHF x86_sahf |
6b889d89 | 396 | #define TARGET_RECIP x86_recip |
04e1d06b | 397 | #define TARGET_FUSED_MADD x86_fused_muladd |
8b96a312 L |
398 | #define TARGET_AES (TARGET_SSE2 && x86_aes) |
399 | #define TARGET_PCLMUL (TARGET_SSE2 && x86_pclmul) | |
80fd744f | 400 | |
80fd744f RH |
401 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
402 | ||
403 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
404 | #define TARGET_MIX_SSE_I387 \ | |
405 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
406 | ||
407 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
408 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
409 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
410 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
1ef45b77 | 411 | |
0a1c5e55 UB |
412 | extern int ix86_isa_flags; |
413 | ||
67adf6a9 RH |
414 | #ifndef TARGET_64BIT_DEFAULT |
415 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 416 | #endif |
74dc3e94 RH |
417 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
418 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
419 | #endif | |
25f94bb5 | 420 | |
79f5e442 ZD |
421 | /* Fence to use after loop using storent. */ |
422 | ||
423 | extern tree x86_mfence; | |
424 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
425 | ||
0ed4a390 JL |
426 | /* Once GDB has been enhanced to deal with functions without frame |
427 | pointers, we can change this to allow for elimination of | |
428 | the frame pointer in leaf functions. */ | |
429 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 430 | |
0a1c5e55 UB |
431 | /* Extra bits to force. */ |
432 | #define TARGET_SUBTARGET_DEFAULT 0 | |
433 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
434 | ||
435 | /* Extra bits to force on w/ 32-bit mode. */ | |
436 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
437 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
438 | ||
ccf8e764 RH |
439 | /* Extra bits to force on w/ 64-bit mode. */ |
440 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 441 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 442 | |
b069de3b SS |
443 | /* This is not really a target flag, but is done this way so that |
444 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
445 | redefines this to 1. */ | |
446 | #define TARGET_MACHO 0 | |
447 | ||
ccf8e764 | 448 | /* Likewise, for the Windows 64-bit ABI. */ |
d29899ba | 449 | #define TARGET_64BIT_MS_ABI 0 |
ccf8e764 | 450 | |
cc69336f RH |
451 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
452 | with the rounding mode forced to 53 bits. */ | |
453 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
454 | ||
f5316dfe MM |
455 | /* Sometimes certain combinations of command options do not make |
456 | sense on a particular target machine. You can define a macro | |
457 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
458 | defined, is executed once just after all the command options have | |
459 | been parsed. | |
460 | ||
461 | Don't use this macro to turn on various extra optimizations for | |
462 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
463 | ||
464 | #define OVERRIDE_OPTIONS override_options () | |
465 | ||
d4ba09c0 | 466 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
467 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
468 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 469 | |
682cd442 GK |
470 | /* -march=native handling only makes sense with compiler running on |
471 | an x86 or x86_64 chip. If changing this condition, also change | |
472 | the condition in driver-i386.c. */ | |
473 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
474 | /* In driver-i386.c. */ |
475 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
476 | #define EXTRA_SPEC_FUNCTIONS \ | |
477 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 478 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
479 | #endif |
480 | ||
1cba2b96 EC |
481 | /* Support for configure-time defaults of some command line options. |
482 | The order here is important so that -march doesn't squash the | |
483 | tune or cpu values. */ | |
ce998900 | 484 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 485 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
ce998900 | 486 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
1cba2b96 | 487 | {"arch", "%{!march=*:-march=%(VALUE)}"} |
7816bea0 | 488 | |
241e1a89 SC |
489 | /* Specs for the compiler proper */ |
490 | ||
628714d8 | 491 | #ifndef CC1_CPU_SPEC |
fa959ce4 | 492 | #define CC1_CPU_SPEC_1 "\ |
9d913bbf | 493 | %{mcpu=*:-mtune=%* \ |
d347d4c7 | 494 | %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ |
9d913bbf | 495 | %<mcpu=* \ |
c93e80a5 JH |
496 | %{mintel-syntax:-masm=intel \ |
497 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
498 | %{mno-intel-syntax:-masm=att \ | |
499 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
fa959ce4 | 500 | |
682cd442 | 501 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
502 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
503 | #else | |
504 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
edccdcb1 L |
505 | "%{march=native:%<march=native %:local_cpu_detect(arch) \ |
506 | %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ | |
fa959ce4 MM |
507 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" |
508 | #endif | |
241e1a89 | 509 | #endif |
c98f8742 | 510 | \f |
30efe578 | 511 | /* Target CPU builtins. */ |
1ba7b414 NB |
512 | #define TARGET_CPU_CPP_BUILTINS() \ |
513 | do \ | |
514 | { \ | |
515 | size_t arch_len = strlen (ix86_arch_string); \ | |
9e555526 | 516 | size_t tune_len = strlen (ix86_tune_string); \ |
1ba7b414 | 517 | int last_arch_char = ix86_arch_string[arch_len - 1]; \ |
7706ca5d | 518 | int last_tune_char = ix86_tune_string[tune_len - 1]; \ |
1ba7b414 NB |
519 | \ |
520 | if (TARGET_64BIT) \ | |
521 | { \ | |
522 | builtin_assert ("cpu=x86_64"); \ | |
26b0ad13 | 523 | builtin_assert ("machine=x86_64"); \ |
97242ddc JH |
524 | builtin_define ("__amd64"); \ |
525 | builtin_define ("__amd64__"); \ | |
1ba7b414 NB |
526 | builtin_define ("__x86_64"); \ |
527 | builtin_define ("__x86_64__"); \ | |
528 | } \ | |
529 | else \ | |
530 | { \ | |
531 | builtin_assert ("cpu=i386"); \ | |
532 | builtin_assert ("machine=i386"); \ | |
533 | builtin_define_std ("i386"); \ | |
534 | } \ | |
535 | \ | |
8383d43c UB |
536 | /* Built-ins based on -march=. */ \ |
537 | switch (ix86_arch) \ | |
538 | { \ | |
539 | case PROCESSOR_I386: \ | |
540 | break; \ | |
541 | case PROCESSOR_I486: \ | |
542 | builtin_define ("__i486"); \ | |
543 | builtin_define ("__i486__"); \ | |
544 | break; \ | |
545 | case PROCESSOR_PENTIUM: \ | |
546 | builtin_define ("__i586"); \ | |
547 | builtin_define ("__i586__"); \ | |
548 | builtin_define ("__pentium"); \ | |
549 | builtin_define ("__pentium__"); \ | |
550 | if (last_arch_char == 'x') \ | |
551 | builtin_define ("__pentium_mmx__"); \ | |
552 | break; \ | |
553 | case PROCESSOR_PENTIUMPRO: \ | |
554 | builtin_define ("__i686"); \ | |
555 | builtin_define ("__i686__"); \ | |
556 | builtin_define ("__pentiumpro"); \ | |
557 | builtin_define ("__pentiumpro__"); \ | |
558 | break; \ | |
559 | case PROCESSOR_GEODE: \ | |
560 | builtin_define ("__geode"); \ | |
561 | builtin_define ("__geode__"); \ | |
562 | break; \ | |
563 | case PROCESSOR_K6: \ | |
564 | builtin_define ("__k6"); \ | |
565 | builtin_define ("__k6__"); \ | |
566 | if (last_arch_char == '2') \ | |
567 | builtin_define ("__k6_2__"); \ | |
568 | else if (last_arch_char == '3') \ | |
569 | builtin_define ("__k6_3__"); \ | |
570 | break; \ | |
571 | case PROCESSOR_ATHLON: \ | |
572 | builtin_define ("__athlon"); \ | |
573 | builtin_define ("__athlon__"); \ | |
574 | /* Only plain "athlon" lacks SSE. */ \ | |
575 | if (last_arch_char != 'n') \ | |
576 | builtin_define ("__athlon_sse__"); \ | |
577 | break; \ | |
578 | case PROCESSOR_K8: \ | |
579 | builtin_define ("__k8"); \ | |
580 | builtin_define ("__k8__"); \ | |
581 | break; \ | |
582 | case PROCESSOR_AMDFAM10: \ | |
583 | builtin_define ("__amdfam10"); \ | |
584 | builtin_define ("__amdfam10__"); \ | |
585 | break; \ | |
586 | case PROCESSOR_PENTIUM4: \ | |
587 | builtin_define ("__pentium4"); \ | |
588 | builtin_define ("__pentium4__"); \ | |
589 | break; \ | |
590 | case PROCESSOR_NOCONA: \ | |
591 | builtin_define ("__nocona"); \ | |
592 | builtin_define ("__nocona__"); \ | |
593 | break; \ | |
594 | case PROCESSOR_CORE2: \ | |
595 | builtin_define ("__core2"); \ | |
596 | builtin_define ("__core2__"); \ | |
597 | break; \ | |
598 | case PROCESSOR_GENERIC32: \ | |
599 | case PROCESSOR_GENERIC64: \ | |
600 | case PROCESSOR_max: \ | |
601 | gcc_unreachable (); \ | |
602 | } \ | |
603 | \ | |
604 | /* Built-ins based on -mtune=. */ \ | |
605 | switch (ix86_tune) \ | |
1ba7b414 | 606 | { \ |
8383d43c UB |
607 | case PROCESSOR_I386: \ |
608 | builtin_define ("__tune_i386__"); \ | |
609 | break; \ | |
610 | case PROCESSOR_I486: \ | |
611 | builtin_define ("__tune_i486__"); \ | |
612 | break; \ | |
613 | case PROCESSOR_PENTIUM: \ | |
1ba7b414 NB |
614 | builtin_define ("__tune_i586__"); \ |
615 | builtin_define ("__tune_pentium__"); \ | |
9e555526 | 616 | if (last_tune_char == 'x') \ |
1ba7b414 | 617 | builtin_define ("__tune_pentium_mmx__"); \ |
8383d43c UB |
618 | break; \ |
619 | case PROCESSOR_PENTIUMPRO: \ | |
1ba7b414 NB |
620 | builtin_define ("__tune_i686__"); \ |
621 | builtin_define ("__tune_pentiumpro__"); \ | |
9e555526 | 622 | switch (last_tune_char) \ |
2e37b0ce RH |
623 | { \ |
624 | case '3': \ | |
625 | builtin_define ("__tune_pentium3__"); \ | |
5efb1046 | 626 | /* FALLTHRU */ \ |
2e37b0ce RH |
627 | case '2': \ |
628 | builtin_define ("__tune_pentium2__"); \ | |
629 | break; \ | |
630 | } \ | |
8383d43c UB |
631 | break; \ |
632 | case PROCESSOR_GEODE: \ | |
cfe1b18f | 633 | builtin_define ("__tune_geode__"); \ |
8383d43c UB |
634 | break; \ |
635 | case PROCESSOR_K6: \ | |
1ba7b414 | 636 | builtin_define ("__tune_k6__"); \ |
9e555526 | 637 | if (last_tune_char == '2') \ |
1ba7b414 | 638 | builtin_define ("__tune_k6_2__"); \ |
9e555526 | 639 | else if (last_tune_char == '3') \ |
1ba7b414 | 640 | builtin_define ("__tune_k6_3__"); \ |
8383d43c UB |
641 | break; \ |
642 | case PROCESSOR_ATHLON: \ | |
1ba7b414 NB |
643 | builtin_define ("__tune_athlon__"); \ |
644 | /* Only plain "athlon" lacks SSE. */ \ | |
9e555526 | 645 | if (last_tune_char != 'n') \ |
1ba7b414 | 646 | builtin_define ("__tune_athlon_sse__"); \ |
8383d43c UB |
647 | break; \ |
648 | case PROCESSOR_K8: \ | |
649 | builtin_define ("__tune_k8__"); \ | |
650 | break; \ | |
651 | case PROCESSOR_AMDFAM10: \ | |
652 | builtin_define ("__tune_amdfam10__"); \ | |
653 | break; \ | |
654 | case PROCESSOR_PENTIUM4: \ | |
655 | builtin_define ("__tune_pentium4__"); \ | |
656 | break; \ | |
657 | case PROCESSOR_NOCONA: \ | |
658 | builtin_define ("__tune_nocona__"); \ | |
659 | break; \ | |
660 | case PROCESSOR_CORE2: \ | |
661 | builtin_define ("__tune_core2__"); \ | |
662 | break; \ | |
663 | case PROCESSOR_GENERIC32: \ | |
664 | case PROCESSOR_GENERIC64: \ | |
665 | break; \ | |
666 | case PROCESSOR_max: \ | |
667 | gcc_unreachable (); \ | |
1ba7b414 | 668 | } \ |
1ba7b414 NB |
669 | \ |
670 | if (TARGET_MMX) \ | |
671 | builtin_define ("__MMX__"); \ | |
672 | if (TARGET_3DNOW) \ | |
673 | builtin_define ("__3dNOW__"); \ | |
674 | if (TARGET_3DNOW_A) \ | |
675 | builtin_define ("__3dNOW_A__"); \ | |
676 | if (TARGET_SSE) \ | |
677 | builtin_define ("__SSE__"); \ | |
678 | if (TARGET_SSE2) \ | |
679 | builtin_define ("__SSE2__"); \ | |
9e200aaf KC |
680 | if (TARGET_SSE3) \ |
681 | builtin_define ("__SSE3__"); \ | |
b1875f52 L |
682 | if (TARGET_SSSE3) \ |
683 | builtin_define ("__SSSE3__"); \ | |
9a5cee02 L |
684 | if (TARGET_SSE4_1) \ |
685 | builtin_define ("__SSE4_1__"); \ | |
3b8dd071 L |
686 | if (TARGET_SSE4_2) \ |
687 | builtin_define ("__SSE4_2__"); \ | |
8b96a312 L |
688 | if (TARGET_AES) \ |
689 | builtin_define ("__AES__"); \ | |
690 | if (TARGET_PCLMUL) \ | |
691 | builtin_define ("__PCLMUL__"); \ | |
7706ca5d | 692 | if (TARGET_SSE4A) \ |
21efb4d4 | 693 | builtin_define ("__SSE4A__"); \ |
04e1d06b MM |
694 | if (TARGET_SSE5) \ |
695 | builtin_define ("__SSE5__"); \ | |
48ddd46c JH |
696 | if (TARGET_SSE_MATH && TARGET_SSE) \ |
697 | builtin_define ("__SSE_MATH__"); \ | |
698 | if (TARGET_SSE_MATH && TARGET_SSE2) \ | |
699 | builtin_define ("__SSE2_MATH__"); \ | |
1ba7b414 | 700 | } \ |
30efe578 NB |
701 | while (0) |
702 | ||
c2f17e19 UB |
703 | enum target_cpu_default |
704 | { | |
705 | TARGET_CPU_DEFAULT_generic = 0, | |
706 | ||
707 | TARGET_CPU_DEFAULT_i386, | |
708 | TARGET_CPU_DEFAULT_i486, | |
709 | TARGET_CPU_DEFAULT_pentium, | |
710 | TARGET_CPU_DEFAULT_pentium_mmx, | |
711 | TARGET_CPU_DEFAULT_pentiumpro, | |
712 | TARGET_CPU_DEFAULT_pentium2, | |
713 | TARGET_CPU_DEFAULT_pentium3, | |
714 | TARGET_CPU_DEFAULT_pentium4, | |
715 | TARGET_CPU_DEFAULT_pentium_m, | |
716 | TARGET_CPU_DEFAULT_prescott, | |
717 | TARGET_CPU_DEFAULT_nocona, | |
718 | TARGET_CPU_DEFAULT_core2, | |
719 | ||
720 | TARGET_CPU_DEFAULT_geode, | |
721 | TARGET_CPU_DEFAULT_k6, | |
722 | TARGET_CPU_DEFAULT_k6_2, | |
723 | TARGET_CPU_DEFAULT_k6_3, | |
724 | TARGET_CPU_DEFAULT_athlon, | |
725 | TARGET_CPU_DEFAULT_athlon_sse, | |
726 | TARGET_CPU_DEFAULT_k8, | |
727 | TARGET_CPU_DEFAULT_amdfam10, | |
728 | ||
729 | TARGET_CPU_DEFAULT_max | |
730 | }; | |
0c2dc519 | 731 | |
628714d8 | 732 | #ifndef CC1_SPEC |
8015b78d | 733 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
734 | #endif |
735 | ||
736 | /* This macro defines names of additional specifications to put in the | |
737 | specs that can be used in various specifications like CC1_SPEC. Its | |
738 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
739 | |
740 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 741 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
742 | program. |
743 | ||
744 | Do not define this macro if it does not need to do anything. */ | |
745 | ||
746 | #ifndef SUBTARGET_EXTRA_SPECS | |
747 | #define SUBTARGET_EXTRA_SPECS | |
748 | #endif | |
749 | ||
750 | #define EXTRA_SPECS \ | |
628714d8 | 751 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
752 | SUBTARGET_EXTRA_SPECS |
753 | \f | |
ce998900 | 754 | |
d57a4b98 RH |
755 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
756 | FPU, assume that the fpcw is set to extended precision; when using | |
757 | only SSE, rounding is correct; when using both SSE and the FPU, | |
758 | the rounding precision is indeterminate, since either may be chosen | |
759 | apparently at random. */ | |
760 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 761 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 762 | |
979c67a5 UB |
763 | /* target machine storage layout */ |
764 | ||
65d9c0ab JH |
765 | #define SHORT_TYPE_SIZE 16 |
766 | #define INT_TYPE_SIZE 32 | |
767 | #define FLOAT_TYPE_SIZE 32 | |
768 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
65d9c0ab JH |
769 | #define DOUBLE_TYPE_SIZE 64 |
770 | #define LONG_LONG_TYPE_SIZE 64 | |
979c67a5 UB |
771 | #define LONG_DOUBLE_TYPE_SIZE 80 |
772 | ||
773 | #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE | |
65d9c0ab | 774 | |
67adf6a9 | 775 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 776 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
777 | #else |
778 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
779 | #endif |
780 | ||
c98f8742 JVA |
781 | /* Define this if most significant byte of a word is the lowest numbered. */ |
782 | /* That is true on the 80386. */ | |
783 | ||
784 | #define BITS_BIG_ENDIAN 0 | |
785 | ||
786 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
787 | /* That is not true on the 80386. */ | |
788 | #define BYTES_BIG_ENDIAN 0 | |
789 | ||
790 | /* Define this if most significant word of a multiword number is the lowest | |
791 | numbered. */ | |
792 | /* Not true for 80386 */ | |
793 | #define WORDS_BIG_ENDIAN 0 | |
794 | ||
c98f8742 | 795 | /* Width of a word, in units (bytes). */ |
65d9c0ab | 796 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
2e64c636 JH |
797 | #ifdef IN_LIBGCC2 |
798 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
799 | #else | |
800 | #define MIN_UNITS_PER_WORD 4 | |
801 | #endif | |
c98f8742 | 802 | |
c98f8742 | 803 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 804 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 805 | |
e075ae69 | 806 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
d29899ba | 807 | #define STACK_BOUNDARY BITS_PER_WORD |
c98f8742 | 808 | |
d1f87653 | 809 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 810 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 811 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 812 | |
ead903e9 | 813 | /* As of July 2001, many runtimes do not align the stack properly when |
d1f87653 | 814 | entering main. This causes expand_main_function to forcibly align |
1d482056 RH |
815 | the stack, which results in aligned frames for functions called from |
816 | main, though it does nothing for the alignment of main itself. */ | |
817 | #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ | |
14f73b5a | 818 | (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) |
1d482056 | 819 | |
ebff937c SH |
820 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
821 | mandatory for the 64-bit ABI, and may or may not be true for other | |
822 | operating systems. */ | |
823 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
824 | ||
f963b5d9 RS |
825 | /* Minimum allocation boundary for the code of a function. */ |
826 | #define FUNCTION_BOUNDARY 8 | |
827 | ||
828 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
829 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 830 | |
892a2d68 | 831 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 832 | |
65d9c0ab | 833 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
834 | |
835 | /* Minimum size in bits of the largest boundary to which any | |
836 | and all fundamental data types supported by the hardware | |
837 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 838 | rounder than this. |
fce5a9f2 | 839 | |
d1f87653 | 840 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
841 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
842 | ||
843 | #define BIGGEST_ALIGNMENT 128 | |
844 | ||
822eda12 | 845 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 846 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 847 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 848 | |
17f24ff0 | 849 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 850 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 851 | -malign-double is set. */ |
e932b21b | 852 | |
e83f3cff RH |
853 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
854 | supports no vector modes, cut out the complexity and fall back | |
855 | on BIGGEST_FIELD_ALIGNMENT. */ | |
856 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
857 | #ifdef __x86_64__ |
858 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
859 | #else | |
e83f3cff | 860 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 861 | #endif |
e83f3cff | 862 | #else |
e932b21b JH |
863 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
864 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 865 | #endif |
c98f8742 | 866 | |
e5e8a8bf | 867 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 868 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
869 | and ALIGN is the alignment that the object would ordinarily have. |
870 | The value of this macro is used instead of that alignment to align | |
871 | the object. | |
872 | ||
873 | If this macro is not defined, then ALIGN is used. | |
874 | ||
875 | The typical use of this macro is to increase alignment for string | |
876 | constants to be word aligned so that `strcpy' calls that copy | |
877 | constants can be done inline. */ | |
878 | ||
d9a5f180 | 879 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 880 | |
8a022443 JW |
881 | /* If defined, a C expression to compute the alignment for a static |
882 | variable. TYPE is the data type, and ALIGN is the alignment that | |
883 | the object would ordinarily have. The value of this macro is used | |
884 | instead of that alignment to align the object. | |
885 | ||
886 | If this macro is not defined, then ALIGN is used. | |
887 | ||
888 | One use of this macro is to increase alignment of medium-size | |
889 | data to make it all fit in fewer cache lines. Another is to | |
890 | cause character arrays to be word-aligned so that `strcpy' calls | |
891 | that copy constants to character arrays can be done inline. */ | |
892 | ||
d9a5f180 | 893 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
894 | |
895 | /* If defined, a C expression to compute the alignment for a local | |
896 | variable. TYPE is the data type, and ALIGN is the alignment that | |
897 | the object would ordinarily have. The value of this macro is used | |
898 | instead of that alignment to align the object. | |
899 | ||
900 | If this macro is not defined, then ALIGN is used. | |
901 | ||
902 | One use of this macro is to increase alignment of medium-size | |
903 | data to make it all fit in fewer cache lines. */ | |
904 | ||
d9a5f180 | 905 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) |
8a022443 | 906 | |
53c17031 JH |
907 | /* If defined, a C expression that gives the alignment boundary, in |
908 | bits, of an argument with the specified mode and type. If it is | |
909 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
910 | ||
d9a5f180 GS |
911 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
912 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 913 | |
9cd10576 | 914 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 915 | when given unaligned data. */ |
b4ac57ab | 916 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
917 | |
918 | /* If bit field type is int, don't let it cross an int, | |
919 | and give entire struct the alignment of an int. */ | |
43a88a8c | 920 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 921 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
922 | \f |
923 | /* Standard register usage. */ | |
924 | ||
925 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 926 | for details. */ |
c98f8742 JVA |
927 | |
928 | #define STACK_REGS | |
ce998900 | 929 | |
d9a5f180 | 930 | #define IS_STACK_MODE(MODE) \ |
b5c82fa1 PB |
931 | (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ |
932 | || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
933 | || (MODE) == XFmode) | |
c98f8742 JVA |
934 | |
935 | /* Number of actual hardware registers. | |
936 | The hardware registers are assigned numbers for the compiler | |
937 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
938 | All registers that the compiler knows about must be given numbers, | |
939 | even those that are not normally considered general registers. | |
940 | ||
941 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
942 | We number the floating point registers 8-15. | |
943 | Note that registers 0-7 can be accessed as a short or int, | |
944 | while only 0-3 may be used with byte `mov' instructions. | |
945 | ||
946 | Reg 16 does not correspond to any hardware register, but instead | |
947 | appears in the RTL as an argument pointer prior to reload, and is | |
948 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 949 | pointer. */ |
c98f8742 | 950 | |
b0d95de8 | 951 | #define FIRST_PSEUDO_REGISTER 53 |
c98f8742 | 952 | |
3073d01c ML |
953 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
954 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
955 | ||
956 | #define DWARF_FRAME_REGISTERS 17 | |
957 | ||
c98f8742 JVA |
958 | /* 1 for registers that have pervasive standard uses |
959 | and are not available for the register allocator. | |
3f3f2124 | 960 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 961 | |
3a4416fb RS |
962 | The value is zero if the register is not fixed on either 32 or |
963 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
964 | bit targets, two if it is only fixed on 32bit targets and three | |
965 | if its only fixed on 64bit targets. | |
966 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
3f3f2124 | 967 | */ |
a7180f70 BS |
968 | #define FIXED_REGISTERS \ |
969 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 970 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
971 | /*arg,flags,fpsr,fpcr,frame*/ \ |
972 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
973 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
974 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
975 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
3f3f2124 JH |
976 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
977 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
3a4416fb | 978 | 2, 2, 2, 2, 2, 2, 2, 2, \ |
3f3f2124 | 979 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
ce998900 | 980 | 2, 2, 2, 2, 2, 2, 2, 2 } |
fce5a9f2 | 981 | |
c98f8742 JVA |
982 | |
983 | /* 1 for registers not available across function calls. | |
984 | These must include the FIXED_REGISTERS and also any | |
985 | registers that can be used without being saved. | |
986 | The latter must include the registers where values are returned | |
987 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
988 | Aside from that, you can include as many other registers as you like. |
989 | ||
9d72d996 JJ |
990 | The value is zero if the register is not call used on either 32 or |
991 | 64 bit targets, one if the register if call used on both 32 and 64 | |
992 | bit targets, two if it is only call used on 32bit targets and three | |
993 | if its only call used on 64bit targets. | |
3a4416fb | 994 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. |
3f3f2124 | 995 | */ |
a7180f70 BS |
996 | #define CALL_USED_REGISTERS \ |
997 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 998 | { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
999 | /*arg,flags,fpsr,fpcr,frame*/ \ |
1000 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 1001 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
03c259ad | 1002 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
a7180f70 | 1003 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
3a4416fb | 1004 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1005 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1006 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1007 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
ce998900 | 1008 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 1009 | |
3b3c6a3f MM |
1010 | /* Order in which to allocate registers. Each register must be |
1011 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1012 | late and fixed registers last. Note that, in general, we prefer | |
1013 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1014 | available for storage of persistent values. | |
1015 | ||
162f023b JH |
1016 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
1017 | so this is just empty initializer for array. */ | |
3b3c6a3f | 1018 | |
162f023b JH |
1019 | #define REG_ALLOC_ORDER \ |
1020 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1021 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1022 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
b0d95de8 | 1023 | 48, 49, 50, 51, 52 } |
3b3c6a3f | 1024 | |
162f023b JH |
1025 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
1026 | to be rearranged based on a particular function. When using sse math, | |
03c259ad | 1027 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1028 | |
162f023b | 1029 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 1030 | |
f5316dfe | 1031 | |
c98f8742 | 1032 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 1033 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 1034 | do { \ |
3f3f2124 | 1035 | int i; \ |
b0fede98 | 1036 | unsigned int j; \ |
3f3f2124 JH |
1037 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ |
1038 | { \ | |
3a4416fb RS |
1039 | if (fixed_regs[i] > 1) \ |
1040 | fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ | |
1041 | if (call_used_regs[i] > 1) \ | |
1042 | call_used_regs[i] = (call_used_regs[i] \ | |
1043 | == (TARGET_64BIT ? 3 : 2)); \ | |
3f3f2124 | 1044 | } \ |
b0fede98 | 1045 | j = PIC_OFFSET_TABLE_REGNUM; \ |
7706ca5d | 1046 | if (j != INVALID_REGNUM) \ |
a7180f70 | 1047 | { \ |
7706ca5d L |
1048 | fixed_regs[j] = 1; \ |
1049 | call_used_regs[j] = 1; \ | |
a7180f70 BS |
1050 | } \ |
1051 | if (! TARGET_MMX) \ | |
1052 | { \ | |
1053 | int i; \ | |
1054 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1055 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
33270999 | 1056 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
a7180f70 BS |
1057 | } \ |
1058 | if (! TARGET_SSE) \ | |
1059 | { \ | |
1060 | int i; \ | |
1061 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1062 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
33270999 | 1063 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
a7180f70 BS |
1064 | } \ |
1065 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
1066 | { \ | |
1067 | int i; \ | |
1068 | HARD_REG_SET x; \ | |
1069 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
1070 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
1071 | if (TEST_HARD_REG_BIT (x, i)) \ | |
33270999 AO |
1072 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
1073 | } \ | |
1074 | if (! TARGET_64BIT) \ | |
1075 | { \ | |
1076 | int i; \ | |
1077 | for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ | |
1078 | reg_names[i] = ""; \ | |
1079 | for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ | |
1080 | reg_names[i] = ""; \ | |
a7180f70 | 1081 | } \ |
d29899ba KT |
1082 | if (TARGET_64BIT_MS_ABI) \ |
1083 | { \ | |
1084 | call_used_regs[4 /*RSI*/] = 0; \ | |
1085 | call_used_regs[5 /*RDI*/] = 0; \ | |
1086 | } \ | |
d9a5f180 | 1087 | } while (0) |
c98f8742 JVA |
1088 | |
1089 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
1090 | to hold something of mode MODE. | |
1091 | This is ordinarily the length in words of a value of mode MODE | |
1092 | but can be less for certain modes in special long registers. | |
1093 | ||
fce5a9f2 | 1094 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
1095 | registers. And only registers 0-3 may have mov byte instructions |
1096 | applied to them. | |
1097 | */ | |
1098 | ||
ce998900 | 1099 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
92d0fb09 JH |
1100 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
1101 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 | 1102 | : ((MODE) == XFmode \ |
92d0fb09 | 1103 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1104 | : (MODE) == XCmode \ |
92d0fb09 | 1105 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1106 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1107 | |
8521c414 JM |
1108 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
1109 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
1110 | ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
1111 | ? 0 \ | |
1112 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
1113 | : 0) | |
1114 | ||
1115 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1116 | ||
ce998900 UB |
1117 | #define VALID_SSE2_REG_MODE(MODE) \ |
1118 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1119 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1120 | |
d9a5f180 | 1121 | #define VALID_SSE_REG_MODE(MODE) \ |
ce998900 UB |
1122 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ |
1123 | || (MODE) == SFmode || (MODE) == TFmode) | |
a7180f70 | 1124 | |
47f339cf | 1125 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1126 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1127 | |
d9a5f180 | 1128 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1129 | ((MODE == V1DImode) || (MODE) == DImode \ |
1130 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1131 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1132 | |
accde4cf RH |
1133 | /* ??? No autovectorization into MMX or 3DNOW until we can reliably |
1134 | place emms and femms instructions. */ | |
9d3a9de1 | 1135 | #define UNITS_PER_SIMD_WORD(MODE) (TARGET_SSE ? 16 : UNITS_PER_WORD) |
0bf43309 | 1136 | |
ce998900 UB |
1137 | #define VALID_DFP_MODE_P(MODE) \ |
1138 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1139 | |
d9a5f180 | 1140 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1141 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1142 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1143 | |
d9a5f180 | 1144 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1145 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1146 | || (MODE) == DImode \ | |
1147 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1148 | || (MODE) == CDImode \ | |
1149 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1150 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1151 | |
822eda12 | 1152 | /* Return true for modes passed in SSE registers. */ |
ce998900 UB |
1153 | #define SSE_REG_MODE_P(MODE) \ |
1154 | ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ | |
822eda12 JH |
1155 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ |
1156 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
1157 | ||
e075ae69 | 1158 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1159 | |
a946dd00 | 1160 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1161 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1162 | |
1163 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1164 | when one has mode MODE1 and one has mode MODE2. | |
1165 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1166 | for any hard reg, then this must be 0 for correct output. */ | |
1167 | ||
c1c5b5e3 | 1168 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 1169 | |
ff25ef99 ZD |
1170 | /* It is possible to write patterns to move flags; but until someone |
1171 | does it, */ | |
1172 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1173 | |
e075ae69 | 1174 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1175 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1176 | |
787dc842 JH |
1177 | Kill any attempts to combine saving of modes. */ |
1178 | ||
d9a5f180 GS |
1179 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1180 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1181 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1182 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
d9a5f180 GS |
1183 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ |
1184 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
d2836273 | 1185 | : (MODE)) |
ce998900 | 1186 | |
c98f8742 JVA |
1187 | /* Specify the registers used for certain standard purposes. |
1188 | The values of these macros are register numbers. */ | |
1189 | ||
1190 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1191 | register. The ordinary mov instructions won't work */ | |
1192 | /* #define PC_REGNUM */ | |
1193 | ||
1194 | /* Register to use for pushing function arguments. */ | |
1195 | #define STACK_POINTER_REGNUM 7 | |
1196 | ||
1197 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1198 | #define HARD_FRAME_POINTER_REGNUM 6 |
1199 | ||
1200 | /* Base register for access to local variables of the function. */ | |
b0d95de8 | 1201 | #define FRAME_POINTER_REGNUM 20 |
c98f8742 JVA |
1202 | |
1203 | /* First floating point reg */ | |
1204 | #define FIRST_FLOAT_REG 8 | |
1205 | ||
1206 | /* First & last stack-like regs */ | |
1207 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1208 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1209 | ||
a7180f70 BS |
1210 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1211 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1212 | |
a7180f70 BS |
1213 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
1214 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1215 | ||
3f3f2124 JH |
1216 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
1217 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1218 | ||
1219 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1220 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1221 | ||
c98f8742 JVA |
1222 | /* Value should be nonzero if functions must have frame pointers. |
1223 | Zero means the frame pointer need not be set up (and parms | |
1224 | may be accessed via the stack pointer) in functions that seem suitable. | |
1225 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
1226 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
1227 | ||
aabcd309 | 1228 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1229 | requiring a frame pointer. */ |
1230 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1231 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1232 | #endif | |
1233 | ||
1234 | /* Make sure we can access arbitrary call frames. */ | |
1235 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1236 | |
1237 | /* Base register for access to arguments of the function. */ | |
1238 | #define ARG_POINTER_REGNUM 16 | |
1239 | ||
d2836273 JH |
1240 | /* Register in which static-chain is passed to a function. |
1241 | We do use ECX as static chain register for 32 bit ABI. On the | |
1242 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
2ff8644d | 1243 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG) |
c98f8742 JVA |
1244 | |
1245 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1246 | code access to data items. We don't use PIC pointer for 64bit |
1247 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1248 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1249 | |
1250 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1251 | the pic register when possible. The change is visible after the | |
1252 | prologue has been emitted. */ | |
1253 | ||
1254 | #define REAL_PIC_OFFSET_TABLE_REGNUM 3 | |
1255 | ||
1256 | #define PIC_OFFSET_TABLE_REGNUM \ | |
7dcbf659 JH |
1257 | ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ |
1258 | || !flag_pic ? INVALID_REGNUM \ | |
bd09bdeb RH |
1259 | : reload_completed ? REGNO (pic_offset_table_rtx) \ |
1260 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1261 | |
5fc0e5df KW |
1262 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1263 | ||
c51e6d85 | 1264 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1265 | #define MS_AGGREGATE_RETURN 0 |
1266 | ||
61fec9ff JB |
1267 | /* This is overridden by <netware.h>. */ |
1268 | #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
c98f8742 JVA |
1269 | \f |
1270 | /* Define the classes of registers for register constraints in the | |
1271 | machine description. Also define ranges of constants. | |
1272 | ||
1273 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1274 | If there is more than one class, another class must be named NO_REGS | |
1275 | and contain no registers. | |
1276 | ||
1277 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1278 | another name such as ALL_REGS). This is the class of registers | |
1279 | that is allowed by "g" or "r" in a register constraint. | |
1280 | Also, registers outside this class are allocated only when | |
1281 | instructions express preferences for them. | |
1282 | ||
1283 | The classes must be numbered in nondecreasing order; that is, | |
1284 | a larger-numbered class must never be contained completely | |
1285 | in a smaller-numbered class. | |
1286 | ||
1287 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1288 | class that represents their union. |
1289 | ||
1290 | It might seem that class BREG is unnecessary, since no useful 386 | |
1291 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1292 | and the "b" register constraint is useful in asms for syscalls. |
1293 | ||
03c259ad | 1294 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1295 | |
1296 | enum reg_class | |
1297 | { | |
1298 | NO_REGS, | |
e075ae69 | 1299 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1300 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1301 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1302 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1303 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1304 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1305 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1306 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1307 | FLOAT_REGS, | |
06f4e35d | 1308 | SSE_FIRST_REG, |
a7180f70 BS |
1309 | SSE_REGS, |
1310 | MMX_REGS, | |
446988df JH |
1311 | FP_TOP_SSE_REGS, |
1312 | FP_SECOND_SSE_REGS, | |
1313 | FLOAT_SSE_REGS, | |
1314 | FLOAT_INT_REGS, | |
1315 | INT_SSE_REGS, | |
1316 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1317 | ALL_REGS, LIM_REG_CLASSES |
1318 | }; | |
1319 | ||
d9a5f180 GS |
1320 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1321 | ||
1322 | #define INTEGER_CLASS_P(CLASS) \ | |
1323 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1324 | #define FLOAT_CLASS_P(CLASS) \ | |
1325 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1326 | #define SSE_CLASS_P(CLASS) \ | |
06f4e35d | 1327 | reg_class_subset_p ((CLASS), SSE_REGS) |
d9a5f180 | 1328 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1329 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1330 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1331 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1332 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1333 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1334 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1335 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1336 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1337 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1338 | ||
1339 | #define Q_CLASS_P(CLASS) \ | |
1340 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1341 | |
43f3a59d | 1342 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1343 | |
1344 | #define REG_CLASS_NAMES \ | |
1345 | { "NO_REGS", \ | |
ab408a86 | 1346 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1347 | "SIREG", "DIREG", \ |
e075ae69 RH |
1348 | "AD_REGS", \ |
1349 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1350 | "INDEX_REGS", \ |
3f3f2124 | 1351 | "LEGACY_REGS", \ |
c98f8742 JVA |
1352 | "GENERAL_REGS", \ |
1353 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1354 | "FLOAT_REGS", \ | |
cb482895 | 1355 | "SSE_FIRST_REG", \ |
a7180f70 BS |
1356 | "SSE_REGS", \ |
1357 | "MMX_REGS", \ | |
446988df JH |
1358 | "FP_TOP_SSE_REGS", \ |
1359 | "FP_SECOND_SSE_REGS", \ | |
1360 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1361 | "FLOAT_INT_REGS", \ |
446988df JH |
1362 | "INT_SSE_REGS", \ |
1363 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1364 | "ALL_REGS" } |
1365 | ||
1366 | /* Define which registers fit in which classes. | |
1367 | This is an initializer for a vector of HARD_REG_SET | |
1368 | of length N_REG_CLASSES. */ | |
1369 | ||
a7180f70 | 1370 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1371 | { { 0x00, 0x0 }, \ |
1372 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1373 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1374 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1375 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1376 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
b0d95de8 UB |
1377 | { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ |
1378 | { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1379 | { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1380 | { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
3f3f2124 JH |
1381 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ |
1382 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
cb482895 | 1383 | { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ |
b0d95de8 UB |
1384 | { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ |
1385 | { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1386 | { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1387 | { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1388 | { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \ | |
1389 | { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1390 | { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1391 | { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1392 | { 0xffffffff,0x1fffff } \ | |
e075ae69 | 1393 | } |
c98f8742 JVA |
1394 | |
1395 | /* The same information, inverted: | |
1396 | Return the class number of the smallest class containing | |
1397 | reg number REGNO. This could be a conditional expression | |
1398 | or could index an array. */ | |
1399 | ||
c98f8742 JVA |
1400 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1401 | ||
1402 | /* When defined, the compiler allows registers explicitly used in the | |
1403 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1404 | extending the lifetime of these registers. */ |
c98f8742 | 1405 | |
2922fe9e | 1406 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 | 1407 | |
fb84c7a0 | 1408 | #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4) |
3f3f2124 | 1409 | |
d9a5f180 | 1410 | #define GENERAL_REGNO_P(N) \ |
fb84c7a0 | 1411 | ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) |
3f3f2124 JH |
1412 | |
1413 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1414 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1415 | |
1416 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1417 | ||
fb84c7a0 UB |
1418 | #define REX_INT_REGNO_P(N) \ |
1419 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 JH |
1420 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1421 | ||
c98f8742 | 1422 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
fb84c7a0 | 1423 | #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
446988df | 1424 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1425 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1426 | |
54a88090 | 1427 | #define X87_FLOAT_MODE_P(MODE) \ |
27ac40e2 | 1428 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) |
54a88090 | 1429 | |
fb84c7a0 UB |
1430 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) |
1431 | #define SSE_REGNO_P(N) \ | |
1432 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
1433 | || REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1434 | |
4977bab6 | 1435 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1436 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1437 | |
d9a5f180 GS |
1438 | #define SSE_REGNO(N) \ |
1439 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
446988df | 1440 | |
d9a5f180 | 1441 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1442 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1443 | |
d6023b50 UB |
1444 | #define SSE_VEC_FLOAT_MODE_P(MODE) \ |
1445 | ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) | |
1446 | ||
d9a5f180 | 1447 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) |
fb84c7a0 | 1448 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1449 | |
fb84c7a0 | 1450 | #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) |
fb84c7a0 | 1451 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
c98f8742 | 1452 | |
d9a5f180 | 1453 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1454 | |
e075ae69 RH |
1455 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1456 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1457 | ||
c98f8742 JVA |
1458 | /* The class value for index registers, and the one for base regs. */ |
1459 | ||
1460 | #define INDEX_REG_CLASS INDEX_REGS | |
1461 | #define BASE_REG_CLASS GENERAL_REGS | |
1462 | ||
c98f8742 | 1463 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1464 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1465 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1466 | |
d2836273 JH |
1467 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1468 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1469 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1470 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1471 | ? Q_REGS : (CLASS)) |
1472 | ||
1473 | /* Given an rtx X being reloaded into a reg required to be | |
1474 | in class CLASS, return the class of reg to actually use. | |
1475 | In general this is just CLASS; but on some machines | |
1476 | in some cases it is preferable to use a more restrictive class. | |
1477 | On the 80386 series, we prevent floating constants from being | |
1478 | reloaded into floating registers (since no move-insn can do that) | |
1479 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1480 | ||
d398b3b1 | 1481 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1482 | QImode must go into class Q_REGS. |
d398b3b1 | 1483 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1484 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1485 | |
d9a5f180 GS |
1486 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1487 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e | 1488 | |
b5c82fa1 PB |
1489 | /* Discourage putting floating-point values in SSE registers unless |
1490 | SSE math is being used, and likewise for the 387 registers. */ | |
1491 | ||
1492 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
1493 | ix86_preferred_output_reload_class ((X), (CLASS)) | |
1494 | ||
85ff473e | 1495 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1496 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1497 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1498 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 | 1499 | |
c62b3659 UB |
1500 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1501 | There is no need to emit full 64 bit move on 64 bit targets | |
1502 | for integral modes that can be moved using 32 bit move. */ | |
1503 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1504 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1505 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1506 | : MODE) | |
1507 | ||
c98f8742 JVA |
1508 | /* Return the maximum number of consecutive registers |
1509 | needed to represent mode MODE in a register of class CLASS. */ | |
1510 | /* On the 80386, this is the size of MODE in words, | |
f8a1ebc6 | 1511 | except in the FP regs, where a single reg is always enough. */ |
a7180f70 | 1512 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1513 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1514 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 JH |
1515 | : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ |
1516 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1517 | |
1518 | /* A C expression whose value is nonzero if pseudos that have been | |
1519 | assigned to registers of class CLASS would likely be spilled | |
1520 | because registers of CLASS are needed for spill registers. | |
1521 | ||
1522 | The default value of this macro returns 1 if CLASS has exactly one | |
1523 | register and zero otherwise. On most machines, this default | |
1524 | should be used. Only define this macro to some other expression | |
1525 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1526 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1527 | macro returns nonzero for those classes, those pseudos will only |
1528 | be allocated by `global.c', which knows how to reallocate the | |
1529 | pseudo to another register. If there would not be another | |
1530 | register available for reallocation, you should not change the | |
1531 | definition of this macro since the only effect of such a | |
1532 | definition would be to slow down register allocation. */ | |
1533 | ||
1534 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1535 | (((CLASS) == AREG) \ | |
1536 | || ((CLASS) == DREG) \ | |
1537 | || ((CLASS) == CREG) \ | |
1538 | || ((CLASS) == BREG) \ | |
1539 | || ((CLASS) == AD_REGS) \ | |
1540 | || ((CLASS) == SIREG) \ | |
b0af5c03 JH |
1541 | || ((CLASS) == DIREG) \ |
1542 | || ((CLASS) == FP_TOP_REG) \ | |
1543 | || ((CLASS) == FP_SECOND_REG)) | |
f5316dfe | 1544 | |
1272914c RH |
1545 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1546 | ||
1547 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1548 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1549 | \f |
1550 | /* Stack layout; function entry, exit and calling. */ | |
1551 | ||
1552 | /* Define this if pushing a word on the stack | |
1553 | makes the stack pointer a smaller address. */ | |
1554 | #define STACK_GROWS_DOWNWARD | |
1555 | ||
a4d05547 | 1556 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1557 | is at the high-address end of the local variables; |
1558 | that is, each additional local variable allocated | |
1559 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1560 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1561 | |
1562 | /* Offset within stack frame to start allocating local variables at. | |
1563 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1564 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1565 | of the first local allocated. */ | |
1566 | #define STARTING_FRAME_OFFSET 0 | |
1567 | ||
1568 | /* If we generate an insn to push BYTES bytes, | |
1569 | this says how many the stack pointer really advances by. | |
6541fe75 JJ |
1570 | On 386, we have pushw instruction that decrements by exactly 2 no |
1571 | matter what the position was, there is no pushb. | |
1572 | But as CIE data alignment factor on this arch is -4, we need to make | |
1573 | sure all stack pointer adjustments are in multiple of 4. | |
fce5a9f2 | 1574 | |
d2836273 JH |
1575 | For 64bit ABI we round up to 8 bytes. |
1576 | */ | |
c98f8742 | 1577 | |
d2836273 JH |
1578 | #define PUSH_ROUNDING(BYTES) \ |
1579 | (TARGET_64BIT \ | |
1580 | ? (((BYTES) + 7) & (-8)) \ | |
6541fe75 | 1581 | : (((BYTES) + 3) & (-4))) |
c98f8742 | 1582 | |
f73ad30e JH |
1583 | /* If defined, the maximum amount of space required for outgoing arguments will |
1584 | be computed and placed into the variable | |
38173d38 | 1585 | `crtl->outgoing_args_size'. No space will be pushed onto the |
f73ad30e JH |
1586 | stack for each call; instead, the function prologue should increase the stack |
1587 | frame size by this amount. */ | |
1588 | ||
1589 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1590 | ||
1591 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1592 | instructions to pass outgoing arguments. */ | |
1593 | ||
1594 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1595 | ||
2da4124d L |
1596 | /* We want the stack and args grow in opposite directions, even if |
1597 | PUSH_ARGS is 0. */ | |
1598 | #define PUSH_ARGS_REVERSED 1 | |
1599 | ||
c98f8742 JVA |
1600 | /* Offset of first parameter from the argument pointer register value. */ |
1601 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1602 | ||
a7180f70 BS |
1603 | /* Define this macro if functions should assume that stack space has been |
1604 | allocated for arguments even when their values are passed in registers. | |
1605 | ||
1606 | The value of this macro is the size, in bytes, of the area reserved for | |
1607 | arguments passed in registers for the function represented by FNDECL. | |
1608 | ||
1609 | This space can be allocated by the caller, or be a part of the | |
1610 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1611 | which. */ | |
d29899ba | 1612 | #define REG_PARM_STACK_SPACE(FNDECL) 0 |
a7180f70 | 1613 | |
c98f8742 JVA |
1614 | /* Value is the number of bytes of arguments automatically |
1615 | popped when returning from a subroutine call. | |
8b109b37 | 1616 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1617 | FUNTYPE is the data type of the function (as a tree), |
1618 | or for a library call it is an identifier node for the subroutine name. | |
1619 | SIZE is the number of bytes of arguments passed on the stack. | |
1620 | ||
1621 | On the 80386, the RTD insn may be used to pop them if the number | |
1622 | of args is fixed, but if the number is variable then the caller | |
1623 | must pop them all. RTD can't be used for library calls now | |
1624 | because the library is compiled with the Unix compiler. | |
1625 | Use of RTD is a selectable option, since it is incompatible with | |
1626 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1627 | the caller must always pop the args. |
1628 | ||
1629 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1630 | |
d9a5f180 GS |
1631 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1632 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1633 | |
53c17031 JH |
1634 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1635 | ix86_function_value_regno_p (N) | |
c98f8742 JVA |
1636 | |
1637 | /* Define how to find the value returned by a library function | |
1638 | assuming the value has mode MODE. */ | |
1639 | ||
1640 | #define LIBCALL_VALUE(MODE) \ | |
53c17031 | 1641 | ix86_libcall_value (MODE) |
c98f8742 | 1642 | |
e9125c09 TW |
1643 | /* Define the size of the result block used for communication between |
1644 | untyped_call and untyped_return. The block contains a DImode value | |
1645 | followed by the block used by fnsave and frstor. */ | |
1646 | ||
1647 | #define APPLY_RESULT_SIZE (8+108) | |
1648 | ||
b08de47e | 1649 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1650 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1651 | |
1652 | /* Define a data type for recording info about an argument list | |
1653 | during the scan of that argument list. This data type should | |
1654 | hold all necessary information about the function itself | |
1655 | and about the args processed so far, enough to enable macros | |
b08de47e | 1656 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1657 | |
e075ae69 | 1658 | typedef struct ix86_args { |
fa283935 | 1659 | int words; /* # words passed so far */ |
b08de47e MM |
1660 | int nregs; /* # registers available for passing */ |
1661 | int regno; /* next available register number */ | |
9d72d996 | 1662 | int fastcall; /* fastcall calling convention is used */ |
fa283935 | 1663 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1664 | int sse_nregs; /* # sse registers available for passing */ |
47a37ce4 | 1665 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1666 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1667 | int sse_regno; /* next available sse register number */ | |
1668 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1669 | int mmx_nregs; /* # mmx registers available for passing */ |
1670 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1671 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2f84b963 RG |
1672 | int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should |
1673 | be passed in SSE registers. Otherwise 0. */ | |
b08de47e | 1674 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1675 | |
1676 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1677 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1678 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1679 | |
0f6937fe | 1680 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
dafc5b82 | 1681 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
c98f8742 JVA |
1682 | |
1683 | /* Update the data in CUM to advance over an argument | |
1684 | of mode MODE and data type TYPE. | |
1685 | (TYPE is null for libcalls where that information may not be available.) */ | |
1686 | ||
d9a5f180 GS |
1687 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1688 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1689 | |
1690 | /* Define where to put the arguments to a function. | |
1691 | Value is zero to push the argument on the stack, | |
1692 | or a hard register in which to store the argument. | |
1693 | ||
1694 | MODE is the argument's machine mode. | |
1695 | TYPE is the data type of the argument (as a tree). | |
1696 | This is null for libcalls where that information may | |
1697 | not be available. | |
1698 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1699 | the preceding args and about the function being called. | |
1700 | NAMED is nonzero if this argument is a named parameter | |
1701 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1702 | ||
c98f8742 | 1703 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1704 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 | 1705 | |
a5fe455b ZW |
1706 | #define TARGET_ASM_FILE_END ix86_file_end |
1707 | #define NEED_INDICATE_EXEC_STACK 0 | |
3a0433fd | 1708 | |
c98f8742 JVA |
1709 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1710 | for profiling a function entry. */ | |
1711 | ||
a5fa1ecd JH |
1712 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1713 | ||
1714 | #define MCOUNT_NAME "_mcount" | |
1715 | ||
1716 | #define PROFILE_COUNT_REGISTER "edx" | |
c98f8742 JVA |
1717 | |
1718 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1719 | the stack pointer does not matter. The value is tested only in | |
1720 | functions that have frame pointers. | |
1721 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1722 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1723 | we have to restore it ourselves from the frame pointer, in order to |
1724 | use pop */ | |
1725 | ||
1726 | #define EXIT_IGNORE_STACK 1 | |
1727 | ||
c98f8742 JVA |
1728 | /* Output assembler code for a block containing the constant parts |
1729 | of a trampoline, leaving space for the variable parts. */ | |
1730 | ||
a269a03c | 1731 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1732 | mov #STATIC,ecx |
a269a03c JC |
1733 | jmp FUNCTION |
1734 | The trampoline is generated entirely at runtime. The operand of JMP | |
1735 | is the address of FUNCTION relative to the instruction following the | |
1736 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1737 | |
1738 | /* Length in units of the trampoline for entering a nested function. */ | |
1739 | ||
39d04363 | 1740 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1741 | |
1742 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1743 | FNADDR is an RTX for the address of the function's pure code. | |
1744 | CXT is an RTX for the static chain value for the function. */ | |
1745 | ||
d9a5f180 GS |
1746 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1747 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1748 | \f |
1749 | /* Definitions for register eliminations. | |
1750 | ||
1751 | This is an array of structures. Each structure initializes one pair | |
1752 | of eliminable registers. The "from" register number is given first, | |
1753 | followed by "to". Eliminations of the same "from" register are listed | |
1754 | in order of preference. | |
1755 | ||
afc2cd05 NC |
1756 | There are two registers that can always be eliminated on the i386. |
1757 | The frame pointer and the arg pointer can be replaced by either the | |
1758 | hard frame pointer or to the stack pointer, depending upon the | |
1759 | circumstances. The hard frame pointer is not used before reload and | |
1760 | so it is not eligible for elimination. */ | |
c98f8742 | 1761 | |
564d80f4 JH |
1762 | #define ELIMINABLE_REGS \ |
1763 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1764 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1765 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1766 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1767 | |
2c5a510c RH |
1768 | /* Given FROM and TO register numbers, say whether this elimination is |
1769 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1770 | |
1771 | All other eliminations are valid. */ | |
1772 | ||
2c5a510c | 1773 | #define CAN_ELIMINATE(FROM, TO) \ |
979c67a5 | 1774 | ((TO) == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1) |
c98f8742 JVA |
1775 | |
1776 | /* Define the offset between two registers, one to be eliminated, and the other | |
1777 | its replacement, at the start of a routine. */ | |
1778 | ||
d9a5f180 GS |
1779 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1780 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1781 | \f |
1782 | /* Addressing modes, and classification of registers for them. */ | |
1783 | ||
c98f8742 JVA |
1784 | /* Macros to check register numbers against specific register classes. */ |
1785 | ||
1786 | /* These assume that REGNO is a hard or pseudo reg number. | |
1787 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1788 | or a pseudo reg currently allocated to a suitable hard reg. | |
1789 | Since they use reg_renumber, they are safe only once reg_renumber | |
1790 | has been allocated, which happens in local-alloc.c. */ | |
1791 | ||
3f3f2124 JH |
1792 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1793 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1794 | || REX_INT_REGNO_P (REGNO) \ |
1795 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1796 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1797 | |
3f3f2124 | 1798 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1799 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1800 | || (REGNO) == ARG_POINTER_REGNUM \ |
1801 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1802 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1803 | |
c98f8742 JVA |
1804 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1805 | and check its validity for a certain class. | |
1806 | We have two alternate definitions for each of them. | |
1807 | The usual definition accepts all pseudo regs; the other rejects | |
1808 | them unless they have been allocated suitable hard regs. | |
1809 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1810 | ||
1811 | Most source files want to accept pseudo regs in the hope that | |
1812 | they will get allocated to the class that the insn wants them to be in. | |
1813 | Source files for reload pass need to be strict. | |
1814 | After reload, it makes no difference, since pseudo regs have | |
1815 | been eliminated by then. */ | |
1816 | ||
c98f8742 | 1817 | |
ff482c8d | 1818 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1819 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1820 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1821 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1822 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1823 | ||
3b3c6a3f | 1824 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1825 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1826 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1827 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1828 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1829 | |
3b3c6a3f MM |
1830 | /* Strict versions, hard registers only */ |
1831 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1832 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1833 | |
3b3c6a3f | 1834 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1835 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1836 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1837 | |
1838 | #else | |
d9a5f180 GS |
1839 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1840 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1841 | #endif |
1842 | ||
1843 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1844 | that is a valid memory address for an instruction. | |
1845 | The MODE argument is the machine mode for the MEM expression | |
1846 | that wants to use this address. | |
1847 | ||
1848 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1849 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1850 | ||
1851 | See legitimize_pic_address in i386.c for details as to what | |
1852 | constitutes a legitimate address when -fpic is used. */ | |
1853 | ||
1854 | #define MAX_REGS_PER_ADDRESS 2 | |
1855 | ||
f996902d | 1856 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1857 | |
1858 | /* Nonzero if the constant value X is a legitimate general operand. | |
1859 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1860 | ||
f996902d | 1861 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1862 | |
3b3c6a3f MM |
1863 | #ifdef REG_OK_STRICT |
1864 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1865 | do { \ |
1866 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1867 | goto ADDR; \ |
d9a5f180 | 1868 | } while (0) |
c98f8742 | 1869 | |
3b3c6a3f MM |
1870 | #else |
1871 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1872 | do { \ |
1873 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1874 | goto ADDR; \ |
d9a5f180 | 1875 | } while (0) |
c98f8742 | 1876 | |
3b3c6a3f MM |
1877 | #endif |
1878 | ||
b949ea8b JW |
1879 | /* If defined, a C expression to determine the base term of address X. |
1880 | This macro is used in only one place: `find_base_term' in alias.c. | |
1881 | ||
1882 | It is always safe for this macro to not be defined. It exists so | |
1883 | that alias analysis can understand machine-dependent addresses. | |
1884 | ||
1885 | The typical use of this macro is to handle addresses containing | |
1886 | a label_ref or symbol_ref within an UNSPEC. */ | |
1887 | ||
d9a5f180 | 1888 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1889 | |
c98f8742 JVA |
1890 | /* Try machine-dependent ways of modifying an illegitimate address |
1891 | to be legitimate. If we find one, return the new, valid address. | |
1892 | This macro is used in only one place: `memory_address' in explow.c. | |
1893 | ||
1894 | OLDX is the address as it was before break_out_memory_refs was called. | |
1895 | In some cases it is useful to look at this to decide what needs to be done. | |
1896 | ||
1897 | MODE and WIN are passed so that this macro can use | |
1898 | GO_IF_LEGITIMATE_ADDRESS. | |
1899 | ||
1900 | It is always safe for this macro to do nothing. It exists to recognize | |
1901 | opportunities to optimize the output. | |
1902 | ||
1903 | For the 80386, we handle X+REG by loading X into a register R and | |
1904 | using R+REG. R will go in a general reg and indexing will be used. | |
1905 | However, if REG is a broken-out memory address or multiplication, | |
1906 | nothing needs to be done because REG can certainly go in a general reg. | |
1907 | ||
1908 | When -fpic is used, special handling is needed for symbolic references. | |
1909 | See comments by legitimize_pic_address in i386.c for details. */ | |
1910 | ||
3b3c6a3f | 1911 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
1912 | do { \ |
1913 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1914 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 1915 | goto WIN; \ |
d9a5f180 | 1916 | } while (0) |
c98f8742 JVA |
1917 | |
1918 | /* Nonzero if the constant value X is a legitimate general operand | |
fce5a9f2 | 1919 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1920 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1921 | ||
f996902d | 1922 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1923 | |
1924 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1925 | (GET_CODE (X) == SYMBOL_REF \ |
1926 | || GET_CODE (X) == LABEL_REF \ | |
1927 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
1928 | |
1929 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1930 | has an effect that depends on the machine mode it is used for. | |
1931 | On the 80386, only postdecrement and postincrement address depend thus | |
b9a76028 MS |
1932 | (the amount of decrement or increment being the length of the operand). |
1933 | These are now caught in recog.c. */ | |
1934 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
c98f8742 | 1935 | \f |
b08de47e MM |
1936 | /* Max number of args passed in registers. If this is more than 3, we will |
1937 | have problems with ebx (register #4), since it is a caller save register and | |
1938 | is also used as the pic register in ELF. So for now, don't allow more than | |
1939 | 3 registers to be passed in registers. */ | |
1940 | ||
d2836273 JH |
1941 | #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) |
1942 | ||
bcf17554 JH |
1943 | #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) |
1944 | ||
1945 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
b08de47e | 1946 | |
c98f8742 JVA |
1947 | \f |
1948 | /* Specify the machine mode that this machine uses | |
1949 | for the index in the tablejump instruction. */ | |
dc4d7240 JH |
1950 | #define CASE_VECTOR_MODE \ |
1951 | (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) | |
c98f8742 | 1952 | |
c98f8742 JVA |
1953 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1954 | #define DEFAULT_SIGNED_CHAR 1 | |
1955 | ||
1956 | /* Max number of bytes we can move from memory to memory | |
1957 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1958 | #define MOVE_MAX 16 |
1959 | ||
1960 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1961 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1962 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 1963 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 1964 | |
7e24ffc9 | 1965 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1966 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1967 | Increasing the value will always make code faster, but eventually |
1968 | incurs high cost in increased code size. | |
c98f8742 | 1969 | |
e2e52e1b | 1970 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1971 | |
e2e52e1b | 1972 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 | 1973 | |
45d78e7f JJ |
1974 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1975 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1976 | ||
979c67a5 | 1977 | #define CLEAR_RATIO (optimize_size ? 2 : MIN (6, ix86_cost->move_ratio)) |
45d78e7f | 1978 | |
c98f8742 JVA |
1979 | /* Define if shifts truncate the shift count |
1980 | which implies one can omit a sign-extension or zero-extension | |
1981 | of a shift count. */ | |
892a2d68 | 1982 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
1983 | |
1984 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1985 | ||
1986 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1987 | is done just by pretending it is already truncated. */ | |
1988 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1989 | ||
d9f32422 JH |
1990 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1991 | TYPE and which has the specified mode and signedness is to be | |
1992 | stored in a register. This macro is only called when TYPE is a | |
1993 | scalar type. | |
1994 | ||
f710504c | 1995 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1996 | quantities to SImode. The choice depends on target type. */ |
1997 | ||
1998 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1999 | do { \ |
d9f32422 JH |
2000 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
2001 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
2002 | (MODE) = SImode; \ |
2003 | } while (0) | |
d9f32422 | 2004 | |
c98f8742 JVA |
2005 | /* Specify the machine mode that pointers have. |
2006 | After generation of rtl, the compiler makes no further distinction | |
2007 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 2008 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
2009 | |
2010 | /* A function address in a call instruction | |
2011 | is a byte address (for indexing purposes) | |
2012 | so give the MEM rtx a byte's mode. */ | |
2013 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 2014 | \f |
96e7ae40 JH |
2015 | /* A C expression for the cost of moving data from a register in class FROM to |
2016 | one in class TO. The classes are expressed using the enumeration values | |
2017 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
2018 | interpreted relative to that. | |
d4ba09c0 | 2019 | |
96e7ae40 JH |
2020 | It is not required that the cost always equal 2 when FROM is the same as TO; |
2021 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 2022 | general registers. */ |
d4ba09c0 | 2023 | |
f84aa48a | 2024 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 2025 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
2026 | |
2027 | /* A C expression for the cost of moving data of mode M between a | |
2028 | register and memory. A value of 2 is the default; this cost is | |
2029 | relative to those in `REGISTER_MOVE_COST'. | |
2030 | ||
2031 | If moving between registers and memory is more expensive than | |
2032 | between two registers, you should define this macro to express the | |
fa79946e | 2033 | relative cost. */ |
d4ba09c0 | 2034 | |
d9a5f180 GS |
2035 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
2036 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
2037 | |
2038 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2039 | is the default; other values are interpreted relative to that. */ | |
2040 | ||
e075ae69 | 2041 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
2042 | |
2043 | /* Define this macro as a C expression which is nonzero if accessing | |
2044 | less than a word of memory (i.e. a `char' or a `short') is no | |
2045 | faster than accessing a word of memory, i.e., if such access | |
2046 | require more than one instruction or if there is no difference in | |
2047 | cost between byte and (aligned) word loads. | |
2048 | ||
2049 | When this macro is not defined, the compiler will access a field by | |
2050 | finding the smallest containing object; when it is defined, a | |
2051 | fullword load will be used if alignment permits. Unless bytes | |
2052 | accesses are faster than word accesses, using word accesses is | |
2053 | preferable since it may eliminate subsequent memory access if | |
2054 | subsequent accesses occur to other fields in the same word of the | |
2055 | structure, but to different bytes. */ | |
2056 | ||
2057 | #define SLOW_BYTE_ACCESS 0 | |
2058 | ||
2059 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2060 | #define SLOW_SHORT_ACCESS 0 | |
2061 | ||
d4ba09c0 SC |
2062 | /* Define this macro to be the value 1 if unaligned accesses have a |
2063 | cost many times greater than aligned accesses, for example if they | |
2064 | are emulated in a trap handler. | |
2065 | ||
9cd10576 KH |
2066 | When this macro is nonzero, the compiler will act as if |
2067 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2068 | moves. This can cause significantly more instructions to be |
9cd10576 | 2069 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2070 | accesses only add a cycle or two to the time for a memory access. |
2071 | ||
2072 | If the value of this macro is always zero, it need not be defined. */ | |
2073 | ||
e1565e65 | 2074 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 2075 | |
d4ba09c0 SC |
2076 | /* Define this macro if it is as good or better to call a constant |
2077 | function address than to call an address kept in a register. | |
2078 | ||
2079 | Desirable on the 386 because a CALL with a constant address is | |
2080 | faster than one with a register address. */ | |
2081 | ||
2082 | #define NO_FUNCTION_CSE | |
c98f8742 | 2083 | \f |
c572e5ba JVA |
2084 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2085 | return the mode to be used for the comparison. | |
2086 | ||
2087 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2088 | VOIDmode should be used in all other cases. |
c572e5ba | 2089 | |
16189740 | 2090 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2091 | possible, to allow for more combinations. */ |
c98f8742 | 2092 | |
d9a5f180 | 2093 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2094 | |
9cd10576 | 2095 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2096 | reversed. */ |
2097 | ||
2098 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2099 | ||
2100 | /* A C expression whose value is reversed condition code of the CODE for | |
2101 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2102 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2103 | |
c98f8742 JVA |
2104 | \f |
2105 | /* Control the assembler format that we output, to the extent | |
2106 | this does not vary between assemblers. */ | |
2107 | ||
2108 | /* How to refer to registers in assembler output. | |
892a2d68 | 2109 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2110 | |
a7b376ee | 2111 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2112 | For non floating point regs, the following are the HImode names. |
2113 | ||
2114 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
a55f4481 | 2115 | instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ |
c98f8742 | 2116 | |
a7180f70 BS |
2117 | #define HI_REGISTER_NAMES \ |
2118 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2119 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2120 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2121 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2122 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 JH |
2123 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
2124 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 2125 | |
c98f8742 JVA |
2126 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2127 | ||
2128 | /* Table of additional register names to use in user input. */ | |
2129 | ||
2130 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
2131 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2132 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
2133 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
2134 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 2135 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
21bf822e | 2136 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } |
c98f8742 JVA |
2137 | |
2138 | /* Note we are omitting these since currently I don't know how | |
2139 | to get gcc to use these, since they want the same but different | |
2140 | number as al, and ax. | |
2141 | */ | |
2142 | ||
c98f8742 | 2143 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2144 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2145 | |
2146 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2147 | of regs 0 through 3. */ |
c98f8742 JVA |
2148 | |
2149 | #define QI_HIGH_REGISTER_NAMES \ | |
2150 | {"ah", "dh", "ch", "bh", } | |
2151 | ||
2152 | /* How to renumber registers for dbx and gdb. */ | |
2153 | ||
d9a5f180 GS |
2154 | #define DBX_REGISTER_NUMBER(N) \ |
2155 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2156 | |
9a82e702 MS |
2157 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2158 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2159 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2160 | |
469ac993 JM |
2161 | /* Before the prologue, RA is at 0(%esp). */ |
2162 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2163 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2164 | |
e414ab29 | 2165 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2166 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2167 | ((COUNT) == 0 \ | |
2168 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2169 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2170 | |
892a2d68 | 2171 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2172 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2173 | |
a6ab3aad | 2174 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2175 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2176 | |
1020a5ab RH |
2177 | /* Describe how we implement __builtin_eh_return. */ |
2178 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2179 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2180 | ||
ad919812 | 2181 | |
e4c4ebeb RH |
2182 | /* Select a format to encode pointers in exception handling data. CODE |
2183 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2184 | true if the symbol may be affected by dynamic relocations. | |
2185 | ||
2186 | ??? All x86 object file formats are capable of representing this. | |
2187 | After all, the relocation needed is the same as for the call insn. | |
2188 | Whether or not a particular assembler allows us to enter such, I | |
2189 | guess we'll have to see. */ | |
d9a5f180 | 2190 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2191 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2192 | |
c98f8742 JVA |
2193 | /* This is how to output an insn to push a register on the stack. |
2194 | It need not be very fast code. */ | |
2195 | ||
d9a5f180 | 2196 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2197 | do { \ |
2198 | if (TARGET_64BIT) \ | |
2199 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2200 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2201 | else \ | |
2202 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2203 | } while (0) | |
c98f8742 JVA |
2204 | |
2205 | /* This is how to output an insn to pop a register from the stack. | |
2206 | It need not be very fast code. */ | |
2207 | ||
d9a5f180 | 2208 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2209 | do { \ |
2210 | if (TARGET_64BIT) \ | |
2211 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2212 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2213 | else \ | |
2214 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2215 | } while (0) | |
c98f8742 | 2216 | |
f88c65f7 | 2217 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2218 | |
2219 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2220 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2221 | |
f88c65f7 | 2222 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2223 | |
33f7f353 | 2224 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2225 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2226 | |
f7288899 EC |
2227 | /* Under some conditions we need jump tables in the text section, |
2228 | because the assembler cannot handle label differences between | |
2229 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2230 | |
2231 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2232 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2233 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2234 | |
cea3bd3e RH |
2235 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2236 | and switch back. For x86 we do this only to save a few bytes that | |
2237 | would otherwise be unused in the text section. */ | |
2238 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2239 | asm (SECTION_OP "\n\t" \ | |
2240 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2241 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 2242 | \f |
c98f8742 JVA |
2243 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2244 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
2245 | Effect of various CODE letters is described in i386.c near |
2246 | print_operand function. */ | |
c98f8742 | 2247 | |
d9a5f180 | 2248 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
c9d259cb | 2249 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') |
c98f8742 JVA |
2250 | |
2251 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
d9a5f180 | 2252 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
2253 | |
2254 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 2255 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 2256 | |
f996902d RH |
2257 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
2258 | do { \ | |
2259 | if (! output_addr_const_extra (FILE, (X))) \ | |
2260 | goto FAIL; \ | |
2261 | } while (0); | |
d4ba09c0 | 2262 | \f |
5bf0ebab RH |
2263 | /* Which processor to schedule for. The cpu attribute defines a list that |
2264 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
2265 | ||
2266 | enum processor_type | |
2267 | { | |
8383d43c | 2268 | PROCESSOR_I386 = 0, /* 80386 */ |
5bf0ebab RH |
2269 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2270 | PROCESSOR_PENTIUM, | |
2271 | PROCESSOR_PENTIUMPRO, | |
cfe1b18f | 2272 | PROCESSOR_GEODE, |
5bf0ebab RH |
2273 | PROCESSOR_K6, |
2274 | PROCESSOR_ATHLON, | |
2275 | PROCESSOR_PENTIUM4, | |
4977bab6 | 2276 | PROCESSOR_K8, |
89c43c0a | 2277 | PROCESSOR_NOCONA, |
05f85dbb | 2278 | PROCESSOR_CORE2, |
d326eaf0 JH |
2279 | PROCESSOR_GENERIC32, |
2280 | PROCESSOR_GENERIC64, | |
21efb4d4 | 2281 | PROCESSOR_AMDFAM10, |
5bf0ebab RH |
2282 | PROCESSOR_max |
2283 | }; | |
2284 | ||
9e555526 | 2285 | extern enum processor_type ix86_tune; |
5bf0ebab | 2286 | extern enum processor_type ix86_arch; |
5bf0ebab RH |
2287 | |
2288 | enum fpmath_unit | |
2289 | { | |
2290 | FPMATH_387 = 1, | |
2291 | FPMATH_SSE = 2 | |
2292 | }; | |
2293 | ||
2294 | extern enum fpmath_unit ix86_fpmath; | |
5bf0ebab | 2295 | |
f996902d RH |
2296 | enum tls_dialect |
2297 | { | |
2298 | TLS_DIALECT_GNU, | |
5bf5a10b | 2299 | TLS_DIALECT_GNU2, |
f996902d RH |
2300 | TLS_DIALECT_SUN |
2301 | }; | |
2302 | ||
2303 | extern enum tls_dialect ix86_tls_dialect; | |
f996902d | 2304 | |
6189a572 | 2305 | enum cmodel { |
5bf0ebab RH |
2306 | CM_32, /* The traditional 32-bit ABI. */ |
2307 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2308 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2309 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2310 | CM_LARGE, /* No assumptions. */ | |
7dcbf659 | 2311 | CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ |
dc4d7240 JH |
2312 | CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ |
2313 | CM_LARGE_PIC /* No assumptions. */ | |
6189a572 JH |
2314 | }; |
2315 | ||
5bf0ebab | 2316 | extern enum cmodel ix86_cmodel; |
5bf0ebab | 2317 | |
8362f420 JH |
2318 | /* Size of the RED_ZONE area. */ |
2319 | #define RED_ZONE_SIZE 128 | |
2320 | /* Reserved area of the red zone for temporaries. */ | |
2321 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
2322 | |
2323 | enum asm_dialect { | |
2324 | ASM_ATT, | |
2325 | ASM_INTEL | |
2326 | }; | |
5bf0ebab | 2327 | |
80f33d06 | 2328 | extern enum asm_dialect ix86_asm_dialect; |
95899b34 | 2329 | extern unsigned int ix86_preferred_stack_boundary; |
7dcbf659 | 2330 | extern int ix86_branch_cost, ix86_section_threshold; |
5bf0ebab RH |
2331 | |
2332 | /* Smallest class containing REGNO. */ | |
2333 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2334 | ||
d9a5f180 GS |
2335 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
2336 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
1ef45b77 | 2337 | extern rtx ix86_compare_emitted; |
22fb740d JH |
2338 | \f |
2339 | /* To properly truncate FP values into integers, we need to set i387 control | |
2340 | word. We can't emit proper mode switching code before reload, as spills | |
2341 | generated by reload may truncate values incorrectly, but we still can avoid | |
2342 | redundant computation of new control word by the mode switching pass. | |
2343 | The fldcw instructions are still emitted redundantly, but this is probably | |
2344 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2345 | the sequence. |
22fb740d JH |
2346 | |
2347 | The machinery is to emit simple truncation instructions and split them | |
2348 | before reload to instructions having USEs of two memory locations that | |
2349 | are filled by this code to old and new control word. | |
fce5a9f2 | 2350 | |
22fb740d JH |
2351 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2352 | needed. */ | |
2353 | ||
ff680eb1 UB |
2354 | enum ix86_entity |
2355 | { | |
2356 | I387_TRUNC = 0, | |
2357 | I387_FLOOR, | |
2358 | I387_CEIL, | |
2359 | I387_MASK_PM, | |
2360 | MAX_386_ENTITIES | |
2361 | }; | |
2362 | ||
1cba2b96 | 2363 | enum ix86_stack_slot |
ff680eb1 | 2364 | { |
80dcd3aa UB |
2365 | SLOT_VIRTUAL = 0, |
2366 | SLOT_TEMP, | |
ff680eb1 UB |
2367 | SLOT_CW_STORED, |
2368 | SLOT_CW_TRUNC, | |
2369 | SLOT_CW_FLOOR, | |
2370 | SLOT_CW_CEIL, | |
2371 | SLOT_CW_MASK_PM, | |
2372 | MAX_386_STACK_LOCALS | |
2373 | }; | |
22fb740d JH |
2374 | |
2375 | /* Define this macro if the port needs extra instructions inserted | |
2376 | for mode switching in an optimizing compilation. */ | |
2377 | ||
ff680eb1 UB |
2378 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2379 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2380 | |
2381 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2382 | initializer for an array of integers. Each initializer element N | |
2383 | refers to an entity that needs mode switching, and specifies the | |
2384 | number of different modes that might need to be set for this | |
2385 | entity. The position of the initializer in the initializer - | |
2386 | starting counting at zero - determines the integer that is used to | |
2387 | refer to the mode-switched entity in question. */ | |
2388 | ||
ff680eb1 UB |
2389 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2390 | { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
22fb740d JH |
2391 | |
2392 | /* ENTITY is an integer specifying a mode-switched entity. If | |
2393 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2394 | return an integer value not larger than the corresponding element | |
2395 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
ff680eb1 UB |
2396 | must be switched into prior to the execution of INSN. */ |
2397 | ||
2398 | #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
22fb740d JH |
2399 | |
2400 | /* This macro specifies the order in which modes for ENTITY are | |
2401 | processed. 0 is the highest priority. */ | |
2402 | ||
d9a5f180 | 2403 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
2404 | |
2405 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2406 | is the set of hard registers live at the point where the insn(s) | |
2407 | are to be inserted. */ | |
2408 | ||
2409 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
1d1df0df | 2410 | ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ |
ff680eb1 | 2411 | ? emit_i387_cw_initialization (MODE), 0 \ |
22fb740d | 2412 | : 0) |
ff680eb1 | 2413 | |
0f0138b6 JH |
2414 | \f |
2415 | /* Avoid renaming of stack registers, as doing so in combination with | |
2416 | scheduling just increases amount of live registers at time and in | |
2417 | the turn amount of fxch instructions needed. | |
2418 | ||
43f3a59d | 2419 | ??? Maybe Pentium chips benefits from renaming, someone can try.... */ |
0f0138b6 | 2420 | |
d9a5f180 | 2421 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
fb84c7a0 | 2422 | (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) |
22fb740d | 2423 | |
3b3c6a3f | 2424 | \f |
e91f04de | 2425 | #define FASTCALL_PREFIX '@' |
fa1a0d02 JH |
2426 | \f |
2427 | struct machine_function GTY(()) | |
2428 | { | |
2429 | struct stack_local_entry *stack_locals; | |
2430 | const char *some_ld_name; | |
150cdc9e | 2431 | rtx force_align_arg_pointer; |
fa1a0d02 JH |
2432 | int save_varrargs_registers; |
2433 | int accesses_prev_frame; | |
ff680eb1 | 2434 | int optimize_mode_switching[MAX_386_ENTITIES]; |
d9b40e8d JH |
2435 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to |
2436 | determine the style used. */ | |
2437 | int use_fast_prologue_epilogue; | |
d7394366 JH |
2438 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed |
2439 | for. */ | |
2440 | int use_fast_prologue_epilogue_nregs; | |
5bf5a10b AO |
2441 | /* If true, the current function needs the default PIC register, not |
2442 | an alternate register (on x86) and must not use the red zone (on | |
2443 | x86_64), even if it's a leaf function. We don't want the | |
2444 | function to be regarded as non-leaf because TLS calls need not | |
2445 | affect register allocation. This flag is set when a TLS call | |
2446 | instruction is expanded within a function, and never reset, even | |
2447 | if all such instructions are optimized away. Use the | |
2448 | ix86_current_function_calls_tls_descriptor macro for a better | |
2449 | approximation. */ | |
2450 | int tls_descriptor_call_expanded_p; | |
fa1a0d02 JH |
2451 | }; |
2452 | ||
2453 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
2454 | #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) | |
2455 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
5bf5a10b AO |
2456 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2457 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2458 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2459 | calls are optimized away, we try to detect cases in which it was | |
2460 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2461 | verify whether there's any such instruction live by testing that | |
2462 | REG_SP is live. */ | |
2463 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2464 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
249e6b63 | 2465 | |
1bc7c5b6 ZW |
2466 | /* Control behavior of x86_file_start. */ |
2467 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2468 | #define X86_FILE_START_FLTUSED false | |
2469 | ||
7dcbf659 JH |
2470 | /* Flag to mark data that is in the large address area. */ |
2471 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2472 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2473 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2474 | |
2475 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2476 | have defined always, to avoid ifdefing. */ | |
2477 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2478 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2479 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2480 | ||
2481 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2482 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2483 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2484 | ||
e70444a8 HJ |
2485 | /* Model costs for vectorizer. */ |
2486 | ||
2487 | /* Cost of conditional branch. */ | |
2488 | #undef TARG_COND_BRANCH_COST | |
2489 | #define TARG_COND_BRANCH_COST ix86_cost->branch_cost | |
2490 | ||
2491 | /* Cost of any scalar operation, excluding load and store. */ | |
2492 | #undef TARG_SCALAR_STMT_COST | |
2493 | #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost | |
2494 | ||
2495 | /* Cost of scalar load. */ | |
2496 | #undef TARG_SCALAR_LOAD_COST | |
2497 | #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost | |
2498 | ||
2499 | /* Cost of scalar store. */ | |
2500 | #undef TARG_SCALAR_STORE_COST | |
2501 | #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost | |
2502 | ||
2503 | /* Cost of any vector operation, excluding load, store or vector to scalar | |
4f3f76e6 | 2504 | operation. */ |
e70444a8 HJ |
2505 | #undef TARG_VEC_STMT_COST |
2506 | #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost | |
2507 | ||
2508 | /* Cost of vector to scalar operation. */ | |
2509 | #undef TARG_VEC_TO_SCALAR_COST | |
2510 | #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost | |
2511 | ||
2512 | /* Cost of scalar to vector operation. */ | |
2513 | #undef TARG_SCALAR_TO_VEC_COST | |
2514 | #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost | |
2515 | ||
2516 | /* Cost of aligned vector load. */ | |
2517 | #undef TARG_VEC_LOAD_COST | |
2518 | #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost | |
2519 | ||
2520 | /* Cost of misaligned vector load. */ | |
2521 | #undef TARG_VEC_UNALIGNED_LOAD_COST | |
2522 | #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost | |
2523 | ||
2524 | /* Cost of vector store. */ | |
2525 | #undef TARG_VEC_STORE_COST | |
2526 | #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost | |
2527 | ||
2528 | /* Cost of conditional taken branch for vectorizer cost model. */ | |
2529 | #undef TARG_COND_TAKEN_BRANCH_COST | |
2530 | #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost | |
2531 | ||
2532 | /* Cost of conditional not taken branch for vectorizer cost model. */ | |
2533 | #undef TARG_COND_NOT_TAKEN_BRANCH_COST | |
2534 | #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost | |
2535 | ||
c98f8742 JVA |
2536 | /* |
2537 | Local variables: | |
2538 | version-control: t | |
2539 | End: | |
2540 | */ |