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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
83ffe9cd | 2 | Copyright (C) 1988-2023 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
1751bec0 ML |
42 | #define TARGET_CMPXCHG16B TARGET_CX16 |
43 | #define TARGET_CMPXCHG16B_P(x) TARGET_CX16_P(x) | |
41a4ef22 | 44 | |
1751bec0 | 45 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 46 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
1751bec0 ML |
47 | #define TARGET_X32 TARGET_ABI_X32 |
48 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) | |
49 | #define TARGET_16BIT TARGET_CODE16 | |
d5d618b5 | 50 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) |
04e1d06b | 51 | |
dfa61b9e L |
52 | #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) |
53 | ||
26b5109f RS |
54 | #include "config/vxworks-dummy.h" |
55 | ||
7eb68c06 | 56 | #include "config/i386/i386-opts.h" |
ccf8e764 | 57 | |
c69fa2d4 | 58 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 59 | |
8c996513 JH |
60 | /* Specify what algorithm to use for stringops on known size. |
61 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
62 | known at compile time or estimated via feedback, the SIZE array | |
63 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 64 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
65 | When NOALIGN is true the code guaranting the alignment of the memory |
66 | block is skipped. | |
67 | ||
8c996513 | 68 | For example initializer: |
4f3f76e6 | 69 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 70 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 71 | be used otherwise. */ |
8c996513 JH |
72 | struct stringop_algs |
73 | { | |
74 | const enum stringop_alg unknown_size; | |
75 | const struct stringop_strategy { | |
f99f6eb5 IS |
76 | /* Several older compilers delete the default constructor because of the |
77 | const entries (see PR100246). Manually specifying a CTOR works around | |
78 | this issue. Since this header is used by code compiled with the C | |
79 | compiler we must guard the addition. */ | |
80 | #ifdef __cplusplus | |
858d7ee1 JJ |
81 | constexpr |
82 | stringop_strategy (int _max = -1, enum stringop_alg _alg = libcall, | |
83 | int _noalign = false) | |
f99f6eb5 IS |
84 | : max (_max), alg (_alg), noalign (_noalign) {} |
85 | #endif | |
8c996513 JH |
86 | const int max; |
87 | const enum stringop_alg alg; | |
340ef734 | 88 | int noalign; |
c69fa2d4 | 89 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
90 | }; |
91 | ||
f8977166 RS |
92 | /* Analog of COSTS_N_INSNS when optimizing for size. */ |
93 | #ifndef COSTS_N_BYTES | |
94 | #define COSTS_N_BYTES(N) ((N) * 2) | |
95 | #endif | |
96 | ||
d321551c L |
97 | /* Define the specific costs for a given cpu. NB: hard_register is used |
98 | by TARGET_REGISTER_MOVE_COST and TARGET_MEMORY_MOVE_COST to compute | |
99 | hard register move costs by register allocator. Relative costs of | |
100 | pseudo register load and store versus pseudo register moves in RTL | |
101 | expressions for TARGET_RTX_COSTS can be different from relative | |
102 | costs of hard registers to get the most efficient operations with | |
103 | pseudo registers. */ | |
d4ba09c0 SC |
104 | |
105 | struct processor_costs { | |
d321551c L |
106 | /* Costs used by register allocator. integer->integer register move |
107 | cost is 2. */ | |
108 | struct | |
109 | { | |
110 | const int movzbl_load; /* cost of loading using movzbl */ | |
111 | const int int_load[3]; /* cost of loading integer registers | |
112 | in QImode, HImode and SImode relative | |
113 | to reg-reg move (2). */ | |
114 | const int int_store[3]; /* cost of storing integer register | |
115 | in QImode, HImode and SImode */ | |
116 | const int fp_move; /* cost of reg,reg fld/fst */ | |
117 | const int fp_load[3]; /* cost of loading FP register | |
118 | in SFmode, DFmode and XFmode */ | |
119 | const int fp_store[3]; /* cost of storing FP register | |
120 | in SFmode, DFmode and XFmode */ | |
121 | const int mmx_move; /* cost of moving MMX register. */ | |
122 | const int mmx_load[2]; /* cost of loading MMX register | |
123 | in SImode and DImode */ | |
124 | const int mmx_store[2]; /* cost of storing MMX register | |
125 | in SImode and DImode */ | |
126 | const int xmm_move; /* cost of moving XMM register. */ | |
127 | const int ymm_move; /* cost of moving XMM register. */ | |
128 | const int zmm_move; /* cost of moving XMM register. */ | |
129 | const int sse_load[5]; /* cost of loading SSE register | |
130 | in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
131 | const int sse_store[5]; /* cost of storing SSE register | |
132 | in SImode, DImode and TImode. */ | |
133 | const int sse_to_integer; /* cost of moving SSE register to integer. */ | |
134 | const int integer_to_sse; /* cost of moving integer register to SSE. */ | |
00cb3494 L |
135 | const int mask_to_integer; /* cost of moving mask register to integer. */ |
136 | const int integer_to_mask; /* cost of moving integer register to mask. */ | |
137 | const int mask_load[3]; /* cost of loading mask registers | |
138 | in QImode, HImode and SImode. */ | |
139 | const int mask_store[3]; /* cost of storing mask register | |
140 | in QImode, HImode and SImode. */ | |
141 | const int mask_move; /* cost of moving mask register. */ | |
d321551c L |
142 | } hard_register; |
143 | ||
8b60264b KG |
144 | const int add; /* cost of an add instruction */ |
145 | const int lea; /* cost of a lea instruction */ | |
146 | const int shift_var; /* variable shift costs */ | |
147 | const int shift_const; /* constant shift costs */ | |
f676971a | 148 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 149 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 150 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 151 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 152 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
153 | int movsx; /* The cost of movsx operation. */ |
154 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
155 | const int large_insn; /* insns larger than this cost more */ |
156 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 157 | memory-to-memory move insns. */ |
25e22b19 L |
158 | const int clear_ratio; /* The threshold of number of scalar |
159 | memory clearing insns. */ | |
8b60264b | 160 | const int int_load[3]; /* cost of loading integer registers |
96e7ae40 JH |
161 | in QImode, HImode and SImode relative |
162 | to reg-reg move (2). */ | |
8b60264b | 163 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 164 | in QImode, HImode and SImode */ |
df41dbaf JH |
165 | const int sse_load[5]; /* cost of loading SSE register |
166 | in 32bit, 64bit, 128bit, 256bit and 512bit */ | |
df41dbaf | 167 | const int sse_store[5]; /* cost of storing SSE register |
d321551c L |
168 | in 32bit, 64bit, 128bit, 256bit and 512bit */ |
169 | const int sse_unaligned_load[5];/* cost of unaligned load. */ | |
df41dbaf | 170 | const int sse_unaligned_store[5];/* cost of unaligned store. */ |
d321551c L |
171 | const int xmm_move, ymm_move, /* cost of moving XMM and YMM register. */ |
172 | zmm_move; | |
66574c53 | 173 | const int sse_to_integer; /* cost of moving SSE register to integer. */ |
a4fe6139 JH |
174 | const int gather_static, gather_per_elt; /* Cost of gather load is computed |
175 | as static + per_item * nelts. */ | |
176 | const int scatter_static, scatter_per_elt; /* Cost of gather store is | |
177 | computed as static + per_item * nelts. */ | |
46cb0441 ZD |
178 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
179 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
180 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
181 | const int simultaneous_prefetches; /* number of parallel prefetch | |
182 | operations. */ | |
4977bab6 | 183 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
184 | const int fadd; /* cost of FADD and FSUB instructions. */ |
185 | const int fmul; /* cost of FMUL instruction. */ | |
186 | const int fdiv; /* cost of FDIV instruction. */ | |
187 | const int fabs; /* cost of FABS instruction. */ | |
188 | const int fchs; /* cost of FCHS instruction. */ | |
189 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 190 | /* Specify what algorithm |
bee51209 | 191 | to use for stringops on unknown size. */ |
c53c148c | 192 | const int sse_op; /* cost of cheap SSE instruction. */ |
6065f444 JH |
193 | const int addss; /* cost of ADDSS/SD SUBSS/SD instructions. */ |
194 | const int mulss; /* cost of MULSS instructions. */ | |
195 | const int mulsd; /* cost of MULSD instructions. */ | |
c53c148c JH |
196 | const int fmass; /* cost of FMASS instructions. */ |
197 | const int fmasd; /* cost of FMASD instructions. */ | |
6065f444 JH |
198 | const int divss; /* cost of DIVSS instructions. */ |
199 | const int divsd; /* cost of DIVSD instructions. */ | |
200 | const int sqrtss; /* cost of SQRTSS instructions. */ | |
201 | const int sqrtsd; /* cost of SQRTSD instructions. */ | |
a813c280 JH |
202 | const int reassoc_int, reassoc_fp, reassoc_vec_int, reassoc_vec_fp; |
203 | /* Specify reassociation width for integer, | |
204 | fp, vector integer and vector fp | |
205 | operations. Generally should correspond | |
206 | to number of instructions executed in | |
207 | parallel. See also | |
208 | ix86_reassociation_width. */ | |
ad83025e | 209 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
210 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer |
211 | cost model. */ | |
212 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
213 | vectorizer cost model. */ | |
7dc58b50 ML |
214 | |
215 | /* The "0:0:8" label alignment specified for some processors generates | |
216 | secondary 8-byte alignment only for those label/jump/loop targets | |
217 | which have primary alignment. */ | |
218 | const char *const align_loop; /* Loop alignment. */ | |
219 | const char *const align_jump; /* Jump alignment. */ | |
220 | const char *const align_label; /* Label alignment. */ | |
221 | const char *const align_func; /* Function alignment. */ | |
071e428c HW |
222 | |
223 | const unsigned small_unroll_ninsns; /* Insn count limit for small loop | |
224 | to be unrolled. */ | |
225 | const unsigned small_unroll_factor; /* Unroll factor for small loop to | |
226 | be unrolled. */ | |
d4ba09c0 SC |
227 | }; |
228 | ||
8b60264b | 229 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
230 | extern const struct processor_costs ix86_size_cost; |
231 | ||
232 | #define ix86_cur_cost() \ | |
233 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 234 | |
c98f8742 JVA |
235 | /* Macros used in the machine description to test the flags. */ |
236 | ||
b97de419 | 237 | /* configure can arrange to change it. */ |
e075ae69 | 238 | |
35b528be | 239 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 240 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 241 | #endif |
35b528be | 242 | |
004d3859 GK |
243 | #ifndef TARGET_FPMATH_DEFAULT |
244 | #define TARGET_FPMATH_DEFAULT \ | |
245 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
246 | #endif | |
247 | ||
bf7b5747 ST |
248 | #ifndef TARGET_FPMATH_DEFAULT_P |
249 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
250 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
251 | #endif | |
252 | ||
c207fd99 L |
253 | /* If the i387 is disabled or -miamcu is used , then do not return |
254 | values in it. */ | |
255 | #define TARGET_FLOAT_RETURNS_IN_80387 \ | |
256 | (TARGET_FLOAT_RETURNS && TARGET_80387 && !TARGET_IAMCU) | |
257 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) \ | |
258 | (TARGET_FLOAT_RETURNS_P(x) && TARGET_80387_P(x) && !TARGET_IAMCU_P(x)) | |
b08de47e | 259 | |
5791cc29 JT |
260 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
261 | compile-time constant. */ | |
262 | #ifdef IN_LIBGCC2 | |
6ac49599 | 263 | #undef TARGET_64BIT |
5791cc29 JT |
264 | #ifdef __x86_64__ |
265 | #define TARGET_64BIT 1 | |
266 | #else | |
267 | #define TARGET_64BIT 0 | |
268 | #endif | |
269 | #else | |
6ac49599 RS |
270 | #ifndef TARGET_BI_ARCH |
271 | #undef TARGET_64BIT | |
e49080ec | 272 | #undef TARGET_64BIT_P |
67adf6a9 | 273 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 274 | #define TARGET_64BIT 1 |
e49080ec | 275 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
276 | #else |
277 | #define TARGET_64BIT 0 | |
e49080ec | 278 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
279 | #endif |
280 | #endif | |
5791cc29 | 281 | #endif |
25f94bb5 | 282 | |
750054a2 CT |
283 | #define HAS_LONG_COND_BRANCH 1 |
284 | #define HAS_LONG_UNCOND_BRANCH 1 | |
285 | ||
f23881fc | 286 | #define TARGET_CPU_P(CPU) (ix86_tune == PROCESSOR_ ## CPU) |
a269a03c | 287 | |
80fd744f RH |
288 | /* Feature tests against the various tunings. */ |
289 | enum ix86_tune_indices { | |
4b8bc035 | 290 | #undef DEF_TUNE |
3ad20bd4 | 291 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
292 | #include "x86-tune.def" |
293 | #undef DEF_TUNE | |
294 | X86_TUNE_LAST | |
80fd744f RH |
295 | }; |
296 | ||
ab442df7 | 297 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
298 | |
299 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
300 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
301 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
302 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 303 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
304 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
305 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
306 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
307 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
308 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
309 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
310 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
311 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
312 | #define TARGET_LCP_STALL \ |
313 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
314 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
315 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
316 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
317 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
318 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
319 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
320 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
321 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
322 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
323 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
324 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
bf24f4ec L |
325 | #define TARGET_PREFER_KNOWN_REP_MOVSB_STOSB \ |
326 | ix86_tune_features[X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB] | |
5783ad0e UB |
327 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
328 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
329 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
330 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
331 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
332 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
333 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
334 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
335 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
336 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
337 | #define TARGET_INTEGER_DFMODE_MOVES \ |
338 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
339 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
340 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
341 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
342 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
48b3caff L |
343 | #define TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY \ |
344 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY] | |
345 | #define TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY \ | |
346 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY] | |
1133125e HJ |
347 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
348 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
349 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
350 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
351 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
352 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
353 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
354 | #define TARGET_SSE_TYPELESS_STORES \ | |
355 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
356 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
357 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
358 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
359 | #define TARGET_PROLOGUE_USING_MOVE \ | |
360 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
361 | #define TARGET_EPILOGUE_USING_MOVE \ | |
362 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
363 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
364 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
365 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
366 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
367 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
368 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
369 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 370 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
371 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
372 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
373 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
374 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
375 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
376 | #define TARGET_PAD_SHORT_FUNCTION \ |
377 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
378 | #define TARGET_EXT_80387_CONSTANTS \ |
379 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
380 | #define TARGET_AVOID_VECTOR_DECODE \ |
381 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
382 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
383 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
384 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
385 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
386 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
387 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
388 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
389 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
390 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
391 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
392 | #define TARGET_USE_VECTOR_CONVERTS \ |
393 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
394 | #define TARGET_SLOW_PSHUFB \ |
395 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
8e0dc054 JJ |
396 | #define TARGET_AVOID_4BYTE_PREFIXES \ |
397 | ix86_tune_features[X86_TUNE_AVOID_4BYTE_PREFIXES] | |
87126675 JH |
398 | #define TARGET_USE_GATHER_2PARTS \ |
399 | ix86_tune_features[X86_TUNE_USE_GATHER_2PARTS] | |
400 | #define TARGET_USE_GATHER_4PARTS \ | |
401 | ix86_tune_features[X86_TUNE_USE_GATHER_4PARTS] | |
f6aa5171 JH |
402 | #define TARGET_USE_GATHER \ |
403 | ix86_tune_features[X86_TUNE_USE_GATHER] | |
0dc41f28 WM |
404 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
405 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
406 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
407 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 408 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
409 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
410 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
411 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
412 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
413 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
414 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 415 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
416 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
417 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
5d0878e7 JH |
418 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
419 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
586bbef1 HL |
420 | #define TARGET_AVX256_SPLIT_REGS \ |
421 | ix86_tune_features[X86_TUNE_AVX256_SPLIT_REGS] | |
eef81eef JH |
422 | #define TARGET_AVX512_SPLIT_REGS \ |
423 | ix86_tune_features[X86_TUNE_AVX512_SPLIT_REGS] | |
55a2c322 VM |
424 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
425 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
426 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
427 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 428 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 429 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
430 | #define TARGET_ADJUST_UNROLL \ |
431 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
374f5bf8 UB |
432 | #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ |
433 | ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
ca90b1ed YR |
434 | #define TARGET_ONE_IF_CONV_INSN \ |
435 | ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] | |
3c5e83d5 | 436 | #define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE] |
348188bf L |
437 | #define TARGET_EMIT_VZEROUPPER \ |
438 | ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] | |
da86c5af HW |
439 | #define TARGET_EXPAND_ABS \ |
440 | ix86_tune_features[X86_TUNE_EXPAND_ABS] | |
97d51c17 | 441 | #define TARGET_V2DF_REDUCTION_PREFER_HADDPD \ |
442 | ix86_tune_features[X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD] | |
1c257558 | 443 | #define TARGET_DEST_FALSE_DEP_FOR_GLC \ |
444 | ix86_tune_features[X86_TUNE_DEST_FALSE_DEP_FOR_GLC] | |
df7b0cc4 | 445 | |
80fd744f RH |
446 | /* Feature tests against the various architecture variations. */ |
447 | enum ix86_arch_indices { | |
cef31f9c | 448 | X86_ARCH_CMOV, |
80fd744f RH |
449 | X86_ARCH_CMPXCHG, |
450 | X86_ARCH_CMPXCHG8B, | |
451 | X86_ARCH_XADD, | |
452 | X86_ARCH_BSWAP, | |
453 | ||
454 | X86_ARCH_LAST | |
455 | }; | |
4f3f76e6 | 456 | |
ab442df7 | 457 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 458 | |
cef31f9c | 459 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
460 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
461 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
462 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
463 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
464 | ||
cef31f9c UB |
465 | /* For sane SSE instruction set generation we need fcomi instruction. |
466 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
467 | expands to a sequence that includes conditional move. */ | |
468 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
469 | ||
80fd744f RH |
470 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
471 | ||
08a4adcf UB |
472 | extern unsigned char ix86_prefetch_sse; |
473 | #define TARGET_PREFETCH_SSE ix86_prefetch_sse | |
80fd744f | 474 | |
80fd744f RH |
475 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
476 | ||
477 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
478 | #define TARGET_MIX_SSE_I387 \ | |
479 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
480 | ||
5fa578f0 UB |
481 | #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) |
482 | #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) | |
483 | #define TARGET_HARD_XF_REGS (TARGET_80387) | |
484 | ||
80fd744f RH |
485 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
486 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
487 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 488 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 489 | |
67adf6a9 RH |
490 | #ifndef TARGET_64BIT_DEFAULT |
491 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 492 | #endif |
74dc3e94 RH |
493 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
494 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
495 | #endif | |
25f94bb5 | 496 | |
e0ea8797 AH |
497 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
498 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
499 | ||
79f5e442 ZD |
500 | /* Fence to use after loop using storent. */ |
501 | ||
d243f400 | 502 | extern GTY(()) tree x86_mfence; |
79f5e442 ZD |
503 | #define FENCE_FOLLOWING_MOVNT x86_mfence |
504 | ||
0ed4a390 JL |
505 | /* Once GDB has been enhanced to deal with functions without frame |
506 | pointers, we can change this to allow for elimination of | |
507 | the frame pointer in leaf functions. */ | |
508 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 509 | |
0a1c5e55 UB |
510 | /* Extra bits to force. */ |
511 | #define TARGET_SUBTARGET_DEFAULT 0 | |
512 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
513 | ||
514 | /* Extra bits to force on w/ 32-bit mode. */ | |
515 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
516 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
517 | ||
ccf8e764 RH |
518 | /* Extra bits to force on w/ 64-bit mode. */ |
519 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
8b131a8a UB |
520 | /* Enable MMX, SSE and SSE2 by default. */ |
521 | #define TARGET_SUBTARGET64_ISA_DEFAULT \ | |
522 | (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2) | |
ccf8e764 | 523 | |
fee3eacd IS |
524 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
525 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 526 | #define TARGET_MACHO 0 |
d308419c | 527 | #define TARGET_MACHO_SYMBOL_STUBS 0 |
fee3eacd IS |
528 | #define MACHOPIC_ATT_STUB 0 |
529 | /* (b) Macros defined in config/darwin.h */ | |
530 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
531 | #define MACHOPIC_INDIRECT 0 | |
532 | #define MACHOPIC_PURE 0 | |
9005471b | 533 | |
5a579c3b LE |
534 | /* For the RDOS */ |
535 | #define TARGET_RDOS 0 | |
536 | ||
9005471b | 537 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
538 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
539 | ||
6510e8bb KT |
540 | /* For the Windows 32-bit ABI. */ |
541 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
542 | ||
f81c9774 RH |
543 | /* This is re-defined by cygming.h. */ |
544 | #define TARGET_SEH 0 | |
545 | ||
51212b32 | 546 | /* The default abi used by target. */ |
7c800926 | 547 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 548 | |
b8b3f0ca | 549 | /* The default TLS segment register used by target. */ |
00402c94 RH |
550 | #define DEFAULT_TLS_SEG_REG \ |
551 | (TARGET_64BIT ? ADDR_SPACE_SEG_FS : ADDR_SPACE_SEG_GS) | |
b8b3f0ca | 552 | |
cc69336f RH |
553 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
554 | with the rounding mode forced to 53 bits. */ | |
555 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
556 | ||
98ae96d2 PB |
557 | #ifndef SUBTARGET_DRIVER_SELF_SPECS |
558 | # define SUBTARGET_DRIVER_SELF_SPECS "" | |
559 | #endif | |
560 | ||
561 | #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS | |
562 | ||
682cd442 GK |
563 | /* -march=native handling only makes sense with compiler running on |
564 | an x86 or x86_64 chip. If changing this condition, also change | |
e53b6e56 | 565 | the condition in driver-i386.cc. */ |
682cd442 | 566 | #if defined(__i386__) || defined(__x86_64__) |
e53b6e56 | 567 | /* In driver-i386.cc. */ |
fa959ce4 MM |
568 | extern const char *host_detect_local_cpu (int argc, const char **argv); |
569 | #define EXTRA_SPEC_FUNCTIONS \ | |
570 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 571 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
572 | #endif |
573 | ||
8981c15b JM |
574 | #if TARGET_64BIT_DEFAULT |
575 | #define OPT_ARCH64 "!m32" | |
576 | #define OPT_ARCH32 "m32" | |
577 | #else | |
f0ea7581 L |
578 | #define OPT_ARCH64 "m64|mx32" |
579 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
580 | #endif |
581 | ||
1cba2b96 EC |
582 | /* Support for configure-time defaults of some command line options. |
583 | The order here is important so that -march doesn't squash the | |
584 | tune or cpu values. */ | |
ce998900 | 585 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 586 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
587 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
588 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 589 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
590 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
591 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
592 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
593 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
594 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 595 | |
241e1a89 SC |
596 | /* Specs for the compiler proper */ |
597 | ||
628714d8 | 598 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 599 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 600 | |
682cd442 | 601 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
602 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
603 | #else | |
cc11b924 | 604 | #define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}" |
fa959ce4 | 605 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ |
cc11b924 L |
606 | "%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \ |
607 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \ | |
608 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}" | |
fa959ce4 | 609 | #endif |
241e1a89 | 610 | #endif |
c98f8742 | 611 | \f |
30efe578 | 612 | /* Target CPU builtins. */ |
ab442df7 MM |
613 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
614 | ||
615 | /* Target Pragmas. */ | |
616 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 617 | |
628714d8 | 618 | #ifndef CC1_SPEC |
8015b78d | 619 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
620 | #endif |
621 | ||
622 | /* This macro defines names of additional specifications to put in the | |
623 | specs that can be used in various specifications like CC1_SPEC. Its | |
624 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
625 | |
626 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 627 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
628 | program. |
629 | ||
630 | Do not define this macro if it does not need to do anything. */ | |
631 | ||
632 | #ifndef SUBTARGET_EXTRA_SPECS | |
633 | #define SUBTARGET_EXTRA_SPECS | |
634 | #endif | |
635 | ||
636 | #define EXTRA_SPECS \ | |
628714d8 | 637 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
638 | SUBTARGET_EXTRA_SPECS |
639 | \f | |
ce998900 | 640 | |
8ce94e44 JM |
641 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
642 | SFmode, DFmode and XFmode) in the current excess precision | |
643 | configuration. */ | |
b8cab8a5 | 644 | #define X87_ENABLE_ARITH(MODE) \ |
e401db7b JJ |
645 | (ix86_unsafe_math_optimizations \ |
646 | || ix86_excess_precision == EXCESS_PRECISION_FAST \ | |
b8cab8a5 | 647 | || (MODE) == XFmode) |
8ce94e44 JM |
648 | |
649 | /* Likewise, whether to allow direct conversions from integer mode | |
650 | IMODE (HImode, SImode or DImode) to MODE. */ | |
651 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
e401db7b JJ |
652 | (ix86_unsafe_math_optimizations \ |
653 | || ix86_excess_precision == EXCESS_PRECISION_FAST \ | |
8ce94e44 JM |
654 | || (MODE) == XFmode \ |
655 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
656 | || (IMODE) == HImode) | |
657 | ||
979c67a5 UB |
658 | /* target machine storage layout */ |
659 | ||
65d9c0ab JH |
660 | #define SHORT_TYPE_SIZE 16 |
661 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
662 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
663 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 664 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 665 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 666 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
667 | #define LONG_DOUBLE_TYPE_SIZE \ |
668 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 669 | |
c637141a | 670 | #define WIDEST_HARDWARE_FP_SIZE 80 |
65d9c0ab | 671 | |
67adf6a9 | 672 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 673 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
674 | #else |
675 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
676 | #endif |
677 | ||
c98f8742 JVA |
678 | /* Define this if most significant byte of a word is the lowest numbered. */ |
679 | /* That is true on the 80386. */ | |
680 | ||
681 | #define BITS_BIG_ENDIAN 0 | |
682 | ||
683 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
684 | /* That is not true on the 80386. */ | |
685 | #define BYTES_BIG_ENDIAN 0 | |
686 | ||
687 | /* Define this if most significant word of a multiword number is the lowest | |
688 | numbered. */ | |
689 | /* Not true for 80386 */ | |
690 | #define WORDS_BIG_ENDIAN 0 | |
691 | ||
c98f8742 | 692 | /* Width of a word, in units (bytes). */ |
4ae8027b | 693 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
694 | |
695 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
696 | #define MIN_UNITS_PER_WORD 4 |
697 | #endif | |
c98f8742 | 698 | |
c98f8742 | 699 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 700 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 701 | |
e075ae69 | 702 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
bd5d3961 | 703 | #define STACK_BOUNDARY (TARGET_64BIT_MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 704 | |
2e3f842f L |
705 | /* Stack boundary of the main function guaranteed by OS. */ |
706 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
707 | ||
de1132d1 | 708 | /* Minimum stack boundary. */ |
cba9c789 | 709 | #define MIN_STACK_BOUNDARY BITS_PER_WORD |
2e3f842f | 710 | |
d1f87653 | 711 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 712 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 713 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 714 | |
de1132d1 | 715 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
716 | both 32bit and 64bit, to support codes that need 128 bit stack |
717 | alignment for SSE instructions, but can't realign the stack. */ | |
d9063947 L |
718 | #define PREFERRED_STACK_BOUNDARY_DEFAULT \ |
719 | (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) | |
2e3f842f L |
720 | |
721 | /* 1 if -mstackrealign should be turned on by default. It will | |
722 | generate an alternate prologue and epilogue that realigns the | |
723 | runtime stack if nessary. This supports mixing codes that keep a | |
724 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 725 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
726 | #define STACK_REALIGN_DEFAULT 0 |
727 | ||
728 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
729 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 730 | |
a2851b75 TG |
731 | /* According to Windows x64 software convention, the maximum stack allocatable |
732 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
733 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
734 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
735 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
736 | prologue. | |
737 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 738 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
739 | regs, then save them, and then allocate the remaining. There is no SEH |
740 | unwind info for this later allocation. */ | |
741 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
742 | ||
ebff937c SH |
743 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
744 | mandatory for the 64-bit ABI, and may or may not be true for other | |
745 | operating systems. */ | |
746 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
747 | ||
f963b5d9 RS |
748 | /* Minimum allocation boundary for the code of a function. */ |
749 | #define FUNCTION_BOUNDARY 8 | |
750 | ||
751 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
752 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 753 | |
c98f8742 JVA |
754 | /* Minimum size in bits of the largest boundary to which any |
755 | and all fundamental data types supported by the hardware | |
756 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 757 | rounder than this. |
fce5a9f2 | 758 | |
d1f87653 | 759 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
6d2b7199 BS |
760 | and Pentium Pro XFmode values at 128 bit boundaries. |
761 | ||
762 | When increasing the maximum, also update | |
763 | TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ | |
17f24ff0 | 764 | |
3f97cb0b | 765 | #define BIGGEST_ALIGNMENT \ |
0076c82f | 766 | (TARGET_IAMCU ? 32 : (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))) |
17f24ff0 | 767 | |
2e3f842f L |
768 | /* Maximum stack alignment. */ |
769 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
770 | ||
6e4f1168 L |
771 | /* Alignment value for attribute ((aligned)). It is a constant since |
772 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
e9c9e772 | 773 | #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) |
6e4f1168 | 774 | |
822eda12 | 775 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 776 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 777 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 778 | |
17f24ff0 | 779 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 780 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 781 | -malign-double is set. */ |
e932b21b | 782 | |
e83f3cff RH |
783 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
784 | supports no vector modes, cut out the complexity and fall back | |
785 | on BIGGEST_FIELD_ALIGNMENT. */ | |
786 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
787 | #ifdef __x86_64__ |
788 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
789 | #else | |
e83f3cff | 790 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 791 | #endif |
e83f3cff | 792 | #else |
a4cf4b64 RB |
793 | #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \ |
794 | x86_field_alignment ((TYPE), (COMPUTED)) | |
e83f3cff | 795 | #endif |
c98f8742 | 796 | |
8a022443 JW |
797 | /* If defined, a C expression to compute the alignment for a static |
798 | variable. TYPE is the data type, and ALIGN is the alignment that | |
799 | the object would ordinarily have. The value of this macro is used | |
800 | instead of that alignment to align the object. | |
801 | ||
802 | If this macro is not defined, then ALIGN is used. | |
803 | ||
804 | One use of this macro is to increase alignment of medium-size | |
805 | data to make it all fit in fewer cache lines. Another is to | |
806 | cause character arrays to be word-aligned so that `strcpy' calls | |
807 | that copy constants to character arrays can be done inline. */ | |
808 | ||
df8a1d28 JJ |
809 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
810 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
811 | ||
812 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
813 | some alignment increase, instead of optimization only purposes. E.g. | |
814 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
815 | must be aligned to 16 byte boundaries. | |
816 | ||
817 | If this macro is not defined, then ALIGN is used. */ | |
818 | ||
819 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
820 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
821 | |
822 | /* If defined, a C expression to compute the alignment for a local | |
823 | variable. TYPE is the data type, and ALIGN is the alignment that | |
824 | the object would ordinarily have. The value of this macro is used | |
825 | instead of that alignment to align the object. | |
826 | ||
827 | If this macro is not defined, then ALIGN is used. | |
828 | ||
829 | One use of this macro is to increase alignment of medium-size | |
830 | data to make it all fit in fewer cache lines. */ | |
831 | ||
76fe54f0 L |
832 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
833 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
834 | ||
835 | /* If defined, a C expression to compute the alignment for stack slot. | |
836 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
837 | is the alignment that the slot would ordinarily have. The value of | |
838 | this macro is used instead of that alignment to align the slot. | |
839 | ||
840 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
841 | Otherwise, LOCAL_ALIGNMENT will be used. | |
842 | ||
843 | One use of this macro is to set alignment of stack slot to the | |
844 | maximum alignment of all possible modes which the slot may have. */ | |
845 | ||
846 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
847 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 848 | |
9bfaf89d JJ |
849 | /* If defined, a C expression to compute the alignment for a local |
850 | variable DECL. | |
851 | ||
852 | If this macro is not defined, then | |
853 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
854 | ||
855 | One use of this macro is to increase alignment of medium-size | |
856 | data to make it all fit in fewer cache lines. */ | |
857 | ||
858 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
859 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
860 | ||
ae58e548 JJ |
861 | /* If defined, a C expression to compute the minimum required alignment |
862 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
863 | MODE, assuming normal alignment ALIGN. | |
864 | ||
865 | If this macro is not defined, then (ALIGN) will be used. */ | |
866 | ||
867 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
1a6e82b8 | 868 | ix86_minimum_alignment ((EXP), (MODE), (ALIGN)) |
ae58e548 | 869 | |
9bfaf89d | 870 | |
9cd10576 | 871 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 872 | when given unaligned data. */ |
b4ac57ab | 873 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
874 | |
875 | /* If bit field type is int, don't let it cross an int, | |
876 | and give entire struct the alignment of an int. */ | |
43a88a8c | 877 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 878 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
879 | \f |
880 | /* Standard register usage. */ | |
881 | ||
e53b6e56 | 882 | /* This processor has special stack-like registers. See reg-stack.cc |
892a2d68 | 883 | for details. */ |
c98f8742 JVA |
884 | |
885 | #define STACK_REGS | |
ce998900 | 886 | |
f48b4284 UB |
887 | #define IS_STACK_MODE(MODE) \ |
888 | (X87_FLOAT_MODE_P (MODE) \ | |
889 | && (!(SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ | |
890 | || TARGET_MIX_SSE_I387)) | |
c98f8742 JVA |
891 | |
892 | /* Number of actual hardware registers. | |
893 | The hardware registers are assigned numbers for the compiler | |
894 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
895 | All registers that the compiler knows about must be given numbers, | |
896 | even those that are not normally considered general registers. | |
897 | ||
898 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
899 | We number the floating point registers 8-15. | |
900 | Note that registers 0-7 can be accessed as a short or int, | |
901 | while only 0-3 may be used with byte `mov' instructions. | |
902 | ||
903 | Reg 16 does not correspond to any hardware register, but instead | |
904 | appears in the RTL as an argument pointer prior to reload, and is | |
905 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 906 | pointer. */ |
c98f8742 | 907 | |
05416670 | 908 | #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG |
c98f8742 | 909 | |
3073d01c ML |
910 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
911 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
912 | ||
913 | #define DWARF_FRAME_REGISTERS 17 | |
914 | ||
c98f8742 JVA |
915 | /* 1 for registers that have pervasive standard uses |
916 | and are not available for the register allocator. | |
3f3f2124 | 917 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 918 | |
621bc046 UB |
919 | REX registers are disabled for 32bit targets in |
920 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
921 | ||
a7180f70 BS |
922 | #define FIXED_REGISTERS \ |
923 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 924 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
eaa17c21 UB |
925 | /*arg,flags,fpsr,frame*/ \ |
926 | 1, 1, 1, 1, \ | |
a7180f70 BS |
927 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
928 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 929 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
930 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
931 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 932 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 933 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
934 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
935 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
936 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
937 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
938 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
939 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
eafa30ef | 940 | 0, 0, 0, 0, 0, 0, 0, 0 } |
c98f8742 JVA |
941 | |
942 | /* 1 for registers not available across function calls. | |
943 | These must include the FIXED_REGISTERS and also any | |
944 | registers that can be used without being saved. | |
945 | The latter must include the registers where values are returned | |
946 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
947 | Aside from that, you can include as many other registers as you like. |
948 | ||
621bc046 UB |
949 | Value is set to 1 if the register is call used unconditionally. |
950 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
951 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
952 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
953 | ||
954 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
955 | ||
1f3ccbc8 L |
956 | #define CALL_USED_REGISTERS_MASK(IS_64BIT_MS_ABI) \ |
957 | ((IS_64BIT_MS_ABI) ? (1 << 3) : TARGET_64BIT ? (1 << 2) : (1 << 1)) | |
958 | ||
a7180f70 BS |
959 | #define CALL_USED_REGISTERS \ |
960 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 961 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
eaa17c21 UB |
962 | /*arg,flags,fpsr,frame*/ \ |
963 | 1, 1, 1, 1, \ | |
a7180f70 | 964 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 965 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 966 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 967 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 968 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 969 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 970 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
971 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
972 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
79ab8c43 | 973 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f97cb0b | 974 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ |
79ab8c43 | 975 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
85a77221 | 976 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ |
eafa30ef | 977 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 978 | |
3cc5f862 UB |
979 | /* Order in which to allocate registers. Each register must be |
980 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
981 | late and fixed registers last. Note that, in general, we prefer | |
982 | registers listed in CALL_USED_REGISTERS, keeping the others | |
983 | available for storage of persistent values. | |
984 | ||
985 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, | |
986 | so this is just empty initializer for array. */ | |
987 | ||
988 | #define REG_ALLOC_ORDER \ | |
989 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
990 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
991 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
992 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
993 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 } | |
994 | ||
5a733826 | 995 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 996 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 997 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 998 | |
5a733826 | 999 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1000 | |
f5316dfe | 1001 | |
7c800926 KT |
1002 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1003 | ||
8521c414 | 1004 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
7bf65250 UB |
1005 | (TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT \ |
1006 | && GENERAL_REGNO_P (REGNO) \ | |
1007 | && ((MODE) == XFmode || (MODE) == XCmode)) | |
8521c414 JM |
1008 | |
1009 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1010 | ||
e21b52af HL |
1011 | #define REGMODE_NATURAL_SIZE(MODE) ix86_regmode_natural_size (MODE) |
1012 | ||
95879c72 L |
1013 | #define VALID_AVX256_REG_MODE(MODE) \ |
1014 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1015 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
6910cad5 | 1016 | || (MODE) == V4DFmode || (MODE) == V16HFmode || (MODE) == V16BFmode) |
95879c72 | 1017 | |
271e36d9 UB |
1018 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
1019 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) | |
ff97910d | 1020 | |
3f97cb0b | 1021 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
826c22df | 1022 | ((MODE) == DImode || (MODE) == DFmode \ |
1023 | || (MODE) == SImode || (MODE) == SFmode \ | |
1024 | || (MODE) == HImode || (MODE) == HFmode || (MODE) == BFmode) | |
3f97cb0b AI |
1025 | |
1026 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1027 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 | 1028 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
6910cad5 | 1029 | || (MODE) == V4TImode || (MODE) == V32HFmode || (MODE) == V32BFmode) |
9e4a4dd6 | 1030 | |
e6f146d2 SP |
1031 | #define VALID_AVX512F_REG_OR_XI_MODE(MODE) \ |
1032 | (VALID_AVX512F_REG_MODE (MODE) || (MODE) == XImode) | |
1033 | ||
05416670 | 1034 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ |
9e4a4dd6 | 1035 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ |
40bd4bf9 | 1036 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode \ |
9e2a82e1 | 1037 | || (MODE) == TFmode || (MODE) == V1TImode || (MODE) == V8HFmode \ |
6910cad5 | 1038 | || (MODE) == V8BFmode || (MODE) == TImode) |
9e2a82e1 | 1039 | |
1040 | #define VALID_AVX512FP16_REG_MODE(MODE) \ | |
6913cad2 | 1041 | ((MODE) == V8HFmode || (MODE) == V16HFmode || (MODE) == V32HFmode) |
3f97cb0b | 1042 | |
ce998900 UB |
1043 | #define VALID_SSE2_REG_MODE(MODE) \ |
1044 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
271e36d9 | 1045 | || (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \ |
6913cad2 | 1046 | || (MODE) == V8BFmode || (MODE) == V4BFmode || (MODE) == V2BFmode \ |
663a014e | 1047 | || (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \ |
826c22df | 1048 | || (MODE) == V2DImode || (MODE) == V2QImode \ |
1049 | || (MODE) == DFmode || (MODE) == DImode \ | |
6624ad73 | 1050 | || (MODE) == HFmode || (MODE) == BFmode) |
fbe5eb6d | 1051 | |
d9a5f180 | 1052 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1053 | ((MODE) == V1TImode || (MODE) == TImode \ |
1054 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
826c22df | 1055 | || (MODE) == SFmode || (MODE) == SImode \ |
1056 | || (MODE) == TFmode || (MODE) == TDmode) | |
a7180f70 | 1057 | |
47f339cf | 1058 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1059 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1060 | |
eea10afe | 1061 | /* To match ia32 psABI, V4HFmode should be added here. */ |
d9a5f180 | 1062 | #define VALID_MMX_REG_MODE(MODE) \ |
879f9d0b | 1063 | ((MODE) == V1DImode || (MODE) == DImode \ |
10a97ae6 | 1064 | || (MODE) == V2SImode || (MODE) == SImode \ |
eea10afe | 1065 | || (MODE) == V4HImode || (MODE) == V8QImode \ |
6913cad2 | 1066 | || (MODE) == V4HFmode || (MODE) == V4BFmode) |
a7180f70 | 1067 | |
05416670 UB |
1068 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1069 | ||
1070 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) | |
1071 | ||
d9a5f180 | 1072 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 | 1073 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
a6841211 | 1074 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) |
a946dd00 | 1075 | |
d9a5f180 | 1076 | #define VALID_INT_MODE_P(MODE) \ |
46ca31d6 UB |
1077 | ((MODE) == QImode || (MODE) == HImode \ |
1078 | || (MODE) == SImode || (MODE) == DImode \ | |
1079 | || (MODE) == CQImode || (MODE) == CHImode \ | |
1080 | || (MODE) == CSImode || (MODE) == CDImode \ | |
f364cdff | 1081 | || (MODE) == SDmode || (MODE) == DDmode \ |
6624ad73 | 1082 | || (MODE) == HFmode || (MODE) == HCmode || (MODE) == BFmode \ |
6913cad2 | 1083 | || (MODE) == V2HImode || (MODE) == V2HFmode || (MODE) == V2BFmode \ |
9ff206d3 | 1084 | || (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \ |
46ca31d6 UB |
1085 | || (TARGET_64BIT \ |
1086 | && ((MODE) == TImode || (MODE) == CTImode \ | |
ea30c7bd UB |
1087 | || (MODE) == TFmode || (MODE) == TCmode \ |
1088 | || (MODE) == V8QImode || (MODE) == V4HImode \ | |
f364cdff | 1089 | || (MODE) == V2SImode || (MODE) == TDmode))) |
a946dd00 | 1090 | |
822eda12 | 1091 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1092 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1093 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1094 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1095 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1096 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1097 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1098 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1099 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
6910cad5 | 1100 | || (MODE) == V16SFmode \ |
1101 | || (MODE) == V32HFmode || (MODE) == V16HFmode || (MODE) == V8HFmode \ | |
1102 | || (MODE) == V32BFmode || (MODE) == V16BFmode || (MODE) == V8BFmode) | |
822eda12 | 1103 | |
05416670 UB |
1104 | #define X87_FLOAT_MODE_P(MODE) \ |
1105 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
85a77221 | 1106 | |
05416670 UB |
1107 | #define SSE_FLOAT_MODE_P(MODE) \ |
1108 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
1109 | ||
a6841211 GX |
1110 | #define SSE_FLOAT_MODE_SSEMATH_OR_HF_P(MODE) \ |
1111 | ((SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH) \ | |
1112 | || (TARGET_AVX512FP16 && (MODE) == HFmode)) | |
1113 | ||
05416670 UB |
1114 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ |
1115 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1116 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
9e4a4dd6 | 1117 | |
7026bb95 | 1118 | #define VALID_BCST_MODE_P(MODE) \ |
1119 | ((MODE) == SFmode || (MODE) == DFmode \ | |
7afcb534 | 1120 | || (MODE) == SImode || (MODE) == DImode \ |
1121 | || (MODE) == HFmode) | |
7026bb95 | 1122 | |
ff25ef99 ZD |
1123 | /* It is possible to write patterns to move flags; but until someone |
1124 | does it, */ | |
1125 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1126 | |
e075ae69 | 1127 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1128 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1129 | |
787dc842 JH |
1130 | Kill any attempts to combine saving of modes. */ |
1131 | ||
d9a5f180 GS |
1132 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1133 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1134 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
737d6a1a | 1135 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), NULL) \ |
a60c3351 UB |
1136 | : (MODE) == HImode && !((GENERAL_REGNO_P (REGNO) \ |
1137 | && TARGET_PARTIAL_REG_STALL) \ | |
85a77221 | 1138 | || MASK_REGNO_P (REGNO)) ? SImode \ |
a60c3351 | 1139 | : (MODE) == QImode && !(ANY_QI_REGNO_P (REGNO) \ |
85a77221 | 1140 | || MASK_REGNO_P (REGNO)) ? SImode \ |
d2836273 | 1141 | : (MODE)) |
ce998900 | 1142 | |
c98f8742 JVA |
1143 | /* Specify the registers used for certain standard purposes. |
1144 | The values of these macros are register numbers. */ | |
1145 | ||
1146 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1147 | register. The ordinary mov instructions won't work */ | |
1148 | /* #define PC_REGNUM */ | |
1149 | ||
05416670 UB |
1150 | /* Base register for access to arguments of the function. */ |
1151 | #define ARG_POINTER_REGNUM ARGP_REG | |
1152 | ||
c98f8742 | 1153 | /* Register to use for pushing function arguments. */ |
05416670 | 1154 | #define STACK_POINTER_REGNUM SP_REG |
c98f8742 JVA |
1155 | |
1156 | /* Base register for access to local variables of the function. */ | |
05416670 UB |
1157 | #define FRAME_POINTER_REGNUM FRAME_REG |
1158 | #define HARD_FRAME_POINTER_REGNUM BP_REG | |
564d80f4 | 1159 | |
05416670 UB |
1160 | #define FIRST_INT_REG AX_REG |
1161 | #define LAST_INT_REG SP_REG | |
c98f8742 | 1162 | |
05416670 UB |
1163 | #define FIRST_QI_REG AX_REG |
1164 | #define LAST_QI_REG BX_REG | |
c98f8742 JVA |
1165 | |
1166 | /* First & last stack-like regs */ | |
05416670 UB |
1167 | #define FIRST_STACK_REG ST0_REG |
1168 | #define LAST_STACK_REG ST7_REG | |
c98f8742 | 1169 | |
05416670 UB |
1170 | #define FIRST_SSE_REG XMM0_REG |
1171 | #define LAST_SSE_REG XMM7_REG | |
fce5a9f2 | 1172 | |
05416670 UB |
1173 | #define FIRST_MMX_REG MM0_REG |
1174 | #define LAST_MMX_REG MM7_REG | |
a7180f70 | 1175 | |
05416670 UB |
1176 | #define FIRST_REX_INT_REG R8_REG |
1177 | #define LAST_REX_INT_REG R15_REG | |
3f3f2124 | 1178 | |
05416670 UB |
1179 | #define FIRST_REX_SSE_REG XMM8_REG |
1180 | #define LAST_REX_SSE_REG XMM15_REG | |
3f3f2124 | 1181 | |
05416670 UB |
1182 | #define FIRST_EXT_REX_SSE_REG XMM16_REG |
1183 | #define LAST_EXT_REX_SSE_REG XMM31_REG | |
3f97cb0b | 1184 | |
05416670 UB |
1185 | #define FIRST_MASK_REG MASK0_REG |
1186 | #define LAST_MASK_REG MASK7_REG | |
85a77221 | 1187 | |
aabcd309 | 1188 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1189 | requiring a frame pointer. */ |
1190 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1191 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1192 | #endif | |
1193 | ||
d730fd95 AT |
1194 | /* Define the shadow offset for asan. Other OS's can override in the |
1195 | respective tm.h files. */ | |
1196 | #ifndef SUBTARGET_SHADOW_OFFSET | |
1197 | #define SUBTARGET_SHADOW_OFFSET \ | |
1198 | (TARGET_LP64 ? HOST_WIDE_INT_C (0x7fff8000) : HOST_WIDE_INT_1 << 29) | |
1199 | #endif | |
1200 | ||
6fca22eb RH |
1201 | /* Make sure we can access arbitrary call frames. */ |
1202 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 | 1203 | |
c98f8742 | 1204 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1205 | code access to data items. We don't use PIC pointer for 64bit |
1206 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1207 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1208 | |
1209 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1210 | the pic register when possible. The change is visible after the | |
1211 | prologue has been emitted. */ | |
1212 | ||
e8b5eb25 | 1213 | #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) |
bd09bdeb | 1214 | |
bcb21886 | 1215 | #define PIC_OFFSET_TABLE_REGNUM \ |
d290bb1d IE |
1216 | (ix86_use_pseudo_pic_reg () \ |
1217 | ? (pic_offset_table_rtx \ | |
1218 | ? INVALID_REGNUM \ | |
1219 | : REAL_PIC_OFFSET_TABLE_REGNUM) \ | |
1220 | : INVALID_REGNUM) | |
c98f8742 | 1221 | |
5fc0e5df KW |
1222 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1223 | ||
c51e6d85 | 1224 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1225 | #define MS_AGGREGATE_RETURN 0 |
1226 | ||
61fec9ff | 1227 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1228 | \f |
1229 | /* Define the classes of registers for register constraints in the | |
1230 | machine description. Also define ranges of constants. | |
1231 | ||
1232 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1233 | If there is more than one class, another class must be named NO_REGS | |
1234 | and contain no registers. | |
1235 | ||
1236 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1237 | another name such as ALL_REGS). This is the class of registers | |
1238 | that is allowed by "g" or "r" in a register constraint. | |
1239 | Also, registers outside this class are allocated only when | |
1240 | instructions express preferences for them. | |
1241 | ||
1242 | The classes must be numbered in nondecreasing order; that is, | |
1243 | a larger-numbered class must never be contained completely | |
2e24efd3 AM |
1244 | in a smaller-numbered class. This is why CLOBBERED_REGS class |
1245 | is listed early, even though in 64-bit mode it contains more | |
1246 | registers than just %eax, %ecx, %edx. | |
c98f8742 JVA |
1247 | |
1248 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1249 | class that represents their union. |
1250 | ||
eaa17c21 | 1251 | The flags and fpsr registers are in no class. */ |
c98f8742 JVA |
1252 | |
1253 | enum reg_class | |
1254 | { | |
1255 | NO_REGS, | |
e075ae69 | 1256 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1257 | AD_REGS, /* %eax/%edx for DImode */ |
2e24efd3 | 1258 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
c98f8742 | 1259 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1260 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
de86ff8f | 1261 | TLS_GOTBASE_REGS, /* %ebx %ecx %edx %esi %edi %ebp */ |
c98f8742 | 1262 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1263 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
63001560 UB |
1264 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1265 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1266 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1267 | FLOAT_REGS, | |
06f4e35d | 1268 | SSE_FIRST_REG, |
45392c76 | 1269 | NO_REX_SSE_REGS, |
a7180f70 | 1270 | SSE_REGS, |
3f97cb0b | 1271 | ALL_SSE_REGS, |
a7180f70 | 1272 | MMX_REGS, |
446988df JH |
1273 | FLOAT_SSE_REGS, |
1274 | FLOAT_INT_REGS, | |
1275 | INT_SSE_REGS, | |
1276 | FLOAT_INT_SSE_REGS, | |
85a77221 | 1277 | MASK_REGS, |
d18cbbf6 | 1278 | ALL_MASK_REGS, |
2d2bc36c | 1279 | INT_MASK_REGS, |
d18cbbf6 UB |
1280 | ALL_REGS, |
1281 | LIM_REG_CLASSES | |
c98f8742 JVA |
1282 | }; |
1283 | ||
d9a5f180 GS |
1284 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1285 | ||
1286 | #define INTEGER_CLASS_P(CLASS) \ | |
1287 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1288 | #define FLOAT_CLASS_P(CLASS) \ | |
1289 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1290 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1291 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d1011a41 | 1292 | #define INT_SSE_CLASS_P(CLASS) \ |
1293 | reg_class_subset_p ((CLASS), INT_SSE_REGS) | |
d9a5f180 | 1294 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1295 | ((CLASS) == MMX_REGS) |
4ed04e93 | 1296 | #define MASK_CLASS_P(CLASS) \ |
d18cbbf6 | 1297 | reg_class_subset_p ((CLASS), ALL_MASK_REGS) |
d9a5f180 GS |
1298 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1299 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1300 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1301 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1302 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1303 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1304 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1305 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 | 1306 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
d18cbbf6 | 1307 | reg_classes_intersect_p ((CLASS), ALL_MASK_REGS) |
d9a5f180 GS |
1308 | |
1309 | #define Q_CLASS_P(CLASS) \ | |
1310 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1311 | |
0bd72901 UB |
1312 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1313 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1314 | ||
43f3a59d | 1315 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1316 | |
1317 | #define REG_CLASS_NAMES \ | |
1318 | { "NO_REGS", \ | |
ab408a86 | 1319 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1320 | "SIREG", "DIREG", \ |
e075ae69 | 1321 | "AD_REGS", \ |
2e24efd3 | 1322 | "CLOBBERED_REGS", \ |
e075ae69 | 1323 | "Q_REGS", "NON_Q_REGS", \ |
de86ff8f | 1324 | "TLS_GOTBASE_REGS", \ |
c98f8742 | 1325 | "INDEX_REGS", \ |
3f3f2124 | 1326 | "LEGACY_REGS", \ |
c98f8742 JVA |
1327 | "GENERAL_REGS", \ |
1328 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1329 | "FLOAT_REGS", \ | |
cb482895 | 1330 | "SSE_FIRST_REG", \ |
45392c76 | 1331 | "NO_REX_SSE_REGS", \ |
a7180f70 | 1332 | "SSE_REGS", \ |
3f97cb0b | 1333 | "ALL_SSE_REGS", \ |
a7180f70 | 1334 | "MMX_REGS", \ |
446988df | 1335 | "FLOAT_SSE_REGS", \ |
8fcaaa80 | 1336 | "FLOAT_INT_REGS", \ |
446988df JH |
1337 | "INT_SSE_REGS", \ |
1338 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 | 1339 | "MASK_REGS", \ |
d18cbbf6 | 1340 | "ALL_MASK_REGS", \ |
2d2bc36c | 1341 | "INT_MASK_REGS", \ |
c98f8742 JVA |
1342 | "ALL_REGS" } |
1343 | ||
ac2e563f RH |
1344 | /* Define which registers fit in which classes. This is an initializer |
1345 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1346 | ||
621bc046 UB |
1347 | Note that CLOBBERED_REGS are calculated by |
1348 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1349 | |
d18cbbf6 | 1350 | #define REG_CLASS_CONTENTS \ |
eaa17c21 UB |
1351 | { { 0x0, 0x0, 0x0 }, /* NO_REGS */ \ |
1352 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1353 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1354 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1355 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1356 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1357 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1358 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
1359 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ | |
1360 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ | |
1361 | { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ | |
1362 | { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ | |
1363 | { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ | |
1364 | { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
1365 | { 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \ | |
1366 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1367 | { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1368 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1369 | { 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
1370 | { 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \ | |
1371 | { 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \ | |
1372 | { 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \ | |
1373 | { 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \ | |
1374 | { 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \ | |
1375 | { 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1376 | { 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \ | |
1377 | { 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \ | |
1378 | { 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \ | |
1379 | { 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \ | |
2d2bc36c | 1380 | { 0x900ff, 0xff0, 0xff0 }, /* INT_MASK_REGS */ \ |
eaa17c21 | 1381 | { 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \ |
e075ae69 | 1382 | } |
c98f8742 JVA |
1383 | |
1384 | /* The same information, inverted: | |
1385 | Return the class number of the smallest class containing | |
1386 | reg number REGNO. This could be a conditional expression | |
1387 | or could index an array. */ | |
1388 | ||
1a6e82b8 | 1389 | #define REGNO_REG_CLASS(REGNO) (regclass_map[(REGNO)]) |
c98f8742 | 1390 | |
42db504c SB |
1391 | /* When this hook returns true for MODE, the compiler allows |
1392 | registers explicitly used in the rtl to be used as spill registers | |
1393 | but prevents the compiler from extending the lifetime of these | |
1394 | registers. */ | |
1395 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1396 | |
fc27f749 | 1397 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
05416670 UB |
1398 | #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) |
1399 | ||
1400 | #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) | |
1401 | #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) | |
1402 | ||
1403 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
1404 | #define REX_INT_REGNO_P(N) \ | |
1405 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1406 | |
58b0b34c | 1407 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 | 1408 | #define GENERAL_REGNO_P(N) \ |
58b0b34c | 1409 | (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) |
3f3f2124 | 1410 | |
fc27f749 UB |
1411 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1412 | #define ANY_QI_REGNO_P(N) \ | |
1413 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1414 | |
66aaf16f UB |
1415 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1416 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1417 | |
fc27f749 | 1418 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 | 1419 | #define SSE_REGNO_P(N) \ |
ef342b2d | 1420 | (LEGACY_SSE_REGNO_P (N) \ |
3f97cb0b AI |
1421 | || REX_SSE_REGNO_P (N) \ |
1422 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1423 | |
ef342b2d UB |
1424 | #define LEGACY_SSE_REGNO_P(N) \ |
1425 | IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) | |
1426 | ||
4977bab6 | 1427 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1428 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1429 | |
0a48088a IT |
1430 | #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) |
1431 | ||
3f97cb0b AI |
1432 | #define EXT_REX_SSE_REGNO_P(N) \ |
1433 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1434 | ||
05416670 UB |
1435 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
1436 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) | |
3f97cb0b | 1437 | |
9e4a4dd6 | 1438 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 | 1439 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
e21b52af | 1440 | #define MASK_PAIR_REGNO_P(N) ((((N) - FIRST_MASK_REG) & 1) == 0) |
446988df | 1441 | |
fc27f749 | 1442 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1443 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1444 | |
e075ae69 | 1445 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
adb67ffb | 1446 | #define CC_REGNO_P(X) ((X) == FLAGS_REG) |
e075ae69 | 1447 | |
5fbb13a7 KY |
1448 | #define MOD4_SSE_REG_P(X) (REG_P (X) && MOD4_SSE_REGNO_P (REGNO (X))) |
1449 | #define MOD4_SSE_REGNO_P(N) ((N) == XMM0_REG \ | |
1450 | || (N) == XMM4_REG \ | |
1451 | || (N) == XMM8_REG \ | |
1452 | || (N) == XMM12_REG \ | |
1453 | || (N) == XMM16_REG \ | |
1454 | || (N) == XMM20_REG \ | |
1455 | || (N) == XMM24_REG \ | |
1456 | || (N) == XMM28_REG) | |
1457 | ||
05416670 UB |
1458 | /* First floating point reg */ |
1459 | #define FIRST_FLOAT_REG FIRST_STACK_REG | |
1460 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) | |
1461 | ||
02469d3a UB |
1462 | #define GET_SSE_REGNO(N) \ |
1463 | ((N) < 8 ? FIRST_SSE_REG + (N) \ | |
1464 | : (N) < 16 ? FIRST_REX_SSE_REG + (N) - 8 \ | |
1465 | : FIRST_EXT_REX_SSE_REG + (N) - 16) | |
05416670 | 1466 | |
c98f8742 JVA |
1467 | /* The class value for index registers, and the one for base regs. */ |
1468 | ||
1469 | #define INDEX_REG_CLASS INDEX_REGS | |
1470 | #define BASE_REG_CLASS GENERAL_REGS | |
c98f8742 JVA |
1471 | \f |
1472 | /* Stack layout; function entry, exit and calling. */ | |
1473 | ||
1474 | /* Define this if pushing a word on the stack | |
1475 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1476 | #define STACK_GROWS_DOWNWARD 1 |
c98f8742 | 1477 | |
a4d05547 | 1478 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1479 | is at the high-address end of the local variables; |
1480 | that is, each additional local variable allocated | |
1481 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1482 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 | 1483 | |
7b4df2bf | 1484 | #define PUSH_ROUNDING(BYTES) ix86_push_rounding (BYTES) |
8c2b2fae UB |
1485 | |
1486 | /* If defined, the maximum amount of space required for outgoing arguments | |
1487 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1488 | No space will be pushed onto the stack for each call; instead, the | |
1489 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1490 | |
1491 | In 32bit mode enabling argument accumulation results in about 5% code size | |
56aae4b7 | 1492 | growth because move instructions are less compact than push. In 64bit |
41ee845b JH |
1493 | mode the difference is less drastic but visible. |
1494 | ||
1495 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1496 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1497 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1498 | |
1499 | With the 64-bit MS ABI, we can generate correct code with or without | |
1500 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1501 | generated without accumulated args is terrible. | |
41ee845b JH |
1502 | |
1503 | If stack probes are required, the space used for large function | |
1504 | arguments on the stack must also be probed, so enable | |
f8071c05 L |
1505 | -maccumulate-outgoing-args so this happens in the prologue. |
1506 | ||
1507 | We must use argument accumulation in interrupt function if stack | |
1508 | may be realigned to avoid DRAP. */ | |
f73ad30e | 1509 | |
6c6094f1 | 1510 | #define ACCUMULATE_OUTGOING_ARGS \ |
f8071c05 L |
1511 | ((TARGET_ACCUMULATE_OUTGOING_ARGS \ |
1512 | && optimize_function_for_speed_p (cfun)) \ | |
1513 | || (cfun->machine->func_type != TYPE_NORMAL \ | |
1514 | && crtl->stack_realign_needed) \ | |
1515 | || TARGET_STACK_PROBE \ | |
1516 | || TARGET_64BIT_MS_ABI \ | |
ff734e26 | 1517 | || (TARGET_MACHO && crtl->profile)) |
f73ad30e | 1518 | |
2da4124d | 1519 | /* We want the stack and args grow in opposite directions, even if |
967b4653 | 1520 | targetm.calls.push_argument returns false. */ |
2da4124d L |
1521 | #define PUSH_ARGS_REVERSED 1 |
1522 | ||
c98f8742 JVA |
1523 | /* Offset of first parameter from the argument pointer register value. */ |
1524 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1525 | ||
a7180f70 BS |
1526 | /* Define this macro if functions should assume that stack space has been |
1527 | allocated for arguments even when their values are passed in registers. | |
1528 | ||
1529 | The value of this macro is the size, in bytes, of the area reserved for | |
1530 | arguments passed in registers for the function represented by FNDECL. | |
1531 | ||
1532 | This space can be allocated by the caller, or be a part of the | |
1533 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1534 | which. */ | |
7c800926 KT |
1535 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1536 | ||
4ae8027b | 1537 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1538 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1539 | |
c98f8742 JVA |
1540 | /* Define how to find the value returned by a library function |
1541 | assuming the value has mode MODE. */ | |
1542 | ||
4ae8027b | 1543 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1544 | |
e9125c09 TW |
1545 | /* Define the size of the result block used for communication between |
1546 | untyped_call and untyped_return. The block contains a DImode value | |
1547 | followed by the block used by fnsave and frstor. */ | |
1548 | ||
1549 | #define APPLY_RESULT_SIZE (8+108) | |
1550 | ||
b08de47e | 1551 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1552 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1553 | |
1554 | /* Define a data type for recording info about an argument list | |
1555 | during the scan of that argument list. This data type should | |
1556 | hold all necessary information about the function itself | |
1557 | and about the args processed so far, enough to enable macros | |
b08de47e | 1558 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1559 | |
e075ae69 | 1560 | typedef struct ix86_args { |
fa283935 | 1561 | int words; /* # words passed so far */ |
b08de47e MM |
1562 | int nregs; /* # registers available for passing */ |
1563 | int regno; /* next available register number */ | |
3e65f251 KT |
1564 | int fastcall; /* fastcall or thiscall calling convention |
1565 | is used */ | |
fa283935 | 1566 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1567 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1568 | int warn_avx512f; /* True when we want to warn |
1569 | about AVX512F ABI. */ | |
95879c72 | 1570 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1571 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 | 1572 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
974aedcc MP |
1573 | int warn_empty; /* True when we want to warn about empty classes |
1574 | passing ABI change. */ | |
fa283935 UB |
1575 | int sse_regno; /* next available sse register number */ |
1576 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1577 | int mmx_nregs; /* # mmx registers available for passing */ |
1578 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1579 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1580 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1581 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1582 | SFmode/DFmode arguments should be passed | |
1583 | in SSE registers. Otherwise 0. */ | |
d5e254e1 | 1584 | int stdarg; /* Set to 1 if function is stdarg. */ |
51212b32 | 1585 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1586 | MS_ABI for ms abi. */ |
e66fc623 | 1587 | tree decl; /* Callee decl. */ |
b08de47e | 1588 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1589 | |
1590 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1591 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1592 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1593 | |
0f6937fe | 1594 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1595 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1596 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1597 | |
c98f8742 JVA |
1598 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1599 | for profiling a function entry. */ | |
1600 | ||
1a6e82b8 UB |
1601 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
1602 | x86_function_profiler ((FILE), (LABELNO)) | |
a5fa1ecd JH |
1603 | |
1604 | #define MCOUNT_NAME "_mcount" | |
1605 | ||
3c5273a9 KT |
1606 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1607 | ||
a5fa1ecd | 1608 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1609 | |
1610 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1611 | the stack pointer does not matter. The value is tested only in | |
1612 | functions that have frame pointers. | |
1613 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1614 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1615 | we have to restore it ourselves from the frame pointer, in order to |
1616 | use pop */ | |
1617 | ||
1618 | #define EXIT_IGNORE_STACK 1 | |
1619 | ||
f8071c05 L |
1620 | /* Define this macro as a C expression that is nonzero for registers |
1621 | used by the epilogue or the `return' pattern. */ | |
1622 | ||
1623 | #define EPILOGUE_USES(REGNO) ix86_epilogue_uses (REGNO) | |
1624 | ||
c98f8742 JVA |
1625 | /* Output assembler code for a block containing the constant parts |
1626 | of a trampoline, leaving space for the variable parts. */ | |
1627 | ||
a269a03c | 1628 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1629 | mov #STATIC,ecx |
a269a03c JC |
1630 | jmp FUNCTION |
1631 | The trampoline is generated entirely at runtime. The operand of JMP | |
1632 | is the address of FUNCTION relative to the instruction following the | |
1633 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1634 | |
1635 | /* Length in units of the trampoline for entering a nested function. */ | |
1636 | ||
6514899f | 1637 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 28 : 14) |
c98f8742 JVA |
1638 | \f |
1639 | /* Definitions for register eliminations. | |
1640 | ||
1641 | This is an array of structures. Each structure initializes one pair | |
1642 | of eliminable registers. The "from" register number is given first, | |
1643 | followed by "to". Eliminations of the same "from" register are listed | |
1644 | in order of preference. | |
1645 | ||
afc2cd05 NC |
1646 | There are two registers that can always be eliminated on the i386. |
1647 | The frame pointer and the arg pointer can be replaced by either the | |
1648 | hard frame pointer or to the stack pointer, depending upon the | |
1649 | circumstances. The hard frame pointer is not used before reload and | |
1650 | so it is not eligible for elimination. */ | |
c98f8742 | 1651 | |
564d80f4 JH |
1652 | #define ELIMINABLE_REGS \ |
1653 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1654 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1655 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1656 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1657 | |
c98f8742 JVA |
1658 | /* Define the offset between two registers, one to be eliminated, and the other |
1659 | its replacement, at the start of a routine. */ | |
1660 | ||
d9a5f180 GS |
1661 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1662 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1663 | \f |
1664 | /* Addressing modes, and classification of registers for them. */ | |
1665 | ||
c98f8742 JVA |
1666 | /* Macros to check register numbers against specific register classes. */ |
1667 | ||
1668 | /* These assume that REGNO is a hard or pseudo reg number. | |
1669 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1670 | or a pseudo reg currently allocated to a suitable hard reg. | |
1671 | Since they use reg_renumber, they are safe only once reg_renumber | |
e53b6e56 | 1672 | has been allocated, which happens in reginfo.cc during register |
aeb9f7cf | 1673 | allocation. */ |
c98f8742 | 1674 | |
3f3f2124 JH |
1675 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1676 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1677 | || REX_INT_REGNO_P (REGNO) \ |
1678 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1679 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1680 | |
3f3f2124 | 1681 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1682 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1683 | || (REGNO) == ARG_POINTER_REGNUM \ |
1684 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1685 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1686 | |
c98f8742 JVA |
1687 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1688 | and check its validity for a certain class. | |
1689 | We have two alternate definitions for each of them. | |
1690 | The usual definition accepts all pseudo regs; the other rejects | |
1691 | them unless they have been allocated suitable hard regs. | |
1692 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1693 | ||
1694 | Most source files want to accept pseudo regs in the hope that | |
1695 | they will get allocated to the class that the insn wants them to be in. | |
1696 | Source files for reload pass need to be strict. | |
1697 | After reload, it makes no difference, since pseudo regs have | |
1698 | been eliminated by then. */ | |
1699 | ||
c98f8742 | 1700 | |
ff482c8d | 1701 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1702 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1703 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1704 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1705 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1706 | ||
3b3c6a3f | 1707 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1708 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1709 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1710 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1711 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1712 | |
3b3c6a3f MM |
1713 | /* Strict versions, hard registers only */ |
1714 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1715 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1716 | |
3b3c6a3f | 1717 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1718 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1719 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1720 | |
1721 | #else | |
d9a5f180 GS |
1722 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1723 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1724 | #endif |
1725 | ||
331d9186 | 1726 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1727 | that is a valid memory address for an instruction. |
1728 | The MODE argument is the machine mode for the MEM expression | |
1729 | that wants to use this address. | |
1730 | ||
331d9186 | 1731 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1732 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1733 | ||
e53b6e56 | 1734 | See legitimize_pic_address in i386.cc for details as to what |
c98f8742 JVA |
1735 | constitutes a legitimate address when -fpic is used. */ |
1736 | ||
1737 | #define MAX_REGS_PER_ADDRESS 2 | |
1738 | ||
f996902d | 1739 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1740 | |
b949ea8b | 1741 | /* If defined, a C expression to determine the base term of address X. |
e53b6e56 | 1742 | This macro is used in only one place: `find_base_term' in alias.cc. |
b949ea8b JW |
1743 | |
1744 | It is always safe for this macro to not be defined. It exists so | |
1745 | that alias analysis can understand machine-dependent addresses. | |
1746 | ||
1747 | The typical use of this macro is to handle addresses containing | |
1748 | a label_ref or symbol_ref within an UNSPEC. */ | |
1749 | ||
d9a5f180 | 1750 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1751 | |
c98f8742 | 1752 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1753 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1754 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1755 | ||
f996902d | 1756 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 | 1757 | |
6ddb30f9 | 1758 | #define STRIP_UNARY(X) (UNARY_P (X) ? XEXP (X, 0) : X) |
1759 | ||
c98f8742 | 1760 | #define SYMBOLIC_CONST(X) \ |
d9a5f180 GS |
1761 | (GET_CODE (X) == SYMBOL_REF \ |
1762 | || GET_CODE (X) == LABEL_REF \ | |
1763 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1764 | \f |
b08de47e MM |
1765 | /* Max number of args passed in registers. If this is more than 3, we will |
1766 | have problems with ebx (register #4), since it is a caller save register and | |
1767 | is also used as the pic register in ELF. So for now, don't allow more than | |
1768 | 3 registers to be passed in registers. */ | |
1769 | ||
7c800926 KT |
1770 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1771 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1772 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1773 | |
72fa3605 | 1774 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1775 | |
4ae8027b | 1776 | #define REGPARM_MAX \ |
2824d6e5 UB |
1777 | (TARGET_64BIT \ |
1778 | ? (TARGET_64BIT_MS_ABI \ | |
1779 | ? X86_64_MS_REGPARM_MAX \ | |
1780 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1781 | : X86_32_REGPARM_MAX) |
d2836273 | 1782 | |
72fa3605 UB |
1783 | #define X86_64_SSE_REGPARM_MAX 8 |
1784 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1785 | ||
b6010cab | 1786 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1787 | |
4ae8027b | 1788 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1789 | (TARGET_64BIT \ |
1790 | ? (TARGET_64BIT_MS_ABI \ | |
1791 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1792 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1793 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 | 1794 | |
f4a0e873 UB |
1795 | #define X86_32_MMX_REGPARM_MAX (TARGET_MMX ? (TARGET_MACHO ? 0 : 3) : 0) |
1796 | ||
1797 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : X86_32_MMX_REGPARM_MAX) | |
c98f8742 JVA |
1798 | \f |
1799 | /* Specify the machine mode that this machine uses | |
1800 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1801 | #define CASE_VECTOR_MODE \ |
6025b127 | 1802 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1803 | |
c98f8742 JVA |
1804 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1805 | #define DEFAULT_SIGNED_CHAR 1 | |
1806 | ||
29f0e955 L |
1807 | /* The constant maximum number of bytes that a single instruction can |
1808 | move quickly between memory and registers or between two memory | |
1809 | locations. */ | |
1810 | #define MAX_MOVE_MAX 64 | |
1811 | ||
1812 | /* Max number of bytes we can move from memory to memory in one | |
1813 | reasonably fast instruction, as opposed to MOVE_MAX_PIECES which | |
1814 | is the number of bytes at a time which we can move efficiently. | |
1815 | MOVE_MAX_PIECES defaults to MOVE_MAX. */ | |
1816 | ||
1817 | #define MOVE_MAX \ | |
654cd743 L |
1818 | ((TARGET_AVX512F \ |
1819 | && (ix86_move_max == PVW_AVX512 \ | |
1820 | || ix86_store_max == PVW_AVX512)) \ | |
29f0e955 L |
1821 | ? 64 \ |
1822 | : ((TARGET_AVX \ | |
654cd743 L |
1823 | && (ix86_move_max >= PVW_AVX256 \ |
1824 | || ix86_store_max >= PVW_AVX256)) \ | |
29f0e955 L |
1825 | ? 32 \ |
1826 | : ((TARGET_SSE2 \ | |
1827 | && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ | |
1828 | && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ | |
1829 | ? 16 : UNITS_PER_WORD))) | |
1830 | ||
5738a64f L |
1831 | /* STORE_MAX_PIECES is the number of bytes at a time that we can store |
1832 | efficiently. Allow 16/32/64 bytes only if inter-unit move is enabled | |
1833 | since vec_duplicate enabled by inter-unit move is used to implement | |
1834 | store_by_pieces of 16/32/64 bytes. */ | |
29f0e955 | 1835 | #define STORE_MAX_PIECES \ |
5738a64f | 1836 | (TARGET_INTER_UNIT_MOVES_TO_VEC \ |
654cd743 | 1837 | ? ((TARGET_AVX512F && ix86_store_max == PVW_AVX512) \ |
5738a64f L |
1838 | ? 64 \ |
1839 | : ((TARGET_AVX \ | |
654cd743 | 1840 | && ix86_store_max >= PVW_AVX256) \ |
5738a64f L |
1841 | ? 32 \ |
1842 | : ((TARGET_SSE2 \ | |
1843 | && TARGET_SSE_UNALIGNED_STORE_OPTIMAL) \ | |
1844 | ? 16 : UNITS_PER_WORD))) \ | |
1845 | : UNITS_PER_WORD) | |
c98f8742 | 1846 | |
7e24ffc9 | 1847 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
76715c32 | 1848 | move-instruction pairs, we will do a cpymem or libcall instead. |
7e24ffc9 HPN |
1849 | Increasing the value will always make code faster, but eventually |
1850 | incurs high cost in increased code size. | |
c98f8742 | 1851 | |
e2e52e1b | 1852 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1853 | |
e04ad03d | 1854 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1855 | |
45d78e7f JJ |
1856 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1857 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1858 | ||
25e22b19 | 1859 | #define CLEAR_RATIO(speed) ((speed) ? ix86_cost->clear_ratio : 2) |
45d78e7f | 1860 | |
53f00dde UB |
1861 | /* Define if shifts truncate the shift count which implies one can |
1862 | omit a sign-extension or zero-extension of a shift count. | |
1863 | ||
1864 | On i386, shifts do truncate the count. But bit test instructions | |
1865 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1866 | |
1867 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1868 | ||
d9f32422 JH |
1869 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1870 | TYPE and which has the specified mode and signedness is to be | |
1871 | stored in a register. This macro is only called when TYPE is a | |
1872 | scalar type. | |
1873 | ||
f710504c | 1874 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1875 | quantities to SImode. The choice depends on target type. */ |
1876 | ||
1877 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1878 | do { \ |
d9f32422 JH |
1879 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1880 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1881 | (MODE) = SImode; \ |
1882 | } while (0) | |
d9f32422 | 1883 | |
c98f8742 JVA |
1884 | /* Specify the machine mode that pointers have. |
1885 | After generation of rtl, the compiler makes no further distinction | |
1886 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1887 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1888 | |
5e1e91c4 L |
1889 | /* Supply a definition of STACK_SAVEAREA_MODE for emit_stack_save. |
1890 | NONLOCAL needs space to save both shadow stack and stack pointers. | |
1891 | ||
1892 | FIXME: We only need to save and restore stack pointer in ptr_mode. | |
1893 | But expand_builtin_setjmp_setup and expand_builtin_longjmp use Pmode | |
1894 | to save and restore stack pointer. See | |
1895 | https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84150 | |
1896 | */ | |
1897 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
1898 | ((LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) | |
1899 | ||
d16b9d1c UB |
1900 | /* Specify the machine_mode of the size increment |
1901 | operand of an 'allocate_stack' named pattern. */ | |
1902 | #define STACK_SIZE_MODE Pmode | |
1903 | ||
f0ea7581 L |
1904 | /* A C expression whose value is zero if pointers that need to be extended |
1905 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1906 | greater then zero if they are zero-extended and less then zero if the | |
1907 | ptr_extend instruction should be used. */ | |
1908 | ||
1909 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1910 | ||
c98f8742 JVA |
1911 | /* A function address in a call instruction |
1912 | is a byte address (for indexing purposes) | |
1913 | so give the MEM rtx a byte's mode. */ | |
1914 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1915 | \f |
d4ba09c0 | 1916 | |
d4ba09c0 SC |
1917 | /* A C expression for the cost of a branch instruction. A value of 1 |
1918 | is the default; other values are interpreted relative to that. */ | |
1919 | ||
3a4fd356 JH |
1920 | #define BRANCH_COST(speed_p, predictable_p) \ |
1921 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1922 | |
e327d1a3 L |
1923 | /* An integer expression for the size in bits of the largest integer machine |
1924 | mode that should actually be used. We allow pairs of registers. */ | |
1925 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1926 | ||
d4ba09c0 SC |
1927 | /* Define this macro as a C expression which is nonzero if accessing |
1928 | less than a word of memory (i.e. a `char' or a `short') is no | |
1929 | faster than accessing a word of memory, i.e., if such access | |
1930 | require more than one instruction or if there is no difference in | |
1931 | cost between byte and (aligned) word loads. | |
1932 | ||
1933 | When this macro is not defined, the compiler will access a field by | |
1934 | finding the smallest containing object; when it is defined, a | |
1935 | fullword load will be used if alignment permits. Unless bytes | |
1936 | accesses are faster than word accesses, using word accesses is | |
1937 | preferable since it may eliminate subsequent memory access if | |
1938 | subsequent accesses occur to other fields in the same word of the | |
1939 | structure, but to different bytes. */ | |
1940 | ||
1941 | #define SLOW_BYTE_ACCESS 0 | |
1942 | ||
d4ba09c0 SC |
1943 | /* Define this macro if it is as good or better to call a constant |
1944 | function address than to call an address kept in a register. | |
1945 | ||
1946 | Desirable on the 386 because a CALL with a constant address is | |
1947 | faster than one with a register address. */ | |
1948 | ||
1e8552c2 | 1949 | #define NO_FUNCTION_CSE 1 |
c98f8742 | 1950 | \f |
c572e5ba JVA |
1951 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1952 | return the mode to be used for the comparison. | |
1953 | ||
1954 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 1955 | VOIDmode should be used in all other cases. |
c572e5ba | 1956 | |
16189740 | 1957 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 1958 | possible, to allow for more combinations. */ |
c98f8742 | 1959 | |
d9a5f180 | 1960 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 1961 | |
9cd10576 | 1962 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
1963 | reversed. */ |
1964 | ||
1965 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1966 | ||
1967 | /* A C expression whose value is reversed condition code of the CODE for | |
1968 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 1969 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 1970 | |
c98f8742 JVA |
1971 | \f |
1972 | /* Control the assembler format that we output, to the extent | |
1973 | this does not vary between assemblers. */ | |
1974 | ||
1975 | /* How to refer to registers in assembler output. | |
892a2d68 | 1976 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 1977 | |
a7b376ee | 1978 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
1979 | For non floating point regs, the following are the HImode names. |
1980 | ||
1981 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
1982 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
1983 | "y" code. */ | |
c98f8742 | 1984 | |
a7180f70 BS |
1985 | #define HI_REGISTER_NAMES \ |
1986 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 1987 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
eaa17c21 | 1988 | "argp", "flags", "fpsr", "frame", \ |
a7180f70 | 1989 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 1990 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 1991 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
1992 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
1993 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
1994 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
1995 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 1996 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
eafa30ef | 1997 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } |
a7180f70 | 1998 | |
c98f8742 JVA |
1999 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2000 | ||
50bec228 UB |
2001 | #define QI_REGISTER_NAMES \ |
2002 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl"} | |
2003 | ||
2004 | #define QI_HIGH_REGISTER_NAMES \ | |
2005 | {"ah", "dh", "ch", "bh"} | |
2006 | ||
c98f8742 JVA |
2007 | /* Table of additional register names to use in user input. */ |
2008 | ||
eaa17c21 UB |
2009 | #define ADDITIONAL_REGISTER_NAMES \ |
2010 | { \ | |
2011 | { "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \ | |
2012 | { "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \ | |
2013 | { "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \ | |
2014 | { "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \ | |
2015 | { "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \ | |
50bec228 | 2016 | { "sil", SI_REG }, { "dil", DI_REG }, { "bpl", BP_REG }, { "spl", SP_REG }, \ |
eaa17c21 UB |
2017 | { "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \ |
2018 | { "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \ | |
2019 | { "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \ | |
2020 | { "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \ | |
2021 | { "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \ | |
2022 | { "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \ | |
2023 | { "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \ | |
2024 | { "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \ | |
2025 | { "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \ | |
2026 | { "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \ | |
2027 | { "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \ | |
2028 | { "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \ | |
2029 | { "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \ | |
2030 | { "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \ | |
2031 | { "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \ | |
2032 | { "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \ | |
2033 | { "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \ | |
2034 | } | |
c98f8742 | 2035 | |
ca60bd93 | 2036 | /* How to renumber registers for gdb. */ |
c98f8742 | 2037 | |
ca60bd93 ML |
2038 | #define DEBUGGER_REGNO(N) \ |
2039 | (TARGET_64BIT ? debugger64_register_map[(N)] : debugger_register_map[(N)]) | |
83774849 | 2040 | |
ca60bd93 ML |
2041 | extern int const debugger_register_map[FIRST_PSEUDO_REGISTER]; |
2042 | extern int const debugger64_register_map[FIRST_PSEUDO_REGISTER]; | |
2043 | extern int const svr4_debugger_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2044 | |
469ac993 JM |
2045 | /* Before the prologue, RA is at 0(%esp). */ |
2046 | #define INCOMING_RETURN_ADDR_RTX \ | |
2efb4214 | 2047 | gen_rtx_MEM (Pmode, stack_pointer_rtx) |
fce5a9f2 | 2048 | |
e414ab29 | 2049 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1a6e82b8 UB |
2050 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2051 | ((COUNT) == 0 \ | |
2052 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ | |
2053 | -UNITS_PER_WORD)) \ | |
2054 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, (FRAME), UNITS_PER_WORD))) | |
e414ab29 | 2055 | |
892a2d68 | 2056 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2057 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2058 | |
a10b3cf1 L |
2059 | /* Before the prologue, there are return address and error code for |
2060 | exception handler on the top of the frame. */ | |
2061 | #define INCOMING_FRAME_SP_OFFSET \ | |
2062 | (cfun->machine->func_type == TYPE_EXCEPTION \ | |
2063 | ? 2 * UNITS_PER_WORD : UNITS_PER_WORD) | |
a6ab3aad | 2064 | |
26fc730d JJ |
2065 | /* The value of INCOMING_FRAME_SP_OFFSET the assembler assumes in |
2066 | .cfi_startproc. */ | |
2067 | #define DEFAULT_INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD | |
2068 | ||
1020a5ab | 2069 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2070 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2071 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2072 | |
ad919812 | 2073 | |
e4c4ebeb RH |
2074 | /* Select a format to encode pointers in exception handling data. CODE |
2075 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2076 | true if the symbol may be affected by dynamic relocations. | |
2077 | ||
2078 | ??? All x86 object file formats are capable of representing this. | |
2079 | After all, the relocation needed is the same as for the call insn. | |
2080 | Whether or not a particular assembler allows us to enter such, I | |
2081 | guess we'll have to see. */ | |
d9a5f180 | 2082 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2083 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2084 | |
ec1895c1 UB |
2085 | /* These are a couple of extensions to the formats accepted |
2086 | by asm_fprintf: | |
2087 | %z prints out opcode suffix for word-mode instruction | |
2088 | %r prints out word-mode name for reg_names[arg] */ | |
2089 | #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ | |
2090 | case 'z': \ | |
2091 | fputc (TARGET_64BIT ? 'q' : 'l', (FILE)); \ | |
2092 | break; \ | |
2093 | \ | |
2094 | case 'r': \ | |
2095 | { \ | |
2096 | unsigned int regno = va_arg ((ARGS), int); \ | |
2097 | if (LEGACY_INT_REGNO_P (regno)) \ | |
2098 | fputc (TARGET_64BIT ? 'r' : 'e', (FILE)); \ | |
2099 | fputs (reg_names[regno], (FILE)); \ | |
2100 | break; \ | |
2101 | } | |
2102 | ||
2103 | /* This is how to output an insn to push a register on the stack. */ | |
2104 | ||
2105 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
2106 | asm_fprintf ((FILE), "\tpush%z\t%%%r\n", (REGNO)) | |
2107 | ||
2108 | /* This is how to output an insn to pop a register from the stack. */ | |
c98f8742 | 2109 | |
d9a5f180 | 2110 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
ec1895c1 | 2111 | asm_fprintf ((FILE), "\tpop%z\t%%%r\n", (REGNO)) |
c98f8742 | 2112 | |
f88c65f7 | 2113 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2114 | |
2115 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2116 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2117 | |
f88c65f7 | 2118 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2119 | |
33f7f353 | 2120 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2121 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2122 | |
63001560 | 2123 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2124 | |
2125 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2126 | { \ | |
2127 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2128 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2129 | } |
2130 | ||
2131 | /* A C statement or statements which output an assembler instruction | |
2132 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2133 | variable of type `char *' which points to the opcode name in | |
2134 | its "internal" form--the form that is written in the machine | |
2135 | description. */ | |
2136 | ||
2137 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2138 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2139 | ||
6a90d232 L |
2140 | /* A C statement to output to the stdio stream FILE an assembler |
2141 | command to pad the location counter to a multiple of 1<<LOG | |
2142 | bytes if it is within MAX_SKIP bytes. */ | |
2143 | ||
2144 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
c4551a27 AO |
2145 | # define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ |
2146 | do { \ | |
2147 | if ((LOG) != 0) { \ | |
dd047c67 | 2148 | if ((MAX_SKIP) == 0 || (MAX_SKIP) >= (1 << (LOG)) - 1) \ |
c4551a27 | 2149 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ |
6a90d232 | 2150 | else \ |
c4551a27 AO |
2151 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ |
2152 | } \ | |
2153 | } while (0) | |
6a90d232 L |
2154 | #endif |
2155 | ||
135a687e KT |
2156 | /* Write the extra assembler code needed to declare a function |
2157 | properly. */ | |
2158 | ||
2159 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2160 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
1a6e82b8 | 2161 | ix86_asm_output_function_label ((FILE), (NAME), (DECL)) |
135a687e | 2162 | |
c892d8f5 JJ |
2163 | /* A C statement (sans semicolon) to output a reference to SYMBOL_REF SYM. |
2164 | If not defined, assemble_name will be used to output the name of the | |
2165 | symbol. This macro may be used to modify the way a symbol is referenced | |
2166 | depending on information encoded by TARGET_ENCODE_SECTION_INFO. */ | |
2167 | ||
2168 | #ifndef ASM_OUTPUT_SYMBOL_REF | |
2169 | #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) \ | |
2170 | do { \ | |
2171 | const char *name \ | |
2172 | = assemble_name_resolve (XSTR (x, 0)); \ | |
2173 | /* In -masm=att wrap identifiers that start with $ \ | |
2174 | into parens. */ \ | |
2175 | if (ASSEMBLER_DIALECT == ASM_ATT \ | |
2176 | && name[0] == '$' \ | |
2177 | && user_label_prefix[0] == '\0') \ | |
2178 | { \ | |
2179 | fputc ('(', (FILE)); \ | |
2180 | assemble_name_raw ((FILE), name); \ | |
2181 | fputc (')', (FILE)); \ | |
2182 | } \ | |
2183 | else \ | |
2184 | assemble_name_raw ((FILE), name); \ | |
2185 | } while (0) | |
2186 | #endif | |
2187 | ||
f7288899 EC |
2188 | /* Under some conditions we need jump tables in the text section, |
2189 | because the assembler cannot handle label differences between | |
85e10e4f | 2190 | sections. */ |
f88c65f7 RH |
2191 | |
2192 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
85e10e4f | 2193 | (flag_pic && !(TARGET_64BIT || HAVE_AS_GOTOFF_IN_DATA)) |
c98f8742 | 2194 | |
cea3bd3e RH |
2195 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2196 | and switch back. For x86 we do this only to save a few bytes that | |
2197 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2198 | #define CRT_MKSTR2(VAL) #VAL |
2199 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2200 | ||
2201 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2202 | asm (SECTION_OP "\n\t" \ | |
2203 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2204 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2205 | |
2206 | /* Default threshold for putting data in large sections | |
2207 | with x86-64 medium memory model */ | |
2208 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
74b42c8b | 2209 | \f |
b97de419 | 2210 | /* Which processor to tune code generation for. These must be in sync |
e53b6e56 | 2211 | with processor_target_table in i386.cc. */ |
5bf0ebab RH |
2212 | |
2213 | enum processor_type | |
2214 | { | |
b97de419 L |
2215 | PROCESSOR_GENERIC = 0, |
2216 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2217 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2218 | PROCESSOR_PENTIUM, | |
2d6b2e28 | 2219 | PROCESSOR_LAKEMONT, |
5bf0ebab | 2220 | PROCESSOR_PENTIUMPRO, |
5bf0ebab | 2221 | PROCESSOR_PENTIUM4, |
89c43c0a | 2222 | PROCESSOR_NOCONA, |
340ef734 | 2223 | PROCESSOR_CORE2, |
d3c11974 L |
2224 | PROCESSOR_NEHALEM, |
2225 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2226 | PROCESSOR_HASWELL, |
d3c11974 L |
2227 | PROCESSOR_BONNELL, |
2228 | PROCESSOR_SILVERMONT, | |
50e461df | 2229 | PROCESSOR_GOLDMONT, |
74b2bb19 | 2230 | PROCESSOR_GOLDMONT_PLUS, |
a548a5a1 | 2231 | PROCESSOR_TREMONT, |
fabe470b | 2232 | PROCESSOR_SIERRAFOREST, |
c4f8f8af | 2233 | PROCESSOR_GRANDRIDGE, |
52747219 | 2234 | PROCESSOR_KNL, |
cace2309 | 2235 | PROCESSOR_KNM, |
176a3386 | 2236 | PROCESSOR_SKYLAKE, |
06caf59d | 2237 | PROCESSOR_SKYLAKE_AVX512, |
c234d831 | 2238 | PROCESSOR_CANNONLAKE, |
79ab5364 JK |
2239 | PROCESSOR_ICELAKE_CLIENT, |
2240 | PROCESSOR_ICELAKE_SERVER, | |
7cab07f0 | 2241 | PROCESSOR_CASCADELAKE, |
a9fcfec3 HL |
2242 | PROCESSOR_TIGERLAKE, |
2243 | PROCESSOR_COOPERLAKE, | |
ba9c87d3 CL |
2244 | PROCESSOR_SAPPHIRERAPIDS, |
2245 | PROCESSOR_ALDERLAKE, | |
c02c39fa | 2246 | PROCESSOR_ROCKETLAKE, |
339ffc5a | 2247 | PROCESSOR_GRANITERAPIDS, |
9a7f94d7 | 2248 | PROCESSOR_INTEL, |
a239aff8 | 2249 | PROCESSOR_LUJIAZUI, |
b97de419 L |
2250 | PROCESSOR_GEODE, |
2251 | PROCESSOR_K6, | |
2252 | PROCESSOR_ATHLON, | |
2253 | PROCESSOR_K8, | |
21efb4d4 | 2254 | PROCESSOR_AMDFAM10, |
1133125e | 2255 | PROCESSOR_BDVER1, |
4d652a18 | 2256 | PROCESSOR_BDVER2, |
eb2f2b44 | 2257 | PROCESSOR_BDVER3, |
ed97ad47 | 2258 | PROCESSOR_BDVER4, |
14b52538 | 2259 | PROCESSOR_BTVER1, |
e32bfc16 | 2260 | PROCESSOR_BTVER2, |
9ce29eb0 | 2261 | PROCESSOR_ZNVER1, |
2901f42f | 2262 | PROCESSOR_ZNVER2, |
3e2ae3ee | 2263 | PROCESSOR_ZNVER3, |
bf3b532b | 2264 | PROCESSOR_ZNVER4, |
5bf0ebab RH |
2265 | PROCESSOR_max |
2266 | }; | |
2267 | ||
c98c2430 | 2268 | #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS) |
2559ef9f | 2269 | extern const char *const processor_names[]; |
c98c2430 ML |
2270 | |
2271 | #include "wide-int-bitmask.h" | |
2272 | ||
14431e66 ML |
2273 | enum pta_flag |
2274 | { | |
2275 | #define DEF_PTA(NAME) _ ## NAME, | |
2276 | #include "i386-isa.def" | |
2277 | #undef DEF_PTA | |
2278 | END_PTA | |
2279 | }; | |
2280 | ||
2281 | /* wide_int_bitmask can handle only 128 flags. */ | |
2282 | STATIC_ASSERT (END_PTA <= 128); | |
2283 | ||
2284 | #define WIDE_INT_BITMASK_FROM_NTH(N) (N < 64 ? wide_int_bitmask (0, 1ULL << N) \ | |
2285 | : wide_int_bitmask (1ULL << (N - 64), 0)) | |
2286 | ||
2287 | #define DEF_PTA(NAME) constexpr wide_int_bitmask PTA_ ## NAME \ | |
2288 | = WIDE_INT_BITMASK_FROM_NTH ((pta_flag) _ ## NAME); | |
2289 | #include "i386-isa.def" | |
2290 | #undef DEF_PTA | |
a1541628 JJ |
2291 | |
2292 | constexpr wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE | |
324bec55 | 2293 | | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR; |
a1541628 JJ |
2294 | constexpr wide_int_bitmask PTA_X86_64_V2 = (PTA_X86_64_BASELINE |
2295 | & (~PTA_NO_SAHF)) | |
324bec55 | 2296 | | PTA_CX16 | PTA_POPCNT | PTA_SSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_SSSE3; |
a1541628 | 2297 | constexpr wide_int_bitmask PTA_X86_64_V3 = PTA_X86_64_V2 |
324bec55 FW |
2298 | | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT |
2299 | | PTA_MOVBE | PTA_XSAVE; | |
a1541628 | 2300 | constexpr wide_int_bitmask PTA_X86_64_V4 = PTA_X86_64_V3 |
324bec55 | 2301 | | PTA_AVX512F | PTA_AVX512BW | PTA_AVX512CD | PTA_AVX512DQ | PTA_AVX512VL; |
299a53d7 | 2302 | |
a1541628 | 2303 | constexpr wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 |
c98c2430 | 2304 | | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR; |
a1541628 | 2305 | constexpr wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 |
c98c2430 | 2306 | | PTA_POPCNT; |
a1541628 JJ |
2307 | constexpr wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL; |
2308 | constexpr wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE | |
c98c2430 | 2309 | | PTA_XSAVEOPT; |
a1541628 | 2310 | constexpr wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE |
c98c2430 | 2311 | | PTA_RDRND | PTA_F16C; |
a1541628 | 2312 | constexpr wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI |
c98c2430 | 2313 | | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE; |
a1541628 | 2314 | constexpr wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_RDSEED |
c2099c16 | 2315 | | PTA_PRFCHW; |
a1541628 JJ |
2316 | constexpr wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES |
2317 | | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SGX; | |
2318 | constexpr wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | |
c98c2430 ML |
2319 | | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU |
2320 | | PTA_CLWB; | |
a1541628 JJ |
2321 | constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 |
2322 | | PTA_AVX512VNNI; | |
2323 | constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; | |
2324 | constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | |
c98c2430 ML |
2325 | | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU |
2326 | | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; | |
a1541628 | 2327 | constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI |
c98c2430 | 2328 | | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG |
c422e5f8 | 2329 | | PTA_RDPID | PTA_AVX512VPOPCNTDQ; |
c02c39fa | 2330 | constexpr wide_int_bitmask PTA_ROCKETLAKE = PTA_ICELAKE_CLIENT & ~PTA_SGX; |
a1541628 JJ |
2331 | constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT |
2332 | | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB; | |
2333 | constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI | |
632a2f50 | 2334 | | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL; |
16fe6e8c | 2335 | constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI |
11c72f20 CL |
2336 | | PTA_MOVDIR64B | PTA_ENQCMD | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG |
2337 | | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | |
2338 | | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16 | PTA_AVX512BF16; | |
a1541628 JJ |
2339 | constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF |
2340 | | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1; | |
2341 | constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; | |
2342 | constexpr wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | |
2343 | | PTA_RDRND | PTA_PRFCHW; | |
2344 | constexpr wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | |
2345 | | PTA_XSAVE | PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | |
2346 | | PTA_XSAVEOPT | PTA_FSGSBASE; | |
2347 | constexpr wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID | |
41f8d1fc | 2348 | | PTA_SGX | PTA_PTWRITE; |
a1541628 | 2349 | constexpr wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB |
dc7e8839 | 2350 | | PTA_GFNI | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_CLDEMOTE | PTA_WAITPKG; |
f2be0833 CL |
2351 | constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT | PTA_ADX | PTA_AVX |
2352 | | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_LZCNT | |
2353 | | PTA_PCONFIG | PTA_PKU | PTA_VAES | PTA_VPCLMULQDQ | PTA_SERIALIZE | |
2354 | | PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI; | |
fabe470b HJ |
2355 | constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA |
2356 | | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD; | |
339ffc5a HJ |
2357 | constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 |
2358 | | PTA_PREFETCHI; | |
c4f8f8af | 2359 | constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; |
a1541628 | 2360 | constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW |
c98c2430 | 2361 | | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; |
bf3b532b TJ |
2362 | constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 |
2363 | | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 | |
2364 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 | PTA_BMI | PTA_BMI2 | |
2365 | | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | |
2366 | | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED | |
2367 | | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES | PTA_SHA | PTA_LZCNT | |
2368 | | PTA_POPCNT; | |
2369 | constexpr wide_int_bitmask PTA_ZNVER2 = PTA_ZNVER1 | PTA_CLWB | PTA_RDPID | |
2370 | | PTA_WBNOINVD; | |
2371 | constexpr wide_int_bitmask PTA_ZNVER3 = PTA_ZNVER2 | PTA_VAES | PTA_VPCLMULQDQ | |
2372 | | PTA_PKU; | |
2373 | constexpr wide_int_bitmask PTA_ZNVER4 = PTA_ZNVER3 | PTA_AVX512F | PTA_AVX512DQ | |
2374 | | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL | |
2375 | | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI | |
2376 | | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ; | |
c98c2430 ML |
2377 | |
2378 | #ifndef GENERATOR_FILE | |
2379 | ||
2380 | #include "insn-attr-common.h" | |
2381 | ||
3fb2c2f4 L |
2382 | #include "common/config/i386/i386-cpuinfo.h" |
2383 | ||
6c1dae73 | 2384 | class pta |
c98c2430 | 2385 | { |
6c1dae73 | 2386 | public: |
c98c2430 ML |
2387 | const char *const name; /* processor name or nickname. */ |
2388 | const enum processor_type processor; | |
2389 | const enum attr_cpu schedule; | |
2390 | const wide_int_bitmask flags; | |
3fb2c2f4 L |
2391 | const int model; |
2392 | const enum feature_priority priority; | |
c98c2430 ML |
2393 | }; |
2394 | ||
2395 | extern const pta processor_alias_table[]; | |
5ebdd535 | 2396 | extern unsigned int const pta_size; |
3fb2c2f4 | 2397 | extern unsigned int const num_arch_names; |
c98c2430 ML |
2398 | #endif |
2399 | ||
2400 | #endif | |
2401 | ||
9e555526 | 2402 | extern enum processor_type ix86_tune; |
5bf0ebab | 2403 | extern enum processor_type ix86_arch; |
5bf0ebab | 2404 | |
8362f420 JH |
2405 | /* Size of the RED_ZONE area. */ |
2406 | #define RED_ZONE_SIZE 128 | |
2407 | /* Reserved area of the red zone for temporaries. */ | |
2408 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2409 | |
95899b34 | 2410 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2411 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2412 | |
2413 | /* Smallest class containing REGNO. */ | |
2414 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2415 | ||
0948ccb2 PB |
2416 | enum ix86_fpcmp_strategy { |
2417 | IX86_FPCMP_SAHF, | |
2418 | IX86_FPCMP_COMI, | |
2419 | IX86_FPCMP_ARITH | |
2420 | }; | |
22fb740d JH |
2421 | \f |
2422 | /* To properly truncate FP values into integers, we need to set i387 control | |
2423 | word. We can't emit proper mode switching code before reload, as spills | |
2424 | generated by reload may truncate values incorrectly, but we still can avoid | |
2425 | redundant computation of new control word by the mode switching pass. | |
2426 | The fldcw instructions are still emitted redundantly, but this is probably | |
2427 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2428 | the sequence. |
22fb740d JH |
2429 | |
2430 | The machinery is to emit simple truncation instructions and split them | |
2431 | before reload to instructions having USEs of two memory locations that | |
2432 | are filled by this code to old and new control word. | |
fce5a9f2 | 2433 | |
22fb740d JH |
2434 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2435 | needed. */ | |
2436 | ||
c7ca8ef8 UB |
2437 | enum ix86_stack_slot |
2438 | { | |
2439 | SLOT_TEMP = 0, | |
2440 | SLOT_CW_STORED, | |
d3b92f35 | 2441 | SLOT_CW_ROUNDEVEN, |
c7ca8ef8 UB |
2442 | SLOT_CW_TRUNC, |
2443 | SLOT_CW_FLOOR, | |
2444 | SLOT_CW_CEIL, | |
80008279 | 2445 | SLOT_STV_TEMP, |
eabf7bbe | 2446 | SLOT_FLOATxFDI_387, |
c7ca8ef8 UB |
2447 | MAX_386_STACK_LOCALS |
2448 | }; | |
2449 | ||
ff680eb1 UB |
2450 | enum ix86_entity |
2451 | { | |
c7ca8ef8 UB |
2452 | X86_DIRFLAG = 0, |
2453 | AVX_U128, | |
d3b92f35 | 2454 | I387_ROUNDEVEN, |
ff97910d | 2455 | I387_TRUNC, |
ff680eb1 UB |
2456 | I387_FLOOR, |
2457 | I387_CEIL, | |
ff680eb1 UB |
2458 | MAX_386_ENTITIES |
2459 | }; | |
2460 | ||
c7ca8ef8 | 2461 | enum x86_dirflag_state |
ff680eb1 | 2462 | { |
c7ca8ef8 UB |
2463 | X86_DIRFLAG_RESET, |
2464 | X86_DIRFLAG_ANY | |
ff680eb1 | 2465 | }; |
22fb740d | 2466 | |
ff97910d VY |
2467 | enum avx_u128_state |
2468 | { | |
2469 | AVX_U128_CLEAN, | |
2470 | AVX_U128_DIRTY, | |
2471 | AVX_U128_ANY | |
2472 | }; | |
2473 | ||
22fb740d JH |
2474 | /* Define this macro if the port needs extra instructions inserted |
2475 | for mode switching in an optimizing compilation. */ | |
2476 | ||
ff680eb1 UB |
2477 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2478 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2479 | |
2480 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2481 | initializer for an array of integers. Each initializer element N | |
2482 | refers to an entity that needs mode switching, and specifies the | |
2483 | number of different modes that might need to be set for this | |
2484 | entity. The position of the initializer in the initializer - | |
2485 | starting counting at zero - determines the integer that is used to | |
2486 | refer to the mode-switched entity in question. */ | |
2487 | ||
c7ca8ef8 UB |
2488 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2489 | { X86_DIRFLAG_ANY, AVX_U128_ANY, \ | |
d3b92f35 | 2490 | I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
22fb740d | 2491 | |
0f0138b6 JH |
2492 | \f |
2493 | /* Avoid renaming of stack registers, as doing so in combination with | |
2494 | scheduling just increases amount of live registers at time and in | |
2495 | the turn amount of fxch instructions needed. | |
2496 | ||
3f97cb0b AI |
2497 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2498 | ||
2499 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2500 | |
1a6e82b8 UB |
2501 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
2502 | (!STACK_REGNO_P (SRC) \ | |
2503 | && EXT_REX_SSE_REGNO_P (SRC) == EXT_REX_SSE_REGNO_P (TARGET)) | |
22fb740d | 2504 | |
3b3c6a3f | 2505 | \f |
e91f04de | 2506 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2507 | \f |
77560086 BE |
2508 | #ifndef USED_FOR_TARGET |
2509 | /* Structure describing stack frame layout. | |
2510 | Stack grows downward: | |
2511 | ||
2512 | [arguments] | |
2513 | <- ARG_POINTER | |
2514 | saved pc | |
2515 | ||
2516 | saved static chain if ix86_static_chain_on_stack | |
2517 | ||
2518 | saved frame pointer if frame_pointer_needed | |
2519 | <- HARD_FRAME_POINTER | |
2520 | [saved regs] | |
2521 | <- reg_save_offset | |
2522 | [padding0] | |
2523 | <- stack_realign_offset | |
2524 | [saved SSE regs] | |
2525 | OR | |
2526 | [stub-saved registers for ms x64 --> sysv clobbers | |
2527 | <- Start of out-of-line, stub-saved/restored regs | |
2528 | (see libgcc/config/i386/(sav|res)ms64*.S) | |
2529 | [XMM6-15] | |
2530 | [RSI] | |
2531 | [RDI] | |
2532 | [?RBX] only if RBX is clobbered | |
2533 | [?RBP] only if RBP and RBX are clobbered | |
2534 | [?R12] only if R12 and all previous regs are clobbered | |
2535 | [?R13] only if R13 and all previous regs are clobbered | |
2536 | [?R14] only if R14 and all previous regs are clobbered | |
2537 | [?R15] only if R15 and all previous regs are clobbered | |
2538 | <- end of stub-saved/restored regs | |
2539 | [padding1] | |
2540 | ] | |
5d9d834d | 2541 | <- sse_reg_save_offset |
77560086 BE |
2542 | [padding2] |
2543 | | <- FRAME_POINTER | |
2544 | [va_arg registers] | | |
2545 | | | |
2546 | [frame] | | |
2547 | | | |
2548 | [padding2] | = to_allocate | |
2549 | <- STACK_POINTER | |
2550 | */ | |
2551 | struct GTY(()) ix86_frame | |
2552 | { | |
2553 | int nsseregs; | |
2554 | int nregs; | |
2555 | int va_arg_size; | |
2556 | int red_zone_size; | |
2557 | int outgoing_arguments_size; | |
2558 | ||
2559 | /* The offsets relative to ARG_POINTER. */ | |
2560 | HOST_WIDE_INT frame_pointer_offset; | |
2561 | HOST_WIDE_INT hard_frame_pointer_offset; | |
2562 | HOST_WIDE_INT stack_pointer_offset; | |
2563 | HOST_WIDE_INT hfp_save_offset; | |
2564 | HOST_WIDE_INT reg_save_offset; | |
122f9da1 | 2565 | HOST_WIDE_INT stack_realign_allocate; |
77560086 | 2566 | HOST_WIDE_INT stack_realign_offset; |
77560086 BE |
2567 | HOST_WIDE_INT sse_reg_save_offset; |
2568 | ||
2569 | /* When save_regs_using_mov is set, emit prologue using | |
2570 | move instead of push instructions. */ | |
2571 | bool save_regs_using_mov; | |
2f007861 RS |
2572 | |
2573 | /* Assume without checking that: | |
2574 | EXPENSIVE_P = expensive_function_p (EXPENSIVE_COUNT). */ | |
2575 | bool expensive_p; | |
2576 | int expensive_count; | |
77560086 BE |
2577 | }; |
2578 | ||
122f9da1 DS |
2579 | /* Machine specific frame tracking during prologue/epilogue generation. All |
2580 | values are positive, but since the x86 stack grows downward, are subtratced | |
2581 | from the CFA to produce a valid address. */ | |
cd9c1ca8 | 2582 | |
ec7ded37 | 2583 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2584 | { |
ec7ded37 RH |
2585 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2586 | is drap_reg, we don't bother trying to record here the real CFA when | |
2587 | it might really be a DW_CFA_def_cfa_expression. */ | |
2588 | rtx cfa_reg; | |
2589 | HOST_WIDE_INT cfa_offset; | |
2590 | ||
2591 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2592 | When stack frame re-alignment is active, these may not be relative | |
2593 | to the CFA. However, in all cases they are relative to the offsets | |
2594 | of the saved registers stored in ix86_frame. */ | |
2595 | HOST_WIDE_INT sp_offset; | |
2596 | HOST_WIDE_INT fp_offset; | |
2597 | ||
2598 | /* The size of the red-zone that may be assumed for the purposes of | |
2599 | eliding register restore notes in the epilogue. This may be zero | |
2600 | if no red-zone is in effect, or may be reduced from the real | |
2601 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2602 | int red_zone_offset; | |
2603 | ||
2604 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2605 | value within the frame. If false then the offset above should be | |
2606 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2607 | thus has an offset of zero. */ | |
2608 | BOOL_BITFIELD sp_valid : 1; | |
2609 | BOOL_BITFIELD fp_valid : 1; | |
2610 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2611 | |
2612 | /* Indicate whether the local stack frame has been re-aligned. When | |
2613 | set, the SP/FP offsets above are relative to the aligned frame | |
2614 | and not the CFA. */ | |
2615 | BOOL_BITFIELD realigned : 1; | |
d6d4d770 DS |
2616 | |
2617 | /* Indicates whether the stack pointer has been re-aligned. When set, | |
2618 | SP/FP continue to be relative to the CFA, but the stack pointer | |
122f9da1 DS |
2619 | should only be used for offsets > sp_realigned_offset, while |
2620 | the frame pointer should be used for offsets <= sp_realigned_fp_last. | |
d6d4d770 DS |
2621 | The flags realigned and sp_realigned are mutually exclusive. */ |
2622 | BOOL_BITFIELD sp_realigned : 1; | |
2623 | ||
122f9da1 DS |
2624 | /* If sp_realigned is set, this is the last valid offset from the CFA |
2625 | that can be used for access with the frame pointer. */ | |
2626 | HOST_WIDE_INT sp_realigned_fp_last; | |
2627 | ||
2628 | /* If sp_realigned is set, this is the offset from the CFA that the stack | |
2629 | pointer was realigned, and may or may not be equal to sp_realigned_fp_last. | |
2630 | Access via the stack pointer is only valid for offsets that are greater than | |
2631 | this value. */ | |
d6d4d770 | 2632 | HOST_WIDE_INT sp_realigned_offset; |
cd9c1ca8 RH |
2633 | }; |
2634 | ||
e53b6e56 | 2635 | /* Private to winnt.cc. */ |
f81c9774 RH |
2636 | struct seh_frame_state; |
2637 | ||
f8071c05 L |
2638 | enum function_type |
2639 | { | |
2640 | TYPE_UNKNOWN = 0, | |
2641 | TYPE_NORMAL, | |
2642 | /* The current function is an interrupt service routine with a | |
2643 | pointer argument as specified by the "interrupt" attribute. */ | |
2644 | TYPE_INTERRUPT, | |
2645 | /* The current function is an interrupt service routine with a | |
2646 | pointer argument and an integer argument as specified by the | |
2647 | "interrupt" attribute. */ | |
2648 | TYPE_EXCEPTION | |
2649 | }; | |
2650 | ||
3dcea658 L |
2651 | enum queued_insn_type |
2652 | { | |
2653 | TYPE_NONE = 0, | |
2654 | TYPE_ENDBR, | |
2655 | TYPE_PATCHABLE_AREA | |
2656 | }; | |
2657 | ||
d1b38208 | 2658 | struct GTY(()) machine_function { |
fa1a0d02 | 2659 | struct stack_local_entry *stack_locals; |
4aab97f9 L |
2660 | int varargs_gpr_size; |
2661 | int varargs_fpr_size; | |
ff680eb1 | 2662 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b | 2663 | |
77560086 BE |
2664 | /* Cached initial frame layout for the current function. */ |
2665 | struct ix86_frame frame; | |
3452586b | 2666 | |
7458026b ILT |
2667 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2668 | the stack arguments for a function with a variable number of | |
2669 | arguments. This is set at the start of the function and is used | |
2670 | to initialize the overflow_arg_area field of the va_list | |
2671 | structure. */ | |
2672 | rtx split_stack_varargs_pointer; | |
2673 | ||
3452586b RH |
2674 | /* This value is used for amd64 targets and specifies the current abi |
2675 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2676 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2677 | |
2678 | /* Nonzero if the function accesses a previous frame. */ | |
2679 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2680 | ||
922e3e33 UB |
2681 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2682 | expander to determine the style used. */ | |
3452586b RH |
2683 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2684 | ||
1e4490dc UB |
2685 | /* Nonzero if the current function calls pc thunk and |
2686 | must not use the red zone. */ | |
2687 | BOOL_BITFIELD pc_thunk_call_expanded : 1; | |
2688 | ||
5bf5a10b AO |
2689 | /* If true, the current function needs the default PIC register, not |
2690 | an alternate register (on x86) and must not use the red zone (on | |
2691 | x86_64), even if it's a leaf function. We don't want the | |
2692 | function to be regarded as non-leaf because TLS calls need not | |
2693 | affect register allocation. This flag is set when a TLS call | |
2694 | instruction is expanded within a function, and never reset, even | |
2695 | if all such instructions are optimized away. Use the | |
2696 | ix86_current_function_calls_tls_descriptor macro for a better | |
2697 | approximation. */ | |
3452586b RH |
2698 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2699 | ||
2700 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2701 | stack below the return address. */ | |
2702 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2703 | |
529a6471 JJ |
2704 | /* If true, it is safe to not save/restore DRAP register. */ |
2705 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2706 | ||
f8071c05 L |
2707 | /* Function type. */ |
2708 | ENUM_BITFIELD(function_type) func_type : 2; | |
2709 | ||
da99fd4a L |
2710 | /* How to generate indirec branch. */ |
2711 | ENUM_BITFIELD(indirect_branch) indirect_branch_type : 3; | |
2712 | ||
2713 | /* If true, the current function has local indirect jumps, like | |
2714 | "indirect_jump" or "tablejump". */ | |
2715 | BOOL_BITFIELD has_local_indirect_jump : 1; | |
2716 | ||
45e14019 L |
2717 | /* How to generate function return. */ |
2718 | ENUM_BITFIELD(indirect_branch) function_return_type : 3; | |
2719 | ||
f8071c05 L |
2720 | /* If true, the current function is a function specified with |
2721 | the "interrupt" or "no_caller_saved_registers" attribute. */ | |
2722 | BOOL_BITFIELD no_caller_saved_registers : 1; | |
2723 | ||
a0ff7835 L |
2724 | /* If true, there is register available for argument passing. This |
2725 | is used only in ix86_function_ok_for_sibcall by 32-bit to determine | |
2726 | if there is scratch register available for indirect sibcall. In | |
2727 | 64-bit, rax, r10 and r11 are scratch registers which aren't used to | |
2728 | pass arguments and can be used for indirect sibcall. */ | |
2729 | BOOL_BITFIELD arg_reg_available : 1; | |
2730 | ||
d6d4d770 | 2731 | /* If true, we're out-of-lining reg save/restore for regs clobbered |
5d9d834d | 2732 | by 64-bit ms_abi functions calling a sysv_abi function. */ |
d6d4d770 DS |
2733 | BOOL_BITFIELD call_ms2sysv : 1; |
2734 | ||
2735 | /* If true, the incoming 16-byte aligned stack has an offset (of 8) and | |
5d9d834d | 2736 | needs padding prior to out-of-line stub save/restore area. */ |
d6d4d770 DS |
2737 | BOOL_BITFIELD call_ms2sysv_pad_in : 1; |
2738 | ||
d6d4d770 DS |
2739 | /* This is the number of extra registers saved by stub (valid range is |
2740 | 0-6). Each additional register is only saved/restored by the stubs | |
2741 | if all successive ones are. (Will always be zero when using a hard | |
2742 | frame pointer.) */ | |
2743 | unsigned int call_ms2sysv_extra_regs:3; | |
2744 | ||
35c95658 L |
2745 | /* Nonzero if the function places outgoing arguments on stack. */ |
2746 | BOOL_BITFIELD outgoing_args_on_stack : 1; | |
2747 | ||
3dcea658 L |
2748 | /* If true, ENDBR or patchable area is queued at function entrance. */ |
2749 | ENUM_BITFIELD(queued_insn_type) insn_queued_at_entrance : 2; | |
2750 | ||
2751 | /* If true, the function label has been emitted. */ | |
2752 | BOOL_BITFIELD function_label_emitted : 1; | |
708c728d | 2753 | |
c2080a1f L |
2754 | /* True if the function needs a stack frame. */ |
2755 | BOOL_BITFIELD stack_frame_required : 1; | |
2756 | ||
5e2eabe1 L |
2757 | /* True if we should act silently, rather than raise an error for |
2758 | invalid calls. */ | |
2759 | BOOL_BITFIELD silent_p : 1; | |
2760 | ||
3f04e378 L |
2761 | /* True if red zone is used. */ |
2762 | BOOL_BITFIELD red_zone_used : 1; | |
2763 | ||
cd3410cc L |
2764 | /* The largest alignment, in bytes, of stack slot actually used. */ |
2765 | unsigned int max_used_stack_alignment; | |
2766 | ||
ec7ded37 RH |
2767 | /* During prologue/epilogue generation, the current frame state. |
2768 | Otherwise, the frame state at the end of the prologue. */ | |
2769 | struct machine_frame_state fs; | |
f81c9774 RH |
2770 | |
2771 | /* During SEH output, this is non-null. */ | |
2772 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2773 | }; |
2bf6d935 ML |
2774 | |
2775 | extern GTY(()) tree sysv_va_list_type_node; | |
2776 | extern GTY(()) tree ms_va_list_type_node; | |
cd9c1ca8 | 2777 | #endif |
fa1a0d02 JH |
2778 | |
2779 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2780 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2781 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2782 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
1e4490dc | 2783 | #define ix86_pc_thunk_call_expanded (cfun->machine->pc_thunk_call_expanded) |
5bf5a10b AO |
2784 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2785 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2786 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2787 | calls are optimized away, we try to detect cases in which it was | |
2788 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2789 | verify whether there's any such instruction live by testing that | |
2790 | REG_SP is live. */ | |
2791 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2792 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2793 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
3f04e378 | 2794 | #define ix86_red_zone_used (cfun->machine->red_zone_used) |
249e6b63 | 2795 | |
1bc7c5b6 ZW |
2796 | /* Control behavior of x86_file_start. */ |
2797 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2798 | #define X86_FILE_START_FLTUSED false | |
2799 | ||
7dcbf659 JH |
2800 | /* Flag to mark data that is in the large address area. */ |
2801 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2802 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2803 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2804 | |
2805 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2806 | have defined always, to avoid ifdefing. */ | |
2807 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2808 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2809 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2810 | ||
2811 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2812 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2813 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2814 | ||
82c0e1a0 KT |
2815 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2816 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2817 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2818 | ||
7942e47e RY |
2819 | extern void debug_ready_dispatch (void); |
2820 | extern void debug_dispatch_window (int); | |
2821 | ||
91afcfa3 QN |
2822 | /* The value at zero is only defined for the BMI instructions |
2823 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2824 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
4f73bf20 | 2825 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 2 : 0) |
91afcfa3 | 2826 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
4f73bf20 | 2827 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 2 : 0) |
91afcfa3 QN |
2828 | |
2829 | ||
b8ce4e94 KT |
2830 | /* Flags returned by ix86_get_callcvt (). */ |
2831 | #define IX86_CALLCVT_CDECL 0x1 | |
2832 | #define IX86_CALLCVT_STDCALL 0x2 | |
2833 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2834 | #define IX86_CALLCVT_THISCALL 0x8 | |
2835 | #define IX86_CALLCVT_REGPARM 0x10 | |
2836 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2837 | ||
2838 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2839 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2840 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2841 | ||
b86b9f44 MM |
2842 | #define RECIP_MASK_NONE 0x00 |
2843 | #define RECIP_MASK_DIV 0x01 | |
2844 | #define RECIP_MASK_SQRT 0x02 | |
2845 | #define RECIP_MASK_VEC_DIV 0x04 | |
2846 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2847 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2848 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2849 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2850 | |
2851 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2852 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2853 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2854 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2855 | ||
ab2c4ec8 SS |
2856 | /* Use 128-bit AVX instructions in the auto-vectorizer. */ |
2857 | #define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128) | |
2858 | /* Use 256-bit AVX instructions in the auto-vectorizer. */ | |
02a70367 SS |
2859 | #define TARGET_PREFER_AVX256 (TARGET_PREFER_AVX128 \ |
2860 | || prefer_vector_width_type == PVW_AVX256) | |
ab2c4ec8 | 2861 | |
c2c601b2 L |
2862 | #define TARGET_INDIRECT_BRANCH_REGISTER \ |
2863 | (ix86_indirect_branch_register \ | |
2864 | || cfun->machine->indirect_branch_type != indirect_branch_keep) | |
2865 | ||
5dcfdccd KY |
2866 | #define IX86_HLE_ACQUIRE (1 << 16) |
2867 | #define IX86_HLE_RELEASE (1 << 17) | |
2868 | ||
e83b8e2e JJ |
2869 | /* For switching between functions with different target attributes. */ |
2870 | #define SWITCHABLE_TARGET 1 | |
2871 | ||
44d0de8d UB |
2872 | #define TARGET_SUPPORTS_WIDE_INT 1 |
2873 | ||
2bf6d935 ML |
2874 | #if !defined(GENERATOR_FILE) && !defined(IN_LIBGCC2) |
2875 | extern enum attr_cpu ix86_schedule; | |
2876 | ||
2877 | #define NUM_X86_64_MS_CLOBBERED_REGS 12 | |
2878 | #endif | |
2879 | ||
da24fce3 JJ |
2880 | /* __builtin_eh_return can't handle stack realignment, so disable MMX/SSE |
2881 | in 32-bit libgcc functions that call it. */ | |
caa6c33c | 2882 | #ifndef __x86_64__ |
da24fce3 | 2883 | #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((target ("no-mmx,no-sse"))) |
caa6c33c JJ |
2884 | #endif |
2885 | ||
c98f8742 JVA |
2886 | /* |
2887 | Local variables: | |
2888 | version-control: t | |
2889 | End: | |
2890 | */ |