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e075ae69 | 1 | /* Definitions of target machine for GNU compiler for IA-32. |
4592bdcb JL |
2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000 |
3 | Free Software Foundation, Inc. | |
c98f8742 JVA |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
97aadbb9 | 19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
d4ba09c0 | 20 | Boston, MA 02111-1307, USA. */ |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
e075ae69 RH |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
c98f8742 | 36 | |
95393dfd CH |
37 | /* Stubs for half-pic support if not OSF/1 reference platform. */ |
38 | ||
39 | #ifndef HALF_PIC_P | |
40 | #define HALF_PIC_P() 0 | |
41 | #define HALF_PIC_NUMBER_PTRS 0 | |
42 | #define HALF_PIC_NUMBER_REFS 0 | |
43 | #define HALF_PIC_ENCODE(DECL) | |
44 | #define HALF_PIC_DECLARE(NAME) | |
45 | #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") | |
46 | #define HALF_PIC_ADDRESS_P(X) 0 | |
47 | #define HALF_PIC_PTR(X) X | |
48 | #define HALF_PIC_FINISH(STREAM) | |
49 | #endif | |
50 | ||
d4ba09c0 SC |
51 | /* Define the specific costs for a given cpu */ |
52 | ||
53 | struct processor_costs { | |
54 | int add; /* cost of an add instruction */ | |
55 | int lea; /* cost of a lea instruction */ | |
56 | int shift_var; /* variable shift costs */ | |
57 | int shift_const; /* constant shift costs */ | |
58 | int mult_init; /* cost of starting a multiply */ | |
59 | int mult_bit; /* cost of multiply per each bit set */ | |
60 | int divide; /* cost of a divide/mod */ | |
e075ae69 | 61 | int large_insn; /* insns larger than this cost more */ |
e2e52e1b JH |
62 | int move_ratio; /* The threshold of number of scalar memory-to-memory |
63 | move insns. */ | |
7c6b971d | 64 | int movzbl_load; /* cost of loading using movzbl */ |
96e7ae40 JH |
65 | int int_load[3]; /* cost of loading integer registers |
66 | in QImode, HImode and SImode relative | |
67 | to reg-reg move (2). */ | |
68 | int int_store[3]; /* cost of storing integer register | |
69 | in QImode, HImode and SImode */ | |
70 | int fp_move; /* cost of reg,reg fld/fst */ | |
71 | int fp_load[3]; /* cost of loading FP register | |
72 | in SFmode, DFmode and XFmode */ | |
73 | int fp_store[3]; /* cost of storing FP register | |
74 | in SFmode, DFmode and XFmode */ | |
d4ba09c0 SC |
75 | }; |
76 | ||
77 | extern struct processor_costs *ix86_cost; | |
78 | ||
c98f8742 JVA |
79 | /* Run-time compilation parameters selecting different hardware subsets. */ |
80 | ||
81 | extern int target_flags; | |
82 | ||
83 | /* Macros used in the machine description to test the flags. */ | |
84 | ||
ddd5a7c1 | 85 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 86 | |
35b528be RS |
87 | #ifndef TARGET_CPU_DEFAULT |
88 | #define TARGET_CPU_DEFAULT 0 | |
89 | #endif | |
90 | ||
3b3c6a3f | 91 | /* Masks for the -m switches */ |
e075ae69 RH |
92 | #define MASK_80387 0x00000001 /* Hardware floating point */ |
93 | #define MASK_RTD 0x00000002 /* Use ret that pops args */ | |
94 | #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */ | |
95 | #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */ | |
96 | #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */ | |
97 | #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */ | |
98 | #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */ | |
99 | #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */ | |
100 | #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */ | |
79f05c19 JH |
101 | #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */ |
102 | #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */ | |
e075ae69 RH |
103 | |
104 | /* Temporary codegen switches */ | |
dc174fb1 MM |
105 | #define MASK_INTEL_SYNTAX 0x00000200 |
106 | #define MASK_DEBUG_ARG 0x00000400 /* function_arg */ | |
107 | #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */ | |
3b3c6a3f MM |
108 | |
109 | /* Use the floating point instructions */ | |
110 | #define TARGET_80387 (target_flags & MASK_80387) | |
111 | ||
c98f8742 JVA |
112 | /* Compile using ret insn that pops args. |
113 | This will not work unless you use prototypes at least | |
114 | for all functions that can take varying numbers of args. */ | |
3b3c6a3f MM |
115 | #define TARGET_RTD (target_flags & MASK_RTD) |
116 | ||
b08de47e MM |
117 | /* Align doubles to a two word boundary. This breaks compatibility with |
118 | the published ABI's for structures containing doubles, but produces | |
119 | faster code on the pentium. */ | |
120 | #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) | |
c98f8742 | 121 | |
d7cd15e9 RS |
122 | /* Put uninitialized locals into bss, not data. |
123 | Meaningful only on svr3. */ | |
3b3c6a3f | 124 | #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) |
d7cd15e9 | 125 | |
c572e5ba JVA |
126 | /* Use IEEE floating point comparisons. These handle correctly the cases |
127 | where the result of a comparison is unordered. Normally SIGFPE is | |
128 | generated in such cases, in which case this isn't needed. */ | |
3b3c6a3f | 129 | #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) |
c572e5ba | 130 | |
8c2bf92a JVA |
131 | /* Functions that return a floating point value may return that value |
132 | in the 387 FPU or in 386 integer registers. If set, this flag causes | |
133 | the 387 to be used, which is compatible with most calling conventions. */ | |
3b3c6a3f | 134 | #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) |
8c2bf92a | 135 | |
099800e3 RK |
136 | /* Disable generation of FP sin, cos and sqrt operations for 387. |
137 | This is because FreeBSD lacks these in the math-emulator-code */ | |
3b3c6a3f MM |
138 | #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) |
139 | ||
2f2fa5b1 | 140 | /* Don't create frame pointers for leaf functions */ |
e075ae69 RH |
141 | #define TARGET_OMIT_LEAF_FRAME_POINTER \ |
142 | (target_flags & MASK_OMIT_LEAF_FRAME_POINTER) | |
f6f58ba3 | 143 | |
3b3c6a3f MM |
144 | /* Debug GO_IF_LEGITIMATE_ADDRESS */ |
145 | #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR) | |
146 | ||
b08de47e MM |
147 | /* Debug FUNCTION_ARG macros */ |
148 | #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG) | |
149 | ||
f7746310 SC |
150 | #define TARGET_386 (ix86_cpu == PROCESSOR_I386) |
151 | #define TARGET_486 (ix86_cpu == PROCESSOR_I486) | |
152 | #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM) | |
3a0433fd | 153 | #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO) |
a269a03c | 154 | #define TARGET_K6 (ix86_cpu == PROCESSOR_K6) |
309ada50 | 155 | #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON) |
a269a03c JC |
156 | |
157 | #define CPUMASK (1 << ix86_cpu) | |
158 | extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; | |
159 | extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; | |
160 | extern const int x86_unroll_strlen, x86_use_q_reg, x86_use_any_reg; | |
e075ae69 RH |
161 | extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; |
162 | extern const int x86_use_loop, x86_use_fiop, x86_use_mov0; | |
163 | extern const int x86_use_cltd, x86_read_modify_write; | |
164 | extern const int x86_read_modify, x86_split_long_moves; | |
f90800f8 | 165 | extern const int x86_promote_QImode, x86_single_stringop; |
d9f32422 JH |
166 | extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; |
167 | extern const int x86_promote_hi_regs; | |
a269a03c JC |
168 | |
169 | #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK) | |
170 | #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK) | |
171 | #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK) | |
172 | #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK) | |
173 | #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK) | |
174 | #define TARGET_USE_Q_REG (x86_use_q_reg & CPUMASK) | |
175 | #define TARGET_USE_ANY_REG (x86_use_any_reg & CPUMASK) | |
176 | #define TARGET_CMOVE (x86_cmove & (1 << ix86_arch)) | |
177 | #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK) | |
178 | #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK) | |
e075ae69 RH |
179 | #define TARGET_USE_SAHF (x86_use_sahf & CPUMASK) |
180 | #define TARGET_MOVX (x86_movx & CPUMASK) | |
181 | #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK) | |
182 | #define TARGET_USE_LOOP (x86_use_loop & CPUMASK) | |
183 | #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK) | |
184 | #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK) | |
185 | #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK) | |
186 | #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK) | |
187 | #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK) | |
188 | #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK) | |
e9e80858 | 189 | #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK) |
f90800f8 | 190 | #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK) |
d9f32422 JH |
191 | #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK) |
192 | #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK) | |
193 | #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK) | |
194 | #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK) | |
a269a03c | 195 | |
8c9be447 | 196 | #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE) |
3b3c6a3f | 197 | |
79f05c19 JH |
198 | #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS)) |
199 | #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS) | |
200 | ||
e075ae69 RH |
201 | #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0) |
202 | ||
203 | #define TARGET_SWITCHES \ | |
204 | { { "80387", MASK_80387, "Use hardware fp" }, \ | |
205 | { "no-80387", -MASK_80387, "Do not use hardware fp" }, \ | |
206 | { "hard-float", MASK_80387, "Use hardware fp" }, \ | |
207 | { "soft-float", -MASK_80387, "Do not use hardware fp" }, \ | |
208 | { "no-soft-float", MASK_80387, "Use hardware fp" }, \ | |
209 | { "386", 0, "Same as -mcpu=i386" }, \ | |
210 | { "486", 0, "Same as -mcpu=i486" }, \ | |
211 | { "pentium", 0, "Same as -mcpu=pentium" }, \ | |
212 | { "pentiumpro", 0, "Same as -mcpu=pentiumpro" }, \ | |
213 | { "rtd", MASK_RTD, "Alternate calling convention" }, \ | |
214 | { "no-rtd", -MASK_RTD, "Use normal calling convention" }, \ | |
215 | { "align-double", MASK_ALIGN_DOUBLE, \ | |
216 | "Align some doubles on dword boundary" }, \ | |
217 | { "no-align-double", -MASK_ALIGN_DOUBLE, \ | |
218 | "Align doubles on word boundary" }, \ | |
219 | { "svr3-shlib", MASK_SVR3_SHLIB, \ | |
220 | "Uninitialized locals in .bss" }, \ | |
221 | { "no-svr3-shlib", -MASK_SVR3_SHLIB, \ | |
222 | "Uninitialized locals in .data" }, \ | |
223 | { "ieee-fp", MASK_IEEE_FP, \ | |
224 | "Use IEEE math for fp comparisons" }, \ | |
225 | { "no-ieee-fp", -MASK_IEEE_FP, \ | |
226 | "Do not use IEEE math for fp comparisons" }, \ | |
227 | { "fp-ret-in-387", MASK_FLOAT_RETURNS, \ | |
228 | "Return values of functions in FPU registers" }, \ | |
229 | { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \ | |
230 | "Do not return values of functions in FPU registers"}, \ | |
231 | { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \ | |
232 | "Do not generate sin, cos, sqrt for FPU" }, \ | |
233 | { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \ | |
234 | "Generate sin, cos, sqrt for FPU"}, \ | |
235 | { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \ | |
236 | "Omit the frame pointer in leaf functions" }, \ | |
237 | { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \ | |
238 | { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \ | |
239 | { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \ | |
240 | { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \ | |
241 | { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \ | |
242 | { "stack-arg-probe", MASK_STACK_PROBE, "Enable stack probing" }, \ | |
243 | { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \ | |
244 | { "windows", 0, 0 /* undocumented */ }, \ | |
245 | { "dll", 0, 0 /* undocumented */ }, \ | |
246 | { "intel-syntax", MASK_INTEL_SYNTAX, \ | |
247 | "Emit Intel syntax assembler opcodes" }, \ | |
248 | { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \ | |
79f05c19 JH |
249 | { "align-stringops", -MASK_NO_ALIGN_STROPS, \ |
250 | "Align destination of the string operations" }, \ | |
251 | { "no-align-stringops", MASK_NO_ALIGN_STROPS, \ | |
252 | "Do not align destination of the string operations" }, \ | |
4be2e5d9 | 253 | { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \ |
79f05c19 JH |
254 | "Inline all known string operations" }, \ |
255 | { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \ | |
256 | "Do not inline all known string operations" }, \ | |
e075ae69 RH |
257 | SUBTARGET_SWITCHES \ |
258 | { "", TARGET_DEFAULT, 0 }} | |
241e1a89 | 259 | |
d4ba09c0 SC |
260 | /* Which processor to schedule for. The cpu attribute defines a list that |
261 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
262 | ||
241e1a89 | 263 | enum processor_type |
e075ae69 RH |
264 | { |
265 | PROCESSOR_I386, /* 80386 */ | |
241e1a89 SC |
266 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
267 | PROCESSOR_PENTIUM, | |
a269a03c | 268 | PROCESSOR_PENTIUMPRO, |
e075ae69 | 269 | PROCESSOR_K6, |
309ada50 | 270 | PROCESSOR_ATHLON, |
e075ae69 RH |
271 | PROCESSOR_max |
272 | }; | |
241e1a89 | 273 | |
e42ea7f9 | 274 | extern enum processor_type ix86_cpu; |
241e1a89 | 275 | |
bcd86433 | 276 | extern int ix86_arch; |
241e1a89 | 277 | |
f5316dfe MM |
278 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
279 | command options that have values. Its definition is an | |
280 | initializer with a subgrouping for each command option. | |
281 | ||
282 | Each subgrouping contains a string constant, that defines the | |
283 | fixed part of the option name, and the address of a variable. The | |
284 | variable, type `char *', is set to the variable part of the given | |
285 | option if the fixed part matches. The actual option name is made | |
286 | by appending `-m' to the specified name. */ | |
e075ae69 RH |
287 | #define TARGET_OPTIONS \ |
288 | { { "cpu=", &ix86_cpu_string, \ | |
289 | "Schedule code for given CPU"}, \ | |
290 | { "arch=", &ix86_arch_string, \ | |
291 | "Generate code for given CPU"}, \ | |
292 | { "reg-alloc=", &ix86_reg_alloc_order, \ | |
293 | "Control allocation order of integer registers" }, \ | |
294 | { "regparm=", &ix86_regparm_string, \ | |
295 | "Number of registers used to pass integer arguments" }, \ | |
296 | { "align-loops=", &ix86_align_loops_string, \ | |
297 | "Loop code aligned to this power of 2" }, \ | |
298 | { "align-jumps=", &ix86_align_jumps_string, \ | |
299 | "Jump targets are aligned to this power of 2" }, \ | |
300 | { "align-functions=", &ix86_align_funcs_string, \ | |
301 | "Function starts are aligned to this power of 2" }, \ | |
302 | { "preferred-stack-boundary=", \ | |
303 | &ix86_preferred_stack_boundary_string, \ | |
304 | "Attempt to keep stack aligned to this power of 2" }, \ | |
305 | { "branch-cost=", &ix86_branch_cost_string, \ | |
306 | "Branches are this expensive (1-5, arbitrary units)" }, \ | |
307 | SUBTARGET_OPTIONS \ | |
b08de47e | 308 | } |
f5316dfe MM |
309 | |
310 | /* Sometimes certain combinations of command options do not make | |
311 | sense on a particular target machine. You can define a macro | |
312 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
313 | defined, is executed once just after all the command options have | |
314 | been parsed. | |
315 | ||
316 | Don't use this macro to turn on various extra optimizations for | |
317 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
318 | ||
319 | #define OVERRIDE_OPTIONS override_options () | |
320 | ||
321 | /* These are meant to be redefined in the host dependent files */ | |
95393dfd | 322 | #define SUBTARGET_SWITCHES |
f5316dfe | 323 | #define SUBTARGET_OPTIONS |
95393dfd | 324 | |
d4ba09c0 | 325 | /* Define this to change the optimizations performed by default. */ |
c6aded7c | 326 | #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) |
d4ba09c0 | 327 | |
241e1a89 SC |
328 | /* Specs for the compiler proper */ |
329 | ||
628714d8 RK |
330 | #ifndef CC1_CPU_SPEC |
331 | #define CC1_CPU_SPEC "\ | |
241e1a89 | 332 | %{!mcpu*: \ |
5a6ee819 RH |
333 | %{m386:-mcpu=i386} \ |
334 | %{m486:-mcpu=i486} \ | |
241e1a89 SC |
335 | %{mpentium:-mcpu=pentium} \ |
336 | %{mpentiumpro:-mcpu=pentiumpro}}" | |
337 | #endif | |
c98f8742 | 338 | \f |
84b77fba | 339 | #ifndef CPP_CPU_DEFAULT_SPEC |
d5c65c96 | 340 | #if TARGET_CPU_DEFAULT == 1 |
5a6ee819 RH |
341 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__" |
342 | #endif | |
da594c94 | 343 | #if TARGET_CPU_DEFAULT == 2 |
5a6ee819 RH |
344 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium__" |
345 | #endif | |
da594c94 | 346 | #if TARGET_CPU_DEFAULT == 3 |
5a6ee819 | 347 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentiumpro__" |
da594c94 | 348 | #endif |
5a6ee819 RH |
349 | #if TARGET_CPU_DEFAULT == 4 |
350 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__" | |
da594c94 | 351 | #endif |
309ada50 JH |
352 | #if TARGET_CPU_DEFAULT == 5 |
353 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__" | |
354 | #endif | |
5a6ee819 RH |
355 | #ifndef CPP_CPU_DEFAULT_SPEC |
356 | #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__" | |
84b77fba JW |
357 | #endif |
358 | #endif /* CPP_CPU_DEFAULT_SPEC */ | |
33c1d53a | 359 | |
84b77fba | 360 | #ifndef CPP_CPU_SPEC |
bcd86433 | 361 | #define CPP_CPU_SPEC "\ |
5d46457e | 362 | -Acpu(i386) -Amachine(i386) \ |
1228a9bd | 363 | %{!ansi:-Di386} -D__i386 -D__i386__ \ |
5a6ee819 RH |
364 | %{march=i386:%{!mcpu*:-D__tune_i386__ }}\ |
365 | %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\ | |
366 | %{march=pentium|march=i586:-D__pentium -D__pentium__ \ | |
367 | %{!mcpu*:-D__tune_pentium__ }}\ | |
368 | %{march=pentiumpro|march=i686:-D__pentiumpro -D__pentiumpro__ \ | |
369 | %{!mcpu*:-D__tune_pentiumpro__ }}\ | |
370 | %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\ | |
309ada50 | 371 | %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\ |
5a6ee819 RH |
372 | %{m386|mcpu=i386:-D__tune_i386__ }\ |
373 | %{m486|mcpu=i486:-D__tune_i486__ }\ | |
374 | %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_pentium__ }\ | |
375 | %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_pentiumpro__ }\ | |
376 | %{mcpu=k6:-D__tune_k6__ }\ | |
309ada50 | 377 | %{mcpu=athlon:-D__tune_athlon__ }\ |
5a6ee819 | 378 | %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}" |
84b77fba | 379 | #endif |
bcd86433 | 380 | |
628714d8 | 381 | #ifndef CC1_SPEC |
8015b78d | 382 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
383 | #endif |
384 | ||
385 | /* This macro defines names of additional specifications to put in the | |
386 | specs that can be used in various specifications like CC1_SPEC. Its | |
387 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
388 | |
389 | Each subgrouping contains a string constant, that defines the | |
390 | specification name, and a string constant that used by the GNU CC driver | |
391 | program. | |
392 | ||
393 | Do not define this macro if it does not need to do anything. */ | |
394 | ||
395 | #ifndef SUBTARGET_EXTRA_SPECS | |
396 | #define SUBTARGET_EXTRA_SPECS | |
397 | #endif | |
398 | ||
399 | #define EXTRA_SPECS \ | |
84b77fba | 400 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ |
bcd86433 | 401 | { "cpp_cpu", CPP_CPU_SPEC }, \ |
628714d8 | 402 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
403 | SUBTARGET_EXTRA_SPECS |
404 | \f | |
c98f8742 JVA |
405 | /* target machine storage layout */ |
406 | ||
0038aea6 JVA |
407 | /* Define for XFmode extended real floating point support. |
408 | This will automatically cause REAL_ARITHMETIC to be defined. */ | |
409 | #define LONG_DOUBLE_TYPE_SIZE 96 | |
410 | ||
411 | /* Define if you don't want extended real, but do want to use the | |
412 | software floating point emulator for REAL_ARITHMETIC and | |
413 | decimal <-> binary conversion. */ | |
414 | /* #define REAL_ARITHMETIC */ | |
415 | ||
c98f8742 JVA |
416 | /* Define this if most significant byte of a word is the lowest numbered. */ |
417 | /* That is true on the 80386. */ | |
418 | ||
419 | #define BITS_BIG_ENDIAN 0 | |
420 | ||
421 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
422 | /* That is not true on the 80386. */ | |
423 | #define BYTES_BIG_ENDIAN 0 | |
424 | ||
425 | /* Define this if most significant word of a multiword number is the lowest | |
426 | numbered. */ | |
427 | /* Not true for 80386 */ | |
428 | #define WORDS_BIG_ENDIAN 0 | |
429 | ||
b4ac57ab | 430 | /* number of bits in an addressable storage unit */ |
c98f8742 JVA |
431 | #define BITS_PER_UNIT 8 |
432 | ||
433 | /* Width in bits of a "word", which is the contents of a machine register. | |
434 | Note that this is not necessarily the width of data type `int'; | |
435 | if using 16-bit ints on a 80386, this would still be 32. | |
436 | But on a machine with 16-bit registers, this would be 16. */ | |
437 | #define BITS_PER_WORD 32 | |
438 | ||
439 | /* Width of a word, in units (bytes). */ | |
440 | #define UNITS_PER_WORD 4 | |
441 | ||
442 | /* Width in bits of a pointer. | |
443 | See also the macro `Pmode' defined below. */ | |
444 | #define POINTER_SIZE 32 | |
445 | ||
446 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
447 | #define PARM_BOUNDARY 32 | |
448 | ||
e075ae69 | 449 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
d5c65c96 | 450 | #define STACK_BOUNDARY 32 |
c98f8742 | 451 | |
3af4bd89 JH |
452 | /* Boundary (in *bits*) on which the stack pointer preferrs to be |
453 | aligned; the compiler cannot rely on having this alignment. */ | |
e075ae69 | 454 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 455 | |
e075ae69 RH |
456 | /* Allocation boundary for the code of a function. */ |
457 | #define FUNCTION_BOUNDARY \ | |
458 | (1 << ((ix86_align_funcs >= 0 ? ix86_align_funcs : -ix86_align_funcs) + 3)) | |
c98f8742 JVA |
459 | |
460 | /* Alignment of field after `int : 0' in a structure. */ | |
461 | ||
462 | #define EMPTY_FIELD_BOUNDARY 32 | |
463 | ||
464 | /* Minimum size in bits of the largest boundary to which any | |
465 | and all fundamental data types supported by the hardware | |
466 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 JH |
467 | rounder than this. |
468 | ||
469 | Pentium+ preferrs DFmode values to be alignmed to 64 bit boundary | |
470 | and Pentium Pro XFmode values at 128 bit boundaries. */ | |
471 | ||
472 | #define BIGGEST_ALIGNMENT 128 | |
473 | ||
474 | /* The published ABIs say that doubles should be aligned on word | |
6fc605d8 ZW |
475 | boundaries, so lower the aligment for structure fields unless |
476 | -malign-double is set. */ | |
477 | /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be | |
478 | constant. Use the smaller value in that context. */ | |
479 | #ifndef IN_TARGET_LIBS | |
17f24ff0 | 480 | #define BIGGEST_FIELD_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) |
6fc605d8 ZW |
481 | #else |
482 | #define BIGGEST_FIELD_ALIGNMENT 32 | |
483 | #endif | |
c98f8742 | 484 | |
e5e8a8bf JW |
485 | /* If defined, a C expression to compute the alignment given to a |
486 | constant that is being placed in memory. CONSTANT is the constant | |
487 | and ALIGN is the alignment that the object would ordinarily have. | |
488 | The value of this macro is used instead of that alignment to align | |
489 | the object. | |
490 | ||
491 | If this macro is not defined, then ALIGN is used. | |
492 | ||
493 | The typical use of this macro is to increase alignment for string | |
494 | constants to be word aligned so that `strcpy' calls that copy | |
495 | constants can be done inline. */ | |
496 | ||
497 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
498 | (TREE_CODE (EXP) == REAL_CST \ | |
499 | ? ((TYPE_MODE (TREE_TYPE (EXP)) == DFmode && (ALIGN) < 64) \ | |
500 | ? 64 \ | |
501 | : (TYPE_MODE (TREE_TYPE (EXP)) == XFmode && (ALIGN) < 128) \ | |
502 | ? 128 \ | |
503 | : (ALIGN)) \ | |
504 | : TREE_CODE (EXP) == STRING_CST \ | |
505 | ? ((TREE_STRING_LENGTH (EXP) >= 31 && (ALIGN) < 256) \ | |
506 | ? 256 \ | |
507 | : (ALIGN)) \ | |
508 | : (ALIGN)) | |
d4ba09c0 | 509 | |
8a022443 JW |
510 | /* If defined, a C expression to compute the alignment for a static |
511 | variable. TYPE is the data type, and ALIGN is the alignment that | |
512 | the object would ordinarily have. The value of this macro is used | |
513 | instead of that alignment to align the object. | |
514 | ||
515 | If this macro is not defined, then ALIGN is used. | |
516 | ||
517 | One use of this macro is to increase alignment of medium-size | |
518 | data to make it all fit in fewer cache lines. Another is to | |
519 | cause character arrays to be word-aligned so that `strcpy' calls | |
520 | that copy constants to character arrays can be done inline. */ | |
521 | ||
522 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
523 | ((AGGREGATE_TYPE_P (TYPE) \ | |
524 | && TYPE_SIZE (TYPE) \ | |
525 | && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \ | |
526 | && (TREE_INT_CST_LOW (TYPE_SIZE (TYPE)) >= 256 \ | |
527 | || TREE_INT_CST_HIGH (TYPE_SIZE (TYPE))) && (ALIGN) < 256) \ | |
528 | ? 256 \ | |
529 | : TREE_CODE (TYPE) == ARRAY_TYPE \ | |
530 | ? ((TYPE_MODE (TREE_TYPE (TYPE)) == DFmode && (ALIGN) < 64) \ | |
531 | ? 64 \ | |
532 | : (TYPE_MODE (TREE_TYPE (TYPE)) == XFmode && (ALIGN) < 128) \ | |
533 | ? 128 \ | |
534 | : (ALIGN)) \ | |
535 | : TREE_CODE (TYPE) == COMPLEX_TYPE \ | |
536 | ? ((TYPE_MODE (TYPE) == DCmode && (ALIGN) < 64) \ | |
537 | ? 64 \ | |
538 | : (TYPE_MODE (TYPE) == XCmode && (ALIGN) < 128) \ | |
539 | ? 128 \ | |
540 | : (ALIGN)) \ | |
541 | : ((TREE_CODE (TYPE) == RECORD_TYPE \ | |
542 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
543 | || TREE_CODE (TYPE) == QUAL_UNION_TYPE) \ | |
544 | && TYPE_FIELDS (TYPE)) \ | |
545 | ? ((DECL_MODE (TYPE_FIELDS (TYPE)) == DFmode && (ALIGN) < 64) \ | |
546 | ? 64 \ | |
547 | : (DECL_MODE (TYPE_FIELDS (TYPE)) == XFmode && (ALIGN) < 128) \ | |
548 | ? 128 \ | |
549 | : (ALIGN)) \ | |
550 | : TREE_CODE (TYPE) == REAL_TYPE \ | |
551 | ? ((TYPE_MODE (TYPE) == DFmode && (ALIGN) < 64) \ | |
552 | ? 64 \ | |
553 | : (TYPE_MODE (TYPE) == XFmode && (ALIGN) < 128) \ | |
d16790f2 JW |
554 | ? 128 \ |
555 | : (ALIGN)) \ | |
556 | : (ALIGN)) | |
557 | ||
558 | /* If defined, a C expression to compute the alignment for a local | |
559 | variable. TYPE is the data type, and ALIGN is the alignment that | |
560 | the object would ordinarily have. The value of this macro is used | |
561 | instead of that alignment to align the object. | |
562 | ||
563 | If this macro is not defined, then ALIGN is used. | |
564 | ||
565 | One use of this macro is to increase alignment of medium-size | |
566 | data to make it all fit in fewer cache lines. */ | |
567 | ||
568 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
569 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
570 | ? ((TYPE_MODE (TREE_TYPE (TYPE)) == DFmode && (ALIGN) < 64) \ | |
571 | ? 64 \ | |
572 | : (TYPE_MODE (TREE_TYPE (TYPE)) == XFmode && (ALIGN) < 128) \ | |
573 | ? 128 \ | |
574 | : (ALIGN)) \ | |
575 | : TREE_CODE (TYPE) == COMPLEX_TYPE \ | |
576 | ? ((TYPE_MODE (TYPE) == DCmode && (ALIGN) < 64) \ | |
577 | ? 64 \ | |
578 | : (TYPE_MODE (TYPE) == XCmode && (ALIGN) < 128) \ | |
579 | ? 128 \ | |
580 | : (ALIGN)) \ | |
581 | : ((TREE_CODE (TYPE) == RECORD_TYPE \ | |
582 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
583 | || TREE_CODE (TYPE) == QUAL_UNION_TYPE) \ | |
584 | && TYPE_FIELDS (TYPE)) \ | |
585 | ? ((DECL_MODE (TYPE_FIELDS (TYPE)) == DFmode && (ALIGN) < 64) \ | |
586 | ? 64 \ | |
587 | : (DECL_MODE (TYPE_FIELDS (TYPE)) == XFmode && (ALIGN) < 128) \ | |
588 | ? 128 \ | |
589 | : (ALIGN)) \ | |
590 | : TREE_CODE (TYPE) == REAL_TYPE \ | |
591 | ? ((TYPE_MODE (TYPE) == DFmode && (ALIGN) < 64) \ | |
592 | ? 64 \ | |
593 | : (TYPE_MODE (TYPE) == XFmode && (ALIGN) < 128) \ | |
8a022443 JW |
594 | ? 128 \ |
595 | : (ALIGN)) \ | |
596 | : (ALIGN)) | |
597 | ||
b4ac57ab | 598 | /* Set this non-zero if move instructions will actually fail to work |
c98f8742 | 599 | when given unaligned data. */ |
b4ac57ab | 600 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
601 | |
602 | /* If bit field type is int, don't let it cross an int, | |
603 | and give entire struct the alignment of an int. */ | |
604 | /* Required on the 386 since it doesn't have bitfield insns. */ | |
605 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
606 | ||
607 | /* Align loop starts for optimal branching. */ | |
e075ae69 RH |
608 | #define LOOP_ALIGN(LABEL) \ |
609 | (ix86_align_loops < 0 ? -ix86_align_loops : ix86_align_loops) | |
610 | #define LOOP_ALIGN_MAX_SKIP \ | |
611 | (ix86_align_loops < -3 ? (1<<(-ix86_align_loops-1))-1 : 0) | |
612 | ||
613 | /* This is how to align an instruction for optimal branching. */ | |
614 | #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ | |
615 | (ix86_align_jumps < 0 ? -ix86_align_jumps : ix86_align_jumps) | |
616 | #define LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP \ | |
617 | (ix86_align_jumps < -3 ? (1<<(-ix86_align_jumps-1))-1 : 0) | |
c98f8742 JVA |
618 | \f |
619 | /* Standard register usage. */ | |
620 | ||
621 | /* This processor has special stack-like registers. See reg-stack.c | |
622 | for details. */ | |
623 | ||
624 | #define STACK_REGS | |
d4ba09c0 | 625 | #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode || mode==XFmode) |
c98f8742 JVA |
626 | |
627 | /* Number of actual hardware registers. | |
628 | The hardware registers are assigned numbers for the compiler | |
629 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
630 | All registers that the compiler knows about must be given numbers, | |
631 | even those that are not normally considered general registers. | |
632 | ||
633 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
634 | We number the floating point registers 8-15. | |
635 | Note that registers 0-7 can be accessed as a short or int, | |
636 | while only 0-3 may be used with byte `mov' instructions. | |
637 | ||
638 | Reg 16 does not correspond to any hardware register, but instead | |
639 | appears in the RTL as an argument pointer prior to reload, and is | |
640 | eliminated during reloading in favor of either the stack or frame | |
641 | pointer. */ | |
642 | ||
564d80f4 | 643 | #define FIRST_PSEUDO_REGISTER 21 |
c98f8742 | 644 | |
3073d01c ML |
645 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
646 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
647 | ||
648 | #define DWARF_FRAME_REGISTERS 17 | |
649 | ||
c98f8742 JVA |
650 | /* 1 for registers that have pervasive standard uses |
651 | and are not available for the register allocator. | |
652 | On the 80386, the stack pointer is such, as is the arg pointer. */ | |
653 | #define FIXED_REGISTERS \ | |
7c7ef435 | 654 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr, dir*/ \ |
564d80f4 JH |
655 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \ |
656 | /*frame */ \ | |
657 | 1} | |
c98f8742 JVA |
658 | |
659 | /* 1 for registers not available across function calls. | |
660 | These must include the FIXED_REGISTERS and also any | |
661 | registers that can be used without being saved. | |
662 | The latter must include the registers where values are returned | |
663 | and the register where structure-value addresses are passed. | |
664 | Aside from that, you can include as many other registers as you like. */ | |
665 | ||
666 | #define CALL_USED_REGISTERS \ | |
7c7ef435 | 667 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,flags,fpsr, dir*/ \ |
564d80f4 JH |
668 | { 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
669 | /*frame */ \ | |
670 | 1} | |
c98f8742 | 671 | |
3b3c6a3f MM |
672 | /* Order in which to allocate registers. Each register must be |
673 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
674 | late and fixed registers last. Note that, in general, we prefer | |
675 | registers listed in CALL_USED_REGISTERS, keeping the others | |
676 | available for storage of persistent values. | |
677 | ||
678 | Three different versions of REG_ALLOC_ORDER have been tried: | |
679 | ||
680 | If the order is edx, ecx, eax, ... it produces a slightly faster compiler, | |
681 | but slower code on simple functions returning values in eax. | |
682 | ||
683 | If the order is eax, ecx, edx, ... it causes reload to abort when compiling | |
684 | perl 4.036 due to not being able to create a DImode register (to hold a 2 | |
685 | word union). | |
686 | ||
687 | If the order is eax, edx, ecx, ... it produces better code for simple | |
688 | functions, and a slightly slower compiler. Users complained about the code | |
689 | generated by allocating edx first, so restore the 'natural' order of things. */ | |
690 | ||
184ff798 | 691 | #define REG_ALLOC_ORDER \ |
7c7ef435 | 692 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg,cc,fpsr, dir*/ \ |
564d80f4 JH |
693 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,17, 18, 19, \ |
694 | /*frame */ \ | |
695 | 20} | |
f5316dfe MM |
696 | |
697 | /* A C statement (sans semicolon) to choose the order in which to | |
698 | allocate hard registers for pseudo-registers local to a basic | |
699 | block. | |
700 | ||
701 | Store the desired register order in the array `reg_alloc_order'. | |
702 | Element 0 should be the register to allocate first; element 1, the | |
703 | next register; and so on. | |
704 | ||
705 | The macro body should not assume anything about the contents of | |
706 | `reg_alloc_order' before execution of the macro. | |
707 | ||
708 | On most machines, it is not necessary to define this macro. */ | |
709 | ||
710 | #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () | |
184ff798 | 711 | |
c98f8742 JVA |
712 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
713 | #define CONDITIONAL_REGISTER_USAGE \ | |
714 | { \ | |
715 | if (flag_pic) \ | |
716 | { \ | |
717 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
718 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
719 | } \ | |
8c2bf92a JVA |
720 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ |
721 | { \ | |
722 | int i; \ | |
723 | HARD_REG_SET x; \ | |
724 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
725 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ | |
726 | if (TEST_HARD_REG_BIT (x, i)) \ | |
727 | fixed_regs[i] = call_used_regs[i] = 1; \ | |
728 | } \ | |
c98f8742 JVA |
729 | } |
730 | ||
731 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
732 | to hold something of mode MODE. | |
733 | This is ordinarily the length in words of a value of mode MODE | |
734 | but can be less for certain modes in special long registers. | |
735 | ||
736 | Actually there are no two word move instructions for consecutive | |
737 | registers. And only registers 0-3 may have mov byte instructions | |
738 | applied to them. | |
739 | */ | |
740 | ||
741 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
742 | (FP_REGNO_P (REGNO) ? 1 \ | |
743 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
744 | ||
e075ae69 | 745 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 746 | |
e075ae69 RH |
747 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
748 | /* Flags and only flags can only hold CCmode values. */ \ | |
749 | (CC_REGNO_P (REGNO) \ | |
750 | ? GET_MODE_CLASS (MODE) == MODE_CC \ | |
751 | : GET_MODE_CLASS (MODE) == MODE_CC ? 0 \ | |
752 | /* FP regs can only hold floating point; make it clear they \ | |
753 | cannot hold TFmode floats. */ \ | |
0038aea6 | 754 | : FP_REGNO_P (REGNO) \ |
e075ae69 RH |
755 | ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
756 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
62acf5fd | 757 | && GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\ |
e075ae69 RH |
758 | : (REGNO) < 4 ? 1 \ |
759 | /* Other regs cannot do byte accesses. */ \ | |
760 | : (MODE) != QImode ? 1 \ | |
7c6b971d JH |
761 | : reload_in_progress || reload_completed \ |
762 | || !TARGET_PARTIAL_REG_STALL) | |
c98f8742 JVA |
763 | |
764 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
765 | when one has mode MODE1 and one has mode MODE2. | |
766 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
767 | for any hard reg, then this must be 0 for correct output. */ | |
768 | ||
95912252 RH |
769 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
770 | ((MODE1) == (MODE2) \ | |
63be02db JM |
771 | || ((MODE1) == SImode && (MODE2) == HImode) \ |
772 | || ((MODE1) == HImode && (MODE2) == SImode)) | |
c98f8742 | 773 | |
e075ae69 RH |
774 | /* Specify the modes required to caller save a given hard regno. |
775 | We do this on i386 to prevent flags from being saved at all. */ | |
776 | ||
777 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS) \ | |
778 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
779 | : choose_hard_reg_mode ((REGNO), (NREGS))) | |
780 | ||
c98f8742 JVA |
781 | /* Specify the registers used for certain standard purposes. |
782 | The values of these macros are register numbers. */ | |
783 | ||
784 | /* on the 386 the pc register is %eip, and is not usable as a general | |
785 | register. The ordinary mov instructions won't work */ | |
786 | /* #define PC_REGNUM */ | |
787 | ||
788 | /* Register to use for pushing function arguments. */ | |
789 | #define STACK_POINTER_REGNUM 7 | |
790 | ||
791 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
792 | #define HARD_FRAME_POINTER_REGNUM 6 |
793 | ||
794 | /* Base register for access to local variables of the function. */ | |
795 | #define FRAME_POINTER_REGNUM 20 | |
c98f8742 JVA |
796 | |
797 | /* First floating point reg */ | |
798 | #define FIRST_FLOAT_REG 8 | |
799 | ||
800 | /* First & last stack-like regs */ | |
801 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
802 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
803 | ||
e075ae69 RH |
804 | #define FLAGS_REG 17 |
805 | #define FPSR_REG 18 | |
7c7ef435 | 806 | #define DIRFLAG_REG 19 |
e075ae69 | 807 | |
c98f8742 JVA |
808 | /* Value should be nonzero if functions must have frame pointers. |
809 | Zero means the frame pointer need not be set up (and parms | |
810 | may be accessed via the stack pointer) in functions that seem suitable. | |
811 | This is computed in `reload', in reload1.c. */ | |
2f2fa5b1 | 812 | #define FRAME_POINTER_REQUIRED (TARGET_OMIT_LEAF_FRAME_POINTER && !leaf_function_p ()) |
c98f8742 JVA |
813 | |
814 | /* Base register for access to arguments of the function. */ | |
815 | #define ARG_POINTER_REGNUM 16 | |
816 | ||
817 | /* Register in which static-chain is passed to a function. */ | |
818 | #define STATIC_CHAIN_REGNUM 2 | |
819 | ||
820 | /* Register to hold the addressing base for position independent | |
821 | code access to data items. */ | |
822 | #define PIC_OFFSET_TABLE_REGNUM 3 | |
823 | ||
824 | /* Register in which address to store a structure value | |
825 | arrives in the function. On the 386, the prologue | |
826 | copies this from the stack to register %eax. */ | |
827 | #define STRUCT_VALUE_INCOMING 0 | |
828 | ||
829 | /* Place in which caller passes the structure value address. | |
830 | 0 means push the value on the stack like an argument. */ | |
831 | #define STRUCT_VALUE 0 | |
713225d4 MM |
832 | |
833 | /* A C expression which can inhibit the returning of certain function | |
834 | values in registers, based on the type of value. A nonzero value | |
835 | says to return the function value in memory, just as large | |
836 | structures are always returned. Here TYPE will be a C expression | |
837 | of type `tree', representing the data type of the value. | |
838 | ||
839 | Note that values of mode `BLKmode' must be explicitly handled by | |
840 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
841 | regardless of this macro. On most systems, it is possible to | |
842 | leave the macro undefined; this causes a default definition to be | |
843 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
844 | otherwise. | |
845 | ||
846 | Do not use this macro to indicate that structures and unions | |
847 | should always be returned in memory. You should instead use | |
848 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
849 | ||
850 | #define RETURN_IN_MEMORY(TYPE) \ | |
851 | ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12) | |
852 | ||
c98f8742 JVA |
853 | \f |
854 | /* Define the classes of registers for register constraints in the | |
855 | machine description. Also define ranges of constants. | |
856 | ||
857 | One of the classes must always be named ALL_REGS and include all hard regs. | |
858 | If there is more than one class, another class must be named NO_REGS | |
859 | and contain no registers. | |
860 | ||
861 | The name GENERAL_REGS must be the name of a class (or an alias for | |
862 | another name such as ALL_REGS). This is the class of registers | |
863 | that is allowed by "g" or "r" in a register constraint. | |
864 | Also, registers outside this class are allocated only when | |
865 | instructions express preferences for them. | |
866 | ||
867 | The classes must be numbered in nondecreasing order; that is, | |
868 | a larger-numbered class must never be contained completely | |
869 | in a smaller-numbered class. | |
870 | ||
871 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
872 | class that represents their union. |
873 | ||
874 | It might seem that class BREG is unnecessary, since no useful 386 | |
875 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
876 | and the "b" register constraint is useful in asms for syscalls. |
877 | ||
878 | The flags and fpsr registers are in no class. */ | |
c98f8742 JVA |
879 | |
880 | enum reg_class | |
881 | { | |
882 | NO_REGS, | |
e075ae69 | 883 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 884 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 885 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 886 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 JVA |
887 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
888 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ | |
889 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ | |
890 | FLOAT_REGS, | |
8fcaaa80 | 891 | FLOAT_INT_REGS, /* FLOAT_REGS and GENERAL_REGS. */ |
c98f8742 JVA |
892 | ALL_REGS, LIM_REG_CLASSES |
893 | }; | |
894 | ||
895 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
896 | ||
4cbb525c JVA |
897 | #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) |
898 | ||
7c6b971d JH |
899 | #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS)) |
900 | ||
c98f8742 JVA |
901 | /* Give names of register classes as strings for dump file. */ |
902 | ||
903 | #define REG_CLASS_NAMES \ | |
904 | { "NO_REGS", \ | |
ab408a86 | 905 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 906 | "SIREG", "DIREG", \ |
e075ae69 RH |
907 | "AD_REGS", \ |
908 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 JVA |
909 | "INDEX_REGS", \ |
910 | "GENERAL_REGS", \ | |
911 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
912 | "FLOAT_REGS", \ | |
8fcaaa80 | 913 | "FLOAT_INT_REGS", \ |
c98f8742 JVA |
914 | "ALL_REGS" } |
915 | ||
916 | /* Define which registers fit in which classes. | |
917 | This is an initializer for a vector of HARD_REG_SET | |
918 | of length N_REG_CLASSES. */ | |
919 | ||
e075ae69 | 920 | #define REG_CLASS_CONTENTS \ |
47f3558c | 921 | { {0}, \ |
e075ae69 RH |
922 | {0x1}, {0x2}, {0x4}, {0x8},/* AREG, DREG, CREG, BREG */ \ |
923 | {0x10}, {0x20}, /* SIREG, DIREG */ \ | |
47f3558c JL |
924 | {0x3}, /* AD_REGS */ \ |
925 | {0xf}, /* Q_REGS */ \ | |
564d80f4 | 926 | {0x1100f0}, /* NON_Q_REGS */ \ |
e075ae69 | 927 | {0x7f}, /* INDEX_REGS */ \ |
564d80f4 | 928 | {0x1100ff}, /* GENERAL_REGS */ \ |
47f3558c JL |
929 | {0x0100}, {0x0200}, /* FP_TOP_REG, FP_SECOND_REG */ \ |
930 | {0xff00}, /* FLOAT_REGS */ \ | |
564d80f4 JH |
931 | {0x11ffff}, /* FLOAT_INT_REGS */ \ |
932 | {0x17ffff} \ | |
e075ae69 | 933 | } |
c98f8742 JVA |
934 | |
935 | /* The same information, inverted: | |
936 | Return the class number of the smallest class containing | |
937 | reg number REGNO. This could be a conditional expression | |
938 | or could index an array. */ | |
939 | ||
c98f8742 JVA |
940 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
941 | ||
942 | /* When defined, the compiler allows registers explicitly used in the | |
943 | rtl to be used as spill registers but prevents the compiler from | |
944 | extending the lifetime of these registers. */ | |
945 | ||
2922fe9e | 946 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 JVA |
947 | |
948 | #define QI_REG_P(X) \ | |
949 | (REG_P (X) && REGNO (X) < 4) | |
950 | #define NON_QI_REG_P(X) \ | |
951 | (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) | |
952 | ||
953 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
954 | #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) | |
955 | ||
956 | #define STACK_REG_P(xop) (REG_P (xop) && \ | |
957 | REGNO (xop) >= FIRST_STACK_REG && \ | |
958 | REGNO (xop) <= LAST_STACK_REG) | |
959 | ||
960 | #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) | |
961 | ||
962 | #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) | |
963 | ||
e075ae69 RH |
964 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
965 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
966 | ||
c98f8742 JVA |
967 | /* The class value for index registers, and the one for base regs. */ |
968 | ||
969 | #define INDEX_REG_CLASS INDEX_REGS | |
970 | #define BASE_REG_CLASS GENERAL_REGS | |
971 | ||
972 | /* Get reg_class from a letter such as appears in the machine description. */ | |
973 | ||
974 | #define REG_CLASS_FROM_LETTER(C) \ | |
8c2bf92a JVA |
975 | ((C) == 'r' ? GENERAL_REGS : \ |
976 | (C) == 'q' ? Q_REGS : \ | |
977 | (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
978 | ? FLOAT_REGS \ | |
979 | : NO_REGS) : \ | |
980 | (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
981 | ? FP_TOP_REG \ | |
982 | : NO_REGS) : \ | |
983 | (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ | |
984 | ? FP_SECOND_REG \ | |
985 | : NO_REGS) : \ | |
986 | (C) == 'a' ? AREG : \ | |
987 | (C) == 'b' ? BREG : \ | |
988 | (C) == 'c' ? CREG : \ | |
989 | (C) == 'd' ? DREG : \ | |
4b71cd6e | 990 | (C) == 'A' ? AD_REGS : \ |
8c2bf92a | 991 | (C) == 'D' ? DIREG : \ |
c98f8742 JVA |
992 | (C) == 'S' ? SIREG : NO_REGS) |
993 | ||
994 | /* The letters I, J, K, L and M in a register constraint string | |
995 | can be used to stand for particular ranges of immediate operands. | |
996 | This macro defines what the ranges are. | |
997 | C is the letter, and VALUE is a constant value. | |
998 | Return 1 if VALUE is in the range specified by C. | |
999 | ||
1000 | I is for non-DImode shifts. | |
1001 | J is for DImode shifts. | |
e075ae69 RH |
1002 | K is for signed imm8 operands. |
1003 | L is for andsi as zero-extending move. | |
c98f8742 JVA |
1004 | M is for shifts that can be executed by the "lea" opcode. |
1005 | */ | |
1006 | ||
e075ae69 RH |
1007 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
1008 | ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \ | |
1009 | : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \ | |
1010 | : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \ | |
1011 | : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \ | |
1012 | : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \ | |
1013 | : 0) | |
c98f8742 JVA |
1014 | |
1015 | /* Similar, but for floating constants, and defining letters G and H. | |
b4ac57ab RS |
1016 | Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if |
1017 | TARGET_387 isn't set, because the stack register converter may need to | |
c47f5ea5 | 1018 | load 0.0 into the function value register. */ |
c98f8742 JVA |
1019 | |
1020 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
c47f5ea5 | 1021 | ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) |
c98f8742 JVA |
1022 | |
1023 | /* Place additional restrictions on the register class to use when it | |
4cbb525c JVA |
1024 | is necessary to be able to hold a value of mode MODE in a reload |
1025 | register for which class CLASS would ordinarily be used. */ | |
c98f8742 JVA |
1026 | |
1027 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
1028 | ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ | |
1029 | ? Q_REGS : (CLASS)) | |
1030 | ||
1031 | /* Given an rtx X being reloaded into a reg required to be | |
1032 | in class CLASS, return the class of reg to actually use. | |
1033 | In general this is just CLASS; but on some machines | |
1034 | in some cases it is preferable to use a more restrictive class. | |
1035 | On the 80386 series, we prevent floating constants from being | |
1036 | reloaded into floating registers (since no move-insn can do that) | |
1037 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1038 | ||
d398b3b1 | 1039 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1040 | QImode must go into class Q_REGS. |
d398b3b1 JVA |
1041 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
1042 | movdf to do mem-to-mem moves through integer regs. */ | |
c98f8742 | 1043 | |
b66a3ac1 RH |
1044 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
1045 | (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode \ | |
1046 | ? (standard_80387_constant_p (X) \ | |
d7a29404 JH |
1047 | ? CLASS \ |
1048 | : (reg_class_subset_p (CLASS, FLOAT_REGS) \ | |
1049 | ? NO_REGS \ | |
1050 | : reg_class_subset_p (CLASS, GENERAL_REGS) ? CLASS : GENERAL_REGS)) \ | |
85ff473e | 1051 | : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ |
85ff473e JVA |
1052 | : (CLASS)) |
1053 | ||
1054 | /* If we are copying between general and FP registers, we need a memory | |
1055 | location. */ | |
1056 | ||
1057 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ | |
e075ae69 RH |
1058 | (FLOAT_CLASS_P (CLASS1) != FLOAT_CLASS_P (CLASS2)) |
1059 | ||
1060 | /* QImode spills from non-QI registers need a scratch. This does not | |
1061 | happen often -- the only example so far requires an uninitialized | |
1062 | pseudo. */ | |
1063 | ||
1064 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ | |
1065 | ((CLASS) == GENERAL_REGS && (MODE) == QImode ? Q_REGS : NO_REGS) | |
c98f8742 JVA |
1066 | |
1067 | /* Return the maximum number of consecutive registers | |
1068 | needed to represent mode MODE in a register of class CLASS. */ | |
1069 | /* On the 80386, this is the size of MODE in words, | |
1070 | except in the FP regs, where a single reg is always enough. */ | |
1071 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
4cbb525c JVA |
1072 | (FLOAT_CLASS_P (CLASS) ? 1 : \ |
1073 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1074 | |
1075 | /* A C expression whose value is nonzero if pseudos that have been | |
1076 | assigned to registers of class CLASS would likely be spilled | |
1077 | because registers of CLASS are needed for spill registers. | |
1078 | ||
1079 | The default value of this macro returns 1 if CLASS has exactly one | |
1080 | register and zero otherwise. On most machines, this default | |
1081 | should be used. Only define this macro to some other expression | |
1082 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1083 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1084 | macro returns nonzero for those classes, those pseudos will only |
1085 | be allocated by `global.c', which knows how to reallocate the | |
1086 | pseudo to another register. If there would not be another | |
1087 | register available for reallocation, you should not change the | |
1088 | definition of this macro since the only effect of such a | |
1089 | definition would be to slow down register allocation. */ | |
1090 | ||
1091 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1092 | (((CLASS) == AREG) \ | |
1093 | || ((CLASS) == DREG) \ | |
1094 | || ((CLASS) == CREG) \ | |
1095 | || ((CLASS) == BREG) \ | |
1096 | || ((CLASS) == AD_REGS) \ | |
1097 | || ((CLASS) == SIREG) \ | |
1098 | || ((CLASS) == DIREG)) | |
1099 | ||
e075ae69 RH |
1100 | /* A C statement that adds to CLOBBERS any hard regs the port wishes |
1101 | to automatically clobber for all asms. | |
1102 | ||
1103 | We do this in the new i386 backend to maintain source compatibility | |
1104 | with the old cc0-based compiler. */ | |
1105 | ||
1106 | #define MD_ASM_CLOBBERS(CLOBBERS) \ | |
1107 | do { \ | |
1108 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\ | |
1109 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \ | |
7c7ef435 | 1110 | (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \ |
e075ae69 | 1111 | } while (0) |
c98f8742 JVA |
1112 | \f |
1113 | /* Stack layout; function entry, exit and calling. */ | |
1114 | ||
1115 | /* Define this if pushing a word on the stack | |
1116 | makes the stack pointer a smaller address. */ | |
1117 | #define STACK_GROWS_DOWNWARD | |
1118 | ||
1119 | /* Define this if the nominal address of the stack frame | |
1120 | is at the high-address end of the local variables; | |
1121 | that is, each additional local variable allocated | |
1122 | goes at a more negative offset in the frame. */ | |
1123 | #define FRAME_GROWS_DOWNWARD | |
1124 | ||
1125 | /* Offset within stack frame to start allocating local variables at. | |
1126 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1127 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1128 | of the first local allocated. */ | |
1129 | #define STARTING_FRAME_OFFSET 0 | |
1130 | ||
1131 | /* If we generate an insn to push BYTES bytes, | |
1132 | this says how many the stack pointer really advances by. | |
1133 | On 386 pushw decrements by exactly 2 no matter what the position was. | |
1134 | On the 386 there is no pushb; we use pushw instead, and this | |
1135 | has the effect of rounding up to 2. */ | |
1136 | ||
1137 | #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) | |
1138 | ||
1139 | /* Offset of first parameter from the argument pointer register value. */ | |
1140 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1141 | ||
1142 | /* Value is the number of bytes of arguments automatically | |
1143 | popped when returning from a subroutine call. | |
8b109b37 | 1144 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1145 | FUNTYPE is the data type of the function (as a tree), |
1146 | or for a library call it is an identifier node for the subroutine name. | |
1147 | SIZE is the number of bytes of arguments passed on the stack. | |
1148 | ||
1149 | On the 80386, the RTD insn may be used to pop them if the number | |
1150 | of args is fixed, but if the number is variable then the caller | |
1151 | must pop them all. RTD can't be used for library calls now | |
1152 | because the library is compiled with the Unix compiler. | |
1153 | Use of RTD is a selectable option, since it is incompatible with | |
1154 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1155 | the caller must always pop the args. |
1156 | ||
1157 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1158 | |
b08de47e | 1159 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ |
e075ae69 | 1160 | (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE)) |
c98f8742 | 1161 | |
8c2bf92a JVA |
1162 | /* Define how to find the value returned by a function. |
1163 | VALTYPE is the data type of the value (as a tree). | |
1164 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1165 | otherwise, FUNC is 0. */ | |
c98f8742 | 1166 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
f64cecad | 1167 | gen_rtx_REG (TYPE_MODE (VALTYPE), \ |
c5c76735 | 1168 | VALUE_REGNO (TYPE_MODE (VALTYPE))) |
c98f8742 JVA |
1169 | |
1170 | /* Define how to find the value returned by a library function | |
1171 | assuming the value has mode MODE. */ | |
1172 | ||
1173 | #define LIBCALL_VALUE(MODE) \ | |
f64cecad | 1174 | gen_rtx_REG (MODE, VALUE_REGNO (MODE)) |
c98f8742 | 1175 | |
e9125c09 TW |
1176 | /* Define the size of the result block used for communication between |
1177 | untyped_call and untyped_return. The block contains a DImode value | |
1178 | followed by the block used by fnsave and frstor. */ | |
1179 | ||
1180 | #define APPLY_RESULT_SIZE (8+108) | |
1181 | ||
b08de47e MM |
1182 | /* 1 if N is a possible register number for function argument passing. */ |
1183 | #define FUNCTION_ARG_REGNO_P(N) ((N) >= 0 && (N) < REGPARM_MAX) | |
c98f8742 JVA |
1184 | |
1185 | /* Define a data type for recording info about an argument list | |
1186 | during the scan of that argument list. This data type should | |
1187 | hold all necessary information about the function itself | |
1188 | and about the args processed so far, enough to enable macros | |
b08de47e | 1189 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1190 | |
e075ae69 | 1191 | typedef struct ix86_args { |
b08de47e MM |
1192 | int words; /* # words passed so far */ |
1193 | int nregs; /* # registers available for passing */ | |
1194 | int regno; /* next available register number */ | |
1195 | } CUMULATIVE_ARGS; | |
c98f8742 JVA |
1196 | |
1197 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1198 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1199 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1200 | |
2c7ee1a6 | 1201 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ |
b08de47e | 1202 | (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) |
c98f8742 JVA |
1203 | |
1204 | /* Update the data in CUM to advance over an argument | |
1205 | of mode MODE and data type TYPE. | |
1206 | (TYPE is null for libcalls where that information may not be available.) */ | |
1207 | ||
1208 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
b08de47e | 1209 | (function_arg_advance (&CUM, MODE, TYPE, NAMED)) |
c98f8742 JVA |
1210 | |
1211 | /* Define where to put the arguments to a function. | |
1212 | Value is zero to push the argument on the stack, | |
1213 | or a hard register in which to store the argument. | |
1214 | ||
1215 | MODE is the argument's machine mode. | |
1216 | TYPE is the data type of the argument (as a tree). | |
1217 | This is null for libcalls where that information may | |
1218 | not be available. | |
1219 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1220 | the preceding args and about the function being called. | |
1221 | NAMED is nonzero if this argument is a named parameter | |
1222 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1223 | ||
c98f8742 | 1224 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
b08de47e | 1225 | (function_arg (&CUM, MODE, TYPE, NAMED)) |
c98f8742 JVA |
1226 | |
1227 | /* For an arg passed partly in registers and partly in memory, | |
1228 | this is the number of registers used. | |
1229 | For args passed entirely in registers or entirely in memory, zero. */ | |
1230 | ||
e075ae69 | 1231 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
c98f8742 | 1232 | |
cbbf65e0 RH |
1233 | /* If PIC, we cannot optimize sibling calls to global functions |
1234 | because the PLT requires %ebx live. */ | |
1235 | #define FUNCTION_OK_FOR_SIBCALL(DECL) \ | |
1236 | (DECL && (! flag_pic || ! TREE_PUBLIC (DECL))) | |
1237 | ||
3a0433fd SC |
1238 | /* This macro is invoked just before the start of a function. |
1239 | It is used here to output code for -fpic that will load the | |
1240 | return address into %ebx. */ | |
1241 | ||
1242 | #undef ASM_OUTPUT_FUNCTION_PREFIX | |
1243 | #define ASM_OUTPUT_FUNCTION_PREFIX(FILE, FNNAME) \ | |
1244 | asm_output_function_prefix (FILE, FNNAME) | |
1245 | ||
c98f8742 JVA |
1246 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1247 | for profiling a function entry. */ | |
1248 | ||
1249 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
1250 | { \ | |
1251 | if (flag_pic) \ | |
1252 | { \ | |
e075ae69 | 1253 | fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \ |
c98f8742 | 1254 | LPREFIX, (LABELNO)); \ |
e075ae69 | 1255 | fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \ |
c98f8742 JVA |
1256 | } \ |
1257 | else \ | |
1258 | { \ | |
e075ae69 RH |
1259 | fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ |
1260 | fprintf (FILE, "\tcall\t_mcount\n"); \ | |
c98f8742 JVA |
1261 | } \ |
1262 | } | |
1263 | ||
1cf5eda8 | 1264 | |
6e753900 RK |
1265 | /* There are three profiling modes for basic blocks available. |
1266 | The modes are selected at compile time by using the options | |
1267 | -a or -ax of the gnu compiler. | |
1268 | The variable `profile_block_flag' will be set according to the | |
1269 | selected option. | |
1cf5eda8 | 1270 | |
6e753900 | 1271 | profile_block_flag == 0, no option used: |
1cf5eda8 | 1272 | |
6e753900 | 1273 | No profiling done. |
1cf5eda8 | 1274 | |
6e753900 RK |
1275 | profile_block_flag == 1, -a option used. |
1276 | ||
1277 | Count frequency of execution of every basic block. | |
1278 | ||
1279 | profile_block_flag == 2, -ax option used. | |
1280 | ||
1281 | Generate code to allow several different profiling modes at run time. | |
1282 | Available modes are: | |
1283 | Produce a trace of all basic blocks. | |
1284 | Count frequency of jump instructions executed. | |
1285 | In every mode it is possible to start profiling upon entering | |
1286 | certain functions and to disable profiling of some other functions. | |
1287 | ||
1288 | The result of basic-block profiling will be written to a file `bb.out'. | |
1289 | If the -ax option is used parameters for the profiling will be read | |
1290 | from file `bb.in'. | |
1291 | ||
1292 | */ | |
1293 | ||
1294 | /* The following macro shall output assembler code to FILE | |
e075ae69 | 1295 | to initialize basic-block profiling. */ |
1cf5eda8 MM |
1296 | |
1297 | #undef FUNCTION_BLOCK_PROFILER | |
e075ae69 RH |
1298 | #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \ |
1299 | ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL) | |
1cf5eda8 | 1300 | |
6e753900 | 1301 | /* The following macro shall output assembler code to FILE |
e075ae69 | 1302 | to increment a counter associated with basic block number BLOCKNO. */ |
6e753900 | 1303 | |
e075ae69 RH |
1304 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ |
1305 | ix86_output_block_profiler (FILE, BLOCKNO) | |
1cf5eda8 | 1306 | |
e075ae69 | 1307 | /* The following macro shall output rtl for the epilogue |
6e753900 RK |
1308 | to indicate a return from function during basic-block profiling. |
1309 | ||
1310 | If profiling_block_flag == 2: | |
1311 | ||
1312 | Output assembler code to call function `__bb_trace_ret'. | |
1313 | ||
1314 | Note that function `__bb_trace_ret' must not change the | |
1315 | machine state, especially the flag register. To grant | |
1316 | this, you must output code to save and restore registers | |
78a0d70c ZW |
1317 | either in this macro or in the macros MACHINE_STATE_SAVE |
1318 | and MACHINE_STATE_RESTORE. The last two macros will be | |
6e753900 RK |
1319 | used in the function `__bb_trace_ret', so you must make |
1320 | sure that the function prologue does not change any | |
78a0d70c | 1321 | register prior to saving it with MACHINE_STATE_SAVE. |
6e753900 RK |
1322 | |
1323 | else if profiling_block_flag != 0: | |
1324 | ||
1325 | The macro will not be used, so it need not distinguish | |
1326 | these cases. | |
1327 | */ | |
1328 | ||
e075ae69 RH |
1329 | #define FUNCTION_BLOCK_PROFILER_EXIT \ |
1330 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, \ | |
1331 | gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \ | |
1332 | const0_rtx)) | |
6e753900 RK |
1333 | |
1334 | /* The function `__bb_trace_func' is called in every basic block | |
1335 | and is not allowed to change the machine state. Saving (restoring) | |
1336 | the state can either be done in the BLOCK_PROFILER macro, | |
1337 | before calling function (rsp. after returning from function) | |
1338 | `__bb_trace_func', or it can be done inside the function by | |
1339 | defining the macros: | |
1340 | ||
1341 | MACHINE_STATE_SAVE(ID) | |
1342 | MACHINE_STATE_RESTORE(ID) | |
1343 | ||
1344 | In the latter case care must be taken, that the prologue code | |
1345 | of function `__bb_trace_func' does not already change the | |
1346 | state prior to saving it with MACHINE_STATE_SAVE. | |
1347 | ||
1348 | The parameter `ID' is a string identifying a unique macro use. | |
1349 | ||
1350 | On the i386 the initialization code at the begin of | |
1351 | function `__bb_trace_func' contains a `sub' instruction | |
1352 | therefore we handle save and restore of the flag register | |
78a0d70c ZW |
1353 | in the BLOCK_PROFILER macro. |
1354 | ||
1355 | Note that ebx, esi, and edi are callee-save, so we don't have to | |
1356 | preserve them explicitly. */ | |
6e753900 | 1357 | |
e075ae69 RH |
1358 | #define MACHINE_STATE_SAVE(ID) \ |
1359 | do { \ | |
1360 | register int eax_ __asm__("eax"); \ | |
1361 | register int ecx_ __asm__("ecx"); \ | |
1362 | register int edx_ __asm__("edx"); \ | |
78a0d70c ZW |
1363 | __asm__ __volatile__ ("\ |
1364 | push{l} %0\n\t\ | |
1365 | push{l} %1\n\t\ | |
1366 | push{l} %2" \ | |
1367 | : : "r"(eax_), "r"(ecx_), "r"(edx_)); \ | |
e075ae69 RH |
1368 | } while (0); |
1369 | ||
1370 | #define MACHINE_STATE_RESTORE(ID) \ | |
1371 | do { \ | |
1372 | register int eax_ __asm__("eax"); \ | |
1373 | register int ecx_ __asm__("ecx"); \ | |
1374 | register int edx_ __asm__("edx"); \ | |
78a0d70c ZW |
1375 | __asm__ __volatile__ ("\ |
1376 | pop{l} %2\n\t\ | |
1377 | pop{l} %1\n\t\ | |
1378 | pop{l} %0" \ | |
1379 | : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \ | |
e075ae69 | 1380 | } while (0); |
6e753900 | 1381 | |
c98f8742 JVA |
1382 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1383 | the stack pointer does not matter. The value is tested only in | |
1384 | functions that have frame pointers. | |
1385 | No definition is equivalent to always zero. */ | |
1386 | /* Note on the 386 it might be more efficient not to define this since | |
1387 | we have to restore it ourselves from the frame pointer, in order to | |
1388 | use pop */ | |
1389 | ||
1390 | #define EXIT_IGNORE_STACK 1 | |
1391 | ||
c98f8742 JVA |
1392 | /* Output assembler code for a block containing the constant parts |
1393 | of a trampoline, leaving space for the variable parts. */ | |
1394 | ||
a269a03c | 1395 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1396 | mov #STATIC,ecx |
a269a03c JC |
1397 | jmp FUNCTION |
1398 | The trampoline is generated entirely at runtime. The operand of JMP | |
1399 | is the address of FUNCTION relative to the instruction following the | |
1400 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1401 | |
1402 | /* Length in units of the trampoline for entering a nested function. */ | |
1403 | ||
a269a03c | 1404 | #define TRAMPOLINE_SIZE 10 |
c98f8742 JVA |
1405 | |
1406 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1407 | FNADDR is an RTX for the address of the function's pure code. | |
1408 | CXT is an RTX for the static chain value for the function. */ | |
1409 | ||
1410 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1411 | { \ | |
a269a03c JC |
1412 | /* Compute offset from the end of the jmp to the target function. */ \ |
1413 | rtx disp = expand_binop (SImode, sub_optab, FNADDR, \ | |
1414 | plus_constant (TRAMP, 10), \ | |
1415 | NULL_RTX, 1, OPTAB_DIRECT); \ | |
1416 | emit_move_insn (gen_rtx_MEM (QImode, TRAMP), GEN_INT (0xb9)); \ | |
f64cecad | 1417 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 1)), CXT); \ |
a269a03c JC |
1418 | emit_move_insn (gen_rtx_MEM (QImode, plus_constant (TRAMP, 5)), GEN_INT (0xe9));\ |
1419 | emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 6)), disp); \ | |
c98f8742 JVA |
1420 | } |
1421 | \f | |
1422 | /* Definitions for register eliminations. | |
1423 | ||
1424 | This is an array of structures. Each structure initializes one pair | |
1425 | of eliminable registers. The "from" register number is given first, | |
1426 | followed by "to". Eliminations of the same "from" register are listed | |
1427 | in order of preference. | |
1428 | ||
564d80f4 JH |
1429 | We have three registers that can be eliminated on the i386. First, the |
1430 | hard frame pointer register can often be eliminated in favor of the stack | |
1431 | pointer register. Secondly, the argument and frame pointer register can | |
1432 | always be eliminated; They are replaced with either the stack or frame pointer. */ | |
c98f8742 | 1433 | |
564d80f4 JH |
1434 | #define ELIMINABLE_REGS \ |
1435 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1436 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1437 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1438 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1439 | |
2c5a510c RH |
1440 | /* Given FROM and TO register numbers, say whether this elimination is |
1441 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1442 | |
1443 | All other eliminations are valid. */ | |
1444 | ||
2c5a510c RH |
1445 | #define CAN_ELIMINATE(FROM, TO) \ |
1446 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
c98f8742 JVA |
1447 | |
1448 | /* Define the offset between two registers, one to be eliminated, and the other | |
1449 | its replacement, at the start of a routine. */ | |
1450 | ||
1451 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
0903fcab | 1452 | (OFFSET) = ix86_initial_elimination_offset (FROM, TO) |
c98f8742 JVA |
1453 | \f |
1454 | /* Addressing modes, and classification of registers for them. */ | |
1455 | ||
940da324 JL |
1456 | /* #define HAVE_POST_INCREMENT 0 */ |
1457 | /* #define HAVE_POST_DECREMENT 0 */ | |
c98f8742 | 1458 | |
940da324 JL |
1459 | /* #define HAVE_PRE_DECREMENT 0 */ |
1460 | /* #define HAVE_PRE_INCREMENT 0 */ | |
c98f8742 JVA |
1461 | |
1462 | /* Macros to check register numbers against specific register classes. */ | |
1463 | ||
1464 | /* These assume that REGNO is a hard or pseudo reg number. | |
1465 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1466 | or a pseudo reg currently allocated to a suitable hard reg. | |
1467 | Since they use reg_renumber, they are safe only once reg_renumber | |
1468 | has been allocated, which happens in local-alloc.c. */ | |
1469 | ||
1470 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1471 | ((REGNO) < STACK_POINTER_REGNUM \ | |
1472 | || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) | |
1473 | ||
1474 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1475 | ((REGNO) <= STACK_POINTER_REGNUM \ | |
1476 | || (REGNO) == ARG_POINTER_REGNUM \ | |
564d80f4 | 1477 | || (REGNO) == FRAME_POINTER_REGNUM \ |
c98f8742 JVA |
1478 | || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) |
1479 | ||
1480 | #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) | |
1481 | #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) | |
1482 | ||
1483 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1484 | and check its validity for a certain class. | |
1485 | We have two alternate definitions for each of them. | |
1486 | The usual definition accepts all pseudo regs; the other rejects | |
1487 | them unless they have been allocated suitable hard regs. | |
1488 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1489 | ||
1490 | Most source files want to accept pseudo regs in the hope that | |
1491 | they will get allocated to the class that the insn wants them to be in. | |
1492 | Source files for reload pass need to be strict. | |
1493 | After reload, it makes no difference, since pseudo regs have | |
1494 | been eliminated by then. */ | |
1495 | ||
c98f8742 | 1496 | |
3b3c6a3f MM |
1497 | /* Non strict versions, pseudos are ok */ |
1498 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
1499 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
c98f8742 JVA |
1500 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1501 | ||
3b3c6a3f MM |
1502 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
1503 | (REGNO (X) <= STACK_POINTER_REGNUM \ | |
1504 | || REGNO (X) == ARG_POINTER_REGNUM \ | |
564d80f4 | 1505 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1506 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1507 | |
3b3c6a3f | 1508 | #define REG_OK_FOR_STRREG_NONSTRICT_P(X) \ |
c98f8742 JVA |
1509 | (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1510 | ||
3b3c6a3f MM |
1511 | /* Strict versions, hard registers only */ |
1512 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1513 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1514 | #define REG_OK_FOR_STRREG_STRICT_P(X) \ | |
c98f8742 JVA |
1515 | (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) |
1516 | ||
3b3c6a3f MM |
1517 | #ifndef REG_OK_STRICT |
1518 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
1519 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
1520 | #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X) | |
1521 | ||
1522 | #else | |
1523 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
1524 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
1525 | #define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X) | |
c98f8742 JVA |
1526 | #endif |
1527 | ||
1528 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1529 | that is a valid memory address for an instruction. | |
1530 | The MODE argument is the machine mode for the MEM expression | |
1531 | that wants to use this address. | |
1532 | ||
1533 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1534 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1535 | ||
1536 | See legitimize_pic_address in i386.c for details as to what | |
1537 | constitutes a legitimate address when -fpic is used. */ | |
1538 | ||
1539 | #define MAX_REGS_PER_ADDRESS 2 | |
1540 | ||
91bb873f RH |
1541 | #define CONSTANT_ADDRESS_P(X) \ |
1542 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1543 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST) | |
c98f8742 JVA |
1544 | |
1545 | /* Nonzero if the constant value X is a legitimate general operand. | |
1546 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1547 | ||
d7a29404 | 1548 | #define LEGITIMATE_CONSTANT_P(X) 1 |
c98f8742 | 1549 | |
3b3c6a3f MM |
1550 | #ifdef REG_OK_STRICT |
1551 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1552 | { \ | |
1553 | if (legitimate_address_p (MODE, X, 1)) \ | |
1554 | goto ADDR; \ | |
1555 | } | |
c98f8742 | 1556 | |
3b3c6a3f MM |
1557 | #else |
1558 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
c98f8742 | 1559 | { \ |
3b3c6a3f | 1560 | if (legitimate_address_p (MODE, X, 0)) \ |
c98f8742 | 1561 | goto ADDR; \ |
c98f8742 JVA |
1562 | } |
1563 | ||
3b3c6a3f MM |
1564 | #endif |
1565 | ||
c98f8742 JVA |
1566 | /* Try machine-dependent ways of modifying an illegitimate address |
1567 | to be legitimate. If we find one, return the new, valid address. | |
1568 | This macro is used in only one place: `memory_address' in explow.c. | |
1569 | ||
1570 | OLDX is the address as it was before break_out_memory_refs was called. | |
1571 | In some cases it is useful to look at this to decide what needs to be done. | |
1572 | ||
1573 | MODE and WIN are passed so that this macro can use | |
1574 | GO_IF_LEGITIMATE_ADDRESS. | |
1575 | ||
1576 | It is always safe for this macro to do nothing. It exists to recognize | |
1577 | opportunities to optimize the output. | |
1578 | ||
1579 | For the 80386, we handle X+REG by loading X into a register R and | |
1580 | using R+REG. R will go in a general reg and indexing will be used. | |
1581 | However, if REG is a broken-out memory address or multiplication, | |
1582 | nothing needs to be done because REG can certainly go in a general reg. | |
1583 | ||
1584 | When -fpic is used, special handling is needed for symbolic references. | |
1585 | See comments by legitimize_pic_address in i386.c for details. */ | |
1586 | ||
3b3c6a3f MM |
1587 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
1588 | { \ | |
3b3c6a3f MM |
1589 | (X) = legitimize_address (X, OLDX, MODE); \ |
1590 | if (memory_address_p (MODE, X)) \ | |
1591 | goto WIN; \ | |
1592 | } | |
c98f8742 | 1593 | |
d4ba09c0 SC |
1594 | #define REWRITE_ADDRESS(x) rewrite_address(x) |
1595 | ||
c98f8742 JVA |
1596 | /* Nonzero if the constant value X is a legitimate general operand |
1597 | when generating PIC code. It is given that flag_pic is on and | |
1598 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1599 | ||
e075ae69 RH |
1600 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
1601 | (! SYMBOLIC_CONST (X) \ | |
1602 | || legitimate_pic_address_disp_p (X)) | |
c98f8742 JVA |
1603 | |
1604 | #define SYMBOLIC_CONST(X) \ | |
1605 | (GET_CODE (X) == SYMBOL_REF \ | |
1606 | || GET_CODE (X) == LABEL_REF \ | |
1607 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
1608 | ||
1609 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1610 | has an effect that depends on the machine mode it is used for. | |
1611 | On the 80386, only postdecrement and postincrement address depend thus | |
1612 | (the amount of decrement or increment being the length of the operand). */ | |
1613 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1614 | if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL | |
1615 | \f | |
1616 | /* Define this macro if references to a symbol must be treated | |
1617 | differently depending on something about the variable or | |
1618 | function named by the symbol (such as what section it is in). | |
1619 | ||
b4ac57ab | 1620 | On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol |
c98f8742 JVA |
1621 | so that we may access it directly in the GOT. */ |
1622 | ||
90e0ee00 AH |
1623 | #define ENCODE_SECTION_INFO(DECL) \ |
1624 | do \ | |
1625 | { \ | |
1626 | if (flag_pic) \ | |
1627 | { \ | |
1628 | rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ | |
1629 | ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ | |
1630 | \ | |
1631 | if (GET_CODE (rtl) == MEM) \ | |
1632 | { \ | |
1633 | if (TARGET_DEBUG_ADDR \ | |
1634 | && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \ | |
1635 | { \ | |
1636 | fprintf (stderr, "Encode %s, public = %d\n", \ | |
1637 | IDENTIFIER_POINTER (DECL_NAME (DECL)), \ | |
1638 | TREE_PUBLIC (DECL)); \ | |
1639 | } \ | |
1640 | \ | |
1641 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ | |
1642 | = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ | |
1643 | || ! TREE_PUBLIC (DECL)); \ | |
1644 | } \ | |
1645 | } \ | |
1646 | } \ | |
c98f8742 | 1647 | while (0) |
d398b3b1 | 1648 | |
638b724c MM |
1649 | /* The `FINALIZE_PIC' macro serves as a hook to emit these special |
1650 | codes once the function is being compiled into assembly code, but | |
1651 | not before. (It is not done before, because in the case of | |
1652 | compiling an inline function, it would lead to multiple PIC | |
1653 | prologues being included in functions which used inline functions | |
1654 | and were compiled to assembly language.) */ | |
1655 | ||
1656 | #define FINALIZE_PIC \ | |
1657 | do \ | |
1658 | { \ | |
638b724c MM |
1659 | current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \ |
1660 | } \ | |
1661 | while (0) | |
1662 | ||
b08de47e MM |
1663 | \f |
1664 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
1665 | with arguments ARGS is a valid machine specific attribute for DECL. | |
1666 | The attributes in ATTRIBUTES have previously been assigned to DECL. */ | |
1667 | ||
7db4b149 | 1668 | #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \ |
e075ae69 | 1669 | (ix86_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS)) |
b08de47e MM |
1670 | |
1671 | /* If defined, a C expression whose value is nonzero if IDENTIFIER | |
1672 | with arguments ARGS is a valid machine specific attribute for TYPE. | |
1673 | The attributes in ATTRIBUTES have previously been assigned to TYPE. */ | |
1674 | ||
7db4b149 | 1675 | #define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ |
e075ae69 | 1676 | (ix86_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) |
b08de47e MM |
1677 | |
1678 | /* If defined, a C expression whose value is zero if the attributes on | |
1679 | TYPE1 and TYPE2 are incompatible, one if they are compatible, and | |
1680 | two if they are nearly compatible (which causes a warning to be | |
1681 | generated). */ | |
1682 | ||
1683 | #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ | |
e075ae69 | 1684 | (ix86_comp_type_attributes (TYPE1, TYPE2)) |
b08de47e MM |
1685 | |
1686 | /* If defined, a C statement that assigns default attributes to newly | |
1687 | defined TYPE. */ | |
1688 | ||
1689 | /* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */ | |
1690 | ||
1691 | /* Max number of args passed in registers. If this is more than 3, we will | |
1692 | have problems with ebx (register #4), since it is a caller save register and | |
1693 | is also used as the pic register in ELF. So for now, don't allow more than | |
1694 | 3 registers to be passed in registers. */ | |
1695 | ||
1696 | #define REGPARM_MAX 3 | |
1697 | ||
c98f8742 JVA |
1698 | \f |
1699 | /* Specify the machine mode that this machine uses | |
1700 | for the index in the tablejump instruction. */ | |
1701 | #define CASE_VECTOR_MODE Pmode | |
1702 | ||
18543a22 ILT |
1703 | /* Define as C expression which evaluates to nonzero if the tablejump |
1704 | instruction expects the table to contain offsets from the address of the | |
1705 | table. | |
1706 | Do not define this if the table should contain absolute addresses. */ | |
1707 | /* #define CASE_VECTOR_PC_RELATIVE 1 */ | |
c98f8742 JVA |
1708 | |
1709 | /* Specify the tree operation to be used to convert reals to integers. | |
1710 | This should be changed to take advantage of fist --wfs ?? | |
1711 | */ | |
1712 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1713 | ||
1714 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1715 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1716 | ||
1717 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1718 | #define DEFAULT_SIGNED_CHAR 1 | |
1719 | ||
1720 | /* Max number of bytes we can move from memory to memory | |
1721 | in one reasonably fast instruction. */ | |
1722 | #define MOVE_MAX 4 | |
1723 | ||
7e24ffc9 HPN |
1724 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
1725 | move-instruction pairs, we will do a movstr or libcall instead. | |
1726 | Increasing the value will always make code faster, but eventually | |
1727 | incurs high cost in increased code size. | |
c98f8742 | 1728 | |
e2e52e1b | 1729 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1730 | |
e2e52e1b | 1731 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 JVA |
1732 | |
1733 | /* Define if shifts truncate the shift count | |
1734 | which implies one can omit a sign-extension or zero-extension | |
1735 | of a shift count. */ | |
241e1a89 | 1736 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
1737 | |
1738 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1739 | ||
1740 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1741 | is done just by pretending it is already truncated. */ | |
1742 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1743 | ||
1744 | /* We assume that the store-condition-codes instructions store 0 for false | |
1745 | and some other value for true. This is the value stored for true. */ | |
1746 | ||
1747 | #define STORE_FLAG_VALUE 1 | |
1748 | ||
1749 | /* When a prototype says `char' or `short', really pass an `int'. | |
1750 | (The 386 can't easily push less than an int.) */ | |
1751 | ||
cb560352 | 1752 | #define PROMOTE_PROTOTYPES 1 |
c98f8742 | 1753 | |
d9f32422 JH |
1754 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1755 | TYPE and which has the specified mode and signedness is to be | |
1756 | stored in a register. This macro is only called when TYPE is a | |
1757 | scalar type. | |
1758 | ||
1759 | On i386 it is sometimes usefull to promote HImode and QImode | |
1760 | quantities to SImode. The choice depends on target type. */ | |
1761 | ||
1762 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1763 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ | |
1764 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
1765 | (MODE) = SImode; | |
1766 | ||
c98f8742 JVA |
1767 | /* Specify the machine mode that pointers have. |
1768 | After generation of rtl, the compiler makes no further distinction | |
1769 | between pointers and any other objects of this machine mode. */ | |
1770 | #define Pmode SImode | |
1771 | ||
1772 | /* A function address in a call instruction | |
1773 | is a byte address (for indexing purposes) | |
1774 | so give the MEM rtx a byte's mode. */ | |
1775 | #define FUNCTION_MODE QImode | |
d4ba09c0 SC |
1776 | \f |
1777 | /* A part of a C `switch' statement that describes the relative costs | |
1778 | of constant RTL expressions. It must contain `case' labels for | |
1779 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
1780 | and `const_double'. Each case must ultimately reach a `return' | |
1781 | statement to return the relative cost of the use of that kind of | |
1782 | constant value in an expression. The cost may depend on the | |
1783 | precise value of the constant, which is available for examination | |
1784 | in X, and the rtx code of the expression in which it is contained, | |
1785 | found in OUTER_CODE. | |
1786 | ||
1787 | CODE is the expression code--redundant, since it can be obtained | |
1788 | with `GET_CODE (X)'. */ | |
c98f8742 | 1789 | |
3bb22aee | 1790 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ |
c98f8742 | 1791 | case CONST_INT: \ |
e5e809f4 | 1792 | return (unsigned) INTVAL (RTX) < 256 ? 0 : 1; \ |
c98f8742 JVA |
1793 | case CONST: \ |
1794 | case LABEL_REF: \ | |
1795 | case SYMBOL_REF: \ | |
76565a24 | 1796 | return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 1; \ |
d4ba09c0 | 1797 | \ |
c98f8742 JVA |
1798 | case CONST_DOUBLE: \ |
1799 | { \ | |
7488be4e JVA |
1800 | int code; \ |
1801 | if (GET_MODE (RTX) == VOIDmode) \ | |
1802 | return 2; \ | |
d4ba09c0 | 1803 | \ |
7488be4e | 1804 | code = standard_80387_constant_p (RTX); \ |
c98f8742 JVA |
1805 | return code == 1 ? 0 : \ |
1806 | code == 2 ? 1 : \ | |
1807 | 2; \ | |
3bb22aee | 1808 | } |
c98f8742 | 1809 | |
76565a24 | 1810 | /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */ |
e075ae69 RH |
1811 | #define TOPLEVEL_COSTS_N_INSNS(N) \ |
1812 | do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0) | |
76565a24 | 1813 | |
d4ba09c0 SC |
1814 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. |
1815 | This can be used, for example, to indicate how costly a multiply | |
1816 | instruction is. In writing this macro, you can use the construct | |
1817 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
1818 | instructions. OUTER_CODE is the code of the expression in which X | |
1819 | is contained. | |
1820 | ||
1821 | This macro is optional; do not define it if the default cost | |
1822 | assumptions are adequate for the target machine. */ | |
1823 | ||
1824 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
1825 | case ASHIFT: \ | |
1826 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1827 | && GET_MODE (XEXP (X, 0)) == SImode) \ | |
1828 | { \ | |
1829 | HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
d4ba09c0 | 1830 | if (value == 1) \ |
e075ae69 | 1831 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ |
d4ba09c0 | 1832 | if (value == 2 || value == 3) \ |
e075ae69 | 1833 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ |
d4ba09c0 SC |
1834 | } \ |
1835 | /* fall through */ \ | |
1836 | \ | |
1837 | case ROTATE: \ | |
1838 | case ASHIFTRT: \ | |
1839 | case LSHIFTRT: \ | |
1840 | case ROTATERT: \ | |
76565a24 SC |
1841 | if (GET_MODE (XEXP (X, 0)) == DImode) \ |
1842 | { \ | |
1843 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
54d26233 MH |
1844 | { \ |
1845 | if (INTVAL (XEXP (X, 1)) > 32) \ | |
e075ae69 RH |
1846 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \ |
1847 | else \ | |
1848 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \ | |
1849 | } \ | |
1850 | else \ | |
1851 | { \ | |
1852 | if (GET_CODE (XEXP (X, 1)) == AND) \ | |
1853 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \ | |
1854 | else \ | |
1855 | TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \ | |
54d26233 | 1856 | } \ |
76565a24 | 1857 | } \ |
e075ae69 RH |
1858 | else \ |
1859 | { \ | |
1860 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1861 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ | |
1862 | else \ | |
1863 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \ | |
1864 | } \ | |
1865 | break; \ | |
d4ba09c0 SC |
1866 | \ |
1867 | case MULT: \ | |
1868 | if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1869 | { \ | |
1870 | unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \ | |
1871 | int nbits = 0; \ | |
1872 | \ | |
76565a24 | 1873 | if (value == 2) \ |
e075ae69 | 1874 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ |
76565a24 | 1875 | if (value == 4 || value == 8) \ |
e075ae69 | 1876 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \ |
76565a24 | 1877 | \ |
d4ba09c0 SC |
1878 | while (value != 0) \ |
1879 | { \ | |
1880 | nbits++; \ | |
1881 | value >>= 1; \ | |
1882 | } \ | |
1883 | \ | |
76565a24 | 1884 | if (nbits == 1) \ |
e075ae69 RH |
1885 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \ |
1886 | else \ | |
1887 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ | |
1888 | + nbits * ix86_cost->mult_bit); \ | |
d4ba09c0 | 1889 | } \ |
d4ba09c0 | 1890 | else /* This is arbitrary */ \ |
76565a24 SC |
1891 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \ |
1892 | + 7 * ix86_cost->mult_bit); \ | |
d4ba09c0 SC |
1893 | \ |
1894 | case DIV: \ | |
1895 | case UDIV: \ | |
1896 | case MOD: \ | |
1897 | case UMOD: \ | |
76565a24 | 1898 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \ |
d4ba09c0 SC |
1899 | \ |
1900 | case PLUS: \ | |
e075ae69 RH |
1901 | if (GET_CODE (XEXP (X, 0)) == PLUS \ |
1902 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \ | |
1903 | && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \ | |
1904 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1905 | { \ | |
1906 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \ | |
1907 | if (val == 2 || val == 4 || val == 8) \ | |
1908 | { \ | |
1909 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
1910 | + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \ | |
1911 | + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \ | |
1912 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1913 | } \ | |
1914 | } \ | |
1915 | else if (GET_CODE (XEXP (X, 0)) == MULT \ | |
1916 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
1917 | { \ | |
1918 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
1919 | if (val == 2 || val == 4 || val == 8) \ | |
1920 | { \ | |
1921 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
1922 | + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ | |
1923 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1924 | } \ | |
1925 | } \ | |
1926 | else if (GET_CODE (XEXP (X, 0)) == PLUS) \ | |
1927 | { \ | |
1928 | return (COSTS_N_INSNS (ix86_cost->lea) \ | |
1929 | + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ | |
1930 | + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \ | |
1931 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1932 | } \ | |
d4ba09c0 SC |
1933 | \ |
1934 | /* fall through */ \ | |
1935 | case AND: \ | |
1936 | case IOR: \ | |
1937 | case XOR: \ | |
1938 | case MINUS: \ | |
76565a24 | 1939 | if (GET_MODE (X) == DImode) \ |
e075ae69 RH |
1940 | return (COSTS_N_INSNS (ix86_cost->add) * 2 \ |
1941 | + (rtx_cost (XEXP (X, 0), OUTER_CODE) \ | |
1942 | << (GET_MODE (XEXP (X, 0)) != DImode)) \ | |
1943 | + (rtx_cost (XEXP (X, 1), OUTER_CODE) \ | |
1944 | << (GET_MODE (XEXP (X, 1)) != DImode))); \ | |
1945 | \ | |
1946 | /* fall through */ \ | |
d4ba09c0 SC |
1947 | case NEG: \ |
1948 | case NOT: \ | |
76565a24 | 1949 | if (GET_MODE (X) == DImode) \ |
e075ae69 RH |
1950 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \ |
1951 | TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \ | |
1952 | \ | |
1953 | egress_rtx_costs: \ | |
1954 | break; | |
d4ba09c0 SC |
1955 | |
1956 | ||
1957 | /* An expression giving the cost of an addressing mode that contains | |
1958 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
1959 | expression and the `CONST_COSTS' values. | |
1960 | ||
1961 | For most CISC machines, the default cost is a good approximation | |
1962 | of the true cost of the addressing mode. However, on RISC | |
1963 | machines, all instructions normally have the same length and | |
1964 | execution time. Hence all addresses will have equal costs. | |
1965 | ||
1966 | In cases where more than one form of an address is known, the form | |
1967 | with the lowest cost will be used. If multiple forms have the | |
1968 | same, lowest, cost, the one that is the most complex will be used. | |
1969 | ||
1970 | For example, suppose an address that is equal to the sum of a | |
1971 | register and a constant is used twice in the same basic block. | |
1972 | When this macro is not defined, the address will be computed in a | |
1973 | register and memory references will be indirect through that | |
1974 | register. On machines where the cost of the addressing mode | |
1975 | containing the sum is no higher than that of a simple indirect | |
1976 | reference, this will produce an additional instruction and | |
1977 | possibly require an additional register. Proper specification of | |
1978 | this macro eliminates this overhead for such machines. | |
1979 | ||
1980 | Similar use of this macro is made in strength reduction of loops. | |
1981 | ||
1982 | ADDRESS need not be valid as an address. In such a case, the cost | |
1983 | is not relevant and can be any value; invalid addresses need not be | |
1984 | assigned a different cost. | |
1985 | ||
1986 | On machines where an address involving more than one register is as | |
1987 | cheap as an address computation involving only one register, | |
1988 | defining `ADDRESS_COST' to reflect this can cause two registers to | |
1989 | be live over a region of code where only one would have been if | |
1990 | `ADDRESS_COST' were not defined in that manner. This effect should | |
1991 | be considered in the definition of this macro. Equivalent costs | |
1992 | should probably only be given to addresses with different numbers | |
1993 | of registers on machines with lots of registers. | |
1994 | ||
1995 | This macro will normally either not be defined or be defined as a | |
1996 | constant. | |
c98f8742 JVA |
1997 | |
1998 | For i386, it is better to use a complex address than let gcc copy | |
1999 | the address into a reg and make a new pseudo. But not if the address | |
2000 | requires to two regs - that would mean more pseudos with longer | |
2001 | lifetimes. */ | |
2002 | ||
2003 | #define ADDRESS_COST(RTX) \ | |
2004 | ((CONSTANT_P (RTX) \ | |
2005 | || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ | |
2006 | && REG_P (XEXP (RTX, 0)))) ? 0 \ | |
2007 | : REG_P (RTX) ? 1 \ | |
2008 | : 2) | |
d4ba09c0 | 2009 | |
96e7ae40 JH |
2010 | /* A C expression for the cost of moving data from a register in class FROM to |
2011 | one in class TO. The classes are expressed using the enumeration values | |
2012 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
2013 | interpreted relative to that. | |
d4ba09c0 | 2014 | |
96e7ae40 JH |
2015 | It is not required that the cost always equal 2 when FROM is the same as TO; |
2016 | on some machines it is expensive to move between registers if they are not | |
2017 | general registers. | |
d4ba09c0 SC |
2018 | |
2019 | On the i386, copying between floating-point and fixed-point | |
96e7ae40 JH |
2020 | registers is done trough memory. |
2021 | ||
2022 | Integer -> fp moves are noticeably slower than the opposite direction | |
2023 | because of the partial memory stall they cause. Give it an | |
2024 | arbitary high cost. | |
2025 | */ | |
d4ba09c0 SC |
2026 | |
2027 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ | |
96e7ae40 JH |
2028 | ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ |
2029 | ? (MEMORY_MOVE_COST (DFmode, CLASS1, 0) \ | |
2030 | + MEMORY_MOVE_COST (DFmode, CLASS2, 1)) \ | |
2031 | : (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2)) ? 10 : 2) | |
d4ba09c0 SC |
2032 | |
2033 | /* A C expression for the cost of moving data of mode M between a | |
2034 | register and memory. A value of 2 is the default; this cost is | |
2035 | relative to those in `REGISTER_MOVE_COST'. | |
2036 | ||
2037 | If moving between registers and memory is more expensive than | |
2038 | between two registers, you should define this macro to express the | |
7c6b971d JH |
2039 | relative cost. |
2040 | ||
2041 | Model also increased moving costs of QImode registers in non | |
2042 | Q_REGS classes. | |
2043 | */ | |
d4ba09c0 | 2044 | |
96e7ae40 JH |
2045 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ |
2046 | (FLOAT_CLASS_P (CLASS) \ | |
2047 | ? (GET_MODE_SIZE (MODE)==4 \ | |
2048 | ? (IN ? ix86_cost->fp_load[0] : ix86_cost->fp_store[0]) \ | |
2049 | : (GET_MODE_SIZE (MODE)==8 \ | |
2050 | ? (IN ? ix86_cost->fp_load[1] : ix86_cost->fp_store[1]) \ | |
2051 | : (IN ? ix86_cost->fp_load[2] : ix86_cost->fp_store[2]))) \ | |
2052 | : (GET_MODE_SIZE (MODE)==1 \ | |
7c6b971d JH |
2053 | ? (IN ? (Q_CLASS_P (CLASS) ? ix86_cost->int_load[0] \ |
2054 | : ix86_cost->movzbl_load) \ | |
2055 | : (Q_CLASS_P (CLASS) ? ix86_cost->int_store[0] \ | |
2056 | : ix86_cost->int_store[0] + 4)) \ | |
96e7ae40 JH |
2057 | : (GET_MODE_SIZE (MODE)==2 \ |
2058 | ? (IN ? ix86_cost->int_load[1] : ix86_cost->int_store[1]) \ | |
2059 | : ((IN ? ix86_cost->int_load[2] : ix86_cost->int_store[2]) \ | |
2060 | * GET_MODE_SIZE (MODE) / 4)))) | |
d4ba09c0 SC |
2061 | |
2062 | /* A C expression for the cost of a branch instruction. A value of 1 | |
2063 | is the default; other values are interpreted relative to that. */ | |
2064 | ||
e075ae69 | 2065 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
2066 | |
2067 | /* Define this macro as a C expression which is nonzero if accessing | |
2068 | less than a word of memory (i.e. a `char' or a `short') is no | |
2069 | faster than accessing a word of memory, i.e., if such access | |
2070 | require more than one instruction or if there is no difference in | |
2071 | cost between byte and (aligned) word loads. | |
2072 | ||
2073 | When this macro is not defined, the compiler will access a field by | |
2074 | finding the smallest containing object; when it is defined, a | |
2075 | fullword load will be used if alignment permits. Unless bytes | |
2076 | accesses are faster than word accesses, using word accesses is | |
2077 | preferable since it may eliminate subsequent memory access if | |
2078 | subsequent accesses occur to other fields in the same word of the | |
2079 | structure, but to different bytes. */ | |
2080 | ||
2081 | #define SLOW_BYTE_ACCESS 0 | |
2082 | ||
2083 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2084 | #define SLOW_SHORT_ACCESS 0 | |
2085 | ||
2086 | /* Define this macro if zero-extension (of a `char' or `short' to an | |
2087 | `int') can be done faster if the destination is a register that is | |
2088 | known to be zero. | |
2089 | ||
2090 | If you define this macro, you must have instruction patterns that | |
2091 | recognize RTL structures like this: | |
2092 | ||
2093 | (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...) | |
2094 | ||
2095 | and likewise for `HImode'. */ | |
2096 | ||
2097 | /* #define SLOW_ZERO_EXTEND */ | |
2098 | ||
2099 | /* Define this macro to be the value 1 if unaligned accesses have a | |
2100 | cost many times greater than aligned accesses, for example if they | |
2101 | are emulated in a trap handler. | |
2102 | ||
2103 | When this macro is non-zero, the compiler will act as if | |
2104 | `STRICT_ALIGNMENT' were non-zero when generating code for block | |
2105 | moves. This can cause significantly more instructions to be | |
2106 | produced. Therefore, do not set this macro non-zero if unaligned | |
2107 | accesses only add a cycle or two to the time for a memory access. | |
2108 | ||
2109 | If the value of this macro is always zero, it need not be defined. */ | |
2110 | ||
e1565e65 | 2111 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 SC |
2112 | |
2113 | /* Define this macro to inhibit strength reduction of memory | |
2114 | addresses. (On some machines, such strength reduction seems to do | |
2115 | harm rather than good.) */ | |
2116 | ||
2117 | /* #define DONT_REDUCE_ADDR */ | |
2118 | ||
2119 | /* Define this macro if it is as good or better to call a constant | |
2120 | function address than to call an address kept in a register. | |
2121 | ||
2122 | Desirable on the 386 because a CALL with a constant address is | |
2123 | faster than one with a register address. */ | |
2124 | ||
2125 | #define NO_FUNCTION_CSE | |
2126 | ||
2127 | /* Define this macro if it is as good or better for a function to call | |
2128 | itself with an explicit address than to call an address kept in a | |
2129 | register. */ | |
2130 | ||
2131 | #define NO_RECURSIVE_FUNCTION_CSE | |
2132 | ||
2133 | /* A C statement (sans semicolon) to update the integer variable COST | |
2134 | based on the relationship between INSN that is dependent on | |
2135 | DEP_INSN through the dependence LINK. The default is to make no | |
2136 | adjustment to COST. This can be used for example to specify to | |
2137 | the scheduler that an output- or anti-dependence does not incur | |
2138 | the same cost as a data-dependence. */ | |
2139 | ||
e075ae69 RH |
2140 | #define ADJUST_COST(insn,link,dep_insn,cost) \ |
2141 | (cost) = ix86_adjust_cost(insn, link, dep_insn, cost) | |
d4ba09c0 | 2142 | |
e075ae69 RH |
2143 | #define ISSUE_RATE \ |
2144 | ix86_issue_rate () | |
2145 | ||
2146 | #define MD_SCHED_INIT(DUMP, SCHED_VERBOSE) \ | |
2147 | ix86_sched_init (DUMP, SCHED_VERBOSE) | |
d4ba09c0 | 2148 | |
e075ae69 RH |
2149 | #define MD_SCHED_REORDER(DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK, CIM) \ |
2150 | (CIM) = ix86_sched_reorder (DUMP, SCHED_VERBOSE, READY, N_READY, CLOCK) | |
a269a03c | 2151 | |
e075ae69 RH |
2152 | #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \ |
2153 | ((CAN_ISSUE_MORE) = \ | |
2154 | ix86_variable_issue (DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE)) | |
c98f8742 | 2155 | \f |
c572e5ba JVA |
2156 | /* Add any extra modes needed to represent the condition code. |
2157 | ||
e075ae69 RH |
2158 | For the i386, we need separate modes when floating-point |
2159 | equality comparisons are being done. | |
2160 | ||
2161 | Add CCNO to indicate No Overflow, which is often also includes | |
2162 | No Carry. This is typically used on the output of logicals, | |
2163 | and is only valid in comparisons against zero. */ | |
c572e5ba | 2164 | |
e075ae69 RH |
2165 | #define EXTRA_CC_MODES \ |
2166 | CC(CCNOmode, "CCNO") \ | |
2167 | CC(CCFPmode, "CCFP") \ | |
2168 | CC(CCFPUmode, "CCFPU") | |
c572e5ba JVA |
2169 | |
2170 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2171 | return the mode to be used for the comparison. | |
2172 | ||
2173 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2174 | VOIDmode should be used in all other cases. |
c572e5ba | 2175 | |
e075ae69 RH |
2176 | For integer comparisons against zero, reduce to CCNOmode if |
2177 | possible, to allow for more combinations. */ | |
c98f8742 | 2178 | |
e075ae69 RH |
2179 | #define SELECT_CC_MODE(OP,X,Y) \ |
2180 | (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
2181 | ? (OP) == EQ || (OP) == NE ? CCFPUmode : CCFPmode \ | |
2182 | : (OP) == LE || (OP) == GT ? CCmode \ | |
2183 | : (Y) != const0_rtx ? CCmode \ | |
2184 | : CCNOmode) | |
c98f8742 JVA |
2185 | \f |
2186 | /* Control the assembler format that we output, to the extent | |
2187 | this does not vary between assemblers. */ | |
2188 | ||
2189 | /* How to refer to registers in assembler output. | |
2190 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2191 | ||
2192 | /* In order to refer to the first 8 regs as 32 bit regs prefix an "e" | |
2193 | For non floating point regs, the following are the HImode names. | |
2194 | ||
2195 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
9e06e321 | 2196 | instead of just "%st". PRINT_REG handles this with the "y" code. */ |
c98f8742 | 2197 | |
e075ae69 RH |
2198 | #define HI_REGISTER_NAMES \ |
2199 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
2200 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \ | |
564d80f4 | 2201 | "flags","fpsr", "dirflag", "frame" } |
c98f8742 JVA |
2202 | |
2203 | #define REGISTER_NAMES HI_REGISTER_NAMES | |
2204 | ||
2205 | /* Table of additional register names to use in user input. */ | |
2206 | ||
2207 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
2208 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2209 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2210 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2211 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } | |
c98f8742 JVA |
2212 | |
2213 | /* Note we are omitting these since currently I don't know how | |
2214 | to get gcc to use these, since they want the same but different | |
2215 | number as al, and ax. | |
2216 | */ | |
2217 | ||
b4ac57ab | 2218 | /* note the last four are not really qi_registers, but |
c98f8742 JVA |
2219 | the md will have to never output movb into one of them |
2220 | only a movw . There is no movb into the last four regs */ | |
2221 | ||
2222 | #define QI_REGISTER_NAMES \ | |
2223 | {"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} | |
2224 | ||
2225 | /* These parallel the array above, and can be used to access bits 8:15 | |
2226 | of regs 0 through 3. */ | |
2227 | ||
2228 | #define QI_HIGH_REGISTER_NAMES \ | |
2229 | {"ah", "dh", "ch", "bh", } | |
2230 | ||
2231 | /* How to renumber registers for dbx and gdb. */ | |
2232 | ||
83774849 RH |
2233 | #define DBX_REGISTER_NUMBER(n) dbx_register_map[n] |
2234 | ||
2235 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
2236 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2237 | |
469ac993 JM |
2238 | /* Before the prologue, RA is at 0(%esp). */ |
2239 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2240 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
c5c76735 | 2241 | |
e414ab29 RH |
2242 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
2243 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
2244 | ((COUNT) == 0 \ | |
c5c76735 JL |
2245 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -4))\ |
2246 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, 4))) | |
e414ab29 | 2247 | |
469ac993 JM |
2248 | /* PC is dbx register 8; let's use that column for RA. */ |
2249 | #define DWARF_FRAME_RETURN_COLUMN 8 | |
2250 | ||
a6ab3aad JM |
2251 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
2252 | #define INCOMING_FRAME_SP_OFFSET 4 | |
2253 | ||
c98f8742 JVA |
2254 | /* This is how to output the definition of a user-level label named NAME, |
2255 | such as the label on a static function or variable NAME. */ | |
2256 | ||
2257 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2258 | (assemble_name (FILE, NAME), fputs (":\n", FILE)) | |
2259 | ||
2260 | /* This is how to output an assembler line defining a `double' constant. */ | |
2261 | ||
0038aea6 JVA |
2262 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
2263 | do { long l[2]; \ | |
2264 | REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ | |
e075ae69 | 2265 | fprintf (FILE, "%s\t0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \ |
0038aea6 | 2266 | } while (0) |
c98f8742 | 2267 | |
0038aea6 JVA |
2268 | /* This is how to output a `long double' extended real constant. */ |
2269 | ||
2270 | #undef ASM_OUTPUT_LONG_DOUBLE | |
2271 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
2272 | do { long l[3]; \ | |
2273 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ | |
e075ae69 | 2274 | fprintf (FILE, "%s\t0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \ |
0038aea6 | 2275 | } while (0) |
c98f8742 JVA |
2276 | |
2277 | /* This is how to output an assembler line defining a `float' constant. */ | |
2278 | ||
0038aea6 JVA |
2279 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
2280 | do { long l; \ | |
2281 | REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ | |
e075ae69 | 2282 | fprintf ((FILE), "%s\t0x%lx\n", ASM_LONG, l); \ |
c98f8742 JVA |
2283 | } while (0) |
2284 | ||
c98f8742 JVA |
2285 | /* Store in OUTPUT a string (made with alloca) containing |
2286 | an assembler-name for a local static variable named NAME. | |
2287 | LABELNO is an integer which is different for each call. */ | |
2288 | ||
2289 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2290 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2291 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2292 | ||
c98f8742 JVA |
2293 | /* This is how to output an assembler line defining an `int' constant. */ |
2294 | ||
2295 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
e075ae69 | 2296 | ( fprintf (FILE, "%s\t", ASM_LONG), \ |
c98f8742 JVA |
2297 | output_addr_const (FILE,(VALUE)), \ |
2298 | putc('\n',FILE)) | |
2299 | ||
2300 | /* Likewise for `char' and `short' constants. */ | |
2301 | /* is this supposed to do align too?? */ | |
2302 | ||
2303 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
e075ae69 | 2304 | ( fprintf (FILE, "%s\t", ASM_SHORT), \ |
c98f8742 JVA |
2305 | output_addr_const (FILE,(VALUE)), \ |
2306 | putc('\n',FILE)) | |
2307 | ||
c98f8742 | 2308 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ |
e075ae69 | 2309 | ( fprintf (FILE, "%s\t", ASM_BYTE_OP), \ |
c98f8742 JVA |
2310 | output_addr_const (FILE, (VALUE)), \ |
2311 | putc ('\n', FILE)) | |
2312 | ||
2313 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2314 | ||
2315 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
e075ae69 | 2316 | asm_fprintf ((FILE), "%s\t0x%x\n", ASM_BYTE_OP, (VALUE)) |
c98f8742 JVA |
2317 | |
2318 | /* This is how to output an insn to push a register on the stack. | |
2319 | It need not be very fast code. */ | |
2320 | ||
2321 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
e075ae69 | 2322 | asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO]) |
c98f8742 JVA |
2323 | |
2324 | /* This is how to output an insn to pop a register from the stack. | |
2325 | It need not be very fast code. */ | |
2326 | ||
2327 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
e075ae69 | 2328 | asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO]) |
c98f8742 JVA |
2329 | |
2330 | /* This is how to output an element of a case-vector that is absolute. | |
2331 | */ | |
2332 | ||
2333 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
2334 | fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) | |
2335 | ||
2336 | /* This is how to output an element of a case-vector that is relative. | |
2337 | We don't use these on the 386 yet, because the ATT assembler can't do | |
2338 | forward reference the differences. | |
2339 | */ | |
2340 | ||
33f7f353 | 2341 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
e075ae69 | 2342 | fprintf (FILE, "\t%s\t%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL) |
c98f8742 | 2343 | |
1865dbb5 JM |
2344 | /* A C statement that outputs an address constant appropriate to |
2345 | for DWARF debugging. */ | |
2346 | ||
2347 | #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \ | |
2348 | i386_dwarf_output_addr_const((FILE),(X)) | |
2349 | ||
2350 | /* Either simplify a location expression, or return the original. */ | |
2351 | ||
2352 | #define ASM_SIMPLIFY_DWARF_ADDR(X) \ | |
2353 | i386_simplify_dwarf_addr(X) | |
2354 | ||
c98f8742 JVA |
2355 | /* Define the parentheses used to group arithmetic operations |
2356 | in assembler code. */ | |
2357 | ||
2358 | #define ASM_OPEN_PAREN "" | |
2359 | #define ASM_CLOSE_PAREN "" | |
2360 | ||
2361 | /* Define results of standard character escape sequences. */ | |
2362 | #define TARGET_BELL 007 | |
2363 | #define TARGET_BS 010 | |
2364 | #define TARGET_TAB 011 | |
2365 | #define TARGET_NEWLINE 012 | |
2366 | #define TARGET_VT 013 | |
2367 | #define TARGET_FF 014 | |
2368 | #define TARGET_CR 015 | |
74b42c8b | 2369 | \f |
c98f8742 JVA |
2370 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2371 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2372 | The CODE z takes the size of operand from the following digit, and | |
2373 | outputs b,w,or l respectively. | |
2374 | ||
2375 | On the 80386, we use several such letters: | |
2376 | f -- float insn (print a CONST_DOUBLE as a float rather than in hex). | |
0038aea6 | 2377 | L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. |
c98f8742 JVA |
2378 | R -- print the prefix for register names. |
2379 | z -- print the opcode suffix for the size of the current operand. | |
2380 | * -- print a star (in certain assembler syntax) | |
5cb6195d RH |
2381 | P -- if PIC, print an @PLT suffix. |
2382 | X -- don't print any sort of PIC '@' suffix for a symbol. | |
5cb6195d RH |
2383 | s -- ??? something to do with double shifts. not actually used, afaik. |
2384 | C -- print a conditional move suffix corresponding to the op code. | |
2385 | c -- likewise, but reverse the condition. | |
2386 | F,f -- likewise, but for floating-point. */ | |
c98f8742 JVA |
2387 | |
2388 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
e075ae69 | 2389 | ((CODE) == '*') |
c98f8742 | 2390 | |
74b42c8b RS |
2391 | /* Print the name of a register based on its machine mode and number. |
2392 | If CODE is 'w', pretend the mode is HImode. | |
2393 | If CODE is 'b', pretend the mode is QImode. | |
2394 | If CODE is 'k', pretend the mode is SImode. | |
2395 | If CODE is 'h', pretend the reg is the `high' byte register. | |
2396 | If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ | |
2397 | ||
e075ae69 RH |
2398 | #define PRINT_REG(X, CODE, FILE) \ |
2399 | print_reg (X, CODE, FILE) | |
74b42c8b | 2400 | |
c98f8742 JVA |
2401 | #define PRINT_OPERAND(FILE, X, CODE) \ |
2402 | print_operand (FILE, X, CODE) | |
c98f8742 JVA |
2403 | |
2404 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2405 | print_operand_address (FILE, ADDR) | |
2406 | ||
aa3e8d2a JVA |
2407 | /* Print the name of a register for based on its machine mode and number. |
2408 | This macro is used to print debugging output. | |
2409 | This macro is different from PRINT_REG in that it may be used in | |
2410 | programs that are not linked with aux-output.o. */ | |
2411 | ||
e075ae69 | 2412 | #define DEBUG_PRINT_REG(X, CODE, FILE) \ |
69ddee61 KG |
2413 | do { static const char * const hi_name[] = HI_REGISTER_NAMES; \ |
2414 | static const char * const qi_name[] = QI_REGISTER_NAMES; \ | |
e075ae69 RH |
2415 | fprintf (FILE, "%d ", REGNO (X)); \ |
2416 | if (REGNO (X) == FLAGS_REG) \ | |
2417 | { fputs ("flags", FILE); break; } \ | |
7c7ef435 JH |
2418 | if (REGNO (X) == DIRFLAG_REG) \ |
2419 | { fputs ("dirflag", FILE); break; } \ | |
e075ae69 RH |
2420 | if (REGNO (X) == FPSR_REG) \ |
2421 | { fputs ("fpsr", FILE); break; } \ | |
aa3e8d2a JVA |
2422 | if (REGNO (X) == ARG_POINTER_REGNUM) \ |
2423 | { fputs ("argp", FILE); break; } \ | |
564d80f4 JH |
2424 | if (REGNO (X) == FRAME_POINTER_REGNUM) \ |
2425 | { fputs ("frame", FILE); break; } \ | |
aa3e8d2a JVA |
2426 | if (STACK_TOP_P (X)) \ |
2427 | { fputs ("st(0)", FILE); break; } \ | |
b0ceea8c RK |
2428 | if (FP_REG_P (X)) \ |
2429 | { fputs (hi_name[REGNO(X)], FILE); break; } \ | |
aa3e8d2a JVA |
2430 | switch (GET_MODE_SIZE (GET_MODE (X))) \ |
2431 | { \ | |
b0ceea8c RK |
2432 | default: \ |
2433 | fputs ("e", FILE); \ | |
aa3e8d2a JVA |
2434 | case 2: \ |
2435 | fputs (hi_name[REGNO (X)], FILE); \ | |
2436 | break; \ | |
2437 | case 1: \ | |
2438 | fputs (qi_name[REGNO (X)], FILE); \ | |
2439 | break; \ | |
2440 | } \ | |
2441 | } while (0) | |
2442 | ||
c98f8742 JVA |
2443 | /* Routines in libgcc that return floats must return them in an fp reg, |
2444 | just as other functions do which return such values. | |
2445 | These macros make that happen. */ | |
2446 | ||
2447 | #define FLOAT_VALUE_TYPE float | |
2448 | #define INTIFY(FLOATVAL) FLOATVAL | |
2449 | ||
c98f8742 JVA |
2450 | /* a letter which is not needed by the normal asm syntax, which |
2451 | we can use for operand syntax in the extended asm */ | |
2452 | ||
2453 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 2454 | #define RET return "" |
f64cecad | 2455 | #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx)) |
d4ba09c0 | 2456 | \f |
e075ae69 RH |
2457 | /* Define the codes that are matched by predicates in i386.c. */ |
2458 | ||
2459 | #define PREDICATE_CODES \ | |
2460 | {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ | |
2247f6ed JH |
2461 | {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ |
2462 | LABEL_REF, SUBREG, REG, MEM}}, \ | |
e075ae69 RH |
2463 | {"pic_symbolic_operand", {CONST}}, \ |
2464 | {"call_insn_operand", {MEM}}, \ | |
e075ae69 RH |
2465 | {"constant_call_address_operand", {MEM}}, \ |
2466 | {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \ | |
2467 | {"const1_operand", {CONST_INT}}, \ | |
2468 | {"const248_operand", {CONST_INT}}, \ | |
2469 | {"incdec_operand", {CONST_INT}}, \ | |
2470 | {"reg_no_sp_operand", {SUBREG, REG}}, \ | |
2c5a510c RH |
2471 | {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \ |
2472 | SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \ | |
2473 | {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \ | |
e075ae69 RH |
2474 | {"q_regs_operand", {SUBREG, REG}}, \ |
2475 | {"non_q_regs_operand", {SUBREG, REG}}, \ | |
2476 | {"no_comparison_operator", {EQ, NE, LT, GE, LTU, GTU, LEU, GEU}}, \ | |
2477 | {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU}}, \ | |
2478 | {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \ | |
2479 | {"ext_register_operand", {SUBREG, REG}}, \ | |
2480 | {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \ | |
2481 | {"mult_operator", {MULT}}, \ | |
2482 | {"div_operator", {DIV}}, \ | |
2483 | {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \ | |
2484 | UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \ | |
2485 | UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \ | |
2486 | LSHIFTRT, ROTATERT}}, \ | |
e9e80858 | 2487 | {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \ |
e075ae69 RH |
2488 | {"memory_displacement_operand", {MEM}}, \ |
2489 | {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ | |
6343a50e ZW |
2490 | LABEL_REF, SUBREG, REG, MEM, AND}}, \ |
2491 | {"long_memory_operand", {MEM}}, | |
c76aab11 RH |
2492 | |
2493 | /* A list of predicates that do special things with modes, and so | |
2494 | should not elicit warnings for VOIDmode match_operand. */ | |
2495 | ||
2496 | #define SPECIAL_MODE_PREDICATES \ | |
2497 | "ext_register_operand", | |
c98f8742 | 2498 | \f |
f5316dfe | 2499 | /* Variables in i386.c */ |
9c23aa47 ZW |
2500 | extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */ |
2501 | extern const char *ix86_arch_string; /* for -march=<xxx> */ | |
e075ae69 RH |
2502 | extern const char *ix86_reg_alloc_order; /* register allocation order */ |
2503 | extern const char *ix86_regparm_string; /* # registers to use to pass args */ | |
2504 | extern const char *ix86_align_loops_string; /* power of two alignment for loops */ | |
2505 | extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */ | |
2506 | extern const char *ix86_align_funcs_string; /* power of two alignment for functions */ | |
2507 | extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */ | |
2508 | extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */ | |
2509 | extern int ix86_regparm; /* ix86_regparm_string as a number */ | |
2510 | extern int ix86_align_loops; /* power of two alignment for loops */ | |
2511 | extern int ix86_align_jumps; /* power of two alignment for non-loop jumps */ | |
2512 | extern int ix86_align_funcs; /* power of two alignment for functions */ | |
2513 | extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */ | |
2514 | extern int ix86_branch_cost; /* values 1-5: see jump.c */ | |
2515 | extern const char * const hi_reg_name[]; /* names for 16 bit regs */ | |
2516 | extern const char * const qi_reg_name[]; /* names for 8 bit regs (low) */ | |
2517 | extern const char * const qi_high_reg_name[]; /* names for 8 bit regs (high) */ | |
2518 | extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */ | |
2519 | extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */ | |
2520 | extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */ | |
3b3c6a3f | 2521 | \f |
c98f8742 JVA |
2522 | /* |
2523 | Local variables: | |
2524 | version-control: t | |
2525 | End: | |
2526 | */ |