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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
5624e564 | 2 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
90922d36 | 42 | #define TARGET_64BIT TARGET_ISA_64BIT |
bf7b5747 | 43 | #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) |
90922d36 | 44 | #define TARGET_MMX TARGET_ISA_MMX |
bf7b5747 | 45 | #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) |
90922d36 | 46 | #define TARGET_3DNOW TARGET_ISA_3DNOW |
bf7b5747 | 47 | #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) |
90922d36 | 48 | #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A |
bf7b5747 | 49 | #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) |
90922d36 | 50 | #define TARGET_SSE TARGET_ISA_SSE |
bf7b5747 | 51 | #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) |
90922d36 | 52 | #define TARGET_SSE2 TARGET_ISA_SSE2 |
bf7b5747 | 53 | #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) |
90922d36 | 54 | #define TARGET_SSE3 TARGET_ISA_SSE3 |
bf7b5747 | 55 | #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) |
90922d36 | 56 | #define TARGET_SSSE3 TARGET_ISA_SSSE3 |
bf7b5747 | 57 | #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) |
90922d36 | 58 | #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 |
bf7b5747 | 59 | #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) |
90922d36 | 60 | #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 |
bf7b5747 | 61 | #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) |
90922d36 | 62 | #define TARGET_AVX TARGET_ISA_AVX |
bf7b5747 | 63 | #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) |
90922d36 | 64 | #define TARGET_AVX2 TARGET_ISA_AVX2 |
bf7b5747 | 65 | #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) |
cb610367 UB |
66 | #define TARGET_AVX512F TARGET_ISA_AVX512F |
67 | #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
68 | #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
69 | #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
70 | #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
71 | #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
72 | #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
73 | #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
07165dd7 AI |
74 | #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ |
75 | #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
b525d943 AI |
76 | #define TARGET_AVX512BW TARGET_ISA_AVX512BW |
77 | #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
f4af595f AI |
78 | #define TARGET_AVX512VL TARGET_ISA_AVX512VL |
79 | #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
3dcc8af5 IT |
80 | #define TARGET_AVX512VBMI TARGET_ISA_AVX512VBMI |
81 | #define TARGET_AVX512VBMI_P(x) TARGET_ISA_AVX512VBMI_P(x) | |
4190ea38 IT |
82 | #define TARGET_AVX512IFMA TARGET_ISA_AVX512IFMA |
83 | #define TARGET_AVX512IFMA_P(x) TARGET_ISA_AVX512IFMA_P(x) | |
90922d36 | 84 | #define TARGET_FMA TARGET_ISA_FMA |
bf7b5747 | 85 | #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) |
90922d36 | 86 | #define TARGET_SSE4A TARGET_ISA_SSE4A |
bf7b5747 | 87 | #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) |
90922d36 | 88 | #define TARGET_FMA4 TARGET_ISA_FMA4 |
bf7b5747 | 89 | #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) |
90922d36 | 90 | #define TARGET_XOP TARGET_ISA_XOP |
bf7b5747 | 91 | #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) |
90922d36 | 92 | #define TARGET_LWP TARGET_ISA_LWP |
bf7b5747 | 93 | #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) |
90922d36 MM |
94 | #define TARGET_ROUND TARGET_ISA_ROUND |
95 | #define TARGET_ABM TARGET_ISA_ABM | |
bf7b5747 | 96 | #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) |
90922d36 | 97 | #define TARGET_BMI TARGET_ISA_BMI |
bf7b5747 | 98 | #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) |
90922d36 | 99 | #define TARGET_BMI2 TARGET_ISA_BMI2 |
bf7b5747 | 100 | #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) |
90922d36 | 101 | #define TARGET_LZCNT TARGET_ISA_LZCNT |
bf7b5747 | 102 | #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) |
90922d36 | 103 | #define TARGET_TBM TARGET_ISA_TBM |
bf7b5747 | 104 | #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) |
90922d36 | 105 | #define TARGET_POPCNT TARGET_ISA_POPCNT |
bf7b5747 | 106 | #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) |
90922d36 | 107 | #define TARGET_SAHF TARGET_ISA_SAHF |
bf7b5747 | 108 | #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) |
90922d36 | 109 | #define TARGET_MOVBE TARGET_ISA_MOVBE |
bf7b5747 | 110 | #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) |
90922d36 | 111 | #define TARGET_CRC32 TARGET_ISA_CRC32 |
bf7b5747 | 112 | #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) |
90922d36 | 113 | #define TARGET_AES TARGET_ISA_AES |
bf7b5747 | 114 | #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) |
c1618f82 AI |
115 | #define TARGET_SHA TARGET_ISA_SHA |
116 | #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
9cdea277 IT |
117 | #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT |
118 | #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
119 | #define TARGET_XSAVEC TARGET_ISA_XSAVEC | |
120 | #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
121 | #define TARGET_XSAVES TARGET_ISA_XSAVES | |
122 | #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
90922d36 | 123 | #define TARGET_PCLMUL TARGET_ISA_PCLMUL |
bf7b5747 | 124 | #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) |
cb610367 UB |
125 | #define TARGET_CMPXCHG16B TARGET_ISA_CX16 |
126 | #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) | |
90922d36 | 127 | #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
bf7b5747 | 128 | #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) |
90922d36 | 129 | #define TARGET_RDRND TARGET_ISA_RDRND |
bf7b5747 | 130 | #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) |
90922d36 | 131 | #define TARGET_F16C TARGET_ISA_F16C |
bf7b5747 | 132 | #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) |
cb610367 UB |
133 | #define TARGET_RTM TARGET_ISA_RTM |
134 | #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
90922d36 | 135 | #define TARGET_HLE TARGET_ISA_HLE |
bf7b5747 | 136 | #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) |
90922d36 | 137 | #define TARGET_RDSEED TARGET_ISA_RDSEED |
bf7b5747 | 138 | #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) |
90922d36 | 139 | #define TARGET_PRFCHW TARGET_ISA_PRFCHW |
bf7b5747 | 140 | #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) |
90922d36 | 141 | #define TARGET_ADX TARGET_ISA_ADX |
bf7b5747 | 142 | #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) |
3a0d99bb | 143 | #define TARGET_FXSR TARGET_ISA_FXSR |
bf7b5747 | 144 | #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) |
3a0d99bb | 145 | #define TARGET_XSAVE TARGET_ISA_XSAVE |
bf7b5747 | 146 | #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) |
3a0d99bb | 147 | #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT |
bf7b5747 | 148 | #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) |
43b3f52f IT |
149 | #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 |
150 | #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
d5e254e1 IE |
151 | #define TARGET_MPX TARGET_ISA_MPX |
152 | #define TARGET_MPX_P(x) TARGET_ISA_MPX_P(x) | |
36e9b73e IT |
153 | #define TARGET_PCOMMIT TARGET_ISA_PCOMMIT |
154 | #define TARGET_PCOMMIT_P(x) TARGET_ISA_PCOMMIT_P(x) | |
9c3bca11 IT |
155 | #define TARGET_CLWB TARGET_ISA_CLWB |
156 | #define TARGET_CLWB_P(x) TARGET_ISA_CLWB_P(x) | |
500a08b2 VK |
157 | #define TARGET_MWAITX TARGET_ISA_MWAITX |
158 | #define TARGET_MWAITX_P(x) TARGET_ISA_MWAITX_P(x) | |
ab442df7 | 159 | |
90922d36 | 160 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 161 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
90922d36 | 162 | #define TARGET_X32 TARGET_ABI_X32 |
bf7b5747 | 163 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) |
d5d618b5 L |
164 | #define TARGET_16BIT TARGET_CODE16 |
165 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
04e1d06b | 166 | |
cbf2e4d4 HJ |
167 | /* SSE4.1 defines round instructions */ |
168 | #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 | |
90922d36 | 169 | #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) |
0a1c5e55 | 170 | |
26b5109f RS |
171 | #include "config/vxworks-dummy.h" |
172 | ||
7eb68c06 | 173 | #include "config/i386/i386-opts.h" |
ccf8e764 | 174 | |
c69fa2d4 | 175 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 176 | |
8c996513 JH |
177 | /* Specify what algorithm to use for stringops on known size. |
178 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
179 | known at compile time or estimated via feedback, the SIZE array | |
180 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 181 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
182 | When NOALIGN is true the code guaranting the alignment of the memory |
183 | block is skipped. | |
184 | ||
8c996513 | 185 | For example initializer: |
4f3f76e6 | 186 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 187 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 188 | be used otherwise. */ |
8c996513 JH |
189 | struct stringop_algs |
190 | { | |
191 | const enum stringop_alg unknown_size; | |
192 | const struct stringop_strategy { | |
193 | const int max; | |
194 | const enum stringop_alg alg; | |
340ef734 | 195 | int noalign; |
c69fa2d4 | 196 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
197 | }; |
198 | ||
d4ba09c0 SC |
199 | /* Define the specific costs for a given cpu */ |
200 | ||
201 | struct processor_costs { | |
8b60264b KG |
202 | const int add; /* cost of an add instruction */ |
203 | const int lea; /* cost of a lea instruction */ | |
204 | const int shift_var; /* variable shift costs */ | |
205 | const int shift_const; /* constant shift costs */ | |
f676971a | 206 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 207 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 208 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 209 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 210 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
211 | int movsx; /* The cost of movsx operation. */ |
212 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
213 | const int large_insn; /* insns larger than this cost more */ |
214 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 215 | memory-to-memory move insns. */ |
8b60264b KG |
216 | const int movzbl_load; /* cost of loading using movzbl */ |
217 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
218 | in QImode, HImode and SImode relative |
219 | to reg-reg move (2). */ | |
8b60264b | 220 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 221 | in QImode, HImode and SImode */ |
8b60264b KG |
222 | const int fp_move; /* cost of reg,reg fld/fst */ |
223 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 224 | in SFmode, DFmode and XFmode */ |
8b60264b | 225 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 226 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
227 | const int mmx_move; /* cost of moving MMX register. */ |
228 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 229 | in SImode and DImode */ |
8b60264b | 230 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 231 | in SImode and DImode */ |
8b60264b KG |
232 | const int sse_move; /* cost of moving SSE register. */ |
233 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 234 | in SImode, DImode and TImode*/ |
8b60264b | 235 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 236 | in SImode, DImode and TImode*/ |
8b60264b | 237 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 238 | integer and vice versa. */ |
46cb0441 ZD |
239 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
240 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
241 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
242 | const int simultaneous_prefetches; /* number of parallel prefetch | |
243 | operations. */ | |
4977bab6 | 244 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
245 | const int fadd; /* cost of FADD and FSUB instructions. */ |
246 | const int fmul; /* cost of FMUL instruction. */ | |
247 | const int fdiv; /* cost of FDIV instruction. */ | |
248 | const int fabs; /* cost of FABS instruction. */ | |
249 | const int fchs; /* cost of FCHS instruction. */ | |
250 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 251 | /* Specify what algorithm |
bee51209 | 252 | to use for stringops on unknown size. */ |
ad83025e | 253 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
254 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
255 | load and store. */ | |
256 | const int scalar_load_cost; /* Cost of scalar load. */ | |
257 | const int scalar_store_cost; /* Cost of scalar store. */ | |
258 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
259 | load, store, vector-to-scalar and | |
260 | scalar-to-vector operation. */ | |
261 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
262 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 263 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
264 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
265 | const int vec_store_cost; /* Cost of vector store. */ | |
266 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
267 | cost model. */ | |
268 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
269 | vectorizer cost model. */ | |
d4ba09c0 SC |
270 | }; |
271 | ||
8b60264b | 272 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
273 | extern const struct processor_costs ix86_size_cost; |
274 | ||
275 | #define ix86_cur_cost() \ | |
276 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 277 | |
c98f8742 JVA |
278 | /* Macros used in the machine description to test the flags. */ |
279 | ||
b97de419 | 280 | /* configure can arrange to change it. */ |
e075ae69 | 281 | |
35b528be | 282 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 283 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 284 | #endif |
35b528be | 285 | |
004d3859 GK |
286 | #ifndef TARGET_FPMATH_DEFAULT |
287 | #define TARGET_FPMATH_DEFAULT \ | |
288 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
289 | #endif | |
290 | ||
bf7b5747 ST |
291 | #ifndef TARGET_FPMATH_DEFAULT_P |
292 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
293 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
294 | #endif | |
295 | ||
6ac49599 | 296 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
bf7b5747 | 297 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x) |
b08de47e | 298 | |
5791cc29 JT |
299 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
300 | compile-time constant. */ | |
301 | #ifdef IN_LIBGCC2 | |
6ac49599 | 302 | #undef TARGET_64BIT |
5791cc29 JT |
303 | #ifdef __x86_64__ |
304 | #define TARGET_64BIT 1 | |
305 | #else | |
306 | #define TARGET_64BIT 0 | |
307 | #endif | |
308 | #else | |
6ac49599 RS |
309 | #ifndef TARGET_BI_ARCH |
310 | #undef TARGET_64BIT | |
e49080ec | 311 | #undef TARGET_64BIT_P |
67adf6a9 | 312 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 313 | #define TARGET_64BIT 1 |
e49080ec | 314 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
315 | #else |
316 | #define TARGET_64BIT 0 | |
e49080ec | 317 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
318 | #endif |
319 | #endif | |
5791cc29 | 320 | #endif |
25f94bb5 | 321 | |
750054a2 CT |
322 | #define HAS_LONG_COND_BRANCH 1 |
323 | #define HAS_LONG_UNCOND_BRANCH 1 | |
324 | ||
9e555526 RH |
325 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
326 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
327 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
328 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 329 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
330 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
331 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
332 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
333 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 334 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 335 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
340ef734 | 336 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d3c11974 L |
337 | #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) |
338 | #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
3a579e09 | 339 | #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) |
d3c11974 L |
340 | #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) |
341 | #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
52747219 | 342 | #define TARGET_KNL (ix86_tune == PROCESSOR_KNL) |
06caf59d | 343 | #define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512) |
9a7f94d7 | 344 | #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
9d532162 | 345 | #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) |
21efb4d4 | 346 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
1133125e | 347 | #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
4d652a18 | 348 | #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
eb2f2b44 | 349 | #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) |
ed97ad47 | 350 | #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) |
14b52538 | 351 | #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
e32bfc16 | 352 | #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
a269a03c | 353 | |
80fd744f RH |
354 | /* Feature tests against the various tunings. */ |
355 | enum ix86_tune_indices { | |
4b8bc035 | 356 | #undef DEF_TUNE |
3ad20bd4 | 357 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
358 | #include "x86-tune.def" |
359 | #undef DEF_TUNE | |
360 | X86_TUNE_LAST | |
80fd744f RH |
361 | }; |
362 | ||
ab442df7 | 363 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
364 | |
365 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
366 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
367 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
368 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 369 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
370 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
371 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
372 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
373 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
374 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
375 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
376 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
377 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
378 | #define TARGET_LCP_STALL \ |
379 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
380 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
381 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
382 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
383 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
384 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
385 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
386 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
387 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
388 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
389 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
390 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
5783ad0e UB |
391 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
392 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
393 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
394 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
395 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
396 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
397 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
398 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
399 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
400 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
401 | #define TARGET_INTEGER_DFMODE_MOVES \ |
402 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
403 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
404 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
405 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
406 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
1133125e HJ |
407 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
408 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
409 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
410 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
411 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
412 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
413 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
414 | #define TARGET_SSE_TYPELESS_STORES \ | |
415 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
416 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
417 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
418 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
419 | #define TARGET_PROLOGUE_USING_MOVE \ | |
420 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
421 | #define TARGET_EPILOGUE_USING_MOVE \ | |
422 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
423 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
424 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
425 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
426 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
427 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
428 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
429 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 430 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
431 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
432 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
433 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
434 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
435 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
436 | #define TARGET_PAD_SHORT_FUNCTION \ |
437 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
438 | #define TARGET_EXT_80387_CONSTANTS \ |
439 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
440 | #define TARGET_AVOID_VECTOR_DECODE \ |
441 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
442 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
443 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
444 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
445 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
446 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
447 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
448 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
449 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
450 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
451 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
452 | #define TARGET_USE_VECTOR_CONVERTS \ |
453 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
454 | #define TARGET_SLOW_PSHUFB \ |
455 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
f7917029 ES |
456 | #define TARGET_VECTOR_PARALLEL_EXECUTION \ |
457 | ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION] | |
0dc41f28 WM |
458 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
459 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
460 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
461 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 462 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
463 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
464 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
465 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
466 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
467 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
468 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 469 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
470 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
471 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
e72eba85 L |
472 | #define TARGET_VECTORIZE_DOUBLE \ |
473 | ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] | |
5d0878e7 JH |
474 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
475 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
5c0d88e6 CF |
476 | #define TARGET_AVX128_OPTIMAL \ |
477 | ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] | |
df7b0cc4 EI |
478 | #define TARGET_REASSOC_INT_TO_PARALLEL \ |
479 | ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] | |
480 | #define TARGET_REASSOC_FP_TO_PARALLEL \ | |
481 | ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] | |
55a2c322 VM |
482 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
483 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
484 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
485 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 486 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 487 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
488 | #define TARGET_ADJUST_UNROLL \ |
489 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
374f5bf8 UB |
490 | #define TARGET_AVOID_FALSE_DEP_FOR_BMI \ |
491 | ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] | |
df7b0cc4 | 492 | |
80fd744f RH |
493 | /* Feature tests against the various architecture variations. */ |
494 | enum ix86_arch_indices { | |
cef31f9c | 495 | X86_ARCH_CMOV, |
80fd744f RH |
496 | X86_ARCH_CMPXCHG, |
497 | X86_ARCH_CMPXCHG8B, | |
498 | X86_ARCH_XADD, | |
499 | X86_ARCH_BSWAP, | |
500 | ||
501 | X86_ARCH_LAST | |
502 | }; | |
4f3f76e6 | 503 | |
ab442df7 | 504 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 505 | |
cef31f9c | 506 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
507 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
508 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
509 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
510 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
511 | ||
cef31f9c UB |
512 | /* For sane SSE instruction set generation we need fcomi instruction. |
513 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
514 | expands to a sequence that includes conditional move. */ | |
515 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
516 | ||
80fd744f RH |
517 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
518 | ||
cb261eb7 | 519 | extern unsigned char x86_prefetch_sse; |
80fd744f RH |
520 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
521 | ||
80fd744f RH |
522 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
523 | ||
524 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
525 | #define TARGET_MIX_SSE_I387 \ | |
526 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
527 | ||
5fa578f0 UB |
528 | #define TARGET_HARD_SF_REGS (TARGET_80387 || TARGET_MMX || TARGET_SSE) |
529 | #define TARGET_HARD_DF_REGS (TARGET_80387 || TARGET_SSE) | |
530 | #define TARGET_HARD_XF_REGS (TARGET_80387) | |
531 | ||
80fd744f RH |
532 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
533 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
534 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 535 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 536 | |
67adf6a9 RH |
537 | #ifndef TARGET_64BIT_DEFAULT |
538 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 539 | #endif |
74dc3e94 RH |
540 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
541 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
542 | #endif | |
25f94bb5 | 543 | |
e0ea8797 AH |
544 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
545 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
546 | ||
79f5e442 ZD |
547 | /* Fence to use after loop using storent. */ |
548 | ||
549 | extern tree x86_mfence; | |
550 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
551 | ||
0ed4a390 JL |
552 | /* Once GDB has been enhanced to deal with functions without frame |
553 | pointers, we can change this to allow for elimination of | |
554 | the frame pointer in leaf functions. */ | |
555 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 556 | |
0a1c5e55 UB |
557 | /* Extra bits to force. */ |
558 | #define TARGET_SUBTARGET_DEFAULT 0 | |
559 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
560 | ||
561 | /* Extra bits to force on w/ 32-bit mode. */ | |
562 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
563 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
564 | ||
ccf8e764 RH |
565 | /* Extra bits to force on w/ 64-bit mode. */ |
566 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 567 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 568 | |
fee3eacd IS |
569 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
570 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 571 | #define TARGET_MACHO 0 |
9005471b | 572 | #define TARGET_MACHO_BRANCH_ISLANDS 0 |
fee3eacd IS |
573 | #define MACHOPIC_ATT_STUB 0 |
574 | /* (b) Macros defined in config/darwin.h */ | |
575 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
576 | #define MACHOPIC_INDIRECT 0 | |
577 | #define MACHOPIC_PURE 0 | |
9005471b | 578 | |
5a579c3b LE |
579 | /* For the RDOS */ |
580 | #define TARGET_RDOS 0 | |
581 | ||
9005471b | 582 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
583 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
584 | ||
6510e8bb KT |
585 | /* For the Windows 32-bit ABI. */ |
586 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
587 | ||
f81c9774 RH |
588 | /* This is re-defined by cygming.h. */ |
589 | #define TARGET_SEH 0 | |
590 | ||
a3d7ab92 KT |
591 | /* This is re-defined by cygming.h. */ |
592 | #define TARGET_PECOFF 0 | |
593 | ||
51212b32 | 594 | /* The default abi used by target. */ |
7c800926 | 595 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 596 | |
b8b3f0ca LE |
597 | /* The default TLS segment register used by target. */ |
598 | #define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS) | |
599 | ||
cc69336f RH |
600 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
601 | with the rounding mode forced to 53 bits. */ | |
602 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
603 | ||
682cd442 GK |
604 | /* -march=native handling only makes sense with compiler running on |
605 | an x86 or x86_64 chip. If changing this condition, also change | |
606 | the condition in driver-i386.c. */ | |
607 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
608 | /* In driver-i386.c. */ |
609 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
610 | #define EXTRA_SPEC_FUNCTIONS \ | |
611 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 612 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
613 | #endif |
614 | ||
8981c15b JM |
615 | #if TARGET_64BIT_DEFAULT |
616 | #define OPT_ARCH64 "!m32" | |
617 | #define OPT_ARCH32 "m32" | |
618 | #else | |
f0ea7581 L |
619 | #define OPT_ARCH64 "m64|mx32" |
620 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
621 | #endif |
622 | ||
1cba2b96 EC |
623 | /* Support for configure-time defaults of some command line options. |
624 | The order here is important so that -march doesn't squash the | |
625 | tune or cpu values. */ | |
ce998900 | 626 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 627 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
628 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
629 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 630 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
631 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
632 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
633 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
634 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
635 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 636 | |
241e1a89 SC |
637 | /* Specs for the compiler proper */ |
638 | ||
628714d8 | 639 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 640 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 641 | |
682cd442 | 642 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
643 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
644 | #else | |
645 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
96f5b137 L |
646 | "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
647 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ | |
648 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" | |
fa959ce4 | 649 | #endif |
241e1a89 | 650 | #endif |
c98f8742 | 651 | \f |
30efe578 | 652 | /* Target CPU builtins. */ |
ab442df7 MM |
653 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
654 | ||
655 | /* Target Pragmas. */ | |
656 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 657 | |
628714d8 | 658 | #ifndef CC1_SPEC |
8015b78d | 659 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
660 | #endif |
661 | ||
662 | /* This macro defines names of additional specifications to put in the | |
663 | specs that can be used in various specifications like CC1_SPEC. Its | |
664 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
665 | |
666 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 667 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
668 | program. |
669 | ||
670 | Do not define this macro if it does not need to do anything. */ | |
671 | ||
672 | #ifndef SUBTARGET_EXTRA_SPECS | |
673 | #define SUBTARGET_EXTRA_SPECS | |
674 | #endif | |
675 | ||
676 | #define EXTRA_SPECS \ | |
628714d8 | 677 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
678 | SUBTARGET_EXTRA_SPECS |
679 | \f | |
ce998900 | 680 | |
d57a4b98 RH |
681 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
682 | FPU, assume that the fpcw is set to extended precision; when using | |
683 | only SSE, rounding is correct; when using both SSE and the FPU, | |
684 | the rounding precision is indeterminate, since either may be chosen | |
685 | apparently at random. */ | |
686 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 687 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 688 | |
8ce94e44 JM |
689 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
690 | SFmode, DFmode and XFmode) in the current excess precision | |
691 | configuration. */ | |
692 | #define X87_ENABLE_ARITH(MODE) \ | |
693 | (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) | |
694 | ||
695 | /* Likewise, whether to allow direct conversions from integer mode | |
696 | IMODE (HImode, SImode or DImode) to MODE. */ | |
697 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
698 | (flag_excess_precision == EXCESS_PRECISION_FAST \ | |
699 | || (MODE) == XFmode \ | |
700 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
701 | || (IMODE) == HImode) | |
702 | ||
979c67a5 UB |
703 | /* target machine storage layout */ |
704 | ||
65d9c0ab JH |
705 | #define SHORT_TYPE_SIZE 16 |
706 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
707 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
708 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 709 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 710 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 711 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
712 | #define LONG_DOUBLE_TYPE_SIZE \ |
713 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 714 | |
c637141a | 715 | #define WIDEST_HARDWARE_FP_SIZE 80 |
65d9c0ab | 716 | |
67adf6a9 | 717 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 718 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
719 | #else |
720 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
721 | #endif |
722 | ||
c98f8742 JVA |
723 | /* Define this if most significant byte of a word is the lowest numbered. */ |
724 | /* That is true on the 80386. */ | |
725 | ||
726 | #define BITS_BIG_ENDIAN 0 | |
727 | ||
728 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
729 | /* That is not true on the 80386. */ | |
730 | #define BYTES_BIG_ENDIAN 0 | |
731 | ||
732 | /* Define this if most significant word of a multiword number is the lowest | |
733 | numbered. */ | |
734 | /* Not true for 80386 */ | |
735 | #define WORDS_BIG_ENDIAN 0 | |
736 | ||
c98f8742 | 737 | /* Width of a word, in units (bytes). */ |
4ae8027b | 738 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
739 | |
740 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
741 | #define MIN_UNITS_PER_WORD 4 |
742 | #endif | |
c98f8742 | 743 | |
c98f8742 | 744 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 745 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 746 | |
e075ae69 | 747 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
4ae8027b | 748 | #define STACK_BOUNDARY \ |
51212b32 | 749 | (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 750 | |
2e3f842f L |
751 | /* Stack boundary of the main function guaranteed by OS. */ |
752 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
753 | ||
de1132d1 | 754 | /* Minimum stack boundary. */ |
5bfb2af2 | 755 | #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32) |
2e3f842f | 756 | |
d1f87653 | 757 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 758 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 759 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 760 | |
de1132d1 | 761 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
762 | both 32bit and 64bit, to support codes that need 128 bit stack |
763 | alignment for SSE instructions, but can't realign the stack. */ | |
d9063947 L |
764 | #define PREFERRED_STACK_BOUNDARY_DEFAULT \ |
765 | (TARGET_IAMCU ? MIN_STACK_BOUNDARY : 128) | |
2e3f842f L |
766 | |
767 | /* 1 if -mstackrealign should be turned on by default. It will | |
768 | generate an alternate prologue and epilogue that realigns the | |
769 | runtime stack if nessary. This supports mixing codes that keep a | |
770 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 771 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
772 | #define STACK_REALIGN_DEFAULT 0 |
773 | ||
774 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
775 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 776 | |
a2851b75 TG |
777 | /* According to Windows x64 software convention, the maximum stack allocatable |
778 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
779 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
780 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
781 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
782 | prologue. | |
783 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 784 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
785 | regs, then save them, and then allocate the remaining. There is no SEH |
786 | unwind info for this later allocation. */ | |
787 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
788 | ||
ebff937c SH |
789 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
790 | mandatory for the 64-bit ABI, and may or may not be true for other | |
791 | operating systems. */ | |
792 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
793 | ||
f963b5d9 RS |
794 | /* Minimum allocation boundary for the code of a function. */ |
795 | #define FUNCTION_BOUNDARY 8 | |
796 | ||
797 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
798 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 799 | |
c98f8742 JVA |
800 | /* Minimum size in bits of the largest boundary to which any |
801 | and all fundamental data types supported by the hardware | |
802 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 803 | rounder than this. |
fce5a9f2 | 804 | |
d1f87653 | 805 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
6d2b7199 BS |
806 | and Pentium Pro XFmode values at 128 bit boundaries. |
807 | ||
808 | When increasing the maximum, also update | |
809 | TARGET_ABSOLUTE_BIGGEST_ALIGNMENT. */ | |
17f24ff0 | 810 | |
3f97cb0b | 811 | #define BIGGEST_ALIGNMENT \ |
d9063947 | 812 | (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : (TARGET_IAMCU ? 32 : 128))) |
17f24ff0 | 813 | |
2e3f842f L |
814 | /* Maximum stack alignment. */ |
815 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
816 | ||
6e4f1168 L |
817 | /* Alignment value for attribute ((aligned)). It is a constant since |
818 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
e9c9e772 | 819 | #define ATTRIBUTE_ALIGNED_VALUE (TARGET_IAMCU ? 32 : 128) |
6e4f1168 | 820 | |
822eda12 | 821 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 822 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 823 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 824 | |
17f24ff0 | 825 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 826 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 827 | -malign-double is set. */ |
e932b21b | 828 | |
e83f3cff RH |
829 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
830 | supports no vector modes, cut out the complexity and fall back | |
831 | on BIGGEST_FIELD_ALIGNMENT. */ | |
832 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
833 | #ifdef __x86_64__ |
834 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
835 | #else | |
e83f3cff | 836 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 837 | #endif |
e83f3cff | 838 | #else |
e932b21b JH |
839 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
840 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 841 | #endif |
c98f8742 | 842 | |
e5e8a8bf | 843 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 844 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
845 | and ALIGN is the alignment that the object would ordinarily have. |
846 | The value of this macro is used instead of that alignment to align | |
847 | the object. | |
848 | ||
849 | If this macro is not defined, then ALIGN is used. | |
850 | ||
851 | The typical use of this macro is to increase alignment for string | |
852 | constants to be word aligned so that `strcpy' calls that copy | |
853 | constants can be done inline. */ | |
854 | ||
d9a5f180 | 855 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 856 | |
8a022443 JW |
857 | /* If defined, a C expression to compute the alignment for a static |
858 | variable. TYPE is the data type, and ALIGN is the alignment that | |
859 | the object would ordinarily have. The value of this macro is used | |
860 | instead of that alignment to align the object. | |
861 | ||
862 | If this macro is not defined, then ALIGN is used. | |
863 | ||
864 | One use of this macro is to increase alignment of medium-size | |
865 | data to make it all fit in fewer cache lines. Another is to | |
866 | cause character arrays to be word-aligned so that `strcpy' calls | |
867 | that copy constants to character arrays can be done inline. */ | |
868 | ||
df8a1d28 JJ |
869 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
870 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
871 | ||
872 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
873 | some alignment increase, instead of optimization only purposes. E.g. | |
874 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
875 | must be aligned to 16 byte boundaries. | |
876 | ||
877 | If this macro is not defined, then ALIGN is used. */ | |
878 | ||
879 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
880 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
881 | |
882 | /* If defined, a C expression to compute the alignment for a local | |
883 | variable. TYPE is the data type, and ALIGN is the alignment that | |
884 | the object would ordinarily have. The value of this macro is used | |
885 | instead of that alignment to align the object. | |
886 | ||
887 | If this macro is not defined, then ALIGN is used. | |
888 | ||
889 | One use of this macro is to increase alignment of medium-size | |
890 | data to make it all fit in fewer cache lines. */ | |
891 | ||
76fe54f0 L |
892 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
893 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
894 | ||
895 | /* If defined, a C expression to compute the alignment for stack slot. | |
896 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
897 | is the alignment that the slot would ordinarily have. The value of | |
898 | this macro is used instead of that alignment to align the slot. | |
899 | ||
900 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
901 | Otherwise, LOCAL_ALIGNMENT will be used. | |
902 | ||
903 | One use of this macro is to set alignment of stack slot to the | |
904 | maximum alignment of all possible modes which the slot may have. */ | |
905 | ||
906 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
907 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 908 | |
9bfaf89d JJ |
909 | /* If defined, a C expression to compute the alignment for a local |
910 | variable DECL. | |
911 | ||
912 | If this macro is not defined, then | |
913 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
914 | ||
915 | One use of this macro is to increase alignment of medium-size | |
916 | data to make it all fit in fewer cache lines. */ | |
917 | ||
918 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
919 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
920 | ||
ae58e548 JJ |
921 | /* If defined, a C expression to compute the minimum required alignment |
922 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
923 | MODE, assuming normal alignment ALIGN. | |
924 | ||
925 | If this macro is not defined, then (ALIGN) will be used. */ | |
926 | ||
927 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
928 | ix86_minimum_alignment (EXP, MODE, ALIGN) | |
929 | ||
9bfaf89d | 930 | |
9cd10576 | 931 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 932 | when given unaligned data. */ |
b4ac57ab | 933 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
934 | |
935 | /* If bit field type is int, don't let it cross an int, | |
936 | and give entire struct the alignment of an int. */ | |
43a88a8c | 937 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 938 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
939 | \f |
940 | /* Standard register usage. */ | |
941 | ||
942 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 943 | for details. */ |
c98f8742 JVA |
944 | |
945 | #define STACK_REGS | |
ce998900 | 946 | |
d9a5f180 | 947 | #define IS_STACK_MODE(MODE) \ |
63001560 UB |
948 | (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ |
949 | || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ | |
b5c82fa1 | 950 | || (MODE) == XFmode) |
c98f8742 JVA |
951 | |
952 | /* Number of actual hardware registers. | |
953 | The hardware registers are assigned numbers for the compiler | |
954 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
955 | All registers that the compiler knows about must be given numbers, | |
956 | even those that are not normally considered general registers. | |
957 | ||
958 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
959 | We number the floating point registers 8-15. | |
960 | Note that registers 0-7 can be accessed as a short or int, | |
961 | while only 0-3 may be used with byte `mov' instructions. | |
962 | ||
963 | Reg 16 does not correspond to any hardware register, but instead | |
964 | appears in the RTL as an argument pointer prior to reload, and is | |
965 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 966 | pointer. */ |
c98f8742 | 967 | |
05416670 | 968 | #define FIRST_PSEUDO_REGISTER FIRST_PSEUDO_REG |
c98f8742 | 969 | |
3073d01c ML |
970 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
971 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
972 | ||
973 | #define DWARF_FRAME_REGISTERS 17 | |
974 | ||
c98f8742 JVA |
975 | /* 1 for registers that have pervasive standard uses |
976 | and are not available for the register allocator. | |
3f3f2124 | 977 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 978 | |
621bc046 UB |
979 | REX registers are disabled for 32bit targets in |
980 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
981 | ||
a7180f70 BS |
982 | #define FIXED_REGISTERS \ |
983 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 984 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
985 | /*arg,flags,fpsr,fpcr,frame*/ \ |
986 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
987 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
988 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 989 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
990 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
991 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 992 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 993 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
994 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
995 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
996 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
997 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
998 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
999 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
d5e254e1 IE |
1000 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
1001 | /* b0, b1, b2, b3*/ \ | |
1002 | 0, 0, 0, 0 } | |
c98f8742 JVA |
1003 | |
1004 | /* 1 for registers not available across function calls. | |
1005 | These must include the FIXED_REGISTERS and also any | |
1006 | registers that can be used without being saved. | |
1007 | The latter must include the registers where values are returned | |
1008 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
1009 | Aside from that, you can include as many other registers as you like. |
1010 | ||
621bc046 UB |
1011 | Value is set to 1 if the register is call used unconditionally. |
1012 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
1013 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
1014 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
1015 | ||
1016 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
1017 | ||
a7180f70 BS |
1018 | #define CALL_USED_REGISTERS \ |
1019 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 1020 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
1021 | /*arg,flags,fpsr,fpcr,frame*/ \ |
1022 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 1023 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 1024 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 1025 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 1026 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1027 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1028 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1029 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1030 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1031 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1032 | 6, 6, 6, 6, 6, 6, 6, 6, \ | |
1033 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1034 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1035 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
d5e254e1 IE |
1036 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
1037 | /* b0, b1, b2, b3*/ \ | |
1038 | 1, 1, 1, 1 } | |
c98f8742 | 1039 | |
3b3c6a3f MM |
1040 | /* Order in which to allocate registers. Each register must be |
1041 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1042 | late and fixed registers last. Note that, in general, we prefer | |
1043 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1044 | available for storage of persistent values. | |
1045 | ||
5a733826 | 1046 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
162f023b | 1047 | so this is just empty initializer for array. */ |
3b3c6a3f | 1048 | |
162f023b JH |
1049 | #define REG_ALLOC_ORDER \ |
1050 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1051 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1052 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
3f97cb0b | 1053 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
d5e254e1 IE |
1054 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, \ |
1055 | 78, 79, 80 } | |
3b3c6a3f | 1056 | |
5a733826 | 1057 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 1058 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 1059 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1060 | |
5a733826 | 1061 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1062 | |
f5316dfe | 1063 | |
7c800926 KT |
1064 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1065 | ||
c98f8742 JVA |
1066 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1067 | to hold something of mode MODE. | |
1068 | This is ordinarily the length in words of a value of mode MODE | |
1069 | but can be less for certain modes in special long registers. | |
1070 | ||
fce5a9f2 | 1071 | Actually there are no two word move instructions for consecutive |
c98f8742 | 1072 | registers. And only registers 0-3 may have mov byte instructions |
63001560 | 1073 | applied to them. */ |
c98f8742 | 1074 | |
ce998900 | 1075 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
d5e254e1 IE |
1076 | (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
1077 | || MASK_REGNO_P (REGNO) || BND_REGNO_P (REGNO) \ | |
92d0fb09 | 1078 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ |
f8a1ebc6 | 1079 | : ((MODE) == XFmode \ |
92d0fb09 | 1080 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1081 | : (MODE) == XCmode \ |
92d0fb09 | 1082 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1083 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1084 | |
8521c414 JM |
1085 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
1086 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
66aaf16f | 1087 | ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
8521c414 JM |
1088 | ? 0 \ |
1089 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
1090 | : 0) | |
1091 | ||
1092 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1093 | ||
95879c72 L |
1094 | #define VALID_AVX256_REG_MODE(MODE) \ |
1095 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb JJ |
1096 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
1097 | || (MODE) == V4DFmode) | |
95879c72 | 1098 | |
4ac005ba | 1099 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
ff97910d VY |
1100 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) |
1101 | ||
3f97cb0b AI |
1102 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
1103 | ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
1104 | || (MODE) == SFmode) | |
1105 | ||
1106 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1107 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 AI |
1108 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
1109 | || (MODE) == V4TImode) | |
1110 | ||
05416670 | 1111 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ |
9e4a4dd6 AI |
1112 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ |
1113 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode) | |
3f97cb0b | 1114 | |
ce998900 UB |
1115 | #define VALID_SSE2_REG_MODE(MODE) \ |
1116 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1117 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1118 | |
d9a5f180 | 1119 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1120 | ((MODE) == V1TImode || (MODE) == TImode \ |
1121 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
ce998900 | 1122 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1123 | |
47f339cf | 1124 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1125 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1126 | |
d9a5f180 | 1127 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1128 | ((MODE == V1DImode) || (MODE) == DImode \ |
1129 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1130 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1131 | |
05416670 UB |
1132 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1133 | ||
1134 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) | |
1135 | ||
d5e254e1 IE |
1136 | #define VALID_BND_REG_MODE(MODE) \ |
1137 | (TARGET_64BIT ? (MODE) == BND64mode : (MODE) == BND32mode) | |
1138 | ||
ce998900 UB |
1139 | #define VALID_DFP_MODE_P(MODE) \ |
1140 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1141 | |
d9a5f180 | 1142 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1143 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1144 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1145 | |
d9a5f180 | 1146 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1147 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1148 | || (MODE) == DImode \ | |
1149 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1150 | || (MODE) == CDImode \ | |
1151 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1152 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1153 | |
822eda12 | 1154 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1155 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1156 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1157 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1158 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1159 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1160 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1161 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1162 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
1163 | || (MODE) == V16SFmode) | |
822eda12 | 1164 | |
05416670 UB |
1165 | #define X87_FLOAT_MODE_P(MODE) \ |
1166 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
85a77221 | 1167 | |
05416670 UB |
1168 | #define SSE_FLOAT_MODE_P(MODE) \ |
1169 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
1170 | ||
1171 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ | |
1172 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1173 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
9e4a4dd6 | 1174 | |
e075ae69 | 1175 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1176 | |
a946dd00 | 1177 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1178 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1179 | |
1180 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1181 | when one has mode MODE1 and one has mode MODE2. | |
1182 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1183 | for any hard reg, then this must be 0 for correct output. */ | |
1184 | ||
c1c5b5e3 | 1185 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 1186 | |
ff25ef99 ZD |
1187 | /* It is possible to write patterns to move flags; but until someone |
1188 | does it, */ | |
1189 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1190 | |
e075ae69 | 1191 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1192 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1193 | |
787dc842 JH |
1194 | Kill any attempts to combine saving of modes. */ |
1195 | ||
d9a5f180 GS |
1196 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1197 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1198 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1199 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
85a77221 AI |
1200 | : (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \ |
1201 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
1202 | : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \ | |
1203 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
d2836273 | 1204 | : (MODE)) |
ce998900 | 1205 | |
51ba747a RH |
1206 | /* The only ABI that saves SSE registers across calls is Win64 (thus no |
1207 | need to check the current ABI here), and with AVX enabled Win64 only | |
1208 | guarantees that the low 16 bytes are saved. */ | |
1209 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
1210 | (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) | |
1211 | ||
c98f8742 JVA |
1212 | /* Specify the registers used for certain standard purposes. |
1213 | The values of these macros are register numbers. */ | |
1214 | ||
1215 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1216 | register. The ordinary mov instructions won't work */ | |
1217 | /* #define PC_REGNUM */ | |
1218 | ||
05416670 UB |
1219 | /* Base register for access to arguments of the function. */ |
1220 | #define ARG_POINTER_REGNUM ARGP_REG | |
1221 | ||
c98f8742 | 1222 | /* Register to use for pushing function arguments. */ |
05416670 | 1223 | #define STACK_POINTER_REGNUM SP_REG |
c98f8742 JVA |
1224 | |
1225 | /* Base register for access to local variables of the function. */ | |
05416670 UB |
1226 | #define FRAME_POINTER_REGNUM FRAME_REG |
1227 | #define HARD_FRAME_POINTER_REGNUM BP_REG | |
564d80f4 | 1228 | |
05416670 UB |
1229 | #define FIRST_INT_REG AX_REG |
1230 | #define LAST_INT_REG SP_REG | |
c98f8742 | 1231 | |
05416670 UB |
1232 | #define FIRST_QI_REG AX_REG |
1233 | #define LAST_QI_REG BX_REG | |
c98f8742 JVA |
1234 | |
1235 | /* First & last stack-like regs */ | |
05416670 UB |
1236 | #define FIRST_STACK_REG ST0_REG |
1237 | #define LAST_STACK_REG ST7_REG | |
c98f8742 | 1238 | |
05416670 UB |
1239 | #define FIRST_SSE_REG XMM0_REG |
1240 | #define LAST_SSE_REG XMM7_REG | |
fce5a9f2 | 1241 | |
05416670 UB |
1242 | #define FIRST_MMX_REG MM0_REG |
1243 | #define LAST_MMX_REG MM7_REG | |
a7180f70 | 1244 | |
05416670 UB |
1245 | #define FIRST_REX_INT_REG R8_REG |
1246 | #define LAST_REX_INT_REG R15_REG | |
3f3f2124 | 1247 | |
05416670 UB |
1248 | #define FIRST_REX_SSE_REG XMM8_REG |
1249 | #define LAST_REX_SSE_REG XMM15_REG | |
3f3f2124 | 1250 | |
05416670 UB |
1251 | #define FIRST_EXT_REX_SSE_REG XMM16_REG |
1252 | #define LAST_EXT_REX_SSE_REG XMM31_REG | |
3f97cb0b | 1253 | |
05416670 UB |
1254 | #define FIRST_MASK_REG MASK0_REG |
1255 | #define LAST_MASK_REG MASK7_REG | |
85a77221 | 1256 | |
05416670 UB |
1257 | #define FIRST_BND_REG BND0_REG |
1258 | #define LAST_BND_REG BND3_REG | |
d5e254e1 | 1259 | |
aabcd309 | 1260 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1261 | requiring a frame pointer. */ |
1262 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1263 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1264 | #endif | |
1265 | ||
1266 | /* Make sure we can access arbitrary call frames. */ | |
1267 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 | 1268 | |
c98f8742 | 1269 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1270 | code access to data items. We don't use PIC pointer for 64bit |
1271 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1272 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1273 | |
1274 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1275 | the pic register when possible. The change is visible after the | |
1276 | prologue has been emitted. */ | |
1277 | ||
e8b5eb25 | 1278 | #define REAL_PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? R15_REG : BX_REG) |
bd09bdeb | 1279 | |
bcb21886 | 1280 | #define PIC_OFFSET_TABLE_REGNUM \ |
d290bb1d IE |
1281 | (ix86_use_pseudo_pic_reg () \ |
1282 | ? (pic_offset_table_rtx \ | |
1283 | ? INVALID_REGNUM \ | |
1284 | : REAL_PIC_OFFSET_TABLE_REGNUM) \ | |
1285 | : INVALID_REGNUM) | |
c98f8742 | 1286 | |
5fc0e5df KW |
1287 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1288 | ||
c51e6d85 | 1289 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1290 | #define MS_AGGREGATE_RETURN 0 |
1291 | ||
61fec9ff | 1292 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1293 | \f |
1294 | /* Define the classes of registers for register constraints in the | |
1295 | machine description. Also define ranges of constants. | |
1296 | ||
1297 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1298 | If there is more than one class, another class must be named NO_REGS | |
1299 | and contain no registers. | |
1300 | ||
1301 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1302 | another name such as ALL_REGS). This is the class of registers | |
1303 | that is allowed by "g" or "r" in a register constraint. | |
1304 | Also, registers outside this class are allocated only when | |
1305 | instructions express preferences for them. | |
1306 | ||
1307 | The classes must be numbered in nondecreasing order; that is, | |
1308 | a larger-numbered class must never be contained completely | |
2e24efd3 AM |
1309 | in a smaller-numbered class. This is why CLOBBERED_REGS class |
1310 | is listed early, even though in 64-bit mode it contains more | |
1311 | registers than just %eax, %ecx, %edx. | |
c98f8742 JVA |
1312 | |
1313 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1314 | class that represents their union. |
1315 | ||
1316 | It might seem that class BREG is unnecessary, since no useful 386 | |
1317 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1318 | and the "b" register constraint is useful in asms for syscalls. |
1319 | ||
03c259ad | 1320 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1321 | |
1322 | enum reg_class | |
1323 | { | |
1324 | NO_REGS, | |
e075ae69 | 1325 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1326 | AD_REGS, /* %eax/%edx for DImode */ |
2e24efd3 | 1327 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
c98f8742 | 1328 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1329 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1330 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1331 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
63001560 UB |
1332 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1333 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1334 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1335 | FLOAT_REGS, | |
06f4e35d | 1336 | SSE_FIRST_REG, |
45392c76 | 1337 | NO_REX_SSE_REGS, |
a7180f70 | 1338 | SSE_REGS, |
3f97cb0b | 1339 | EVEX_SSE_REGS, |
d5e254e1 | 1340 | BND_REGS, |
3f97cb0b | 1341 | ALL_SSE_REGS, |
a7180f70 | 1342 | MMX_REGS, |
446988df JH |
1343 | FP_TOP_SSE_REGS, |
1344 | FP_SECOND_SSE_REGS, | |
1345 | FLOAT_SSE_REGS, | |
1346 | FLOAT_INT_REGS, | |
1347 | INT_SSE_REGS, | |
1348 | FLOAT_INT_SSE_REGS, | |
85a77221 AI |
1349 | MASK_EVEX_REGS, |
1350 | MASK_REGS, | |
c98f8742 JVA |
1351 | ALL_REGS, LIM_REG_CLASSES |
1352 | }; | |
1353 | ||
d9a5f180 GS |
1354 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1355 | ||
1356 | #define INTEGER_CLASS_P(CLASS) \ | |
1357 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1358 | #define FLOAT_CLASS_P(CLASS) \ | |
1359 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1360 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1361 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1362 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1363 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1364 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1365 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1366 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1367 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1368 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1369 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1370 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1371 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 AI |
1372 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
1373 | reg_classes_intersect_p ((CLASS), MASK_REGS) | |
d9a5f180 GS |
1374 | |
1375 | #define Q_CLASS_P(CLASS) \ | |
1376 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1377 | |
0bd72901 UB |
1378 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1379 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1380 | ||
43f3a59d | 1381 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1382 | |
1383 | #define REG_CLASS_NAMES \ | |
1384 | { "NO_REGS", \ | |
ab408a86 | 1385 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1386 | "SIREG", "DIREG", \ |
e075ae69 | 1387 | "AD_REGS", \ |
2e24efd3 | 1388 | "CLOBBERED_REGS", \ |
e075ae69 | 1389 | "Q_REGS", "NON_Q_REGS", \ |
c98f8742 | 1390 | "INDEX_REGS", \ |
3f3f2124 | 1391 | "LEGACY_REGS", \ |
c98f8742 JVA |
1392 | "GENERAL_REGS", \ |
1393 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1394 | "FLOAT_REGS", \ | |
cb482895 | 1395 | "SSE_FIRST_REG", \ |
45392c76 | 1396 | "NO_REX_SSE_REGS", \ |
a7180f70 | 1397 | "SSE_REGS", \ |
3f97cb0b | 1398 | "EVEX_SSE_REGS", \ |
d5e254e1 | 1399 | "BND_REGS", \ |
3f97cb0b | 1400 | "ALL_SSE_REGS", \ |
a7180f70 | 1401 | "MMX_REGS", \ |
446988df JH |
1402 | "FP_TOP_SSE_REGS", \ |
1403 | "FP_SECOND_SSE_REGS", \ | |
1404 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1405 | "FLOAT_INT_REGS", \ |
446988df JH |
1406 | "INT_SSE_REGS", \ |
1407 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 AI |
1408 | "MASK_EVEX_REGS", \ |
1409 | "MASK_REGS", \ | |
c98f8742 JVA |
1410 | "ALL_REGS" } |
1411 | ||
ac2e563f RH |
1412 | /* Define which registers fit in which classes. This is an initializer |
1413 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1414 | ||
621bc046 UB |
1415 | Note that CLOBBERED_REGS are calculated by |
1416 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1417 | |
3f97cb0b | 1418 | #define REG_CLASS_CONTENTS \ |
d5e254e1 IE |
1419 | { { 0x00, 0x0, 0x0 }, \ |
1420 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1421 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1422 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1423 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1424 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1425 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1426 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
2e24efd3 | 1427 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ |
d5e254e1 IE |
1428 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ |
1429 | { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ | |
1430 | { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ | |
1431 | { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
d5e254e1 IE |
1432 | { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ |
1433 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1434 | { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1435 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1436 | { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
45392c76 | 1437 | { 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \ |
d5e254e1 IE |
1438 | { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ |
1439 | { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ | |
1440 | { 0x0, 0x0,0x1e000 }, /* BND_REGS */ \ | |
1441 | { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ | |
1442 | { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ | |
1443 | { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ | |
1444 | { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ | |
1445 | { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ | |
1446 | { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1447 | { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ | |
1448 | { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ | |
1449 | { 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \ | |
1450 | { 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \ | |
1451 | { 0xffffffff,0xffffffff, 0x1fff } \ | |
e075ae69 | 1452 | } |
c98f8742 JVA |
1453 | |
1454 | /* The same information, inverted: | |
1455 | Return the class number of the smallest class containing | |
1456 | reg number REGNO. This could be a conditional expression | |
1457 | or could index an array. */ | |
1458 | ||
c98f8742 JVA |
1459 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1460 | ||
42db504c SB |
1461 | /* When this hook returns true for MODE, the compiler allows |
1462 | registers explicitly used in the rtl to be used as spill registers | |
1463 | but prevents the compiler from extending the lifetime of these | |
1464 | registers. */ | |
1465 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1466 | |
fc27f749 | 1467 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
05416670 UB |
1468 | #define QI_REGNO_P(N) IN_RANGE ((N), FIRST_QI_REG, LAST_QI_REG) |
1469 | ||
1470 | #define LEGACY_INT_REG_P(X) (REG_P (X) && LEGACY_INT_REGNO_P (REGNO (X))) | |
1471 | #define LEGACY_INT_REGNO_P(N) (IN_RANGE ((N), FIRST_INT_REG, LAST_INT_REG)) | |
1472 | ||
1473 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
1474 | #define REX_INT_REGNO_P(N) \ | |
1475 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1476 | |
58b0b34c | 1477 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 | 1478 | #define GENERAL_REGNO_P(N) \ |
58b0b34c | 1479 | (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) |
3f3f2124 | 1480 | |
fc27f749 UB |
1481 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1482 | #define ANY_QI_REGNO_P(N) \ | |
1483 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1484 | |
66aaf16f UB |
1485 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1486 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1487 | |
fc27f749 | 1488 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1489 | #define SSE_REGNO_P(N) \ |
1490 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
3f97cb0b AI |
1491 | || REX_SSE_REGNO_P (N) \ |
1492 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1493 | |
4977bab6 | 1494 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1495 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1496 | |
0a48088a IT |
1497 | #define EXT_REX_SSE_REG_P(X) (REG_P (X) && EXT_REX_SSE_REGNO_P (REGNO (X))) |
1498 | ||
3f97cb0b AI |
1499 | #define EXT_REX_SSE_REGNO_P(N) \ |
1500 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1501 | ||
05416670 UB |
1502 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
1503 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) | |
3f97cb0b | 1504 | |
9e4a4dd6 | 1505 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 | 1506 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
446988df | 1507 | |
fc27f749 | 1508 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1509 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1510 | |
e075ae69 RH |
1511 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1512 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1513 | ||
58b0b34c | 1514 | #define BND_REG_P(X) (REG_P (X) && BND_REGNO_P (REGNO (X))) |
d5e254e1 | 1515 | #define BND_REGNO_P(N) IN_RANGE ((N), FIRST_BND_REG, LAST_BND_REG) |
d5e254e1 | 1516 | |
05416670 UB |
1517 | /* First floating point reg */ |
1518 | #define FIRST_FLOAT_REG FIRST_STACK_REG | |
1519 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_FLOAT_REG) | |
1520 | ||
1521 | #define SSE_REGNO(N) \ | |
1522 | ((N) < 8 ? FIRST_SSE_REG + (N) \ | |
1523 | : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ | |
1524 | : (FIRST_EXT_REX_SSE_REG + (N) - 16)) | |
1525 | ||
c98f8742 JVA |
1526 | /* The class value for index registers, and the one for base regs. */ |
1527 | ||
1528 | #define INDEX_REG_CLASS INDEX_REGS | |
1529 | #define BASE_REG_CLASS GENERAL_REGS | |
1530 | ||
c98f8742 | 1531 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1532 | is necessary to be able to hold a value of mode MODE in a reload |
b197fc48 UB |
1533 | register for which class CLASS would ordinarily be used. |
1534 | ||
1535 | We avoid classes containing registers from multiple units due to | |
1536 | the limitation in ix86_secondary_memory_needed. We limit these | |
1537 | classes to their "natural mode" single unit register class, depending | |
1538 | on the unit availability. | |
1539 | ||
1540 | Please note that reg_class_subset_p is not commutative, so these | |
1541 | conditions mean "... if (CLASS) includes ALL registers from the | |
1542 | register set." */ | |
1543 | ||
1544 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
1545 | (((MODE) == QImode && !TARGET_64BIT \ | |
1546 | && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ | |
1547 | : (((MODE) == SImode || (MODE) == DImode) \ | |
1548 | && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ | |
1549 | : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ | |
1550 | && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ | |
1551 | : (X87_FLOAT_MODE_P (MODE) \ | |
1552 | && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ | |
1553 | : (CLASS)) | |
c98f8742 | 1554 | |
85ff473e | 1555 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1556 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1557 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1558 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 | 1559 | |
c62b3659 UB |
1560 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1561 | There is no need to emit full 64 bit move on 64 bit targets | |
1562 | for integral modes that can be moved using 32 bit move. */ | |
1563 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1564 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1565 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1566 | : MODE) | |
1567 | ||
1272914c RH |
1568 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1569 | ||
1570 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1571 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1572 | \f |
1573 | /* Stack layout; function entry, exit and calling. */ | |
1574 | ||
1575 | /* Define this if pushing a word on the stack | |
1576 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1577 | #define STACK_GROWS_DOWNWARD 1 |
c98f8742 | 1578 | |
a4d05547 | 1579 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1580 | is at the high-address end of the local variables; |
1581 | that is, each additional local variable allocated | |
1582 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1583 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1584 | |
1585 | /* Offset within stack frame to start allocating local variables at. | |
1586 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1587 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1588 | of the first local allocated. */ | |
1589 | #define STARTING_FRAME_OFFSET 0 | |
1590 | ||
8c2b2fae UB |
1591 | /* If we generate an insn to push BYTES bytes, this says how many the stack |
1592 | pointer really advances by. On 386, we have pushw instruction that | |
1593 | decrements by exactly 2 no matter what the position was, there is no pushb. | |
1594 | ||
1595 | But as CIE data alignment factor on this arch is -4 for 32bit targets | |
1596 | and -8 for 64bit targets, we need to make sure all stack pointer adjustments | |
1597 | are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ | |
c98f8742 | 1598 | |
d2836273 | 1599 | #define PUSH_ROUNDING(BYTES) \ |
8c2b2fae UB |
1600 | (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) |
1601 | ||
1602 | /* If defined, the maximum amount of space required for outgoing arguments | |
1603 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1604 | No space will be pushed onto the stack for each call; instead, the | |
1605 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1606 | |
1607 | In 32bit mode enabling argument accumulation results in about 5% code size | |
1608 | growth becuase move instructions are less compact than push. In 64bit | |
1609 | mode the difference is less drastic but visible. | |
1610 | ||
1611 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1612 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1613 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1614 | |
1615 | With the 64-bit MS ABI, we can generate correct code with or without | |
1616 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1617 | generated without accumulated args is terrible. | |
41ee845b JH |
1618 | |
1619 | If stack probes are required, the space used for large function | |
1620 | arguments on the stack must also be probed, so enable | |
1621 | -maccumulate-outgoing-args so this happens in the prologue. */ | |
f73ad30e | 1622 | |
6c6094f1 | 1623 | #define ACCUMULATE_OUTGOING_ARGS \ |
41ee845b JH |
1624 | ((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \ |
1625 | || TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI) | |
f73ad30e JH |
1626 | |
1627 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1628 | instructions to pass outgoing arguments. */ | |
1629 | ||
1630 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1631 | ||
2da4124d L |
1632 | /* We want the stack and args grow in opposite directions, even if |
1633 | PUSH_ARGS is 0. */ | |
1634 | #define PUSH_ARGS_REVERSED 1 | |
1635 | ||
c98f8742 JVA |
1636 | /* Offset of first parameter from the argument pointer register value. */ |
1637 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1638 | ||
a7180f70 BS |
1639 | /* Define this macro if functions should assume that stack space has been |
1640 | allocated for arguments even when their values are passed in registers. | |
1641 | ||
1642 | The value of this macro is the size, in bytes, of the area reserved for | |
1643 | arguments passed in registers for the function represented by FNDECL. | |
1644 | ||
1645 | This space can be allocated by the caller, or be a part of the | |
1646 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1647 | which. */ | |
7c800926 KT |
1648 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1649 | ||
4ae8027b | 1650 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1651 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1652 | |
c98f8742 JVA |
1653 | /* Define how to find the value returned by a library function |
1654 | assuming the value has mode MODE. */ | |
1655 | ||
4ae8027b | 1656 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1657 | |
e9125c09 TW |
1658 | /* Define the size of the result block used for communication between |
1659 | untyped_call and untyped_return. The block contains a DImode value | |
1660 | followed by the block used by fnsave and frstor. */ | |
1661 | ||
1662 | #define APPLY_RESULT_SIZE (8+108) | |
1663 | ||
b08de47e | 1664 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1665 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1666 | |
1667 | /* Define a data type for recording info about an argument list | |
1668 | during the scan of that argument list. This data type should | |
1669 | hold all necessary information about the function itself | |
1670 | and about the args processed so far, enough to enable macros | |
b08de47e | 1671 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1672 | |
e075ae69 | 1673 | typedef struct ix86_args { |
fa283935 | 1674 | int words; /* # words passed so far */ |
b08de47e MM |
1675 | int nregs; /* # registers available for passing */ |
1676 | int regno; /* next available register number */ | |
3e65f251 KT |
1677 | int fastcall; /* fastcall or thiscall calling convention |
1678 | is used */ | |
fa283935 | 1679 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1680 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1681 | int warn_avx512f; /* True when we want to warn |
1682 | about AVX512F ABI. */ | |
95879c72 | 1683 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1684 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1685 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1686 | int sse_regno; /* next available sse register number */ | |
1687 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1688 | int mmx_nregs; /* # mmx registers available for passing */ |
1689 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1690 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1691 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1692 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1693 | SFmode/DFmode arguments should be passed | |
1694 | in SSE registers. Otherwise 0. */ | |
d5e254e1 IE |
1695 | int bnd_regno; /* next available bnd register number */ |
1696 | int bnds_in_bt; /* number of bounds expected in BT. */ | |
1697 | int force_bnd_pass; /* number of bounds expected for stdarg arg. */ | |
1698 | int stdarg; /* Set to 1 if function is stdarg. */ | |
51212b32 | 1699 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1700 | MS_ABI for ms abi. */ |
e66fc623 | 1701 | tree decl; /* Callee decl. */ |
b08de47e | 1702 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1703 | |
1704 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1705 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1706 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1707 | |
0f6937fe | 1708 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1709 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1710 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1711 | |
c98f8742 JVA |
1712 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1713 | for profiling a function entry. */ | |
1714 | ||
a5fa1ecd JH |
1715 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1716 | ||
1717 | #define MCOUNT_NAME "_mcount" | |
1718 | ||
3c5273a9 KT |
1719 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1720 | ||
a5fa1ecd | 1721 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1722 | |
1723 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1724 | the stack pointer does not matter. The value is tested only in | |
1725 | functions that have frame pointers. | |
1726 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1727 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1728 | we have to restore it ourselves from the frame pointer, in order to |
1729 | use pop */ | |
1730 | ||
1731 | #define EXIT_IGNORE_STACK 1 | |
1732 | ||
c98f8742 JVA |
1733 | /* Output assembler code for a block containing the constant parts |
1734 | of a trampoline, leaving space for the variable parts. */ | |
1735 | ||
a269a03c | 1736 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1737 | mov #STATIC,ecx |
a269a03c JC |
1738 | jmp FUNCTION |
1739 | The trampoline is generated entirely at runtime. The operand of JMP | |
1740 | is the address of FUNCTION relative to the instruction following the | |
1741 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1742 | |
1743 | /* Length in units of the trampoline for entering a nested function. */ | |
1744 | ||
3452586b | 1745 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) |
c98f8742 JVA |
1746 | \f |
1747 | /* Definitions for register eliminations. | |
1748 | ||
1749 | This is an array of structures. Each structure initializes one pair | |
1750 | of eliminable registers. The "from" register number is given first, | |
1751 | followed by "to". Eliminations of the same "from" register are listed | |
1752 | in order of preference. | |
1753 | ||
afc2cd05 NC |
1754 | There are two registers that can always be eliminated on the i386. |
1755 | The frame pointer and the arg pointer can be replaced by either the | |
1756 | hard frame pointer or to the stack pointer, depending upon the | |
1757 | circumstances. The hard frame pointer is not used before reload and | |
1758 | so it is not eligible for elimination. */ | |
c98f8742 | 1759 | |
564d80f4 JH |
1760 | #define ELIMINABLE_REGS \ |
1761 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1762 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1763 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1764 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1765 | |
c98f8742 JVA |
1766 | /* Define the offset between two registers, one to be eliminated, and the other |
1767 | its replacement, at the start of a routine. */ | |
1768 | ||
d9a5f180 GS |
1769 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1770 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1771 | \f |
1772 | /* Addressing modes, and classification of registers for them. */ | |
1773 | ||
c98f8742 JVA |
1774 | /* Macros to check register numbers against specific register classes. */ |
1775 | ||
1776 | /* These assume that REGNO is a hard or pseudo reg number. | |
1777 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1778 | or a pseudo reg currently allocated to a suitable hard reg. | |
1779 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1780 | has been allocated, which happens in reginfo.c during register |
1781 | allocation. */ | |
c98f8742 | 1782 | |
3f3f2124 JH |
1783 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1784 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1785 | || REX_INT_REGNO_P (REGNO) \ |
1786 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1787 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1788 | |
3f3f2124 | 1789 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1790 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1791 | || (REGNO) == ARG_POINTER_REGNUM \ |
1792 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1793 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1794 | |
c98f8742 JVA |
1795 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1796 | and check its validity for a certain class. | |
1797 | We have two alternate definitions for each of them. | |
1798 | The usual definition accepts all pseudo regs; the other rejects | |
1799 | them unless they have been allocated suitable hard regs. | |
1800 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1801 | ||
1802 | Most source files want to accept pseudo regs in the hope that | |
1803 | they will get allocated to the class that the insn wants them to be in. | |
1804 | Source files for reload pass need to be strict. | |
1805 | After reload, it makes no difference, since pseudo regs have | |
1806 | been eliminated by then. */ | |
1807 | ||
c98f8742 | 1808 | |
ff482c8d | 1809 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1810 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1811 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1812 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1813 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1814 | ||
3b3c6a3f | 1815 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1816 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1817 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1818 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1819 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1820 | |
3b3c6a3f MM |
1821 | /* Strict versions, hard registers only */ |
1822 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1823 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1824 | |
3b3c6a3f | 1825 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1826 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1827 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1828 | |
1829 | #else | |
d9a5f180 GS |
1830 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1831 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1832 | #endif |
1833 | ||
331d9186 | 1834 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1835 | that is a valid memory address for an instruction. |
1836 | The MODE argument is the machine mode for the MEM expression | |
1837 | that wants to use this address. | |
1838 | ||
331d9186 | 1839 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1840 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1841 | ||
1842 | See legitimize_pic_address in i386.c for details as to what | |
1843 | constitutes a legitimate address when -fpic is used. */ | |
1844 | ||
1845 | #define MAX_REGS_PER_ADDRESS 2 | |
1846 | ||
f996902d | 1847 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1848 | |
b949ea8b JW |
1849 | /* If defined, a C expression to determine the base term of address X. |
1850 | This macro is used in only one place: `find_base_term' in alias.c. | |
1851 | ||
1852 | It is always safe for this macro to not be defined. It exists so | |
1853 | that alias analysis can understand machine-dependent addresses. | |
1854 | ||
1855 | The typical use of this macro is to handle addresses containing | |
1856 | a label_ref or symbol_ref within an UNSPEC. */ | |
1857 | ||
d9a5f180 | 1858 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1859 | |
c98f8742 | 1860 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1861 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1862 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1863 | ||
f996902d | 1864 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1865 | |
1866 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1867 | (GET_CODE (X) == SYMBOL_REF \ |
1868 | || GET_CODE (X) == LABEL_REF \ | |
1869 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1870 | \f |
b08de47e MM |
1871 | /* Max number of args passed in registers. If this is more than 3, we will |
1872 | have problems with ebx (register #4), since it is a caller save register and | |
1873 | is also used as the pic register in ELF. So for now, don't allow more than | |
1874 | 3 registers to be passed in registers. */ | |
1875 | ||
7c800926 KT |
1876 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1877 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1878 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1879 | |
72fa3605 | 1880 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1881 | |
4ae8027b | 1882 | #define REGPARM_MAX \ |
2824d6e5 UB |
1883 | (TARGET_64BIT \ |
1884 | ? (TARGET_64BIT_MS_ABI \ | |
1885 | ? X86_64_MS_REGPARM_MAX \ | |
1886 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1887 | : X86_32_REGPARM_MAX) |
d2836273 | 1888 | |
72fa3605 UB |
1889 | #define X86_64_SSE_REGPARM_MAX 8 |
1890 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1891 | ||
b6010cab | 1892 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1893 | |
4ae8027b | 1894 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1895 | (TARGET_64BIT \ |
1896 | ? (TARGET_64BIT_MS_ABI \ | |
1897 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1898 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1899 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 JH |
1900 | |
1901 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
c98f8742 JVA |
1902 | \f |
1903 | /* Specify the machine mode that this machine uses | |
1904 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1905 | #define CASE_VECTOR_MODE \ |
6025b127 | 1906 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1907 | |
c98f8742 JVA |
1908 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1909 | #define DEFAULT_SIGNED_CHAR 1 | |
1910 | ||
1911 | /* Max number of bytes we can move from memory to memory | |
1912 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1913 | #define MOVE_MAX 16 |
1914 | ||
1915 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1916 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1917 | number of bytes we can move with a single instruction. */ |
63001560 | 1918 | #define MOVE_MAX_PIECES UNITS_PER_WORD |
c98f8742 | 1919 | |
7e24ffc9 | 1920 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1921 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1922 | Increasing the value will always make code faster, but eventually |
1923 | incurs high cost in increased code size. | |
c98f8742 | 1924 | |
e2e52e1b | 1925 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1926 | |
e04ad03d | 1927 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1928 | |
45d78e7f JJ |
1929 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1930 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1931 | ||
e04ad03d | 1932 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1933 | |
53f00dde UB |
1934 | /* Define if shifts truncate the shift count which implies one can |
1935 | omit a sign-extension or zero-extension of a shift count. | |
1936 | ||
1937 | On i386, shifts do truncate the count. But bit test instructions | |
1938 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1939 | |
1940 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1941 | ||
1942 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1943 | is done just by pretending it is already truncated. */ | |
1944 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1945 | ||
d9f32422 JH |
1946 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1947 | TYPE and which has the specified mode and signedness is to be | |
1948 | stored in a register. This macro is only called when TYPE is a | |
1949 | scalar type. | |
1950 | ||
f710504c | 1951 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1952 | quantities to SImode. The choice depends on target type. */ |
1953 | ||
1954 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1955 | do { \ |
d9f32422 JH |
1956 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1957 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1958 | (MODE) = SImode; \ |
1959 | } while (0) | |
d9f32422 | 1960 | |
c98f8742 JVA |
1961 | /* Specify the machine mode that pointers have. |
1962 | After generation of rtl, the compiler makes no further distinction | |
1963 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1964 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1965 | |
d5e254e1 IE |
1966 | /* Specify the machine mode that bounds have. */ |
1967 | #define BNDmode (ix86_pmode == PMODE_DI ? BND64mode : BND32mode) | |
1968 | ||
f0ea7581 L |
1969 | /* A C expression whose value is zero if pointers that need to be extended |
1970 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1971 | greater then zero if they are zero-extended and less then zero if the | |
1972 | ptr_extend instruction should be used. */ | |
1973 | ||
1974 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1975 | ||
c98f8742 JVA |
1976 | /* A function address in a call instruction |
1977 | is a byte address (for indexing purposes) | |
1978 | so give the MEM rtx a byte's mode. */ | |
1979 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1980 | \f |
d4ba09c0 | 1981 | |
d4ba09c0 SC |
1982 | /* A C expression for the cost of a branch instruction. A value of 1 |
1983 | is the default; other values are interpreted relative to that. */ | |
1984 | ||
3a4fd356 JH |
1985 | #define BRANCH_COST(speed_p, predictable_p) \ |
1986 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1987 | |
e327d1a3 L |
1988 | /* An integer expression for the size in bits of the largest integer machine |
1989 | mode that should actually be used. We allow pairs of registers. */ | |
1990 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1991 | ||
d4ba09c0 SC |
1992 | /* Define this macro as a C expression which is nonzero if accessing |
1993 | less than a word of memory (i.e. a `char' or a `short') is no | |
1994 | faster than accessing a word of memory, i.e., if such access | |
1995 | require more than one instruction or if there is no difference in | |
1996 | cost between byte and (aligned) word loads. | |
1997 | ||
1998 | When this macro is not defined, the compiler will access a field by | |
1999 | finding the smallest containing object; when it is defined, a | |
2000 | fullword load will be used if alignment permits. Unless bytes | |
2001 | accesses are faster than word accesses, using word accesses is | |
2002 | preferable since it may eliminate subsequent memory access if | |
2003 | subsequent accesses occur to other fields in the same word of the | |
2004 | structure, but to different bytes. */ | |
2005 | ||
2006 | #define SLOW_BYTE_ACCESS 0 | |
2007 | ||
2008 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
2009 | #define SLOW_SHORT_ACCESS 0 | |
2010 | ||
d4ba09c0 SC |
2011 | /* Define this macro to be the value 1 if unaligned accesses have a |
2012 | cost many times greater than aligned accesses, for example if they | |
2013 | are emulated in a trap handler. | |
2014 | ||
9cd10576 KH |
2015 | When this macro is nonzero, the compiler will act as if |
2016 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 2017 | moves. This can cause significantly more instructions to be |
9cd10576 | 2018 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
2019 | accesses only add a cycle or two to the time for a memory access. |
2020 | ||
2021 | If the value of this macro is always zero, it need not be defined. */ | |
2022 | ||
e1565e65 | 2023 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 2024 | |
d4ba09c0 SC |
2025 | /* Define this macro if it is as good or better to call a constant |
2026 | function address than to call an address kept in a register. | |
2027 | ||
2028 | Desirable on the 386 because a CALL with a constant address is | |
2029 | faster than one with a register address. */ | |
2030 | ||
1e8552c2 | 2031 | #define NO_FUNCTION_CSE 1 |
c98f8742 | 2032 | \f |
c572e5ba JVA |
2033 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
2034 | return the mode to be used for the comparison. | |
2035 | ||
2036 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 2037 | VOIDmode should be used in all other cases. |
c572e5ba | 2038 | |
16189740 | 2039 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2040 | possible, to allow for more combinations. */ |
c98f8742 | 2041 | |
d9a5f180 | 2042 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2043 | |
9cd10576 | 2044 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2045 | reversed. */ |
2046 | ||
2047 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2048 | ||
2049 | /* A C expression whose value is reversed condition code of the CODE for | |
2050 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2051 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2052 | |
c98f8742 JVA |
2053 | \f |
2054 | /* Control the assembler format that we output, to the extent | |
2055 | this does not vary between assemblers. */ | |
2056 | ||
2057 | /* How to refer to registers in assembler output. | |
892a2d68 | 2058 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2059 | |
a7b376ee | 2060 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2061 | For non floating point regs, the following are the HImode names. |
2062 | ||
2063 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
2064 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
2065 | "y" code. */ | |
c98f8742 | 2066 | |
a7180f70 BS |
2067 | #define HI_REGISTER_NAMES \ |
2068 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2069 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2070 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2071 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2072 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 2073 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
2074 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
2075 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
2076 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
2077 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 2078 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
d5e254e1 IE |
2079 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", \ |
2080 | "bnd0", "bnd1", "bnd2", "bnd3" } | |
a7180f70 | 2081 | |
c98f8742 JVA |
2082 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2083 | ||
2084 | /* Table of additional register names to use in user input. */ | |
2085 | ||
2086 | #define ADDITIONAL_REGISTER_NAMES \ | |
7c831c4d KY |
2087 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2088 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2089 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
2090 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
2091 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2092 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ | |
2093 | { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ | |
2094 | { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ | |
2095 | { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ | |
2096 | { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ | |
2097 | { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ | |
2098 | { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ | |
2099 | { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ | |
2100 | { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ | |
2101 | { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ | |
2102 | { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ | |
2103 | { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ | |
2104 | { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ | |
2105 | { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ | |
2106 | { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ | |
2107 | { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ | |
2108 | { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } | |
c98f8742 JVA |
2109 | |
2110 | /* Note we are omitting these since currently I don't know how | |
2111 | to get gcc to use these, since they want the same but different | |
2112 | number as al, and ax. | |
2113 | */ | |
2114 | ||
c98f8742 | 2115 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2116 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2117 | |
2118 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2119 | of regs 0 through 3. */ |
c98f8742 JVA |
2120 | |
2121 | #define QI_HIGH_REGISTER_NAMES \ | |
2122 | {"ah", "dh", "ch", "bh", } | |
2123 | ||
2124 | /* How to renumber registers for dbx and gdb. */ | |
2125 | ||
d9a5f180 GS |
2126 | #define DBX_REGISTER_NUMBER(N) \ |
2127 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2128 | |
9a82e702 MS |
2129 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2130 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2131 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2132 | |
780a5b71 UB |
2133 | extern int const x86_64_ms_sysv_extra_clobbered_registers[12]; |
2134 | ||
469ac993 JM |
2135 | /* Before the prologue, RA is at 0(%esp). */ |
2136 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2137 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2138 | |
e414ab29 | 2139 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2140 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2141 | ((COUNT) == 0 \ | |
0a81f074 RS |
2142 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ |
2143 | -UNITS_PER_WORD)) \ | |
2144 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2145 | |
892a2d68 | 2146 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2147 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2148 | |
a6ab3aad | 2149 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2150 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2151 | |
1020a5ab | 2152 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2153 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2154 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2155 | |
ad919812 | 2156 | |
e4c4ebeb RH |
2157 | /* Select a format to encode pointers in exception handling data. CODE |
2158 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2159 | true if the symbol may be affected by dynamic relocations. | |
2160 | ||
2161 | ??? All x86 object file formats are capable of representing this. | |
2162 | After all, the relocation needed is the same as for the call insn. | |
2163 | Whether or not a particular assembler allows us to enter such, I | |
2164 | guess we'll have to see. */ | |
d9a5f180 | 2165 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2166 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2167 | |
c98f8742 JVA |
2168 | /* This is how to output an insn to push a register on the stack. |
2169 | It need not be very fast code. */ | |
2170 | ||
d9a5f180 | 2171 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2172 | do { \ |
2173 | if (TARGET_64BIT) \ | |
2174 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2175 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2176 | else \ | |
2177 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2178 | } while (0) | |
c98f8742 JVA |
2179 | |
2180 | /* This is how to output an insn to pop a register from the stack. | |
2181 | It need not be very fast code. */ | |
2182 | ||
d9a5f180 | 2183 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2184 | do { \ |
2185 | if (TARGET_64BIT) \ | |
2186 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2187 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2188 | else \ | |
2189 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2190 | } while (0) | |
c98f8742 | 2191 | |
f88c65f7 | 2192 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2193 | |
2194 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2195 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2196 | |
f88c65f7 | 2197 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2198 | |
33f7f353 | 2199 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2200 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2201 | |
63001560 | 2202 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2203 | |
2204 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2205 | { \ | |
2206 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2207 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2208 | } |
2209 | ||
2210 | /* A C statement or statements which output an assembler instruction | |
2211 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2212 | variable of type `char *' which points to the opcode name in | |
2213 | its "internal" form--the form that is written in the machine | |
2214 | description. */ | |
2215 | ||
2216 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2217 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2218 | ||
6a90d232 L |
2219 | /* A C statement to output to the stdio stream FILE an assembler |
2220 | command to pad the location counter to a multiple of 1<<LOG | |
2221 | bytes if it is within MAX_SKIP bytes. */ | |
2222 | ||
2223 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
2224 | #undef ASM_OUTPUT_MAX_SKIP_PAD | |
2225 | #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ | |
2226 | if ((LOG) != 0) \ | |
2227 | { \ | |
2228 | if ((MAX_SKIP) == 0) \ | |
2229 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2230 | else \ | |
2231 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ | |
2232 | } | |
2233 | #endif | |
2234 | ||
135a687e KT |
2235 | /* Write the extra assembler code needed to declare a function |
2236 | properly. */ | |
2237 | ||
2238 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2239 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
2240 | ix86_asm_output_function_label (FILE, NAME, DECL) | |
2241 | ||
f7288899 EC |
2242 | /* Under some conditions we need jump tables in the text section, |
2243 | because the assembler cannot handle label differences between | |
2244 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2245 | |
2246 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2247 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2248 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2249 | |
cea3bd3e RH |
2250 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2251 | and switch back. For x86 we do this only to save a few bytes that | |
2252 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2253 | #define CRT_MKSTR2(VAL) #VAL |
2254 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2255 | ||
2256 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2257 | asm (SECTION_OP "\n\t" \ | |
2258 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2259 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2260 | |
2261 | /* Default threshold for putting data in large sections | |
2262 | with x86-64 medium memory model */ | |
2263 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
776280c4 UB |
2264 | |
2265 | /* Adjust the length of the insn with the length of BND prefix. */ | |
0453025d UB |
2266 | |
2267 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2268 | do { \ | |
2269 | if (NONDEBUG_INSN_P (INSN) && INSN_CODE (INSN) >= 0 \ | |
2270 | && get_attr_maybe_prefix_bnd (INSN)) \ | |
2271 | LENGTH += ix86_bnd_prefixed_insn_p (INSN); \ | |
776280c4 | 2272 | } while (0) |
74b42c8b | 2273 | \f |
b97de419 L |
2274 | /* Which processor to tune code generation for. These must be in sync |
2275 | with processor_target_table in i386.c. */ | |
5bf0ebab RH |
2276 | |
2277 | enum processor_type | |
2278 | { | |
b97de419 L |
2279 | PROCESSOR_GENERIC = 0, |
2280 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2281 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2282 | PROCESSOR_PENTIUM, | |
89e5941d | 2283 | PROCESSOR_LAKEMOUNT, |
5bf0ebab | 2284 | PROCESSOR_PENTIUMPRO, |
5bf0ebab | 2285 | PROCESSOR_PENTIUM4, |
89c43c0a | 2286 | PROCESSOR_NOCONA, |
340ef734 | 2287 | PROCESSOR_CORE2, |
d3c11974 L |
2288 | PROCESSOR_NEHALEM, |
2289 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2290 | PROCESSOR_HASWELL, |
d3c11974 L |
2291 | PROCESSOR_BONNELL, |
2292 | PROCESSOR_SILVERMONT, | |
52747219 | 2293 | PROCESSOR_KNL, |
06caf59d | 2294 | PROCESSOR_SKYLAKE_AVX512, |
9a7f94d7 | 2295 | PROCESSOR_INTEL, |
b97de419 L |
2296 | PROCESSOR_GEODE, |
2297 | PROCESSOR_K6, | |
2298 | PROCESSOR_ATHLON, | |
2299 | PROCESSOR_K8, | |
21efb4d4 | 2300 | PROCESSOR_AMDFAM10, |
1133125e | 2301 | PROCESSOR_BDVER1, |
4d652a18 | 2302 | PROCESSOR_BDVER2, |
eb2f2b44 | 2303 | PROCESSOR_BDVER3, |
ed97ad47 | 2304 | PROCESSOR_BDVER4, |
14b52538 | 2305 | PROCESSOR_BTVER1, |
e32bfc16 | 2306 | PROCESSOR_BTVER2, |
5bf0ebab RH |
2307 | PROCESSOR_max |
2308 | }; | |
2309 | ||
9e555526 | 2310 | extern enum processor_type ix86_tune; |
5bf0ebab | 2311 | extern enum processor_type ix86_arch; |
5bf0ebab | 2312 | |
8362f420 JH |
2313 | /* Size of the RED_ZONE area. */ |
2314 | #define RED_ZONE_SIZE 128 | |
2315 | /* Reserved area of the red zone for temporaries. */ | |
2316 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2317 | |
95899b34 | 2318 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2319 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2320 | |
2321 | /* Smallest class containing REGNO. */ | |
2322 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2323 | ||
0948ccb2 PB |
2324 | enum ix86_fpcmp_strategy { |
2325 | IX86_FPCMP_SAHF, | |
2326 | IX86_FPCMP_COMI, | |
2327 | IX86_FPCMP_ARITH | |
2328 | }; | |
22fb740d JH |
2329 | \f |
2330 | /* To properly truncate FP values into integers, we need to set i387 control | |
2331 | word. We can't emit proper mode switching code before reload, as spills | |
2332 | generated by reload may truncate values incorrectly, but we still can avoid | |
2333 | redundant computation of new control word by the mode switching pass. | |
2334 | The fldcw instructions are still emitted redundantly, but this is probably | |
2335 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2336 | the sequence. |
22fb740d JH |
2337 | |
2338 | The machinery is to emit simple truncation instructions and split them | |
2339 | before reload to instructions having USEs of two memory locations that | |
2340 | are filled by this code to old and new control word. | |
fce5a9f2 | 2341 | |
22fb740d JH |
2342 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2343 | needed. */ | |
2344 | ||
ff680eb1 UB |
2345 | enum ix86_entity |
2346 | { | |
ff97910d VY |
2347 | AVX_U128 = 0, |
2348 | I387_TRUNC, | |
ff680eb1 UB |
2349 | I387_FLOOR, |
2350 | I387_CEIL, | |
2351 | I387_MASK_PM, | |
2352 | MAX_386_ENTITIES | |
2353 | }; | |
2354 | ||
1cba2b96 | 2355 | enum ix86_stack_slot |
ff680eb1 | 2356 | { |
443ca5fc | 2357 | SLOT_TEMP = 0, |
ff680eb1 UB |
2358 | SLOT_CW_STORED, |
2359 | SLOT_CW_TRUNC, | |
2360 | SLOT_CW_FLOOR, | |
2361 | SLOT_CW_CEIL, | |
2362 | SLOT_CW_MASK_PM, | |
2363 | MAX_386_STACK_LOCALS | |
2364 | }; | |
22fb740d | 2365 | |
ff97910d VY |
2366 | enum avx_u128_state |
2367 | { | |
2368 | AVX_U128_CLEAN, | |
2369 | AVX_U128_DIRTY, | |
2370 | AVX_U128_ANY | |
2371 | }; | |
2372 | ||
22fb740d JH |
2373 | /* Define this macro if the port needs extra instructions inserted |
2374 | for mode switching in an optimizing compilation. */ | |
2375 | ||
ff680eb1 UB |
2376 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2377 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2378 | |
2379 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2380 | initializer for an array of integers. Each initializer element N | |
2381 | refers to an entity that needs mode switching, and specifies the | |
2382 | number of different modes that might need to be set for this | |
2383 | entity. The position of the initializer in the initializer - | |
2384 | starting counting at zero - determines the integer that is used to | |
2385 | refer to the mode-switched entity in question. */ | |
2386 | ||
ff680eb1 | 2387 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
ff97910d | 2388 | { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
22fb740d | 2389 | |
0f0138b6 JH |
2390 | \f |
2391 | /* Avoid renaming of stack registers, as doing so in combination with | |
2392 | scheduling just increases amount of live registers at time and in | |
2393 | the turn amount of fxch instructions needed. | |
2394 | ||
3f97cb0b AI |
2395 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2396 | ||
2397 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2398 | |
3f97cb0b AI |
2399 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \ |
2400 | (EXT_REX_SSE_REGNO_P (SRC) == \ | |
2401 | EXT_REX_SSE_REGNO_P (TARGET))) | |
22fb740d | 2402 | |
3b3c6a3f | 2403 | \f |
e91f04de | 2404 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2405 | \f |
ec7ded37 | 2406 | /* Machine specific frame tracking during prologue/epilogue generation. */ |
cd9c1ca8 | 2407 | |
604a6be9 | 2408 | #ifndef USED_FOR_TARGET |
ec7ded37 | 2409 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2410 | { |
ec7ded37 RH |
2411 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2412 | is drap_reg, we don't bother trying to record here the real CFA when | |
2413 | it might really be a DW_CFA_def_cfa_expression. */ | |
2414 | rtx cfa_reg; | |
2415 | HOST_WIDE_INT cfa_offset; | |
2416 | ||
2417 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2418 | When stack frame re-alignment is active, these may not be relative | |
2419 | to the CFA. However, in all cases they are relative to the offsets | |
2420 | of the saved registers stored in ix86_frame. */ | |
2421 | HOST_WIDE_INT sp_offset; | |
2422 | HOST_WIDE_INT fp_offset; | |
2423 | ||
2424 | /* The size of the red-zone that may be assumed for the purposes of | |
2425 | eliding register restore notes in the epilogue. This may be zero | |
2426 | if no red-zone is in effect, or may be reduced from the real | |
2427 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2428 | int red_zone_offset; | |
2429 | ||
2430 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2431 | value within the frame. If false then the offset above should be | |
2432 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2433 | thus has an offset of zero. */ | |
2434 | BOOL_BITFIELD sp_valid : 1; | |
2435 | BOOL_BITFIELD fp_valid : 1; | |
2436 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2437 | |
2438 | /* Indicate whether the local stack frame has been re-aligned. When | |
2439 | set, the SP/FP offsets above are relative to the aligned frame | |
2440 | and not the CFA. */ | |
2441 | BOOL_BITFIELD realigned : 1; | |
cd9c1ca8 RH |
2442 | }; |
2443 | ||
f81c9774 RH |
2444 | /* Private to winnt.c. */ |
2445 | struct seh_frame_state; | |
2446 | ||
d1b38208 | 2447 | struct GTY(()) machine_function { |
fa1a0d02 JH |
2448 | struct stack_local_entry *stack_locals; |
2449 | const char *some_ld_name; | |
4aab97f9 L |
2450 | int varargs_gpr_size; |
2451 | int varargs_fpr_size; | |
ff680eb1 | 2452 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b RH |
2453 | |
2454 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE | |
2455 | has been computed for. */ | |
2456 | int use_fast_prologue_epilogue_nregs; | |
2457 | ||
7458026b ILT |
2458 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2459 | the stack arguments for a function with a variable number of | |
2460 | arguments. This is set at the start of the function and is used | |
2461 | to initialize the overflow_arg_area field of the va_list | |
2462 | structure. */ | |
2463 | rtx split_stack_varargs_pointer; | |
2464 | ||
3452586b RH |
2465 | /* This value is used for amd64 targets and specifies the current abi |
2466 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2467 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2468 | |
2469 | /* Nonzero if the function accesses a previous frame. */ | |
2470 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2471 | ||
2472 | /* Nonzero if the function requires a CLD in the prologue. */ | |
2473 | BOOL_BITFIELD needs_cld : 1; | |
2474 | ||
922e3e33 UB |
2475 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2476 | expander to determine the style used. */ | |
3452586b RH |
2477 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2478 | ||
5bf5a10b AO |
2479 | /* If true, the current function needs the default PIC register, not |
2480 | an alternate register (on x86) and must not use the red zone (on | |
2481 | x86_64), even if it's a leaf function. We don't want the | |
2482 | function to be regarded as non-leaf because TLS calls need not | |
2483 | affect register allocation. This flag is set when a TLS call | |
2484 | instruction is expanded within a function, and never reset, even | |
2485 | if all such instructions are optimized away. Use the | |
2486 | ix86_current_function_calls_tls_descriptor macro for a better | |
2487 | approximation. */ | |
3452586b RH |
2488 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2489 | ||
2490 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2491 | stack below the return address. */ | |
2492 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2493 | |
529a6471 JJ |
2494 | /* If true, it is safe to not save/restore DRAP register. */ |
2495 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2496 | ||
a0ff7835 L |
2497 | /* If true, there is register available for argument passing. This |
2498 | is used only in ix86_function_ok_for_sibcall by 32-bit to determine | |
2499 | if there is scratch register available for indirect sibcall. In | |
2500 | 64-bit, rax, r10 and r11 are scratch registers which aren't used to | |
2501 | pass arguments and can be used for indirect sibcall. */ | |
2502 | BOOL_BITFIELD arg_reg_available : 1; | |
2503 | ||
ec7ded37 RH |
2504 | /* During prologue/epilogue generation, the current frame state. |
2505 | Otherwise, the frame state at the end of the prologue. */ | |
2506 | struct machine_frame_state fs; | |
f81c9774 RH |
2507 | |
2508 | /* During SEH output, this is non-null. */ | |
2509 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2510 | }; |
cd9c1ca8 | 2511 | #endif |
fa1a0d02 JH |
2512 | |
2513 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2514 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2515 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2516 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
922e3e33 | 2517 | #define ix86_current_function_needs_cld (cfun->machine->needs_cld) |
5bf5a10b AO |
2518 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2519 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2520 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2521 | calls are optimized away, we try to detect cases in which it was | |
2522 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2523 | verify whether there's any such instruction live by testing that | |
2524 | REG_SP is live. */ | |
2525 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2526 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2527 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
249e6b63 | 2528 | |
1bc7c5b6 ZW |
2529 | /* Control behavior of x86_file_start. */ |
2530 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2531 | #define X86_FILE_START_FLTUSED false | |
2532 | ||
7dcbf659 JH |
2533 | /* Flag to mark data that is in the large address area. */ |
2534 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2535 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2536 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2537 | |
2538 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2539 | have defined always, to avoid ifdefing. */ | |
2540 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2541 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2542 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2543 | ||
2544 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2545 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2546 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2547 | ||
82c0e1a0 KT |
2548 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2549 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2550 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2551 | ||
7942e47e RY |
2552 | extern void debug_ready_dispatch (void); |
2553 | extern void debug_dispatch_window (int); | |
2554 | ||
91afcfa3 QN |
2555 | /* The value at zero is only defined for the BMI instructions |
2556 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2557 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1068ced5 | 2558 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI ? 1 : 0) |
91afcfa3 | 2559 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
1068ced5 | 2560 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT ? 1 : 0) |
91afcfa3 QN |
2561 | |
2562 | ||
b8ce4e94 KT |
2563 | /* Flags returned by ix86_get_callcvt (). */ |
2564 | #define IX86_CALLCVT_CDECL 0x1 | |
2565 | #define IX86_CALLCVT_STDCALL 0x2 | |
2566 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2567 | #define IX86_CALLCVT_THISCALL 0x8 | |
2568 | #define IX86_CALLCVT_REGPARM 0x10 | |
2569 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2570 | ||
2571 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2572 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2573 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2574 | ||
b86b9f44 MM |
2575 | #define RECIP_MASK_NONE 0x00 |
2576 | #define RECIP_MASK_DIV 0x01 | |
2577 | #define RECIP_MASK_SQRT 0x02 | |
2578 | #define RECIP_MASK_VEC_DIV 0x04 | |
2579 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2580 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2581 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2582 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2583 | |
2584 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2585 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2586 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2587 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2588 | ||
5dcfdccd KY |
2589 | #define IX86_HLE_ACQUIRE (1 << 16) |
2590 | #define IX86_HLE_RELEASE (1 << 17) | |
2591 | ||
e83b8e2e JJ |
2592 | /* For switching between functions with different target attributes. */ |
2593 | #define SWITCHABLE_TARGET 1 | |
2594 | ||
44d0de8d UB |
2595 | #define TARGET_SUPPORTS_WIDE_INT 1 |
2596 | ||
c98f8742 JVA |
2597 | /* |
2598 | Local variables: | |
2599 | version-control: t | |
2600 | End: | |
2601 | */ |