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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
cf011243 | 2 | Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, |
5bf5a10b | 3 | 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
c98f8742 | 4 | |
188fc5b5 | 5 | This file is part of GCC. |
c98f8742 | 6 | |
188fc5b5 | 7 | GCC is free software; you can redistribute it and/or modify |
c98f8742 JVA |
8 | it under the terms of the GNU General Public License as published by |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
188fc5b5 | 12 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
188fc5b5 | 18 | along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
19 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
c98f8742 JVA |
21 | |
22 | /* The purpose of this file is to define the characteristics of the i386, | |
b4ac57ab | 23 | independent of assembler syntax or operating system. |
c98f8742 JVA |
24 | |
25 | Three other files build on this one to describe a specific assembler syntax: | |
26 | bsd386.h, att386.h, and sun386.h. | |
27 | ||
28 | The actual tm.h file for a particular system should include | |
29 | this file, and then the file for the appropriate assembler syntax. | |
30 | ||
31 | Many macros that specify assembler syntax are omitted entirely from | |
32 | this file because they really belong in the files for particular | |
e075ae69 RH |
33 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, |
34 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
35 | that start with ASM_ or end in ASM_OP. */ | |
c98f8742 | 36 | |
d4ba09c0 SC |
37 | /* Define the specific costs for a given cpu */ |
38 | ||
39 | struct processor_costs { | |
8b60264b KG |
40 | const int add; /* cost of an add instruction */ |
41 | const int lea; /* cost of a lea instruction */ | |
42 | const int shift_var; /* variable shift costs */ | |
43 | const int shift_const; /* constant shift costs */ | |
f676971a | 44 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 45 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 46 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 47 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 48 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
49 | int movsx; /* The cost of movsx operation. */ |
50 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
51 | const int large_insn; /* insns larger than this cost more */ |
52 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 53 | memory-to-memory move insns. */ |
8b60264b KG |
54 | const int movzbl_load; /* cost of loading using movzbl */ |
55 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
56 | in QImode, HImode and SImode relative |
57 | to reg-reg move (2). */ | |
8b60264b | 58 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 59 | in QImode, HImode and SImode */ |
8b60264b KG |
60 | const int fp_move; /* cost of reg,reg fld/fst */ |
61 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 62 | in SFmode, DFmode and XFmode */ |
8b60264b | 63 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 64 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
65 | const int mmx_move; /* cost of moving MMX register. */ |
66 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 67 | in SImode and DImode */ |
8b60264b | 68 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 69 | in SImode and DImode */ |
8b60264b KG |
70 | const int sse_move; /* cost of moving SSE register. */ |
71 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 72 | in SImode, DImode and TImode*/ |
8b60264b | 73 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 74 | in SImode, DImode and TImode*/ |
8b60264b | 75 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 76 | integer and vice versa. */ |
f4365627 JH |
77 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
78 | const int simultaneous_prefetches; /* number of parallel prefetch | |
79 | operations. */ | |
4977bab6 | 80 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
81 | const int fadd; /* cost of FADD and FSUB instructions. */ |
82 | const int fmul; /* cost of FMUL instruction. */ | |
83 | const int fdiv; /* cost of FDIV instruction. */ | |
84 | const int fabs; /* cost of FABS instruction. */ | |
85 | const int fchs; /* cost of FCHS instruction. */ | |
86 | const int fsqrt; /* cost of FSQRT instruction. */ | |
d4ba09c0 SC |
87 | }; |
88 | ||
8b60264b | 89 | extern const struct processor_costs *ix86_cost; |
d4ba09c0 | 90 | |
c98f8742 JVA |
91 | /* Macros used in the machine description to test the flags. */ |
92 | ||
ddd5a7c1 | 93 | /* configure can arrange to make this 2, to force a 486. */ |
e075ae69 | 94 | |
35b528be | 95 | #ifndef TARGET_CPU_DEFAULT |
d326eaf0 | 96 | #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic |
10e9fecc | 97 | #endif |
35b528be | 98 | |
004d3859 GK |
99 | #ifndef TARGET_FPMATH_DEFAULT |
100 | #define TARGET_FPMATH_DEFAULT \ | |
101 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
102 | #endif | |
103 | ||
6ac49599 | 104 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
b08de47e | 105 | |
5791cc29 JT |
106 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
107 | compile-time constant. */ | |
108 | #ifdef IN_LIBGCC2 | |
6ac49599 | 109 | #undef TARGET_64BIT |
5791cc29 JT |
110 | #ifdef __x86_64__ |
111 | #define TARGET_64BIT 1 | |
112 | #else | |
113 | #define TARGET_64BIT 0 | |
114 | #endif | |
115 | #else | |
6ac49599 RS |
116 | #ifndef TARGET_BI_ARCH |
117 | #undef TARGET_64BIT | |
67adf6a9 | 118 | #if TARGET_64BIT_DEFAULT |
0c2dc519 JH |
119 | #define TARGET_64BIT 1 |
120 | #else | |
121 | #define TARGET_64BIT 0 | |
122 | #endif | |
123 | #endif | |
5791cc29 | 124 | #endif |
25f94bb5 | 125 | |
750054a2 CT |
126 | #define HAS_LONG_COND_BRANCH 1 |
127 | #define HAS_LONG_UNCOND_BRANCH 1 | |
128 | ||
9e555526 RH |
129 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
130 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
131 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
132 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 133 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
134 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
135 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
136 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
137 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 138 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 139 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
05f85dbb | 140 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d326eaf0 JH |
141 | #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) |
142 | #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
143 | #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
a269a03c | 144 | |
9e555526 | 145 | #define TUNEMASK (1 << ix86_tune) |
a269a03c | 146 | extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and; |
1e993cb8 | 147 | extern const int x86_use_bit_test, x86_cmove, x86_deep_branch; |
ef6257cd | 148 | extern const int x86_branch_hints, x86_unroll_strlen; |
e075ae69 | 149 | extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx; |
862e2886 | 150 | extern const int x86_use_himode_fiop, x86_use_simode_fiop; |
0e8c2b0d | 151 | extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write; |
e075ae69 | 152 | extern const int x86_read_modify, x86_split_long_moves; |
285464d0 | 153 | extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix; |
d9f32422 | 154 | extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs; |
0b5107cf | 155 | extern const int x86_promote_hi_regs, x86_integer_DFmode_moves; |
bdeb029c | 156 | extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8; |
0b5107cf | 157 | extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall; |
c6036a37 | 158 | extern const int x86_accumulate_outgoing_args, x86_prologue_using_move; |
b972dd02 | 159 | extern const int x86_epilogue_using_move, x86_decompose_lea; |
495333a6 | 160 | extern const int x86_arch_always_fancy_math_387, x86_shift1; |
41afe4ef | 161 | extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs; |
4977bab6 | 162 | extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor; |
41afe4ef | 163 | extern const int x86_use_ffreep; |
ad7b96a9 | 164 | extern const int x86_inter_unit_moves, x86_schedule; |
7cacf53e | 165 | extern const int x86_use_bt; |
a0274e3e | 166 | extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd; |
d326eaf0 JH |
167 | extern const int x86_use_incdec; |
168 | extern const int x86_pad_returns; | |
167fa32c | 169 | extern const int x86_bswap; |
995cc369 | 170 | extern const int x86_partial_flag_reg_stall; |
f4365627 | 171 | extern int x86_prefetch_sse; |
a269a03c | 172 | |
9e555526 RH |
173 | #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK) |
174 | #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK) | |
175 | #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK) | |
176 | #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK) | |
177 | #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK) | |
0644b628 JH |
178 | /* For sane SSE instruction set generation we need fcomi instruction. It is |
179 | safe to enable all CMOVE instructions. */ | |
180 | #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE) | |
1e993cb8 | 181 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
9e555526 RH |
182 | #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK) |
183 | #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK) | |
184 | #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK) | |
185 | #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT) | |
186 | #define TARGET_MOVX (x86_movx & TUNEMASK) | |
187 | #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK) | |
995cc369 | 188 | #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK) |
0e8c2b0d UB |
189 | #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK) |
190 | #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK) | |
9e555526 RH |
191 | #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK) |
192 | #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK) | |
193 | #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK) | |
194 | #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK) | |
195 | #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK) | |
196 | #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK) | |
197 | #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK) | |
198 | #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK) | |
199 | #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK) | |
200 | #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK) | |
201 | #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK) | |
202 | #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK) | |
203 | #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK) | |
204 | #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK) | |
205 | #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK) | |
206 | #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK) | |
207 | #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK) | |
208 | #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK) | |
4977bab6 | 209 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ |
9e555526 | 210 | (x86_sse_partial_reg_dependency & TUNEMASK) |
41afe4ef | 211 | #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK) |
9e555526 | 212 | #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK) |
9e555526 RH |
213 | #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK) |
214 | #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK) | |
215 | #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK) | |
216 | #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK) | |
f4365627 | 217 | #define TARGET_PREFETCH_SSE (x86_prefetch_sse) |
9e555526 RH |
218 | #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK) |
219 | #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK) | |
220 | #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK) | |
221 | #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK) | |
be04394b | 222 | #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK) |
ad7b96a9 | 223 | #define TARGET_SCHEDULE (x86_schedule & TUNEMASK) |
7cacf53e | 224 | #define TARGET_USE_BT (x86_use_bt & TUNEMASK) |
d326eaf0 JH |
225 | #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK) |
226 | #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK) | |
a269a03c | 227 | |
c93e80a5 | 228 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
e075ae69 | 229 | |
965f5423 JH |
230 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) |
231 | #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \ | |
232 | && (ix86_fpmath & FPMATH_387)) | |
4977bab6 | 233 | |
f996902d | 234 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) |
5bf5a10b AO |
235 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) |
236 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
f996902d RH |
237 | #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) |
238 | ||
1ef45b77 | 239 | #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch)) |
a0274e3e JJ |
240 | #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch)) |
241 | #define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch)) | |
1ef45b77 | 242 | #define TARGET_XADD (x86_xadd & (1 << ix86_arch)) |
167fa32c | 243 | #define TARGET_BSWAP (x86_bswap & (1 << ix86_arch)) |
1ef45b77 | 244 | |
67adf6a9 RH |
245 | #ifndef TARGET_64BIT_DEFAULT |
246 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 247 | #endif |
74dc3e94 RH |
248 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
249 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
250 | #endif | |
25f94bb5 | 251 | |
0ed4a390 JL |
252 | /* Once GDB has been enhanced to deal with functions without frame |
253 | pointers, we can change this to allow for elimination of | |
254 | the frame pointer in leaf functions. */ | |
255 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 256 | |
b069de3b SS |
257 | /* This is not really a target flag, but is done this way so that |
258 | it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
259 | redefines this to 1. */ | |
260 | #define TARGET_MACHO 0 | |
261 | ||
cc69336f RH |
262 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
263 | with the rounding mode forced to 53 bits. */ | |
264 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
265 | ||
f5316dfe MM |
266 | /* Sometimes certain combinations of command options do not make |
267 | sense on a particular target machine. You can define a macro | |
268 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
269 | defined, is executed once just after all the command options have | |
270 | been parsed. | |
271 | ||
272 | Don't use this macro to turn on various extra optimizations for | |
273 | `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
274 | ||
275 | #define OVERRIDE_OPTIONS override_options () | |
276 | ||
d4ba09c0 | 277 | /* Define this to change the optimizations performed by default. */ |
d9a5f180 GS |
278 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ |
279 | optimization_options ((LEVEL), (SIZE)) | |
d4ba09c0 | 280 | |
682cd442 GK |
281 | /* -march=native handling only makes sense with compiler running on |
282 | an x86 or x86_64 chip. If changing this condition, also change | |
283 | the condition in driver-i386.c. */ | |
284 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
285 | /* In driver-i386.c. */ |
286 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
287 | #define EXTRA_SPEC_FUNCTIONS \ | |
288 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 289 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
290 | #endif |
291 | ||
1cba2b96 EC |
292 | /* Support for configure-time defaults of some command line options. |
293 | The order here is important so that -march doesn't squash the | |
294 | tune or cpu values. */ | |
7816bea0 | 295 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 296 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
1cba2b96 EC |
297 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
298 | {"arch", "%{!march=*:-march=%(VALUE)}"} | |
7816bea0 | 299 | |
241e1a89 SC |
300 | /* Specs for the compiler proper */ |
301 | ||
628714d8 | 302 | #ifndef CC1_CPU_SPEC |
fa959ce4 | 303 | #define CC1_CPU_SPEC_1 "\ |
9d913bbf KC |
304 | %{!mtune*: \ |
305 | %{m386:mtune=i386 \ | |
306 | %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \ | |
307 | %{m486:-mtune=i486 \ | |
308 | %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \ | |
309 | %{mpentium:-mtune=pentium \ | |
310 | %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \ | |
311 | %{mpentiumpro:-mtune=pentiumpro \ | |
312 | %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \ | |
313 | %{mcpu=*:-mtune=%* \ | |
314 | %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \ | |
315 | %<mcpu=* \ | |
c93e80a5 JH |
316 | %{mintel-syntax:-masm=intel \ |
317 | %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
318 | %{mno-intel-syntax:-masm=att \ | |
319 | %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
fa959ce4 | 320 | |
682cd442 | 321 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
322 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
323 | #else | |
324 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
325 | "%{march=native:%<march=native %:local_cpu_detect(arch)} \ | |
326 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
327 | #endif | |
241e1a89 | 328 | #endif |
c98f8742 | 329 | \f |
30efe578 | 330 | /* Target CPU builtins. */ |
1ba7b414 NB |
331 | #define TARGET_CPU_CPP_BUILTINS() \ |
332 | do \ | |
333 | { \ | |
334 | size_t arch_len = strlen (ix86_arch_string); \ | |
9e555526 | 335 | size_t tune_len = strlen (ix86_tune_string); \ |
1ba7b414 | 336 | int last_arch_char = ix86_arch_string[arch_len - 1]; \ |
9e555526 | 337 | int last_tune_char = ix86_tune_string[tune_len - 1]; \ |
1ba7b414 NB |
338 | \ |
339 | if (TARGET_64BIT) \ | |
340 | { \ | |
341 | builtin_assert ("cpu=x86_64"); \ | |
26b0ad13 | 342 | builtin_assert ("machine=x86_64"); \ |
97242ddc JH |
343 | builtin_define ("__amd64"); \ |
344 | builtin_define ("__amd64__"); \ | |
1ba7b414 NB |
345 | builtin_define ("__x86_64"); \ |
346 | builtin_define ("__x86_64__"); \ | |
347 | } \ | |
348 | else \ | |
349 | { \ | |
350 | builtin_assert ("cpu=i386"); \ | |
351 | builtin_assert ("machine=i386"); \ | |
352 | builtin_define_std ("i386"); \ | |
353 | } \ | |
354 | \ | |
9d913bbf | 355 | /* Built-ins based on -mtune= (or -march= if no \ |
9e555526 | 356 | -mtune= given). */ \ |
1ba7b414 NB |
357 | if (TARGET_386) \ |
358 | builtin_define ("__tune_i386__"); \ | |
359 | else if (TARGET_486) \ | |
360 | builtin_define ("__tune_i486__"); \ | |
361 | else if (TARGET_PENTIUM) \ | |
362 | { \ | |
363 | builtin_define ("__tune_i586__"); \ | |
364 | builtin_define ("__tune_pentium__"); \ | |
9e555526 | 365 | if (last_tune_char == 'x') \ |
1ba7b414 NB |
366 | builtin_define ("__tune_pentium_mmx__"); \ |
367 | } \ | |
368 | else if (TARGET_PENTIUMPRO) \ | |
369 | { \ | |
370 | builtin_define ("__tune_i686__"); \ | |
371 | builtin_define ("__tune_pentiumpro__"); \ | |
9e555526 | 372 | switch (last_tune_char) \ |
2e37b0ce RH |
373 | { \ |
374 | case '3': \ | |
375 | builtin_define ("__tune_pentium3__"); \ | |
5efb1046 | 376 | /* FALLTHRU */ \ |
2e37b0ce RH |
377 | case '2': \ |
378 | builtin_define ("__tune_pentium2__"); \ | |
379 | break; \ | |
380 | } \ | |
1ba7b414 | 381 | } \ |
cfe1b18f VM |
382 | else if (TARGET_GEODE) \ |
383 | { \ | |
384 | builtin_define ("__tune_geode__"); \ | |
385 | } \ | |
1ba7b414 NB |
386 | else if (TARGET_K6) \ |
387 | { \ | |
388 | builtin_define ("__tune_k6__"); \ | |
9e555526 | 389 | if (last_tune_char == '2') \ |
1ba7b414 | 390 | builtin_define ("__tune_k6_2__"); \ |
9e555526 | 391 | else if (last_tune_char == '3') \ |
1ba7b414 NB |
392 | builtin_define ("__tune_k6_3__"); \ |
393 | } \ | |
394 | else if (TARGET_ATHLON) \ | |
395 | { \ | |
396 | builtin_define ("__tune_athlon__"); \ | |
397 | /* Only plain "athlon" lacks SSE. */ \ | |
9e555526 | 398 | if (last_tune_char != 'n') \ |
1ba7b414 NB |
399 | builtin_define ("__tune_athlon_sse__"); \ |
400 | } \ | |
4977bab6 ZW |
401 | else if (TARGET_K8) \ |
402 | builtin_define ("__tune_k8__"); \ | |
1ba7b414 NB |
403 | else if (TARGET_PENTIUM4) \ |
404 | builtin_define ("__tune_pentium4__"); \ | |
89c43c0a VM |
405 | else if (TARGET_NOCONA) \ |
406 | builtin_define ("__tune_nocona__"); \ | |
05f85dbb VM |
407 | else if (TARGET_CORE2) \ |
408 | builtin_define ("__tune_core2__"); \ | |
1ba7b414 NB |
409 | \ |
410 | if (TARGET_MMX) \ | |
411 | builtin_define ("__MMX__"); \ | |
412 | if (TARGET_3DNOW) \ | |
413 | builtin_define ("__3dNOW__"); \ | |
414 | if (TARGET_3DNOW_A) \ | |
415 | builtin_define ("__3dNOW_A__"); \ | |
416 | if (TARGET_SSE) \ | |
417 | builtin_define ("__SSE__"); \ | |
418 | if (TARGET_SSE2) \ | |
419 | builtin_define ("__SSE2__"); \ | |
9e200aaf KC |
420 | if (TARGET_SSE3) \ |
421 | builtin_define ("__SSE3__"); \ | |
b1875f52 L |
422 | if (TARGET_SSSE3) \ |
423 | builtin_define ("__SSSE3__"); \ | |
48ddd46c JH |
424 | if (TARGET_SSE_MATH && TARGET_SSE) \ |
425 | builtin_define ("__SSE_MATH__"); \ | |
426 | if (TARGET_SSE_MATH && TARGET_SSE2) \ | |
427 | builtin_define ("__SSE2_MATH__"); \ | |
1ba7b414 NB |
428 | \ |
429 | /* Built-ins based on -march=. */ \ | |
430 | if (ix86_arch == PROCESSOR_I486) \ | |
431 | { \ | |
432 | builtin_define ("__i486"); \ | |
433 | builtin_define ("__i486__"); \ | |
434 | } \ | |
435 | else if (ix86_arch == PROCESSOR_PENTIUM) \ | |
436 | { \ | |
437 | builtin_define ("__i586"); \ | |
438 | builtin_define ("__i586__"); \ | |
439 | builtin_define ("__pentium"); \ | |
440 | builtin_define ("__pentium__"); \ | |
441 | if (last_arch_char == 'x') \ | |
442 | builtin_define ("__pentium_mmx__"); \ | |
443 | } \ | |
444 | else if (ix86_arch == PROCESSOR_PENTIUMPRO) \ | |
445 | { \ | |
446 | builtin_define ("__i686"); \ | |
447 | builtin_define ("__i686__"); \ | |
448 | builtin_define ("__pentiumpro"); \ | |
449 | builtin_define ("__pentiumpro__"); \ | |
450 | } \ | |
cfe1b18f VM |
451 | else if (ix86_arch == PROCESSOR_GEODE) \ |
452 | { \ | |
453 | builtin_define ("__geode"); \ | |
454 | builtin_define ("__geode__"); \ | |
455 | } \ | |
1ba7b414 NB |
456 | else if (ix86_arch == PROCESSOR_K6) \ |
457 | { \ | |
458 | \ | |
459 | builtin_define ("__k6"); \ | |
460 | builtin_define ("__k6__"); \ | |
461 | if (last_arch_char == '2') \ | |
462 | builtin_define ("__k6_2__"); \ | |
463 | else if (last_arch_char == '3') \ | |
464 | builtin_define ("__k6_3__"); \ | |
465 | } \ | |
466 | else if (ix86_arch == PROCESSOR_ATHLON) \ | |
467 | { \ | |
468 | builtin_define ("__athlon"); \ | |
469 | builtin_define ("__athlon__"); \ | |
470 | /* Only plain "athlon" lacks SSE. */ \ | |
471 | if (last_arch_char != 'n') \ | |
472 | builtin_define ("__athlon_sse__"); \ | |
473 | } \ | |
4977bab6 ZW |
474 | else if (ix86_arch == PROCESSOR_K8) \ |
475 | { \ | |
476 | builtin_define ("__k8"); \ | |
477 | builtin_define ("__k8__"); \ | |
478 | } \ | |
1ba7b414 NB |
479 | else if (ix86_arch == PROCESSOR_PENTIUM4) \ |
480 | { \ | |
481 | builtin_define ("__pentium4"); \ | |
482 | builtin_define ("__pentium4__"); \ | |
483 | } \ | |
89c43c0a VM |
484 | else if (ix86_arch == PROCESSOR_NOCONA) \ |
485 | { \ | |
486 | builtin_define ("__nocona"); \ | |
487 | builtin_define ("__nocona__"); \ | |
488 | } \ | |
05f85dbb VM |
489 | else if (ix86_arch == PROCESSOR_CORE2) \ |
490 | { \ | |
491 | builtin_define ("__core2"); \ | |
492 | builtin_define ("__core2__"); \ | |
493 | } \ | |
1ba7b414 | 494 | } \ |
30efe578 NB |
495 | while (0) |
496 | ||
f4365627 JH |
497 | #define TARGET_CPU_DEFAULT_i386 0 |
498 | #define TARGET_CPU_DEFAULT_i486 1 | |
499 | #define TARGET_CPU_DEFAULT_pentium 2 | |
91d2f4ba JH |
500 | #define TARGET_CPU_DEFAULT_pentium_mmx 3 |
501 | #define TARGET_CPU_DEFAULT_pentiumpro 4 | |
502 | #define TARGET_CPU_DEFAULT_pentium2 5 | |
503 | #define TARGET_CPU_DEFAULT_pentium3 6 | |
504 | #define TARGET_CPU_DEFAULT_pentium4 7 | |
cfe1b18f VM |
505 | #define TARGET_CPU_DEFAULT_geode 8 |
506 | #define TARGET_CPU_DEFAULT_k6 9 | |
507 | #define TARGET_CPU_DEFAULT_k6_2 10 | |
508 | #define TARGET_CPU_DEFAULT_k6_3 11 | |
509 | #define TARGET_CPU_DEFAULT_athlon 12 | |
510 | #define TARGET_CPU_DEFAULT_athlon_sse 13 | |
511 | #define TARGET_CPU_DEFAULT_k8 14 | |
512 | #define TARGET_CPU_DEFAULT_pentium_m 15 | |
513 | #define TARGET_CPU_DEFAULT_prescott 16 | |
514 | #define TARGET_CPU_DEFAULT_nocona 17 | |
05f85dbb VM |
515 | #define TARGET_CPU_DEFAULT_core2 18 |
516 | #define TARGET_CPU_DEFAULT_generic 19 | |
f4365627 JH |
517 | |
518 | #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\ | |
519 | "pentiumpro", "pentium2", "pentium3", \ | |
cfe1b18f | 520 | "pentium4", "geode", "k6", "k6-2", "k6-3", \ |
5bbeea44 | 521 | "athlon", "athlon-4", "k8", \ |
d326eaf0 | 522 | "pentium-m", "prescott", "nocona", \ |
05f85dbb | 523 | "core2", "generic"} |
0c2dc519 | 524 | |
628714d8 | 525 | #ifndef CC1_SPEC |
8015b78d | 526 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
527 | #endif |
528 | ||
529 | /* This macro defines names of additional specifications to put in the | |
530 | specs that can be used in various specifications like CC1_SPEC. Its | |
531 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
532 | |
533 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 534 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
535 | program. |
536 | ||
537 | Do not define this macro if it does not need to do anything. */ | |
538 | ||
539 | #ifndef SUBTARGET_EXTRA_SPECS | |
540 | #define SUBTARGET_EXTRA_SPECS | |
541 | #endif | |
542 | ||
543 | #define EXTRA_SPECS \ | |
628714d8 | 544 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
545 | SUBTARGET_EXTRA_SPECS |
546 | \f | |
c98f8742 JVA |
547 | /* target machine storage layout */ |
548 | ||
968a7562 | 549 | #define LONG_DOUBLE_TYPE_SIZE 80 |
2b589241 | 550 | |
d57a4b98 RH |
551 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
552 | FPU, assume that the fpcw is set to extended precision; when using | |
553 | only SSE, rounding is correct; when using both SSE and the FPU, | |
554 | the rounding precision is indeterminate, since either may be chosen | |
555 | apparently at random. */ | |
556 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 557 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 558 | |
65d9c0ab JH |
559 | #define SHORT_TYPE_SIZE 16 |
560 | #define INT_TYPE_SIZE 32 | |
561 | #define FLOAT_TYPE_SIZE 32 | |
562 | #define LONG_TYPE_SIZE BITS_PER_WORD | |
65d9c0ab JH |
563 | #define DOUBLE_TYPE_SIZE 64 |
564 | #define LONG_LONG_TYPE_SIZE 64 | |
565 | ||
67adf6a9 | 566 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 567 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
568 | #else |
569 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
570 | #endif |
571 | ||
c98f8742 JVA |
572 | /* Define this if most significant byte of a word is the lowest numbered. */ |
573 | /* That is true on the 80386. */ | |
574 | ||
575 | #define BITS_BIG_ENDIAN 0 | |
576 | ||
577 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
578 | /* That is not true on the 80386. */ | |
579 | #define BYTES_BIG_ENDIAN 0 | |
580 | ||
581 | /* Define this if most significant word of a multiword number is the lowest | |
582 | numbered. */ | |
583 | /* Not true for 80386 */ | |
584 | #define WORDS_BIG_ENDIAN 0 | |
585 | ||
c98f8742 | 586 | /* Width of a word, in units (bytes). */ |
65d9c0ab | 587 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
2e64c636 JH |
588 | #ifdef IN_LIBGCC2 |
589 | #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
590 | #else | |
591 | #define MIN_UNITS_PER_WORD 4 | |
592 | #endif | |
c98f8742 | 593 | |
c98f8742 | 594 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 595 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 596 | |
e075ae69 | 597 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
65d9c0ab | 598 | #define STACK_BOUNDARY BITS_PER_WORD |
c98f8742 | 599 | |
d1f87653 | 600 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 601 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 602 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 603 | |
ead903e9 | 604 | /* As of July 2001, many runtimes do not align the stack properly when |
d1f87653 | 605 | entering main. This causes expand_main_function to forcibly align |
1d482056 RH |
606 | the stack, which results in aligned frames for functions called from |
607 | main, though it does nothing for the alignment of main itself. */ | |
608 | #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \ | |
14f73b5a | 609 | (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT) |
1d482056 | 610 | |
f963b5d9 RS |
611 | /* Minimum allocation boundary for the code of a function. */ |
612 | #define FUNCTION_BOUNDARY 8 | |
613 | ||
614 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
615 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 616 | |
892a2d68 | 617 | /* Alignment of field after `int : 0' in a structure. */ |
c98f8742 | 618 | |
65d9c0ab | 619 | #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD |
c98f8742 JVA |
620 | |
621 | /* Minimum size in bits of the largest boundary to which any | |
622 | and all fundamental data types supported by the hardware | |
623 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 624 | rounder than this. |
fce5a9f2 | 625 | |
d1f87653 | 626 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
627 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
628 | ||
629 | #define BIGGEST_ALIGNMENT 128 | |
630 | ||
822eda12 | 631 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 632 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 633 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 634 | |
17f24ff0 | 635 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 636 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 637 | -malign-double is set. */ |
e932b21b | 638 | |
e83f3cff RH |
639 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
640 | supports no vector modes, cut out the complexity and fall back | |
641 | on BIGGEST_FIELD_ALIGNMENT. */ | |
642 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
643 | #ifdef __x86_64__ |
644 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
645 | #else | |
e83f3cff | 646 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 647 | #endif |
e83f3cff | 648 | #else |
e932b21b JH |
649 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
650 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 651 | #endif |
c98f8742 | 652 | |
e5e8a8bf | 653 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 654 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
655 | and ALIGN is the alignment that the object would ordinarily have. |
656 | The value of this macro is used instead of that alignment to align | |
657 | the object. | |
658 | ||
659 | If this macro is not defined, then ALIGN is used. | |
660 | ||
661 | The typical use of this macro is to increase alignment for string | |
662 | constants to be word aligned so that `strcpy' calls that copy | |
663 | constants can be done inline. */ | |
664 | ||
d9a5f180 | 665 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 666 | |
8a022443 JW |
667 | /* If defined, a C expression to compute the alignment for a static |
668 | variable. TYPE is the data type, and ALIGN is the alignment that | |
669 | the object would ordinarily have. The value of this macro is used | |
670 | instead of that alignment to align the object. | |
671 | ||
672 | If this macro is not defined, then ALIGN is used. | |
673 | ||
674 | One use of this macro is to increase alignment of medium-size | |
675 | data to make it all fit in fewer cache lines. Another is to | |
676 | cause character arrays to be word-aligned so that `strcpy' calls | |
677 | that copy constants to character arrays can be done inline. */ | |
678 | ||
d9a5f180 | 679 | #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) |
d16790f2 JW |
680 | |
681 | /* If defined, a C expression to compute the alignment for a local | |
682 | variable. TYPE is the data type, and ALIGN is the alignment that | |
683 | the object would ordinarily have. The value of this macro is used | |
684 | instead of that alignment to align the object. | |
685 | ||
686 | If this macro is not defined, then ALIGN is used. | |
687 | ||
688 | One use of this macro is to increase alignment of medium-size | |
689 | data to make it all fit in fewer cache lines. */ | |
690 | ||
d9a5f180 | 691 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN)) |
8a022443 | 692 | |
53c17031 JH |
693 | /* If defined, a C expression that gives the alignment boundary, in |
694 | bits, of an argument with the specified mode and type. If it is | |
695 | not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
696 | ||
d9a5f180 GS |
697 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ |
698 | ix86_function_arg_boundary ((MODE), (TYPE)) | |
53c17031 | 699 | |
9cd10576 | 700 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 701 | when given unaligned data. */ |
b4ac57ab | 702 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
703 | |
704 | /* If bit field type is int, don't let it cross an int, | |
705 | and give entire struct the alignment of an int. */ | |
43a88a8c | 706 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 707 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
708 | \f |
709 | /* Standard register usage. */ | |
710 | ||
711 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 712 | for details. */ |
c98f8742 JVA |
713 | |
714 | #define STACK_REGS | |
d9a5f180 | 715 | #define IS_STACK_MODE(MODE) \ |
b5c82fa1 PB |
716 | (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ |
717 | || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
718 | || (MODE) == XFmode) | |
c98f8742 JVA |
719 | |
720 | /* Number of actual hardware registers. | |
721 | The hardware registers are assigned numbers for the compiler | |
722 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
723 | All registers that the compiler knows about must be given numbers, | |
724 | even those that are not normally considered general registers. | |
725 | ||
726 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
727 | We number the floating point registers 8-15. | |
728 | Note that registers 0-7 can be accessed as a short or int, | |
729 | while only 0-3 may be used with byte `mov' instructions. | |
730 | ||
731 | Reg 16 does not correspond to any hardware register, but instead | |
732 | appears in the RTL as an argument pointer prior to reload, and is | |
733 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 734 | pointer. */ |
c98f8742 | 735 | |
03c259ad | 736 | #define FIRST_PSEUDO_REGISTER 54 |
c98f8742 | 737 | |
3073d01c ML |
738 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
739 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
740 | ||
741 | #define DWARF_FRAME_REGISTERS 17 | |
742 | ||
c98f8742 JVA |
743 | /* 1 for registers that have pervasive standard uses |
744 | and are not available for the register allocator. | |
3f3f2124 | 745 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 746 | |
3a4416fb RS |
747 | The value is zero if the register is not fixed on either 32 or |
748 | 64 bit targets, one if the register if fixed on both 32 and 64 | |
749 | bit targets, two if it is only fixed on 32bit targets and three | |
750 | if its only fixed on 64bit targets. | |
751 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
3f3f2124 | 752 | */ |
a7180f70 BS |
753 | #define FIXED_REGISTERS \ |
754 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 755 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
03c259ad UB |
756 | /*arg,flags,fpsr,fpcr,dir,frame*/ \ |
757 | 1, 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
758 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
759 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
760 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ | |
3f3f2124 JH |
761 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
762 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
3a4416fb | 763 | 2, 2, 2, 2, 2, 2, 2, 2, \ |
3f3f2124 | 764 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3a4416fb | 765 | 2, 2, 2, 2, 2, 2, 2, 2} |
fce5a9f2 | 766 | |
c98f8742 JVA |
767 | |
768 | /* 1 for registers not available across function calls. | |
769 | These must include the FIXED_REGISTERS and also any | |
770 | registers that can be used without being saved. | |
771 | The latter must include the registers where values are returned | |
772 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
773 | Aside from that, you can include as many other registers as you like. |
774 | ||
9d72d996 JJ |
775 | The value is zero if the register is not call used on either 32 or |
776 | 64 bit targets, one if the register if call used on both 32 and 64 | |
777 | bit targets, two if it is only call used on 32bit targets and three | |
778 | if its only call used on 64bit targets. | |
3a4416fb | 779 | Proper values are computed in the CONDITIONAL_REGISTER_USAGE. |
3f3f2124 | 780 | */ |
a7180f70 BS |
781 | #define CALL_USED_REGISTERS \ |
782 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 783 | { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
03c259ad UB |
784 | /*arg,flags,fpsr,fpcr,dir,frame*/ \ |
785 | 1, 1, 1, 1, 1, 1, \ | |
a7180f70 | 786 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
03c259ad | 787 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
a7180f70 | 788 | /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \ |
3a4416fb | 789 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 790 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 791 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 792 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3a4416fb | 793 | 1, 1, 1, 1, 1, 1, 1, 1} \ |
c98f8742 | 794 | |
3b3c6a3f MM |
795 | /* Order in which to allocate registers. Each register must be |
796 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
797 | late and fixed registers last. Note that, in general, we prefer | |
798 | registers listed in CALL_USED_REGISTERS, keeping the others | |
799 | available for storage of persistent values. | |
800 | ||
162f023b JH |
801 | The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, |
802 | so this is just empty initializer for array. */ | |
3b3c6a3f | 803 | |
162f023b JH |
804 | #define REG_ALLOC_ORDER \ |
805 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
806 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
807 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
03c259ad | 808 | 48, 49, 50, 51, 52, 53 } |
3b3c6a3f | 809 | |
162f023b JH |
810 | /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order |
811 | to be rearranged based on a particular function. When using sse math, | |
03c259ad | 812 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 813 | |
162f023b | 814 | #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () |
3b3c6a3f | 815 | |
f5316dfe | 816 | |
c98f8742 | 817 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
a7180f70 | 818 | #define CONDITIONAL_REGISTER_USAGE \ |
d9a5f180 | 819 | do { \ |
3f3f2124 JH |
820 | int i; \ |
821 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
822 | { \ | |
3a4416fb RS |
823 | if (fixed_regs[i] > 1) \ |
824 | fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \ | |
825 | if (call_used_regs[i] > 1) \ | |
826 | call_used_regs[i] = (call_used_regs[i] \ | |
827 | == (TARGET_64BIT ? 3 : 2)); \ | |
3f3f2124 | 828 | } \ |
5b43fed1 | 829 | if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ |
a7180f70 BS |
830 | { \ |
831 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
832 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
833 | } \ | |
834 | if (! TARGET_MMX) \ | |
835 | { \ | |
836 | int i; \ | |
837 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
838 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \ | |
33270999 | 839 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
a7180f70 BS |
840 | } \ |
841 | if (! TARGET_SSE) \ | |
842 | { \ | |
843 | int i; \ | |
844 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
845 | if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \ | |
33270999 | 846 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
a7180f70 BS |
847 | } \ |
848 | if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ | |
849 | { \ | |
850 | int i; \ | |
851 | HARD_REG_SET x; \ | |
852 | COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ | |
853 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ | |
854 | if (TEST_HARD_REG_BIT (x, i)) \ | |
33270999 AO |
855 | fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \ |
856 | } \ | |
857 | if (! TARGET_64BIT) \ | |
858 | { \ | |
859 | int i; \ | |
860 | for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \ | |
861 | reg_names[i] = ""; \ | |
862 | for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \ | |
863 | reg_names[i] = ""; \ | |
a7180f70 | 864 | } \ |
d9a5f180 | 865 | } while (0) |
c98f8742 JVA |
866 | |
867 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
868 | to hold something of mode MODE. | |
869 | This is ordinarily the length in words of a value of mode MODE | |
870 | but can be less for certain modes in special long registers. | |
871 | ||
fce5a9f2 | 872 | Actually there are no two word move instructions for consecutive |
c98f8742 JVA |
873 | registers. And only registers 0-3 may have mov byte instructions |
874 | applied to them. | |
875 | */ | |
876 | ||
877 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
92d0fb09 JH |
878 | (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
879 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 | 880 | : ((MODE) == XFmode \ |
92d0fb09 | 881 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 882 | : (MODE) == XCmode \ |
92d0fb09 | 883 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 884 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 885 | |
fbe5eb6d BS |
886 | #define VALID_SSE2_REG_MODE(MODE) \ |
887 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
6c4ccfd8 | 888 | || (MODE) == V2DImode || (MODE) == DFmode) |
fbe5eb6d | 889 | |
d9a5f180 GS |
890 | #define VALID_SSE_REG_MODE(MODE) \ |
891 | ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
dcbca208 | 892 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 893 | |
47f339cf BS |
894 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
895 | ((MODE) == V2SFmode || (MODE) == SFmode) | |
896 | ||
d9a5f180 GS |
897 | #define VALID_MMX_REG_MODE(MODE) \ |
898 | ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \ | |
a7180f70 BS |
899 | || (MODE) == V2SImode || (MODE) == SImode) |
900 | ||
accde4cf RH |
901 | /* ??? No autovectorization into MMX or 3DNOW until we can reliably |
902 | place emms and femms instructions. */ | |
c4336539 | 903 | #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD) |
0bf43309 | 904 | |
d9a5f180 | 905 | #define VALID_FP_MODE_P(MODE) \ |
f8a1ebc6 JH |
906 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
907 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 908 | |
d9a5f180 GS |
909 | #define VALID_INT_MODE_P(MODE) \ |
910 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
911 | || (MODE) == DImode \ | |
912 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
913 | || (MODE) == CDImode \ | |
f8a1ebc6 JH |
914 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ |
915 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 916 | |
822eda12 JH |
917 | /* Return true for modes passed in SSE registers. */ |
918 | #define SSE_REG_MODE_P(MODE) \ | |
f8a1ebc6 | 919 | ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ |
822eda12 JH |
920 | || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ |
921 | || (MODE) == V4SFmode || (MODE) == V4SImode) | |
922 | ||
e075ae69 | 923 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 924 | |
a946dd00 | 925 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 926 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
927 | |
928 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
929 | when one has mode MODE1 and one has mode MODE2. | |
930 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
931 | for any hard reg, then this must be 0 for correct output. */ | |
932 | ||
c1c5b5e3 | 933 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 934 | |
ff25ef99 ZD |
935 | /* It is possible to write patterns to move flags; but until someone |
936 | does it, */ | |
937 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 938 | |
e075ae69 | 939 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 940 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 941 | |
787dc842 JH |
942 | Kill any attempts to combine saving of modes. */ |
943 | ||
d9a5f180 GS |
944 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
945 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
946 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
fee226d2 | 947 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\ |
d9a5f180 GS |
948 | : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ |
949 | : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \ | |
d2836273 | 950 | : (MODE)) |
c98f8742 JVA |
951 | /* Specify the registers used for certain standard purposes. |
952 | The values of these macros are register numbers. */ | |
953 | ||
954 | /* on the 386 the pc register is %eip, and is not usable as a general | |
955 | register. The ordinary mov instructions won't work */ | |
956 | /* #define PC_REGNUM */ | |
957 | ||
958 | /* Register to use for pushing function arguments. */ | |
959 | #define STACK_POINTER_REGNUM 7 | |
960 | ||
961 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
962 | #define HARD_FRAME_POINTER_REGNUM 6 |
963 | ||
964 | /* Base register for access to local variables of the function. */ | |
03c259ad | 965 | #define FRAME_POINTER_REGNUM 21 |
c98f8742 JVA |
966 | |
967 | /* First floating point reg */ | |
968 | #define FIRST_FLOAT_REG 8 | |
969 | ||
970 | /* First & last stack-like regs */ | |
971 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
972 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
973 | ||
a7180f70 BS |
974 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
975 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 976 | |
a7180f70 BS |
977 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) |
978 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
979 | ||
3f3f2124 JH |
980 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) |
981 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
982 | ||
983 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
984 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
985 | ||
c98f8742 JVA |
986 | /* Value should be nonzero if functions must have frame pointers. |
987 | Zero means the frame pointer need not be set up (and parms | |
988 | may be accessed via the stack pointer) in functions that seem suitable. | |
989 | This is computed in `reload', in reload1.c. */ | |
6fca22eb RH |
990 | #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () |
991 | ||
aabcd309 | 992 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
993 | requiring a frame pointer. */ |
994 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
995 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
996 | #endif | |
997 | ||
998 | /* Make sure we can access arbitrary call frames. */ | |
999 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1000 | |
1001 | /* Base register for access to arguments of the function. */ | |
1002 | #define ARG_POINTER_REGNUM 16 | |
1003 | ||
d2836273 JH |
1004 | /* Register in which static-chain is passed to a function. |
1005 | We do use ECX as static chain register for 32 bit ABI. On the | |
1006 | 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
1007 | #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2) | |
c98f8742 JVA |
1008 | |
1009 | /* Register to hold the addressing base for position independent | |
5b43fed1 RH |
1010 | code access to data items. We don't use PIC pointer for 64bit |
1011 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1012 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1013 | |
1014 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1015 | the pic register when possible. The change is visible after the | |
1016 | prologue has been emitted. */ | |
1017 | ||
1018 | #define REAL_PIC_OFFSET_TABLE_REGNUM 3 | |
1019 | ||
1020 | #define PIC_OFFSET_TABLE_REGNUM \ | |
7dcbf659 JH |
1021 | ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ |
1022 | || !flag_pic ? INVALID_REGNUM \ | |
bd09bdeb RH |
1023 | : reload_completed ? REGNO (pic_offset_table_rtx) \ |
1024 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1025 | |
5fc0e5df KW |
1026 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1027 | ||
713225d4 MM |
1028 | /* A C expression which can inhibit the returning of certain function |
1029 | values in registers, based on the type of value. A nonzero value | |
1030 | says to return the function value in memory, just as large | |
1031 | structures are always returned. Here TYPE will be a C expression | |
1032 | of type `tree', representing the data type of the value. | |
1033 | ||
1034 | Note that values of mode `BLKmode' must be explicitly handled by | |
1035 | this macro. Also, the option `-fpcc-struct-return' takes effect | |
1036 | regardless of this macro. On most systems, it is possible to | |
1037 | leave the macro undefined; this causes a default definition to be | |
1038 | used, whose value is the constant 1 for `BLKmode' values, and 0 | |
1039 | otherwise. | |
1040 | ||
1041 | Do not use this macro to indicate that structures and unions | |
1042 | should always be returned in memory. You should instead use | |
1043 | `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ | |
1044 | ||
d9a5f180 | 1045 | #define RETURN_IN_MEMORY(TYPE) \ |
53c17031 | 1046 | ix86_return_in_memory (TYPE) |
713225d4 | 1047 | |
c51e6d85 | 1048 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1049 | #define MS_AGGREGATE_RETURN 0 |
1050 | ||
61fec9ff JB |
1051 | /* This is overridden by <netware.h>. */ |
1052 | #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
c98f8742 JVA |
1053 | \f |
1054 | /* Define the classes of registers for register constraints in the | |
1055 | machine description. Also define ranges of constants. | |
1056 | ||
1057 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1058 | If there is more than one class, another class must be named NO_REGS | |
1059 | and contain no registers. | |
1060 | ||
1061 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1062 | another name such as ALL_REGS). This is the class of registers | |
1063 | that is allowed by "g" or "r" in a register constraint. | |
1064 | Also, registers outside this class are allocated only when | |
1065 | instructions express preferences for them. | |
1066 | ||
1067 | The classes must be numbered in nondecreasing order; that is, | |
1068 | a larger-numbered class must never be contained completely | |
1069 | in a smaller-numbered class. | |
1070 | ||
1071 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1072 | class that represents their union. |
1073 | ||
1074 | It might seem that class BREG is unnecessary, since no useful 386 | |
1075 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1076 | and the "b" register constraint is useful in asms for syscalls. |
1077 | ||
03c259ad | 1078 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1079 | |
1080 | enum reg_class | |
1081 | { | |
1082 | NO_REGS, | |
e075ae69 | 1083 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1084 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1085 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1086 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1087 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 JH |
1088 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
1089 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
c98f8742 JVA |
1090 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1091 | FLOAT_REGS, | |
a7180f70 BS |
1092 | SSE_REGS, |
1093 | MMX_REGS, | |
446988df JH |
1094 | FP_TOP_SSE_REGS, |
1095 | FP_SECOND_SSE_REGS, | |
1096 | FLOAT_SSE_REGS, | |
1097 | FLOAT_INT_REGS, | |
1098 | INT_SSE_REGS, | |
1099 | FLOAT_INT_SSE_REGS, | |
c98f8742 JVA |
1100 | ALL_REGS, LIM_REG_CLASSES |
1101 | }; | |
1102 | ||
d9a5f180 GS |
1103 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1104 | ||
1105 | #define INTEGER_CLASS_P(CLASS) \ | |
1106 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1107 | #define FLOAT_CLASS_P(CLASS) \ | |
1108 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1109 | #define SSE_CLASS_P(CLASS) \ | |
f75959a6 | 1110 | ((CLASS) == SSE_REGS) |
d9a5f180 | 1111 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1112 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1113 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1114 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1115 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1116 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1117 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1118 | reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1119 | #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1120 | reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1121 | ||
1122 | #define Q_CLASS_P(CLASS) \ | |
1123 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1124 | |
43f3a59d | 1125 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1126 | |
1127 | #define REG_CLASS_NAMES \ | |
1128 | { "NO_REGS", \ | |
ab408a86 | 1129 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1130 | "SIREG", "DIREG", \ |
e075ae69 RH |
1131 | "AD_REGS", \ |
1132 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1133 | "INDEX_REGS", \ |
3f3f2124 | 1134 | "LEGACY_REGS", \ |
c98f8742 JVA |
1135 | "GENERAL_REGS", \ |
1136 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1137 | "FLOAT_REGS", \ | |
a7180f70 BS |
1138 | "SSE_REGS", \ |
1139 | "MMX_REGS", \ | |
446988df JH |
1140 | "FP_TOP_SSE_REGS", \ |
1141 | "FP_SECOND_SSE_REGS", \ | |
1142 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1143 | "FLOAT_INT_REGS", \ |
446988df JH |
1144 | "INT_SSE_REGS", \ |
1145 | "FLOAT_INT_SSE_REGS", \ | |
c98f8742 JVA |
1146 | "ALL_REGS" } |
1147 | ||
1148 | /* Define which registers fit in which classes. | |
1149 | This is an initializer for a vector of HARD_REG_SET | |
1150 | of length N_REG_CLASSES. */ | |
1151 | ||
a7180f70 | 1152 | #define REG_CLASS_CONTENTS \ |
3f3f2124 JH |
1153 | { { 0x00, 0x0 }, \ |
1154 | { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1155 | { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1156 | { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1157 | { 0x03, 0x0 }, /* AD_REGS */ \ | |
1158 | { 0x0f, 0x0 }, /* Q_REGS */ \ | |
03c259ad UB |
1159 | { 0x2100f0, 0x3fc0 }, /* NON_Q_REGS */ \ |
1160 | { 0x7f, 0x3fc0 }, /* INDEX_REGS */ \ | |
1161 | { 0x2100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1162 | { 0x2100ff, 0x3fc0 }, /* GENERAL_REGS */ \ | |
3f3f2124 JH |
1163 | { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ |
1164 | { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
03c259ad UB |
1165 | { 0x3fc00000,0x3fc000 }, /* SSE_REGS */ \ |
1166 | { 0xc0000000, 0x3f }, /* MMX_REGS */ \ | |
1167 | { 0x3fc00100,0x3fc000 }, /* FP_TOP_SSE_REG */ \ | |
1168 | { 0x3fc00200,0x3fc000 }, /* FP_SECOND_SSE_REG */ \ | |
1169 | { 0x3fc0ff00,0x3fc000 }, /* FLOAT_SSE_REGS */ \ | |
1170 | { 0x1ffff, 0x3fc0 }, /* FLOAT_INT_REGS */ \ | |
1171 | { 0x3fc100ff,0x3fffc0 }, /* INT_SSE_REGS */ \ | |
1172 | { 0x3fc1ffff,0x3fffc0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1173 | { 0xffffffff,0x3fffff } \ | |
e075ae69 | 1174 | } |
c98f8742 JVA |
1175 | |
1176 | /* The same information, inverted: | |
1177 | Return the class number of the smallest class containing | |
1178 | reg number REGNO. This could be a conditional expression | |
1179 | or could index an array. */ | |
1180 | ||
c98f8742 JVA |
1181 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1182 | ||
1183 | /* When defined, the compiler allows registers explicitly used in the | |
1184 | rtl to be used as spill registers but prevents the compiler from | |
892a2d68 | 1185 | extending the lifetime of these registers. */ |
c98f8742 | 1186 | |
2922fe9e | 1187 | #define SMALL_REGISTER_CLASSES 1 |
c98f8742 | 1188 | |
fb84c7a0 | 1189 | #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4) |
3f3f2124 | 1190 | |
d9a5f180 | 1191 | #define GENERAL_REGNO_P(N) \ |
fb84c7a0 | 1192 | ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) |
3f3f2124 JH |
1193 | |
1194 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1195 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
3f3f2124 JH |
1196 | |
1197 | #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1198 | ||
c98f8742 | 1199 | #define NON_QI_REG_P(X) \ |
fb84c7a0 | 1200 | (REG_P (X) && IN_RANGE (REGNO (X), 4, FIRST_PSEUDO_REGISTER - 1)) |
c98f8742 | 1201 | |
fb84c7a0 UB |
1202 | #define REX_INT_REGNO_P(N) \ |
1203 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 JH |
1204 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
1205 | ||
c98f8742 | 1206 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) |
fb84c7a0 | 1207 | #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) |
446988df | 1208 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
d9a5f180 | 1209 | #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1210 | |
fb84c7a0 UB |
1211 | #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) |
1212 | #define SSE_REGNO_P(N) \ | |
1213 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
1214 | || REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1215 | |
4977bab6 | 1216 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1217 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1218 | |
d9a5f180 GS |
1219 | #define SSE_REGNO(N) \ |
1220 | ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
446988df | 1221 | |
d9a5f180 | 1222 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1223 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1224 | |
d9a5f180 | 1225 | #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) |
fb84c7a0 | 1226 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1227 | |
fb84c7a0 UB |
1228 | #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) |
1229 | #define NON_STACK_REG_P(XOP) \ | |
1230 | (REG_P (XOP) && ! STACK_REGNO_P (REGNO (XOP))) | |
1231 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
c98f8742 | 1232 | |
d9a5f180 | 1233 | #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) |
c98f8742 | 1234 | |
e075ae69 RH |
1235 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1236 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1237 | ||
c98f8742 JVA |
1238 | /* The class value for index registers, and the one for base regs. */ |
1239 | ||
1240 | #define INDEX_REG_CLASS INDEX_REGS | |
1241 | #define BASE_REG_CLASS GENERAL_REGS | |
1242 | ||
c98f8742 | 1243 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1244 | is necessary to be able to hold a value of mode MODE in a reload |
892a2d68 | 1245 | register for which class CLASS would ordinarily be used. */ |
c98f8742 | 1246 | |
d2836273 JH |
1247 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
1248 | ((MODE) == QImode && !TARGET_64BIT \ | |
3b8d200e JJ |
1249 | && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ |
1250 | || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
c98f8742 JVA |
1251 | ? Q_REGS : (CLASS)) |
1252 | ||
1253 | /* Given an rtx X being reloaded into a reg required to be | |
1254 | in class CLASS, return the class of reg to actually use. | |
1255 | In general this is just CLASS; but on some machines | |
1256 | in some cases it is preferable to use a more restrictive class. | |
1257 | On the 80386 series, we prevent floating constants from being | |
1258 | reloaded into floating registers (since no move-insn can do that) | |
1259 | and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1260 | ||
d398b3b1 | 1261 | /* Put float CONST_DOUBLE in the constant pool instead of fp regs. |
c98f8742 | 1262 | QImode must go into class Q_REGS. |
d398b3b1 | 1263 | Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and |
892a2d68 | 1264 | movdf to do mem-to-mem moves through integer regs. */ |
c98f8742 | 1265 | |
d9a5f180 GS |
1266 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
1267 | ix86_preferred_reload_class ((X), (CLASS)) | |
85ff473e | 1268 | |
b5c82fa1 PB |
1269 | /* Discourage putting floating-point values in SSE registers unless |
1270 | SSE math is being used, and likewise for the 387 registers. */ | |
1271 | ||
1272 | #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
1273 | ix86_preferred_output_reload_class ((X), (CLASS)) | |
1274 | ||
85ff473e | 1275 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1276 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1277 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1278 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 RH |
1279 | |
1280 | /* QImode spills from non-QI registers need a scratch. This does not | |
fce5a9f2 | 1281 | happen often -- the only example so far requires an uninitialized |
e075ae69 RH |
1282 | pseudo. */ |
1283 | ||
d9a5f180 | 1284 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ |
3b8d200e JJ |
1285 | (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \ |
1286 | || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \ | |
d2836273 | 1287 | ? Q_REGS : NO_REGS) |
c98f8742 JVA |
1288 | |
1289 | /* Return the maximum number of consecutive registers | |
1290 | needed to represent mode MODE in a register of class CLASS. */ | |
1291 | /* On the 80386, this is the size of MODE in words, | |
f8a1ebc6 | 1292 | except in the FP regs, where a single reg is always enough. */ |
a7180f70 | 1293 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
92d0fb09 JH |
1294 | (!MAYBE_INTEGER_CLASS_P (CLASS) \ |
1295 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
f8a1ebc6 JH |
1296 | : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ |
1297 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
f5316dfe MM |
1298 | |
1299 | /* A C expression whose value is nonzero if pseudos that have been | |
1300 | assigned to registers of class CLASS would likely be spilled | |
1301 | because registers of CLASS are needed for spill registers. | |
1302 | ||
1303 | The default value of this macro returns 1 if CLASS has exactly one | |
1304 | register and zero otherwise. On most machines, this default | |
1305 | should be used. Only define this macro to some other expression | |
1306 | if pseudo allocated by `local-alloc.c' end up in memory because | |
ddd5a7c1 | 1307 | their hard registers were needed for spill registers. If this |
f5316dfe MM |
1308 | macro returns nonzero for those classes, those pseudos will only |
1309 | be allocated by `global.c', which knows how to reallocate the | |
1310 | pseudo to another register. If there would not be another | |
1311 | register available for reallocation, you should not change the | |
1312 | definition of this macro since the only effect of such a | |
1313 | definition would be to slow down register allocation. */ | |
1314 | ||
1315 | #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1316 | (((CLASS) == AREG) \ | |
1317 | || ((CLASS) == DREG) \ | |
1318 | || ((CLASS) == CREG) \ | |
1319 | || ((CLASS) == BREG) \ | |
1320 | || ((CLASS) == AD_REGS) \ | |
1321 | || ((CLASS) == SIREG) \ | |
b0af5c03 JH |
1322 | || ((CLASS) == DIREG) \ |
1323 | || ((CLASS) == FP_TOP_REG) \ | |
1324 | || ((CLASS) == FP_SECOND_REG)) | |
f5316dfe | 1325 | |
1272914c RH |
1326 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1327 | ||
1328 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1329 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1330 | \f |
1331 | /* Stack layout; function entry, exit and calling. */ | |
1332 | ||
1333 | /* Define this if pushing a word on the stack | |
1334 | makes the stack pointer a smaller address. */ | |
1335 | #define STACK_GROWS_DOWNWARD | |
1336 | ||
a4d05547 | 1337 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1338 | is at the high-address end of the local variables; |
1339 | that is, each additional local variable allocated | |
1340 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1341 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1342 | |
1343 | /* Offset within stack frame to start allocating local variables at. | |
1344 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1345 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1346 | of the first local allocated. */ | |
1347 | #define STARTING_FRAME_OFFSET 0 | |
1348 | ||
1349 | /* If we generate an insn to push BYTES bytes, | |
1350 | this says how many the stack pointer really advances by. | |
6541fe75 JJ |
1351 | On 386, we have pushw instruction that decrements by exactly 2 no |
1352 | matter what the position was, there is no pushb. | |
1353 | But as CIE data alignment factor on this arch is -4, we need to make | |
1354 | sure all stack pointer adjustments are in multiple of 4. | |
fce5a9f2 | 1355 | |
d2836273 JH |
1356 | For 64bit ABI we round up to 8 bytes. |
1357 | */ | |
c98f8742 | 1358 | |
d2836273 JH |
1359 | #define PUSH_ROUNDING(BYTES) \ |
1360 | (TARGET_64BIT \ | |
1361 | ? (((BYTES) + 7) & (-8)) \ | |
6541fe75 | 1362 | : (((BYTES) + 3) & (-4))) |
c98f8742 | 1363 | |
f73ad30e JH |
1364 | /* If defined, the maximum amount of space required for outgoing arguments will |
1365 | be computed and placed into the variable | |
1366 | `current_function_outgoing_args_size'. No space will be pushed onto the | |
1367 | stack for each call; instead, the function prologue should increase the stack | |
1368 | frame size by this amount. */ | |
1369 | ||
1370 | #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS | |
1371 | ||
1372 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1373 | instructions to pass outgoing arguments. */ | |
1374 | ||
1375 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1376 | ||
2da4124d L |
1377 | /* We want the stack and args grow in opposite directions, even if |
1378 | PUSH_ARGS is 0. */ | |
1379 | #define PUSH_ARGS_REVERSED 1 | |
1380 | ||
c98f8742 JVA |
1381 | /* Offset of first parameter from the argument pointer register value. */ |
1382 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1383 | ||
a7180f70 BS |
1384 | /* Define this macro if functions should assume that stack space has been |
1385 | allocated for arguments even when their values are passed in registers. | |
1386 | ||
1387 | The value of this macro is the size, in bytes, of the area reserved for | |
1388 | arguments passed in registers for the function represented by FNDECL. | |
1389 | ||
1390 | This space can be allocated by the caller, or be a part of the | |
1391 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1392 | which. */ | |
1393 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
1394 | ||
c98f8742 JVA |
1395 | /* Value is the number of bytes of arguments automatically |
1396 | popped when returning from a subroutine call. | |
8b109b37 | 1397 | FUNDECL is the declaration node of the function (as a tree), |
c98f8742 JVA |
1398 | FUNTYPE is the data type of the function (as a tree), |
1399 | or for a library call it is an identifier node for the subroutine name. | |
1400 | SIZE is the number of bytes of arguments passed on the stack. | |
1401 | ||
1402 | On the 80386, the RTD insn may be used to pop them if the number | |
1403 | of args is fixed, but if the number is variable then the caller | |
1404 | must pop them all. RTD can't be used for library calls now | |
1405 | because the library is compiled with the Unix compiler. | |
1406 | Use of RTD is a selectable option, since it is incompatible with | |
1407 | standard Unix calling sequences. If the option is not selected, | |
b08de47e MM |
1408 | the caller must always pop the args. |
1409 | ||
1410 | The attribute stdcall is equivalent to RTD on a per module basis. */ | |
c98f8742 | 1411 | |
d9a5f180 GS |
1412 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ |
1413 | ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
c98f8742 | 1414 | |
53c17031 JH |
1415 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1416 | ix86_function_value_regno_p (N) | |
c98f8742 JVA |
1417 | |
1418 | /* Define how to find the value returned by a library function | |
1419 | assuming the value has mode MODE. */ | |
1420 | ||
1421 | #define LIBCALL_VALUE(MODE) \ | |
53c17031 | 1422 | ix86_libcall_value (MODE) |
c98f8742 | 1423 | |
e9125c09 TW |
1424 | /* Define the size of the result block used for communication between |
1425 | untyped_call and untyped_return. The block contains a DImode value | |
1426 | followed by the block used by fnsave and frstor. */ | |
1427 | ||
1428 | #define APPLY_RESULT_SIZE (8+108) | |
1429 | ||
b08de47e | 1430 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1431 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1432 | |
1433 | /* Define a data type for recording info about an argument list | |
1434 | during the scan of that argument list. This data type should | |
1435 | hold all necessary information about the function itself | |
1436 | and about the args processed so far, enough to enable macros | |
b08de47e | 1437 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1438 | |
e075ae69 | 1439 | typedef struct ix86_args { |
b08de47e MM |
1440 | int nregs; /* # registers available for passing */ |
1441 | int regno; /* next available register number */ | |
47a37ce4 | 1442 | int words; /* # words passed so far */ |
9d72d996 | 1443 | int fastcall; /* fastcall calling convention is used */ |
47a37ce4 UB |
1444 | int x87_nregs; /* # x87 registers available for passing */ |
1445 | int x87_regno; /* # next available x87 register number */ | |
a7180f70 BS |
1446 | int sse_nregs; /* # sse registers available for passing */ |
1447 | int sse_regno; /* next available sse register number */ | |
47a37ce4 | 1448 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
bcf17554 JH |
1449 | int mmx_nregs; /* # mmx registers available for passing */ |
1450 | int mmx_regno; /* next available mmx register number */ | |
47a37ce4 | 1451 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
892a2d68 | 1452 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
47a37ce4 UB |
1453 | int float_in_x87; /* 1 if floating point arguments should |
1454 | be passed in 80387 registere. */ | |
2f84b963 RG |
1455 | int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should |
1456 | be passed in SSE registers. Otherwise 0. */ | |
b08de47e | 1457 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1458 | |
1459 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1460 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1461 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1462 | |
0f6937fe | 1463 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
dafc5b82 | 1464 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) |
c98f8742 JVA |
1465 | |
1466 | /* Update the data in CUM to advance over an argument | |
1467 | of mode MODE and data type TYPE. | |
1468 | (TYPE is null for libcalls where that information may not be available.) */ | |
1469 | ||
d9a5f180 GS |
1470 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
1471 | function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
c98f8742 JVA |
1472 | |
1473 | /* Define where to put the arguments to a function. | |
1474 | Value is zero to push the argument on the stack, | |
1475 | or a hard register in which to store the argument. | |
1476 | ||
1477 | MODE is the argument's machine mode. | |
1478 | TYPE is the data type of the argument (as a tree). | |
1479 | This is null for libcalls where that information may | |
1480 | not be available. | |
1481 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1482 | the preceding args and about the function being called. | |
1483 | NAMED is nonzero if this argument is a named parameter | |
1484 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1485 | ||
c98f8742 | 1486 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
d9a5f180 | 1487 | function_arg (&(CUM), (MODE), (TYPE), (NAMED)) |
c98f8742 | 1488 | |
ad919812 | 1489 | /* Implement `va_start' for varargs and stdarg. */ |
e5faf155 ZW |
1490 | #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \ |
1491 | ix86_va_start (VALIST, NEXTARG) | |
ad919812 | 1492 | |
a5fe455b ZW |
1493 | #define TARGET_ASM_FILE_END ix86_file_end |
1494 | #define NEED_INDICATE_EXEC_STACK 0 | |
3a0433fd | 1495 | |
c98f8742 JVA |
1496 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1497 | for profiling a function entry. */ | |
1498 | ||
a5fa1ecd JH |
1499 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1500 | ||
1501 | #define MCOUNT_NAME "_mcount" | |
1502 | ||
1503 | #define PROFILE_COUNT_REGISTER "edx" | |
c98f8742 JVA |
1504 | |
1505 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1506 | the stack pointer does not matter. The value is tested only in | |
1507 | functions that have frame pointers. | |
1508 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1509 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1510 | we have to restore it ourselves from the frame pointer, in order to |
1511 | use pop */ | |
1512 | ||
1513 | #define EXIT_IGNORE_STACK 1 | |
1514 | ||
c98f8742 JVA |
1515 | /* Output assembler code for a block containing the constant parts |
1516 | of a trampoline, leaving space for the variable parts. */ | |
1517 | ||
a269a03c | 1518 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1519 | mov #STATIC,ecx |
a269a03c JC |
1520 | jmp FUNCTION |
1521 | The trampoline is generated entirely at runtime. The operand of JMP | |
1522 | is the address of FUNCTION relative to the instruction following the | |
1523 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1524 | |
1525 | /* Length in units of the trampoline for entering a nested function. */ | |
1526 | ||
39d04363 | 1527 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) |
c98f8742 JVA |
1528 | |
1529 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1530 | FNADDR is an RTX for the address of the function's pure code. | |
1531 | CXT is an RTX for the static chain value for the function. */ | |
1532 | ||
d9a5f180 GS |
1533 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
1534 | x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
c98f8742 JVA |
1535 | \f |
1536 | /* Definitions for register eliminations. | |
1537 | ||
1538 | This is an array of structures. Each structure initializes one pair | |
1539 | of eliminable registers. The "from" register number is given first, | |
1540 | followed by "to". Eliminations of the same "from" register are listed | |
1541 | in order of preference. | |
1542 | ||
afc2cd05 NC |
1543 | There are two registers that can always be eliminated on the i386. |
1544 | The frame pointer and the arg pointer can be replaced by either the | |
1545 | hard frame pointer or to the stack pointer, depending upon the | |
1546 | circumstances. The hard frame pointer is not used before reload and | |
1547 | so it is not eligible for elimination. */ | |
c98f8742 | 1548 | |
564d80f4 JH |
1549 | #define ELIMINABLE_REGS \ |
1550 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1551 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1552 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1553 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1554 | |
2c5a510c RH |
1555 | /* Given FROM and TO register numbers, say whether this elimination is |
1556 | allowed. Frame pointer elimination is automatically handled. | |
c98f8742 JVA |
1557 | |
1558 | All other eliminations are valid. */ | |
1559 | ||
2c5a510c RH |
1560 | #define CAN_ELIMINATE(FROM, TO) \ |
1561 | ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) | |
c98f8742 JVA |
1562 | |
1563 | /* Define the offset between two registers, one to be eliminated, and the other | |
1564 | its replacement, at the start of a routine. */ | |
1565 | ||
d9a5f180 GS |
1566 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1567 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1568 | \f |
1569 | /* Addressing modes, and classification of registers for them. */ | |
1570 | ||
c98f8742 JVA |
1571 | /* Macros to check register numbers against specific register classes. */ |
1572 | ||
1573 | /* These assume that REGNO is a hard or pseudo reg number. | |
1574 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1575 | or a pseudo reg currently allocated to a suitable hard reg. | |
1576 | Since they use reg_renumber, they are safe only once reg_renumber | |
1577 | has been allocated, which happens in local-alloc.c. */ | |
1578 | ||
3f3f2124 JH |
1579 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1580 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1581 | || REX_INT_REGNO_P (REGNO) \ |
1582 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1583 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1584 | |
3f3f2124 | 1585 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1586 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1587 | || (REGNO) == ARG_POINTER_REGNUM \ |
1588 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1589 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1590 | |
d9a5f180 GS |
1591 | #define REGNO_OK_FOR_SIREG_P(REGNO) \ |
1592 | ((REGNO) == 4 || reg_renumber[(REGNO)] == 4) | |
1593 | #define REGNO_OK_FOR_DIREG_P(REGNO) \ | |
1594 | ((REGNO) == 5 || reg_renumber[(REGNO)] == 5) | |
c98f8742 JVA |
1595 | |
1596 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1597 | and check its validity for a certain class. | |
1598 | We have two alternate definitions for each of them. | |
1599 | The usual definition accepts all pseudo regs; the other rejects | |
1600 | them unless they have been allocated suitable hard regs. | |
1601 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1602 | ||
1603 | Most source files want to accept pseudo regs in the hope that | |
1604 | they will get allocated to the class that the insn wants them to be in. | |
1605 | Source files for reload pass need to be strict. | |
1606 | After reload, it makes no difference, since pseudo regs have | |
1607 | been eliminated by then. */ | |
1608 | ||
c98f8742 | 1609 | |
ff482c8d | 1610 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1611 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1612 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1613 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1614 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1615 | ||
3b3c6a3f | 1616 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1617 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1618 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1619 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1620 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1621 | |
3b3c6a3f MM |
1622 | /* Strict versions, hard registers only */ |
1623 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1624 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1625 | |
3b3c6a3f | 1626 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1627 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1628 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1629 | |
1630 | #else | |
d9a5f180 GS |
1631 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1632 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1633 | #endif |
1634 | ||
1635 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1636 | that is a valid memory address for an instruction. | |
1637 | The MODE argument is the machine mode for the MEM expression | |
1638 | that wants to use this address. | |
1639 | ||
1640 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1641 | except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1642 | ||
1643 | See legitimize_pic_address in i386.c for details as to what | |
1644 | constitutes a legitimate address when -fpic is used. */ | |
1645 | ||
1646 | #define MAX_REGS_PER_ADDRESS 2 | |
1647 | ||
f996902d | 1648 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 JVA |
1649 | |
1650 | /* Nonzero if the constant value X is a legitimate general operand. | |
1651 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1652 | ||
f996902d | 1653 | #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) |
c98f8742 | 1654 | |
3b3c6a3f MM |
1655 | #ifdef REG_OK_STRICT |
1656 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1657 | do { \ |
1658 | if (legitimate_address_p ((MODE), (X), 1)) \ | |
3b3c6a3f | 1659 | goto ADDR; \ |
d9a5f180 | 1660 | } while (0) |
c98f8742 | 1661 | |
3b3c6a3f MM |
1662 | #else |
1663 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
d9a5f180 GS |
1664 | do { \ |
1665 | if (legitimate_address_p ((MODE), (X), 0)) \ | |
c98f8742 | 1666 | goto ADDR; \ |
d9a5f180 | 1667 | } while (0) |
c98f8742 | 1668 | |
3b3c6a3f MM |
1669 | #endif |
1670 | ||
b949ea8b JW |
1671 | /* If defined, a C expression to determine the base term of address X. |
1672 | This macro is used in only one place: `find_base_term' in alias.c. | |
1673 | ||
1674 | It is always safe for this macro to not be defined. It exists so | |
1675 | that alias analysis can understand machine-dependent addresses. | |
1676 | ||
1677 | The typical use of this macro is to handle addresses containing | |
1678 | a label_ref or symbol_ref within an UNSPEC. */ | |
1679 | ||
d9a5f180 | 1680 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1681 | |
c98f8742 JVA |
1682 | /* Try machine-dependent ways of modifying an illegitimate address |
1683 | to be legitimate. If we find one, return the new, valid address. | |
1684 | This macro is used in only one place: `memory_address' in explow.c. | |
1685 | ||
1686 | OLDX is the address as it was before break_out_memory_refs was called. | |
1687 | In some cases it is useful to look at this to decide what needs to be done. | |
1688 | ||
1689 | MODE and WIN are passed so that this macro can use | |
1690 | GO_IF_LEGITIMATE_ADDRESS. | |
1691 | ||
1692 | It is always safe for this macro to do nothing. It exists to recognize | |
1693 | opportunities to optimize the output. | |
1694 | ||
1695 | For the 80386, we handle X+REG by loading X into a register R and | |
1696 | using R+REG. R will go in a general reg and indexing will be used. | |
1697 | However, if REG is a broken-out memory address or multiplication, | |
1698 | nothing needs to be done because REG can certainly go in a general reg. | |
1699 | ||
1700 | When -fpic is used, special handling is needed for symbolic references. | |
1701 | See comments by legitimize_pic_address in i386.c for details. */ | |
1702 | ||
3b3c6a3f | 1703 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
d9a5f180 GS |
1704 | do { \ |
1705 | (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1706 | if (memory_address_p ((MODE), (X))) \ | |
3b3c6a3f | 1707 | goto WIN; \ |
d9a5f180 | 1708 | } while (0) |
c98f8742 | 1709 | |
d9a5f180 | 1710 | #define REWRITE_ADDRESS(X) rewrite_address (X) |
d4ba09c0 | 1711 | |
c98f8742 | 1712 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1713 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1714 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1715 | ||
f996902d | 1716 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1717 | |
1718 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1719 | (GET_CODE (X) == SYMBOL_REF \ |
1720 | || GET_CODE (X) == LABEL_REF \ | |
1721 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 JVA |
1722 | |
1723 | /* Go to LABEL if ADDR (a legitimate address expression) | |
1724 | has an effect that depends on the machine mode it is used for. | |
1725 | On the 80386, only postdecrement and postincrement address depend thus | |
1726 | (the amount of decrement or increment being the length of the operand). */ | |
d9a5f180 GS |
1727 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
1728 | do { \ | |
1729 | if (GET_CODE (ADDR) == POST_INC \ | |
1730 | || GET_CODE (ADDR) == POST_DEC) \ | |
1731 | goto LABEL; \ | |
1732 | } while (0) | |
c98f8742 | 1733 | \f |
b08de47e MM |
1734 | /* Max number of args passed in registers. If this is more than 3, we will |
1735 | have problems with ebx (register #4), since it is a caller save register and | |
1736 | is also used as the pic register in ELF. So for now, don't allow more than | |
1737 | 3 registers to be passed in registers. */ | |
1738 | ||
d2836273 JH |
1739 | #define REGPARM_MAX (TARGET_64BIT ? 6 : 3) |
1740 | ||
47a37ce4 UB |
1741 | #define X87_REGPARM_MAX 3 |
1742 | ||
bcf17554 JH |
1743 | #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0)) |
1744 | ||
1745 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
b08de47e | 1746 | |
c98f8742 JVA |
1747 | \f |
1748 | /* Specify the machine mode that this machine uses | |
1749 | for the index in the tablejump instruction. */ | |
6eb791fc | 1750 | #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode) |
c98f8742 | 1751 | |
c98f8742 JVA |
1752 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1753 | #define DEFAULT_SIGNED_CHAR 1 | |
1754 | ||
1755 | /* Max number of bytes we can move from memory to memory | |
1756 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1757 | #define MOVE_MAX 16 |
1758 | ||
1759 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1760 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1761 | number of bytes we can move with a single instruction. */ |
65d9c0ab | 1762 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
c98f8742 | 1763 | |
7e24ffc9 | 1764 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1765 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1766 | Increasing the value will always make code faster, but eventually |
1767 | incurs high cost in increased code size. | |
c98f8742 | 1768 | |
e2e52e1b | 1769 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1770 | |
e2e52e1b | 1771 | #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio) |
c98f8742 | 1772 | |
45d78e7f JJ |
1773 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1774 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1775 | ||
1776 | #define CLEAR_RATIO (optimize_size ? 2 \ | |
1777 | : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio) | |
1778 | ||
c98f8742 JVA |
1779 | /* Define if shifts truncate the shift count |
1780 | which implies one can omit a sign-extension or zero-extension | |
1781 | of a shift count. */ | |
892a2d68 | 1782 | /* On i386, shifts do truncate the count. But bit opcodes don't. */ |
c98f8742 JVA |
1783 | |
1784 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1785 | ||
1786 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1787 | is done just by pretending it is already truncated. */ | |
1788 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1789 | ||
d9f32422 JH |
1790 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1791 | TYPE and which has the specified mode and signedness is to be | |
1792 | stored in a register. This macro is only called when TYPE is a | |
1793 | scalar type. | |
1794 | ||
f710504c | 1795 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1796 | quantities to SImode. The choice depends on target type. */ |
1797 | ||
1798 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1799 | do { \ |
d9f32422 JH |
1800 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1801 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1802 | (MODE) = SImode; \ |
1803 | } while (0) | |
d9f32422 | 1804 | |
c98f8742 JVA |
1805 | /* Specify the machine mode that pointers have. |
1806 | After generation of rtl, the compiler makes no further distinction | |
1807 | between pointers and any other objects of this machine mode. */ | |
65d9c0ab | 1808 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
c98f8742 JVA |
1809 | |
1810 | /* A function address in a call instruction | |
1811 | is a byte address (for indexing purposes) | |
1812 | so give the MEM rtx a byte's mode. */ | |
1813 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1814 | \f |
96e7ae40 JH |
1815 | /* A C expression for the cost of moving data from a register in class FROM to |
1816 | one in class TO. The classes are expressed using the enumeration values | |
1817 | such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
1818 | interpreted relative to that. | |
d4ba09c0 | 1819 | |
96e7ae40 JH |
1820 | It is not required that the cost always equal 2 when FROM is the same as TO; |
1821 | on some machines it is expensive to move between registers if they are not | |
f84aa48a | 1822 | general registers. */ |
d4ba09c0 | 1823 | |
f84aa48a | 1824 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
d9a5f180 | 1825 | ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) |
d4ba09c0 SC |
1826 | |
1827 | /* A C expression for the cost of moving data of mode M between a | |
1828 | register and memory. A value of 2 is the default; this cost is | |
1829 | relative to those in `REGISTER_MOVE_COST'. | |
1830 | ||
1831 | If moving between registers and memory is more expensive than | |
1832 | between two registers, you should define this macro to express the | |
fa79946e | 1833 | relative cost. */ |
d4ba09c0 | 1834 | |
d9a5f180 GS |
1835 | #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ |
1836 | ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
d4ba09c0 SC |
1837 | |
1838 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1839 | is the default; other values are interpreted relative to that. */ | |
1840 | ||
e075ae69 | 1841 | #define BRANCH_COST ix86_branch_cost |
d4ba09c0 SC |
1842 | |
1843 | /* Define this macro as a C expression which is nonzero if accessing | |
1844 | less than a word of memory (i.e. a `char' or a `short') is no | |
1845 | faster than accessing a word of memory, i.e., if such access | |
1846 | require more than one instruction or if there is no difference in | |
1847 | cost between byte and (aligned) word loads. | |
1848 | ||
1849 | When this macro is not defined, the compiler will access a field by | |
1850 | finding the smallest containing object; when it is defined, a | |
1851 | fullword load will be used if alignment permits. Unless bytes | |
1852 | accesses are faster than word accesses, using word accesses is | |
1853 | preferable since it may eliminate subsequent memory access if | |
1854 | subsequent accesses occur to other fields in the same word of the | |
1855 | structure, but to different bytes. */ | |
1856 | ||
1857 | #define SLOW_BYTE_ACCESS 0 | |
1858 | ||
1859 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1860 | #define SLOW_SHORT_ACCESS 0 | |
1861 | ||
d4ba09c0 SC |
1862 | /* Define this macro to be the value 1 if unaligned accesses have a |
1863 | cost many times greater than aligned accesses, for example if they | |
1864 | are emulated in a trap handler. | |
1865 | ||
9cd10576 KH |
1866 | When this macro is nonzero, the compiler will act as if |
1867 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 1868 | moves. This can cause significantly more instructions to be |
9cd10576 | 1869 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
1870 | accesses only add a cycle or two to the time for a memory access. |
1871 | ||
1872 | If the value of this macro is always zero, it need not be defined. */ | |
1873 | ||
e1565e65 | 1874 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 1875 | |
d4ba09c0 SC |
1876 | /* Define this macro if it is as good or better to call a constant |
1877 | function address than to call an address kept in a register. | |
1878 | ||
1879 | Desirable on the 386 because a CALL with a constant address is | |
1880 | faster than one with a register address. */ | |
1881 | ||
1882 | #define NO_FUNCTION_CSE | |
c98f8742 | 1883 | \f |
c572e5ba JVA |
1884 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1885 | return the mode to be used for the comparison. | |
1886 | ||
1887 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 1888 | VOIDmode should be used in all other cases. |
c572e5ba | 1889 | |
16189740 | 1890 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 1891 | possible, to allow for more combinations. */ |
c98f8742 | 1892 | |
d9a5f180 | 1893 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 1894 | |
9cd10576 | 1895 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
1896 | reversed. */ |
1897 | ||
1898 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1899 | ||
1900 | /* A C expression whose value is reversed condition code of the CODE for | |
1901 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 1902 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 1903 | |
c98f8742 JVA |
1904 | \f |
1905 | /* Control the assembler format that we output, to the extent | |
1906 | this does not vary between assemblers. */ | |
1907 | ||
1908 | /* How to refer to registers in assembler output. | |
892a2d68 | 1909 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 1910 | |
21bf822e | 1911 | /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e". |
c98f8742 JVA |
1912 | For non floating point regs, the following are the HImode names. |
1913 | ||
1914 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
a55f4481 | 1915 | instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ |
c98f8742 | 1916 | |
a7180f70 BS |
1917 | #define HI_REGISTER_NAMES \ |
1918 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 1919 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
03c259ad | 1920 | "argp", "flags", "fpsr", "fpcr", "dirflag", "frame", \ |
a7180f70 | 1921 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 1922 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 JH |
1923 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
1924 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
a7180f70 | 1925 | |
c98f8742 JVA |
1926 | #define REGISTER_NAMES HI_REGISTER_NAMES |
1927 | ||
1928 | /* Table of additional register names to use in user input. */ | |
1929 | ||
1930 | #define ADDITIONAL_REGISTER_NAMES \ | |
54d26233 MH |
1931 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
1932 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
3f3f2124 JH |
1933 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ |
1934 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
54d26233 | 1935 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ |
21bf822e | 1936 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } |
c98f8742 JVA |
1937 | |
1938 | /* Note we are omitting these since currently I don't know how | |
1939 | to get gcc to use these, since they want the same but different | |
1940 | number as al, and ax. | |
1941 | */ | |
1942 | ||
c98f8742 | 1943 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 1944 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
1945 | |
1946 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 1947 | of regs 0 through 3. */ |
c98f8742 JVA |
1948 | |
1949 | #define QI_HIGH_REGISTER_NAMES \ | |
1950 | {"ah", "dh", "ch", "bh", } | |
1951 | ||
1952 | /* How to renumber registers for dbx and gdb. */ | |
1953 | ||
d9a5f180 GS |
1954 | #define DBX_REGISTER_NUMBER(N) \ |
1955 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 1956 | |
9a82e702 MS |
1957 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
1958 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
1959 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 1960 | |
469ac993 JM |
1961 | /* Before the prologue, RA is at 0(%esp). */ |
1962 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 1963 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 1964 | |
e414ab29 | 1965 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
1966 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1967 | ((COUNT) == 0 \ | |
1968 | ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
1969 | : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
e414ab29 | 1970 | |
892a2d68 | 1971 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 1972 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 1973 | |
a6ab3aad | 1974 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 1975 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 1976 | |
1020a5ab RH |
1977 | /* Describe how we implement __builtin_eh_return. */ |
1978 | #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
1979 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
1980 | ||
ad919812 | 1981 | |
e4c4ebeb RH |
1982 | /* Select a format to encode pointers in exception handling data. CODE |
1983 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1984 | true if the symbol may be affected by dynamic relocations. | |
1985 | ||
1986 | ??? All x86 object file formats are capable of representing this. | |
1987 | After all, the relocation needed is the same as for the call insn. | |
1988 | Whether or not a particular assembler allows us to enter such, I | |
1989 | guess we'll have to see. */ | |
d9a5f180 | 1990 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 1991 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 1992 | |
c98f8742 JVA |
1993 | /* This is how to output an insn to push a register on the stack. |
1994 | It need not be very fast code. */ | |
1995 | ||
d9a5f180 | 1996 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
1997 | do { \ |
1998 | if (TARGET_64BIT) \ | |
1999 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2000 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2001 | else \ | |
2002 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2003 | } while (0) | |
c98f8742 JVA |
2004 | |
2005 | /* This is how to output an insn to pop a register from the stack. | |
2006 | It need not be very fast code. */ | |
2007 | ||
d9a5f180 | 2008 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2009 | do { \ |
2010 | if (TARGET_64BIT) \ | |
2011 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2012 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2013 | else \ | |
2014 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2015 | } while (0) | |
c98f8742 | 2016 | |
f88c65f7 | 2017 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2018 | |
2019 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2020 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2021 | |
f88c65f7 | 2022 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2023 | |
33f7f353 | 2024 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2025 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2026 | |
f7288899 EC |
2027 | /* Under some conditions we need jump tables in the text section, |
2028 | because the assembler cannot handle label differences between | |
2029 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2030 | |
2031 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2032 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2033 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2034 | |
cea3bd3e RH |
2035 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2036 | and switch back. For x86 we do this only to save a few bytes that | |
2037 | would otherwise be unused in the text section. */ | |
2038 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2039 | asm (SECTION_OP "\n\t" \ | |
2040 | "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2041 | TEXT_SECTION_ASM_OP); | |
74b42c8b | 2042 | \f |
c98f8742 JVA |
2043 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2044 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
ef6257cd JH |
2045 | Effect of various CODE letters is described in i386.c near |
2046 | print_operand function. */ | |
c98f8742 | 2047 | |
d9a5f180 | 2048 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
f996902d | 2049 | ((CODE) == '*' || (CODE) == '+' || (CODE) == '&') |
c98f8742 JVA |
2050 | |
2051 | #define PRINT_OPERAND(FILE, X, CODE) \ | |
d9a5f180 | 2052 | print_operand ((FILE), (X), (CODE)) |
c98f8742 JVA |
2053 | |
2054 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
d9a5f180 | 2055 | print_operand_address ((FILE), (ADDR)) |
c98f8742 | 2056 | |
f996902d RH |
2057 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ |
2058 | do { \ | |
2059 | if (! output_addr_const_extra (FILE, (X))) \ | |
2060 | goto FAIL; \ | |
2061 | } while (0); | |
2062 | ||
c98f8742 JVA |
2063 | /* a letter which is not needed by the normal asm syntax, which |
2064 | we can use for operand syntax in the extended asm */ | |
2065 | ||
2066 | #define ASM_OPERAND_LETTER '#' | |
c98f8742 | 2067 | #define RET return "" |
d9a5f180 | 2068 | #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx)) |
d4ba09c0 | 2069 | \f |
5bf0ebab RH |
2070 | /* Which processor to schedule for. The cpu attribute defines a list that |
2071 | mirrors this list, so changes to i386.md must be made at the same time. */ | |
2072 | ||
2073 | enum processor_type | |
2074 | { | |
2075 | PROCESSOR_I386, /* 80386 */ | |
2076 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
2077 | PROCESSOR_PENTIUM, | |
2078 | PROCESSOR_PENTIUMPRO, | |
cfe1b18f | 2079 | PROCESSOR_GEODE, |
5bf0ebab RH |
2080 | PROCESSOR_K6, |
2081 | PROCESSOR_ATHLON, | |
2082 | PROCESSOR_PENTIUM4, | |
4977bab6 | 2083 | PROCESSOR_K8, |
89c43c0a | 2084 | PROCESSOR_NOCONA, |
05f85dbb | 2085 | PROCESSOR_CORE2, |
d326eaf0 JH |
2086 | PROCESSOR_GENERIC32, |
2087 | PROCESSOR_GENERIC64, | |
5bf0ebab RH |
2088 | PROCESSOR_max |
2089 | }; | |
2090 | ||
9e555526 | 2091 | extern enum processor_type ix86_tune; |
5bf0ebab | 2092 | extern enum processor_type ix86_arch; |
5bf0ebab RH |
2093 | |
2094 | enum fpmath_unit | |
2095 | { | |
2096 | FPMATH_387 = 1, | |
2097 | FPMATH_SSE = 2 | |
2098 | }; | |
2099 | ||
2100 | extern enum fpmath_unit ix86_fpmath; | |
5bf0ebab | 2101 | |
f996902d RH |
2102 | enum tls_dialect |
2103 | { | |
2104 | TLS_DIALECT_GNU, | |
5bf5a10b | 2105 | TLS_DIALECT_GNU2, |
f996902d RH |
2106 | TLS_DIALECT_SUN |
2107 | }; | |
2108 | ||
2109 | extern enum tls_dialect ix86_tls_dialect; | |
f996902d | 2110 | |
6189a572 | 2111 | enum cmodel { |
5bf0ebab RH |
2112 | CM_32, /* The traditional 32-bit ABI. */ |
2113 | CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2114 | CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2115 | CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2116 | CM_LARGE, /* No assumptions. */ | |
7dcbf659 JH |
2117 | CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ |
2118 | CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */ | |
6189a572 JH |
2119 | }; |
2120 | ||
5bf0ebab | 2121 | extern enum cmodel ix86_cmodel; |
5bf0ebab | 2122 | |
8362f420 JH |
2123 | /* Size of the RED_ZONE area. */ |
2124 | #define RED_ZONE_SIZE 128 | |
2125 | /* Reserved area of the red zone for temporaries. */ | |
2126 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 JH |
2127 | |
2128 | enum asm_dialect { | |
2129 | ASM_ATT, | |
2130 | ASM_INTEL | |
2131 | }; | |
5bf0ebab | 2132 | |
80f33d06 | 2133 | extern enum asm_dialect ix86_asm_dialect; |
95899b34 | 2134 | extern unsigned int ix86_preferred_stack_boundary; |
7dcbf659 | 2135 | extern int ix86_branch_cost, ix86_section_threshold; |
5bf0ebab RH |
2136 | |
2137 | /* Smallest class containing REGNO. */ | |
2138 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2139 | ||
d9a5f180 GS |
2140 | extern rtx ix86_compare_op0; /* operand 0 for comparisons */ |
2141 | extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
1ef45b77 | 2142 | extern rtx ix86_compare_emitted; |
22fb740d JH |
2143 | \f |
2144 | /* To properly truncate FP values into integers, we need to set i387 control | |
2145 | word. We can't emit proper mode switching code before reload, as spills | |
2146 | generated by reload may truncate values incorrectly, but we still can avoid | |
2147 | redundant computation of new control word by the mode switching pass. | |
2148 | The fldcw instructions are still emitted redundantly, but this is probably | |
2149 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2150 | the sequence. |
22fb740d JH |
2151 | |
2152 | The machinery is to emit simple truncation instructions and split them | |
2153 | before reload to instructions having USEs of two memory locations that | |
2154 | are filled by this code to old and new control word. | |
fce5a9f2 | 2155 | |
22fb740d JH |
2156 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2157 | needed. */ | |
2158 | ||
ff680eb1 UB |
2159 | enum ix86_entity |
2160 | { | |
2161 | I387_TRUNC = 0, | |
2162 | I387_FLOOR, | |
2163 | I387_CEIL, | |
2164 | I387_MASK_PM, | |
2165 | MAX_386_ENTITIES | |
2166 | }; | |
2167 | ||
1cba2b96 | 2168 | enum ix86_stack_slot |
ff680eb1 UB |
2169 | { |
2170 | SLOT_TEMP = 0, | |
2171 | SLOT_CW_STORED, | |
2172 | SLOT_CW_TRUNC, | |
2173 | SLOT_CW_FLOOR, | |
2174 | SLOT_CW_CEIL, | |
2175 | SLOT_CW_MASK_PM, | |
2176 | MAX_386_STACK_LOCALS | |
2177 | }; | |
22fb740d JH |
2178 | |
2179 | /* Define this macro if the port needs extra instructions inserted | |
2180 | for mode switching in an optimizing compilation. */ | |
2181 | ||
ff680eb1 UB |
2182 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2183 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2184 | |
2185 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2186 | initializer for an array of integers. Each initializer element N | |
2187 | refers to an entity that needs mode switching, and specifies the | |
2188 | number of different modes that might need to be set for this | |
2189 | entity. The position of the initializer in the initializer - | |
2190 | starting counting at zero - determines the integer that is used to | |
2191 | refer to the mode-switched entity in question. */ | |
2192 | ||
ff680eb1 UB |
2193 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
2194 | { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
22fb740d JH |
2195 | |
2196 | /* ENTITY is an integer specifying a mode-switched entity. If | |
2197 | `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2198 | return an integer value not larger than the corresponding element | |
2199 | in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
ff680eb1 UB |
2200 | must be switched into prior to the execution of INSN. */ |
2201 | ||
2202 | #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
22fb740d JH |
2203 | |
2204 | /* This macro specifies the order in which modes for ENTITY are | |
2205 | processed. 0 is the highest priority. */ | |
2206 | ||
d9a5f180 | 2207 | #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) |
22fb740d JH |
2208 | |
2209 | /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2210 | is the set of hard registers live at the point where the insn(s) | |
2211 | are to be inserted. */ | |
2212 | ||
2213 | #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
1d1df0df | 2214 | ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ |
ff680eb1 | 2215 | ? emit_i387_cw_initialization (MODE), 0 \ |
22fb740d | 2216 | : 0) |
ff680eb1 | 2217 | |
0f0138b6 JH |
2218 | \f |
2219 | /* Avoid renaming of stack registers, as doing so in combination with | |
2220 | scheduling just increases amount of live registers at time and in | |
2221 | the turn amount of fxch instructions needed. | |
2222 | ||
43f3a59d | 2223 | ??? Maybe Pentium chips benefits from renaming, someone can try.... */ |
0f0138b6 | 2224 | |
d9a5f180 | 2225 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ |
fb84c7a0 | 2226 | (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) |
22fb740d | 2227 | |
3b3c6a3f | 2228 | \f |
e91f04de CH |
2229 | #define DLL_IMPORT_EXPORT_PREFIX '#' |
2230 | ||
2231 | #define FASTCALL_PREFIX '@' | |
fa1a0d02 JH |
2232 | \f |
2233 | struct machine_function GTY(()) | |
2234 | { | |
2235 | struct stack_local_entry *stack_locals; | |
2236 | const char *some_ld_name; | |
150cdc9e | 2237 | rtx force_align_arg_pointer; |
fa1a0d02 JH |
2238 | int save_varrargs_registers; |
2239 | int accesses_prev_frame; | |
ff680eb1 | 2240 | int optimize_mode_switching[MAX_386_ENTITIES]; |
d9b40e8d JH |
2241 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to |
2242 | determine the style used. */ | |
2243 | int use_fast_prologue_epilogue; | |
d7394366 JH |
2244 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed |
2245 | for. */ | |
2246 | int use_fast_prologue_epilogue_nregs; | |
5bf5a10b AO |
2247 | /* If true, the current function needs the default PIC register, not |
2248 | an alternate register (on x86) and must not use the red zone (on | |
2249 | x86_64), even if it's a leaf function. We don't want the | |
2250 | function to be regarded as non-leaf because TLS calls need not | |
2251 | affect register allocation. This flag is set when a TLS call | |
2252 | instruction is expanded within a function, and never reset, even | |
2253 | if all such instructions are optimized away. Use the | |
2254 | ix86_current_function_calls_tls_descriptor macro for a better | |
2255 | approximation. */ | |
2256 | int tls_descriptor_call_expanded_p; | |
fa1a0d02 JH |
2257 | }; |
2258 | ||
2259 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
2260 | #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers) | |
2261 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
5bf5a10b AO |
2262 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2263 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2264 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2265 | calls are optimized away, we try to detect cases in which it was | |
2266 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2267 | verify whether there's any such instruction live by testing that | |
2268 | REG_SP is live. */ | |
2269 | #define ix86_current_function_calls_tls_descriptor \ | |
2270 | (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG]) | |
249e6b63 | 2271 | |
1bc7c5b6 ZW |
2272 | /* Control behavior of x86_file_start. */ |
2273 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2274 | #define X86_FILE_START_FLTUSED false | |
2275 | ||
7dcbf659 JH |
2276 | /* Flag to mark data that is in the large address area. */ |
2277 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2278 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2279 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
c98f8742 JVA |
2280 | /* |
2281 | Local variables: | |
2282 | version-control: t | |
2283 | End: | |
2284 | */ |