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188fc5b5 | 1 | /* Definitions of target machine for GCC for IA-32. |
23a5b65a | 2 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c98f8742 | 3 | |
188fc5b5 | 4 | This file is part of GCC. |
c98f8742 | 5 | |
188fc5b5 | 6 | GCC is free software; you can redistribute it and/or modify |
c98f8742 | 7 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
c98f8742 JVA |
9 | any later version. |
10 | ||
188fc5b5 | 11 | GCC is distributed in the hope that it will be useful, |
c98f8742 JVA |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
748086b7 JJ |
16 | Under Section 7 of GPL version 3, you are granted additional |
17 | permissions described in the GCC Runtime Library Exception, version | |
18 | 3.1, as published by the Free Software Foundation. | |
19 | ||
20 | You should have received a copy of the GNU General Public License and | |
21 | a copy of the GCC Runtime Library Exception along with this program; | |
22 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 23 | <http://www.gnu.org/licenses/>. */ |
c98f8742 | 24 | |
ccf8e764 RH |
25 | /* The purpose of this file is to define the characteristics of the i386, |
26 | independent of assembler syntax or operating system. | |
27 | ||
28 | Three other files build on this one to describe a specific assembler syntax: | |
29 | bsd386.h, att386.h, and sun386.h. | |
30 | ||
31 | The actual tm.h file for a particular system should include | |
32 | this file, and then the file for the appropriate assembler syntax. | |
33 | ||
34 | Many macros that specify assembler syntax are omitted entirely from | |
35 | this file because they really belong in the files for particular | |
36 | assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
37 | ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
38 | that start with ASM_ or end in ASM_OP. */ | |
39 | ||
0a1c5e55 UB |
40 | /* Redefines for option macros. */ |
41 | ||
90922d36 | 42 | #define TARGET_64BIT TARGET_ISA_64BIT |
bf7b5747 | 43 | #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x) |
90922d36 | 44 | #define TARGET_MMX TARGET_ISA_MMX |
bf7b5747 | 45 | #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x) |
90922d36 | 46 | #define TARGET_3DNOW TARGET_ISA_3DNOW |
bf7b5747 | 47 | #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x) |
90922d36 | 48 | #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A |
bf7b5747 | 49 | #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x) |
90922d36 | 50 | #define TARGET_SSE TARGET_ISA_SSE |
bf7b5747 | 51 | #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x) |
90922d36 | 52 | #define TARGET_SSE2 TARGET_ISA_SSE2 |
bf7b5747 | 53 | #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x) |
90922d36 | 54 | #define TARGET_SSE3 TARGET_ISA_SSE3 |
bf7b5747 | 55 | #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x) |
90922d36 | 56 | #define TARGET_SSSE3 TARGET_ISA_SSSE3 |
bf7b5747 | 57 | #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x) |
90922d36 | 58 | #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 |
bf7b5747 | 59 | #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x) |
90922d36 | 60 | #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 |
bf7b5747 | 61 | #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x) |
90922d36 | 62 | #define TARGET_AVX TARGET_ISA_AVX |
bf7b5747 | 63 | #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x) |
90922d36 | 64 | #define TARGET_AVX2 TARGET_ISA_AVX2 |
bf7b5747 | 65 | #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x) |
cb610367 UB |
66 | #define TARGET_AVX512F TARGET_ISA_AVX512F |
67 | #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x) | |
68 | #define TARGET_AVX512PF TARGET_ISA_AVX512PF | |
69 | #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x) | |
70 | #define TARGET_AVX512ER TARGET_ISA_AVX512ER | |
71 | #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x) | |
72 | #define TARGET_AVX512CD TARGET_ISA_AVX512CD | |
73 | #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x) | |
07165dd7 AI |
74 | #define TARGET_AVX512DQ TARGET_ISA_AVX512DQ |
75 | #define TARGET_AVX512DQ_P(x) TARGET_ISA_AVX512DQ_P(x) | |
b525d943 AI |
76 | #define TARGET_AVX512BW TARGET_ISA_AVX512BW |
77 | #define TARGET_AVX512BW_P(x) TARGET_ISA_AVX512BW_P(x) | |
f4af595f AI |
78 | #define TARGET_AVX512VL TARGET_ISA_AVX512VL |
79 | #define TARGET_AVX512VL_P(x) TARGET_ISA_AVX512VL_P(x) | |
90922d36 | 80 | #define TARGET_FMA TARGET_ISA_FMA |
bf7b5747 | 81 | #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x) |
90922d36 | 82 | #define TARGET_SSE4A TARGET_ISA_SSE4A |
bf7b5747 | 83 | #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x) |
90922d36 | 84 | #define TARGET_FMA4 TARGET_ISA_FMA4 |
bf7b5747 | 85 | #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x) |
90922d36 | 86 | #define TARGET_XOP TARGET_ISA_XOP |
bf7b5747 | 87 | #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x) |
90922d36 | 88 | #define TARGET_LWP TARGET_ISA_LWP |
bf7b5747 | 89 | #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x) |
90922d36 MM |
90 | #define TARGET_ROUND TARGET_ISA_ROUND |
91 | #define TARGET_ABM TARGET_ISA_ABM | |
bf7b5747 | 92 | #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) |
90922d36 | 93 | #define TARGET_BMI TARGET_ISA_BMI |
bf7b5747 | 94 | #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) |
90922d36 | 95 | #define TARGET_BMI2 TARGET_ISA_BMI2 |
bf7b5747 | 96 | #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x) |
90922d36 | 97 | #define TARGET_LZCNT TARGET_ISA_LZCNT |
bf7b5747 | 98 | #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x) |
90922d36 | 99 | #define TARGET_TBM TARGET_ISA_TBM |
bf7b5747 | 100 | #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x) |
90922d36 | 101 | #define TARGET_POPCNT TARGET_ISA_POPCNT |
bf7b5747 | 102 | #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x) |
90922d36 | 103 | #define TARGET_SAHF TARGET_ISA_SAHF |
bf7b5747 | 104 | #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x) |
90922d36 | 105 | #define TARGET_MOVBE TARGET_ISA_MOVBE |
bf7b5747 | 106 | #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x) |
90922d36 | 107 | #define TARGET_CRC32 TARGET_ISA_CRC32 |
bf7b5747 | 108 | #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x) |
90922d36 | 109 | #define TARGET_AES TARGET_ISA_AES |
bf7b5747 | 110 | #define TARGET_AES_P(x) TARGET_ISA_AES_P(x) |
c1618f82 AI |
111 | #define TARGET_SHA TARGET_ISA_SHA |
112 | #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x) | |
9cdea277 IT |
113 | #define TARGET_CLFLUSHOPT TARGET_ISA_CLFLUSHOPT |
114 | #define TARGET_CLFLUSHOPT_P(x) TARGET_ISA_CLFLUSHOPT_P(x) | |
115 | #define TARGET_XSAVEC TARGET_ISA_XSAVEC | |
116 | #define TARGET_XSAVEC_P(x) TARGET_ISA_XSAVEC_P(x) | |
117 | #define TARGET_XSAVES TARGET_ISA_XSAVES | |
118 | #define TARGET_XSAVES_P(x) TARGET_ISA_XSAVES_P(x) | |
90922d36 | 119 | #define TARGET_PCLMUL TARGET_ISA_PCLMUL |
bf7b5747 | 120 | #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x) |
cb610367 UB |
121 | #define TARGET_CMPXCHG16B TARGET_ISA_CX16 |
122 | #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x) | |
90922d36 | 123 | #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE |
bf7b5747 | 124 | #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x) |
90922d36 | 125 | #define TARGET_RDRND TARGET_ISA_RDRND |
bf7b5747 | 126 | #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x) |
90922d36 | 127 | #define TARGET_F16C TARGET_ISA_F16C |
bf7b5747 | 128 | #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x) |
cb610367 UB |
129 | #define TARGET_RTM TARGET_ISA_RTM |
130 | #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x) | |
90922d36 | 131 | #define TARGET_HLE TARGET_ISA_HLE |
bf7b5747 | 132 | #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x) |
90922d36 | 133 | #define TARGET_RDSEED TARGET_ISA_RDSEED |
bf7b5747 | 134 | #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x) |
90922d36 | 135 | #define TARGET_PRFCHW TARGET_ISA_PRFCHW |
bf7b5747 | 136 | #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x) |
90922d36 | 137 | #define TARGET_ADX TARGET_ISA_ADX |
bf7b5747 | 138 | #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x) |
3a0d99bb | 139 | #define TARGET_FXSR TARGET_ISA_FXSR |
bf7b5747 | 140 | #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x) |
3a0d99bb | 141 | #define TARGET_XSAVE TARGET_ISA_XSAVE |
bf7b5747 | 142 | #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x) |
3a0d99bb | 143 | #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT |
bf7b5747 | 144 | #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x) |
43b3f52f IT |
145 | #define TARGET_PREFETCHWT1 TARGET_ISA_PREFETCHWT1 |
146 | #define TARGET_PREFETCHWT1_P(x) TARGET_ISA_PREFETCHWT1_P(x) | |
ab442df7 | 147 | |
90922d36 | 148 | #define TARGET_LP64 TARGET_ABI_64 |
bf7b5747 | 149 | #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) |
90922d36 | 150 | #define TARGET_X32 TARGET_ABI_X32 |
bf7b5747 | 151 | #define TARGET_X32_P(x) TARGET_ABI_X32_P(x) |
d5d618b5 L |
152 | #define TARGET_16BIT TARGET_CODE16 |
153 | #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) | |
04e1d06b | 154 | |
cbf2e4d4 HJ |
155 | /* SSE4.1 defines round instructions */ |
156 | #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 | |
90922d36 | 157 | #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) |
0a1c5e55 | 158 | |
26b5109f RS |
159 | #include "config/vxworks-dummy.h" |
160 | ||
7eb68c06 | 161 | #include "config/i386/i386-opts.h" |
ccf8e764 | 162 | |
c69fa2d4 | 163 | #define MAX_STRINGOP_ALGS 4 |
ccf8e764 | 164 | |
8c996513 JH |
165 | /* Specify what algorithm to use for stringops on known size. |
166 | When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
167 | known at compile time or estimated via feedback, the SIZE array | |
168 | is walked in order until MAX is greater then the estimate (or -1 | |
4f3f76e6 | 169 | means infinity). Corresponding ALG is used then. |
340ef734 JH |
170 | When NOALIGN is true the code guaranting the alignment of the memory |
171 | block is skipped. | |
172 | ||
8c996513 | 173 | For example initializer: |
4f3f76e6 | 174 | {{256, loop}, {-1, rep_prefix_4_byte}} |
8c996513 | 175 | will use loop for blocks smaller or equal to 256 bytes, rep prefix will |
ccf8e764 | 176 | be used otherwise. */ |
8c996513 JH |
177 | struct stringop_algs |
178 | { | |
179 | const enum stringop_alg unknown_size; | |
180 | const struct stringop_strategy { | |
181 | const int max; | |
182 | const enum stringop_alg alg; | |
340ef734 | 183 | int noalign; |
c69fa2d4 | 184 | } size [MAX_STRINGOP_ALGS]; |
8c996513 JH |
185 | }; |
186 | ||
d4ba09c0 SC |
187 | /* Define the specific costs for a given cpu */ |
188 | ||
189 | struct processor_costs { | |
8b60264b KG |
190 | const int add; /* cost of an add instruction */ |
191 | const int lea; /* cost of a lea instruction */ | |
192 | const int shift_var; /* variable shift costs */ | |
193 | const int shift_const; /* constant shift costs */ | |
f676971a | 194 | const int mult_init[5]; /* cost of starting a multiply |
4977bab6 | 195 | in QImode, HImode, SImode, DImode, TImode*/ |
8b60264b | 196 | const int mult_bit; /* cost of multiply per each bit set */ |
f676971a | 197 | const int divide[5]; /* cost of a divide/mod |
4977bab6 | 198 | in QImode, HImode, SImode, DImode, TImode*/ |
44cf5b6a JH |
199 | int movsx; /* The cost of movsx operation. */ |
200 | int movzx; /* The cost of movzx operation. */ | |
8b60264b KG |
201 | const int large_insn; /* insns larger than this cost more */ |
202 | const int move_ratio; /* The threshold of number of scalar | |
ac775968 | 203 | memory-to-memory move insns. */ |
8b60264b KG |
204 | const int movzbl_load; /* cost of loading using movzbl */ |
205 | const int int_load[3]; /* cost of loading integer registers | |
96e7ae40 JH |
206 | in QImode, HImode and SImode relative |
207 | to reg-reg move (2). */ | |
8b60264b | 208 | const int int_store[3]; /* cost of storing integer register |
96e7ae40 | 209 | in QImode, HImode and SImode */ |
8b60264b KG |
210 | const int fp_move; /* cost of reg,reg fld/fst */ |
211 | const int fp_load[3]; /* cost of loading FP register | |
96e7ae40 | 212 | in SFmode, DFmode and XFmode */ |
8b60264b | 213 | const int fp_store[3]; /* cost of storing FP register |
96e7ae40 | 214 | in SFmode, DFmode and XFmode */ |
8b60264b KG |
215 | const int mmx_move; /* cost of moving MMX register. */ |
216 | const int mmx_load[2]; /* cost of loading MMX register | |
fa79946e | 217 | in SImode and DImode */ |
8b60264b | 218 | const int mmx_store[2]; /* cost of storing MMX register |
fa79946e | 219 | in SImode and DImode */ |
8b60264b KG |
220 | const int sse_move; /* cost of moving SSE register. */ |
221 | const int sse_load[3]; /* cost of loading SSE register | |
fa79946e | 222 | in SImode, DImode and TImode*/ |
8b60264b | 223 | const int sse_store[3]; /* cost of storing SSE register |
fa79946e | 224 | in SImode, DImode and TImode*/ |
8b60264b | 225 | const int mmxsse_to_integer; /* cost of moving mmxsse register to |
fa79946e | 226 | integer and vice versa. */ |
46cb0441 ZD |
227 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ |
228 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
f4365627 JH |
229 | const int prefetch_block; /* bytes moved to cache for prefetch. */ |
230 | const int simultaneous_prefetches; /* number of parallel prefetch | |
231 | operations. */ | |
4977bab6 | 232 | const int branch_cost; /* Default value for BRANCH_COST. */ |
229b303a RS |
233 | const int fadd; /* cost of FADD and FSUB instructions. */ |
234 | const int fmul; /* cost of FMUL instruction. */ | |
235 | const int fdiv; /* cost of FDIV instruction. */ | |
236 | const int fabs; /* cost of FABS instruction. */ | |
237 | const int fchs; /* cost of FCHS instruction. */ | |
238 | const int fsqrt; /* cost of FSQRT instruction. */ | |
8c996513 | 239 | /* Specify what algorithm |
bee51209 | 240 | to use for stringops on unknown size. */ |
ad83025e | 241 | struct stringop_algs *memcpy, *memset; |
e70444a8 HJ |
242 | const int scalar_stmt_cost; /* Cost of any scalar operation, excluding |
243 | load and store. */ | |
244 | const int scalar_load_cost; /* Cost of scalar load. */ | |
245 | const int scalar_store_cost; /* Cost of scalar store. */ | |
246 | const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
247 | load, store, vector-to-scalar and | |
248 | scalar-to-vector operation. */ | |
249 | const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
250 | const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
4f3f76e6 | 251 | const int vec_align_load_cost; /* Cost of aligned vector load. */ |
e70444a8 HJ |
252 | const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ |
253 | const int vec_store_cost; /* Cost of vector store. */ | |
254 | const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
255 | cost model. */ | |
256 | const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
257 | vectorizer cost model. */ | |
d4ba09c0 SC |
258 | }; |
259 | ||
8b60264b | 260 | extern const struct processor_costs *ix86_cost; |
b2077fd2 JH |
261 | extern const struct processor_costs ix86_size_cost; |
262 | ||
263 | #define ix86_cur_cost() \ | |
264 | (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
d4ba09c0 | 265 | |
c98f8742 JVA |
266 | /* Macros used in the machine description to test the flags. */ |
267 | ||
b97de419 | 268 | /* configure can arrange to change it. */ |
e075ae69 | 269 | |
35b528be | 270 | #ifndef TARGET_CPU_DEFAULT |
b97de419 | 271 | #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC |
10e9fecc | 272 | #endif |
35b528be | 273 | |
004d3859 GK |
274 | #ifndef TARGET_FPMATH_DEFAULT |
275 | #define TARGET_FPMATH_DEFAULT \ | |
276 | (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
277 | #endif | |
278 | ||
bf7b5747 ST |
279 | #ifndef TARGET_FPMATH_DEFAULT_P |
280 | #define TARGET_FPMATH_DEFAULT_P(x) \ | |
281 | (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387) | |
282 | #endif | |
283 | ||
6ac49599 | 284 | #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS |
bf7b5747 | 285 | #define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x) |
b08de47e | 286 | |
5791cc29 JT |
287 | /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a |
288 | compile-time constant. */ | |
289 | #ifdef IN_LIBGCC2 | |
6ac49599 | 290 | #undef TARGET_64BIT |
5791cc29 JT |
291 | #ifdef __x86_64__ |
292 | #define TARGET_64BIT 1 | |
293 | #else | |
294 | #define TARGET_64BIT 0 | |
295 | #endif | |
296 | #else | |
6ac49599 RS |
297 | #ifndef TARGET_BI_ARCH |
298 | #undef TARGET_64BIT | |
e49080ec | 299 | #undef TARGET_64BIT_P |
67adf6a9 | 300 | #if TARGET_64BIT_DEFAULT |
0c2dc519 | 301 | #define TARGET_64BIT 1 |
e49080ec | 302 | #define TARGET_64BIT_P(x) 1 |
0c2dc519 JH |
303 | #else |
304 | #define TARGET_64BIT 0 | |
e49080ec | 305 | #define TARGET_64BIT_P(x) 0 |
0c2dc519 JH |
306 | #endif |
307 | #endif | |
5791cc29 | 308 | #endif |
25f94bb5 | 309 | |
750054a2 CT |
310 | #define HAS_LONG_COND_BRANCH 1 |
311 | #define HAS_LONG_UNCOND_BRANCH 1 | |
312 | ||
9e555526 RH |
313 | #define TARGET_386 (ix86_tune == PROCESSOR_I386) |
314 | #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
315 | #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
316 | #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
cfe1b18f | 317 | #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) |
9e555526 RH |
318 | #define TARGET_K6 (ix86_tune == PROCESSOR_K6) |
319 | #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
320 | #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
321 | #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
4977bab6 | 322 | #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) |
89c43c0a | 323 | #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) |
340ef734 | 324 | #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) |
d3c11974 L |
325 | #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM) |
326 | #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE) | |
3a579e09 | 327 | #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) |
d3c11974 L |
328 | #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL) |
329 | #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT) | |
9a7f94d7 | 330 | #define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL) |
9d532162 | 331 | #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC) |
21efb4d4 | 332 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) |
1133125e | 333 | #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) |
4d652a18 | 334 | #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) |
eb2f2b44 | 335 | #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) |
ed97ad47 | 336 | #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4) |
14b52538 | 337 | #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) |
e32bfc16 | 338 | #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) |
a269a03c | 339 | |
80fd744f RH |
340 | /* Feature tests against the various tunings. */ |
341 | enum ix86_tune_indices { | |
4b8bc035 | 342 | #undef DEF_TUNE |
3ad20bd4 | 343 | #define DEF_TUNE(tune, name, selector) tune, |
4b8bc035 XDL |
344 | #include "x86-tune.def" |
345 | #undef DEF_TUNE | |
346 | X86_TUNE_LAST | |
80fd744f RH |
347 | }; |
348 | ||
ab442df7 | 349 | extern unsigned char ix86_tune_features[X86_TUNE_LAST]; |
80fd744f RH |
350 | |
351 | #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
352 | #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
353 | #define TARGET_ZERO_EXTEND_WITH_AND \ | |
354 | ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
80fd744f | 355 | #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] |
80fd744f RH |
356 | #define TARGET_BRANCH_PREDICTION_HINTS \ |
357 | ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
358 | #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
359 | #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
360 | #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
361 | #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
362 | #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
363 | ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
7b38ee83 TJ |
364 | #define TARGET_LCP_STALL \ |
365 | ix86_tune_features[X86_TUNE_LCP_STALL] | |
80fd744f RH |
366 | #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] |
367 | #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
368 | #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
369 | #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
370 | #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
371 | #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
372 | #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
373 | #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
374 | #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
375 | #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
376 | #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
5783ad0e UB |
377 | #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \ |
378 | ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES] | |
80fd744f RH |
379 | #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] |
380 | #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
381 | #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
382 | #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
d8b08ecd UB |
383 | #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] |
384 | #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] | |
385 | #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] | |
386 | #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] | |
80fd744f RH |
387 | #define TARGET_INTEGER_DFMODE_MOVES \ |
388 | ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
389 | #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
390 | ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
391 | #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
392 | ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
1133125e HJ |
393 | #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ |
394 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] | |
395 | #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ | |
396 | ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] | |
397 | #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ | |
398 | ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] | |
80fd744f RH |
399 | #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] |
400 | #define TARGET_SSE_TYPELESS_STORES \ | |
401 | ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
402 | #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
403 | #define TARGET_MEMORY_MISMATCH_STALL \ | |
404 | ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
405 | #define TARGET_PROLOGUE_USING_MOVE \ | |
406 | ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
407 | #define TARGET_EPILOGUE_USING_MOVE \ | |
408 | ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
409 | #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
410 | #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
00fcb892 UB |
411 | #define TARGET_INTER_UNIT_MOVES_TO_VEC \ |
412 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC] | |
413 | #define TARGET_INTER_UNIT_MOVES_FROM_VEC \ | |
414 | ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC] | |
415 | #define TARGET_INTER_UNIT_CONVERSIONS \ | |
630ecd8d | 416 | ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] |
80fd744f RH |
417 | #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] |
418 | #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
419 | #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
420 | #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
421 | #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
e7ed95a2 L |
422 | #define TARGET_PAD_SHORT_FUNCTION \ |
423 | ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] | |
80fd744f RH |
424 | #define TARGET_EXT_80387_CONSTANTS \ |
425 | ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
ddff69b9 MM |
426 | #define TARGET_AVOID_VECTOR_DECODE \ |
427 | ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
a646aded UB |
428 | #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ |
429 | ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
ddff69b9 MM |
430 | #define TARGET_SLOW_IMUL_IMM32_MEM \ |
431 | ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
432 | #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
433 | #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
434 | #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
435 | #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
54723b46 L |
436 | #define TARGET_USE_VECTOR_FP_CONVERTS \ |
437 | ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
354f84af UB |
438 | #define TARGET_USE_VECTOR_CONVERTS \ |
439 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
a4ef7f3e ES |
440 | #define TARGET_SLOW_PSHUFB \ |
441 | ix86_tune_features[X86_TUNE_SLOW_PSHUFB] | |
f7917029 ES |
442 | #define TARGET_VECTOR_PARALLEL_EXECUTION \ |
443 | ix86_tune_features[X86_TUNE_VECTOR_PARALLEL_EXECUTION] | |
0dc41f28 WM |
444 | #define TARGET_FUSE_CMP_AND_BRANCH_32 \ |
445 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] | |
446 | #define TARGET_FUSE_CMP_AND_BRANCH_64 \ | |
447 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64] | |
354f84af | 448 | #define TARGET_FUSE_CMP_AND_BRANCH \ |
0dc41f28 WM |
449 | (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \ |
450 | : TARGET_FUSE_CMP_AND_BRANCH_32) | |
451 | #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \ | |
452 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS] | |
453 | #define TARGET_FUSE_ALU_AND_BRANCH \ | |
454 | ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH] | |
b6837b94 | 455 | #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] |
9a7f94d7 L |
456 | #define TARGET_AVOID_LEA_FOR_ADDR \ |
457 | ix86_tune_features[X86_TUNE_AVOID_LEA_FOR_ADDR] | |
e72eba85 L |
458 | #define TARGET_VECTORIZE_DOUBLE \ |
459 | ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] | |
5d0878e7 JH |
460 | #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ |
461 | ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] | |
5c0d88e6 CF |
462 | #define TARGET_AVX128_OPTIMAL \ |
463 | ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] | |
df7b0cc4 EI |
464 | #define TARGET_REASSOC_INT_TO_PARALLEL \ |
465 | ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] | |
466 | #define TARGET_REASSOC_FP_TO_PARALLEL \ | |
467 | ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] | |
55a2c322 VM |
468 | #define TARGET_GENERAL_REGS_SSE_SPILL \ |
469 | ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] | |
6c72ea12 UB |
470 | #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ |
471 | ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] | |
55805e54 | 472 | #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \ |
0f1d3965 | 473 | ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] |
2f62165d GG |
474 | #define TARGET_ADJUST_UNROLL \ |
475 | ix86_tune_features[X86_TUNE_ADJUST_UNROLL] | |
df7b0cc4 | 476 | |
80fd744f RH |
477 | /* Feature tests against the various architecture variations. */ |
478 | enum ix86_arch_indices { | |
cef31f9c | 479 | X86_ARCH_CMOV, |
80fd744f RH |
480 | X86_ARCH_CMPXCHG, |
481 | X86_ARCH_CMPXCHG8B, | |
482 | X86_ARCH_XADD, | |
483 | X86_ARCH_BSWAP, | |
484 | ||
485 | X86_ARCH_LAST | |
486 | }; | |
4f3f76e6 | 487 | |
ab442df7 | 488 | extern unsigned char ix86_arch_features[X86_ARCH_LAST]; |
80fd744f | 489 | |
cef31f9c | 490 | #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] |
80fd744f RH |
491 | #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] |
492 | #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
493 | #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
494 | #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
495 | ||
cef31f9c UB |
496 | /* For sane SSE instruction set generation we need fcomi instruction. |
497 | It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic | |
498 | expands to a sequence that includes conditional move. */ | |
499 | #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) | |
500 | ||
80fd744f RH |
501 | #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) |
502 | ||
cb261eb7 | 503 | extern unsigned char x86_prefetch_sse; |
80fd744f RH |
504 | #define TARGET_PREFETCH_SSE x86_prefetch_sse |
505 | ||
80fd744f RH |
506 | #define ASSEMBLER_DIALECT (ix86_asm_dialect) |
507 | ||
508 | #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
509 | #define TARGET_MIX_SSE_I387 \ | |
510 | ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
511 | ||
512 | #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
513 | #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
514 | #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
d2af65b9 | 515 | #define TARGET_SUN_TLS 0 |
1ef45b77 | 516 | |
67adf6a9 RH |
517 | #ifndef TARGET_64BIT_DEFAULT |
518 | #define TARGET_64BIT_DEFAULT 0 | |
25f94bb5 | 519 | #endif |
74dc3e94 RH |
520 | #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT |
521 | #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
522 | #endif | |
25f94bb5 | 523 | |
e0ea8797 AH |
524 | #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL) |
525 | #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS) | |
526 | ||
79f5e442 ZD |
527 | /* Fence to use after loop using storent. */ |
528 | ||
529 | extern tree x86_mfence; | |
530 | #define FENCE_FOLLOWING_MOVNT x86_mfence | |
531 | ||
0ed4a390 JL |
532 | /* Once GDB has been enhanced to deal with functions without frame |
533 | pointers, we can change this to allow for elimination of | |
534 | the frame pointer in leaf functions. */ | |
535 | #define TARGET_DEFAULT 0 | |
67adf6a9 | 536 | |
0a1c5e55 UB |
537 | /* Extra bits to force. */ |
538 | #define TARGET_SUBTARGET_DEFAULT 0 | |
539 | #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
540 | ||
541 | /* Extra bits to force on w/ 32-bit mode. */ | |
542 | #define TARGET_SUBTARGET32_DEFAULT 0 | |
543 | #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
544 | ||
ccf8e764 RH |
545 | /* Extra bits to force on w/ 64-bit mode. */ |
546 | #define TARGET_SUBTARGET64_DEFAULT 0 | |
0a1c5e55 | 547 | #define TARGET_SUBTARGET64_ISA_DEFAULT 0 |
ccf8e764 | 548 | |
fee3eacd IS |
549 | /* Replace MACH-O, ifdefs by in-line tests, where possible. |
550 | (a) Macros defined in config/i386/darwin.h */ | |
b069de3b | 551 | #define TARGET_MACHO 0 |
9005471b | 552 | #define TARGET_MACHO_BRANCH_ISLANDS 0 |
fee3eacd IS |
553 | #define MACHOPIC_ATT_STUB 0 |
554 | /* (b) Macros defined in config/darwin.h */ | |
555 | #define MACHO_DYNAMIC_NO_PIC_P 0 | |
556 | #define MACHOPIC_INDIRECT 0 | |
557 | #define MACHOPIC_PURE 0 | |
9005471b | 558 | |
5a579c3b LE |
559 | /* For the RDOS */ |
560 | #define TARGET_RDOS 0 | |
561 | ||
9005471b | 562 | /* For the Windows 64-bit ABI. */ |
7c800926 KT |
563 | #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) |
564 | ||
6510e8bb KT |
565 | /* For the Windows 32-bit ABI. */ |
566 | #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
567 | ||
f81c9774 RH |
568 | /* This is re-defined by cygming.h. */ |
569 | #define TARGET_SEH 0 | |
570 | ||
a3d7ab92 KT |
571 | /* This is re-defined by cygming.h. */ |
572 | #define TARGET_PECOFF 0 | |
573 | ||
51212b32 | 574 | /* The default abi used by target. */ |
7c800926 | 575 | #define DEFAULT_ABI SYSV_ABI |
ccf8e764 | 576 | |
b8b3f0ca LE |
577 | /* The default TLS segment register used by target. */ |
578 | #define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS) | |
579 | ||
cc69336f RH |
580 | /* Subtargets may reset this to 1 in order to enable 96-bit long double |
581 | with the rounding mode forced to 53 bits. */ | |
582 | #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
583 | ||
682cd442 GK |
584 | /* -march=native handling only makes sense with compiler running on |
585 | an x86 or x86_64 chip. If changing this condition, also change | |
586 | the condition in driver-i386.c. */ | |
587 | #if defined(__i386__) || defined(__x86_64__) | |
fa959ce4 MM |
588 | /* In driver-i386.c. */ |
589 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
590 | #define EXTRA_SPEC_FUNCTIONS \ | |
591 | { "local_cpu_detect", host_detect_local_cpu }, | |
682cd442 | 592 | #define HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
593 | #endif |
594 | ||
8981c15b JM |
595 | #if TARGET_64BIT_DEFAULT |
596 | #define OPT_ARCH64 "!m32" | |
597 | #define OPT_ARCH32 "m32" | |
598 | #else | |
f0ea7581 L |
599 | #define OPT_ARCH64 "m64|mx32" |
600 | #define OPT_ARCH32 "m64|mx32:;" | |
8981c15b JM |
601 | #endif |
602 | ||
1cba2b96 EC |
603 | /* Support for configure-time defaults of some command line options. |
604 | The order here is important so that -march doesn't squash the | |
605 | tune or cpu values. */ | |
ce998900 | 606 | #define OPTION_DEFAULT_SPECS \ |
da2d4c01 | 607 | {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
608 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
609 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
ce998900 | 610 | {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ |
8981c15b JM |
611 | {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ |
612 | {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
613 | {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
614 | {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
615 | {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
7816bea0 | 616 | |
241e1a89 SC |
617 | /* Specs for the compiler proper */ |
618 | ||
628714d8 | 619 | #ifndef CC1_CPU_SPEC |
eb5bb0fd | 620 | #define CC1_CPU_SPEC_1 "" |
fa959ce4 | 621 | |
682cd442 | 622 | #ifndef HAVE_LOCAL_CPU_DETECT |
fa959ce4 MM |
623 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 |
624 | #else | |
625 | #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
96f5b137 L |
626 | "%{march=native:%>march=native %:local_cpu_detect(arch) \ |
627 | %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ | |
628 | %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" | |
fa959ce4 | 629 | #endif |
241e1a89 | 630 | #endif |
c98f8742 | 631 | \f |
30efe578 | 632 | /* Target CPU builtins. */ |
ab442df7 MM |
633 | #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () |
634 | ||
635 | /* Target Pragmas. */ | |
636 | #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
30efe578 | 637 | |
628714d8 | 638 | #ifndef CC1_SPEC |
8015b78d | 639 | #define CC1_SPEC "%(cc1_cpu) " |
628714d8 RK |
640 | #endif |
641 | ||
642 | /* This macro defines names of additional specifications to put in the | |
643 | specs that can be used in various specifications like CC1_SPEC. Its | |
644 | definition is an initializer with a subgrouping for each command option. | |
bcd86433 SC |
645 | |
646 | Each subgrouping contains a string constant, that defines the | |
188fc5b5 | 647 | specification name, and a string constant that used by the GCC driver |
bcd86433 SC |
648 | program. |
649 | ||
650 | Do not define this macro if it does not need to do anything. */ | |
651 | ||
652 | #ifndef SUBTARGET_EXTRA_SPECS | |
653 | #define SUBTARGET_EXTRA_SPECS | |
654 | #endif | |
655 | ||
656 | #define EXTRA_SPECS \ | |
628714d8 | 657 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
bcd86433 SC |
658 | SUBTARGET_EXTRA_SPECS |
659 | \f | |
ce998900 | 660 | |
d57a4b98 RH |
661 | /* Set the value of FLT_EVAL_METHOD in float.h. When using only the |
662 | FPU, assume that the fpcw is set to extended precision; when using | |
663 | only SSE, rounding is correct; when using both SSE and the FPU, | |
664 | the rounding precision is indeterminate, since either may be chosen | |
665 | apparently at random. */ | |
666 | #define TARGET_FLT_EVAL_METHOD \ | |
5ccd517a | 667 | (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) |
0038aea6 | 668 | |
8ce94e44 JM |
669 | /* Whether to allow x87 floating-point arithmetic on MODE (one of |
670 | SFmode, DFmode and XFmode) in the current excess precision | |
671 | configuration. */ | |
672 | #define X87_ENABLE_ARITH(MODE) \ | |
673 | (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) | |
674 | ||
675 | /* Likewise, whether to allow direct conversions from integer mode | |
676 | IMODE (HImode, SImode or DImode) to MODE. */ | |
677 | #define X87_ENABLE_FLOAT(MODE, IMODE) \ | |
678 | (flag_excess_precision == EXCESS_PRECISION_FAST \ | |
679 | || (MODE) == XFmode \ | |
680 | || ((MODE) == DFmode && (IMODE) == SImode) \ | |
681 | || (IMODE) == HImode) | |
682 | ||
979c67a5 UB |
683 | /* target machine storage layout */ |
684 | ||
65d9c0ab JH |
685 | #define SHORT_TYPE_SIZE 16 |
686 | #define INT_TYPE_SIZE 32 | |
f0ea7581 L |
687 | #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) |
688 | #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) | |
a96ad348 | 689 | #define LONG_LONG_TYPE_SIZE 64 |
65d9c0ab | 690 | #define FLOAT_TYPE_SIZE 32 |
65d9c0ab | 691 | #define DOUBLE_TYPE_SIZE 64 |
a2a1ddb5 L |
692 | #define LONG_DOUBLE_TYPE_SIZE \ |
693 | (TARGET_LONG_DOUBLE_64 ? 64 : (TARGET_LONG_DOUBLE_128 ? 128 : 80)) | |
979c67a5 | 694 | |
c637141a L |
695 | /* Define this to set long double type size to use in libgcc2.c, which can |
696 | not depend on target_flags. */ | |
697 | #ifdef __LONG_DOUBLE_64__ | |
698 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
a2a1ddb5 L |
699 | #elif defined (__LONG_DOUBLE_128__) |
700 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
c637141a L |
701 | #else |
702 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 | |
703 | #endif | |
704 | ||
705 | #define WIDEST_HARDWARE_FP_SIZE 80 | |
65d9c0ab | 706 | |
67adf6a9 | 707 | #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT |
0c2dc519 | 708 | #define MAX_BITS_PER_WORD 64 |
0c2dc519 JH |
709 | #else |
710 | #define MAX_BITS_PER_WORD 32 | |
0c2dc519 JH |
711 | #endif |
712 | ||
c98f8742 JVA |
713 | /* Define this if most significant byte of a word is the lowest numbered. */ |
714 | /* That is true on the 80386. */ | |
715 | ||
716 | #define BITS_BIG_ENDIAN 0 | |
717 | ||
718 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
719 | /* That is not true on the 80386. */ | |
720 | #define BYTES_BIG_ENDIAN 0 | |
721 | ||
722 | /* Define this if most significant word of a multiword number is the lowest | |
723 | numbered. */ | |
724 | /* Not true for 80386 */ | |
725 | #define WORDS_BIG_ENDIAN 0 | |
726 | ||
c98f8742 | 727 | /* Width of a word, in units (bytes). */ |
4ae8027b | 728 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
63001560 UB |
729 | |
730 | #ifndef IN_LIBGCC2 | |
2e64c636 JH |
731 | #define MIN_UNITS_PER_WORD 4 |
732 | #endif | |
c98f8742 | 733 | |
c98f8742 | 734 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
65d9c0ab | 735 | #define PARM_BOUNDARY BITS_PER_WORD |
c98f8742 | 736 | |
e075ae69 | 737 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ |
4ae8027b | 738 | #define STACK_BOUNDARY \ |
51212b32 | 739 | (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) |
c98f8742 | 740 | |
2e3f842f L |
741 | /* Stack boundary of the main function guaranteed by OS. */ |
742 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
743 | ||
de1132d1 | 744 | /* Minimum stack boundary. */ |
5bfb2af2 | 745 | #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32) |
2e3f842f | 746 | |
d1f87653 | 747 | /* Boundary (in *bits*) on which the stack pointer prefers to be |
3af4bd89 | 748 | aligned; the compiler cannot rely on having this alignment. */ |
e075ae69 | 749 | #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary |
65954bd8 | 750 | |
de1132d1 | 751 | /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for |
2e3f842f L |
752 | both 32bit and 64bit, to support codes that need 128 bit stack |
753 | alignment for SSE instructions, but can't realign the stack. */ | |
754 | #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
755 | ||
756 | /* 1 if -mstackrealign should be turned on by default. It will | |
757 | generate an alternate prologue and epilogue that realigns the | |
758 | runtime stack if nessary. This supports mixing codes that keep a | |
759 | 4-byte aligned stack, as specified by i386 psABI, with codes that | |
890b9b96 | 760 | need a 16-byte aligned stack, as required by SSE instructions. */ |
2e3f842f L |
761 | #define STACK_REALIGN_DEFAULT 0 |
762 | ||
763 | /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
764 | #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
1d482056 | 765 | |
a2851b75 TG |
766 | /* According to Windows x64 software convention, the maximum stack allocatable |
767 | in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of | |
768 | instructions allowed to adjust the stack pointer in the epilog, forcing the | |
769 | use of frame pointer for frames larger than 2 GB. This theorical limit | |
770 | is reduced by 256, an over-estimated upper bound for the stack use by the | |
771 | prologue. | |
772 | We define only one threshold for both the prolog and the epilog. When the | |
4e523f33 | 773 | frame size is larger than this threshold, we allocate the area to save SSE |
a2851b75 TG |
774 | regs, then save them, and then allocate the remaining. There is no SEH |
775 | unwind info for this later allocation. */ | |
776 | #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) | |
777 | ||
ebff937c SH |
778 | /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is |
779 | mandatory for the 64-bit ABI, and may or may not be true for other | |
780 | operating systems. */ | |
781 | #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
782 | ||
f963b5d9 RS |
783 | /* Minimum allocation boundary for the code of a function. */ |
784 | #define FUNCTION_BOUNDARY 8 | |
785 | ||
786 | /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
787 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
c98f8742 | 788 | |
c98f8742 JVA |
789 | /* Minimum size in bits of the largest boundary to which any |
790 | and all fundamental data types supported by the hardware | |
791 | might need to be aligned. No data type wants to be aligned | |
17f24ff0 | 792 | rounder than this. |
fce5a9f2 | 793 | |
d1f87653 | 794 | Pentium+ prefers DFmode values to be aligned to 64 bit boundary |
17f24ff0 JH |
795 | and Pentium Pro XFmode values at 128 bit boundaries. */ |
796 | ||
3f97cb0b AI |
797 | #define BIGGEST_ALIGNMENT \ |
798 | (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128)) | |
17f24ff0 | 799 | |
2e3f842f L |
800 | /* Maximum stack alignment. */ |
801 | #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
802 | ||
6e4f1168 L |
803 | /* Alignment value for attribute ((aligned)). It is a constant since |
804 | it is the part of the ABI. We shouldn't change it with -mavx. */ | |
805 | #define ATTRIBUTE_ALIGNED_VALUE 128 | |
806 | ||
822eda12 | 807 | /* Decide whether a variable of mode MODE should be 128 bit aligned. */ |
a7180f70 | 808 | #define ALIGN_MODE_128(MODE) \ |
4501d314 | 809 | ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) |
a7180f70 | 810 | |
17f24ff0 | 811 | /* The published ABIs say that doubles should be aligned on word |
d1f87653 | 812 | boundaries, so lower the alignment for structure fields unless |
6fc605d8 | 813 | -malign-double is set. */ |
e932b21b | 814 | |
e83f3cff RH |
815 | /* ??? Blah -- this macro is used directly by libobjc. Since it |
816 | supports no vector modes, cut out the complexity and fall back | |
817 | on BIGGEST_FIELD_ALIGNMENT. */ | |
818 | #ifdef IN_TARGET_LIBS | |
ef49d42e JH |
819 | #ifdef __x86_64__ |
820 | #define BIGGEST_FIELD_ALIGNMENT 128 | |
821 | #else | |
e83f3cff | 822 | #define BIGGEST_FIELD_ALIGNMENT 32 |
ef49d42e | 823 | #endif |
e83f3cff | 824 | #else |
e932b21b JH |
825 | #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ |
826 | x86_field_alignment (FIELD, COMPUTED) | |
e83f3cff | 827 | #endif |
c98f8742 | 828 | |
e5e8a8bf | 829 | /* If defined, a C expression to compute the alignment given to a |
a7180f70 | 830 | constant that is being placed in memory. EXP is the constant |
e5e8a8bf JW |
831 | and ALIGN is the alignment that the object would ordinarily have. |
832 | The value of this macro is used instead of that alignment to align | |
833 | the object. | |
834 | ||
835 | If this macro is not defined, then ALIGN is used. | |
836 | ||
837 | The typical use of this macro is to increase alignment for string | |
838 | constants to be word aligned so that `strcpy' calls that copy | |
839 | constants can be done inline. */ | |
840 | ||
d9a5f180 | 841 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) |
d4ba09c0 | 842 | |
8a022443 JW |
843 | /* If defined, a C expression to compute the alignment for a static |
844 | variable. TYPE is the data type, and ALIGN is the alignment that | |
845 | the object would ordinarily have. The value of this macro is used | |
846 | instead of that alignment to align the object. | |
847 | ||
848 | If this macro is not defined, then ALIGN is used. | |
849 | ||
850 | One use of this macro is to increase alignment of medium-size | |
851 | data to make it all fit in fewer cache lines. Another is to | |
852 | cause character arrays to be word-aligned so that `strcpy' calls | |
853 | that copy constants to character arrays can be done inline. */ | |
854 | ||
df8a1d28 JJ |
855 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
856 | ix86_data_alignment ((TYPE), (ALIGN), true) | |
857 | ||
858 | /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates | |
859 | some alignment increase, instead of optimization only purposes. E.g. | |
860 | AMD x86-64 psABI says that variables with array type larger than 15 bytes | |
861 | must be aligned to 16 byte boundaries. | |
862 | ||
863 | If this macro is not defined, then ALIGN is used. */ | |
864 | ||
865 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
866 | ix86_data_alignment ((TYPE), (ALIGN), false) | |
d16790f2 JW |
867 | |
868 | /* If defined, a C expression to compute the alignment for a local | |
869 | variable. TYPE is the data type, and ALIGN is the alignment that | |
870 | the object would ordinarily have. The value of this macro is used | |
871 | instead of that alignment to align the object. | |
872 | ||
873 | If this macro is not defined, then ALIGN is used. | |
874 | ||
875 | One use of this macro is to increase alignment of medium-size | |
876 | data to make it all fit in fewer cache lines. */ | |
877 | ||
76fe54f0 L |
878 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ |
879 | ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
880 | ||
881 | /* If defined, a C expression to compute the alignment for stack slot. | |
882 | TYPE is the data type, MODE is the widest mode available, and ALIGN | |
883 | is the alignment that the slot would ordinarily have. The value of | |
884 | this macro is used instead of that alignment to align the slot. | |
885 | ||
886 | If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
887 | Otherwise, LOCAL_ALIGNMENT will be used. | |
888 | ||
889 | One use of this macro is to set alignment of stack slot to the | |
890 | maximum alignment of all possible modes which the slot may have. */ | |
891 | ||
892 | #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
893 | ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
8a022443 | 894 | |
9bfaf89d JJ |
895 | /* If defined, a C expression to compute the alignment for a local |
896 | variable DECL. | |
897 | ||
898 | If this macro is not defined, then | |
899 | LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
900 | ||
901 | One use of this macro is to increase alignment of medium-size | |
902 | data to make it all fit in fewer cache lines. */ | |
903 | ||
904 | #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
905 | ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
906 | ||
ae58e548 JJ |
907 | /* If defined, a C expression to compute the minimum required alignment |
908 | for dynamic stack realignment purposes for EXP (a TYPE or DECL), | |
909 | MODE, assuming normal alignment ALIGN. | |
910 | ||
911 | If this macro is not defined, then (ALIGN) will be used. */ | |
912 | ||
913 | #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ | |
914 | ix86_minimum_alignment (EXP, MODE, ALIGN) | |
915 | ||
9bfaf89d | 916 | |
9cd10576 | 917 | /* Set this nonzero if move instructions will actually fail to work |
c98f8742 | 918 | when given unaligned data. */ |
b4ac57ab | 919 | #define STRICT_ALIGNMENT 0 |
c98f8742 JVA |
920 | |
921 | /* If bit field type is int, don't let it cross an int, | |
922 | and give entire struct the alignment of an int. */ | |
43a88a8c | 923 | /* Required on the 386 since it doesn't have bit-field insns. */ |
c98f8742 | 924 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
c98f8742 JVA |
925 | \f |
926 | /* Standard register usage. */ | |
927 | ||
928 | /* This processor has special stack-like registers. See reg-stack.c | |
892a2d68 | 929 | for details. */ |
c98f8742 JVA |
930 | |
931 | #define STACK_REGS | |
ce998900 | 932 | |
d9a5f180 | 933 | #define IS_STACK_MODE(MODE) \ |
63001560 UB |
934 | (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ |
935 | || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ | |
b5c82fa1 | 936 | || (MODE) == XFmode) |
c98f8742 JVA |
937 | |
938 | /* Number of actual hardware registers. | |
939 | The hardware registers are assigned numbers for the compiler | |
940 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
941 | All registers that the compiler knows about must be given numbers, | |
942 | even those that are not normally considered general registers. | |
943 | ||
944 | In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
945 | We number the floating point registers 8-15. | |
946 | Note that registers 0-7 can be accessed as a short or int, | |
947 | while only 0-3 may be used with byte `mov' instructions. | |
948 | ||
949 | Reg 16 does not correspond to any hardware register, but instead | |
950 | appears in the RTL as an argument pointer prior to reload, and is | |
951 | eliminated during reloading in favor of either the stack or frame | |
892a2d68 | 952 | pointer. */ |
c98f8742 | 953 | |
089d1227 | 954 | #define FIRST_PSEUDO_REGISTER 77 |
c98f8742 | 955 | |
3073d01c ML |
956 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
957 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
958 | ||
959 | #define DWARF_FRAME_REGISTERS 17 | |
960 | ||
c98f8742 JVA |
961 | /* 1 for registers that have pervasive standard uses |
962 | and are not available for the register allocator. | |
3f3f2124 | 963 | On the 80386, the stack pointer is such, as is the arg pointer. |
fce5a9f2 | 964 | |
621bc046 UB |
965 | REX registers are disabled for 32bit targets in |
966 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
967 | ||
a7180f70 BS |
968 | #define FIXED_REGISTERS \ |
969 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
3a4416fb | 970 | { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ |
b0d95de8 UB |
971 | /*arg,flags,fpsr,fpcr,frame*/ \ |
972 | 1, 1, 1, 1, 1, \ | |
a7180f70 BS |
973 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
974 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
78168632 | 975 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3f3f2124 JH |
976 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
977 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
621bc046 | 978 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
3f3f2124 | 979 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
980 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
981 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
982 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
983 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
984 | 0, 0, 0, 0, 0, 0, 0, 0, \ |
985 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
089d1227 | 986 | 0, 0, 0, 0, 0, 0, 0, 0 } |
c98f8742 JVA |
987 | |
988 | /* 1 for registers not available across function calls. | |
989 | These must include the FIXED_REGISTERS and also any | |
990 | registers that can be used without being saved. | |
991 | The latter must include the registers where values are returned | |
992 | and the register where structure-value addresses are passed. | |
fce5a9f2 EC |
993 | Aside from that, you can include as many other registers as you like. |
994 | ||
621bc046 UB |
995 | Value is set to 1 if the register is call used unconditionally. |
996 | Bit one is set if the register is call used on TARGET_32BIT ABI. | |
997 | Bit two is set if the register is call used on TARGET_64BIT ABI. | |
998 | Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. | |
999 | ||
1000 | Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
1001 | ||
a7180f70 BS |
1002 | #define CALL_USED_REGISTERS \ |
1003 | /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
621bc046 | 1004 | { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
b0d95de8 UB |
1005 | /*arg,flags,fpsr,fpcr,frame*/ \ |
1006 | 1, 1, 1, 1, 1, \ | |
a7180f70 | 1007 | /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ |
621bc046 | 1008 | 1, 1, 1, 1, 1, 1, 6, 6, \ |
78168632 | 1009 | /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ |
3a4416fb | 1010 | 1, 1, 1, 1, 1, 1, 1, 1, \ |
3f3f2124 | 1011 | /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ |
3a4416fb | 1012 | 1, 1, 1, 1, 2, 2, 2, 2, \ |
3f3f2124 | 1013 | /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ |
3f97cb0b AI |
1014 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1015 | /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \ | |
1016 | 6, 6, 6, 6, 6, 6, 6, 6, \ | |
1017 | /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \ | |
85a77221 AI |
1018 | 6, 6, 6, 6, 6, 6, 6, 6, \ |
1019 | /* k0, k1, k2, k3, k4, k5, k6, k7*/ \ | |
089d1227 | 1020 | 1, 1, 1, 1, 1, 1, 1, 1 } |
c98f8742 | 1021 | |
3b3c6a3f MM |
1022 | /* Order in which to allocate registers. Each register must be |
1023 | listed once, even those in FIXED_REGISTERS. List frame pointer | |
1024 | late and fixed registers last. Note that, in general, we prefer | |
1025 | registers listed in CALL_USED_REGISTERS, keeping the others | |
1026 | available for storage of persistent values. | |
1027 | ||
5a733826 | 1028 | The ADJUST_REG_ALLOC_ORDER actually overwrite the order, |
162f023b | 1029 | so this is just empty initializer for array. */ |
3b3c6a3f | 1030 | |
162f023b JH |
1031 | #define REG_ALLOC_ORDER \ |
1032 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
1033 | 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
1034 | 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
3f97cb0b | 1035 | 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
089d1227 | 1036 | 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76 } |
3b3c6a3f | 1037 | |
5a733826 | 1038 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
162f023b | 1039 | to be rearranged based on a particular function. When using sse math, |
03c259ad | 1040 | we want to allocate SSE before x87 registers and vice versa. */ |
3b3c6a3f | 1041 | |
5a733826 | 1042 | #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () |
3b3c6a3f | 1043 | |
f5316dfe | 1044 | |
7c800926 KT |
1045 | #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) |
1046 | ||
c98f8742 JVA |
1047 | /* Return number of consecutive hard regs needed starting at reg REGNO |
1048 | to hold something of mode MODE. | |
1049 | This is ordinarily the length in words of a value of mode MODE | |
1050 | but can be less for certain modes in special long registers. | |
1051 | ||
fce5a9f2 | 1052 | Actually there are no two word move instructions for consecutive |
c98f8742 | 1053 | registers. And only registers 0-3 may have mov byte instructions |
63001560 | 1054 | applied to them. */ |
c98f8742 | 1055 | |
ce998900 | 1056 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
9e4a4dd6 AI |
1057 | (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) \ |
1058 | || MMX_REGNO_P (REGNO) || MASK_REGNO_P (REGNO) \ | |
92d0fb09 | 1059 | ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ |
f8a1ebc6 | 1060 | : ((MODE) == XFmode \ |
92d0fb09 | 1061 | ? (TARGET_64BIT ? 2 : 3) \ |
f8a1ebc6 | 1062 | : (MODE) == XCmode \ |
92d0fb09 | 1063 | ? (TARGET_64BIT ? 4 : 6) \ |
2b589241 | 1064 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) |
c98f8742 | 1065 | |
8521c414 JM |
1066 | #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ |
1067 | ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
66aaf16f | 1068 | ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ |
8521c414 JM |
1069 | ? 0 \ |
1070 | : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
1071 | : 0) | |
1072 | ||
1073 | #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
1074 | ||
95879c72 L |
1075 | #define VALID_AVX256_REG_MODE(MODE) \ |
1076 | ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb JJ |
1077 | || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ |
1078 | || (MODE) == V4DFmode) | |
95879c72 | 1079 | |
4ac005ba | 1080 | #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ |
ff97910d VY |
1081 | (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) |
1082 | ||
3f97cb0b AI |
1083 | #define VALID_AVX512F_SCALAR_MODE(MODE) \ |
1084 | ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \ | |
1085 | || (MODE) == SFmode) | |
1086 | ||
1087 | #define VALID_AVX512F_REG_MODE(MODE) \ | |
1088 | ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \ | |
9e4a4dd6 AI |
1089 | || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode \ |
1090 | || (MODE) == V4TImode) | |
1091 | ||
1092 | #define VALID_AVX512VL_128_REG_MODE(MODE) \ | |
1093 | ((MODE) == V2DImode || (MODE) == V2DFmode || (MODE) == V16QImode \ | |
1094 | || (MODE) == V4SImode || (MODE) == V4SFmode || (MODE) == V8HImode) | |
3f97cb0b | 1095 | |
ce998900 UB |
1096 | #define VALID_SSE2_REG_MODE(MODE) \ |
1097 | ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1098 | || (MODE) == V2DImode || (MODE) == DFmode) | |
fbe5eb6d | 1099 | |
d9a5f180 | 1100 | #define VALID_SSE_REG_MODE(MODE) \ |
fe6ae2da UB |
1101 | ((MODE) == V1TImode || (MODE) == TImode \ |
1102 | || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
ce998900 | 1103 | || (MODE) == SFmode || (MODE) == TFmode) |
a7180f70 | 1104 | |
47f339cf | 1105 | #define VALID_MMX_REG_MODE_3DNOW(MODE) \ |
ce998900 | 1106 | ((MODE) == V2SFmode || (MODE) == SFmode) |
47f339cf | 1107 | |
d9a5f180 | 1108 | #define VALID_MMX_REG_MODE(MODE) \ |
10a97ae6 UB |
1109 | ((MODE == V1DImode) || (MODE) == DImode \ |
1110 | || (MODE) == V2SImode || (MODE) == SImode \ | |
1111 | || (MODE) == V4HImode || (MODE) == V8QImode) | |
a7180f70 | 1112 | |
ce998900 UB |
1113 | #define VALID_DFP_MODE_P(MODE) \ |
1114 | ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
62d75179 | 1115 | |
d9a5f180 | 1116 | #define VALID_FP_MODE_P(MODE) \ |
ce998900 UB |
1117 | ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ |
1118 | || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
a946dd00 | 1119 | |
d9a5f180 | 1120 | #define VALID_INT_MODE_P(MODE) \ |
ce998900 UB |
1121 | ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ |
1122 | || (MODE) == DImode \ | |
1123 | || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1124 | || (MODE) == CDImode \ | |
1125 | || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1126 | || (MODE) == TFmode || (MODE) == TCmode))) | |
a946dd00 | 1127 | |
822eda12 | 1128 | /* Return true for modes passed in SSE registers. */ |
ce998900 | 1129 | #define SSE_REG_MODE_P(MODE) \ |
fe6ae2da UB |
1130 | ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ |
1131 | || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
1132 | || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
1133 | || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
8a0436cb | 1134 | || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ |
3f97cb0b AI |
1135 | || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \ |
1136 | || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \ | |
1137 | || (MODE) == V16SFmode) | |
822eda12 | 1138 | |
85a77221 AI |
1139 | #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode) |
1140 | ||
9e4a4dd6 AI |
1141 | #define VALID_MASK_AVX512BW_MODE(MODE) ((MODE) == SImode || (MODE) == DImode) |
1142 | ||
e075ae69 | 1143 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ |
48227a2c | 1144 | |
a946dd00 | 1145 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
d9a5f180 | 1146 | ix86_hard_regno_mode_ok ((REGNO), (MODE)) |
c98f8742 JVA |
1147 | |
1148 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
1149 | when one has mode MODE1 and one has mode MODE2. | |
1150 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1151 | for any hard reg, then this must be 0 for correct output. */ | |
1152 | ||
c1c5b5e3 | 1153 | #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) |
d2836273 | 1154 | |
ff25ef99 ZD |
1155 | /* It is possible to write patterns to move flags; but until someone |
1156 | does it, */ | |
1157 | #define AVOID_CCMODE_COPIES | |
c98f8742 | 1158 | |
e075ae69 | 1159 | /* Specify the modes required to caller save a given hard regno. |
787dc842 | 1160 | We do this on i386 to prevent flags from being saved at all. |
e075ae69 | 1161 | |
787dc842 JH |
1162 | Kill any attempts to combine saving of modes. */ |
1163 | ||
d9a5f180 GS |
1164 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
1165 | (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1166 | : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
ce998900 | 1167 | : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ |
85a77221 AI |
1168 | : (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \ |
1169 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
1170 | : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \ | |
1171 | || MASK_REGNO_P (REGNO)) ? SImode \ | |
d2836273 | 1172 | : (MODE)) |
ce998900 | 1173 | |
51ba747a RH |
1174 | /* The only ABI that saves SSE registers across calls is Win64 (thus no |
1175 | need to check the current ABI here), and with AVX enabled Win64 only | |
1176 | guarantees that the low 16 bytes are saved. */ | |
1177 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
1178 | (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) | |
1179 | ||
c98f8742 JVA |
1180 | /* Specify the registers used for certain standard purposes. |
1181 | The values of these macros are register numbers. */ | |
1182 | ||
1183 | /* on the 386 the pc register is %eip, and is not usable as a general | |
1184 | register. The ordinary mov instructions won't work */ | |
1185 | /* #define PC_REGNUM */ | |
1186 | ||
1187 | /* Register to use for pushing function arguments. */ | |
1188 | #define STACK_POINTER_REGNUM 7 | |
1189 | ||
1190 | /* Base register for access to local variables of the function. */ | |
564d80f4 JH |
1191 | #define HARD_FRAME_POINTER_REGNUM 6 |
1192 | ||
1193 | /* Base register for access to local variables of the function. */ | |
b0d95de8 | 1194 | #define FRAME_POINTER_REGNUM 20 |
c98f8742 JVA |
1195 | |
1196 | /* First floating point reg */ | |
1197 | #define FIRST_FLOAT_REG 8 | |
1198 | ||
1199 | /* First & last stack-like regs */ | |
1200 | #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1201 | #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1202 | ||
a7180f70 BS |
1203 | #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) |
1204 | #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
fce5a9f2 | 1205 | |
3f97cb0b | 1206 | #define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/ |
a7180f70 BS |
1207 | #define LAST_MMX_REG (FIRST_MMX_REG + 7) |
1208 | ||
3f97cb0b | 1209 | #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/ |
3f3f2124 JH |
1210 | #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) |
1211 | ||
3f97cb0b | 1212 | #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/ |
3f3f2124 JH |
1213 | #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) |
1214 | ||
3f97cb0b AI |
1215 | #define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/ |
1216 | #define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/ | |
1217 | ||
85a77221 AI |
1218 | #define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/ |
1219 | #define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/ | |
1220 | ||
aabcd309 | 1221 | /* Override this in other tm.h files to cope with various OS lossage |
6fca22eb RH |
1222 | requiring a frame pointer. */ |
1223 | #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1224 | #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1225 | #endif | |
1226 | ||
1227 | /* Make sure we can access arbitrary call frames. */ | |
1228 | #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
c98f8742 JVA |
1229 | |
1230 | /* Base register for access to arguments of the function. */ | |
1231 | #define ARG_POINTER_REGNUM 16 | |
1232 | ||
c98f8742 | 1233 | /* Register to hold the addressing base for position independent |
5b43fed1 RH |
1234 | code access to data items. We don't use PIC pointer for 64bit |
1235 | mode. Define the regnum to dummy value to prevent gcc from | |
fce5a9f2 | 1236 | pessimizing code dealing with EBX. |
bd09bdeb RH |
1237 | |
1238 | To avoid clobbering a call-saved register unnecessarily, we renumber | |
1239 | the pic register when possible. The change is visible after the | |
1240 | prologue has been emitted. */ | |
1241 | ||
2e3f842f | 1242 | #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG |
bd09bdeb RH |
1243 | |
1244 | #define PIC_OFFSET_TABLE_REGNUM \ | |
82c0e1a0 | 1245 | ((TARGET_64BIT && (ix86_cmodel == CM_SMALL_PIC \ |
a3d7ab92 | 1246 | || TARGET_PECOFF)) \ |
7dcbf659 | 1247 | || !flag_pic ? INVALID_REGNUM \ |
bd09bdeb RH |
1248 | : reload_completed ? REGNO (pic_offset_table_rtx) \ |
1249 | : REAL_PIC_OFFSET_TABLE_REGNUM) | |
c98f8742 | 1250 | |
5fc0e5df KW |
1251 | #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" |
1252 | ||
c51e6d85 | 1253 | /* This is overridden by <cygwin.h>. */ |
5e062767 DS |
1254 | #define MS_AGGREGATE_RETURN 0 |
1255 | ||
61fec9ff | 1256 | #define KEEP_AGGREGATE_RETURN_POINTER 0 |
c98f8742 JVA |
1257 | \f |
1258 | /* Define the classes of registers for register constraints in the | |
1259 | machine description. Also define ranges of constants. | |
1260 | ||
1261 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1262 | If there is more than one class, another class must be named NO_REGS | |
1263 | and contain no registers. | |
1264 | ||
1265 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1266 | another name such as ALL_REGS). This is the class of registers | |
1267 | that is allowed by "g" or "r" in a register constraint. | |
1268 | Also, registers outside this class are allocated only when | |
1269 | instructions express preferences for them. | |
1270 | ||
1271 | The classes must be numbered in nondecreasing order; that is, | |
1272 | a larger-numbered class must never be contained completely | |
1273 | in a smaller-numbered class. | |
1274 | ||
1275 | For any two classes, it is very desirable that there be another | |
ab408a86 JVA |
1276 | class that represents their union. |
1277 | ||
1278 | It might seem that class BREG is unnecessary, since no useful 386 | |
1279 | opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
e075ae69 RH |
1280 | and the "b" register constraint is useful in asms for syscalls. |
1281 | ||
03c259ad | 1282 | The flags, fpsr and fpcr registers are in no class. */ |
c98f8742 JVA |
1283 | |
1284 | enum reg_class | |
1285 | { | |
1286 | NO_REGS, | |
e075ae69 | 1287 | AREG, DREG, CREG, BREG, SIREG, DIREG, |
4b71cd6e | 1288 | AD_REGS, /* %eax/%edx for DImode */ |
c98f8742 | 1289 | Q_REGS, /* %eax %ebx %ecx %edx */ |
564d80f4 | 1290 | NON_Q_REGS, /* %esi %edi %ebp %esp */ |
c98f8742 | 1291 | INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ |
3f3f2124 | 1292 | LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ |
621bc046 | 1293 | CLOBBERED_REGS, /* call-clobbered integer registers */ |
63001560 UB |
1294 | GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp |
1295 | %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ | |
c98f8742 JVA |
1296 | FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ |
1297 | FLOAT_REGS, | |
06f4e35d | 1298 | SSE_FIRST_REG, |
a7180f70 | 1299 | SSE_REGS, |
3f97cb0b AI |
1300 | EVEX_SSE_REGS, |
1301 | ALL_SSE_REGS, | |
a7180f70 | 1302 | MMX_REGS, |
446988df JH |
1303 | FP_TOP_SSE_REGS, |
1304 | FP_SECOND_SSE_REGS, | |
1305 | FLOAT_SSE_REGS, | |
1306 | FLOAT_INT_REGS, | |
1307 | INT_SSE_REGS, | |
1308 | FLOAT_INT_SSE_REGS, | |
85a77221 AI |
1309 | MASK_EVEX_REGS, |
1310 | MASK_REGS, | |
c98f8742 JVA |
1311 | ALL_REGS, LIM_REG_CLASSES |
1312 | }; | |
1313 | ||
d9a5f180 GS |
1314 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) |
1315 | ||
1316 | #define INTEGER_CLASS_P(CLASS) \ | |
1317 | reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1318 | #define FLOAT_CLASS_P(CLASS) \ | |
1319 | reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1320 | #define SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1321 | reg_class_subset_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1322 | #define MMX_CLASS_P(CLASS) \ |
f75959a6 | 1323 | ((CLASS) == MMX_REGS) |
d9a5f180 GS |
1324 | #define MAYBE_INTEGER_CLASS_P(CLASS) \ |
1325 | reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1326 | #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1327 | reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1328 | #define MAYBE_SSE_CLASS_P(CLASS) \ | |
3f97cb0b | 1329 | reg_classes_intersect_p ((CLASS), ALL_SSE_REGS) |
d9a5f180 | 1330 | #define MAYBE_MMX_CLASS_P(CLASS) \ |
0bd72901 | 1331 | reg_classes_intersect_p ((CLASS), MMX_REGS) |
85a77221 AI |
1332 | #define MAYBE_MASK_CLASS_P(CLASS) \ |
1333 | reg_classes_intersect_p ((CLASS), MASK_REGS) | |
d9a5f180 GS |
1334 | |
1335 | #define Q_CLASS_P(CLASS) \ | |
1336 | reg_class_subset_p ((CLASS), Q_REGS) | |
7c6b971d | 1337 | |
0bd72901 UB |
1338 | #define MAYBE_NON_Q_CLASS_P(CLASS) \ |
1339 | reg_classes_intersect_p ((CLASS), NON_Q_REGS) | |
1340 | ||
43f3a59d | 1341 | /* Give names of register classes as strings for dump file. */ |
c98f8742 JVA |
1342 | |
1343 | #define REG_CLASS_NAMES \ | |
1344 | { "NO_REGS", \ | |
ab408a86 | 1345 | "AREG", "DREG", "CREG", "BREG", \ |
c98f8742 | 1346 | "SIREG", "DIREG", \ |
e075ae69 RH |
1347 | "AD_REGS", \ |
1348 | "Q_REGS", "NON_Q_REGS", \ | |
c98f8742 | 1349 | "INDEX_REGS", \ |
3f3f2124 | 1350 | "LEGACY_REGS", \ |
621bc046 | 1351 | "CLOBBERED_REGS", \ |
c98f8742 JVA |
1352 | "GENERAL_REGS", \ |
1353 | "FP_TOP_REG", "FP_SECOND_REG", \ | |
1354 | "FLOAT_REGS", \ | |
cb482895 | 1355 | "SSE_FIRST_REG", \ |
a7180f70 | 1356 | "SSE_REGS", \ |
3f97cb0b AI |
1357 | "EVEX_SSE_REGS", \ |
1358 | "ALL_SSE_REGS", \ | |
a7180f70 | 1359 | "MMX_REGS", \ |
446988df JH |
1360 | "FP_TOP_SSE_REGS", \ |
1361 | "FP_SECOND_SSE_REGS", \ | |
1362 | "FLOAT_SSE_REGS", \ | |
8fcaaa80 | 1363 | "FLOAT_INT_REGS", \ |
446988df JH |
1364 | "INT_SSE_REGS", \ |
1365 | "FLOAT_INT_SSE_REGS", \ | |
85a77221 AI |
1366 | "MASK_EVEX_REGS", \ |
1367 | "MASK_REGS", \ | |
c98f8742 JVA |
1368 | "ALL_REGS" } |
1369 | ||
ac2e563f RH |
1370 | /* Define which registers fit in which classes. This is an initializer |
1371 | for a vector of HARD_REG_SET of length N_REG_CLASSES. | |
1372 | ||
621bc046 UB |
1373 | Note that CLOBBERED_REGS are calculated by |
1374 | TARGET_CONDITIONAL_REGISTER_USAGE. */ | |
c98f8742 | 1375 | |
3f97cb0b | 1376 | #define REG_CLASS_CONTENTS \ |
089d1227 IE |
1377 | { { 0x00, 0x0, 0x0 }, \ |
1378 | { 0x01, 0x0, 0x0 }, /* AREG */ \ | |
1379 | { 0x02, 0x0, 0x0 }, /* DREG */ \ | |
1380 | { 0x04, 0x0, 0x0 }, /* CREG */ \ | |
1381 | { 0x08, 0x0, 0x0 }, /* BREG */ \ | |
1382 | { 0x10, 0x0, 0x0 }, /* SIREG */ \ | |
1383 | { 0x20, 0x0, 0x0 }, /* DIREG */ \ | |
1384 | { 0x03, 0x0, 0x0 }, /* AD_REGS */ \ | |
1385 | { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ | |
1386 | { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \ | |
1387 | { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \ | |
1388 | { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ | |
1389 | { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \ | |
1390 | { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \ | |
1391 | { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ | |
1392 | { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ | |
1393 | { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ | |
1394 | { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \ | |
1395 | { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \ | |
1396 | { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \ | |
1397 | { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \ | |
1398 | { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \ | |
1399 | { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \ | |
1400 | { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \ | |
1401 | { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \ | |
1402 | { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \ | |
1403 | { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \ | |
1404 | { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \ | |
1405 | { 0x0, 0x0,0x1fc0 }, /* MASK_EVEX_REGS */ \ | |
1406 | { 0x0, 0x0,0x1fe0 }, /* MASK_REGS */ \ | |
1407 | { 0xffffffff,0xffffffff,0x1fff } \ | |
e075ae69 | 1408 | } |
c98f8742 JVA |
1409 | |
1410 | /* The same information, inverted: | |
1411 | Return the class number of the smallest class containing | |
1412 | reg number REGNO. This could be a conditional expression | |
1413 | or could index an array. */ | |
1414 | ||
c98f8742 JVA |
1415 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) |
1416 | ||
42db504c SB |
1417 | /* When this hook returns true for MODE, the compiler allows |
1418 | registers explicitly used in the rtl to be used as spill registers | |
1419 | but prevents the compiler from extending the lifetime of these | |
1420 | registers. */ | |
1421 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true | |
c98f8742 | 1422 | |
fc27f749 UB |
1423 | #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) |
1424 | #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG) | |
3f3f2124 JH |
1425 | |
1426 | #define GENERAL_REG_P(X) \ | |
6189a572 | 1427 | (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) |
fc27f749 UB |
1428 | #define GENERAL_REGNO_P(N) \ |
1429 | (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N)) | |
3f3f2124 | 1430 | |
fc27f749 UB |
1431 | #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) |
1432 | #define ANY_QI_REGNO_P(N) \ | |
1433 | (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) | |
3f3f2124 | 1434 | |
fc27f749 | 1435 | #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1436 | #define REX_INT_REGNO_P(N) \ |
1437 | IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
3f3f2124 | 1438 | |
66aaf16f UB |
1439 | #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) |
1440 | #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
fc27f749 | 1441 | |
446988df | 1442 | #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) |
66aaf16f | 1443 | #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) |
a7180f70 | 1444 | |
54a88090 | 1445 | #define X87_FLOAT_MODE_P(MODE) \ |
27ac40e2 | 1446 | (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) |
54a88090 | 1447 | |
fc27f749 | 1448 | #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) |
fb84c7a0 UB |
1449 | #define SSE_REGNO_P(N) \ |
1450 | (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
3f97cb0b AI |
1451 | || REX_SSE_REGNO_P (N) \ |
1452 | || EXT_REX_SSE_REGNO_P (N)) | |
3f3f2124 | 1453 | |
4977bab6 | 1454 | #define REX_SSE_REGNO_P(N) \ |
fb84c7a0 | 1455 | IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) |
4977bab6 | 1456 | |
3f97cb0b AI |
1457 | #define EXT_REX_SSE_REGNO_P(N) \ |
1458 | IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG) | |
1459 | ||
d9a5f180 | 1460 | #define SSE_REGNO(N) \ |
3f97cb0b AI |
1461 | ((N) < 8 ? FIRST_SSE_REG + (N) \ |
1462 | : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \ | |
1463 | : (FIRST_EXT_REX_SSE_REG + (N) - 16)) | |
1464 | ||
9e4a4dd6 | 1465 | #define MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) |
85a77221 AI |
1466 | #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG) |
1467 | #define ANY_MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X))) | |
446988df | 1468 | |
d9a5f180 | 1469 | #define SSE_FLOAT_MODE_P(MODE) \ |
91da27c5 | 1470 | ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) |
a7180f70 | 1471 | |
cbf2e4d4 HJ |
1472 | #define FMA4_VEC_FLOAT_MODE_P(MODE) \ |
1473 | (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1474 | || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1475 | ||
fc27f749 | 1476 | #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) |
fb84c7a0 | 1477 | #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) |
fce5a9f2 | 1478 | |
fc27f749 | 1479 | #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG) |
c98f8742 | 1480 | |
e075ae69 RH |
1481 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) |
1482 | #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1483 | ||
c98f8742 JVA |
1484 | /* The class value for index registers, and the one for base regs. */ |
1485 | ||
1486 | #define INDEX_REG_CLASS INDEX_REGS | |
1487 | #define BASE_REG_CLASS GENERAL_REGS | |
1488 | ||
c98f8742 | 1489 | /* Place additional restrictions on the register class to use when it |
4cbb525c | 1490 | is necessary to be able to hold a value of mode MODE in a reload |
b197fc48 UB |
1491 | register for which class CLASS would ordinarily be used. |
1492 | ||
1493 | We avoid classes containing registers from multiple units due to | |
1494 | the limitation in ix86_secondary_memory_needed. We limit these | |
1495 | classes to their "natural mode" single unit register class, depending | |
1496 | on the unit availability. | |
1497 | ||
1498 | Please note that reg_class_subset_p is not commutative, so these | |
1499 | conditions mean "... if (CLASS) includes ALL registers from the | |
1500 | register set." */ | |
1501 | ||
1502 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
1503 | (((MODE) == QImode && !TARGET_64BIT \ | |
1504 | && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ | |
1505 | : (((MODE) == SImode || (MODE) == DImode) \ | |
1506 | && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ | |
1507 | : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ | |
1508 | && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ | |
1509 | : (X87_FLOAT_MODE_P (MODE) \ | |
1510 | && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ | |
1511 | : (CLASS)) | |
c98f8742 | 1512 | |
85ff473e | 1513 | /* If we are copying between general and FP registers, we need a memory |
f84aa48a | 1514 | location. The same is true for SSE and MMX registers. */ |
d9a5f180 GS |
1515 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1516 | ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
e075ae69 | 1517 | |
c62b3659 UB |
1518 | /* Get_secondary_mem widens integral modes to BITS_PER_WORD. |
1519 | There is no need to emit full 64 bit move on 64 bit targets | |
1520 | for integral modes that can be moved using 32 bit move. */ | |
1521 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1522 | (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1523 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1524 | : MODE) | |
1525 | ||
1272914c RH |
1526 | /* Return a class of registers that cannot change FROM mode to TO mode. */ |
1527 | ||
1528 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1529 | ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
c98f8742 JVA |
1530 | \f |
1531 | /* Stack layout; function entry, exit and calling. */ | |
1532 | ||
1533 | /* Define this if pushing a word on the stack | |
1534 | makes the stack pointer a smaller address. */ | |
1535 | #define STACK_GROWS_DOWNWARD | |
1536 | ||
a4d05547 | 1537 | /* Define this to nonzero if the nominal address of the stack frame |
c98f8742 JVA |
1538 | is at the high-address end of the local variables; |
1539 | that is, each additional local variable allocated | |
1540 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1541 | #define FRAME_GROWS_DOWNWARD 1 |
c98f8742 JVA |
1542 | |
1543 | /* Offset within stack frame to start allocating local variables at. | |
1544 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1545 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1546 | of the first local allocated. */ | |
1547 | #define STARTING_FRAME_OFFSET 0 | |
1548 | ||
8c2b2fae UB |
1549 | /* If we generate an insn to push BYTES bytes, this says how many the stack |
1550 | pointer really advances by. On 386, we have pushw instruction that | |
1551 | decrements by exactly 2 no matter what the position was, there is no pushb. | |
1552 | ||
1553 | But as CIE data alignment factor on this arch is -4 for 32bit targets | |
1554 | and -8 for 64bit targets, we need to make sure all stack pointer adjustments | |
1555 | are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ | |
c98f8742 | 1556 | |
d2836273 | 1557 | #define PUSH_ROUNDING(BYTES) \ |
8c2b2fae UB |
1558 | (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) |
1559 | ||
1560 | /* If defined, the maximum amount of space required for outgoing arguments | |
1561 | will be computed and placed into the variable `crtl->outgoing_args_size'. | |
1562 | No space will be pushed onto the stack for each call; instead, the | |
1563 | function prologue should increase the stack frame size by this amount. | |
41ee845b JH |
1564 | |
1565 | In 32bit mode enabling argument accumulation results in about 5% code size | |
1566 | growth becuase move instructions are less compact than push. In 64bit | |
1567 | mode the difference is less drastic but visible. | |
1568 | ||
1569 | FIXME: Unlike earlier implementations, the size of unwind info seems to | |
f830ddc2 | 1570 | actually grow with accumulation. Is that because accumulated args |
41ee845b | 1571 | unwind info became unnecesarily bloated? |
f830ddc2 RH |
1572 | |
1573 | With the 64-bit MS ABI, we can generate correct code with or without | |
1574 | accumulated args, but because of OUTGOING_REG_PARM_STACK_SPACE the code | |
1575 | generated without accumulated args is terrible. | |
41ee845b JH |
1576 | |
1577 | If stack probes are required, the space used for large function | |
1578 | arguments on the stack must also be probed, so enable | |
1579 | -maccumulate-outgoing-args so this happens in the prologue. */ | |
f73ad30e | 1580 | |
6c6094f1 | 1581 | #define ACCUMULATE_OUTGOING_ARGS \ |
41ee845b JH |
1582 | ((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \ |
1583 | || TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI) | |
f73ad30e JH |
1584 | |
1585 | /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1586 | instructions to pass outgoing arguments. */ | |
1587 | ||
1588 | #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1589 | ||
2da4124d L |
1590 | /* We want the stack and args grow in opposite directions, even if |
1591 | PUSH_ARGS is 0. */ | |
1592 | #define PUSH_ARGS_REVERSED 1 | |
1593 | ||
c98f8742 JVA |
1594 | /* Offset of first parameter from the argument pointer register value. */ |
1595 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1596 | ||
a7180f70 BS |
1597 | /* Define this macro if functions should assume that stack space has been |
1598 | allocated for arguments even when their values are passed in registers. | |
1599 | ||
1600 | The value of this macro is the size, in bytes, of the area reserved for | |
1601 | arguments passed in registers for the function represented by FNDECL. | |
1602 | ||
1603 | This space can be allocated by the caller, or be a part of the | |
1604 | machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1605 | which. */ | |
7c800926 KT |
1606 | #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) |
1607 | ||
4ae8027b | 1608 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ |
6510e8bb | 1609 | (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) |
7c800926 | 1610 | |
c98f8742 JVA |
1611 | /* Define how to find the value returned by a library function |
1612 | assuming the value has mode MODE. */ | |
1613 | ||
4ae8027b | 1614 | #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) |
c98f8742 | 1615 | |
e9125c09 TW |
1616 | /* Define the size of the result block used for communication between |
1617 | untyped_call and untyped_return. The block contains a DImode value | |
1618 | followed by the block used by fnsave and frstor. */ | |
1619 | ||
1620 | #define APPLY_RESULT_SIZE (8+108) | |
1621 | ||
b08de47e | 1622 | /* 1 if N is a possible register number for function argument passing. */ |
53c17031 | 1623 | #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) |
c98f8742 JVA |
1624 | |
1625 | /* Define a data type for recording info about an argument list | |
1626 | during the scan of that argument list. This data type should | |
1627 | hold all necessary information about the function itself | |
1628 | and about the args processed so far, enough to enable macros | |
b08de47e | 1629 | such as FUNCTION_ARG to determine where the next arg should go. */ |
c98f8742 | 1630 | |
e075ae69 | 1631 | typedef struct ix86_args { |
fa283935 | 1632 | int words; /* # words passed so far */ |
b08de47e MM |
1633 | int nregs; /* # registers available for passing */ |
1634 | int regno; /* next available register number */ | |
3e65f251 KT |
1635 | int fastcall; /* fastcall or thiscall calling convention |
1636 | is used */ | |
fa283935 | 1637 | int sse_words; /* # sse words passed so far */ |
a7180f70 | 1638 | int sse_nregs; /* # sse registers available for passing */ |
223cdd15 UB |
1639 | int warn_avx512f; /* True when we want to warn |
1640 | about AVX512F ABI. */ | |
95879c72 | 1641 | int warn_avx; /* True when we want to warn about AVX ABI. */ |
47a37ce4 | 1642 | int warn_sse; /* True when we want to warn about SSE ABI. */ |
fa283935 UB |
1643 | int warn_mmx; /* True when we want to warn about MMX ABI. */ |
1644 | int sse_regno; /* next available sse register number */ | |
1645 | int mmx_words; /* # mmx words passed so far */ | |
bcf17554 JH |
1646 | int mmx_nregs; /* # mmx registers available for passing */ |
1647 | int mmx_regno; /* next available mmx register number */ | |
892a2d68 | 1648 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ |
2767a7f2 | 1649 | int caller; /* true if it is caller. */ |
2824d6e5 UB |
1650 | int float_in_sse; /* Set to 1 or 2 for 32bit targets if |
1651 | SFmode/DFmode arguments should be passed | |
1652 | in SSE registers. Otherwise 0. */ | |
51212b32 | 1653 | enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise |
7c800926 | 1654 | MS_ABI for ms abi. */ |
b08de47e | 1655 | } CUMULATIVE_ARGS; |
c98f8742 JVA |
1656 | |
1657 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1658 | for a call to a function whose data type is FNTYPE. | |
b08de47e | 1659 | For a library call, FNTYPE is 0. */ |
c98f8742 | 1660 | |
0f6937fe | 1661 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
2767a7f2 L |
1662 | init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ |
1663 | (N_NAMED_ARGS) != -1) | |
c98f8742 | 1664 | |
c98f8742 JVA |
1665 | /* Output assembler code to FILE to increment profiler label # LABELNO |
1666 | for profiling a function entry. */ | |
1667 | ||
a5fa1ecd JH |
1668 | #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) |
1669 | ||
1670 | #define MCOUNT_NAME "_mcount" | |
1671 | ||
3c5273a9 KT |
1672 | #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" |
1673 | ||
a5fa1ecd | 1674 | #define PROFILE_COUNT_REGISTER "edx" |
c98f8742 JVA |
1675 | |
1676 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1677 | the stack pointer does not matter. The value is tested only in | |
1678 | functions that have frame pointers. | |
1679 | No definition is equivalent to always zero. */ | |
fce5a9f2 | 1680 | /* Note on the 386 it might be more efficient not to define this since |
c98f8742 JVA |
1681 | we have to restore it ourselves from the frame pointer, in order to |
1682 | use pop */ | |
1683 | ||
1684 | #define EXIT_IGNORE_STACK 1 | |
1685 | ||
c98f8742 JVA |
1686 | /* Output assembler code for a block containing the constant parts |
1687 | of a trampoline, leaving space for the variable parts. */ | |
1688 | ||
a269a03c | 1689 | /* On the 386, the trampoline contains two instructions: |
c98f8742 | 1690 | mov #STATIC,ecx |
a269a03c JC |
1691 | jmp FUNCTION |
1692 | The trampoline is generated entirely at runtime. The operand of JMP | |
1693 | is the address of FUNCTION relative to the instruction following the | |
1694 | JMP (which is 5 bytes long). */ | |
c98f8742 JVA |
1695 | |
1696 | /* Length in units of the trampoline for entering a nested function. */ | |
1697 | ||
3452586b | 1698 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) |
c98f8742 JVA |
1699 | \f |
1700 | /* Definitions for register eliminations. | |
1701 | ||
1702 | This is an array of structures. Each structure initializes one pair | |
1703 | of eliminable registers. The "from" register number is given first, | |
1704 | followed by "to". Eliminations of the same "from" register are listed | |
1705 | in order of preference. | |
1706 | ||
afc2cd05 NC |
1707 | There are two registers that can always be eliminated on the i386. |
1708 | The frame pointer and the arg pointer can be replaced by either the | |
1709 | hard frame pointer or to the stack pointer, depending upon the | |
1710 | circumstances. The hard frame pointer is not used before reload and | |
1711 | so it is not eligible for elimination. */ | |
c98f8742 | 1712 | |
564d80f4 JH |
1713 | #define ELIMINABLE_REGS \ |
1714 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1715 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1716 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1717 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
c98f8742 | 1718 | |
c98f8742 JVA |
1719 | /* Define the offset between two registers, one to be eliminated, and the other |
1720 | its replacement, at the start of a routine. */ | |
1721 | ||
d9a5f180 GS |
1722 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1723 | ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
c98f8742 JVA |
1724 | \f |
1725 | /* Addressing modes, and classification of registers for them. */ | |
1726 | ||
c98f8742 JVA |
1727 | /* Macros to check register numbers against specific register classes. */ |
1728 | ||
1729 | /* These assume that REGNO is a hard or pseudo reg number. | |
1730 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1731 | or a pseudo reg currently allocated to a suitable hard reg. | |
1732 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1733 | has been allocated, which happens in reginfo.c during register |
1734 | allocation. */ | |
c98f8742 | 1735 | |
3f3f2124 JH |
1736 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
1737 | ((REGNO) < STACK_POINTER_REGNUM \ | |
fb84c7a0 UB |
1738 | || REX_INT_REGNO_P (REGNO) \ |
1739 | || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1740 | || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
c98f8742 | 1741 | |
3f3f2124 | 1742 | #define REGNO_OK_FOR_BASE_P(REGNO) \ |
fb84c7a0 | 1743 | (GENERAL_REGNO_P (REGNO) \ |
3f3f2124 JH |
1744 | || (REGNO) == ARG_POINTER_REGNUM \ |
1745 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
fb84c7a0 | 1746 | || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) |
c98f8742 | 1747 | |
c98f8742 JVA |
1748 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
1749 | and check its validity for a certain class. | |
1750 | We have two alternate definitions for each of them. | |
1751 | The usual definition accepts all pseudo regs; the other rejects | |
1752 | them unless they have been allocated suitable hard regs. | |
1753 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1754 | ||
1755 | Most source files want to accept pseudo regs in the hope that | |
1756 | they will get allocated to the class that the insn wants them to be in. | |
1757 | Source files for reload pass need to be strict. | |
1758 | After reload, it makes no difference, since pseudo regs have | |
1759 | been eliminated by then. */ | |
1760 | ||
c98f8742 | 1761 | |
ff482c8d | 1762 | /* Non strict versions, pseudos are ok. */ |
3b3c6a3f MM |
1763 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
1764 | (REGNO (X) < STACK_POINTER_REGNUM \ | |
fb84c7a0 | 1765 | || REX_INT_REGNO_P (REGNO (X)) \ |
c98f8742 JVA |
1766 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1767 | ||
3b3c6a3f | 1768 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ |
fb84c7a0 | 1769 | (GENERAL_REGNO_P (REGNO (X)) \ |
3b3c6a3f | 1770 | || REGNO (X) == ARG_POINTER_REGNUM \ |
3f3f2124 | 1771 | || REGNO (X) == FRAME_POINTER_REGNUM \ |
3b3c6a3f | 1772 | || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
c98f8742 | 1773 | |
3b3c6a3f MM |
1774 | /* Strict versions, hard registers only */ |
1775 | #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1776 | #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
c98f8742 | 1777 | |
3b3c6a3f | 1778 | #ifndef REG_OK_STRICT |
d9a5f180 GS |
1779 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
1780 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
3b3c6a3f MM |
1781 | |
1782 | #else | |
d9a5f180 GS |
1783 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) |
1784 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
c98f8742 JVA |
1785 | #endif |
1786 | ||
331d9186 | 1787 | /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression |
c98f8742 JVA |
1788 | that is a valid memory address for an instruction. |
1789 | The MODE argument is the machine mode for the MEM expression | |
1790 | that wants to use this address. | |
1791 | ||
331d9186 | 1792 | The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, |
c98f8742 JVA |
1793 | except for CONSTANT_ADDRESS_P which is usually machine-independent. |
1794 | ||
1795 | See legitimize_pic_address in i386.c for details as to what | |
1796 | constitutes a legitimate address when -fpic is used. */ | |
1797 | ||
1798 | #define MAX_REGS_PER_ADDRESS 2 | |
1799 | ||
f996902d | 1800 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
c98f8742 | 1801 | |
ae1547cc UB |
1802 | /* Try a machine-dependent way of reloading an illegitimate address |
1803 | operand. If we find one, push the reload and jump to WIN. This | |
1804 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
1805 | ||
1806 | #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ | |
1807 | do { \ | |
1808 | if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
1809 | (int)(TYPE), (INDL))) \ | |
1810 | goto WIN; \ | |
1811 | } while (0) | |
1812 | ||
b949ea8b JW |
1813 | /* If defined, a C expression to determine the base term of address X. |
1814 | This macro is used in only one place: `find_base_term' in alias.c. | |
1815 | ||
1816 | It is always safe for this macro to not be defined. It exists so | |
1817 | that alias analysis can understand machine-dependent addresses. | |
1818 | ||
1819 | The typical use of this macro is to handle addresses containing | |
1820 | a label_ref or symbol_ref within an UNSPEC. */ | |
1821 | ||
d9a5f180 | 1822 | #define FIND_BASE_TERM(X) ix86_find_base_term (X) |
b949ea8b | 1823 | |
c98f8742 | 1824 | /* Nonzero if the constant value X is a legitimate general operand |
fce5a9f2 | 1825 | when generating PIC code. It is given that flag_pic is on and |
c98f8742 JVA |
1826 | that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
1827 | ||
f996902d | 1828 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
c98f8742 JVA |
1829 | |
1830 | #define SYMBOLIC_CONST(X) \ | |
d9a5f180 GS |
1831 | (GET_CODE (X) == SYMBOL_REF \ |
1832 | || GET_CODE (X) == LABEL_REF \ | |
1833 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
c98f8742 | 1834 | \f |
b08de47e MM |
1835 | /* Max number of args passed in registers. If this is more than 3, we will |
1836 | have problems with ebx (register #4), since it is a caller save register and | |
1837 | is also used as the pic register in ELF. So for now, don't allow more than | |
1838 | 3 registers to be passed in registers. */ | |
1839 | ||
7c800926 KT |
1840 | /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ |
1841 | #define X86_64_REGPARM_MAX 6 | |
72fa3605 | 1842 | #define X86_64_MS_REGPARM_MAX 4 |
7c800926 | 1843 | |
72fa3605 | 1844 | #define X86_32_REGPARM_MAX 3 |
7c800926 | 1845 | |
4ae8027b | 1846 | #define REGPARM_MAX \ |
2824d6e5 UB |
1847 | (TARGET_64BIT \ |
1848 | ? (TARGET_64BIT_MS_ABI \ | |
1849 | ? X86_64_MS_REGPARM_MAX \ | |
1850 | : X86_64_REGPARM_MAX) \ | |
4ae8027b | 1851 | : X86_32_REGPARM_MAX) |
d2836273 | 1852 | |
72fa3605 UB |
1853 | #define X86_64_SSE_REGPARM_MAX 8 |
1854 | #define X86_64_MS_SSE_REGPARM_MAX 4 | |
1855 | ||
b6010cab | 1856 | #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) |
72fa3605 | 1857 | |
4ae8027b | 1858 | #define SSE_REGPARM_MAX \ |
2824d6e5 UB |
1859 | (TARGET_64BIT \ |
1860 | ? (TARGET_64BIT_MS_ABI \ | |
1861 | ? X86_64_MS_SSE_REGPARM_MAX \ | |
1862 | : X86_64_SSE_REGPARM_MAX) \ | |
4ae8027b | 1863 | : X86_32_SSE_REGPARM_MAX) |
bcf17554 JH |
1864 | |
1865 | #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
c98f8742 JVA |
1866 | \f |
1867 | /* Specify the machine mode that this machine uses | |
1868 | for the index in the tablejump instruction. */ | |
dc4d7240 | 1869 | #define CASE_VECTOR_MODE \ |
6025b127 | 1870 | (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) |
c98f8742 | 1871 | |
c98f8742 JVA |
1872 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1873 | #define DEFAULT_SIGNED_CHAR 1 | |
1874 | ||
1875 | /* Max number of bytes we can move from memory to memory | |
1876 | in one reasonably fast instruction. */ | |
65d9c0ab JH |
1877 | #define MOVE_MAX 16 |
1878 | ||
1879 | /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1880 | move efficiently, as opposed to MOVE_MAX which is the maximum | |
892a2d68 | 1881 | number of bytes we can move with a single instruction. */ |
63001560 | 1882 | #define MOVE_MAX_PIECES UNITS_PER_WORD |
c98f8742 | 1883 | |
7e24ffc9 | 1884 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1885 | move-instruction pairs, we will do a movmem or libcall instead. |
7e24ffc9 HPN |
1886 | Increasing the value will always make code faster, but eventually |
1887 | incurs high cost in increased code size. | |
c98f8742 | 1888 | |
e2e52e1b | 1889 | If you don't define this, a reasonable default is used. */ |
c98f8742 | 1890 | |
e04ad03d | 1891 | #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) |
c98f8742 | 1892 | |
45d78e7f JJ |
1893 | /* If a clear memory operation would take CLEAR_RATIO or more simple |
1894 | move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1895 | ||
e04ad03d | 1896 | #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) |
45d78e7f | 1897 | |
53f00dde UB |
1898 | /* Define if shifts truncate the shift count which implies one can |
1899 | omit a sign-extension or zero-extension of a shift count. | |
1900 | ||
1901 | On i386, shifts do truncate the count. But bit test instructions | |
1902 | take the modulo of the bit offset operand. */ | |
c98f8742 JVA |
1903 | |
1904 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1905 | ||
1906 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1907 | is done just by pretending it is already truncated. */ | |
1908 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1909 | ||
d9f32422 JH |
1910 | /* A macro to update M and UNSIGNEDP when an object whose type is |
1911 | TYPE and which has the specified mode and signedness is to be | |
1912 | stored in a register. This macro is only called when TYPE is a | |
1913 | scalar type. | |
1914 | ||
f710504c | 1915 | On i386 it is sometimes useful to promote HImode and QImode |
d9f32422 JH |
1916 | quantities to SImode. The choice depends on target type. */ |
1917 | ||
1918 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
d9a5f180 | 1919 | do { \ |
d9f32422 JH |
1920 | if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ |
1921 | || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
d9a5f180 GS |
1922 | (MODE) = SImode; \ |
1923 | } while (0) | |
d9f32422 | 1924 | |
c98f8742 JVA |
1925 | /* Specify the machine mode that pointers have. |
1926 | After generation of rtl, the compiler makes no further distinction | |
1927 | between pointers and any other objects of this machine mode. */ | |
28968d91 | 1928 | #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) |
c98f8742 | 1929 | |
f0ea7581 L |
1930 | /* A C expression whose value is zero if pointers that need to be extended |
1931 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and | |
1932 | greater then zero if they are zero-extended and less then zero if the | |
1933 | ptr_extend instruction should be used. */ | |
1934 | ||
1935 | #define POINTERS_EXTEND_UNSIGNED 1 | |
1936 | ||
c98f8742 JVA |
1937 | /* A function address in a call instruction |
1938 | is a byte address (for indexing purposes) | |
1939 | so give the MEM rtx a byte's mode. */ | |
1940 | #define FUNCTION_MODE QImode | |
d4ba09c0 | 1941 | \f |
d4ba09c0 | 1942 | |
d4ba09c0 SC |
1943 | /* A C expression for the cost of a branch instruction. A value of 1 |
1944 | is the default; other values are interpreted relative to that. */ | |
1945 | ||
3a4fd356 JH |
1946 | #define BRANCH_COST(speed_p, predictable_p) \ |
1947 | (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
d4ba09c0 | 1948 | |
e327d1a3 L |
1949 | /* An integer expression for the size in bits of the largest integer machine |
1950 | mode that should actually be used. We allow pairs of registers. */ | |
1951 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
1952 | ||
d4ba09c0 SC |
1953 | /* Define this macro as a C expression which is nonzero if accessing |
1954 | less than a word of memory (i.e. a `char' or a `short') is no | |
1955 | faster than accessing a word of memory, i.e., if such access | |
1956 | require more than one instruction or if there is no difference in | |
1957 | cost between byte and (aligned) word loads. | |
1958 | ||
1959 | When this macro is not defined, the compiler will access a field by | |
1960 | finding the smallest containing object; when it is defined, a | |
1961 | fullword load will be used if alignment permits. Unless bytes | |
1962 | accesses are faster than word accesses, using word accesses is | |
1963 | preferable since it may eliminate subsequent memory access if | |
1964 | subsequent accesses occur to other fields in the same word of the | |
1965 | structure, but to different bytes. */ | |
1966 | ||
1967 | #define SLOW_BYTE_ACCESS 0 | |
1968 | ||
1969 | /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1970 | #define SLOW_SHORT_ACCESS 0 | |
1971 | ||
d4ba09c0 SC |
1972 | /* Define this macro to be the value 1 if unaligned accesses have a |
1973 | cost many times greater than aligned accesses, for example if they | |
1974 | are emulated in a trap handler. | |
1975 | ||
9cd10576 KH |
1976 | When this macro is nonzero, the compiler will act as if |
1977 | `STRICT_ALIGNMENT' were nonzero when generating code for block | |
d4ba09c0 | 1978 | moves. This can cause significantly more instructions to be |
9cd10576 | 1979 | produced. Therefore, do not set this macro nonzero if unaligned |
d4ba09c0 SC |
1980 | accesses only add a cycle or two to the time for a memory access. |
1981 | ||
1982 | If the value of this macro is always zero, it need not be defined. */ | |
1983 | ||
e1565e65 | 1984 | /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ |
d4ba09c0 | 1985 | |
d4ba09c0 SC |
1986 | /* Define this macro if it is as good or better to call a constant |
1987 | function address than to call an address kept in a register. | |
1988 | ||
1989 | Desirable on the 386 because a CALL with a constant address is | |
1990 | faster than one with a register address. */ | |
1991 | ||
1992 | #define NO_FUNCTION_CSE | |
c98f8742 | 1993 | \f |
c572e5ba JVA |
1994 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
1995 | return the mode to be used for the comparison. | |
1996 | ||
1997 | For floating-point equality comparisons, CCFPEQmode should be used. | |
e075ae69 | 1998 | VOIDmode should be used in all other cases. |
c572e5ba | 1999 | |
16189740 | 2000 | For integer comparisons against zero, reduce to CCNOmode or CCZmode if |
e075ae69 | 2001 | possible, to allow for more combinations. */ |
c98f8742 | 2002 | |
d9a5f180 | 2003 | #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) |
9e7adcb3 | 2004 | |
9cd10576 | 2005 | /* Return nonzero if MODE implies a floating point inequality can be |
9e7adcb3 JH |
2006 | reversed. */ |
2007 | ||
2008 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
2009 | ||
2010 | /* A C expression whose value is reversed condition code of the CODE for | |
2011 | comparison done in CC_MODE mode. */ | |
3c5cb3e4 | 2012 | #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) |
9e7adcb3 | 2013 | |
c98f8742 JVA |
2014 | \f |
2015 | /* Control the assembler format that we output, to the extent | |
2016 | this does not vary between assemblers. */ | |
2017 | ||
2018 | /* How to refer to registers in assembler output. | |
892a2d68 | 2019 | This sequence is indexed by compiler's hard-register-number (see above). */ |
c98f8742 | 2020 | |
a7b376ee | 2021 | /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". |
c98f8742 JVA |
2022 | For non floating point regs, the following are the HImode names. |
2023 | ||
2024 | For float regs, the stack top is sometimes referred to as "%st(0)" | |
6e2188e0 NF |
2025 | instead of just "%st". TARGET_PRINT_OPERAND handles this with the |
2026 | "y" code. */ | |
c98f8742 | 2027 | |
a7180f70 BS |
2028 | #define HI_REGISTER_NAMES \ |
2029 | {"ax","dx","cx","bx","si","di","bp","sp", \ | |
480feac0 | 2030 | "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ |
b0d95de8 | 2031 | "argp", "flags", "fpsr", "fpcr", "frame", \ |
a7180f70 | 2032 | "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ |
03c259ad | 2033 | "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ |
3f3f2124 | 2034 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ |
3f97cb0b AI |
2035 | "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \ |
2036 | "xmm16", "xmm17", "xmm18", "xmm19", \ | |
2037 | "xmm20", "xmm21", "xmm22", "xmm23", \ | |
2038 | "xmm24", "xmm25", "xmm26", "xmm27", \ | |
85a77221 | 2039 | "xmm28", "xmm29", "xmm30", "xmm31", \ |
089d1227 | 2040 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" } |
a7180f70 | 2041 | |
c98f8742 JVA |
2042 | #define REGISTER_NAMES HI_REGISTER_NAMES |
2043 | ||
2044 | /* Table of additional register names to use in user input. */ | |
2045 | ||
2046 | #define ADDITIONAL_REGISTER_NAMES \ | |
7c831c4d KY |
2047 | { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ |
2048 | { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2049 | { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
2050 | { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
2051 | { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2052 | { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \ | |
2053 | { "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \ | |
2054 | { "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \ | |
2055 | { "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \ | |
2056 | { "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \ | |
2057 | { "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \ | |
2058 | { "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \ | |
2059 | { "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \ | |
2060 | { "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \ | |
2061 | { "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \ | |
2062 | { "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \ | |
2063 | { "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \ | |
2064 | { "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \ | |
2065 | { "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \ | |
2066 | { "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \ | |
2067 | { "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \ | |
2068 | { "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} } | |
c98f8742 JVA |
2069 | |
2070 | /* Note we are omitting these since currently I don't know how | |
2071 | to get gcc to use these, since they want the same but different | |
2072 | number as al, and ax. | |
2073 | */ | |
2074 | ||
c98f8742 | 2075 | #define QI_REGISTER_NAMES \ |
3f3f2124 | 2076 | {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} |
c98f8742 JVA |
2077 | |
2078 | /* These parallel the array above, and can be used to access bits 8:15 | |
892a2d68 | 2079 | of regs 0 through 3. */ |
c98f8742 JVA |
2080 | |
2081 | #define QI_HIGH_REGISTER_NAMES \ | |
2082 | {"ah", "dh", "ch", "bh", } | |
2083 | ||
2084 | /* How to renumber registers for dbx and gdb. */ | |
2085 | ||
d9a5f180 GS |
2086 | #define DBX_REGISTER_NUMBER(N) \ |
2087 | (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
83774849 | 2088 | |
9a82e702 MS |
2089 | extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; |
2090 | extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2091 | extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
c98f8742 | 2092 | |
780a5b71 UB |
2093 | extern int const x86_64_ms_sysv_extra_clobbered_registers[12]; |
2094 | ||
469ac993 JM |
2095 | /* Before the prologue, RA is at 0(%esp). */ |
2096 | #define INCOMING_RETURN_ADDR_RTX \ | |
f64cecad | 2097 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) |
fce5a9f2 | 2098 | |
e414ab29 | 2099 | /* After the prologue, RA is at -4(AP) in the current frame. */ |
1020a5ab RH |
2100 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
2101 | ((COUNT) == 0 \ | |
0a81f074 RS |
2102 | ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ |
2103 | -UNITS_PER_WORD)) \ | |
2104 | : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) | |
e414ab29 | 2105 | |
892a2d68 | 2106 | /* PC is dbx register 8; let's use that column for RA. */ |
0f7fa3d0 | 2107 | #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) |
469ac993 | 2108 | |
a6ab3aad | 2109 | /* Before the prologue, the top of the frame is at 4(%esp). */ |
0f7fa3d0 | 2110 | #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD |
a6ab3aad | 2111 | |
1020a5ab | 2112 | /* Describe how we implement __builtin_eh_return. */ |
2824d6e5 UB |
2113 | #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) |
2114 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) | |
1020a5ab | 2115 | |
ad919812 | 2116 | |
e4c4ebeb RH |
2117 | /* Select a format to encode pointers in exception handling data. CODE |
2118 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2119 | true if the symbol may be affected by dynamic relocations. | |
2120 | ||
2121 | ??? All x86 object file formats are capable of representing this. | |
2122 | After all, the relocation needed is the same as for the call insn. | |
2123 | Whether or not a particular assembler allows us to enter such, I | |
2124 | guess we'll have to see. */ | |
d9a5f180 | 2125 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
72ce3d4a | 2126 | asm_preferred_eh_data_format ((CODE), (GLOBAL)) |
e4c4ebeb | 2127 | |
c98f8742 JVA |
2128 | /* This is how to output an insn to push a register on the stack. |
2129 | It need not be very fast code. */ | |
2130 | ||
d9a5f180 | 2131 | #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ |
0d1c5774 JJ |
2132 | do { \ |
2133 | if (TARGET_64BIT) \ | |
2134 | asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2135 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2136 | else \ | |
2137 | asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2138 | } while (0) | |
c98f8742 JVA |
2139 | |
2140 | /* This is how to output an insn to pop a register from the stack. | |
2141 | It need not be very fast code. */ | |
2142 | ||
d9a5f180 | 2143 | #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ |
0d1c5774 JJ |
2144 | do { \ |
2145 | if (TARGET_64BIT) \ | |
2146 | asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2147 | reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2148 | else \ | |
2149 | asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2150 | } while (0) | |
c98f8742 | 2151 | |
f88c65f7 | 2152 | /* This is how to output an element of a case-vector that is absolute. */ |
c98f8742 JVA |
2153 | |
2154 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
d9a5f180 | 2155 | ix86_output_addr_vec_elt ((FILE), (VALUE)) |
c98f8742 | 2156 | |
f88c65f7 | 2157 | /* This is how to output an element of a case-vector that is relative. */ |
c98f8742 | 2158 | |
33f7f353 | 2159 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
d9a5f180 | 2160 | ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) |
f88c65f7 | 2161 | |
63001560 | 2162 | /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ |
95879c72 L |
2163 | |
2164 | #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2165 | { \ | |
2166 | if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
63001560 | 2167 | (PTR) += TARGET_AVX ? 1 : 2; \ |
95879c72 L |
2168 | } |
2169 | ||
2170 | /* A C statement or statements which output an assembler instruction | |
2171 | opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2172 | variable of type `char *' which points to the opcode name in | |
2173 | its "internal" form--the form that is written in the machine | |
2174 | description. */ | |
2175 | ||
2176 | #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2177 | ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2178 | ||
6a90d232 L |
2179 | /* A C statement to output to the stdio stream FILE an assembler |
2180 | command to pad the location counter to a multiple of 1<<LOG | |
2181 | bytes if it is within MAX_SKIP bytes. */ | |
2182 | ||
2183 | #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN | |
2184 | #undef ASM_OUTPUT_MAX_SKIP_PAD | |
2185 | #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ | |
2186 | if ((LOG) != 0) \ | |
2187 | { \ | |
2188 | if ((MAX_SKIP) == 0) \ | |
2189 | fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ | |
2190 | else \ | |
2191 | fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ | |
2192 | } | |
2193 | #endif | |
2194 | ||
135a687e KT |
2195 | /* Write the extra assembler code needed to declare a function |
2196 | properly. */ | |
2197 | ||
2198 | #undef ASM_OUTPUT_FUNCTION_LABEL | |
2199 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
2200 | ix86_asm_output_function_label (FILE, NAME, DECL) | |
2201 | ||
f7288899 EC |
2202 | /* Under some conditions we need jump tables in the text section, |
2203 | because the assembler cannot handle label differences between | |
2204 | sections. This is the case for x86_64 on Mach-O for example. */ | |
f88c65f7 RH |
2205 | |
2206 | #define JUMP_TABLES_IN_TEXT_SECTION \ | |
f7288899 EC |
2207 | (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ |
2208 | || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
c98f8742 | 2209 | |
cea3bd3e RH |
2210 | /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, |
2211 | and switch back. For x86 we do this only to save a few bytes that | |
2212 | would otherwise be unused in the text section. */ | |
ad211091 KT |
2213 | #define CRT_MKSTR2(VAL) #VAL |
2214 | #define CRT_MKSTR(x) CRT_MKSTR2(x) | |
2215 | ||
2216 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2217 | asm (SECTION_OP "\n\t" \ | |
2218 | "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ | |
cea3bd3e | 2219 | TEXT_SECTION_ASM_OP); |
5a579c3b LE |
2220 | |
2221 | /* Default threshold for putting data in large sections | |
2222 | with x86-64 medium memory model */ | |
2223 | #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 | |
74b42c8b | 2224 | \f |
b97de419 L |
2225 | /* Which processor to tune code generation for. These must be in sync |
2226 | with processor_target_table in i386.c. */ | |
5bf0ebab RH |
2227 | |
2228 | enum processor_type | |
2229 | { | |
b97de419 L |
2230 | PROCESSOR_GENERIC = 0, |
2231 | PROCESSOR_I386, /* 80386 */ | |
5bf0ebab RH |
2232 | PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ |
2233 | PROCESSOR_PENTIUM, | |
2234 | PROCESSOR_PENTIUMPRO, | |
5bf0ebab | 2235 | PROCESSOR_PENTIUM4, |
89c43c0a | 2236 | PROCESSOR_NOCONA, |
340ef734 | 2237 | PROCESSOR_CORE2, |
d3c11974 L |
2238 | PROCESSOR_NEHALEM, |
2239 | PROCESSOR_SANDYBRIDGE, | |
3a579e09 | 2240 | PROCESSOR_HASWELL, |
d3c11974 L |
2241 | PROCESSOR_BONNELL, |
2242 | PROCESSOR_SILVERMONT, | |
9a7f94d7 | 2243 | PROCESSOR_INTEL, |
b97de419 L |
2244 | PROCESSOR_GEODE, |
2245 | PROCESSOR_K6, | |
2246 | PROCESSOR_ATHLON, | |
2247 | PROCESSOR_K8, | |
21efb4d4 | 2248 | PROCESSOR_AMDFAM10, |
1133125e | 2249 | PROCESSOR_BDVER1, |
4d652a18 | 2250 | PROCESSOR_BDVER2, |
eb2f2b44 | 2251 | PROCESSOR_BDVER3, |
ed97ad47 | 2252 | PROCESSOR_BDVER4, |
14b52538 | 2253 | PROCESSOR_BTVER1, |
e32bfc16 | 2254 | PROCESSOR_BTVER2, |
5bf0ebab RH |
2255 | PROCESSOR_max |
2256 | }; | |
2257 | ||
9e555526 | 2258 | extern enum processor_type ix86_tune; |
5bf0ebab | 2259 | extern enum processor_type ix86_arch; |
5bf0ebab | 2260 | |
8362f420 JH |
2261 | /* Size of the RED_ZONE area. */ |
2262 | #define RED_ZONE_SIZE 128 | |
2263 | /* Reserved area of the red zone for temporaries. */ | |
2264 | #define RED_ZONE_RESERVE 8 | |
c93e80a5 | 2265 | |
95899b34 | 2266 | extern unsigned int ix86_preferred_stack_boundary; |
2e3f842f | 2267 | extern unsigned int ix86_incoming_stack_boundary; |
5bf0ebab RH |
2268 | |
2269 | /* Smallest class containing REGNO. */ | |
2270 | extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2271 | ||
0948ccb2 PB |
2272 | enum ix86_fpcmp_strategy { |
2273 | IX86_FPCMP_SAHF, | |
2274 | IX86_FPCMP_COMI, | |
2275 | IX86_FPCMP_ARITH | |
2276 | }; | |
22fb740d JH |
2277 | \f |
2278 | /* To properly truncate FP values into integers, we need to set i387 control | |
2279 | word. We can't emit proper mode switching code before reload, as spills | |
2280 | generated by reload may truncate values incorrectly, but we still can avoid | |
2281 | redundant computation of new control word by the mode switching pass. | |
2282 | The fldcw instructions are still emitted redundantly, but this is probably | |
2283 | not going to be noticeable problem, as most CPUs do have fast path for | |
fce5a9f2 | 2284 | the sequence. |
22fb740d JH |
2285 | |
2286 | The machinery is to emit simple truncation instructions and split them | |
2287 | before reload to instructions having USEs of two memory locations that | |
2288 | are filled by this code to old and new control word. | |
fce5a9f2 | 2289 | |
22fb740d JH |
2290 | Post-reload pass may be later used to eliminate the redundant fildcw if |
2291 | needed. */ | |
2292 | ||
ff680eb1 UB |
2293 | enum ix86_entity |
2294 | { | |
ff97910d VY |
2295 | AVX_U128 = 0, |
2296 | I387_TRUNC, | |
ff680eb1 UB |
2297 | I387_FLOOR, |
2298 | I387_CEIL, | |
2299 | I387_MASK_PM, | |
2300 | MAX_386_ENTITIES | |
2301 | }; | |
2302 | ||
1cba2b96 | 2303 | enum ix86_stack_slot |
ff680eb1 | 2304 | { |
443ca5fc | 2305 | SLOT_TEMP = 0, |
ff680eb1 UB |
2306 | SLOT_CW_STORED, |
2307 | SLOT_CW_TRUNC, | |
2308 | SLOT_CW_FLOOR, | |
2309 | SLOT_CW_CEIL, | |
2310 | SLOT_CW_MASK_PM, | |
2311 | MAX_386_STACK_LOCALS | |
2312 | }; | |
22fb740d | 2313 | |
ff97910d VY |
2314 | enum avx_u128_state |
2315 | { | |
2316 | AVX_U128_CLEAN, | |
2317 | AVX_U128_DIRTY, | |
2318 | AVX_U128_ANY | |
2319 | }; | |
2320 | ||
22fb740d JH |
2321 | /* Define this macro if the port needs extra instructions inserted |
2322 | for mode switching in an optimizing compilation. */ | |
2323 | ||
ff680eb1 UB |
2324 | #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ |
2325 | ix86_optimize_mode_switching[(ENTITY)] | |
22fb740d JH |
2326 | |
2327 | /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2328 | initializer for an array of integers. Each initializer element N | |
2329 | refers to an entity that needs mode switching, and specifies the | |
2330 | number of different modes that might need to be set for this | |
2331 | entity. The position of the initializer in the initializer - | |
2332 | starting counting at zero - determines the integer that is used to | |
2333 | refer to the mode-switched entity in question. */ | |
2334 | ||
ff680eb1 | 2335 | #define NUM_MODES_FOR_MODE_SWITCHING \ |
ff97910d | 2336 | { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } |
22fb740d | 2337 | |
0f0138b6 JH |
2338 | \f |
2339 | /* Avoid renaming of stack registers, as doing so in combination with | |
2340 | scheduling just increases amount of live registers at time and in | |
2341 | the turn amount of fxch instructions needed. | |
2342 | ||
3f97cb0b AI |
2343 | ??? Maybe Pentium chips benefits from renaming, someone can try.... |
2344 | ||
2345 | Don't rename evex to non-evex sse registers. */ | |
0f0138b6 | 2346 | |
3f97cb0b AI |
2347 | #define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \ |
2348 | (EXT_REX_SSE_REGNO_P (SRC) == \ | |
2349 | EXT_REX_SSE_REGNO_P (TARGET))) | |
22fb740d | 2350 | |
3b3c6a3f | 2351 | \f |
e91f04de | 2352 | #define FASTCALL_PREFIX '@' |
fa1a0d02 | 2353 | \f |
ec7ded37 | 2354 | /* Machine specific frame tracking during prologue/epilogue generation. */ |
cd9c1ca8 | 2355 | |
604a6be9 | 2356 | #ifndef USED_FOR_TARGET |
ec7ded37 | 2357 | struct GTY(()) machine_frame_state |
cd9c1ca8 | 2358 | { |
ec7ded37 RH |
2359 | /* This pair tracks the currently active CFA as reg+offset. When reg |
2360 | is drap_reg, we don't bother trying to record here the real CFA when | |
2361 | it might really be a DW_CFA_def_cfa_expression. */ | |
2362 | rtx cfa_reg; | |
2363 | HOST_WIDE_INT cfa_offset; | |
2364 | ||
2365 | /* The current offset (canonically from the CFA) of ESP and EBP. | |
2366 | When stack frame re-alignment is active, these may not be relative | |
2367 | to the CFA. However, in all cases they are relative to the offsets | |
2368 | of the saved registers stored in ix86_frame. */ | |
2369 | HOST_WIDE_INT sp_offset; | |
2370 | HOST_WIDE_INT fp_offset; | |
2371 | ||
2372 | /* The size of the red-zone that may be assumed for the purposes of | |
2373 | eliding register restore notes in the epilogue. This may be zero | |
2374 | if no red-zone is in effect, or may be reduced from the real | |
2375 | red-zone value by a maximum runtime stack re-alignment value. */ | |
2376 | int red_zone_offset; | |
2377 | ||
2378 | /* Indicate whether each of ESP, EBP or DRAP currently holds a valid | |
2379 | value within the frame. If false then the offset above should be | |
2380 | ignored. Note that DRAP, if valid, *always* points to the CFA and | |
2381 | thus has an offset of zero. */ | |
2382 | BOOL_BITFIELD sp_valid : 1; | |
2383 | BOOL_BITFIELD fp_valid : 1; | |
2384 | BOOL_BITFIELD drap_valid : 1; | |
c9f4c451 RH |
2385 | |
2386 | /* Indicate whether the local stack frame has been re-aligned. When | |
2387 | set, the SP/FP offsets above are relative to the aligned frame | |
2388 | and not the CFA. */ | |
2389 | BOOL_BITFIELD realigned : 1; | |
cd9c1ca8 RH |
2390 | }; |
2391 | ||
f81c9774 RH |
2392 | /* Private to winnt.c. */ |
2393 | struct seh_frame_state; | |
2394 | ||
d1b38208 | 2395 | struct GTY(()) machine_function { |
fa1a0d02 JH |
2396 | struct stack_local_entry *stack_locals; |
2397 | const char *some_ld_name; | |
4aab97f9 L |
2398 | int varargs_gpr_size; |
2399 | int varargs_fpr_size; | |
ff680eb1 | 2400 | int optimize_mode_switching[MAX_386_ENTITIES]; |
3452586b RH |
2401 | |
2402 | /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE | |
2403 | has been computed for. */ | |
2404 | int use_fast_prologue_epilogue_nregs; | |
2405 | ||
7458026b ILT |
2406 | /* For -fsplit-stack support: A stack local which holds a pointer to |
2407 | the stack arguments for a function with a variable number of | |
2408 | arguments. This is set at the start of the function and is used | |
2409 | to initialize the overflow_arg_area field of the va_list | |
2410 | structure. */ | |
2411 | rtx split_stack_varargs_pointer; | |
2412 | ||
3452586b RH |
2413 | /* This value is used for amd64 targets and specifies the current abi |
2414 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
25efe060 | 2415 | ENUM_BITFIELD(calling_abi) call_abi : 8; |
3452586b RH |
2416 | |
2417 | /* Nonzero if the function accesses a previous frame. */ | |
2418 | BOOL_BITFIELD accesses_prev_frame : 1; | |
2419 | ||
2420 | /* Nonzero if the function requires a CLD in the prologue. */ | |
2421 | BOOL_BITFIELD needs_cld : 1; | |
2422 | ||
922e3e33 UB |
2423 | /* Set by ix86_compute_frame_layout and used by prologue/epilogue |
2424 | expander to determine the style used. */ | |
3452586b RH |
2425 | BOOL_BITFIELD use_fast_prologue_epilogue : 1; |
2426 | ||
5bf5a10b AO |
2427 | /* If true, the current function needs the default PIC register, not |
2428 | an alternate register (on x86) and must not use the red zone (on | |
2429 | x86_64), even if it's a leaf function. We don't want the | |
2430 | function to be regarded as non-leaf because TLS calls need not | |
2431 | affect register allocation. This flag is set when a TLS call | |
2432 | instruction is expanded within a function, and never reset, even | |
2433 | if all such instructions are optimized away. Use the | |
2434 | ix86_current_function_calls_tls_descriptor macro for a better | |
2435 | approximation. */ | |
3452586b RH |
2436 | BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; |
2437 | ||
2438 | /* If true, the current function has a STATIC_CHAIN is placed on the | |
2439 | stack below the return address. */ | |
2440 | BOOL_BITFIELD static_chain_on_stack : 1; | |
25efe060 | 2441 | |
529a6471 JJ |
2442 | /* If true, it is safe to not save/restore DRAP register. */ |
2443 | BOOL_BITFIELD no_drap_save_restore : 1; | |
2444 | ||
ec7ded37 RH |
2445 | /* During prologue/epilogue generation, the current frame state. |
2446 | Otherwise, the frame state at the end of the prologue. */ | |
2447 | struct machine_frame_state fs; | |
f81c9774 RH |
2448 | |
2449 | /* During SEH output, this is non-null. */ | |
2450 | struct seh_frame_state * GTY((skip(""))) seh; | |
fa1a0d02 | 2451 | }; |
cd9c1ca8 | 2452 | #endif |
fa1a0d02 JH |
2453 | |
2454 | #define ix86_stack_locals (cfun->machine->stack_locals) | |
4aab97f9 L |
2455 | #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) |
2456 | #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
fa1a0d02 | 2457 | #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) |
922e3e33 | 2458 | #define ix86_current_function_needs_cld (cfun->machine->needs_cld) |
5bf5a10b AO |
2459 | #define ix86_tls_descriptor_calls_expanded_in_cfun \ |
2460 | (cfun->machine->tls_descriptor_call_expanded_p) | |
2461 | /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2462 | calls are optimized away, we try to detect cases in which it was | |
2463 | optimized away. Since such instructions (use (reg REG_SP)), we can | |
2464 | verify whether there's any such instruction live by testing that | |
2465 | REG_SP is live. */ | |
2466 | #define ix86_current_function_calls_tls_descriptor \ | |
6fb5fa3c | 2467 | (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) |
3452586b | 2468 | #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) |
249e6b63 | 2469 | |
1bc7c5b6 ZW |
2470 | /* Control behavior of x86_file_start. */ |
2471 | #define X86_FILE_START_VERSION_DIRECTIVE false | |
2472 | #define X86_FILE_START_FLTUSED false | |
2473 | ||
7dcbf659 JH |
2474 | /* Flag to mark data that is in the large address area. */ |
2475 | #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2476 | #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2477 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
da489f73 RH |
2478 | |
2479 | /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2480 | have defined always, to avoid ifdefing. */ | |
2481 | #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2482 | #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2483 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2484 | ||
2485 | #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2486 | #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2487 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2488 | ||
82c0e1a0 KT |
2489 | #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4) |
2490 | #define SYMBOL_REF_STUBVAR_P(X) \ | |
2491 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0) | |
2492 | ||
7942e47e RY |
2493 | extern void debug_ready_dispatch (void); |
2494 | extern void debug_dispatch_window (int); | |
2495 | ||
91afcfa3 QN |
2496 | /* The value at zero is only defined for the BMI instructions |
2497 | LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ | |
2498 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
2499 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI) | |
2500 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
5fcafa60 | 2501 | ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT) |
91afcfa3 QN |
2502 | |
2503 | ||
b8ce4e94 KT |
2504 | /* Flags returned by ix86_get_callcvt (). */ |
2505 | #define IX86_CALLCVT_CDECL 0x1 | |
2506 | #define IX86_CALLCVT_STDCALL 0x2 | |
2507 | #define IX86_CALLCVT_FASTCALL 0x4 | |
2508 | #define IX86_CALLCVT_THISCALL 0x8 | |
2509 | #define IX86_CALLCVT_REGPARM 0x10 | |
2510 | #define IX86_CALLCVT_SSEREGPARM 0x20 | |
2511 | ||
2512 | #define IX86_BASE_CALLCVT(FLAGS) \ | |
2513 | ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ | |
2514 | | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) | |
2515 | ||
b86b9f44 MM |
2516 | #define RECIP_MASK_NONE 0x00 |
2517 | #define RECIP_MASK_DIV 0x01 | |
2518 | #define RECIP_MASK_SQRT 0x02 | |
2519 | #define RECIP_MASK_VEC_DIV 0x04 | |
2520 | #define RECIP_MASK_VEC_SQRT 0x08 | |
2521 | #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ | |
2522 | | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) | |
bbe996ec | 2523 | #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) |
b86b9f44 MM |
2524 | |
2525 | #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) | |
2526 | #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) | |
2527 | #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) | |
2528 | #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) | |
2529 | ||
5dcfdccd KY |
2530 | #define IX86_HLE_ACQUIRE (1 << 16) |
2531 | #define IX86_HLE_RELEASE (1 << 17) | |
2532 | ||
e83b8e2e JJ |
2533 | /* For switching between functions with different target attributes. */ |
2534 | #define SWITCHABLE_TARGET 1 | |
2535 | ||
c98f8742 JVA |
2536 | /* |
2537 | Local variables: | |
2538 | version-control: t | |
2539 | End: | |
2540 | */ |