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6ac49599 RS |
1 | ; Options for the IA-32 and AMD64 ports of the compiler. |
2 | ||
5624e564 | 3 | ; Copyright (C) 2005-2015 Free Software Foundation, Inc. |
6ac49599 RS |
4 | ; |
5 | ; This file is part of GCC. | |
6 | ; | |
7 | ; GCC is free software; you can redistribute it and/or modify it under | |
8 | ; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 9 | ; Software Foundation; either version 3, or (at your option) any later |
6ac49599 RS |
10 | ; version. |
11 | ; | |
12 | ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | ; for more details. | |
16 | ; | |
17 | ; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | ; along with GCC; see the file COPYING3. If not see |
19 | ; <http://www.gnu.org/licenses/>. | |
6ac49599 | 20 | |
7eb68c06 JM |
21 | HeaderInclude |
22 | config/i386/i386-opts.h | |
23 | ||
e90afde6 JM |
24 | ; Bit flags that specify the ISA we are compiling for. |
25 | Variable | |
df385b9c | 26 | HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT |
e90afde6 | 27 | |
1333f97f JM |
28 | ; A mask of ix86_isa_flags that includes bit X if X was set or cleared |
29 | ; on the command line. | |
30 | Variable | |
df385b9c | 31 | HOST_WIDE_INT ix86_isa_flags_explicit |
1333f97f | 32 | |
b86b9f44 | 33 | TargetVariable |
bbe996ec | 34 | int recip_mask = RECIP_MASK_DEFAULT |
b86b9f44 MM |
35 | |
36 | Variable | |
37 | int recip_mask_explicit | |
38 | ||
39 | TargetSave | |
40 | int x_recip_mask_explicit | |
41 | ||
ab442df7 MM |
42 | ;; Definitions to add to the cl_target_option structure |
43 | ;; -march= processor | |
44 | TargetSave | |
45 | unsigned char arch | |
46 | ||
47 | ;; -mtune= processor | |
48 | TargetSave | |
49 | unsigned char tune | |
50 | ||
80f1fd0d ST |
51 | ;; -march= processor-string |
52 | TargetSave | |
53 | const char *x_ix86_arch_string | |
54 | ||
55 | ;; -mtune= processor-string | |
56 | TargetSave | |
57 | const char *x_ix86_tune_string | |
58 | ||
7ab91c5f L |
59 | ;; CPU schedule model |
60 | TargetSave | |
61 | unsigned char schedule | |
62 | ||
d0d7b0b3 JH |
63 | ;; True if processor has SSE prefetch instruction. |
64 | TargetSave | |
65 | unsigned char prefetch_sse | |
66 | ||
ab442df7 MM |
67 | ;; branch cost |
68 | TargetSave | |
69 | unsigned char branch_cost | |
70 | ||
71 | ;; which flags were passed by the user | |
72 | TargetSave | |
df385b9c | 73 | HOST_WIDE_INT x_ix86_isa_flags_explicit |
ab442df7 MM |
74 | |
75 | ;; which flags were passed by the user | |
bf7b5747 | 76 | Variable |
d4d24ba4 | 77 | int ix86_target_flags_explicit |
ab442df7 | 78 | |
bf7b5747 ST |
79 | ;; which flags were passed by the user |
80 | TargetSave | |
81 | HOST_WIDE_INT x_ix86_target_flags_explicit | |
82 | ||
ab442df7 MM |
83 | ;; whether -mtune was not specified |
84 | TargetSave | |
85 | unsigned char tune_defaulted | |
86 | ||
87 | ;; whether -march was specified | |
88 | TargetSave | |
89 | unsigned char arch_specified | |
90 | ||
80f1fd0d ST |
91 | ;; -mcmodel= model |
92 | TargetSave | |
93 | enum cmodel x_ix86_cmodel | |
94 | ||
95 | ;; -mabi= | |
96 | TargetSave | |
97 | enum calling_abi x_ix86_abi | |
98 | ||
99 | ;; -masm= | |
100 | TargetSave | |
101 | enum asm_dialect x_ix86_asm_dialect | |
102 | ||
103 | ;; -mbranch-cost= | |
104 | TargetSave | |
105 | int x_ix86_branch_cost | |
106 | ||
107 | ;; -mdump-tune-features= | |
108 | TargetSave | |
109 | int x_ix86_dump_tunes | |
110 | ||
111 | ;; -mstackrealign= | |
112 | TargetSave | |
113 | int x_ix86_force_align_arg_pointer | |
114 | ||
115 | ;; -mforce-drap= | |
116 | TargetSave | |
117 | int x_ix86_force_drap | |
118 | ||
119 | ;; -mincoming-stack-boundary= | |
120 | TargetSave | |
121 | int x_ix86_incoming_stack_boundary_arg | |
122 | ||
123 | ;; -maddress-mode= | |
124 | TargetSave | |
125 | enum pmode x_ix86_pmode | |
126 | ||
127 | ;; -mpreferred-stack-boundary= | |
128 | TargetSave | |
129 | int x_ix86_preferred_stack_boundary_arg | |
130 | ||
131 | ;; -mrecip= | |
132 | TargetSave | |
133 | const char *x_ix86_recip_name | |
134 | ||
135 | ;; -mregparm= | |
136 | TargetSave | |
137 | int x_ix86_regparm | |
138 | ||
139 | ;; -mlarge-data-threshold= | |
140 | TargetSave | |
141 | int x_ix86_section_threshold | |
142 | ||
143 | ;; -msse2avx= | |
144 | TargetSave | |
145 | int x_ix86_sse2avx | |
146 | ||
147 | ;; -mstack-protector-guard= | |
148 | TargetSave | |
149 | enum stack_protector_guard x_ix86_stack_protector_guard | |
150 | ||
151 | ;; -mstringop-strategy= | |
152 | TargetSave | |
153 | enum stringop_alg x_ix86_stringop_alg | |
154 | ||
155 | ;; -mtls-dialect= | |
156 | TargetSave | |
157 | enum tls_dialect x_ix86_tls_dialect | |
158 | ||
159 | ;; -mtune-ctrl= | |
160 | TargetSave | |
161 | const char *x_ix86_tune_ctrl_string | |
162 | ||
163 | ;; -mmemcpy-strategy= | |
164 | TargetSave | |
165 | const char *x_ix86_tune_memcpy_strategy | |
166 | ||
167 | ;; -mmemset-strategy= | |
168 | TargetSave | |
169 | const char *x_ix86_tune_memset_strategy | |
170 | ||
171 | ;; -mno-default= | |
172 | TargetSave | |
173 | int x_ix86_tune_no_default | |
174 | ||
175 | ;; -mveclibabi= | |
176 | TargetSave | |
177 | enum ix86_veclibabi x_ix86_veclibabi_type | |
178 | ||
ab442df7 | 179 | ;; x86 options |
6ac49599 | 180 | m128bit-long-double |
ab442df7 | 181 | Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save |
6ac49599 RS |
182 | sizeof(long double) is 16 |
183 | ||
6ac49599 | 184 | m80387 |
ab442df7 | 185 | Target Report Mask(80387) Save |
6ac49599 RS |
186 | Use hardware fp |
187 | ||
188 | m96bit-long-double | |
ab442df7 | 189 | Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save |
6ac49599 RS |
190 | sizeof(long double) is 12 |
191 | ||
c637141a | 192 | mlong-double-80 |
a2a1ddb5 | 193 | Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save |
c637141a L |
194 | Use 80-bit long double |
195 | ||
196 | mlong-double-64 | |
a2a1ddb5 | 197 | Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save |
c637141a L |
198 | Use 64-bit long double |
199 | ||
a2a1ddb5 L |
200 | mlong-double-128 |
201 | Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save | |
202 | Use 128-bit long double | |
203 | ||
6ac49599 | 204 | maccumulate-outgoing-args |
ab442df7 | 205 | Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save |
6ac49599 RS |
206 | Reserve space for outgoing arguments in the function prologue |
207 | ||
208 | malign-double | |
ab442df7 | 209 | Target Report Mask(ALIGN_DOUBLE) Save |
6ac49599 RS |
210 | Align some doubles on dword boundary |
211 | ||
212 | malign-functions= | |
7eb68c06 | 213 | Target RejectNegative Joined UInteger |
6ac49599 RS |
214 | Function starts are aligned to this power of 2 |
215 | ||
216 | malign-jumps= | |
7eb68c06 | 217 | Target RejectNegative Joined UInteger |
6ac49599 RS |
218 | Jump targets are aligned to this power of 2 |
219 | ||
220 | malign-loops= | |
7eb68c06 | 221 | Target RejectNegative Joined UInteger |
6ac49599 RS |
222 | Loop code aligned to this power of 2 |
223 | ||
224 | malign-stringops | |
ab442df7 | 225 | Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save |
6ac49599 RS |
226 | Align destination of the string operations |
227 | ||
239711f6 L |
228 | malign-data= |
229 | Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) | |
230 | Use the given data alignment | |
231 | ||
232 | Enum | |
233 | Name(ix86_align_data) Type(enum ix86_align_data) | |
234 | Known data alignment choices (for use with the -malign-data= option): | |
235 | ||
236 | EnumValue | |
237 | Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) | |
238 | ||
239 | EnumValue | |
240 | Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) | |
241 | ||
242 | EnumValue | |
243 | Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) | |
244 | ||
6ac49599 | 245 | march= |
55bea00a | 246 | Target RejectNegative Joined Var(ix86_arch_string) |
6ac49599 RS |
247 | Generate code for given CPU |
248 | ||
249 | masm= | |
7eb68c06 | 250 | Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) |
6ac49599 RS |
251 | Use given assembler dialect |
252 | ||
7eb68c06 JM |
253 | Enum |
254 | Name(asm_dialect) Type(enum asm_dialect) | |
255 | Known assembler dialects (for use with the -masm-dialect= option): | |
256 | ||
257 | EnumValue | |
258 | Enum(asm_dialect) String(intel) Value(ASM_INTEL) | |
259 | ||
260 | EnumValue | |
261 | Enum(asm_dialect) String(att) Value(ASM_ATT) | |
262 | ||
6ac49599 | 263 | mbranch-cost= |
7eb68c06 | 264 | Target RejectNegative Joined UInteger Var(ix86_branch_cost) |
6ac49599 RS |
265 | Branches are this expensive (1-5, arbitrary units) |
266 | ||
7dcbf659 | 267 | mlarge-data-threshold= |
5a579c3b | 268 | Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) |
7dcbf659 JH |
269 | Data greater than given threshold will go into .ldata section in x86-64 medium model |
270 | ||
6ac49599 | 271 | mcmodel= |
7eb68c06 | 272 | Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) |
6ac49599 RS |
273 | Use given x86-64 code model |
274 | ||
7eb68c06 JM |
275 | Enum |
276 | Name(cmodel) Type(enum cmodel) | |
277 | Known code models (for use with the -mcmodel= option): | |
278 | ||
279 | EnumValue | |
280 | Enum(cmodel) String(small) Value(CM_SMALL) | |
281 | ||
282 | EnumValue | |
283 | Enum(cmodel) String(medium) Value(CM_MEDIUM) | |
284 | ||
285 | EnumValue | |
286 | Enum(cmodel) String(large) Value(CM_LARGE) | |
287 | ||
288 | EnumValue | |
289 | Enum(cmodel) String(32) Value(CM_32) | |
290 | ||
291 | EnumValue | |
292 | Enum(cmodel) String(kernel) Value(CM_KERNEL) | |
293 | ||
28968d91 L |
294 | maddress-mode= |
295 | Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) | |
296 | Use given address mode | |
297 | ||
298 | Enum | |
299 | Name(pmode) Type(enum pmode) | |
300 | Known address mode (for use with the -maddress-mode= option): | |
301 | ||
302 | EnumValue | |
303 | Enum(pmode) String(short) Value(PMODE_SI) | |
304 | ||
305 | EnumValue | |
306 | Enum(pmode) String(long) Value(PMODE_DI) | |
307 | ||
2d2bd949 JM |
308 | mcpu= |
309 | Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) | |
310 | ||
6ac49599 | 311 | mfancy-math-387 |
ab442df7 | 312 | Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save |
6ac49599 RS |
313 | Generate sin, cos, sqrt for FPU |
314 | ||
2e3f842f L |
315 | mforce-drap |
316 | Target Report Var(ix86_force_drap) | |
317 | Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack | |
318 | ||
6ac49599 | 319 | mfp-ret-in-387 |
ab442df7 | 320 | Target Report Mask(FLOAT_RETURNS) Save |
6ac49599 RS |
321 | Return values of functions in FPU registers |
322 | ||
323 | mfpmath= | |
8023568e | 324 | Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save |
6ac49599 RS |
325 | Generate floating point mathematics using given instruction set |
326 | ||
8023568e JM |
327 | Enum |
328 | Name(fpmath_unit) Type(enum fpmath_unit) | |
329 | Valid arguments to -mfpmath=: | |
330 | ||
331 | EnumValue | |
332 | Enum(fpmath_unit) String(387) Value(FPMATH_387) | |
333 | ||
334 | EnumValue | |
335 | Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) | |
336 | ||
337 | EnumValue | |
338 | Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) | |
339 | ||
340 | EnumValue | |
341 | Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) | |
342 | ||
343 | EnumValue | |
344 | Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) | |
345 | ||
346 | EnumValue | |
347 | Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) | |
348 | ||
349 | EnumValue | |
350 | Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) | |
351 | ||
6ac49599 | 352 | mhard-float |
719e1e80 | 353 | Target RejectNegative Mask(80387) Save |
6ac49599 RS |
354 | Use hardware fp |
355 | ||
356 | mieee-fp | |
ab442df7 | 357 | Target Report Mask(IEEE_FP) Save |
6ac49599 RS |
358 | Use IEEE math for fp comparisons |
359 | ||
360 | minline-all-stringops | |
ab442df7 | 361 | Target Report Mask(INLINE_ALL_STRINGOPS) Save |
6ac49599 RS |
362 | Inline all known string operations |
363 | ||
8c996513 | 364 | minline-stringops-dynamically |
ab442df7 | 365 | Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save |
8c996513 JH |
366 | Inline memset/memcpy string operations, but perform inline version only for small blocks |
367 | ||
6ac49599 | 368 | mintel-syntax |
2d2bd949 | 369 | Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) |
6ac49599 RS |
370 | ;; Deprecated |
371 | ||
6ac49599 | 372 | mms-bitfields |
ab442df7 | 373 | Target Report Mask(MS_BITFIELD_LAYOUT) Save |
6ac49599 RS |
374 | Use native (MS) bitfield layout |
375 | ||
376 | mno-align-stringops | |
ab442df7 | 377 | Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save |
6ac49599 RS |
378 | |
379 | mno-fancy-math-387 | |
ab442df7 | 380 | Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save |
6ac49599 RS |
381 | |
382 | mno-push-args | |
ab442df7 | 383 | Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save |
6ac49599 RS |
384 | |
385 | mno-red-zone | |
ab442df7 | 386 | Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save |
6ac49599 RS |
387 | |
388 | momit-leaf-frame-pointer | |
ab442df7 | 389 | Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save |
6ac49599 RS |
390 | Omit the frame pointer in leaf functions |
391 | ||
7eb68c06 JM |
392 | mpc32 |
393 | Target RejectNegative Report | |
394 | Set 80387 floating-point precision to 32-bit | |
395 | ||
396 | mpc64 | |
397 | Target RejectNegative Report | |
398 | Set 80387 floating-point precision to 64-bit | |
399 | ||
400 | mpc80 | |
401 | Target RejectNegative Report | |
402 | Set 80387 floating-point precision to 80-bit | |
577565f9 | 403 | |
6ac49599 | 404 | mpreferred-stack-boundary= |
7eb68c06 | 405 | Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) |
6ac49599 RS |
406 | Attempt to keep stack aligned to this power of 2 |
407 | ||
2e3f842f | 408 | mincoming-stack-boundary= |
7eb68c06 | 409 | Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) |
2e3f842f L |
410 | Assume incoming stack aligned to this power of 2 |
411 | ||
6ac49599 | 412 | mpush-args |
ab442df7 | 413 | Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save |
6ac49599 RS |
414 | Use push instructions to save outgoing arguments |
415 | ||
416 | mred-zone | |
ab442df7 | 417 | Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save |
6ac49599 RS |
418 | Use red-zone in the x86-64 code |
419 | ||
420 | mregparm= | |
7eb68c06 | 421 | Target RejectNegative Joined UInteger Var(ix86_regparm) |
6ac49599 RS |
422 | Number of registers used to pass integer arguments |
423 | ||
424 | mrtd | |
ab442df7 | 425 | Target Report Mask(RTD) Save |
6ac49599 RS |
426 | Alternate calling convention |
427 | ||
428 | msoft-float | |
ab442df7 | 429 | Target InverseMask(80387) Save |
6ac49599 RS |
430 | Do not use hardware fp |
431 | ||
1f97667f | 432 | msseregparm |
ab442df7 | 433 | Target RejectNegative Mask(SSEREGPARM) Save |
1f97667f RG |
434 | Use SSE register passing conventions for SF and DF mode |
435 | ||
33932946 | 436 | mstackrealign |
2e3f842f | 437 | Target Report Var(ix86_force_align_arg_pointer) Init(-1) |
33932946 SH |
438 | Realign stack in prologue |
439 | ||
6ac49599 | 440 | mstack-arg-probe |
ab442df7 | 441 | Target Report Mask(STACK_PROBE) Save |
6ac49599 RS |
442 | Enable stack probing |
443 | ||
ad83025e XDL |
444 | mmemcpy-strategy= |
445 | Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) | |
446 | Specify memcpy expansion strategy when expected size is known | |
447 | ||
448 | mmemset-strategy= | |
449 | Target RejectNegative Joined Var(ix86_tune_memset_strategy) | |
450 | Specify memset expansion strategy when expected size is known | |
451 | ||
8c996513 | 452 | mstringop-strategy= |
7eb68c06 | 453 | Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) |
8c996513 JH |
454 | Chose strategy to generate stringop using |
455 | ||
7eb68c06 JM |
456 | Enum |
457 | Name(stringop_alg) Type(enum stringop_alg) | |
458 | Valid arguments to -mstringop-strategy=: | |
459 | ||
460 | EnumValue | |
461 | Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) | |
462 | ||
463 | EnumValue | |
464 | Enum(stringop_alg) String(libcall) Value(libcall) | |
465 | ||
466 | EnumValue | |
467 | Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) | |
468 | ||
469 | EnumValue | |
470 | Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) | |
471 | ||
472 | EnumValue | |
473 | Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) | |
474 | ||
475 | EnumValue | |
476 | Enum(stringop_alg) String(loop) Value(loop) | |
477 | ||
478 | EnumValue | |
479 | Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) | |
480 | ||
930b700b MZ |
481 | EnumValue |
482 | Enum(stringop_alg) String(vector_loop) Value(vector_loop) | |
483 | ||
6ac49599 | 484 | mtls-dialect= |
7eb68c06 | 485 | Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) |
6ac49599 RS |
486 | Use given thread-local storage dialect |
487 | ||
7eb68c06 JM |
488 | Enum |
489 | Name(tls_dialect) Type(enum tls_dialect) | |
490 | Known TLS dialects (for use with the -mtls-dialect= option): | |
491 | ||
492 | EnumValue | |
493 | Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) | |
494 | ||
495 | EnumValue | |
496 | Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) | |
497 | ||
6ac49599 RS |
498 | mtls-direct-seg-refs |
499 | Target Report Mask(TLS_DIRECT_SEG_REFS) | |
500 | Use direct references against %gs when accessing tls data | |
501 | ||
502 | mtune= | |
55bea00a | 503 | Target RejectNegative Joined Var(ix86_tune_string) |
6ac49599 RS |
504 | Schedule code for given CPU |
505 | ||
4b8bc035 XDL |
506 | mtune-ctrl= |
507 | Target RejectNegative Joined Var(ix86_tune_ctrl_string) | |
508 | Fine grain control of tune features | |
509 | ||
3ad20bd4 XDL |
510 | mno-default |
511 | Target RejectNegative Var(ix86_tune_no_default) Init(0) | |
512 | Clear all tune features | |
513 | ||
514 | mdump-tune-features | |
515 | Target RejectNegative Var(ix86_dump_tunes) Init(0) | |
516 | ||
51212b32 | 517 | mabi= |
7eb68c06 | 518 | Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) |
51212b32 L |
519 | Generate code that conforms to the given ABI |
520 | ||
7eb68c06 JM |
521 | Enum |
522 | Name(calling_abi) Type(enum calling_abi) | |
523 | Known ABIs (for use with the -mabi= option): | |
524 | ||
525 | EnumValue | |
526 | Enum(calling_abi) String(sysv) Value(SYSV_ABI) | |
527 | ||
528 | EnumValue | |
529 | Enum(calling_abi) String(ms) Value(MS_ABI) | |
530 | ||
a5ea943c | 531 | mveclibabi= |
7eb68c06 | 532 | Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) |
a5ea943c RG |
533 | Vector library ABI to use |
534 | ||
7eb68c06 JM |
535 | Enum |
536 | Name(ix86_veclibabi) Type(enum ix86_veclibabi) | |
537 | Known vectorization library ABIs (for use with the -mveclibabi= option): | |
538 | ||
539 | EnumValue | |
540 | Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) | |
541 | ||
542 | EnumValue | |
543 | Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) | |
544 | ||
2770264a RO |
545 | mvect8-ret-in-mem |
546 | Target Report Mask(VECT8_RETURNS) Save | |
547 | Return 8-byte vectors in memory | |
548 | ||
ab442df7 MM |
549 | mrecip |
550 | Target Report Mask(RECIP) Save | |
551 | Generate reciprocals instead of divss and sqrtss. | |
552 | ||
b86b9f44 MM |
553 | mrecip= |
554 | Target Report RejectNegative Joined Var(ix86_recip_name) | |
555 | Control generation of reciprocal estimates. | |
556 | ||
ab442df7 MM |
557 | mcld |
558 | Target Report Mask(CLD) Save | |
559 | Generate cld instruction in the function prologue. | |
560 | ||
2767a7f2 L |
561 | mvzeroupper |
562 | Target Report Mask(VZEROUPPER) Save | |
563 | Generate vzeroupper instruction before a transfer of control flow out of | |
564 | the function. | |
565 | ||
7942e47e RY |
566 | mdispatch-scheduler |
567 | Target RejectNegative Var(flag_dispatch_scheduler) | |
ed97ad47 | 568 | Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 or bdver4 and Haifa scheduling |
7942e47e RY |
569 | is selected. |
570 | ||
d9c64246 | 571 | mprefer-avx128 |
5c0d88e6 | 572 | Target Report Mask(PREFER_AVX128) SAVE |
d9c64246 CF |
573 | Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. |
574 | ||
0a1c5e55 UB |
575 | ;; ISA support |
576 | ||
577 | m32 | |
f0036cca | 578 | Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
579 | Generate 32bit i386 code |
580 | ||
581 | m64 | |
1ab8b791 | 582 | Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
583 | Generate 64bit x86-64 code |
584 | ||
f0ea7581 | 585 | mx32 |
d5d618b5 | 586 | Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save |
f0ea7581 L |
587 | Generate 32bit x86-64 code |
588 | ||
d5d618b5 L |
589 | m16 |
590 | Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save | |
591 | Generate 16bit i386 code | |
592 | ||
0a1c5e55 | 593 | mmmx |
f0036cca | 594 | Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
595 | Support MMX built-in functions |
596 | ||
597 | m3dnow | |
f0036cca | 598 | Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
599 | Support 3DNow! built-in functions |
600 | ||
601 | m3dnowa | |
f0036cca | 602 | Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
603 | Support Athlon 3Dnow! built-in functions |
604 | ||
605 | msse | |
f0036cca | 606 | Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
607 | Support MMX and SSE built-in functions and code generation |
608 | ||
609 | msse2 | |
f0036cca | 610 | Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
611 | Support MMX, SSE and SSE2 built-in functions and code generation |
612 | ||
613 | msse3 | |
f0036cca | 614 | Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
615 | Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation |
616 | ||
617 | mssse3 | |
f0036cca | 618 | Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
619 | Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation |
620 | ||
621 | msse4.1 | |
f0036cca | 622 | Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
623 | Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation |
624 | ||
3b8dd071 | 625 | msse4.2 |
f0036cca | 626 | Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save |
3b8dd071 L |
627 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation |
628 | ||
629 | msse4 | |
719e1e80 | 630 | Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save |
3b8dd071 L |
631 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation |
632 | ||
633 | mno-sse4 | |
719e1e80 | 634 | Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save |
3b8dd071 L |
635 | Do not support SSE4.1 and SSE4.2 built-in functions and code generation |
636 | ||
eb5bb0fd JM |
637 | msse5 |
638 | Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) | |
639 | ;; Deprecated | |
640 | ||
95879c72 | 641 | mavx |
6fc4dbc7 | 642 | Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save |
95879c72 L |
643 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation |
644 | ||
7afac110 KY |
645 | mavx2 |
646 | Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save | |
647 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation | |
648 | ||
3f97cb0b AI |
649 | mavx512f |
650 | Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save | |
651 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation | |
652 | ||
653 | mavx512pf | |
654 | Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save | |
655 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation | |
656 | ||
657 | mavx512er | |
658 | Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save | |
659 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation | |
660 | ||
661 | mavx512cd | |
662 | Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save | |
663 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation | |
664 | ||
07165dd7 AI |
665 | mavx512dq |
666 | Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save | |
667 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation | |
668 | ||
b525d943 AI |
669 | mavx512bw |
670 | Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save | |
671 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation | |
672 | ||
f4af595f AI |
673 | mavx512vl |
674 | Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save | |
675 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation | |
4190ea38 IT |
676 | |
677 | mavx512ifma | |
678 | Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save | |
679 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation | |
3dcc8af5 IT |
680 | |
681 | mavx512vbmi | |
682 | Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save | |
683 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation | |
f4af595f | 684 | |
95879c72 | 685 | mfma |
6fc4dbc7 | 686 | Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save |
95879c72 L |
687 | Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation |
688 | ||
0a1c5e55 | 689 | msse4a |
f0036cca | 690 | Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
691 | Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation |
692 | ||
cbf2e4d4 | 693 | mfma4 |
f0036cca | 694 | Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save |
cbf2e4d4 HJ |
695 | Support FMA4 built-in functions and code generation |
696 | ||
43a8b705 | 697 | mxop |
f0036cca | 698 | Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save |
43a8b705 HJ |
699 | Support XOP built-in functions and code generation |
700 | ||
3e901069 | 701 | mlwp |
f0036cca | 702 | Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save |
3e901069 HJ |
703 | Support LWP built-in functions and code generation |
704 | ||
0a1c5e55 | 705 | mabm |
f0036cca | 706 | Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
707 | Support code generation of Advanced Bit Manipulation (ABM) instructions. |
708 | ||
0a1c5e55 | 709 | mpopcnt |
f0036cca | 710 | Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save |
0a1c5e55 UB |
711 | Support code generation of popcnt instruction. |
712 | ||
91afcfa3 QN |
713 | mbmi |
714 | Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save | |
715 | Support BMI built-in functions and code generation | |
716 | ||
82feeb8d L |
717 | mbmi2 |
718 | Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save | |
719 | Support BMI2 built-in functions and code generation | |
720 | ||
5fcafa60 KY |
721 | mlzcnt |
722 | Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save | |
723 | Support LZCNT built-in function and code generation | |
724 | ||
5dcfdccd KY |
725 | mhle |
726 | Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save | |
727 | Support Hardware Lock Elision prefixes | |
728 | ||
4c340b5d KY |
729 | mrdseed |
730 | Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save | |
731 | Support RDSEED instruction | |
732 | ||
e61c94dd KY |
733 | mprfchw |
734 | Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save | |
735 | Support PREFETCHW instruction | |
736 | ||
d05e383b MZ |
737 | madx |
738 | Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save | |
739 | Support flag-preserving add-carry instructions | |
740 | ||
9cdea277 IT |
741 | mclflushopt |
742 | Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save | |
743 | Support CLFLUSHOPT instructions | |
744 | ||
9c3bca11 IT |
745 | mclwb |
746 | Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save | |
747 | Support CLWB instruction | |
748 | ||
36e9b73e IT |
749 | mpcommit |
750 | Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save | |
751 | Support PCOMMIT instruction | |
752 | ||
3a0d99bb AI |
753 | mfxsr |
754 | Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save | |
755 | Support FXSAVE and FXRSTOR instructions | |
756 | ||
757 | mxsave | |
758 | Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save | |
759 | Support XSAVE and XRSTOR instructions | |
760 | ||
761 | mxsaveopt | |
762 | Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save | |
763 | Support XSAVEOPT instruction | |
764 | ||
9cdea277 IT |
765 | mxsavec |
766 | Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save | |
767 | Support XSAVEC instructions | |
768 | ||
769 | mxsaves | |
770 | Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save | |
771 | Support XSAVES and XRSTORS instructions | |
772 | ||
94d13ad1 QN |
773 | mtbm |
774 | Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save | |
775 | Support TBM built-in functions and code generation | |
776 | ||
ab442df7 | 777 | mcx16 |
f0036cca | 778 | Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save |
ab442df7 MM |
779 | Support code generation of cmpxchg16b instruction. |
780 | ||
0a1c5e55 | 781 | msahf |
f0036cca | 782 | Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save |
0a1c5e55 | 783 | Support code generation of sahf instruction in 64bit x86-64 code. |
6b889d89 | 784 | |
cabf85c3 | 785 | mmovbe |
f0036cca | 786 | Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save |
cabf85c3 L |
787 | Support code generation of movbe instruction. |
788 | ||
8ed0ce99 | 789 | mcrc32 |
f0036cca | 790 | Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save |
8ed0ce99 L |
791 | Support code generation of crc32 instruction. |
792 | ||
8b96a312 | 793 | maes |
f0036cca | 794 | Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save |
8b96a312 L |
795 | Support AES built-in functions and code generation |
796 | ||
c1618f82 AI |
797 | msha |
798 | Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save | |
799 | Support SHA1 and SHA256 built-in functions and code generation | |
800 | ||
8b96a312 | 801 | mpclmul |
f0036cca | 802 | Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save |
8b96a312 | 803 | Support PCLMUL built-in functions and code generation |
bd459cb6 L |
804 | |
805 | msse2avx | |
806 | Target Report Var(ix86_sse2avx) | |
807 | Encode SSE instructions with VEX prefix | |
4ee89d5f L |
808 | |
809 | mfsgsbase | |
f0036cca | 810 | Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save |
4ee89d5f L |
811 | Support FSGSBASE built-in functions and code generation |
812 | ||
813 | mrdrnd | |
f0036cca | 814 | Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save |
4ee89d5f L |
815 | Support RDRND built-in functions and code generation |
816 | ||
817 | mf16c | |
f0036cca | 818 | Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save |
4ee89d5f | 819 | Support F16C built-in functions and code generation |
3c5273a9 | 820 | |
43b3f52f IT |
821 | mprefetchwt1 |
822 | Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save | |
823 | Support PREFETCHWT1 built-in functions and code generation | |
824 | ||
3c5273a9 KT |
825 | mfentry |
826 | Target Report Var(flag_fentry) Init(-1) | |
827 | Emit profiling counter call at function entry before prologue. | |
26ec9308 | 828 | |
ecc81e33 AK |
829 | mrecord-mcount |
830 | Target Report Var(flag_record_mcount) Init(0) | |
831 | Generate __mcount_loc section with all mcount or __fentry__ calls. | |
832 | ||
833 | mnop-mcount | |
834 | Target Report Var(flag_nop_mcount) Init(0) | |
835 | Generate mcount/__fentry__ calls as nops. To activate they need to be | |
836 | patched in. | |
837 | ||
fbe575b6 L |
838 | mskip-rax-setup |
839 | Target Report Var(flag_skip_rax_setup) Init(0) | |
840 | Skip setting up RAX register when passing variable arguments. | |
841 | ||
26ec9308 L |
842 | m8bit-idiv |
843 | Target Report Mask(USE_8BIT_IDIV) Save | |
844 | Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check | |
d253656a L |
845 | |
846 | mavx256-split-unaligned-load | |
847 | Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save | |
848 | Split 32-byte AVX unaligned load | |
849 | ||
850 | mavx256-split-unaligned-store | |
851 | Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save | |
852 | Split 32-byte AVX unaligned store | |
bf2eaa3f KY |
853 | |
854 | mrtm | |
855 | Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save | |
856 | Support RTM built-in functions and code generation | |
e0ea8797 | 857 | |
d5e254e1 IE |
858 | mmpx |
859 | Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save | |
860 | Support MPX code generation | |
861 | ||
500a08b2 VK |
862 | mmwaitx |
863 | Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save | |
864 | Support MWAITX and MONITORX built-in functions and code generation | |
865 | ||
e0ea8797 AH |
866 | mstack-protector-guard= |
867 | Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) | |
868 | Use given stack-protector guard | |
869 | ||
870 | Enum | |
871 | Name(stack_protector_guard) Type(enum stack_protector_guard) | |
872 | Known stack protector guard (for use with the -mstack-protector-guard= option): | |
873 | ||
874 | EnumValue | |
875 | Enum(stack_protector_guard) String(tls) Value(SSP_TLS) | |
876 | ||
877 | EnumValue | |
878 | Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) |