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8fe75e43 | 1 | ;; Predicate definitions for IA-32 and x86-64. |
a945c346 | 2 | ;; Copyright (C) 2004-2024 Free Software Foundation, Inc. |
8fe75e43 RH |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
8fe75e43 RH |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
8fe75e43 | 19 | |
19ed9d7b | 20 | ;; Return true if OP is either a i387 or SSE fp register. |
8fe75e43 RH |
21 | (define_predicate "any_fp_register_operand" |
22 | (and (match_code "reg") | |
23 | (match_test "ANY_FP_REGNO_P (REGNO (op))"))) | |
24 | ||
19ed9d7b | 25 | ;; Return true if OP is an i387 fp register. |
8fe75e43 RH |
26 | (define_predicate "fp_register_operand" |
27 | (and (match_code "reg") | |
66aaf16f | 28 | (match_test "STACK_REGNO_P (REGNO (op))"))) |
8fe75e43 | 29 | |
85a77221 AI |
30 | ;; True if the operand is a GENERAL class register. |
31 | (define_predicate "general_reg_operand" | |
32 | (and (match_code "reg") | |
00cbba89 | 33 | (match_test "GENERAL_REGNO_P (REGNO (op))"))) |
85a77221 | 34 | |
8cac2378 UB |
35 | ;; True if the operand is an INDEX class register. |
36 | (define_predicate "index_reg_operand" | |
37 | (and (match_code "reg") | |
38 | (match_test "INDEX_REGNO_P (REGNO (op))"))) | |
39 | ||
cb1fd5b4 UB |
40 | ;; True if the operand is a nonimmediate operand with GENERAL class register. |
41 | (define_predicate "nonimmediate_gr_operand" | |
42 | (if_then_else (match_code "reg") | |
43 | (match_test "GENERAL_REGNO_P (REGNO (op))") | |
44 | (match_operand 0 "nonimmediate_operand"))) | |
45 | ||
cd3fe55a UB |
46 | ;; True if the operand is a general operand with GENERAL class register. |
47 | (define_predicate "general_gr_operand" | |
48 | (if_then_else (match_code "reg") | |
49 | (match_test "GENERAL_REGNO_P (REGNO (op))") | |
50 | (match_operand 0 "general_operand"))) | |
51 | ||
8fe75e43 RH |
52 | ;; True if the operand is an MMX register. |
53 | (define_predicate "mmx_reg_operand" | |
54 | (and (match_code "reg") | |
55 | (match_test "MMX_REGNO_P (REGNO (op))"))) | |
770b37b9 | 56 | |
b74ebb2a L |
57 | ;; Match register operands, but include memory operands for |
58 | ;; !TARGET_MMX_WITH_SSE. | |
59 | (define_predicate "register_mmxmem_operand" | |
60 | (ior (match_operand 0 "register_operand") | |
61 | (and (not (match_test "TARGET_MMX_WITH_SSE")) | |
62 | (match_operand 0 "memory_operand")))) | |
63 | ||
770b37b9 UB |
64 | ;; True if the operand is an SSE register. |
65 | (define_predicate "sse_reg_operand" | |
66 | (and (match_code "reg") | |
67 | (match_test "SSE_REGNO_P (REGNO (op))"))) | |
8fe75e43 | 68 | |
55d2ee57 UB |
69 | ;; Return true if op is a QImode register. |
70 | (define_predicate "any_QIreg_operand" | |
71 | (and (match_code "reg") | |
72 | (match_test "ANY_QI_REGNO_P (REGNO (op))"))) | |
8fe75e43 | 73 | |
55d2ee57 UB |
74 | ;; Return true if op is one of QImode registers: %[abcd][hl]. |
75 | (define_predicate "QIreg_operand" | |
76 | (and (match_code "reg") | |
77 | (match_test "QI_REGNO_P (REGNO (op))"))) | |
78 | ||
79 | ;; Return true if op is a QImode register operand other than %[abcd][hl]. | |
80 | (define_predicate "ext_QIreg_operand" | |
81 | (and (match_test "TARGET_64BIT") | |
82 | (match_code "reg") | |
83 | (not (match_test "QI_REGNO_P (REGNO (op))")))) | |
84 | ||
85 | ;; Return true if op is the AX register. | |
86 | (define_predicate "ax_reg_operand" | |
87 | (and (match_code "reg") | |
88 | (match_test "REGNO (op) == AX_REG"))) | |
89 | ||
90 | ;; Return true if op is the flags register. | |
fadf10e9 | 91 | (define_special_predicate "flags_reg_operand" |
55d2ee57 UB |
92 | (and (match_code "reg") |
93 | (match_test "REGNO (op) == FLAGS_REG"))) | |
cb105922 | 94 | |
388cb292 | 95 | ;; True if the operand is a MASK register. |
96 | (define_predicate "mask_reg_operand" | |
97 | (and (match_code "reg") | |
98 | (match_test "MASK_REGNO_P (REGNO (op))"))) | |
99 | ||
1f34cf9b UB |
100 | ;; Match a DI, SI or HImode register operand. |
101 | (define_special_predicate "int248_register_operand" | |
00b8a212 UB |
102 | (and (match_operand 0 "register_operand") |
103 | (ior (and (match_test "TARGET_64BIT") | |
104 | (match_test "GET_MODE (op) == DImode")) | |
105 | (match_test "GET_MODE (op) == SImode") | |
106 | (match_test "GET_MODE (op) == HImode")))) | |
107 | ||
15643a0d JJ |
108 | ;; Match a DI, SI, HI or QImode nonimmediate_operand. |
109 | (define_special_predicate "int_nonimmediate_operand" | |
110 | (and (match_operand 0 "nonimmediate_operand") | |
111 | (ior (and (match_test "TARGET_64BIT") | |
112 | (match_test "GET_MODE (op) == DImode")) | |
113 | (match_test "GET_MODE (op) == SImode") | |
114 | (match_test "GET_MODE (op) == HImode") | |
115 | (match_test "GET_MODE (op) == QImode")))) | |
116 | ||
c8802daf UB |
117 | ;; Match register operands, but include memory operands for TARGET_SSE_MATH. |
118 | (define_predicate "register_ssemem_operand" | |
119 | (if_then_else | |
120 | (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH") | |
121 | (match_operand 0 "nonimmediate_operand") | |
122 | (match_operand 0 "register_operand"))) | |
123 | ||
ebae28e9 UB |
124 | ;; Match nonimmediate operands, but exclude memory operands |
125 | ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled. | |
126 | (define_predicate "nonimm_ssenomem_operand" | |
8b38916a UB |
127 | (if_then_else |
128 | (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH") | |
129 | (not (match_test "TARGET_MIX_SSE_I387"))) | |
130 | (match_operand 0 "register_operand") | |
131 | (match_operand 0 "nonimmediate_operand"))) | |
132 | ||
133 | ;; The above predicate, suitable for x87 arithmetic operators. | |
134 | (define_predicate "x87nonimm_ssenomem_operand" | |
ebae28e9 UB |
135 | (if_then_else |
136 | (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH") | |
137 | (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)"))) | |
138 | (match_operand 0 "register_operand") | |
139 | (match_operand 0 "nonimmediate_operand"))) | |
8c292b10 | 140 | |
846e2ad8 UB |
141 | ;; Match register operands, include memory operand for TARGET_SSE4_1. |
142 | (define_predicate "register_sse4nonimm_operand" | |
143 | (if_then_else (match_test "TARGET_SSE4_1") | |
144 | (match_operand 0 "nonimmediate_operand") | |
145 | (match_operand 0 "register_operand"))) | |
146 | ||
d5e254e1 IE |
147 | ;; Return true if VALUE is symbol reference |
148 | (define_predicate "symbol_operand" | |
149 | (match_code "symbol_ref")) | |
150 | ||
9a5381f7 | 151 | ;; Return true if VALUE is an ENDBR opcode in immediate field. |
152 | (define_predicate "ix86_endbr_immediate_operand" | |
153 | (match_code "const_int") | |
154 | { | |
155 | if (flag_cf_protection & CF_BRANCH) | |
156 | { | |
157 | unsigned HOST_WIDE_INT imm = UINTVAL (op); | |
158 | unsigned HOST_WIDE_INT val = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3; | |
159 | ||
160 | if (imm == val) | |
d6345481 | 161 | return true; |
9a5381f7 | 162 | |
163 | /* NB: Encoding is byte based. */ | |
164 | if (TARGET_64BIT) | |
165 | for (; imm >= val; imm >>= 8) | |
166 | if (imm == val) | |
d6345481 | 167 | return true; |
9a5381f7 | 168 | } |
169 | ||
d6345481 | 170 | return false; |
9a5381f7 | 171 | }) |
172 | ||
19ed9d7b | 173 | ;; Return true if VALUE can be stored in a sign extended immediate field. |
8fe75e43 RH |
174 | (define_predicate "x86_64_immediate_operand" |
175 | (match_code "const_int,symbol_ref,label_ref,const") | |
176 | { | |
9a5381f7 | 177 | if (ix86_endbr_immediate_operand (op, VOIDmode)) |
178 | return false; | |
179 | ||
8fe75e43 RH |
180 | if (!TARGET_64BIT) |
181 | return immediate_operand (op, mode); | |
182 | ||
183 | switch (GET_CODE (op)) | |
184 | { | |
185 | case CONST_INT: | |
44d0de8d | 186 | { |
1a58b548 | 187 | HOST_WIDE_INT val = INTVAL (op); |
44d0de8d UB |
188 | return trunc_int_for_mode (val, SImode) == val; |
189 | } | |
8fe75e43 | 190 | case SYMBOL_REF: |
e3d62871 UB |
191 | /* TLS symbols are not constant. */ |
192 | if (SYMBOL_REF_TLS_MODEL (op)) | |
193 | return false; | |
194 | ||
195 | /* Load the external function address via the GOT slot. */ | |
196 | if (ix86_force_load_from_GOT_p (op)) | |
197 | return false; | |
198 | ||
8fe75e43 RH |
199 | /* For certain code models, the symbolic references are known to fit. |
200 | in CM_SMALL_PIC model we know it fits if it is local to the shared | |
201 | library. Don't count TLS SYMBOL_REFs here, since they should fit | |
202 | only if inside of UNSPEC handled below. */ | |
7dcbf659 JH |
203 | return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL |
204 | || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op))); | |
8fe75e43 RH |
205 | |
206 | case LABEL_REF: | |
207 | /* For certain code models, the code is near as well. */ | |
208 | return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM | |
209 | || ix86_cmodel == CM_KERNEL); | |
210 | ||
211 | case CONST: | |
212 | /* We also may accept the offsetted memory references in certain | |
213 | special cases. */ | |
214 | if (GET_CODE (XEXP (op, 0)) == UNSPEC) | |
215 | switch (XINT (XEXP (op, 0), 1)) | |
216 | { | |
217 | case UNSPEC_GOTPCREL: | |
218 | case UNSPEC_DTPOFF: | |
219 | case UNSPEC_GOTNTPOFF: | |
220 | case UNSPEC_NTPOFF: | |
19ed9d7b | 221 | return true; |
8fe75e43 RH |
222 | default: |
223 | break; | |
224 | } | |
225 | ||
226 | if (GET_CODE (XEXP (op, 0)) == PLUS) | |
227 | { | |
228 | rtx op1 = XEXP (XEXP (op, 0), 0); | |
229 | rtx op2 = XEXP (XEXP (op, 0), 1); | |
8fe75e43 | 230 | |
3e7f831c | 231 | if (ix86_cmodel == CM_LARGE && GET_CODE (op1) != UNSPEC) |
19ed9d7b | 232 | return false; |
7656aee4 | 233 | if (!CONST_INT_P (op2)) |
19ed9d7b | 234 | return false; |
4368a420 | 235 | |
1a58b548 | 236 | HOST_WIDE_INT offset = INTVAL (op2); |
4368a420 UB |
237 | if (trunc_int_for_mode (offset, SImode) != offset) |
238 | return false; | |
239 | ||
8fe75e43 RH |
240 | switch (GET_CODE (op1)) |
241 | { | |
242 | case SYMBOL_REF: | |
fd4aca96 RH |
243 | /* TLS symbols are not constant. */ |
244 | if (SYMBOL_REF_TLS_MODEL (op1)) | |
19ed9d7b | 245 | return false; |
e3d62871 UB |
246 | |
247 | /* Load the external function address via the GOT slot. */ | |
248 | if (ix86_force_load_from_GOT_p (op1)) | |
249 | return false; | |
250 | ||
8fe75e43 RH |
251 | /* For CM_SMALL assume that latest object is 16MB before |
252 | end of 31bits boundary. We may also accept pretty | |
253 | large negative constants knowing that all objects are | |
254 | in the positive half of address space. */ | |
7dcbf659 JH |
255 | if ((ix86_cmodel == CM_SMALL |
256 | || (ix86_cmodel == CM_MEDIUM | |
257 | && !SYMBOL_REF_FAR_ADDR_P (op1))) | |
4368a420 | 258 | && offset < 16*1024*1024) |
19ed9d7b | 259 | return true; |
8fe75e43 RH |
260 | /* For CM_KERNEL we know that all object resist in the |
261 | negative half of 32bits address space. We may not | |
262 | accept negative offsets, since they may be just off | |
263 | and we may accept pretty large positive ones. */ | |
264 | if (ix86_cmodel == CM_KERNEL | |
4368a420 | 265 | && offset > 0) |
19ed9d7b | 266 | return true; |
8fe75e43 RH |
267 | break; |
268 | ||
269 | case LABEL_REF: | |
270 | /* These conditions are similar to SYMBOL_REF ones, just the | |
271 | constraints for code models differ. */ | |
272 | if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM) | |
4368a420 | 273 | && offset < 16*1024*1024) |
19ed9d7b | 274 | return true; |
8fe75e43 | 275 | if (ix86_cmodel == CM_KERNEL |
4368a420 | 276 | && offset > 0) |
19ed9d7b | 277 | return true; |
8fe75e43 RH |
278 | break; |
279 | ||
280 | case UNSPEC: | |
281 | switch (XINT (op1, 1)) | |
282 | { | |
283 | case UNSPEC_DTPOFF: | |
284 | case UNSPEC_NTPOFF: | |
4368a420 | 285 | return true; |
8fe75e43 RH |
286 | } |
287 | break; | |
288 | ||
289 | default: | |
290 | break; | |
291 | } | |
292 | } | |
293 | break; | |
294 | ||
295 | default: | |
7637e42c | 296 | gcc_unreachable (); |
8fe75e43 RH |
297 | } |
298 | ||
19ed9d7b | 299 | return false; |
8fe75e43 RH |
300 | }) |
301 | ||
19ed9d7b | 302 | ;; Return true if VALUE can be stored in the zero extended immediate field. |
8fe75e43 | 303 | (define_predicate "x86_64_zext_immediate_operand" |
44d0de8d | 304 | (match_code "const_int,symbol_ref,label_ref,const") |
8fe75e43 | 305 | { |
9a5381f7 | 306 | if (ix86_endbr_immediate_operand (op, VOIDmode)) |
307 | return false; | |
308 | ||
8fe75e43 RH |
309 | switch (GET_CODE (op)) |
310 | { | |
8fe75e43 | 311 | case CONST_INT: |
44d0de8d | 312 | return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff); |
8fe75e43 RH |
313 | |
314 | case SYMBOL_REF: | |
8fe75e43 | 315 | /* TLS symbols are not constant. */ |
fd4aca96 | 316 | if (SYMBOL_REF_TLS_MODEL (op)) |
8fe75e43 | 317 | return false; |
e3d62871 UB |
318 | |
319 | /* Load the external function address via the GOT slot. */ | |
320 | if (ix86_force_load_from_GOT_p (op)) | |
321 | return false; | |
322 | ||
323 | /* For certain code models, the symbolic references are known to fit. */ | |
7dcbf659 JH |
324 | return (ix86_cmodel == CM_SMALL |
325 | || (ix86_cmodel == CM_MEDIUM | |
326 | && !SYMBOL_REF_FAR_ADDR_P (op))); | |
8fe75e43 RH |
327 | |
328 | case LABEL_REF: | |
329 | /* For certain code models, the code is near as well. */ | |
330 | return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM; | |
331 | ||
332 | case CONST: | |
333 | /* We also may accept the offsetted memory references in certain | |
334 | special cases. */ | |
335 | if (GET_CODE (XEXP (op, 0)) == PLUS) | |
336 | { | |
337 | rtx op1 = XEXP (XEXP (op, 0), 0); | |
338 | rtx op2 = XEXP (XEXP (op, 0), 1); | |
339 | ||
340 | if (ix86_cmodel == CM_LARGE) | |
19ed9d7b | 341 | return false; |
4368a420 UB |
342 | if (!CONST_INT_P (op2)) |
343 | return false; | |
344 | ||
1a58b548 | 345 | HOST_WIDE_INT offset = INTVAL (op2); |
4368a420 UB |
346 | if (trunc_int_for_mode (offset, SImode) != offset) |
347 | return false; | |
348 | ||
8fe75e43 RH |
349 | switch (GET_CODE (op1)) |
350 | { | |
351 | case SYMBOL_REF: | |
fd4aca96 RH |
352 | /* TLS symbols are not constant. */ |
353 | if (SYMBOL_REF_TLS_MODEL (op1)) | |
19ed9d7b | 354 | return false; |
e3d62871 UB |
355 | |
356 | /* Load the external function address via the GOT slot. */ | |
357 | if (ix86_force_load_from_GOT_p (op1)) | |
358 | return false; | |
359 | ||
8fe75e43 RH |
360 | /* For small code model we may accept pretty large positive |
361 | offsets, since one bit is available for free. Negative | |
362 | offsets are limited by the size of NULL pointer area | |
363 | specified by the ABI. */ | |
7dcbf659 JH |
364 | if ((ix86_cmodel == CM_SMALL |
365 | || (ix86_cmodel == CM_MEDIUM | |
366 | && !SYMBOL_REF_FAR_ADDR_P (op1))) | |
4368a420 | 367 | && offset > -0x10000) |
19ed9d7b | 368 | return true; |
8fe75e43 RH |
369 | /* ??? For the kernel, we may accept adjustment of |
370 | -0x10000000, since we know that it will just convert | |
371 | negative address space to positive, but perhaps this | |
372 | is not worthwhile. */ | |
373 | break; | |
374 | ||
375 | case LABEL_REF: | |
376 | /* These conditions are similar to SYMBOL_REF ones, just the | |
377 | constraints for code models differ. */ | |
378 | if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM) | |
4368a420 | 379 | && offset > -0x10000) |
19ed9d7b | 380 | return true; |
8fe75e43 RH |
381 | break; |
382 | ||
383 | default: | |
19ed9d7b | 384 | return false; |
8fe75e43 RH |
385 | } |
386 | } | |
387 | break; | |
388 | ||
389 | default: | |
7637e42c | 390 | gcc_unreachable (); |
8fe75e43 | 391 | } |
19ed9d7b | 392 | return false; |
8fe75e43 RH |
393 | }) |
394 | ||
31ed1665 JJ |
395 | ;; Return true if VALUE is a constant integer whose low and high words satisfy |
396 | ;; x86_64_immediate_operand. | |
397 | (define_predicate "x86_64_hilo_int_operand" | |
398 | (match_code "const_int,const_wide_int") | |
399 | { | |
400 | switch (GET_CODE (op)) | |
401 | { | |
402 | case CONST_INT: | |
403 | return x86_64_immediate_operand (op, mode); | |
404 | ||
405 | case CONST_WIDE_INT: | |
406 | gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2); | |
407 | return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)), | |
408 | DImode) | |
409 | && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, | |
410 | 1)), | |
411 | DImode)); | |
412 | ||
413 | default: | |
414 | gcc_unreachable (); | |
415 | } | |
416 | }) | |
417 | ||
47a6cc4e JJ |
418 | ;; Return true if VALUE is a constant integer whose value is |
419 | ;; x86_64_immediate_operand value zero extended from word mode to mode. | |
420 | (define_predicate "x86_64_dwzext_immediate_operand" | |
421 | (match_code "const_int,const_wide_int") | |
422 | { | |
9a5381f7 | 423 | if (ix86_endbr_immediate_operand (op, VOIDmode)) |
424 | return false; | |
425 | ||
47a6cc4e JJ |
426 | switch (GET_CODE (op)) |
427 | { | |
428 | case CONST_INT: | |
429 | if (!TARGET_64BIT) | |
430 | return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff); | |
431 | return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff); | |
432 | ||
433 | case CONST_WIDE_INT: | |
434 | if (!TARGET_64BIT) | |
435 | return false; | |
436 | return (CONST_WIDE_INT_NUNITS (op) == 2 | |
437 | && CONST_WIDE_INT_ELT (op, 1) == 0 | |
438 | && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode) | |
439 | == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0))); | |
440 | ||
441 | default: | |
442 | gcc_unreachable (); | |
443 | } | |
444 | }) | |
445 | ||
d5e254e1 IE |
446 | ;; Return true if size of VALUE can be stored in a sign |
447 | ;; extended immediate field. | |
448 | (define_predicate "x86_64_immediate_size_operand" | |
449 | (and (match_code "symbol_ref") | |
450 | (ior (not (match_test "TARGET_64BIT")) | |
451 | (match_test "ix86_cmodel == CM_SMALL") | |
452 | (match_test "ix86_cmodel == CM_KERNEL")))) | |
453 | ||
19ed9d7b | 454 | ;; Return true if OP is general operand representable on x86_64. |
8fe75e43 RH |
455 | (define_predicate "x86_64_general_operand" |
456 | (if_then_else (match_test "TARGET_64BIT") | |
457 | (ior (match_operand 0 "nonimmediate_operand") | |
458 | (match_operand 0 "x86_64_immediate_operand")) | |
459 | (match_operand 0 "general_operand"))) | |
460 | ||
31ed1665 JJ |
461 | ;; Return true if OP's both words are general operands representable |
462 | ;; on x86_64. | |
463 | (define_predicate "x86_64_hilo_general_operand" | |
464 | (if_then_else (match_test "TARGET_64BIT") | |
465 | (ior (match_operand 0 "nonimmediate_operand") | |
466 | (match_operand 0 "x86_64_hilo_int_operand")) | |
467 | (match_operand 0 "general_operand"))) | |
468 | ||
d1873c57 JJ |
469 | ;; Return true if OP is non-VOIDmode general operand representable |
470 | ;; on x86_64. This predicate is used in sign-extending conversion | |
471 | ;; operations that require non-VOIDmode immediate operands. | |
472 | (define_predicate "x86_64_sext_operand" | |
473 | (and (match_test "GET_MODE (op) != VOIDmode") | |
474 | (match_operand 0 "x86_64_general_operand"))) | |
475 | ||
476 | ;; Return true if OP is non-VOIDmode general operand. This predicate | |
477 | ;; is used in sign-extending conversion operations that require | |
478 | ;; non-VOIDmode immediate operands. | |
479 | (define_predicate "sext_operand" | |
480 | (and (match_test "GET_MODE (op) != VOIDmode") | |
481 | (match_operand 0 "general_operand"))) | |
482 | ||
7482c470 UB |
483 | ;; Return true if OP is representable on x86_64 as zero-extended operand. |
484 | ;; This predicate is used in zero-extending conversion operations that | |
485 | ;; require non-VOIDmode immediate operands. | |
486 | (define_predicate "x86_64_zext_operand" | |
ca538e97 UB |
487 | (if_then_else (match_test "TARGET_64BIT") |
488 | (ior (match_operand 0 "nonimmediate_operand") | |
3cb2b15b UB |
489 | (and (match_operand 0 "x86_64_zext_immediate_operand") |
490 | (match_test "GET_MODE (op) != VOIDmode"))) | |
7482c470 | 491 | (match_operand 0 "nonimmediate_operand"))) |
ca538e97 | 492 | |
19ed9d7b | 493 | ;; Return true if OP is general operand representable on x86_64 |
8fe75e43 RH |
494 | ;; as either sign extended or zero extended constant. |
495 | (define_predicate "x86_64_szext_general_operand" | |
496 | (if_then_else (match_test "TARGET_64BIT") | |
497 | (ior (match_operand 0 "nonimmediate_operand") | |
aaf5d6c0 UB |
498 | (match_operand 0 "x86_64_immediate_operand") |
499 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
8fe75e43 RH |
500 | (match_operand 0 "general_operand"))) |
501 | ||
19ed9d7b | 502 | ;; Return true if OP is nonmemory operand representable on x86_64. |
8fe75e43 RH |
503 | (define_predicate "x86_64_nonmemory_operand" |
504 | (if_then_else (match_test "TARGET_64BIT") | |
505 | (ior (match_operand 0 "register_operand") | |
506 | (match_operand 0 "x86_64_immediate_operand")) | |
507 | (match_operand 0 "nonmemory_operand"))) | |
508 | ||
19ed9d7b | 509 | ;; Return true if OP is nonmemory operand representable on x86_64. |
8fe75e43 RH |
510 | (define_predicate "x86_64_szext_nonmemory_operand" |
511 | (if_then_else (match_test "TARGET_64BIT") | |
512 | (ior (match_operand 0 "register_operand") | |
aaf5d6c0 UB |
513 | (match_operand 0 "x86_64_immediate_operand") |
514 | (match_operand 0 "x86_64_zext_immediate_operand")) | |
8fe75e43 RH |
515 | (match_operand 0 "nonmemory_operand"))) |
516 | ||
47efdea4 JH |
517 | ;; Return true when operand is PIC expression that can be computed by lea |
518 | ;; operation. | |
a2e49bb2 | 519 | (define_predicate "pic_32bit_operand" |
47efdea4 JH |
520 | (match_code "const,symbol_ref,label_ref") |
521 | { | |
522 | if (!flag_pic) | |
19ed9d7b | 523 | return false; |
a2e49bb2 | 524 | |
47efdea4 JH |
525 | /* Rule out relocations that translate into 64bit constants. */ |
526 | if (TARGET_64BIT && GET_CODE (op) == CONST) | |
527 | { | |
528 | op = XEXP (op, 0); | |
7656aee4 | 529 | if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1))) |
47efdea4 JH |
530 | op = XEXP (op, 0); |
531 | if (GET_CODE (op) == UNSPEC | |
532 | && (XINT (op, 1) == UNSPEC_GOTOFF | |
533 | || XINT (op, 1) == UNSPEC_GOT)) | |
19ed9d7b | 534 | return false; |
47efdea4 | 535 | } |
a2e49bb2 | 536 | |
47efdea4 JH |
537 | return symbolic_operand (op, mode); |
538 | }) | |
539 | ||
19ed9d7b | 540 | ;; Return true if OP is nonmemory operand acceptable by movabs patterns. |
8fe75e43 | 541 | (define_predicate "x86_64_movabs_operand" |
7aecd4e8 UB |
542 | (and (match_operand 0 "nonmemory_operand") |
543 | (not (match_operand 0 "pic_32bit_operand")))) | |
8fe75e43 | 544 | |
19ed9d7b | 545 | ;; Return true if OP is either a symbol reference or a sum of a symbol |
8fe75e43 RH |
546 | ;; reference and a constant. |
547 | (define_predicate "symbolic_operand" | |
548 | (match_code "symbol_ref,label_ref,const") | |
549 | { | |
550 | switch (GET_CODE (op)) | |
551 | { | |
552 | case SYMBOL_REF: | |
553 | case LABEL_REF: | |
19ed9d7b | 554 | return true; |
8fe75e43 RH |
555 | |
556 | case CONST: | |
557 | op = XEXP (op, 0); | |
558 | if (GET_CODE (op) == SYMBOL_REF | |
559 | || GET_CODE (op) == LABEL_REF | |
560 | || (GET_CODE (op) == UNSPEC | |
561 | && (XINT (op, 1) == UNSPEC_GOT | |
562 | || XINT (op, 1) == UNSPEC_GOTOFF | |
986ce92f | 563 | || XINT (op, 1) == UNSPEC_PCREL |
8fe75e43 | 564 | || XINT (op, 1) == UNSPEC_GOTPCREL))) |
19ed9d7b | 565 | return true; |
8fe75e43 | 566 | if (GET_CODE (op) != PLUS |
7656aee4 | 567 | || !CONST_INT_P (XEXP (op, 1))) |
19ed9d7b | 568 | return false; |
8fe75e43 RH |
569 | |
570 | op = XEXP (op, 0); | |
571 | if (GET_CODE (op) == SYMBOL_REF | |
572 | || GET_CODE (op) == LABEL_REF) | |
19ed9d7b | 573 | return true; |
8fe75e43 RH |
574 | /* Only @GOTOFF gets offsets. */ |
575 | if (GET_CODE (op) != UNSPEC | |
576 | || XINT (op, 1) != UNSPEC_GOTOFF) | |
19ed9d7b | 577 | return false; |
8fe75e43 RH |
578 | |
579 | op = XVECEXP (op, 0, 0); | |
580 | if (GET_CODE (op) == SYMBOL_REF | |
581 | || GET_CODE (op) == LABEL_REF) | |
19ed9d7b UB |
582 | return true; |
583 | return false; | |
8fe75e43 RH |
584 | |
585 | default: | |
7637e42c | 586 | gcc_unreachable (); |
8fe75e43 RH |
587 | } |
588 | }) | |
589 | ||
8fe75e43 RH |
590 | ;; Return true if OP is a symbolic operand that resolves locally. |
591 | (define_predicate "local_symbolic_operand" | |
592 | (match_code "const,label_ref,symbol_ref") | |
593 | { | |
594 | if (GET_CODE (op) == CONST | |
595 | && GET_CODE (XEXP (op, 0)) == PLUS | |
7656aee4 | 596 | && CONST_INT_P (XEXP (XEXP (op, 0), 1))) |
8fe75e43 RH |
597 | op = XEXP (XEXP (op, 0), 0); |
598 | ||
599 | if (GET_CODE (op) == LABEL_REF) | |
19ed9d7b | 600 | return true; |
8fe75e43 RH |
601 | |
602 | if (GET_CODE (op) != SYMBOL_REF) | |
19ed9d7b | 603 | return false; |
8fe75e43 | 604 | |
19ed9d7b UB |
605 | if (SYMBOL_REF_TLS_MODEL (op)) |
606 | return false; | |
c1a46941 | 607 | |
9216baf1 KT |
608 | /* Dll-imported symbols are always external. */ |
609 | if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op)) | |
610 | return false; | |
8fe75e43 | 611 | if (SYMBOL_REF_LOCAL_P (op)) |
19ed9d7b | 612 | return true; |
8fe75e43 RH |
613 | |
614 | /* There is, however, a not insubstantial body of code in the rest of | |
615 | the compiler that assumes it can just stick the results of | |
616 | ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */ | |
617 | /* ??? This is a hack. Should update the body of the compiler to | |
618 | always create a DECL an invoke targetm.encode_section_info. */ | |
619 | if (strncmp (XSTR (op, 0), internal_label_prefix, | |
620 | internal_label_prefix_len) == 0) | |
19ed9d7b | 621 | return true; |
8fe75e43 | 622 | |
19ed9d7b | 623 | return false; |
8fe75e43 RH |
624 | }) |
625 | ||
b384d9a0 HJ |
626 | (define_predicate "local_func_symbolic_operand" |
627 | (match_operand 0 "local_symbolic_operand") | |
628 | { | |
629 | if (GET_CODE (op) == CONST | |
630 | && GET_CODE (XEXP (op, 0)) == PLUS | |
631 | && CONST_INT_P (XEXP (XEXP (op, 0), 1))) | |
632 | op = XEXP (XEXP (op, 0), 0); | |
633 | ||
634 | if (GET_CODE (op) == SYMBOL_REF | |
635 | && !SYMBOL_REF_FUNCTION_P (op)) | |
636 | return false; | |
637 | ||
638 | return true; | |
639 | }) | |
640 | ||
170bdaba RS |
641 | ;; Test for a legitimate @GOTOFF operand. |
642 | ;; | |
643 | ;; VxWorks does not impose a fixed gap between segments; the run-time | |
644 | ;; gap can be different from the object-file gap. We therefore can't | |
645 | ;; use @GOTOFF unless we are absolutely sure that the symbol is in the | |
646 | ;; same segment as the GOT. Unfortunately, the flexibility of linker | |
647 | ;; scripts means that we can't be sure of that in general, so assume | |
6c5fffd1 | 648 | ;; @GOTOFF is not valid on VxWorks, except with the large code model. |
170bdaba | 649 | (define_predicate "gotoff_operand" |
6c5fffd1 EB |
650 | (and (ior (not (match_test "TARGET_VXWORKS_RTP")) |
651 | (match_test "ix86_cmodel == CM_LARGE") | |
652 | (match_test "ix86_cmodel == CM_LARGE_PIC")) | |
170bdaba RS |
653 | (match_operand 0 "local_symbolic_operand"))) |
654 | ||
8fe75e43 | 655 | ;; Test for various thread-local symbols. |
62a1c041 | 656 | (define_special_predicate "tls_symbolic_operand" |
8fe75e43 | 657 | (and (match_code "symbol_ref") |
19ed9d7b | 658 | (match_test "SYMBOL_REF_TLS_MODEL (op)"))) |
8fe75e43 | 659 | |
62a1c041 | 660 | (define_special_predicate "tls_modbase_operand" |
5bf5a10b AO |
661 | (and (match_code "symbol_ref") |
662 | (match_test "op == ix86_tls_module_base ()"))) | |
f3648f7d UB |
663 | |
664 | (define_predicate "tls_address_pattern" | |
665 | (and (match_code "set,parallel,unspec,unspec_volatile") | |
666 | (match_test "ix86_tls_address_pattern_p (op)"))) | |
5bf5a10b | 667 | |
8fe75e43 | 668 | ;; Test for a pc-relative call operand |
a1d3d84b | 669 | (define_predicate "constant_call_address_operand" |
da489f73 RH |
670 | (match_code "symbol_ref") |
671 | { | |
e7c77c4f AK |
672 | if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC |
673 | || flag_force_indirect_call) | |
da489f73 RH |
674 | return false; |
675 | if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op)) | |
676 | return false; | |
677 | return true; | |
678 | }) | |
8fe75e43 | 679 | |
cae48a9d | 680 | ;; True for any non-virtual and non-eliminable register. Used in places where |
4150f926 UB |
681 | ;; instantiation of such a register may cause the pattern to not be recognized. |
682 | (define_predicate "register_no_elim_operand" | |
683 | (match_operand 0 "register_operand") | |
684 | { | |
3a6d28d6 | 685 | if (SUBREG_P (op)) |
4150f926 | 686 | op = SUBREG_REG (op); |
b3dd7d8b UB |
687 | |
688 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand | |
689 | because it is guaranteed to be reloaded into one. */ | |
690 | if (MEM_P (op)) | |
691 | return true; | |
692 | ||
4150f926 UB |
693 | return !(op == arg_pointer_rtx |
694 | || op == frame_pointer_rtx | |
cae48a9d | 695 | || VIRTUAL_REGISTER_P (op)); |
4150f926 UB |
696 | }) |
697 | ||
508f0828 UB |
698 | ;; Similarly, but include the stack pointer. This is used |
699 | ;; to prevent esp from being used as an index reg. | |
0fa872c4 | 700 | (define_predicate "register_no_SP_operand" |
8fe75e43 RH |
701 | (match_operand 0 "register_operand") |
702 | { | |
3a6d28d6 | 703 | if (SUBREG_P (op)) |
8fe75e43 | 704 | op = SUBREG_REG (op); |
b3dd7d8b | 705 | |
508f0828 UB |
706 | /* Before reload, we can allow (SUBREG (MEM...)) as a register operand |
707 | because it is guaranteed to be reloaded into one. */ | |
708 | if (MEM_P (op)) | |
709 | return true; | |
710 | ||
711 | return !(op == arg_pointer_rtx | |
712 | || op == frame_pointer_rtx | |
713 | || op == stack_pointer_rtx | |
714 | || VIRTUAL_REGISTER_P (op)); | |
8fe75e43 RH |
715 | }) |
716 | ||
508f0828 UB |
717 | ;; P6 processors will jump to the address after the decrement when %esp |
718 | ;; is used as a call operand, so they will execute return address as a code. | |
719 | ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17. | |
720 | ||
721 | (define_predicate "call_register_operand" | |
722 | (if_then_else (match_test "TARGET_64BIT") | |
723 | (match_operand 0 "register_operand") | |
0fa872c4 | 724 | (match_operand 0 "register_no_SP_operand"))) |
508f0828 | 725 | |
8fe75e43 RH |
726 | ;; Return false if this is any eliminable register. Otherwise general_operand. |
727 | (define_predicate "general_no_elim_operand" | |
728 | (if_then_else (match_code "reg,subreg") | |
729 | (match_operand 0 "register_no_elim_operand") | |
730 | (match_operand 0 "general_operand"))) | |
731 | ||
732 | ;; Return false if this is any eliminable register. Otherwise | |
733 | ;; register_operand or a constant. | |
734 | (define_predicate "nonmemory_no_elim_operand" | |
735 | (ior (match_operand 0 "register_no_elim_operand") | |
736 | (match_operand 0 "immediate_operand"))) | |
737 | ||
6025b127 L |
738 | ;; Test for a valid operand for indirect branch. |
739 | (define_predicate "indirect_branch_operand" | |
b9719055 | 740 | (ior (match_operand 0 "register_operand") |
c2c601b2 | 741 | (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
894c144c | 742 | (not (match_test "TARGET_X32")) |
b9719055 | 743 | (match_operand 0 "memory_operand")))) |
6025b127 | 744 | |
55d2ee57 | 745 | ;; Return true if OP is a memory operands that can be used in sibcalls. |
af9345d7 L |
746 | ;; Since sibcall never returns, we can only use call-clobbered register |
747 | ;; as GOT base. Allow GOT slot here only with pseudo register as GOT | |
748 | ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32 | |
749 | ;; and *sibcall_value_GOT_32 patterns. | |
55d2ee57 | 750 | (define_predicate "sibcall_memory_operand" |
af9345d7 L |
751 | (match_operand 0 "memory_operand") |
752 | { | |
753 | op = XEXP (op, 0); | |
754 | if (CONSTANT_P (op)) | |
755 | return true; | |
756 | if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0))) | |
757 | { | |
758 | int regno = REGNO (XEXP (op, 0)); | |
a365fa06 | 759 | if (!HARD_REGISTER_NUM_P (regno) || call_used_or_fixed_reg_p (regno)) |
af9345d7 L |
760 | { |
761 | op = XEXP (op, 1); | |
762 | if (GOT32_symbol_operand (op, VOIDmode)) | |
763 | return true; | |
764 | } | |
765 | } | |
766 | return false; | |
767 | }) | |
55d2ee57 | 768 | |
fa87d16d L |
769 | ;; Return true if OP is a GOT memory operand. |
770 | (define_predicate "GOT_memory_operand" | |
1b51f038 UB |
771 | (and (match_operand 0 "memory_operand") |
772 | (match_code "const" "0") | |
773 | (match_code "unspec" "00") | |
774 | (match_test "XINT (XEXP (XEXP (op, 0), 0), 1) == UNSPEC_GOTPCREL"))) | |
fa87d16d | 775 | |
8fe75e43 | 776 | ;; Test for a valid operand for a call instruction. |
1ce8d925 UB |
777 | ;; Allow constant call address operands in Pmode only. |
778 | (define_special_predicate "call_insn_operand" | |
a1d3d84b UB |
779 | (ior (match_test "constant_call_address_operand |
780 | (op, mode == VOIDmode ? mode : Pmode)") | |
508f0828 | 781 | (match_operand 0 "call_register_operand") |
c2c601b2 | 782 | (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
5ca876c3 L |
783 | (ior (and (not (match_test "TARGET_X32")) |
784 | (match_operand 0 "memory_operand")) | |
785 | (and (match_test "TARGET_X32 && Pmode == DImode") | |
786 | (match_operand 0 "GOT_memory_operand")))))) | |
8fe75e43 | 787 | |
35fd3193 | 788 | ;; Similarly, but for tail calls, in which we cannot allow memory references. |
1ce8d925 | 789 | (define_special_predicate "sibcall_insn_operand" |
a1d3d84b UB |
790 | (ior (match_test "constant_call_address_operand |
791 | (op, mode == VOIDmode ? mode : Pmode)") | |
cb105922 | 792 | (match_operand 0 "register_no_elim_operand") |
c2c601b2 | 793 | (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER")) |
5ca876c3 L |
794 | (ior (and (not (match_test "TARGET_X32")) |
795 | (match_operand 0 "sibcall_memory_operand")) | |
796 | (and (match_test "TARGET_X32 && Pmode == DImode") | |
797 | (match_operand 0 "GOT_memory_operand")))))) | |
f70d27e0 | 798 | |
af9345d7 L |
799 | ;; Return true if OP is a 32-bit GOT symbol operand. |
800 | (define_predicate "GOT32_symbol_operand" | |
1b51f038 UB |
801 | (and (match_code "const") |
802 | (match_code "unspec" "0") | |
803 | (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_GOT"))) | |
af9345d7 | 804 | |
8fe75e43 RH |
805 | ;; Match exactly zero. |
806 | (define_predicate "const0_operand" | |
eebe7d1c | 807 | (match_code "const_int,const_double,const_vector") |
b4e82619 RH |
808 | { |
809 | if (mode == VOIDmode) | |
810 | mode = GET_MODE (op); | |
811 | return op == CONST0_RTX (mode); | |
812 | }) | |
8fe75e43 | 813 | |
55284a77 | 814 | ;; Match one or a vector with all elements equal to one. |
8fe75e43 | 815 | (define_predicate "const1_operand" |
eebe7d1c | 816 | (match_code "const_int,const_double,const_vector") |
880ab4be AT |
817 | { |
818 | if (mode == VOIDmode) | |
819 | mode = GET_MODE (op); | |
820 | return op == CONST1_RTX (mode); | |
821 | }) | |
8fe75e43 | 822 | |
a7d56fb8 UB |
823 | ;; Match exactly -1. |
824 | (define_predicate "constm1_operand" | |
825 | (and (match_code "const_int") | |
2ff0cbe5 | 826 | (match_test "op == constm1_rtx"))) |
a7d56fb8 | 827 | |
f7acbf4c RS |
828 | ;; Match exactly eight. |
829 | (define_predicate "const8_operand" | |
830 | (and (match_code "const_int") | |
831 | (match_test "INTVAL (op) == 8"))) | |
832 | ||
a952487c JJ |
833 | ;; Match exactly 128. |
834 | (define_predicate "const128_operand" | |
835 | (and (match_code "const_int") | |
836 | (match_test "INTVAL (op) == 128"))) | |
837 | ||
88b590c5 UB |
838 | ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation |
839 | (define_predicate "const_32bit_mask" | |
840 | (and (match_code "const_int") | |
841 | (match_test "trunc_int_for_mode (INTVAL (op), DImode) | |
842 | == (HOST_WIDE_INT) 0xffffffff"))) | |
843 | ||
8fe75e43 RH |
844 | ;; Match 2, 4, or 8. Used for leal multiplicands. |
845 | (define_predicate "const248_operand" | |
846 | (match_code "const_int") | |
847 | { | |
848 | HOST_WIDE_INT i = INTVAL (op); | |
849 | return i == 2 || i == 4 || i == 8; | |
850 | }) | |
851 | ||
d697acca BS |
852 | ;; Match 1, 2, or 3. Used for lea shift amounts. |
853 | (define_predicate "const123_operand" | |
854 | (match_code "const_int") | |
855 | { | |
856 | HOST_WIDE_INT i = INTVAL (op); | |
857 | return i == 1 || i == 2 || i == 3; | |
858 | }) | |
859 | ||
66b03f81 UB |
860 | ;; Match 2, 3, 6, or 7 |
861 | (define_predicate "const2367_operand" | |
cf73ee60 KY |
862 | (match_code "const_int") |
863 | { | |
864 | HOST_WIDE_INT i = INTVAL (op); | |
66b03f81 | 865 | return i == 2 || i == 3 || i == 6 || i == 7; |
cf73ee60 KY |
866 | }) |
867 | ||
977e83a3 KY |
868 | ;; Match 1, 2, 4, or 8 |
869 | (define_predicate "const1248_operand" | |
870 | (match_code "const_int") | |
871 | { | |
872 | HOST_WIDE_INT i = INTVAL (op); | |
873 | return i == 1 || i == 2 || i == 4 || i == 8; | |
874 | }) | |
875 | ||
3b4c46d7 L |
876 | ;; Match 3, 5, or 9. Used for leal multiplicands. |
877 | (define_predicate "const359_operand" | |
878 | (match_code "const_int") | |
879 | { | |
880 | HOST_WIDE_INT i = INTVAL (op); | |
881 | return i == 3 || i == 5 || i == 9; | |
882 | }) | |
883 | ||
de72ea02 IT |
884 | ;; Match 4 or 8 to 11. Used for embeded rounding. |
885 | (define_predicate "const_4_or_8_to_11_operand" | |
886 | (match_code "const_int") | |
887 | { | |
888 | HOST_WIDE_INT i = INTVAL (op); | |
889 | return i == 4 || (i >= 8 && i <= 11); | |
890 | }) | |
891 | ||
892 | ;; Match 4 or 8. Used for SAE. | |
893 | (define_predicate "const48_operand" | |
894 | (match_code "const_int") | |
895 | { | |
896 | HOST_WIDE_INT i = INTVAL (op); | |
897 | return i == 4 || i == 8; | |
898 | }) | |
899 | ||
ef719a44 RH |
900 | ;; Match 0 or 1. |
901 | (define_predicate "const_0_to_1_operand" | |
902 | (and (match_code "const_int") | |
77fa1d54 UB |
903 | (ior (match_test "op == const0_rtx") |
904 | (match_test "op == const1_rtx")))) | |
ef719a44 | 905 | |
8fe75e43 RH |
906 | ;; Match 0 to 3. |
907 | (define_predicate "const_0_to_3_operand" | |
908 | (and (match_code "const_int") | |
8dde5924 | 909 | (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) |
8fe75e43 | 910 | |
47490470 AI |
911 | ;; Match 0 to 4. |
912 | (define_predicate "const_0_to_4_operand" | |
913 | (and (match_code "const_int") | |
914 | (match_test "IN_RANGE (INTVAL (op), 0, 4)"))) | |
915 | ||
916 | ;; Match 0 to 5. | |
917 | (define_predicate "const_0_to_5_operand" | |
918 | (and (match_code "const_int") | |
919 | (match_test "IN_RANGE (INTVAL (op), 0, 5)"))) | |
920 | ||
8fe75e43 RH |
921 | ;; Match 0 to 7. |
922 | (define_predicate "const_0_to_7_operand" | |
923 | (and (match_code "const_int") | |
8dde5924 | 924 | (match_test "IN_RANGE (INTVAL (op), 0, 7)"))) |
8fe75e43 RH |
925 | |
926 | ;; Match 0 to 15. | |
927 | (define_predicate "const_0_to_15_operand" | |
928 | (and (match_code "const_int") | |
8dde5924 | 929 | (match_test "IN_RANGE (INTVAL (op), 0, 15)"))) |
8fe75e43 | 930 | |
04e1d06b MM |
931 | ;; Match 0 to 31. |
932 | (define_predicate "const_0_to_31_operand" | |
933 | (and (match_code "const_int") | |
934 | (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) | |
935 | ||
7cacf53e RH |
936 | ;; Match 0 to 63. |
937 | (define_predicate "const_0_to_63_operand" | |
938 | (and (match_code "const_int") | |
8dde5924 | 939 | (match_test "IN_RANGE (INTVAL (op), 0, 63)"))) |
7cacf53e | 940 | |
5b7a9751 RS |
941 | ;; Match 0 to 127. |
942 | (define_predicate "const_0_to_127_operand" | |
943 | (and (match_code "const_int") | |
944 | (match_test "IN_RANGE (INTVAL (op), 0, 127)"))) | |
945 | ||
8fe75e43 RH |
946 | ;; Match 0 to 255. |
947 | (define_predicate "const_0_to_255_operand" | |
948 | (and (match_code "const_int") | |
8dde5924 | 949 | (match_test "IN_RANGE (INTVAL (op), 0, 255)"))) |
8fe75e43 | 950 | |
ef719a44 RH |
951 | ;; Match (0 to 255) * 8 |
952 | (define_predicate "const_0_to_255_mul_8_operand" | |
953 | (match_code "const_int") | |
954 | { | |
955 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
956 | return val <= 255*8 && val % 8 == 0; | |
957 | }) | |
958 | ||
4991e209 RS |
959 | ;; Match 1 to 255 except multiples of 8 |
960 | (define_predicate "const_0_to_255_not_mul_8_operand" | |
961 | (match_code "const_int") | |
962 | { | |
963 | unsigned HOST_WIDE_INT val = INTVAL (op); | |
964 | return val <= 255 && val % 8 != 0; | |
965 | }) | |
966 | ||
19ed9d7b | 967 | ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand |
ef719a44 RH |
968 | ;; for shift & compare patterns, as shifting by 0 does not change flags). |
969 | (define_predicate "const_1_to_31_operand" | |
970 | (and (match_code "const_int") | |
8dde5924 | 971 | (match_test "IN_RANGE (INTVAL (op), 1, 31)"))) |
ef719a44 | 972 | |
19ed9d7b | 973 | ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand |
934f2a96 UB |
974 | ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags). |
975 | (define_predicate "const_1_to_63_operand" | |
976 | (and (match_code "const_int") | |
977 | (match_test "IN_RANGE (INTVAL (op), 1, 63)"))) | |
978 | ||
ef719a44 RH |
979 | ;; Match 2 or 3. |
980 | (define_predicate "const_2_to_3_operand" | |
981 | (and (match_code "const_int") | |
8dde5924 | 982 | (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) |
ef719a44 | 983 | |
95879c72 L |
984 | ;; Match 4 to 5. |
985 | (define_predicate "const_4_to_5_operand" | |
986 | (and (match_code "const_int") | |
987 | (match_test "IN_RANGE (INTVAL (op), 4, 5)"))) | |
988 | ||
ef719a44 RH |
989 | ;; Match 4 to 7. |
990 | (define_predicate "const_4_to_7_operand" | |
991 | (and (match_code "const_int") | |
8dde5924 | 992 | (match_test "IN_RANGE (INTVAL (op), 4, 7)"))) |
ef719a44 | 993 | |
95879c72 L |
994 | ;; Match 6 to 7. |
995 | (define_predicate "const_6_to_7_operand" | |
996 | (and (match_code "const_int") | |
997 | (match_test "IN_RANGE (INTVAL (op), 6, 7)"))) | |
998 | ||
c003c6d6 AI |
999 | ;; Match 8 to 9. |
1000 | (define_predicate "const_8_to_9_operand" | |
1001 | (and (match_code "const_int") | |
1002 | (match_test "IN_RANGE (INTVAL (op), 8, 9)"))) | |
1003 | ||
95879c72 L |
1004 | ;; Match 8 to 11. |
1005 | (define_predicate "const_8_to_11_operand" | |
1006 | (and (match_code "const_int") | |
1007 | (match_test "IN_RANGE (INTVAL (op), 8, 11)"))) | |
1008 | ||
2e2206fa AI |
1009 | ;; Match 8 to 15. |
1010 | (define_predicate "const_8_to_15_operand" | |
1011 | (and (match_code "const_int") | |
1012 | (match_test "IN_RANGE (INTVAL (op), 8, 15)"))) | |
1013 | ||
c003c6d6 AI |
1014 | ;; Match 10 to 11. |
1015 | (define_predicate "const_10_to_11_operand" | |
1016 | (and (match_code "const_int") | |
1017 | (match_test "IN_RANGE (INTVAL (op), 10, 11)"))) | |
1018 | ||
1019 | ;; Match 12 to 13. | |
1020 | (define_predicate "const_12_to_13_operand" | |
1021 | (and (match_code "const_int") | |
1022 | (match_test "IN_RANGE (INTVAL (op), 12, 13)"))) | |
1023 | ||
95879c72 L |
1024 | ;; Match 12 to 15. |
1025 | (define_predicate "const_12_to_15_operand" | |
1026 | (and (match_code "const_int") | |
1027 | (match_test "IN_RANGE (INTVAL (op), 12, 15)"))) | |
1028 | ||
c003c6d6 AI |
1029 | ;; Match 14 to 15. |
1030 | (define_predicate "const_14_to_15_operand" | |
1031 | (and (match_code "const_int") | |
1032 | (match_test "IN_RANGE (INTVAL (op), 14, 15)"))) | |
1033 | ||
1034 | ;; Match 16 to 19. | |
1035 | (define_predicate "const_16_to_19_operand" | |
1036 | (and (match_code "const_int") | |
1037 | (match_test "IN_RANGE (INTVAL (op), 16, 19)"))) | |
1038 | ||
2e2206fa AI |
1039 | ;; Match 16 to 31. |
1040 | (define_predicate "const_16_to_31_operand" | |
1041 | (and (match_code "const_int") | |
1042 | (match_test "IN_RANGE (INTVAL (op), 16, 31)"))) | |
1043 | ||
c003c6d6 AI |
1044 | ;; Match 20 to 23. |
1045 | (define_predicate "const_20_to_23_operand" | |
1046 | (and (match_code "const_int") | |
1047 | (match_test "IN_RANGE (INTVAL (op), 20, 23)"))) | |
1048 | ||
1049 | ;; Match 24 to 27. | |
1050 | (define_predicate "const_24_to_27_operand" | |
1051 | (and (match_code "const_int") | |
1052 | (match_test "IN_RANGE (INTVAL (op), 24, 27)"))) | |
1053 | ||
1054 | ;; Match 28 to 31. | |
1055 | (define_predicate "const_28_to_31_operand" | |
1056 | (and (match_code "const_int") | |
1057 | (match_test "IN_RANGE (INTVAL (op), 28, 31)"))) | |
1058 | ||
8fe75e43 RH |
1059 | ;; True if this is a constant appropriate for an increment or decrement. |
1060 | (define_predicate "incdec_operand" | |
1061 | (match_code "const_int") | |
1062 | { | |
1063 | /* On Pentium4, the inc and dec operations causes extra dependency on flag | |
1064 | registers, since carry flag is not set. */ | |
700ae70c | 1065 | if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ()) |
19ed9d7b | 1066 | return false; |
8fe75e43 RH |
1067 | return op == const1_rtx || op == constm1_rtx; |
1068 | }) | |
1069 | ||
287cc750 | 1070 | ;; True for registers, or const_int_operand, used to vec_setm expander. |
8d980e84 | 1071 | (define_predicate "vec_setm_sse41_operand" |
287cc750 | 1072 | (ior (and (match_operand 0 "register_operand") |
f6587817 | 1073 | (match_test "TARGET_SSE4_1")) |
287cc750 | 1074 | (match_code "const_int"))) |
1075 | ||
8d980e84 UB |
1076 | (define_predicate "vec_setm_avx2_operand" |
1077 | (ior (and (match_operand 0 "register_operand") | |
1078 | (match_test "TARGET_AVX2")) | |
1079 | (match_code "const_int"))) | |
1080 | ||
20a2c8ac UB |
1081 | (define_predicate "vec_setm_mmx_operand" |
1082 | (ior (and (match_operand 0 "register_operand") | |
1083 | (match_test "TARGET_SSE4_1") | |
1084 | (match_test "TARGET_MMX_WITH_SSE")) | |
1085 | (match_code "const_int"))) | |
1086 | ||
93330ea1 RH |
1087 | ;; True for registers, or 1 or -1. Used to optimize double-word shifts. |
1088 | (define_predicate "reg_or_pm1_operand" | |
1089 | (ior (match_operand 0 "register_operand") | |
1090 | (and (match_code "const_int") | |
77fa1d54 UB |
1091 | (ior (match_test "op == const1_rtx") |
1092 | (match_test "op == constm1_rtx"))))) | |
93330ea1 | 1093 | |
6ddb30f9 | 1094 | ;; True for registers, or (not: registers). Used to optimize 3-operand |
1095 | ;; bitwise operation. | |
bc9c8e5f | 1096 | (define_predicate "regmem_or_bitnot_regmem_operand" |
1097 | (ior (match_operand 0 "nonimmediate_operand") | |
6ddb30f9 | 1098 | (and (match_code "not") |
bc9c8e5f | 1099 | (match_test "nonimmediate_operand (XEXP (op, 0), mode)")))) |
6ddb30f9 | 1100 | |
8fe75e43 RH |
1101 | ;; True if OP is acceptable as operand of DImode shift expander. |
1102 | (define_predicate "shiftdi_operand" | |
1103 | (if_then_else (match_test "TARGET_64BIT") | |
1104 | (match_operand 0 "nonimmediate_operand") | |
1105 | (match_operand 0 "register_operand"))) | |
1106 | ||
93330ea1 RH |
1107 | (define_predicate "ashldi_input_operand" |
1108 | (if_then_else (match_test "TARGET_64BIT") | |
1109 | (match_operand 0 "nonimmediate_operand") | |
1110 | (match_operand 0 "reg_or_pm1_operand"))) | |
1111 | ||
8fe75e43 | 1112 | ;; Return true if OP is a vector load from the constant pool with just |
0e40b5f2 | 1113 | ;; the first element nonzero. |
8fe75e43 RH |
1114 | (define_predicate "zero_extended_scalar_load_operand" |
1115 | (match_code "mem") | |
1116 | { | |
1117 | unsigned n_elts; | |
76ff5c24 | 1118 | op = avoid_constant_pool_reference (op); |
1a66936f | 1119 | |
76ff5c24 | 1120 | if (GET_CODE (op) != CONST_VECTOR) |
19ed9d7b | 1121 | return false; |
1a66936f UB |
1122 | |
1123 | n_elts = CONST_VECTOR_NUNITS (op); | |
1124 | ||
8fe75e43 RH |
1125 | for (n_elts--; n_elts > 0; n_elts--) |
1126 | { | |
1127 | rtx elt = CONST_VECTOR_ELT (op, n_elts); | |
1128 | if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op)))) | |
19ed9d7b | 1129 | return false; |
8fe75e43 | 1130 | } |
19ed9d7b | 1131 | return true; |
8fe75e43 RH |
1132 | }) |
1133 | ||
ee78c20e | 1134 | /* Return true if operand is a float vector constant that is all ones. */ |
1135 | (define_predicate "float_vector_all_ones_operand" | |
1136 | (match_code "const_vector,mem") | |
1137 | { | |
1138 | mode = GET_MODE (op); | |
1139 | if (!FLOAT_MODE_P (mode) | |
1140 | || (MEM_P (op) | |
1141 | && (!SYMBOL_REF_P (XEXP (op, 0)) | |
1142 | || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))))) | |
1143 | return false; | |
1144 | ||
1145 | if (MEM_P (op)) | |
1146 | { | |
1147 | op = get_pool_constant (XEXP (op, 0)); | |
1148 | if (GET_CODE (op) != CONST_VECTOR) | |
1149 | return false; | |
1150 | ||
1151 | if (GET_MODE (op) != mode | |
1152 | && INTEGRAL_MODE_P (GET_MODE (op)) | |
1153 | && op == CONSTM1_RTX (GET_MODE (op))) | |
1154 | return true; | |
1155 | } | |
1156 | ||
1157 | rtx first = XVECEXP (op, 0, 0); | |
1158 | for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++) | |
1159 | { | |
1160 | rtx tmp = XVECEXP (op, 0, i); | |
1161 | if (!rtx_equal_p (tmp, first)) | |
1162 | return false; | |
1163 | } | |
1164 | if (GET_MODE (first) == E_SFmode) | |
1165 | { | |
1166 | long l; | |
1167 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l); | |
1168 | return (l & 0xffffffff) == 0xffffffff; | |
1169 | } | |
1170 | else if (GET_MODE (first) == E_DFmode) | |
1171 | { | |
1172 | long l[2]; | |
1173 | REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l); | |
1174 | return ((l[0] & 0xffffffff) == 0xffffffff | |
1175 | && (l[1] & 0xffffffff) == 0xffffffff); | |
1176 | } | |
1177 | else | |
1178 | return false; | |
1179 | }) | |
1180 | ||
13c556d6 | 1181 | /* Return true if operand is an integral vector constant that is all ones. */ |
5656a184 | 1182 | (define_predicate "vector_all_ones_operand" |
30aa6349 RS |
1183 | (and (match_code "const_vector") |
1184 | (match_test "INTEGRAL_MODE_P (GET_MODE (op))") | |
1185 | (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) | |
5656a184 | 1186 | |
13c556d6 | 1187 | /* Return true if operand is a vector constant that is all ones. */ |
1188 | (define_predicate "int_float_vector_all_ones_operand" | |
1189 | (ior (match_operand 0 "vector_all_ones_operand") | |
1190 | (match_operand 0 "float_vector_all_ones_operand") | |
1191 | (match_test "op == constm1_rtx"))) | |
1192 | ||
a282f086 HL |
1193 | /* Return true if operand is an 128/256bit all ones vector |
1194 | that zero-extends to 256/512bit. */ | |
1195 | (define_predicate "vector_all_ones_zero_extend_half_operand" | |
1196 | (match_code "const_vector") | |
1197 | { | |
1198 | mode = GET_MODE (op); | |
1199 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT | |
1200 | || (GET_MODE_SIZE (mode) != 32 | |
1201 | && GET_MODE_SIZE (mode) != 64)) | |
1202 | return false; | |
1203 | ||
1204 | int nelts = CONST_VECTOR_NUNITS (op); | |
1205 | for (int i = 0; i != nelts; i++) | |
1206 | { | |
1207 | rtx elt = CONST_VECTOR_ELT (op, i); | |
1208 | if (i < nelts / 2 | |
1209 | && elt != CONSTM1_RTX (GET_MODE_INNER (mode))) | |
1210 | return false; | |
1211 | if (i >= nelts / 2 | |
1212 | && elt != CONST0_RTX (GET_MODE_INNER (mode))) | |
1213 | return false; | |
1214 | } | |
1215 | return true; | |
1216 | }) | |
1217 | ||
1218 | /* Return true if operand is an 128bit all ones vector | |
1219 | that zero extends to 512bit. */ | |
1220 | (define_predicate "vector_all_ones_zero_extend_quarter_operand" | |
1221 | (match_code "const_vector") | |
1222 | { | |
1223 | mode = GET_MODE (op); | |
1224 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT | |
1225 | || GET_MODE_SIZE (mode) != 64) | |
1226 | return false; | |
1227 | ||
1228 | int nelts = CONST_VECTOR_NUNITS (op); | |
1229 | for (int i = 0; i != nelts; i++) | |
1230 | { | |
1231 | rtx elt = CONST_VECTOR_ELT (op, i); | |
1232 | if (i < nelts / 4 | |
1233 | && elt != CONSTM1_RTX (GET_MODE_INNER (mode))) | |
1234 | return false; | |
1235 | if (i >= nelts / 4 | |
1236 | && elt != CONST0_RTX (GET_MODE_INNER (mode))) | |
1237 | return false; | |
1238 | } | |
1239 | return true; | |
1240 | }) | |
1241 | ||
3f50525d L |
1242 | ; Return true when OP is operand acceptable for vector memory operand. |
1243 | ; Only AVX can have misaligned memory operand. | |
1244 | (define_predicate "vector_memory_operand" | |
1245 | (and (match_operand 0 "memory_operand") | |
1246 | (ior (match_test "TARGET_AVX") | |
1247 | (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)")))) | |
1248 | ||
acf93f1e L |
1249 | ; Return true when OP is register_operand or vector_memory_operand. |
1250 | (define_predicate "vector_operand" | |
1251 | (ior (match_operand 0 "register_operand") | |
1252 | (match_operand 0 "vector_memory_operand"))) | |
1253 | ||
fa271afb JJ |
1254 | ; Return true when OP is register_operand, vector_memory_operand |
1255 | ; or const_vector. | |
1256 | (define_predicate "vector_or_const_vector_operand" | |
1257 | (ior (match_operand 0 "register_operand") | |
1258 | (match_operand 0 "vector_memory_operand") | |
1259 | (match_code "const_vector"))) | |
1260 | ||
7026bb95 | 1261 | (define_predicate "bcst_mem_operand" |
1262 | (and (match_code "vec_duplicate") | |
1263 | (and (match_test "TARGET_AVX512F") | |
1264 | (ior (match_test "TARGET_AVX512VL") | |
c1eef66b HJ |
1265 | (and (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64") |
1266 | (match_test "TARGET_EVEX512")))) | |
7026bb95 | 1267 | (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))") |
4d232131 L |
1268 | (match_test "GET_MODE (XEXP (op, 0)) |
1269 | == GET_MODE_INNER (GET_MODE (op))") | |
7026bb95 | 1270 | (match_test "memory_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) |
1271 | ||
1272 | ; Return true when OP is bcst_mem_operand or vector_memory_operand. | |
1273 | (define_predicate "bcst_vector_operand" | |
1274 | (ior (match_operand 0 "vector_operand") | |
1275 | (match_operand 0 "bcst_mem_operand"))) | |
1276 | ||
42bace41 JJ |
1277 | ;; Return true when OP is either nonimmediate operand, or any |
1278 | ;; CONST_VECTOR. | |
1279 | (define_predicate "nonimmediate_or_const_vector_operand" | |
1280 | (ior (match_operand 0 "nonimmediate_operand") | |
1281 | (match_code "const_vector"))) | |
1282 | ||
813ccbe9 | 1283 | (define_predicate "nonimmediate_or_const_vec_dup_operand" |
1284 | (ior (match_operand 0 "nonimmediate_operand") | |
1285 | (match_test "const_vec_duplicate_p (op)"))) | |
1286 | ||
4be31286 AO |
1287 | ;; Return true when OP is either register operand, or any |
1288 | ;; CONST_VECTOR. | |
1289 | (define_predicate "reg_or_const_vector_operand" | |
1290 | (ior (match_operand 0 "register_operand") | |
1291 | (match_code "const_vector"))) | |
1292 | ||
f3a5e75c L |
1293 | ;; Return true when OP is CONST_VECTOR which can be converted to a |
1294 | ;; sign extended 32-bit integer. | |
1295 | (define_predicate "x86_64_const_vector_operand" | |
1296 | (match_code "const_vector") | |
1297 | { | |
43c2505b RS |
1298 | if (mode == VOIDmode) |
1299 | mode = GET_MODE (op); | |
1300 | else if (GET_MODE (op) != mode) | |
1301 | return false; | |
f3a5e75c L |
1302 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) |
1303 | return false; | |
1304 | HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op, mode); | |
1305 | return trunc_int_for_mode (val, SImode) == val; | |
1306 | }) | |
1307 | ||
605b6425 | 1308 | (define_predicate "nonimmediate_or_x86_64_const_vector_operand" |
1309 | (ior (match_operand 0 "nonimmediate_operand") | |
1310 | (match_operand 0 "x86_64_const_vector_operand"))) | |
1311 | ||
19ed9d7b | 1312 | ;; Return true when OP is nonimmediate or standard SSE constant. |
5656a184 | 1313 | (define_predicate "nonimmediate_or_sse_const_operand" |
55284a77 UB |
1314 | (ior (match_operand 0 "nonimmediate_operand") |
1315 | (match_test "standard_sse_constant_p (op, mode)"))) | |
5656a184 | 1316 | |
eb701deb RH |
1317 | ;; Return true if OP is a register or a zero. |
1318 | (define_predicate "reg_or_0_operand" | |
1319 | (ior (match_operand 0 "register_operand") | |
1320 | (match_operand 0 "const0_operand"))) | |
1321 | ||
808d8de5 UB |
1322 | ; Return true when OP is a nonimmediate or zero. |
1323 | (define_predicate "nonimm_or_0_operand" | |
1324 | (ior (match_operand 0 "nonimmediate_operand") | |
1325 | (match_operand 0 "const0_operand"))) | |
1326 | ||
65e95828 UB |
1327 | ;; Return true for RTX codes that force SImode address. |
1328 | (define_predicate "SImode_address_operand" | |
1329 | (match_code "subreg,zero_extend,and")) | |
1330 | ||
249be95c | 1331 | ;; Return true if op is a valid address for LEA, and does not contain |
5da6a383 UB |
1332 | ;; a segment override. Defined as a special predicate to allow |
1333 | ;; mode-less const_int operands pass to address_operand. | |
66d6cbaa | 1334 | (define_special_predicate "address_no_seg_operand" |
0d9a5f8a | 1335 | (match_test "address_operand (op, VOIDmode)") |
8fe75e43 RH |
1336 | { |
1337 | struct ix86_address parts; | |
7637e42c NS |
1338 | int ok; |
1339 | ||
0d9a5f8a UB |
1340 | if (!CONST_INT_P (op) |
1341 | && mode != VOIDmode | |
1342 | && GET_MODE (op) != mode) | |
1343 | return false; | |
1344 | ||
7637e42c NS |
1345 | ok = ix86_decompose_address (op, &parts); |
1346 | gcc_assert (ok); | |
00402c94 | 1347 | return parts.seg == ADDR_SPACE_GENERIC; |
8fe75e43 RH |
1348 | }) |
1349 | ||
e43451aa JJ |
1350 | ;; Return true if op if a valid base register, displacement or |
1351 | ;; sum of base register and displacement for VSIB addressing. | |
1352 | (define_predicate "vsib_address_operand" | |
0d9a5f8a | 1353 | (match_test "address_operand (op, VOIDmode)") |
e43451aa JJ |
1354 | { |
1355 | struct ix86_address parts; | |
1356 | int ok; | |
1357 | rtx disp; | |
1358 | ||
1359 | ok = ix86_decompose_address (op, &parts); | |
1360 | gcc_assert (ok); | |
00402c94 | 1361 | if (parts.index || parts.seg != ADDR_SPACE_GENERIC) |
e43451aa JJ |
1362 | return false; |
1363 | ||
1364 | /* VSIB addressing doesn't support (%rip). */ | |
f7bc421d | 1365 | if (parts.disp) |
e43451aa | 1366 | { |
f7bc421d JJ |
1367 | disp = parts.disp; |
1368 | if (GET_CODE (disp) == CONST) | |
1369 | { | |
1370 | disp = XEXP (disp, 0); | |
1371 | if (GET_CODE (disp) == PLUS) | |
1372 | disp = XEXP (disp, 0); | |
1373 | if (GET_CODE (disp) == UNSPEC) | |
1374 | switch (XINT (disp, 1)) | |
1375 | { | |
1376 | case UNSPEC_GOTPCREL: | |
1377 | case UNSPEC_PCREL: | |
1378 | case UNSPEC_GOTNTPOFF: | |
1379 | return false; | |
1380 | } | |
1381 | } | |
1382 | if (TARGET_64BIT | |
1383 | && flag_pic | |
1384 | && (GET_CODE (disp) == SYMBOL_REF | |
1385 | || GET_CODE (disp) == LABEL_REF)) | |
1386 | return false; | |
e43451aa JJ |
1387 | } |
1388 | ||
1389 | return true; | |
1390 | }) | |
1391 | ||
1392 | (define_predicate "vsib_mem_operator" | |
1393 | (match_code "mem")) | |
1394 | ||
19ed9d7b | 1395 | ;; Return true if the rtx is known to be at least 32 bits aligned. |
8fe75e43 RH |
1396 | (define_predicate "aligned_operand" |
1397 | (match_operand 0 "general_operand") | |
1398 | { | |
1399 | struct ix86_address parts; | |
7637e42c | 1400 | int ok; |
8fe75e43 RH |
1401 | |
1402 | /* Registers and immediate operands are always "aligned". */ | |
52f84254 | 1403 | if (!MEM_P (op)) |
19ed9d7b | 1404 | return true; |
8fe75e43 | 1405 | |
d326eaf0 JH |
1406 | /* All patterns using aligned_operand on memory operands ends up |
1407 | in promoting memory operand to 64bit and thus causing memory mismatch. */ | |
700ae70c | 1408 | if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ()) |
19ed9d7b | 1409 | return false; |
d326eaf0 | 1410 | |
8fe75e43 RH |
1411 | /* Don't even try to do any aligned optimizations with volatiles. */ |
1412 | if (MEM_VOLATILE_P (op)) | |
19ed9d7b | 1413 | return false; |
0cd0c6fb JJ |
1414 | |
1415 | if (MEM_ALIGN (op) >= 32) | |
19ed9d7b | 1416 | return true; |
0cd0c6fb | 1417 | |
8fe75e43 RH |
1418 | op = XEXP (op, 0); |
1419 | ||
1420 | /* Pushes and pops are only valid on the stack pointer. */ | |
1421 | if (GET_CODE (op) == PRE_DEC | |
1422 | || GET_CODE (op) == POST_INC) | |
19ed9d7b | 1423 | return true; |
8fe75e43 RH |
1424 | |
1425 | /* Decode the address. */ | |
7637e42c NS |
1426 | ok = ix86_decompose_address (op, &parts); |
1427 | gcc_assert (ok); | |
8fe75e43 | 1428 | |
3a6d28d6 | 1429 | if (parts.base && SUBREG_P (parts.base)) |
24911a50 | 1430 | parts.base = SUBREG_REG (parts.base); |
3a6d28d6 | 1431 | if (parts.index && SUBREG_P (parts.index)) |
24911a50 UB |
1432 | parts.index = SUBREG_REG (parts.index); |
1433 | ||
8fe75e43 RH |
1434 | /* Look for some component that isn't known to be aligned. */ |
1435 | if (parts.index) | |
1436 | { | |
1437 | if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32) | |
19ed9d7b | 1438 | return false; |
8fe75e43 RH |
1439 | } |
1440 | if (parts.base) | |
1441 | { | |
1442 | if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32) | |
19ed9d7b | 1443 | return false; |
8fe75e43 RH |
1444 | } |
1445 | if (parts.disp) | |
1446 | { | |
7656aee4 | 1447 | if (!CONST_INT_P (parts.disp) |
19ed9d7b UB |
1448 | || (INTVAL (parts.disp) & 3)) |
1449 | return false; | |
8fe75e43 RH |
1450 | } |
1451 | ||
1452 | /* Didn't find one -- this must be an aligned address. */ | |
19ed9d7b | 1453 | return true; |
8fe75e43 RH |
1454 | }) |
1455 | ||
19ed9d7b | 1456 | ;; Return true if OP is memory operand with a displacement. |
8fe75e43 RH |
1457 | (define_predicate "memory_displacement_operand" |
1458 | (match_operand 0 "memory_operand") | |
1459 | { | |
1460 | struct ix86_address parts; | |
7637e42c NS |
1461 | int ok; |
1462 | ||
1463 | ok = ix86_decompose_address (XEXP (op, 0), &parts); | |
1464 | gcc_assert (ok); | |
8fe75e43 RH |
1465 | return parts.disp != NULL_RTX; |
1466 | }) | |
1467 | ||
19ed9d7b | 1468 | ;; Return true if OP is memory operand with a displacement only. |
1c287121 UB |
1469 | (define_predicate "memory_displacement_only_operand" |
1470 | (match_operand 0 "memory_operand") | |
1471 | { | |
1472 | struct ix86_address parts; | |
1473 | int ok; | |
1474 | ||
a952487c | 1475 | if (TARGET_64BIT) |
19ed9d7b | 1476 | return false; |
a952487c | 1477 | |
1c287121 UB |
1478 | ok = ix86_decompose_address (XEXP (op, 0), &parts); |
1479 | gcc_assert (ok); | |
1480 | ||
1481 | if (parts.base || parts.index) | |
19ed9d7b | 1482 | return false; |
1c287121 UB |
1483 | |
1484 | return parts.disp != NULL_RTX; | |
1485 | }) | |
1486 | ||
19ed9d7b | 1487 | ;; Return true if OP is memory operand that cannot be represented |
8fe75e43 RH |
1488 | ;; by the modRM array. |
1489 | (define_predicate "long_memory_operand" | |
1490 | (and (match_operand 0 "memory_operand") | |
cab54dfa | 1491 | (match_test "memory_address_length (op, false)"))) |
8fe75e43 | 1492 | |
19ed9d7b | 1493 | ;; Return true if OP is a comparison operator that can be issued by fcmov. |
8fe75e43 RH |
1494 | (define_predicate "fcmov_comparison_operator" |
1495 | (match_operand 0 "comparison_operator") | |
1496 | { | |
ef4bddc2 | 1497 | machine_mode inmode = GET_MODE (XEXP (op, 0)); |
8fe75e43 RH |
1498 | enum rtx_code code = GET_CODE (op); |
1499 | ||
3f563e0b | 1500 | if (inmode == CCFPmode) |
d03ca8a6 UB |
1501 | code = ix86_fp_compare_code_to_integer (code); |
1502 | ||
8fe75e43 RH |
1503 | /* i387 supports just limited amount of conditional codes. */ |
1504 | switch (code) | |
1505 | { | |
d03ca8a6 UB |
1506 | case GEU: case LTU: |
1507 | if (inmode == CCCmode || inmode == CCGZmode) | |
1508 | return true; | |
1509 | /* FALLTHRU */ | |
1510 | case GTU: case LEU: | |
1511 | if (inmode == CCmode || inmode == CCFPmode) | |
19ed9d7b UB |
1512 | return true; |
1513 | return false; | |
8fe75e43 RH |
1514 | case ORDERED: case UNORDERED: |
1515 | case EQ: case NE: | |
19ed9d7b | 1516 | return true; |
8fe75e43 | 1517 | default: |
19ed9d7b | 1518 | return false; |
8fe75e43 RH |
1519 | } |
1520 | }) | |
1521 | ||
19ed9d7b | 1522 | ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns. |
8fe75e43 RH |
1523 | ;; The first set are supported directly; the second set can't be done with |
1524 | ;; full IEEE support, i.e. NaNs. | |
07c0852e UB |
1525 | |
1526 | (define_predicate "sse_comparison_operator" | |
1527 | (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered") | |
77fa1d54 UB |
1528 | (and (match_test "TARGET_AVX") |
1529 | (match_code "ge,gt,uneq,unle,unlt,ltgt")))) | |
95879c72 | 1530 | |
04e1d06b MM |
1531 | (define_predicate "ix86_comparison_int_operator" |
1532 | (match_code "ne,eq,ge,gt,le,lt")) | |
1533 | ||
1534 | (define_predicate "ix86_comparison_uns_operator" | |
1535 | (match_code "ne,eq,geu,gtu,leu,ltu")) | |
1536 | ||
33ee5810 UB |
1537 | (define_predicate "bt_comparison_operator" |
1538 | (match_code "ne,eq")) | |
1539 | ||
8ea03e90 UB |
1540 | (define_predicate "shr_comparison_operator" |
1541 | (match_code "gtu,leu")) | |
1542 | ||
7c287930 UB |
1543 | (define_predicate "add_comparison_operator" |
1544 | (match_code "geu,ltu")) | |
1545 | ||
19ed9d7b | 1546 | ;; Return true if OP is a valid comparison operator in valid mode. |
8fe75e43 RH |
1547 | (define_predicate "ix86_comparison_operator" |
1548 | (match_operand 0 "comparison_operator") | |
1549 | { | |
ef4bddc2 | 1550 | machine_mode inmode = GET_MODE (XEXP (op, 0)); |
8fe75e43 RH |
1551 | enum rtx_code code = GET_CODE (op); |
1552 | ||
3f563e0b | 1553 | if (inmode == CCFPmode) |
0948ccb2 PB |
1554 | return ix86_trivial_fp_comparison_operator (op, mode); |
1555 | ||
8fe75e43 RH |
1556 | switch (code) |
1557 | { | |
1558 | case EQ: case NE: | |
fe944402 UB |
1559 | if (inmode == CCGZmode) |
1560 | return false; | |
19ed9d7b | 1561 | return true; |
fe944402 | 1562 | case GE: case LT: |
8fe75e43 | 1563 | if (inmode == CCmode || inmode == CCGCmode |
fe944402 | 1564 | || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode) |
19ed9d7b UB |
1565 | return true; |
1566 | return false; | |
fe944402 | 1567 | case GEU: case LTU: |
d03ca8a6 | 1568 | if (inmode == CCCmode || inmode == CCGZmode) |
fe944402 UB |
1569 | return true; |
1570 | /* FALLTHRU */ | |
1571 | case GTU: case LEU: | |
d03ca8a6 | 1572 | if (inmode == CCmode) |
19ed9d7b UB |
1573 | return true; |
1574 | return false; | |
d39d658d | 1575 | case ORDERED: case UNORDERED: |
8fe75e43 | 1576 | if (inmode == CCmode) |
19ed9d7b UB |
1577 | return true; |
1578 | return false; | |
8fe75e43 RH |
1579 | case GT: case LE: |
1580 | if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode) | |
19ed9d7b UB |
1581 | return true; |
1582 | return false; | |
8fe75e43 | 1583 | default: |
19ed9d7b | 1584 | return false; |
8fe75e43 RH |
1585 | } |
1586 | }) | |
1587 | ||
19ed9d7b UB |
1588 | ;; Return true if OP is a valid comparison operator |
1589 | ;; testing carry flag to be set. | |
8fe75e43 | 1590 | (define_predicate "ix86_carry_flag_operator" |
d03ca8a6 | 1591 | (match_code "ltu,unlt") |
8fe75e43 | 1592 | { |
ef4bddc2 | 1593 | machine_mode inmode = GET_MODE (XEXP (op, 0)); |
8fe75e43 RH |
1594 | enum rtx_code code = GET_CODE (op); |
1595 | ||
3f563e0b | 1596 | if (inmode == CCFPmode) |
d03ca8a6 UB |
1597 | code = ix86_fp_compare_code_to_integer (code); |
1598 | else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode) | |
19ed9d7b | 1599 | return false; |
8fe75e43 RH |
1600 | |
1601 | return code == LTU; | |
1602 | }) | |
1603 | ||
c111f606 UB |
1604 | ;; Return true if OP is a valid comparison operator |
1605 | ;; testing carry flag to be unset. | |
1606 | (define_predicate "ix86_carry_flag_unset_operator" | |
1607 | (match_code "geu,ge") | |
1608 | { | |
1609 | machine_mode inmode = GET_MODE (XEXP (op, 0)); | |
1610 | enum rtx_code code = GET_CODE (op); | |
1611 | ||
1612 | if (inmode == CCFPmode) | |
1613 | code = ix86_fp_compare_code_to_integer (code); | |
1614 | else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode) | |
1615 | return false; | |
1616 | ||
1617 | return code == GEU; | |
1618 | }) | |
1619 | ||
19ed9d7b | 1620 | ;; Return true if this comparison only requires testing one flag bit. |
0948ccb2 PB |
1621 | (define_predicate "ix86_trivial_fp_comparison_operator" |
1622 | (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")) | |
1623 | ||
19ed9d7b | 1624 | ;; Return true if we know how to do this comparison. Others require |
0948ccb2 PB |
1625 | ;; testing more than one flag bit, and we let the generic middle-end |
1626 | ;; code do that. | |
1627 | (define_predicate "ix86_fp_comparison_operator" | |
1628 | (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op)) | |
1629 | == IX86_FPCMP_ARITH") | |
1630 | (match_operand 0 "comparison_operator") | |
1631 | (match_operand 0 "ix86_trivial_fp_comparison_operator"))) | |
1632 | ||
4afbebcd RS |
1633 | ;; Return true if we can perform this comparison on TImode operands. |
1634 | (define_predicate "ix86_timode_comparison_operator" | |
1635 | (if_then_else (match_test "TARGET_64BIT") | |
1636 | (match_operand 0 "ordered_comparison_operator") | |
1637 | (match_operand 0 "bt_comparison_operator"))) | |
1638 | ||
1639 | ;; Return true if this is a valid second operand for a TImode comparison. | |
1640 | (define_predicate "ix86_timode_comparison_operand" | |
1641 | (if_then_else (match_test "TARGET_64BIT") | |
1642 | (match_operand 0 "x86_64_general_operand") | |
1643 | (match_operand 0 "nonimmediate_operand"))) | |
1644 | ||
8fe75e43 RH |
1645 | ;; Nearly general operand, but accept any const_double, since we wish |
1646 | ;; to be able to drop them into memory rather than have them get pulled | |
1647 | ;; into registers. | |
1648 | (define_predicate "cmp_fp_expander_operand" | |
1649 | (ior (match_code "const_double") | |
1650 | (match_operand 0 "general_operand"))) | |
1651 | ||
1652 | ;; Return true if this is a valid binary floating-point operation. | |
1653 | (define_predicate "binary_fp_operator" | |
1654 | (match_code "plus,minus,mult,div")) | |
1655 | ||
1656 | ;; Return true if this is a multiply operation. | |
1657 | (define_predicate "mult_operator" | |
1658 | (match_code "mult")) | |
1659 | ||
1660 | ;; Return true if this is a division operation. | |
1661 | (define_predicate "div_operator" | |
1662 | (match_code "div")) | |
1663 | ||
f1b13064 JJ |
1664 | ;; Return true if this is a and, ior or xor operation. |
1665 | (define_predicate "logic_operator" | |
1666 | (match_code "and,ior,xor")) | |
1667 | ||
3f831b7d JJ |
1668 | ;; Return true if this is a plus, minus, and, ior or xor operation. |
1669 | (define_predicate "plusminuslogic_operator" | |
1670 | (match_code "plus,minus,and,ior,xor")) | |
1671 | ||
8fe75e43 RH |
1672 | ;; Return true for ARITHMETIC_P. |
1673 | (define_predicate "arith_or_logical_operator" | |
513618db RH |
1674 | (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div, |
1675 | mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert")) | |
8fe75e43 | 1676 | |
bab64f23 PB |
1677 | ;; Return true for COMMUTATIVE_P. |
1678 | (define_predicate "commutative_operator" | |
1679 | (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax")) | |
1680 | ||
19ed9d7b | 1681 | ;; Return true if OP is a binary operator that can be promoted to wider mode. |
8fe75e43 | 1682 | (define_predicate "promotable_binary_operator" |
67266ebb | 1683 | (ior (match_code "plus,minus,and,ior,xor,ashift") |
8fe75e43 | 1684 | (and (match_code "mult") |
a646aded | 1685 | (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL")))) |
8fe75e43 | 1686 | |
25da5dc7 RH |
1687 | (define_predicate "compare_operator" |
1688 | (match_code "compare")) | |
7cacf53e | 1689 | |
272484da UB |
1690 | (define_predicate "extract_operator" |
1691 | (match_code "zero_extract,sign_extract")) | |
1692 | ||
f913cc2a UB |
1693 | ;; Return true if OP is a memory operand, aligned to |
1694 | ;; less than its natural alignment. | |
66e1ecfe L |
1695 | (define_predicate "misaligned_operand" |
1696 | (and (match_code "mem") | |
f913cc2a | 1697 | (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)"))) |
95879c72 | 1698 | |
94de7e22 | 1699 | ;; Return true if OP is a parallel for an mov{d,q,dqa,ps,pd} vec_select, |
1700 | ;; where one of the two operands of the vec_concat is const0_operand. | |
1701 | (define_predicate "movq_parallel" | |
1702 | (match_code "parallel") | |
1703 | { | |
1704 | unsigned nelt = XVECLEN (op, 0); | |
1705 | unsigned nelt2 = nelt >> 1; | |
1706 | unsigned i; | |
1707 | ||
1708 | if (nelt < 2) | |
1709 | return false; | |
1710 | ||
1711 | /* Validate that all of the elements are constants, | |
1712 | lower halves of permute are lower halves of the first operand, | |
1713 | upper halves of permute come from any of the second operand. */ | |
1714 | for (i = 0; i < nelt; ++i) | |
1715 | { | |
1716 | rtx er = XVECEXP (op, 0, i); | |
1717 | unsigned HOST_WIDE_INT ei; | |
1718 | ||
1719 | if (!CONST_INT_P (er)) | |
d6345481 | 1720 | return false; |
94de7e22 | 1721 | ei = INTVAL (er); |
1722 | if (i < nelt2 && ei != i) | |
d6345481 | 1723 | return false; |
94de7e22 | 1724 | if (i >= nelt2 && (ei < nelt || ei >= nelt << 1)) |
d6345481 | 1725 | return false; |
94de7e22 | 1726 | } |
1727 | ||
d6345481 | 1728 | return true; |
94de7e22 | 1729 | }) |
1730 | ||
19ed9d7b | 1731 | ;; Return true if OP is a vzeroall operation, known to be a PARALLEL. |
95879c72 L |
1732 | (define_predicate "vzeroall_operation" |
1733 | (match_code "parallel") | |
1734 | { | |
85b1d1bd | 1735 | unsigned i, nregs = TARGET_64BIT ? 16 : 8; |
95879c72 | 1736 | |
85b1d1bd | 1737 | if ((unsigned) XVECLEN (op, 0) != 1 + nregs) |
19ed9d7b | 1738 | return false; |
95879c72 | 1739 | |
85b1d1bd UB |
1740 | for (i = 0; i < nregs; i++) |
1741 | { | |
1742 | rtx elt = XVECEXP (op, 0, i+1); | |
1743 | ||
1744 | if (GET_CODE (elt) != SET | |
1745 | || GET_CODE (SET_DEST (elt)) != REG | |
1746 | || GET_MODE (SET_DEST (elt)) != V8SImode | |
02469d3a | 1747 | || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i) |
85b1d1bd | 1748 | || SET_SRC (elt) != CONST0_RTX (V8SImode)) |
19ed9d7b | 1749 | return false; |
85b1d1bd | 1750 | } |
19ed9d7b | 1751 | return true; |
85b1d1bd UB |
1752 | }) |
1753 | ||
b38ab29f UB |
1754 | ;; return true if OP is a vzeroall pattern. |
1755 | (define_predicate "vzeroall_pattern" | |
1756 | (and (match_code "parallel") | |
1757 | (match_code "unspec_volatile" "a") | |
1758 | (match_test "XINT (XVECEXP (op, 0, 0), 1) == UNSPECV_VZEROALL"))) | |
1759 | ||
1760 | ;; return true if OP is a vzeroupper pattern. | |
1761 | (define_predicate "vzeroupper_pattern" | |
69811448 | 1762 | (and (match_code "parallel") |
9a90b311 | 1763 | (match_code "unspec" "b") |
1764 | (match_test "XINT (XVECEXP (op, 0, 1), 1) == UNSPEC_CALLEE_ABI") | |
1765 | (match_test "INTVAL (XVECEXP (XVECEXP (op, 0, 1), 0, 0)) == ABI_VZEROUPPER"))) | |
ff97910d | 1766 | |
7121e32b UB |
1767 | ;; Return true if OP is an addsub vec_merge operation |
1768 | (define_predicate "addsub_vm_operator" | |
1769 | (match_code "vec_merge") | |
1770 | { | |
1771 | rtx op0, op1; | |
1772 | int swapped; | |
1773 | HOST_WIDE_INT mask; | |
1774 | int nunits, elt; | |
1775 | ||
1776 | op0 = XEXP (op, 0); | |
1777 | op1 = XEXP (op, 1); | |
1778 | ||
1779 | /* Sanity check. */ | |
1780 | if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS) | |
1781 | swapped = 0; | |
1782 | else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS) | |
1783 | swapped = 1; | |
1784 | else | |
1785 | gcc_unreachable (); | |
1786 | ||
1787 | mask = INTVAL (XEXP (op, 2)); | |
1788 | nunits = GET_MODE_NUNITS (mode); | |
1789 | ||
1790 | for (elt = 0; elt < nunits; elt++) | |
1791 | { | |
1792 | /* bit clear: take from op0, set: take from op1 */ | |
1793 | int bit = !(mask & (HOST_WIDE_INT_1U << elt)); | |
1794 | ||
1795 | if (bit != ((elt & 1) ^ swapped)) | |
1796 | return false; | |
1797 | } | |
1798 | ||
1799 | return true; | |
1800 | }) | |
1801 | ||
1802 | ;; Return true if OP is an addsub vec_select/vec_concat operation | |
1803 | (define_predicate "addsub_vs_operator" | |
1804 | (and (match_code "vec_select") | |
1805 | (match_code "vec_concat" "0")) | |
1806 | { | |
1807 | rtx op0, op1; | |
1808 | bool swapped; | |
1809 | int nunits, elt; | |
1810 | ||
1811 | op0 = XEXP (XEXP (op, 0), 0); | |
1812 | op1 = XEXP (XEXP (op, 0), 1); | |
1813 | ||
1814 | /* Sanity check. */ | |
1815 | if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS) | |
1816 | swapped = false; | |
1817 | else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS) | |
1818 | swapped = true; | |
1819 | else | |
1820 | gcc_unreachable (); | |
1821 | ||
1822 | nunits = GET_MODE_NUNITS (mode); | |
1823 | if (XVECLEN (XEXP (op, 1), 0) != nunits) | |
1824 | return false; | |
1825 | ||
1826 | /* We already checked that permutation is suitable for addsub, | |
1827 | so only look at the first element of the parallel. */ | |
1828 | elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0)); | |
5e04b3b6 | 1829 | |
7121e32b UB |
1830 | return elt == (swapped ? nunits : 0); |
1831 | }) | |
1832 | ||
1833 | ;; Return true if OP is a parallel for an addsub vec_select. | |
1834 | (define_predicate "addsub_vs_parallel" | |
1835 | (and (match_code "parallel") | |
1836 | (match_code "const_int" "a")) | |
1837 | { | |
1838 | int nelt = XVECLEN (op, 0); | |
1839 | int elt, i; | |
1840 | ||
1841 | if (nelt < 2) | |
1842 | return false; | |
1843 | ||
1844 | /* Check that the permutation is suitable for addsub. | |
1845 | For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */ | |
1846 | elt = INTVAL (XVECEXP (op, 0, 0)); | |
1847 | if (elt == 0) | |
1848 | { | |
1849 | for (i = 1; i < nelt; ++i) | |
1850 | if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt)) | |
1851 | return false; | |
1852 | } | |
1853 | else if (elt == nelt) | |
1854 | { | |
1855 | for (i = 1; i < nelt; ++i) | |
1856 | if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt)) | |
1857 | return false; | |
1858 | } | |
1859 | else | |
1860 | return false; | |
1861 | ||
1862 | return true; | |
1863 | }) | |
1864 | ||
faf2b6bc | 1865 | ;; Return true if OP is a constant pool in perm{w,d,b} which constains index |
1866 | ;; match pmov{dw,wb,qd}. | |
1867 | (define_predicate "permvar_truncate_operand" | |
1868 | (match_code "mem") | |
1869 | { | |
1870 | int nelt = GET_MODE_NUNITS (mode); | |
1871 | int perm[128]; | |
1872 | int id; | |
1873 | ||
1874 | if (!INTEGRAL_MODE_P (mode) || !VECTOR_MODE_P (mode)) | |
1875 | return false; | |
1876 | ||
1877 | if (nelt < 2) | |
1878 | return false; | |
1879 | ||
1880 | if (!ix86_extract_perm_from_pool_constant (&perm[0], op)) | |
1881 | return false; | |
1882 | ||
1883 | id = exact_log2 (nelt); | |
1884 | ||
1885 | /* Check that the permutation is suitable for pmovz{bw,wd,dq}. | |
1886 | For example V16HImode to V8HImode | |
1887 | { 0 2 4 6 8 10 12 14 * * * * * * * * }. */ | |
1888 | for (int i = 0; i != nelt / 2; i++) | |
1889 | if ((perm[i] & ((1 << id) - 1)) != i * 2) | |
1890 | return false; | |
1891 | ||
1892 | return true; | |
1893 | }) | |
1894 | ||
1895 | ;; Return true if OP is a constant pool in shufb which constains index | |
1896 | ;; match pmovdw. | |
1897 | (define_predicate "pshufb_truncv4siv4hi_operand" | |
1898 | (match_code "mem") | |
1899 | { | |
1900 | int perm[128]; | |
1901 | ||
1902 | if (mode != E_V16QImode) | |
1903 | return false; | |
1904 | ||
1905 | if (!ix86_extract_perm_from_pool_constant (&perm[0], op)) | |
1906 | return false; | |
1907 | ||
1908 | /* Check that the permutation is suitable for pmovdw. | |
1909 | For example V4SImode to V4HImode | |
1910 | { 0 1 4 5 8 9 12 13 * * * * * * * * }. | |
1911 | index = i % 2 + (i / 2) * 4. */ | |
1912 | for (int i = 0; i != 8; i++) | |
1913 | { | |
1914 | /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */ | |
1915 | if (perm[i] & 128) | |
1916 | return false; | |
1917 | ||
1918 | if ((perm[i] & 15) != ((i & 1) + (i & 0xFE) * 2)) | |
1919 | return false; | |
1920 | } | |
1921 | ||
1922 | return true; | |
1923 | }) | |
1924 | ||
1925 | ;; Return true if OP is a constant pool in shufb which constains index | |
1926 | ;; match pmovdw. | |
1927 | (define_predicate "pshufb_truncv8hiv8qi_operand" | |
1928 | (match_code "mem") | |
1929 | { | |
1930 | int perm[128]; | |
1931 | ||
1932 | if (mode != E_V16QImode) | |
1933 | return false; | |
1934 | ||
1935 | if (!ix86_extract_perm_from_pool_constant (&perm[0], op)) | |
1936 | return false; | |
1937 | ||
1938 | /* Check that the permutation is suitable for pmovwb. | |
1939 | For example V16QImode to V8QImode | |
1940 | { 0 2 4 6 8 10 12 14 * * * * * * * * }. | |
1941 | index = i % 2 + (i / 2) * 4. */ | |
1942 | for (int i = 0; i != 8; i++) | |
1943 | { | |
1944 | /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */ | |
1945 | if (perm[i] & 128) | |
1946 | return false; | |
1947 | ||
1948 | if ((perm[i] & 15) != i * 2) | |
1949 | return false; | |
1950 | } | |
1951 | ||
1952 | return true; | |
1953 | }) | |
1954 | ||
b668a06e JJ |
1955 | ;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select, |
1956 | ;; where one of the two operands of the vec_concat is const0_operand. | |
1957 | (define_predicate "pmovzx_parallel" | |
1958 | (and (match_code "parallel") | |
1959 | (match_code "const_int" "a")) | |
1960 | { | |
1961 | int nelt = XVECLEN (op, 0); | |
1962 | int elt, i; | |
1963 | ||
1964 | if (nelt < 2) | |
1965 | return false; | |
1966 | ||
1967 | /* Check that the permutation is suitable for pmovz{bw,wd,dq}. | |
1968 | For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */ | |
1969 | elt = INTVAL (XVECEXP (op, 0, 0)); | |
1970 | if (elt == 0) | |
1971 | { | |
1972 | for (i = 1; i < nelt; ++i) | |
1973 | if ((i & 1) != 0) | |
1974 | { | |
1975 | if (INTVAL (XVECEXP (op, 0, i)) < nelt) | |
1976 | return false; | |
1977 | } | |
1978 | else if (INTVAL (XVECEXP (op, 0, i)) != i / 2) | |
1979 | return false; | |
1980 | } | |
1981 | else | |
1982 | return false; | |
1983 | ||
1984 | return true; | |
1985 | }) | |
1986 | ||
8f9fea41 HJ |
1987 | ;; Return true if OP is a const vector with duplicate value. |
1988 | (define_predicate "const_vector_duplicate_operand" | |
1989 | (match_code "const_vector") | |
1990 | { | |
1991 | rtx elt = XVECEXP (op, 0, 0); | |
1992 | int i, nelt = XVECLEN (op, 0); | |
1993 | ||
1994 | for (i = 1; i < nelt; ++i) | |
1995 | if (!rtx_equal_p (elt, XVECEXP (op, 0, i))) | |
1996 | return false; | |
1997 | return true; | |
1998 | }) | |
1999 | ||
7121e32b | 2000 | ;; Return true if OP is a parallel for a vbroadcast permute. |
5e04b3b6 RH |
2001 | (define_predicate "avx_vbroadcast_operand" |
2002 | (and (match_code "parallel") | |
2003 | (match_code "const_int" "a")) | |
2004 | { | |
2005 | rtx elt = XVECEXP (op, 0, 0); | |
2006 | int i, nelt = XVECLEN (op, 0); | |
2007 | ||
2008 | /* Don't bother checking there are the right number of operands, | |
2009 | merely that they're all identical. */ | |
2010 | for (i = 1; i < nelt; ++i) | |
2011 | if (XVECEXP (op, 0, i) != elt) | |
2012 | return false; | |
2013 | return true; | |
2014 | }) | |
96d86115 | 2015 | |
edbb0749 ES |
2016 | ;; Return true if OP is a parallel for a palignr permute. |
2017 | (define_predicate "palignr_operand" | |
2018 | (and (match_code "parallel") | |
2019 | (match_code "const_int" "a")) | |
2020 | { | |
2021 | int elt = INTVAL (XVECEXP (op, 0, 0)); | |
2022 | int i, nelt = XVECLEN (op, 0); | |
2023 | ||
2024 | /* Check that an order in the permutation is suitable for palignr. | |
2025 | For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */ | |
2026 | for (i = 1; i < nelt; ++i) | |
2027 | if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt)) | |
2028 | return false; | |
2029 | return true; | |
2030 | }) | |
2031 | ||
96d86115 RH |
2032 | ;; Return true if OP is a proper third operand to vpblendw256. |
2033 | (define_predicate "avx2_pblendw_operand" | |
2034 | (match_code "const_int") | |
2035 | { | |
2036 | HOST_WIDE_INT val = INTVAL (op); | |
2037 | HOST_WIDE_INT low = val & 0xff; | |
524857ec | 2038 | return val == ((low << 8) | low); |
96d86115 | 2039 | }) |
baee1763 | 2040 | |
acf93f1e | 2041 | ;; Return true if OP is vector_operand or CONST_VECTOR. |
baee1763 | 2042 | (define_predicate "general_vector_operand" |
acf93f1e | 2043 | (ior (match_operand 0 "vector_operand") |
baee1763 | 2044 | (match_code "const_vector"))) |
0fe65b75 AI |
2045 | |
2046 | ;; Return true if OP is either -1 constant or stored in register. | |
2047 | (define_predicate "register_or_constm1_operand" | |
2048 | (ior (match_operand 0 "register_operand") | |
2049 | (and (match_code "const_int") | |
2050 | (match_test "op == constm1_rtx")))) | |
d6d4d770 DS |
2051 | |
2052 | ;; Return true if the vector ends with between 12 and 18 register saves using | |
2053 | ;; RAX as the base address. | |
2054 | (define_predicate "save_multiple" | |
2055 | (match_code "parallel") | |
2056 | { | |
2057 | const unsigned len = XVECLEN (op, 0); | |
2058 | unsigned i; | |
2059 | ||
2060 | /* Starting from end of vector, count register saves. */ | |
2061 | for (i = 0; i < len; ++i) | |
2062 | { | |
2063 | rtx src, dest, addr; | |
2064 | rtx e = XVECEXP (op, 0, len - 1 - i); | |
2065 | ||
2066 | if (GET_CODE (e) != SET) | |
2067 | break; | |
2068 | ||
2069 | src = SET_SRC (e); | |
2070 | dest = SET_DEST (e); | |
2071 | ||
2072 | if (!REG_P (src) || !MEM_P (dest)) | |
2073 | break; | |
2074 | ||
2075 | addr = XEXP (dest, 0); | |
2076 | ||
2077 | /* Good if dest address is in RAX. */ | |
2078 | if (REG_P (addr) && REGNO (addr) == AX_REG) | |
2079 | continue; | |
2080 | ||
2081 | /* Good if dest address is offset of RAX. */ | |
2082 | if (GET_CODE (addr) == PLUS | |
2083 | && REG_P (XEXP (addr, 0)) | |
2084 | && REGNO (XEXP (addr, 0)) == AX_REG) | |
2085 | continue; | |
2086 | ||
2087 | break; | |
2088 | } | |
2089 | return (i >= 12 && i <= 18); | |
2090 | }) | |
2091 | ||
2092 | ||
2093 | ;; Return true if the vector ends with between 12 and 18 register loads using | |
2094 | ;; RSI as the base address. | |
2095 | (define_predicate "restore_multiple" | |
2096 | (match_code "parallel") | |
2097 | { | |
2098 | const unsigned len = XVECLEN (op, 0); | |
2099 | unsigned i; | |
2100 | ||
2101 | /* Starting from end of vector, count register restores. */ | |
2102 | for (i = 0; i < len; ++i) | |
2103 | { | |
2104 | rtx src, dest, addr; | |
2105 | rtx e = XVECEXP (op, 0, len - 1 - i); | |
2106 | ||
2107 | if (GET_CODE (e) != SET) | |
2108 | break; | |
2109 | ||
2110 | src = SET_SRC (e); | |
2111 | dest = SET_DEST (e); | |
2112 | ||
2113 | if (!MEM_P (src) || !REG_P (dest)) | |
2114 | break; | |
2115 | ||
2116 | addr = XEXP (src, 0); | |
2117 | ||
2118 | /* Good if src address is in RSI. */ | |
2119 | if (REG_P (addr) && REGNO (addr) == SI_REG) | |
2120 | continue; | |
2121 | ||
2122 | /* Good if src address is offset of RSI. */ | |
2123 | if (GET_CODE (addr) == PLUS | |
2124 | && REG_P (XEXP (addr, 0)) | |
2125 | && REGNO (XEXP (addr, 0)) == SI_REG) | |
2126 | continue; | |
2127 | ||
2128 | break; | |
2129 | } | |
2130 | return (i >= 12 && i <= 18); | |
2131 | }) | |
632a2f50 | 2132 | |
2133 | ;; Keylocker specific predicates | |
2134 | (define_predicate "encodekey128_operation" | |
2135 | (match_code "parallel") | |
2136 | { | |
2137 | unsigned i; | |
2138 | rtx elt; | |
2139 | ||
2140 | if (XVECLEN (op, 0) != 8) | |
2141 | return false; | |
2142 | ||
2143 | for(i = 0; i < 3; i++) | |
2144 | { | |
2145 | elt = XVECEXP (op, 0, i + 1); | |
2146 | if (GET_CODE (elt) != SET | |
2147 | || GET_CODE (SET_DEST (elt)) != REG | |
2148 | || GET_MODE (SET_DEST (elt)) != V2DImode | |
2149 | || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i) | |
2150 | || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE | |
2151 | || GET_MODE (SET_SRC (elt)) != V2DImode | |
2152 | || XVECLEN(SET_SRC (elt), 0) != 1 | |
2153 | || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx) | |
2154 | return false; | |
2155 | } | |
2156 | ||
2157 | for(i = 4; i < 7; i++) | |
2158 | { | |
2159 | elt = XVECEXP (op, 0, i); | |
db288230 L |
2160 | if (GET_CODE (elt) != CLOBBER |
2161 | || GET_MODE (elt) != VOIDmode | |
2162 | || GET_CODE (XEXP (elt, 0)) != REG | |
2163 | || GET_MODE (XEXP (elt, 0)) != V2DImode | |
2164 | || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i)) | |
632a2f50 | 2165 | return false; |
2166 | } | |
2167 | ||
2168 | elt = XVECEXP (op, 0, 7); | |
2169 | if (GET_CODE (elt) != CLOBBER | |
2170 | || GET_MODE (elt) != VOIDmode | |
2171 | || GET_CODE (XEXP (elt, 0)) != REG | |
2172 | || GET_MODE (XEXP (elt, 0)) != CCmode | |
2173 | || REGNO (XEXP (elt, 0)) != FLAGS_REG) | |
2174 | return false; | |
2175 | return true; | |
2176 | }) | |
2177 | ||
2178 | (define_predicate "encodekey256_operation" | |
2179 | (match_code "parallel") | |
2180 | { | |
2181 | unsigned i; | |
2182 | rtx elt; | |
2183 | ||
2184 | if (XVECLEN (op, 0) != 9) | |
2185 | return false; | |
2186 | ||
2187 | elt = SET_SRC (XVECEXP (op, 0, 0)); | |
2188 | elt = XVECEXP (elt, 0, 2); | |
2189 | if (!REG_P (elt) | |
2190 | || REGNO(elt) != GET_SSE_REGNO (1)) | |
2191 | return false; | |
2192 | ||
2193 | for(i = 0; i < 4; i++) | |
2194 | { | |
2195 | elt = XVECEXP (op, 0, i + 1); | |
2196 | if (GET_CODE (elt) != SET | |
2197 | || GET_CODE (SET_DEST (elt)) != REG | |
2198 | || GET_MODE (SET_DEST (elt)) != V2DImode | |
2199 | || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i) | |
2200 | || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE | |
2201 | || GET_MODE (SET_SRC (elt)) != V2DImode | |
2202 | || XVECLEN(SET_SRC (elt), 0) != 1 | |
2203 | || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx) | |
2204 | return false; | |
2205 | } | |
2206 | ||
2207 | for(i = 4; i < 7; i++) | |
2208 | { | |
2209 | elt = XVECEXP (op, 0, i + 1); | |
db288230 L |
2210 | if (GET_CODE (elt) != CLOBBER |
2211 | || GET_MODE (elt) != VOIDmode | |
2212 | || GET_CODE (XEXP (elt, 0)) != REG | |
2213 | || GET_MODE (XEXP (elt, 0)) != V2DImode | |
2214 | || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i)) | |
632a2f50 | 2215 | return false; |
2216 | } | |
2217 | ||
2218 | elt = XVECEXP (op, 0, 8); | |
2219 | if (GET_CODE (elt) != CLOBBER | |
2220 | || GET_MODE (elt) != VOIDmode | |
2221 | || GET_CODE (XEXP (elt, 0)) != REG | |
2222 | || GET_MODE (XEXP (elt, 0)) != CCmode | |
2223 | || REGNO (XEXP (elt, 0)) != FLAGS_REG) | |
2224 | return false; | |
2225 | return true; | |
2226 | }) | |
2227 | ||
2228 | ||
2229 | (define_predicate "aeswidekl_operation" | |
2230 | (match_code "parallel") | |
2231 | { | |
2232 | unsigned i; | |
2233 | rtx elt; | |
2234 | ||
2235 | for (i = 0; i < 8; i++) | |
2236 | { | |
2237 | elt = XVECEXP (op, 0, i + 1); | |
2238 | if (GET_CODE (elt) != SET | |
2239 | || GET_CODE (SET_DEST (elt)) != REG | |
2240 | || GET_MODE (SET_DEST (elt)) != V2DImode | |
2241 | || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i) | |
2242 | || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE | |
2243 | || GET_MODE (SET_SRC (elt)) != V2DImode | |
2244 | || XVECLEN (SET_SRC (elt), 0) != 1 | |
cc477955 | 2245 | || !REG_P (XVECEXP (SET_SRC (elt), 0, 0)) |
632a2f50 | 2246 | || REGNO (XVECEXP (SET_SRC (elt), 0, 0)) != GET_SSE_REGNO (i)) |
2247 | return false; | |
2248 | } | |
2249 | return true; | |
2250 | }) |