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ba8ab355 | 1 | /* Subroutines used for code generation on intel 80960. |
c2749e2d RH |
2 | Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999 |
3 | Free Software Foundation, Inc. | |
ba8ab355 JW |
4 | Contributed by Steven McGeady, Intel Corp. |
5 | Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson | |
6 | Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. | |
7 | ||
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
5b1a918b RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ba8ab355 | 24 | |
ba8ab355 | 25 | #include "config.h" |
c5c76735 | 26 | #include "system.h" |
ba8ab355 JW |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
33 | #include "insn-flags.h" | |
34 | #include "output.h" | |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "tree.h" | |
38 | #include "insn-codes.h" | |
ba8ab355 | 39 | #include "expr.h" |
5bcff23f | 40 | #include "except.h" |
ba8ab355 JW |
41 | #include "function.h" |
42 | #include "recog.h" | |
43 | #include <math.h> | |
44 | ||
45 | /* Save the operands last given to a compare for use when we | |
46 | generate a scc or bcc insn. */ | |
47 | ||
48 | rtx i960_compare_op0, i960_compare_op1; | |
49 | ||
50 | /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS | |
51 | macro in i960.h. */ | |
52 | ||
53 | static int i960_maxbitalignment; | |
54 | static int i960_last_maxbitalignment; | |
55 | ||
56 | /* Used to implement switching between MEM and ALU insn types, for better | |
57 | C series performance. */ | |
58 | ||
59 | enum insn_types i960_last_insn_type; | |
60 | ||
ba8ab355 JW |
61 | /* The leaf-procedure return register. Set only if this is a leaf routine. */ |
62 | ||
63 | static int i960_leaf_ret_reg; | |
64 | ||
65 | /* True if replacing tail calls with jumps is OK. */ | |
66 | ||
67 | static int tail_call_ok; | |
68 | ||
69 | /* A string containing a list of insns to emit in the epilogue so as to | |
70 | restore all registers saved by the prologue. Created by the prologue | |
71 | code as it saves registers away. */ | |
72 | ||
73 | char epilogue_string[1000]; | |
74 | ||
75 | /* A unique number (per function) for return labels. */ | |
76 | ||
77 | static int ret_label = 0; | |
78 | ||
c25d3f20 JW |
79 | /* This is true if FNDECL is either a varargs or a stdarg function. |
80 | This is used to help identify functions that use an argument block. */ | |
81 | ||
82 | #define VARARGS_STDARG_FUNCTION(FNDECL) \ | |
83 | ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \ | |
84 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \ | |
85 | || current_function_varargs) | |
86 | ||
ba8ab355 JW |
87 | /* Handle pragmas for compatibility with Intel's compilers. */ |
88 | ||
89 | /* ??? This is incomplete, since it does not handle all pragmas that the | |
c9040e2c | 90 | intel compilers understand. */ |
ba8ab355 | 91 | |
05a81fe5 | 92 | int |
67988bd2 NC |
93 | process_pragma (p_getc, p_ungetc, pname) |
94 | int (* p_getc) PROTO ((void)); | |
95 | void (* p_ungetc) PROTO ((int)); | |
96 | char * pname; | |
ba8ab355 | 97 | { |
ba8ab355 | 98 | int i; |
119d0c36 | 99 | register int c; |
67988bd2 NC |
100 | char buf[20]; |
101 | char *s = buf; | |
102 | int align; | |
ba8ab355 | 103 | |
67988bd2 NC |
104 | /* Should be pragma 'far' or equivalent for callx/balx here. */ |
105 | if (strcmp (pname, "align") != 0) | |
119d0c36 | 106 | return 0; |
67988bd2 NC |
107 | |
108 | do | |
109 | { | |
110 | c = p_getc (); | |
111 | } | |
112 | while (c == ' ' || c == '\t'); | |
ba8ab355 | 113 | |
67988bd2 NC |
114 | if (c == '(') |
115 | c = p_getc (); | |
116 | ||
117 | while (c >= '0' && c <= '9') | |
c9040e2c | 118 | { |
67988bd2 NC |
119 | if (s < buf + sizeof buf - 1) |
120 | *s++ = c; | |
121 | c = p_getc (); | |
c9040e2c | 122 | } |
67988bd2 NC |
123 | |
124 | *s = '\0'; | |
ba8ab355 | 125 | |
67988bd2 NC |
126 | /* We had to read a non-numerical character to get out of the |
127 | while loop---often a newline. So, we have to put it back to | |
128 | make sure we continue to parse everything properly. */ | |
129 | ||
130 | p_ungetc (c); | |
131 | ||
132 | align = atoi (buf); | |
c9040e2c | 133 | |
67988bd2 NC |
134 | switch (align) |
135 | { | |
136 | case 0: | |
137 | /* Return to last alignment. */ | |
138 | align = i960_last_maxbitalignment / 8; | |
139 | /* Fall through. */ | |
140 | case 16: | |
141 | case 8: | |
142 | case 4: | |
143 | case 2: | |
144 | case 1: | |
145 | i960_last_maxbitalignment = i960_maxbitalignment; | |
146 | i960_maxbitalignment = align * 8; | |
147 | break; | |
148 | ||
149 | default: | |
150 | /* Silently ignore bad values. */ | |
151 | break; | |
152 | } | |
153 | ||
154 | /* NOTE: ic960 R3.0 pragma align definition: | |
155 | ||
156 | #pragma align [(size)] | (identifier=size[,...]) | |
157 | #pragma noalign [(identifier)[,...]] | |
158 | ||
159 | (all parens are optional) | |
160 | ||
161 | - size is [1,2,4,8,16] | |
162 | - noalign means size==1 | |
163 | - applies only to component elements of a struct (and union?) | |
164 | - identifier applies to structure tag (only) | |
165 | - missing identifier means next struct | |
166 | ||
167 | - alignment rules for bitfields need more investigation */ | |
168 | ||
169 | return 1; | |
ba8ab355 | 170 | } |
ba8ab355 JW |
171 | |
172 | /* Initialize variables before compiling any files. */ | |
173 | ||
174 | void | |
175 | i960_initialize () | |
176 | { | |
177 | if (TARGET_IC_COMPAT2_0) | |
178 | { | |
179 | i960_maxbitalignment = 8; | |
180 | i960_last_maxbitalignment = 128; | |
181 | } | |
182 | else | |
183 | { | |
184 | i960_maxbitalignment = 128; | |
185 | i960_last_maxbitalignment = 8; | |
186 | } | |
187 | } | |
188 | \f | |
189 | /* Return true if OP can be used as the source of an fp move insn. */ | |
190 | ||
191 | int | |
192 | fpmove_src_operand (op, mode) | |
193 | rtx op; | |
194 | enum machine_mode mode; | |
195 | { | |
196 | return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode)); | |
197 | } | |
198 | ||
199 | #if 0 | |
200 | /* Return true if OP is a register or zero. */ | |
201 | ||
202 | int | |
203 | reg_or_zero_operand (op, mode) | |
204 | rtx op; | |
205 | enum machine_mode mode; | |
206 | { | |
207 | return register_operand (op, mode) || op == const0_rtx; | |
208 | } | |
209 | #endif | |
210 | ||
211 | /* Return truth value of whether OP can be used as an operands in a three | |
212 | address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */ | |
213 | ||
214 | int | |
215 | arith_operand (op, mode) | |
216 | rtx op; | |
217 | enum machine_mode mode; | |
218 | { | |
219 | return (register_operand (op, mode) || literal (op, mode)); | |
220 | } | |
221 | ||
f20200f4 TG |
222 | /* Return truth value of whether OP can be used as an operands in a three |
223 | address logic insn, possibly complementing OP, of mode MODE. */ | |
224 | ||
225 | int | |
226 | logic_operand (op, mode) | |
227 | rtx op; | |
228 | enum machine_mode mode; | |
229 | { | |
230 | return (register_operand (op, mode) | |
231 | || (GET_CODE (op) == CONST_INT | |
232 | && INTVAL(op) >= -32 && INTVAL(op) < 32)); | |
233 | } | |
234 | ||
ba8ab355 JW |
235 | /* Return true if OP is a register or a valid floating point literal. */ |
236 | ||
237 | int | |
238 | fp_arith_operand (op, mode) | |
239 | rtx op; | |
240 | enum machine_mode mode; | |
241 | { | |
242 | return (register_operand (op, mode) || fp_literal (op, mode)); | |
243 | } | |
244 | ||
245 | /* Return true is OP is a register or a valid signed integer literal. */ | |
246 | ||
247 | int | |
248 | signed_arith_operand (op, mode) | |
249 | rtx op; | |
250 | enum machine_mode mode; | |
251 | { | |
252 | return (register_operand (op, mode) || signed_literal (op, mode)); | |
253 | } | |
254 | ||
255 | /* Return truth value of whether OP is a integer which fits the | |
256 | range constraining immediate operands in three-address insns. */ | |
257 | ||
258 | int | |
259 | literal (op, mode) | |
260 | rtx op; | |
261 | enum machine_mode mode; | |
262 | { | |
263 | return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32); | |
264 | } | |
265 | ||
266 | /* Return true if OP is a float constant of 1. */ | |
267 | ||
268 | int | |
269 | fp_literal_one (op, mode) | |
270 | rtx op; | |
271 | enum machine_mode mode; | |
272 | { | |
5cca7d17 | 273 | return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode)); |
ba8ab355 JW |
274 | } |
275 | ||
276 | /* Return true if OP is a float constant of 0. */ | |
277 | ||
278 | int | |
279 | fp_literal_zero (op, mode) | |
280 | rtx op; | |
281 | enum machine_mode mode; | |
282 | { | |
5cca7d17 | 283 | return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode)); |
ba8ab355 JW |
284 | } |
285 | ||
286 | /* Return true if OP is a valid floating point literal. */ | |
287 | ||
288 | int | |
289 | fp_literal(op, mode) | |
290 | rtx op; | |
291 | enum machine_mode mode; | |
292 | { | |
293 | return fp_literal_zero (op, mode) || fp_literal_one (op, mode); | |
294 | } | |
295 | ||
296 | /* Return true if OP is a valid signed immediate constant. */ | |
297 | ||
298 | int | |
299 | signed_literal(op, mode) | |
300 | rtx op; | |
301 | enum machine_mode mode; | |
302 | { | |
303 | return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32); | |
304 | } | |
305 | ||
306 | /* Return truth value of statement that OP is a symbolic memory | |
307 | operand of mode MODE. */ | |
308 | ||
309 | int | |
310 | symbolic_memory_operand (op, mode) | |
311 | rtx op; | |
312 | enum machine_mode mode; | |
313 | { | |
314 | if (GET_CODE (op) == SUBREG) | |
315 | op = SUBREG_REG (op); | |
316 | if (GET_CODE (op) != MEM) | |
317 | return 0; | |
318 | op = XEXP (op, 0); | |
319 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
320 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
321 | } | |
322 | ||
323 | /* Return truth value of whether OP is EQ or NE. */ | |
324 | ||
325 | int | |
326 | eq_or_neq (op, mode) | |
327 | rtx op; | |
328 | enum machine_mode mode; | |
329 | { | |
330 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
331 | } | |
332 | ||
333 | /* OP is an integer register or a constant. */ | |
334 | ||
335 | int | |
336 | arith32_operand (op, mode) | |
337 | rtx op; | |
338 | enum machine_mode mode; | |
339 | { | |
340 | if (register_operand (op, mode)) | |
341 | return 1; | |
342 | return (CONSTANT_P (op)); | |
343 | } | |
344 | ||
345 | /* Return true if OP is an integer constant which is a power of 2. */ | |
346 | ||
347 | int | |
348 | power2_operand (op,mode) | |
349 | rtx op; | |
350 | enum machine_mode mode; | |
351 | { | |
b47de04b | 352 | if (GET_CODE (op) != CONST_INT) |
ba8ab355 JW |
353 | return 0; |
354 | ||
355 | return exact_log2 (INTVAL (op)) >= 0; | |
356 | } | |
357 | ||
b47de04b JW |
358 | /* Return true if OP is an integer constant which is the complement of a |
359 | power of 2. */ | |
360 | ||
361 | int | |
362 | cmplpower2_operand (op, mode) | |
363 | rtx op; | |
364 | enum machine_mode mode; | |
365 | { | |
366 | if (GET_CODE (op) != CONST_INT) | |
367 | return 0; | |
368 | ||
369 | return exact_log2 (~ INTVAL (op)) >= 0; | |
370 | } | |
371 | ||
ba8ab355 JW |
372 | /* If VAL has only one bit set, return the index of that bit. Otherwise |
373 | return -1. */ | |
374 | ||
375 | int | |
376 | bitpos (val) | |
377 | unsigned int val; | |
378 | { | |
379 | register int i; | |
380 | ||
381 | for (i = 0; val != 0; i++, val >>= 1) | |
382 | { | |
383 | if (val & 1) | |
384 | { | |
385 | if (val != 1) | |
386 | return -1; | |
387 | return i; | |
388 | } | |
389 | } | |
390 | return -1; | |
391 | } | |
392 | ||
393 | /* Return non-zero if OP is a mask, i.e. all one bits are consecutive. | |
394 | The return value indicates how many consecutive non-zero bits exist | |
395 | if this is a mask. This is the same as the next function, except that | |
396 | it does not indicate what the start and stop bit positions are. */ | |
397 | ||
398 | int | |
399 | is_mask (val) | |
400 | unsigned int val; | |
401 | { | |
402 | register int start, end, i; | |
403 | ||
404 | start = -1; | |
405 | for (i = 0; val != 0; val >>= 1, i++) | |
406 | { | |
407 | if (val & 1) | |
408 | { | |
409 | if (start < 0) | |
410 | start = i; | |
411 | ||
412 | end = i; | |
413 | continue; | |
414 | } | |
415 | /* Still looking for the first bit. */ | |
416 | if (start < 0) | |
417 | continue; | |
418 | ||
419 | /* We've seen the start of a bit sequence, and now a zero. There | |
420 | must be more one bits, otherwise we would have exited the loop. | |
421 | Therefore, it is not a mask. */ | |
422 | if (val) | |
423 | return 0; | |
424 | } | |
425 | ||
426 | /* The bit string has ones from START to END bit positions only. */ | |
427 | return end - start + 1; | |
428 | } | |
429 | ||
430 | /* If VAL is a mask, then return nonzero, with S set to the starting bit | |
431 | position and E set to the ending bit position of the mask. The return | |
432 | value indicates how many consecutive bits exist in the mask. This is | |
433 | the same as the previous function, except that it also indicates the | |
434 | start and end bit positions of the mask. */ | |
435 | ||
436 | int | |
437 | bitstr (val, s, e) | |
438 | unsigned int val; | |
439 | int *s, *e; | |
440 | { | |
441 | register int start, end, i; | |
442 | ||
443 | start = -1; | |
444 | end = -1; | |
445 | for (i = 0; val != 0; val >>= 1, i++) | |
446 | { | |
447 | if (val & 1) | |
448 | { | |
449 | if (start < 0) | |
450 | start = i; | |
451 | ||
452 | end = i; | |
453 | continue; | |
454 | } | |
455 | ||
456 | /* Still looking for the first bit. */ | |
457 | if (start < 0) | |
458 | continue; | |
459 | ||
460 | /* We've seen the start of a bit sequence, and now a zero. There | |
461 | must be more one bits, otherwise we would have exited the loop. | |
462 | Therefor, it is not a mask. */ | |
463 | if (val) | |
464 | { | |
465 | start = -1; | |
466 | end = -1; | |
467 | break; | |
468 | } | |
469 | } | |
470 | ||
471 | /* The bit string has ones from START to END bit positions only. */ | |
472 | *s = start; | |
473 | *e = end; | |
474 | return ((start < 0) ? 0 : end - start + 1); | |
475 | } | |
476 | \f | |
477 | /* Return the machine mode to use for a comparison. */ | |
478 | ||
479 | enum machine_mode | |
480 | select_cc_mode (op, x) | |
481 | RTX_CODE op; | |
482 | rtx x; | |
483 | { | |
484 | if (op == GTU || op == LTU || op == GEU || op == LEU) | |
485 | return CC_UNSmode; | |
486 | return CCmode; | |
487 | } | |
488 | ||
489 | /* X and Y are two things to compare using CODE. Emit the compare insn and | |
490 | return the rtx for register 36 in the proper mode. */ | |
491 | ||
492 | rtx | |
493 | gen_compare_reg (code, x, y) | |
494 | enum rtx_code code; | |
495 | rtx x, y; | |
496 | { | |
497 | rtx cc_reg; | |
679655e6 | 498 | enum machine_mode ccmode = SELECT_CC_MODE (code, x, y); |
ba8ab355 JW |
499 | enum machine_mode mode |
500 | = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x); | |
501 | ||
502 | if (mode == SImode) | |
503 | { | |
504 | if (! arith_operand (x, mode)) | |
505 | x = force_reg (SImode, x); | |
506 | if (! arith_operand (y, mode)) | |
507 | y = force_reg (SImode, y); | |
508 | } | |
509 | ||
c5c76735 JL |
510 | cc_reg = gen_rtx_REG (ccmode, 36); |
511 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, | |
512 | gen_rtx_COMPARE (ccmode, x, y))); | |
ba8ab355 JW |
513 | |
514 | return cc_reg; | |
515 | } | |
516 | ||
517 | /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2, | |
518 | REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar | |
519 | are 4. Indexed addresses are cost 6. */ | |
520 | ||
521 | /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */ | |
522 | ||
523 | int | |
524 | i960_address_cost (x) | |
525 | rtx x; | |
526 | { | |
527 | #if 0 | |
528 | /* Handled before calling here. */ | |
529 | if (GET_CODE (x) == REG) | |
530 | return 1; | |
531 | #endif | |
3410b2f3 AM |
532 | /* This is a MEMA operand -- it's free. */ |
533 | if (GET_CODE (x) == CONST_INT | |
534 | && INTVAL (x) >= 0 | |
535 | && INTVAL (x) < 4096) | |
536 | return 0; | |
537 | ||
ba8ab355 JW |
538 | if (GET_CODE (x) == PLUS) |
539 | { | |
540 | rtx base = XEXP (x, 0); | |
541 | rtx offset = XEXP (x, 1); | |
542 | ||
543 | if (GET_CODE (base) == SUBREG) | |
544 | base = SUBREG_REG (base); | |
545 | if (GET_CODE (offset) == SUBREG) | |
546 | offset = SUBREG_REG (offset); | |
547 | ||
548 | if (GET_CODE (base) == REG) | |
549 | { | |
550 | if (GET_CODE (offset) == REG) | |
551 | return 2; | |
552 | if (GET_CODE (offset) == CONST_INT) | |
553 | { | |
554 | if ((unsigned)INTVAL (offset) < 2047) | |
555 | return 2; | |
556 | return 4; | |
557 | } | |
558 | if (CONSTANT_P (offset)) | |
559 | return 4; | |
560 | } | |
561 | if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT) | |
562 | return 6; | |
563 | ||
c0954bcd JW |
564 | /* This is an invalid address. The return value doesn't matter, but |
565 | for convenience we make this more expensive than anything else. */ | |
566 | return 12; | |
ba8ab355 JW |
567 | } |
568 | if (GET_CODE (x) == MULT) | |
569 | return 6; | |
570 | ||
571 | /* Symbol_refs and other unrecognized addresses are cost 4. */ | |
572 | return 4; | |
573 | } | |
574 | \f | |
575 | /* Emit insns to move operands[1] into operands[0]. | |
576 | ||
577 | Return 1 if we have written out everything that needs to be done to | |
578 | do the move. Otherwise, return 0 and the caller will emit the move | |
e4d26fc7 | 579 | normally. */ |
ba8ab355 JW |
580 | |
581 | int | |
582 | emit_move_sequence (operands, mode) | |
583 | rtx *operands; | |
584 | enum machine_mode mode; | |
585 | { | |
ba8ab355 | 586 | /* We can only store registers to memory. */ |
e4d26fc7 VM |
587 | |
588 | if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG | |
589 | && (operands[1] != const0_rtx || current_function_args_size | |
590 | || current_function_varargs || current_function_stdarg | |
591 | || rtx_equal_function_value_matters)) | |
592 | /* Here we use the same test as movsi+1 pattern -- see i960.md. */ | |
3a89bbcb RK |
593 | operands[1] = force_reg (mode, operands[1]); |
594 | ||
595 | /* Storing multi-word values in unaligned hard registers to memory may | |
596 | require a scratch since we have to store them a register at a time and | |
597 | adding 4 to the memory address may not yield a valid insn. */ | |
598 | /* ??? We don't always need the scratch, but that would complicate things. | |
599 | Maybe later. */ | |
e5e809f4 JL |
600 | /* ??? We must also handle stores to pseudos here, because the pseudo may be |
601 | replaced with a MEM later. This would be cleaner if we didn't have | |
602 | a separate pattern for unaligned DImode/TImode stores. */ | |
3a89bbcb | 603 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD |
e5e809f4 JL |
604 | && (GET_CODE (operands[0]) == MEM |
605 | || (GET_CODE (operands[0]) == REG | |
606 | && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) | |
3a89bbcb RK |
607 | && GET_CODE (operands[1]) == REG |
608 | && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER | |
609 | && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode)) | |
610 | { | |
c5c76735 JL |
611 | emit_insn (gen_rtx_PARALLEL |
612 | (VOIDmode, | |
613 | gen_rtvec (2, | |
614 | gen_rtx_SET (VOIDmode, operands[0], operands[1]), | |
615 | gen_rtx_CLOBBER (VOIDmode, | |
616 | gen_rtx_SCRATCH (Pmode))))); | |
3a89bbcb RK |
617 | return 1; |
618 | } | |
ba8ab355 JW |
619 | |
620 | return 0; | |
621 | } | |
3a89bbcb RK |
622 | |
623 | /* Output assembler to move a double word value. */ | |
624 | ||
625 | char * | |
626 | i960_output_move_double (dst, src) | |
627 | rtx dst, src; | |
628 | { | |
629 | rtx operands[5]; | |
630 | ||
631 | if (GET_CODE (dst) == REG | |
632 | && GET_CODE (src) == REG) | |
633 | { | |
634 | if ((REGNO (src) & 1) | |
635 | || (REGNO (dst) & 1)) | |
636 | { | |
637 | /* We normally copy the low-numbered register first. However, if | |
638 | the second source register is the same as the first destination | |
639 | register, we must copy in the opposite order. */ | |
640 | if (REGNO (src) + 1 == REGNO (dst)) | |
641 | return "mov %D1,%D0\n\tmov %1,%0"; | |
642 | else | |
643 | return "mov %1,%0\n\tmov %D1,%D0"; | |
644 | } | |
645 | else | |
646 | return "movl %1,%0"; | |
647 | } | |
648 | else if (GET_CODE (dst) == REG | |
649 | && GET_CODE (src) == CONST_INT | |
650 | && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I')) | |
651 | { | |
652 | if (REGNO (dst) & 1) | |
653 | return "mov %1,%0\n\tmov 0,%D0"; | |
654 | else | |
655 | return "movl %1,%0"; | |
656 | } | |
657 | else if (GET_CODE (dst) == REG | |
658 | && GET_CODE (src) == MEM) | |
659 | { | |
660 | if (REGNO (dst) & 1) | |
661 | { | |
662 | /* One can optimize a few cases here, but you have to be | |
663 | careful of clobbering registers used in the address and | |
664 | edge conditions. */ | |
665 | operands[0] = dst; | |
666 | operands[1] = src; | |
c5c76735 JL |
667 | operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 1); |
668 | operands[3] = gen_rtx_MEM (word_mode, operands[2]); | |
3a89bbcb RK |
669 | operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); |
670 | output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands); | |
671 | return ""; | |
672 | } | |
673 | else | |
674 | return "ldl %1,%0"; | |
675 | } | |
676 | else if (GET_CODE (dst) == MEM | |
677 | && GET_CODE (src) == REG) | |
678 | { | |
679 | if (REGNO (src) & 1) | |
680 | { | |
e4d26fc7 VM |
681 | operands[0] = dst; |
682 | operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD); | |
683 | if (! memory_address_p (word_mode, XEXP (operands[1], 0))) | |
684 | abort (); | |
685 | operands[2] = src; | |
686 | output_asm_insn ("st %2,%0\n\tst %D2,%1", operands); | |
687 | return ""; | |
3a89bbcb RK |
688 | } |
689 | return "stl %1,%0"; | |
690 | } | |
691 | else | |
692 | abort (); | |
693 | } | |
694 | ||
e4d26fc7 VM |
695 | /* Output assembler to move a double word zero. */ |
696 | ||
697 | char * | |
698 | i960_output_move_double_zero (dst) | |
699 | rtx dst; | |
700 | { | |
701 | rtx operands[2]; | |
702 | ||
703 | operands[0] = dst; | |
704 | { | |
705 | operands[1] = adj_offsettable_operand (dst, 4); | |
706 | output_asm_insn ("st g14,%0\n\tst g14,%1", operands); | |
707 | } | |
708 | return ""; | |
709 | } | |
710 | ||
3a89bbcb RK |
711 | /* Output assembler to move a quad word value. */ |
712 | ||
713 | char * | |
714 | i960_output_move_quad (dst, src) | |
715 | rtx dst, src; | |
716 | { | |
717 | rtx operands[7]; | |
718 | ||
719 | if (GET_CODE (dst) == REG | |
720 | && GET_CODE (src) == REG) | |
721 | { | |
722 | if ((REGNO (src) & 3) | |
723 | || (REGNO (dst) & 3)) | |
724 | { | |
725 | /* We normally copy starting with the low numbered register. | |
726 | However, if there is an overlap such that the first dest reg | |
727 | is <= the last source reg but not < the first source reg, we | |
728 | must copy in the opposite order. */ | |
729 | if (REGNO (dst) <= REGNO (src) + 3 | |
730 | && REGNO (dst) >= REGNO (src)) | |
731 | return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0"; | |
732 | else | |
733 | return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0"; | |
734 | } | |
735 | else | |
736 | return "movq %1,%0"; | |
737 | } | |
738 | else if (GET_CODE (dst) == REG | |
739 | && GET_CODE (src) == CONST_INT | |
740 | && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I')) | |
741 | { | |
742 | if (REGNO (dst) & 3) | |
743 | return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0"; | |
744 | else | |
745 | return "movq %1,%0"; | |
746 | } | |
747 | else if (GET_CODE (dst) == REG | |
748 | && GET_CODE (src) == MEM) | |
749 | { | |
750 | if (REGNO (dst) & 3) | |
751 | { | |
752 | /* One can optimize a few cases here, but you have to be | |
753 | careful of clobbering registers used in the address and | |
754 | edge conditions. */ | |
755 | operands[0] = dst; | |
756 | operands[1] = src; | |
c5c76735 JL |
757 | operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 3); |
758 | operands[3] = gen_rtx_MEM (word_mode, operands[2]); | |
3a89bbcb RK |
759 | operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); |
760 | operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD); | |
761 | operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD); | |
762 | output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands); | |
763 | return ""; | |
764 | } | |
765 | else | |
766 | return "ldq %1,%0"; | |
767 | } | |
768 | else if (GET_CODE (dst) == MEM | |
769 | && GET_CODE (src) == REG) | |
770 | { | |
771 | if (REGNO (src) & 3) | |
772 | { | |
e4d26fc7 VM |
773 | operands[0] = dst; |
774 | operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD); | |
775 | operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD); | |
776 | operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD); | |
777 | if (! memory_address_p (word_mode, XEXP (operands[3], 0))) | |
778 | abort (); | |
779 | operands[4] = src; | |
780 | output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands); | |
781 | return ""; | |
3a89bbcb RK |
782 | } |
783 | return "stq %1,%0"; | |
784 | } | |
785 | else | |
786 | abort (); | |
787 | } | |
e4d26fc7 VM |
788 | |
789 | /* Output assembler to move a quad word zero. */ | |
790 | ||
791 | char * | |
792 | i960_output_move_quad_zero (dst) | |
793 | rtx dst; | |
794 | { | |
795 | rtx operands[4]; | |
796 | ||
797 | operands[0] = dst; | |
798 | { | |
799 | operands[1] = adj_offsettable_operand (dst, 4); | |
800 | operands[2] = adj_offsettable_operand (dst, 8); | |
801 | operands[3] = adj_offsettable_operand (dst, 12); | |
802 | output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands); | |
803 | } | |
804 | return ""; | |
805 | } | |
806 | ||
ba8ab355 | 807 | \f |
37aba850 TG |
808 | /* Emit insns to load a constant to non-floating point registers. |
809 | Uses several strategies to try to use as few insns as possible. */ | |
ba8ab355 JW |
810 | |
811 | char * | |
812 | i960_output_ldconst (dst, src) | |
813 | register rtx dst, src; | |
814 | { | |
815 | register int rsrc1; | |
816 | register unsigned rsrc2; | |
817 | enum machine_mode mode = GET_MODE (dst); | |
818 | rtx operands[4]; | |
ba8ab355 JW |
819 | |
820 | operands[0] = operands[2] = dst; | |
821 | operands[1] = operands[3] = src; | |
822 | ||
823 | /* Anything that isn't a compile time constant, such as a SYMBOL_REF, | |
824 | must be a ldconst insn. */ | |
825 | ||
826 | if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE) | |
827 | { | |
828 | output_asm_insn ("ldconst %1,%0", operands); | |
829 | return ""; | |
830 | } | |
37aba850 TG |
831 | else if (mode == XFmode) |
832 | { | |
833 | REAL_VALUE_TYPE d; | |
834 | long value_long[3]; | |
835 | int i; | |
836 | ||
837 | if (fp_literal_zero (src, XFmode)) | |
838 | return "movt 0,%0"; | |
839 | ||
840 | REAL_VALUE_FROM_CONST_DOUBLE (d, src); | |
841 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long); | |
842 | ||
843 | output_asm_insn ("# ldconst %1,%0",operands); | |
844 | ||
845 | for (i = 0; i < 3; i++) | |
846 | { | |
c5c76735 | 847 | operands[0] = gen_rtx_REG (SImode, REGNO (dst) + i); |
37aba850 TG |
848 | operands[1] = GEN_INT (value_long[i]); |
849 | output_asm_insn (i960_output_ldconst (operands[0], operands[1]), | |
850 | operands); | |
851 | } | |
852 | ||
853 | return ""; | |
854 | } | |
ba8ab355 JW |
855 | else if (mode == DFmode) |
856 | { | |
857 | rtx first, second; | |
858 | ||
5cca7d17 JW |
859 | if (fp_literal_zero (src, DFmode)) |
860 | return "movl 0,%0"; | |
ba8ab355 | 861 | |
ba8ab355 JW |
862 | split_double (src, &first, &second); |
863 | ||
864 | output_asm_insn ("# ldconst %1,%0",operands); | |
865 | ||
c5c76735 | 866 | operands[0] = gen_rtx_REG (SImode, REGNO (dst)); |
ba8ab355 JW |
867 | operands[1] = first; |
868 | output_asm_insn (i960_output_ldconst (operands[0], operands[1]), | |
869 | operands); | |
c5c76735 | 870 | operands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1); |
ba8ab355 JW |
871 | operands[1] = second; |
872 | output_asm_insn (i960_output_ldconst (operands[0], operands[1]), | |
873 | operands); | |
874 | return ""; | |
ba8ab355 | 875 | } |
37aba850 TG |
876 | else if (mode == SFmode) |
877 | { | |
878 | REAL_VALUE_TYPE d; | |
879 | long value; | |
880 | ||
881 | REAL_VALUE_FROM_CONST_DOUBLE (d, src); | |
882 | REAL_VALUE_TO_TARGET_SINGLE (d, value); | |
883 | ||
884 | output_asm_insn ("# ldconst %1,%0",operands); | |
c5c76735 | 885 | operands[0] = gen_rtx_REG (SImode, REGNO (dst)); |
3a598fbe | 886 | operands[1] = GEN_INT (value); |
37aba850 TG |
887 | output_asm_insn (i960_output_ldconst (operands[0], operands[1]), |
888 | operands); | |
889 | return ""; | |
890 | } | |
ba8ab355 JW |
891 | else if (mode == TImode) |
892 | { | |
893 | /* ??? This is currently not handled at all. */ | |
894 | abort (); | |
895 | ||
896 | /* Note: lowest order word goes in lowest numbered reg. */ | |
897 | rsrc1 = INTVAL (src); | |
898 | if (rsrc1 >= 0 && rsrc1 < 32) | |
899 | return "movq %1,%0"; | |
900 | else | |
901 | output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands); | |
902 | /* Go pick up the low-order word. */ | |
903 | } | |
904 | else if (mode == DImode) | |
905 | { | |
518dd866 | 906 | rtx upperhalf, lowerhalf, xoperands[2]; |
ba8ab355 | 907 | |
ca01dc12 TG |
908 | if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT) |
909 | split_double (src, &lowerhalf, &upperhalf); | |
910 | ||
ba8ab355 JW |
911 | else |
912 | abort (); | |
913 | ||
914 | /* Note: lowest order word goes in lowest numbered reg. */ | |
915 | /* Numbers from 0 to 31 can be handled with a single insn. */ | |
916 | rsrc1 = INTVAL (lowerhalf); | |
917 | if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32) | |
918 | return "movl %1,%0"; | |
919 | ||
920 | /* Output the upper half with a recursive call. */ | |
c5c76735 | 921 | xoperands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1); |
518dd866 JW |
922 | xoperands[1] = upperhalf; |
923 | output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]), | |
924 | xoperands); | |
ba8ab355 JW |
925 | /* The lower word is emitted as normally. */ |
926 | } | |
ba8ab355 JW |
927 | else |
928 | { | |
929 | rsrc1 = INTVAL (src); | |
930 | if (mode == QImode) | |
931 | { | |
932 | if (rsrc1 > 0xff) | |
933 | rsrc1 &= 0xff; | |
934 | } | |
935 | else if (mode == HImode) | |
936 | { | |
937 | if (rsrc1 > 0xffff) | |
938 | rsrc1 &= 0xffff; | |
939 | } | |
940 | } | |
941 | ||
942 | if (rsrc1 >= 0) | |
943 | { | |
944 | /* ldconst 0..31,X -> mov 0..31,X */ | |
945 | if (rsrc1 < 32) | |
946 | { | |
947 | if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) | |
948 | return "lda %1,%0"; | |
949 | return "mov %1,%0"; | |
950 | } | |
951 | ||
952 | /* ldconst 32..63,X -> add 31,nn,X */ | |
953 | if (rsrc1 < 63) | |
954 | { | |
955 | if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) | |
956 | return "lda %1,%0"; | |
3a598fbe | 957 | operands[1] = GEN_INT (rsrc1 - 31); |
ba8ab355 JW |
958 | output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands); |
959 | return ""; | |
960 | } | |
961 | } | |
962 | else if (rsrc1 < 0) | |
963 | { | |
964 | /* ldconst -1..-31 -> sub 0,0..31,X */ | |
965 | if (rsrc1 >= -31) | |
966 | { | |
967 | /* return 'sub -(%1),0,%0' */ | |
3a598fbe | 968 | operands[1] = GEN_INT (- rsrc1); |
ba8ab355 JW |
969 | output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands); |
970 | return ""; | |
971 | } | |
972 | ||
973 | /* ldconst -32 -> not 31,X */ | |
974 | if (rsrc1 == -32) | |
975 | { | |
3a598fbe | 976 | operands[1] = GEN_INT (~rsrc1); |
ba8ab355 JW |
977 | output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands); |
978 | return ""; | |
979 | } | |
980 | } | |
981 | ||
982 | /* If const is a single bit. */ | |
983 | if (bitpos (rsrc1) >= 0) | |
984 | { | |
3a598fbe | 985 | operands[1] = GEN_INT (bitpos (rsrc1)); |
ba8ab355 JW |
986 | output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands); |
987 | return ""; | |
988 | } | |
989 | ||
990 | /* If const is a bit string of less than 6 bits (1..31 shifted). */ | |
991 | if (is_mask (rsrc1)) | |
992 | { | |
993 | int s, e; | |
994 | ||
995 | if (bitstr (rsrc1, &s, &e) < 6) | |
996 | { | |
997 | rsrc2 = ((unsigned int) rsrc1) >> s; | |
3a598fbe JL |
998 | operands[1] = GEN_INT (rsrc2); |
999 | operands[2] = GEN_INT (s); | |
ba8ab355 JW |
1000 | output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands); |
1001 | return ""; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /* Unimplemented cases: | |
1006 | const is in range 0..31 but rotated around end of word: | |
1007 | ror 31,3,g0 -> ldconst 0xe0000003,g0 | |
1008 | ||
1009 | and any 2 instruction cases that might be worthwhile */ | |
1010 | ||
1011 | output_asm_insn ("ldconst %1,%0", operands); | |
1012 | return ""; | |
1013 | } | |
1014 | ||
1015 | /* Determine if there is an opportunity for a bypass optimization. | |
2296cba3 | 1016 | Bypass succeeds on the 960K* if the destination of the previous |
ba8ab355 JW |
1017 | instruction is the second operand of the current instruction. |
1018 | Bypass always succeeds on the C*. | |
1019 | ||
1020 | Return 1 if the pattern should interchange the operands. | |
1021 | ||
1022 | CMPBR_FLAG is true if this is for a compare-and-branch insn. | |
1023 | OP1 and OP2 are the two source operands of a 3 operand insn. */ | |
1024 | ||
1025 | int | |
1026 | i960_bypass (insn, op1, op2, cmpbr_flag) | |
1027 | register rtx insn, op1, op2; | |
1028 | int cmpbr_flag; | |
1029 | { | |
1030 | register rtx prev_insn, prev_dest; | |
1031 | ||
1032 | if (TARGET_C_SERIES) | |
1033 | return 0; | |
1034 | ||
1035 | /* Can't do this if op1 isn't a register. */ | |
1036 | if (! REG_P (op1)) | |
1037 | return 0; | |
1038 | ||
1039 | /* Can't do this for a compare-and-branch if both ops aren't regs. */ | |
1040 | if (cmpbr_flag && ! REG_P (op2)) | |
1041 | return 0; | |
1042 | ||
1043 | prev_insn = prev_real_insn (insn); | |
1044 | ||
1045 | if (prev_insn && GET_CODE (prev_insn) == INSN | |
1046 | && GET_CODE (PATTERN (prev_insn)) == SET) | |
1047 | { | |
1048 | prev_dest = SET_DEST (PATTERN (prev_insn)); | |
1049 | if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1)) | |
1050 | || (GET_CODE (prev_dest) == SUBREG | |
1051 | && GET_CODE (SUBREG_REG (prev_dest)) == REG | |
1052 | && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1))) | |
1053 | return 1; | |
1054 | } | |
1055 | return 0; | |
1056 | } | |
1057 | \f | |
1058 | /* Output the code which declares the function name. This also handles | |
1059 | leaf routines, which have special requirements, and initializes some | |
1060 | global variables. */ | |
1061 | ||
1062 | void | |
1063 | i960_function_name_declare (file, name, fndecl) | |
1064 | FILE *file; | |
1065 | char *name; | |
1066 | tree fndecl; | |
1067 | { | |
1068 | register int i, j; | |
1069 | int leaf_proc_ok; | |
1070 | rtx insn; | |
1071 | ||
1072 | /* Increment global return label. */ | |
1073 | ||
1074 | ret_label++; | |
1075 | ||
1076 | /* Compute whether tail calls and leaf routine optimizations can be performed | |
1077 | for this function. */ | |
1078 | ||
1079 | if (TARGET_TAILCALL) | |
1080 | tail_call_ok = 1; | |
1081 | else | |
1082 | tail_call_ok = 0; | |
1083 | ||
1084 | if (TARGET_LEAFPROC) | |
1085 | leaf_proc_ok = 1; | |
1086 | else | |
1087 | leaf_proc_ok = 0; | |
1088 | ||
ddd5a7c1 | 1089 | /* Even if nobody uses extra parms, can't have leafproc or tail calls if |
ba8ab355 JW |
1090 | argblock, because argblock uses g14 implicitly. */ |
1091 | ||
c25d3f20 | 1092 | if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl)) |
ba8ab355 JW |
1093 | { |
1094 | tail_call_ok = 0; | |
1095 | leaf_proc_ok = 0; | |
1096 | } | |
1097 | ||
1098 | /* See if caller passes in an address to return value. */ | |
1099 | ||
1100 | if (aggregate_value_p (DECL_RESULT (fndecl))) | |
1101 | { | |
1102 | tail_call_ok = 0; | |
1103 | leaf_proc_ok = 0; | |
1104 | } | |
1105 | ||
1106 | /* Can not use tail calls or make this a leaf routine if there is a non | |
1107 | zero frame size. */ | |
1108 | ||
1109 | if (get_frame_size () != 0) | |
1110 | leaf_proc_ok = 0; | |
1111 | ||
1112 | /* I don't understand this condition, and do not think that it is correct. | |
1113 | Apparently this is just checking whether the frame pointer is used, and | |
1114 | we can't trust regs_ever_live[fp] since it is (almost?) always set. */ | |
1115 | ||
1116 | if (tail_call_ok) | |
1117 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1118 | if (GET_CODE (insn) == INSN | |
1119 | && reg_mentioned_p (frame_pointer_rtx, insn)) | |
1120 | { | |
1121 | tail_call_ok = 0; | |
1122 | break; | |
1123 | } | |
1124 | ||
1125 | /* Check for CALL insns. Can not be a leaf routine if there are any. */ | |
1126 | ||
1127 | if (leaf_proc_ok) | |
1128 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
1129 | if (GET_CODE (insn) == CALL_INSN) | |
1130 | { | |
1131 | leaf_proc_ok = 0; | |
1132 | break; | |
1133 | } | |
1134 | ||
1135 | /* Can not be a leaf routine if any non-call clobbered registers are | |
1136 | used in this function. */ | |
1137 | ||
1138 | if (leaf_proc_ok) | |
1139 | for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1140 | if (regs_ever_live[i] | |
1141 | && ((! call_used_regs[i]) || (i > 7 && i < 12))) | |
1142 | { | |
1143 | /* Global registers. */ | |
1144 | if (i < 16 && i > 7 && i != 13) | |
1145 | leaf_proc_ok = 0; | |
1146 | /* Local registers. */ | |
1147 | else if (i < 32) | |
1148 | leaf_proc_ok = 0; | |
1149 | } | |
1150 | ||
1151 | /* Now choose a leaf return register, if we can find one, and if it is | |
1152 | OK for this to be a leaf routine. */ | |
1153 | ||
1154 | i960_leaf_ret_reg = -1; | |
1155 | ||
1156 | if (optimize && leaf_proc_ok) | |
1157 | { | |
1158 | for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++) | |
1159 | if (regs_ever_live[i] == 0) | |
1160 | { | |
1161 | i960_leaf_ret_reg = i; | |
1162 | regs_ever_live[i] = 1; | |
1163 | break; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | /* Do this after choosing the leaf return register, so it will be listed | |
1168 | if one was chosen. */ | |
1169 | ||
bb562bfc | 1170 | fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name)); |
ba8ab355 JW |
1171 | fprintf (file, "\t# Registers used: "); |
1172 | ||
1173 | for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1174 | { | |
1175 | if (regs_ever_live[i]) | |
1176 | { | |
1177 | fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*"); | |
1178 | ||
1179 | if (i > 15 && j == 0) | |
1180 | { | |
1181 | fprintf (file,"\n\t#\t\t "); | |
1182 | j++; | |
1183 | } | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | fprintf (file, "\n"); | |
1188 | ||
1189 | if (i960_leaf_ret_reg >= 0) | |
1190 | { | |
1191 | /* Make it a leaf procedure. */ | |
1192 | ||
1193 | if (TREE_PUBLIC (fndecl)) | |
bb562bfc | 1194 | fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name)); |
ba8ab355 | 1195 | |
bb562bfc JW |
1196 | fprintf (file, "\t.leafproc\t"); |
1197 | assemble_name (file, name); | |
1198 | fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name)); | |
1199 | ASM_OUTPUT_LABEL (file, name); | |
c3c7ea1f | 1200 | fprintf (file, "\tlda Li960R%d,g14\n", ret_label); |
bb562bfc | 1201 | fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name)); |
ba8ab355 JW |
1202 | fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg); |
1203 | ||
1204 | if (TARGET_C_SERIES) | |
1205 | { | |
1206 | fprintf (file, "\tlda 0,g14\n"); | |
1207 | i960_last_insn_type = I_TYPE_MEM; | |
1208 | } | |
1209 | else | |
1210 | { | |
1211 | fprintf (file, "\tmov 0,g14\n"); | |
1212 | i960_last_insn_type = I_TYPE_REG; | |
1213 | } | |
1214 | } | |
1215 | else | |
1216 | { | |
1217 | ASM_OUTPUT_LABEL (file, name); | |
1218 | i960_last_insn_type = I_TYPE_CTRL; | |
1219 | } | |
1220 | } | |
1221 | \f | |
1222 | /* Compute and return the frame size. */ | |
1223 | ||
1224 | int | |
1225 | compute_frame_size (size) | |
1226 | int size; | |
1227 | { | |
1228 | int actual_fsize; | |
c25d3f20 | 1229 | int outgoing_args_size = current_function_outgoing_args_size; |
ba8ab355 JW |
1230 | |
1231 | /* The STARTING_FRAME_OFFSET is totally hidden to us as far | |
1232 | as size is concerned. */ | |
1233 | actual_fsize = (size + 15) & -16; | |
1234 | actual_fsize += (outgoing_args_size + 15) & -16; | |
1235 | ||
1236 | return actual_fsize; | |
1237 | } | |
1238 | ||
9ef06443 VM |
1239 | /* Here register group is range of registers which can be moved by |
1240 | one i960 instruction. */ | |
1241 | ||
1242 | struct reg_group | |
1243 | { | |
1244 | char start_reg; | |
1245 | char length; | |
1246 | }; | |
1247 | ||
1248 | /* The following functions forms the biggest as possible register | |
1249 | groups with registers in STATE. REGS contain states of the | |
1250 | registers in range [start, finish_reg). The function returns the | |
1251 | number of groups formed. */ | |
1252 | static int | |
1253 | i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups) | |
1254 | int start_reg; | |
1255 | int finish_reg; | |
1256 | int *regs; | |
1257 | int state; | |
1258 | struct reg_group *reg_groups; | |
1259 | { | |
1260 | int i; | |
1261 | int nw = 0; | |
1262 | ||
1263 | for (i = start_reg; i < finish_reg; ) | |
1264 | { | |
1265 | if (regs [i] != state) | |
1266 | { | |
1267 | i++; | |
1268 | continue; | |
1269 | } | |
1270 | else if (i % 2 != 0 || regs [i + 1] != state) | |
1271 | reg_groups [nw].length = 1; | |
1272 | else if (i % 4 != 0 || regs [i + 2] != state) | |
1273 | reg_groups [nw].length = 2; | |
1274 | else if (regs [i + 3] != state) | |
1275 | reg_groups [nw].length = 3; | |
1276 | else | |
1277 | reg_groups [nw].length = 4; | |
1278 | reg_groups [nw].start_reg = i; | |
1279 | i += reg_groups [nw].length; | |
1280 | nw++; | |
1281 | } | |
1282 | return nw; | |
1283 | } | |
1284 | ||
1285 | /* We sort register winodws in descending order by length. */ | |
1286 | static int | |
1287 | i960_reg_group_compare (group1, group2) | |
1288 | void *group1; | |
1289 | void *group2; | |
1290 | { | |
1291 | struct reg_group *w1 = group1; | |
1292 | struct reg_group *w2 = group2; | |
1293 | ||
1294 | if (w1->length > w2->length) | |
1295 | return -1; | |
1296 | else if (w1->length < w2->length) | |
1297 | return 1; | |
1298 | else | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | /* Split the first register group in REG_GROUPS on subgroups one of | |
1303 | which will contain SUBGROUP_LENGTH registers. The function | |
1304 | returns new number of winodws. */ | |
1305 | static int | |
1306 | i960_split_reg_group (reg_groups, nw, subgroup_length) | |
1307 | struct reg_group *reg_groups; | |
1308 | int nw; | |
1309 | int subgroup_length; | |
1310 | { | |
1311 | if (subgroup_length < reg_groups->length - subgroup_length) | |
1312 | /* This guarantees correct alignments of the two subgroups for | |
1313 | i960 (see spliting for the group length 2, 3, 4). More | |
1314 | generalized algorithm would require splitting the group more | |
1315 | two subgroups. */ | |
1316 | subgroup_length = reg_groups->length - subgroup_length; | |
1317 | /* More generalized algorithm would require to try merging | |
1318 | subgroups here. But in case i960 it always results in failure | |
1319 | because of register group alignment. */ | |
1320 | reg_groups[nw].length = reg_groups->length - subgroup_length; | |
1321 | reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length; | |
1322 | nw++; | |
1323 | reg_groups->length = subgroup_length; | |
1324 | qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare); | |
1325 | return nw; | |
1326 | } | |
1327 | ||
ba8ab355 JW |
1328 | /* Output code for the function prologue. */ |
1329 | ||
1330 | void | |
1331 | i960_function_prologue (file, size) | |
1332 | FILE *file; | |
1333 | unsigned int size; | |
1334 | { | |
1335 | register int i, j, nr; | |
1336 | int n_iregs = 0; | |
1337 | int rsize = 0; | |
77a02b01 | 1338 | int actual_fsize, offset; |
9ef06443 VM |
1339 | int gnw, lnw; |
1340 | struct reg_group *g, *l; | |
ba8ab355 JW |
1341 | char tmpstr[1000]; |
1342 | /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved | |
1343 | somewhere. */ | |
1344 | int regs[FIRST_PSEUDO_REGISTER]; | |
9ef06443 VM |
1345 | /* All global registers (which must be saved) divided by groups. */ |
1346 | struct reg_group global_reg_groups [16]; | |
1347 | /* All local registers (which are available) divided by groups. */ | |
1348 | struct reg_group local_reg_groups [16]; | |
1349 | ||
ba8ab355 JW |
1350 | |
1351 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
1352 | if (regs_ever_live[i] | |
a45f3331 JW |
1353 | && ((! call_used_regs[i]) || (i > 7 && i < 12)) |
1354 | /* No need to save the static chain pointer. */ | |
1355 | && ! (i == STATIC_CHAIN_REGNUM && current_function_needs_context)) | |
ba8ab355 JW |
1356 | { |
1357 | regs[i] = -1; | |
1358 | /* Count global registers that need saving. */ | |
1359 | if (i < 16) | |
1360 | n_iregs++; | |
1361 | } | |
1362 | else | |
1363 | regs[i] = 0; | |
1364 | ||
1365 | epilogue_string[0] = '\0'; | |
1366 | ||
7a24dbcf JW |
1367 | if (profile_flag || profile_block_flag) |
1368 | { | |
1369 | /* When profiling, we may use registers 20 to 27 to save arguments, so | |
1370 | they can't be used here for saving globals. J is the number of | |
1371 | argument registers the mcount call will save. */ | |
1372 | for (j = 7; j >= 0 && ! regs_ever_live[j]; j--) | |
1373 | ; | |
1374 | ||
1375 | for (i = 20; i <= j + 20; i++) | |
1376 | regs[i] = -1; | |
1377 | } | |
1378 | ||
9ef06443 VM |
1379 | gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups); |
1380 | lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups); | |
1381 | qsort (global_reg_groups, gnw, sizeof (struct reg_group), | |
1382 | i960_reg_group_compare); | |
1383 | qsort (local_reg_groups, lnw, sizeof (struct reg_group), | |
1384 | i960_reg_group_compare); | |
1385 | for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;) | |
ba8ab355 | 1386 | { |
9ef06443 | 1387 | if (g->length == l->length) |
ba8ab355 | 1388 | { |
ba8ab355 | 1389 | fprintf (file, "\tmov%s %s,%s\n", |
9ef06443 VM |
1390 | ((g->length == 4) ? "q" : |
1391 | (g->length == 3) ? "t" : | |
1392 | (g->length == 2) ? "l" : ""), | |
1393 | reg_names[g->start_reg], reg_names[l->start_reg]); | |
ba8ab355 | 1394 | sprintf (tmpstr, "\tmov%s %s,%s\n", |
9ef06443 VM |
1395 | ((g->length == 4) ? "q" : |
1396 | (g->length == 3) ? "t" : | |
1397 | (g->length == 2) ? "l" : ""), | |
1398 | reg_names[l->start_reg], reg_names[g->start_reg]); | |
ba8ab355 | 1399 | strcat (epilogue_string, tmpstr); |
9ef06443 VM |
1400 | n_iregs -= g->length; |
1401 | for (i = 0; i < g->length; i++) | |
1402 | { | |
1403 | regs [i + g->start_reg] = 1; | |
1404 | regs [i + l->start_reg] = -1; | |
1405 | regs_ever_live [i + l->start_reg] = 1; | |
1406 | } | |
1407 | g++; | |
1408 | l++; | |
1409 | gnw--; | |
1410 | lnw--; | |
ba8ab355 | 1411 | } |
9ef06443 VM |
1412 | else if (g->length > l->length) |
1413 | gnw = i960_split_reg_group (g, gnw, l->length); | |
1414 | else | |
1415 | lnw = i960_split_reg_group (l, lnw, g->length); | |
ba8ab355 JW |
1416 | } |
1417 | ||
1418 | /* N_iregs is now the number of global registers that haven't been saved | |
1419 | yet. */ | |
1420 | ||
1421 | rsize = (n_iregs * 4); | |
1422 | actual_fsize = compute_frame_size (size) + rsize; | |
1423 | #if 0 | |
1424 | /* ??? The 1.2.1 compiler does this also. This is meant to round the frame | |
1425 | size up to the nearest multiple of 16. I don't know whether this is | |
77a02b01 JW |
1426 | necessary, or even desirable. |
1427 | ||
1428 | The frame pointer must be aligned, but the call instruction takes care of | |
1429 | that. If we leave the stack pointer unaligned, we may save a little on | |
1430 | dynamic stack allocation. And we don't lose, at least according to the | |
1431 | i960CA manual. */ | |
ba8ab355 JW |
1432 | actual_fsize = (actual_fsize + 15) & ~0xF; |
1433 | #endif | |
1434 | ||
1435 | /* Allocate space for register save and locals. */ | |
1436 | if (actual_fsize > 0) | |
1437 | { | |
1438 | if (actual_fsize < 32) | |
1439 | fprintf (file, "\taddo %d,sp,sp\n", actual_fsize); | |
1440 | else | |
1441 | fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize); | |
1442 | } | |
77a02b01 JW |
1443 | |
1444 | /* Take hardware register save area created by the call instruction | |
2ea998c8 DE |
1445 | into account, but store them before the argument block area. */ |
1446 | offset = 64 + actual_fsize - compute_frame_size (0) - rsize; | |
ba8ab355 | 1447 | /* Save registers on stack if needed. */ |
9ef06443 VM |
1448 | /* ??? Is it worth to use the same algorithm as one for saving |
1449 | global registers in local registers? */ | |
ba8ab355 JW |
1450 | for (i = 0, j = n_iregs; j > 0 && i < 16; i++) |
1451 | { | |
1452 | if (regs[i] != -1) | |
1453 | continue; | |
1454 | ||
1455 | nr = 1; | |
1456 | ||
77a02b01 | 1457 | if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0) |
ba8ab355 JW |
1458 | nr = 2; |
1459 | ||
77a02b01 JW |
1460 | if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1 |
1461 | && offset % 4 == 0) | |
ba8ab355 JW |
1462 | nr = 3; |
1463 | ||
1464 | if (nr == 3 && regs[i+3] == -1) | |
1465 | nr = 4; | |
1466 | ||
1467 | fprintf (file,"\tst%s %s,%d(fp)\n", | |
1468 | ((nr == 4) ? "q" : | |
1469 | (nr == 3) ? "t" : | |
1470 | (nr == 2) ? "l" : ""), | |
77a02b01 | 1471 | reg_names[i], offset); |
ba8ab355 JW |
1472 | sprintf (tmpstr,"\tld%s %d(fp),%s\n", |
1473 | ((nr == 4) ? "q" : | |
1474 | (nr == 3) ? "t" : | |
1475 | (nr == 2) ? "l" : ""), | |
77a02b01 | 1476 | offset, reg_names[i]); |
ba8ab355 JW |
1477 | strcat (epilogue_string, tmpstr); |
1478 | i += nr-1; | |
1479 | j -= nr; | |
77a02b01 | 1480 | offset += nr * 4; |
ba8ab355 JW |
1481 | } |
1482 | ||
1483 | if (actual_fsize == 0 && size == 0 && rsize == 0) | |
1484 | return; | |
1485 | ||
1486 | fprintf (file, "\t#Prologue stats:\n"); | |
1487 | fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize); | |
1488 | ||
1489 | if (size) | |
1490 | fprintf (file, "\t# Local Variable Size: %d bytes\n", size); | |
1491 | if (rsize) | |
1492 | fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n", | |
1493 | n_iregs, rsize); | |
1494 | fprintf (file, "\t#End Prologue#\n"); | |
1495 | } | |
1496 | ||
7a24dbcf JW |
1497 | /* Output code for the function profiler. */ |
1498 | ||
1499 | void | |
1500 | output_function_profiler (file, labelno) | |
1501 | FILE *file; | |
1502 | int labelno; | |
1503 | { | |
1504 | /* The last used parameter register. */ | |
1505 | int last_parm_reg; | |
1506 | int i, j, increment; | |
c25d3f20 JW |
1507 | int varargs_stdarg_function |
1508 | = VARARGS_STDARG_FUNCTION (current_function_decl); | |
7a24dbcf JW |
1509 | |
1510 | /* Figure out the last used parameter register. The proper thing to do | |
1511 | is to walk incoming args of the function. A function might have live | |
1512 | parameter registers even if it has no incoming args. Note that we | |
1513 | don't have to save parameter registers g8 to g11 because they are | |
1514 | call preserved. */ | |
1515 | ||
1516 | /* See also output_function_prologue, which tries to use local registers | |
1517 | for preserved call-saved global registers. */ | |
1518 | ||
1519 | for (last_parm_reg = 7; | |
1520 | last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg]; | |
1521 | last_parm_reg--) | |
1522 | ; | |
1523 | ||
1524 | /* Save parameter registers in regs r4 (20) to r11 (27). */ | |
1525 | ||
1526 | for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) | |
1527 | { | |
1528 | if (i % 4 == 0 && (last_parm_reg - i) >= 3) | |
1529 | increment = 4; | |
1530 | else if (i % 4 == 0 && (last_parm_reg - i) >= 2) | |
1531 | increment = 3; | |
1532 | else if (i % 2 == 0 && (last_parm_reg - i) >= 1) | |
1533 | increment = 2; | |
1534 | else | |
1535 | increment = 1; | |
1536 | ||
1537 | fprintf (file, "\tmov%s g%d,r%d\n", | |
1538 | (increment == 4 ? "q" : increment == 3 ? "t" | |
1539 | : increment == 2 ? "l": ""), i, j); | |
1540 | } | |
1541 | ||
1542 | /* If this function uses the arg pointer, then save it in r3 and then | |
1543 | set it to zero. */ | |
1544 | ||
c25d3f20 | 1545 | if (current_function_args_size != 0 || varargs_stdarg_function) |
bfc965cf | 1546 | fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n"); |
7a24dbcf JW |
1547 | |
1548 | /* Load location address into g0 and call mcount. */ | |
1549 | ||
1550 | fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno); | |
1551 | ||
1552 | /* If this function uses the arg pointer, restore it. */ | |
1553 | ||
c25d3f20 | 1554 | if (current_function_args_size != 0 || varargs_stdarg_function) |
bfc965cf | 1555 | fprintf (file, "\tmov r3,g14\n"); |
7a24dbcf JW |
1556 | |
1557 | /* Restore parameter registers. */ | |
1558 | ||
1559 | for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment) | |
1560 | { | |
1561 | if (i % 4 == 0 && (last_parm_reg - i) >= 3) | |
1562 | increment = 4; | |
1563 | else if (i % 4 == 0 && (last_parm_reg - i) >= 2) | |
1564 | increment = 3; | |
1565 | else if (i % 2 == 0 && (last_parm_reg - i) >= 1) | |
1566 | increment = 2; | |
1567 | else | |
1568 | increment = 1; | |
1569 | ||
1570 | fprintf (file, "\tmov%s r%d,g%d\n", | |
1571 | (increment == 4 ? "q" : increment == 3 ? "t" | |
1572 | : increment == 2 ? "l": ""), j, i); | |
1573 | } | |
1574 | } | |
1575 | ||
ba8ab355 JW |
1576 | /* Output code for the function epilogue. */ |
1577 | ||
1578 | void | |
1579 | i960_function_epilogue (file, size) | |
1580 | FILE *file; | |
1581 | unsigned int size; | |
1582 | { | |
1583 | if (i960_leaf_ret_reg >= 0) | |
1584 | { | |
c3c7ea1f | 1585 | fprintf (file, "Li960R%d: ret\n", ret_label); |
ba8ab355 JW |
1586 | return; |
1587 | } | |
1588 | ||
1589 | if (*epilogue_string == 0) | |
1590 | { | |
1591 | register rtx tmp; | |
1592 | ||
1593 | /* Emit a return insn, but only if control can fall through to here. */ | |
1594 | ||
1595 | tmp = get_last_insn (); | |
1596 | while (tmp) | |
1597 | { | |
1598 | if (GET_CODE (tmp) == BARRIER) | |
1599 | return; | |
1600 | if (GET_CODE (tmp) == CODE_LABEL) | |
1601 | break; | |
1602 | if (GET_CODE (tmp) == JUMP_INSN) | |
1603 | { | |
1604 | if (GET_CODE (PATTERN (tmp)) == RETURN) | |
1605 | return; | |
1606 | break; | |
1607 | } | |
1608 | if (GET_CODE (tmp) == NOTE) | |
1609 | { | |
1610 | tmp = PREV_INSN (tmp); | |
1611 | continue; | |
1612 | } | |
1613 | break; | |
1614 | } | |
c3c7ea1f | 1615 | fprintf (file, "Li960R%d: ret\n", ret_label); |
ba8ab355 JW |
1616 | return; |
1617 | } | |
1618 | ||
c3c7ea1f | 1619 | fprintf (file, "Li960R%d:\n", ret_label); |
ba8ab355 JW |
1620 | |
1621 | fprintf (file, "\t#EPILOGUE#\n"); | |
1622 | ||
1623 | /* Output the string created by the prologue which will restore all | |
1624 | registers saved by the prologue. */ | |
1625 | ||
1626 | if (epilogue_string[0] != '\0') | |
1627 | fprintf (file, "%s", epilogue_string); | |
1628 | ||
4c876b4f RK |
1629 | /* Must clear g14 on return if this function set it. |
1630 | Only varargs/stdarg functions modify g14. */ | |
ba8ab355 | 1631 | |
4c876b4f | 1632 | if (VARARGS_STDARG_FUNCTION (current_function_decl)) |
ba8ab355 JW |
1633 | fprintf (file, "\tmov 0,g14\n"); |
1634 | ||
1635 | fprintf (file, "\tret\n"); | |
1636 | fprintf (file, "\t#End Epilogue#\n"); | |
1637 | } | |
1638 | ||
1639 | /* Output code for a call insn. */ | |
1640 | ||
1641 | char * | |
fda792c6 JW |
1642 | i960_output_call_insn (target, argsize_rtx, arg_pointer, insn) |
1643 | register rtx target, argsize_rtx, arg_pointer, insn; | |
ba8ab355 | 1644 | { |
ba8ab355 JW |
1645 | int argsize = INTVAL (argsize_rtx); |
1646 | rtx nexti = next_real_insn (insn); | |
fda792c6 | 1647 | rtx operands[2]; |
c25d3f20 JW |
1648 | int varargs_stdarg_function |
1649 | = VARARGS_STDARG_FUNCTION (current_function_decl); | |
ba8ab355 JW |
1650 | |
1651 | operands[0] = target; | |
83f49630 | 1652 | operands[1] = arg_pointer; |
83f49630 | 1653 | |
c25d3f20 | 1654 | if (current_function_args_size != 0 || varargs_stdarg_function) |
fda792c6 | 1655 | output_asm_insn ("mov g14,r3", operands); |
83f49630 JW |
1656 | |
1657 | if (argsize > 48) | |
1658 | output_asm_insn ("lda %a1,g14", operands); | |
c25d3f20 | 1659 | else if (current_function_args_size != 0 || varargs_stdarg_function) |
83f49630 | 1660 | output_asm_insn ("mov 0,g14", operands); |
ba8ab355 | 1661 | |
76542a00 JW |
1662 | /* The code used to assume that calls to SYMBOL_REFs could not be more |
1663 | than 24 bits away (b vs bx, callj vs callx). This is not true. This | |
1664 | feature is now implemented by relaxing in the GNU linker. It can convert | |
1665 | bx to b if in range, and callx to calls/call/balx/bal as appropriate. */ | |
ba8ab355 JW |
1666 | |
1667 | /* Nexti could be zero if the called routine is volatile. */ | |
1668 | if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok | |
1669 | && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN)) | |
1670 | { | |
1671 | /* Delete following return insn. */ | |
1672 | if (nexti && no_labels_between_p (insn, nexti)) | |
1673 | delete_insn (nexti); | |
76542a00 | 1674 | output_asm_insn ("bx %0", operands); |
ba8ab355 JW |
1675 | return "# notreached"; |
1676 | } | |
1677 | ||
76542a00 | 1678 | output_asm_insn ("callx %0", operands); |
83f49630 | 1679 | |
4c876b4f RK |
1680 | /* If the caller sets g14 to the address of the argblock, then the caller |
1681 | must clear it after the return. */ | |
1682 | ||
c25d3f20 | 1683 | if (current_function_args_size != 0 || varargs_stdarg_function) |
fda792c6 | 1684 | output_asm_insn ("mov r3,g14", operands); |
4c876b4f RK |
1685 | else if (argsize > 48) |
1686 | output_asm_insn ("mov 0,g14", operands); | |
83f49630 | 1687 | |
ba8ab355 JW |
1688 | return ""; |
1689 | } | |
1690 | ||
1691 | /* Output code for a return insn. */ | |
1692 | ||
1693 | char * | |
1694 | i960_output_ret_insn (insn) | |
1695 | register rtx insn; | |
1696 | { | |
1697 | static char lbuf[20]; | |
1698 | ||
1699 | if (*epilogue_string != 0) | |
1700 | { | |
1701 | if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0) | |
1702 | return ""; | |
1703 | ||
c3c7ea1f | 1704 | sprintf (lbuf, "b Li960R%d", ret_label); |
ba8ab355 JW |
1705 | return lbuf; |
1706 | } | |
1707 | ||
4c876b4f RK |
1708 | /* Must clear g14 on return if this function set it. |
1709 | Only varargs/stdarg functions modify g14. */ | |
1710 | ||
1711 | if (VARARGS_STDARG_FUNCTION (current_function_decl)) | |
ba8ab355 JW |
1712 | output_asm_insn ("mov 0,g14", 0); |
1713 | ||
1714 | if (i960_leaf_ret_reg >= 0) | |
1715 | { | |
1716 | sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]); | |
1717 | return lbuf; | |
1718 | } | |
1719 | return "ret"; | |
1720 | } | |
1721 | \f | |
1722 | #if 0 | |
1723 | /* Return a character string representing the branch prediction | |
1724 | opcode to be tacked on an instruction. This must at least | |
1725 | return a null string. */ | |
1726 | ||
1727 | char * | |
1728 | i960_br_predict_opcode (lab_ref, insn) | |
1729 | rtx lab_ref, insn; | |
1730 | { | |
1731 | if (TARGET_BRANCH_PREDICT) | |
1732 | { | |
1733 | unsigned long label_uid; | |
1734 | ||
1735 | if (GET_CODE (lab_ref) == CODE_LABEL) | |
1736 | label_uid = INSN_UID (lab_ref); | |
1737 | else if (GET_CODE (lab_ref) == LABEL_REF) | |
1738 | label_uid = INSN_UID (XEXP (lab_ref, 0)); | |
1739 | else | |
1740 | return ".f"; | |
1741 | ||
1742 | /* If not optimizing, then the insn_addresses array will not be | |
1743 | valid. In this case, always return ".t" since most branches | |
1744 | are taken. If optimizing, return .t for backward branches | |
1745 | and .f for forward branches. */ | |
1746 | if (! optimize | |
1747 | || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)]) | |
1748 | return ".t"; | |
1749 | return ".f"; | |
1750 | } | |
1751 | ||
1752 | return ""; | |
1753 | } | |
1754 | #endif | |
1755 | ||
1756 | /* Print the operand represented by rtx X formatted by code CODE. */ | |
1757 | ||
1758 | void | |
1759 | i960_print_operand (file, x, code) | |
1760 | FILE *file; | |
1761 | rtx x; | |
1762 | char code; | |
1763 | { | |
1764 | enum rtx_code rtxcode = GET_CODE (x); | |
1765 | ||
1766 | if (rtxcode == REG) | |
1767 | { | |
1768 | switch (code) | |
1769 | { | |
1770 | case 'D': | |
3a89bbcb | 1771 | /* Second reg of a double or quad. */ |
ba8ab355 JW |
1772 | fprintf (file, "%s", reg_names[REGNO (x)+1]); |
1773 | break; | |
1774 | ||
3a89bbcb RK |
1775 | case 'E': |
1776 | /* Third reg of a quad. */ | |
1777 | fprintf (file, "%s", reg_names[REGNO (x)+2]); | |
1778 | break; | |
1779 | ||
1780 | case 'F': | |
1781 | /* Fourth reg of a quad. */ | |
1782 | fprintf (file, "%s", reg_names[REGNO (x)+3]); | |
1783 | break; | |
1784 | ||
ba8ab355 JW |
1785 | case 0: |
1786 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
1787 | break; | |
1788 | ||
1789 | default: | |
1790 | abort (); | |
1791 | } | |
1792 | return; | |
1793 | } | |
1794 | else if (rtxcode == MEM) | |
1795 | { | |
1796 | output_address (XEXP (x, 0)); | |
1797 | return; | |
1798 | } | |
1799 | else if (rtxcode == CONST_INT) | |
1800 | { | |
f20200f4 TG |
1801 | HOST_WIDE_INT val = INTVAL (x); |
1802 | if (code == 'C') | |
1803 | val = ~val; | |
1804 | if (val > 9999 || val < -999) | |
1805 | fprintf (file, "0x%x", val); | |
ba8ab355 | 1806 | else |
f20200f4 | 1807 | fprintf (file, "%d", val); |
ba8ab355 JW |
1808 | return; |
1809 | } | |
1810 | else if (rtxcode == CONST_DOUBLE) | |
1811 | { | |
ca01dc12 TG |
1812 | REAL_VALUE_TYPE d; |
1813 | char dstr[30]; | |
ba8ab355 | 1814 | |
ca01dc12 | 1815 | if (x == CONST0_RTX (GET_MODE (x))) |
ba8ab355 JW |
1816 | { |
1817 | fprintf (file, "0f0.0"); | |
1818 | return; | |
1819 | } | |
ca01dc12 | 1820 | else if (x == CONST1_RTX (GET_MODE (x))) |
ba8ab355 JW |
1821 | { |
1822 | fprintf (file, "0f1.0"); | |
1823 | return; | |
1824 | } | |
1825 | ||
ba8ab355 | 1826 | REAL_VALUE_FROM_CONST_DOUBLE (d, x); |
ca01dc12 TG |
1827 | REAL_VALUE_TO_DECIMAL (d, "%#g", dstr); |
1828 | fprintf (file, "0f%s", dstr); | |
ba8ab355 JW |
1829 | return; |
1830 | } | |
1831 | ||
1832 | switch(code) | |
1833 | { | |
1834 | case 'B': | |
1835 | /* Branch or jump, depending on assembler. */ | |
1836 | if (TARGET_ASM_COMPAT) | |
1837 | fputs ("j", file); | |
1838 | else | |
1839 | fputs ("b", file); | |
1840 | break; | |
1841 | ||
1842 | case 'S': | |
1843 | /* Sign of condition. */ | |
1844 | if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU) | |
1845 | || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU)) | |
1846 | fputs ("o", file); | |
1847 | else if ((rtxcode == GT) || (rtxcode == LT) | |
1848 | || (rtxcode == GE) || (rtxcode == LE)) | |
1849 | fputs ("i", file); | |
1850 | else | |
1851 | abort(); | |
1852 | break; | |
1853 | ||
1854 | case 'I': | |
1855 | /* Inverted condition. */ | |
1856 | rtxcode = reverse_condition (rtxcode); | |
1857 | goto normal; | |
1858 | ||
1859 | case 'X': | |
1860 | /* Inverted condition w/ reversed operands. */ | |
1861 | rtxcode = reverse_condition (rtxcode); | |
1862 | /* Fallthrough. */ | |
1863 | ||
1864 | case 'R': | |
1865 | /* Reversed operand condition. */ | |
1866 | rtxcode = swap_condition (rtxcode); | |
1867 | /* Fallthrough. */ | |
1868 | ||
1869 | case 'C': | |
1870 | /* Normal condition. */ | |
1871 | normal: | |
1872 | if (rtxcode == EQ) { fputs ("e", file); return; } | |
1873 | else if (rtxcode == NE) { fputs ("ne", file); return; } | |
1874 | else if (rtxcode == GT) { fputs ("g", file); return; } | |
1875 | else if (rtxcode == GTU) { fputs ("g", file); return; } | |
1876 | else if (rtxcode == LT) { fputs ("l", file); return; } | |
1877 | else if (rtxcode == LTU) { fputs ("l", file); return; } | |
1878 | else if (rtxcode == GE) { fputs ("ge", file); return; } | |
1879 | else if (rtxcode == GEU) { fputs ("ge", file); return; } | |
1880 | else if (rtxcode == LE) { fputs ("le", file); return; } | |
1881 | else if (rtxcode == LEU) { fputs ("le", file); return; } | |
1882 | else abort (); | |
1883 | break; | |
1884 | ||
1885 | case 0: | |
1886 | output_addr_const (file, x); | |
1887 | break; | |
1888 | ||
1889 | default: | |
1890 | abort (); | |
1891 | } | |
1892 | ||
1893 | return; | |
1894 | } | |
1895 | \f | |
1896 | /* Print a memory address as an operand to reference that memory location. | |
1897 | ||
1898 | This is exactly the same as legitimate_address_p, except that it the prints | |
1899 | addresses instead of recognizing them. */ | |
1900 | ||
1901 | void | |
1902 | i960_print_operand_addr (file, addr) | |
1903 | FILE *file; | |
1904 | register rtx addr; | |
1905 | { | |
1906 | rtx breg, ireg; | |
1907 | rtx scale, offset; | |
1908 | ||
1909 | ireg = 0; | |
1910 | breg = 0; | |
1911 | offset = 0; | |
1912 | scale = const1_rtx; | |
1913 | ||
1914 | if (GET_CODE (addr) == REG) | |
1915 | breg = addr; | |
1916 | else if (CONSTANT_P (addr)) | |
1917 | offset = addr; | |
1918 | else if (GET_CODE (addr) == PLUS) | |
1919 | { | |
1920 | rtx op0, op1; | |
1921 | ||
1922 | op0 = XEXP (addr, 0); | |
1923 | op1 = XEXP (addr, 1); | |
1924 | ||
1925 | if (GET_CODE (op0) == REG) | |
1926 | { | |
1927 | breg = op0; | |
1928 | if (GET_CODE (op1) == REG) | |
1929 | ireg = op1; | |
1930 | else if (CONSTANT_P (op1)) | |
1931 | offset = op1; | |
1932 | else | |
1933 | abort (); | |
1934 | } | |
1935 | else if (GET_CODE (op0) == PLUS) | |
1936 | { | |
1937 | if (GET_CODE (XEXP (op0, 0)) == MULT) | |
1938 | { | |
1939 | ireg = XEXP (XEXP (op0, 0), 0); | |
1940 | scale = XEXP (XEXP (op0, 0), 1); | |
1941 | if (GET_CODE (XEXP (op0, 1)) == REG) | |
1942 | { | |
1943 | breg = XEXP (op0, 1); | |
1944 | offset = op1; | |
1945 | } | |
1946 | else | |
1947 | abort (); | |
1948 | } | |
1949 | else if (GET_CODE (XEXP (op0, 0)) == REG) | |
1950 | { | |
1951 | breg = XEXP (op0, 0); | |
1952 | if (GET_CODE (XEXP (op0, 1)) == REG) | |
1953 | { | |
1954 | ireg = XEXP (op0, 1); | |
1955 | offset = op1; | |
1956 | } | |
1957 | else | |
1958 | abort (); | |
1959 | } | |
1960 | else | |
1961 | abort (); | |
1962 | } | |
1963 | else if (GET_CODE (op0) == MULT) | |
1964 | { | |
1965 | ireg = XEXP (op0, 0); | |
1966 | scale = XEXP (op0, 1); | |
1967 | if (GET_CODE (op1) == REG) | |
1968 | breg = op1; | |
1969 | else if (CONSTANT_P (op1)) | |
1970 | offset = op1; | |
1971 | else | |
1972 | abort (); | |
1973 | } | |
1974 | else | |
1975 | abort (); | |
1976 | } | |
1977 | else if (GET_CODE (addr) == MULT) | |
1978 | { | |
a2f30f14 | 1979 | ireg = XEXP (addr, 0); |
ba8ab355 JW |
1980 | scale = XEXP (addr, 1); |
1981 | } | |
1982 | else | |
1983 | abort (); | |
1984 | ||
1985 | if (offset) | |
1986 | output_addr_const (file, offset); | |
1987 | if (breg) | |
1988 | fprintf (file, "(%s)", reg_names[REGNO (breg)]); | |
1989 | if (ireg) | |
1990 | fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale)); | |
1991 | } | |
1992 | \f | |
1993 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1994 | that is a valid memory address for an instruction. | |
1995 | The MODE argument is the machine mode for the MEM expression | |
1996 | that wants to use this address. | |
1997 | ||
1998 | On 80960, legitimate addresses are: | |
1999 | base ld (g0),r0 | |
2000 | disp (12 or 32 bit) ld foo,r0 | |
2001 | base + index ld (g0)[g1*1],r0 | |
2002 | base + displ ld 0xf00(g0),r0 | |
2003 | base + index*scale + displ ld 0xf00(g0)[g1*4],r0 | |
2004 | index*scale + base ld (g0)[g1*4],r0 | |
2005 | index*scale + displ ld 0xf00[g1*4],r0 | |
2006 | index*scale ld [g1*4],r0 | |
2007 | index + base + displ ld 0xf00(g0)[g1*1],r0 | |
2008 | ||
2009 | In each case, scale can be 1, 2, 4, 8, or 16. */ | |
2010 | ||
2011 | /* This is exactly the same as i960_print_operand_addr, except that | |
2012 | it recognizes addresses instead of printing them. | |
2013 | ||
2014 | It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should | |
2015 | convert common non-canonical forms to canonical form so that they will | |
2016 | be recognized. */ | |
2017 | ||
0a56ad62 JW |
2018 | /* These two macros allow us to accept either a REG or a SUBREG anyplace |
2019 | where a register is valid. */ | |
2020 | ||
2021 | #define RTX_OK_FOR_BASE_P(X, STRICT) \ | |
2022 | ((GET_CODE (X) == REG \ | |
2023 | && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \ | |
2024 | || (GET_CODE (X) == SUBREG \ | |
2025 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2026 | && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \ | |
2027 | : REG_OK_FOR_BASE_P (SUBREG_REG (X))))) | |
2028 | ||
2029 | #define RTX_OK_FOR_INDEX_P(X, STRICT) \ | |
2030 | ((GET_CODE (X) == REG \ | |
2031 | && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\ | |
2032 | || (GET_CODE (X) == SUBREG \ | |
2033 | && GET_CODE (SUBREG_REG (X)) == REG \ | |
2034 | && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \ | |
2035 | : REG_OK_FOR_INDEX_P (SUBREG_REG (X))))) | |
2036 | ||
ba8ab355 JW |
2037 | int |
2038 | legitimate_address_p (mode, addr, strict) | |
2039 | enum machine_mode mode; | |
2040 | register rtx addr; | |
2041 | int strict; | |
2042 | { | |
0a56ad62 JW |
2043 | if (RTX_OK_FOR_BASE_P (addr, strict)) |
2044 | return 1; | |
ba8ab355 JW |
2045 | else if (CONSTANT_P (addr)) |
2046 | return 1; | |
2047 | else if (GET_CODE (addr) == PLUS) | |
2048 | { | |
2049 | rtx op0, op1; | |
2050 | ||
2051 | if (! TARGET_COMPLEX_ADDR && ! reload_completed) | |
2052 | return 0; | |
2053 | ||
2054 | op0 = XEXP (addr, 0); | |
2055 | op1 = XEXP (addr, 1); | |
2056 | ||
0a56ad62 | 2057 | if (RTX_OK_FOR_BASE_P (op0, strict)) |
ba8ab355 | 2058 | { |
0a56ad62 JW |
2059 | if (RTX_OK_FOR_INDEX_P (op1, strict)) |
2060 | return 1; | |
ba8ab355 JW |
2061 | else if (CONSTANT_P (op1)) |
2062 | return 1; | |
2063 | else | |
2064 | return 0; | |
2065 | } | |
2066 | else if (GET_CODE (op0) == PLUS) | |
2067 | { | |
2068 | if (GET_CODE (XEXP (op0, 0)) == MULT) | |
2069 | { | |
0a56ad62 | 2070 | if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict) |
ba8ab355 JW |
2071 | && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1)))) |
2072 | return 0; | |
2073 | ||
0a56ad62 JW |
2074 | if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict) |
2075 | && CONSTANT_P (op1)) | |
2076 | return 1; | |
ba8ab355 JW |
2077 | else |
2078 | return 0; | |
2079 | } | |
0a56ad62 | 2080 | else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict)) |
ba8ab355 | 2081 | { |
0a56ad62 JW |
2082 | if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict) |
2083 | && CONSTANT_P (op1)) | |
2084 | return 1; | |
ba8ab355 JW |
2085 | else |
2086 | return 0; | |
2087 | } | |
2088 | else | |
2089 | return 0; | |
2090 | } | |
2091 | else if (GET_CODE (op0) == MULT) | |
2092 | { | |
0a56ad62 | 2093 | if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict) |
ba8ab355 JW |
2094 | && SCALE_TERM_P (XEXP (op0, 1)))) |
2095 | return 0; | |
2096 | ||
0a56ad62 JW |
2097 | if (RTX_OK_FOR_BASE_P (op1, strict)) |
2098 | return 1; | |
ba8ab355 JW |
2099 | else if (CONSTANT_P (op1)) |
2100 | return 1; | |
2101 | else | |
2102 | return 0; | |
2103 | } | |
2104 | else | |
2105 | return 0; | |
2106 | } | |
2107 | else if (GET_CODE (addr) == MULT) | |
2108 | { | |
2109 | if (! TARGET_COMPLEX_ADDR && ! reload_completed) | |
2110 | return 0; | |
2111 | ||
0a56ad62 | 2112 | return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict) |
ba8ab355 JW |
2113 | && SCALE_TERM_P (XEXP (addr, 1))); |
2114 | } | |
2115 | else | |
2116 | return 0; | |
2117 | } | |
2118 | ||
2119 | /* Try machine-dependent ways of modifying an illegitimate address | |
2120 | to be legitimate. If we find one, return the new, valid address. | |
2121 | This macro is used in only one place: `memory_address' in explow.c. | |
2122 | ||
2123 | This converts some non-canonical addresses to canonical form so they | |
2124 | can be recognized. */ | |
2125 | ||
2126 | rtx | |
2127 | legitimize_address (x, oldx, mode) | |
2128 | register rtx x; | |
2129 | register rtx oldx; | |
2130 | enum machine_mode mode; | |
2131 | { | |
2132 | if (GET_CODE (x) == SYMBOL_REF) | |
2133 | { | |
2134 | abort (); | |
2135 | x = copy_to_reg (x); | |
2136 | } | |
2137 | ||
2138 | if (! TARGET_COMPLEX_ADDR && ! reload_completed) | |
2139 | return x; | |
2140 | ||
2141 | /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) | |
2142 | into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be | |
2143 | created by virtual register instantiation, register elimination, and | |
2144 | similar optimizations. */ | |
2145 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT | |
2146 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
c5c76735 JL |
2147 | x = gen_rtx_PLUS (Pmode, |
2148 | gen_rtx_PLUS (Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), | |
2149 | XEXP (XEXP (x, 1), 1)); | |
ba8ab355 JW |
2150 | |
2151 | /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) | |
2152 | into (plus (plus (mult (reg) (const)) (reg)) (const)). */ | |
2153 | else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS | |
2154 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
2155 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS | |
2156 | && CONSTANT_P (XEXP (x, 1))) | |
2157 | { | |
2158 | rtx constant, other; | |
2159 | ||
2160 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2161 | { | |
2162 | constant = XEXP (x, 1); | |
2163 | other = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
2164 | } | |
2165 | else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) | |
2166 | { | |
2167 | constant = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
2168 | other = XEXP (x, 1); | |
2169 | } | |
2170 | else | |
2171 | constant = 0; | |
2172 | ||
2173 | if (constant) | |
c5c76735 JL |
2174 | x = gen_rtx_PLUS (Pmode, |
2175 | gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0), | |
2176 | XEXP (XEXP (XEXP (x, 0), 1), 0)), | |
2177 | plus_constant (other, INTVAL (constant))); | |
ba8ab355 JW |
2178 | } |
2179 | ||
2180 | return x; | |
2181 | } | |
2182 | \f | |
2183 | #if 0 | |
2184 | /* Return the most stringent alignment that we are willing to consider | |
2185 | objects of size SIZE and known alignment ALIGN as having. */ | |
2186 | ||
2187 | int | |
2188 | i960_alignment (size, align) | |
2189 | int size; | |
2190 | int align; | |
2191 | { | |
2192 | int i; | |
2193 | ||
2194 | if (! TARGET_STRICT_ALIGN) | |
2195 | if (TARGET_IC_COMPAT2_0 || align >= 4) | |
2196 | { | |
2197 | i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; | |
2198 | if (i > align) | |
2199 | align = i; | |
2200 | } | |
2201 | ||
2202 | return align; | |
2203 | } | |
2204 | #endif | |
2205 | \f | |
ba8ab355 | 2206 | |
2129b081 JW |
2207 | int |
2208 | hard_regno_mode_ok (regno, mode) | |
2209 | int regno; | |
2210 | enum machine_mode mode; | |
2211 | { | |
2212 | if (regno < 32) | |
2213 | { | |
2214 | switch (mode) | |
2215 | { | |
2216 | case CCmode: case CC_UNSmode: case CC_CHKmode: | |
2217 | return 0; | |
ba8ab355 | 2218 | |
2129b081 JW |
2219 | case DImode: case DFmode: |
2220 | return (regno & 1) == 0; | |
ba8ab355 | 2221 | |
2129b081 JW |
2222 | case TImode: case XFmode: |
2223 | return (regno & 3) == 0; | |
ba8ab355 | 2224 | |
2129b081 JW |
2225 | default: |
2226 | return 1; | |
2227 | } | |
2228 | } | |
2229 | else if (regno >= 32 && regno < 36) | |
2230 | { | |
2231 | switch (mode) | |
2232 | { | |
2233 | case SFmode: case DFmode: case XFmode: | |
2234 | case SCmode: case DCmode: | |
2235 | return 1; | |
ba8ab355 | 2236 | |
2129b081 JW |
2237 | default: |
2238 | return 0; | |
2239 | } | |
2240 | } | |
2241 | else if (regno == 36) | |
2242 | { | |
2243 | switch (mode) | |
2244 | { | |
2245 | case CCmode: case CC_UNSmode: case CC_CHKmode: | |
2246 | return 1; | |
ba8ab355 | 2247 | |
2129b081 JW |
2248 | default: |
2249 | return 0; | |
2250 | } | |
2251 | } | |
2252 | else if (regno == 37) | |
2253 | return 0; | |
ba8ab355 | 2254 | |
2129b081 JW |
2255 | abort (); |
2256 | } | |
ba8ab355 JW |
2257 | |
2258 | \f | |
2259 | /* Return the minimum alignment of an expression rtx X in bytes. This takes | |
2260 | advantage of machine specific facts, such as knowing that the frame pointer | |
2261 | is always 16 byte aligned. */ | |
2262 | ||
2263 | int | |
2264 | i960_expr_alignment (x, size) | |
2265 | rtx x; | |
2266 | int size; | |
2267 | { | |
2268 | int align = 1; | |
2269 | ||
2270 | if (x == 0) | |
2271 | return 1; | |
2272 | ||
2273 | switch (GET_CODE(x)) | |
2274 | { | |
2275 | case CONST_INT: | |
2276 | align = INTVAL(x); | |
2277 | ||
2278 | if ((align & 0xf) == 0) | |
2279 | align = 16; | |
2280 | else if ((align & 0x7) == 0) | |
2281 | align = 8; | |
2282 | else if ((align & 0x3) == 0) | |
2283 | align = 4; | |
2284 | else if ((align & 0x1) == 0) | |
2285 | align = 2; | |
2286 | else | |
2287 | align = 1; | |
2288 | break; | |
2289 | ||
2290 | case PLUS: | |
2291 | align = MIN (i960_expr_alignment (XEXP (x, 0), size), | |
2292 | i960_expr_alignment (XEXP (x, 1), size)); | |
2293 | break; | |
2294 | ||
2295 | case SYMBOL_REF: | |
2296 | /* If this is a valid program, objects are guaranteed to be | |
2297 | correctly aligned for whatever size the reference actually is. */ | |
2298 | align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT; | |
2299 | break; | |
2300 | ||
2301 | case REG: | |
2302 | if (REGNO (x) == FRAME_POINTER_REGNUM) | |
2303 | align = 16; | |
2304 | break; | |
2305 | ||
2306 | case ASHIFT: | |
ba8ab355 JW |
2307 | align = i960_expr_alignment (XEXP (x, 0)); |
2308 | ||
2309 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2310 | { | |
2311 | align = align << INTVAL (XEXP (x, 1)); | |
2312 | align = MIN (align, 16); | |
2313 | } | |
2314 | break; | |
2315 | ||
2316 | case MULT: | |
2317 | align = (i960_expr_alignment (XEXP (x, 0), size) * | |
2318 | i960_expr_alignment (XEXP (x, 1), size)); | |
2319 | ||
2320 | align = MIN (align, 16); | |
2321 | break; | |
2322 | } | |
2323 | ||
2324 | return align; | |
2325 | } | |
2326 | ||
2327 | /* Return true if it is possible to reference both BASE and OFFSET, which | |
2328 | have alignment at least as great as 4 byte, as if they had alignment valid | |
2329 | for an object of size SIZE. */ | |
2330 | ||
2331 | int | |
2332 | i960_improve_align (base, offset, size) | |
2333 | rtx base; | |
2334 | rtx offset; | |
2335 | int size; | |
2336 | { | |
2337 | int i, j; | |
2338 | ||
2339 | /* We have at least a word reference to the object, so we know it has to | |
2340 | be aligned at least to 4 bytes. */ | |
2341 | ||
2342 | i = MIN (i960_expr_alignment (base, 4), | |
2343 | i960_expr_alignment (offset, 4)); | |
2344 | ||
2345 | i = MAX (i, 4); | |
2346 | ||
2347 | /* We know the size of the request. If strict align is not enabled, we | |
2348 | can guess that the alignment is OK for the requested size. */ | |
2349 | ||
2350 | if (! TARGET_STRICT_ALIGN) | |
2351 | if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i) | |
2352 | i = j; | |
2353 | ||
2354 | return (i >= size); | |
2355 | } | |
2356 | ||
2357 | /* Return true if it is possible to access BASE and OFFSET, which have 4 byte | |
2358 | (SImode) alignment as if they had 16 byte (TImode) alignment. */ | |
2359 | ||
2360 | int | |
2361 | i960_si_ti (base, offset) | |
2362 | rtx base; | |
2363 | rtx offset; | |
2364 | { | |
2365 | return i960_improve_align (base, offset, 16); | |
2366 | } | |
2367 | ||
2368 | /* Return true if it is possible to access BASE and OFFSET, which have 4 byte | |
2369 | (SImode) alignment as if they had 8 byte (DImode) alignment. */ | |
2370 | ||
2371 | int | |
2372 | i960_si_di (base, offset) | |
2373 | rtx base; | |
2374 | rtx offset; | |
2375 | { | |
2376 | return i960_improve_align (base, offset, 8); | |
2377 | } | |
2378 | \f | |
2379 | /* Return raw values of size and alignment (in words) for the data | |
2380 | type being accessed. These values will be rounded by the caller. */ | |
2381 | ||
2382 | static void | |
2383 | i960_arg_size_and_align (mode, type, size_out, align_out) | |
2384 | enum machine_mode mode; | |
2385 | tree type; | |
2386 | int *size_out; | |
2387 | int *align_out; | |
2388 | { | |
2389 | int size, align; | |
2390 | ||
2391 | /* Use formal alignment requirements of type being passed, except make | |
2392 | it at least a word. If we don't have a type, this is a library call, | |
2393 | and the parm has to be of scalar type. In this case, consider its | |
2394 | formal alignment requirement to be its size in words. */ | |
2395 | ||
2396 | if (mode == BLKmode) | |
2397 | size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2398 | else if (mode == VOIDmode) | |
2399 | { | |
2400 | /* End of parm list. */ | |
3a598fbe JL |
2401 | if (type == 0 || TYPE_MODE (type) != VOIDmode) |
2402 | abort (); | |
ba8ab355 JW |
2403 | size = 1; |
2404 | } | |
2405 | else | |
2406 | size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
2407 | ||
2408 | if (type == 0) | |
280fc31e RK |
2409 | { |
2410 | /* ??? This is a hack to properly correct the alignment of XFmode | |
2411 | values without affecting anything else. */ | |
2412 | if (size == 3) | |
2413 | align = 4; | |
2414 | else | |
2415 | align = size; | |
2416 | } | |
ba8ab355 JW |
2417 | else if (TYPE_ALIGN (type) >= BITS_PER_WORD) |
2418 | align = TYPE_ALIGN (type) / BITS_PER_WORD; | |
2419 | else | |
2420 | align = 1; | |
2421 | ||
2422 | *size_out = size; | |
2423 | *align_out = align; | |
2424 | } | |
2425 | ||
2426 | /* On the 80960 the first 12 args are in registers and the rest are pushed. | |
2427 | Any arg that is bigger than 4 words is placed on the stack and all | |
2428 | subsequent arguments are placed on the stack. | |
2429 | ||
2430 | Additionally, parameters with an alignment requirement stronger than | |
280fc31e RK |
2431 | a word must be aligned appropriately. Note that this means that a |
2432 | 64 bit object with a 32 bit alignment is not 64 bit aligned and may be | |
2433 | passed in an odd/even register pair. */ | |
ba8ab355 JW |
2434 | |
2435 | /* Update CUM to advance past an argument described by MODE and TYPE. */ | |
2436 | ||
2437 | void | |
2438 | i960_function_arg_advance (cum, mode, type, named) | |
2439 | CUMULATIVE_ARGS *cum; | |
2440 | enum machine_mode mode; | |
2441 | tree type; | |
2442 | int named; | |
2443 | { | |
2444 | int size, align; | |
2445 | ||
2446 | i960_arg_size_and_align (mode, type, &size, &align); | |
2447 | ||
c25d3f20 | 2448 | if (size > 4 || cum->ca_nstackparms != 0 |
025a8875 | 2449 | || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS |
29008b51 | 2450 | || MUST_PASS_IN_STACK (mode, type)) |
b41ac904 DE |
2451 | { |
2452 | /* Indicate that all the registers are in use, even if all are not, | |
2453 | so va_start will compute the right value. */ | |
2454 | cum->ca_nregparms = NPARM_REGS; | |
2455 | cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size; | |
2456 | } | |
ba8ab355 | 2457 | else |
025a8875 | 2458 | cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size; |
ba8ab355 JW |
2459 | } |
2460 | ||
2461 | /* Return the register that the argument described by MODE and TYPE is | |
2462 | passed in, or else return 0 if it is passed on the stack. */ | |
2463 | ||
2464 | rtx | |
2465 | i960_function_arg (cum, mode, type, named) | |
2466 | CUMULATIVE_ARGS *cum; | |
2467 | enum machine_mode mode; | |
2468 | tree type; | |
2469 | int named; | |
2470 | { | |
2471 | rtx ret; | |
2472 | int size, align; | |
2473 | ||
2474 | i960_arg_size_and_align (mode, type, &size, &align); | |
2475 | ||
c25d3f20 | 2476 | if (size > 4 || cum->ca_nstackparms != 0 |
025a8875 | 2477 | || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS |
29008b51 | 2478 | || MUST_PASS_IN_STACK (mode, type)) |
ba8ab355 | 2479 | { |
025a8875 | 2480 | cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align); |
ba8ab355 JW |
2481 | ret = 0; |
2482 | } | |
2483 | else | |
2484 | { | |
025a8875 | 2485 | cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align); |
c5c76735 | 2486 | ret = gen_rtx_REG (mode, cum->ca_nregparms); |
ba8ab355 JW |
2487 | } |
2488 | ||
2489 | return ret; | |
2490 | } | |
ba8ab355 JW |
2491 | \f |
2492 | /* Floating-point support. */ | |
2493 | ||
37aba850 TG |
2494 | void |
2495 | i960_output_long_double (file, value) | |
2496 | FILE *file; | |
2497 | REAL_VALUE_TYPE value; | |
2498 | { | |
2499 | long value_long[3]; | |
2500 | char dstr[30]; | |
2501 | ||
2502 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long); | |
2503 | REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr); | |
2504 | ||
2505 | fprintf (file, | |
2506 | "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n", | |
2507 | value_long[0], dstr, value_long[1], value_long[2]); | |
2508 | fprintf (file, "\t.word\t0x0\n"); | |
2509 | } | |
2510 | ||
ba8ab355 JW |
2511 | void |
2512 | i960_output_double (file, value) | |
2513 | FILE *file; | |
ca01dc12 | 2514 | REAL_VALUE_TYPE value; |
ba8ab355 | 2515 | { |
bd657ba5 | 2516 | long value_long[2]; |
1aa8bf84 TG |
2517 | char dstr[30]; |
2518 | ||
bd657ba5 | 2519 | REAL_VALUE_TO_TARGET_DOUBLE (value, value_long); |
1aa8bf84 | 2520 | REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr); |
bd657ba5 | 2521 | |
1aa8bf84 TG |
2522 | fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n", |
2523 | value_long[0], dstr, value_long[1]); | |
ba8ab355 | 2524 | } |
ca01dc12 | 2525 | |
ba8ab355 JW |
2526 | void |
2527 | i960_output_float (file, value) | |
2528 | FILE *file; | |
ca01dc12 | 2529 | REAL_VALUE_TYPE value; |
ba8ab355 | 2530 | { |
bd657ba5 | 2531 | long value_long; |
1aa8bf84 TG |
2532 | char dstr[30]; |
2533 | ||
bd657ba5 | 2534 | REAL_VALUE_TO_TARGET_SINGLE (value, value_long); |
1aa8bf84 | 2535 | REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr); |
bd657ba5 | 2536 | |
1aa8bf84 | 2537 | fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr); |
ba8ab355 JW |
2538 | } |
2539 | \f | |
2540 | /* Return the number of bits that an object of size N bytes is aligned to. */ | |
2541 | ||
2542 | int | |
2543 | i960_object_bytes_bitalign (n) | |
2544 | int n; | |
2545 | { | |
2546 | if (n > 8) n = 128; | |
2547 | else if (n > 4) n = 64; | |
2548 | else if (n > 2) n = 32; | |
2549 | else if (n > 1) n = 16; | |
2550 | else n = 8; | |
2551 | ||
2552 | return n; | |
2553 | } | |
2554 | ||
c9040e2c ILT |
2555 | /* Compute the alignment for an aggregate type TSIZE. |
2556 | Alignment is MAX (greatest member alignment, | |
2557 | MIN (pragma align, structure size alignment)). */ | |
ba8ab355 JW |
2558 | |
2559 | int | |
2560 | i960_round_align (align, tsize) | |
2561 | int align; | |
2562 | tree tsize; | |
2563 | { | |
c9040e2c | 2564 | int new_align; |
b676e9e2 | 2565 | |
ba8ab355 JW |
2566 | if (TREE_CODE (tsize) != INTEGER_CST) |
2567 | return align; | |
2568 | ||
c9040e2c ILT |
2569 | new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize) |
2570 | / BITS_PER_UNIT); | |
2571 | /* Handle #pragma align. */ | |
2572 | if (new_align > i960_maxbitalignment) | |
2573 | new_align = i960_maxbitalignment; | |
2574 | ||
2575 | if (align < new_align) | |
2576 | align = new_align; | |
2577 | ||
ba8ab355 JW |
2578 | return align; |
2579 | } | |
2580 | \f | |
2581 | /* Do any needed setup for a varargs function. For the i960, we must | |
2296cba3 | 2582 | create a register parameter block if one doesn't exist, and then copy |
ba8ab355 JW |
2583 | all register parameters to memory. */ |
2584 | ||
2585 | void | |
2586 | i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) | |
2587 | CUMULATIVE_ARGS *cum; | |
2588 | enum machine_mode mode; | |
2589 | tree type; | |
2590 | int *pretend_size; | |
2591 | int no_rtl; | |
2592 | { | |
b41ac904 DE |
2593 | /* Note: for a varargs fn with only a va_alist argument, this is 0. */ |
2594 | int first_reg = cum->ca_nregparms; | |
ba8ab355 | 2595 | |
b41ac904 DE |
2596 | /* Copy only unnamed register arguments to memory. If there are |
2597 | any stack parms, there are no unnamed arguments in registers, and | |
2598 | an argument block was already allocated by the caller. | |
2599 | Remember that any arg bigger than 4 words is passed on the stack as | |
2600 | are all subsequent args. | |
2601 | ||
2602 | If there are no stack arguments but there are exactly NPARM_REGS | |
2603 | registers, either there were no extra arguments or the caller | |
2604 | allocated an argument block. */ | |
2605 | ||
2606 | if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl) | |
2607 | { | |
2608 | rtx label = gen_label_rtx (); | |
2609 | rtx regblock; | |
2610 | ||
2611 | /* If arg_pointer_rtx == 0, no arguments were passed on the stack | |
2612 | and we need to allocate a chunk to save the registers (if any | |
2613 | arguments were passed on the stack the caller would allocate the | |
2614 | 48 bytes as well). We must allocate all 48 bytes (12*4) because | |
2615 | va_start assumes it. */ | |
2616 | emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx)); | |
2617 | emit_jump_insn (gen_bne (label)); | |
c5c76735 JL |
2618 | emit_insn (gen_rtx_SET (VOIDmode, arg_pointer_rtx, |
2619 | stack_pointer_rtx)); | |
2620 | emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
2621 | memory_address (SImode, | |
2622 | plus_constant (stack_pointer_rtx, | |
2623 | 48)))); | |
b41ac904 DE |
2624 | emit_label (label); |
2625 | ||
2626 | /* ??? Note that we unnecessarily store one extra register for stdarg | |
c5c76735 JL |
2627 | fns. We could optimize this, but it's kept as for now. */ |
2628 | regblock = gen_rtx_MEM (BLKmode, | |
b41ac904 DE |
2629 | plus_constant (arg_pointer_rtx, |
2630 | first_reg * 4)); | |
c2749e2d | 2631 | MEM_ALIAS_SET (regblock) = get_varargs_alias_set (); |
b41ac904 DE |
2632 | move_block_from_reg (first_reg, regblock, |
2633 | NPARM_REGS - first_reg, | |
2634 | (NPARM_REGS - first_reg) * UNITS_PER_WORD); | |
ba8ab355 JW |
2635 | } |
2636 | } | |
2637 | ||
c2749e2d RH |
2638 | /* Define the `__builtin_va_list' type for the ABI. */ |
2639 | ||
2640 | tree | |
2641 | i960_build_va_list () | |
2642 | { | |
2643 | return build_array_type (unsigned_type_node, | |
2644 | build_index_type (size_one_node)); | |
2645 | } | |
2646 | ||
2647 | /* Implement `va_start' for varargs and stdarg. */ | |
2648 | ||
2649 | void | |
2650 | i960_va_start (stdarg_p, valist, nextarg) | |
2651 | int stdarg_p ATTRIBUTE_UNUSED; | |
2652 | tree valist; | |
2653 | rtx nextarg ATTRIBUTE_UNUSED; | |
2654 | { | |
2655 | tree d, s, t; | |
2656 | ||
2657 | s = make_tree (unsigned_type_node, arg_pointer_rtx); | |
2658 | d = build (ARRAY_REF, unsigned_type_node, valist, size_zero_node); | |
2659 | t = build (MODIFY_EXPR, unsigned_type_node, d, s); | |
2660 | TREE_SIDE_EFFECTS (t) = 1; | |
2661 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2662 | ||
2663 | s = build_int_2 ((current_function_args_info.ca_nregparms | |
2664 | + current_function_args_info.ca_nstackparms) * 4, 0); | |
2665 | d = build (ARRAY_REF, unsigned_type_node, valist, size_one_node); | |
2666 | t = build (MODIFY_EXPR, unsigned_type_node, d, s); | |
2667 | TREE_SIDE_EFFECTS (t) = 1; | |
2668 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2669 | } | |
2670 | ||
2671 | /* Implement `va_arg'. */ | |
2672 | ||
2673 | rtx | |
2674 | i960_va_arg (valist, type) | |
2675 | tree valist, type; | |
2676 | { | |
2677 | HOST_WIDE_INT siz, ali; | |
2678 | tree base, num, pad, next, this, t1, t2, int48; | |
2679 | rtx addr_rtx; | |
2680 | ||
2681 | base = build (ARRAY_REF, unsigned_type_node, valist, size_zero_node); | |
2682 | num = build (ARRAY_REF, unsigned_type_node, valist, size_one_node); | |
2683 | ||
2684 | /* Round up sizeof(type) to a word. */ | |
2685 | siz = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; | |
2686 | ||
2687 | /* Round up alignment to a word. */ | |
2688 | ali = TYPE_ALIGN (type); | |
2689 | if (ali < BITS_PER_WORD) | |
2690 | ali = BITS_PER_WORD; | |
2691 | ali /= BITS_PER_UNIT; | |
2692 | ||
2693 | /* Align NUM appropriate for the argument. */ | |
2694 | pad = fold (build (PLUS_EXPR, unsigned_type_node, num, | |
2695 | build_int_2 (ali - 1, 0))); | |
2696 | pad = fold (build (BIT_AND_EXPR, unsigned_type_node, pad, | |
2697 | build_int_2 (-ali, -1))); | |
2698 | pad = save_expr (pad); | |
2699 | ||
2700 | /* Increment VPAD past this argument. */ | |
2701 | next = fold (build (PLUS_EXPR, unsigned_type_node, pad, | |
2702 | build_int_2 (siz, 0))); | |
2703 | next = save_expr (next); | |
2704 | ||
2705 | /* Find the offset for the current argument. Mind peculiar overflow | |
2706 | from registers to stack. */ | |
2707 | int48 = build_int_2 (48, 0); | |
2708 | if (siz > 16) | |
2709 | t2 = integer_one_node; | |
2710 | else | |
2711 | t2 = fold (build (GT_EXPR, integer_type_node, next, int48)); | |
2712 | t1 = fold (build (LE_EXPR, integer_type_node, num, int48)); | |
2713 | t1 = fold (build (TRUTH_AND_EXPR, integer_type_node, t1, t2)); | |
2714 | this = fold (build (COND_EXPR, unsigned_type_node, t1, int48, pad)); | |
2715 | ||
2716 | /* Find the address for the current argument. */ | |
2717 | t1 = fold (build (PLUS_EXPR, unsigned_type_node, base, this)); | |
2718 | t1 = build1 (NOP_EXPR, ptr_type_node, t1); | |
2719 | addr_rtx = expand_expr (t1, NULL_RTX, Pmode, EXPAND_NORMAL); | |
2720 | ||
2721 | /* Increment NUM. */ | |
2722 | t1 = build (MODIFY_EXPR, unsigned_type_node, num, next); | |
2723 | TREE_SIDE_EFFECTS (t1) = 1; | |
2724 | expand_expr (t1, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2725 | ||
2726 | return addr_rtx; | |
2727 | } | |
2728 | ||
ba8ab355 JW |
2729 | /* Calculate the final size of the reg parm stack space for the current |
2730 | function, based on how many bytes would be allocated on the stack. */ | |
2731 | ||
2732 | int | |
2733 | i960_final_reg_parm_stack_space (const_size, var_size) | |
2734 | int const_size; | |
2735 | tree var_size; | |
2736 | { | |
2737 | if (var_size || const_size > 48) | |
2738 | return 48; | |
2739 | else | |
2740 | return 0; | |
2741 | } | |
2742 | ||
2743 | /* Calculate the size of the reg parm stack space. This is a bit complicated | |
2744 | on the i960. */ | |
2745 | ||
2746 | int | |
2747 | i960_reg_parm_stack_space (fndecl) | |
2748 | tree fndecl; | |
2749 | { | |
2750 | /* In this case, we are called from emit_library_call, and we don't need | |
2751 | to pretend we have more space for parameters than what's apparent. */ | |
2752 | if (fndecl == 0) | |
2753 | return 0; | |
2754 | ||
2755 | /* In this case, we are called from locate_and_pad_parms when we're | |
2756 | not IN_REGS, so we have an arg block. */ | |
2757 | if (fndecl != current_function_decl) | |
2758 | return 48; | |
2759 | ||
2760 | /* Otherwise, we have an arg block if the current function has more than | |
2761 | 48 bytes of parameters. */ | |
c25d3f20 | 2762 | if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl)) |
ba8ab355 JW |
2763 | return 48; |
2764 | else | |
2765 | return 0; | |
2766 | } | |
2767 | \f | |
2768 | /* Return the register class of a scratch register needed to copy IN into | |
2769 | or out of a register in CLASS in MODE. If it can be done directly, | |
2770 | NO_REGS is returned. */ | |
2771 | ||
2772 | enum reg_class | |
2773 | secondary_reload_class (class, mode, in) | |
2774 | enum reg_class class; | |
2775 | enum machine_mode mode; | |
2776 | rtx in; | |
2777 | { | |
2778 | int regno = -1; | |
2779 | ||
2780 | if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG) | |
2781 | regno = true_regnum (in); | |
2782 | ||
2783 | /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put | |
2784 | LOCAL_OR_GLOBAL_REGS into anything. */ | |
2785 | if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS | |
2786 | || class == GLOBAL_REGS || (regno >= 0 && regno < 32)) | |
2787 | return NO_REGS; | |
2788 | ||
2789 | /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */ | |
2790 | if (class == FP_REGS | |
4c1dfa8f | 2791 | && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER) |
ba8ab355 JW |
2792 | || in == CONST0_RTX (mode) || in == CONST1_RTX (mode))) |
2793 | return NO_REGS; | |
2794 | ||
2795 | return LOCAL_OR_GLOBAL_REGS; | |
2796 | } | |
2797 | \f | |
ba8ab355 JW |
2798 | /* Look at the opcode P, and set i96_last_insn_type to indicate which |
2799 | function unit it executed on. */ | |
2800 | ||
2801 | /* ??? This would make more sense as an attribute. */ | |
2802 | ||
2803 | void | |
2804 | i960_scan_opcode (p) | |
2805 | char *p; | |
2806 | { | |
2807 | switch (*p) | |
2808 | { | |
2809 | case 'a': | |
2810 | case 'd': | |
2811 | case 'e': | |
2812 | case 'm': | |
2813 | case 'n': | |
2814 | case 'o': | |
2815 | case 'r': | |
2816 | /* Ret is not actually of type REG, but it won't matter, because no | |
2817 | insn will ever follow it. */ | |
2818 | case 'u': | |
2819 | case 'x': | |
2820 | i960_last_insn_type = I_TYPE_REG; | |
2821 | break; | |
2822 | ||
2823 | case 'b': | |
2824 | if (p[1] == 'x' || p[3] == 'x') | |
2825 | i960_last_insn_type = I_TYPE_MEM; | |
2826 | i960_last_insn_type = I_TYPE_CTRL; | |
2827 | break; | |
2828 | ||
2829 | case 'f': | |
2830 | case 't': | |
2831 | i960_last_insn_type = I_TYPE_CTRL; | |
2832 | break; | |
2833 | ||
2834 | case 'c': | |
2835 | if (p[1] == 'a') | |
2836 | { | |
2837 | if (p[4] == 'x') | |
2838 | i960_last_insn_type = I_TYPE_MEM; | |
2839 | else | |
2840 | i960_last_insn_type = I_TYPE_CTRL; | |
2841 | } | |
2842 | else if (p[1] == 'm') | |
2843 | { | |
2844 | if (p[3] == 'd') | |
2845 | i960_last_insn_type = I_TYPE_REG; | |
2846 | else if (p[4] == 'b' || p[4] == 'j') | |
2847 | i960_last_insn_type = I_TYPE_CTRL; | |
2848 | else | |
2849 | i960_last_insn_type = I_TYPE_REG; | |
2850 | } | |
2851 | else | |
2852 | i960_last_insn_type = I_TYPE_REG; | |
2853 | break; | |
2854 | ||
2855 | case 'l': | |
2856 | i960_last_insn_type = I_TYPE_MEM; | |
2857 | break; | |
2858 | ||
2859 | case 's': | |
2860 | if (p[1] == 't') | |
2861 | i960_last_insn_type = I_TYPE_MEM; | |
2862 | else | |
2863 | i960_last_insn_type = I_TYPE_REG; | |
2864 | break; | |
2865 | } | |
2866 | } |