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c65ebc55 | 1 | /* Definitions of target machine for GNU compiler. |
5624e564 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
c65ebc55 | 3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
9c808aad | 4 | David Mosberger <davidm@hpl.hp.com>. |
c65ebc55 | 5 | |
3bed2930 | 6 | This file is part of GCC. |
c65ebc55 | 7 | |
3bed2930 | 8 | GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
11 | any later version. |
12 | ||
3bed2930 | 13 | GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c65ebc55 | 21 | |
c65ebc55 | 22 | #include "config.h" |
ed9ccd8a | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
c65ebc55 | 26 | #include "rtl.h" |
40e23961 MC |
27 | #include "hash-set.h" |
28 | #include "machmode.h" | |
29 | #include "vec.h" | |
30 | #include "double-int.h" | |
31 | #include "input.h" | |
32 | #include "alias.h" | |
33 | #include "symtab.h" | |
34 | #include "wide-int.h" | |
35 | #include "inchash.h" | |
c65ebc55 | 36 | #include "tree.h" |
40e23961 | 37 | #include "fold-const.h" |
d8a2d370 DN |
38 | #include "stringpool.h" |
39 | #include "stor-layout.h" | |
40 | #include "calls.h" | |
41 | #include "varasm.h" | |
c65ebc55 JW |
42 | #include "regs.h" |
43 | #include "hard-reg-set.h" | |
c65ebc55 JW |
44 | #include "insn-config.h" |
45 | #include "conditions.h" | |
c65ebc55 JW |
46 | #include "output.h" |
47 | #include "insn-attr.h" | |
48 | #include "flags.h" | |
49 | #include "recog.h" | |
36566b39 PK |
50 | #include "hashtab.h" |
51 | #include "function.h" | |
52 | #include "statistics.h" | |
53 | #include "real.h" | |
54 | #include "fixed-value.h" | |
55 | #include "expmed.h" | |
56 | #include "dojump.h" | |
57 | #include "explow.h" | |
58 | #include "emit-rtl.h" | |
59 | #include "stmt.h" | |
c65ebc55 | 60 | #include "expr.h" |
b0710fe1 | 61 | #include "insn-codes.h" |
e78d8e51 | 62 | #include "optabs.h" |
c65ebc55 | 63 | #include "except.h" |
c65ebc55 | 64 | #include "ggc.h" |
60393bbc AM |
65 | #include "predict.h" |
66 | #include "dominance.h" | |
67 | #include "cfg.h" | |
68 | #include "cfgrtl.h" | |
69 | #include "cfganal.h" | |
70 | #include "lcm.h" | |
71 | #include "cfgbuild.h" | |
72 | #include "cfgcleanup.h" | |
c65ebc55 | 73 | #include "basic-block.h" |
f2972bf8 | 74 | #include "libfuncs.h" |
718f9c0f | 75 | #include "diagnostic-core.h" |
2130b7fb | 76 | #include "sched-int.h" |
eced69b5 | 77 | #include "timevar.h" |
672a6f42 NB |
78 | #include "target.h" |
79 | #include "target-def.h" | |
7b84aac0 | 80 | #include "common/common-target.h" |
98d2b17e | 81 | #include "tm_p.h" |
3a4f280b | 82 | #include "hash-table.h" |
08744705 | 83 | #include "langhooks.h" |
2fb9a547 AM |
84 | #include "tree-ssa-alias.h" |
85 | #include "internal-fn.h" | |
86 | #include "gimple-fold.h" | |
87 | #include "tree-eh.h" | |
88 | #include "gimple-expr.h" | |
89 | #include "is-a.h" | |
18f429e2 | 90 | #include "gimple.h" |
45b0be94 | 91 | #include "gimplify.h" |
4de67c26 | 92 | #include "intl.h" |
6fb5fa3c | 93 | #include "df.h" |
658f32fd | 94 | #include "debug.h" |
bb83aa4b | 95 | #include "params.h" |
6fb5fa3c | 96 | #include "dbgcnt.h" |
13f70342 | 97 | #include "tm-constrs.h" |
388092d5 | 98 | #include "sel-sched.h" |
69e18c09 | 99 | #include "reload.h" |
96e45421 | 100 | #include "opts.h" |
7ee2468b | 101 | #include "dumpfile.h" |
9b2b7279 | 102 | #include "builtins.h" |
c65ebc55 JW |
103 | |
104 | /* This is used for communication between ASM_OUTPUT_LABEL and | |
105 | ASM_OUTPUT_LABELREF. */ | |
106 | int ia64_asm_output_label = 0; | |
107 | ||
c65ebc55 | 108 | /* Register names for ia64_expand_prologue. */ |
3b572406 | 109 | static const char * const ia64_reg_numbers[96] = |
c65ebc55 JW |
110 | { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
111 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
112 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
113 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
114 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
115 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
116 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
117 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
118 | "r96", "r97", "r98", "r99", "r100","r101","r102","r103", | |
119 | "r104","r105","r106","r107","r108","r109","r110","r111", | |
120 | "r112","r113","r114","r115","r116","r117","r118","r119", | |
121 | "r120","r121","r122","r123","r124","r125","r126","r127"}; | |
122 | ||
123 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 124 | static const char * const ia64_input_reg_names[8] = |
c65ebc55 JW |
125 | { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" }; |
126 | ||
127 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 128 | static const char * const ia64_local_reg_names[80] = |
c65ebc55 JW |
129 | { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", |
130 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", | |
131 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", | |
132 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", | |
133 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", | |
134 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", | |
135 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", | |
136 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", | |
137 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", | |
138 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" }; | |
139 | ||
140 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 141 | static const char * const ia64_output_reg_names[8] = |
c65ebc55 JW |
142 | { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" }; |
143 | ||
c65ebc55 JW |
144 | /* Variables which are this size or smaller are put in the sdata/sbss |
145 | sections. */ | |
146 | ||
3b572406 | 147 | unsigned int ia64_section_threshold; |
30028c85 VM |
148 | |
149 | /* The following variable is used by the DFA insn scheduler. The value is | |
150 | TRUE if we do insn bundling instead of insn scheduling. */ | |
151 | int bundling_p = 0; | |
152 | ||
6fb5fa3c DB |
153 | enum ia64_frame_regs |
154 | { | |
155 | reg_fp, | |
156 | reg_save_b0, | |
157 | reg_save_pr, | |
158 | reg_save_ar_pfs, | |
159 | reg_save_ar_unat, | |
160 | reg_save_ar_lc, | |
161 | reg_save_gp, | |
162 | number_of_ia64_frame_regs | |
163 | }; | |
164 | ||
599aedd9 RH |
165 | /* Structure to be filled in by ia64_compute_frame_size with register |
166 | save masks and offsets for the current function. */ | |
167 | ||
168 | struct ia64_frame_info | |
169 | { | |
170 | HOST_WIDE_INT total_size; /* size of the stack frame, not including | |
171 | the caller's scratch area. */ | |
172 | HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */ | |
173 | HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */ | |
174 | HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */ | |
175 | HARD_REG_SET mask; /* mask of saved registers. */ | |
9c808aad | 176 | unsigned int gr_used_mask; /* mask of registers in use as gr spill |
599aedd9 RH |
177 | registers or long-term scratches. */ |
178 | int n_spilled; /* number of spilled registers. */ | |
6fb5fa3c | 179 | int r[number_of_ia64_frame_regs]; /* Frame related registers. */ |
599aedd9 RH |
180 | int n_input_regs; /* number of input registers used. */ |
181 | int n_local_regs; /* number of local registers used. */ | |
182 | int n_output_regs; /* number of output registers used. */ | |
183 | int n_rotate_regs; /* number of rotating registers used. */ | |
184 | ||
185 | char need_regstk; /* true if a .regstk directive needed. */ | |
186 | char initialized; /* true if the data is finalized. */ | |
187 | }; | |
188 | ||
189 | /* Current frame information calculated by ia64_compute_frame_size. */ | |
190 | static struct ia64_frame_info current_frame_info; | |
6fb5fa3c DB |
191 | /* The actual registers that are emitted. */ |
192 | static int emitted_frame_related_regs[number_of_ia64_frame_regs]; | |
3b572406 | 193 | \f |
9c808aad | 194 | static int ia64_first_cycle_multipass_dfa_lookahead (void); |
ce1ce33a | 195 | static void ia64_dependencies_evaluation_hook (rtx_insn *, rtx_insn *); |
9c808aad AJ |
196 | static void ia64_init_dfa_pre_cycle_insn (void); |
197 | static rtx ia64_dfa_pre_cycle_insn (void); | |
ac44248e DM |
198 | static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *, int); |
199 | static int ia64_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *); | |
048d0d36 | 200 | static void ia64_h_i_d_extended (void); |
388092d5 AB |
201 | static void * ia64_alloc_sched_context (void); |
202 | static void ia64_init_sched_context (void *, bool); | |
203 | static void ia64_set_sched_context (void *); | |
204 | static void ia64_clear_sched_context (void *); | |
205 | static void ia64_free_sched_context (void *); | |
ef4bddc2 | 206 | static int ia64_mode_to_int (machine_mode); |
048d0d36 | 207 | static void ia64_set_sched_flags (spec_info_t); |
ac44248e DM |
208 | static ds_t ia64_get_insn_spec_ds (rtx_insn *); |
209 | static ds_t ia64_get_insn_checked_ds (rtx_insn *); | |
388092d5 | 210 | static bool ia64_skip_rtx_p (const_rtx); |
ac44248e | 211 | static int ia64_speculate_insn (rtx_insn *, ds_t, rtx *); |
8e90de43 | 212 | static bool ia64_needs_block_p (ds_t); |
ac44248e | 213 | static rtx ia64_gen_spec_check (rtx_insn *, rtx_insn *, ds_t); |
048d0d36 MK |
214 | static int ia64_spec_check_p (rtx); |
215 | static int ia64_spec_check_src_p (rtx); | |
9c808aad AJ |
216 | static rtx gen_tls_get_addr (void); |
217 | static rtx gen_thread_pointer (void); | |
6fb5fa3c | 218 | static int find_gr_spill (enum ia64_frame_regs, int); |
9c808aad AJ |
219 | static int next_scratch_gr_reg (void); |
220 | static void mark_reg_gr_used_mask (rtx, void *); | |
221 | static void ia64_compute_frame_size (HOST_WIDE_INT); | |
222 | static void setup_spill_pointers (int, rtx, HOST_WIDE_INT); | |
223 | static void finish_spill_pointers (void); | |
224 | static rtx spill_restore_mem (rtx, HOST_WIDE_INT); | |
225 | static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx); | |
226 | static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT); | |
227 | static rtx gen_movdi_x (rtx, rtx, rtx); | |
228 | static rtx gen_fr_spill_x (rtx, rtx, rtx); | |
229 | static rtx gen_fr_restore_x (rtx, rtx, rtx); | |
230 | ||
930572b9 | 231 | static void ia64_option_override (void); |
7b5cbb57 | 232 | static bool ia64_can_eliminate (const int, const int); |
ef4bddc2 RS |
233 | static machine_mode hfa_element_mode (const_tree, bool); |
234 | static void ia64_setup_incoming_varargs (cumulative_args_t, machine_mode, | |
351a758b | 235 | tree, int *, int); |
ef4bddc2 | 236 | static int ia64_arg_partial_bytes (cumulative_args_t, machine_mode, |
78a52f11 | 237 | tree, bool); |
ef4bddc2 | 238 | static rtx ia64_function_arg_1 (cumulative_args_t, machine_mode, |
ffa88471 | 239 | const_tree, bool, bool); |
ef4bddc2 | 240 | static rtx ia64_function_arg (cumulative_args_t, machine_mode, |
ffa88471 | 241 | const_tree, bool); |
d5cc9181 | 242 | static rtx ia64_function_incoming_arg (cumulative_args_t, |
ef4bddc2 RS |
243 | machine_mode, const_tree, bool); |
244 | static void ia64_function_arg_advance (cumulative_args_t, machine_mode, | |
ffa88471 | 245 | const_tree, bool); |
ef4bddc2 | 246 | static unsigned int ia64_function_arg_boundary (machine_mode, |
c2ed6cf8 | 247 | const_tree); |
9c808aad | 248 | static bool ia64_function_ok_for_sibcall (tree, tree); |
586de218 | 249 | static bool ia64_return_in_memory (const_tree, const_tree); |
ba90d838 | 250 | static rtx ia64_function_value (const_tree, const_tree, bool); |
ef4bddc2 | 251 | static rtx ia64_libcall_value (machine_mode, const_rtx); |
ba90d838 | 252 | static bool ia64_function_value_regno_p (const unsigned int); |
ef4bddc2 | 253 | static int ia64_register_move_cost (machine_mode, reg_class_t, |
c21fc181 | 254 | reg_class_t); |
ef4bddc2 | 255 | static int ia64_memory_move_cost (machine_mode mode, reg_class_t, |
69e18c09 | 256 | bool); |
68f932c4 | 257 | static bool ia64_rtx_costs (rtx, int, int, int, int *, bool); |
215b063c | 258 | static int ia64_unspec_may_trap_p (const_rtx, unsigned); |
9c808aad AJ |
259 | static void fix_range (const char *); |
260 | static struct machine_function * ia64_init_machine_status (void); | |
261 | static void emit_insn_group_barriers (FILE *); | |
262 | static void emit_all_insn_group_barriers (FILE *); | |
263 | static void final_emit_insn_group_barriers (FILE *); | |
264 | static void emit_predicate_relation_info (void); | |
265 | static void ia64_reorg (void); | |
3101faab | 266 | static bool ia64_in_small_data_p (const_tree); |
658f32fd | 267 | static void process_epilogue (FILE *, rtx, bool, bool); |
9c808aad | 268 | |
9c808aad AJ |
269 | static bool ia64_assemble_integer (rtx, unsigned int, int); |
270 | static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT); | |
271 | static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
272 | static void ia64_output_function_end_prologue (FILE *); | |
273 | ||
5e50b799 AS |
274 | static void ia64_print_operand (FILE *, rtx, int); |
275 | static void ia64_print_operand_address (FILE *, rtx); | |
276 | static bool ia64_print_operand_punct_valid_p (unsigned char code); | |
277 | ||
9c808aad | 278 | static int ia64_issue_rate (void); |
ac44248e | 279 | static int ia64_adjust_cost_2 (rtx_insn *, int, rtx_insn *, int, dw_t); |
9c808aad | 280 | static void ia64_sched_init (FILE *, int, int); |
048d0d36 MK |
281 | static void ia64_sched_init_global (FILE *, int, int); |
282 | static void ia64_sched_finish_global (FILE *, int); | |
9c808aad | 283 | static void ia64_sched_finish (FILE *, int); |
ce1ce33a DM |
284 | static int ia64_dfa_sched_reorder (FILE *, int, rtx_insn **, int *, int, int); |
285 | static int ia64_sched_reorder (FILE *, int, rtx_insn **, int *, int); | |
286 | static int ia64_sched_reorder2 (FILE *, int, rtx_insn **, int *, int); | |
ac44248e | 287 | static int ia64_variable_issue (FILE *, int, rtx_insn *, int); |
9c808aad | 288 | |
ac44248e | 289 | static void ia64_asm_unwind_emit (FILE *, rtx_insn *); |
a68b5e52 RH |
290 | static void ia64_asm_emit_except_personality (rtx); |
291 | static void ia64_asm_init_sections (void); | |
292 | ||
f0a0390e | 293 | static enum unwind_info_type ia64_debug_unwind_info (void); |
f0a0390e | 294 | |
9c808aad AJ |
295 | static struct bundle_state *get_free_bundle_state (void); |
296 | static void free_bundle_state (struct bundle_state *); | |
297 | static void initiate_bundle_states (void); | |
298 | static void finish_bundle_states (void); | |
9c808aad AJ |
299 | static int insert_bundle_state (struct bundle_state *); |
300 | static void initiate_bundle_state_table (void); | |
301 | static void finish_bundle_state_table (void); | |
302 | static int try_issue_nops (struct bundle_state *, int); | |
303 | static int try_issue_insn (struct bundle_state *, rtx); | |
b32d5189 DM |
304 | static void issue_nops_and_insn (struct bundle_state *, int, rtx_insn *, |
305 | int, int); | |
9c808aad AJ |
306 | static int get_max_pos (state_t); |
307 | static int get_template (state_t, int); | |
308 | ||
b32d5189 | 309 | static rtx_insn *get_next_important_insn (rtx_insn *, rtx_insn *); |
647d790d DM |
310 | static bool important_for_bundling_p (rtx_insn *); |
311 | static bool unknown_for_bundling_p (rtx_insn *); | |
b32d5189 | 312 | static void bundling (FILE *, int, rtx_insn *, rtx_insn *); |
9c808aad AJ |
313 | |
314 | static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
315 | HOST_WIDE_INT, tree); | |
316 | static void ia64_file_start (void); | |
812b587e | 317 | static void ia64_globalize_decl_name (FILE *, tree); |
9c808aad | 318 | |
9b580a0b RH |
319 | static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED; |
320 | static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED; | |
ef4bddc2 | 321 | static section *ia64_select_rtx_section (machine_mode, rtx, |
d6b5193b | 322 | unsigned HOST_WIDE_INT); |
fdbe66f2 EB |
323 | static void ia64_output_dwarf_dtprel (FILE *, int, rtx) |
324 | ATTRIBUTE_UNUSED; | |
abb8b19a | 325 | static unsigned int ia64_section_type_flags (tree, const char *, int); |
1f7aa7cd SE |
326 | static void ia64_init_libfuncs (void) |
327 | ATTRIBUTE_UNUSED; | |
c15c90bb ZW |
328 | static void ia64_hpux_init_libfuncs (void) |
329 | ATTRIBUTE_UNUSED; | |
6bc709c1 L |
330 | static void ia64_sysv4_init_libfuncs (void) |
331 | ATTRIBUTE_UNUSED; | |
738e7b39 RK |
332 | static void ia64_vms_init_libfuncs (void) |
333 | ATTRIBUTE_UNUSED; | |
c252db20 L |
334 | static void ia64_soft_fp_init_libfuncs (void) |
335 | ATTRIBUTE_UNUSED; | |
ef4bddc2 | 336 | static bool ia64_vms_valid_pointer_mode (machine_mode mode) |
f2972bf8 | 337 | ATTRIBUTE_UNUSED; |
30ed9d3d TG |
338 | static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *) |
339 | ATTRIBUTE_UNUSED; | |
a5fe455b | 340 | |
d8def3cf | 341 | static bool ia64_attribute_takes_identifier_p (const_tree); |
a32767e4 | 342 | static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *); |
812b587e | 343 | static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *); |
a32767e4 | 344 | static void ia64_encode_section_info (tree, rtx, int); |
351a758b | 345 | static rtx ia64_struct_value_rtx (tree, int); |
726a989a | 346 | static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
ef4bddc2 RS |
347 | static bool ia64_scalar_mode_supported_p (machine_mode mode); |
348 | static bool ia64_vector_mode_supported_p (machine_mode mode); | |
349 | static bool ia64_libgcc_floating_mode_supported_p (machine_mode mode); | |
350 | static bool ia64_legitimate_constant_p (machine_mode, rtx); | |
351 | static bool ia64_legitimate_address_p (machine_mode, rtx, bool); | |
352 | static bool ia64_cannot_force_const_mem (machine_mode, rtx); | |
3101faab KG |
353 | static const char *ia64_mangle_type (const_tree); |
354 | static const char *ia64_invalid_conversion (const_tree, const_tree); | |
355 | static const char *ia64_invalid_unary_op (int, const_tree); | |
356 | static const char *ia64_invalid_binary_op (int, const_tree, const_tree); | |
ef4bddc2 | 357 | static machine_mode ia64_c_mode_for_suffix (char); |
2a1211e5 | 358 | static void ia64_trampoline_init (rtx, tree, rtx); |
2b7e2984 | 359 | static void ia64_override_options_after_change (void); |
ef4bddc2 | 360 | static bool ia64_member_type_forces_blk (const_tree, machine_mode); |
5c255b57 | 361 | |
b14446e2 | 362 | static tree ia64_builtin_decl (unsigned, bool); |
ab177ad5 AS |
363 | |
364 | static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t); | |
ef4bddc2 | 365 | static machine_mode ia64_get_reg_raw_mode (int regno); |
f16d3f39 JH |
366 | static section * ia64_hpux_function_section (tree, enum node_frequency, |
367 | bool, bool); | |
e6431744 | 368 | |
ef4bddc2 | 369 | static bool ia64_vectorize_vec_perm_const_ok (machine_mode vmode, |
e6431744 RH |
370 | const unsigned char *sel); |
371 | ||
372 | #define MAX_VECT_LEN 8 | |
373 | ||
374 | struct expand_vec_perm_d | |
375 | { | |
376 | rtx target, op0, op1; | |
377 | unsigned char perm[MAX_VECT_LEN]; | |
ef4bddc2 | 378 | machine_mode vmode; |
e6431744 RH |
379 | unsigned char nelt; |
380 | bool one_operand_p; | |
381 | bool testing_p; | |
382 | }; | |
383 | ||
384 | static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d); | |
385 | ||
672a6f42 | 386 | \f |
e6542f4e RH |
387 | /* Table of valid machine attributes. */ |
388 | static const struct attribute_spec ia64_attribute_table[] = | |
389 | { | |
62d784f7 KT |
390 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
391 | affects_type_identity } */ | |
392 | { "syscall_linkage", 0, 0, false, true, true, NULL, false }, | |
393 | { "model", 1, 1, true, false, false, ia64_handle_model_attribute, | |
394 | false }, | |
30ed9d3d | 395 | #if TARGET_ABI_OPEN_VMS |
62d784f7 KT |
396 | { "common_object", 1, 1, true, false, false, |
397 | ia64_vms_common_object_attribute, false }, | |
30ed9d3d | 398 | #endif |
812b587e | 399 | { "version_id", 1, 1, true, false, false, |
62d784f7 KT |
400 | ia64_handle_version_id_attribute, false }, |
401 | { NULL, 0, 0, false, false, false, NULL, false } | |
e6542f4e RH |
402 | }; |
403 | ||
672a6f42 | 404 | /* Initialize the GCC target structure. */ |
91d231cb JM |
405 | #undef TARGET_ATTRIBUTE_TABLE |
406 | #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table | |
672a6f42 | 407 | |
f6155fda SS |
408 | #undef TARGET_INIT_BUILTINS |
409 | #define TARGET_INIT_BUILTINS ia64_init_builtins | |
410 | ||
411 | #undef TARGET_EXPAND_BUILTIN | |
412 | #define TARGET_EXPAND_BUILTIN ia64_expand_builtin | |
413 | ||
b14446e2 SE |
414 | #undef TARGET_BUILTIN_DECL |
415 | #define TARGET_BUILTIN_DECL ia64_builtin_decl | |
416 | ||
301d03af RS |
417 | #undef TARGET_ASM_BYTE_OP |
418 | #define TARGET_ASM_BYTE_OP "\tdata1\t" | |
419 | #undef TARGET_ASM_ALIGNED_HI_OP | |
420 | #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t" | |
421 | #undef TARGET_ASM_ALIGNED_SI_OP | |
422 | #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t" | |
423 | #undef TARGET_ASM_ALIGNED_DI_OP | |
424 | #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t" | |
425 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
426 | #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t" | |
427 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
428 | #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t" | |
429 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
430 | #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t" | |
431 | #undef TARGET_ASM_INTEGER | |
432 | #define TARGET_ASM_INTEGER ia64_assemble_integer | |
433 | ||
930572b9 AS |
434 | #undef TARGET_OPTION_OVERRIDE |
435 | #define TARGET_OPTION_OVERRIDE ia64_option_override | |
436 | ||
08c148a8 NB |
437 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
438 | #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue | |
b4c25db2 NB |
439 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE |
440 | #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue | |
08c148a8 NB |
441 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
442 | #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue | |
443 | ||
5e50b799 AS |
444 | #undef TARGET_PRINT_OPERAND |
445 | #define TARGET_PRINT_OPERAND ia64_print_operand | |
446 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
447 | #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address | |
448 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
449 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p | |
450 | ||
ae46c4e0 RH |
451 | #undef TARGET_IN_SMALL_DATA_P |
452 | #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p | |
453 | ||
388092d5 AB |
454 | #undef TARGET_SCHED_ADJUST_COST_2 |
455 | #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2 | |
c237e94a ZW |
456 | #undef TARGET_SCHED_ISSUE_RATE |
457 | #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate | |
458 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
459 | #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue | |
460 | #undef TARGET_SCHED_INIT | |
461 | #define TARGET_SCHED_INIT ia64_sched_init | |
462 | #undef TARGET_SCHED_FINISH | |
463 | #define TARGET_SCHED_FINISH ia64_sched_finish | |
048d0d36 MK |
464 | #undef TARGET_SCHED_INIT_GLOBAL |
465 | #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global | |
466 | #undef TARGET_SCHED_FINISH_GLOBAL | |
467 | #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global | |
c237e94a ZW |
468 | #undef TARGET_SCHED_REORDER |
469 | #define TARGET_SCHED_REORDER ia64_sched_reorder | |
470 | #undef TARGET_SCHED_REORDER2 | |
471 | #define TARGET_SCHED_REORDER2 ia64_sched_reorder2 | |
c237e94a | 472 | |
30028c85 VM |
473 | #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK |
474 | #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook | |
475 | ||
30028c85 VM |
476 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
477 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead | |
478 | ||
479 | #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN | |
480 | #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn | |
481 | #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN | |
482 | #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn | |
483 | ||
484 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD | |
485 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\ | |
486 | ia64_first_cycle_multipass_dfa_lookahead_guard | |
487 | ||
488 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
489 | #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle | |
490 | ||
048d0d36 MK |
491 | #undef TARGET_SCHED_H_I_D_EXTENDED |
492 | #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended | |
493 | ||
388092d5 AB |
494 | #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT |
495 | #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context | |
496 | ||
497 | #undef TARGET_SCHED_INIT_SCHED_CONTEXT | |
498 | #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context | |
499 | ||
500 | #undef TARGET_SCHED_SET_SCHED_CONTEXT | |
501 | #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context | |
502 | ||
503 | #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT | |
504 | #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context | |
505 | ||
506 | #undef TARGET_SCHED_FREE_SCHED_CONTEXT | |
507 | #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context | |
508 | ||
048d0d36 MK |
509 | #undef TARGET_SCHED_SET_SCHED_FLAGS |
510 | #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags | |
511 | ||
388092d5 AB |
512 | #undef TARGET_SCHED_GET_INSN_SPEC_DS |
513 | #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds | |
514 | ||
515 | #undef TARGET_SCHED_GET_INSN_CHECKED_DS | |
516 | #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds | |
517 | ||
048d0d36 MK |
518 | #undef TARGET_SCHED_SPECULATE_INSN |
519 | #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn | |
520 | ||
521 | #undef TARGET_SCHED_NEEDS_BLOCK_P | |
522 | #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p | |
523 | ||
e855c69d | 524 | #undef TARGET_SCHED_GEN_SPEC_CHECK |
388092d5 | 525 | #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check |
048d0d36 | 526 | |
388092d5 AB |
527 | #undef TARGET_SCHED_SKIP_RTX_P |
528 | #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p | |
529 | ||
599aedd9 RH |
530 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
531 | #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall | |
78a52f11 RH |
532 | #undef TARGET_ARG_PARTIAL_BYTES |
533 | #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes | |
ffa88471 SE |
534 | #undef TARGET_FUNCTION_ARG |
535 | #define TARGET_FUNCTION_ARG ia64_function_arg | |
536 | #undef TARGET_FUNCTION_INCOMING_ARG | |
537 | #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg | |
538 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
539 | #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance | |
c2ed6cf8 NF |
540 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
541 | #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary | |
599aedd9 | 542 | |
c590b625 RH |
543 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
544 | #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk | |
3961e8fe | 545 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 546 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 547 | |
1bc7c5b6 ZW |
548 | #undef TARGET_ASM_FILE_START |
549 | #define TARGET_ASM_FILE_START ia64_file_start | |
550 | ||
812b587e SE |
551 | #undef TARGET_ASM_GLOBALIZE_DECL_NAME |
552 | #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name | |
553 | ||
de8f4b07 AS |
554 | #undef TARGET_REGISTER_MOVE_COST |
555 | #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost | |
69e18c09 AS |
556 | #undef TARGET_MEMORY_MOVE_COST |
557 | #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost | |
3c50106f RH |
558 | #undef TARGET_RTX_COSTS |
559 | #define TARGET_RTX_COSTS ia64_rtx_costs | |
dcefdf67 | 560 | #undef TARGET_ADDRESS_COST |
b413068c | 561 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 |
3c50106f | 562 | |
215b063c PB |
563 | #undef TARGET_UNSPEC_MAY_TRAP_P |
564 | #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p | |
565 | ||
18dbd950 RS |
566 | #undef TARGET_MACHINE_DEPENDENT_REORG |
567 | #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg | |
568 | ||
a32767e4 DM |
569 | #undef TARGET_ENCODE_SECTION_INFO |
570 | #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info | |
571 | ||
abb8b19a AM |
572 | #undef TARGET_SECTION_TYPE_FLAGS |
573 | #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags | |
574 | ||
fdbe66f2 EB |
575 | #ifdef HAVE_AS_TLS |
576 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
577 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel | |
578 | #endif | |
579 | ||
351a758b KH |
580 | /* ??? Investigate. */ |
581 | #if 0 | |
582 | #undef TARGET_PROMOTE_PROTOTYPES | |
583 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
584 | #endif | |
585 | ||
ba90d838 AS |
586 | #undef TARGET_FUNCTION_VALUE |
587 | #define TARGET_FUNCTION_VALUE ia64_function_value | |
588 | #undef TARGET_LIBCALL_VALUE | |
589 | #define TARGET_LIBCALL_VALUE ia64_libcall_value | |
590 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
591 | #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p | |
592 | ||
351a758b KH |
593 | #undef TARGET_STRUCT_VALUE_RTX |
594 | #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx | |
595 | #undef TARGET_RETURN_IN_MEMORY | |
596 | #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory | |
351a758b KH |
597 | #undef TARGET_SETUP_INCOMING_VARARGS |
598 | #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs | |
599 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
600 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
fe984136 RH |
601 | #undef TARGET_MUST_PASS_IN_STACK |
602 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
ffa88471 SE |
603 | #undef TARGET_GET_RAW_RESULT_MODE |
604 | #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode | |
605 | #undef TARGET_GET_RAW_ARG_MODE | |
606 | #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode | |
351a758b | 607 | |
d9886a9e L |
608 | #undef TARGET_MEMBER_TYPE_FORCES_BLK |
609 | #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk | |
610 | ||
cd3ce9b4 JM |
611 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
612 | #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg | |
613 | ||
38f8b050 | 614 | #undef TARGET_ASM_UNWIND_EMIT |
a68b5e52 RH |
615 | #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit |
616 | #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY | |
617 | #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality | |
618 | #undef TARGET_ASM_INIT_SECTIONS | |
619 | #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections | |
951120ea | 620 | |
f0a0390e RH |
621 | #undef TARGET_DEBUG_UNWIND_INFO |
622 | #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info | |
f0a0390e | 623 | |
88ed5ef5 SE |
624 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
625 | #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p | |
f61134e8 RH |
626 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
627 | #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p | |
88ed5ef5 | 628 | |
8cc4b7a2 JM |
629 | #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P |
630 | #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \ | |
631 | ia64_libgcc_floating_mode_supported_p | |
632 | ||
445cf5eb JM |
633 | /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur |
634 | in an order different from the specified program order. */ | |
635 | #undef TARGET_RELAXED_ORDERING | |
636 | #define TARGET_RELAXED_ORDERING true | |
637 | ||
1a627b35 RS |
638 | #undef TARGET_LEGITIMATE_CONSTANT_P |
639 | #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p | |
903a9601 AS |
640 | #undef TARGET_LEGITIMATE_ADDRESS_P |
641 | #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p | |
1a627b35 | 642 | |
5e6c8b64 RH |
643 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
644 | #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem | |
645 | ||
608063c3 JB |
646 | #undef TARGET_MANGLE_TYPE |
647 | #define TARGET_MANGLE_TYPE ia64_mangle_type | |
cac24f06 | 648 | |
4de67c26 JM |
649 | #undef TARGET_INVALID_CONVERSION |
650 | #define TARGET_INVALID_CONVERSION ia64_invalid_conversion | |
651 | #undef TARGET_INVALID_UNARY_OP | |
652 | #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op | |
653 | #undef TARGET_INVALID_BINARY_OP | |
654 | #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op | |
655 | ||
a31fa2e0 SE |
656 | #undef TARGET_C_MODE_FOR_SUFFIX |
657 | #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix | |
658 | ||
7b5cbb57 AS |
659 | #undef TARGET_CAN_ELIMINATE |
660 | #define TARGET_CAN_ELIMINATE ia64_can_eliminate | |
661 | ||
2a1211e5 RH |
662 | #undef TARGET_TRAMPOLINE_INIT |
663 | #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init | |
664 | ||
1d0216c8 RS |
665 | #undef TARGET_CAN_USE_DOLOOP_P |
666 | #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost | |
810d71d0 | 667 | #undef TARGET_INVALID_WITHIN_DOLOOP |
ac44248e | 668 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null |
810d71d0 | 669 | |
2b7e2984 SE |
670 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
671 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change | |
672 | ||
ab177ad5 AS |
673 | #undef TARGET_PREFERRED_RELOAD_CLASS |
674 | #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class | |
675 | ||
2ba42841 AO |
676 | #undef TARGET_DELAY_SCHED2 |
677 | #define TARGET_DELAY_SCHED2 true | |
678 | ||
679 | /* Variable tracking should be run after all optimizations which | |
680 | change order of insns. It also needs a valid CFG. */ | |
681 | #undef TARGET_DELAY_VARTRACK | |
682 | #define TARGET_DELAY_VARTRACK true | |
683 | ||
e6431744 RH |
684 | #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK |
685 | #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok | |
686 | ||
d8def3cf JJ |
687 | #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P |
688 | #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P ia64_attribute_takes_identifier_p | |
689 | ||
f6897b10 | 690 | struct gcc_target targetm = TARGET_INITIALIZER; |
3b572406 | 691 | \f |
d8def3cf JJ |
692 | /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain |
693 | identifier as an argument, so the front end shouldn't look it up. */ | |
694 | ||
695 | static bool | |
696 | ia64_attribute_takes_identifier_p (const_tree attr_id) | |
697 | { | |
698 | if (is_attribute_p ("model", attr_id)) | |
699 | return true; | |
700 | #if TARGET_ABI_OPEN_VMS | |
701 | if (is_attribute_p ("common_object", attr_id)) | |
702 | return true; | |
703 | #endif | |
704 | return false; | |
705 | } | |
706 | ||
a32767e4 DM |
707 | typedef enum |
708 | { | |
709 | ADDR_AREA_NORMAL, /* normal address area */ | |
710 | ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */ | |
711 | } | |
712 | ia64_addr_area; | |
713 | ||
714 | static GTY(()) tree small_ident1; | |
715 | static GTY(()) tree small_ident2; | |
716 | ||
717 | static void | |
718 | init_idents (void) | |
719 | { | |
720 | if (small_ident1 == 0) | |
721 | { | |
722 | small_ident1 = get_identifier ("small"); | |
723 | small_ident2 = get_identifier ("__small__"); | |
724 | } | |
725 | } | |
726 | ||
727 | /* Retrieve the address area that has been chosen for the given decl. */ | |
728 | ||
729 | static ia64_addr_area | |
730 | ia64_get_addr_area (tree decl) | |
731 | { | |
732 | tree model_attr; | |
733 | ||
734 | model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); | |
735 | if (model_attr) | |
736 | { | |
737 | tree id; | |
738 | ||
739 | init_idents (); | |
740 | id = TREE_VALUE (TREE_VALUE (model_attr)); | |
741 | if (id == small_ident1 || id == small_ident2) | |
742 | return ADDR_AREA_SMALL; | |
743 | } | |
744 | return ADDR_AREA_NORMAL; | |
745 | } | |
746 | ||
747 | static tree | |
f61134e8 RH |
748 | ia64_handle_model_attribute (tree *node, tree name, tree args, |
749 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
a32767e4 DM |
750 | { |
751 | ia64_addr_area addr_area = ADDR_AREA_NORMAL; | |
752 | ia64_addr_area area; | |
753 | tree arg, decl = *node; | |
754 | ||
755 | init_idents (); | |
756 | arg = TREE_VALUE (args); | |
757 | if (arg == small_ident1 || arg == small_ident2) | |
758 | { | |
759 | addr_area = ADDR_AREA_SMALL; | |
760 | } | |
761 | else | |
762 | { | |
29d08eba JM |
763 | warning (OPT_Wattributes, "invalid argument of %qE attribute", |
764 | name); | |
a32767e4 DM |
765 | *no_add_attrs = true; |
766 | } | |
767 | ||
768 | switch (TREE_CODE (decl)) | |
769 | { | |
770 | case VAR_DECL: | |
771 | if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) | |
772 | == FUNCTION_DECL) | |
773 | && !TREE_STATIC (decl)) | |
774 | { | |
c5d75364 MLI |
775 | error_at (DECL_SOURCE_LOCATION (decl), |
776 | "an address area attribute cannot be specified for " | |
777 | "local variables"); | |
a32767e4 DM |
778 | *no_add_attrs = true; |
779 | } | |
780 | area = ia64_get_addr_area (decl); | |
781 | if (area != ADDR_AREA_NORMAL && addr_area != area) | |
782 | { | |
dee15844 JM |
783 | error ("address area of %q+D conflicts with previous " |
784 | "declaration", decl); | |
a32767e4 DM |
785 | *no_add_attrs = true; |
786 | } | |
787 | break; | |
788 | ||
789 | case FUNCTION_DECL: | |
c5d75364 | 790 | error_at (DECL_SOURCE_LOCATION (decl), |
d575725b L |
791 | "address area attribute cannot be specified for " |
792 | "functions"); | |
a32767e4 DM |
793 | *no_add_attrs = true; |
794 | break; | |
795 | ||
796 | default: | |
29d08eba JM |
797 | warning (OPT_Wattributes, "%qE attribute ignored", |
798 | name); | |
a32767e4 DM |
799 | *no_add_attrs = true; |
800 | break; | |
801 | } | |
802 | ||
803 | return NULL_TREE; | |
804 | } | |
805 | ||
30ed9d3d TG |
806 | /* Part of the low level implementation of DEC Ada pragma Common_Object which |
807 | enables the shared use of variables stored in overlaid linker areas | |
808 | corresponding to the use of Fortran COMMON. */ | |
809 | ||
810 | static tree | |
811 | ia64_vms_common_object_attribute (tree *node, tree name, tree args, | |
812 | int flags ATTRIBUTE_UNUSED, | |
813 | bool *no_add_attrs) | |
814 | { | |
815 | tree decl = *node; | |
fe5798c0 TG |
816 | tree id; |
817 | ||
818 | gcc_assert (DECL_P (decl)); | |
30ed9d3d TG |
819 | |
820 | DECL_COMMON (decl) = 1; | |
821 | id = TREE_VALUE (args); | |
fe5798c0 | 822 | if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) |
30ed9d3d | 823 | { |
fe5798c0 | 824 | error ("%qE attribute requires a string constant argument", name); |
30ed9d3d TG |
825 | *no_add_attrs = true; |
826 | return NULL_TREE; | |
827 | } | |
30ed9d3d TG |
828 | return NULL_TREE; |
829 | } | |
830 | ||
831 | /* Part of the low level implementation of DEC Ada pragma Common_Object. */ | |
832 | ||
833 | void | |
834 | ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name, | |
835 | unsigned HOST_WIDE_INT size, | |
836 | unsigned int align) | |
837 | { | |
838 | tree attr = DECL_ATTRIBUTES (decl); | |
839 | ||
fe5798c0 | 840 | if (attr) |
30ed9d3d | 841 | attr = lookup_attribute ("common_object", attr); |
fe5798c0 | 842 | if (attr) |
30ed9d3d | 843 | { |
fe5798c0 TG |
844 | tree id = TREE_VALUE (TREE_VALUE (attr)); |
845 | const char *name; | |
30ed9d3d | 846 | |
fe5798c0 TG |
847 | if (TREE_CODE (id) == IDENTIFIER_NODE) |
848 | name = IDENTIFIER_POINTER (id); | |
849 | else if (TREE_CODE (id) == STRING_CST) | |
850 | name = TREE_STRING_POINTER (id); | |
851 | else | |
852 | abort (); | |
30ed9d3d | 853 | |
fe5798c0 | 854 | fprintf (file, "\t.vms_common\t\"%s\",", name); |
30ed9d3d | 855 | } |
fe5798c0 TG |
856 | else |
857 | fprintf (file, "%s", COMMON_ASM_OP); | |
30ed9d3d | 858 | |
fe5798c0 TG |
859 | /* Code from elfos.h. */ |
860 | assemble_name (file, name); | |
861 | fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u", | |
862 | size, align / BITS_PER_UNIT); | |
30ed9d3d | 863 | |
fe5798c0 | 864 | fputc ('\n', file); |
30ed9d3d TG |
865 | } |
866 | ||
a32767e4 DM |
867 | static void |
868 | ia64_encode_addr_area (tree decl, rtx symbol) | |
869 | { | |
870 | int flags; | |
871 | ||
872 | flags = SYMBOL_REF_FLAGS (symbol); | |
873 | switch (ia64_get_addr_area (decl)) | |
874 | { | |
875 | case ADDR_AREA_NORMAL: break; | |
876 | case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break; | |
e820471b | 877 | default: gcc_unreachable (); |
a32767e4 DM |
878 | } |
879 | SYMBOL_REF_FLAGS (symbol) = flags; | |
880 | } | |
881 | ||
882 | static void | |
883 | ia64_encode_section_info (tree decl, rtx rtl, int first) | |
884 | { | |
885 | default_encode_section_info (decl, rtl, first); | |
886 | ||
2897f1d4 | 887 | /* Careful not to prod global register variables. */ |
a32767e4 | 888 | if (TREE_CODE (decl) == VAR_DECL |
2897f1d4 L |
889 | && GET_CODE (DECL_RTL (decl)) == MEM |
890 | && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF | |
a32767e4 DM |
891 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
892 | ia64_encode_addr_area (decl, XEXP (rtl, 0)); | |
893 | } | |
894 | \f | |
557b9df5 RH |
895 | /* Return 1 if the operands of a move are ok. */ |
896 | ||
897 | int | |
9c808aad | 898 | ia64_move_ok (rtx dst, rtx src) |
557b9df5 RH |
899 | { |
900 | /* If we're under init_recog_no_volatile, we'll not be able to use | |
901 | memory_operand. So check the code directly and don't worry about | |
902 | the validity of the underlying address, which should have been | |
903 | checked elsewhere anyway. */ | |
904 | if (GET_CODE (dst) != MEM) | |
905 | return 1; | |
906 | if (GET_CODE (src) == MEM) | |
907 | return 0; | |
908 | if (register_operand (src, VOIDmode)) | |
909 | return 1; | |
910 | ||
911 | /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */ | |
912 | if (INTEGRAL_MODE_P (GET_MODE (dst))) | |
913 | return src == const0_rtx; | |
914 | else | |
13f70342 | 915 | return satisfies_constraint_G (src); |
557b9df5 | 916 | } |
9b7bf67d | 917 | |
a71aef0b JB |
918 | /* Return 1 if the operands are ok for a floating point load pair. */ |
919 | ||
920 | int | |
921 | ia64_load_pair_ok (rtx dst, rtx src) | |
922 | { | |
22be5918 EB |
923 | /* ??? There is a thinko in the implementation of the "x" constraint and the |
924 | FP_REGS class. The constraint will also reject (reg f30:TI) so we must | |
925 | also return false for it. */ | |
926 | if (GET_CODE (dst) != REG | |
927 | || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1))) | |
a71aef0b JB |
928 | return 0; |
929 | if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src)) | |
930 | return 0; | |
931 | switch (GET_CODE (XEXP (src, 0))) | |
932 | { | |
933 | case REG: | |
934 | case POST_INC: | |
935 | break; | |
936 | case POST_DEC: | |
937 | return 0; | |
938 | case POST_MODIFY: | |
939 | { | |
940 | rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1); | |
941 | ||
942 | if (GET_CODE (adjust) != CONST_INT | |
943 | || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src))) | |
944 | return 0; | |
945 | } | |
946 | break; | |
947 | default: | |
948 | abort (); | |
949 | } | |
950 | return 1; | |
951 | } | |
952 | ||
08744705 | 953 | int |
9c808aad | 954 | addp4_optimize_ok (rtx op1, rtx op2) |
08744705 | 955 | { |
08744705 SE |
956 | return (basereg_operand (op1, GET_MODE(op1)) != |
957 | basereg_operand (op2, GET_MODE(op2))); | |
958 | } | |
959 | ||
9e4f94de | 960 | /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction. |
041f25e6 RH |
961 | Return the length of the field, or <= 0 on failure. */ |
962 | ||
963 | int | |
9c808aad | 964 | ia64_depz_field_mask (rtx rop, rtx rshift) |
041f25e6 RH |
965 | { |
966 | unsigned HOST_WIDE_INT op = INTVAL (rop); | |
967 | unsigned HOST_WIDE_INT shift = INTVAL (rshift); | |
968 | ||
969 | /* Get rid of the zero bits we're shifting in. */ | |
970 | op >>= shift; | |
971 | ||
972 | /* We must now have a solid block of 1's at bit 0. */ | |
973 | return exact_log2 (op + 1); | |
974 | } | |
975 | ||
5e6c8b64 RH |
976 | /* Return the TLS model to use for ADDR. */ |
977 | ||
978 | static enum tls_model | |
979 | tls_symbolic_operand_type (rtx addr) | |
980 | { | |
81f40b79 | 981 | enum tls_model tls_kind = TLS_MODEL_NONE; |
5e6c8b64 RH |
982 | |
983 | if (GET_CODE (addr) == CONST) | |
984 | { | |
985 | if (GET_CODE (XEXP (addr, 0)) == PLUS | |
986 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF) | |
987 | tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0)); | |
988 | } | |
989 | else if (GET_CODE (addr) == SYMBOL_REF) | |
990 | tls_kind = SYMBOL_REF_TLS_MODEL (addr); | |
991 | ||
992 | return tls_kind; | |
993 | } | |
994 | ||
903a9601 AS |
995 | /* Returns true if REG (assumed to be a `reg' RTX) is valid for use |
996 | as a base register. */ | |
997 | ||
998 | static inline bool | |
999 | ia64_reg_ok_for_base_p (const_rtx reg, bool strict) | |
1000 | { | |
1001 | if (strict | |
1002 | && REGNO_OK_FOR_BASE_P (REGNO (reg))) | |
1003 | return true; | |
1004 | else if (!strict | |
1005 | && (GENERAL_REGNO_P (REGNO (reg)) | |
1006 | || !HARD_REGISTER_P (reg))) | |
1007 | return true; | |
1008 | else | |
1009 | return false; | |
1010 | } | |
1011 | ||
1012 | static bool | |
1013 | ia64_legitimate_address_reg (const_rtx reg, bool strict) | |
1014 | { | |
1015 | if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict)) | |
1016 | || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0)) | |
1017 | && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict))) | |
1018 | return true; | |
1019 | ||
1020 | return false; | |
1021 | } | |
1022 | ||
1023 | static bool | |
1024 | ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict) | |
1025 | { | |
1026 | if (GET_CODE (disp) == PLUS | |
1027 | && rtx_equal_p (reg, XEXP (disp, 0)) | |
1028 | && (ia64_legitimate_address_reg (XEXP (disp, 1), strict) | |
1029 | || (CONST_INT_P (XEXP (disp, 1)) | |
1030 | && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255)))) | |
1031 | return true; | |
1032 | ||
1033 | return false; | |
1034 | } | |
1035 | ||
1036 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ | |
1037 | ||
1038 | static bool | |
ef4bddc2 | 1039 | ia64_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, |
903a9601 AS |
1040 | rtx x, bool strict) |
1041 | { | |
1042 | if (ia64_legitimate_address_reg (x, strict)) | |
1043 | return true; | |
1044 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
1045 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
1046 | && XEXP (x, 0) != arg_pointer_rtx) | |
1047 | return true; | |
1048 | else if (GET_CODE (x) == POST_MODIFY | |
1049 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
1050 | && XEXP (x, 0) != arg_pointer_rtx | |
1051 | && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict)) | |
1052 | return true; | |
1053 | else | |
1054 | return false; | |
1055 | } | |
1056 | ||
5e6c8b64 RH |
1057 | /* Return true if X is a constant that is valid for some immediate |
1058 | field in an instruction. */ | |
1059 | ||
1a627b35 | 1060 | static bool |
ef4bddc2 | 1061 | ia64_legitimate_constant_p (machine_mode mode, rtx x) |
5e6c8b64 RH |
1062 | { |
1063 | switch (GET_CODE (x)) | |
1064 | { | |
1065 | case CONST_INT: | |
1066 | case LABEL_REF: | |
1067 | return true; | |
1068 | ||
1069 | case CONST_DOUBLE: | |
1a627b35 | 1070 | if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode) |
5e6c8b64 | 1071 | return true; |
13f70342 | 1072 | return satisfies_constraint_G (x); |
5e6c8b64 RH |
1073 | |
1074 | case CONST: | |
1075 | case SYMBOL_REF: | |
d0970db2 JW |
1076 | /* ??? Short term workaround for PR 28490. We must make the code here |
1077 | match the code in ia64_expand_move and move_operand, even though they | |
1078 | are both technically wrong. */ | |
1079 | if (tls_symbolic_operand_type (x) == 0) | |
1080 | { | |
1081 | HOST_WIDE_INT addend = 0; | |
1082 | rtx op = x; | |
1083 | ||
1084 | if (GET_CODE (op) == CONST | |
1085 | && GET_CODE (XEXP (op, 0)) == PLUS | |
1086 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) | |
1087 | { | |
1088 | addend = INTVAL (XEXP (XEXP (op, 0), 1)); | |
1089 | op = XEXP (XEXP (op, 0), 0); | |
1090 | } | |
1091 | ||
1a627b35 RS |
1092 | if (any_offset_symbol_operand (op, mode) |
1093 | || function_operand (op, mode)) | |
7ab62966 | 1094 | return true; |
1a627b35 | 1095 | if (aligned_offset_symbol_operand (op, mode)) |
d0970db2 JW |
1096 | return (addend & 0x3fff) == 0; |
1097 | return false; | |
1098 | } | |
1099 | return false; | |
5e6c8b64 | 1100 | |
b4e3537b | 1101 | case CONST_VECTOR: |
1a627b35 RS |
1102 | if (mode == V2SFmode) |
1103 | return satisfies_constraint_Y (x); | |
b4e3537b | 1104 | |
1a627b35 RS |
1105 | return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT |
1106 | && GET_MODE_SIZE (mode) <= 8); | |
b4e3537b | 1107 | |
5e6c8b64 RH |
1108 | default: |
1109 | return false; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* Don't allow TLS addresses to get spilled to memory. */ | |
1114 | ||
1115 | static bool | |
ef4bddc2 | 1116 | ia64_cannot_force_const_mem (machine_mode mode, rtx x) |
5e6c8b64 | 1117 | { |
fbbf66e7 | 1118 | if (mode == RFmode) |
103a6411 | 1119 | return true; |
5e6c8b64 RH |
1120 | return tls_symbolic_operand_type (x) != 0; |
1121 | } | |
1122 | ||
9b7bf67d | 1123 | /* Expand a symbolic constant load. */ |
9b7bf67d | 1124 | |
5e6c8b64 | 1125 | bool |
9c808aad | 1126 | ia64_expand_load_address (rtx dest, rtx src) |
9b7bf67d | 1127 | { |
e820471b | 1128 | gcc_assert (GET_CODE (dest) == REG); |
7b6e506e | 1129 | |
ae49d6e5 RH |
1130 | /* ILP32 mode still loads 64-bits of data from the GOT. This avoids |
1131 | having to pointer-extend the value afterward. Other forms of address | |
1132 | computation below are also more natural to compute as 64-bit quantities. | |
1133 | If we've been given an SImode destination register, change it. */ | |
1134 | if (GET_MODE (dest) != Pmode) | |
38ae7651 RS |
1135 | dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), |
1136 | byte_lowpart_offset (Pmode, GET_MODE (dest))); | |
ae49d6e5 | 1137 | |
5e6c8b64 RH |
1138 | if (TARGET_NO_PIC) |
1139 | return false; | |
1140 | if (small_addr_symbolic_operand (src, VOIDmode)) | |
1141 | return false; | |
1142 | ||
1143 | if (TARGET_AUTO_PIC) | |
1144 | emit_insn (gen_load_gprel64 (dest, src)); | |
1cdbd630 | 1145 | else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src)) |
5e6c8b64 | 1146 | emit_insn (gen_load_fptr (dest, src)); |
21515593 | 1147 | else if (sdata_symbolic_operand (src, VOIDmode)) |
5e6c8b64 RH |
1148 | emit_insn (gen_load_gprel (dest, src)); |
1149 | else | |
21515593 | 1150 | { |
5e6c8b64 RH |
1151 | HOST_WIDE_INT addend = 0; |
1152 | rtx tmp; | |
21515593 | 1153 | |
5e6c8b64 RH |
1154 | /* We did split constant offsets in ia64_expand_move, and we did try |
1155 | to keep them split in move_operand, but we also allowed reload to | |
1156 | rematerialize arbitrary constants rather than spill the value to | |
1157 | the stack and reload it. So we have to be prepared here to split | |
1158 | them apart again. */ | |
1159 | if (GET_CODE (src) == CONST) | |
1160 | { | |
1161 | HOST_WIDE_INT hi, lo; | |
9b7bf67d | 1162 | |
5e6c8b64 RH |
1163 | hi = INTVAL (XEXP (XEXP (src, 0), 1)); |
1164 | lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000; | |
1165 | hi = hi - lo; | |
9b7bf67d | 1166 | |
5e6c8b64 RH |
1167 | if (lo != 0) |
1168 | { | |
1169 | addend = lo; | |
0a81f074 | 1170 | src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi); |
5e6c8b64 RH |
1171 | } |
1172 | } | |
ae49d6e5 RH |
1173 | |
1174 | tmp = gen_rtx_HIGH (Pmode, src); | |
1175 | tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx); | |
1176 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1177 | ||
1f88caaa | 1178 | tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src); |
ae49d6e5 | 1179 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); |
5e6c8b64 RH |
1180 | |
1181 | if (addend) | |
1182 | { | |
1183 | tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend)); | |
1184 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1185 | } | |
ae49d6e5 | 1186 | } |
5e6c8b64 RH |
1187 | |
1188 | return true; | |
9b7bf67d | 1189 | } |
97e242b0 | 1190 | |
e2500fed | 1191 | static GTY(()) rtx gen_tls_tga; |
7b6e506e | 1192 | static rtx |
9c808aad | 1193 | gen_tls_get_addr (void) |
7b6e506e | 1194 | { |
e2500fed | 1195 | if (!gen_tls_tga) |
21515593 | 1196 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); |
e2500fed | 1197 | return gen_tls_tga; |
7b6e506e RH |
1198 | } |
1199 | ||
e2500fed | 1200 | static GTY(()) rtx thread_pointer_rtx; |
7b6e506e | 1201 | static rtx |
9c808aad | 1202 | gen_thread_pointer (void) |
7b6e506e | 1203 | { |
e2500fed | 1204 | if (!thread_pointer_rtx) |
389fdba0 | 1205 | thread_pointer_rtx = gen_rtx_REG (Pmode, 13); |
135ca7b2 | 1206 | return thread_pointer_rtx; |
7b6e506e RH |
1207 | } |
1208 | ||
21515593 | 1209 | static rtx |
5e6c8b64 | 1210 | ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1, |
b15b83fb | 1211 | rtx orig_op1, HOST_WIDE_INT addend) |
21515593 | 1212 | { |
dd3d2b35 DM |
1213 | rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp; |
1214 | rtx_insn *insns; | |
b15b83fb | 1215 | rtx orig_op0 = op0; |
5e6c8b64 RH |
1216 | HOST_WIDE_INT addend_lo, addend_hi; |
1217 | ||
21515593 RH |
1218 | switch (tls_kind) |
1219 | { | |
1220 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1221 | start_sequence (); | |
1222 | ||
1223 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1224 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1225 | |
1226 | tga_op2 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1227 | emit_insn (gen_load_dtprel (tga_op2, op1)); |
9c808aad | 1228 | |
21515593 RH |
1229 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, |
1230 | LCT_CONST, Pmode, 2, tga_op1, | |
1231 | Pmode, tga_op2, Pmode); | |
1232 | ||
1233 | insns = get_insns (); | |
1234 | end_sequence (); | |
1235 | ||
0d433a6a RH |
1236 | if (GET_MODE (op0) != Pmode) |
1237 | op0 = tga_ret; | |
21515593 | 1238 | emit_libcall_block (insns, op0, tga_ret, op1); |
0d433a6a | 1239 | break; |
21515593 RH |
1240 | |
1241 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1242 | /* ??? This isn't the completely proper way to do local-dynamic | |
1243 | If the call to __tls_get_addr is used only by a single symbol, | |
1244 | then we should (somehow) move the dtprel to the second arg | |
1245 | to avoid the extra add. */ | |
1246 | start_sequence (); | |
1247 | ||
1248 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1249 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1250 | |
1251 | tga_op2 = const0_rtx; | |
1252 | ||
1253 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, | |
1254 | LCT_CONST, Pmode, 2, tga_op1, | |
1255 | Pmode, tga_op2, Pmode); | |
1256 | ||
1257 | insns = get_insns (); | |
1258 | end_sequence (); | |
1259 | ||
1260 | tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1261 | UNSPEC_LD_BASE); | |
1262 | tmp = gen_reg_rtx (Pmode); | |
1263 | emit_libcall_block (insns, tmp, tga_ret, tga_eqv); | |
1264 | ||
0d433a6a RH |
1265 | if (!register_operand (op0, Pmode)) |
1266 | op0 = gen_reg_rtx (Pmode); | |
21515593 RH |
1267 | if (TARGET_TLS64) |
1268 | { | |
0d433a6a RH |
1269 | emit_insn (gen_load_dtprel (op0, op1)); |
1270 | emit_insn (gen_adddi3 (op0, tmp, op0)); | |
21515593 RH |
1271 | } |
1272 | else | |
5e6c8b64 | 1273 | emit_insn (gen_add_dtprel (op0, op1, tmp)); |
0d433a6a | 1274 | break; |
21515593 RH |
1275 | |
1276 | case TLS_MODEL_INITIAL_EXEC: | |
b15b83fb JJ |
1277 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; |
1278 | addend_hi = addend - addend_lo; | |
1279 | ||
0a81f074 | 1280 | op1 = plus_constant (Pmode, op1, addend_hi); |
5e6c8b64 RH |
1281 | addend = addend_lo; |
1282 | ||
21515593 | 1283 | tmp = gen_reg_rtx (Pmode); |
5e6c8b64 | 1284 | emit_insn (gen_load_tprel (tmp, op1)); |
21515593 | 1285 | |
0d433a6a RH |
1286 | if (!register_operand (op0, Pmode)) |
1287 | op0 = gen_reg_rtx (Pmode); | |
1288 | emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ())); | |
1289 | break; | |
21515593 RH |
1290 | |
1291 | case TLS_MODEL_LOCAL_EXEC: | |
0d433a6a RH |
1292 | if (!register_operand (op0, Pmode)) |
1293 | op0 = gen_reg_rtx (Pmode); | |
5e6c8b64 RH |
1294 | |
1295 | op1 = orig_op1; | |
1296 | addend = 0; | |
21515593 RH |
1297 | if (TARGET_TLS64) |
1298 | { | |
0d433a6a | 1299 | emit_insn (gen_load_tprel (op0, op1)); |
5e6c8b64 | 1300 | emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ())); |
21515593 RH |
1301 | } |
1302 | else | |
5e6c8b64 | 1303 | emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ())); |
0d433a6a | 1304 | break; |
21515593 RH |
1305 | |
1306 | default: | |
e820471b | 1307 | gcc_unreachable (); |
21515593 | 1308 | } |
0d433a6a | 1309 | |
5e6c8b64 RH |
1310 | if (addend) |
1311 | op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend), | |
1312 | orig_op0, 1, OPTAB_DIRECT); | |
0d433a6a RH |
1313 | if (orig_op0 == op0) |
1314 | return NULL_RTX; | |
1315 | if (GET_MODE (orig_op0) == Pmode) | |
1316 | return op0; | |
1317 | return gen_lowpart (GET_MODE (orig_op0), op0); | |
21515593 RH |
1318 | } |
1319 | ||
7b6e506e | 1320 | rtx |
9c808aad | 1321 | ia64_expand_move (rtx op0, rtx op1) |
7b6e506e | 1322 | { |
ef4bddc2 | 1323 | machine_mode mode = GET_MODE (op0); |
7b6e506e RH |
1324 | |
1325 | if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1)) | |
1326 | op1 = force_reg (mode, op1); | |
1327 | ||
21515593 | 1328 | if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode)) |
7b6e506e | 1329 | { |
5e6c8b64 | 1330 | HOST_WIDE_INT addend = 0; |
7b6e506e | 1331 | enum tls_model tls_kind; |
5e6c8b64 RH |
1332 | rtx sym = op1; |
1333 | ||
1334 | if (GET_CODE (op1) == CONST | |
1335 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
1336 | && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT) | |
1337 | { | |
1338 | addend = INTVAL (XEXP (XEXP (op1, 0), 1)); | |
1339 | sym = XEXP (XEXP (op1, 0), 0); | |
1340 | } | |
1341 | ||
1342 | tls_kind = tls_symbolic_operand_type (sym); | |
1343 | if (tls_kind) | |
b15b83fb | 1344 | return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend); |
5e6c8b64 RH |
1345 | |
1346 | if (any_offset_symbol_operand (sym, mode)) | |
1347 | addend = 0; | |
1348 | else if (aligned_offset_symbol_operand (sym, mode)) | |
1349 | { | |
1350 | HOST_WIDE_INT addend_lo, addend_hi; | |
1351 | ||
1352 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; | |
1353 | addend_hi = addend - addend_lo; | |
1354 | ||
1355 | if (addend_lo != 0) | |
1356 | { | |
0a81f074 | 1357 | op1 = plus_constant (mode, sym, addend_hi); |
5e6c8b64 RH |
1358 | addend = addend_lo; |
1359 | } | |
21e43850 L |
1360 | else |
1361 | addend = 0; | |
5e6c8b64 RH |
1362 | } |
1363 | else | |
1364 | op1 = sym; | |
1365 | ||
1366 | if (reload_completed) | |
1367 | { | |
1368 | /* We really should have taken care of this offset earlier. */ | |
1369 | gcc_assert (addend == 0); | |
1370 | if (ia64_expand_load_address (op0, op1)) | |
1371 | return NULL_RTX; | |
1372 | } | |
21515593 | 1373 | |
5e6c8b64 | 1374 | if (addend) |
7b6e506e | 1375 | { |
b3a13419 | 1376 | rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode); |
5e6c8b64 RH |
1377 | |
1378 | emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1)); | |
1379 | ||
1380 | op1 = expand_simple_binop (mode, PLUS, subtarget, | |
1381 | GEN_INT (addend), op0, 1, OPTAB_DIRECT); | |
1382 | if (op0 == op1) | |
1383 | return NULL_RTX; | |
7b6e506e RH |
1384 | } |
1385 | } | |
1386 | ||
1387 | return op1; | |
1388 | } | |
1389 | ||
21515593 RH |
1390 | /* Split a move from OP1 to OP0 conditional on COND. */ |
1391 | ||
1392 | void | |
9c808aad | 1393 | ia64_emit_cond_move (rtx op0, rtx op1, rtx cond) |
21515593 | 1394 | { |
dd3d2b35 | 1395 | rtx_insn *insn, *first = get_last_insn (); |
21515593 RH |
1396 | |
1397 | emit_move_insn (op0, op1); | |
1398 | ||
1399 | for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn)) | |
1400 | if (INSN_P (insn)) | |
1401 | PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), | |
1402 | PATTERN (insn)); | |
1403 | } | |
1404 | ||
f57fc998 | 1405 | /* Split a post-reload TImode or TFmode reference into two DImode |
2ffe0e02 ZW |
1406 | components. This is made extra difficult by the fact that we do |
1407 | not get any scratch registers to work with, because reload cannot | |
1408 | be prevented from giving us a scratch that overlaps the register | |
1409 | pair involved. So instead, when addressing memory, we tweak the | |
1410 | pointer register up and back down with POST_INCs. Or up and not | |
1411 | back down when we can get away with it. | |
1412 | ||
1413 | REVERSED is true when the loads must be done in reversed order | |
1414 | (high word first) for correctness. DEAD is true when the pointer | |
1415 | dies with the second insn we generate and therefore the second | |
1416 | address must not carry a postmodify. | |
1417 | ||
1418 | May return an insn which is to be emitted after the moves. */ | |
3f622353 | 1419 | |
f57fc998 | 1420 | static rtx |
2ffe0e02 | 1421 | ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) |
3f622353 | 1422 | { |
2ffe0e02 ZW |
1423 | rtx fixup = 0; |
1424 | ||
3f622353 RH |
1425 | switch (GET_CODE (in)) |
1426 | { | |
1427 | case REG: | |
2ffe0e02 ZW |
1428 | out[reversed] = gen_rtx_REG (DImode, REGNO (in)); |
1429 | out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1); | |
1430 | break; | |
3f622353 RH |
1431 | |
1432 | case CONST_INT: | |
1433 | case CONST_DOUBLE: | |
2ffe0e02 | 1434 | /* Cannot occur reversed. */ |
e820471b | 1435 | gcc_assert (!reversed); |
2ffe0e02 | 1436 | |
f57fc998 ZW |
1437 | if (GET_MODE (in) != TFmode) |
1438 | split_double (in, &out[0], &out[1]); | |
1439 | else | |
1440 | /* split_double does not understand how to split a TFmode | |
1441 | quantity into a pair of DImode constants. */ | |
1442 | { | |
1443 | REAL_VALUE_TYPE r; | |
1444 | unsigned HOST_WIDE_INT p[2]; | |
1445 | long l[4]; /* TFmode is 128 bits */ | |
1446 | ||
1447 | REAL_VALUE_FROM_CONST_DOUBLE (r, in); | |
1448 | real_to_target (l, &r, TFmode); | |
1449 | ||
1450 | if (FLOAT_WORDS_BIG_ENDIAN) | |
1451 | { | |
1452 | p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1]; | |
1453 | p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3]; | |
1454 | } | |
1455 | else | |
1456 | { | |
9eb578c8 L |
1457 | p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0]; |
1458 | p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2]; | |
f57fc998 ZW |
1459 | } |
1460 | out[0] = GEN_INT (p[0]); | |
1461 | out[1] = GEN_INT (p[1]); | |
1462 | } | |
2ffe0e02 ZW |
1463 | break; |
1464 | ||
1465 | case MEM: | |
1466 | { | |
1467 | rtx base = XEXP (in, 0); | |
1468 | rtx offset; | |
1469 | ||
1470 | switch (GET_CODE (base)) | |
1471 | { | |
1472 | case REG: | |
1473 | if (!reversed) | |
1474 | { | |
1475 | out[0] = adjust_automodify_address | |
1476 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1477 | out[1] = adjust_automodify_address | |
1478 | (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8); | |
1479 | } | |
1480 | else | |
1481 | { | |
1482 | /* Reversal requires a pre-increment, which can only | |
1483 | be done as a separate insn. */ | |
1484 | emit_insn (gen_adddi3 (base, base, GEN_INT (8))); | |
1485 | out[0] = adjust_automodify_address | |
1486 | (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8); | |
1487 | out[1] = adjust_address (in, DImode, 0); | |
1488 | } | |
1489 | break; | |
1490 | ||
1491 | case POST_INC: | |
e820471b NS |
1492 | gcc_assert (!reversed && !dead); |
1493 | ||
2ffe0e02 ZW |
1494 | /* Just do the increment in two steps. */ |
1495 | out[0] = adjust_automodify_address (in, DImode, 0, 0); | |
1496 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1497 | break; | |
1498 | ||
1499 | case POST_DEC: | |
e820471b NS |
1500 | gcc_assert (!reversed && !dead); |
1501 | ||
2ffe0e02 ZW |
1502 | /* Add 8, subtract 24. */ |
1503 | base = XEXP (base, 0); | |
1504 | out[0] = adjust_automodify_address | |
1505 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1506 | out[1] = adjust_automodify_address | |
1507 | (in, DImode, | |
0a81f074 RS |
1508 | gen_rtx_POST_MODIFY (Pmode, base, |
1509 | plus_constant (Pmode, base, -24)), | |
2ffe0e02 ZW |
1510 | 8); |
1511 | break; | |
1512 | ||
1513 | case POST_MODIFY: | |
e820471b NS |
1514 | gcc_assert (!reversed && !dead); |
1515 | ||
2ffe0e02 ZW |
1516 | /* Extract and adjust the modification. This case is |
1517 | trickier than the others, because we might have an | |
1518 | index register, or we might have a combined offset that | |
1519 | doesn't fit a signed 9-bit displacement field. We can | |
1520 | assume the incoming expression is already legitimate. */ | |
1521 | offset = XEXP (base, 1); | |
1522 | base = XEXP (base, 0); | |
1523 | ||
1524 | out[0] = adjust_automodify_address | |
1525 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1526 | ||
1527 | if (GET_CODE (XEXP (offset, 1)) == REG) | |
1528 | { | |
1529 | /* Can't adjust the postmodify to match. Emit the | |
1530 | original, then a separate addition insn. */ | |
1531 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1532 | fixup = gen_adddi3 (base, base, GEN_INT (-8)); | |
1533 | } | |
2ffe0e02 ZW |
1534 | else |
1535 | { | |
e820471b NS |
1536 | gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT); |
1537 | if (INTVAL (XEXP (offset, 1)) < -256 + 8) | |
1538 | { | |
1539 | /* Again the postmodify cannot be made to match, | |
1540 | but in this case it's more efficient to get rid | |
1541 | of the postmodify entirely and fix up with an | |
1542 | add insn. */ | |
1543 | out[1] = adjust_automodify_address (in, DImode, base, 8); | |
1544 | fixup = gen_adddi3 | |
1545 | (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8)); | |
1546 | } | |
1547 | else | |
1548 | { | |
1549 | /* Combined offset still fits in the displacement field. | |
1550 | (We cannot overflow it at the high end.) */ | |
1551 | out[1] = adjust_automodify_address | |
1552 | (in, DImode, gen_rtx_POST_MODIFY | |
1553 | (Pmode, base, gen_rtx_PLUS | |
1554 | (Pmode, base, | |
1555 | GEN_INT (INTVAL (XEXP (offset, 1)) - 8))), | |
1556 | 8); | |
1557 | } | |
2ffe0e02 ZW |
1558 | } |
1559 | break; | |
1560 | ||
1561 | default: | |
e820471b | 1562 | gcc_unreachable (); |
2ffe0e02 ZW |
1563 | } |
1564 | break; | |
1565 | } | |
3f622353 RH |
1566 | |
1567 | default: | |
e820471b | 1568 | gcc_unreachable (); |
3f622353 | 1569 | } |
2ffe0e02 ZW |
1570 | |
1571 | return fixup; | |
3f622353 RH |
1572 | } |
1573 | ||
f57fc998 ZW |
1574 | /* Split a TImode or TFmode move instruction after reload. |
1575 | This is used by *movtf_internal and *movti_internal. */ | |
1576 | void | |
1577 | ia64_split_tmode_move (rtx operands[]) | |
1578 | { | |
2ffe0e02 ZW |
1579 | rtx in[2], out[2], insn; |
1580 | rtx fixup[2]; | |
1581 | bool dead = false; | |
1582 | bool reversed = false; | |
1583 | ||
1584 | /* It is possible for reload to decide to overwrite a pointer with | |
1585 | the value it points to. In that case we have to do the loads in | |
1586 | the appropriate order so that the pointer is not destroyed too | |
1587 | early. Also we must not generate a postmodify for that second | |
6d3f673c KY |
1588 | load, or rws_access_regno will die. And we must not generate a |
1589 | postmodify for the second load if the destination register | |
1590 | overlaps with the base register. */ | |
2ffe0e02 ZW |
1591 | if (GET_CODE (operands[1]) == MEM |
1592 | && reg_overlap_mentioned_p (operands[0], operands[1])) | |
f57fc998 | 1593 | { |
2ffe0e02 ZW |
1594 | rtx base = XEXP (operands[1], 0); |
1595 | while (GET_CODE (base) != REG) | |
1596 | base = XEXP (base, 0); | |
f57fc998 | 1597 | |
2ffe0e02 | 1598 | if (REGNO (base) == REGNO (operands[0])) |
6d3f673c | 1599 | reversed = true; |
2430d1e2 | 1600 | |
6d3f673c KY |
1601 | if (refers_to_regno_p (REGNO (operands[0]), |
1602 | REGNO (operands[0])+2, | |
1603 | base, 0)) | |
2430d1e2 | 1604 | dead = true; |
2ffe0e02 ZW |
1605 | } |
1606 | /* Another reason to do the moves in reversed order is if the first | |
1607 | element of the target register pair is also the second element of | |
1608 | the source register pair. */ | |
1609 | if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG | |
1610 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
1611 | reversed = true; | |
1612 | ||
1613 | fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead); | |
1614 | fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead); | |
1615 | ||
1616 | #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \ | |
1617 | if (GET_CODE (EXP) == MEM \ | |
1618 | && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \ | |
1619 | || GET_CODE (XEXP (EXP, 0)) == POST_INC \ | |
1620 | || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \ | |
bbbbb16a | 1621 | add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0)) |
2ffe0e02 ZW |
1622 | |
1623 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0])); | |
1624 | MAYBE_ADD_REG_INC_NOTE (insn, in[0]); | |
1625 | MAYBE_ADD_REG_INC_NOTE (insn, out[0]); | |
1626 | ||
1627 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1])); | |
1628 | MAYBE_ADD_REG_INC_NOTE (insn, in[1]); | |
1629 | MAYBE_ADD_REG_INC_NOTE (insn, out[1]); | |
1630 | ||
1631 | if (fixup[0]) | |
1632 | emit_insn (fixup[0]); | |
1633 | if (fixup[1]) | |
1634 | emit_insn (fixup[1]); | |
1635 | ||
1636 | #undef MAYBE_ADD_REG_INC_NOTE | |
f57fc998 ZW |
1637 | } |
1638 | ||
02befdf4 | 1639 | /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go |
3f622353 RH |
1640 | through memory plus an extra GR scratch register. Except that you can |
1641 | either get the first from SECONDARY_MEMORY_NEEDED or the second from | |
1642 | SECONDARY_RELOAD_CLASS, but not both. | |
1643 | ||
1644 | We got into problems in the first place by allowing a construct like | |
02befdf4 | 1645 | (subreg:XF (reg:TI)), which we got from a union containing a long double. |
f5143c46 | 1646 | This solution attempts to prevent this situation from occurring. When |
3f622353 RH |
1647 | we see something like the above, we spill the inner register to memory. */ |
1648 | ||
4de67c26 | 1649 | static rtx |
ef4bddc2 | 1650 | spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode) |
3f622353 RH |
1651 | { |
1652 | if (GET_CODE (in) == SUBREG | |
1653 | && GET_MODE (SUBREG_REG (in)) == TImode | |
1654 | && GET_CODE (SUBREG_REG (in)) == REG) | |
1655 | { | |
9474e8ab | 1656 | rtx memt = assign_stack_temp (TImode, 16); |
68d22aa5 | 1657 | emit_move_insn (memt, SUBREG_REG (in)); |
4de67c26 | 1658 | return adjust_address (memt, mode, 0); |
3f622353 RH |
1659 | } |
1660 | else if (force && GET_CODE (in) == REG) | |
1661 | { | |
9474e8ab | 1662 | rtx memx = assign_stack_temp (mode, 16); |
68d22aa5 RH |
1663 | emit_move_insn (memx, in); |
1664 | return memx; | |
3f622353 | 1665 | } |
3f622353 RH |
1666 | else |
1667 | return in; | |
1668 | } | |
f2f90c63 | 1669 | |
4de67c26 JM |
1670 | /* Expand the movxf or movrf pattern (MODE says which) with the given |
1671 | OPERANDS, returning true if the pattern should then invoke | |
1672 | DONE. */ | |
1673 | ||
1674 | bool | |
ef4bddc2 | 1675 | ia64_expand_movxf_movrf (machine_mode mode, rtx operands[]) |
4de67c26 JM |
1676 | { |
1677 | rtx op0 = operands[0]; | |
1678 | ||
1679 | if (GET_CODE (op0) == SUBREG) | |
1680 | op0 = SUBREG_REG (op0); | |
1681 | ||
1682 | /* We must support XFmode loads into general registers for stdarg/vararg, | |
1683 | unprototyped calls, and a rare case where a long double is passed as | |
1684 | an argument after a float HFA fills the FP registers. We split them into | |
1685 | DImode loads for convenience. We also need to support XFmode stores | |
1686 | for the last case. This case does not happen for stdarg/vararg routines, | |
1687 | because we do a block store to memory of unnamed arguments. */ | |
1688 | ||
1689 | if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) | |
1690 | { | |
1691 | rtx out[2]; | |
1692 | ||
1693 | /* We're hoping to transform everything that deals with XFmode | |
1694 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1695 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1696 | |
1697 | /* Struct to register can just use TImode instead. */ | |
1698 | if ((GET_CODE (operands[1]) == SUBREG | |
1699 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
1700 | || (GET_CODE (operands[1]) == REG | |
1701 | && GR_REGNO_P (REGNO (operands[1])))) | |
1702 | { | |
1703 | rtx op1 = operands[1]; | |
1704 | ||
1705 | if (GET_CODE (op1) == SUBREG) | |
1706 | op1 = SUBREG_REG (op1); | |
1707 | else | |
1708 | op1 = gen_rtx_REG (TImode, REGNO (op1)); | |
1709 | ||
1710 | emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); | |
1711 | return true; | |
1712 | } | |
1713 | ||
1714 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1715 | { | |
ae4d3291 | 1716 | /* Don't word-swap when reading in the constant. */ |
4de67c26 | 1717 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), |
ae4d3291 JW |
1718 | operand_subword (operands[1], WORDS_BIG_ENDIAN, |
1719 | 0, mode)); | |
4de67c26 | 1720 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), |
ae4d3291 JW |
1721 | operand_subword (operands[1], !WORDS_BIG_ENDIAN, |
1722 | 0, mode)); | |
4de67c26 JM |
1723 | return true; |
1724 | } | |
1725 | ||
1726 | /* If the quantity is in a register not known to be GR, spill it. */ | |
1727 | if (register_operand (operands[1], mode)) | |
1728 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode); | |
1729 | ||
1730 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
1731 | ||
ae4d3291 JW |
1732 | /* Don't word-swap when reading in the value. */ |
1733 | out[0] = gen_rtx_REG (DImode, REGNO (op0)); | |
1734 | out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1); | |
4de67c26 JM |
1735 | |
1736 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); | |
1737 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
1738 | return true; | |
1739 | } | |
1740 | ||
1741 | if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1]))) | |
1742 | { | |
1743 | /* We're hoping to transform everything that deals with XFmode | |
1744 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1745 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1746 | |
1747 | /* Op0 can't be a GR_REG here, as that case is handled above. | |
1748 | If op0 is a register, then we spill op1, so that we now have a | |
1749 | MEM operand. This requires creating an XFmode subreg of a TImode reg | |
1750 | to force the spill. */ | |
1751 | if (register_operand (operands[0], mode)) | |
1752 | { | |
1753 | rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1])); | |
1754 | op1 = gen_rtx_SUBREG (mode, op1, 0); | |
1755 | operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode); | |
1756 | } | |
1757 | ||
1758 | else | |
1759 | { | |
1760 | rtx in[2]; | |
1761 | ||
ae4d3291 JW |
1762 | gcc_assert (GET_CODE (operands[0]) == MEM); |
1763 | ||
1764 | /* Don't word-swap when writing out the value. */ | |
1765 | in[0] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1766 | in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); | |
4de67c26 JM |
1767 | |
1768 | emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]); | |
1769 | emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]); | |
1770 | return true; | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | if (!reload_in_progress && !reload_completed) | |
1775 | { | |
1776 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode); | |
1777 | ||
1778 | if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG) | |
1779 | { | |
1780 | rtx memt, memx, in = operands[1]; | |
1781 | if (CONSTANT_P (in)) | |
1782 | in = validize_mem (force_const_mem (mode, in)); | |
1783 | if (GET_CODE (in) == MEM) | |
1784 | memt = adjust_address (in, TImode, 0); | |
1785 | else | |
1786 | { | |
9474e8ab | 1787 | memt = assign_stack_temp (TImode, 16); |
4de67c26 JM |
1788 | memx = adjust_address (memt, mode, 0); |
1789 | emit_move_insn (memx, in); | |
1790 | } | |
1791 | emit_move_insn (op0, memt); | |
1792 | return true; | |
1793 | } | |
1794 | ||
1795 | if (!ia64_move_ok (operands[0], operands[1])) | |
1796 | operands[1] = force_reg (mode, operands[1]); | |
1797 | } | |
1798 | ||
1799 | return false; | |
1800 | } | |
1801 | ||
f90b7a5a PB |
1802 | /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1 |
1803 | with the expression that holds the compare result (in VOIDmode). */ | |
f2f90c63 | 1804 | |
24ea7948 ZW |
1805 | static GTY(()) rtx cmptf_libfunc; |
1806 | ||
f90b7a5a PB |
1807 | void |
1808 | ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1) | |
f2f90c63 | 1809 | { |
f90b7a5a | 1810 | enum rtx_code code = GET_CODE (*expr); |
f2f90c63 RH |
1811 | rtx cmp; |
1812 | ||
1813 | /* If we have a BImode input, then we already have a compare result, and | |
1814 | do not need to emit another comparison. */ | |
f90b7a5a | 1815 | if (GET_MODE (*op0) == BImode) |
f2f90c63 | 1816 | { |
f90b7a5a PB |
1817 | gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx); |
1818 | cmp = *op0; | |
f2f90c63 | 1819 | } |
24ea7948 ZW |
1820 | /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a |
1821 | magic number as its third argument, that indicates what to do. | |
1822 | The return value is an integer to be compared against zero. */ | |
f90b7a5a | 1823 | else if (TARGET_HPUX && GET_MODE (*op0) == TFmode) |
24ea7948 ZW |
1824 | { |
1825 | enum qfcmp_magic { | |
8fc53a5f | 1826 | QCMP_INV = 1, /* Raise FP_INVALID on NaNs as a side effect. */ |
24ea7948 ZW |
1827 | QCMP_UNORD = 2, |
1828 | QCMP_EQ = 4, | |
1829 | QCMP_LT = 8, | |
1830 | QCMP_GT = 16 | |
32e8bb8e ILT |
1831 | }; |
1832 | int magic; | |
24ea7948 ZW |
1833 | enum rtx_code ncode; |
1834 | rtx ret, insns; | |
e820471b | 1835 | |
f90b7a5a | 1836 | gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode); |
24ea7948 ZW |
1837 | switch (code) |
1838 | { | |
1839 | /* 1 = equal, 0 = not equal. Equality operators do | |
8fc53a5f | 1840 | not raise FP_INVALID when given a NaN operand. */ |
24ea7948 ZW |
1841 | case EQ: magic = QCMP_EQ; ncode = NE; break; |
1842 | case NE: magic = QCMP_EQ; ncode = EQ; break; | |
1843 | /* isunordered() from C99. */ | |
1844 | case UNORDERED: magic = QCMP_UNORD; ncode = NE; break; | |
b1346fa3 | 1845 | case ORDERED: magic = QCMP_UNORD; ncode = EQ; break; |
24ea7948 | 1846 | /* Relational operators raise FP_INVALID when given |
8fc53a5f | 1847 | a NaN operand. */ |
24ea7948 ZW |
1848 | case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break; |
1849 | case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
1850 | case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break; | |
1851 | case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
8fc53a5f EB |
1852 | /* Unordered relational operators do not raise FP_INVALID |
1853 | when given a NaN operand. */ | |
1854 | case UNLT: magic = QCMP_LT |QCMP_UNORD; ncode = NE; break; | |
1855 | case UNLE: magic = QCMP_LT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1856 | case UNGT: magic = QCMP_GT |QCMP_UNORD; ncode = NE; break; | |
1857 | case UNGE: magic = QCMP_GT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1858 | /* Not supported. */ | |
1859 | case UNEQ: | |
1860 | case LTGT: | |
e820471b | 1861 | default: gcc_unreachable (); |
24ea7948 ZW |
1862 | } |
1863 | ||
1864 | start_sequence (); | |
1865 | ||
1866 | ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3, | |
f90b7a5a | 1867 | *op0, TFmode, *op1, TFmode, |
24ea7948 ZW |
1868 | GEN_INT (magic), DImode); |
1869 | cmp = gen_reg_rtx (BImode); | |
1870 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
1871 | gen_rtx_fmt_ee (ncode, BImode, | |
1872 | ret, const0_rtx))); | |
1873 | ||
1874 | insns = get_insns (); | |
1875 | end_sequence (); | |
1876 | ||
1877 | emit_libcall_block (insns, cmp, cmp, | |
f90b7a5a | 1878 | gen_rtx_fmt_ee (code, BImode, *op0, *op1)); |
24ea7948 ZW |
1879 | code = NE; |
1880 | } | |
f2f90c63 RH |
1881 | else |
1882 | { | |
1883 | cmp = gen_reg_rtx (BImode); | |
1884 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
f90b7a5a | 1885 | gen_rtx_fmt_ee (code, BImode, *op0, *op1))); |
f2f90c63 RH |
1886 | code = NE; |
1887 | } | |
1888 | ||
f90b7a5a PB |
1889 | *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx); |
1890 | *op0 = cmp; | |
1891 | *op1 = const0_rtx; | |
f2f90c63 | 1892 | } |
2ed4af6f | 1893 | |
e934ca47 RH |
1894 | /* Generate an integral vector comparison. Return true if the condition has |
1895 | been reversed, and so the sense of the comparison should be inverted. */ | |
f61134e8 RH |
1896 | |
1897 | static bool | |
ef4bddc2 | 1898 | ia64_expand_vecint_compare (enum rtx_code code, machine_mode mode, |
f61134e8 RH |
1899 | rtx dest, rtx op0, rtx op1) |
1900 | { | |
1901 | bool negate = false; | |
1902 | rtx x; | |
1903 | ||
e934ca47 | 1904 | /* Canonicalize the comparison to EQ, GT, GTU. */ |
f61134e8 RH |
1905 | switch (code) |
1906 | { | |
1907 | case EQ: | |
1908 | case GT: | |
e934ca47 | 1909 | case GTU: |
f61134e8 RH |
1910 | break; |
1911 | ||
1912 | case NE: | |
f61134e8 | 1913 | case LE: |
e934ca47 RH |
1914 | case LEU: |
1915 | code = reverse_condition (code); | |
f61134e8 RH |
1916 | negate = true; |
1917 | break; | |
1918 | ||
1919 | case GE: | |
e934ca47 RH |
1920 | case GEU: |
1921 | code = reverse_condition (code); | |
f61134e8 RH |
1922 | negate = true; |
1923 | /* FALLTHRU */ | |
1924 | ||
1925 | case LT: | |
f61134e8 | 1926 | case LTU: |
e934ca47 RH |
1927 | code = swap_condition (code); |
1928 | x = op0, op0 = op1, op1 = x; | |
1929 | break; | |
f61134e8 | 1930 | |
e934ca47 RH |
1931 | default: |
1932 | gcc_unreachable (); | |
1933 | } | |
f61134e8 | 1934 | |
e934ca47 | 1935 | /* Unsigned parallel compare is not supported by the hardware. Play some |
6283ba26 | 1936 | tricks to turn this into a signed comparison against 0. */ |
e934ca47 RH |
1937 | if (code == GTU) |
1938 | { | |
1939 | switch (mode) | |
1940 | { | |
1941 | case V2SImode: | |
f61134e8 | 1942 | { |
e934ca47 RH |
1943 | rtx t1, t2, mask; |
1944 | ||
9540f5ef SE |
1945 | /* Subtract (-(INT MAX) - 1) from both operands to make |
1946 | them signed. */ | |
1947 | mask = GEN_INT (0x80000000); | |
e934ca47 | 1948 | mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask)); |
9540f5ef SE |
1949 | mask = force_reg (mode, mask); |
1950 | t1 = gen_reg_rtx (mode); | |
1951 | emit_insn (gen_subv2si3 (t1, op0, mask)); | |
1952 | t2 = gen_reg_rtx (mode); | |
1953 | emit_insn (gen_subv2si3 (t2, op1, mask)); | |
1954 | op0 = t1; | |
1955 | op1 = t2; | |
6283ba26 | 1956 | code = GT; |
f61134e8 | 1957 | } |
e934ca47 RH |
1958 | break; |
1959 | ||
1960 | case V8QImode: | |
1961 | case V4HImode: | |
1962 | /* Perform a parallel unsigned saturating subtraction. */ | |
1963 | x = gen_reg_rtx (mode); | |
1964 | emit_insn (gen_rtx_SET (VOIDmode, x, | |
1965 | gen_rtx_US_MINUS (mode, op0, op1))); | |
6283ba26 RH |
1966 | |
1967 | code = EQ; | |
1968 | op0 = x; | |
1969 | op1 = CONST0_RTX (mode); | |
1970 | negate = !negate; | |
e934ca47 RH |
1971 | break; |
1972 | ||
1973 | default: | |
1974 | gcc_unreachable (); | |
1975 | } | |
f61134e8 RH |
1976 | } |
1977 | ||
1978 | x = gen_rtx_fmt_ee (code, mode, op0, op1); | |
1979 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
1980 | ||
1981 | return negate; | |
1982 | } | |
1983 | ||
f61134e8 RH |
1984 | /* Emit an integral vector conditional move. */ |
1985 | ||
1986 | void | |
1987 | ia64_expand_vecint_cmov (rtx operands[]) | |
1988 | { | |
ef4bddc2 | 1989 | machine_mode mode = GET_MODE (operands[0]); |
f61134e8 RH |
1990 | enum rtx_code code = GET_CODE (operands[3]); |
1991 | bool negate; | |
1992 | rtx cmp, x, ot, of; | |
1993 | ||
f61134e8 RH |
1994 | cmp = gen_reg_rtx (mode); |
1995 | negate = ia64_expand_vecint_compare (code, mode, cmp, | |
1996 | operands[4], operands[5]); | |
1997 | ||
1998 | ot = operands[1+negate]; | |
1999 | of = operands[2-negate]; | |
2000 | ||
2001 | if (ot == CONST0_RTX (mode)) | |
2002 | { | |
2003 | if (of == CONST0_RTX (mode)) | |
2004 | { | |
2005 | emit_move_insn (operands[0], ot); | |
2006 | return; | |
2007 | } | |
2008 | ||
2009 | x = gen_rtx_NOT (mode, cmp); | |
2010 | x = gen_rtx_AND (mode, x, of); | |
2011 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
2012 | } | |
2013 | else if (of == CONST0_RTX (mode)) | |
2014 | { | |
2015 | x = gen_rtx_AND (mode, cmp, ot); | |
2016 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
2017 | } | |
2018 | else | |
2019 | { | |
2020 | rtx t, f; | |
2021 | ||
2022 | t = gen_reg_rtx (mode); | |
2023 | x = gen_rtx_AND (mode, cmp, operands[1+negate]); | |
2024 | emit_insn (gen_rtx_SET (VOIDmode, t, x)); | |
2025 | ||
2026 | f = gen_reg_rtx (mode); | |
2027 | x = gen_rtx_NOT (mode, cmp); | |
2028 | x = gen_rtx_AND (mode, x, operands[2-negate]); | |
2029 | emit_insn (gen_rtx_SET (VOIDmode, f, x)); | |
2030 | ||
2031 | x = gen_rtx_IOR (mode, t, f); | |
2032 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
2033 | } | |
2034 | } | |
2035 | ||
2036 | /* Emit an integral vector min or max operation. Return true if all done. */ | |
2037 | ||
2038 | bool | |
ef4bddc2 | 2039 | ia64_expand_vecint_minmax (enum rtx_code code, machine_mode mode, |
f61134e8 RH |
2040 | rtx operands[]) |
2041 | { | |
cabddb23 | 2042 | rtx xops[6]; |
f61134e8 RH |
2043 | |
2044 | /* These four combinations are supported directly. */ | |
2045 | if (mode == V8QImode && (code == UMIN || code == UMAX)) | |
2046 | return false; | |
2047 | if (mode == V4HImode && (code == SMIN || code == SMAX)) | |
2048 | return false; | |
2049 | ||
93b4080b RH |
2050 | /* This combination can be implemented with only saturating subtraction. */ |
2051 | if (mode == V4HImode && code == UMAX) | |
2052 | { | |
2053 | rtx x, tmp = gen_reg_rtx (mode); | |
2054 | ||
2055 | x = gen_rtx_US_MINUS (mode, operands[1], operands[2]); | |
2056 | emit_insn (gen_rtx_SET (VOIDmode, tmp, x)); | |
2057 | ||
2058 | emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2])); | |
2059 | return true; | |
2060 | } | |
2061 | ||
f61134e8 RH |
2062 | /* Everything else implemented via vector comparisons. */ |
2063 | xops[0] = operands[0]; | |
2064 | xops[4] = xops[1] = operands[1]; | |
2065 | xops[5] = xops[2] = operands[2]; | |
2066 | ||
2067 | switch (code) | |
2068 | { | |
2069 | case UMIN: | |
2070 | code = LTU; | |
2071 | break; | |
2072 | case UMAX: | |
2073 | code = GTU; | |
2074 | break; | |
2075 | case SMIN: | |
2076 | code = LT; | |
2077 | break; | |
2078 | case SMAX: | |
2079 | code = GT; | |
2080 | break; | |
2081 | default: | |
e820471b | 2082 | gcc_unreachable (); |
f61134e8 RH |
2083 | } |
2084 | xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]); | |
2085 | ||
2086 | ia64_expand_vecint_cmov (xops); | |
2087 | return true; | |
2088 | } | |
2089 | ||
55eaaa5b RH |
2090 | /* The vectors LO and HI each contain N halves of a double-wide vector. |
2091 | Reassemble either the first N/2 or the second N/2 elements. */ | |
604e3ff3 RH |
2092 | |
2093 | void | |
55eaaa5b | 2094 | ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp) |
604e3ff3 | 2095 | { |
ef4bddc2 | 2096 | machine_mode vmode = GET_MODE (lo); |
e6431744 RH |
2097 | unsigned int i, high, nelt = GET_MODE_NUNITS (vmode); |
2098 | struct expand_vec_perm_d d; | |
2099 | bool ok; | |
604e3ff3 | 2100 | |
e6431744 RH |
2101 | d.target = gen_lowpart (vmode, out); |
2102 | d.op0 = (TARGET_BIG_ENDIAN ? hi : lo); | |
2103 | d.op1 = (TARGET_BIG_ENDIAN ? lo : hi); | |
2104 | d.vmode = vmode; | |
2105 | d.nelt = nelt; | |
2106 | d.one_operand_p = false; | |
2107 | d.testing_p = false; | |
2108 | ||
2109 | high = (highp ? nelt / 2 : 0); | |
2110 | for (i = 0; i < nelt / 2; ++i) | |
604e3ff3 | 2111 | { |
e6431744 RH |
2112 | d.perm[i * 2] = i + high; |
2113 | d.perm[i * 2 + 1] = i + high + nelt; | |
604e3ff3 RH |
2114 | } |
2115 | ||
e6431744 RH |
2116 | ok = ia64_expand_vec_perm_const_1 (&d); |
2117 | gcc_assert (ok); | |
604e3ff3 RH |
2118 | } |
2119 | ||
55eaaa5b | 2120 | /* Return a vector of the sign-extension of VEC. */ |
e898620c | 2121 | |
55eaaa5b RH |
2122 | static rtx |
2123 | ia64_unpack_sign (rtx vec, bool unsignedp) | |
e898620c | 2124 | { |
ef4bddc2 | 2125 | machine_mode mode = GET_MODE (vec); |
55eaaa5b | 2126 | rtx zero = CONST0_RTX (mode); |
e898620c | 2127 | |
e898620c | 2128 | if (unsignedp) |
55eaaa5b | 2129 | return zero; |
e898620c RH |
2130 | else |
2131 | { | |
55eaaa5b | 2132 | rtx sign = gen_reg_rtx (mode); |
e898620c RH |
2133 | bool neg; |
2134 | ||
55eaaa5b | 2135 | neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero); |
e898620c | 2136 | gcc_assert (!neg); |
55eaaa5b RH |
2137 | |
2138 | return sign; | |
e898620c | 2139 | } |
55eaaa5b | 2140 | } |
e898620c | 2141 | |
55eaaa5b | 2142 | /* Emit an integral vector unpack operation. */ |
e898620c | 2143 | |
55eaaa5b RH |
2144 | void |
2145 | ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp) | |
2146 | { | |
2147 | rtx sign = ia64_unpack_sign (operands[1], unsignedp); | |
2148 | ia64_unpack_assemble (operands[0], operands[1], sign, highp); | |
e898620c RH |
2149 | } |
2150 | ||
55eaaa5b RH |
2151 | /* Emit an integral vector widening sum operations. */ |
2152 | ||
604e3ff3 | 2153 | void |
55eaaa5b | 2154 | ia64_expand_widen_sum (rtx operands[3], bool unsignedp) |
604e3ff3 | 2155 | { |
ef4bddc2 | 2156 | machine_mode wmode; |
55eaaa5b | 2157 | rtx l, h, t, sign; |
604e3ff3 | 2158 | |
55eaaa5b RH |
2159 | sign = ia64_unpack_sign (operands[1], unsignedp); |
2160 | ||
2161 | wmode = GET_MODE (operands[0]); | |
2162 | l = gen_reg_rtx (wmode); | |
2163 | h = gen_reg_rtx (wmode); | |
604e3ff3 | 2164 | |
55eaaa5b RH |
2165 | ia64_unpack_assemble (l, operands[1], sign, false); |
2166 | ia64_unpack_assemble (h, operands[1], sign, true); | |
604e3ff3 | 2167 | |
55eaaa5b RH |
2168 | t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT); |
2169 | t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT); | |
2170 | if (t != operands[0]) | |
2171 | emit_move_insn (operands[0], t); | |
604e3ff3 RH |
2172 | } |
2173 | ||
2ed4af6f RH |
2174 | /* Emit the appropriate sequence for a call. */ |
2175 | ||
2176 | void | |
9c808aad AJ |
2177 | ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED, |
2178 | int sibcall_p) | |
2ed4af6f | 2179 | { |
599aedd9 | 2180 | rtx insn, b0; |
2ed4af6f RH |
2181 | |
2182 | addr = XEXP (addr, 0); | |
c8083186 | 2183 | addr = convert_memory_address (DImode, addr); |
2ed4af6f | 2184 | b0 = gen_rtx_REG (DImode, R_BR (0)); |
2ed4af6f | 2185 | |
599aedd9 | 2186 | /* ??? Should do this for functions known to bind local too. */ |
2ed4af6f RH |
2187 | if (TARGET_NO_PIC || TARGET_AUTO_PIC) |
2188 | { | |
2189 | if (sibcall_p) | |
599aedd9 | 2190 | insn = gen_sibcall_nogp (addr); |
2ed4af6f | 2191 | else if (! retval) |
599aedd9 | 2192 | insn = gen_call_nogp (addr, b0); |
2ed4af6f | 2193 | else |
599aedd9 RH |
2194 | insn = gen_call_value_nogp (retval, addr, b0); |
2195 | insn = emit_call_insn (insn); | |
2ed4af6f | 2196 | } |
2ed4af6f | 2197 | else |
599aedd9 RH |
2198 | { |
2199 | if (sibcall_p) | |
2200 | insn = gen_sibcall_gp (addr); | |
2201 | else if (! retval) | |
2202 | insn = gen_call_gp (addr, b0); | |
2203 | else | |
2204 | insn = gen_call_value_gp (retval, addr, b0); | |
2205 | insn = emit_call_insn (insn); | |
2ed4af6f | 2206 | |
599aedd9 RH |
2207 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2208 | } | |
6dad5a56 | 2209 | |
599aedd9 | 2210 | if (sibcall_p) |
4e14f1f9 | 2211 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0); |
f2972bf8 DR |
2212 | |
2213 | if (TARGET_ABI_OPEN_VMS) | |
2214 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2215 | gen_rtx_REG (DImode, GR_REG (25))); | |
599aedd9 RH |
2216 | } |
2217 | ||
6fb5fa3c DB |
2218 | static void |
2219 | reg_emitted (enum ia64_frame_regs r) | |
2220 | { | |
2221 | if (emitted_frame_related_regs[r] == 0) | |
2222 | emitted_frame_related_regs[r] = current_frame_info.r[r]; | |
2223 | else | |
2224 | gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]); | |
2225 | } | |
2226 | ||
2227 | static int | |
2228 | get_reg (enum ia64_frame_regs r) | |
2229 | { | |
2230 | reg_emitted (r); | |
2231 | return current_frame_info.r[r]; | |
2232 | } | |
2233 | ||
2234 | static bool | |
2235 | is_emitted (int regno) | |
2236 | { | |
09639a83 | 2237 | unsigned int r; |
6fb5fa3c DB |
2238 | |
2239 | for (r = reg_fp; r < number_of_ia64_frame_regs; r++) | |
2240 | if (emitted_frame_related_regs[r] == regno) | |
2241 | return true; | |
2242 | return false; | |
2243 | } | |
2244 | ||
599aedd9 | 2245 | void |
9c808aad | 2246 | ia64_reload_gp (void) |
599aedd9 RH |
2247 | { |
2248 | rtx tmp; | |
2249 | ||
6fb5fa3c DB |
2250 | if (current_frame_info.r[reg_save_gp]) |
2251 | { | |
2252 | tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp)); | |
2253 | } | |
2ed4af6f | 2254 | else |
599aedd9 RH |
2255 | { |
2256 | HOST_WIDE_INT offset; | |
13f70342 | 2257 | rtx offset_r; |
599aedd9 RH |
2258 | |
2259 | offset = (current_frame_info.spill_cfa_off | |
2260 | + current_frame_info.spill_size); | |
2261 | if (frame_pointer_needed) | |
2262 | { | |
2263 | tmp = hard_frame_pointer_rtx; | |
2264 | offset = -offset; | |
2265 | } | |
2266 | else | |
2267 | { | |
2268 | tmp = stack_pointer_rtx; | |
2269 | offset = current_frame_info.total_size - offset; | |
2270 | } | |
2271 | ||
13f70342 RH |
2272 | offset_r = GEN_INT (offset); |
2273 | if (satisfies_constraint_I (offset_r)) | |
2274 | emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r)); | |
599aedd9 RH |
2275 | else |
2276 | { | |
13f70342 | 2277 | emit_move_insn (pic_offset_table_rtx, offset_r); |
599aedd9 RH |
2278 | emit_insn (gen_adddi3 (pic_offset_table_rtx, |
2279 | pic_offset_table_rtx, tmp)); | |
2280 | } | |
2281 | ||
2282 | tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx); | |
2283 | } | |
2284 | ||
2285 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2286 | } | |
2287 | ||
2288 | void | |
9c808aad AJ |
2289 | ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r, |
2290 | rtx scratch_b, int noreturn_p, int sibcall_p) | |
599aedd9 RH |
2291 | { |
2292 | rtx insn; | |
2293 | bool is_desc = false; | |
2294 | ||
2295 | /* If we find we're calling through a register, then we're actually | |
2296 | calling through a descriptor, so load up the values. */ | |
4e14f1f9 | 2297 | if (REG_P (addr) && GR_REGNO_P (REGNO (addr))) |
599aedd9 RH |
2298 | { |
2299 | rtx tmp; | |
2300 | bool addr_dead_p; | |
2301 | ||
2302 | /* ??? We are currently constrained to *not* use peep2, because | |
2a43945f | 2303 | we can legitimately change the global lifetime of the GP |
9c808aad | 2304 | (in the form of killing where previously live). This is |
599aedd9 RH |
2305 | because a call through a descriptor doesn't use the previous |
2306 | value of the GP, while a direct call does, and we do not | |
2307 | commit to either form until the split here. | |
2308 | ||
2309 | That said, this means that we lack precise life info for | |
2310 | whether ADDR is dead after this call. This is not terribly | |
2311 | important, since we can fix things up essentially for free | |
2312 | with the POST_DEC below, but it's nice to not use it when we | |
2313 | can immediately tell it's not necessary. */ | |
2314 | addr_dead_p = ((noreturn_p || sibcall_p | |
2315 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, | |
2316 | REGNO (addr))) | |
2317 | && !FUNCTION_ARG_REGNO_P (REGNO (addr))); | |
2318 | ||
2319 | /* Load the code address into scratch_b. */ | |
2320 | tmp = gen_rtx_POST_INC (Pmode, addr); | |
2321 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2322 | emit_move_insn (scratch_r, tmp); | |
2323 | emit_move_insn (scratch_b, scratch_r); | |
2324 | ||
2325 | /* Load the GP address. If ADDR is not dead here, then we must | |
2326 | revert the change made above via the POST_INCREMENT. */ | |
2327 | if (!addr_dead_p) | |
2328 | tmp = gen_rtx_POST_DEC (Pmode, addr); | |
2329 | else | |
2330 | tmp = addr; | |
2331 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2332 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2333 | ||
2334 | is_desc = true; | |
2335 | addr = scratch_b; | |
2336 | } | |
2ed4af6f | 2337 | |
6dad5a56 | 2338 | if (sibcall_p) |
599aedd9 RH |
2339 | insn = gen_sibcall_nogp (addr); |
2340 | else if (retval) | |
2341 | insn = gen_call_value_nogp (retval, addr, retaddr); | |
6dad5a56 | 2342 | else |
599aedd9 | 2343 | insn = gen_call_nogp (addr, retaddr); |
6dad5a56 | 2344 | emit_call_insn (insn); |
2ed4af6f | 2345 | |
599aedd9 RH |
2346 | if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p) |
2347 | ia64_reload_gp (); | |
2ed4af6f | 2348 | } |
16df4ee6 RH |
2349 | |
2350 | /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically. | |
2351 | ||
2352 | This differs from the generic code in that we know about the zero-extending | |
2353 | properties of cmpxchg, and the zero-extending requirements of ar.ccv. We | |
2354 | also know that ld.acq+cmpxchg.rel equals a full barrier. | |
2355 | ||
2356 | The loop we want to generate looks like | |
2357 | ||
2358 | cmp_reg = mem; | |
2359 | label: | |
2360 | old_reg = cmp_reg; | |
2361 | new_reg = cmp_reg op val; | |
2362 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) | |
2363 | if (cmp_reg != old_reg) | |
2364 | goto label; | |
2365 | ||
2366 | Note that we only do the plain load from memory once. Subsequent | |
2367 | iterations use the value loaded by the compare-and-swap pattern. */ | |
2368 | ||
2369 | void | |
2370 | ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
28875d67 | 2371 | rtx old_dst, rtx new_dst, enum memmodel model) |
16df4ee6 | 2372 | { |
ef4bddc2 | 2373 | machine_mode mode = GET_MODE (mem); |
16df4ee6 RH |
2374 | rtx old_reg, new_reg, cmp_reg, ar_ccv, label; |
2375 | enum insn_code icode; | |
2376 | ||
2377 | /* Special case for using fetchadd. */ | |
dca13767 JJ |
2378 | if ((mode == SImode || mode == DImode) |
2379 | && (code == PLUS || code == MINUS) | |
2380 | && fetchadd_operand (val, mode)) | |
16df4ee6 | 2381 | { |
dca13767 JJ |
2382 | if (code == MINUS) |
2383 | val = GEN_INT (-INTVAL (val)); | |
2384 | ||
16df4ee6 RH |
2385 | if (!old_dst) |
2386 | old_dst = gen_reg_rtx (mode); | |
2387 | ||
28875d67 RH |
2388 | switch (model) |
2389 | { | |
2390 | case MEMMODEL_ACQ_REL: | |
2391 | case MEMMODEL_SEQ_CST: | |
2392 | emit_insn (gen_memory_barrier ()); | |
2393 | /* FALLTHRU */ | |
2394 | case MEMMODEL_RELAXED: | |
2395 | case MEMMODEL_ACQUIRE: | |
2396 | case MEMMODEL_CONSUME: | |
2397 | if (mode == SImode) | |
2398 | icode = CODE_FOR_fetchadd_acq_si; | |
2399 | else | |
2400 | icode = CODE_FOR_fetchadd_acq_di; | |
2401 | break; | |
2402 | case MEMMODEL_RELEASE: | |
2403 | if (mode == SImode) | |
2404 | icode = CODE_FOR_fetchadd_rel_si; | |
2405 | else | |
2406 | icode = CODE_FOR_fetchadd_rel_di; | |
2407 | break; | |
2408 | ||
2409 | default: | |
2410 | gcc_unreachable (); | |
2411 | } | |
16df4ee6 | 2412 | |
16df4ee6 RH |
2413 | emit_insn (GEN_FCN (icode) (old_dst, mem, val)); |
2414 | ||
2415 | if (new_dst) | |
2416 | { | |
2417 | new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst, | |
2418 | true, OPTAB_WIDEN); | |
2419 | if (new_reg != new_dst) | |
2420 | emit_move_insn (new_dst, new_reg); | |
2421 | } | |
2422 | return; | |
2423 | } | |
2424 | ||
2425 | /* Because of the volatile mem read, we get an ld.acq, which is the | |
28875d67 RH |
2426 | front half of the full barrier. The end half is the cmpxchg.rel. |
2427 | For relaxed and release memory models, we don't need this. But we | |
2428 | also don't bother trying to prevent it either. */ | |
2429 | gcc_assert (model == MEMMODEL_RELAXED | |
2430 | || model == MEMMODEL_RELEASE | |
2431 | || MEM_VOLATILE_P (mem)); | |
16df4ee6 RH |
2432 | |
2433 | old_reg = gen_reg_rtx (DImode); | |
2434 | cmp_reg = gen_reg_rtx (DImode); | |
2435 | label = gen_label_rtx (); | |
2436 | ||
2437 | if (mode != DImode) | |
2438 | { | |
2439 | val = simplify_gen_subreg (DImode, val, mode, 0); | |
2440 | emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1)); | |
2441 | } | |
2442 | else | |
2443 | emit_move_insn (cmp_reg, mem); | |
2444 | ||
2445 | emit_label (label); | |
2446 | ||
2447 | ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); | |
2448 | emit_move_insn (old_reg, cmp_reg); | |
2449 | emit_move_insn (ar_ccv, cmp_reg); | |
2450 | ||
2451 | if (old_dst) | |
2452 | emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg)); | |
2453 | ||
2454 | new_reg = cmp_reg; | |
2455 | if (code == NOT) | |
2456 | { | |
974920dc UB |
2457 | new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX, |
2458 | true, OPTAB_DIRECT); | |
2459 | new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true); | |
16df4ee6 | 2460 | } |
974920dc UB |
2461 | else |
2462 | new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX, | |
2463 | true, OPTAB_DIRECT); | |
16df4ee6 RH |
2464 | |
2465 | if (mode != DImode) | |
2466 | new_reg = gen_lowpart (mode, new_reg); | |
2467 | if (new_dst) | |
2468 | emit_move_insn (new_dst, new_reg); | |
2469 | ||
28875d67 | 2470 | switch (model) |
16df4ee6 | 2471 | { |
28875d67 RH |
2472 | case MEMMODEL_RELAXED: |
2473 | case MEMMODEL_ACQUIRE: | |
2474 | case MEMMODEL_CONSUME: | |
2475 | switch (mode) | |
2476 | { | |
2477 | case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break; | |
2478 | case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break; | |
2479 | case SImode: icode = CODE_FOR_cmpxchg_acq_si; break; | |
2480 | case DImode: icode = CODE_FOR_cmpxchg_acq_di; break; | |
2481 | default: | |
2482 | gcc_unreachable (); | |
2483 | } | |
2484 | break; | |
2485 | ||
2486 | case MEMMODEL_RELEASE: | |
2487 | case MEMMODEL_ACQ_REL: | |
2488 | case MEMMODEL_SEQ_CST: | |
2489 | switch (mode) | |
2490 | { | |
2491 | case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break; | |
2492 | case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break; | |
2493 | case SImode: icode = CODE_FOR_cmpxchg_rel_si; break; | |
2494 | case DImode: icode = CODE_FOR_cmpxchg_rel_di; break; | |
2495 | default: | |
2496 | gcc_unreachable (); | |
2497 | } | |
2498 | break; | |
2499 | ||
16df4ee6 RH |
2500 | default: |
2501 | gcc_unreachable (); | |
2502 | } | |
2503 | ||
2504 | emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg)); | |
2505 | ||
6819a463 | 2506 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label); |
16df4ee6 | 2507 | } |
809d4ef1 | 2508 | \f |
3b572406 RH |
2509 | /* Begin the assembly file. */ |
2510 | ||
1bc7c5b6 | 2511 | static void |
9c808aad | 2512 | ia64_file_start (void) |
1bc7c5b6 ZW |
2513 | { |
2514 | default_file_start (); | |
2515 | emit_safe_across_calls (); | |
2516 | } | |
2517 | ||
3b572406 | 2518 | void |
9c808aad | 2519 | emit_safe_across_calls (void) |
3b572406 RH |
2520 | { |
2521 | unsigned int rs, re; | |
2522 | int out_state; | |
2523 | ||
2524 | rs = 1; | |
2525 | out_state = 0; | |
2526 | while (1) | |
2527 | { | |
2528 | while (rs < 64 && call_used_regs[PR_REG (rs)]) | |
2529 | rs++; | |
2530 | if (rs >= 64) | |
2531 | break; | |
2532 | for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++) | |
2533 | continue; | |
2534 | if (out_state == 0) | |
2535 | { | |
1bc7c5b6 | 2536 | fputs ("\t.pred.safe_across_calls ", asm_out_file); |
3b572406 RH |
2537 | out_state = 1; |
2538 | } | |
2539 | else | |
1bc7c5b6 | 2540 | fputc (',', asm_out_file); |
3b572406 | 2541 | if (re == rs + 1) |
1bc7c5b6 | 2542 | fprintf (asm_out_file, "p%u", rs); |
3b572406 | 2543 | else |
1bc7c5b6 | 2544 | fprintf (asm_out_file, "p%u-p%u", rs, re - 1); |
3b572406 RH |
2545 | rs = re + 1; |
2546 | } | |
2547 | if (out_state) | |
1bc7c5b6 | 2548 | fputc ('\n', asm_out_file); |
3b572406 RH |
2549 | } |
2550 | ||
812b587e SE |
2551 | /* Globalize a declaration. */ |
2552 | ||
2553 | static void | |
2554 | ia64_globalize_decl_name (FILE * stream, tree decl) | |
2555 | { | |
2556 | const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
2557 | tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl)); | |
2558 | if (version_attr) | |
2559 | { | |
2560 | tree v = TREE_VALUE (TREE_VALUE (version_attr)); | |
2561 | const char *p = TREE_STRING_POINTER (v); | |
2562 | fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p); | |
2563 | } | |
2564 | targetm.asm_out.globalize_label (stream, name); | |
2565 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2566 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); | |
2567 | } | |
2568 | ||
97e242b0 RH |
2569 | /* Helper function for ia64_compute_frame_size: find an appropriate general |
2570 | register to spill some special register to. SPECIAL_SPILL_MASK contains | |
2571 | bits in GR0 to GR31 that have already been allocated by this routine. | |
2572 | TRY_LOCALS is true if we should attempt to locate a local regnum. */ | |
c65ebc55 | 2573 | |
97e242b0 | 2574 | static int |
6fb5fa3c | 2575 | find_gr_spill (enum ia64_frame_regs r, int try_locals) |
97e242b0 RH |
2576 | { |
2577 | int regno; | |
2578 | ||
6fb5fa3c DB |
2579 | if (emitted_frame_related_regs[r] != 0) |
2580 | { | |
2581 | regno = emitted_frame_related_regs[r]; | |
2951f79b JJ |
2582 | if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed) |
2583 | && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1) | |
6fb5fa3c | 2584 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; |
416ff32e | 2585 | else if (crtl->is_leaf |
6fb5fa3c DB |
2586 | && regno >= GR_REG (1) && regno <= GR_REG (31)) |
2587 | current_frame_info.gr_used_mask |= 1 << regno; | |
2588 | ||
2589 | return regno; | |
2590 | } | |
2591 | ||
97e242b0 RH |
2592 | /* If this is a leaf function, first try an otherwise unused |
2593 | call-clobbered register. */ | |
416ff32e | 2594 | if (crtl->is_leaf) |
97e242b0 RH |
2595 | { |
2596 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) | |
6fb5fa3c | 2597 | if (! df_regs_ever_live_p (regno) |
97e242b0 RH |
2598 | && call_used_regs[regno] |
2599 | && ! fixed_regs[regno] | |
2600 | && ! global_regs[regno] | |
6fb5fa3c DB |
2601 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0 |
2602 | && ! is_emitted (regno)) | |
97e242b0 RH |
2603 | { |
2604 | current_frame_info.gr_used_mask |= 1 << regno; | |
2605 | return regno; | |
2606 | } | |
2607 | } | |
2608 | ||
2609 | if (try_locals) | |
2610 | { | |
2611 | regno = current_frame_info.n_local_regs; | |
9502c558 JW |
2612 | /* If there is a frame pointer, then we can't use loc79, because |
2613 | that is HARD_FRAME_POINTER_REGNUM. In particular, see the | |
2614 | reg_name switching code in ia64_expand_prologue. */ | |
2951f79b JJ |
2615 | while (regno < (80 - frame_pointer_needed)) |
2616 | if (! is_emitted (LOC_REG (regno++))) | |
2617 | { | |
2618 | current_frame_info.n_local_regs = regno; | |
2619 | return LOC_REG (regno - 1); | |
2620 | } | |
97e242b0 RH |
2621 | } |
2622 | ||
2623 | /* Failed to find a general register to spill to. Must use stack. */ | |
2624 | return 0; | |
2625 | } | |
2626 | ||
2627 | /* In order to make for nice schedules, we try to allocate every temporary | |
2628 | to a different register. We must of course stay away from call-saved, | |
2629 | fixed, and global registers. We must also stay away from registers | |
2630 | allocated in current_frame_info.gr_used_mask, since those include regs | |
2631 | used all through the prologue. | |
2632 | ||
2633 | Any register allocated here must be used immediately. The idea is to | |
2634 | aid scheduling, not to solve data flow problems. */ | |
2635 | ||
2636 | static int last_scratch_gr_reg; | |
2637 | ||
2638 | static int | |
9c808aad | 2639 | next_scratch_gr_reg (void) |
97e242b0 RH |
2640 | { |
2641 | int i, regno; | |
2642 | ||
2643 | for (i = 0; i < 32; ++i) | |
2644 | { | |
2645 | regno = (last_scratch_gr_reg + i + 1) & 31; | |
2646 | if (call_used_regs[regno] | |
2647 | && ! fixed_regs[regno] | |
2648 | && ! global_regs[regno] | |
2649 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0) | |
2650 | { | |
2651 | last_scratch_gr_reg = regno; | |
2652 | return regno; | |
2653 | } | |
2654 | } | |
2655 | ||
2656 | /* There must be _something_ available. */ | |
e820471b | 2657 | gcc_unreachable (); |
97e242b0 RH |
2658 | } |
2659 | ||
2660 | /* Helper function for ia64_compute_frame_size, called through | |
2661 | diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */ | |
2662 | ||
2663 | static void | |
9c808aad | 2664 | mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED) |
c65ebc55 | 2665 | { |
97e242b0 RH |
2666 | unsigned int regno = REGNO (reg); |
2667 | if (regno < 32) | |
f95e79cc | 2668 | { |
c8b622ff | 2669 | unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)]; |
f95e79cc RH |
2670 | for (i = 0; i < n; ++i) |
2671 | current_frame_info.gr_used_mask |= 1 << (regno + i); | |
2672 | } | |
c65ebc55 JW |
2673 | } |
2674 | ||
6fb5fa3c | 2675 | |
c65ebc55 JW |
2676 | /* Returns the number of bytes offset between the frame pointer and the stack |
2677 | pointer for the current function. SIZE is the number of bytes of space | |
2678 | needed for local variables. */ | |
97e242b0 RH |
2679 | |
2680 | static void | |
9c808aad | 2681 | ia64_compute_frame_size (HOST_WIDE_INT size) |
c65ebc55 | 2682 | { |
97e242b0 RH |
2683 | HOST_WIDE_INT total_size; |
2684 | HOST_WIDE_INT spill_size = 0; | |
2685 | HOST_WIDE_INT extra_spill_size = 0; | |
2686 | HOST_WIDE_INT pretend_args_size; | |
c65ebc55 | 2687 | HARD_REG_SET mask; |
97e242b0 RH |
2688 | int n_spilled = 0; |
2689 | int spilled_gr_p = 0; | |
2690 | int spilled_fr_p = 0; | |
2691 | unsigned int regno; | |
2951f79b JJ |
2692 | int min_regno; |
2693 | int max_regno; | |
97e242b0 | 2694 | int i; |
c65ebc55 | 2695 | |
97e242b0 RH |
2696 | if (current_frame_info.initialized) |
2697 | return; | |
294dac80 | 2698 | |
97e242b0 | 2699 | memset (¤t_frame_info, 0, sizeof current_frame_info); |
c65ebc55 JW |
2700 | CLEAR_HARD_REG_SET (mask); |
2701 | ||
97e242b0 RH |
2702 | /* Don't allocate scratches to the return register. */ |
2703 | diddle_return_value (mark_reg_gr_used_mask, NULL); | |
2704 | ||
2705 | /* Don't allocate scratches to the EH scratch registers. */ | |
2706 | if (cfun->machine->ia64_eh_epilogue_sp) | |
2707 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL); | |
2708 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
2709 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL); | |
c65ebc55 | 2710 | |
7b84aac0 EB |
2711 | /* Static stack checking uses r2 and r3. */ |
2712 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) | |
2713 | current_frame_info.gr_used_mask |= 0xc; | |
2714 | ||
97e242b0 RH |
2715 | /* Find the size of the register stack frame. We have only 80 local |
2716 | registers, because we reserve 8 for the inputs and 8 for the | |
2717 | outputs. */ | |
2718 | ||
2719 | /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed, | |
2720 | since we'll be adjusting that down later. */ | |
2721 | regno = LOC_REG (78) + ! frame_pointer_needed; | |
2722 | for (; regno >= LOC_REG (0); regno--) | |
6fb5fa3c | 2723 | if (df_regs_ever_live_p (regno) && !is_emitted (regno)) |
97e242b0 RH |
2724 | break; |
2725 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; | |
c65ebc55 | 2726 | |
3f67ac08 DM |
2727 | /* For functions marked with the syscall_linkage attribute, we must mark |
2728 | all eight input registers as in use, so that locals aren't visible to | |
2729 | the caller. */ | |
2730 | ||
2731 | if (cfun->machine->n_varargs > 0 | |
2732 | || lookup_attribute ("syscall_linkage", | |
2733 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
97e242b0 RH |
2734 | current_frame_info.n_input_regs = 8; |
2735 | else | |
2736 | { | |
2737 | for (regno = IN_REG (7); regno >= IN_REG (0); regno--) | |
6fb5fa3c | 2738 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2739 | break; |
2740 | current_frame_info.n_input_regs = regno - IN_REG (0) + 1; | |
2741 | } | |
2742 | ||
2743 | for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--) | |
6fb5fa3c | 2744 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2745 | break; |
2746 | i = regno - OUT_REG (0) + 1; | |
2747 | ||
d26afa4f | 2748 | #ifndef PROFILE_HOOK |
97e242b0 | 2749 | /* When -p profiling, we need one output register for the mcount argument. |
9e4f94de | 2750 | Likewise for -a profiling for the bb_init_func argument. For -ax |
97e242b0 RH |
2751 | profiling, we need two output registers for the two bb_init_trace_func |
2752 | arguments. */ | |
e3b5732b | 2753 | if (crtl->profile) |
97e242b0 | 2754 | i = MAX (i, 1); |
d26afa4f | 2755 | #endif |
97e242b0 RH |
2756 | current_frame_info.n_output_regs = i; |
2757 | ||
2758 | /* ??? No rotating register support yet. */ | |
2759 | current_frame_info.n_rotate_regs = 0; | |
2760 | ||
2761 | /* Discover which registers need spilling, and how much room that | |
9c808aad | 2762 | will take. Begin with floating point and general registers, |
97e242b0 RH |
2763 | which will always wind up on the stack. */ |
2764 | ||
2765 | for (regno = FR_REG (2); regno <= FR_REG (127); regno++) | |
6fb5fa3c | 2766 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2767 | { |
2768 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2769 | spill_size += 16; |
2770 | n_spilled += 1; | |
2771 | spilled_fr_p = 1; | |
c65ebc55 JW |
2772 | } |
2773 | ||
97e242b0 | 2774 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) |
6fb5fa3c | 2775 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2776 | { |
2777 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2778 | spill_size += 8; |
2779 | n_spilled += 1; | |
2780 | spilled_gr_p = 1; | |
c65ebc55 JW |
2781 | } |
2782 | ||
97e242b0 | 2783 | for (regno = BR_REG (1); regno <= BR_REG (7); regno++) |
6fb5fa3c | 2784 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2785 | { |
2786 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2787 | spill_size += 8; |
2788 | n_spilled += 1; | |
c65ebc55 JW |
2789 | } |
2790 | ||
97e242b0 RH |
2791 | /* Now come all special registers that might get saved in other |
2792 | general registers. */ | |
9c808aad | 2793 | |
97e242b0 RH |
2794 | if (frame_pointer_needed) |
2795 | { | |
6fb5fa3c | 2796 | current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1); |
0c35f902 JW |
2797 | /* If we did not get a register, then we take LOC79. This is guaranteed |
2798 | to be free, even if regs_ever_live is already set, because this is | |
2799 | HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs, | |
2800 | as we don't count loc79 above. */ | |
6fb5fa3c | 2801 | if (current_frame_info.r[reg_fp] == 0) |
0c35f902 | 2802 | { |
6fb5fa3c DB |
2803 | current_frame_info.r[reg_fp] = LOC_REG (79); |
2804 | current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1; | |
0c35f902 | 2805 | } |
97e242b0 RH |
2806 | } |
2807 | ||
416ff32e | 2808 | if (! crtl->is_leaf) |
c65ebc55 | 2809 | { |
97e242b0 RH |
2810 | /* Emit a save of BR0 if we call other functions. Do this even |
2811 | if this function doesn't return, as EH depends on this to be | |
2812 | able to unwind the stack. */ | |
2813 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
2814 | ||
6fb5fa3c DB |
2815 | current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1); |
2816 | if (current_frame_info.r[reg_save_b0] == 0) | |
97e242b0 | 2817 | { |
ae1e2d4c | 2818 | extra_spill_size += 8; |
97e242b0 RH |
2819 | n_spilled += 1; |
2820 | } | |
2821 | ||
2822 | /* Similarly for ar.pfs. */ | |
2823 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2824 | current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1); |
2825 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
97e242b0 RH |
2826 | { |
2827 | extra_spill_size += 8; | |
2828 | n_spilled += 1; | |
2829 | } | |
599aedd9 RH |
2830 | |
2831 | /* Similarly for gp. Note that if we're calling setjmp, the stacked | |
2832 | registers are clobbered, so we fall back to the stack. */ | |
6fb5fa3c | 2833 | current_frame_info.r[reg_save_gp] |
e3b5732b | 2834 | = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1)); |
6fb5fa3c | 2835 | if (current_frame_info.r[reg_save_gp] == 0) |
599aedd9 RH |
2836 | { |
2837 | SET_HARD_REG_BIT (mask, GR_REG (1)); | |
2838 | spill_size += 8; | |
2839 | n_spilled += 1; | |
2840 | } | |
c65ebc55 JW |
2841 | } |
2842 | else | |
97e242b0 | 2843 | { |
6fb5fa3c | 2844 | if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)]) |
97e242b0 RH |
2845 | { |
2846 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
ae1e2d4c | 2847 | extra_spill_size += 8; |
97e242b0 RH |
2848 | n_spilled += 1; |
2849 | } | |
f5bdba44 | 2850 | |
6fb5fa3c | 2851 | if (df_regs_ever_live_p (AR_PFS_REGNUM)) |
f5bdba44 RH |
2852 | { |
2853 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2854 | current_frame_info.r[reg_save_ar_pfs] |
2855 | = find_gr_spill (reg_save_ar_pfs, 1); | |
2856 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
f5bdba44 RH |
2857 | { |
2858 | extra_spill_size += 8; | |
2859 | n_spilled += 1; | |
2860 | } | |
2861 | } | |
97e242b0 | 2862 | } |
c65ebc55 | 2863 | |
97e242b0 RH |
2864 | /* Unwind descriptor hackery: things are most efficient if we allocate |
2865 | consecutive GR save registers for RP, PFS, FP in that order. However, | |
2866 | it is absolutely critical that FP get the only hard register that's | |
2867 | guaranteed to be free, so we allocated it first. If all three did | |
2868 | happen to be allocated hard regs, and are consecutive, rearrange them | |
6fb5fa3c DB |
2869 | into the preferred order now. |
2870 | ||
2871 | If we have already emitted code for any of those registers, | |
2872 | then it's already too late to change. */ | |
2951f79b JJ |
2873 | min_regno = MIN (current_frame_info.r[reg_fp], |
2874 | MIN (current_frame_info.r[reg_save_b0], | |
2875 | current_frame_info.r[reg_save_ar_pfs])); | |
2876 | max_regno = MAX (current_frame_info.r[reg_fp], | |
2877 | MAX (current_frame_info.r[reg_save_b0], | |
2878 | current_frame_info.r[reg_save_ar_pfs])); | |
2879 | if (min_regno > 0 | |
2880 | && min_regno + 2 == max_regno | |
2881 | && (current_frame_info.r[reg_fp] == min_regno + 1 | |
2882 | || current_frame_info.r[reg_save_b0] == min_regno + 1 | |
2883 | || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1) | |
2884 | && (emitted_frame_related_regs[reg_save_b0] == 0 | |
2885 | || emitted_frame_related_regs[reg_save_b0] == min_regno) | |
2886 | && (emitted_frame_related_regs[reg_save_ar_pfs] == 0 | |
2887 | || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1) | |
2888 | && (emitted_frame_related_regs[reg_fp] == 0 | |
2889 | || emitted_frame_related_regs[reg_fp] == min_regno + 2)) | |
5527bf14 | 2890 | { |
2951f79b JJ |
2891 | current_frame_info.r[reg_save_b0] = min_regno; |
2892 | current_frame_info.r[reg_save_ar_pfs] = min_regno + 1; | |
2893 | current_frame_info.r[reg_fp] = min_regno + 2; | |
5527bf14 RH |
2894 | } |
2895 | ||
97e242b0 RH |
2896 | /* See if we need to store the predicate register block. */ |
2897 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2898 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
97e242b0 RH |
2899 | break; |
2900 | if (regno <= PR_REG (63)) | |
c65ebc55 | 2901 | { |
97e242b0 | 2902 | SET_HARD_REG_BIT (mask, PR_REG (0)); |
6fb5fa3c DB |
2903 | current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1); |
2904 | if (current_frame_info.r[reg_save_pr] == 0) | |
97e242b0 RH |
2905 | { |
2906 | extra_spill_size += 8; | |
2907 | n_spilled += 1; | |
2908 | } | |
2909 | ||
2910 | /* ??? Mark them all as used so that register renaming and such | |
2911 | are free to use them. */ | |
2912 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2913 | df_set_regs_ever_live (regno, true); |
c65ebc55 JW |
2914 | } |
2915 | ||
97e242b0 | 2916 | /* If we're forced to use st8.spill, we're forced to save and restore |
f5bdba44 RH |
2917 | ar.unat as well. The check for existing liveness allows inline asm |
2918 | to touch ar.unat. */ | |
2919 | if (spilled_gr_p || cfun->machine->n_varargs | |
6fb5fa3c | 2920 | || df_regs_ever_live_p (AR_UNAT_REGNUM)) |
97e242b0 | 2921 | { |
6fb5fa3c | 2922 | df_set_regs_ever_live (AR_UNAT_REGNUM, true); |
97e242b0 | 2923 | SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM); |
6fb5fa3c DB |
2924 | current_frame_info.r[reg_save_ar_unat] |
2925 | = find_gr_spill (reg_save_ar_unat, spill_size == 0); | |
2926 | if (current_frame_info.r[reg_save_ar_unat] == 0) | |
97e242b0 RH |
2927 | { |
2928 | extra_spill_size += 8; | |
2929 | n_spilled += 1; | |
2930 | } | |
2931 | } | |
2932 | ||
6fb5fa3c | 2933 | if (df_regs_ever_live_p (AR_LC_REGNUM)) |
97e242b0 RH |
2934 | { |
2935 | SET_HARD_REG_BIT (mask, AR_LC_REGNUM); | |
6fb5fa3c DB |
2936 | current_frame_info.r[reg_save_ar_lc] |
2937 | = find_gr_spill (reg_save_ar_lc, spill_size == 0); | |
2938 | if (current_frame_info.r[reg_save_ar_lc] == 0) | |
97e242b0 RH |
2939 | { |
2940 | extra_spill_size += 8; | |
2941 | n_spilled += 1; | |
2942 | } | |
2943 | } | |
2944 | ||
2945 | /* If we have an odd number of words of pretend arguments written to | |
2946 | the stack, then the FR save area will be unaligned. We round the | |
2947 | size of this area up to keep things 16 byte aligned. */ | |
2948 | if (spilled_fr_p) | |
38173d38 | 2949 | pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size); |
97e242b0 | 2950 | else |
38173d38 | 2951 | pretend_args_size = crtl->args.pretend_args_size; |
97e242b0 RH |
2952 | |
2953 | total_size = (spill_size + extra_spill_size + size + pretend_args_size | |
38173d38 | 2954 | + crtl->outgoing_args_size); |
97e242b0 RH |
2955 | total_size = IA64_STACK_ALIGN (total_size); |
2956 | ||
2957 | /* We always use the 16-byte scratch area provided by the caller, but | |
2958 | if we are a leaf function, there's no one to which we need to provide | |
44bd7f65 EB |
2959 | a scratch area. However, if the function allocates dynamic stack space, |
2960 | the dynamic offset is computed early and contains STACK_POINTER_OFFSET, | |
2961 | so we need to cope. */ | |
2962 | if (crtl->is_leaf && !cfun->calls_alloca) | |
97e242b0 RH |
2963 | total_size = MAX (0, total_size - 16); |
2964 | ||
c65ebc55 | 2965 | current_frame_info.total_size = total_size; |
97e242b0 RH |
2966 | current_frame_info.spill_cfa_off = pretend_args_size - 16; |
2967 | current_frame_info.spill_size = spill_size; | |
2968 | current_frame_info.extra_spill_size = extra_spill_size; | |
c65ebc55 | 2969 | COPY_HARD_REG_SET (current_frame_info.mask, mask); |
97e242b0 | 2970 | current_frame_info.n_spilled = n_spilled; |
c65ebc55 | 2971 | current_frame_info.initialized = reload_completed; |
97e242b0 RH |
2972 | } |
2973 | ||
7b5cbb57 AS |
2974 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2975 | ||
2976 | bool | |
2977 | ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
2978 | { | |
416ff32e | 2979 | return (to == BR_REG (0) ? crtl->is_leaf : true); |
7b5cbb57 AS |
2980 | } |
2981 | ||
97e242b0 RH |
2982 | /* Compute the initial difference between the specified pair of registers. */ |
2983 | ||
2984 | HOST_WIDE_INT | |
9c808aad | 2985 | ia64_initial_elimination_offset (int from, int to) |
97e242b0 RH |
2986 | { |
2987 | HOST_WIDE_INT offset; | |
2988 | ||
2989 | ia64_compute_frame_size (get_frame_size ()); | |
2990 | switch (from) | |
2991 | { | |
2992 | case FRAME_POINTER_REGNUM: | |
e820471b | 2993 | switch (to) |
97e242b0 | 2994 | { |
e820471b | 2995 | case HARD_FRAME_POINTER_REGNUM: |
44bd7f65 EB |
2996 | offset = -current_frame_info.total_size; |
2997 | if (!crtl->is_leaf || cfun->calls_alloca) | |
2998 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
2999 | break; |
3000 | ||
3001 | case STACK_POINTER_REGNUM: | |
44bd7f65 EB |
3002 | offset = 0; |
3003 | if (!crtl->is_leaf || cfun->calls_alloca) | |
3004 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
3005 | break; |
3006 | ||
3007 | default: | |
3008 | gcc_unreachable (); | |
97e242b0 | 3009 | } |
97e242b0 | 3010 | break; |
c65ebc55 | 3011 | |
97e242b0 RH |
3012 | case ARG_POINTER_REGNUM: |
3013 | /* Arguments start above the 16 byte save area, unless stdarg | |
3014 | in which case we store through the 16 byte save area. */ | |
e820471b NS |
3015 | switch (to) |
3016 | { | |
3017 | case HARD_FRAME_POINTER_REGNUM: | |
38173d38 | 3018 | offset = 16 - crtl->args.pretend_args_size; |
e820471b NS |
3019 | break; |
3020 | ||
3021 | case STACK_POINTER_REGNUM: | |
3022 | offset = (current_frame_info.total_size | |
38173d38 | 3023 | + 16 - crtl->args.pretend_args_size); |
e820471b NS |
3024 | break; |
3025 | ||
3026 | default: | |
3027 | gcc_unreachable (); | |
3028 | } | |
97e242b0 RH |
3029 | break; |
3030 | ||
97e242b0 | 3031 | default: |
e820471b | 3032 | gcc_unreachable (); |
97e242b0 RH |
3033 | } |
3034 | ||
3035 | return offset; | |
c65ebc55 JW |
3036 | } |
3037 | ||
97e242b0 RH |
3038 | /* If there are more than a trivial number of register spills, we use |
3039 | two interleaved iterators so that we can get two memory references | |
3040 | per insn group. | |
3041 | ||
3042 | In order to simplify things in the prologue and epilogue expanders, | |
3043 | we use helper functions to fix up the memory references after the | |
3044 | fact with the appropriate offsets to a POST_MODIFY memory mode. | |
3045 | The following data structure tracks the state of the two iterators | |
3046 | while insns are being emitted. */ | |
3047 | ||
3048 | struct spill_fill_data | |
c65ebc55 | 3049 | { |
dd3d2b35 | 3050 | rtx_insn *init_after; /* point at which to emit initializations */ |
97e242b0 RH |
3051 | rtx init_reg[2]; /* initial base register */ |
3052 | rtx iter_reg[2]; /* the iterator registers */ | |
3053 | rtx *prev_addr[2]; /* address of last memory use */ | |
dd3d2b35 | 3054 | rtx_insn *prev_insn[2]; /* the insn corresponding to prev_addr */ |
97e242b0 RH |
3055 | HOST_WIDE_INT prev_off[2]; /* last offset */ |
3056 | int n_iter; /* number of iterators in use */ | |
3057 | int next_iter; /* next iterator to use */ | |
3058 | unsigned int save_gr_used_mask; | |
3059 | }; | |
3060 | ||
3061 | static struct spill_fill_data spill_fill_data; | |
c65ebc55 | 3062 | |
97e242b0 | 3063 | static void |
9c808aad | 3064 | setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3065 | { |
3066 | int i; | |
3067 | ||
3068 | spill_fill_data.init_after = get_last_insn (); | |
3069 | spill_fill_data.init_reg[0] = init_reg; | |
3070 | spill_fill_data.init_reg[1] = init_reg; | |
3071 | spill_fill_data.prev_addr[0] = NULL; | |
3072 | spill_fill_data.prev_addr[1] = NULL; | |
703cf211 BS |
3073 | spill_fill_data.prev_insn[0] = NULL; |
3074 | spill_fill_data.prev_insn[1] = NULL; | |
97e242b0 RH |
3075 | spill_fill_data.prev_off[0] = cfa_off; |
3076 | spill_fill_data.prev_off[1] = cfa_off; | |
3077 | spill_fill_data.next_iter = 0; | |
3078 | spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask; | |
3079 | ||
3080 | spill_fill_data.n_iter = 1 + (n_spills > 2); | |
3081 | for (i = 0; i < spill_fill_data.n_iter; ++i) | |
c65ebc55 | 3082 | { |
97e242b0 RH |
3083 | int regno = next_scratch_gr_reg (); |
3084 | spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno); | |
3085 | current_frame_info.gr_used_mask |= 1 << regno; | |
3086 | } | |
3087 | } | |
3088 | ||
3089 | static void | |
9c808aad | 3090 | finish_spill_pointers (void) |
97e242b0 RH |
3091 | { |
3092 | current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask; | |
3093 | } | |
c65ebc55 | 3094 | |
97e242b0 | 3095 | static rtx |
9c808aad | 3096 | spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3097 | { |
3098 | int iter = spill_fill_data.next_iter; | |
3099 | HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off; | |
3100 | rtx disp_rtx = GEN_INT (disp); | |
3101 | rtx mem; | |
3102 | ||
3103 | if (spill_fill_data.prev_addr[iter]) | |
3104 | { | |
13f70342 | 3105 | if (satisfies_constraint_N (disp_rtx)) |
703cf211 BS |
3106 | { |
3107 | *spill_fill_data.prev_addr[iter] | |
3108 | = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter], | |
3109 | gen_rtx_PLUS (DImode, | |
3110 | spill_fill_data.iter_reg[iter], | |
3111 | disp_rtx)); | |
bbbbb16a ILT |
3112 | add_reg_note (spill_fill_data.prev_insn[iter], |
3113 | REG_INC, spill_fill_data.iter_reg[iter]); | |
703cf211 | 3114 | } |
c65ebc55 JW |
3115 | else |
3116 | { | |
97e242b0 | 3117 | /* ??? Could use register post_modify for loads. */ |
13f70342 | 3118 | if (!satisfies_constraint_I (disp_rtx)) |
97e242b0 RH |
3119 | { |
3120 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); | |
3121 | emit_move_insn (tmp, disp_rtx); | |
3122 | disp_rtx = tmp; | |
3123 | } | |
3124 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3125 | spill_fill_data.iter_reg[iter], disp_rtx)); | |
c65ebc55 | 3126 | } |
97e242b0 RH |
3127 | } |
3128 | /* Micro-optimization: if we've created a frame pointer, it's at | |
3129 | CFA 0, which may allow the real iterator to be initialized lower, | |
3130 | slightly increasing parallelism. Also, if there are few saves | |
3131 | it may eliminate the iterator entirely. */ | |
3132 | else if (disp == 0 | |
3133 | && spill_fill_data.init_reg[iter] == stack_pointer_rtx | |
3134 | && frame_pointer_needed) | |
3135 | { | |
3136 | mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx); | |
ba4828e0 | 3137 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
97e242b0 RH |
3138 | return mem; |
3139 | } | |
3140 | else | |
3141 | { | |
dd3d2b35 DM |
3142 | rtx seq; |
3143 | rtx_insn *insn; | |
809d4ef1 | 3144 | |
97e242b0 RH |
3145 | if (disp == 0) |
3146 | seq = gen_movdi (spill_fill_data.iter_reg[iter], | |
3147 | spill_fill_data.init_reg[iter]); | |
3148 | else | |
c65ebc55 | 3149 | { |
97e242b0 RH |
3150 | start_sequence (); |
3151 | ||
13f70342 | 3152 | if (!satisfies_constraint_I (disp_rtx)) |
c65ebc55 | 3153 | { |
97e242b0 RH |
3154 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); |
3155 | emit_move_insn (tmp, disp_rtx); | |
3156 | disp_rtx = tmp; | |
c65ebc55 | 3157 | } |
97e242b0 RH |
3158 | |
3159 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3160 | spill_fill_data.init_reg[iter], | |
3161 | disp_rtx)); | |
3162 | ||
2f937369 | 3163 | seq = get_insns (); |
97e242b0 | 3164 | end_sequence (); |
c65ebc55 | 3165 | } |
809d4ef1 | 3166 | |
97e242b0 RH |
3167 | /* Careful for being the first insn in a sequence. */ |
3168 | if (spill_fill_data.init_after) | |
892a4e60 | 3169 | insn = emit_insn_after (seq, spill_fill_data.init_after); |
97e242b0 | 3170 | else |
bc08aefe | 3171 | { |
dd3d2b35 | 3172 | rtx_insn *first = get_insns (); |
bc08aefe | 3173 | if (first) |
892a4e60 | 3174 | insn = emit_insn_before (seq, first); |
bc08aefe | 3175 | else |
892a4e60 | 3176 | insn = emit_insn (seq); |
bc08aefe | 3177 | } |
892a4e60 | 3178 | spill_fill_data.init_after = insn; |
97e242b0 | 3179 | } |
c65ebc55 | 3180 | |
97e242b0 | 3181 | mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]); |
c65ebc55 | 3182 | |
97e242b0 RH |
3183 | /* ??? Not all of the spills are for varargs, but some of them are. |
3184 | The rest of the spills belong in an alias set of their own. But | |
3185 | it doesn't actually hurt to include them here. */ | |
ba4828e0 | 3186 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
809d4ef1 | 3187 | |
97e242b0 RH |
3188 | spill_fill_data.prev_addr[iter] = &XEXP (mem, 0); |
3189 | spill_fill_data.prev_off[iter] = cfa_off; | |
c65ebc55 | 3190 | |
97e242b0 RH |
3191 | if (++iter >= spill_fill_data.n_iter) |
3192 | iter = 0; | |
3193 | spill_fill_data.next_iter = iter; | |
c65ebc55 | 3194 | |
97e242b0 RH |
3195 | return mem; |
3196 | } | |
5527bf14 | 3197 | |
97e242b0 | 3198 | static void |
9c808aad AJ |
3199 | do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off, |
3200 | rtx frame_reg) | |
97e242b0 | 3201 | { |
703cf211 | 3202 | int iter = spill_fill_data.next_iter; |
dd3d2b35 DM |
3203 | rtx mem; |
3204 | rtx_insn *insn; | |
5527bf14 | 3205 | |
97e242b0 | 3206 | mem = spill_restore_mem (reg, cfa_off); |
870f9ec0 | 3207 | insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off))); |
703cf211 | 3208 | spill_fill_data.prev_insn[iter] = insn; |
5527bf14 | 3209 | |
97e242b0 RH |
3210 | if (frame_reg) |
3211 | { | |
3212 | rtx base; | |
3213 | HOST_WIDE_INT off; | |
3214 | ||
3215 | RTX_FRAME_RELATED_P (insn) = 1; | |
3216 | ||
9c808aad | 3217 | /* Don't even pretend that the unwind code can intuit its way |
97e242b0 RH |
3218 | through a pair of interleaved post_modify iterators. Just |
3219 | provide the correct answer. */ | |
3220 | ||
3221 | if (frame_pointer_needed) | |
3222 | { | |
3223 | base = hard_frame_pointer_rtx; | |
3224 | off = - cfa_off; | |
5527bf14 | 3225 | } |
97e242b0 RH |
3226 | else |
3227 | { | |
3228 | base = stack_pointer_rtx; | |
3229 | off = current_frame_info.total_size - cfa_off; | |
3230 | } | |
3231 | ||
5c255b57 | 3232 | add_reg_note (insn, REG_CFA_OFFSET, |
bbbbb16a ILT |
3233 | gen_rtx_SET (VOIDmode, |
3234 | gen_rtx_MEM (GET_MODE (reg), | |
0a81f074 RS |
3235 | plus_constant (Pmode, |
3236 | base, off)), | |
bbbbb16a | 3237 | frame_reg)); |
c65ebc55 JW |
3238 | } |
3239 | } | |
3240 | ||
97e242b0 | 3241 | static void |
9c808aad | 3242 | do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 | 3243 | { |
703cf211 | 3244 | int iter = spill_fill_data.next_iter; |
dd3d2b35 | 3245 | rtx_insn *insn; |
703cf211 BS |
3246 | |
3247 | insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off), | |
3248 | GEN_INT (cfa_off))); | |
3249 | spill_fill_data.prev_insn[iter] = insn; | |
97e242b0 RH |
3250 | } |
3251 | ||
870f9ec0 RH |
3252 | /* Wrapper functions that discards the CONST_INT spill offset. These |
3253 | exist so that we can give gr_spill/gr_fill the offset they need and | |
9e4f94de | 3254 | use a consistent function interface. */ |
870f9ec0 RH |
3255 | |
3256 | static rtx | |
9c808aad | 3257 | gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3258 | { |
3259 | return gen_movdi (dest, src); | |
3260 | } | |
3261 | ||
3262 | static rtx | |
9c808aad | 3263 | gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3264 | { |
3265 | return gen_fr_spill (dest, src); | |
3266 | } | |
3267 | ||
3268 | static rtx | |
9c808aad | 3269 | gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3270 | { |
3271 | return gen_fr_restore (dest, src); | |
3272 | } | |
c65ebc55 | 3273 | |
7b84aac0 EB |
3274 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
3275 | ||
3276 | /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */ | |
3277 | #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0) | |
3278 | ||
3279 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
0dca9cd8 EB |
3280 | inclusive. These are offsets from the current stack pointer. BS_SIZE |
3281 | is the size of the backing store. ??? This clobbers r2 and r3. */ | |
7b84aac0 EB |
3282 | |
3283 | static void | |
0dca9cd8 EB |
3284 | ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size, |
3285 | int bs_size) | |
7b84aac0 | 3286 | { |
7b84aac0 EB |
3287 | rtx r2 = gen_rtx_REG (Pmode, GR_REG (2)); |
3288 | rtx r3 = gen_rtx_REG (Pmode, GR_REG (3)); | |
0dca9cd8 EB |
3289 | rtx p6 = gen_rtx_REG (BImode, PR_REG (6)); |
3290 | ||
3291 | /* On the IA-64 there is a second stack in memory, namely the Backing Store | |
3292 | of the Register Stack Engine. We also need to probe it after checking | |
3293 | that the 2 stacks don't overlap. */ | |
3294 | emit_insn (gen_bsp_value (r3)); | |
3295 | emit_move_insn (r2, GEN_INT (-(first + size))); | |
3296 | ||
3297 | /* Compare current value of BSP and SP registers. */ | |
3298 | emit_insn (gen_rtx_SET (VOIDmode, p6, | |
3299 | gen_rtx_fmt_ee (LTU, BImode, | |
3300 | r3, stack_pointer_rtx))); | |
3301 | ||
3302 | /* Compute the address of the probe for the Backing Store (which grows | |
3303 | towards higher addresses). We probe only at the first offset of | |
3304 | the next page because some OS (eg Linux/ia64) only extend the | |
3305 | backing store when this specific address is hit (but generate a SEGV | |
3306 | on other address). Page size is the worst case (4KB). The reserve | |
3307 | size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough. | |
3308 | Also compute the address of the last probe for the memory stack | |
3309 | (which grows towards lower addresses). */ | |
3310 | emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095))); | |
3311 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3312 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3313 | ||
3314 | /* Compare them and raise SEGV if the former has topped the latter. */ | |
3315 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3316 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
3317 | gen_rtx_SET (VOIDmode, p6, | |
3318 | gen_rtx_fmt_ee (GEU, BImode, | |
3319 | r3, r2)))); | |
3320 | emit_insn (gen_rtx_SET (VOIDmode, | |
3321 | gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12), | |
3322 | const0_rtx), | |
3323 | const0_rtx)); | |
3324 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3325 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
3326 | gen_rtx_TRAP_IF (VOIDmode, const1_rtx, | |
3327 | GEN_INT (11)))); | |
7b84aac0 EB |
3328 | |
3329 | /* Probe the Backing Store if necessary. */ | |
3330 | if (bs_size > 0) | |
3331 | emit_stack_probe (r3); | |
3332 | ||
3333 | /* Probe the memory stack if necessary. */ | |
3334 | if (size == 0) | |
3335 | ; | |
3336 | ||
3337 | /* See if we have a constant small number of probes to generate. If so, | |
3338 | that's the easy case. */ | |
3339 | else if (size <= PROBE_INTERVAL) | |
3340 | emit_stack_probe (r2); | |
3341 | ||
3342 | /* The run-time loop is made up of 8 insns in the generic case while this | |
3343 | compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */ | |
3344 | else if (size <= 4 * PROBE_INTERVAL) | |
3345 | { | |
3346 | HOST_WIDE_INT i; | |
3347 | ||
3348 | emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL))); | |
3349 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3350 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3351 | emit_stack_probe (r2); | |
3352 | ||
3353 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until | |
3354 | it exceeds SIZE. If only two probes are needed, this will not | |
3355 | generate any code. Then probe at FIRST + SIZE. */ | |
3356 | for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
3357 | { | |
3358 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3359 | plus_constant (Pmode, r2, -PROBE_INTERVAL))); |
7b84aac0 EB |
3360 | emit_stack_probe (r2); |
3361 | } | |
3362 | ||
3363 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3364 | plus_constant (Pmode, r2, |
7b84aac0 EB |
3365 | (i - PROBE_INTERVAL) - size))); |
3366 | emit_stack_probe (r2); | |
3367 | } | |
3368 | ||
3369 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
3370 | extra careful with variables wrapping around because we might be at | |
3371 | the very top (or the very bottom) of the address space and we have | |
3372 | to be able to handle this case properly; in particular, we use an | |
3373 | equality test for the loop condition. */ | |
3374 | else | |
3375 | { | |
3376 | HOST_WIDE_INT rounded_size; | |
3377 | ||
3378 | emit_move_insn (r2, GEN_INT (-first)); | |
3379 | ||
3380 | ||
3381 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
3382 | ||
3383 | rounded_size = size & -PROBE_INTERVAL; | |
3384 | ||
3385 | ||
3386 | /* Step 2: compute initial and final value of the loop counter. */ | |
3387 | ||
3388 | /* TEST_ADDR = SP + FIRST. */ | |
3389 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3390 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3391 | ||
3392 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
3393 | if (rounded_size > (1 << 21)) | |
3394 | { | |
3395 | emit_move_insn (r3, GEN_INT (-rounded_size)); | |
3396 | emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3))); | |
3397 | } | |
3398 | else | |
3399 | emit_insn (gen_rtx_SET (VOIDmode, r3, | |
3400 | gen_rtx_PLUS (Pmode, r2, | |
3401 | GEN_INT (-rounded_size)))); | |
3402 | ||
3403 | ||
3404 | /* Step 3: the loop | |
3405 | ||
3406 | while (TEST_ADDR != LAST_ADDR) | |
3407 | { | |
3408 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
3409 | probe at TEST_ADDR | |
3410 | } | |
3411 | ||
3412 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
3413 | until it is equal to ROUNDED_SIZE. */ | |
3414 | ||
3415 | emit_insn (gen_probe_stack_range (r2, r2, r3)); | |
3416 | ||
3417 | ||
3418 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
3419 | that SIZE is equal to ROUNDED_SIZE. */ | |
3420 | ||
3421 | /* TEMP = SIZE - ROUNDED_SIZE. */ | |
3422 | if (size != rounded_size) | |
3423 | { | |
3424 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 TG |
3425 | plus_constant (Pmode, r2, |
3426 | rounded_size - size))); | |
7b84aac0 EB |
3427 | emit_stack_probe (r2); |
3428 | } | |
3429 | } | |
3430 | ||
3431 | /* Make sure nothing is scheduled before we are done. */ | |
3432 | emit_insn (gen_blockage ()); | |
3433 | } | |
3434 | ||
3435 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
3436 | absolute addresses. */ | |
3437 | ||
3438 | const char * | |
3439 | output_probe_stack_range (rtx reg1, rtx reg2) | |
3440 | { | |
3441 | static int labelno = 0; | |
3442 | char loop_lab[32], end_lab[32]; | |
3443 | rtx xops[3]; | |
3444 | ||
3445 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno); | |
3446 | ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++); | |
3447 | ||
3448 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
3449 | ||
3450 | /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */ | |
3451 | xops[0] = reg1; | |
3452 | xops[1] = reg2; | |
3453 | xops[2] = gen_rtx_REG (BImode, PR_REG (6)); | |
3454 | output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops); | |
3455 | fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]); | |
3456 | assemble_name_raw (asm_out_file, end_lab); | |
3457 | fputc ('\n', asm_out_file); | |
3458 | ||
3459 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ | |
3460 | xops[1] = GEN_INT (-PROBE_INTERVAL); | |
3461 | output_asm_insn ("addl %0 = %1, %0", xops); | |
3462 | fputs ("\t;;\n", asm_out_file); | |
3463 | ||
3464 | /* Probe at TEST_ADDR and branch. */ | |
3465 | output_asm_insn ("probe.w.fault %0, 0", xops); | |
3466 | fprintf (asm_out_file, "\tbr "); | |
3467 | assemble_name_raw (asm_out_file, loop_lab); | |
3468 | fputc ('\n', asm_out_file); | |
3469 | ||
3470 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab); | |
3471 | ||
3472 | return ""; | |
3473 | } | |
3474 | ||
c65ebc55 JW |
3475 | /* Called after register allocation to add any instructions needed for the |
3476 | prologue. Using a prologue insn is favored compared to putting all of the | |
08c148a8 | 3477 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3478 | to intermix instructions with the saves of the caller saved registers. In |
3479 | some cases, it might be necessary to emit a barrier instruction as the last | |
3480 | insn to prevent such scheduling. | |
3481 | ||
3482 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
97e242b0 RH |
3483 | so that the debug info generation code can handle them properly. |
3484 | ||
073a8998 | 3485 | The register save area is laid out like so: |
97e242b0 RH |
3486 | cfa+16 |
3487 | [ varargs spill area ] | |
3488 | [ fr register spill area ] | |
3489 | [ br register spill area ] | |
3490 | [ ar register spill area ] | |
3491 | [ pr register spill area ] | |
3492 | [ gr register spill area ] */ | |
c65ebc55 JW |
3493 | |
3494 | /* ??? Get inefficient code when the frame size is larger than can fit in an | |
3495 | adds instruction. */ | |
3496 | ||
c65ebc55 | 3497 | void |
9c808aad | 3498 | ia64_expand_prologue (void) |
c65ebc55 | 3499 | { |
dd3d2b35 DM |
3500 | rtx_insn *insn; |
3501 | rtx ar_pfs_save_reg, ar_unat_save_reg; | |
97e242b0 RH |
3502 | int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs; |
3503 | rtx reg, alt_reg; | |
3504 | ||
3505 | ia64_compute_frame_size (get_frame_size ()); | |
3506 | last_scratch_gr_reg = 15; | |
3507 | ||
a11e0df4 | 3508 | if (flag_stack_usage_info) |
d3c12306 EB |
3509 | current_function_static_stack_size = current_frame_info.total_size; |
3510 | ||
7b84aac0 | 3511 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
0dca9cd8 EB |
3512 | { |
3513 | HOST_WIDE_INT size = current_frame_info.total_size; | |
3514 | int bs_size = BACKING_STORE_SIZE (current_frame_info.n_input_regs | |
3515 | + current_frame_info.n_local_regs); | |
3516 | ||
3517 | if (crtl->is_leaf && !cfun->calls_alloca) | |
3518 | { | |
3519 | if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) | |
3520 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
3521 | size - STACK_CHECK_PROTECT, | |
3522 | bs_size); | |
3523 | else if (size + bs_size > STACK_CHECK_PROTECT) | |
3524 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, 0, bs_size); | |
3525 | } | |
3526 | else if (size + bs_size > 0) | |
3527 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, size, bs_size); | |
3528 | } | |
7b84aac0 | 3529 | |
6fb5fa3c DB |
3530 | if (dump_file) |
3531 | { | |
3532 | fprintf (dump_file, "ia64 frame related registers " | |
3533 | "recorded in current_frame_info.r[]:\n"); | |
3534 | #define PRINTREG(a) if (current_frame_info.r[a]) \ | |
3535 | fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a]) | |
3536 | PRINTREG(reg_fp); | |
3537 | PRINTREG(reg_save_b0); | |
3538 | PRINTREG(reg_save_pr); | |
3539 | PRINTREG(reg_save_ar_pfs); | |
3540 | PRINTREG(reg_save_ar_unat); | |
3541 | PRINTREG(reg_save_ar_lc); | |
3542 | PRINTREG(reg_save_gp); | |
3543 | #undef PRINTREG | |
3544 | } | |
3545 | ||
97e242b0 RH |
3546 | /* If there is no epilogue, then we don't need some prologue insns. |
3547 | We need to avoid emitting the dead prologue insns, because flow | |
3548 | will complain about them. */ | |
c65ebc55 JW |
3549 | if (optimize) |
3550 | { | |
97e242b0 | 3551 | edge e; |
9924d7d8 | 3552 | edge_iterator ei; |
97e242b0 | 3553 | |
fefa31b5 | 3554 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) |
c65ebc55 JW |
3555 | if ((e->flags & EDGE_FAKE) == 0 |
3556 | && (e->flags & EDGE_FALLTHRU) != 0) | |
3557 | break; | |
3558 | epilogue_p = (e != NULL); | |
3559 | } | |
3560 | else | |
3561 | epilogue_p = 1; | |
3562 | ||
97e242b0 RH |
3563 | /* Set the local, input, and output register names. We need to do this |
3564 | for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in | |
3565 | half. If we use in/loc/out register names, then we get assembler errors | |
3566 | in crtn.S because there is no alloc insn or regstk directive in there. */ | |
3567 | if (! TARGET_REG_NAMES) | |
3568 | { | |
3569 | int inputs = current_frame_info.n_input_regs; | |
3570 | int locals = current_frame_info.n_local_regs; | |
3571 | int outputs = current_frame_info.n_output_regs; | |
3572 | ||
3573 | for (i = 0; i < inputs; i++) | |
3574 | reg_names[IN_REG (i)] = ia64_reg_numbers[i]; | |
3575 | for (i = 0; i < locals; i++) | |
3576 | reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i]; | |
3577 | for (i = 0; i < outputs; i++) | |
3578 | reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i]; | |
3579 | } | |
c65ebc55 | 3580 | |
97e242b0 RH |
3581 | /* Set the frame pointer register name. The regnum is logically loc79, |
3582 | but of course we'll not have allocated that many locals. Rather than | |
3583 | worrying about renumbering the existing rtxs, we adjust the name. */ | |
9502c558 JW |
3584 | /* ??? This code means that we can never use one local register when |
3585 | there is a frame pointer. loc79 gets wasted in this case, as it is | |
3586 | renamed to a register that will never be used. See also the try_locals | |
3587 | code in find_gr_spill. */ | |
6fb5fa3c | 3588 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
3589 | { |
3590 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
3591 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
3592 | = reg_names[current_frame_info.r[reg_fp]]; |
3593 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
97e242b0 | 3594 | } |
c65ebc55 | 3595 | |
97e242b0 RH |
3596 | /* We don't need an alloc instruction if we've used no outputs or locals. */ |
3597 | if (current_frame_info.n_local_regs == 0 | |
2ed4af6f | 3598 | && current_frame_info.n_output_regs == 0 |
38173d38 | 3599 | && current_frame_info.n_input_regs <= crtl->args.info.int_regs |
f5bdba44 | 3600 | && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
97e242b0 RH |
3601 | { |
3602 | /* If there is no alloc, but there are input registers used, then we | |
3603 | need a .regstk directive. */ | |
3604 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
3605 | ar_pfs_save_reg = NULL_RTX; | |
3606 | } | |
3607 | else | |
3608 | { | |
3609 | current_frame_info.need_regstk = 0; | |
c65ebc55 | 3610 | |
6fb5fa3c DB |
3611 | if (current_frame_info.r[reg_save_ar_pfs]) |
3612 | { | |
3613 | regno = current_frame_info.r[reg_save_ar_pfs]; | |
3614 | reg_emitted (reg_save_ar_pfs); | |
3615 | } | |
97e242b0 RH |
3616 | else |
3617 | regno = next_scratch_gr_reg (); | |
3618 | ar_pfs_save_reg = gen_rtx_REG (DImode, regno); | |
3619 | ||
9c808aad | 3620 | insn = emit_insn (gen_alloc (ar_pfs_save_reg, |
97e242b0 RH |
3621 | GEN_INT (current_frame_info.n_input_regs), |
3622 | GEN_INT (current_frame_info.n_local_regs), | |
3623 | GEN_INT (current_frame_info.n_output_regs), | |
3624 | GEN_INT (current_frame_info.n_rotate_regs))); | |
9f2ff8e5 RH |
3625 | if (current_frame_info.r[reg_save_ar_pfs]) |
3626 | { | |
3627 | RTX_FRAME_RELATED_P (insn) = 1; | |
3628 | add_reg_note (insn, REG_CFA_REGISTER, | |
3629 | gen_rtx_SET (VOIDmode, | |
3630 | ar_pfs_save_reg, | |
3631 | gen_rtx_REG (DImode, AR_PFS_REGNUM))); | |
3632 | } | |
97e242b0 | 3633 | } |
c65ebc55 | 3634 | |
97e242b0 | 3635 | /* Set up frame pointer, stack pointer, and spill iterators. */ |
c65ebc55 | 3636 | |
26a110f5 | 3637 | n_varargs = cfun->machine->n_varargs; |
97e242b0 RH |
3638 | setup_spill_pointers (current_frame_info.n_spilled + n_varargs, |
3639 | stack_pointer_rtx, 0); | |
c65ebc55 | 3640 | |
97e242b0 RH |
3641 | if (frame_pointer_needed) |
3642 | { | |
3643 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
3644 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3645 | |
3646 | /* Force the unwind info to recognize this as defining a new CFA, | |
3647 | rather than some temp register setup. */ | |
3648 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX); | |
97e242b0 | 3649 | } |
c65ebc55 | 3650 | |
97e242b0 RH |
3651 | if (current_frame_info.total_size != 0) |
3652 | { | |
3653 | rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size); | |
3654 | rtx offset; | |
c65ebc55 | 3655 | |
13f70342 | 3656 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
3657 | offset = frame_size_rtx; |
3658 | else | |
3659 | { | |
3660 | regno = next_scratch_gr_reg (); | |
9c808aad | 3661 | offset = gen_rtx_REG (DImode, regno); |
97e242b0 RH |
3662 | emit_move_insn (offset, frame_size_rtx); |
3663 | } | |
c65ebc55 | 3664 | |
97e242b0 RH |
3665 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, |
3666 | stack_pointer_rtx, offset)); | |
c65ebc55 | 3667 | |
97e242b0 RH |
3668 | if (! frame_pointer_needed) |
3669 | { | |
3670 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3671 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
3672 | gen_rtx_SET (VOIDmode, | |
3673 | stack_pointer_rtx, | |
3674 | gen_rtx_PLUS (DImode, | |
3675 | stack_pointer_rtx, | |
3676 | frame_size_rtx))); | |
97e242b0 | 3677 | } |
c65ebc55 | 3678 | |
97e242b0 RH |
3679 | /* ??? At this point we must generate a magic insn that appears to |
3680 | modify the stack pointer, the frame pointer, and all spill | |
3681 | iterators. This would allow the most scheduling freedom. For | |
3682 | now, just hard stop. */ | |
3683 | emit_insn (gen_blockage ()); | |
3684 | } | |
c65ebc55 | 3685 | |
97e242b0 RH |
3686 | /* Must copy out ar.unat before doing any integer spills. */ |
3687 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
c65ebc55 | 3688 | { |
6fb5fa3c DB |
3689 | if (current_frame_info.r[reg_save_ar_unat]) |
3690 | { | |
3691 | ar_unat_save_reg | |
3692 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3693 | reg_emitted (reg_save_ar_unat); | |
3694 | } | |
97e242b0 | 3695 | else |
c65ebc55 | 3696 | { |
97e242b0 RH |
3697 | alt_regno = next_scratch_gr_reg (); |
3698 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3699 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
c65ebc55 | 3700 | } |
c65ebc55 | 3701 | |
97e242b0 RH |
3702 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
3703 | insn = emit_move_insn (ar_unat_save_reg, reg); | |
5c255b57 RH |
3704 | if (current_frame_info.r[reg_save_ar_unat]) |
3705 | { | |
3706 | RTX_FRAME_RELATED_P (insn) = 1; | |
3707 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); | |
3708 | } | |
97e242b0 RH |
3709 | |
3710 | /* Even if we're not going to generate an epilogue, we still | |
3711 | need to save the register so that EH works. */ | |
6fb5fa3c | 3712 | if (! epilogue_p && current_frame_info.r[reg_save_ar_unat]) |
d0e82870 | 3713 | emit_insn (gen_prologue_use (ar_unat_save_reg)); |
c65ebc55 JW |
3714 | } |
3715 | else | |
97e242b0 RH |
3716 | ar_unat_save_reg = NULL_RTX; |
3717 | ||
3718 | /* Spill all varargs registers. Do this before spilling any GR registers, | |
3719 | since we want the UNAT bits for the GR registers to override the UNAT | |
3720 | bits from varargs, which we don't care about. */ | |
c65ebc55 | 3721 | |
97e242b0 RH |
3722 | cfa_off = -16; |
3723 | for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno) | |
c65ebc55 | 3724 | { |
97e242b0 | 3725 | reg = gen_rtx_REG (DImode, regno); |
870f9ec0 | 3726 | do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX); |
c65ebc55 | 3727 | } |
c65ebc55 | 3728 | |
97e242b0 RH |
3729 | /* Locate the bottom of the register save area. */ |
3730 | cfa_off = (current_frame_info.spill_cfa_off | |
3731 | + current_frame_info.spill_size | |
3732 | + current_frame_info.extra_spill_size); | |
c65ebc55 | 3733 | |
97e242b0 RH |
3734 | /* Save the predicate register block either in a register or in memory. */ |
3735 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3736 | { | |
3737 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
6fb5fa3c | 3738 | if (current_frame_info.r[reg_save_pr] != 0) |
1ff5b671 | 3739 | { |
6fb5fa3c DB |
3740 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); |
3741 | reg_emitted (reg_save_pr); | |
97e242b0 | 3742 | insn = emit_move_insn (alt_reg, reg); |
1ff5b671 | 3743 | |
97e242b0 RH |
3744 | /* ??? Denote pr spill/fill by a DImode move that modifies all |
3745 | 64 hard registers. */ | |
1ff5b671 | 3746 | RTX_FRAME_RELATED_P (insn) = 1; |
5c255b57 | 3747 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
46327bc5 | 3748 | |
97e242b0 RH |
3749 | /* Even if we're not going to generate an epilogue, we still |
3750 | need to save the register so that EH works. */ | |
3751 | if (! epilogue_p) | |
d0e82870 | 3752 | emit_insn (gen_prologue_use (alt_reg)); |
1ff5b671 JW |
3753 | } |
3754 | else | |
97e242b0 RH |
3755 | { |
3756 | alt_regno = next_scratch_gr_reg (); | |
3757 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3758 | insn = emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3759 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3760 | cfa_off -= 8; |
3761 | } | |
c65ebc55 JW |
3762 | } |
3763 | ||
97e242b0 RH |
3764 | /* Handle AR regs in numerical order. All of them get special handling. */ |
3765 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM) | |
6fb5fa3c | 3766 | && current_frame_info.r[reg_save_ar_unat] == 0) |
c65ebc55 | 3767 | { |
97e242b0 | 3768 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
870f9ec0 | 3769 | do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg); |
97e242b0 | 3770 | cfa_off -= 8; |
c65ebc55 | 3771 | } |
97e242b0 RH |
3772 | |
3773 | /* The alloc insn already copied ar.pfs into a general register. The | |
3774 | only thing we have to do now is copy that register to a stack slot | |
3775 | if we'd not allocated a local register for the job. */ | |
f5bdba44 | 3776 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM) |
6fb5fa3c | 3777 | && current_frame_info.r[reg_save_ar_pfs] == 0) |
c65ebc55 | 3778 | { |
97e242b0 | 3779 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
870f9ec0 | 3780 | do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg); |
97e242b0 RH |
3781 | cfa_off -= 8; |
3782 | } | |
3783 | ||
3784 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3785 | { | |
3786 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
6fb5fa3c | 3787 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
97e242b0 | 3788 | { |
6fb5fa3c DB |
3789 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); |
3790 | reg_emitted (reg_save_ar_lc); | |
97e242b0 RH |
3791 | insn = emit_move_insn (alt_reg, reg); |
3792 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 3793 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
97e242b0 RH |
3794 | |
3795 | /* Even if we're not going to generate an epilogue, we still | |
3796 | need to save the register so that EH works. */ | |
3797 | if (! epilogue_p) | |
d0e82870 | 3798 | emit_insn (gen_prologue_use (alt_reg)); |
97e242b0 | 3799 | } |
c65ebc55 JW |
3800 | else |
3801 | { | |
97e242b0 RH |
3802 | alt_regno = next_scratch_gr_reg (); |
3803 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3804 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3805 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3806 | cfa_off -= 8; |
3807 | } | |
3808 | } | |
3809 | ||
ae1e2d4c AS |
3810 | /* Save the return pointer. */ |
3811 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3812 | { | |
3813 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
6fb5fa3c | 3814 | if (current_frame_info.r[reg_save_b0] != 0) |
ae1e2d4c | 3815 | { |
6fb5fa3c DB |
3816 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); |
3817 | reg_emitted (reg_save_b0); | |
ae1e2d4c AS |
3818 | insn = emit_move_insn (alt_reg, reg); |
3819 | RTX_FRAME_RELATED_P (insn) = 1; | |
5f740973 RH |
3820 | add_reg_note (insn, REG_CFA_REGISTER, |
3821 | gen_rtx_SET (VOIDmode, alt_reg, pc_rtx)); | |
ae1e2d4c AS |
3822 | |
3823 | /* Even if we're not going to generate an epilogue, we still | |
3824 | need to save the register so that EH works. */ | |
3825 | if (! epilogue_p) | |
3826 | emit_insn (gen_prologue_use (alt_reg)); | |
3827 | } | |
3828 | else | |
3829 | { | |
3830 | alt_regno = next_scratch_gr_reg (); | |
3831 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3832 | emit_move_insn (alt_reg, reg); | |
3833 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); | |
3834 | cfa_off -= 8; | |
3835 | } | |
3836 | } | |
3837 | ||
6fb5fa3c | 3838 | if (current_frame_info.r[reg_save_gp]) |
599aedd9 | 3839 | { |
6fb5fa3c | 3840 | reg_emitted (reg_save_gp); |
599aedd9 | 3841 | insn = emit_move_insn (gen_rtx_REG (DImode, |
6fb5fa3c | 3842 | current_frame_info.r[reg_save_gp]), |
599aedd9 | 3843 | pic_offset_table_rtx); |
599aedd9 RH |
3844 | } |
3845 | ||
97e242b0 | 3846 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3847 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3848 | + current_frame_info.spill_size)); | |
97e242b0 RH |
3849 | |
3850 | /* Spill all general registers. */ | |
3851 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
3852 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3853 | { | |
3854 | reg = gen_rtx_REG (DImode, regno); | |
3855 | do_spill (gen_gr_spill, reg, cfa_off, reg); | |
3856 | cfa_off -= 8; | |
3857 | } | |
3858 | ||
97e242b0 RH |
3859 | /* Spill the rest of the BR registers. */ |
3860 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) | |
3861 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3862 | { | |
3863 | alt_regno = next_scratch_gr_reg (); | |
3864 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3865 | reg = gen_rtx_REG (DImode, regno); | |
3866 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3867 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3868 | cfa_off -= 8; |
3869 | } | |
3870 | ||
3871 | /* Align the frame and spill all FR registers. */ | |
3872 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
3873 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3874 | { | |
e820471b | 3875 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 3876 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 3877 | do_spill (gen_fr_spill_x, reg, cfa_off, reg); |
97e242b0 RH |
3878 | cfa_off -= 16; |
3879 | } | |
3880 | ||
e820471b | 3881 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
3882 | |
3883 | finish_spill_pointers (); | |
c65ebc55 JW |
3884 | } |
3885 | ||
8e7745dc DR |
3886 | /* Output the textual info surrounding the prologue. */ |
3887 | ||
3888 | void | |
3889 | ia64_start_function (FILE *file, const char *fnname, | |
3890 | tree decl ATTRIBUTE_UNUSED) | |
3891 | { | |
4b12e93d TG |
3892 | #if TARGET_ABI_OPEN_VMS |
3893 | vms_start_function (fnname); | |
8e7745dc DR |
3894 | #endif |
3895 | ||
3896 | fputs ("\t.proc ", file); | |
3897 | assemble_name (file, fnname); | |
3898 | fputc ('\n', file); | |
3899 | ASM_OUTPUT_LABEL (file, fnname); | |
3900 | } | |
3901 | ||
c65ebc55 | 3902 | /* Called after register allocation to add any instructions needed for the |
5519a4f9 | 3903 | epilogue. Using an epilogue insn is favored compared to putting all of the |
08c148a8 | 3904 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3905 | to intermix instructions with the saves of the caller saved registers. In |
3906 | some cases, it might be necessary to emit a barrier instruction as the last | |
3907 | insn to prevent such scheduling. */ | |
3908 | ||
3909 | void | |
9c808aad | 3910 | ia64_expand_epilogue (int sibcall_p) |
c65ebc55 | 3911 | { |
dd3d2b35 DM |
3912 | rtx_insn *insn; |
3913 | rtx reg, alt_reg, ar_unat_save_reg; | |
97e242b0 RH |
3914 | int regno, alt_regno, cfa_off; |
3915 | ||
3916 | ia64_compute_frame_size (get_frame_size ()); | |
3917 | ||
3918 | /* If there is a frame pointer, then we use it instead of the stack | |
3919 | pointer, so that the stack pointer does not need to be valid when | |
3920 | the epilogue starts. See EXIT_IGNORE_STACK. */ | |
3921 | if (frame_pointer_needed) | |
3922 | setup_spill_pointers (current_frame_info.n_spilled, | |
3923 | hard_frame_pointer_rtx, 0); | |
3924 | else | |
9c808aad | 3925 | setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx, |
97e242b0 RH |
3926 | current_frame_info.total_size); |
3927 | ||
3928 | if (current_frame_info.total_size != 0) | |
3929 | { | |
3930 | /* ??? At this point we must generate a magic insn that appears to | |
3931 | modify the spill iterators and the frame pointer. This would | |
3932 | allow the most scheduling freedom. For now, just hard stop. */ | |
3933 | emit_insn (gen_blockage ()); | |
3934 | } | |
3935 | ||
3936 | /* Locate the bottom of the register save area. */ | |
3937 | cfa_off = (current_frame_info.spill_cfa_off | |
3938 | + current_frame_info.spill_size | |
3939 | + current_frame_info.extra_spill_size); | |
3940 | ||
3941 | /* Restore the predicate registers. */ | |
3942 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3943 | { | |
6fb5fa3c DB |
3944 | if (current_frame_info.r[reg_save_pr] != 0) |
3945 | { | |
3946 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); | |
3947 | reg_emitted (reg_save_pr); | |
3948 | } | |
97e242b0 RH |
3949 | else |
3950 | { | |
3951 | alt_regno = next_scratch_gr_reg (); | |
3952 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3953 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3954 | cfa_off -= 8; |
3955 | } | |
3956 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
3957 | emit_move_insn (reg, alt_reg); | |
3958 | } | |
3959 | ||
3960 | /* Restore the application registers. */ | |
3961 | ||
3962 | /* Load the saved unat from the stack, but do not restore it until | |
3963 | after the GRs have been restored. */ | |
3964 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
3965 | { | |
6fb5fa3c DB |
3966 | if (current_frame_info.r[reg_save_ar_unat] != 0) |
3967 | { | |
3968 | ar_unat_save_reg | |
3969 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3970 | reg_emitted (reg_save_ar_unat); | |
3971 | } | |
97e242b0 RH |
3972 | else |
3973 | { | |
3974 | alt_regno = next_scratch_gr_reg (); | |
3975 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3976 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
870f9ec0 | 3977 | do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off); |
97e242b0 RH |
3978 | cfa_off -= 8; |
3979 | } | |
3980 | } | |
3981 | else | |
3982 | ar_unat_save_reg = NULL_RTX; | |
9c808aad | 3983 | |
6fb5fa3c | 3984 | if (current_frame_info.r[reg_save_ar_pfs] != 0) |
97e242b0 | 3985 | { |
6fb5fa3c DB |
3986 | reg_emitted (reg_save_ar_pfs); |
3987 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]); | |
97e242b0 RH |
3988 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
3989 | emit_move_insn (reg, alt_reg); | |
3990 | } | |
4e14f1f9 | 3991 | else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
c65ebc55 | 3992 | { |
97e242b0 RH |
3993 | alt_regno = next_scratch_gr_reg (); |
3994 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3995 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3996 | cfa_off -= 8; |
3997 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); | |
3998 | emit_move_insn (reg, alt_reg); | |
3999 | } | |
4000 | ||
4001 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
4002 | { | |
6fb5fa3c DB |
4003 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
4004 | { | |
4005 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); | |
4006 | reg_emitted (reg_save_ar_lc); | |
4007 | } | |
97e242b0 RH |
4008 | else |
4009 | { | |
4010 | alt_regno = next_scratch_gr_reg (); | |
4011 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4012 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4013 | cfa_off -= 8; |
4014 | } | |
4015 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
4016 | emit_move_insn (reg, alt_reg); | |
4017 | } | |
4018 | ||
ae1e2d4c AS |
4019 | /* Restore the return pointer. */ |
4020 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4021 | { | |
6fb5fa3c DB |
4022 | if (current_frame_info.r[reg_save_b0] != 0) |
4023 | { | |
4024 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4025 | reg_emitted (reg_save_b0); | |
4026 | } | |
ae1e2d4c AS |
4027 | else |
4028 | { | |
4029 | alt_regno = next_scratch_gr_reg (); | |
4030 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
4031 | do_restore (gen_movdi_x, alt_reg, cfa_off); | |
4032 | cfa_off -= 8; | |
4033 | } | |
4034 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
4035 | emit_move_insn (reg, alt_reg); | |
4036 | } | |
4037 | ||
97e242b0 | 4038 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
4039 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
4040 | + current_frame_info.spill_size)); | |
97e242b0 | 4041 | |
599aedd9 RH |
4042 | /* The GP may be stored on the stack in the prologue, but it's |
4043 | never restored in the epilogue. Skip the stack slot. */ | |
4044 | if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1))) | |
4045 | cfa_off -= 8; | |
4046 | ||
97e242b0 | 4047 | /* Restore all general registers. */ |
599aedd9 | 4048 | for (regno = GR_REG (2); regno <= GR_REG (31); ++regno) |
97e242b0 | 4049 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) |
0c96007e | 4050 | { |
97e242b0 RH |
4051 | reg = gen_rtx_REG (DImode, regno); |
4052 | do_restore (gen_gr_restore, reg, cfa_off); | |
4053 | cfa_off -= 8; | |
0c96007e | 4054 | } |
9c808aad | 4055 | |
ae1e2d4c | 4056 | /* Restore the branch registers. */ |
97e242b0 RH |
4057 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) |
4058 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
0c96007e | 4059 | { |
97e242b0 RH |
4060 | alt_regno = next_scratch_gr_reg (); |
4061 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4062 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4063 | cfa_off -= 8; |
4064 | reg = gen_rtx_REG (DImode, regno); | |
4065 | emit_move_insn (reg, alt_reg); | |
4066 | } | |
c65ebc55 | 4067 | |
97e242b0 RH |
4068 | /* Restore floating point registers. */ |
4069 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
4070 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4071 | { | |
e820471b | 4072 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 4073 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 4074 | do_restore (gen_fr_restore_x, reg, cfa_off); |
97e242b0 | 4075 | cfa_off -= 16; |
0c96007e | 4076 | } |
97e242b0 RH |
4077 | |
4078 | /* Restore ar.unat for real. */ | |
4079 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
4080 | { | |
4081 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); | |
4082 | emit_move_insn (reg, ar_unat_save_reg); | |
c65ebc55 JW |
4083 | } |
4084 | ||
e820471b | 4085 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
4086 | |
4087 | finish_spill_pointers (); | |
c65ebc55 | 4088 | |
c93646bd JJ |
4089 | if (current_frame_info.total_size |
4090 | || cfun->machine->ia64_eh_epilogue_sp | |
4091 | || frame_pointer_needed) | |
97e242b0 RH |
4092 | { |
4093 | /* ??? At this point we must generate a magic insn that appears to | |
4094 | modify the spill iterators, the stack pointer, and the frame | |
4095 | pointer. This would allow the most scheduling freedom. For now, | |
4096 | just hard stop. */ | |
4097 | emit_insn (gen_blockage ()); | |
4098 | } | |
c65ebc55 | 4099 | |
97e242b0 RH |
4100 | if (cfun->machine->ia64_eh_epilogue_sp) |
4101 | emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp); | |
4102 | else if (frame_pointer_needed) | |
4103 | { | |
4104 | insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
4105 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 4106 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL); |
97e242b0 RH |
4107 | } |
4108 | else if (current_frame_info.total_size) | |
0c96007e | 4109 | { |
97e242b0 RH |
4110 | rtx offset, frame_size_rtx; |
4111 | ||
4112 | frame_size_rtx = GEN_INT (current_frame_info.total_size); | |
13f70342 | 4113 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
4114 | offset = frame_size_rtx; |
4115 | else | |
4116 | { | |
4117 | regno = next_scratch_gr_reg (); | |
4118 | offset = gen_rtx_REG (DImode, regno); | |
4119 | emit_move_insn (offset, frame_size_rtx); | |
4120 | } | |
4121 | ||
4122 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
4123 | offset)); | |
4124 | ||
4125 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
4126 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
4127 | gen_rtx_SET (VOIDmode, | |
4128 | stack_pointer_rtx, | |
4129 | gen_rtx_PLUS (DImode, | |
4130 | stack_pointer_rtx, | |
4131 | frame_size_rtx))); | |
0c96007e | 4132 | } |
97e242b0 RH |
4133 | |
4134 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
4135 | emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp)); | |
9c808aad | 4136 | |
2ed4af6f RH |
4137 | if (! sibcall_p) |
4138 | emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0)))); | |
25250265 | 4139 | else |
8206fc89 AM |
4140 | { |
4141 | int fp = GR_REG (2); | |
5c255b57 RH |
4142 | /* We need a throw away register here, r0 and r1 are reserved, |
4143 | so r2 is the first available call clobbered register. If | |
4144 | there was a frame_pointer register, we may have swapped the | |
4145 | names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make | |
4146 | sure we're using the string "r2" when emitting the register | |
4147 | name for the assembler. */ | |
6fb5fa3c DB |
4148 | if (current_frame_info.r[reg_fp] |
4149 | && current_frame_info.r[reg_fp] == GR_REG (2)) | |
8206fc89 AM |
4150 | fp = HARD_FRAME_POINTER_REGNUM; |
4151 | ||
4152 | /* We must emit an alloc to force the input registers to become output | |
4153 | registers. Otherwise, if the callee tries to pass its parameters | |
4154 | through to another call without an intervening alloc, then these | |
4155 | values get lost. */ | |
4156 | /* ??? We don't need to preserve all input registers. We only need to | |
4157 | preserve those input registers used as arguments to the sibling call. | |
4158 | It is unclear how to compute that number here. */ | |
4159 | if (current_frame_info.n_input_regs != 0) | |
a8f5224e DM |
4160 | { |
4161 | rtx n_inputs = GEN_INT (current_frame_info.n_input_regs); | |
c2b40eba | 4162 | |
a8f5224e DM |
4163 | insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp), |
4164 | const0_rtx, const0_rtx, | |
4165 | n_inputs, const0_rtx)); | |
4166 | RTX_FRAME_RELATED_P (insn) = 1; | |
c2b40eba RH |
4167 | |
4168 | /* ??? We need to mark the alloc as frame-related so that it gets | |
4169 | passed into ia64_asm_unwind_emit for ia64-specific unwinding. | |
4170 | But there's nothing dwarf2 related to be done wrt the register | |
4171 | windows. If we do nothing, dwarf2out will abort on the UNSPEC; | |
4172 | the empty parallel means dwarf2out will not see anything. */ | |
4173 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
4174 | gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0))); | |
a8f5224e | 4175 | } |
8206fc89 | 4176 | } |
c65ebc55 JW |
4177 | } |
4178 | ||
97e242b0 RH |
4179 | /* Return 1 if br.ret can do all the work required to return from a |
4180 | function. */ | |
4181 | ||
4182 | int | |
9c808aad | 4183 | ia64_direct_return (void) |
97e242b0 RH |
4184 | { |
4185 | if (reload_completed && ! frame_pointer_needed) | |
4186 | { | |
4187 | ia64_compute_frame_size (get_frame_size ()); | |
4188 | ||
4189 | return (current_frame_info.total_size == 0 | |
4190 | && current_frame_info.n_spilled == 0 | |
6fb5fa3c DB |
4191 | && current_frame_info.r[reg_save_b0] == 0 |
4192 | && current_frame_info.r[reg_save_pr] == 0 | |
4193 | && current_frame_info.r[reg_save_ar_pfs] == 0 | |
4194 | && current_frame_info.r[reg_save_ar_unat] == 0 | |
4195 | && current_frame_info.r[reg_save_ar_lc] == 0); | |
97e242b0 RH |
4196 | } |
4197 | return 0; | |
4198 | } | |
4199 | ||
af1e5518 RH |
4200 | /* Return the magic cookie that we use to hold the return address |
4201 | during early compilation. */ | |
4202 | ||
4203 | rtx | |
9c808aad | 4204 | ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED) |
af1e5518 RH |
4205 | { |
4206 | if (count != 0) | |
4207 | return NULL; | |
4208 | return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR); | |
4209 | } | |
4210 | ||
4211 | /* Split this value after reload, now that we know where the return | |
4212 | address is saved. */ | |
4213 | ||
4214 | void | |
9c808aad | 4215 | ia64_split_return_addr_rtx (rtx dest) |
af1e5518 RH |
4216 | { |
4217 | rtx src; | |
4218 | ||
4219 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4220 | { | |
6fb5fa3c DB |
4221 | if (current_frame_info.r[reg_save_b0] != 0) |
4222 | { | |
4223 | src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4224 | reg_emitted (reg_save_b0); | |
4225 | } | |
af1e5518 RH |
4226 | else |
4227 | { | |
4228 | HOST_WIDE_INT off; | |
4229 | unsigned int regno; | |
13f70342 | 4230 | rtx off_r; |
af1e5518 RH |
4231 | |
4232 | /* Compute offset from CFA for BR0. */ | |
4233 | /* ??? Must be kept in sync with ia64_expand_prologue. */ | |
4234 | off = (current_frame_info.spill_cfa_off | |
4235 | + current_frame_info.spill_size); | |
4236 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
4237 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4238 | off -= 8; | |
4239 | ||
4240 | /* Convert CFA offset to a register based offset. */ | |
4241 | if (frame_pointer_needed) | |
4242 | src = hard_frame_pointer_rtx; | |
4243 | else | |
4244 | { | |
4245 | src = stack_pointer_rtx; | |
4246 | off += current_frame_info.total_size; | |
4247 | } | |
4248 | ||
4249 | /* Load address into scratch register. */ | |
13f70342 RH |
4250 | off_r = GEN_INT (off); |
4251 | if (satisfies_constraint_I (off_r)) | |
4252 | emit_insn (gen_adddi3 (dest, src, off_r)); | |
af1e5518 RH |
4253 | else |
4254 | { | |
13f70342 | 4255 | emit_move_insn (dest, off_r); |
af1e5518 RH |
4256 | emit_insn (gen_adddi3 (dest, src, dest)); |
4257 | } | |
4258 | ||
4259 | src = gen_rtx_MEM (Pmode, dest); | |
4260 | } | |
4261 | } | |
4262 | else | |
4263 | src = gen_rtx_REG (DImode, BR_REG (0)); | |
4264 | ||
4265 | emit_move_insn (dest, src); | |
4266 | } | |
4267 | ||
10c9f189 | 4268 | int |
9c808aad | 4269 | ia64_hard_regno_rename_ok (int from, int to) |
10c9f189 RH |
4270 | { |
4271 | /* Don't clobber any of the registers we reserved for the prologue. */ | |
09639a83 | 4272 | unsigned int r; |
10c9f189 | 4273 | |
6fb5fa3c DB |
4274 | for (r = reg_fp; r <= reg_save_ar_lc; r++) |
4275 | if (to == current_frame_info.r[r] | |
4276 | || from == current_frame_info.r[r] | |
4277 | || to == emitted_frame_related_regs[r] | |
4278 | || from == emitted_frame_related_regs[r]) | |
4279 | return 0; | |
2130b7fb | 4280 | |
10c9f189 RH |
4281 | /* Don't use output registers outside the register frame. */ |
4282 | if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs)) | |
4283 | return 0; | |
4284 | ||
4285 | /* Retain even/oddness on predicate register pairs. */ | |
4286 | if (PR_REGNO_P (from) && PR_REGNO_P (to)) | |
4287 | return (from & 1) == (to & 1); | |
4288 | ||
4289 | return 1; | |
4290 | } | |
4291 | ||
301d03af RS |
4292 | /* Target hook for assembling integer objects. Handle word-sized |
4293 | aligned objects and detect the cases when @fptr is needed. */ | |
4294 | ||
4295 | static bool | |
9c808aad | 4296 | ia64_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 4297 | { |
b6a41a62 | 4298 | if (size == POINTER_SIZE / BITS_PER_UNIT |
301d03af RS |
4299 | && !(TARGET_NO_PIC || TARGET_AUTO_PIC) |
4300 | && GET_CODE (x) == SYMBOL_REF | |
1cdbd630 | 4301 | && SYMBOL_REF_FUNCTION_P (x)) |
301d03af | 4302 | { |
1b79dc38 DM |
4303 | static const char * const directive[2][2] = { |
4304 | /* 64-bit pointer */ /* 32-bit pointer */ | |
4305 | { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */ | |
4306 | { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */ | |
4307 | }; | |
4308 | fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file); | |
301d03af RS |
4309 | output_addr_const (asm_out_file, x); |
4310 | fputs (")\n", asm_out_file); | |
4311 | return true; | |
4312 | } | |
4313 | return default_assemble_integer (x, size, aligned_p); | |
4314 | } | |
4315 | ||
c65ebc55 JW |
4316 | /* Emit the function prologue. */ |
4317 | ||
08c148a8 | 4318 | static void |
9c808aad | 4319 | ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
c65ebc55 | 4320 | { |
97e242b0 RH |
4321 | int mask, grsave, grsave_prev; |
4322 | ||
4323 | if (current_frame_info.need_regstk) | |
4324 | fprintf (file, "\t.regstk %d, %d, %d, %d\n", | |
4325 | current_frame_info.n_input_regs, | |
4326 | current_frame_info.n_local_regs, | |
4327 | current_frame_info.n_output_regs, | |
4328 | current_frame_info.n_rotate_regs); | |
c65ebc55 | 4329 | |
d5fabb58 | 4330 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0c96007e AM |
4331 | return; |
4332 | ||
97e242b0 | 4333 | /* Emit the .prologue directive. */ |
809d4ef1 | 4334 | |
97e242b0 RH |
4335 | mask = 0; |
4336 | grsave = grsave_prev = 0; | |
6fb5fa3c | 4337 | if (current_frame_info.r[reg_save_b0] != 0) |
0c96007e | 4338 | { |
97e242b0 | 4339 | mask |= 8; |
6fb5fa3c | 4340 | grsave = grsave_prev = current_frame_info.r[reg_save_b0]; |
97e242b0 | 4341 | } |
6fb5fa3c | 4342 | if (current_frame_info.r[reg_save_ar_pfs] != 0 |
97e242b0 | 4343 | && (grsave_prev == 0 |
6fb5fa3c | 4344 | || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1)) |
97e242b0 RH |
4345 | { |
4346 | mask |= 4; | |
4347 | if (grsave_prev == 0) | |
6fb5fa3c DB |
4348 | grsave = current_frame_info.r[reg_save_ar_pfs]; |
4349 | grsave_prev = current_frame_info.r[reg_save_ar_pfs]; | |
0c96007e | 4350 | } |
6fb5fa3c | 4351 | if (current_frame_info.r[reg_fp] != 0 |
97e242b0 | 4352 | && (grsave_prev == 0 |
6fb5fa3c | 4353 | || current_frame_info.r[reg_fp] == grsave_prev + 1)) |
97e242b0 RH |
4354 | { |
4355 | mask |= 2; | |
4356 | if (grsave_prev == 0) | |
4357 | grsave = HARD_FRAME_POINTER_REGNUM; | |
6fb5fa3c | 4358 | grsave_prev = current_frame_info.r[reg_fp]; |
97e242b0 | 4359 | } |
6fb5fa3c | 4360 | if (current_frame_info.r[reg_save_pr] != 0 |
97e242b0 | 4361 | && (grsave_prev == 0 |
6fb5fa3c | 4362 | || current_frame_info.r[reg_save_pr] == grsave_prev + 1)) |
97e242b0 RH |
4363 | { |
4364 | mask |= 1; | |
4365 | if (grsave_prev == 0) | |
6fb5fa3c | 4366 | grsave = current_frame_info.r[reg_save_pr]; |
97e242b0 RH |
4367 | } |
4368 | ||
738e7b39 | 4369 | if (mask && TARGET_GNU_AS) |
97e242b0 RH |
4370 | fprintf (file, "\t.prologue %d, %d\n", mask, |
4371 | ia64_dbx_register_number (grsave)); | |
4372 | else | |
4373 | fputs ("\t.prologue\n", file); | |
4374 | ||
4375 | /* Emit a .spill directive, if necessary, to relocate the base of | |
4376 | the register spill area. */ | |
4377 | if (current_frame_info.spill_cfa_off != -16) | |
4378 | fprintf (file, "\t.spill %ld\n", | |
4379 | (long) (current_frame_info.spill_cfa_off | |
4380 | + current_frame_info.spill_size)); | |
c65ebc55 JW |
4381 | } |
4382 | ||
0186257f JW |
4383 | /* Emit the .body directive at the scheduled end of the prologue. */ |
4384 | ||
b4c25db2 | 4385 | static void |
9c808aad | 4386 | ia64_output_function_end_prologue (FILE *file) |
0186257f | 4387 | { |
d5fabb58 | 4388 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0186257f JW |
4389 | return; |
4390 | ||
4391 | fputs ("\t.body\n", file); | |
4392 | } | |
4393 | ||
c65ebc55 JW |
4394 | /* Emit the function epilogue. */ |
4395 | ||
08c148a8 | 4396 | static void |
9c808aad AJ |
4397 | ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
4398 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
c65ebc55 | 4399 | { |
8a959ea5 RH |
4400 | int i; |
4401 | ||
6fb5fa3c | 4402 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4403 | { |
4404 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
4405 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
4406 | = reg_names[current_frame_info.r[reg_fp]]; |
4407 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
4408 | reg_emitted (reg_fp); | |
97e242b0 RH |
4409 | } |
4410 | if (! TARGET_REG_NAMES) | |
4411 | { | |
97e242b0 RH |
4412 | for (i = 0; i < current_frame_info.n_input_regs; i++) |
4413 | reg_names[IN_REG (i)] = ia64_input_reg_names[i]; | |
4414 | for (i = 0; i < current_frame_info.n_local_regs; i++) | |
4415 | reg_names[LOC_REG (i)] = ia64_local_reg_names[i]; | |
4416 | for (i = 0; i < current_frame_info.n_output_regs; i++) | |
4417 | reg_names[OUT_REG (i)] = ia64_output_reg_names[i]; | |
4418 | } | |
8a959ea5 | 4419 | |
97e242b0 RH |
4420 | current_frame_info.initialized = 0; |
4421 | } | |
c65ebc55 JW |
4422 | |
4423 | int | |
9c808aad | 4424 | ia64_dbx_register_number (int regno) |
c65ebc55 | 4425 | { |
97e242b0 RH |
4426 | /* In ia64_expand_prologue we quite literally renamed the frame pointer |
4427 | from its home at loc79 to something inside the register frame. We | |
4428 | must perform the same renumbering here for the debug info. */ | |
6fb5fa3c | 4429 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4430 | { |
4431 | if (regno == HARD_FRAME_POINTER_REGNUM) | |
6fb5fa3c DB |
4432 | regno = current_frame_info.r[reg_fp]; |
4433 | else if (regno == current_frame_info.r[reg_fp]) | |
97e242b0 RH |
4434 | regno = HARD_FRAME_POINTER_REGNUM; |
4435 | } | |
4436 | ||
4437 | if (IN_REGNO_P (regno)) | |
4438 | return 32 + regno - IN_REG (0); | |
4439 | else if (LOC_REGNO_P (regno)) | |
4440 | return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0); | |
4441 | else if (OUT_REGNO_P (regno)) | |
4442 | return (32 + current_frame_info.n_input_regs | |
4443 | + current_frame_info.n_local_regs + regno - OUT_REG (0)); | |
4444 | else | |
4445 | return regno; | |
c65ebc55 JW |
4446 | } |
4447 | ||
2a1211e5 RH |
4448 | /* Implement TARGET_TRAMPOLINE_INIT. |
4449 | ||
4450 | The trampoline should set the static chain pointer to value placed | |
4451 | into the trampoline and should branch to the specified routine. | |
4452 | To make the normal indirect-subroutine calling convention work, | |
4453 | the trampoline must look like a function descriptor; the first | |
4454 | word being the target address and the second being the target's | |
4455 | global pointer. | |
4456 | ||
4457 | We abuse the concept of a global pointer by arranging for it | |
4458 | to point to the data we need to load. The complete trampoline | |
4459 | has the following form: | |
4460 | ||
4461 | +-------------------+ \ | |
4462 | TRAMP: | __ia64_trampoline | | | |
4463 | +-------------------+ > fake function descriptor | |
4464 | | TRAMP+16 | | | |
4465 | +-------------------+ / | |
4466 | | target descriptor | | |
4467 | +-------------------+ | |
4468 | | static link | | |
4469 | +-------------------+ | |
4470 | */ | |
4471 | ||
4472 | static void | |
4473 | ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
97e242b0 | 4474 | { |
2a1211e5 RH |
4475 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
4476 | rtx addr, addr_reg, tramp, eight = GEN_INT (8); | |
97e242b0 | 4477 | |
738e7b39 RK |
4478 | /* The Intel assembler requires that the global __ia64_trampoline symbol |
4479 | be declared explicitly */ | |
4480 | if (!TARGET_GNU_AS) | |
4481 | { | |
4482 | static bool declared_ia64_trampoline = false; | |
4483 | ||
4484 | if (!declared_ia64_trampoline) | |
4485 | { | |
4486 | declared_ia64_trampoline = true; | |
b6a41a62 RK |
4487 | (*targetm.asm_out.globalize_label) (asm_out_file, |
4488 | "__ia64_trampoline"); | |
738e7b39 RK |
4489 | } |
4490 | } | |
4491 | ||
5e89a381 | 4492 | /* Make sure addresses are Pmode even if we are in ILP32 mode. */ |
2a1211e5 | 4493 | addr = convert_memory_address (Pmode, XEXP (m_tramp, 0)); |
5e89a381 SE |
4494 | fnaddr = convert_memory_address (Pmode, fnaddr); |
4495 | static_chain = convert_memory_address (Pmode, static_chain); | |
4496 | ||
97e242b0 | 4497 | /* Load up our iterator. */ |
2a1211e5 RH |
4498 | addr_reg = copy_to_reg (addr); |
4499 | m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0); | |
97e242b0 RH |
4500 | |
4501 | /* The first two words are the fake descriptor: | |
4502 | __ia64_trampoline, ADDR+16. */ | |
f2972bf8 DR |
4503 | tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"); |
4504 | if (TARGET_ABI_OPEN_VMS) | |
4505 | { | |
4506 | /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity | |
4507 | in the Macro-32 compiler) and changed the semantics of the LTOFF22 | |
4508 | relocation against function symbols to make it identical to the | |
4509 | LTOFF_FPTR22 relocation. Emit the latter directly to stay within | |
4510 | strict ELF and dereference to get the bare code address. */ | |
4511 | rtx reg = gen_reg_rtx (Pmode); | |
4512 | SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION; | |
4513 | emit_move_insn (reg, tramp); | |
4514 | emit_move_insn (reg, gen_rtx_MEM (Pmode, reg)); | |
4515 | tramp = reg; | |
4516 | } | |
2a1211e5 | 4517 | emit_move_insn (m_tramp, tramp); |
97e242b0 | 4518 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4519 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 | 4520 | |
0a81f074 | 4521 | emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16))); |
97e242b0 | 4522 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4523 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4524 | |
4525 | /* The third word is the target descriptor. */ | |
2a1211e5 | 4526 | emit_move_insn (m_tramp, force_reg (Pmode, fnaddr)); |
97e242b0 | 4527 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4528 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4529 | |
4530 | /* The fourth word is the static chain. */ | |
2a1211e5 | 4531 | emit_move_insn (m_tramp, static_chain); |
97e242b0 | 4532 | } |
c65ebc55 JW |
4533 | \f |
4534 | /* Do any needed setup for a variadic function. CUM has not been updated | |
97e242b0 RH |
4535 | for the last named argument which has type TYPE and mode MODE. |
4536 | ||
4537 | We generate the actual spill instructions during prologue generation. */ | |
4538 | ||
351a758b | 4539 | static void |
ef4bddc2 | 4540 | ia64_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode, |
351a758b | 4541 | tree type, int * pretend_size, |
9c808aad | 4542 | int second_time ATTRIBUTE_UNUSED) |
c65ebc55 | 4543 | { |
d5cc9181 | 4544 | CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum); |
351a758b | 4545 | |
6c535c69 | 4546 | /* Skip the current argument. */ |
d5cc9181 | 4547 | ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1); |
c65ebc55 | 4548 | |
351a758b | 4549 | if (next_cum.words < MAX_ARGUMENT_SLOTS) |
26a110f5 | 4550 | { |
351a758b | 4551 | int n = MAX_ARGUMENT_SLOTS - next_cum.words; |
26a110f5 RH |
4552 | *pretend_size = n * UNITS_PER_WORD; |
4553 | cfun->machine->n_varargs = n; | |
4554 | } | |
c65ebc55 JW |
4555 | } |
4556 | ||
4557 | /* Check whether TYPE is a homogeneous floating point aggregate. If | |
4558 | it is, return the mode of the floating point type that appears | |
4559 | in all leafs. If it is not, return VOIDmode. | |
4560 | ||
4561 | An aggregate is a homogeneous floating point aggregate is if all | |
4562 | fields/elements in it have the same floating point type (e.g, | |
3d6a9acd RH |
4563 | SFmode). 128-bit quad-precision floats are excluded. |
4564 | ||
4565 | Variable sized aggregates should never arrive here, since we should | |
4566 | have already decided to pass them by reference. Top-level zero-sized | |
4567 | aggregates are excluded because our parallels crash the middle-end. */ | |
c65ebc55 | 4568 | |
ef4bddc2 | 4569 | static machine_mode |
586de218 | 4570 | hfa_element_mode (const_tree type, bool nested) |
c65ebc55 | 4571 | { |
ef4bddc2 RS |
4572 | machine_mode element_mode = VOIDmode; |
4573 | machine_mode mode; | |
c65ebc55 JW |
4574 | enum tree_code code = TREE_CODE (type); |
4575 | int know_element_mode = 0; | |
4576 | tree t; | |
4577 | ||
3d6a9acd RH |
4578 | if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type)))) |
4579 | return VOIDmode; | |
4580 | ||
c65ebc55 JW |
4581 | switch (code) |
4582 | { | |
4583 | case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE: | |
0cc8f5c5 | 4584 | case BOOLEAN_TYPE: case POINTER_TYPE: |
c65ebc55 | 4585 | case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE: |
5662a50d | 4586 | case LANG_TYPE: case FUNCTION_TYPE: |
c65ebc55 JW |
4587 | return VOIDmode; |
4588 | ||
4589 | /* Fortran complex types are supposed to be HFAs, so we need to handle | |
4590 | gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex | |
4591 | types though. */ | |
4592 | case COMPLEX_TYPE: | |
16448fd4 | 4593 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT |
02befdf4 ZW |
4594 | && TYPE_MODE (type) != TCmode) |
4595 | return GET_MODE_INNER (TYPE_MODE (type)); | |
c65ebc55 JW |
4596 | else |
4597 | return VOIDmode; | |
4598 | ||
4599 | case REAL_TYPE: | |
4600 | /* We want to return VOIDmode for raw REAL_TYPEs, but the actual | |
4601 | mode if this is contained within an aggregate. */ | |
02befdf4 | 4602 | if (nested && TYPE_MODE (type) != TFmode) |
c65ebc55 JW |
4603 | return TYPE_MODE (type); |
4604 | else | |
4605 | return VOIDmode; | |
4606 | ||
4607 | case ARRAY_TYPE: | |
46399021 | 4608 | return hfa_element_mode (TREE_TYPE (type), 1); |
c65ebc55 JW |
4609 | |
4610 | case RECORD_TYPE: | |
4611 | case UNION_TYPE: | |
4612 | case QUAL_UNION_TYPE: | |
910ad8de | 4613 | for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t)) |
c65ebc55 JW |
4614 | { |
4615 | if (TREE_CODE (t) != FIELD_DECL) | |
4616 | continue; | |
4617 | ||
4618 | mode = hfa_element_mode (TREE_TYPE (t), 1); | |
4619 | if (know_element_mode) | |
4620 | { | |
4621 | if (mode != element_mode) | |
4622 | return VOIDmode; | |
4623 | } | |
4624 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT) | |
4625 | return VOIDmode; | |
4626 | else | |
4627 | { | |
4628 | know_element_mode = 1; | |
4629 | element_mode = mode; | |
4630 | } | |
4631 | } | |
4632 | return element_mode; | |
4633 | ||
4634 | default: | |
4635 | /* If we reach here, we probably have some front-end specific type | |
4636 | that the backend doesn't know about. This can happen via the | |
4637 | aggregate_value_p call in init_function_start. All we can do is | |
4638 | ignore unknown tree types. */ | |
4639 | return VOIDmode; | |
4640 | } | |
4641 | ||
4642 | return VOIDmode; | |
4643 | } | |
4644 | ||
f57fc998 ZW |
4645 | /* Return the number of words required to hold a quantity of TYPE and MODE |
4646 | when passed as an argument. */ | |
4647 | static int | |
ef4bddc2 | 4648 | ia64_function_arg_words (const_tree type, machine_mode mode) |
f57fc998 ZW |
4649 | { |
4650 | int words; | |
4651 | ||
4652 | if (mode == BLKmode) | |
4653 | words = int_size_in_bytes (type); | |
4654 | else | |
4655 | words = GET_MODE_SIZE (mode); | |
4656 | ||
4657 | return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */ | |
4658 | } | |
4659 | ||
4660 | /* Return the number of registers that should be skipped so the current | |
4661 | argument (described by TYPE and WORDS) will be properly aligned. | |
4662 | ||
4663 | Integer and float arguments larger than 8 bytes start at the next | |
4664 | even boundary. Aggregates larger than 8 bytes start at the next | |
4665 | even boundary if the aggregate has 16 byte alignment. Note that | |
4666 | in the 32-bit ABI, TImode and TFmode have only 8-byte alignment | |
4667 | but are still to be aligned in registers. | |
4668 | ||
4669 | ??? The ABI does not specify how to handle aggregates with | |
4670 | alignment from 9 to 15 bytes, or greater than 16. We handle them | |
4671 | all as if they had 16 byte alignment. Such aggregates can occur | |
4672 | only if gcc extensions are used. */ | |
4673 | static int | |
ffa88471 SE |
4674 | ia64_function_arg_offset (const CUMULATIVE_ARGS *cum, |
4675 | const_tree type, int words) | |
f57fc998 | 4676 | { |
f2972bf8 DR |
4677 | /* No registers are skipped on VMS. */ |
4678 | if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0) | |
f57fc998 ZW |
4679 | return 0; |
4680 | ||
4681 | if (type | |
4682 | && TREE_CODE (type) != INTEGER_TYPE | |
4683 | && TREE_CODE (type) != REAL_TYPE) | |
4684 | return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT; | |
4685 | else | |
4686 | return words > 1; | |
4687 | } | |
4688 | ||
c65ebc55 JW |
4689 | /* Return rtx for register where argument is passed, or zero if it is passed |
4690 | on the stack. */ | |
c65ebc55 JW |
4691 | /* ??? 128-bit quad-precision floats are always passed in general |
4692 | registers. */ | |
4693 | ||
ffa88471 | 4694 | static rtx |
ef4bddc2 | 4695 | ia64_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, |
ffa88471 | 4696 | const_tree type, bool named, bool incoming) |
c65ebc55 | 4697 | { |
d5cc9181 JR |
4698 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4699 | ||
c65ebc55 | 4700 | int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST); |
f57fc998 ZW |
4701 | int words = ia64_function_arg_words (type, mode); |
4702 | int offset = ia64_function_arg_offset (cum, type, words); | |
ef4bddc2 | 4703 | machine_mode hfa_mode = VOIDmode; |
c65ebc55 | 4704 | |
f2972bf8 DR |
4705 | /* For OPEN VMS, emit the instruction setting up the argument register here, |
4706 | when we know this will be together with the other arguments setup related | |
4707 | insns. This is not the conceptually best place to do this, but this is | |
4708 | the easiest as we have convenient access to cumulative args info. */ | |
4709 | ||
4710 | if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node | |
4711 | && named == 1) | |
4712 | { | |
4713 | unsigned HOST_WIDE_INT regval = cum->words; | |
4714 | int i; | |
4715 | ||
4716 | for (i = 0; i < 8; i++) | |
4717 | regval |= ((int) cum->atypes[i]) << (i * 3 + 8); | |
4718 | ||
4719 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)), | |
4720 | GEN_INT (regval)); | |
4721 | } | |
4722 | ||
c65ebc55 JW |
4723 | /* If all argument slots are used, then it must go on the stack. */ |
4724 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4725 | return 0; | |
4726 | ||
472b8fdc TG |
4727 | /* On OpenVMS argument is either in Rn or Fn. */ |
4728 | if (TARGET_ABI_OPEN_VMS) | |
4729 | { | |
4730 | if (FLOAT_MODE_P (mode)) | |
4731 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words); | |
4732 | else | |
4733 | return gen_rtx_REG (mode, basereg + cum->words); | |
4734 | } | |
4735 | ||
c65ebc55 JW |
4736 | /* Check for and handle homogeneous FP aggregates. */ |
4737 | if (type) | |
4738 | hfa_mode = hfa_element_mode (type, 0); | |
4739 | ||
4740 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4741 | and unprototyped hfas are passed specially. */ | |
4742 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4743 | { | |
4744 | rtx loc[16]; | |
4745 | int i = 0; | |
4746 | int fp_regs = cum->fp_regs; | |
4747 | int int_regs = cum->words + offset; | |
4748 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4749 | int byte_size; | |
4750 | int args_byte_size; | |
4751 | ||
4752 | /* If prototyped, pass it in FR regs then GR regs. | |
4753 | If not prototyped, pass it in both FR and GR regs. | |
4754 | ||
4755 | If this is an SFmode aggregate, then it is possible to run out of | |
4756 | FR regs while GR regs are still left. In that case, we pass the | |
4757 | remaining part in the GR regs. */ | |
4758 | ||
4759 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4760 | of the argument, the last FP register, or the last argument slot. */ | |
4761 | ||
4762 | byte_size = ((mode == BLKmode) | |
4763 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4764 | args_byte_size = int_regs * UNITS_PER_WORD; | |
4765 | offset = 0; | |
4766 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4767 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++) | |
4768 | { | |
4769 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4770 | gen_rtx_REG (hfa_mode, (FR_ARG_FIRST | |
4771 | + fp_regs)), | |
4772 | GEN_INT (offset)); | |
c65ebc55 JW |
4773 | offset += hfa_size; |
4774 | args_byte_size += hfa_size; | |
4775 | fp_regs++; | |
4776 | } | |
4777 | ||
4778 | /* If no prototype, then the whole thing must go in GR regs. */ | |
4779 | if (! cum->prototype) | |
4780 | offset = 0; | |
4781 | /* If this is an SFmode aggregate, then we might have some left over | |
4782 | that needs to go in GR regs. */ | |
4783 | else if (byte_size != offset) | |
4784 | int_regs += offset / UNITS_PER_WORD; | |
4785 | ||
4786 | /* Fill in the GR regs. We must use DImode here, not the hfa mode. */ | |
4787 | ||
4788 | for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++) | |
4789 | { | |
ef4bddc2 | 4790 | machine_mode gr_mode = DImode; |
826b47cc | 4791 | unsigned int gr_size; |
c65ebc55 JW |
4792 | |
4793 | /* If we have an odd 4 byte hunk because we ran out of FR regs, | |
4794 | then this goes in a GR reg left adjusted/little endian, right | |
4795 | adjusted/big endian. */ | |
4796 | /* ??? Currently this is handled wrong, because 4-byte hunks are | |
4797 | always right adjusted/little endian. */ | |
4798 | if (offset & 0x4) | |
4799 | gr_mode = SImode; | |
4800 | /* If we have an even 4 byte hunk because the aggregate is a | |
4801 | multiple of 4 bytes in size, then this goes in a GR reg right | |
4802 | adjusted/little endian. */ | |
4803 | else if (byte_size - offset == 4) | |
4804 | gr_mode = SImode; | |
4805 | ||
4806 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4807 | gen_rtx_REG (gr_mode, (basereg | |
4808 | + int_regs)), | |
4809 | GEN_INT (offset)); | |
826b47cc ZW |
4810 | |
4811 | gr_size = GET_MODE_SIZE (gr_mode); | |
4812 | offset += gr_size; | |
4813 | if (gr_size == UNITS_PER_WORD | |
4814 | || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0)) | |
4815 | int_regs++; | |
4816 | else if (gr_size > UNITS_PER_WORD) | |
4817 | int_regs += gr_size / UNITS_PER_WORD; | |
c65ebc55 | 4818 | } |
9dec91d4 | 4819 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 4820 | } |
f2972bf8 | 4821 | |
c65ebc55 JW |
4822 | /* Integral and aggregates go in general registers. If we have run out of |
4823 | FR registers, then FP values must also go in general registers. This can | |
4824 | happen when we have a SFmode HFA. */ | |
02befdf4 ZW |
4825 | else if (mode == TFmode || mode == TCmode |
4826 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
3870df96 SE |
4827 | { |
4828 | int byte_size = ((mode == BLKmode) | |
4829 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4830 | if (BYTES_BIG_ENDIAN | |
4831 | && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type))) | |
4832 | && byte_size < UNITS_PER_WORD | |
4833 | && byte_size > 0) | |
4834 | { | |
4835 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
4836 | gen_rtx_REG (DImode, | |
4837 | (basereg + cum->words | |
4838 | + offset)), | |
4839 | const0_rtx); | |
4840 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg)); | |
4841 | } | |
4842 | else | |
4843 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
4844 | ||
4845 | } | |
c65ebc55 JW |
4846 | |
4847 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4848 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4849 | else if (cum->prototype) |
4850 | { | |
f9c887ac | 4851 | if (named) |
c65ebc55 | 4852 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs); |
f9c887ac ZW |
4853 | /* In big-endian mode, an anonymous SFmode value must be represented |
4854 | as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force | |
4855 | the value into the high half of the general register. */ | |
4856 | else if (BYTES_BIG_ENDIAN && mode == SFmode) | |
4857 | return gen_rtx_PARALLEL (mode, | |
4858 | gen_rtvec (1, | |
4859 | gen_rtx_EXPR_LIST (VOIDmode, | |
4860 | gen_rtx_REG (DImode, basereg + cum->words + offset), | |
4861 | const0_rtx))); | |
4862 | else | |
4863 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
c65ebc55 JW |
4864 | } |
4865 | /* If there is no prototype, then FP values go in both FR and GR | |
4866 | registers. */ | |
4867 | else | |
4868 | { | |
f9c887ac | 4869 | /* See comment above. */ |
ef4bddc2 | 4870 | machine_mode inner_mode = |
f9c887ac ZW |
4871 | (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode; |
4872 | ||
c65ebc55 JW |
4873 | rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode, |
4874 | gen_rtx_REG (mode, (FR_ARG_FIRST | |
4875 | + cum->fp_regs)), | |
4876 | const0_rtx); | |
4877 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
f9c887ac | 4878 | gen_rtx_REG (inner_mode, |
c65ebc55 JW |
4879 | (basereg + cum->words |
4880 | + offset)), | |
4881 | const0_rtx); | |
809d4ef1 | 4882 | |
c65ebc55 JW |
4883 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg)); |
4884 | } | |
4885 | } | |
4886 | ||
ffa88471 SE |
4887 | /* Implement TARGET_FUNCION_ARG target hook. */ |
4888 | ||
4889 | static rtx | |
ef4bddc2 | 4890 | ia64_function_arg (cumulative_args_t cum, machine_mode mode, |
ffa88471 SE |
4891 | const_tree type, bool named) |
4892 | { | |
4893 | return ia64_function_arg_1 (cum, mode, type, named, false); | |
4894 | } | |
4895 | ||
4896 | /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */ | |
4897 | ||
4898 | static rtx | |
d5cc9181 | 4899 | ia64_function_incoming_arg (cumulative_args_t cum, |
ef4bddc2 | 4900 | machine_mode mode, |
ffa88471 SE |
4901 | const_tree type, bool named) |
4902 | { | |
4903 | return ia64_function_arg_1 (cum, mode, type, named, true); | |
4904 | } | |
4905 | ||
78a52f11 | 4906 | /* Return number of bytes, at the beginning of the argument, that must be |
c65ebc55 JW |
4907 | put in registers. 0 is the argument is entirely in registers or entirely |
4908 | in memory. */ | |
4909 | ||
78a52f11 | 4910 | static int |
ef4bddc2 | 4911 | ia64_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, |
78a52f11 | 4912 | tree type, bool named ATTRIBUTE_UNUSED) |
c65ebc55 | 4913 | { |
d5cc9181 JR |
4914 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4915 | ||
f57fc998 ZW |
4916 | int words = ia64_function_arg_words (type, mode); |
4917 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4918 | |
4919 | /* If all argument slots are used, then it must go on the stack. */ | |
4920 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4921 | return 0; | |
4922 | ||
4923 | /* It doesn't matter whether the argument goes in FR or GR regs. If | |
4924 | it fits within the 8 argument slots, then it goes entirely in | |
4925 | registers. If it extends past the last argument slot, then the rest | |
4926 | goes on the stack. */ | |
4927 | ||
4928 | if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS) | |
4929 | return 0; | |
4930 | ||
78a52f11 | 4931 | return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD; |
c65ebc55 JW |
4932 | } |
4933 | ||
f2972bf8 DR |
4934 | /* Return ivms_arg_type based on machine_mode. */ |
4935 | ||
4936 | static enum ivms_arg_type | |
ef4bddc2 | 4937 | ia64_arg_type (machine_mode mode) |
f2972bf8 DR |
4938 | { |
4939 | switch (mode) | |
4940 | { | |
4941 | case SFmode: | |
4942 | return FS; | |
4943 | case DFmode: | |
4944 | return FT; | |
4945 | default: | |
4946 | return I64; | |
4947 | } | |
4948 | } | |
4949 | ||
c65ebc55 JW |
4950 | /* Update CUM to point after this argument. This is patterned after |
4951 | ia64_function_arg. */ | |
4952 | ||
ffa88471 | 4953 | static void |
ef4bddc2 | 4954 | ia64_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
ffa88471 | 4955 | const_tree type, bool named) |
c65ebc55 | 4956 | { |
d5cc9181 | 4957 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
f57fc998 ZW |
4958 | int words = ia64_function_arg_words (type, mode); |
4959 | int offset = ia64_function_arg_offset (cum, type, words); | |
ef4bddc2 | 4960 | machine_mode hfa_mode = VOIDmode; |
c65ebc55 JW |
4961 | |
4962 | /* If all arg slots are already full, then there is nothing to do. */ | |
4963 | if (cum->words >= MAX_ARGUMENT_SLOTS) | |
f2972bf8 DR |
4964 | { |
4965 | cum->words += words + offset; | |
4966 | return; | |
4967 | } | |
c65ebc55 | 4968 | |
f2972bf8 | 4969 | cum->atypes[cum->words] = ia64_arg_type (mode); |
c65ebc55 JW |
4970 | cum->words += words + offset; |
4971 | ||
472b8fdc TG |
4972 | /* On OpenVMS argument is either in Rn or Fn. */ |
4973 | if (TARGET_ABI_OPEN_VMS) | |
4974 | { | |
4975 | cum->int_regs = cum->words; | |
4976 | cum->fp_regs = cum->words; | |
4977 | return; | |
4978 | } | |
4979 | ||
c65ebc55 JW |
4980 | /* Check for and handle homogeneous FP aggregates. */ |
4981 | if (type) | |
4982 | hfa_mode = hfa_element_mode (type, 0); | |
4983 | ||
4984 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4985 | and unprototyped hfas are passed specially. */ | |
4986 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4987 | { | |
4988 | int fp_regs = cum->fp_regs; | |
4989 | /* This is the original value of cum->words + offset. */ | |
4990 | int int_regs = cum->words - words; | |
4991 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4992 | int byte_size; | |
4993 | int args_byte_size; | |
4994 | ||
4995 | /* If prototyped, pass it in FR regs then GR regs. | |
4996 | If not prototyped, pass it in both FR and GR regs. | |
4997 | ||
4998 | If this is an SFmode aggregate, then it is possible to run out of | |
4999 | FR regs while GR regs are still left. In that case, we pass the | |
5000 | remaining part in the GR regs. */ | |
5001 | ||
5002 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
5003 | of the argument, the last FP register, or the last argument slot. */ | |
5004 | ||
5005 | byte_size = ((mode == BLKmode) | |
5006 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
5007 | args_byte_size = int_regs * UNITS_PER_WORD; | |
5008 | offset = 0; | |
5009 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
5010 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));) | |
5011 | { | |
c65ebc55 JW |
5012 | offset += hfa_size; |
5013 | args_byte_size += hfa_size; | |
5014 | fp_regs++; | |
5015 | } | |
5016 | ||
5017 | cum->fp_regs = fp_regs; | |
5018 | } | |
5019 | ||
d13256a3 SE |
5020 | /* Integral and aggregates go in general registers. So do TFmode FP values. |
5021 | If we have run out of FR registers, then other FP values must also go in | |
5022 | general registers. This can happen when we have a SFmode HFA. */ | |
5023 | else if (mode == TFmode || mode == TCmode | |
5024 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
648fe28b | 5025 | cum->int_regs = cum->words; |
c65ebc55 JW |
5026 | |
5027 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 5028 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
5029 | else if (cum->prototype) |
5030 | { | |
5031 | if (! named) | |
648fe28b | 5032 | cum->int_regs = cum->words; |
c65ebc55 JW |
5033 | else |
5034 | /* ??? Complex types should not reach here. */ | |
5035 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
5036 | } | |
5037 | /* If there is no prototype, then FP values go in both FR and GR | |
5038 | registers. */ | |
5039 | else | |
9c808aad | 5040 | { |
648fe28b RH |
5041 | /* ??? Complex types should not reach here. */ |
5042 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
5043 | cum->int_regs = cum->words; | |
5044 | } | |
c65ebc55 | 5045 | } |
51dcde6f | 5046 | |
d13256a3 | 5047 | /* Arguments with alignment larger than 8 bytes start at the next even |
93348822 | 5048 | boundary. On ILP32 HPUX, TFmode arguments start on next even boundary |
d13256a3 SE |
5049 | even though their normal alignment is 8 bytes. See ia64_function_arg. */ |
5050 | ||
c2ed6cf8 | 5051 | static unsigned int |
ef4bddc2 | 5052 | ia64_function_arg_boundary (machine_mode mode, const_tree type) |
d13256a3 | 5053 | { |
d13256a3 SE |
5054 | if (mode == TFmode && TARGET_HPUX && TARGET_ILP32) |
5055 | return PARM_BOUNDARY * 2; | |
5056 | ||
5057 | if (type) | |
5058 | { | |
5059 | if (TYPE_ALIGN (type) > PARM_BOUNDARY) | |
5060 | return PARM_BOUNDARY * 2; | |
5061 | else | |
5062 | return PARM_BOUNDARY; | |
5063 | } | |
5064 | ||
5065 | if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY) | |
5066 | return PARM_BOUNDARY * 2; | |
5067 | else | |
5068 | return PARM_BOUNDARY; | |
5069 | } | |
5070 | ||
599aedd9 RH |
5071 | /* True if it is OK to do sibling call optimization for the specified |
5072 | call expression EXP. DECL will be the called function, or NULL if | |
5073 | this is an indirect call. */ | |
5074 | static bool | |
9c808aad | 5075 | ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
599aedd9 | 5076 | { |
097f3d48 JW |
5077 | /* We can't perform a sibcall if the current function has the syscall_linkage |
5078 | attribute. */ | |
5079 | if (lookup_attribute ("syscall_linkage", | |
5080 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
5081 | return false; | |
5082 | ||
b23ba0b8 | 5083 | /* We must always return with our current GP. This means we can |
c208436c SE |
5084 | only sibcall to functions defined in the current module unless |
5085 | TARGET_CONST_GP is set to true. */ | |
5086 | return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP; | |
599aedd9 | 5087 | } |
c65ebc55 | 5088 | \f |
c65ebc55 JW |
5089 | |
5090 | /* Implement va_arg. */ | |
5091 | ||
23a60a04 | 5092 | static tree |
726a989a RB |
5093 | ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
5094 | gimple_seq *post_p) | |
cd3ce9b4 | 5095 | { |
cd3ce9b4 | 5096 | /* Variable sized types are passed by reference. */ |
08b0dc1b | 5097 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
cd3ce9b4 | 5098 | { |
23a60a04 JM |
5099 | tree ptrtype = build_pointer_type (type); |
5100 | tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p); | |
c2433d7d | 5101 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5102 | } |
5103 | ||
5104 | /* Aggregate arguments with alignment larger than 8 bytes start at | |
5105 | the next even boundary. Integer and floating point arguments | |
5106 | do so if they are larger than 8 bytes, whether or not they are | |
5107 | also aligned larger than 8 bytes. */ | |
5108 | if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE) | |
5109 | ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT) | |
5110 | { | |
5d49b6a7 | 5111 | tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1); |
47a25a46 | 5112 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
5d49b6a7 | 5113 | build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD)); |
726a989a | 5114 | gimplify_assign (unshare_expr (valist), t, pre_p); |
cd3ce9b4 JM |
5115 | } |
5116 | ||
23a60a04 | 5117 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 | 5118 | } |
c65ebc55 JW |
5119 | \f |
5120 | /* Return 1 if function return value returned in memory. Return 0 if it is | |
5121 | in a register. */ | |
5122 | ||
351a758b | 5123 | static bool |
586de218 | 5124 | ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED) |
c65ebc55 | 5125 | { |
ef4bddc2 RS |
5126 | machine_mode mode; |
5127 | machine_mode hfa_mode; | |
487b97e0 | 5128 | HOST_WIDE_INT byte_size; |
c65ebc55 JW |
5129 | |
5130 | mode = TYPE_MODE (valtype); | |
487b97e0 RH |
5131 | byte_size = GET_MODE_SIZE (mode); |
5132 | if (mode == BLKmode) | |
5133 | { | |
5134 | byte_size = int_size_in_bytes (valtype); | |
5135 | if (byte_size < 0) | |
351a758b | 5136 | return true; |
487b97e0 | 5137 | } |
c65ebc55 JW |
5138 | |
5139 | /* Hfa's with up to 8 elements are returned in the FP argument registers. */ | |
5140 | ||
5141 | hfa_mode = hfa_element_mode (valtype, 0); | |
5142 | if (hfa_mode != VOIDmode) | |
5143 | { | |
5144 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
5145 | ||
c65ebc55 | 5146 | if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS) |
351a758b | 5147 | return true; |
c65ebc55 | 5148 | else |
351a758b | 5149 | return false; |
c65ebc55 | 5150 | } |
c65ebc55 | 5151 | else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS) |
351a758b | 5152 | return true; |
c65ebc55 | 5153 | else |
351a758b | 5154 | return false; |
c65ebc55 JW |
5155 | } |
5156 | ||
5157 | /* Return rtx for register that holds the function return value. */ | |
5158 | ||
ba90d838 AS |
5159 | static rtx |
5160 | ia64_function_value (const_tree valtype, | |
5161 | const_tree fn_decl_or_type, | |
5162 | bool outgoing ATTRIBUTE_UNUSED) | |
c65ebc55 | 5163 | { |
ef4bddc2 RS |
5164 | machine_mode mode; |
5165 | machine_mode hfa_mode; | |
f2972bf8 | 5166 | int unsignedp; |
ba90d838 | 5167 | const_tree func = fn_decl_or_type; |
c65ebc55 | 5168 | |
ba90d838 AS |
5169 | if (fn_decl_or_type |
5170 | && !DECL_P (fn_decl_or_type)) | |
5171 | func = NULL; | |
5172 | ||
c65ebc55 JW |
5173 | mode = TYPE_MODE (valtype); |
5174 | hfa_mode = hfa_element_mode (valtype, 0); | |
5175 | ||
5176 | if (hfa_mode != VOIDmode) | |
5177 | { | |
5178 | rtx loc[8]; | |
5179 | int i; | |
5180 | int hfa_size; | |
5181 | int byte_size; | |
5182 | int offset; | |
5183 | ||
5184 | hfa_size = GET_MODE_SIZE (hfa_mode); | |
5185 | byte_size = ((mode == BLKmode) | |
5186 | ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode)); | |
5187 | offset = 0; | |
5188 | for (i = 0; offset < byte_size; i++) | |
5189 | { | |
5190 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5191 | gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i), | |
5192 | GEN_INT (offset)); | |
c65ebc55 JW |
5193 | offset += hfa_size; |
5194 | } | |
9dec91d4 | 5195 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 5196 | } |
f57fc998 | 5197 | else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode) |
c65ebc55 JW |
5198 | return gen_rtx_REG (mode, FR_ARG_FIRST); |
5199 | else | |
3870df96 | 5200 | { |
8c5cacfd RH |
5201 | bool need_parallel = false; |
5202 | ||
5203 | /* In big-endian mode, we need to manage the layout of aggregates | |
5204 | in the registers so that we get the bits properly aligned in | |
5205 | the highpart of the registers. */ | |
3870df96 SE |
5206 | if (BYTES_BIG_ENDIAN |
5207 | && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype)))) | |
8c5cacfd RH |
5208 | need_parallel = true; |
5209 | ||
5210 | /* Something like struct S { long double x; char a[0] } is not an | |
5211 | HFA structure, and therefore doesn't go in fp registers. But | |
5212 | the middle-end will give it XFmode anyway, and XFmode values | |
5213 | don't normally fit in integer registers. So we need to smuggle | |
5214 | the value inside a parallel. */ | |
4de67c26 | 5215 | else if (mode == XFmode || mode == XCmode || mode == RFmode) |
8c5cacfd RH |
5216 | need_parallel = true; |
5217 | ||
5218 | if (need_parallel) | |
3870df96 SE |
5219 | { |
5220 | rtx loc[8]; | |
5221 | int offset; | |
5222 | int bytesize; | |
5223 | int i; | |
5224 | ||
5225 | offset = 0; | |
5226 | bytesize = int_size_in_bytes (valtype); | |
543144ed JM |
5227 | /* An empty PARALLEL is invalid here, but the return value |
5228 | doesn't matter for empty structs. */ | |
5229 | if (bytesize == 0) | |
5230 | return gen_rtx_REG (mode, GR_RET_FIRST); | |
3870df96 SE |
5231 | for (i = 0; offset < bytesize; i++) |
5232 | { | |
5233 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5234 | gen_rtx_REG (DImode, | |
5235 | GR_RET_FIRST + i), | |
5236 | GEN_INT (offset)); | |
5237 | offset += UNITS_PER_WORD; | |
5238 | } | |
5239 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); | |
5240 | } | |
8c5cacfd | 5241 | |
8ee95727 TG |
5242 | mode = promote_function_mode (valtype, mode, &unsignedp, |
5243 | func ? TREE_TYPE (func) : NULL_TREE, | |
5244 | true); | |
f2972bf8 | 5245 | |
8c5cacfd | 5246 | return gen_rtx_REG (mode, GR_RET_FIRST); |
3870df96 | 5247 | } |
c65ebc55 JW |
5248 | } |
5249 | ||
ba90d838 AS |
5250 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
5251 | ||
5252 | static rtx | |
ef4bddc2 | 5253 | ia64_libcall_value (machine_mode mode, |
ba90d838 AS |
5254 | const_rtx fun ATTRIBUTE_UNUSED) |
5255 | { | |
5256 | return gen_rtx_REG (mode, | |
5257 | (((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5258 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5259 | && (mode) != TFmode) | |
5260 | ? FR_RET_FIRST : GR_RET_FIRST)); | |
5261 | } | |
5262 | ||
5263 | /* Worker function for FUNCTION_VALUE_REGNO_P. */ | |
5264 | ||
5265 | static bool | |
5266 | ia64_function_value_regno_p (const unsigned int regno) | |
5267 | { | |
5268 | return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST) | |
5269 | || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST)); | |
5270 | } | |
5271 | ||
fdbe66f2 | 5272 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
5273 | We need to emit DTP-relative relocations. */ |
5274 | ||
fdbe66f2 | 5275 | static void |
9c808aad | 5276 | ia64_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 | 5277 | { |
6f3113ed SE |
5278 | gcc_assert (size == 4 || size == 8); |
5279 | if (size == 4) | |
5280 | fputs ("\tdata4.ua\t@dtprel(", file); | |
5281 | else | |
5282 | fputs ("\tdata8.ua\t@dtprel(", file); | |
6b2300b3 JJ |
5283 | output_addr_const (file, x); |
5284 | fputs (")", file); | |
5285 | } | |
5286 | ||
c65ebc55 JW |
5287 | /* Print a memory address as an operand to reference that memory location. */ |
5288 | ||
5289 | /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps | |
5290 | also call this from ia64_print_operand for memory addresses. */ | |
5291 | ||
5e50b799 | 5292 | static void |
9c808aad AJ |
5293 | ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED, |
5294 | rtx address ATTRIBUTE_UNUSED) | |
c65ebc55 JW |
5295 | { |
5296 | } | |
5297 | ||
3569057d | 5298 | /* Print an operand to an assembler instruction. |
c65ebc55 JW |
5299 | C Swap and print a comparison operator. |
5300 | D Print an FP comparison operator. | |
5301 | E Print 32 - constant, for SImode shifts as extract. | |
66db6b45 | 5302 | e Print 64 - constant, for DImode rotates. |
c65ebc55 JW |
5303 | F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or |
5304 | a floating point register emitted normally. | |
735b94a7 | 5305 | G A floating point constant. |
c65ebc55 | 5306 | I Invert a predicate register by adding 1. |
e5bde68a | 5307 | J Select the proper predicate register for a condition. |
6b6c1201 | 5308 | j Select the inverse predicate register for a condition. |
c65ebc55 JW |
5309 | O Append .acq for volatile load. |
5310 | P Postincrement of a MEM. | |
5311 | Q Append .rel for volatile store. | |
4883241c | 5312 | R Print .s .d or nothing for a single, double or no truncation. |
c65ebc55 JW |
5313 | S Shift amount for shladd instruction. |
5314 | T Print an 8-bit sign extended number (K) as a 32-bit unsigned number | |
5315 | for Intel assembler. | |
5316 | U Print an 8-bit sign extended number (K) as a 64-bit unsigned number | |
5317 | for Intel assembler. | |
a71aef0b | 5318 | X A pair of floating point registers. |
c65ebc55 | 5319 | r Print register name, or constant 0 as r0. HP compatibility for |
f61134e8 RH |
5320 | Linux kernel. |
5321 | v Print vector constant value as an 8-byte integer value. */ | |
5322 | ||
5e50b799 | 5323 | static void |
9c808aad | 5324 | ia64_print_operand (FILE * file, rtx x, int code) |
c65ebc55 | 5325 | { |
e57b9d65 RH |
5326 | const char *str; |
5327 | ||
c65ebc55 JW |
5328 | switch (code) |
5329 | { | |
c65ebc55 JW |
5330 | case 0: |
5331 | /* Handled below. */ | |
5332 | break; | |
809d4ef1 | 5333 | |
c65ebc55 JW |
5334 | case 'C': |
5335 | { | |
5336 | enum rtx_code c = swap_condition (GET_CODE (x)); | |
5337 | fputs (GET_RTX_NAME (c), file); | |
5338 | return; | |
5339 | } | |
5340 | ||
5341 | case 'D': | |
e57b9d65 RH |
5342 | switch (GET_CODE (x)) |
5343 | { | |
5344 | case NE: | |
5345 | str = "neq"; | |
5346 | break; | |
5347 | case UNORDERED: | |
5348 | str = "unord"; | |
5349 | break; | |
5350 | case ORDERED: | |
5351 | str = "ord"; | |
5352 | break; | |
86ad1da0 SE |
5353 | case UNLT: |
5354 | str = "nge"; | |
5355 | break; | |
5356 | case UNLE: | |
5357 | str = "ngt"; | |
5358 | break; | |
5359 | case UNGT: | |
5360 | str = "nle"; | |
5361 | break; | |
5362 | case UNGE: | |
5363 | str = "nlt"; | |
5364 | break; | |
8fc53a5f EB |
5365 | case UNEQ: |
5366 | case LTGT: | |
5367 | gcc_unreachable (); | |
e57b9d65 RH |
5368 | default: |
5369 | str = GET_RTX_NAME (GET_CODE (x)); | |
5370 | break; | |
5371 | } | |
5372 | fputs (str, file); | |
c65ebc55 JW |
5373 | return; |
5374 | ||
5375 | case 'E': | |
5376 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); | |
5377 | return; | |
5378 | ||
66db6b45 RH |
5379 | case 'e': |
5380 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x)); | |
5381 | return; | |
5382 | ||
c65ebc55 JW |
5383 | case 'F': |
5384 | if (x == CONST0_RTX (GET_MODE (x))) | |
e57b9d65 | 5385 | str = reg_names [FR_REG (0)]; |
c65ebc55 | 5386 | else if (x == CONST1_RTX (GET_MODE (x))) |
e57b9d65 | 5387 | str = reg_names [FR_REG (1)]; |
c65ebc55 | 5388 | else |
e820471b NS |
5389 | { |
5390 | gcc_assert (GET_CODE (x) == REG); | |
5391 | str = reg_names [REGNO (x)]; | |
5392 | } | |
e57b9d65 | 5393 | fputs (str, file); |
c65ebc55 JW |
5394 | return; |
5395 | ||
735b94a7 SE |
5396 | case 'G': |
5397 | { | |
5398 | long val[4]; | |
5399 | REAL_VALUE_TYPE rv; | |
5400 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
5401 | real_to_target (val, &rv, GET_MODE (x)); | |
5402 | if (GET_MODE (x) == SFmode) | |
5403 | fprintf (file, "0x%08lx", val[0] & 0xffffffff); | |
5404 | else if (GET_MODE (x) == DFmode) | |
5405 | fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1]) | |
5406 | & 0xffffffff, | |
5407 | (WORDS_BIG_ENDIAN ? val[1] : val[0]) | |
5408 | & 0xffffffff); | |
5409 | else | |
5410 | output_operand_lossage ("invalid %%G mode"); | |
5411 | } | |
5412 | return; | |
5413 | ||
c65ebc55 JW |
5414 | case 'I': |
5415 | fputs (reg_names [REGNO (x) + 1], file); | |
5416 | return; | |
5417 | ||
e5bde68a | 5418 | case 'J': |
6b6c1201 RH |
5419 | case 'j': |
5420 | { | |
5421 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5422 | if (GET_CODE (x) == EQ) | |
5423 | regno += 1; | |
5424 | if (code == 'j') | |
5425 | regno ^= 1; | |
5426 | fputs (reg_names [regno], file); | |
5427 | } | |
e5bde68a RH |
5428 | return; |
5429 | ||
c65ebc55 JW |
5430 | case 'O': |
5431 | if (MEM_VOLATILE_P (x)) | |
5432 | fputs(".acq", file); | |
5433 | return; | |
5434 | ||
5435 | case 'P': | |
5436 | { | |
4b983fdc | 5437 | HOST_WIDE_INT value; |
c65ebc55 | 5438 | |
4b983fdc RH |
5439 | switch (GET_CODE (XEXP (x, 0))) |
5440 | { | |
5441 | default: | |
5442 | return; | |
5443 | ||
5444 | case POST_MODIFY: | |
5445 | x = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
5446 | if (GET_CODE (x) == CONST_INT) | |
08012cda | 5447 | value = INTVAL (x); |
e820471b | 5448 | else |
4b983fdc | 5449 | { |
e820471b | 5450 | gcc_assert (GET_CODE (x) == REG); |
08012cda | 5451 | fprintf (file, ", %s", reg_names[REGNO (x)]); |
4b983fdc RH |
5452 | return; |
5453 | } | |
4b983fdc | 5454 | break; |
c65ebc55 | 5455 | |
4b983fdc RH |
5456 | case POST_INC: |
5457 | value = GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc | 5458 | break; |
c65ebc55 | 5459 | |
4b983fdc | 5460 | case POST_DEC: |
08012cda | 5461 | value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x)); |
4b983fdc RH |
5462 | break; |
5463 | } | |
809d4ef1 | 5464 | |
4a0a75dd | 5465 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value); |
c65ebc55 JW |
5466 | return; |
5467 | } | |
5468 | ||
5469 | case 'Q': | |
5470 | if (MEM_VOLATILE_P (x)) | |
5471 | fputs(".rel", file); | |
5472 | return; | |
5473 | ||
4883241c SE |
5474 | case 'R': |
5475 | if (x == CONST0_RTX (GET_MODE (x))) | |
5476 | fputs(".s", file); | |
5477 | else if (x == CONST1_RTX (GET_MODE (x))) | |
5478 | fputs(".d", file); | |
5479 | else if (x == CONST2_RTX (GET_MODE (x))) | |
5480 | ; | |
5481 | else | |
5482 | output_operand_lossage ("invalid %%R value"); | |
5483 | return; | |
5484 | ||
c65ebc55 | 5485 | case 'S': |
809d4ef1 | 5486 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
c65ebc55 JW |
5487 | return; |
5488 | ||
5489 | case 'T': | |
5490 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5491 | { | |
809d4ef1 | 5492 | fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5493 | return; |
5494 | } | |
5495 | break; | |
5496 | ||
5497 | case 'U': | |
5498 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5499 | { | |
3b572406 | 5500 | const char *prefix = "0x"; |
c65ebc55 JW |
5501 | if (INTVAL (x) & 0x80000000) |
5502 | { | |
5503 | fprintf (file, "0xffffffff"); | |
5504 | prefix = ""; | |
5505 | } | |
809d4ef1 | 5506 | fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5507 | return; |
5508 | } | |
5509 | break; | |
809d4ef1 | 5510 | |
a71aef0b JB |
5511 | case 'X': |
5512 | { | |
5513 | unsigned int regno = REGNO (x); | |
5514 | fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]); | |
5515 | } | |
5516 | return; | |
5517 | ||
c65ebc55 | 5518 | case 'r': |
18a3c539 JW |
5519 | /* If this operand is the constant zero, write it as register zero. |
5520 | Any register, zero, or CONST_INT value is OK here. */ | |
c65ebc55 JW |
5521 | if (GET_CODE (x) == REG) |
5522 | fputs (reg_names[REGNO (x)], file); | |
5523 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5524 | fputs ("r0", file); | |
18a3c539 JW |
5525 | else if (GET_CODE (x) == CONST_INT) |
5526 | output_addr_const (file, x); | |
c65ebc55 JW |
5527 | else |
5528 | output_operand_lossage ("invalid %%r value"); | |
5529 | return; | |
5530 | ||
f61134e8 RH |
5531 | case 'v': |
5532 | gcc_assert (GET_CODE (x) == CONST_VECTOR); | |
5533 | x = simplify_subreg (DImode, x, GET_MODE (x), 0); | |
5534 | break; | |
5535 | ||
85548039 RH |
5536 | case '+': |
5537 | { | |
5538 | const char *which; | |
9c808aad | 5539 | |
85548039 RH |
5540 | /* For conditional branches, returns or calls, substitute |
5541 | sptk, dptk, dpnt, or spnt for %s. */ | |
5542 | x = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
5543 | if (x) | |
5544 | { | |
e5af9ddd | 5545 | int pred_val = XINT (x, 0); |
85548039 RH |
5546 | |
5547 | /* Guess top and bottom 10% statically predicted. */ | |
2c9e13f3 JH |
5548 | if (pred_val < REG_BR_PROB_BASE / 50 |
5549 | && br_prob_note_reliable_p (x)) | |
85548039 RH |
5550 | which = ".spnt"; |
5551 | else if (pred_val < REG_BR_PROB_BASE / 2) | |
5552 | which = ".dpnt"; | |
2c9e13f3 JH |
5553 | else if (pred_val < REG_BR_PROB_BASE / 100 * 98 |
5554 | || !br_prob_note_reliable_p (x)) | |
85548039 RH |
5555 | which = ".dptk"; |
5556 | else | |
5557 | which = ".sptk"; | |
5558 | } | |
b64925dc | 5559 | else if (CALL_P (current_output_insn)) |
85548039 RH |
5560 | which = ".sptk"; |
5561 | else | |
5562 | which = ".dptk"; | |
5563 | ||
5564 | fputs (which, file); | |
5565 | return; | |
5566 | } | |
5567 | ||
6f8aa100 RH |
5568 | case ',': |
5569 | x = current_insn_predicate; | |
5570 | if (x) | |
5571 | { | |
5572 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5573 | if (GET_CODE (x) == EQ) | |
5574 | regno += 1; | |
6f8aa100 RH |
5575 | fprintf (file, "(%s) ", reg_names [regno]); |
5576 | } | |
5577 | return; | |
5578 | ||
c65ebc55 JW |
5579 | default: |
5580 | output_operand_lossage ("ia64_print_operand: unknown code"); | |
5581 | return; | |
5582 | } | |
5583 | ||
5584 | switch (GET_CODE (x)) | |
5585 | { | |
5586 | /* This happens for the spill/restore instructions. */ | |
5587 | case POST_INC: | |
4b983fdc RH |
5588 | case POST_DEC: |
5589 | case POST_MODIFY: | |
c65ebc55 | 5590 | x = XEXP (x, 0); |
ed168e45 | 5591 | /* ... fall through ... */ |
c65ebc55 JW |
5592 | |
5593 | case REG: | |
5594 | fputs (reg_names [REGNO (x)], file); | |
5595 | break; | |
5596 | ||
5597 | case MEM: | |
5598 | { | |
5599 | rtx addr = XEXP (x, 0); | |
ec8e098d | 5600 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC) |
c65ebc55 JW |
5601 | addr = XEXP (addr, 0); |
5602 | fprintf (file, "[%s]", reg_names [REGNO (addr)]); | |
5603 | break; | |
5604 | } | |
809d4ef1 | 5605 | |
c65ebc55 JW |
5606 | default: |
5607 | output_addr_const (file, x); | |
5608 | break; | |
5609 | } | |
5610 | ||
5611 | return; | |
5612 | } | |
5e50b799 AS |
5613 | |
5614 | /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ | |
5615 | ||
5616 | static bool | |
5617 | ia64_print_operand_punct_valid_p (unsigned char code) | |
5618 | { | |
5619 | return (code == '+' || code == ','); | |
5620 | } | |
c65ebc55 | 5621 | \f |
3c50106f RH |
5622 | /* Compute a (partial) cost for rtx X. Return true if the complete |
5623 | cost has been computed, and false if subexpressions should be | |
5624 | scanned. In either case, *TOTAL contains the cost result. */ | |
5625 | /* ??? This is incomplete. */ | |
5626 | ||
5627 | static bool | |
68f932c4 RS |
5628 | ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
5629 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
5630 | { |
5631 | switch (code) | |
5632 | { | |
5633 | case CONST_INT: | |
5634 | switch (outer_code) | |
5635 | { | |
5636 | case SET: | |
13f70342 | 5637 | *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1); |
3c50106f RH |
5638 | return true; |
5639 | case PLUS: | |
13f70342 | 5640 | if (satisfies_constraint_I (x)) |
3c50106f | 5641 | *total = 0; |
13f70342 | 5642 | else if (satisfies_constraint_J (x)) |
3c50106f RH |
5643 | *total = 1; |
5644 | else | |
5645 | *total = COSTS_N_INSNS (1); | |
5646 | return true; | |
5647 | default: | |
13f70342 | 5648 | if (satisfies_constraint_K (x) || satisfies_constraint_L (x)) |
3c50106f RH |
5649 | *total = 0; |
5650 | else | |
5651 | *total = COSTS_N_INSNS (1); | |
5652 | return true; | |
5653 | } | |
5654 | ||
5655 | case CONST_DOUBLE: | |
5656 | *total = COSTS_N_INSNS (1); | |
5657 | return true; | |
5658 | ||
5659 | case CONST: | |
5660 | case SYMBOL_REF: | |
5661 | case LABEL_REF: | |
5662 | *total = COSTS_N_INSNS (3); | |
5663 | return true; | |
5664 | ||
f19f1e5e RH |
5665 | case FMA: |
5666 | *total = COSTS_N_INSNS (4); | |
5667 | return true; | |
5668 | ||
3c50106f RH |
5669 | case MULT: |
5670 | /* For multiplies wider than HImode, we have to go to the FPU, | |
5671 | which normally involves copies. Plus there's the latency | |
5672 | of the multiply itself, and the latency of the instructions to | |
5673 | transfer integer regs to FP regs. */ | |
f19f1e5e RH |
5674 | if (FLOAT_MODE_P (GET_MODE (x))) |
5675 | *total = COSTS_N_INSNS (4); | |
5676 | else if (GET_MODE_SIZE (GET_MODE (x)) > 2) | |
3c50106f RH |
5677 | *total = COSTS_N_INSNS (10); |
5678 | else | |
5679 | *total = COSTS_N_INSNS (2); | |
5680 | return true; | |
5681 | ||
5682 | case PLUS: | |
5683 | case MINUS: | |
f19f1e5e RH |
5684 | if (FLOAT_MODE_P (GET_MODE (x))) |
5685 | { | |
5686 | *total = COSTS_N_INSNS (4); | |
5687 | return true; | |
5688 | } | |
5689 | /* FALLTHRU */ | |
5690 | ||
3c50106f RH |
5691 | case ASHIFT: |
5692 | case ASHIFTRT: | |
5693 | case LSHIFTRT: | |
5694 | *total = COSTS_N_INSNS (1); | |
5695 | return true; | |
5696 | ||
5697 | case DIV: | |
5698 | case UDIV: | |
5699 | case MOD: | |
5700 | case UMOD: | |
5701 | /* We make divide expensive, so that divide-by-constant will be | |
5702 | optimized to a multiply. */ | |
5703 | *total = COSTS_N_INSNS (60); | |
5704 | return true; | |
5705 | ||
5706 | default: | |
5707 | return false; | |
5708 | } | |
5709 | } | |
5710 | ||
9e4f94de | 5711 | /* Calculate the cost of moving data from a register in class FROM to |
7109d286 | 5712 | one in class TO, using MODE. */ |
5527bf14 | 5713 | |
de8f4b07 | 5714 | static int |
ef4bddc2 | 5715 | ia64_register_move_cost (machine_mode mode, reg_class_t from, |
6f76a878 | 5716 | reg_class_t to) |
a87cf97e | 5717 | { |
7109d286 RH |
5718 | /* ADDL_REGS is the same as GR_REGS for movement purposes. */ |
5719 | if (to == ADDL_REGS) | |
5720 | to = GR_REGS; | |
5721 | if (from == ADDL_REGS) | |
5722 | from = GR_REGS; | |
5723 | ||
5724 | /* All costs are symmetric, so reduce cases by putting the | |
5725 | lower number class as the destination. */ | |
5726 | if (from < to) | |
5727 | { | |
6f76a878 | 5728 | reg_class_t tmp = to; |
7109d286 RH |
5729 | to = from, from = tmp; |
5730 | } | |
5731 | ||
02befdf4 | 5732 | /* Moving from FR<->GR in XFmode must be more expensive than 2, |
7109d286 | 5733 | so that we get secondary memory reloads. Between FR_REGS, |
69e18c09 | 5734 | we have to make this at least as expensive as memory_move_cost |
7109d286 | 5735 | to avoid spectacularly poor register class preferencing. */ |
4de67c26 | 5736 | if (mode == XFmode || mode == RFmode) |
7109d286 RH |
5737 | { |
5738 | if (to != GR_REGS || from != GR_REGS) | |
69e18c09 | 5739 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5740 | else |
5741 | return 3; | |
5742 | } | |
5743 | ||
5744 | switch (to) | |
5745 | { | |
5746 | case PR_REGS: | |
5747 | /* Moving between PR registers takes two insns. */ | |
5748 | if (from == PR_REGS) | |
5749 | return 3; | |
5750 | /* Moving between PR and anything but GR is impossible. */ | |
5751 | if (from != GR_REGS) | |
69e18c09 | 5752 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5753 | break; |
5754 | ||
5755 | case BR_REGS: | |
5756 | /* Moving between BR and anything but GR is impossible. */ | |
5757 | if (from != GR_REGS && from != GR_AND_BR_REGS) | |
69e18c09 | 5758 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5759 | break; |
5760 | ||
5761 | case AR_I_REGS: | |
5762 | case AR_M_REGS: | |
5763 | /* Moving between AR and anything but GR is impossible. */ | |
5764 | if (from != GR_REGS) | |
69e18c09 | 5765 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5766 | break; |
5767 | ||
5768 | case GR_REGS: | |
5769 | case FR_REGS: | |
a71aef0b | 5770 | case FP_REGS: |
7109d286 RH |
5771 | case GR_AND_FR_REGS: |
5772 | case GR_AND_BR_REGS: | |
5773 | case ALL_REGS: | |
5774 | break; | |
5775 | ||
5776 | default: | |
e820471b | 5777 | gcc_unreachable (); |
7109d286 | 5778 | } |
3f622353 | 5779 | |
5527bf14 RH |
5780 | return 2; |
5781 | } | |
c65ebc55 | 5782 | |
69e18c09 AS |
5783 | /* Calculate the cost of moving data of MODE from a register to or from |
5784 | memory. */ | |
5785 | ||
5786 | static int | |
ef4bddc2 | 5787 | ia64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
69e18c09 AS |
5788 | reg_class_t rclass, |
5789 | bool in ATTRIBUTE_UNUSED) | |
5790 | { | |
5791 | if (rclass == GENERAL_REGS | |
5792 | || rclass == FR_REGS | |
5793 | || rclass == FP_REGS | |
5794 | || rclass == GR_AND_FR_REGS) | |
5795 | return 4; | |
5796 | else | |
5797 | return 10; | |
5798 | } | |
5799 | ||
ab177ad5 AS |
5800 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions |
5801 | on RCLASS to use when copying X into that class. */ | |
f61134e8 | 5802 | |
ab177ad5 AS |
5803 | static reg_class_t |
5804 | ia64_preferred_reload_class (rtx x, reg_class_t rclass) | |
f61134e8 | 5805 | { |
0a2aaacc | 5806 | switch (rclass) |
f61134e8 RH |
5807 | { |
5808 | case FR_REGS: | |
a71aef0b | 5809 | case FP_REGS: |
f61134e8 RH |
5810 | /* Don't allow volatile mem reloads into floating point registers. |
5811 | This is defined to force reload to choose the r/m case instead | |
5812 | of the f/f case when reloading (set (reg fX) (mem/v)). */ | |
5813 | if (MEM_P (x) && MEM_VOLATILE_P (x)) | |
5814 | return NO_REGS; | |
5815 | ||
5816 | /* Force all unrecognized constants into the constant pool. */ | |
5817 | if (CONSTANT_P (x)) | |
5818 | return NO_REGS; | |
5819 | break; | |
5820 | ||
5821 | case AR_M_REGS: | |
5822 | case AR_I_REGS: | |
5823 | if (!OBJECT_P (x)) | |
5824 | return NO_REGS; | |
5825 | break; | |
5826 | ||
5827 | default: | |
5828 | break; | |
5829 | } | |
5830 | ||
0a2aaacc | 5831 | return rclass; |
f61134e8 RH |
5832 | } |
5833 | ||
c65ebc55 | 5834 | /* This function returns the register class required for a secondary |
0a2aaacc | 5835 | register when copying between one of the registers in RCLASS, and X, |
c65ebc55 JW |
5836 | using MODE. A return value of NO_REGS means that no secondary register |
5837 | is required. */ | |
5838 | ||
5839 | enum reg_class | |
0a2aaacc | 5840 | ia64_secondary_reload_class (enum reg_class rclass, |
ef4bddc2 | 5841 | machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
c65ebc55 JW |
5842 | { |
5843 | int regno = -1; | |
5844 | ||
5845 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
5846 | regno = true_regnum (x); | |
5847 | ||
0a2aaacc | 5848 | switch (rclass) |
97e242b0 RH |
5849 | { |
5850 | case BR_REGS: | |
7109d286 RH |
5851 | case AR_M_REGS: |
5852 | case AR_I_REGS: | |
5853 | /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global | |
5854 | interaction. We end up with two pseudos with overlapping lifetimes | |
5855 | both of which are equiv to the same constant, and both which need | |
5856 | to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end | |
5857 | changes depending on the path length, which means the qty_first_reg | |
5858 | check in make_regs_eqv can give different answers at different times. | |
5859 | At some point I'll probably need a reload_indi pattern to handle | |
5860 | this. | |
5861 | ||
5862 | We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we | |
5863 | wound up with a FP register from GR_AND_FR_REGS. Extend that to all | |
5864 | non-general registers for good measure. */ | |
5865 | if (regno >= 0 && ! GENERAL_REGNO_P (regno)) | |
97e242b0 RH |
5866 | return GR_REGS; |
5867 | ||
5868 | /* This is needed if a pseudo used as a call_operand gets spilled to a | |
5869 | stack slot. */ | |
5870 | if (GET_CODE (x) == MEM) | |
5871 | return GR_REGS; | |
5872 | break; | |
5873 | ||
5874 | case FR_REGS: | |
a71aef0b | 5875 | case FP_REGS: |
c51e6d85 | 5876 | /* Need to go through general registers to get to other class regs. */ |
7109d286 RH |
5877 | if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno))) |
5878 | return GR_REGS; | |
9c808aad | 5879 | |
97e242b0 RH |
5880 | /* This can happen when a paradoxical subreg is an operand to the |
5881 | muldi3 pattern. */ | |
5882 | /* ??? This shouldn't be necessary after instruction scheduling is | |
5883 | enabled, because paradoxical subregs are not accepted by | |
5884 | register_operand when INSN_SCHEDULING is defined. Or alternatively, | |
5885 | stop the paradoxical subreg stupidity in the *_operand functions | |
5886 | in recog.c. */ | |
5887 | if (GET_CODE (x) == MEM | |
5888 | && (GET_MODE (x) == SImode || GET_MODE (x) == HImode | |
5889 | || GET_MODE (x) == QImode)) | |
5890 | return GR_REGS; | |
5891 | ||
5892 | /* This can happen because of the ior/and/etc patterns that accept FP | |
5893 | registers as operands. If the third operand is a constant, then it | |
5894 | needs to be reloaded into a FP register. */ | |
5895 | if (GET_CODE (x) == CONST_INT) | |
5896 | return GR_REGS; | |
5897 | ||
5898 | /* This can happen because of register elimination in a muldi3 insn. | |
5899 | E.g. `26107 * (unsigned long)&u'. */ | |
5900 | if (GET_CODE (x) == PLUS) | |
5901 | return GR_REGS; | |
5902 | break; | |
5903 | ||
5904 | case PR_REGS: | |
f2f90c63 | 5905 | /* ??? This happens if we cse/gcse a BImode value across a call, |
97e242b0 RH |
5906 | and the function has a nonlocal goto. This is because global |
5907 | does not allocate call crossing pseudos to hard registers when | |
e3b5732b | 5908 | crtl->has_nonlocal_goto is true. This is relatively |
97e242b0 RH |
5909 | common for C++ programs that use exceptions. To reproduce, |
5910 | return NO_REGS and compile libstdc++. */ | |
5911 | if (GET_CODE (x) == MEM) | |
5912 | return GR_REGS; | |
f2f90c63 RH |
5913 | |
5914 | /* This can happen when we take a BImode subreg of a DImode value, | |
5915 | and that DImode value winds up in some non-GR register. */ | |
5916 | if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno)) | |
5917 | return GR_REGS; | |
97e242b0 RH |
5918 | break; |
5919 | ||
5920 | default: | |
5921 | break; | |
5922 | } | |
c65ebc55 JW |
5923 | |
5924 | return NO_REGS; | |
5925 | } | |
5926 | ||
215b063c PB |
5927 | \f |
5928 | /* Implement targetm.unspec_may_trap_p hook. */ | |
5929 | static int | |
5930 | ia64_unspec_may_trap_p (const_rtx x, unsigned flags) | |
5931 | { | |
c84a808e EB |
5932 | switch (XINT (x, 1)) |
5933 | { | |
5934 | case UNSPEC_LDA: | |
5935 | case UNSPEC_LDS: | |
5936 | case UNSPEC_LDSA: | |
5937 | case UNSPEC_LDCCLR: | |
5938 | case UNSPEC_CHKACLR: | |
5939 | case UNSPEC_CHKS: | |
5940 | /* These unspecs are just wrappers. */ | |
5941 | return may_trap_p_1 (XVECEXP (x, 0, 0), flags); | |
215b063c PB |
5942 | } |
5943 | ||
5944 | return default_unspec_may_trap_p (x, flags); | |
5945 | } | |
5946 | ||
c65ebc55 JW |
5947 | \f |
5948 | /* Parse the -mfixed-range= option string. */ | |
5949 | ||
5950 | static void | |
9c808aad | 5951 | fix_range (const char *const_str) |
c65ebc55 JW |
5952 | { |
5953 | int i, first, last; | |
3b572406 | 5954 | char *str, *dash, *comma; |
c65ebc55 JW |
5955 | |
5956 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
5957 | REG2 are either register names or register numbers. The effect | |
5958 | of this option is to mark the registers in the range from REG1 to | |
5959 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
5960 | used, e.g., to ensure that kernel mode code doesn't use f32-f127. */ | |
5961 | ||
3b572406 RH |
5962 | i = strlen (const_str); |
5963 | str = (char *) alloca (i + 1); | |
5964 | memcpy (str, const_str, i + 1); | |
5965 | ||
c65ebc55 JW |
5966 | while (1) |
5967 | { | |
5968 | dash = strchr (str, '-'); | |
5969 | if (!dash) | |
5970 | { | |
d4ee4d25 | 5971 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
c65ebc55 JW |
5972 | return; |
5973 | } | |
5974 | *dash = '\0'; | |
5975 | ||
5976 | comma = strchr (dash + 1, ','); | |
5977 | if (comma) | |
5978 | *comma = '\0'; | |
5979 | ||
5980 | first = decode_reg_name (str); | |
5981 | if (first < 0) | |
5982 | { | |
d4ee4d25 | 5983 | warning (0, "unknown register name: %s", str); |
c65ebc55 JW |
5984 | return; |
5985 | } | |
5986 | ||
5987 | last = decode_reg_name (dash + 1); | |
5988 | if (last < 0) | |
5989 | { | |
d4ee4d25 | 5990 | warning (0, "unknown register name: %s", dash + 1); |
c65ebc55 JW |
5991 | return; |
5992 | } | |
5993 | ||
5994 | *dash = '-'; | |
5995 | ||
5996 | if (first > last) | |
5997 | { | |
d4ee4d25 | 5998 | warning (0, "%s-%s is an empty range", str, dash + 1); |
c65ebc55 JW |
5999 | return; |
6000 | } | |
6001 | ||
6002 | for (i = first; i <= last; ++i) | |
6003 | fixed_regs[i] = call_used_regs[i] = 1; | |
6004 | ||
6005 | if (!comma) | |
6006 | break; | |
6007 | ||
6008 | *comma = ','; | |
6009 | str = comma + 1; | |
6010 | } | |
6011 | } | |
6012 | ||
930572b9 | 6013 | /* Implement TARGET_OPTION_OVERRIDE. */ |
c65ebc55 | 6014 | |
930572b9 AS |
6015 | static void |
6016 | ia64_option_override (void) | |
c65ebc55 | 6017 | { |
e6cc0c98 JM |
6018 | unsigned int i; |
6019 | cl_deferred_option *opt; | |
9771b263 DN |
6020 | vec<cl_deferred_option> *v |
6021 | = (vec<cl_deferred_option> *) ia64_deferred_options; | |
e6cc0c98 | 6022 | |
9771b263 DN |
6023 | if (v) |
6024 | FOR_EACH_VEC_ELT (*v, i, opt) | |
6025 | { | |
6026 | switch (opt->opt_index) | |
6027 | { | |
6028 | case OPT_mfixed_range_: | |
6029 | fix_range (opt->arg); | |
6030 | break; | |
e6cc0c98 | 6031 | |
9771b263 DN |
6032 | default: |
6033 | gcc_unreachable (); | |
6034 | } | |
6035 | } | |
e6cc0c98 | 6036 | |
59da9a7d JW |
6037 | if (TARGET_AUTO_PIC) |
6038 | target_flags |= MASK_CONST_GP; | |
6039 | ||
7e1e7d4c VM |
6040 | /* Numerous experiment shows that IRA based loop pressure |
6041 | calculation works better for RTL loop invariant motion on targets | |
6042 | with enough (>= 32) registers. It is an expensive optimization. | |
6043 | So it is on only for peak performance. */ | |
6044 | if (optimize >= 3) | |
6045 | flag_ira_loop_pressure = 1; | |
6046 | ||
6047 | ||
fa37ed29 JM |
6048 | ia64_section_threshold = (global_options_set.x_g_switch_value |
6049 | ? g_switch_value | |
6050 | : IA64_DEFAULT_GVALUE); | |
2b7e2984 SE |
6051 | |
6052 | init_machine_status = ia64_init_machine_status; | |
6053 | ||
6054 | if (align_functions <= 0) | |
6055 | align_functions = 64; | |
6056 | if (align_loops <= 0) | |
6057 | align_loops = 32; | |
6058 | if (TARGET_ABI_OPEN_VMS) | |
6059 | flag_no_common = 1; | |
6060 | ||
6061 | ia64_override_options_after_change(); | |
6062 | } | |
6063 | ||
6064 | /* Implement targetm.override_options_after_change. */ | |
6065 | ||
6066 | static void | |
6067 | ia64_override_options_after_change (void) | |
6068 | { | |
388092d5 | 6069 | if (optimize >= 3 |
d4d24ba4 JM |
6070 | && !global_options_set.x_flag_selective_scheduling |
6071 | && !global_options_set.x_flag_selective_scheduling2) | |
388092d5 AB |
6072 | { |
6073 | flag_selective_scheduling2 = 1; | |
6074 | flag_sel_sched_pipelining = 1; | |
6075 | } | |
6076 | if (mflag_sched_control_spec == 2) | |
6077 | { | |
6078 | /* Control speculation is on by default for the selective scheduler, | |
6079 | but not for the Haifa scheduler. */ | |
6080 | mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0; | |
6081 | } | |
6082 | if (flag_sel_sched_pipelining && flag_auto_inc_dec) | |
6083 | { | |
6084 | /* FIXME: remove this when we'd implement breaking autoinsns as | |
6085 | a transformation. */ | |
6086 | flag_auto_inc_dec = 0; | |
6087 | } | |
c65ebc55 | 6088 | } |
dbdd120f | 6089 | |
6fb5fa3c DB |
6090 | /* Initialize the record of emitted frame related registers. */ |
6091 | ||
6092 | void ia64_init_expanders (void) | |
6093 | { | |
6094 | memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs)); | |
6095 | } | |
6096 | ||
dbdd120f RH |
6097 | static struct machine_function * |
6098 | ia64_init_machine_status (void) | |
6099 | { | |
766090c2 | 6100 | return ggc_cleared_alloc<machine_function> (); |
dbdd120f | 6101 | } |
c65ebc55 | 6102 | \f |
647d790d DM |
6103 | static enum attr_itanium_class ia64_safe_itanium_class (rtx_insn *); |
6104 | static enum attr_type ia64_safe_type (rtx_insn *); | |
2130b7fb | 6105 | |
2130b7fb | 6106 | static enum attr_itanium_class |
647d790d | 6107 | ia64_safe_itanium_class (rtx_insn *insn) |
2130b7fb BS |
6108 | { |
6109 | if (recog_memoized (insn) >= 0) | |
6110 | return get_attr_itanium_class (insn); | |
b5b8b0ac AO |
6111 | else if (DEBUG_INSN_P (insn)) |
6112 | return ITANIUM_CLASS_IGNORE; | |
2130b7fb BS |
6113 | else |
6114 | return ITANIUM_CLASS_UNKNOWN; | |
6115 | } | |
6116 | ||
6117 | static enum attr_type | |
647d790d | 6118 | ia64_safe_type (rtx_insn *insn) |
2130b7fb BS |
6119 | { |
6120 | if (recog_memoized (insn) >= 0) | |
6121 | return get_attr_type (insn); | |
6122 | else | |
6123 | return TYPE_UNKNOWN; | |
6124 | } | |
6125 | \f | |
c65ebc55 JW |
6126 | /* The following collection of routines emit instruction group stop bits as |
6127 | necessary to avoid dependencies. */ | |
6128 | ||
6129 | /* Need to track some additional registers as far as serialization is | |
6130 | concerned so we can properly handle br.call and br.ret. We could | |
6131 | make these registers visible to gcc, but since these registers are | |
6132 | never explicitly used in gcc generated code, it seems wasteful to | |
6133 | do so (plus it would make the call and return patterns needlessly | |
6134 | complex). */ | |
c65ebc55 | 6135 | #define REG_RP (BR_REG (0)) |
c65ebc55 | 6136 | #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1) |
c65ebc55 JW |
6137 | /* This is used for volatile asms which may require a stop bit immediately |
6138 | before and after them. */ | |
5527bf14 | 6139 | #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2) |
870f9ec0 RH |
6140 | #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3) |
6141 | #define NUM_REGS (AR_UNAT_BIT_0 + 64) | |
c65ebc55 | 6142 | |
f2f90c63 RH |
6143 | /* For each register, we keep track of how it has been written in the |
6144 | current instruction group. | |
6145 | ||
6146 | If a register is written unconditionally (no qualifying predicate), | |
6147 | WRITE_COUNT is set to 2 and FIRST_PRED is ignored. | |
6148 | ||
6149 | If a register is written if its qualifying predicate P is true, we | |
6150 | set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register | |
6151 | may be written again by the complement of P (P^1) and when this happens, | |
6152 | WRITE_COUNT gets set to 2. | |
6153 | ||
6154 | The result of this is that whenever an insn attempts to write a register | |
e03f5d43 | 6155 | whose WRITE_COUNT is two, we need to issue an insn group barrier first. |
f2f90c63 RH |
6156 | |
6157 | If a predicate register is written by a floating-point insn, we set | |
6158 | WRITTEN_BY_FP to true. | |
6159 | ||
6160 | If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND | |
6161 | to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */ | |
6162 | ||
444a356a JJ |
6163 | #if GCC_VERSION >= 4000 |
6164 | #define RWS_FIELD_TYPE __extension__ unsigned short | |
6165 | #else | |
6166 | #define RWS_FIELD_TYPE unsigned int | |
6167 | #endif | |
c65ebc55 JW |
6168 | struct reg_write_state |
6169 | { | |
444a356a JJ |
6170 | RWS_FIELD_TYPE write_count : 2; |
6171 | RWS_FIELD_TYPE first_pred : 10; | |
6172 | RWS_FIELD_TYPE written_by_fp : 1; | |
6173 | RWS_FIELD_TYPE written_by_and : 1; | |
6174 | RWS_FIELD_TYPE written_by_or : 1; | |
c65ebc55 JW |
6175 | }; |
6176 | ||
6177 | /* Cumulative info for the current instruction group. */ | |
6178 | struct reg_write_state rws_sum[NUM_REGS]; | |
444a356a JJ |
6179 | #ifdef ENABLE_CHECKING |
6180 | /* Bitmap whether a register has been written in the current insn. */ | |
6181 | HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) | |
6182 | / HOST_BITS_PER_WIDEST_FAST_INT]; | |
6183 | ||
6184 | static inline void | |
6185 | rws_insn_set (int regno) | |
6186 | { | |
6187 | gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno)); | |
6188 | SET_HARD_REG_BIT (rws_insn, regno); | |
6189 | } | |
6190 | ||
6191 | static inline int | |
6192 | rws_insn_test (int regno) | |
6193 | { | |
6194 | return TEST_HARD_REG_BIT (rws_insn, regno); | |
6195 | } | |
6196 | #else | |
6197 | /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */ | |
6198 | unsigned char rws_insn[2]; | |
6199 | ||
6200 | static inline void | |
6201 | rws_insn_set (int regno) | |
6202 | { | |
6203 | if (regno == REG_AR_CFM) | |
6204 | rws_insn[0] = 1; | |
6205 | else if (regno == REG_VOLATILE) | |
6206 | rws_insn[1] = 1; | |
6207 | } | |
6208 | ||
6209 | static inline int | |
6210 | rws_insn_test (int regno) | |
6211 | { | |
6212 | if (regno == REG_AR_CFM) | |
6213 | return rws_insn[0]; | |
6214 | if (regno == REG_VOLATILE) | |
6215 | return rws_insn[1]; | |
6216 | return 0; | |
6217 | } | |
6218 | #endif | |
c65ebc55 | 6219 | |
25250265 | 6220 | /* Indicates whether this is the first instruction after a stop bit, |
e820471b NS |
6221 | in which case we don't need another stop bit. Without this, |
6222 | ia64_variable_issue will die when scheduling an alloc. */ | |
25250265 JW |
6223 | static int first_instruction; |
6224 | ||
c65ebc55 JW |
6225 | /* Misc flags needed to compute RAW/WAW dependencies while we are traversing |
6226 | RTL for one instruction. */ | |
6227 | struct reg_flags | |
6228 | { | |
6229 | unsigned int is_write : 1; /* Is register being written? */ | |
6230 | unsigned int is_fp : 1; /* Is register used as part of an fp op? */ | |
6231 | unsigned int is_branch : 1; /* Is register used as part of a branch? */ | |
f2f90c63 RH |
6232 | unsigned int is_and : 1; /* Is register used as part of and.orcm? */ |
6233 | unsigned int is_or : 1; /* Is register used as part of or.andcm? */ | |
2ed4af6f | 6234 | unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */ |
c65ebc55 JW |
6235 | }; |
6236 | ||
444a356a | 6237 | static void rws_update (int, struct reg_flags, int); |
9c808aad AJ |
6238 | static int rws_access_regno (int, struct reg_flags, int); |
6239 | static int rws_access_reg (rtx, struct reg_flags, int); | |
c1bc6ca8 JW |
6240 | static void update_set_flags (rtx, struct reg_flags *); |
6241 | static int set_src_needs_barrier (rtx, struct reg_flags, int); | |
9c808aad AJ |
6242 | static int rtx_needs_barrier (rtx, struct reg_flags, int); |
6243 | static void init_insn_group_barriers (void); | |
647d790d DM |
6244 | static int group_barrier_needed (rtx_insn *); |
6245 | static int safe_group_barrier_needed (rtx_insn *); | |
444a356a | 6246 | static int in_safe_group_barrier; |
3b572406 | 6247 | |
c65ebc55 JW |
6248 | /* Update *RWS for REGNO, which is being written by the current instruction, |
6249 | with predicate PRED, and associated register flags in FLAGS. */ | |
6250 | ||
6251 | static void | |
444a356a | 6252 | rws_update (int regno, struct reg_flags flags, int pred) |
c65ebc55 | 6253 | { |
3e7c7805 | 6254 | if (pred) |
444a356a | 6255 | rws_sum[regno].write_count++; |
3e7c7805 | 6256 | else |
444a356a JJ |
6257 | rws_sum[regno].write_count = 2; |
6258 | rws_sum[regno].written_by_fp |= flags.is_fp; | |
f2f90c63 | 6259 | /* ??? Not tracking and/or across differing predicates. */ |
444a356a JJ |
6260 | rws_sum[regno].written_by_and = flags.is_and; |
6261 | rws_sum[regno].written_by_or = flags.is_or; | |
6262 | rws_sum[regno].first_pred = pred; | |
c65ebc55 JW |
6263 | } |
6264 | ||
6265 | /* Handle an access to register REGNO of type FLAGS using predicate register | |
444a356a | 6266 | PRED. Update rws_sum array. Return 1 if this access creates |
c65ebc55 JW |
6267 | a dependency with an earlier instruction in the same group. */ |
6268 | ||
6269 | static int | |
9c808aad | 6270 | rws_access_regno (int regno, struct reg_flags flags, int pred) |
c65ebc55 JW |
6271 | { |
6272 | int need_barrier = 0; | |
c65ebc55 | 6273 | |
e820471b | 6274 | gcc_assert (regno < NUM_REGS); |
c65ebc55 | 6275 | |
f2f90c63 RH |
6276 | if (! PR_REGNO_P (regno)) |
6277 | flags.is_and = flags.is_or = 0; | |
6278 | ||
c65ebc55 JW |
6279 | if (flags.is_write) |
6280 | { | |
12c2c7aa JW |
6281 | int write_count; |
6282 | ||
444a356a | 6283 | rws_insn_set (regno); |
12c2c7aa | 6284 | write_count = rws_sum[regno].write_count; |
12c2c7aa JW |
6285 | |
6286 | switch (write_count) | |
c65ebc55 JW |
6287 | { |
6288 | case 0: | |
6289 | /* The register has not been written yet. */ | |
444a356a JJ |
6290 | if (!in_safe_group_barrier) |
6291 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6292 | break; |
6293 | ||
6294 | case 1: | |
89774469 SE |
6295 | /* The register has been written via a predicate. Treat |
6296 | it like a unconditional write and do not try to check | |
6297 | for complementary pred reg in earlier write. */ | |
f2f90c63 | 6298 | if (flags.is_and && rws_sum[regno].written_by_and) |
9c808aad | 6299 | ; |
f2f90c63 RH |
6300 | else if (flags.is_or && rws_sum[regno].written_by_or) |
6301 | ; | |
89774469 | 6302 | else |
c65ebc55 | 6303 | need_barrier = 1; |
444a356a JJ |
6304 | if (!in_safe_group_barrier) |
6305 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6306 | break; |
6307 | ||
6308 | case 2: | |
6309 | /* The register has been unconditionally written already. We | |
6310 | need a barrier. */ | |
f2f90c63 RH |
6311 | if (flags.is_and && rws_sum[regno].written_by_and) |
6312 | ; | |
6313 | else if (flags.is_or && rws_sum[regno].written_by_or) | |
6314 | ; | |
6315 | else | |
6316 | need_barrier = 1; | |
444a356a JJ |
6317 | if (!in_safe_group_barrier) |
6318 | { | |
6319 | rws_sum[regno].written_by_and = flags.is_and; | |
6320 | rws_sum[regno].written_by_or = flags.is_or; | |
6321 | } | |
c65ebc55 JW |
6322 | break; |
6323 | ||
6324 | default: | |
e820471b | 6325 | gcc_unreachable (); |
c65ebc55 JW |
6326 | } |
6327 | } | |
6328 | else | |
6329 | { | |
6330 | if (flags.is_branch) | |
6331 | { | |
6332 | /* Branches have several RAW exceptions that allow to avoid | |
6333 | barriers. */ | |
6334 | ||
5527bf14 | 6335 | if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM) |
c65ebc55 JW |
6336 | /* RAW dependencies on branch regs are permissible as long |
6337 | as the writer is a non-branch instruction. Since we | |
6338 | never generate code that uses a branch register written | |
6339 | by a branch instruction, handling this case is | |
6340 | easy. */ | |
5527bf14 | 6341 | return 0; |
c65ebc55 JW |
6342 | |
6343 | if (REGNO_REG_CLASS (regno) == PR_REGS | |
6344 | && ! rws_sum[regno].written_by_fp) | |
6345 | /* The predicates of a branch are available within the | |
6346 | same insn group as long as the predicate was written by | |
ed168e45 | 6347 | something other than a floating-point instruction. */ |
c65ebc55 JW |
6348 | return 0; |
6349 | } | |
6350 | ||
f2f90c63 RH |
6351 | if (flags.is_and && rws_sum[regno].written_by_and) |
6352 | return 0; | |
6353 | if (flags.is_or && rws_sum[regno].written_by_or) | |
6354 | return 0; | |
6355 | ||
c65ebc55 JW |
6356 | switch (rws_sum[regno].write_count) |
6357 | { | |
6358 | case 0: | |
6359 | /* The register has not been written yet. */ | |
6360 | break; | |
6361 | ||
6362 | case 1: | |
89774469 SE |
6363 | /* The register has been written via a predicate, assume we |
6364 | need a barrier (don't check for complementary regs). */ | |
6365 | need_barrier = 1; | |
c65ebc55 JW |
6366 | break; |
6367 | ||
6368 | case 2: | |
6369 | /* The register has been unconditionally written already. We | |
6370 | need a barrier. */ | |
6371 | need_barrier = 1; | |
6372 | break; | |
6373 | ||
6374 | default: | |
e820471b | 6375 | gcc_unreachable (); |
c65ebc55 JW |
6376 | } |
6377 | } | |
6378 | ||
6379 | return need_barrier; | |
6380 | } | |
6381 | ||
97e242b0 | 6382 | static int |
9c808aad | 6383 | rws_access_reg (rtx reg, struct reg_flags flags, int pred) |
97e242b0 RH |
6384 | { |
6385 | int regno = REGNO (reg); | |
6386 | int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); | |
6387 | ||
6388 | if (n == 1) | |
6389 | return rws_access_regno (regno, flags, pred); | |
6390 | else | |
6391 | { | |
6392 | int need_barrier = 0; | |
6393 | while (--n >= 0) | |
6394 | need_barrier |= rws_access_regno (regno + n, flags, pred); | |
6395 | return need_barrier; | |
6396 | } | |
6397 | } | |
6398 | ||
112333d3 BS |
6399 | /* Examine X, which is a SET rtx, and update the flags, the predicate, and |
6400 | the condition, stored in *PFLAGS, *PPRED and *PCOND. */ | |
6401 | ||
6402 | static void | |
c1bc6ca8 | 6403 | update_set_flags (rtx x, struct reg_flags *pflags) |
112333d3 BS |
6404 | { |
6405 | rtx src = SET_SRC (x); | |
6406 | ||
112333d3 BS |
6407 | switch (GET_CODE (src)) |
6408 | { | |
6409 | case CALL: | |
6410 | return; | |
6411 | ||
6412 | case IF_THEN_ELSE: | |
048d0d36 | 6413 | /* There are four cases here: |
c8d3810f RH |
6414 | (1) The destination is (pc), in which case this is a branch, |
6415 | nothing here applies. | |
6416 | (2) The destination is ar.lc, in which case this is a | |
6417 | doloop_end_internal, | |
6418 | (3) The destination is an fp register, in which case this is | |
6419 | an fselect instruction. | |
048d0d36 MK |
6420 | (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case |
6421 | this is a check load. | |
c8d3810f RH |
6422 | In all cases, nothing we do in this function applies. */ |
6423 | return; | |
112333d3 BS |
6424 | |
6425 | default: | |
ec8e098d | 6426 | if (COMPARISON_P (src) |
c8d3810f | 6427 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0)))) |
112333d3 BS |
6428 | /* Set pflags->is_fp to 1 so that we know we're dealing |
6429 | with a floating point comparison when processing the | |
6430 | destination of the SET. */ | |
6431 | pflags->is_fp = 1; | |
6432 | ||
6433 | /* Discover if this is a parallel comparison. We only handle | |
6434 | and.orcm and or.andcm at present, since we must retain a | |
6435 | strict inverse on the predicate pair. */ | |
6436 | else if (GET_CODE (src) == AND) | |
6437 | pflags->is_and = 1; | |
6438 | else if (GET_CODE (src) == IOR) | |
6439 | pflags->is_or = 1; | |
6440 | ||
6441 | break; | |
6442 | } | |
6443 | } | |
6444 | ||
6445 | /* Subroutine of rtx_needs_barrier; this function determines whether the | |
6446 | source of a given SET rtx found in X needs a barrier. FLAGS and PRED | |
6447 | are as in rtx_needs_barrier. COND is an rtx that holds the condition | |
6448 | for this insn. */ | |
9c808aad | 6449 | |
112333d3 | 6450 | static int |
c1bc6ca8 | 6451 | set_src_needs_barrier (rtx x, struct reg_flags flags, int pred) |
112333d3 BS |
6452 | { |
6453 | int need_barrier = 0; | |
6454 | rtx dst; | |
6455 | rtx src = SET_SRC (x); | |
6456 | ||
6457 | if (GET_CODE (src) == CALL) | |
6458 | /* We don't need to worry about the result registers that | |
6459 | get written by subroutine call. */ | |
6460 | return rtx_needs_barrier (src, flags, pred); | |
6461 | else if (SET_DEST (x) == pc_rtx) | |
6462 | { | |
6463 | /* X is a conditional branch. */ | |
6464 | /* ??? This seems redundant, as the caller sets this bit for | |
6465 | all JUMP_INSNs. */ | |
048d0d36 MK |
6466 | if (!ia64_spec_check_src_p (src)) |
6467 | flags.is_branch = 1; | |
112333d3 BS |
6468 | return rtx_needs_barrier (src, flags, pred); |
6469 | } | |
6470 | ||
048d0d36 MK |
6471 | if (ia64_spec_check_src_p (src)) |
6472 | /* Avoid checking one register twice (in condition | |
6473 | and in 'then' section) for ldc pattern. */ | |
6474 | { | |
6475 | gcc_assert (REG_P (XEXP (src, 2))); | |
6476 | need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred); | |
6477 | ||
6478 | /* We process MEM below. */ | |
6479 | src = XEXP (src, 1); | |
6480 | } | |
6481 | ||
6482 | need_barrier |= rtx_needs_barrier (src, flags, pred); | |
112333d3 | 6483 | |
112333d3 BS |
6484 | dst = SET_DEST (x); |
6485 | if (GET_CODE (dst) == ZERO_EXTRACT) | |
6486 | { | |
6487 | need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred); | |
6488 | need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred); | |
112333d3 BS |
6489 | } |
6490 | return need_barrier; | |
6491 | } | |
6492 | ||
b38ba463 ZW |
6493 | /* Handle an access to rtx X of type FLAGS using predicate register |
6494 | PRED. Return 1 if this access creates a dependency with an earlier | |
6495 | instruction in the same group. */ | |
c65ebc55 JW |
6496 | |
6497 | static int | |
9c808aad | 6498 | rtx_needs_barrier (rtx x, struct reg_flags flags, int pred) |
c65ebc55 JW |
6499 | { |
6500 | int i, j; | |
6501 | int is_complemented = 0; | |
6502 | int need_barrier = 0; | |
6503 | const char *format_ptr; | |
6504 | struct reg_flags new_flags; | |
c1bc6ca8 | 6505 | rtx cond; |
c65ebc55 JW |
6506 | |
6507 | if (! x) | |
6508 | return 0; | |
6509 | ||
6510 | new_flags = flags; | |
6511 | ||
6512 | switch (GET_CODE (x)) | |
6513 | { | |
9c808aad | 6514 | case SET: |
c1bc6ca8 JW |
6515 | update_set_flags (x, &new_flags); |
6516 | need_barrier = set_src_needs_barrier (x, new_flags, pred); | |
112333d3 | 6517 | if (GET_CODE (SET_SRC (x)) != CALL) |
c65ebc55 | 6518 | { |
112333d3 BS |
6519 | new_flags.is_write = 1; |
6520 | need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred); | |
c65ebc55 | 6521 | } |
c65ebc55 JW |
6522 | break; |
6523 | ||
6524 | case CALL: | |
6525 | new_flags.is_write = 0; | |
97e242b0 | 6526 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
c65ebc55 JW |
6527 | |
6528 | /* Avoid multiple register writes, in case this is a pattern with | |
e820471b | 6529 | multiple CALL rtx. This avoids a failure in rws_access_reg. */ |
444a356a | 6530 | if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM)) |
c65ebc55 JW |
6531 | { |
6532 | new_flags.is_write = 1; | |
97e242b0 RH |
6533 | need_barrier |= rws_access_regno (REG_RP, new_flags, pred); |
6534 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred); | |
6535 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6536 | } |
6537 | break; | |
6538 | ||
e5bde68a RH |
6539 | case COND_EXEC: |
6540 | /* X is a predicated instruction. */ | |
6541 | ||
6542 | cond = COND_EXEC_TEST (x); | |
e820471b | 6543 | gcc_assert (!pred); |
e5bde68a RH |
6544 | need_barrier = rtx_needs_barrier (cond, flags, 0); |
6545 | ||
6546 | if (GET_CODE (cond) == EQ) | |
6547 | is_complemented = 1; | |
6548 | cond = XEXP (cond, 0); | |
e820471b | 6549 | gcc_assert (GET_CODE (cond) == REG |
c1bc6ca8 | 6550 | && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS); |
e5bde68a RH |
6551 | pred = REGNO (cond); |
6552 | if (is_complemented) | |
6553 | ++pred; | |
6554 | ||
6555 | need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred); | |
6556 | return need_barrier; | |
6557 | ||
c65ebc55 | 6558 | case CLOBBER: |
c65ebc55 | 6559 | case USE: |
c65ebc55 JW |
6560 | /* Clobber & use are for earlier compiler-phases only. */ |
6561 | break; | |
6562 | ||
6563 | case ASM_OPERANDS: | |
6564 | case ASM_INPUT: | |
6565 | /* We always emit stop bits for traditional asms. We emit stop bits | |
6566 | for volatile extended asms if TARGET_VOL_ASM_STOP is true. */ | |
6567 | if (GET_CODE (x) != ASM_OPERANDS | |
6568 | || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP)) | |
6569 | { | |
6570 | /* Avoid writing the register multiple times if we have multiple | |
e820471b | 6571 | asm outputs. This avoids a failure in rws_access_reg. */ |
444a356a | 6572 | if (! rws_insn_test (REG_VOLATILE)) |
c65ebc55 JW |
6573 | { |
6574 | new_flags.is_write = 1; | |
97e242b0 | 6575 | rws_access_regno (REG_VOLATILE, new_flags, pred); |
c65ebc55 JW |
6576 | } |
6577 | return 1; | |
6578 | } | |
6579 | ||
6580 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
1e5f1716 | 6581 | We cannot just fall through here since then we would be confused |
c65ebc55 JW |
6582 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate |
6583 | traditional asms unlike their normal usage. */ | |
6584 | ||
6585 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i) | |
6586 | if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred)) | |
6587 | need_barrier = 1; | |
6588 | break; | |
6589 | ||
6590 | case PARALLEL: | |
6591 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
112333d3 BS |
6592 | { |
6593 | rtx pat = XVECEXP (x, 0, i); | |
051d8245 | 6594 | switch (GET_CODE (pat)) |
112333d3 | 6595 | { |
051d8245 | 6596 | case SET: |
c1bc6ca8 JW |
6597 | update_set_flags (pat, &new_flags); |
6598 | need_barrier |= set_src_needs_barrier (pat, new_flags, pred); | |
051d8245 RH |
6599 | break; |
6600 | ||
6601 | case USE: | |
6602 | case CALL: | |
6603 | case ASM_OPERANDS: | |
6604 | need_barrier |= rtx_needs_barrier (pat, flags, pred); | |
6605 | break; | |
6606 | ||
6607 | case CLOBBER: | |
628162ea JJ |
6608 | if (REG_P (XEXP (pat, 0)) |
6609 | && extract_asm_operands (x) != NULL_RTX | |
6610 | && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM) | |
6611 | { | |
6612 | new_flags.is_write = 1; | |
6613 | need_barrier |= rtx_needs_barrier (XEXP (pat, 0), | |
6614 | new_flags, pred); | |
6615 | new_flags = flags; | |
6616 | } | |
6617 | break; | |
6618 | ||
051d8245 RH |
6619 | case RETURN: |
6620 | break; | |
6621 | ||
6622 | default: | |
6623 | gcc_unreachable (); | |
112333d3 | 6624 | } |
112333d3 BS |
6625 | } |
6626 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
6627 | { | |
6628 | rtx pat = XVECEXP (x, 0, i); | |
6629 | if (GET_CODE (pat) == SET) | |
6630 | { | |
6631 | if (GET_CODE (SET_SRC (pat)) != CALL) | |
6632 | { | |
6633 | new_flags.is_write = 1; | |
6634 | need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags, | |
6635 | pred); | |
6636 | } | |
6637 | } | |
339cb12e | 6638 | else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN) |
112333d3 BS |
6639 | need_barrier |= rtx_needs_barrier (pat, flags, pred); |
6640 | } | |
c65ebc55 JW |
6641 | break; |
6642 | ||
6643 | case SUBREG: | |
077bc924 JM |
6644 | need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred); |
6645 | break; | |
c65ebc55 | 6646 | case REG: |
870f9ec0 RH |
6647 | if (REGNO (x) == AR_UNAT_REGNUM) |
6648 | { | |
6649 | for (i = 0; i < 64; ++i) | |
6650 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred); | |
6651 | } | |
6652 | else | |
6653 | need_barrier = rws_access_reg (x, flags, pred); | |
c65ebc55 JW |
6654 | break; |
6655 | ||
6656 | case MEM: | |
6657 | /* Find the regs used in memory address computation. */ | |
6658 | new_flags.is_write = 0; | |
6659 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6660 | break; | |
6661 | ||
051d8245 | 6662 | case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR: |
c65ebc55 JW |
6663 | case SYMBOL_REF: case LABEL_REF: case CONST: |
6664 | break; | |
6665 | ||
6666 | /* Operators with side-effects. */ | |
6667 | case POST_INC: case POST_DEC: | |
e820471b | 6668 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
c65ebc55 JW |
6669 | |
6670 | new_flags.is_write = 0; | |
97e242b0 | 6671 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 | 6672 | new_flags.is_write = 1; |
97e242b0 | 6673 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6674 | break; |
6675 | ||
6676 | case POST_MODIFY: | |
e820471b | 6677 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
4b983fdc RH |
6678 | |
6679 | new_flags.is_write = 0; | |
97e242b0 | 6680 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6681 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); |
6682 | new_flags.is_write = 1; | |
97e242b0 | 6683 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 JW |
6684 | break; |
6685 | ||
6686 | /* Handle common unary and binary ops for efficiency. */ | |
6687 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
6688 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
6689 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
6690 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
6691 | case NE: case EQ: case GE: case GT: case LE: | |
6692 | case LT: case GEU: case GTU: case LEU: case LTU: | |
6693 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6694 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); | |
6695 | break; | |
6696 | ||
6697 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
6698 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
6699 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
c407570a | 6700 | case SQRT: case FFS: case POPCOUNT: |
c65ebc55 JW |
6701 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6702 | break; | |
6703 | ||
051d8245 RH |
6704 | case VEC_SELECT: |
6705 | /* VEC_SELECT's second argument is a PARALLEL with integers that | |
6706 | describe the elements selected. On ia64, those integers are | |
6707 | always constants. Avoid walking the PARALLEL so that we don't | |
e820471b | 6708 | get confused with "normal" parallels and then die. */ |
051d8245 RH |
6709 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6710 | break; | |
6711 | ||
c65ebc55 JW |
6712 | case UNSPEC: |
6713 | switch (XINT (x, 1)) | |
6714 | { | |
7b6e506e RH |
6715 | case UNSPEC_LTOFF_DTPMOD: |
6716 | case UNSPEC_LTOFF_DTPREL: | |
6717 | case UNSPEC_DTPREL: | |
6718 | case UNSPEC_LTOFF_TPREL: | |
6719 | case UNSPEC_TPREL: | |
6720 | case UNSPEC_PRED_REL_MUTEX: | |
6721 | case UNSPEC_PIC_CALL: | |
6722 | case UNSPEC_MF: | |
6723 | case UNSPEC_FETCHADD_ACQ: | |
28875d67 | 6724 | case UNSPEC_FETCHADD_REL: |
7b6e506e RH |
6725 | case UNSPEC_BSP_VALUE: |
6726 | case UNSPEC_FLUSHRS: | |
6727 | case UNSPEC_BUNDLE_SELECTOR: | |
6728 | break; | |
6729 | ||
086c0f96 RH |
6730 | case UNSPEC_GR_SPILL: |
6731 | case UNSPEC_GR_RESTORE: | |
870f9ec0 RH |
6732 | { |
6733 | HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); | |
6734 | HOST_WIDE_INT bit = (offset >> 3) & 63; | |
6735 | ||
6736 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
83338d15 | 6737 | new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL); |
870f9ec0 RH |
6738 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit, |
6739 | new_flags, pred); | |
6740 | break; | |
6741 | } | |
9c808aad | 6742 | |
086c0f96 RH |
6743 | case UNSPEC_FR_SPILL: |
6744 | case UNSPEC_FR_RESTORE: | |
c407570a | 6745 | case UNSPEC_GETF_EXP: |
b38ba463 | 6746 | case UNSPEC_SETF_EXP: |
086c0f96 | 6747 | case UNSPEC_ADDP4: |
b38ba463 | 6748 | case UNSPEC_FR_SQRT_RECIP_APPROX: |
07acc7b3 | 6749 | case UNSPEC_FR_SQRT_RECIP_APPROX_RES: |
048d0d36 MK |
6750 | case UNSPEC_LDA: |
6751 | case UNSPEC_LDS: | |
388092d5 | 6752 | case UNSPEC_LDS_A: |
048d0d36 MK |
6753 | case UNSPEC_LDSA: |
6754 | case UNSPEC_CHKACLR: | |
6755 | case UNSPEC_CHKS: | |
6dd12198 SE |
6756 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6757 | break; | |
6758 | ||
086c0f96 | 6759 | case UNSPEC_FR_RECIP_APPROX: |
f526a3c8 | 6760 | case UNSPEC_SHRP: |
046625fa | 6761 | case UNSPEC_COPYSIGN: |
1def9c3f | 6762 | case UNSPEC_FR_RECIP_APPROX_RES: |
655f2eb9 RH |
6763 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6764 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); | |
6765 | break; | |
6766 | ||
086c0f96 | 6767 | case UNSPEC_CMPXCHG_ACQ: |
28875d67 | 6768 | case UNSPEC_CMPXCHG_REL: |
0551c32d RH |
6769 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); |
6770 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); | |
6771 | break; | |
6772 | ||
c65ebc55 | 6773 | default: |
e820471b | 6774 | gcc_unreachable (); |
c65ebc55 JW |
6775 | } |
6776 | break; | |
6777 | ||
6778 | case UNSPEC_VOLATILE: | |
6779 | switch (XINT (x, 1)) | |
6780 | { | |
086c0f96 | 6781 | case UNSPECV_ALLOC: |
25250265 JW |
6782 | /* Alloc must always be the first instruction of a group. |
6783 | We force this by always returning true. */ | |
6784 | /* ??? We might get better scheduling if we explicitly check for | |
6785 | input/local/output register dependencies, and modify the | |
6786 | scheduler so that alloc is always reordered to the start of | |
6787 | the current group. We could then eliminate all of the | |
6788 | first_instruction code. */ | |
6789 | rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6790 | |
6791 | new_flags.is_write = 1; | |
25250265 JW |
6792 | rws_access_regno (REG_AR_CFM, new_flags, pred); |
6793 | return 1; | |
c65ebc55 | 6794 | |
086c0f96 | 6795 | case UNSPECV_SET_BSP: |
7b84aac0 | 6796 | case UNSPECV_PROBE_STACK_RANGE: |
3b572406 RH |
6797 | need_barrier = 1; |
6798 | break; | |
6799 | ||
086c0f96 RH |
6800 | case UNSPECV_BLOCKAGE: |
6801 | case UNSPECV_INSN_GROUP_BARRIER: | |
6802 | case UNSPECV_BREAK: | |
6803 | case UNSPECV_PSAC_ALL: | |
6804 | case UNSPECV_PSAC_NORMAL: | |
3b572406 | 6805 | return 0; |
0c96007e | 6806 | |
7b84aac0 EB |
6807 | case UNSPECV_PROBE_STACK_ADDRESS: |
6808 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
6809 | break; | |
6810 | ||
c65ebc55 | 6811 | default: |
e820471b | 6812 | gcc_unreachable (); |
c65ebc55 JW |
6813 | } |
6814 | break; | |
6815 | ||
6816 | case RETURN: | |
6817 | new_flags.is_write = 0; | |
97e242b0 RH |
6818 | need_barrier = rws_access_regno (REG_RP, flags, pred); |
6819 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6820 | |
6821 | new_flags.is_write = 1; | |
97e242b0 RH |
6822 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
6823 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6824 | break; |
6825 | ||
6826 | default: | |
6827 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
6828 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6829 | switch (format_ptr[i]) | |
6830 | { | |
6831 | case '0': /* unused field */ | |
6832 | case 'i': /* integer */ | |
6833 | case 'n': /* note */ | |
6834 | case 'w': /* wide integer */ | |
6835 | case 's': /* pointer to string */ | |
6836 | case 'S': /* optional pointer to string */ | |
6837 | break; | |
6838 | ||
6839 | case 'e': | |
6840 | if (rtx_needs_barrier (XEXP (x, i), flags, pred)) | |
6841 | need_barrier = 1; | |
6842 | break; | |
6843 | ||
6844 | case 'E': | |
6845 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
6846 | if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred)) | |
6847 | need_barrier = 1; | |
6848 | break; | |
6849 | ||
6850 | default: | |
e820471b | 6851 | gcc_unreachable (); |
c65ebc55 | 6852 | } |
2ed4af6f | 6853 | break; |
c65ebc55 JW |
6854 | } |
6855 | return need_barrier; | |
6856 | } | |
6857 | ||
c1bc6ca8 | 6858 | /* Clear out the state for group_barrier_needed at the start of a |
2130b7fb BS |
6859 | sequence of insns. */ |
6860 | ||
6861 | static void | |
9c808aad | 6862 | init_insn_group_barriers (void) |
2130b7fb BS |
6863 | { |
6864 | memset (rws_sum, 0, sizeof (rws_sum)); | |
25250265 | 6865 | first_instruction = 1; |
2130b7fb BS |
6866 | } |
6867 | ||
c1bc6ca8 JW |
6868 | /* Given the current state, determine whether a group barrier (a stop bit) is |
6869 | necessary before INSN. Return nonzero if so. This modifies the state to | |
6870 | include the effects of INSN as a side-effect. */ | |
2130b7fb BS |
6871 | |
6872 | static int | |
647d790d | 6873 | group_barrier_needed (rtx_insn *insn) |
2130b7fb BS |
6874 | { |
6875 | rtx pat; | |
6876 | int need_barrier = 0; | |
6877 | struct reg_flags flags; | |
6878 | ||
6879 | memset (&flags, 0, sizeof (flags)); | |
6880 | switch (GET_CODE (insn)) | |
6881 | { | |
6882 | case NOTE: | |
b5b8b0ac | 6883 | case DEBUG_INSN: |
2130b7fb BS |
6884 | break; |
6885 | ||
6886 | case BARRIER: | |
6887 | /* A barrier doesn't imply an instruction group boundary. */ | |
6888 | break; | |
6889 | ||
6890 | case CODE_LABEL: | |
6891 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6892 | return 1; | |
6893 | ||
6894 | case CALL_INSN: | |
6895 | flags.is_branch = 1; | |
6896 | flags.is_sibcall = SIBLING_CALL_P (insn); | |
6897 | memset (rws_insn, 0, sizeof (rws_insn)); | |
f12f25a7 RH |
6898 | |
6899 | /* Don't bundle a call following another call. */ | |
b64925dc | 6900 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6901 | { |
6902 | need_barrier = 1; | |
6903 | break; | |
6904 | } | |
6905 | ||
2130b7fb BS |
6906 | need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0); |
6907 | break; | |
6908 | ||
6909 | case JUMP_INSN: | |
048d0d36 MK |
6910 | if (!ia64_spec_check_p (insn)) |
6911 | flags.is_branch = 1; | |
f12f25a7 RH |
6912 | |
6913 | /* Don't bundle a jump following a call. */ | |
b64925dc | 6914 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6915 | { |
6916 | need_barrier = 1; | |
6917 | break; | |
6918 | } | |
5efb1046 | 6919 | /* FALLTHRU */ |
2130b7fb BS |
6920 | |
6921 | case INSN: | |
6922 | if (GET_CODE (PATTERN (insn)) == USE | |
6923 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
6924 | /* Don't care about USE and CLOBBER "insns"---those are used to | |
6925 | indicate to the optimizer that it shouldn't get rid of | |
6926 | certain operations. */ | |
6927 | break; | |
6928 | ||
6929 | pat = PATTERN (insn); | |
6930 | ||
6931 | /* Ug. Hack hacks hacked elsewhere. */ | |
6932 | switch (recog_memoized (insn)) | |
6933 | { | |
6934 | /* We play dependency tricks with the epilogue in order | |
6935 | to get proper schedules. Undo this for dv analysis. */ | |
6936 | case CODE_FOR_epilogue_deallocate_stack: | |
bdbe5b8d | 6937 | case CODE_FOR_prologue_allocate_stack: |
2130b7fb BS |
6938 | pat = XVECEXP (pat, 0, 0); |
6939 | break; | |
6940 | ||
6941 | /* The pattern we use for br.cloop confuses the code above. | |
6942 | The second element of the vector is representative. */ | |
6943 | case CODE_FOR_doloop_end_internal: | |
6944 | pat = XVECEXP (pat, 0, 1); | |
6945 | break; | |
6946 | ||
6947 | /* Doesn't generate code. */ | |
6948 | case CODE_FOR_pred_rel_mutex: | |
d0e82870 | 6949 | case CODE_FOR_prologue_use: |
2130b7fb BS |
6950 | return 0; |
6951 | ||
6952 | default: | |
6953 | break; | |
6954 | } | |
6955 | ||
6956 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6957 | need_barrier = rtx_needs_barrier (pat, flags, 0); | |
6958 | ||
6959 | /* Check to see if the previous instruction was a volatile | |
6960 | asm. */ | |
6961 | if (! need_barrier) | |
6962 | need_barrier = rws_access_regno (REG_VOLATILE, flags, 0); | |
388092d5 | 6963 | |
2130b7fb BS |
6964 | break; |
6965 | ||
6966 | default: | |
e820471b | 6967 | gcc_unreachable (); |
2130b7fb | 6968 | } |
25250265 | 6969 | |
7b84aac0 | 6970 | if (first_instruction && important_for_bundling_p (insn)) |
25250265 JW |
6971 | { |
6972 | need_barrier = 0; | |
6973 | first_instruction = 0; | |
6974 | } | |
6975 | ||
2130b7fb BS |
6976 | return need_barrier; |
6977 | } | |
6978 | ||
c1bc6ca8 | 6979 | /* Like group_barrier_needed, but do not clobber the current state. */ |
2130b7fb BS |
6980 | |
6981 | static int | |
647d790d | 6982 | safe_group_barrier_needed (rtx_insn *insn) |
2130b7fb | 6983 | { |
25250265 | 6984 | int saved_first_instruction; |
2130b7fb | 6985 | int t; |
25250265 | 6986 | |
25250265 | 6987 | saved_first_instruction = first_instruction; |
444a356a | 6988 | in_safe_group_barrier = 1; |
25250265 | 6989 | |
c1bc6ca8 | 6990 | t = group_barrier_needed (insn); |
25250265 | 6991 | |
25250265 | 6992 | first_instruction = saved_first_instruction; |
444a356a | 6993 | in_safe_group_barrier = 0; |
25250265 | 6994 | |
2130b7fb BS |
6995 | return t; |
6996 | } | |
6997 | ||
18dbd950 RS |
6998 | /* Scan the current function and insert stop bits as necessary to |
6999 | eliminate dependencies. This function assumes that a final | |
7000 | instruction scheduling pass has been run which has already | |
7001 | inserted most of the necessary stop bits. This function only | |
7002 | inserts new ones at basic block boundaries, since these are | |
7003 | invisible to the scheduler. */ | |
2130b7fb BS |
7004 | |
7005 | static void | |
9c808aad | 7006 | emit_insn_group_barriers (FILE *dump) |
2130b7fb | 7007 | { |
dd3d2b35 DM |
7008 | rtx_insn *insn; |
7009 | rtx_insn *last_label = 0; | |
2130b7fb BS |
7010 | int insns_since_last_label = 0; |
7011 | ||
7012 | init_insn_group_barriers (); | |
7013 | ||
18dbd950 | 7014 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2130b7fb | 7015 | { |
b64925dc | 7016 | if (LABEL_P (insn)) |
2130b7fb BS |
7017 | { |
7018 | if (insns_since_last_label) | |
7019 | last_label = insn; | |
7020 | insns_since_last_label = 0; | |
7021 | } | |
b64925dc | 7022 | else if (NOTE_P (insn) |
a38e7aa5 | 7023 | && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK) |
2130b7fb BS |
7024 | { |
7025 | if (insns_since_last_label) | |
7026 | last_label = insn; | |
7027 | insns_since_last_label = 0; | |
7028 | } | |
b64925dc | 7029 | else if (NONJUMP_INSN_P (insn) |
2130b7fb | 7030 | && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE |
086c0f96 | 7031 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) |
2130b7fb BS |
7032 | { |
7033 | init_insn_group_barriers (); | |
7034 | last_label = 0; | |
7035 | } | |
b5b8b0ac | 7036 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb BS |
7037 | { |
7038 | insns_since_last_label = 1; | |
7039 | ||
c1bc6ca8 | 7040 | if (group_barrier_needed (insn)) |
2130b7fb BS |
7041 | { |
7042 | if (last_label) | |
7043 | { | |
7044 | if (dump) | |
7045 | fprintf (dump, "Emitting stop before label %d\n", | |
7046 | INSN_UID (last_label)); | |
7047 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label); | |
7048 | insn = last_label; | |
112333d3 BS |
7049 | |
7050 | init_insn_group_barriers (); | |
7051 | last_label = 0; | |
2130b7fb | 7052 | } |
2130b7fb BS |
7053 | } |
7054 | } | |
7055 | } | |
7056 | } | |
f4d578da BS |
7057 | |
7058 | /* Like emit_insn_group_barriers, but run if no final scheduling pass was run. | |
7059 | This function has to emit all necessary group barriers. */ | |
7060 | ||
7061 | static void | |
9c808aad | 7062 | emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
f4d578da | 7063 | { |
dd3d2b35 | 7064 | rtx_insn *insn; |
f4d578da BS |
7065 | |
7066 | init_insn_group_barriers (); | |
7067 | ||
18dbd950 | 7068 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f4d578da | 7069 | { |
b64925dc | 7070 | if (BARRIER_P (insn)) |
bd7b9a0f | 7071 | { |
dd3d2b35 | 7072 | rtx_insn *last = prev_active_insn (insn); |
bd7b9a0f RH |
7073 | |
7074 | if (! last) | |
7075 | continue; | |
34f0d87a | 7076 | if (JUMP_TABLE_DATA_P (last)) |
bd7b9a0f RH |
7077 | last = prev_active_insn (last); |
7078 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
7079 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
7080 | ||
7081 | init_insn_group_barriers (); | |
7082 | } | |
b5b8b0ac | 7083 | else if (NONDEBUG_INSN_P (insn)) |
f4d578da | 7084 | { |
bd7b9a0f RH |
7085 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
7086 | init_insn_group_barriers (); | |
c1bc6ca8 | 7087 | else if (group_barrier_needed (insn)) |
f4d578da BS |
7088 | { |
7089 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); | |
7090 | init_insn_group_barriers (); | |
c1bc6ca8 | 7091 | group_barrier_needed (insn); |
f4d578da BS |
7092 | } |
7093 | } | |
7094 | } | |
7095 | } | |
30028c85 | 7096 | |
2130b7fb | 7097 | \f |
2130b7fb | 7098 | |
30028c85 | 7099 | /* Instruction scheduling support. */ |
2130b7fb BS |
7100 | |
7101 | #define NR_BUNDLES 10 | |
7102 | ||
30028c85 | 7103 | /* A list of names of all available bundles. */ |
2130b7fb | 7104 | |
30028c85 | 7105 | static const char *bundle_name [NR_BUNDLES] = |
2130b7fb | 7106 | { |
30028c85 VM |
7107 | ".mii", |
7108 | ".mmi", | |
7109 | ".mfi", | |
7110 | ".mmf", | |
2130b7fb | 7111 | #if NR_BUNDLES == 10 |
30028c85 VM |
7112 | ".bbb", |
7113 | ".mbb", | |
2130b7fb | 7114 | #endif |
30028c85 VM |
7115 | ".mib", |
7116 | ".mmb", | |
7117 | ".mfb", | |
7118 | ".mlx" | |
2130b7fb BS |
7119 | }; |
7120 | ||
30028c85 | 7121 | /* Nonzero if we should insert stop bits into the schedule. */ |
2130b7fb | 7122 | |
30028c85 | 7123 | int ia64_final_schedule = 0; |
2130b7fb | 7124 | |
35fd3193 | 7125 | /* Codes of the corresponding queried units: */ |
2130b7fb | 7126 | |
30028c85 VM |
7127 | static int _0mii_, _0mmi_, _0mfi_, _0mmf_; |
7128 | static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_; | |
2130b7fb | 7129 | |
30028c85 VM |
7130 | static int _1mii_, _1mmi_, _1mfi_, _1mmf_; |
7131 | static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_; | |
2130b7fb | 7132 | |
30028c85 VM |
7133 | static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6; |
7134 | ||
7135 | /* The following variable value is an insn group barrier. */ | |
7136 | ||
dd3d2b35 | 7137 | static rtx_insn *dfa_stop_insn; |
30028c85 VM |
7138 | |
7139 | /* The following variable value is the last issued insn. */ | |
7140 | ||
b32d5189 | 7141 | static rtx_insn *last_scheduled_insn; |
30028c85 | 7142 | |
30028c85 VM |
7143 | /* The following variable value is pointer to a DFA state used as |
7144 | temporary variable. */ | |
7145 | ||
7146 | static state_t temp_dfa_state = NULL; | |
7147 | ||
7148 | /* The following variable value is DFA state after issuing the last | |
7149 | insn. */ | |
7150 | ||
7151 | static state_t prev_cycle_state = NULL; | |
7152 | ||
7153 | /* The following array element values are TRUE if the corresponding | |
9e4f94de | 7154 | insn requires to add stop bits before it. */ |
30028c85 | 7155 | |
048d0d36 MK |
7156 | static char *stops_p = NULL; |
7157 | ||
30028c85 VM |
7158 | /* The following variable is used to set up the mentioned above array. */ |
7159 | ||
7160 | static int stop_before_p = 0; | |
7161 | ||
7162 | /* The following variable value is length of the arrays `clocks' and | |
7163 | `add_cycles'. */ | |
7164 | ||
7165 | static int clocks_length; | |
7166 | ||
048d0d36 MK |
7167 | /* The following variable value is number of data speculations in progress. */ |
7168 | static int pending_data_specs = 0; | |
7169 | ||
388092d5 AB |
7170 | /* Number of memory references on current and three future processor cycles. */ |
7171 | static char mem_ops_in_group[4]; | |
7172 | ||
7173 | /* Number of current processor cycle (from scheduler's point of view). */ | |
7174 | static int current_cycle; | |
7175 | ||
647d790d | 7176 | static rtx ia64_single_set (rtx_insn *); |
9c808aad | 7177 | static void ia64_emit_insn_before (rtx, rtx); |
2130b7fb BS |
7178 | |
7179 | /* Map a bundle number to its pseudo-op. */ | |
7180 | ||
7181 | const char * | |
9c808aad | 7182 | get_bundle_name (int b) |
2130b7fb | 7183 | { |
30028c85 | 7184 | return bundle_name[b]; |
2130b7fb BS |
7185 | } |
7186 | ||
2130b7fb BS |
7187 | |
7188 | /* Return the maximum number of instructions a cpu can issue. */ | |
7189 | ||
c237e94a | 7190 | static int |
9c808aad | 7191 | ia64_issue_rate (void) |
2130b7fb BS |
7192 | { |
7193 | return 6; | |
7194 | } | |
7195 | ||
7196 | /* Helper function - like single_set, but look inside COND_EXEC. */ | |
7197 | ||
7198 | static rtx | |
647d790d | 7199 | ia64_single_set (rtx_insn *insn) |
2130b7fb | 7200 | { |
30fa7e33 | 7201 | rtx x = PATTERN (insn), ret; |
2130b7fb BS |
7202 | if (GET_CODE (x) == COND_EXEC) |
7203 | x = COND_EXEC_CODE (x); | |
7204 | if (GET_CODE (x) == SET) | |
7205 | return x; | |
bdbe5b8d RH |
7206 | |
7207 | /* Special case here prologue_allocate_stack and epilogue_deallocate_stack. | |
7208 | Although they are not classical single set, the second set is there just | |
7209 | to protect it from moving past FP-relative stack accesses. */ | |
7210 | switch (recog_memoized (insn)) | |
30fa7e33 | 7211 | { |
bdbe5b8d | 7212 | case CODE_FOR_prologue_allocate_stack: |
9eb8c09f | 7213 | case CODE_FOR_prologue_allocate_stack_pr: |
bdbe5b8d | 7214 | case CODE_FOR_epilogue_deallocate_stack: |
9eb8c09f | 7215 | case CODE_FOR_epilogue_deallocate_stack_pr: |
bdbe5b8d RH |
7216 | ret = XVECEXP (x, 0, 0); |
7217 | break; | |
7218 | ||
7219 | default: | |
7220 | ret = single_set_2 (insn, x); | |
7221 | break; | |
30fa7e33 | 7222 | } |
bdbe5b8d | 7223 | |
30fa7e33 | 7224 | return ret; |
2130b7fb BS |
7225 | } |
7226 | ||
388092d5 AB |
7227 | /* Adjust the cost of a scheduling dependency. |
7228 | Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN. | |
7229 | COST is the current cost, DW is dependency weakness. */ | |
c237e94a | 7230 | static int |
ac44248e DM |
7231 | ia64_adjust_cost_2 (rtx_insn *insn, int dep_type1, rtx_insn *dep_insn, |
7232 | int cost, dw_t dw) | |
2130b7fb | 7233 | { |
388092d5 | 7234 | enum reg_note dep_type = (enum reg_note) dep_type1; |
2130b7fb BS |
7235 | enum attr_itanium_class dep_class; |
7236 | enum attr_itanium_class insn_class; | |
2130b7fb | 7237 | |
2130b7fb | 7238 | insn_class = ia64_safe_itanium_class (insn); |
30028c85 | 7239 | dep_class = ia64_safe_itanium_class (dep_insn); |
388092d5 AB |
7240 | |
7241 | /* Treat true memory dependencies separately. Ignore apparent true | |
7242 | dependence between store and call (call has a MEM inside a SYMBOL_REF). */ | |
7243 | if (dep_type == REG_DEP_TRUE | |
7244 | && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF) | |
7245 | && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL)) | |
7246 | return 0; | |
7247 | ||
7248 | if (dw == MIN_DEP_WEAK) | |
7249 | /* Store and load are likely to alias, use higher cost to avoid stall. */ | |
7250 | return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST); | |
7251 | else if (dw > MIN_DEP_WEAK) | |
7252 | { | |
7253 | /* Store and load are less likely to alias. */ | |
7254 | if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF) | |
7255 | /* Assume there will be no cache conflict for floating-point data. | |
7256 | For integer data, L1 conflict penalty is huge (17 cycles), so we | |
7257 | never assume it will not cause a conflict. */ | |
7258 | return 0; | |
7259 | else | |
7260 | return cost; | |
7261 | } | |
7262 | ||
7263 | if (dep_type != REG_DEP_OUTPUT) | |
7264 | return cost; | |
7265 | ||
30028c85 VM |
7266 | if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF |
7267 | || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF) | |
2130b7fb BS |
7268 | return 0; |
7269 | ||
2130b7fb BS |
7270 | return cost; |
7271 | } | |
7272 | ||
14d118d6 DM |
7273 | /* Like emit_insn_before, but skip cycle_display notes. |
7274 | ??? When cycle display notes are implemented, update this. */ | |
7275 | ||
7276 | static void | |
9c808aad | 7277 | ia64_emit_insn_before (rtx insn, rtx before) |
14d118d6 DM |
7278 | { |
7279 | emit_insn_before (insn, before); | |
7280 | } | |
7281 | ||
30028c85 VM |
7282 | /* The following function marks insns who produce addresses for load |
7283 | and store insns. Such insns will be placed into M slots because it | |
7284 | decrease latency time for Itanium1 (see function | |
7285 | `ia64_produce_address_p' and the DFA descriptions). */ | |
2130b7fb BS |
7286 | |
7287 | static void | |
ce1ce33a | 7288 | ia64_dependencies_evaluation_hook (rtx_insn *head, rtx_insn *tail) |
2130b7fb | 7289 | { |
ce1ce33a | 7290 | rtx_insn *insn, *next, *next_tail; |
9c808aad | 7291 | |
f12b785d RH |
7292 | /* Before reload, which_alternative is not set, which means that |
7293 | ia64_safe_itanium_class will produce wrong results for (at least) | |
7294 | move instructions. */ | |
7295 | if (!reload_completed) | |
7296 | return; | |
7297 | ||
30028c85 VM |
7298 | next_tail = NEXT_INSN (tail); |
7299 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7300 | if (INSN_P (insn)) | |
7301 | insn->call = 0; | |
7302 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7303 | if (INSN_P (insn) | |
7304 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU) | |
7305 | { | |
e2f6ff94 MK |
7306 | sd_iterator_def sd_it; |
7307 | dep_t dep; | |
7308 | bool has_mem_op_consumer_p = false; | |
b198261f | 7309 | |
e2f6ff94 | 7310 | FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) |
30028c85 | 7311 | { |
a71aef0b JB |
7312 | enum attr_itanium_class c; |
7313 | ||
e2f6ff94 | 7314 | if (DEP_TYPE (dep) != REG_DEP_TRUE) |
f12b785d | 7315 | continue; |
b198261f | 7316 | |
e2f6ff94 | 7317 | next = DEP_CON (dep); |
a71aef0b JB |
7318 | c = ia64_safe_itanium_class (next); |
7319 | if ((c == ITANIUM_CLASS_ST | |
7320 | || c == ITANIUM_CLASS_STF) | |
30028c85 | 7321 | && ia64_st_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7322 | { |
7323 | has_mem_op_consumer_p = true; | |
7324 | break; | |
7325 | } | |
a71aef0b JB |
7326 | else if ((c == ITANIUM_CLASS_LD |
7327 | || c == ITANIUM_CLASS_FLD | |
7328 | || c == ITANIUM_CLASS_FLDP) | |
30028c85 | 7329 | && ia64_ld_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7330 | { |
7331 | has_mem_op_consumer_p = true; | |
7332 | break; | |
7333 | } | |
30028c85 | 7334 | } |
e2f6ff94 MK |
7335 | |
7336 | insn->call = has_mem_op_consumer_p; | |
30028c85 VM |
7337 | } |
7338 | } | |
2130b7fb | 7339 | |
30028c85 | 7340 | /* We're beginning a new block. Initialize data structures as necessary. */ |
2130b7fb | 7341 | |
30028c85 | 7342 | static void |
9c808aad AJ |
7343 | ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
7344 | int sched_verbose ATTRIBUTE_UNUSED, | |
7345 | int max_ready ATTRIBUTE_UNUSED) | |
30028c85 VM |
7346 | { |
7347 | #ifdef ENABLE_CHECKING | |
b32d5189 | 7348 | rtx_insn *insn; |
9c808aad | 7349 | |
388092d5 | 7350 | if (!sel_sched_p () && reload_completed) |
30028c85 VM |
7351 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
7352 | insn != current_sched_info->next_tail; | |
7353 | insn = NEXT_INSN (insn)) | |
e820471b | 7354 | gcc_assert (!SCHED_GROUP_P (insn)); |
30028c85 | 7355 | #endif |
b32d5189 | 7356 | last_scheduled_insn = NULL; |
30028c85 | 7357 | init_insn_group_barriers (); |
388092d5 AB |
7358 | |
7359 | current_cycle = 0; | |
7360 | memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
2130b7fb BS |
7361 | } |
7362 | ||
048d0d36 MK |
7363 | /* We're beginning a scheduling pass. Check assertion. */ |
7364 | ||
7365 | static void | |
7366 | ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, | |
7367 | int sched_verbose ATTRIBUTE_UNUSED, | |
7368 | int max_ready ATTRIBUTE_UNUSED) | |
7369 | { | |
388092d5 | 7370 | gcc_assert (pending_data_specs == 0); |
048d0d36 MK |
7371 | } |
7372 | ||
7373 | /* Scheduling pass is now finished. Free/reset static variable. */ | |
7374 | static void | |
7375 | ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
7376 | int sched_verbose ATTRIBUTE_UNUSED) | |
7377 | { | |
388092d5 AB |
7378 | gcc_assert (pending_data_specs == 0); |
7379 | } | |
7380 | ||
7381 | /* Return TRUE if INSN is a load (either normal or speculative, but not a | |
7382 | speculation check), FALSE otherwise. */ | |
7383 | static bool | |
647d790d | 7384 | is_load_p (rtx_insn *insn) |
388092d5 AB |
7385 | { |
7386 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7387 | ||
7388 | return | |
7389 | ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD) | |
7390 | && get_attr_check_load (insn) == CHECK_LOAD_NO); | |
7391 | } | |
7392 | ||
7393 | /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array | |
7394 | (taking account for 3-cycle cache reference postponing for stores: Intel | |
7395 | Itanium 2 Reference Manual for Software Development and Optimization, | |
7396 | 6.7.3.1). */ | |
7397 | static void | |
647d790d | 7398 | record_memory_reference (rtx_insn *insn) |
388092d5 AB |
7399 | { |
7400 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7401 | ||
7402 | switch (insn_class) { | |
7403 | case ITANIUM_CLASS_FLD: | |
7404 | case ITANIUM_CLASS_LD: | |
7405 | mem_ops_in_group[current_cycle % 4]++; | |
7406 | break; | |
7407 | case ITANIUM_CLASS_STF: | |
7408 | case ITANIUM_CLASS_ST: | |
7409 | mem_ops_in_group[(current_cycle + 3) % 4]++; | |
7410 | break; | |
7411 | default:; | |
7412 | } | |
048d0d36 MK |
7413 | } |
7414 | ||
30028c85 VM |
7415 | /* We are about to being issuing insns for this clock cycle. |
7416 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7417 | |
30028c85 | 7418 | static int |
ce1ce33a | 7419 | ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, |
388092d5 | 7420 | int *pn_ready, int clock_var, |
9c808aad | 7421 | int reorder_type) |
2130b7fb | 7422 | { |
30028c85 VM |
7423 | int n_asms; |
7424 | int n_ready = *pn_ready; | |
ce1ce33a DM |
7425 | rtx_insn **e_ready = ready + n_ready; |
7426 | rtx_insn **insnp; | |
2130b7fb | 7427 | |
30028c85 VM |
7428 | if (sched_verbose) |
7429 | fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type); | |
2130b7fb | 7430 | |
30028c85 | 7431 | if (reorder_type == 0) |
2130b7fb | 7432 | { |
30028c85 VM |
7433 | /* First, move all USEs, CLOBBERs and other crud out of the way. */ |
7434 | n_asms = 0; | |
7435 | for (insnp = ready; insnp < e_ready; insnp++) | |
7436 | if (insnp < e_ready) | |
7437 | { | |
ce1ce33a | 7438 | rtx_insn *insn = *insnp; |
30028c85 VM |
7439 | enum attr_type t = ia64_safe_type (insn); |
7440 | if (t == TYPE_UNKNOWN) | |
7441 | { | |
7442 | if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
7443 | || asm_noperands (PATTERN (insn)) >= 0) | |
7444 | { | |
ce1ce33a | 7445 | rtx_insn *lowest = ready[n_asms]; |
30028c85 VM |
7446 | ready[n_asms] = insn; |
7447 | *insnp = lowest; | |
7448 | n_asms++; | |
7449 | } | |
7450 | else | |
7451 | { | |
ce1ce33a | 7452 | rtx_insn *highest = ready[n_ready - 1]; |
30028c85 VM |
7453 | ready[n_ready - 1] = insn; |
7454 | *insnp = highest; | |
7455 | return 1; | |
7456 | } | |
7457 | } | |
7458 | } | |
98d2b17e | 7459 | |
30028c85 | 7460 | if (n_asms < n_ready) |
98d2b17e | 7461 | { |
30028c85 VM |
7462 | /* Some normal insns to process. Skip the asms. */ |
7463 | ready += n_asms; | |
7464 | n_ready -= n_asms; | |
98d2b17e | 7465 | } |
30028c85 VM |
7466 | else if (n_ready > 0) |
7467 | return 1; | |
2130b7fb BS |
7468 | } |
7469 | ||
30028c85 | 7470 | if (ia64_final_schedule) |
2130b7fb | 7471 | { |
30028c85 VM |
7472 | int deleted = 0; |
7473 | int nr_need_stop = 0; | |
7474 | ||
7475 | for (insnp = ready; insnp < e_ready; insnp++) | |
c1bc6ca8 | 7476 | if (safe_group_barrier_needed (*insnp)) |
30028c85 | 7477 | nr_need_stop++; |
9c808aad | 7478 | |
30028c85 VM |
7479 | if (reorder_type == 1 && n_ready == nr_need_stop) |
7480 | return 0; | |
7481 | if (reorder_type == 0) | |
7482 | return 1; | |
7483 | insnp = e_ready; | |
7484 | /* Move down everything that needs a stop bit, preserving | |
7485 | relative order. */ | |
7486 | while (insnp-- > ready + deleted) | |
7487 | while (insnp >= ready + deleted) | |
7488 | { | |
ce1ce33a | 7489 | rtx_insn *insn = *insnp; |
c1bc6ca8 | 7490 | if (! safe_group_barrier_needed (insn)) |
30028c85 VM |
7491 | break; |
7492 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7493 | *ready = insn; | |
7494 | deleted++; | |
7495 | } | |
7496 | n_ready -= deleted; | |
7497 | ready += deleted; | |
2130b7fb | 7498 | } |
2130b7fb | 7499 | |
388092d5 AB |
7500 | current_cycle = clock_var; |
7501 | if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns) | |
7502 | { | |
7503 | int moved = 0; | |
7504 | ||
7505 | insnp = e_ready; | |
7506 | /* Move down loads/stores, preserving relative order. */ | |
7507 | while (insnp-- > ready + moved) | |
7508 | while (insnp >= ready + moved) | |
7509 | { | |
ce1ce33a | 7510 | rtx_insn *insn = *insnp; |
388092d5 AB |
7511 | if (! is_load_p (insn)) |
7512 | break; | |
7513 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7514 | *ready = insn; | |
7515 | moved++; | |
7516 | } | |
7517 | n_ready -= moved; | |
7518 | ready += moved; | |
7519 | } | |
7520 | ||
30028c85 | 7521 | return 1; |
2130b7fb | 7522 | } |
6b6c1201 | 7523 | |
30028c85 VM |
7524 | /* We are about to being issuing insns for this clock cycle. Override |
7525 | the default sort algorithm to better slot instructions. */ | |
c65ebc55 | 7526 | |
30028c85 | 7527 | static int |
ce1ce33a DM |
7528 | ia64_sched_reorder (FILE *dump, int sched_verbose, rtx_insn **ready, |
7529 | int *pn_ready, int clock_var) | |
2130b7fb | 7530 | { |
30028c85 VM |
7531 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, |
7532 | pn_ready, clock_var, 0); | |
2130b7fb BS |
7533 | } |
7534 | ||
30028c85 VM |
7535 | /* Like ia64_sched_reorder, but called after issuing each insn. |
7536 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7537 | |
30028c85 | 7538 | static int |
9c808aad | 7539 | ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
ce1ce33a | 7540 | int sched_verbose ATTRIBUTE_UNUSED, rtx_insn **ready, |
9c808aad | 7541 | int *pn_ready, int clock_var) |
30028c85 | 7542 | { |
30028c85 VM |
7543 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready, |
7544 | clock_var, 1); | |
2130b7fb BS |
7545 | } |
7546 | ||
30028c85 VM |
7547 | /* We are about to issue INSN. Return the number of insns left on the |
7548 | ready queue that can be issued this cycle. */ | |
2130b7fb | 7549 | |
30028c85 | 7550 | static int |
9c808aad AJ |
7551 | ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
7552 | int sched_verbose ATTRIBUTE_UNUSED, | |
ac44248e | 7553 | rtx_insn *insn, |
9c808aad | 7554 | int can_issue_more ATTRIBUTE_UNUSED) |
2130b7fb | 7555 | { |
388092d5 | 7556 | if (sched_deps_info->generate_spec_deps && !sel_sched_p ()) |
048d0d36 | 7557 | /* Modulo scheduling does not extend h_i_d when emitting |
388092d5 | 7558 | new instructions. Don't use h_i_d, if we don't have to. */ |
048d0d36 MK |
7559 | { |
7560 | if (DONE_SPEC (insn) & BEGIN_DATA) | |
7561 | pending_data_specs++; | |
7562 | if (CHECK_SPEC (insn) & BEGIN_DATA) | |
7563 | pending_data_specs--; | |
7564 | } | |
7565 | ||
b5b8b0ac AO |
7566 | if (DEBUG_INSN_P (insn)) |
7567 | return 1; | |
7568 | ||
30028c85 VM |
7569 | last_scheduled_insn = insn; |
7570 | memcpy (prev_cycle_state, curr_state, dfa_state_size); | |
7571 | if (reload_completed) | |
2130b7fb | 7572 | { |
c1bc6ca8 | 7573 | int needed = group_barrier_needed (insn); |
e820471b NS |
7574 | |
7575 | gcc_assert (!needed); | |
b64925dc | 7576 | if (CALL_P (insn)) |
30028c85 VM |
7577 | init_insn_group_barriers (); |
7578 | stops_p [INSN_UID (insn)] = stop_before_p; | |
7579 | stop_before_p = 0; | |
388092d5 AB |
7580 | |
7581 | record_memory_reference (insn); | |
2130b7fb | 7582 | } |
30028c85 VM |
7583 | return 1; |
7584 | } | |
c65ebc55 | 7585 | |
4960a0cb | 7586 | /* We are choosing insn from the ready queue. Return zero if INSN |
30028c85 | 7587 | can be chosen. */ |
c65ebc55 | 7588 | |
30028c85 | 7589 | static int |
ac44248e | 7590 | ia64_first_cycle_multipass_dfa_lookahead_guard (rtx_insn *insn, int ready_index) |
30028c85 | 7591 | { |
388092d5 | 7592 | gcc_assert (insn && INSN_P (insn)); |
048d0d36 | 7593 | |
4960a0cb MK |
7594 | /* Size of ALAT is 32. As far as we perform conservative |
7595 | data speculation, we keep ALAT half-empty. */ | |
31815ed7 | 7596 | if (pending_data_specs >= 16 && (TODO_SPEC (insn) & BEGIN_DATA)) |
4960a0cb | 7597 | return ready_index == 0 ? -1 : 1; |
048d0d36 | 7598 | |
4960a0cb MK |
7599 | if (ready_index == 0) |
7600 | return 0; | |
7601 | ||
7602 | if ((!reload_completed | |
7603 | || !safe_group_barrier_needed (insn)) | |
7604 | && (!mflag_sched_mem_insns_hard_limit | |
7605 | || !is_load_p (insn) | |
7606 | || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns)) | |
7607 | return 0; | |
676cad4d MK |
7608 | |
7609 | return 1; | |
2130b7fb BS |
7610 | } |
7611 | ||
30028c85 VM |
7612 | /* The following variable value is pseudo-insn used by the DFA insn |
7613 | scheduler to change the DFA state when the simulated clock is | |
7614 | increased. */ | |
2130b7fb | 7615 | |
dd3d2b35 | 7616 | static rtx_insn *dfa_pre_cycle_insn; |
2130b7fb | 7617 | |
388092d5 AB |
7618 | /* Returns 1 when a meaningful insn was scheduled between the last group |
7619 | barrier and LAST. */ | |
7620 | static int | |
b32d5189 | 7621 | scheduled_good_insn (rtx_insn *last) |
388092d5 AB |
7622 | { |
7623 | if (last && recog_memoized (last) >= 0) | |
7624 | return 1; | |
7625 | ||
7626 | for ( ; | |
7627 | last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last) | |
7628 | && !stops_p[INSN_UID (last)]; | |
7629 | last = PREV_INSN (last)) | |
7630 | /* We could hit a NOTE_INSN_DELETED here which is actually outside | |
7631 | the ebb we're scheduling. */ | |
7632 | if (INSN_P (last) && recog_memoized (last) >= 0) | |
7633 | return 1; | |
7634 | ||
7635 | return 0; | |
7636 | } | |
7637 | ||
1e5f1716 | 7638 | /* We are about to being issuing INSN. Return nonzero if we cannot |
30028c85 VM |
7639 | issue it on given cycle CLOCK and return zero if we should not sort |
7640 | the ready queue on the next clock start. */ | |
2130b7fb BS |
7641 | |
7642 | static int | |
ac44248e | 7643 | ia64_dfa_new_cycle (FILE *dump, int verbose, rtx_insn *insn, int last_clock, |
9c808aad | 7644 | int clock, int *sort_p) |
2130b7fb | 7645 | { |
e820471b | 7646 | gcc_assert (insn && INSN_P (insn)); |
b5b8b0ac AO |
7647 | |
7648 | if (DEBUG_INSN_P (insn)) | |
7649 | return 0; | |
7650 | ||
388092d5 AB |
7651 | /* When a group barrier is needed for insn, last_scheduled_insn |
7652 | should be set. */ | |
7653 | gcc_assert (!(reload_completed && safe_group_barrier_needed (insn)) | |
7654 | || last_scheduled_insn); | |
7655 | ||
7656 | if ((reload_completed | |
7657 | && (safe_group_barrier_needed (insn) | |
7658 | || (mflag_sched_stop_bits_after_every_cycle | |
7659 | && last_clock != clock | |
7660 | && last_scheduled_insn | |
7661 | && scheduled_good_insn (last_scheduled_insn)))) | |
30028c85 | 7662 | || (last_scheduled_insn |
b64925dc | 7663 | && (CALL_P (last_scheduled_insn) |
7b84aac0 | 7664 | || unknown_for_bundling_p (last_scheduled_insn)))) |
2130b7fb | 7665 | { |
30028c85 | 7666 | init_insn_group_barriers (); |
388092d5 | 7667 | |
30028c85 VM |
7668 | if (verbose && dump) |
7669 | fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn), | |
7670 | last_clock == clock ? " + cycle advance" : ""); | |
388092d5 | 7671 | |
30028c85 | 7672 | stop_before_p = 1; |
388092d5 AB |
7673 | current_cycle = clock; |
7674 | mem_ops_in_group[current_cycle % 4] = 0; | |
7675 | ||
30028c85 | 7676 | if (last_clock == clock) |
2130b7fb | 7677 | { |
30028c85 VM |
7678 | state_transition (curr_state, dfa_stop_insn); |
7679 | if (TARGET_EARLY_STOP_BITS) | |
7680 | *sort_p = (last_scheduled_insn == NULL_RTX | |
b64925dc | 7681 | || ! CALL_P (last_scheduled_insn)); |
30028c85 VM |
7682 | else |
7683 | *sort_p = 0; | |
7684 | return 1; | |
7685 | } | |
388092d5 AB |
7686 | |
7687 | if (last_scheduled_insn) | |
25069b42 | 7688 | { |
7b84aac0 | 7689 | if (unknown_for_bundling_p (last_scheduled_insn)) |
388092d5 AB |
7690 | state_reset (curr_state); |
7691 | else | |
7692 | { | |
7693 | memcpy (curr_state, prev_cycle_state, dfa_state_size); | |
7694 | state_transition (curr_state, dfa_stop_insn); | |
7695 | state_transition (curr_state, dfa_pre_cycle_insn); | |
7696 | state_transition (curr_state, NULL); | |
7697 | } | |
25069b42 | 7698 | } |
30028c85 | 7699 | } |
30028c85 | 7700 | return 0; |
2130b7fb BS |
7701 | } |
7702 | ||
048d0d36 MK |
7703 | /* Implement targetm.sched.h_i_d_extended hook. |
7704 | Extend internal data structures. */ | |
7705 | static void | |
7706 | ia64_h_i_d_extended (void) | |
7707 | { | |
048d0d36 MK |
7708 | if (stops_p != NULL) |
7709 | { | |
388092d5 | 7710 | int new_clocks_length = get_max_uid () * 3 / 2; |
5ead67f6 | 7711 | stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1); |
048d0d36 MK |
7712 | clocks_length = new_clocks_length; |
7713 | } | |
7714 | } | |
388092d5 AB |
7715 | \f |
7716 | ||
7717 | /* This structure describes the data used by the backend to guide scheduling. | |
7718 | When the current scheduling point is switched, this data should be saved | |
7719 | and restored later, if the scheduler returns to this point. */ | |
7720 | struct _ia64_sched_context | |
7721 | { | |
7722 | state_t prev_cycle_state; | |
b32d5189 | 7723 | rtx_insn *last_scheduled_insn; |
388092d5 AB |
7724 | struct reg_write_state rws_sum[NUM_REGS]; |
7725 | struct reg_write_state rws_insn[NUM_REGS]; | |
7726 | int first_instruction; | |
7727 | int pending_data_specs; | |
7728 | int current_cycle; | |
7729 | char mem_ops_in_group[4]; | |
7730 | }; | |
7731 | typedef struct _ia64_sched_context *ia64_sched_context_t; | |
7732 | ||
7733 | /* Allocates a scheduling context. */ | |
7734 | static void * | |
7735 | ia64_alloc_sched_context (void) | |
7736 | { | |
7737 | return xmalloc (sizeof (struct _ia64_sched_context)); | |
7738 | } | |
7739 | ||
7740 | /* Initializes the _SC context with clean data, if CLEAN_P, and from | |
7741 | the global context otherwise. */ | |
7742 | static void | |
7743 | ia64_init_sched_context (void *_sc, bool clean_p) | |
7744 | { | |
7745 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7746 | ||
7747 | sc->prev_cycle_state = xmalloc (dfa_state_size); | |
7748 | if (clean_p) | |
7749 | { | |
7750 | state_reset (sc->prev_cycle_state); | |
b32d5189 | 7751 | sc->last_scheduled_insn = NULL; |
388092d5 AB |
7752 | memset (sc->rws_sum, 0, sizeof (rws_sum)); |
7753 | memset (sc->rws_insn, 0, sizeof (rws_insn)); | |
7754 | sc->first_instruction = 1; | |
7755 | sc->pending_data_specs = 0; | |
7756 | sc->current_cycle = 0; | |
7757 | memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
7758 | } | |
7759 | else | |
7760 | { | |
7761 | memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size); | |
7762 | sc->last_scheduled_insn = last_scheduled_insn; | |
7763 | memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum)); | |
7764 | memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn)); | |
7765 | sc->first_instruction = first_instruction; | |
7766 | sc->pending_data_specs = pending_data_specs; | |
7767 | sc->current_cycle = current_cycle; | |
7768 | memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7769 | } | |
7770 | } | |
7771 | ||
7772 | /* Sets the global scheduling context to the one pointed to by _SC. */ | |
7773 | static void | |
7774 | ia64_set_sched_context (void *_sc) | |
7775 | { | |
7776 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7777 | ||
7778 | gcc_assert (sc != NULL); | |
7779 | ||
7780 | memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size); | |
7781 | last_scheduled_insn = sc->last_scheduled_insn; | |
7782 | memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum)); | |
7783 | memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn)); | |
7784 | first_instruction = sc->first_instruction; | |
7785 | pending_data_specs = sc->pending_data_specs; | |
7786 | current_cycle = sc->current_cycle; | |
7787 | memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7788 | } | |
7789 | ||
7790 | /* Clears the data in the _SC scheduling context. */ | |
7791 | static void | |
7792 | ia64_clear_sched_context (void *_sc) | |
7793 | { | |
7794 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7795 | ||
7796 | free (sc->prev_cycle_state); | |
7797 | sc->prev_cycle_state = NULL; | |
7798 | } | |
7799 | ||
7800 | /* Frees the _SC scheduling context. */ | |
7801 | static void | |
7802 | ia64_free_sched_context (void *_sc) | |
7803 | { | |
7804 | gcc_assert (_sc != NULL); | |
7805 | ||
7806 | free (_sc); | |
7807 | } | |
7808 | ||
7809 | typedef rtx (* gen_func_t) (rtx, rtx); | |
7810 | ||
7811 | /* Return a function that will generate a load of mode MODE_NO | |
7812 | with speculation types TS. */ | |
7813 | static gen_func_t | |
7814 | get_spec_load_gen_function (ds_t ts, int mode_no) | |
7815 | { | |
7816 | static gen_func_t gen_ld_[] = { | |
7817 | gen_movbi, | |
7818 | gen_movqi_internal, | |
7819 | gen_movhi_internal, | |
7820 | gen_movsi_internal, | |
7821 | gen_movdi_internal, | |
7822 | gen_movsf_internal, | |
7823 | gen_movdf_internal, | |
7824 | gen_movxf_internal, | |
7825 | gen_movti_internal, | |
7826 | gen_zero_extendqidi2, | |
7827 | gen_zero_extendhidi2, | |
7828 | gen_zero_extendsidi2, | |
7829 | }; | |
7830 | ||
7831 | static gen_func_t gen_ld_a[] = { | |
7832 | gen_movbi_advanced, | |
7833 | gen_movqi_advanced, | |
7834 | gen_movhi_advanced, | |
7835 | gen_movsi_advanced, | |
7836 | gen_movdi_advanced, | |
7837 | gen_movsf_advanced, | |
7838 | gen_movdf_advanced, | |
7839 | gen_movxf_advanced, | |
7840 | gen_movti_advanced, | |
7841 | gen_zero_extendqidi2_advanced, | |
7842 | gen_zero_extendhidi2_advanced, | |
7843 | gen_zero_extendsidi2_advanced, | |
7844 | }; | |
7845 | static gen_func_t gen_ld_s[] = { | |
7846 | gen_movbi_speculative, | |
7847 | gen_movqi_speculative, | |
7848 | gen_movhi_speculative, | |
7849 | gen_movsi_speculative, | |
7850 | gen_movdi_speculative, | |
7851 | gen_movsf_speculative, | |
7852 | gen_movdf_speculative, | |
7853 | gen_movxf_speculative, | |
7854 | gen_movti_speculative, | |
7855 | gen_zero_extendqidi2_speculative, | |
7856 | gen_zero_extendhidi2_speculative, | |
7857 | gen_zero_extendsidi2_speculative, | |
7858 | }; | |
7859 | static gen_func_t gen_ld_sa[] = { | |
7860 | gen_movbi_speculative_advanced, | |
7861 | gen_movqi_speculative_advanced, | |
7862 | gen_movhi_speculative_advanced, | |
7863 | gen_movsi_speculative_advanced, | |
7864 | gen_movdi_speculative_advanced, | |
7865 | gen_movsf_speculative_advanced, | |
7866 | gen_movdf_speculative_advanced, | |
7867 | gen_movxf_speculative_advanced, | |
7868 | gen_movti_speculative_advanced, | |
7869 | gen_zero_extendqidi2_speculative_advanced, | |
7870 | gen_zero_extendhidi2_speculative_advanced, | |
7871 | gen_zero_extendsidi2_speculative_advanced, | |
7872 | }; | |
7873 | static gen_func_t gen_ld_s_a[] = { | |
7874 | gen_movbi_speculative_a, | |
7875 | gen_movqi_speculative_a, | |
7876 | gen_movhi_speculative_a, | |
7877 | gen_movsi_speculative_a, | |
7878 | gen_movdi_speculative_a, | |
7879 | gen_movsf_speculative_a, | |
7880 | gen_movdf_speculative_a, | |
7881 | gen_movxf_speculative_a, | |
7882 | gen_movti_speculative_a, | |
7883 | gen_zero_extendqidi2_speculative_a, | |
7884 | gen_zero_extendhidi2_speculative_a, | |
7885 | gen_zero_extendsidi2_speculative_a, | |
7886 | }; | |
7887 | ||
7888 | gen_func_t *gen_ld; | |
7889 | ||
7890 | if (ts & BEGIN_DATA) | |
7891 | { | |
7892 | if (ts & BEGIN_CONTROL) | |
7893 | gen_ld = gen_ld_sa; | |
7894 | else | |
7895 | gen_ld = gen_ld_a; | |
7896 | } | |
7897 | else if (ts & BEGIN_CONTROL) | |
7898 | { | |
7899 | if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL) | |
7900 | || ia64_needs_block_p (ts)) | |
7901 | gen_ld = gen_ld_s; | |
7902 | else | |
7903 | gen_ld = gen_ld_s_a; | |
7904 | } | |
7905 | else if (ts == 0) | |
7906 | gen_ld = gen_ld_; | |
7907 | else | |
7908 | gcc_unreachable (); | |
7909 | ||
7910 | return gen_ld[mode_no]; | |
7911 | } | |
048d0d36 | 7912 | |
ef4bddc2 | 7913 | /* Constants that help mapping 'machine_mode' to int. */ |
048d0d36 MK |
7914 | enum SPEC_MODES |
7915 | { | |
7916 | SPEC_MODE_INVALID = -1, | |
7917 | SPEC_MODE_FIRST = 0, | |
7918 | SPEC_MODE_FOR_EXTEND_FIRST = 1, | |
7919 | SPEC_MODE_FOR_EXTEND_LAST = 3, | |
7920 | SPEC_MODE_LAST = 8 | |
7921 | }; | |
7922 | ||
388092d5 AB |
7923 | enum |
7924 | { | |
7925 | /* Offset to reach ZERO_EXTEND patterns. */ | |
7926 | SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1 | |
7927 | }; | |
7928 | ||
048d0d36 MK |
7929 | /* Return index of the MODE. */ |
7930 | static int | |
ef4bddc2 | 7931 | ia64_mode_to_int (machine_mode mode) |
048d0d36 MK |
7932 | { |
7933 | switch (mode) | |
7934 | { | |
7935 | case BImode: return 0; /* SPEC_MODE_FIRST */ | |
7936 | case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */ | |
7937 | case HImode: return 2; | |
7938 | case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */ | |
7939 | case DImode: return 4; | |
7940 | case SFmode: return 5; | |
7941 | case DFmode: return 6; | |
7942 | case XFmode: return 7; | |
7943 | case TImode: | |
7944 | /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not | |
7945 | mentioned in itanium[12].md. Predicate fp_register_operand also | |
7946 | needs to be defined. Bottom line: better disable for now. */ | |
7947 | return SPEC_MODE_INVALID; | |
7948 | default: return SPEC_MODE_INVALID; | |
7949 | } | |
7950 | } | |
7951 | ||
7952 | /* Provide information about speculation capabilities. */ | |
7953 | static void | |
7954 | ia64_set_sched_flags (spec_info_t spec_info) | |
7955 | { | |
7956 | unsigned int *flags = &(current_sched_info->flags); | |
7957 | ||
7958 | if (*flags & SCHED_RGN | |
388092d5 AB |
7959 | || *flags & SCHED_EBB |
7960 | || *flags & SEL_SCHED) | |
048d0d36 MK |
7961 | { |
7962 | int mask = 0; | |
7963 | ||
a57aee2a | 7964 | if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0) |
388092d5 | 7965 | || (mflag_sched_ar_data_spec && reload_completed)) |
048d0d36 MK |
7966 | { |
7967 | mask |= BEGIN_DATA; | |
388092d5 AB |
7968 | |
7969 | if (!sel_sched_p () | |
7970 | && ((mflag_sched_br_in_data_spec && !reload_completed) | |
7971 | || (mflag_sched_ar_in_data_spec && reload_completed))) | |
048d0d36 MK |
7972 | mask |= BE_IN_DATA; |
7973 | } | |
7974 | ||
388092d5 AB |
7975 | if (mflag_sched_control_spec |
7976 | && (!sel_sched_p () | |
7977 | || reload_completed)) | |
048d0d36 MK |
7978 | { |
7979 | mask |= BEGIN_CONTROL; | |
7980 | ||
388092d5 | 7981 | if (!sel_sched_p () && mflag_sched_in_control_spec) |
048d0d36 MK |
7982 | mask |= BE_IN_CONTROL; |
7983 | } | |
7984 | ||
7ab5df48 AB |
7985 | spec_info->mask = mask; |
7986 | ||
048d0d36 MK |
7987 | if (mask) |
7988 | { | |
6fb5fa3c DB |
7989 | *flags |= USE_DEPS_LIST | DO_SPECULATION; |
7990 | ||
7991 | if (mask & BE_IN_SPEC) | |
7992 | *flags |= NEW_BBS; | |
048d0d36 | 7993 | |
048d0d36 MK |
7994 | spec_info->flags = 0; |
7995 | ||
16d83dd6 MK |
7996 | if ((mask & CONTROL_SPEC) |
7997 | && sel_sched_p () && mflag_sel_sched_dont_check_control_spec) | |
7998 | spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL; | |
388092d5 AB |
7999 | |
8000 | if (sched_verbose >= 1) | |
8001 | spec_info->dump = sched_dump; | |
048d0d36 MK |
8002 | else |
8003 | spec_info->dump = 0; | |
8004 | ||
8005 | if (mflag_sched_count_spec_in_critical_path) | |
8006 | spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; | |
8007 | } | |
8008 | } | |
cd510f15 AM |
8009 | else |
8010 | spec_info->mask = 0; | |
048d0d36 MK |
8011 | } |
8012 | ||
388092d5 AB |
8013 | /* If INSN is an appropriate load return its mode. |
8014 | Return -1 otherwise. */ | |
048d0d36 | 8015 | static int |
647d790d | 8016 | get_mode_no_for_insn (rtx_insn *insn) |
388092d5 AB |
8017 | { |
8018 | rtx reg, mem, mode_rtx; | |
8019 | int mode_no; | |
048d0d36 | 8020 | bool extend_p; |
048d0d36 | 8021 | |
388092d5 | 8022 | extract_insn_cached (insn); |
048d0d36 | 8023 | |
388092d5 AB |
8024 | /* We use WHICH_ALTERNATIVE only after reload. This will |
8025 | guarantee that reload won't touch a speculative insn. */ | |
f6ec1d11 | 8026 | |
388092d5 | 8027 | if (recog_data.n_operands != 2) |
048d0d36 MK |
8028 | return -1; |
8029 | ||
388092d5 AB |
8030 | reg = recog_data.operand[0]; |
8031 | mem = recog_data.operand[1]; | |
f6ec1d11 | 8032 | |
388092d5 AB |
8033 | /* We should use MEM's mode since REG's mode in presence of |
8034 | ZERO_EXTEND will always be DImode. */ | |
8035 | if (get_attr_speculable1 (insn) == SPECULABLE1_YES) | |
8036 | /* Process non-speculative ld. */ | |
8037 | { | |
8038 | if (!reload_completed) | |
8039 | { | |
8040 | /* Do not speculate into regs like ar.lc. */ | |
8041 | if (!REG_P (reg) || AR_REGNO_P (REGNO (reg))) | |
8042 | return -1; | |
8043 | ||
8044 | if (!MEM_P (mem)) | |
8045 | return -1; | |
8046 | ||
8047 | { | |
8048 | rtx mem_reg = XEXP (mem, 0); | |
8049 | ||
8050 | if (!REG_P (mem_reg)) | |
8051 | return -1; | |
8052 | } | |
8053 | ||
8054 | mode_rtx = mem; | |
8055 | } | |
8056 | else if (get_attr_speculable2 (insn) == SPECULABLE2_YES) | |
8057 | { | |
8058 | gcc_assert (REG_P (reg) && MEM_P (mem)); | |
8059 | mode_rtx = mem; | |
8060 | } | |
8061 | else | |
8062 | return -1; | |
8063 | } | |
8064 | else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES | |
8065 | || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES | |
8066 | || get_attr_check_load (insn) == CHECK_LOAD_YES) | |
8067 | /* Process speculative ld or ld.c. */ | |
048d0d36 | 8068 | { |
388092d5 AB |
8069 | gcc_assert (REG_P (reg) && MEM_P (mem)); |
8070 | mode_rtx = mem; | |
048d0d36 MK |
8071 | } |
8072 | else | |
048d0d36 | 8073 | { |
388092d5 | 8074 | enum attr_itanium_class attr_class = get_attr_itanium_class (insn); |
048d0d36 | 8075 | |
388092d5 AB |
8076 | if (attr_class == ITANIUM_CLASS_CHK_A |
8077 | || attr_class == ITANIUM_CLASS_CHK_S_I | |
8078 | || attr_class == ITANIUM_CLASS_CHK_S_F) | |
8079 | /* Process chk. */ | |
8080 | mode_rtx = reg; | |
8081 | else | |
8082 | return -1; | |
048d0d36 | 8083 | } |
f6ec1d11 | 8084 | |
388092d5 | 8085 | mode_no = ia64_mode_to_int (GET_MODE (mode_rtx)); |
f6ec1d11 | 8086 | |
388092d5 | 8087 | if (mode_no == SPEC_MODE_INVALID) |
048d0d36 MK |
8088 | return -1; |
8089 | ||
388092d5 AB |
8090 | extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx)); |
8091 | ||
8092 | if (extend_p) | |
8093 | { | |
8094 | if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no | |
8095 | && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)) | |
8096 | return -1; | |
f6ec1d11 | 8097 | |
388092d5 AB |
8098 | mode_no += SPEC_GEN_EXTEND_OFFSET; |
8099 | } | |
048d0d36 | 8100 | |
388092d5 | 8101 | return mode_no; |
048d0d36 MK |
8102 | } |
8103 | ||
388092d5 AB |
8104 | /* If X is an unspec part of a speculative load, return its code. |
8105 | Return -1 otherwise. */ | |
8106 | static int | |
8107 | get_spec_unspec_code (const_rtx x) | |
8108 | { | |
8109 | if (GET_CODE (x) != UNSPEC) | |
8110 | return -1; | |
048d0d36 | 8111 | |
048d0d36 | 8112 | { |
388092d5 | 8113 | int code; |
048d0d36 | 8114 | |
388092d5 | 8115 | code = XINT (x, 1); |
048d0d36 | 8116 | |
388092d5 AB |
8117 | switch (code) |
8118 | { | |
8119 | case UNSPEC_LDA: | |
8120 | case UNSPEC_LDS: | |
8121 | case UNSPEC_LDS_A: | |
8122 | case UNSPEC_LDSA: | |
8123 | return code; | |
048d0d36 | 8124 | |
388092d5 AB |
8125 | default: |
8126 | return -1; | |
8127 | } | |
8128 | } | |
8129 | } | |
048d0d36 | 8130 | |
388092d5 AB |
8131 | /* Implement skip_rtx_p hook. */ |
8132 | static bool | |
8133 | ia64_skip_rtx_p (const_rtx x) | |
8134 | { | |
8135 | return get_spec_unspec_code (x) != -1; | |
8136 | } | |
048d0d36 | 8137 | |
388092d5 AB |
8138 | /* If INSN is a speculative load, return its UNSPEC code. |
8139 | Return -1 otherwise. */ | |
8140 | static int | |
8141 | get_insn_spec_code (const_rtx insn) | |
8142 | { | |
8143 | rtx pat, reg, mem; | |
048d0d36 | 8144 | |
388092d5 | 8145 | pat = PATTERN (insn); |
048d0d36 | 8146 | |
388092d5 AB |
8147 | if (GET_CODE (pat) == COND_EXEC) |
8148 | pat = COND_EXEC_CODE (pat); | |
048d0d36 | 8149 | |
388092d5 AB |
8150 | if (GET_CODE (pat) != SET) |
8151 | return -1; | |
8152 | ||
8153 | reg = SET_DEST (pat); | |
8154 | if (!REG_P (reg)) | |
8155 | return -1; | |
8156 | ||
8157 | mem = SET_SRC (pat); | |
8158 | if (GET_CODE (mem) == ZERO_EXTEND) | |
8159 | mem = XEXP (mem, 0); | |
8160 | ||
8161 | return get_spec_unspec_code (mem); | |
8162 | } | |
8163 | ||
8164 | /* If INSN is a speculative load, return a ds with the speculation types. | |
8165 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8166 | static ds_t | |
ac44248e | 8167 | ia64_get_insn_spec_ds (rtx_insn *insn) |
388092d5 AB |
8168 | { |
8169 | int code = get_insn_spec_code (insn); | |
8170 | ||
8171 | switch (code) | |
048d0d36 | 8172 | { |
388092d5 AB |
8173 | case UNSPEC_LDA: |
8174 | return BEGIN_DATA; | |
048d0d36 | 8175 | |
388092d5 AB |
8176 | case UNSPEC_LDS: |
8177 | case UNSPEC_LDS_A: | |
8178 | return BEGIN_CONTROL; | |
048d0d36 | 8179 | |
388092d5 AB |
8180 | case UNSPEC_LDSA: |
8181 | return BEGIN_DATA | BEGIN_CONTROL; | |
048d0d36 | 8182 | |
388092d5 AB |
8183 | default: |
8184 | return 0; | |
048d0d36 | 8185 | } |
388092d5 AB |
8186 | } |
8187 | ||
8188 | /* If INSN is a speculative load return a ds with the speculation types that | |
8189 | will be checked. | |
8190 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8191 | static ds_t | |
ac44248e | 8192 | ia64_get_insn_checked_ds (rtx_insn *insn) |
388092d5 AB |
8193 | { |
8194 | int code = get_insn_spec_code (insn); | |
8195 | ||
8196 | switch (code) | |
048d0d36 | 8197 | { |
388092d5 AB |
8198 | case UNSPEC_LDA: |
8199 | return BEGIN_DATA | BEGIN_CONTROL; | |
8200 | ||
8201 | case UNSPEC_LDS: | |
8202 | return BEGIN_CONTROL; | |
8203 | ||
8204 | case UNSPEC_LDS_A: | |
8205 | case UNSPEC_LDSA: | |
8206 | return BEGIN_DATA | BEGIN_CONTROL; | |
8207 | ||
8208 | default: | |
8209 | return 0; | |
048d0d36 | 8210 | } |
388092d5 | 8211 | } |
048d0d36 | 8212 | |
388092d5 AB |
8213 | /* If GEN_P is true, calculate the index of needed speculation check and return |
8214 | speculative pattern for INSN with speculative mode TS, machine mode | |
8215 | MODE_NO and with ZERO_EXTEND (if EXTEND_P is true). | |
8216 | If GEN_P is false, just calculate the index of needed speculation check. */ | |
8217 | static rtx | |
8218 | ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no) | |
8219 | { | |
8220 | rtx pat, new_pat; | |
8221 | gen_func_t gen_load; | |
048d0d36 | 8222 | |
388092d5 | 8223 | gen_load = get_spec_load_gen_function (ts, mode_no); |
048d0d36 | 8224 | |
388092d5 AB |
8225 | new_pat = gen_load (copy_rtx (recog_data.operand[0]), |
8226 | copy_rtx (recog_data.operand[1])); | |
048d0d36 MK |
8227 | |
8228 | pat = PATTERN (insn); | |
8229 | if (GET_CODE (pat) == COND_EXEC) | |
388092d5 AB |
8230 | new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), |
8231 | new_pat); | |
048d0d36 MK |
8232 | |
8233 | return new_pat; | |
8234 | } | |
8235 | ||
048d0d36 | 8236 | static bool |
388092d5 AB |
8237 | insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED, |
8238 | ds_t ds ATTRIBUTE_UNUSED) | |
048d0d36 | 8239 | { |
388092d5 AB |
8240 | return false; |
8241 | } | |
048d0d36 | 8242 | |
388092d5 AB |
8243 | /* Implement targetm.sched.speculate_insn hook. |
8244 | Check if the INSN can be TS speculative. | |
8245 | If 'no' - return -1. | |
8246 | If 'yes' - generate speculative pattern in the NEW_PAT and return 1. | |
8247 | If current pattern of the INSN already provides TS speculation, | |
8248 | return 0. */ | |
8249 | static int | |
ac44248e | 8250 | ia64_speculate_insn (rtx_insn *insn, ds_t ts, rtx *new_pat) |
388092d5 AB |
8251 | { |
8252 | int mode_no; | |
8253 | int res; | |
8254 | ||
8255 | gcc_assert (!(ts & ~SPECULATIVE)); | |
048d0d36 | 8256 | |
388092d5 AB |
8257 | if (ia64_spec_check_p (insn)) |
8258 | return -1; | |
048d0d36 | 8259 | |
388092d5 AB |
8260 | if ((ts & BE_IN_SPEC) |
8261 | && !insn_can_be_in_speculative_p (insn, ts)) | |
8262 | return -1; | |
048d0d36 | 8263 | |
388092d5 | 8264 | mode_no = get_mode_no_for_insn (insn); |
048d0d36 | 8265 | |
388092d5 AB |
8266 | if (mode_no != SPEC_MODE_INVALID) |
8267 | { | |
8268 | if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts)) | |
8269 | res = 0; | |
8270 | else | |
8271 | { | |
8272 | res = 1; | |
8273 | *new_pat = ia64_gen_spec_load (insn, ts, mode_no); | |
8274 | } | |
8275 | } | |
8276 | else | |
8277 | res = -1; | |
048d0d36 | 8278 | |
388092d5 AB |
8279 | return res; |
8280 | } | |
048d0d36 | 8281 | |
388092d5 AB |
8282 | /* Return a function that will generate a check for speculation TS with mode |
8283 | MODE_NO. | |
8284 | If simple check is needed, pass true for SIMPLE_CHECK_P. | |
8285 | If clearing check is needed, pass true for CLEARING_CHECK_P. */ | |
8286 | static gen_func_t | |
8287 | get_spec_check_gen_function (ds_t ts, int mode_no, | |
8288 | bool simple_check_p, bool clearing_check_p) | |
8289 | { | |
8290 | static gen_func_t gen_ld_c_clr[] = { | |
048d0d36 MK |
8291 | gen_movbi_clr, |
8292 | gen_movqi_clr, | |
8293 | gen_movhi_clr, | |
8294 | gen_movsi_clr, | |
8295 | gen_movdi_clr, | |
8296 | gen_movsf_clr, | |
8297 | gen_movdf_clr, | |
8298 | gen_movxf_clr, | |
8299 | gen_movti_clr, | |
8300 | gen_zero_extendqidi2_clr, | |
8301 | gen_zero_extendhidi2_clr, | |
8302 | gen_zero_extendsidi2_clr, | |
388092d5 AB |
8303 | }; |
8304 | static gen_func_t gen_ld_c_nc[] = { | |
8305 | gen_movbi_nc, | |
8306 | gen_movqi_nc, | |
8307 | gen_movhi_nc, | |
8308 | gen_movsi_nc, | |
8309 | gen_movdi_nc, | |
8310 | gen_movsf_nc, | |
8311 | gen_movdf_nc, | |
8312 | gen_movxf_nc, | |
8313 | gen_movti_nc, | |
8314 | gen_zero_extendqidi2_nc, | |
8315 | gen_zero_extendhidi2_nc, | |
8316 | gen_zero_extendsidi2_nc, | |
8317 | }; | |
8318 | static gen_func_t gen_chk_a_clr[] = { | |
048d0d36 MK |
8319 | gen_advanced_load_check_clr_bi, |
8320 | gen_advanced_load_check_clr_qi, | |
8321 | gen_advanced_load_check_clr_hi, | |
8322 | gen_advanced_load_check_clr_si, | |
8323 | gen_advanced_load_check_clr_di, | |
8324 | gen_advanced_load_check_clr_sf, | |
8325 | gen_advanced_load_check_clr_df, | |
8326 | gen_advanced_load_check_clr_xf, | |
8327 | gen_advanced_load_check_clr_ti, | |
8328 | gen_advanced_load_check_clr_di, | |
8329 | gen_advanced_load_check_clr_di, | |
8330 | gen_advanced_load_check_clr_di, | |
388092d5 AB |
8331 | }; |
8332 | static gen_func_t gen_chk_a_nc[] = { | |
8333 | gen_advanced_load_check_nc_bi, | |
8334 | gen_advanced_load_check_nc_qi, | |
8335 | gen_advanced_load_check_nc_hi, | |
8336 | gen_advanced_load_check_nc_si, | |
8337 | gen_advanced_load_check_nc_di, | |
8338 | gen_advanced_load_check_nc_sf, | |
8339 | gen_advanced_load_check_nc_df, | |
8340 | gen_advanced_load_check_nc_xf, | |
8341 | gen_advanced_load_check_nc_ti, | |
8342 | gen_advanced_load_check_nc_di, | |
8343 | gen_advanced_load_check_nc_di, | |
8344 | gen_advanced_load_check_nc_di, | |
8345 | }; | |
8346 | static gen_func_t gen_chk_s[] = { | |
048d0d36 MK |
8347 | gen_speculation_check_bi, |
8348 | gen_speculation_check_qi, | |
8349 | gen_speculation_check_hi, | |
8350 | gen_speculation_check_si, | |
8351 | gen_speculation_check_di, | |
8352 | gen_speculation_check_sf, | |
8353 | gen_speculation_check_df, | |
8354 | gen_speculation_check_xf, | |
8355 | gen_speculation_check_ti, | |
8356 | gen_speculation_check_di, | |
8357 | gen_speculation_check_di, | |
388092d5 | 8358 | gen_speculation_check_di, |
048d0d36 MK |
8359 | }; |
8360 | ||
388092d5 | 8361 | gen_func_t *gen_check; |
048d0d36 | 8362 | |
388092d5 | 8363 | if (ts & BEGIN_DATA) |
048d0d36 | 8364 | { |
388092d5 AB |
8365 | /* We don't need recovery because even if this is ld.sa |
8366 | ALAT entry will be allocated only if NAT bit is set to zero. | |
8367 | So it is enough to use ld.c here. */ | |
8368 | ||
8369 | if (simple_check_p) | |
8370 | { | |
8371 | gcc_assert (mflag_sched_spec_ldc); | |
8372 | ||
8373 | if (clearing_check_p) | |
8374 | gen_check = gen_ld_c_clr; | |
8375 | else | |
8376 | gen_check = gen_ld_c_nc; | |
8377 | } | |
8378 | else | |
8379 | { | |
8380 | if (clearing_check_p) | |
8381 | gen_check = gen_chk_a_clr; | |
8382 | else | |
8383 | gen_check = gen_chk_a_nc; | |
8384 | } | |
048d0d36 | 8385 | } |
388092d5 | 8386 | else if (ts & BEGIN_CONTROL) |
048d0d36 | 8387 | { |
388092d5 AB |
8388 | if (simple_check_p) |
8389 | /* We might want to use ld.sa -> ld.c instead of | |
8390 | ld.s -> chk.s. */ | |
048d0d36 | 8391 | { |
388092d5 | 8392 | gcc_assert (!ia64_needs_block_p (ts)); |
048d0d36 | 8393 | |
388092d5 AB |
8394 | if (clearing_check_p) |
8395 | gen_check = gen_ld_c_clr; | |
8396 | else | |
8397 | gen_check = gen_ld_c_nc; | |
8398 | } | |
8399 | else | |
8400 | { | |
8401 | gen_check = gen_chk_s; | |
048d0d36 | 8402 | } |
388092d5 AB |
8403 | } |
8404 | else | |
8405 | gcc_unreachable (); | |
8406 | ||
8407 | gcc_assert (mode_no >= 0); | |
8408 | return gen_check[mode_no]; | |
8409 | } | |
8410 | ||
8411 | /* Return nonzero, if INSN needs branchy recovery check. */ | |
8412 | static bool | |
8413 | ia64_needs_block_p (ds_t ts) | |
8414 | { | |
8415 | if (ts & BEGIN_DATA) | |
8416 | return !mflag_sched_spec_ldc; | |
8417 | ||
8418 | gcc_assert ((ts & BEGIN_CONTROL) != 0); | |
048d0d36 | 8419 | |
388092d5 AB |
8420 | return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc); |
8421 | } | |
8422 | ||
8e90de43 | 8423 | /* Generate (or regenerate) a recovery check for INSN. */ |
388092d5 | 8424 | static rtx |
ac44248e | 8425 | ia64_gen_spec_check (rtx_insn *insn, rtx_insn *label, ds_t ds) |
388092d5 AB |
8426 | { |
8427 | rtx op1, pat, check_pat; | |
8428 | gen_func_t gen_check; | |
8429 | int mode_no; | |
8430 | ||
8431 | mode_no = get_mode_no_for_insn (insn); | |
8432 | gcc_assert (mode_no >= 0); | |
8433 | ||
8434 | if (label) | |
8435 | op1 = label; | |
8436 | else | |
8437 | { | |
8438 | gcc_assert (!ia64_needs_block_p (ds)); | |
8439 | op1 = copy_rtx (recog_data.operand[1]); | |
048d0d36 | 8440 | } |
388092d5 AB |
8441 | |
8442 | gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX, | |
8443 | true); | |
048d0d36 | 8444 | |
388092d5 | 8445 | check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1); |
048d0d36 MK |
8446 | |
8447 | pat = PATTERN (insn); | |
8448 | if (GET_CODE (pat) == COND_EXEC) | |
8449 | check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), | |
8450 | check_pat); | |
8451 | ||
8452 | return check_pat; | |
8453 | } | |
8454 | ||
8455 | /* Return nonzero, if X is branchy recovery check. */ | |
8456 | static int | |
8457 | ia64_spec_check_p (rtx x) | |
8458 | { | |
8459 | x = PATTERN (x); | |
8460 | if (GET_CODE (x) == COND_EXEC) | |
8461 | x = COND_EXEC_CODE (x); | |
8462 | if (GET_CODE (x) == SET) | |
8463 | return ia64_spec_check_src_p (SET_SRC (x)); | |
8464 | return 0; | |
8465 | } | |
8466 | ||
8467 | /* Return nonzero, if SRC belongs to recovery check. */ | |
8468 | static int | |
8469 | ia64_spec_check_src_p (rtx src) | |
8470 | { | |
8471 | if (GET_CODE (src) == IF_THEN_ELSE) | |
8472 | { | |
8473 | rtx t; | |
8474 | ||
8475 | t = XEXP (src, 0); | |
8476 | if (GET_CODE (t) == NE) | |
8477 | { | |
8478 | t = XEXP (t, 0); | |
8479 | ||
8480 | if (GET_CODE (t) == UNSPEC) | |
8481 | { | |
8482 | int code; | |
8483 | ||
8484 | code = XINT (t, 1); | |
8485 | ||
388092d5 AB |
8486 | if (code == UNSPEC_LDCCLR |
8487 | || code == UNSPEC_LDCNC | |
8488 | || code == UNSPEC_CHKACLR | |
8489 | || code == UNSPEC_CHKANC | |
8490 | || code == UNSPEC_CHKS) | |
048d0d36 MK |
8491 | { |
8492 | gcc_assert (code != 0); | |
8493 | return code; | |
8494 | } | |
8495 | } | |
8496 | } | |
8497 | } | |
8498 | return 0; | |
8499 | } | |
30028c85 | 8500 | \f |
2130b7fb | 8501 | |
30028c85 VM |
8502 | /* The following page contains abstract data `bundle states' which are |
8503 | used for bundling insns (inserting nops and template generation). */ | |
8504 | ||
8505 | /* The following describes state of insn bundling. */ | |
8506 | ||
8507 | struct bundle_state | |
8508 | { | |
8509 | /* Unique bundle state number to identify them in the debugging | |
8510 | output */ | |
8511 | int unique_num; | |
b32d5189 | 8512 | rtx_insn *insn; /* corresponding insn, NULL for the 1st and the last state */ |
30028c85 VM |
8513 | /* number nops before and after the insn */ |
8514 | short before_nops_num, after_nops_num; | |
8515 | int insn_num; /* insn number (0 - for initial state, 1 - for the 1st | |
8516 | insn */ | |
8517 | int cost; /* cost of the state in cycles */ | |
8518 | int accumulated_insns_num; /* number of all previous insns including | |
8519 | nops. L is considered as 2 insns */ | |
8520 | int branch_deviation; /* deviation of previous branches from 3rd slots */ | |
388092d5 | 8521 | int middle_bundle_stops; /* number of stop bits in the middle of bundles */ |
30028c85 VM |
8522 | struct bundle_state *next; /* next state with the same insn_num */ |
8523 | struct bundle_state *originator; /* originator (previous insn state) */ | |
8524 | /* All bundle states are in the following chain. */ | |
8525 | struct bundle_state *allocated_states_chain; | |
8526 | /* The DFA State after issuing the insn and the nops. */ | |
8527 | state_t dfa_state; | |
8528 | }; | |
2130b7fb | 8529 | |
30028c85 | 8530 | /* The following is map insn number to the corresponding bundle state. */ |
2130b7fb | 8531 | |
30028c85 | 8532 | static struct bundle_state **index_to_bundle_states; |
2130b7fb | 8533 | |
30028c85 | 8534 | /* The unique number of next bundle state. */ |
2130b7fb | 8535 | |
30028c85 | 8536 | static int bundle_states_num; |
2130b7fb | 8537 | |
30028c85 | 8538 | /* All allocated bundle states are in the following chain. */ |
2130b7fb | 8539 | |
30028c85 | 8540 | static struct bundle_state *allocated_bundle_states_chain; |
e57b9d65 | 8541 | |
30028c85 VM |
8542 | /* All allocated but not used bundle states are in the following |
8543 | chain. */ | |
870f9ec0 | 8544 | |
30028c85 | 8545 | static struct bundle_state *free_bundle_state_chain; |
2130b7fb | 8546 | |
2130b7fb | 8547 | |
30028c85 | 8548 | /* The following function returns a free bundle state. */ |
2130b7fb | 8549 | |
30028c85 | 8550 | static struct bundle_state * |
9c808aad | 8551 | get_free_bundle_state (void) |
30028c85 VM |
8552 | { |
8553 | struct bundle_state *result; | |
2130b7fb | 8554 | |
30028c85 | 8555 | if (free_bundle_state_chain != NULL) |
2130b7fb | 8556 | { |
30028c85 VM |
8557 | result = free_bundle_state_chain; |
8558 | free_bundle_state_chain = result->next; | |
2130b7fb | 8559 | } |
30028c85 | 8560 | else |
2130b7fb | 8561 | { |
5ead67f6 | 8562 | result = XNEW (struct bundle_state); |
30028c85 VM |
8563 | result->dfa_state = xmalloc (dfa_state_size); |
8564 | result->allocated_states_chain = allocated_bundle_states_chain; | |
8565 | allocated_bundle_states_chain = result; | |
2130b7fb | 8566 | } |
30028c85 VM |
8567 | result->unique_num = bundle_states_num++; |
8568 | return result; | |
9c808aad | 8569 | |
30028c85 | 8570 | } |
2130b7fb | 8571 | |
30028c85 | 8572 | /* The following function frees given bundle state. */ |
2130b7fb | 8573 | |
30028c85 | 8574 | static void |
9c808aad | 8575 | free_bundle_state (struct bundle_state *state) |
30028c85 VM |
8576 | { |
8577 | state->next = free_bundle_state_chain; | |
8578 | free_bundle_state_chain = state; | |
8579 | } | |
2130b7fb | 8580 | |
30028c85 | 8581 | /* Start work with abstract data `bundle states'. */ |
2130b7fb | 8582 | |
30028c85 | 8583 | static void |
9c808aad | 8584 | initiate_bundle_states (void) |
30028c85 VM |
8585 | { |
8586 | bundle_states_num = 0; | |
8587 | free_bundle_state_chain = NULL; | |
8588 | allocated_bundle_states_chain = NULL; | |
2130b7fb BS |
8589 | } |
8590 | ||
30028c85 | 8591 | /* Finish work with abstract data `bundle states'. */ |
2130b7fb BS |
8592 | |
8593 | static void | |
9c808aad | 8594 | finish_bundle_states (void) |
2130b7fb | 8595 | { |
30028c85 VM |
8596 | struct bundle_state *curr_state, *next_state; |
8597 | ||
8598 | for (curr_state = allocated_bundle_states_chain; | |
8599 | curr_state != NULL; | |
8600 | curr_state = next_state) | |
2130b7fb | 8601 | { |
30028c85 VM |
8602 | next_state = curr_state->allocated_states_chain; |
8603 | free (curr_state->dfa_state); | |
8604 | free (curr_state); | |
2130b7fb | 8605 | } |
2130b7fb BS |
8606 | } |
8607 | ||
3a4f280b | 8608 | /* Hashtable helpers. */ |
2130b7fb | 8609 | |
3a4f280b LC |
8610 | struct bundle_state_hasher : typed_noop_remove <bundle_state> |
8611 | { | |
67f58944 TS |
8612 | typedef bundle_state *value_type; |
8613 | typedef bundle_state *compare_type; | |
8614 | static inline hashval_t hash (const bundle_state *); | |
8615 | static inline bool equal (const bundle_state *, const bundle_state *); | |
3a4f280b | 8616 | }; |
2130b7fb | 8617 | |
30028c85 | 8618 | /* The function returns hash of BUNDLE_STATE. */ |
2130b7fb | 8619 | |
3a4f280b | 8620 | inline hashval_t |
67f58944 | 8621 | bundle_state_hasher::hash (const bundle_state *state) |
30028c85 | 8622 | { |
30028c85 | 8623 | unsigned result, i; |
2130b7fb | 8624 | |
30028c85 VM |
8625 | for (result = i = 0; i < dfa_state_size; i++) |
8626 | result += (((unsigned char *) state->dfa_state) [i] | |
8627 | << ((i % CHAR_BIT) * 3 + CHAR_BIT)); | |
8628 | return result + state->insn_num; | |
8629 | } | |
2130b7fb | 8630 | |
30028c85 | 8631 | /* The function returns nonzero if the bundle state keys are equal. */ |
2130b7fb | 8632 | |
3a4f280b | 8633 | inline bool |
67f58944 TS |
8634 | bundle_state_hasher::equal (const bundle_state *state1, |
8635 | const bundle_state *state2) | |
30028c85 | 8636 | { |
30028c85 VM |
8637 | return (state1->insn_num == state2->insn_num |
8638 | && memcmp (state1->dfa_state, state2->dfa_state, | |
8639 | dfa_state_size) == 0); | |
8640 | } | |
2130b7fb | 8641 | |
3a4f280b LC |
8642 | /* Hash table of the bundle states. The key is dfa_state and insn_num |
8643 | of the bundle states. */ | |
8644 | ||
c203e8a7 | 8645 | static hash_table<bundle_state_hasher> *bundle_state_table; |
3a4f280b | 8646 | |
30028c85 VM |
8647 | /* The function inserts the BUNDLE_STATE into the hash table. The |
8648 | function returns nonzero if the bundle has been inserted into the | |
8649 | table. The table contains the best bundle state with given key. */ | |
2130b7fb | 8650 | |
30028c85 | 8651 | static int |
9c808aad | 8652 | insert_bundle_state (struct bundle_state *bundle_state) |
30028c85 | 8653 | { |
3a4f280b | 8654 | struct bundle_state **entry_ptr; |
2130b7fb | 8655 | |
c203e8a7 | 8656 | entry_ptr = bundle_state_table->find_slot (bundle_state, INSERT); |
30028c85 VM |
8657 | if (*entry_ptr == NULL) |
8658 | { | |
8659 | bundle_state->next = index_to_bundle_states [bundle_state->insn_num]; | |
8660 | index_to_bundle_states [bundle_state->insn_num] = bundle_state; | |
3a4f280b | 8661 | *entry_ptr = bundle_state; |
30028c85 | 8662 | return TRUE; |
2130b7fb | 8663 | } |
3a4f280b LC |
8664 | else if (bundle_state->cost < (*entry_ptr)->cost |
8665 | || (bundle_state->cost == (*entry_ptr)->cost | |
8666 | && ((*entry_ptr)->accumulated_insns_num | |
30028c85 | 8667 | > bundle_state->accumulated_insns_num |
3a4f280b | 8668 | || ((*entry_ptr)->accumulated_insns_num |
30028c85 | 8669 | == bundle_state->accumulated_insns_num |
3a4f280b | 8670 | && ((*entry_ptr)->branch_deviation |
388092d5 | 8671 | > bundle_state->branch_deviation |
3a4f280b | 8672 | || ((*entry_ptr)->branch_deviation |
388092d5 | 8673 | == bundle_state->branch_deviation |
3a4f280b | 8674 | && (*entry_ptr)->middle_bundle_stops |
388092d5 | 8675 | > bundle_state->middle_bundle_stops)))))) |
9c808aad | 8676 | |
2130b7fb | 8677 | { |
30028c85 VM |
8678 | struct bundle_state temp; |
8679 | ||
3a4f280b LC |
8680 | temp = **entry_ptr; |
8681 | **entry_ptr = *bundle_state; | |
8682 | (*entry_ptr)->next = temp.next; | |
30028c85 | 8683 | *bundle_state = temp; |
2130b7fb | 8684 | } |
30028c85 VM |
8685 | return FALSE; |
8686 | } | |
2130b7fb | 8687 | |
30028c85 VM |
8688 | /* Start work with the hash table. */ |
8689 | ||
8690 | static void | |
9c808aad | 8691 | initiate_bundle_state_table (void) |
30028c85 | 8692 | { |
c203e8a7 | 8693 | bundle_state_table = new hash_table<bundle_state_hasher> (50); |
2130b7fb BS |
8694 | } |
8695 | ||
30028c85 | 8696 | /* Finish work with the hash table. */ |
e4027dab BS |
8697 | |
8698 | static void | |
9c808aad | 8699 | finish_bundle_state_table (void) |
e4027dab | 8700 | { |
c203e8a7 TS |
8701 | delete bundle_state_table; |
8702 | bundle_state_table = NULL; | |
e4027dab BS |
8703 | } |
8704 | ||
30028c85 | 8705 | \f |
a0a7b566 | 8706 | |
30028c85 VM |
8707 | /* The following variable is a insn `nop' used to check bundle states |
8708 | with different number of inserted nops. */ | |
a0a7b566 | 8709 | |
dd3d2b35 | 8710 | static rtx_insn *ia64_nop; |
a0a7b566 | 8711 | |
30028c85 VM |
8712 | /* The following function tries to issue NOPS_NUM nops for the current |
8713 | state without advancing processor cycle. If it failed, the | |
8714 | function returns FALSE and frees the current state. */ | |
8715 | ||
8716 | static int | |
9c808aad | 8717 | try_issue_nops (struct bundle_state *curr_state, int nops_num) |
a0a7b566 | 8718 | { |
30028c85 | 8719 | int i; |
a0a7b566 | 8720 | |
30028c85 VM |
8721 | for (i = 0; i < nops_num; i++) |
8722 | if (state_transition (curr_state->dfa_state, ia64_nop) >= 0) | |
8723 | { | |
8724 | free_bundle_state (curr_state); | |
8725 | return FALSE; | |
8726 | } | |
8727 | return TRUE; | |
8728 | } | |
a0a7b566 | 8729 | |
30028c85 VM |
8730 | /* The following function tries to issue INSN for the current |
8731 | state without advancing processor cycle. If it failed, the | |
8732 | function returns FALSE and frees the current state. */ | |
a0a7b566 | 8733 | |
30028c85 | 8734 | static int |
9c808aad | 8735 | try_issue_insn (struct bundle_state *curr_state, rtx insn) |
30028c85 VM |
8736 | { |
8737 | if (insn && state_transition (curr_state->dfa_state, insn) >= 0) | |
8738 | { | |
8739 | free_bundle_state (curr_state); | |
8740 | return FALSE; | |
8741 | } | |
8742 | return TRUE; | |
8743 | } | |
a0a7b566 | 8744 | |
30028c85 VM |
8745 | /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN |
8746 | starting with ORIGINATOR without advancing processor cycle. If | |
f32360c7 VM |
8747 | TRY_BUNDLE_END_P is TRUE, the function also/only (if |
8748 | ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle. | |
8749 | If it was successful, the function creates new bundle state and | |
8750 | insert into the hash table and into `index_to_bundle_states'. */ | |
a0a7b566 | 8751 | |
30028c85 | 8752 | static void |
9c808aad | 8753 | issue_nops_and_insn (struct bundle_state *originator, int before_nops_num, |
b32d5189 DM |
8754 | rtx_insn *insn, int try_bundle_end_p, |
8755 | int only_bundle_end_p) | |
30028c85 VM |
8756 | { |
8757 | struct bundle_state *curr_state; | |
8758 | ||
8759 | curr_state = get_free_bundle_state (); | |
8760 | memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size); | |
8761 | curr_state->insn = insn; | |
8762 | curr_state->insn_num = originator->insn_num + 1; | |
8763 | curr_state->cost = originator->cost; | |
8764 | curr_state->originator = originator; | |
8765 | curr_state->before_nops_num = before_nops_num; | |
8766 | curr_state->after_nops_num = 0; | |
8767 | curr_state->accumulated_insns_num | |
8768 | = originator->accumulated_insns_num + before_nops_num; | |
8769 | curr_state->branch_deviation = originator->branch_deviation; | |
388092d5 | 8770 | curr_state->middle_bundle_stops = originator->middle_bundle_stops; |
e820471b NS |
8771 | gcc_assert (insn); |
8772 | if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier) | |
30028c85 | 8773 | { |
e820471b | 8774 | gcc_assert (GET_MODE (insn) != TImode); |
30028c85 VM |
8775 | if (!try_issue_nops (curr_state, before_nops_num)) |
8776 | return; | |
8777 | if (!try_issue_insn (curr_state, insn)) | |
8778 | return; | |
8779 | memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size); | |
388092d5 AB |
8780 | if (curr_state->accumulated_insns_num % 3 != 0) |
8781 | curr_state->middle_bundle_stops++; | |
30028c85 VM |
8782 | if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0 |
8783 | && curr_state->accumulated_insns_num % 3 != 0) | |
a0a7b566 | 8784 | { |
30028c85 VM |
8785 | free_bundle_state (curr_state); |
8786 | return; | |
a0a7b566 | 8787 | } |
a0a7b566 | 8788 | } |
30028c85 | 8789 | else if (GET_MODE (insn) != TImode) |
a0a7b566 | 8790 | { |
30028c85 VM |
8791 | if (!try_issue_nops (curr_state, before_nops_num)) |
8792 | return; | |
8793 | if (!try_issue_insn (curr_state, insn)) | |
8794 | return; | |
f32360c7 | 8795 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8796 | gcc_assert (!unknown_for_bundling_p (insn)); |
e820471b | 8797 | |
30028c85 VM |
8798 | if (ia64_safe_type (insn) == TYPE_L) |
8799 | curr_state->accumulated_insns_num++; | |
8800 | } | |
8801 | else | |
8802 | { | |
68e11b42 JW |
8803 | /* If this is an insn that must be first in a group, then don't allow |
8804 | nops to be emitted before it. Currently, alloc is the only such | |
8805 | supported instruction. */ | |
8806 | /* ??? The bundling automatons should handle this for us, but they do | |
8807 | not yet have support for the first_insn attribute. */ | |
8808 | if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES) | |
8809 | { | |
8810 | free_bundle_state (curr_state); | |
8811 | return; | |
8812 | } | |
8813 | ||
30028c85 VM |
8814 | state_transition (curr_state->dfa_state, dfa_pre_cycle_insn); |
8815 | state_transition (curr_state->dfa_state, NULL); | |
8816 | curr_state->cost++; | |
8817 | if (!try_issue_nops (curr_state, before_nops_num)) | |
8818 | return; | |
8819 | if (!try_issue_insn (curr_state, insn)) | |
8820 | return; | |
f32360c7 | 8821 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8822 | if (unknown_for_bundling_p (insn)) |
f32360c7 VM |
8823 | { |
8824 | /* Finish bundle containing asm insn. */ | |
8825 | curr_state->after_nops_num | |
8826 | = 3 - curr_state->accumulated_insns_num % 3; | |
8827 | curr_state->accumulated_insns_num | |
8828 | += 3 - curr_state->accumulated_insns_num % 3; | |
8829 | } | |
8830 | else if (ia64_safe_type (insn) == TYPE_L) | |
30028c85 VM |
8831 | curr_state->accumulated_insns_num++; |
8832 | } | |
8833 | if (ia64_safe_type (insn) == TYPE_B) | |
8834 | curr_state->branch_deviation | |
8835 | += 2 - (curr_state->accumulated_insns_num - 1) % 3; | |
8836 | if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0) | |
8837 | { | |
f32360c7 | 8838 | if (!only_bundle_end_p && insert_bundle_state (curr_state)) |
a0a7b566 | 8839 | { |
30028c85 VM |
8840 | state_t dfa_state; |
8841 | struct bundle_state *curr_state1; | |
8842 | struct bundle_state *allocated_states_chain; | |
8843 | ||
8844 | curr_state1 = get_free_bundle_state (); | |
8845 | dfa_state = curr_state1->dfa_state; | |
8846 | allocated_states_chain = curr_state1->allocated_states_chain; | |
8847 | *curr_state1 = *curr_state; | |
8848 | curr_state1->dfa_state = dfa_state; | |
8849 | curr_state1->allocated_states_chain = allocated_states_chain; | |
8850 | memcpy (curr_state1->dfa_state, curr_state->dfa_state, | |
8851 | dfa_state_size); | |
8852 | curr_state = curr_state1; | |
a0a7b566 | 8853 | } |
30028c85 VM |
8854 | if (!try_issue_nops (curr_state, |
8855 | 3 - curr_state->accumulated_insns_num % 3)) | |
8856 | return; | |
8857 | curr_state->after_nops_num | |
8858 | = 3 - curr_state->accumulated_insns_num % 3; | |
8859 | curr_state->accumulated_insns_num | |
8860 | += 3 - curr_state->accumulated_insns_num % 3; | |
a0a7b566 | 8861 | } |
30028c85 VM |
8862 | if (!insert_bundle_state (curr_state)) |
8863 | free_bundle_state (curr_state); | |
8864 | return; | |
8865 | } | |
e013f3c7 | 8866 | |
30028c85 VM |
8867 | /* The following function returns position in the two window bundle |
8868 | for given STATE. */ | |
8869 | ||
8870 | static int | |
9c808aad | 8871 | get_max_pos (state_t state) |
30028c85 VM |
8872 | { |
8873 | if (cpu_unit_reservation_p (state, pos_6)) | |
8874 | return 6; | |
8875 | else if (cpu_unit_reservation_p (state, pos_5)) | |
8876 | return 5; | |
8877 | else if (cpu_unit_reservation_p (state, pos_4)) | |
8878 | return 4; | |
8879 | else if (cpu_unit_reservation_p (state, pos_3)) | |
8880 | return 3; | |
8881 | else if (cpu_unit_reservation_p (state, pos_2)) | |
8882 | return 2; | |
8883 | else if (cpu_unit_reservation_p (state, pos_1)) | |
8884 | return 1; | |
8885 | else | |
8886 | return 0; | |
a0a7b566 BS |
8887 | } |
8888 | ||
30028c85 VM |
8889 | /* The function returns code of a possible template for given position |
8890 | and state. The function should be called only with 2 values of | |
96ddf8ef VM |
8891 | position equal to 3 or 6. We avoid generating F NOPs by putting |
8892 | templates containing F insns at the end of the template search | |
8893 | because undocumented anomaly in McKinley derived cores which can | |
8894 | cause stalls if an F-unit insn (including a NOP) is issued within a | |
8895 | six-cycle window after reading certain application registers (such | |
8896 | as ar.bsp). Furthermore, power-considerations also argue against | |
8897 | the use of F-unit instructions unless they're really needed. */ | |
2130b7fb | 8898 | |
c237e94a | 8899 | static int |
9c808aad | 8900 | get_template (state_t state, int pos) |
2130b7fb | 8901 | { |
30028c85 | 8902 | switch (pos) |
2130b7fb | 8903 | { |
30028c85 | 8904 | case 3: |
96ddf8ef | 8905 | if (cpu_unit_reservation_p (state, _0mmi_)) |
30028c85 | 8906 | return 1; |
96ddf8ef VM |
8907 | else if (cpu_unit_reservation_p (state, _0mii_)) |
8908 | return 0; | |
30028c85 VM |
8909 | else if (cpu_unit_reservation_p (state, _0mmb_)) |
8910 | return 7; | |
96ddf8ef VM |
8911 | else if (cpu_unit_reservation_p (state, _0mib_)) |
8912 | return 6; | |
8913 | else if (cpu_unit_reservation_p (state, _0mbb_)) | |
8914 | return 5; | |
8915 | else if (cpu_unit_reservation_p (state, _0bbb_)) | |
8916 | return 4; | |
8917 | else if (cpu_unit_reservation_p (state, _0mmf_)) | |
8918 | return 3; | |
8919 | else if (cpu_unit_reservation_p (state, _0mfi_)) | |
8920 | return 2; | |
30028c85 VM |
8921 | else if (cpu_unit_reservation_p (state, _0mfb_)) |
8922 | return 8; | |
8923 | else if (cpu_unit_reservation_p (state, _0mlx_)) | |
8924 | return 9; | |
8925 | else | |
e820471b | 8926 | gcc_unreachable (); |
30028c85 | 8927 | case 6: |
96ddf8ef | 8928 | if (cpu_unit_reservation_p (state, _1mmi_)) |
30028c85 | 8929 | return 1; |
96ddf8ef VM |
8930 | else if (cpu_unit_reservation_p (state, _1mii_)) |
8931 | return 0; | |
30028c85 VM |
8932 | else if (cpu_unit_reservation_p (state, _1mmb_)) |
8933 | return 7; | |
96ddf8ef VM |
8934 | else if (cpu_unit_reservation_p (state, _1mib_)) |
8935 | return 6; | |
8936 | else if (cpu_unit_reservation_p (state, _1mbb_)) | |
8937 | return 5; | |
8938 | else if (cpu_unit_reservation_p (state, _1bbb_)) | |
8939 | return 4; | |
8940 | else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_)) | |
8941 | return 3; | |
8942 | else if (cpu_unit_reservation_p (state, _1mfi_)) | |
8943 | return 2; | |
30028c85 VM |
8944 | else if (cpu_unit_reservation_p (state, _1mfb_)) |
8945 | return 8; | |
8946 | else if (cpu_unit_reservation_p (state, _1mlx_)) | |
8947 | return 9; | |
8948 | else | |
e820471b | 8949 | gcc_unreachable (); |
30028c85 | 8950 | default: |
e820471b | 8951 | gcc_unreachable (); |
2130b7fb | 8952 | } |
30028c85 | 8953 | } |
2130b7fb | 8954 | |
388092d5 | 8955 | /* True when INSN is important for bundling. */ |
7b84aac0 | 8956 | |
388092d5 | 8957 | static bool |
647d790d | 8958 | important_for_bundling_p (rtx_insn *insn) |
388092d5 AB |
8959 | { |
8960 | return (INSN_P (insn) | |
8961 | && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE | |
8962 | && GET_CODE (PATTERN (insn)) != USE | |
8963 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8964 | } | |
8965 | ||
30028c85 VM |
8966 | /* The following function returns an insn important for insn bundling |
8967 | followed by INSN and before TAIL. */ | |
a0a7b566 | 8968 | |
b32d5189 DM |
8969 | static rtx_insn * |
8970 | get_next_important_insn (rtx_insn *insn, rtx_insn *tail) | |
30028c85 VM |
8971 | { |
8972 | for (; insn && insn != tail; insn = NEXT_INSN (insn)) | |
388092d5 | 8973 | if (important_for_bundling_p (insn)) |
30028c85 | 8974 | return insn; |
b32d5189 | 8975 | return NULL; |
30028c85 VM |
8976 | } |
8977 | ||
7b84aac0 EB |
8978 | /* True when INSN is unknown, but important, for bundling. */ |
8979 | ||
8980 | static bool | |
647d790d | 8981 | unknown_for_bundling_p (rtx_insn *insn) |
7b84aac0 EB |
8982 | { |
8983 | return (INSN_P (insn) | |
8984 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN | |
8985 | && GET_CODE (PATTERN (insn)) != USE | |
8986 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8987 | } | |
8988 | ||
4a4cd49c JJ |
8989 | /* Add a bundle selector TEMPLATE0 before INSN. */ |
8990 | ||
8991 | static void | |
b32d5189 | 8992 | ia64_add_bundle_selector_before (int template0, rtx_insn *insn) |
4a4cd49c JJ |
8993 | { |
8994 | rtx b = gen_bundle_selector (GEN_INT (template0)); | |
8995 | ||
8996 | ia64_emit_insn_before (b, insn); | |
8997 | #if NR_BUNDLES == 10 | |
8998 | if ((template0 == 4 || template0 == 5) | |
d5fabb58 | 8999 | && ia64_except_unwind_info (&global_options) == UI_TARGET) |
4a4cd49c JJ |
9000 | { |
9001 | int i; | |
9002 | rtx note = NULL_RTX; | |
9003 | ||
9004 | /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the | |
9005 | first or second slot. If it is and has REG_EH_NOTE set, copy it | |
9006 | to following nops, as br.call sets rp to the address of following | |
9007 | bundle and therefore an EH region end must be on a bundle | |
9008 | boundary. */ | |
9009 | insn = PREV_INSN (insn); | |
9010 | for (i = 0; i < 3; i++) | |
9011 | { | |
9012 | do | |
9013 | insn = next_active_insn (insn); | |
b64925dc | 9014 | while (NONJUMP_INSN_P (insn) |
4a4cd49c | 9015 | && get_attr_empty (insn) == EMPTY_YES); |
b64925dc | 9016 | if (CALL_P (insn)) |
4a4cd49c JJ |
9017 | note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); |
9018 | else if (note) | |
9019 | { | |
9020 | int code; | |
9021 | ||
9022 | gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop | |
9023 | || code == CODE_FOR_nop_b); | |
9024 | if (find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
9025 | note = NULL_RTX; | |
9026 | else | |
bbbbb16a | 9027 | add_reg_note (insn, REG_EH_REGION, XEXP (note, 0)); |
4a4cd49c JJ |
9028 | } |
9029 | } | |
9030 | } | |
9031 | #endif | |
9032 | } | |
9033 | ||
c856f536 VM |
9034 | /* The following function does insn bundling. Bundling means |
9035 | inserting templates and nop insns to fit insn groups into permitted | |
9036 | templates. Instruction scheduling uses NDFA (non-deterministic | |
9037 | finite automata) encoding informations about the templates and the | |
9038 | inserted nops. Nondeterminism of the automata permits follows | |
9039 | all possible insn sequences very fast. | |
9040 | ||
9041 | Unfortunately it is not possible to get information about inserting | |
9042 | nop insns and used templates from the automata states. The | |
9043 | automata only says that we can issue an insn possibly inserting | |
9044 | some nops before it and using some template. Therefore insn | |
9045 | bundling in this function is implemented by using DFA | |
048d0d36 | 9046 | (deterministic finite automata). We follow all possible insn |
c856f536 VM |
9047 | sequences by inserting 0-2 nops (that is what the NDFA describe for |
9048 | insn scheduling) before/after each insn being bundled. We know the | |
9049 | start of simulated processor cycle from insn scheduling (insn | |
9050 | starting a new cycle has TImode). | |
9051 | ||
9052 | Simple implementation of insn bundling would create enormous | |
9053 | number of possible insn sequences satisfying information about new | |
9054 | cycle ticks taken from the insn scheduling. To make the algorithm | |
9055 | practical we use dynamic programming. Each decision (about | |
9056 | inserting nops and implicitly about previous decisions) is described | |
9057 | by structure bundle_state (see above). If we generate the same | |
9058 | bundle state (key is automaton state after issuing the insns and | |
9059 | nops for it), we reuse already generated one. As consequence we | |
1e5f1716 | 9060 | reject some decisions which cannot improve the solution and |
c856f536 VM |
9061 | reduce memory for the algorithm. |
9062 | ||
9063 | When we reach the end of EBB (extended basic block), we choose the | |
9064 | best sequence and then, moving back in EBB, insert templates for | |
9065 | the best alternative. The templates are taken from querying | |
9066 | automaton state for each insn in chosen bundle states. | |
9067 | ||
9068 | So the algorithm makes two (forward and backward) passes through | |
7400e46b | 9069 | EBB. */ |
a0a7b566 | 9070 | |
30028c85 | 9071 | static void |
b32d5189 | 9072 | bundling (FILE *dump, int verbose, rtx_insn *prev_head_insn, rtx_insn *tail) |
30028c85 VM |
9073 | { |
9074 | struct bundle_state *curr_state, *next_state, *best_state; | |
b32d5189 | 9075 | rtx_insn *insn, *next_insn; |
30028c85 | 9076 | int insn_num; |
f32360c7 | 9077 | int i, bundle_end_p, only_bundle_end_p, asm_p; |
74601584 | 9078 | int pos = 0, max_pos, template0, template1; |
b32d5189 | 9079 | rtx_insn *b; |
30028c85 | 9080 | enum attr_type type; |
2d1b811d | 9081 | |
30028c85 | 9082 | insn_num = 0; |
c856f536 | 9083 | /* Count insns in the EBB. */ |
30028c85 VM |
9084 | for (insn = NEXT_INSN (prev_head_insn); |
9085 | insn && insn != tail; | |
9086 | insn = NEXT_INSN (insn)) | |
9087 | if (INSN_P (insn)) | |
9088 | insn_num++; | |
9089 | if (insn_num == 0) | |
9090 | return; | |
9091 | bundling_p = 1; | |
9092 | dfa_clean_insn_cache (); | |
9093 | initiate_bundle_state_table (); | |
5ead67f6 | 9094 | index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2); |
ff482c8d | 9095 | /* First (forward) pass -- generation of bundle states. */ |
30028c85 VM |
9096 | curr_state = get_free_bundle_state (); |
9097 | curr_state->insn = NULL; | |
9098 | curr_state->before_nops_num = 0; | |
9099 | curr_state->after_nops_num = 0; | |
9100 | curr_state->insn_num = 0; | |
9101 | curr_state->cost = 0; | |
9102 | curr_state->accumulated_insns_num = 0; | |
9103 | curr_state->branch_deviation = 0; | |
388092d5 | 9104 | curr_state->middle_bundle_stops = 0; |
30028c85 VM |
9105 | curr_state->next = NULL; |
9106 | curr_state->originator = NULL; | |
9107 | state_reset (curr_state->dfa_state); | |
9108 | index_to_bundle_states [0] = curr_state; | |
9109 | insn_num = 0; | |
c856f536 | 9110 | /* Shift cycle mark if it is put on insn which could be ignored. */ |
30028c85 VM |
9111 | for (insn = NEXT_INSN (prev_head_insn); |
9112 | insn != tail; | |
9113 | insn = NEXT_INSN (insn)) | |
9114 | if (INSN_P (insn) | |
7b84aac0 | 9115 | && !important_for_bundling_p (insn) |
30028c85 | 9116 | && GET_MODE (insn) == TImode) |
2130b7fb | 9117 | { |
30028c85 VM |
9118 | PUT_MODE (insn, VOIDmode); |
9119 | for (next_insn = NEXT_INSN (insn); | |
9120 | next_insn != tail; | |
9121 | next_insn = NEXT_INSN (next_insn)) | |
7b84aac0 | 9122 | if (important_for_bundling_p (next_insn) |
388092d5 | 9123 | && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier) |
30028c85 VM |
9124 | { |
9125 | PUT_MODE (next_insn, TImode); | |
9126 | break; | |
9127 | } | |
2130b7fb | 9128 | } |
048d0d36 | 9129 | /* Forward pass: generation of bundle states. */ |
30028c85 VM |
9130 | for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail); |
9131 | insn != NULL_RTX; | |
9132 | insn = next_insn) | |
1ad72cef | 9133 | { |
7b84aac0 | 9134 | gcc_assert (important_for_bundling_p (insn)); |
f32360c7 | 9135 | type = ia64_safe_type (insn); |
30028c85 VM |
9136 | next_insn = get_next_important_insn (NEXT_INSN (insn), tail); |
9137 | insn_num++; | |
9138 | index_to_bundle_states [insn_num] = NULL; | |
9139 | for (curr_state = index_to_bundle_states [insn_num - 1]; | |
9140 | curr_state != NULL; | |
9141 | curr_state = next_state) | |
f83594c4 | 9142 | { |
30028c85 | 9143 | pos = curr_state->accumulated_insns_num % 3; |
30028c85 | 9144 | next_state = curr_state->next; |
c856f536 VM |
9145 | /* We must fill up the current bundle in order to start a |
9146 | subsequent asm insn in a new bundle. Asm insn is always | |
9147 | placed in a separate bundle. */ | |
f32360c7 VM |
9148 | only_bundle_end_p |
9149 | = (next_insn != NULL_RTX | |
9150 | && INSN_CODE (insn) == CODE_FOR_insn_group_barrier | |
7b84aac0 | 9151 | && unknown_for_bundling_p (next_insn)); |
c856f536 VM |
9152 | /* We may fill up the current bundle if it is the cycle end |
9153 | without a group barrier. */ | |
30028c85 | 9154 | bundle_end_p |
f32360c7 | 9155 | = (only_bundle_end_p || next_insn == NULL_RTX |
30028c85 VM |
9156 | || (GET_MODE (next_insn) == TImode |
9157 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier)); | |
9158 | if (type == TYPE_F || type == TYPE_B || type == TYPE_L | |
7400e46b | 9159 | || type == TYPE_S) |
f32360c7 VM |
9160 | issue_nops_and_insn (curr_state, 2, insn, bundle_end_p, |
9161 | only_bundle_end_p); | |
9162 | issue_nops_and_insn (curr_state, 1, insn, bundle_end_p, | |
9163 | only_bundle_end_p); | |
9164 | issue_nops_and_insn (curr_state, 0, insn, bundle_end_p, | |
9165 | only_bundle_end_p); | |
f83594c4 | 9166 | } |
e820471b | 9167 | gcc_assert (index_to_bundle_states [insn_num]); |
30028c85 VM |
9168 | for (curr_state = index_to_bundle_states [insn_num]; |
9169 | curr_state != NULL; | |
9170 | curr_state = curr_state->next) | |
9171 | if (verbose >= 2 && dump) | |
9172 | { | |
c856f536 VM |
9173 | /* This structure is taken from generated code of the |
9174 | pipeline hazard recognizer (see file insn-attrtab.c). | |
9175 | Please don't forget to change the structure if a new | |
9176 | automaton is added to .md file. */ | |
30028c85 VM |
9177 | struct DFA_chip |
9178 | { | |
9179 | unsigned short one_automaton_state; | |
9180 | unsigned short oneb_automaton_state; | |
9181 | unsigned short two_automaton_state; | |
9182 | unsigned short twob_automaton_state; | |
9183 | }; | |
9c808aad | 9184 | |
30028c85 VM |
9185 | fprintf |
9186 | (dump, | |
388092d5 | 9187 | "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n", |
30028c85 VM |
9188 | curr_state->unique_num, |
9189 | (curr_state->originator == NULL | |
9190 | ? -1 : curr_state->originator->unique_num), | |
9191 | curr_state->cost, | |
9192 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9193 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9194 | curr_state->middle_bundle_stops, |
7400e46b | 9195 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 VM |
9196 | INSN_UID (insn)); |
9197 | } | |
1ad72cef | 9198 | } |
e820471b NS |
9199 | |
9200 | /* We should find a solution because the 2nd insn scheduling has | |
9201 | found one. */ | |
9202 | gcc_assert (index_to_bundle_states [insn_num]); | |
c856f536 | 9203 | /* Find a state corresponding to the best insn sequence. */ |
30028c85 VM |
9204 | best_state = NULL; |
9205 | for (curr_state = index_to_bundle_states [insn_num]; | |
9206 | curr_state != NULL; | |
9207 | curr_state = curr_state->next) | |
c856f536 VM |
9208 | /* We are just looking at the states with fully filled up last |
9209 | bundle. The first we prefer insn sequences with minimal cost | |
9210 | then with minimal inserted nops and finally with branch insns | |
9211 | placed in the 3rd slots. */ | |
30028c85 VM |
9212 | if (curr_state->accumulated_insns_num % 3 == 0 |
9213 | && (best_state == NULL || best_state->cost > curr_state->cost | |
9214 | || (best_state->cost == curr_state->cost | |
9215 | && (curr_state->accumulated_insns_num | |
9216 | < best_state->accumulated_insns_num | |
9217 | || (curr_state->accumulated_insns_num | |
9218 | == best_state->accumulated_insns_num | |
388092d5 AB |
9219 | && (curr_state->branch_deviation |
9220 | < best_state->branch_deviation | |
9221 | || (curr_state->branch_deviation | |
9222 | == best_state->branch_deviation | |
9223 | && curr_state->middle_bundle_stops | |
9224 | < best_state->middle_bundle_stops))))))) | |
30028c85 | 9225 | best_state = curr_state; |
c856f536 | 9226 | /* Second (backward) pass: adding nops and templates. */ |
388092d5 | 9227 | gcc_assert (best_state); |
30028c85 VM |
9228 | insn_num = best_state->before_nops_num; |
9229 | template0 = template1 = -1; | |
9230 | for (curr_state = best_state; | |
9231 | curr_state->originator != NULL; | |
9232 | curr_state = curr_state->originator) | |
9233 | { | |
9234 | insn = curr_state->insn; | |
7b84aac0 | 9235 | asm_p = unknown_for_bundling_p (insn); |
30028c85 VM |
9236 | insn_num++; |
9237 | if (verbose >= 2 && dump) | |
2130b7fb | 9238 | { |
30028c85 VM |
9239 | struct DFA_chip |
9240 | { | |
9241 | unsigned short one_automaton_state; | |
9242 | unsigned short oneb_automaton_state; | |
9243 | unsigned short two_automaton_state; | |
9244 | unsigned short twob_automaton_state; | |
9245 | }; | |
9c808aad | 9246 | |
30028c85 VM |
9247 | fprintf |
9248 | (dump, | |
388092d5 | 9249 | "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n", |
30028c85 VM |
9250 | curr_state->unique_num, |
9251 | (curr_state->originator == NULL | |
9252 | ? -1 : curr_state->originator->unique_num), | |
9253 | curr_state->cost, | |
9254 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9255 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9256 | curr_state->middle_bundle_stops, |
7400e46b | 9257 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 | 9258 | INSN_UID (insn)); |
2130b7fb | 9259 | } |
c856f536 VM |
9260 | /* Find the position in the current bundle window. The window can |
9261 | contain at most two bundles. Two bundle window means that | |
9262 | the processor will make two bundle rotation. */ | |
30028c85 | 9263 | max_pos = get_max_pos (curr_state->dfa_state); |
c856f536 VM |
9264 | if (max_pos == 6 |
9265 | /* The following (negative template number) means that the | |
9266 | processor did one bundle rotation. */ | |
9267 | || (max_pos == 3 && template0 < 0)) | |
2130b7fb | 9268 | { |
c856f536 VM |
9269 | /* We are at the end of the window -- find template(s) for |
9270 | its bundle(s). */ | |
30028c85 VM |
9271 | pos = max_pos; |
9272 | if (max_pos == 3) | |
9273 | template0 = get_template (curr_state->dfa_state, 3); | |
9274 | else | |
9275 | { | |
9276 | template1 = get_template (curr_state->dfa_state, 3); | |
9277 | template0 = get_template (curr_state->dfa_state, 6); | |
9278 | } | |
9279 | } | |
9280 | if (max_pos > 3 && template1 < 0) | |
c856f536 | 9281 | /* It may happen when we have the stop inside a bundle. */ |
30028c85 | 9282 | { |
e820471b | 9283 | gcc_assert (pos <= 3); |
30028c85 VM |
9284 | template1 = get_template (curr_state->dfa_state, 3); |
9285 | pos += 3; | |
9286 | } | |
f32360c7 | 9287 | if (!asm_p) |
c856f536 | 9288 | /* Emit nops after the current insn. */ |
f32360c7 VM |
9289 | for (i = 0; i < curr_state->after_nops_num; i++) |
9290 | { | |
b32d5189 DM |
9291 | rtx nop_pat = gen_nop (); |
9292 | rtx_insn *nop = emit_insn_after (nop_pat, insn); | |
f32360c7 | 9293 | pos--; |
e820471b | 9294 | gcc_assert (pos >= 0); |
f32360c7 VM |
9295 | if (pos % 3 == 0) |
9296 | { | |
c856f536 VM |
9297 | /* We are at the start of a bundle: emit the template |
9298 | (it should be defined). */ | |
e820471b | 9299 | gcc_assert (template0 >= 0); |
4a4cd49c | 9300 | ia64_add_bundle_selector_before (template0, nop); |
c856f536 VM |
9301 | /* If we have two bundle window, we make one bundle |
9302 | rotation. Otherwise template0 will be undefined | |
9303 | (negative value). */ | |
f32360c7 VM |
9304 | template0 = template1; |
9305 | template1 = -1; | |
9306 | } | |
9307 | } | |
c856f536 VM |
9308 | /* Move the position backward in the window. Group barrier has |
9309 | no slot. Asm insn takes all bundle. */ | |
30028c85 | 9310 | if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier |
7b84aac0 | 9311 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9312 | pos--; |
c856f536 | 9313 | /* Long insn takes 2 slots. */ |
30028c85 VM |
9314 | if (ia64_safe_type (insn) == TYPE_L) |
9315 | pos--; | |
e820471b | 9316 | gcc_assert (pos >= 0); |
30028c85 VM |
9317 | if (pos % 3 == 0 |
9318 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier | |
7b84aac0 | 9319 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9320 | { |
c856f536 VM |
9321 | /* The current insn is at the bundle start: emit the |
9322 | template. */ | |
e820471b | 9323 | gcc_assert (template0 >= 0); |
4a4cd49c | 9324 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9325 | b = PREV_INSN (insn); |
9326 | insn = b; | |
68776c43 | 9327 | /* See comment above in analogous place for emitting nops |
c856f536 | 9328 | after the insn. */ |
30028c85 VM |
9329 | template0 = template1; |
9330 | template1 = -1; | |
9331 | } | |
c856f536 | 9332 | /* Emit nops after the current insn. */ |
30028c85 VM |
9333 | for (i = 0; i < curr_state->before_nops_num; i++) |
9334 | { | |
b32d5189 DM |
9335 | rtx nop_pat = gen_nop (); |
9336 | ia64_emit_insn_before (nop_pat, insn); | |
9337 | rtx_insn *nop = PREV_INSN (insn); | |
30028c85 VM |
9338 | insn = nop; |
9339 | pos--; | |
e820471b | 9340 | gcc_assert (pos >= 0); |
30028c85 VM |
9341 | if (pos % 3 == 0) |
9342 | { | |
68776c43 | 9343 | /* See comment above in analogous place for emitting nops |
c856f536 | 9344 | after the insn. */ |
e820471b | 9345 | gcc_assert (template0 >= 0); |
4a4cd49c | 9346 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9347 | b = PREV_INSN (insn); |
9348 | insn = b; | |
9349 | template0 = template1; | |
9350 | template1 = -1; | |
9351 | } | |
2130b7fb BS |
9352 | } |
9353 | } | |
388092d5 AB |
9354 | |
9355 | #ifdef ENABLE_CHECKING | |
9356 | { | |
9357 | /* Assert right calculation of middle_bundle_stops. */ | |
9358 | int num = best_state->middle_bundle_stops; | |
9359 | bool start_bundle = true, end_bundle = false; | |
9360 | ||
9361 | for (insn = NEXT_INSN (prev_head_insn); | |
9362 | insn && insn != tail; | |
9363 | insn = NEXT_INSN (insn)) | |
9364 | { | |
9365 | if (!INSN_P (insn)) | |
9366 | continue; | |
9367 | if (recog_memoized (insn) == CODE_FOR_bundle_selector) | |
9368 | start_bundle = true; | |
9369 | else | |
9370 | { | |
b32d5189 | 9371 | rtx_insn *next_insn; |
388092d5 AB |
9372 | |
9373 | for (next_insn = NEXT_INSN (insn); | |
9374 | next_insn && next_insn != tail; | |
9375 | next_insn = NEXT_INSN (next_insn)) | |
9376 | if (INSN_P (next_insn) | |
9377 | && (ia64_safe_itanium_class (next_insn) | |
9378 | != ITANIUM_CLASS_IGNORE | |
9379 | || recog_memoized (next_insn) | |
9380 | == CODE_FOR_bundle_selector) | |
9381 | && GET_CODE (PATTERN (next_insn)) != USE | |
9382 | && GET_CODE (PATTERN (next_insn)) != CLOBBER) | |
9383 | break; | |
9384 | ||
9385 | end_bundle = next_insn == NULL_RTX | |
9386 | || next_insn == tail | |
9387 | || (INSN_P (next_insn) | |
9388 | && recog_memoized (next_insn) | |
9389 | == CODE_FOR_bundle_selector); | |
9390 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier | |
9391 | && !start_bundle && !end_bundle | |
9392 | && next_insn | |
7b84aac0 | 9393 | && !unknown_for_bundling_p (next_insn)) |
388092d5 AB |
9394 | num--; |
9395 | ||
9396 | start_bundle = false; | |
9397 | } | |
9398 | } | |
9399 | ||
9400 | gcc_assert (num == 0); | |
9401 | } | |
9402 | #endif | |
9403 | ||
30028c85 VM |
9404 | free (index_to_bundle_states); |
9405 | finish_bundle_state_table (); | |
9406 | bundling_p = 0; | |
9407 | dfa_clean_insn_cache (); | |
2130b7fb | 9408 | } |
c65ebc55 | 9409 | |
30028c85 VM |
9410 | /* The following function is called at the end of scheduling BB or |
9411 | EBB. After reload, it inserts stop bits and does insn bundling. */ | |
9412 | ||
9413 | static void | |
9c808aad | 9414 | ia64_sched_finish (FILE *dump, int sched_verbose) |
c237e94a | 9415 | { |
30028c85 VM |
9416 | if (sched_verbose) |
9417 | fprintf (dump, "// Finishing schedule.\n"); | |
9418 | if (!reload_completed) | |
9419 | return; | |
9420 | if (reload_completed) | |
9421 | { | |
9422 | final_emit_insn_group_barriers (dump); | |
9423 | bundling (dump, sched_verbose, current_sched_info->prev_head, | |
9424 | current_sched_info->next_tail); | |
9425 | if (sched_verbose && dump) | |
9426 | fprintf (dump, "// finishing %d-%d\n", | |
9427 | INSN_UID (NEXT_INSN (current_sched_info->prev_head)), | |
9428 | INSN_UID (PREV_INSN (current_sched_info->next_tail))); | |
9c808aad | 9429 | |
30028c85 VM |
9430 | return; |
9431 | } | |
c237e94a ZW |
9432 | } |
9433 | ||
30028c85 | 9434 | /* The following function inserts stop bits in scheduled BB or EBB. */ |
2130b7fb | 9435 | |
30028c85 | 9436 | static void |
9c808aad | 9437 | final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
2130b7fb | 9438 | { |
dd3d2b35 | 9439 | rtx_insn *insn; |
30028c85 | 9440 | int need_barrier_p = 0; |
388092d5 | 9441 | int seen_good_insn = 0; |
2130b7fb | 9442 | |
30028c85 | 9443 | init_insn_group_barriers (); |
2130b7fb | 9444 | |
30028c85 VM |
9445 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
9446 | insn != current_sched_info->next_tail; | |
9447 | insn = NEXT_INSN (insn)) | |
9448 | { | |
b64925dc | 9449 | if (BARRIER_P (insn)) |
b395ddbe | 9450 | { |
dd3d2b35 | 9451 | rtx_insn *last = prev_active_insn (insn); |
14d118d6 | 9452 | |
30028c85 | 9453 | if (! last) |
b395ddbe | 9454 | continue; |
34f0d87a | 9455 | if (JUMP_TABLE_DATA_P (last)) |
30028c85 VM |
9456 | last = prev_active_insn (last); |
9457 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9458 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
2130b7fb | 9459 | |
30028c85 | 9460 | init_insn_group_barriers (); |
388092d5 | 9461 | seen_good_insn = 0; |
30028c85 | 9462 | need_barrier_p = 0; |
b395ddbe | 9463 | } |
b5b8b0ac | 9464 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb | 9465 | { |
30028c85 | 9466 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
2130b7fb | 9467 | { |
30028c85 | 9468 | init_insn_group_barriers (); |
388092d5 | 9469 | seen_good_insn = 0; |
30028c85 | 9470 | need_barrier_p = 0; |
c65ebc55 | 9471 | } |
388092d5 AB |
9472 | else if (need_barrier_p || group_barrier_needed (insn) |
9473 | || (mflag_sched_stop_bits_after_every_cycle | |
9474 | && GET_MODE (insn) == TImode | |
9475 | && seen_good_insn)) | |
2130b7fb | 9476 | { |
30028c85 VM |
9477 | if (TARGET_EARLY_STOP_BITS) |
9478 | { | |
dd3d2b35 | 9479 | rtx_insn *last; |
9c808aad | 9480 | |
30028c85 VM |
9481 | for (last = insn; |
9482 | last != current_sched_info->prev_head; | |
9483 | last = PREV_INSN (last)) | |
9484 | if (INSN_P (last) && GET_MODE (last) == TImode | |
9485 | && stops_p [INSN_UID (last)]) | |
9486 | break; | |
9487 | if (last == current_sched_info->prev_head) | |
9488 | last = insn; | |
9489 | last = prev_active_insn (last); | |
9490 | if (last | |
9491 | && recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9492 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), | |
9493 | last); | |
9494 | init_insn_group_barriers (); | |
9495 | for (last = NEXT_INSN (last); | |
9496 | last != insn; | |
9497 | last = NEXT_INSN (last)) | |
9498 | if (INSN_P (last)) | |
388092d5 AB |
9499 | { |
9500 | group_barrier_needed (last); | |
9501 | if (recog_memoized (last) >= 0 | |
9502 | && important_for_bundling_p (last)) | |
9503 | seen_good_insn = 1; | |
9504 | } | |
30028c85 VM |
9505 | } |
9506 | else | |
9507 | { | |
9508 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), | |
9509 | insn); | |
9510 | init_insn_group_barriers (); | |
388092d5 | 9511 | seen_good_insn = 0; |
30028c85 | 9512 | } |
c1bc6ca8 | 9513 | group_barrier_needed (insn); |
388092d5 AB |
9514 | if (recog_memoized (insn) >= 0 |
9515 | && important_for_bundling_p (insn)) | |
9516 | seen_good_insn = 1; | |
2130b7fb | 9517 | } |
388092d5 AB |
9518 | else if (recog_memoized (insn) >= 0 |
9519 | && important_for_bundling_p (insn)) | |
034288ef | 9520 | seen_good_insn = 1; |
b64925dc | 9521 | need_barrier_p = (CALL_P (insn) || unknown_for_bundling_p (insn)); |
c65ebc55 | 9522 | } |
2130b7fb | 9523 | } |
30028c85 | 9524 | } |
2130b7fb | 9525 | |
30028c85 | 9526 | \f |
2130b7fb | 9527 | |
a4d05547 | 9528 | /* If the following function returns TRUE, we will use the DFA |
30028c85 | 9529 | insn scheduler. */ |
2130b7fb | 9530 | |
c237e94a | 9531 | static int |
9c808aad | 9532 | ia64_first_cycle_multipass_dfa_lookahead (void) |
2130b7fb | 9533 | { |
30028c85 VM |
9534 | return (reload_completed ? 6 : 4); |
9535 | } | |
2130b7fb | 9536 | |
30028c85 | 9537 | /* The following function initiates variable `dfa_pre_cycle_insn'. */ |
2130b7fb | 9538 | |
30028c85 | 9539 | static void |
9c808aad | 9540 | ia64_init_dfa_pre_cycle_insn (void) |
30028c85 VM |
9541 | { |
9542 | if (temp_dfa_state == NULL) | |
2130b7fb | 9543 | { |
30028c85 VM |
9544 | dfa_state_size = state_size (); |
9545 | temp_dfa_state = xmalloc (dfa_state_size); | |
9546 | prev_cycle_state = xmalloc (dfa_state_size); | |
2130b7fb | 9547 | } |
30028c85 | 9548 | dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ()); |
0f82e5c9 | 9549 | SET_PREV_INSN (dfa_pre_cycle_insn) = SET_NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX; |
30028c85 VM |
9550 | recog_memoized (dfa_pre_cycle_insn); |
9551 | dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3))); | |
0f82e5c9 | 9552 | SET_PREV_INSN (dfa_stop_insn) = SET_NEXT_INSN (dfa_stop_insn) = NULL_RTX; |
30028c85 VM |
9553 | recog_memoized (dfa_stop_insn); |
9554 | } | |
2130b7fb | 9555 | |
30028c85 VM |
9556 | /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN |
9557 | used by the DFA insn scheduler. */ | |
2130b7fb | 9558 | |
30028c85 | 9559 | static rtx |
9c808aad | 9560 | ia64_dfa_pre_cycle_insn (void) |
30028c85 VM |
9561 | { |
9562 | return dfa_pre_cycle_insn; | |
9563 | } | |
2130b7fb | 9564 | |
30028c85 VM |
9565 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9566 | ld) produces address for CONSUMER (of type st or stf). */ | |
2130b7fb | 9567 | |
30028c85 | 9568 | int |
647d790d | 9569 | ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) |
30028c85 VM |
9570 | { |
9571 | rtx dest, reg, mem; | |
2130b7fb | 9572 | |
e820471b | 9573 | gcc_assert (producer && consumer); |
30028c85 | 9574 | dest = ia64_single_set (producer); |
e820471b NS |
9575 | gcc_assert (dest); |
9576 | reg = SET_DEST (dest); | |
9577 | gcc_assert (reg); | |
30028c85 VM |
9578 | if (GET_CODE (reg) == SUBREG) |
9579 | reg = SUBREG_REG (reg); | |
e820471b NS |
9580 | gcc_assert (GET_CODE (reg) == REG); |
9581 | ||
30028c85 | 9582 | dest = ia64_single_set (consumer); |
e820471b NS |
9583 | gcc_assert (dest); |
9584 | mem = SET_DEST (dest); | |
9585 | gcc_assert (mem && GET_CODE (mem) == MEM); | |
30028c85 | 9586 | return reg_mentioned_p (reg, mem); |
2130b7fb BS |
9587 | } |
9588 | ||
30028c85 VM |
9589 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9590 | ld) produces address for CONSUMER (of type ld or fld). */ | |
2130b7fb | 9591 | |
30028c85 | 9592 | int |
647d790d | 9593 | ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer) |
2130b7fb | 9594 | { |
30028c85 VM |
9595 | rtx dest, src, reg, mem; |
9596 | ||
e820471b | 9597 | gcc_assert (producer && consumer); |
30028c85 | 9598 | dest = ia64_single_set (producer); |
e820471b NS |
9599 | gcc_assert (dest); |
9600 | reg = SET_DEST (dest); | |
9601 | gcc_assert (reg); | |
30028c85 VM |
9602 | if (GET_CODE (reg) == SUBREG) |
9603 | reg = SUBREG_REG (reg); | |
e820471b NS |
9604 | gcc_assert (GET_CODE (reg) == REG); |
9605 | ||
30028c85 | 9606 | src = ia64_single_set (consumer); |
e820471b NS |
9607 | gcc_assert (src); |
9608 | mem = SET_SRC (src); | |
9609 | gcc_assert (mem); | |
048d0d36 | 9610 | |
30028c85 VM |
9611 | if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0) |
9612 | mem = XVECEXP (mem, 0, 0); | |
048d0d36 | 9613 | else if (GET_CODE (mem) == IF_THEN_ELSE) |
917f1b7e | 9614 | /* ??? Is this bypass necessary for ld.c? */ |
048d0d36 MK |
9615 | { |
9616 | gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR); | |
9617 | mem = XEXP (mem, 1); | |
9618 | } | |
9619 | ||
30028c85 VM |
9620 | while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND) |
9621 | mem = XEXP (mem, 0); | |
ef1ecf87 | 9622 | |
048d0d36 MK |
9623 | if (GET_CODE (mem) == UNSPEC) |
9624 | { | |
9625 | int c = XINT (mem, 1); | |
9626 | ||
388092d5 AB |
9627 | gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A |
9628 | || c == UNSPEC_LDSA); | |
048d0d36 MK |
9629 | mem = XVECEXP (mem, 0, 0); |
9630 | } | |
9631 | ||
ef1ecf87 | 9632 | /* Note that LO_SUM is used for GOT loads. */ |
e820471b | 9633 | gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM); |
ef1ecf87 | 9634 | |
30028c85 VM |
9635 | return reg_mentioned_p (reg, mem); |
9636 | } | |
9637 | ||
9638 | /* The following function returns TRUE if INSN produces address for a | |
9639 | load/store insn. We will place such insns into M slot because it | |
ff482c8d | 9640 | decreases its latency time. */ |
30028c85 VM |
9641 | |
9642 | int | |
9c808aad | 9643 | ia64_produce_address_p (rtx insn) |
30028c85 VM |
9644 | { |
9645 | return insn->call; | |
2130b7fb | 9646 | } |
30028c85 | 9647 | |
2130b7fb | 9648 | \f |
3b572406 RH |
9649 | /* Emit pseudo-ops for the assembler to describe predicate relations. |
9650 | At present this assumes that we only consider predicate pairs to | |
9651 | be mutex, and that the assembler can deduce proper values from | |
9652 | straight-line code. */ | |
9653 | ||
9654 | static void | |
9c808aad | 9655 | emit_predicate_relation_info (void) |
3b572406 | 9656 | { |
e0082a72 | 9657 | basic_block bb; |
3b572406 | 9658 | |
4f42035e | 9659 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
3b572406 | 9660 | { |
3b572406 | 9661 | int r; |
dd3d2b35 | 9662 | rtx_insn *head = BB_HEAD (bb); |
3b572406 RH |
9663 | |
9664 | /* We only need such notes at code labels. */ | |
b64925dc | 9665 | if (! LABEL_P (head)) |
3b572406 | 9666 | continue; |
740aeb38 | 9667 | if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head))) |
3b572406 RH |
9668 | head = NEXT_INSN (head); |
9669 | ||
9f3b8452 RH |
9670 | /* Skip p0, which may be thought to be live due to (reg:DI p0) |
9671 | grabbing the entire block of predicate registers. */ | |
9672 | for (r = PR_REG (2); r < PR_REG (64); r += 2) | |
6fb5fa3c | 9673 | if (REGNO_REG_SET_P (df_get_live_in (bb), r)) |
3b572406 | 9674 | { |
f2f90c63 | 9675 | rtx p = gen_rtx_REG (BImode, r); |
dd3d2b35 | 9676 | rtx_insn *n = emit_insn_after (gen_pred_rel_mutex (p), head); |
a813c111 | 9677 | if (head == BB_END (bb)) |
1130d5e3 | 9678 | BB_END (bb) = n; |
3b572406 RH |
9679 | head = n; |
9680 | } | |
9681 | } | |
ca3920ad JW |
9682 | |
9683 | /* Look for conditional calls that do not return, and protect predicate | |
9684 | relations around them. Otherwise the assembler will assume the call | |
9685 | returns, and complain about uses of call-clobbered predicates after | |
9686 | the call. */ | |
4f42035e | 9687 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
ca3920ad | 9688 | { |
dd3d2b35 | 9689 | rtx_insn *insn = BB_HEAD (bb); |
9c808aad | 9690 | |
ca3920ad JW |
9691 | while (1) |
9692 | { | |
b64925dc | 9693 | if (CALL_P (insn) |
ca3920ad JW |
9694 | && GET_CODE (PATTERN (insn)) == COND_EXEC |
9695 | && find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
9696 | { | |
dd3d2b35 DM |
9697 | rtx_insn *b = |
9698 | emit_insn_before (gen_safe_across_calls_all (), insn); | |
9699 | rtx_insn *a = emit_insn_after (gen_safe_across_calls_normal (), insn); | |
a813c111 | 9700 | if (BB_HEAD (bb) == insn) |
1130d5e3 | 9701 | BB_HEAD (bb) = b; |
a813c111 | 9702 | if (BB_END (bb) == insn) |
1130d5e3 | 9703 | BB_END (bb) = a; |
ca3920ad | 9704 | } |
9c808aad | 9705 | |
a813c111 | 9706 | if (insn == BB_END (bb)) |
ca3920ad JW |
9707 | break; |
9708 | insn = NEXT_INSN (insn); | |
9709 | } | |
9710 | } | |
3b572406 RH |
9711 | } |
9712 | ||
c65ebc55 JW |
9713 | /* Perform machine dependent operations on the rtl chain INSNS. */ |
9714 | ||
18dbd950 | 9715 | static void |
9c808aad | 9716 | ia64_reorg (void) |
c65ebc55 | 9717 | { |
1e3881c2 JH |
9718 | /* We are freeing block_for_insn in the toplev to keep compatibility |
9719 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
852c6ec7 | 9720 | compute_bb_for_insn (); |
a00fe19f RH |
9721 | |
9722 | /* If optimizing, we'll have split before scheduling. */ | |
9723 | if (optimize == 0) | |
6fb5fa3c | 9724 | split_all_insns (); |
2130b7fb | 9725 | |
2ba42841 | 9726 | if (optimize && flag_schedule_insns_after_reload |
388092d5 | 9727 | && dbg_cnt (ia64_sched2)) |
f4d578da | 9728 | { |
547fdef8 | 9729 | basic_block bb; |
eced69b5 | 9730 | timevar_push (TV_SCHED2); |
f4d578da | 9731 | ia64_final_schedule = 1; |
30028c85 | 9732 | |
547fdef8 BS |
9733 | /* We can't let modulo-sched prevent us from scheduling any bbs, |
9734 | since we need the final schedule to produce bundle information. */ | |
11cd3bed | 9735 | FOR_EACH_BB_FN (bb, cfun) |
547fdef8 BS |
9736 | bb->flags &= ~BB_DISABLE_SCHEDULE; |
9737 | ||
30028c85 VM |
9738 | initiate_bundle_states (); |
9739 | ia64_nop = make_insn_raw (gen_nop ()); | |
0f82e5c9 | 9740 | SET_PREV_INSN (ia64_nop) = SET_NEXT_INSN (ia64_nop) = NULL_RTX; |
30028c85 VM |
9741 | recog_memoized (ia64_nop); |
9742 | clocks_length = get_max_uid () + 1; | |
5ead67f6 | 9743 | stops_p = XCNEWVEC (char, clocks_length); |
7400e46b | 9744 | |
30028c85 VM |
9745 | if (ia64_tune == PROCESSOR_ITANIUM2) |
9746 | { | |
9747 | pos_1 = get_cpu_unit_code ("2_1"); | |
9748 | pos_2 = get_cpu_unit_code ("2_2"); | |
9749 | pos_3 = get_cpu_unit_code ("2_3"); | |
9750 | pos_4 = get_cpu_unit_code ("2_4"); | |
9751 | pos_5 = get_cpu_unit_code ("2_5"); | |
9752 | pos_6 = get_cpu_unit_code ("2_6"); | |
9753 | _0mii_ = get_cpu_unit_code ("2b_0mii."); | |
9754 | _0mmi_ = get_cpu_unit_code ("2b_0mmi."); | |
9755 | _0mfi_ = get_cpu_unit_code ("2b_0mfi."); | |
9756 | _0mmf_ = get_cpu_unit_code ("2b_0mmf."); | |
9757 | _0bbb_ = get_cpu_unit_code ("2b_0bbb."); | |
9758 | _0mbb_ = get_cpu_unit_code ("2b_0mbb."); | |
9759 | _0mib_ = get_cpu_unit_code ("2b_0mib."); | |
9760 | _0mmb_ = get_cpu_unit_code ("2b_0mmb."); | |
9761 | _0mfb_ = get_cpu_unit_code ("2b_0mfb."); | |
9762 | _0mlx_ = get_cpu_unit_code ("2b_0mlx."); | |
9763 | _1mii_ = get_cpu_unit_code ("2b_1mii."); | |
9764 | _1mmi_ = get_cpu_unit_code ("2b_1mmi."); | |
9765 | _1mfi_ = get_cpu_unit_code ("2b_1mfi."); | |
9766 | _1mmf_ = get_cpu_unit_code ("2b_1mmf."); | |
9767 | _1bbb_ = get_cpu_unit_code ("2b_1bbb."); | |
9768 | _1mbb_ = get_cpu_unit_code ("2b_1mbb."); | |
9769 | _1mib_ = get_cpu_unit_code ("2b_1mib."); | |
9770 | _1mmb_ = get_cpu_unit_code ("2b_1mmb."); | |
9771 | _1mfb_ = get_cpu_unit_code ("2b_1mfb."); | |
9772 | _1mlx_ = get_cpu_unit_code ("2b_1mlx."); | |
9773 | } | |
9774 | else | |
9775 | { | |
9776 | pos_1 = get_cpu_unit_code ("1_1"); | |
9777 | pos_2 = get_cpu_unit_code ("1_2"); | |
9778 | pos_3 = get_cpu_unit_code ("1_3"); | |
9779 | pos_4 = get_cpu_unit_code ("1_4"); | |
9780 | pos_5 = get_cpu_unit_code ("1_5"); | |
9781 | pos_6 = get_cpu_unit_code ("1_6"); | |
9782 | _0mii_ = get_cpu_unit_code ("1b_0mii."); | |
9783 | _0mmi_ = get_cpu_unit_code ("1b_0mmi."); | |
9784 | _0mfi_ = get_cpu_unit_code ("1b_0mfi."); | |
9785 | _0mmf_ = get_cpu_unit_code ("1b_0mmf."); | |
9786 | _0bbb_ = get_cpu_unit_code ("1b_0bbb."); | |
9787 | _0mbb_ = get_cpu_unit_code ("1b_0mbb."); | |
9788 | _0mib_ = get_cpu_unit_code ("1b_0mib."); | |
9789 | _0mmb_ = get_cpu_unit_code ("1b_0mmb."); | |
9790 | _0mfb_ = get_cpu_unit_code ("1b_0mfb."); | |
9791 | _0mlx_ = get_cpu_unit_code ("1b_0mlx."); | |
9792 | _1mii_ = get_cpu_unit_code ("1b_1mii."); | |
9793 | _1mmi_ = get_cpu_unit_code ("1b_1mmi."); | |
9794 | _1mfi_ = get_cpu_unit_code ("1b_1mfi."); | |
9795 | _1mmf_ = get_cpu_unit_code ("1b_1mmf."); | |
9796 | _1bbb_ = get_cpu_unit_code ("1b_1bbb."); | |
9797 | _1mbb_ = get_cpu_unit_code ("1b_1mbb."); | |
9798 | _1mib_ = get_cpu_unit_code ("1b_1mib."); | |
9799 | _1mmb_ = get_cpu_unit_code ("1b_1mmb."); | |
9800 | _1mfb_ = get_cpu_unit_code ("1b_1mfb."); | |
9801 | _1mlx_ = get_cpu_unit_code ("1b_1mlx."); | |
9802 | } | |
388092d5 AB |
9803 | |
9804 | if (flag_selective_scheduling2 | |
9805 | && !maybe_skip_selective_scheduling ()) | |
9806 | run_selective_scheduling (); | |
9807 | else | |
9808 | schedule_ebbs (); | |
9809 | ||
9810 | /* Redo alignment computation, as it might gone wrong. */ | |
9811 | compute_alignments (); | |
9812 | ||
6fb5fa3c DB |
9813 | /* We cannot reuse this one because it has been corrupted by the |
9814 | evil glat. */ | |
30028c85 | 9815 | finish_bundle_states (); |
30028c85 | 9816 | free (stops_p); |
048d0d36 | 9817 | stops_p = NULL; |
c263766c | 9818 | emit_insn_group_barriers (dump_file); |
30028c85 | 9819 | |
f4d578da | 9820 | ia64_final_schedule = 0; |
eced69b5 | 9821 | timevar_pop (TV_SCHED2); |
f4d578da BS |
9822 | } |
9823 | else | |
c263766c | 9824 | emit_all_insn_group_barriers (dump_file); |
f2f90c63 | 9825 | |
6fb5fa3c DB |
9826 | df_analyze (); |
9827 | ||
f12f25a7 RH |
9828 | /* A call must not be the last instruction in a function, so that the |
9829 | return address is still within the function, so that unwinding works | |
9830 | properly. Note that IA-64 differs from dwarf2 on this point. */ | |
d5fabb58 | 9831 | if (ia64_except_unwind_info (&global_options) == UI_TARGET) |
f12f25a7 | 9832 | { |
dd3d2b35 | 9833 | rtx_insn *insn; |
f12f25a7 RH |
9834 | int saw_stop = 0; |
9835 | ||
9836 | insn = get_last_insn (); | |
9837 | if (! INSN_P (insn)) | |
9838 | insn = prev_active_insn (insn); | |
2ca57608 | 9839 | if (insn) |
f12f25a7 | 9840 | { |
2ca57608 | 9841 | /* Skip over insns that expand to nothing. */ |
b64925dc | 9842 | while (NONJUMP_INSN_P (insn) |
2ca57608 L |
9843 | && get_attr_empty (insn) == EMPTY_YES) |
9844 | { | |
9845 | if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
9846 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) | |
9847 | saw_stop = 1; | |
9848 | insn = prev_active_insn (insn); | |
9849 | } | |
b64925dc | 9850 | if (CALL_P (insn)) |
2ca57608 L |
9851 | { |
9852 | if (! saw_stop) | |
9853 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9854 | emit_insn (gen_break_f ()); | |
9855 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9856 | } | |
f12f25a7 RH |
9857 | } |
9858 | } | |
9859 | ||
f2f90c63 | 9860 | emit_predicate_relation_info (); |
014a1138 | 9861 | |
2ba42841 | 9862 | if (flag_var_tracking) |
014a1138 JZ |
9863 | { |
9864 | timevar_push (TV_VAR_TRACKING); | |
9865 | variable_tracking_main (); | |
9866 | timevar_pop (TV_VAR_TRACKING); | |
9867 | } | |
0d475361 | 9868 | df_finish_pass (false); |
c65ebc55 JW |
9869 | } |
9870 | \f | |
9871 | /* Return true if REGNO is used by the epilogue. */ | |
9872 | ||
9873 | int | |
9c808aad | 9874 | ia64_epilogue_uses (int regno) |
c65ebc55 | 9875 | { |
6ca3c22f RH |
9876 | switch (regno) |
9877 | { | |
9878 | case R_GR (1): | |
b23ba0b8 RH |
9879 | /* With a call to a function in another module, we will write a new |
9880 | value to "gp". After returning from such a call, we need to make | |
9881 | sure the function restores the original gp-value, even if the | |
9882 | function itself does not use the gp anymore. */ | |
9883 | return !(TARGET_AUTO_PIC || TARGET_NO_PIC); | |
6ca3c22f RH |
9884 | |
9885 | case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3): | |
9886 | case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7): | |
9887 | /* For functions defined with the syscall_linkage attribute, all | |
9888 | input registers are marked as live at all function exits. This | |
9889 | prevents the register allocator from using the input registers, | |
9890 | which in turn makes it possible to restart a system call after | |
9891 | an interrupt without having to save/restore the input registers. | |
9892 | This also prevents kernel data from leaking to application code. */ | |
9893 | return lookup_attribute ("syscall_linkage", | |
9894 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL; | |
9895 | ||
9896 | case R_BR (0): | |
9897 | /* Conditional return patterns can't represent the use of `b0' as | |
9898 | the return address, so we force the value live this way. */ | |
9899 | return 1; | |
6b6c1201 | 9900 | |
6ca3c22f RH |
9901 | case AR_PFS_REGNUM: |
9902 | /* Likewise for ar.pfs, which is used by br.ret. */ | |
9903 | return 1; | |
5527bf14 | 9904 | |
6ca3c22f RH |
9905 | default: |
9906 | return 0; | |
9907 | } | |
c65ebc55 | 9908 | } |
15b5aef3 RH |
9909 | |
9910 | /* Return true if REGNO is used by the frame unwinder. */ | |
9911 | ||
9912 | int | |
9c808aad | 9913 | ia64_eh_uses (int regno) |
15b5aef3 | 9914 | { |
09639a83 | 9915 | unsigned int r; |
6fb5fa3c | 9916 | |
15b5aef3 RH |
9917 | if (! reload_completed) |
9918 | return 0; | |
9919 | ||
6fb5fa3c DB |
9920 | if (regno == 0) |
9921 | return 0; | |
9922 | ||
9923 | for (r = reg_save_b0; r <= reg_save_ar_lc; r++) | |
9924 | if (regno == current_frame_info.r[r] | |
9925 | || regno == emitted_frame_related_regs[r]) | |
9926 | return 1; | |
15b5aef3 RH |
9927 | |
9928 | return 0; | |
9929 | } | |
c65ebc55 | 9930 | \f |
1cdbd630 | 9931 | /* Return true if this goes in small data/bss. */ |
c65ebc55 JW |
9932 | |
9933 | /* ??? We could also support own long data here. Generating movl/add/ld8 | |
9934 | instead of addl,ld8/ld8. This makes the code bigger, but should make the | |
9935 | code faster because there is one less load. This also includes incomplete | |
9936 | types which can't go in sdata/sbss. */ | |
9937 | ||
ae46c4e0 | 9938 | static bool |
3101faab | 9939 | ia64_in_small_data_p (const_tree exp) |
ae46c4e0 RH |
9940 | { |
9941 | if (TARGET_NO_SDATA) | |
9942 | return false; | |
9943 | ||
3907500b RH |
9944 | /* We want to merge strings, so we never consider them small data. */ |
9945 | if (TREE_CODE (exp) == STRING_CST) | |
9946 | return false; | |
9947 | ||
4c494a15 ZW |
9948 | /* Functions are never small data. */ |
9949 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
9950 | return false; | |
9951 | ||
ae46c4e0 RH |
9952 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
9953 | { | |
f961457f | 9954 | const char *section = DECL_SECTION_NAME (exp); |
826eb7ed | 9955 | |
ae46c4e0 | 9956 | if (strcmp (section, ".sdata") == 0 |
826eb7ed JB |
9957 | || strncmp (section, ".sdata.", 7) == 0 |
9958 | || strncmp (section, ".gnu.linkonce.s.", 16) == 0 | |
9959 | || strcmp (section, ".sbss") == 0 | |
9960 | || strncmp (section, ".sbss.", 6) == 0 | |
9961 | || strncmp (section, ".gnu.linkonce.sb.", 17) == 0) | |
ae46c4e0 RH |
9962 | return true; |
9963 | } | |
9964 | else | |
9965 | { | |
9966 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
9967 | ||
9968 | /* If this is an incomplete type with size 0, then we can't put it | |
9969 | in sdata because it might be too big when completed. */ | |
9970 | if (size > 0 && size <= ia64_section_threshold) | |
9971 | return true; | |
9972 | } | |
9973 | ||
9974 | return false; | |
9975 | } | |
0c96007e | 9976 | \f |
ad0fc698 JW |
9977 | /* Output assembly directives for prologue regions. */ |
9978 | ||
9979 | /* The current basic block number. */ | |
9980 | ||
e0082a72 | 9981 | static bool last_block; |
ad0fc698 JW |
9982 | |
9983 | /* True if we need a copy_state command at the start of the next block. */ | |
9984 | ||
e0082a72 | 9985 | static bool need_copy_state; |
ad0fc698 | 9986 | |
658f32fd AO |
9987 | #ifndef MAX_ARTIFICIAL_LABEL_BYTES |
9988 | # define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
9989 | #endif | |
9990 | ||
ad0fc698 JW |
9991 | /* The function emits unwind directives for the start of an epilogue. */ |
9992 | ||
9993 | static void | |
7d3c6cd8 RH |
9994 | process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED, |
9995 | bool unwind, bool frame ATTRIBUTE_UNUSED) | |
ad0fc698 JW |
9996 | { |
9997 | /* If this isn't the last block of the function, then we need to label the | |
9998 | current state, and copy it back in at the start of the next block. */ | |
9999 | ||
e0082a72 | 10000 | if (!last_block) |
ad0fc698 | 10001 | { |
658f32fd AO |
10002 | if (unwind) |
10003 | fprintf (asm_out_file, "\t.label_state %d\n", | |
10004 | ++cfun->machine->state_num); | |
e0082a72 | 10005 | need_copy_state = true; |
ad0fc698 JW |
10006 | } |
10007 | ||
658f32fd AO |
10008 | if (unwind) |
10009 | fprintf (asm_out_file, "\t.restore sp\n"); | |
ad0fc698 | 10010 | } |
0c96007e | 10011 | |
5c255b57 | 10012 | /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */ |
97e242b0 | 10013 | |
5c255b57 RH |
10014 | static void |
10015 | process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn, | |
10016 | bool unwind, bool frame) | |
0c96007e | 10017 | { |
0c96007e | 10018 | rtx dest = SET_DEST (pat); |
5c255b57 | 10019 | rtx src = SET_SRC (pat); |
0c96007e | 10020 | |
5c255b57 | 10021 | if (dest == stack_pointer_rtx) |
0c96007e AM |
10022 | { |
10023 | if (GET_CODE (src) == PLUS) | |
5c255b57 | 10024 | { |
0c96007e AM |
10025 | rtx op0 = XEXP (src, 0); |
10026 | rtx op1 = XEXP (src, 1); | |
e820471b NS |
10027 | |
10028 | gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT); | |
10029 | ||
10030 | if (INTVAL (op1) < 0) | |
658f32fd AO |
10031 | { |
10032 | gcc_assert (!frame_pointer_needed); | |
10033 | if (unwind) | |
5c255b57 RH |
10034 | fprintf (asm_out_file, |
10035 | "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n", | |
658f32fd | 10036 | -INTVAL (op1)); |
658f32fd | 10037 | } |
0186257f | 10038 | else |
658f32fd | 10039 | process_epilogue (asm_out_file, insn, unwind, frame); |
0c96007e | 10040 | } |
0186257f | 10041 | else |
e820471b | 10042 | { |
5c255b57 | 10043 | gcc_assert (src == hard_frame_pointer_rtx); |
658f32fd | 10044 | process_epilogue (asm_out_file, insn, unwind, frame); |
e820471b | 10045 | } |
5c255b57 RH |
10046 | } |
10047 | else if (dest == hard_frame_pointer_rtx) | |
10048 | { | |
10049 | gcc_assert (src == stack_pointer_rtx); | |
10050 | gcc_assert (frame_pointer_needed); | |
0186257f | 10051 | |
5c255b57 RH |
10052 | if (unwind) |
10053 | fprintf (asm_out_file, "\t.vframe r%d\n", | |
10054 | ia64_dbx_register_number (REGNO (dest))); | |
0c96007e | 10055 | } |
5c255b57 RH |
10056 | else |
10057 | gcc_unreachable (); | |
10058 | } | |
0c96007e | 10059 | |
5c255b57 | 10060 | /* This function processes a SET pattern for REG_CFA_REGISTER. */ |
97e242b0 | 10061 | |
5c255b57 RH |
10062 | static void |
10063 | process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind) | |
10064 | { | |
10065 | rtx dest = SET_DEST (pat); | |
10066 | rtx src = SET_SRC (pat); | |
5c255b57 | 10067 | int dest_regno = REGNO (dest); |
5f740973 | 10068 | int src_regno; |
97e242b0 | 10069 | |
5f740973 | 10070 | if (src == pc_rtx) |
5c255b57 | 10071 | { |
5c255b57 | 10072 | /* Saving return address pointer. */ |
5c255b57 RH |
10073 | if (unwind) |
10074 | fprintf (asm_out_file, "\t.save rp, r%d\n", | |
10075 | ia64_dbx_register_number (dest_regno)); | |
5f740973 RH |
10076 | return; |
10077 | } | |
10078 | ||
10079 | src_regno = REGNO (src); | |
97e242b0 | 10080 | |
5f740973 RH |
10081 | switch (src_regno) |
10082 | { | |
5c255b57 RH |
10083 | case PR_REG (0): |
10084 | gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]); | |
10085 | if (unwind) | |
10086 | fprintf (asm_out_file, "\t.save pr, r%d\n", | |
10087 | ia64_dbx_register_number (dest_regno)); | |
10088 | break; | |
97e242b0 | 10089 | |
5c255b57 RH |
10090 | case AR_UNAT_REGNUM: |
10091 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]); | |
10092 | if (unwind) | |
10093 | fprintf (asm_out_file, "\t.save ar.unat, r%d\n", | |
10094 | ia64_dbx_register_number (dest_regno)); | |
10095 | break; | |
97e242b0 | 10096 | |
5c255b57 RH |
10097 | case AR_LC_REGNUM: |
10098 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]); | |
10099 | if (unwind) | |
10100 | fprintf (asm_out_file, "\t.save ar.lc, r%d\n", | |
10101 | ia64_dbx_register_number (dest_regno)); | |
10102 | break; | |
10103 | ||
10104 | default: | |
10105 | /* Everything else should indicate being stored to memory. */ | |
10106 | gcc_unreachable (); | |
0c96007e | 10107 | } |
5c255b57 | 10108 | } |
97e242b0 | 10109 | |
5c255b57 | 10110 | /* This function processes a SET pattern for REG_CFA_OFFSET. */ |
97e242b0 | 10111 | |
5c255b57 RH |
10112 | static void |
10113 | process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind) | |
10114 | { | |
10115 | rtx dest = SET_DEST (pat); | |
10116 | rtx src = SET_SRC (pat); | |
10117 | int src_regno = REGNO (src); | |
10118 | const char *saveop; | |
10119 | HOST_WIDE_INT off; | |
10120 | rtx base; | |
0c96007e | 10121 | |
5c255b57 RH |
10122 | gcc_assert (MEM_P (dest)); |
10123 | if (GET_CODE (XEXP (dest, 0)) == REG) | |
10124 | { | |
10125 | base = XEXP (dest, 0); | |
10126 | off = 0; | |
10127 | } | |
10128 | else | |
10129 | { | |
10130 | gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS | |
10131 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT); | |
10132 | base = XEXP (XEXP (dest, 0), 0); | |
10133 | off = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
10134 | } | |
97e242b0 | 10135 | |
5c255b57 RH |
10136 | if (base == hard_frame_pointer_rtx) |
10137 | { | |
10138 | saveop = ".savepsp"; | |
10139 | off = - off; | |
10140 | } | |
10141 | else | |
10142 | { | |
10143 | gcc_assert (base == stack_pointer_rtx); | |
10144 | saveop = ".savesp"; | |
10145 | } | |
97e242b0 | 10146 | |
5c255b57 RH |
10147 | src_regno = REGNO (src); |
10148 | switch (src_regno) | |
10149 | { | |
10150 | case BR_REG (0): | |
10151 | gcc_assert (!current_frame_info.r[reg_save_b0]); | |
10152 | if (unwind) | |
10153 | fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10154 | saveop, off); | |
10155 | break; | |
97e242b0 | 10156 | |
5c255b57 RH |
10157 | case PR_REG (0): |
10158 | gcc_assert (!current_frame_info.r[reg_save_pr]); | |
10159 | if (unwind) | |
10160 | fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10161 | saveop, off); | |
10162 | break; | |
97e242b0 | 10163 | |
5c255b57 RH |
10164 | case AR_LC_REGNUM: |
10165 | gcc_assert (!current_frame_info.r[reg_save_ar_lc]); | |
10166 | if (unwind) | |
10167 | fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10168 | saveop, off); | |
10169 | break; | |
97e242b0 | 10170 | |
5c255b57 RH |
10171 | case AR_PFS_REGNUM: |
10172 | gcc_assert (!current_frame_info.r[reg_save_ar_pfs]); | |
10173 | if (unwind) | |
10174 | fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10175 | saveop, off); | |
10176 | break; | |
97e242b0 | 10177 | |
5c255b57 RH |
10178 | case AR_UNAT_REGNUM: |
10179 | gcc_assert (!current_frame_info.r[reg_save_ar_unat]); | |
10180 | if (unwind) | |
10181 | fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10182 | saveop, off); | |
10183 | break; | |
97e242b0 | 10184 | |
5c255b57 RH |
10185 | case GR_REG (4): |
10186 | case GR_REG (5): | |
10187 | case GR_REG (6): | |
10188 | case GR_REG (7): | |
10189 | if (unwind) | |
10190 | fprintf (asm_out_file, "\t.save.g 0x%x\n", | |
10191 | 1 << (src_regno - GR_REG (4))); | |
10192 | break; | |
97e242b0 | 10193 | |
5c255b57 RH |
10194 | case BR_REG (1): |
10195 | case BR_REG (2): | |
10196 | case BR_REG (3): | |
10197 | case BR_REG (4): | |
10198 | case BR_REG (5): | |
10199 | if (unwind) | |
10200 | fprintf (asm_out_file, "\t.save.b 0x%x\n", | |
10201 | 1 << (src_regno - BR_REG (1))); | |
10202 | break; | |
97e242b0 | 10203 | |
5c255b57 RH |
10204 | case FR_REG (2): |
10205 | case FR_REG (3): | |
10206 | case FR_REG (4): | |
10207 | case FR_REG (5): | |
10208 | if (unwind) | |
10209 | fprintf (asm_out_file, "\t.save.f 0x%x\n", | |
10210 | 1 << (src_regno - FR_REG (2))); | |
10211 | break; | |
97e242b0 | 10212 | |
5c255b57 RH |
10213 | case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19): |
10214 | case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23): | |
10215 | case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27): | |
10216 | case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31): | |
10217 | if (unwind) | |
10218 | fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n", | |
10219 | 1 << (src_regno - FR_REG (12))); | |
10220 | break; | |
97e242b0 | 10221 | |
5c255b57 RH |
10222 | default: |
10223 | /* ??? For some reason we mark other general registers, even those | |
10224 | we can't represent in the unwind info. Ignore them. */ | |
10225 | break; | |
10226 | } | |
0c96007e AM |
10227 | } |
10228 | ||
0c96007e AM |
10229 | /* This function looks at a single insn and emits any directives |
10230 | required to unwind this insn. */ | |
5c255b57 | 10231 | |
a68b5e52 | 10232 | static void |
ac44248e | 10233 | ia64_asm_unwind_emit (FILE *asm_out_file, rtx_insn *insn) |
0c96007e | 10234 | { |
d5fabb58 | 10235 | bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET; |
658f32fd | 10236 | bool frame = dwarf2out_do_frame (); |
5c255b57 RH |
10237 | rtx note, pat; |
10238 | bool handled_one; | |
10239 | ||
10240 | if (!unwind && !frame) | |
10241 | return; | |
658f32fd | 10242 | |
5c255b57 | 10243 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
0c96007e | 10244 | { |
fefa31b5 DM |
10245 | last_block = NOTE_BASIC_BLOCK (insn)->next_bb |
10246 | == EXIT_BLOCK_PTR_FOR_FN (cfun); | |
97e242b0 | 10247 | |
5c255b57 RH |
10248 | /* Restore unwind state from immediately before the epilogue. */ |
10249 | if (need_copy_state) | |
ad0fc698 | 10250 | { |
5c255b57 | 10251 | if (unwind) |
ad0fc698 | 10252 | { |
5c255b57 RH |
10253 | fprintf (asm_out_file, "\t.body\n"); |
10254 | fprintf (asm_out_file, "\t.copy_state %d\n", | |
10255 | cfun->machine->state_num); | |
ad0fc698 | 10256 | } |
5c255b57 | 10257 | need_copy_state = false; |
ad0fc698 | 10258 | } |
5c255b57 | 10259 | } |
ad0fc698 | 10260 | |
b64925dc | 10261 | if (NOTE_P (insn) || ! RTX_FRAME_RELATED_P (insn)) |
5c255b57 RH |
10262 | return; |
10263 | ||
10264 | /* Look for the ALLOC insn. */ | |
10265 | if (INSN_CODE (insn) == CODE_FOR_alloc) | |
10266 | { | |
10267 | rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
10268 | int dest_regno = REGNO (dest); | |
ad0fc698 | 10269 | |
5c255b57 RH |
10270 | /* If this is the final destination for ar.pfs, then this must |
10271 | be the alloc in the prologue. */ | |
10272 | if (dest_regno == current_frame_info.r[reg_save_ar_pfs]) | |
10273 | { | |
10274 | if (unwind) | |
10275 | fprintf (asm_out_file, "\t.save ar.pfs, r%d\n", | |
10276 | ia64_dbx_register_number (dest_regno)); | |
10277 | } | |
97e242b0 | 10278 | else |
5c255b57 RH |
10279 | { |
10280 | /* This must be an alloc before a sibcall. We must drop the | |
10281 | old frame info. The easiest way to drop the old frame | |
10282 | info is to ensure we had a ".restore sp" directive | |
10283 | followed by a new prologue. If the procedure doesn't | |
10284 | have a memory-stack frame, we'll issue a dummy ".restore | |
10285 | sp" now. */ | |
10286 | if (current_frame_info.total_size == 0 && !frame_pointer_needed) | |
10287 | /* if haven't done process_epilogue() yet, do it now */ | |
10288 | process_epilogue (asm_out_file, insn, unwind, frame); | |
10289 | if (unwind) | |
10290 | fprintf (asm_out_file, "\t.prologue\n"); | |
10291 | } | |
10292 | return; | |
10293 | } | |
0c96007e | 10294 | |
5c255b57 RH |
10295 | handled_one = false; |
10296 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
10297 | switch (REG_NOTE_KIND (note)) | |
10298 | { | |
10299 | case REG_CFA_ADJUST_CFA: | |
10300 | pat = XEXP (note, 0); | |
10301 | if (pat == NULL) | |
10302 | pat = PATTERN (insn); | |
10303 | process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame); | |
10304 | handled_one = true; | |
10305 | break; | |
809d4ef1 | 10306 | |
5c255b57 RH |
10307 | case REG_CFA_OFFSET: |
10308 | pat = XEXP (note, 0); | |
10309 | if (pat == NULL) | |
10310 | pat = PATTERN (insn); | |
10311 | process_cfa_offset (asm_out_file, pat, unwind); | |
10312 | handled_one = true; | |
10313 | break; | |
809d4ef1 | 10314 | |
5c255b57 RH |
10315 | case REG_CFA_REGISTER: |
10316 | pat = XEXP (note, 0); | |
10317 | if (pat == NULL) | |
10318 | pat = PATTERN (insn); | |
10319 | process_cfa_register (asm_out_file, pat, unwind); | |
10320 | handled_one = true; | |
10321 | break; | |
10322 | ||
10323 | case REG_FRAME_RELATED_EXPR: | |
10324 | case REG_CFA_DEF_CFA: | |
10325 | case REG_CFA_EXPRESSION: | |
10326 | case REG_CFA_RESTORE: | |
10327 | case REG_CFA_SET_VDRAP: | |
10328 | /* Not used in the ia64 port. */ | |
10329 | gcc_unreachable (); | |
10330 | ||
10331 | default: | |
10332 | /* Not a frame-related note. */ | |
10333 | break; | |
10334 | } | |
10335 | ||
10336 | /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the | |
10337 | explicit action to take. No guessing required. */ | |
10338 | gcc_assert (handled_one); | |
0c96007e | 10339 | } |
c65ebc55 | 10340 | |
a68b5e52 RH |
10341 | /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */ |
10342 | ||
10343 | static void | |
10344 | ia64_asm_emit_except_personality (rtx personality) | |
10345 | { | |
10346 | fputs ("\t.personality\t", asm_out_file); | |
10347 | output_addr_const (asm_out_file, personality); | |
10348 | fputc ('\n', asm_out_file); | |
10349 | } | |
10350 | ||
10351 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */ | |
10352 | ||
10353 | static void | |
10354 | ia64_asm_init_sections (void) | |
10355 | { | |
10356 | exception_section = get_unnamed_section (0, output_section_asm_op, | |
10357 | "\t.handlerdata"); | |
10358 | } | |
f0a0390e RH |
10359 | |
10360 | /* Implement TARGET_DEBUG_UNWIND_INFO. */ | |
10361 | ||
10362 | static enum unwind_info_type | |
10363 | ia64_debug_unwind_info (void) | |
10364 | { | |
10365 | return UI_TARGET; | |
10366 | } | |
0551c32d | 10367 | \f |
af795c3c RH |
10368 | enum ia64_builtins |
10369 | { | |
10370 | IA64_BUILTIN_BSP, | |
c252db20 L |
10371 | IA64_BUILTIN_COPYSIGNQ, |
10372 | IA64_BUILTIN_FABSQ, | |
10373 | IA64_BUILTIN_FLUSHRS, | |
fcb82ab0 | 10374 | IA64_BUILTIN_INFQ, |
b14446e2 SE |
10375 | IA64_BUILTIN_HUGE_VALQ, |
10376 | IA64_BUILTIN_max | |
af795c3c RH |
10377 | }; |
10378 | ||
b14446e2 SE |
10379 | static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max]; |
10380 | ||
c65ebc55 | 10381 | void |
9c808aad | 10382 | ia64_init_builtins (void) |
c65ebc55 | 10383 | { |
9649812a | 10384 | tree fpreg_type; |
bf9ab6b6 | 10385 | tree float80_type; |
b14446e2 | 10386 | tree decl; |
9649812a MM |
10387 | |
10388 | /* The __fpreg type. */ | |
10389 | fpreg_type = make_node (REAL_TYPE); | |
4de67c26 | 10390 | TYPE_PRECISION (fpreg_type) = 82; |
9649812a MM |
10391 | layout_type (fpreg_type); |
10392 | (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg"); | |
10393 | ||
10394 | /* The __float80 type. */ | |
bf9ab6b6 | 10395 | float80_type = make_node (REAL_TYPE); |
968a7562 | 10396 | TYPE_PRECISION (float80_type) = 80; |
bf9ab6b6 MM |
10397 | layout_type (float80_type); |
10398 | (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); | |
9649812a MM |
10399 | |
10400 | /* The __float128 type. */ | |
02befdf4 | 10401 | if (!TARGET_HPUX) |
9649812a | 10402 | { |
b14446e2 | 10403 | tree ftype; |
9649812a | 10404 | tree float128_type = make_node (REAL_TYPE); |
c252db20 | 10405 | |
9649812a MM |
10406 | TYPE_PRECISION (float128_type) = 128; |
10407 | layout_type (float128_type); | |
10408 | (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); | |
c252db20 L |
10409 | |
10410 | /* TFmode support builtins. */ | |
c0676219 | 10411 | ftype = build_function_type_list (float128_type, NULL_TREE); |
b14446e2 SE |
10412 | decl = add_builtin_function ("__builtin_infq", ftype, |
10413 | IA64_BUILTIN_INFQ, BUILT_IN_MD, | |
10414 | NULL, NULL_TREE); | |
10415 | ia64_builtins[IA64_BUILTIN_INFQ] = decl; | |
c252db20 | 10416 | |
b14446e2 SE |
10417 | decl = add_builtin_function ("__builtin_huge_valq", ftype, |
10418 | IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
10419 | NULL, NULL_TREE); | |
10420 | ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl; | |
fcb82ab0 | 10421 | |
c252db20 L |
10422 | ftype = build_function_type_list (float128_type, |
10423 | float128_type, | |
10424 | NULL_TREE); | |
10425 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
10426 | IA64_BUILTIN_FABSQ, BUILT_IN_MD, | |
10427 | "__fabstf2", NULL_TREE); | |
10428 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10429 | ia64_builtins[IA64_BUILTIN_FABSQ] = decl; |
c252db20 L |
10430 | |
10431 | ftype = build_function_type_list (float128_type, | |
10432 | float128_type, | |
10433 | float128_type, | |
10434 | NULL_TREE); | |
10435 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
10436 | IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
10437 | "__copysigntf3", NULL_TREE); | |
10438 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10439 | ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl; |
9649812a MM |
10440 | } |
10441 | else | |
02befdf4 | 10442 | /* Under HPUX, this is a synonym for "long double". */ |
9649812a MM |
10443 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, |
10444 | "__float128"); | |
10445 | ||
f2972bf8 | 10446 | /* Fwrite on VMS is non-standard. */ |
171da07a RH |
10447 | #if TARGET_ABI_OPEN_VMS |
10448 | vms_patch_builtins (); | |
10449 | #endif | |
f2972bf8 | 10450 | |
6e34d3a3 | 10451 | #define def_builtin(name, type, code) \ |
c79efc4d RÁE |
10452 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, \ |
10453 | NULL, NULL_TREE) | |
0551c32d | 10454 | |
b14446e2 | 10455 | decl = def_builtin ("__builtin_ia64_bsp", |
c0676219 NF |
10456 | build_function_type_list (ptr_type_node, NULL_TREE), |
10457 | IA64_BUILTIN_BSP); | |
b14446e2 | 10458 | ia64_builtins[IA64_BUILTIN_BSP] = decl; |
ce152ef8 | 10459 | |
b14446e2 | 10460 | decl = def_builtin ("__builtin_ia64_flushrs", |
c0676219 NF |
10461 | build_function_type_list (void_type_node, NULL_TREE), |
10462 | IA64_BUILTIN_FLUSHRS); | |
b14446e2 | 10463 | ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl; |
ce152ef8 | 10464 | |
0551c32d | 10465 | #undef def_builtin |
7d522000 SE |
10466 | |
10467 | if (TARGET_HPUX) | |
10468 | { | |
ccea4a27 | 10469 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) |
e79983f4 | 10470 | set_user_assembler_name (decl, "_Isfinite"); |
ccea4a27 | 10471 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) |
e79983f4 | 10472 | set_user_assembler_name (decl, "_Isfinitef"); |
ccea4a27 | 10473 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE) |
e79983f4 | 10474 | set_user_assembler_name (decl, "_Isfinitef128"); |
7d522000 | 10475 | } |
c65ebc55 JW |
10476 | } |
10477 | ||
c65ebc55 | 10478 | rtx |
9c808aad | 10479 | ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
ef4bddc2 | 10480 | machine_mode mode ATTRIBUTE_UNUSED, |
9c808aad | 10481 | int ignore ATTRIBUTE_UNUSED) |
c65ebc55 | 10482 | { |
767fad4c | 10483 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
97e242b0 | 10484 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
c65ebc55 JW |
10485 | |
10486 | switch (fcode) | |
10487 | { | |
ce152ef8 | 10488 | case IA64_BUILTIN_BSP: |
0551c32d RH |
10489 | if (! target || ! register_operand (target, DImode)) |
10490 | target = gen_reg_rtx (DImode); | |
10491 | emit_insn (gen_bsp_value (target)); | |
8419b675 RK |
10492 | #ifdef POINTERS_EXTEND_UNSIGNED |
10493 | target = convert_memory_address (ptr_mode, target); | |
10494 | #endif | |
0551c32d | 10495 | return target; |
ce152ef8 AM |
10496 | |
10497 | case IA64_BUILTIN_FLUSHRS: | |
3b572406 RH |
10498 | emit_insn (gen_flushrs ()); |
10499 | return const0_rtx; | |
ce152ef8 | 10500 | |
c252db20 | 10501 | case IA64_BUILTIN_INFQ: |
fcb82ab0 | 10502 | case IA64_BUILTIN_HUGE_VALQ: |
c252db20 | 10503 | { |
ef4bddc2 | 10504 | machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); |
c252db20 L |
10505 | REAL_VALUE_TYPE inf; |
10506 | rtx tmp; | |
10507 | ||
10508 | real_inf (&inf); | |
6aad068a | 10509 | tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode); |
c252db20 | 10510 | |
6aad068a | 10511 | tmp = validize_mem (force_const_mem (target_mode, tmp)); |
c252db20 L |
10512 | |
10513 | if (target == 0) | |
6aad068a | 10514 | target = gen_reg_rtx (target_mode); |
c252db20 L |
10515 | |
10516 | emit_move_insn (target, tmp); | |
10517 | return target; | |
10518 | } | |
10519 | ||
10520 | case IA64_BUILTIN_FABSQ: | |
10521 | case IA64_BUILTIN_COPYSIGNQ: | |
10522 | return expand_call (exp, target, ignore); | |
10523 | ||
c65ebc55 | 10524 | default: |
c252db20 | 10525 | gcc_unreachable (); |
c65ebc55 JW |
10526 | } |
10527 | ||
0551c32d | 10528 | return NULL_RTX; |
c65ebc55 | 10529 | } |
0d7839da | 10530 | |
b14446e2 SE |
10531 | /* Return the ia64 builtin for CODE. */ |
10532 | ||
10533 | static tree | |
10534 | ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
10535 | { | |
10536 | if (code >= IA64_BUILTIN_max) | |
10537 | return error_mark_node; | |
10538 | ||
10539 | return ia64_builtins[code]; | |
10540 | } | |
10541 | ||
0d7839da SE |
10542 | /* For the HP-UX IA64 aggregate parameters are passed stored in the |
10543 | most significant bits of the stack slot. */ | |
10544 | ||
10545 | enum direction | |
ef4bddc2 | 10546 | ia64_hpux_function_arg_padding (machine_mode mode, const_tree type) |
0d7839da | 10547 | { |
ed168e45 | 10548 | /* Exception to normal case for structures/unions/etc. */ |
0d7839da SE |
10549 | |
10550 | if (type && AGGREGATE_TYPE_P (type) | |
10551 | && int_size_in_bytes (type) < UNITS_PER_WORD) | |
10552 | return upward; | |
10553 | ||
d3704c46 KH |
10554 | /* Fall back to the default. */ |
10555 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
0d7839da | 10556 | } |
686f3bf0 | 10557 | |
c47c29c8 L |
10558 | /* Emit text to declare externally defined variables and functions, because |
10559 | the Intel assembler does not support undefined externals. */ | |
686f3bf0 | 10560 | |
c47c29c8 L |
10561 | void |
10562 | ia64_asm_output_external (FILE *file, tree decl, const char *name) | |
686f3bf0 | 10563 | { |
c47c29c8 L |
10564 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
10565 | set in order to avoid putting out names that are never really | |
10566 | used. */ | |
10567 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
686f3bf0 | 10568 | { |
c47c29c8 | 10569 | /* maybe_assemble_visibility will return 1 if the assembler |
2e226e66 | 10570 | visibility directive is output. */ |
c47c29c8 L |
10571 | int need_visibility = ((*targetm.binds_local_p) (decl) |
10572 | && maybe_assemble_visibility (decl)); | |
57d4f65c | 10573 | |
c47c29c8 L |
10574 | /* GNU as does not need anything here, but the HP linker does |
10575 | need something for external functions. */ | |
10576 | if ((TARGET_HPUX_LD || !TARGET_GNU_AS) | |
10577 | && TREE_CODE (decl) == FUNCTION_DECL) | |
812b587e | 10578 | (*targetm.asm_out.globalize_decl_name) (file, decl); |
c47c29c8 L |
10579 | else if (need_visibility && !TARGET_GNU_AS) |
10580 | (*targetm.asm_out.globalize_label) (file, name); | |
686f3bf0 SE |
10581 | } |
10582 | } | |
10583 | ||
1f7aa7cd | 10584 | /* Set SImode div/mod functions, init_integral_libfuncs only initializes |
6bc709c1 L |
10585 | modes of word_mode and larger. Rename the TFmode libfuncs using the |
10586 | HPUX conventions. __divtf3 is used for XFmode. We need to keep it for | |
10587 | backward compatibility. */ | |
1f7aa7cd SE |
10588 | |
10589 | static void | |
10590 | ia64_init_libfuncs (void) | |
10591 | { | |
10592 | set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); | |
10593 | set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); | |
10594 | set_optab_libfunc (smod_optab, SImode, "__modsi3"); | |
10595 | set_optab_libfunc (umod_optab, SImode, "__umodsi3"); | |
6bc709c1 L |
10596 | |
10597 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
10598 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
10599 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
10600 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
10601 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
10602 | ||
10603 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); | |
10604 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
10605 | set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad"); | |
10606 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
10607 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
10608 | set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80"); | |
10609 | ||
10610 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl"); | |
10611 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
4a73d865 | 10612 | set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad"); |
6bc709c1 L |
10613 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl"); |
10614 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl"); | |
10615 | ||
10616 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
10617 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
4a73d865 | 10618 | set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad"); |
2a3ebe77 JM |
10619 | /* HP-UX 11.23 libc does not have a function for unsigned |
10620 | SImode-to-TFmode conversion. */ | |
10621 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad"); | |
1f7aa7cd SE |
10622 | } |
10623 | ||
c15c90bb | 10624 | /* Rename all the TFmode libfuncs using the HPUX conventions. */ |
738e7b39 | 10625 | |
c15c90bb ZW |
10626 | static void |
10627 | ia64_hpux_init_libfuncs (void) | |
10628 | { | |
1f7aa7cd SE |
10629 | ia64_init_libfuncs (); |
10630 | ||
bdbba3c2 SE |
10631 | /* The HP SI millicode division and mod functions expect DI arguments. |
10632 | By turning them off completely we avoid using both libgcc and the | |
10633 | non-standard millicode routines and use the HP DI millicode routines | |
10634 | instead. */ | |
10635 | ||
10636 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10637 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10638 | set_optab_libfunc (smod_optab, SImode, 0); | |
10639 | set_optab_libfunc (umod_optab, SImode, 0); | |
10640 | ||
10641 | set_optab_libfunc (sdiv_optab, DImode, "__milli_divI"); | |
10642 | set_optab_libfunc (udiv_optab, DImode, "__milli_divU"); | |
10643 | set_optab_libfunc (smod_optab, DImode, "__milli_remI"); | |
10644 | set_optab_libfunc (umod_optab, DImode, "__milli_remU"); | |
10645 | ||
10646 | /* HP-UX libc has TF min/max/abs routines in it. */ | |
c15c90bb ZW |
10647 | set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin"); |
10648 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
10649 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
c15c90bb | 10650 | |
24ea7948 ZW |
10651 | /* ia64_expand_compare uses this. */ |
10652 | cmptf_libfunc = init_one_libfunc ("_U_Qfcmp"); | |
10653 | ||
10654 | /* These should never be used. */ | |
10655 | set_optab_libfunc (eq_optab, TFmode, 0); | |
10656 | set_optab_libfunc (ne_optab, TFmode, 0); | |
10657 | set_optab_libfunc (gt_optab, TFmode, 0); | |
10658 | set_optab_libfunc (ge_optab, TFmode, 0); | |
10659 | set_optab_libfunc (lt_optab, TFmode, 0); | |
10660 | set_optab_libfunc (le_optab, TFmode, 0); | |
c15c90bb | 10661 | } |
738e7b39 RK |
10662 | |
10663 | /* Rename the division and modulus functions in VMS. */ | |
10664 | ||
10665 | static void | |
10666 | ia64_vms_init_libfuncs (void) | |
10667 | { | |
10668 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
10669 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
10670 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
10671 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
10672 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
10673 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
10674 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
10675 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
f2972bf8 DR |
10676 | abort_libfunc = init_one_libfunc ("decc$abort"); |
10677 | memcmp_libfunc = init_one_libfunc ("decc$memcmp"); | |
10678 | #ifdef MEM_LIBFUNCS_INIT | |
10679 | MEM_LIBFUNCS_INIT; | |
10680 | #endif | |
738e7b39 | 10681 | } |
6bc709c1 L |
10682 | |
10683 | /* Rename the TFmode libfuncs available from soft-fp in glibc using | |
10684 | the HPUX conventions. */ | |
10685 | ||
10686 | static void | |
10687 | ia64_sysv4_init_libfuncs (void) | |
10688 | { | |
10689 | ia64_init_libfuncs (); | |
10690 | ||
10691 | /* These functions are not part of the HPUX TFmode interface. We | |
10692 | use them instead of _U_Qfcmp, which doesn't work the way we | |
10693 | expect. */ | |
10694 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); | |
10695 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
10696 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
10697 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
10698 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
10699 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
10700 | ||
10701 | /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in | |
10702 | glibc doesn't have them. */ | |
10703 | } | |
c252db20 L |
10704 | |
10705 | /* Use soft-fp. */ | |
10706 | ||
10707 | static void | |
10708 | ia64_soft_fp_init_libfuncs (void) | |
10709 | { | |
10710 | } | |
f2972bf8 DR |
10711 | |
10712 | static bool | |
ef4bddc2 | 10713 | ia64_vms_valid_pointer_mode (machine_mode mode) |
f2972bf8 DR |
10714 | { |
10715 | return (mode == SImode || mode == DImode); | |
10716 | } | |
ae46c4e0 | 10717 | \f |
9b580a0b RH |
10718 | /* For HPUX, it is illegal to have relocations in shared segments. */ |
10719 | ||
10720 | static int | |
10721 | ia64_hpux_reloc_rw_mask (void) | |
10722 | { | |
10723 | return 3; | |
10724 | } | |
10725 | ||
10726 | /* For others, relax this so that relocations to local data goes in | |
10727 | read-only segments, but we still cannot allow global relocations | |
10728 | in read-only segments. */ | |
10729 | ||
10730 | static int | |
10731 | ia64_reloc_rw_mask (void) | |
10732 | { | |
10733 | return flag_pic ? 3 : 2; | |
10734 | } | |
10735 | ||
d6b5193b RS |
10736 | /* Return the section to use for X. The only special thing we do here |
10737 | is to honor small data. */ | |
b64a1b53 | 10738 | |
d6b5193b | 10739 | static section * |
ef4bddc2 | 10740 | ia64_select_rtx_section (machine_mode mode, rtx x, |
9c808aad | 10741 | unsigned HOST_WIDE_INT align) |
b64a1b53 RH |
10742 | { |
10743 | if (GET_MODE_SIZE (mode) > 0 | |
1f4a2e84 SE |
10744 | && GET_MODE_SIZE (mode) <= ia64_section_threshold |
10745 | && !TARGET_NO_SDATA) | |
d6b5193b | 10746 | return sdata_section; |
b64a1b53 | 10747 | else |
d6b5193b | 10748 | return default_elf_select_rtx_section (mode, x, align); |
b64a1b53 RH |
10749 | } |
10750 | ||
1e1bd14e | 10751 | static unsigned int |
abb8b19a AM |
10752 | ia64_section_type_flags (tree decl, const char *name, int reloc) |
10753 | { | |
10754 | unsigned int flags = 0; | |
10755 | ||
10756 | if (strcmp (name, ".sdata") == 0 | |
10757 | || strncmp (name, ".sdata.", 7) == 0 | |
10758 | || strncmp (name, ".gnu.linkonce.s.", 16) == 0 | |
10759 | || strncmp (name, ".sdata2.", 8) == 0 | |
10760 | || strncmp (name, ".gnu.linkonce.s2.", 17) == 0 | |
10761 | || strcmp (name, ".sbss") == 0 | |
10762 | || strncmp (name, ".sbss.", 6) == 0 | |
10763 | || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) | |
10764 | flags = SECTION_SMALL; | |
10765 | ||
9b580a0b | 10766 | flags |= default_section_type_flags (decl, name, reloc); |
abb8b19a | 10767 | return flags; |
1e1bd14e RH |
10768 | } |
10769 | ||
57782ad8 MM |
10770 | /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a |
10771 | structure type and that the address of that type should be passed | |
10772 | in out0, rather than in r8. */ | |
10773 | ||
10774 | static bool | |
10775 | ia64_struct_retval_addr_is_first_parm_p (tree fntype) | |
10776 | { | |
10777 | tree ret_type = TREE_TYPE (fntype); | |
10778 | ||
10779 | /* The Itanium C++ ABI requires that out0, rather than r8, be used | |
10780 | as the structure return address parameter, if the return value | |
10781 | type has a non-trivial copy constructor or destructor. It is not | |
10782 | clear if this same convention should be used for other | |
10783 | programming languages. Until G++ 3.4, we incorrectly used r8 for | |
10784 | these return values. */ | |
10785 | return (abi_version_at_least (2) | |
10786 | && ret_type | |
10787 | && TYPE_MODE (ret_type) == BLKmode | |
10788 | && TREE_ADDRESSABLE (ret_type) | |
dcc97066 | 10789 | && lang_GNU_CXX ()); |
57782ad8 | 10790 | } |
1e1bd14e | 10791 | |
5f13cfc6 RH |
10792 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
10793 | declaration for the thunk function itself, FUNCTION is the decl for | |
10794 | the target function. DELTA is an immediate constant offset to be | |
272d0bee | 10795 | added to THIS. If VCALL_OFFSET is nonzero, the word at |
5f13cfc6 RH |
10796 | *(*this + vcall_offset) should be added to THIS. */ |
10797 | ||
c590b625 | 10798 | static void |
9c808aad AJ |
10799 | ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
10800 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
10801 | tree function) | |
483ab821 | 10802 | { |
dd3d2b35 DM |
10803 | rtx this_rtx, funexp; |
10804 | rtx_insn *insn; | |
57782ad8 MM |
10805 | unsigned int this_parmno; |
10806 | unsigned int this_regno; | |
13f70342 | 10807 | rtx delta_rtx; |
5f13cfc6 | 10808 | |
599aedd9 | 10809 | reload_completed = 1; |
fe3ad572 | 10810 | epilogue_completed = 1; |
599aedd9 | 10811 | |
5f13cfc6 RH |
10812 | /* Set things up as ia64_expand_prologue might. */ |
10813 | last_scratch_gr_reg = 15; | |
10814 | ||
10815 | memset (¤t_frame_info, 0, sizeof (current_frame_info)); | |
10816 | current_frame_info.spill_cfa_off = -16; | |
10817 | current_frame_info.n_input_regs = 1; | |
10818 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
10819 | ||
5f13cfc6 | 10820 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 10821 | emit_note (NOTE_INSN_PROLOGUE_END); |
5f13cfc6 | 10822 | |
57782ad8 MM |
10823 | /* Figure out whether "this" will be the first parameter (the |
10824 | typical case) or the second parameter (as happens when the | |
10825 | virtual function returns certain class objects). */ | |
10826 | this_parmno | |
10827 | = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk)) | |
10828 | ? 1 : 0); | |
10829 | this_regno = IN_REG (this_parmno); | |
10830 | if (!TARGET_REG_NAMES) | |
10831 | reg_names[this_regno] = ia64_reg_numbers[this_parmno]; | |
10832 | ||
0a2aaacc | 10833 | this_rtx = gen_rtx_REG (Pmode, this_regno); |
13f70342 RH |
10834 | |
10835 | /* Apply the constant offset, if required. */ | |
10836 | delta_rtx = GEN_INT (delta); | |
36c216e5 MM |
10837 | if (TARGET_ILP32) |
10838 | { | |
57782ad8 | 10839 | rtx tmp = gen_rtx_REG (ptr_mode, this_regno); |
36c216e5 | 10840 | REG_POINTER (tmp) = 1; |
13f70342 | 10841 | if (delta && satisfies_constraint_I (delta_rtx)) |
36c216e5 | 10842 | { |
0a2aaacc | 10843 | emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx)); |
36c216e5 MM |
10844 | delta = 0; |
10845 | } | |
10846 | else | |
0a2aaacc | 10847 | emit_insn (gen_ptr_extend (this_rtx, tmp)); |
36c216e5 | 10848 | } |
5f13cfc6 RH |
10849 | if (delta) |
10850 | { | |
13f70342 | 10851 | if (!satisfies_constraint_I (delta_rtx)) |
5f13cfc6 RH |
10852 | { |
10853 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10854 | emit_move_insn (tmp, delta_rtx); | |
10855 | delta_rtx = tmp; | |
10856 | } | |
0a2aaacc | 10857 | emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx)); |
5f13cfc6 RH |
10858 | } |
10859 | ||
10860 | /* Apply the offset from the vtable, if required. */ | |
10861 | if (vcall_offset) | |
10862 | { | |
10863 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
10864 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10865 | ||
36c216e5 MM |
10866 | if (TARGET_ILP32) |
10867 | { | |
10868 | rtx t = gen_rtx_REG (ptr_mode, 2); | |
10869 | REG_POINTER (t) = 1; | |
0a2aaacc | 10870 | emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx)); |
13f70342 | 10871 | if (satisfies_constraint_I (vcall_offset_rtx)) |
36c216e5 | 10872 | { |
13f70342 | 10873 | emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx)); |
36c216e5 MM |
10874 | vcall_offset = 0; |
10875 | } | |
10876 | else | |
10877 | emit_insn (gen_ptr_extend (tmp, t)); | |
10878 | } | |
10879 | else | |
0a2aaacc | 10880 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
5f13cfc6 | 10881 | |
36c216e5 | 10882 | if (vcall_offset) |
5f13cfc6 | 10883 | { |
13f70342 | 10884 | if (!satisfies_constraint_J (vcall_offset_rtx)) |
36c216e5 MM |
10885 | { |
10886 | rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ()); | |
10887 | emit_move_insn (tmp2, vcall_offset_rtx); | |
10888 | vcall_offset_rtx = tmp2; | |
10889 | } | |
10890 | emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
5f13cfc6 | 10891 | } |
5f13cfc6 | 10892 | |
36c216e5 | 10893 | if (TARGET_ILP32) |
13f70342 | 10894 | emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp))); |
36c216e5 MM |
10895 | else |
10896 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
5f13cfc6 | 10897 | |
0a2aaacc | 10898 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
5f13cfc6 RH |
10899 | } |
10900 | ||
10901 | /* Generate a tail call to the target function. */ | |
10902 | if (! TREE_USED (function)) | |
10903 | { | |
10904 | assemble_external (function); | |
10905 | TREE_USED (function) = 1; | |
10906 | } | |
10907 | funexp = XEXP (DECL_RTL (function), 0); | |
10908 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
10909 | ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1); | |
10910 | insn = get_last_insn (); | |
10911 | SIBLING_CALL_P (insn) = 1; | |
599aedd9 RH |
10912 | |
10913 | /* Code generation for calls relies on splitting. */ | |
10914 | reload_completed = 1; | |
fe3ad572 | 10915 | epilogue_completed = 1; |
599aedd9 RH |
10916 | try_split (PATTERN (insn), insn, 0); |
10917 | ||
5f13cfc6 RH |
10918 | emit_barrier (); |
10919 | ||
10920 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
10921 | There's not really enough bulk here to make other passes such as | |
10922 | instruction scheduling worth while. Note that use_thunk calls | |
10923 | assemble_start_function and assemble_end_function. */ | |
599aedd9 | 10924 | |
18dbd950 | 10925 | emit_all_insn_group_barriers (NULL); |
5f13cfc6 | 10926 | insn = get_insns (); |
5f13cfc6 RH |
10927 | shorten_branches (insn); |
10928 | final_start_function (insn, file, 1); | |
c9d691e9 | 10929 | final (insn, file, 1); |
5f13cfc6 | 10930 | final_end_function (); |
599aedd9 RH |
10931 | |
10932 | reload_completed = 0; | |
fe3ad572 | 10933 | epilogue_completed = 0; |
483ab821 MM |
10934 | } |
10935 | ||
351a758b KH |
10936 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
10937 | ||
10938 | static rtx | |
57782ad8 | 10939 | ia64_struct_value_rtx (tree fntype, |
351a758b KH |
10940 | int incoming ATTRIBUTE_UNUSED) |
10941 | { | |
f2972bf8 DR |
10942 | if (TARGET_ABI_OPEN_VMS || |
10943 | (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))) | |
57782ad8 | 10944 | return NULL_RTX; |
351a758b KH |
10945 | return gen_rtx_REG (Pmode, GR_REG (8)); |
10946 | } | |
10947 | ||
88ed5ef5 | 10948 | static bool |
ef4bddc2 | 10949 | ia64_scalar_mode_supported_p (machine_mode mode) |
88ed5ef5 SE |
10950 | { |
10951 | switch (mode) | |
10952 | { | |
10953 | case QImode: | |
10954 | case HImode: | |
10955 | case SImode: | |
10956 | case DImode: | |
10957 | case TImode: | |
10958 | return true; | |
10959 | ||
10960 | case SFmode: | |
10961 | case DFmode: | |
10962 | case XFmode: | |
4de67c26 | 10963 | case RFmode: |
88ed5ef5 SE |
10964 | return true; |
10965 | ||
10966 | case TFmode: | |
c252db20 | 10967 | return true; |
88ed5ef5 SE |
10968 | |
10969 | default: | |
10970 | return false; | |
10971 | } | |
10972 | } | |
10973 | ||
f61134e8 | 10974 | static bool |
ef4bddc2 | 10975 | ia64_vector_mode_supported_p (machine_mode mode) |
f61134e8 RH |
10976 | { |
10977 | switch (mode) | |
10978 | { | |
10979 | case V8QImode: | |
10980 | case V4HImode: | |
10981 | case V2SImode: | |
10982 | return true; | |
10983 | ||
10984 | case V2SFmode: | |
10985 | return true; | |
10986 | ||
10987 | default: | |
10988 | return false; | |
10989 | } | |
10990 | } | |
10991 | ||
8cc4b7a2 JM |
10992 | /* Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P. */ |
10993 | ||
10994 | static bool | |
ef4bddc2 | 10995 | ia64_libgcc_floating_mode_supported_p (machine_mode mode) |
8cc4b7a2 JM |
10996 | { |
10997 | switch (mode) | |
10998 | { | |
10999 | case SFmode: | |
11000 | case DFmode: | |
11001 | return true; | |
11002 | ||
11003 | case XFmode: | |
11004 | #ifdef IA64_NO_LIBGCC_XFMODE | |
11005 | return false; | |
11006 | #else | |
11007 | return true; | |
11008 | #endif | |
11009 | ||
11010 | case TFmode: | |
11011 | #ifdef IA64_NO_LIBGCC_TFMODE | |
11012 | return false; | |
11013 | #else | |
11014 | return true; | |
11015 | #endif | |
11016 | ||
11017 | default: | |
11018 | return false; | |
11019 | } | |
11020 | } | |
11021 | ||
694a2f6e EB |
11022 | /* Implement the FUNCTION_PROFILER macro. */ |
11023 | ||
2b4f149b RH |
11024 | void |
11025 | ia64_output_function_profiler (FILE *file, int labelno) | |
11026 | { | |
694a2f6e EB |
11027 | bool indirect_call; |
11028 | ||
11029 | /* If the function needs a static chain and the static chain | |
11030 | register is r15, we use an indirect call so as to bypass | |
11031 | the PLT stub in case the executable is dynamically linked, | |
11032 | because the stub clobbers r15 as per 5.3.6 of the psABI. | |
11033 | We don't need to do that in non canonical PIC mode. */ | |
11034 | ||
11035 | if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC) | |
11036 | { | |
11037 | gcc_assert (STATIC_CHAIN_REGNUM == 15); | |
11038 | indirect_call = true; | |
11039 | } | |
11040 | else | |
11041 | indirect_call = false; | |
11042 | ||
2b4f149b RH |
11043 | if (TARGET_GNU_AS) |
11044 | fputs ("\t.prologue 4, r40\n", file); | |
11045 | else | |
11046 | fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file); | |
11047 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file); | |
bd8633a3 RH |
11048 | |
11049 | if (NO_PROFILE_COUNTERS) | |
694a2f6e | 11050 | fputs ("\tmov out3 = r0\n", file); |
bd8633a3 RH |
11051 | else |
11052 | { | |
11053 | char buf[20]; | |
11054 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
11055 | ||
11056 | if (TARGET_AUTO_PIC) | |
11057 | fputs ("\tmovl out3 = @gprel(", file); | |
11058 | else | |
11059 | fputs ("\taddl out3 = @ltoff(", file); | |
11060 | assemble_name (file, buf); | |
11061 | if (TARGET_AUTO_PIC) | |
694a2f6e | 11062 | fputs (")\n", file); |
bd8633a3 | 11063 | else |
694a2f6e | 11064 | fputs ("), r1\n", file); |
bd8633a3 RH |
11065 | } |
11066 | ||
694a2f6e EB |
11067 | if (indirect_call) |
11068 | fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file); | |
11069 | fputs ("\t;;\n", file); | |
11070 | ||
2b4f149b | 11071 | fputs ("\t.save rp, r42\n", file); |
bd8633a3 | 11072 | fputs ("\tmov out2 = b0\n", file); |
694a2f6e EB |
11073 | if (indirect_call) |
11074 | fputs ("\tld8 r14 = [r14]\n\t;;\n", file); | |
2b4f149b | 11075 | fputs ("\t.body\n", file); |
2b4f149b | 11076 | fputs ("\tmov out1 = r1\n", file); |
694a2f6e EB |
11077 | if (indirect_call) |
11078 | { | |
11079 | fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file); | |
11080 | fputs ("\tmov b6 = r16\n", file); | |
11081 | fputs ("\tld8 r1 = [r14]\n", file); | |
11082 | fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file); | |
11083 | } | |
11084 | else | |
11085 | fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file); | |
2b4f149b RH |
11086 | } |
11087 | ||
d26afa4f SE |
11088 | static GTY(()) rtx mcount_func_rtx; |
11089 | static rtx | |
11090 | gen_mcount_func_rtx (void) | |
11091 | { | |
11092 | if (!mcount_func_rtx) | |
11093 | mcount_func_rtx = init_one_libfunc ("_mcount"); | |
11094 | return mcount_func_rtx; | |
11095 | } | |
11096 | ||
11097 | void | |
11098 | ia64_profile_hook (int labelno) | |
11099 | { | |
11100 | rtx label, ip; | |
11101 | ||
11102 | if (NO_PROFILE_COUNTERS) | |
11103 | label = const0_rtx; | |
11104 | else | |
11105 | { | |
11106 | char buf[30]; | |
11107 | const char *label_name; | |
11108 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
55504c7c | 11109 | label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf)); |
d26afa4f SE |
11110 | label = gen_rtx_SYMBOL_REF (Pmode, label_name); |
11111 | SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL; | |
11112 | } | |
11113 | ip = gen_reg_rtx (Pmode); | |
11114 | emit_insn (gen_ip_value (ip)); | |
11115 | emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL, | |
11116 | VOIDmode, 3, | |
11117 | gen_rtx_REG (Pmode, BR_REG (0)), Pmode, | |
11118 | ip, Pmode, | |
11119 | label, Pmode); | |
11120 | } | |
11121 | ||
cac24f06 JM |
11122 | /* Return the mangling of TYPE if it is an extended fundamental type. */ |
11123 | ||
11124 | static const char * | |
3101faab | 11125 | ia64_mangle_type (const_tree type) |
cac24f06 | 11126 | { |
608063c3 JB |
11127 | type = TYPE_MAIN_VARIANT (type); |
11128 | ||
11129 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
11130 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
11131 | return NULL; | |
11132 | ||
cac24f06 JM |
11133 | /* On HP-UX, "long double" is mangled as "e" so __float128 is |
11134 | mangled as "e". */ | |
11135 | if (!TARGET_HPUX && TYPE_MODE (type) == TFmode) | |
11136 | return "g"; | |
11137 | /* On HP-UX, "e" is not available as a mangling of __float80 so use | |
11138 | an extended mangling. Elsewhere, "e" is available since long | |
11139 | double is 80 bits. */ | |
11140 | if (TYPE_MODE (type) == XFmode) | |
11141 | return TARGET_HPUX ? "u9__float80" : "e"; | |
4de67c26 JM |
11142 | if (TYPE_MODE (type) == RFmode) |
11143 | return "u7__fpreg"; | |
11144 | return NULL; | |
11145 | } | |
11146 | ||
11147 | /* Return the diagnostic message string if conversion from FROMTYPE to | |
11148 | TOTYPE is not allowed, NULL otherwise. */ | |
11149 | static const char * | |
3101faab | 11150 | ia64_invalid_conversion (const_tree fromtype, const_tree totype) |
4de67c26 JM |
11151 | { |
11152 | /* Reject nontrivial conversion to or from __fpreg. */ | |
11153 | if (TYPE_MODE (fromtype) == RFmode | |
11154 | && TYPE_MODE (totype) != RFmode | |
11155 | && TYPE_MODE (totype) != VOIDmode) | |
11156 | return N_("invalid conversion from %<__fpreg%>"); | |
11157 | if (TYPE_MODE (totype) == RFmode | |
11158 | && TYPE_MODE (fromtype) != RFmode) | |
11159 | return N_("invalid conversion to %<__fpreg%>"); | |
11160 | return NULL; | |
11161 | } | |
11162 | ||
11163 | /* Return the diagnostic message string if the unary operation OP is | |
11164 | not permitted on TYPE, NULL otherwise. */ | |
11165 | static const char * | |
3101faab | 11166 | ia64_invalid_unary_op (int op, const_tree type) |
4de67c26 JM |
11167 | { |
11168 | /* Reject operations on __fpreg other than unary + or &. */ | |
11169 | if (TYPE_MODE (type) == RFmode | |
11170 | && op != CONVERT_EXPR | |
11171 | && op != ADDR_EXPR) | |
11172 | return N_("invalid operation on %<__fpreg%>"); | |
11173 | return NULL; | |
11174 | } | |
11175 | ||
11176 | /* Return the diagnostic message string if the binary operation OP is | |
11177 | not permitted on TYPE1 and TYPE2, NULL otherwise. */ | |
11178 | static const char * | |
3101faab | 11179 | ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2) |
4de67c26 JM |
11180 | { |
11181 | /* Reject operations on __fpreg. */ | |
11182 | if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode) | |
11183 | return N_("invalid operation on %<__fpreg%>"); | |
cac24f06 JM |
11184 | return NULL; |
11185 | } | |
11186 | ||
812b587e SE |
11187 | /* HP-UX version_id attribute. |
11188 | For object foo, if the version_id is set to 1234 put out an alias | |
11189 | of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything | |
11190 | other than an alias statement because it is an illegal symbol name. */ | |
11191 | ||
11192 | static tree | |
11193 | ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED, | |
11194 | tree name ATTRIBUTE_UNUSED, | |
11195 | tree args, | |
11196 | int flags ATTRIBUTE_UNUSED, | |
11197 | bool *no_add_attrs) | |
11198 | { | |
11199 | tree arg = TREE_VALUE (args); | |
11200 | ||
11201 | if (TREE_CODE (arg) != STRING_CST) | |
11202 | { | |
11203 | error("version attribute is not a string"); | |
11204 | *no_add_attrs = true; | |
11205 | return NULL_TREE; | |
11206 | } | |
11207 | return NULL_TREE; | |
11208 | } | |
11209 | ||
a31fa2e0 SE |
11210 | /* Target hook for c_mode_for_suffix. */ |
11211 | ||
ef4bddc2 | 11212 | static machine_mode |
a31fa2e0 SE |
11213 | ia64_c_mode_for_suffix (char suffix) |
11214 | { | |
11215 | if (suffix == 'q') | |
11216 | return TFmode; | |
11217 | if (suffix == 'w') | |
11218 | return XFmode; | |
11219 | ||
11220 | return VOIDmode; | |
11221 | } | |
11222 | ||
f3a83111 SE |
11223 | static GTY(()) rtx ia64_dconst_0_5_rtx; |
11224 | ||
11225 | rtx | |
11226 | ia64_dconst_0_5 (void) | |
11227 | { | |
11228 | if (! ia64_dconst_0_5_rtx) | |
11229 | { | |
11230 | REAL_VALUE_TYPE rv; | |
11231 | real_from_string (&rv, "0.5"); | |
11232 | ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode); | |
11233 | } | |
11234 | return ia64_dconst_0_5_rtx; | |
11235 | } | |
11236 | ||
11237 | static GTY(()) rtx ia64_dconst_0_375_rtx; | |
11238 | ||
11239 | rtx | |
11240 | ia64_dconst_0_375 (void) | |
11241 | { | |
11242 | if (! ia64_dconst_0_375_rtx) | |
11243 | { | |
11244 | REAL_VALUE_TYPE rv; | |
11245 | real_from_string (&rv, "0.375"); | |
11246 | ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode); | |
11247 | } | |
11248 | return ia64_dconst_0_375_rtx; | |
11249 | } | |
11250 | ||
ef4bddc2 | 11251 | static machine_mode |
ffa88471 SE |
11252 | ia64_get_reg_raw_mode (int regno) |
11253 | { | |
11254 | if (FR_REGNO_P (regno)) | |
11255 | return XFmode; | |
11256 | return default_get_reg_raw_mode(regno); | |
11257 | } | |
f3a83111 | 11258 | |
d9886a9e L |
11259 | /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed |
11260 | anymore. */ | |
11261 | ||
11262 | bool | |
ef4bddc2 | 11263 | ia64_member_type_forces_blk (const_tree, machine_mode mode) |
d9886a9e L |
11264 | { |
11265 | return TARGET_HPUX && mode == TFmode; | |
11266 | } | |
11267 | ||
f16d3f39 JH |
11268 | /* Always default to .text section until HP-UX linker is fixed. */ |
11269 | ||
11270 | ATTRIBUTE_UNUSED static section * | |
11271 | ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED, | |
11272 | enum node_frequency freq ATTRIBUTE_UNUSED, | |
11273 | bool startup ATTRIBUTE_UNUSED, | |
11274 | bool exit ATTRIBUTE_UNUSED) | |
11275 | { | |
11276 | return NULL; | |
11277 | } | |
e6431744 RH |
11278 | \f |
11279 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
11280 | return true if that's a valid instruction in the active ISA. */ | |
11281 | ||
11282 | static bool | |
11283 | expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt) | |
11284 | { | |
11285 | rtx rperm[MAX_VECT_LEN], x; | |
11286 | unsigned i; | |
11287 | ||
11288 | for (i = 0; i < nelt; ++i) | |
11289 | rperm[i] = GEN_INT (perm[i]); | |
11290 | ||
11291 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
11292 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
11293 | x = gen_rtx_SET (VOIDmode, target, x); | |
11294 | ||
647d790d DM |
11295 | rtx_insn *insn = emit_insn (x); |
11296 | if (recog_memoized (insn) < 0) | |
e6431744 | 11297 | { |
647d790d | 11298 | remove_insn (insn); |
e6431744 RH |
11299 | return false; |
11300 | } | |
11301 | return true; | |
11302 | } | |
11303 | ||
11304 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
11305 | ||
11306 | static bool | |
11307 | expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
11308 | const unsigned char *perm, unsigned nelt) | |
11309 | { | |
ef4bddc2 | 11310 | machine_mode v2mode; |
e6431744 RH |
11311 | rtx x; |
11312 | ||
11313 | v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); | |
11314 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); | |
11315 | return expand_vselect (target, x, perm, nelt); | |
11316 | } | |
11317 | ||
11318 | /* Try to expand a no-op permutation. */ | |
11319 | ||
11320 | static bool | |
11321 | expand_vec_perm_identity (struct expand_vec_perm_d *d) | |
11322 | { | |
11323 | unsigned i, nelt = d->nelt; | |
11324 | ||
11325 | for (i = 0; i < nelt; ++i) | |
11326 | if (d->perm[i] != i) | |
11327 | return false; | |
11328 | ||
11329 | if (!d->testing_p) | |
11330 | emit_move_insn (d->target, d->op0); | |
11331 | ||
11332 | return true; | |
11333 | } | |
11334 | ||
11335 | /* Try to expand D via a shrp instruction. */ | |
11336 | ||
11337 | static bool | |
11338 | expand_vec_perm_shrp (struct expand_vec_perm_d *d) | |
11339 | { | |
11340 | unsigned i, nelt = d->nelt, shift, mask; | |
2d130b31 | 11341 | rtx tmp, hi, lo; |
e6431744 RH |
11342 | |
11343 | /* ??? Don't force V2SFmode into the integer registers. */ | |
11344 | if (d->vmode == V2SFmode) | |
11345 | return false; | |
11346 | ||
11347 | mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1); | |
11348 | ||
11349 | shift = d->perm[0]; | |
2d130b31 UB |
11350 | if (BYTES_BIG_ENDIAN && shift > nelt) |
11351 | return false; | |
11352 | ||
e6431744 RH |
11353 | for (i = 1; i < nelt; ++i) |
11354 | if (d->perm[i] != ((shift + i) & mask)) | |
11355 | return false; | |
11356 | ||
11357 | if (d->testing_p) | |
11358 | return true; | |
11359 | ||
2d130b31 UB |
11360 | hi = shift < nelt ? d->op1 : d->op0; |
11361 | lo = shift < nelt ? d->op0 : d->op1; | |
11362 | ||
11363 | shift %= nelt; | |
11364 | ||
e6431744 RH |
11365 | shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT; |
11366 | ||
11367 | /* We've eliminated the shift 0 case via expand_vec_perm_identity. */ | |
11368 | gcc_assert (IN_RANGE (shift, 1, 63)); | |
11369 | ||
11370 | /* Recall that big-endian elements are numbered starting at the top of | |
11371 | the register. Ideally we'd have a shift-left-pair. But since we | |
11372 | don't, convert to a shift the other direction. */ | |
11373 | if (BYTES_BIG_ENDIAN) | |
11374 | shift = 64 - shift; | |
11375 | ||
11376 | tmp = gen_reg_rtx (DImode); | |
2d130b31 UB |
11377 | hi = gen_lowpart (DImode, hi); |
11378 | lo = gen_lowpart (DImode, lo); | |
11379 | emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift))); | |
e6431744 RH |
11380 | |
11381 | emit_move_insn (d->target, gen_lowpart (d->vmode, tmp)); | |
11382 | return true; | |
11383 | } | |
11384 | ||
11385 | /* Try to instantiate D in a single instruction. */ | |
11386 | ||
11387 | static bool | |
11388 | expand_vec_perm_1 (struct expand_vec_perm_d *d) | |
11389 | { | |
11390 | unsigned i, nelt = d->nelt; | |
11391 | unsigned char perm2[MAX_VECT_LEN]; | |
11392 | ||
11393 | /* Try single-operand selections. */ | |
11394 | if (d->one_operand_p) | |
11395 | { | |
11396 | if (expand_vec_perm_identity (d)) | |
11397 | return true; | |
11398 | if (expand_vselect (d->target, d->op0, d->perm, nelt)) | |
11399 | return true; | |
11400 | } | |
11401 | ||
11402 | /* Try two operand selections. */ | |
11403 | if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt)) | |
11404 | return true; | |
11405 | ||
11406 | /* Recognize interleave style patterns with reversed operands. */ | |
11407 | if (!d->one_operand_p) | |
11408 | { | |
11409 | for (i = 0; i < nelt; ++i) | |
11410 | { | |
11411 | unsigned e = d->perm[i]; | |
11412 | if (e >= nelt) | |
11413 | e -= nelt; | |
11414 | else | |
11415 | e += nelt; | |
11416 | perm2[i] = e; | |
11417 | } | |
11418 | ||
11419 | if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
11420 | return true; | |
11421 | } | |
11422 | ||
11423 | if (expand_vec_perm_shrp (d)) | |
11424 | return true; | |
11425 | ||
11426 | /* ??? Look for deposit-like permutations where most of the result | |
11427 | comes from one vector unchanged and the rest comes from a | |
11428 | sequential hunk of the other vector. */ | |
11429 | ||
11430 | return false; | |
11431 | } | |
11432 | ||
11433 | /* Pattern match broadcast permutations. */ | |
11434 | ||
11435 | static bool | |
11436 | expand_vec_perm_broadcast (struct expand_vec_perm_d *d) | |
11437 | { | |
11438 | unsigned i, elt, nelt = d->nelt; | |
11439 | unsigned char perm2[2]; | |
11440 | rtx temp; | |
11441 | bool ok; | |
11442 | ||
11443 | if (!d->one_operand_p) | |
11444 | return false; | |
11445 | ||
11446 | elt = d->perm[0]; | |
11447 | for (i = 1; i < nelt; ++i) | |
11448 | if (d->perm[i] != elt) | |
11449 | return false; | |
11450 | ||
11451 | switch (d->vmode) | |
11452 | { | |
11453 | case V2SImode: | |
11454 | case V2SFmode: | |
11455 | /* Implementable by interleave. */ | |
11456 | perm2[0] = elt; | |
11457 | perm2[1] = elt + 2; | |
11458 | ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2); | |
11459 | gcc_assert (ok); | |
11460 | break; | |
11461 | ||
11462 | case V8QImode: | |
11463 | /* Implementable by extract + broadcast. */ | |
11464 | if (BYTES_BIG_ENDIAN) | |
11465 | elt = 7 - elt; | |
11466 | elt *= BITS_PER_UNIT; | |
11467 | temp = gen_reg_rtx (DImode); | |
11468 | emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0), | |
96fda42c | 11469 | GEN_INT (8), GEN_INT (elt))); |
e6431744 RH |
11470 | emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp))); |
11471 | break; | |
11472 | ||
11473 | case V4HImode: | |
11474 | /* Should have been matched directly by vec_select. */ | |
11475 | default: | |
11476 | gcc_unreachable (); | |
11477 | } | |
11478 | ||
11479 | return true; | |
11480 | } | |
11481 | ||
11482 | /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a | |
11483 | two vector permutation into a single vector permutation by using | |
11484 | an interleave operation to merge the vectors. */ | |
11485 | ||
11486 | static bool | |
11487 | expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d) | |
11488 | { | |
11489 | struct expand_vec_perm_d dremap, dfinal; | |
11490 | unsigned char remap[2 * MAX_VECT_LEN]; | |
11491 | unsigned contents, i, nelt, nelt2; | |
11492 | unsigned h0, h1, h2, h3; | |
dd3d2b35 | 11493 | rtx_insn *seq; |
e6431744 RH |
11494 | bool ok; |
11495 | ||
11496 | if (d->one_operand_p) | |
11497 | return false; | |
11498 | ||
11499 | nelt = d->nelt; | |
11500 | nelt2 = nelt / 2; | |
11501 | ||
11502 | /* Examine from whence the elements come. */ | |
11503 | contents = 0; | |
11504 | for (i = 0; i < nelt; ++i) | |
11505 | contents |= 1u << d->perm[i]; | |
11506 | ||
11507 | memset (remap, 0xff, sizeof (remap)); | |
11508 | dremap = *d; | |
11509 | ||
11510 | h0 = (1u << nelt2) - 1; | |
11511 | h1 = h0 << nelt2; | |
11512 | h2 = h0 << nelt; | |
11513 | h3 = h0 << (nelt + nelt2); | |
11514 | ||
11515 | if ((contents & (h0 | h2)) == contents) /* punpck even halves */ | |
11516 | { | |
11517 | for (i = 0; i < nelt; ++i) | |
11518 | { | |
11519 | unsigned which = i / 2 + (i & 1 ? nelt : 0); | |
11520 | remap[which] = i; | |
11521 | dremap.perm[i] = which; | |
11522 | } | |
11523 | } | |
11524 | else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */ | |
11525 | { | |
11526 | for (i = 0; i < nelt; ++i) | |
11527 | { | |
11528 | unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0); | |
11529 | remap[which] = i; | |
11530 | dremap.perm[i] = which; | |
11531 | } | |
11532 | } | |
11533 | else if ((contents & 0x5555) == contents) /* mix even elements */ | |
11534 | { | |
11535 | for (i = 0; i < nelt; ++i) | |
11536 | { | |
11537 | unsigned which = (i & ~1) + (i & 1 ? nelt : 0); | |
11538 | remap[which] = i; | |
11539 | dremap.perm[i] = which; | |
11540 | } | |
11541 | } | |
11542 | else if ((contents & 0xaaaa) == contents) /* mix odd elements */ | |
11543 | { | |
11544 | for (i = 0; i < nelt; ++i) | |
11545 | { | |
11546 | unsigned which = (i | 1) + (i & 1 ? nelt : 0); | |
11547 | remap[which] = i; | |
11548 | dremap.perm[i] = which; | |
11549 | } | |
11550 | } | |
11551 | else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */ | |
11552 | { | |
11553 | unsigned shift = ctz_hwi (contents); | |
11554 | for (i = 0; i < nelt; ++i) | |
11555 | { | |
11556 | unsigned which = (i + shift) & (2 * nelt - 1); | |
11557 | remap[which] = i; | |
11558 | dremap.perm[i] = which; | |
11559 | } | |
11560 | } | |
11561 | else | |
11562 | return false; | |
11563 | ||
11564 | /* Use the remapping array set up above to move the elements from their | |
11565 | swizzled locations into their final destinations. */ | |
11566 | dfinal = *d; | |
11567 | for (i = 0; i < nelt; ++i) | |
11568 | { | |
11569 | unsigned e = remap[d->perm[i]]; | |
11570 | gcc_assert (e < nelt); | |
11571 | dfinal.perm[i] = e; | |
11572 | } | |
b4b78e2d EB |
11573 | if (d->testing_p) |
11574 | dfinal.op0 = gen_raw_REG (dfinal.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11575 | else | |
11576 | dfinal.op0 = gen_reg_rtx (dfinal.vmode); | |
e6431744 RH |
11577 | dfinal.op1 = dfinal.op0; |
11578 | dfinal.one_operand_p = true; | |
11579 | dremap.target = dfinal.op0; | |
11580 | ||
11581 | /* Test if the final remap can be done with a single insn. For V4HImode | |
11582 | this *will* succeed. For V8QImode or V2SImode it may not. */ | |
11583 | start_sequence (); | |
11584 | ok = expand_vec_perm_1 (&dfinal); | |
11585 | seq = get_insns (); | |
11586 | end_sequence (); | |
11587 | if (!ok) | |
11588 | return false; | |
11589 | if (d->testing_p) | |
11590 | return true; | |
11591 | ||
11592 | ok = expand_vec_perm_1 (&dremap); | |
11593 | gcc_assert (ok); | |
11594 | ||
11595 | emit_insn (seq); | |
11596 | return true; | |
11597 | } | |
11598 | ||
11599 | /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode | |
11600 | constant permutation via two mux2 and a merge. */ | |
11601 | ||
11602 | static bool | |
11603 | expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d) | |
11604 | { | |
11605 | unsigned char perm2[4]; | |
11606 | rtx rmask[4]; | |
11607 | unsigned i; | |
11608 | rtx t0, t1, mask, x; | |
11609 | bool ok; | |
11610 | ||
11611 | if (d->vmode != V4HImode || d->one_operand_p) | |
11612 | return false; | |
11613 | if (d->testing_p) | |
11614 | return true; | |
11615 | ||
11616 | for (i = 0; i < 4; ++i) | |
11617 | { | |
11618 | perm2[i] = d->perm[i] & 3; | |
11619 | rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx); | |
11620 | } | |
11621 | mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask)); | |
11622 | mask = force_reg (V4HImode, mask); | |
11623 | ||
11624 | t0 = gen_reg_rtx (V4HImode); | |
11625 | t1 = gen_reg_rtx (V4HImode); | |
11626 | ||
11627 | ok = expand_vselect (t0, d->op0, perm2, 4); | |
11628 | gcc_assert (ok); | |
11629 | ok = expand_vselect (t1, d->op1, perm2, 4); | |
11630 | gcc_assert (ok); | |
11631 | ||
11632 | x = gen_rtx_AND (V4HImode, mask, t0); | |
11633 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
11634 | ||
11635 | x = gen_rtx_NOT (V4HImode, mask); | |
11636 | x = gen_rtx_AND (V4HImode, x, t1); | |
11637 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
11638 | ||
11639 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
11640 | emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); | |
11641 | ||
11642 | return true; | |
11643 | } | |
11644 | ||
11645 | /* The guts of ia64_expand_vec_perm_const, also used by the ok hook. | |
11646 | With all of the interface bits taken care of, perform the expansion | |
11647 | in D and return true on success. */ | |
11648 | ||
11649 | static bool | |
11650 | ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
11651 | { | |
11652 | if (expand_vec_perm_1 (d)) | |
11653 | return true; | |
11654 | if (expand_vec_perm_broadcast (d)) | |
11655 | return true; | |
11656 | if (expand_vec_perm_interleave_2 (d)) | |
11657 | return true; | |
11658 | if (expand_vec_perm_v4hi_5 (d)) | |
11659 | return true; | |
11660 | return false; | |
11661 | } | |
11662 | ||
11663 | bool | |
11664 | ia64_expand_vec_perm_const (rtx operands[4]) | |
11665 | { | |
11666 | struct expand_vec_perm_d d; | |
11667 | unsigned char perm[MAX_VECT_LEN]; | |
11668 | int i, nelt, which; | |
11669 | rtx sel; | |
11670 | ||
11671 | d.target = operands[0]; | |
11672 | d.op0 = operands[1]; | |
11673 | d.op1 = operands[2]; | |
11674 | sel = operands[3]; | |
11675 | ||
11676 | d.vmode = GET_MODE (d.target); | |
11677 | gcc_assert (VECTOR_MODE_P (d.vmode)); | |
11678 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11679 | d.testing_p = false; | |
11680 | ||
11681 | gcc_assert (GET_CODE (sel) == CONST_VECTOR); | |
11682 | gcc_assert (XVECLEN (sel, 0) == nelt); | |
11683 | gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); | |
11684 | ||
11685 | for (i = which = 0; i < nelt; ++i) | |
11686 | { | |
11687 | rtx e = XVECEXP (sel, 0, i); | |
11688 | int ei = INTVAL (e) & (2 * nelt - 1); | |
11689 | ||
11690 | which |= (ei < nelt ? 1 : 2); | |
11691 | d.perm[i] = ei; | |
11692 | perm[i] = ei; | |
11693 | } | |
11694 | ||
11695 | switch (which) | |
11696 | { | |
11697 | default: | |
11698 | gcc_unreachable(); | |
11699 | ||
11700 | case 3: | |
11701 | if (!rtx_equal_p (d.op0, d.op1)) | |
11702 | { | |
11703 | d.one_operand_p = false; | |
11704 | break; | |
11705 | } | |
11706 | ||
11707 | /* The elements of PERM do not suggest that only the first operand | |
11708 | is used, but both operands are identical. Allow easier matching | |
11709 | of the permutation by folding the permutation into the single | |
11710 | input vector. */ | |
11711 | for (i = 0; i < nelt; ++i) | |
11712 | if (d.perm[i] >= nelt) | |
11713 | d.perm[i] -= nelt; | |
11714 | /* FALLTHRU */ | |
11715 | ||
11716 | case 1: | |
11717 | d.op1 = d.op0; | |
11718 | d.one_operand_p = true; | |
11719 | break; | |
11720 | ||
11721 | case 2: | |
11722 | for (i = 0; i < nelt; ++i) | |
11723 | d.perm[i] -= nelt; | |
11724 | d.op0 = d.op1; | |
11725 | d.one_operand_p = true; | |
11726 | break; | |
11727 | } | |
11728 | ||
11729 | if (ia64_expand_vec_perm_const_1 (&d)) | |
11730 | return true; | |
11731 | ||
11732 | /* If the mask says both arguments are needed, but they are the same, | |
11733 | the above tried to expand with one_operand_p true. If that didn't | |
11734 | work, retry with one_operand_p false, as that's what we used in _ok. */ | |
11735 | if (which == 3 && d.one_operand_p) | |
11736 | { | |
11737 | memcpy (d.perm, perm, sizeof (perm)); | |
11738 | d.one_operand_p = false; | |
11739 | return ia64_expand_vec_perm_const_1 (&d); | |
11740 | } | |
11741 | ||
11742 | return false; | |
11743 | } | |
11744 | ||
11745 | /* Implement targetm.vectorize.vec_perm_const_ok. */ | |
11746 | ||
11747 | static bool | |
ef4bddc2 | 11748 | ia64_vectorize_vec_perm_const_ok (machine_mode vmode, |
e6431744 RH |
11749 | const unsigned char *sel) |
11750 | { | |
11751 | struct expand_vec_perm_d d; | |
11752 | unsigned int i, nelt, which; | |
11753 | bool ret; | |
11754 | ||
11755 | d.vmode = vmode; | |
11756 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11757 | d.testing_p = true; | |
11758 | ||
11759 | /* Extract the values from the vector CST into the permutation | |
11760 | array in D. */ | |
11761 | memcpy (d.perm, sel, nelt); | |
11762 | for (i = which = 0; i < nelt; ++i) | |
11763 | { | |
11764 | unsigned char e = d.perm[i]; | |
11765 | gcc_assert (e < 2 * nelt); | |
11766 | which |= (e < nelt ? 1 : 2); | |
11767 | } | |
11768 | ||
11769 | /* For all elements from second vector, fold the elements to first. */ | |
11770 | if (which == 2) | |
11771 | for (i = 0; i < nelt; ++i) | |
11772 | d.perm[i] -= nelt; | |
11773 | ||
11774 | /* Check whether the mask can be applied to the vector type. */ | |
11775 | d.one_operand_p = (which != 3); | |
11776 | ||
11777 | /* Otherwise we have to go through the motions and see if we can | |
11778 | figure out how to generate the requested permutation. */ | |
11779 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11780 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
11781 | if (!d.one_operand_p) | |
11782 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
11783 | ||
11784 | start_sequence (); | |
11785 | ret = ia64_expand_vec_perm_const_1 (&d); | |
11786 | end_sequence (); | |
11787 | ||
11788 | return ret; | |
11789 | } | |
11790 | ||
11791 | void | |
11792 | ia64_expand_vec_setv2sf (rtx operands[3]) | |
11793 | { | |
11794 | struct expand_vec_perm_d d; | |
11795 | unsigned int which; | |
11796 | bool ok; | |
11797 | ||
11798 | d.target = operands[0]; | |
11799 | d.op0 = operands[0]; | |
11800 | d.op1 = gen_reg_rtx (V2SFmode); | |
11801 | d.vmode = V2SFmode; | |
11802 | d.nelt = 2; | |
11803 | d.one_operand_p = false; | |
11804 | d.testing_p = false; | |
11805 | ||
11806 | which = INTVAL (operands[2]); | |
11807 | gcc_assert (which <= 1); | |
11808 | d.perm[0] = 1 - which; | |
11809 | d.perm[1] = which + 2; | |
11810 | ||
11811 | emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode))); | |
11812 | ||
11813 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11814 | gcc_assert (ok); | |
11815 | } | |
11816 | ||
11817 | void | |
11818 | ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd) | |
11819 | { | |
11820 | struct expand_vec_perm_d d; | |
ef4bddc2 | 11821 | machine_mode vmode = GET_MODE (target); |
e6431744 RH |
11822 | unsigned int i, nelt = GET_MODE_NUNITS (vmode); |
11823 | bool ok; | |
11824 | ||
11825 | d.target = target; | |
11826 | d.op0 = op0; | |
11827 | d.op1 = op1; | |
11828 | d.vmode = vmode; | |
11829 | d.nelt = nelt; | |
11830 | d.one_operand_p = false; | |
11831 | d.testing_p = false; | |
11832 | ||
11833 | for (i = 0; i < nelt; ++i) | |
11834 | d.perm[i] = i * 2 + odd; | |
11835 | ||
11836 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11837 | gcc_assert (ok); | |
11838 | } | |
f16d3f39 | 11839 | |
e2500fed | 11840 | #include "gt-ia64.h" |