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c65ebc55 | 1 | /* Definitions of target machine for GNU compiler. |
66647d44 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
96e45421 | 3 | 2009, 2010, 2011 |
7b5cbb57 | 4 | Free Software Foundation, Inc. |
c65ebc55 | 5 | Contributed by James E. Wilson <wilson@cygnus.com> and |
9c808aad | 6 | David Mosberger <davidm@hpl.hp.com>. |
c65ebc55 | 7 | |
3bed2930 | 8 | This file is part of GCC. |
c65ebc55 | 9 | |
3bed2930 | 10 | GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 11 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
13 | any later version. |
14 | ||
3bed2930 | 15 | GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
c65ebc55 | 23 | |
c65ebc55 | 24 | #include "config.h" |
ed9ccd8a | 25 | #include "system.h" |
4977bab6 ZW |
26 | #include "coretypes.h" |
27 | #include "tm.h" | |
c65ebc55 JW |
28 | #include "rtl.h" |
29 | #include "tree.h" | |
c65ebc55 JW |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
c65ebc55 JW |
32 | #include "insn-config.h" |
33 | #include "conditions.h" | |
c65ebc55 JW |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
e78d8e51 | 39 | #include "optabs.h" |
c65ebc55 JW |
40 | #include "except.h" |
41 | #include "function.h" | |
42 | #include "ggc.h" | |
43 | #include "basic-block.h" | |
f2972bf8 | 44 | #include "libfuncs.h" |
718f9c0f | 45 | #include "diagnostic-core.h" |
2130b7fb | 46 | #include "sched-int.h" |
eced69b5 | 47 | #include "timevar.h" |
672a6f42 NB |
48 | #include "target.h" |
49 | #include "target-def.h" | |
7b84aac0 | 50 | #include "common/common-target.h" |
98d2b17e | 51 | #include "tm_p.h" |
30028c85 | 52 | #include "hashtab.h" |
08744705 | 53 | #include "langhooks.h" |
726a989a | 54 | #include "gimple.h" |
4de67c26 | 55 | #include "intl.h" |
6fb5fa3c | 56 | #include "df.h" |
658f32fd | 57 | #include "debug.h" |
bb83aa4b | 58 | #include "params.h" |
6fb5fa3c | 59 | #include "dbgcnt.h" |
13f70342 | 60 | #include "tm-constrs.h" |
388092d5 | 61 | #include "sel-sched.h" |
69e18c09 | 62 | #include "reload.h" |
712959e9 | 63 | #include "dwarf2out.h" |
96e45421 | 64 | #include "opts.h" |
c65ebc55 JW |
65 | |
66 | /* This is used for communication between ASM_OUTPUT_LABEL and | |
67 | ASM_OUTPUT_LABELREF. */ | |
68 | int ia64_asm_output_label = 0; | |
69 | ||
c65ebc55 | 70 | /* Register names for ia64_expand_prologue. */ |
3b572406 | 71 | static const char * const ia64_reg_numbers[96] = |
c65ebc55 JW |
72 | { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
73 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
74 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
75 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
76 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
77 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
78 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
79 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
80 | "r96", "r97", "r98", "r99", "r100","r101","r102","r103", | |
81 | "r104","r105","r106","r107","r108","r109","r110","r111", | |
82 | "r112","r113","r114","r115","r116","r117","r118","r119", | |
83 | "r120","r121","r122","r123","r124","r125","r126","r127"}; | |
84 | ||
85 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 86 | static const char * const ia64_input_reg_names[8] = |
c65ebc55 JW |
87 | { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" }; |
88 | ||
89 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 90 | static const char * const ia64_local_reg_names[80] = |
c65ebc55 JW |
91 | { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", |
92 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", | |
93 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", | |
94 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", | |
95 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", | |
96 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", | |
97 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", | |
98 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", | |
99 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", | |
100 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" }; | |
101 | ||
102 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 103 | static const char * const ia64_output_reg_names[8] = |
c65ebc55 JW |
104 | { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" }; |
105 | ||
c65ebc55 JW |
106 | /* Variables which are this size or smaller are put in the sdata/sbss |
107 | sections. */ | |
108 | ||
3b572406 | 109 | unsigned int ia64_section_threshold; |
30028c85 VM |
110 | |
111 | /* The following variable is used by the DFA insn scheduler. The value is | |
112 | TRUE if we do insn bundling instead of insn scheduling. */ | |
113 | int bundling_p = 0; | |
114 | ||
6fb5fa3c DB |
115 | enum ia64_frame_regs |
116 | { | |
117 | reg_fp, | |
118 | reg_save_b0, | |
119 | reg_save_pr, | |
120 | reg_save_ar_pfs, | |
121 | reg_save_ar_unat, | |
122 | reg_save_ar_lc, | |
123 | reg_save_gp, | |
124 | number_of_ia64_frame_regs | |
125 | }; | |
126 | ||
599aedd9 RH |
127 | /* Structure to be filled in by ia64_compute_frame_size with register |
128 | save masks and offsets for the current function. */ | |
129 | ||
130 | struct ia64_frame_info | |
131 | { | |
132 | HOST_WIDE_INT total_size; /* size of the stack frame, not including | |
133 | the caller's scratch area. */ | |
134 | HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */ | |
135 | HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */ | |
136 | HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */ | |
137 | HARD_REG_SET mask; /* mask of saved registers. */ | |
9c808aad | 138 | unsigned int gr_used_mask; /* mask of registers in use as gr spill |
599aedd9 RH |
139 | registers or long-term scratches. */ |
140 | int n_spilled; /* number of spilled registers. */ | |
6fb5fa3c | 141 | int r[number_of_ia64_frame_regs]; /* Frame related registers. */ |
599aedd9 RH |
142 | int n_input_regs; /* number of input registers used. */ |
143 | int n_local_regs; /* number of local registers used. */ | |
144 | int n_output_regs; /* number of output registers used. */ | |
145 | int n_rotate_regs; /* number of rotating registers used. */ | |
146 | ||
147 | char need_regstk; /* true if a .regstk directive needed. */ | |
148 | char initialized; /* true if the data is finalized. */ | |
149 | }; | |
150 | ||
151 | /* Current frame information calculated by ia64_compute_frame_size. */ | |
152 | static struct ia64_frame_info current_frame_info; | |
6fb5fa3c DB |
153 | /* The actual registers that are emitted. */ |
154 | static int emitted_frame_related_regs[number_of_ia64_frame_regs]; | |
3b572406 | 155 | \f |
9c808aad AJ |
156 | static int ia64_first_cycle_multipass_dfa_lookahead (void); |
157 | static void ia64_dependencies_evaluation_hook (rtx, rtx); | |
158 | static void ia64_init_dfa_pre_cycle_insn (void); | |
159 | static rtx ia64_dfa_pre_cycle_insn (void); | |
160 | static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx); | |
3101faab | 161 | static bool ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx); |
9c808aad | 162 | static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *); |
048d0d36 | 163 | static void ia64_h_i_d_extended (void); |
388092d5 AB |
164 | static void * ia64_alloc_sched_context (void); |
165 | static void ia64_init_sched_context (void *, bool); | |
166 | static void ia64_set_sched_context (void *); | |
167 | static void ia64_clear_sched_context (void *); | |
168 | static void ia64_free_sched_context (void *); | |
048d0d36 MK |
169 | static int ia64_mode_to_int (enum machine_mode); |
170 | static void ia64_set_sched_flags (spec_info_t); | |
388092d5 AB |
171 | static ds_t ia64_get_insn_spec_ds (rtx); |
172 | static ds_t ia64_get_insn_checked_ds (rtx); | |
173 | static bool ia64_skip_rtx_p (const_rtx); | |
048d0d36 | 174 | static int ia64_speculate_insn (rtx, ds_t, rtx *); |
388092d5 AB |
175 | static bool ia64_needs_block_p (int); |
176 | static rtx ia64_gen_spec_check (rtx, rtx, ds_t); | |
048d0d36 MK |
177 | static int ia64_spec_check_p (rtx); |
178 | static int ia64_spec_check_src_p (rtx); | |
9c808aad AJ |
179 | static rtx gen_tls_get_addr (void); |
180 | static rtx gen_thread_pointer (void); | |
6fb5fa3c | 181 | static int find_gr_spill (enum ia64_frame_regs, int); |
9c808aad AJ |
182 | static int next_scratch_gr_reg (void); |
183 | static void mark_reg_gr_used_mask (rtx, void *); | |
184 | static void ia64_compute_frame_size (HOST_WIDE_INT); | |
185 | static void setup_spill_pointers (int, rtx, HOST_WIDE_INT); | |
186 | static void finish_spill_pointers (void); | |
187 | static rtx spill_restore_mem (rtx, HOST_WIDE_INT); | |
188 | static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx); | |
189 | static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT); | |
190 | static rtx gen_movdi_x (rtx, rtx, rtx); | |
191 | static rtx gen_fr_spill_x (rtx, rtx, rtx); | |
192 | static rtx gen_fr_restore_x (rtx, rtx, rtx); | |
193 | ||
930572b9 | 194 | static void ia64_option_override (void); |
7b5cbb57 | 195 | static bool ia64_can_eliminate (const int, const int); |
586de218 | 196 | static enum machine_mode hfa_element_mode (const_tree, bool); |
d5cc9181 | 197 | static void ia64_setup_incoming_varargs (cumulative_args_t, enum machine_mode, |
351a758b | 198 | tree, int *, int); |
d5cc9181 | 199 | static int ia64_arg_partial_bytes (cumulative_args_t, enum machine_mode, |
78a52f11 | 200 | tree, bool); |
d5cc9181 | 201 | static rtx ia64_function_arg_1 (cumulative_args_t, enum machine_mode, |
ffa88471 | 202 | const_tree, bool, bool); |
d5cc9181 | 203 | static rtx ia64_function_arg (cumulative_args_t, enum machine_mode, |
ffa88471 | 204 | const_tree, bool); |
d5cc9181 | 205 | static rtx ia64_function_incoming_arg (cumulative_args_t, |
ffa88471 | 206 | enum machine_mode, const_tree, bool); |
d5cc9181 | 207 | static void ia64_function_arg_advance (cumulative_args_t, enum machine_mode, |
ffa88471 | 208 | const_tree, bool); |
c2ed6cf8 NF |
209 | static unsigned int ia64_function_arg_boundary (enum machine_mode, |
210 | const_tree); | |
9c808aad | 211 | static bool ia64_function_ok_for_sibcall (tree, tree); |
586de218 | 212 | static bool ia64_return_in_memory (const_tree, const_tree); |
ba90d838 AS |
213 | static rtx ia64_function_value (const_tree, const_tree, bool); |
214 | static rtx ia64_libcall_value (enum machine_mode, const_rtx); | |
215 | static bool ia64_function_value_regno_p (const unsigned int); | |
c21fc181 JR |
216 | static int ia64_register_move_cost (enum machine_mode, reg_class_t, |
217 | reg_class_t); | |
69e18c09 AS |
218 | static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t, |
219 | bool); | |
68f932c4 | 220 | static bool ia64_rtx_costs (rtx, int, int, int, int *, bool); |
215b063c | 221 | static int ia64_unspec_may_trap_p (const_rtx, unsigned); |
9c808aad AJ |
222 | static void fix_range (const char *); |
223 | static struct machine_function * ia64_init_machine_status (void); | |
224 | static void emit_insn_group_barriers (FILE *); | |
225 | static void emit_all_insn_group_barriers (FILE *); | |
226 | static void final_emit_insn_group_barriers (FILE *); | |
227 | static void emit_predicate_relation_info (void); | |
228 | static void ia64_reorg (void); | |
3101faab | 229 | static bool ia64_in_small_data_p (const_tree); |
658f32fd | 230 | static void process_epilogue (FILE *, rtx, bool, bool); |
9c808aad | 231 | |
9c808aad AJ |
232 | static bool ia64_assemble_integer (rtx, unsigned int, int); |
233 | static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT); | |
234 | static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
235 | static void ia64_output_function_end_prologue (FILE *); | |
236 | ||
5e50b799 AS |
237 | static void ia64_print_operand (FILE *, rtx, int); |
238 | static void ia64_print_operand_address (FILE *, rtx); | |
239 | static bool ia64_print_operand_punct_valid_p (unsigned char code); | |
240 | ||
9c808aad | 241 | static int ia64_issue_rate (void); |
388092d5 | 242 | static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t); |
9c808aad | 243 | static void ia64_sched_init (FILE *, int, int); |
048d0d36 MK |
244 | static void ia64_sched_init_global (FILE *, int, int); |
245 | static void ia64_sched_finish_global (FILE *, int); | |
9c808aad AJ |
246 | static void ia64_sched_finish (FILE *, int); |
247 | static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int); | |
248 | static int ia64_sched_reorder (FILE *, int, rtx *, int *, int); | |
249 | static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int); | |
250 | static int ia64_variable_issue (FILE *, int, rtx, int); | |
251 | ||
a68b5e52 RH |
252 | static void ia64_asm_unwind_emit (FILE *, rtx); |
253 | static void ia64_asm_emit_except_personality (rtx); | |
254 | static void ia64_asm_init_sections (void); | |
255 | ||
f0a0390e | 256 | static enum unwind_info_type ia64_debug_unwind_info (void); |
f0a0390e | 257 | |
9c808aad AJ |
258 | static struct bundle_state *get_free_bundle_state (void); |
259 | static void free_bundle_state (struct bundle_state *); | |
260 | static void initiate_bundle_states (void); | |
261 | static void finish_bundle_states (void); | |
262 | static unsigned bundle_state_hash (const void *); | |
263 | static int bundle_state_eq_p (const void *, const void *); | |
264 | static int insert_bundle_state (struct bundle_state *); | |
265 | static void initiate_bundle_state_table (void); | |
266 | static void finish_bundle_state_table (void); | |
267 | static int try_issue_nops (struct bundle_state *, int); | |
268 | static int try_issue_insn (struct bundle_state *, rtx); | |
269 | static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int); | |
270 | static int get_max_pos (state_t); | |
271 | static int get_template (state_t, int); | |
272 | ||
273 | static rtx get_next_important_insn (rtx, rtx); | |
388092d5 | 274 | static bool important_for_bundling_p (rtx); |
7b84aac0 | 275 | static bool unknown_for_bundling_p (rtx); |
9c808aad AJ |
276 | static void bundling (FILE *, int, rtx, rtx); |
277 | ||
278 | static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
279 | HOST_WIDE_INT, tree); | |
280 | static void ia64_file_start (void); | |
812b587e | 281 | static void ia64_globalize_decl_name (FILE *, tree); |
9c808aad | 282 | |
9b580a0b RH |
283 | static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED; |
284 | static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED; | |
d6b5193b RS |
285 | static section *ia64_select_rtx_section (enum machine_mode, rtx, |
286 | unsigned HOST_WIDE_INT); | |
fdbe66f2 EB |
287 | static void ia64_output_dwarf_dtprel (FILE *, int, rtx) |
288 | ATTRIBUTE_UNUSED; | |
abb8b19a | 289 | static unsigned int ia64_section_type_flags (tree, const char *, int); |
1f7aa7cd SE |
290 | static void ia64_init_libfuncs (void) |
291 | ATTRIBUTE_UNUSED; | |
c15c90bb ZW |
292 | static void ia64_hpux_init_libfuncs (void) |
293 | ATTRIBUTE_UNUSED; | |
6bc709c1 L |
294 | static void ia64_sysv4_init_libfuncs (void) |
295 | ATTRIBUTE_UNUSED; | |
738e7b39 RK |
296 | static void ia64_vms_init_libfuncs (void) |
297 | ATTRIBUTE_UNUSED; | |
c252db20 L |
298 | static void ia64_soft_fp_init_libfuncs (void) |
299 | ATTRIBUTE_UNUSED; | |
f2972bf8 DR |
300 | static bool ia64_vms_valid_pointer_mode (enum machine_mode mode) |
301 | ATTRIBUTE_UNUSED; | |
30ed9d3d TG |
302 | static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *) |
303 | ATTRIBUTE_UNUSED; | |
a5fe455b | 304 | |
a32767e4 | 305 | static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *); |
812b587e | 306 | static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *); |
a32767e4 | 307 | static void ia64_encode_section_info (tree, rtx, int); |
351a758b | 308 | static rtx ia64_struct_value_rtx (tree, int); |
726a989a | 309 | static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
88ed5ef5 | 310 | static bool ia64_scalar_mode_supported_p (enum machine_mode mode); |
f61134e8 | 311 | static bool ia64_vector_mode_supported_p (enum machine_mode mode); |
1a627b35 | 312 | static bool ia64_legitimate_constant_p (enum machine_mode, rtx); |
903a9601 | 313 | static bool ia64_legitimate_address_p (enum machine_mode, rtx, bool); |
fbbf66e7 | 314 | static bool ia64_cannot_force_const_mem (enum machine_mode, rtx); |
3101faab KG |
315 | static const char *ia64_mangle_type (const_tree); |
316 | static const char *ia64_invalid_conversion (const_tree, const_tree); | |
317 | static const char *ia64_invalid_unary_op (int, const_tree); | |
318 | static const char *ia64_invalid_binary_op (int, const_tree, const_tree); | |
a31fa2e0 | 319 | static enum machine_mode ia64_c_mode_for_suffix (char); |
2a1211e5 | 320 | static void ia64_trampoline_init (rtx, tree, rtx); |
2b7e2984 | 321 | static void ia64_override_options_after_change (void); |
5c255b57 | 322 | |
b14446e2 | 323 | static tree ia64_builtin_decl (unsigned, bool); |
ab177ad5 AS |
324 | |
325 | static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t); | |
ffa88471 | 326 | static enum machine_mode ia64_get_reg_raw_mode (int regno); |
f16d3f39 JH |
327 | static section * ia64_hpux_function_section (tree, enum node_frequency, |
328 | bool, bool); | |
e6431744 RH |
329 | |
330 | static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode, | |
331 | const unsigned char *sel); | |
332 | ||
333 | #define MAX_VECT_LEN 8 | |
334 | ||
335 | struct expand_vec_perm_d | |
336 | { | |
337 | rtx target, op0, op1; | |
338 | unsigned char perm[MAX_VECT_LEN]; | |
339 | enum machine_mode vmode; | |
340 | unsigned char nelt; | |
341 | bool one_operand_p; | |
342 | bool testing_p; | |
343 | }; | |
344 | ||
345 | static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d); | |
346 | ||
672a6f42 | 347 | \f |
e6542f4e RH |
348 | /* Table of valid machine attributes. */ |
349 | static const struct attribute_spec ia64_attribute_table[] = | |
350 | { | |
62d784f7 KT |
351 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
352 | affects_type_identity } */ | |
353 | { "syscall_linkage", 0, 0, false, true, true, NULL, false }, | |
354 | { "model", 1, 1, true, false, false, ia64_handle_model_attribute, | |
355 | false }, | |
30ed9d3d | 356 | #if TARGET_ABI_OPEN_VMS |
62d784f7 KT |
357 | { "common_object", 1, 1, true, false, false, |
358 | ia64_vms_common_object_attribute, false }, | |
30ed9d3d | 359 | #endif |
812b587e | 360 | { "version_id", 1, 1, true, false, false, |
62d784f7 KT |
361 | ia64_handle_version_id_attribute, false }, |
362 | { NULL, 0, 0, false, false, false, NULL, false } | |
e6542f4e RH |
363 | }; |
364 | ||
672a6f42 | 365 | /* Initialize the GCC target structure. */ |
91d231cb JM |
366 | #undef TARGET_ATTRIBUTE_TABLE |
367 | #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table | |
672a6f42 | 368 | |
f6155fda SS |
369 | #undef TARGET_INIT_BUILTINS |
370 | #define TARGET_INIT_BUILTINS ia64_init_builtins | |
371 | ||
372 | #undef TARGET_EXPAND_BUILTIN | |
373 | #define TARGET_EXPAND_BUILTIN ia64_expand_builtin | |
374 | ||
b14446e2 SE |
375 | #undef TARGET_BUILTIN_DECL |
376 | #define TARGET_BUILTIN_DECL ia64_builtin_decl | |
377 | ||
301d03af RS |
378 | #undef TARGET_ASM_BYTE_OP |
379 | #define TARGET_ASM_BYTE_OP "\tdata1\t" | |
380 | #undef TARGET_ASM_ALIGNED_HI_OP | |
381 | #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t" | |
382 | #undef TARGET_ASM_ALIGNED_SI_OP | |
383 | #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t" | |
384 | #undef TARGET_ASM_ALIGNED_DI_OP | |
385 | #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t" | |
386 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
387 | #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t" | |
388 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
389 | #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t" | |
390 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
391 | #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t" | |
392 | #undef TARGET_ASM_INTEGER | |
393 | #define TARGET_ASM_INTEGER ia64_assemble_integer | |
394 | ||
930572b9 AS |
395 | #undef TARGET_OPTION_OVERRIDE |
396 | #define TARGET_OPTION_OVERRIDE ia64_option_override | |
397 | ||
08c148a8 NB |
398 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
399 | #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue | |
b4c25db2 NB |
400 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE |
401 | #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue | |
08c148a8 NB |
402 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
403 | #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue | |
404 | ||
5e50b799 AS |
405 | #undef TARGET_PRINT_OPERAND |
406 | #define TARGET_PRINT_OPERAND ia64_print_operand | |
407 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
408 | #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address | |
409 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
410 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p | |
411 | ||
ae46c4e0 RH |
412 | #undef TARGET_IN_SMALL_DATA_P |
413 | #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p | |
414 | ||
388092d5 AB |
415 | #undef TARGET_SCHED_ADJUST_COST_2 |
416 | #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2 | |
c237e94a ZW |
417 | #undef TARGET_SCHED_ISSUE_RATE |
418 | #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate | |
419 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
420 | #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue | |
421 | #undef TARGET_SCHED_INIT | |
422 | #define TARGET_SCHED_INIT ia64_sched_init | |
423 | #undef TARGET_SCHED_FINISH | |
424 | #define TARGET_SCHED_FINISH ia64_sched_finish | |
048d0d36 MK |
425 | #undef TARGET_SCHED_INIT_GLOBAL |
426 | #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global | |
427 | #undef TARGET_SCHED_FINISH_GLOBAL | |
428 | #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global | |
c237e94a ZW |
429 | #undef TARGET_SCHED_REORDER |
430 | #define TARGET_SCHED_REORDER ia64_sched_reorder | |
431 | #undef TARGET_SCHED_REORDER2 | |
432 | #define TARGET_SCHED_REORDER2 ia64_sched_reorder2 | |
c237e94a | 433 | |
30028c85 VM |
434 | #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK |
435 | #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook | |
436 | ||
30028c85 VM |
437 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
438 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead | |
439 | ||
440 | #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN | |
441 | #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn | |
442 | #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN | |
443 | #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn | |
444 | ||
445 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD | |
446 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\ | |
447 | ia64_first_cycle_multipass_dfa_lookahead_guard | |
448 | ||
449 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
450 | #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle | |
451 | ||
048d0d36 MK |
452 | #undef TARGET_SCHED_H_I_D_EXTENDED |
453 | #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended | |
454 | ||
388092d5 AB |
455 | #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT |
456 | #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context | |
457 | ||
458 | #undef TARGET_SCHED_INIT_SCHED_CONTEXT | |
459 | #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context | |
460 | ||
461 | #undef TARGET_SCHED_SET_SCHED_CONTEXT | |
462 | #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context | |
463 | ||
464 | #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT | |
465 | #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context | |
466 | ||
467 | #undef TARGET_SCHED_FREE_SCHED_CONTEXT | |
468 | #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context | |
469 | ||
048d0d36 MK |
470 | #undef TARGET_SCHED_SET_SCHED_FLAGS |
471 | #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags | |
472 | ||
388092d5 AB |
473 | #undef TARGET_SCHED_GET_INSN_SPEC_DS |
474 | #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds | |
475 | ||
476 | #undef TARGET_SCHED_GET_INSN_CHECKED_DS | |
477 | #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds | |
478 | ||
048d0d36 MK |
479 | #undef TARGET_SCHED_SPECULATE_INSN |
480 | #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn | |
481 | ||
482 | #undef TARGET_SCHED_NEEDS_BLOCK_P | |
483 | #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p | |
484 | ||
e855c69d | 485 | #undef TARGET_SCHED_GEN_SPEC_CHECK |
388092d5 | 486 | #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check |
048d0d36 MK |
487 | |
488 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC | |
489 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD_SPEC\ | |
490 | ia64_first_cycle_multipass_dfa_lookahead_guard_spec | |
491 | ||
388092d5 AB |
492 | #undef TARGET_SCHED_SKIP_RTX_P |
493 | #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p | |
494 | ||
599aedd9 RH |
495 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
496 | #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall | |
78a52f11 RH |
497 | #undef TARGET_ARG_PARTIAL_BYTES |
498 | #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes | |
ffa88471 SE |
499 | #undef TARGET_FUNCTION_ARG |
500 | #define TARGET_FUNCTION_ARG ia64_function_arg | |
501 | #undef TARGET_FUNCTION_INCOMING_ARG | |
502 | #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg | |
503 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
504 | #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance | |
c2ed6cf8 NF |
505 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
506 | #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary | |
599aedd9 | 507 | |
c590b625 RH |
508 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
509 | #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk | |
3961e8fe | 510 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 511 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 512 | |
1bc7c5b6 ZW |
513 | #undef TARGET_ASM_FILE_START |
514 | #define TARGET_ASM_FILE_START ia64_file_start | |
515 | ||
812b587e SE |
516 | #undef TARGET_ASM_GLOBALIZE_DECL_NAME |
517 | #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name | |
518 | ||
de8f4b07 AS |
519 | #undef TARGET_REGISTER_MOVE_COST |
520 | #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost | |
69e18c09 AS |
521 | #undef TARGET_MEMORY_MOVE_COST |
522 | #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost | |
3c50106f RH |
523 | #undef TARGET_RTX_COSTS |
524 | #define TARGET_RTX_COSTS ia64_rtx_costs | |
dcefdf67 | 525 | #undef TARGET_ADDRESS_COST |
8a88c276 | 526 | #define TARGET_ADDRESS_COST hook_int_rtx_bool_0 |
3c50106f | 527 | |
215b063c PB |
528 | #undef TARGET_UNSPEC_MAY_TRAP_P |
529 | #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p | |
530 | ||
18dbd950 RS |
531 | #undef TARGET_MACHINE_DEPENDENT_REORG |
532 | #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg | |
533 | ||
a32767e4 DM |
534 | #undef TARGET_ENCODE_SECTION_INFO |
535 | #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info | |
536 | ||
abb8b19a AM |
537 | #undef TARGET_SECTION_TYPE_FLAGS |
538 | #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags | |
539 | ||
fdbe66f2 EB |
540 | #ifdef HAVE_AS_TLS |
541 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
542 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel | |
543 | #endif | |
544 | ||
351a758b KH |
545 | /* ??? Investigate. */ |
546 | #if 0 | |
547 | #undef TARGET_PROMOTE_PROTOTYPES | |
548 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
549 | #endif | |
550 | ||
ba90d838 AS |
551 | #undef TARGET_FUNCTION_VALUE |
552 | #define TARGET_FUNCTION_VALUE ia64_function_value | |
553 | #undef TARGET_LIBCALL_VALUE | |
554 | #define TARGET_LIBCALL_VALUE ia64_libcall_value | |
555 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
556 | #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p | |
557 | ||
351a758b KH |
558 | #undef TARGET_STRUCT_VALUE_RTX |
559 | #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx | |
560 | #undef TARGET_RETURN_IN_MEMORY | |
561 | #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory | |
351a758b KH |
562 | #undef TARGET_SETUP_INCOMING_VARARGS |
563 | #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs | |
564 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
565 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
fe984136 RH |
566 | #undef TARGET_MUST_PASS_IN_STACK |
567 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
ffa88471 SE |
568 | #undef TARGET_GET_RAW_RESULT_MODE |
569 | #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode | |
570 | #undef TARGET_GET_RAW_ARG_MODE | |
571 | #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode | |
351a758b | 572 | |
cd3ce9b4 JM |
573 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
574 | #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg | |
575 | ||
38f8b050 | 576 | #undef TARGET_ASM_UNWIND_EMIT |
a68b5e52 RH |
577 | #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit |
578 | #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY | |
579 | #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality | |
580 | #undef TARGET_ASM_INIT_SECTIONS | |
581 | #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections | |
951120ea | 582 | |
f0a0390e RH |
583 | #undef TARGET_DEBUG_UNWIND_INFO |
584 | #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info | |
f0a0390e | 585 | |
88ed5ef5 SE |
586 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
587 | #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p | |
f61134e8 RH |
588 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
589 | #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p | |
88ed5ef5 | 590 | |
445cf5eb JM |
591 | /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur |
592 | in an order different from the specified program order. */ | |
593 | #undef TARGET_RELAXED_ORDERING | |
594 | #define TARGET_RELAXED_ORDERING true | |
595 | ||
1a627b35 RS |
596 | #undef TARGET_LEGITIMATE_CONSTANT_P |
597 | #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p | |
903a9601 AS |
598 | #undef TARGET_LEGITIMATE_ADDRESS_P |
599 | #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p | |
1a627b35 | 600 | |
5e6c8b64 RH |
601 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
602 | #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem | |
603 | ||
608063c3 JB |
604 | #undef TARGET_MANGLE_TYPE |
605 | #define TARGET_MANGLE_TYPE ia64_mangle_type | |
cac24f06 | 606 | |
4de67c26 JM |
607 | #undef TARGET_INVALID_CONVERSION |
608 | #define TARGET_INVALID_CONVERSION ia64_invalid_conversion | |
609 | #undef TARGET_INVALID_UNARY_OP | |
610 | #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op | |
611 | #undef TARGET_INVALID_BINARY_OP | |
612 | #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op | |
613 | ||
a31fa2e0 SE |
614 | #undef TARGET_C_MODE_FOR_SUFFIX |
615 | #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix | |
616 | ||
7b5cbb57 AS |
617 | #undef TARGET_CAN_ELIMINATE |
618 | #define TARGET_CAN_ELIMINATE ia64_can_eliminate | |
619 | ||
2a1211e5 RH |
620 | #undef TARGET_TRAMPOLINE_INIT |
621 | #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init | |
622 | ||
810d71d0 JW |
623 | #undef TARGET_INVALID_WITHIN_DOLOOP |
624 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null | |
625 | ||
2b7e2984 SE |
626 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
627 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change | |
628 | ||
ab177ad5 AS |
629 | #undef TARGET_PREFERRED_RELOAD_CLASS |
630 | #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class | |
631 | ||
2ba42841 AO |
632 | #undef TARGET_DELAY_SCHED2 |
633 | #define TARGET_DELAY_SCHED2 true | |
634 | ||
635 | /* Variable tracking should be run after all optimizations which | |
636 | change order of insns. It also needs a valid CFG. */ | |
637 | #undef TARGET_DELAY_VARTRACK | |
638 | #define TARGET_DELAY_VARTRACK true | |
639 | ||
e6431744 RH |
640 | #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK |
641 | #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok | |
642 | ||
f6897b10 | 643 | struct gcc_target targetm = TARGET_INITIALIZER; |
3b572406 | 644 | \f |
a32767e4 DM |
645 | typedef enum |
646 | { | |
647 | ADDR_AREA_NORMAL, /* normal address area */ | |
648 | ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */ | |
649 | } | |
650 | ia64_addr_area; | |
651 | ||
652 | static GTY(()) tree small_ident1; | |
653 | static GTY(()) tree small_ident2; | |
654 | ||
655 | static void | |
656 | init_idents (void) | |
657 | { | |
658 | if (small_ident1 == 0) | |
659 | { | |
660 | small_ident1 = get_identifier ("small"); | |
661 | small_ident2 = get_identifier ("__small__"); | |
662 | } | |
663 | } | |
664 | ||
665 | /* Retrieve the address area that has been chosen for the given decl. */ | |
666 | ||
667 | static ia64_addr_area | |
668 | ia64_get_addr_area (tree decl) | |
669 | { | |
670 | tree model_attr; | |
671 | ||
672 | model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); | |
673 | if (model_attr) | |
674 | { | |
675 | tree id; | |
676 | ||
677 | init_idents (); | |
678 | id = TREE_VALUE (TREE_VALUE (model_attr)); | |
679 | if (id == small_ident1 || id == small_ident2) | |
680 | return ADDR_AREA_SMALL; | |
681 | } | |
682 | return ADDR_AREA_NORMAL; | |
683 | } | |
684 | ||
685 | static tree | |
f61134e8 RH |
686 | ia64_handle_model_attribute (tree *node, tree name, tree args, |
687 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
a32767e4 DM |
688 | { |
689 | ia64_addr_area addr_area = ADDR_AREA_NORMAL; | |
690 | ia64_addr_area area; | |
691 | tree arg, decl = *node; | |
692 | ||
693 | init_idents (); | |
694 | arg = TREE_VALUE (args); | |
695 | if (arg == small_ident1 || arg == small_ident2) | |
696 | { | |
697 | addr_area = ADDR_AREA_SMALL; | |
698 | } | |
699 | else | |
700 | { | |
29d08eba JM |
701 | warning (OPT_Wattributes, "invalid argument of %qE attribute", |
702 | name); | |
a32767e4 DM |
703 | *no_add_attrs = true; |
704 | } | |
705 | ||
706 | switch (TREE_CODE (decl)) | |
707 | { | |
708 | case VAR_DECL: | |
709 | if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) | |
710 | == FUNCTION_DECL) | |
711 | && !TREE_STATIC (decl)) | |
712 | { | |
c5d75364 MLI |
713 | error_at (DECL_SOURCE_LOCATION (decl), |
714 | "an address area attribute cannot be specified for " | |
715 | "local variables"); | |
a32767e4 DM |
716 | *no_add_attrs = true; |
717 | } | |
718 | area = ia64_get_addr_area (decl); | |
719 | if (area != ADDR_AREA_NORMAL && addr_area != area) | |
720 | { | |
dee15844 JM |
721 | error ("address area of %q+D conflicts with previous " |
722 | "declaration", decl); | |
a32767e4 DM |
723 | *no_add_attrs = true; |
724 | } | |
725 | break; | |
726 | ||
727 | case FUNCTION_DECL: | |
c5d75364 | 728 | error_at (DECL_SOURCE_LOCATION (decl), |
d575725b L |
729 | "address area attribute cannot be specified for " |
730 | "functions"); | |
a32767e4 DM |
731 | *no_add_attrs = true; |
732 | break; | |
733 | ||
734 | default: | |
29d08eba JM |
735 | warning (OPT_Wattributes, "%qE attribute ignored", |
736 | name); | |
a32767e4 DM |
737 | *no_add_attrs = true; |
738 | break; | |
739 | } | |
740 | ||
741 | return NULL_TREE; | |
742 | } | |
743 | ||
30ed9d3d TG |
744 | /* Part of the low level implementation of DEC Ada pragma Common_Object which |
745 | enables the shared use of variables stored in overlaid linker areas | |
746 | corresponding to the use of Fortran COMMON. */ | |
747 | ||
748 | static tree | |
749 | ia64_vms_common_object_attribute (tree *node, tree name, tree args, | |
750 | int flags ATTRIBUTE_UNUSED, | |
751 | bool *no_add_attrs) | |
752 | { | |
753 | tree decl = *node; | |
fe5798c0 TG |
754 | tree id; |
755 | ||
756 | gcc_assert (DECL_P (decl)); | |
30ed9d3d TG |
757 | |
758 | DECL_COMMON (decl) = 1; | |
759 | id = TREE_VALUE (args); | |
fe5798c0 | 760 | if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) |
30ed9d3d | 761 | { |
fe5798c0 | 762 | error ("%qE attribute requires a string constant argument", name); |
30ed9d3d TG |
763 | *no_add_attrs = true; |
764 | return NULL_TREE; | |
765 | } | |
30ed9d3d TG |
766 | return NULL_TREE; |
767 | } | |
768 | ||
769 | /* Part of the low level implementation of DEC Ada pragma Common_Object. */ | |
770 | ||
771 | void | |
772 | ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name, | |
773 | unsigned HOST_WIDE_INT size, | |
774 | unsigned int align) | |
775 | { | |
776 | tree attr = DECL_ATTRIBUTES (decl); | |
777 | ||
fe5798c0 | 778 | if (attr) |
30ed9d3d | 779 | attr = lookup_attribute ("common_object", attr); |
fe5798c0 | 780 | if (attr) |
30ed9d3d | 781 | { |
fe5798c0 TG |
782 | tree id = TREE_VALUE (TREE_VALUE (attr)); |
783 | const char *name; | |
30ed9d3d | 784 | |
fe5798c0 TG |
785 | if (TREE_CODE (id) == IDENTIFIER_NODE) |
786 | name = IDENTIFIER_POINTER (id); | |
787 | else if (TREE_CODE (id) == STRING_CST) | |
788 | name = TREE_STRING_POINTER (id); | |
789 | else | |
790 | abort (); | |
30ed9d3d | 791 | |
fe5798c0 | 792 | fprintf (file, "\t.vms_common\t\"%s\",", name); |
30ed9d3d | 793 | } |
fe5798c0 TG |
794 | else |
795 | fprintf (file, "%s", COMMON_ASM_OP); | |
30ed9d3d | 796 | |
fe5798c0 TG |
797 | /* Code from elfos.h. */ |
798 | assemble_name (file, name); | |
799 | fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u", | |
800 | size, align / BITS_PER_UNIT); | |
30ed9d3d | 801 | |
fe5798c0 | 802 | fputc ('\n', file); |
30ed9d3d TG |
803 | } |
804 | ||
a32767e4 DM |
805 | static void |
806 | ia64_encode_addr_area (tree decl, rtx symbol) | |
807 | { | |
808 | int flags; | |
809 | ||
810 | flags = SYMBOL_REF_FLAGS (symbol); | |
811 | switch (ia64_get_addr_area (decl)) | |
812 | { | |
813 | case ADDR_AREA_NORMAL: break; | |
814 | case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break; | |
e820471b | 815 | default: gcc_unreachable (); |
a32767e4 DM |
816 | } |
817 | SYMBOL_REF_FLAGS (symbol) = flags; | |
818 | } | |
819 | ||
820 | static void | |
821 | ia64_encode_section_info (tree decl, rtx rtl, int first) | |
822 | { | |
823 | default_encode_section_info (decl, rtl, first); | |
824 | ||
2897f1d4 | 825 | /* Careful not to prod global register variables. */ |
a32767e4 | 826 | if (TREE_CODE (decl) == VAR_DECL |
2897f1d4 L |
827 | && GET_CODE (DECL_RTL (decl)) == MEM |
828 | && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF | |
a32767e4 DM |
829 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
830 | ia64_encode_addr_area (decl, XEXP (rtl, 0)); | |
831 | } | |
832 | \f | |
557b9df5 RH |
833 | /* Return 1 if the operands of a move are ok. */ |
834 | ||
835 | int | |
9c808aad | 836 | ia64_move_ok (rtx dst, rtx src) |
557b9df5 RH |
837 | { |
838 | /* If we're under init_recog_no_volatile, we'll not be able to use | |
839 | memory_operand. So check the code directly and don't worry about | |
840 | the validity of the underlying address, which should have been | |
841 | checked elsewhere anyway. */ | |
842 | if (GET_CODE (dst) != MEM) | |
843 | return 1; | |
844 | if (GET_CODE (src) == MEM) | |
845 | return 0; | |
846 | if (register_operand (src, VOIDmode)) | |
847 | return 1; | |
848 | ||
849 | /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */ | |
850 | if (INTEGRAL_MODE_P (GET_MODE (dst))) | |
851 | return src == const0_rtx; | |
852 | else | |
13f70342 | 853 | return satisfies_constraint_G (src); |
557b9df5 | 854 | } |
9b7bf67d | 855 | |
a71aef0b JB |
856 | /* Return 1 if the operands are ok for a floating point load pair. */ |
857 | ||
858 | int | |
859 | ia64_load_pair_ok (rtx dst, rtx src) | |
860 | { | |
22be5918 EB |
861 | /* ??? There is a thinko in the implementation of the "x" constraint and the |
862 | FP_REGS class. The constraint will also reject (reg f30:TI) so we must | |
863 | also return false for it. */ | |
864 | if (GET_CODE (dst) != REG | |
865 | || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1))) | |
a71aef0b JB |
866 | return 0; |
867 | if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src)) | |
868 | return 0; | |
869 | switch (GET_CODE (XEXP (src, 0))) | |
870 | { | |
871 | case REG: | |
872 | case POST_INC: | |
873 | break; | |
874 | case POST_DEC: | |
875 | return 0; | |
876 | case POST_MODIFY: | |
877 | { | |
878 | rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1); | |
879 | ||
880 | if (GET_CODE (adjust) != CONST_INT | |
881 | || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src))) | |
882 | return 0; | |
883 | } | |
884 | break; | |
885 | default: | |
886 | abort (); | |
887 | } | |
888 | return 1; | |
889 | } | |
890 | ||
08744705 | 891 | int |
9c808aad | 892 | addp4_optimize_ok (rtx op1, rtx op2) |
08744705 | 893 | { |
08744705 SE |
894 | return (basereg_operand (op1, GET_MODE(op1)) != |
895 | basereg_operand (op2, GET_MODE(op2))); | |
896 | } | |
897 | ||
9e4f94de | 898 | /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction. |
041f25e6 RH |
899 | Return the length of the field, or <= 0 on failure. */ |
900 | ||
901 | int | |
9c808aad | 902 | ia64_depz_field_mask (rtx rop, rtx rshift) |
041f25e6 RH |
903 | { |
904 | unsigned HOST_WIDE_INT op = INTVAL (rop); | |
905 | unsigned HOST_WIDE_INT shift = INTVAL (rshift); | |
906 | ||
907 | /* Get rid of the zero bits we're shifting in. */ | |
908 | op >>= shift; | |
909 | ||
910 | /* We must now have a solid block of 1's at bit 0. */ | |
911 | return exact_log2 (op + 1); | |
912 | } | |
913 | ||
5e6c8b64 RH |
914 | /* Return the TLS model to use for ADDR. */ |
915 | ||
916 | static enum tls_model | |
917 | tls_symbolic_operand_type (rtx addr) | |
918 | { | |
81f40b79 | 919 | enum tls_model tls_kind = TLS_MODEL_NONE; |
5e6c8b64 RH |
920 | |
921 | if (GET_CODE (addr) == CONST) | |
922 | { | |
923 | if (GET_CODE (XEXP (addr, 0)) == PLUS | |
924 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF) | |
925 | tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0)); | |
926 | } | |
927 | else if (GET_CODE (addr) == SYMBOL_REF) | |
928 | tls_kind = SYMBOL_REF_TLS_MODEL (addr); | |
929 | ||
930 | return tls_kind; | |
931 | } | |
932 | ||
903a9601 AS |
933 | /* Returns true if REG (assumed to be a `reg' RTX) is valid for use |
934 | as a base register. */ | |
935 | ||
936 | static inline bool | |
937 | ia64_reg_ok_for_base_p (const_rtx reg, bool strict) | |
938 | { | |
939 | if (strict | |
940 | && REGNO_OK_FOR_BASE_P (REGNO (reg))) | |
941 | return true; | |
942 | else if (!strict | |
943 | && (GENERAL_REGNO_P (REGNO (reg)) | |
944 | || !HARD_REGISTER_P (reg))) | |
945 | return true; | |
946 | else | |
947 | return false; | |
948 | } | |
949 | ||
950 | static bool | |
951 | ia64_legitimate_address_reg (const_rtx reg, bool strict) | |
952 | { | |
953 | if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict)) | |
954 | || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0)) | |
955 | && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict))) | |
956 | return true; | |
957 | ||
958 | return false; | |
959 | } | |
960 | ||
961 | static bool | |
962 | ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict) | |
963 | { | |
964 | if (GET_CODE (disp) == PLUS | |
965 | && rtx_equal_p (reg, XEXP (disp, 0)) | |
966 | && (ia64_legitimate_address_reg (XEXP (disp, 1), strict) | |
967 | || (CONST_INT_P (XEXP (disp, 1)) | |
968 | && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255)))) | |
969 | return true; | |
970 | ||
971 | return false; | |
972 | } | |
973 | ||
974 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ | |
975 | ||
976 | static bool | |
977 | ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
978 | rtx x, bool strict) | |
979 | { | |
980 | if (ia64_legitimate_address_reg (x, strict)) | |
981 | return true; | |
982 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
983 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
984 | && XEXP (x, 0) != arg_pointer_rtx) | |
985 | return true; | |
986 | else if (GET_CODE (x) == POST_MODIFY | |
987 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
988 | && XEXP (x, 0) != arg_pointer_rtx | |
989 | && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict)) | |
990 | return true; | |
991 | else | |
992 | return false; | |
993 | } | |
994 | ||
5e6c8b64 RH |
995 | /* Return true if X is a constant that is valid for some immediate |
996 | field in an instruction. */ | |
997 | ||
1a627b35 RS |
998 | static bool |
999 | ia64_legitimate_constant_p (enum machine_mode mode, rtx x) | |
5e6c8b64 RH |
1000 | { |
1001 | switch (GET_CODE (x)) | |
1002 | { | |
1003 | case CONST_INT: | |
1004 | case LABEL_REF: | |
1005 | return true; | |
1006 | ||
1007 | case CONST_DOUBLE: | |
1a627b35 | 1008 | if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode) |
5e6c8b64 | 1009 | return true; |
13f70342 | 1010 | return satisfies_constraint_G (x); |
5e6c8b64 RH |
1011 | |
1012 | case CONST: | |
1013 | case SYMBOL_REF: | |
d0970db2 JW |
1014 | /* ??? Short term workaround for PR 28490. We must make the code here |
1015 | match the code in ia64_expand_move and move_operand, even though they | |
1016 | are both technically wrong. */ | |
1017 | if (tls_symbolic_operand_type (x) == 0) | |
1018 | { | |
1019 | HOST_WIDE_INT addend = 0; | |
1020 | rtx op = x; | |
1021 | ||
1022 | if (GET_CODE (op) == CONST | |
1023 | && GET_CODE (XEXP (op, 0)) == PLUS | |
1024 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) | |
1025 | { | |
1026 | addend = INTVAL (XEXP (XEXP (op, 0), 1)); | |
1027 | op = XEXP (XEXP (op, 0), 0); | |
1028 | } | |
1029 | ||
1a627b35 RS |
1030 | if (any_offset_symbol_operand (op, mode) |
1031 | || function_operand (op, mode)) | |
7ab62966 | 1032 | return true; |
1a627b35 | 1033 | if (aligned_offset_symbol_operand (op, mode)) |
d0970db2 JW |
1034 | return (addend & 0x3fff) == 0; |
1035 | return false; | |
1036 | } | |
1037 | return false; | |
5e6c8b64 | 1038 | |
b4e3537b | 1039 | case CONST_VECTOR: |
1a627b35 RS |
1040 | if (mode == V2SFmode) |
1041 | return satisfies_constraint_Y (x); | |
b4e3537b | 1042 | |
1a627b35 RS |
1043 | return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT |
1044 | && GET_MODE_SIZE (mode) <= 8); | |
b4e3537b | 1045 | |
5e6c8b64 RH |
1046 | default: |
1047 | return false; | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | /* Don't allow TLS addresses to get spilled to memory. */ | |
1052 | ||
1053 | static bool | |
fbbf66e7 | 1054 | ia64_cannot_force_const_mem (enum machine_mode mode, rtx x) |
5e6c8b64 | 1055 | { |
fbbf66e7 | 1056 | if (mode == RFmode) |
103a6411 | 1057 | return true; |
5e6c8b64 RH |
1058 | return tls_symbolic_operand_type (x) != 0; |
1059 | } | |
1060 | ||
9b7bf67d | 1061 | /* Expand a symbolic constant load. */ |
9b7bf67d | 1062 | |
5e6c8b64 | 1063 | bool |
9c808aad | 1064 | ia64_expand_load_address (rtx dest, rtx src) |
9b7bf67d | 1065 | { |
e820471b | 1066 | gcc_assert (GET_CODE (dest) == REG); |
7b6e506e | 1067 | |
ae49d6e5 RH |
1068 | /* ILP32 mode still loads 64-bits of data from the GOT. This avoids |
1069 | having to pointer-extend the value afterward. Other forms of address | |
1070 | computation below are also more natural to compute as 64-bit quantities. | |
1071 | If we've been given an SImode destination register, change it. */ | |
1072 | if (GET_MODE (dest) != Pmode) | |
38ae7651 RS |
1073 | dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), |
1074 | byte_lowpart_offset (Pmode, GET_MODE (dest))); | |
ae49d6e5 | 1075 | |
5e6c8b64 RH |
1076 | if (TARGET_NO_PIC) |
1077 | return false; | |
1078 | if (small_addr_symbolic_operand (src, VOIDmode)) | |
1079 | return false; | |
1080 | ||
1081 | if (TARGET_AUTO_PIC) | |
1082 | emit_insn (gen_load_gprel64 (dest, src)); | |
1cdbd630 | 1083 | else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src)) |
5e6c8b64 | 1084 | emit_insn (gen_load_fptr (dest, src)); |
21515593 | 1085 | else if (sdata_symbolic_operand (src, VOIDmode)) |
5e6c8b64 RH |
1086 | emit_insn (gen_load_gprel (dest, src)); |
1087 | else | |
21515593 | 1088 | { |
5e6c8b64 RH |
1089 | HOST_WIDE_INT addend = 0; |
1090 | rtx tmp; | |
21515593 | 1091 | |
5e6c8b64 RH |
1092 | /* We did split constant offsets in ia64_expand_move, and we did try |
1093 | to keep them split in move_operand, but we also allowed reload to | |
1094 | rematerialize arbitrary constants rather than spill the value to | |
1095 | the stack and reload it. So we have to be prepared here to split | |
1096 | them apart again. */ | |
1097 | if (GET_CODE (src) == CONST) | |
1098 | { | |
1099 | HOST_WIDE_INT hi, lo; | |
9b7bf67d | 1100 | |
5e6c8b64 RH |
1101 | hi = INTVAL (XEXP (XEXP (src, 0), 1)); |
1102 | lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000; | |
1103 | hi = hi - lo; | |
9b7bf67d | 1104 | |
5e6c8b64 RH |
1105 | if (lo != 0) |
1106 | { | |
1107 | addend = lo; | |
0a81f074 | 1108 | src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi); |
5e6c8b64 RH |
1109 | } |
1110 | } | |
ae49d6e5 RH |
1111 | |
1112 | tmp = gen_rtx_HIGH (Pmode, src); | |
1113 | tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx); | |
1114 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1115 | ||
1f88caaa | 1116 | tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src); |
ae49d6e5 | 1117 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); |
5e6c8b64 RH |
1118 | |
1119 | if (addend) | |
1120 | { | |
1121 | tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend)); | |
1122 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1123 | } | |
ae49d6e5 | 1124 | } |
5e6c8b64 RH |
1125 | |
1126 | return true; | |
9b7bf67d | 1127 | } |
97e242b0 | 1128 | |
e2500fed | 1129 | static GTY(()) rtx gen_tls_tga; |
7b6e506e | 1130 | static rtx |
9c808aad | 1131 | gen_tls_get_addr (void) |
7b6e506e | 1132 | { |
e2500fed | 1133 | if (!gen_tls_tga) |
21515593 | 1134 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); |
e2500fed | 1135 | return gen_tls_tga; |
7b6e506e RH |
1136 | } |
1137 | ||
e2500fed | 1138 | static GTY(()) rtx thread_pointer_rtx; |
7b6e506e | 1139 | static rtx |
9c808aad | 1140 | gen_thread_pointer (void) |
7b6e506e | 1141 | { |
e2500fed | 1142 | if (!thread_pointer_rtx) |
389fdba0 | 1143 | thread_pointer_rtx = gen_rtx_REG (Pmode, 13); |
135ca7b2 | 1144 | return thread_pointer_rtx; |
7b6e506e RH |
1145 | } |
1146 | ||
21515593 | 1147 | static rtx |
5e6c8b64 | 1148 | ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1, |
b15b83fb | 1149 | rtx orig_op1, HOST_WIDE_INT addend) |
21515593 RH |
1150 | { |
1151 | rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns; | |
b15b83fb | 1152 | rtx orig_op0 = op0; |
5e6c8b64 RH |
1153 | HOST_WIDE_INT addend_lo, addend_hi; |
1154 | ||
21515593 RH |
1155 | switch (tls_kind) |
1156 | { | |
1157 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1158 | start_sequence (); | |
1159 | ||
1160 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1161 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1162 | |
1163 | tga_op2 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1164 | emit_insn (gen_load_dtprel (tga_op2, op1)); |
9c808aad | 1165 | |
21515593 RH |
1166 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, |
1167 | LCT_CONST, Pmode, 2, tga_op1, | |
1168 | Pmode, tga_op2, Pmode); | |
1169 | ||
1170 | insns = get_insns (); | |
1171 | end_sequence (); | |
1172 | ||
0d433a6a RH |
1173 | if (GET_MODE (op0) != Pmode) |
1174 | op0 = tga_ret; | |
21515593 | 1175 | emit_libcall_block (insns, op0, tga_ret, op1); |
0d433a6a | 1176 | break; |
21515593 RH |
1177 | |
1178 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1179 | /* ??? This isn't the completely proper way to do local-dynamic | |
1180 | If the call to __tls_get_addr is used only by a single symbol, | |
1181 | then we should (somehow) move the dtprel to the second arg | |
1182 | to avoid the extra add. */ | |
1183 | start_sequence (); | |
1184 | ||
1185 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1186 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1187 | |
1188 | tga_op2 = const0_rtx; | |
1189 | ||
1190 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, | |
1191 | LCT_CONST, Pmode, 2, tga_op1, | |
1192 | Pmode, tga_op2, Pmode); | |
1193 | ||
1194 | insns = get_insns (); | |
1195 | end_sequence (); | |
1196 | ||
1197 | tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1198 | UNSPEC_LD_BASE); | |
1199 | tmp = gen_reg_rtx (Pmode); | |
1200 | emit_libcall_block (insns, tmp, tga_ret, tga_eqv); | |
1201 | ||
0d433a6a RH |
1202 | if (!register_operand (op0, Pmode)) |
1203 | op0 = gen_reg_rtx (Pmode); | |
21515593 RH |
1204 | if (TARGET_TLS64) |
1205 | { | |
0d433a6a RH |
1206 | emit_insn (gen_load_dtprel (op0, op1)); |
1207 | emit_insn (gen_adddi3 (op0, tmp, op0)); | |
21515593 RH |
1208 | } |
1209 | else | |
5e6c8b64 | 1210 | emit_insn (gen_add_dtprel (op0, op1, tmp)); |
0d433a6a | 1211 | break; |
21515593 RH |
1212 | |
1213 | case TLS_MODEL_INITIAL_EXEC: | |
b15b83fb JJ |
1214 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; |
1215 | addend_hi = addend - addend_lo; | |
1216 | ||
0a81f074 | 1217 | op1 = plus_constant (Pmode, op1, addend_hi); |
5e6c8b64 RH |
1218 | addend = addend_lo; |
1219 | ||
21515593 | 1220 | tmp = gen_reg_rtx (Pmode); |
5e6c8b64 | 1221 | emit_insn (gen_load_tprel (tmp, op1)); |
21515593 | 1222 | |
0d433a6a RH |
1223 | if (!register_operand (op0, Pmode)) |
1224 | op0 = gen_reg_rtx (Pmode); | |
1225 | emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ())); | |
1226 | break; | |
21515593 RH |
1227 | |
1228 | case TLS_MODEL_LOCAL_EXEC: | |
0d433a6a RH |
1229 | if (!register_operand (op0, Pmode)) |
1230 | op0 = gen_reg_rtx (Pmode); | |
5e6c8b64 RH |
1231 | |
1232 | op1 = orig_op1; | |
1233 | addend = 0; | |
21515593 RH |
1234 | if (TARGET_TLS64) |
1235 | { | |
0d433a6a | 1236 | emit_insn (gen_load_tprel (op0, op1)); |
5e6c8b64 | 1237 | emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ())); |
21515593 RH |
1238 | } |
1239 | else | |
5e6c8b64 | 1240 | emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ())); |
0d433a6a | 1241 | break; |
21515593 RH |
1242 | |
1243 | default: | |
e820471b | 1244 | gcc_unreachable (); |
21515593 | 1245 | } |
0d433a6a | 1246 | |
5e6c8b64 RH |
1247 | if (addend) |
1248 | op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend), | |
1249 | orig_op0, 1, OPTAB_DIRECT); | |
0d433a6a RH |
1250 | if (orig_op0 == op0) |
1251 | return NULL_RTX; | |
1252 | if (GET_MODE (orig_op0) == Pmode) | |
1253 | return op0; | |
1254 | return gen_lowpart (GET_MODE (orig_op0), op0); | |
21515593 RH |
1255 | } |
1256 | ||
7b6e506e | 1257 | rtx |
9c808aad | 1258 | ia64_expand_move (rtx op0, rtx op1) |
7b6e506e RH |
1259 | { |
1260 | enum machine_mode mode = GET_MODE (op0); | |
1261 | ||
1262 | if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1)) | |
1263 | op1 = force_reg (mode, op1); | |
1264 | ||
21515593 | 1265 | if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode)) |
7b6e506e | 1266 | { |
5e6c8b64 | 1267 | HOST_WIDE_INT addend = 0; |
7b6e506e | 1268 | enum tls_model tls_kind; |
5e6c8b64 RH |
1269 | rtx sym = op1; |
1270 | ||
1271 | if (GET_CODE (op1) == CONST | |
1272 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
1273 | && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT) | |
1274 | { | |
1275 | addend = INTVAL (XEXP (XEXP (op1, 0), 1)); | |
1276 | sym = XEXP (XEXP (op1, 0), 0); | |
1277 | } | |
1278 | ||
1279 | tls_kind = tls_symbolic_operand_type (sym); | |
1280 | if (tls_kind) | |
b15b83fb | 1281 | return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend); |
5e6c8b64 RH |
1282 | |
1283 | if (any_offset_symbol_operand (sym, mode)) | |
1284 | addend = 0; | |
1285 | else if (aligned_offset_symbol_operand (sym, mode)) | |
1286 | { | |
1287 | HOST_WIDE_INT addend_lo, addend_hi; | |
1288 | ||
1289 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; | |
1290 | addend_hi = addend - addend_lo; | |
1291 | ||
1292 | if (addend_lo != 0) | |
1293 | { | |
0a81f074 | 1294 | op1 = plus_constant (mode, sym, addend_hi); |
5e6c8b64 RH |
1295 | addend = addend_lo; |
1296 | } | |
21e43850 L |
1297 | else |
1298 | addend = 0; | |
5e6c8b64 RH |
1299 | } |
1300 | else | |
1301 | op1 = sym; | |
1302 | ||
1303 | if (reload_completed) | |
1304 | { | |
1305 | /* We really should have taken care of this offset earlier. */ | |
1306 | gcc_assert (addend == 0); | |
1307 | if (ia64_expand_load_address (op0, op1)) | |
1308 | return NULL_RTX; | |
1309 | } | |
21515593 | 1310 | |
5e6c8b64 | 1311 | if (addend) |
7b6e506e | 1312 | { |
b3a13419 | 1313 | rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode); |
5e6c8b64 RH |
1314 | |
1315 | emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1)); | |
1316 | ||
1317 | op1 = expand_simple_binop (mode, PLUS, subtarget, | |
1318 | GEN_INT (addend), op0, 1, OPTAB_DIRECT); | |
1319 | if (op0 == op1) | |
1320 | return NULL_RTX; | |
7b6e506e RH |
1321 | } |
1322 | } | |
1323 | ||
1324 | return op1; | |
1325 | } | |
1326 | ||
21515593 RH |
1327 | /* Split a move from OP1 to OP0 conditional on COND. */ |
1328 | ||
1329 | void | |
9c808aad | 1330 | ia64_emit_cond_move (rtx op0, rtx op1, rtx cond) |
21515593 RH |
1331 | { |
1332 | rtx insn, first = get_last_insn (); | |
1333 | ||
1334 | emit_move_insn (op0, op1); | |
1335 | ||
1336 | for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn)) | |
1337 | if (INSN_P (insn)) | |
1338 | PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), | |
1339 | PATTERN (insn)); | |
1340 | } | |
1341 | ||
f57fc998 | 1342 | /* Split a post-reload TImode or TFmode reference into two DImode |
2ffe0e02 ZW |
1343 | components. This is made extra difficult by the fact that we do |
1344 | not get any scratch registers to work with, because reload cannot | |
1345 | be prevented from giving us a scratch that overlaps the register | |
1346 | pair involved. So instead, when addressing memory, we tweak the | |
1347 | pointer register up and back down with POST_INCs. Or up and not | |
1348 | back down when we can get away with it. | |
1349 | ||
1350 | REVERSED is true when the loads must be done in reversed order | |
1351 | (high word first) for correctness. DEAD is true when the pointer | |
1352 | dies with the second insn we generate and therefore the second | |
1353 | address must not carry a postmodify. | |
1354 | ||
1355 | May return an insn which is to be emitted after the moves. */ | |
3f622353 | 1356 | |
f57fc998 | 1357 | static rtx |
2ffe0e02 | 1358 | ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) |
3f622353 | 1359 | { |
2ffe0e02 ZW |
1360 | rtx fixup = 0; |
1361 | ||
3f622353 RH |
1362 | switch (GET_CODE (in)) |
1363 | { | |
1364 | case REG: | |
2ffe0e02 ZW |
1365 | out[reversed] = gen_rtx_REG (DImode, REGNO (in)); |
1366 | out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1); | |
1367 | break; | |
3f622353 RH |
1368 | |
1369 | case CONST_INT: | |
1370 | case CONST_DOUBLE: | |
2ffe0e02 | 1371 | /* Cannot occur reversed. */ |
e820471b | 1372 | gcc_assert (!reversed); |
2ffe0e02 | 1373 | |
f57fc998 ZW |
1374 | if (GET_MODE (in) != TFmode) |
1375 | split_double (in, &out[0], &out[1]); | |
1376 | else | |
1377 | /* split_double does not understand how to split a TFmode | |
1378 | quantity into a pair of DImode constants. */ | |
1379 | { | |
1380 | REAL_VALUE_TYPE r; | |
1381 | unsigned HOST_WIDE_INT p[2]; | |
1382 | long l[4]; /* TFmode is 128 bits */ | |
1383 | ||
1384 | REAL_VALUE_FROM_CONST_DOUBLE (r, in); | |
1385 | real_to_target (l, &r, TFmode); | |
1386 | ||
1387 | if (FLOAT_WORDS_BIG_ENDIAN) | |
1388 | { | |
1389 | p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1]; | |
1390 | p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3]; | |
1391 | } | |
1392 | else | |
1393 | { | |
9eb578c8 L |
1394 | p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0]; |
1395 | p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2]; | |
f57fc998 ZW |
1396 | } |
1397 | out[0] = GEN_INT (p[0]); | |
1398 | out[1] = GEN_INT (p[1]); | |
1399 | } | |
2ffe0e02 ZW |
1400 | break; |
1401 | ||
1402 | case MEM: | |
1403 | { | |
1404 | rtx base = XEXP (in, 0); | |
1405 | rtx offset; | |
1406 | ||
1407 | switch (GET_CODE (base)) | |
1408 | { | |
1409 | case REG: | |
1410 | if (!reversed) | |
1411 | { | |
1412 | out[0] = adjust_automodify_address | |
1413 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1414 | out[1] = adjust_automodify_address | |
1415 | (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8); | |
1416 | } | |
1417 | else | |
1418 | { | |
1419 | /* Reversal requires a pre-increment, which can only | |
1420 | be done as a separate insn. */ | |
1421 | emit_insn (gen_adddi3 (base, base, GEN_INT (8))); | |
1422 | out[0] = adjust_automodify_address | |
1423 | (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8); | |
1424 | out[1] = adjust_address (in, DImode, 0); | |
1425 | } | |
1426 | break; | |
1427 | ||
1428 | case POST_INC: | |
e820471b NS |
1429 | gcc_assert (!reversed && !dead); |
1430 | ||
2ffe0e02 ZW |
1431 | /* Just do the increment in two steps. */ |
1432 | out[0] = adjust_automodify_address (in, DImode, 0, 0); | |
1433 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1434 | break; | |
1435 | ||
1436 | case POST_DEC: | |
e820471b NS |
1437 | gcc_assert (!reversed && !dead); |
1438 | ||
2ffe0e02 ZW |
1439 | /* Add 8, subtract 24. */ |
1440 | base = XEXP (base, 0); | |
1441 | out[0] = adjust_automodify_address | |
1442 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1443 | out[1] = adjust_automodify_address | |
1444 | (in, DImode, | |
0a81f074 RS |
1445 | gen_rtx_POST_MODIFY (Pmode, base, |
1446 | plus_constant (Pmode, base, -24)), | |
2ffe0e02 ZW |
1447 | 8); |
1448 | break; | |
1449 | ||
1450 | case POST_MODIFY: | |
e820471b NS |
1451 | gcc_assert (!reversed && !dead); |
1452 | ||
2ffe0e02 ZW |
1453 | /* Extract and adjust the modification. This case is |
1454 | trickier than the others, because we might have an | |
1455 | index register, or we might have a combined offset that | |
1456 | doesn't fit a signed 9-bit displacement field. We can | |
1457 | assume the incoming expression is already legitimate. */ | |
1458 | offset = XEXP (base, 1); | |
1459 | base = XEXP (base, 0); | |
1460 | ||
1461 | out[0] = adjust_automodify_address | |
1462 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1463 | ||
1464 | if (GET_CODE (XEXP (offset, 1)) == REG) | |
1465 | { | |
1466 | /* Can't adjust the postmodify to match. Emit the | |
1467 | original, then a separate addition insn. */ | |
1468 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1469 | fixup = gen_adddi3 (base, base, GEN_INT (-8)); | |
1470 | } | |
2ffe0e02 ZW |
1471 | else |
1472 | { | |
e820471b NS |
1473 | gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT); |
1474 | if (INTVAL (XEXP (offset, 1)) < -256 + 8) | |
1475 | { | |
1476 | /* Again the postmodify cannot be made to match, | |
1477 | but in this case it's more efficient to get rid | |
1478 | of the postmodify entirely and fix up with an | |
1479 | add insn. */ | |
1480 | out[1] = adjust_automodify_address (in, DImode, base, 8); | |
1481 | fixup = gen_adddi3 | |
1482 | (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8)); | |
1483 | } | |
1484 | else | |
1485 | { | |
1486 | /* Combined offset still fits in the displacement field. | |
1487 | (We cannot overflow it at the high end.) */ | |
1488 | out[1] = adjust_automodify_address | |
1489 | (in, DImode, gen_rtx_POST_MODIFY | |
1490 | (Pmode, base, gen_rtx_PLUS | |
1491 | (Pmode, base, | |
1492 | GEN_INT (INTVAL (XEXP (offset, 1)) - 8))), | |
1493 | 8); | |
1494 | } | |
2ffe0e02 ZW |
1495 | } |
1496 | break; | |
1497 | ||
1498 | default: | |
e820471b | 1499 | gcc_unreachable (); |
2ffe0e02 ZW |
1500 | } |
1501 | break; | |
1502 | } | |
3f622353 RH |
1503 | |
1504 | default: | |
e820471b | 1505 | gcc_unreachable (); |
3f622353 | 1506 | } |
2ffe0e02 ZW |
1507 | |
1508 | return fixup; | |
3f622353 RH |
1509 | } |
1510 | ||
f57fc998 ZW |
1511 | /* Split a TImode or TFmode move instruction after reload. |
1512 | This is used by *movtf_internal and *movti_internal. */ | |
1513 | void | |
1514 | ia64_split_tmode_move (rtx operands[]) | |
1515 | { | |
2ffe0e02 ZW |
1516 | rtx in[2], out[2], insn; |
1517 | rtx fixup[2]; | |
1518 | bool dead = false; | |
1519 | bool reversed = false; | |
1520 | ||
1521 | /* It is possible for reload to decide to overwrite a pointer with | |
1522 | the value it points to. In that case we have to do the loads in | |
1523 | the appropriate order so that the pointer is not destroyed too | |
1524 | early. Also we must not generate a postmodify for that second | |
e820471b | 1525 | load, or rws_access_regno will die. */ |
2ffe0e02 ZW |
1526 | if (GET_CODE (operands[1]) == MEM |
1527 | && reg_overlap_mentioned_p (operands[0], operands[1])) | |
f57fc998 | 1528 | { |
2ffe0e02 ZW |
1529 | rtx base = XEXP (operands[1], 0); |
1530 | while (GET_CODE (base) != REG) | |
1531 | base = XEXP (base, 0); | |
f57fc998 | 1532 | |
2ffe0e02 ZW |
1533 | if (REGNO (base) == REGNO (operands[0])) |
1534 | reversed = true; | |
1535 | dead = true; | |
1536 | } | |
1537 | /* Another reason to do the moves in reversed order is if the first | |
1538 | element of the target register pair is also the second element of | |
1539 | the source register pair. */ | |
1540 | if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG | |
1541 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
1542 | reversed = true; | |
1543 | ||
1544 | fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead); | |
1545 | fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead); | |
1546 | ||
1547 | #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \ | |
1548 | if (GET_CODE (EXP) == MEM \ | |
1549 | && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \ | |
1550 | || GET_CODE (XEXP (EXP, 0)) == POST_INC \ | |
1551 | || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \ | |
bbbbb16a | 1552 | add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0)) |
2ffe0e02 ZW |
1553 | |
1554 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0])); | |
1555 | MAYBE_ADD_REG_INC_NOTE (insn, in[0]); | |
1556 | MAYBE_ADD_REG_INC_NOTE (insn, out[0]); | |
1557 | ||
1558 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1])); | |
1559 | MAYBE_ADD_REG_INC_NOTE (insn, in[1]); | |
1560 | MAYBE_ADD_REG_INC_NOTE (insn, out[1]); | |
1561 | ||
1562 | if (fixup[0]) | |
1563 | emit_insn (fixup[0]); | |
1564 | if (fixup[1]) | |
1565 | emit_insn (fixup[1]); | |
1566 | ||
1567 | #undef MAYBE_ADD_REG_INC_NOTE | |
f57fc998 ZW |
1568 | } |
1569 | ||
02befdf4 | 1570 | /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go |
3f622353 RH |
1571 | through memory plus an extra GR scratch register. Except that you can |
1572 | either get the first from SECONDARY_MEMORY_NEEDED or the second from | |
1573 | SECONDARY_RELOAD_CLASS, but not both. | |
1574 | ||
1575 | We got into problems in the first place by allowing a construct like | |
02befdf4 | 1576 | (subreg:XF (reg:TI)), which we got from a union containing a long double. |
f5143c46 | 1577 | This solution attempts to prevent this situation from occurring. When |
3f622353 RH |
1578 | we see something like the above, we spill the inner register to memory. */ |
1579 | ||
4de67c26 JM |
1580 | static rtx |
1581 | spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode) | |
3f622353 RH |
1582 | { |
1583 | if (GET_CODE (in) == SUBREG | |
1584 | && GET_MODE (SUBREG_REG (in)) == TImode | |
1585 | && GET_CODE (SUBREG_REG (in)) == REG) | |
1586 | { | |
9474e8ab | 1587 | rtx memt = assign_stack_temp (TImode, 16); |
68d22aa5 | 1588 | emit_move_insn (memt, SUBREG_REG (in)); |
4de67c26 | 1589 | return adjust_address (memt, mode, 0); |
3f622353 RH |
1590 | } |
1591 | else if (force && GET_CODE (in) == REG) | |
1592 | { | |
9474e8ab | 1593 | rtx memx = assign_stack_temp (mode, 16); |
68d22aa5 RH |
1594 | emit_move_insn (memx, in); |
1595 | return memx; | |
3f622353 | 1596 | } |
3f622353 RH |
1597 | else |
1598 | return in; | |
1599 | } | |
f2f90c63 | 1600 | |
4de67c26 JM |
1601 | /* Expand the movxf or movrf pattern (MODE says which) with the given |
1602 | OPERANDS, returning true if the pattern should then invoke | |
1603 | DONE. */ | |
1604 | ||
1605 | bool | |
1606 | ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[]) | |
1607 | { | |
1608 | rtx op0 = operands[0]; | |
1609 | ||
1610 | if (GET_CODE (op0) == SUBREG) | |
1611 | op0 = SUBREG_REG (op0); | |
1612 | ||
1613 | /* We must support XFmode loads into general registers for stdarg/vararg, | |
1614 | unprototyped calls, and a rare case where a long double is passed as | |
1615 | an argument after a float HFA fills the FP registers. We split them into | |
1616 | DImode loads for convenience. We also need to support XFmode stores | |
1617 | for the last case. This case does not happen for stdarg/vararg routines, | |
1618 | because we do a block store to memory of unnamed arguments. */ | |
1619 | ||
1620 | if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) | |
1621 | { | |
1622 | rtx out[2]; | |
1623 | ||
1624 | /* We're hoping to transform everything that deals with XFmode | |
1625 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1626 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1627 | |
1628 | /* Struct to register can just use TImode instead. */ | |
1629 | if ((GET_CODE (operands[1]) == SUBREG | |
1630 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
1631 | || (GET_CODE (operands[1]) == REG | |
1632 | && GR_REGNO_P (REGNO (operands[1])))) | |
1633 | { | |
1634 | rtx op1 = operands[1]; | |
1635 | ||
1636 | if (GET_CODE (op1) == SUBREG) | |
1637 | op1 = SUBREG_REG (op1); | |
1638 | else | |
1639 | op1 = gen_rtx_REG (TImode, REGNO (op1)); | |
1640 | ||
1641 | emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); | |
1642 | return true; | |
1643 | } | |
1644 | ||
1645 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1646 | { | |
ae4d3291 | 1647 | /* Don't word-swap when reading in the constant. */ |
4de67c26 | 1648 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), |
ae4d3291 JW |
1649 | operand_subword (operands[1], WORDS_BIG_ENDIAN, |
1650 | 0, mode)); | |
4de67c26 | 1651 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), |
ae4d3291 JW |
1652 | operand_subword (operands[1], !WORDS_BIG_ENDIAN, |
1653 | 0, mode)); | |
4de67c26 JM |
1654 | return true; |
1655 | } | |
1656 | ||
1657 | /* If the quantity is in a register not known to be GR, spill it. */ | |
1658 | if (register_operand (operands[1], mode)) | |
1659 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode); | |
1660 | ||
1661 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
1662 | ||
ae4d3291 JW |
1663 | /* Don't word-swap when reading in the value. */ |
1664 | out[0] = gen_rtx_REG (DImode, REGNO (op0)); | |
1665 | out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1); | |
4de67c26 JM |
1666 | |
1667 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); | |
1668 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
1669 | return true; | |
1670 | } | |
1671 | ||
1672 | if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1]))) | |
1673 | { | |
1674 | /* We're hoping to transform everything that deals with XFmode | |
1675 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1676 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1677 | |
1678 | /* Op0 can't be a GR_REG here, as that case is handled above. | |
1679 | If op0 is a register, then we spill op1, so that we now have a | |
1680 | MEM operand. This requires creating an XFmode subreg of a TImode reg | |
1681 | to force the spill. */ | |
1682 | if (register_operand (operands[0], mode)) | |
1683 | { | |
1684 | rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1])); | |
1685 | op1 = gen_rtx_SUBREG (mode, op1, 0); | |
1686 | operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode); | |
1687 | } | |
1688 | ||
1689 | else | |
1690 | { | |
1691 | rtx in[2]; | |
1692 | ||
ae4d3291 JW |
1693 | gcc_assert (GET_CODE (operands[0]) == MEM); |
1694 | ||
1695 | /* Don't word-swap when writing out the value. */ | |
1696 | in[0] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1697 | in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); | |
4de67c26 JM |
1698 | |
1699 | emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]); | |
1700 | emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]); | |
1701 | return true; | |
1702 | } | |
1703 | } | |
1704 | ||
1705 | if (!reload_in_progress && !reload_completed) | |
1706 | { | |
1707 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode); | |
1708 | ||
1709 | if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG) | |
1710 | { | |
1711 | rtx memt, memx, in = operands[1]; | |
1712 | if (CONSTANT_P (in)) | |
1713 | in = validize_mem (force_const_mem (mode, in)); | |
1714 | if (GET_CODE (in) == MEM) | |
1715 | memt = adjust_address (in, TImode, 0); | |
1716 | else | |
1717 | { | |
9474e8ab | 1718 | memt = assign_stack_temp (TImode, 16); |
4de67c26 JM |
1719 | memx = adjust_address (memt, mode, 0); |
1720 | emit_move_insn (memx, in); | |
1721 | } | |
1722 | emit_move_insn (op0, memt); | |
1723 | return true; | |
1724 | } | |
1725 | ||
1726 | if (!ia64_move_ok (operands[0], operands[1])) | |
1727 | operands[1] = force_reg (mode, operands[1]); | |
1728 | } | |
1729 | ||
1730 | return false; | |
1731 | } | |
1732 | ||
f90b7a5a PB |
1733 | /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1 |
1734 | with the expression that holds the compare result (in VOIDmode). */ | |
f2f90c63 | 1735 | |
24ea7948 ZW |
1736 | static GTY(()) rtx cmptf_libfunc; |
1737 | ||
f90b7a5a PB |
1738 | void |
1739 | ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1) | |
f2f90c63 | 1740 | { |
f90b7a5a | 1741 | enum rtx_code code = GET_CODE (*expr); |
f2f90c63 RH |
1742 | rtx cmp; |
1743 | ||
1744 | /* If we have a BImode input, then we already have a compare result, and | |
1745 | do not need to emit another comparison. */ | |
f90b7a5a | 1746 | if (GET_MODE (*op0) == BImode) |
f2f90c63 | 1747 | { |
f90b7a5a PB |
1748 | gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx); |
1749 | cmp = *op0; | |
f2f90c63 | 1750 | } |
24ea7948 ZW |
1751 | /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a |
1752 | magic number as its third argument, that indicates what to do. | |
1753 | The return value is an integer to be compared against zero. */ | |
f90b7a5a | 1754 | else if (TARGET_HPUX && GET_MODE (*op0) == TFmode) |
24ea7948 ZW |
1755 | { |
1756 | enum qfcmp_magic { | |
1757 | QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */ | |
1758 | QCMP_UNORD = 2, | |
1759 | QCMP_EQ = 4, | |
1760 | QCMP_LT = 8, | |
1761 | QCMP_GT = 16 | |
32e8bb8e ILT |
1762 | }; |
1763 | int magic; | |
24ea7948 ZW |
1764 | enum rtx_code ncode; |
1765 | rtx ret, insns; | |
e820471b | 1766 | |
f90b7a5a | 1767 | gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode); |
24ea7948 ZW |
1768 | switch (code) |
1769 | { | |
1770 | /* 1 = equal, 0 = not equal. Equality operators do | |
1771 | not raise FP_INVALID when given an SNaN operand. */ | |
1772 | case EQ: magic = QCMP_EQ; ncode = NE; break; | |
1773 | case NE: magic = QCMP_EQ; ncode = EQ; break; | |
1774 | /* isunordered() from C99. */ | |
1775 | case UNORDERED: magic = QCMP_UNORD; ncode = NE; break; | |
b1346fa3 | 1776 | case ORDERED: magic = QCMP_UNORD; ncode = EQ; break; |
24ea7948 ZW |
1777 | /* Relational operators raise FP_INVALID when given |
1778 | an SNaN operand. */ | |
1779 | case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break; | |
1780 | case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
1781 | case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break; | |
1782 | case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
1783 | /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT. | |
1784 | Expanders for buneq etc. weuld have to be added to ia64.md | |
1785 | for this to be useful. */ | |
e820471b | 1786 | default: gcc_unreachable (); |
24ea7948 ZW |
1787 | } |
1788 | ||
1789 | start_sequence (); | |
1790 | ||
1791 | ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3, | |
f90b7a5a | 1792 | *op0, TFmode, *op1, TFmode, |
24ea7948 ZW |
1793 | GEN_INT (magic), DImode); |
1794 | cmp = gen_reg_rtx (BImode); | |
1795 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
1796 | gen_rtx_fmt_ee (ncode, BImode, | |
1797 | ret, const0_rtx))); | |
1798 | ||
1799 | insns = get_insns (); | |
1800 | end_sequence (); | |
1801 | ||
1802 | emit_libcall_block (insns, cmp, cmp, | |
f90b7a5a | 1803 | gen_rtx_fmt_ee (code, BImode, *op0, *op1)); |
24ea7948 ZW |
1804 | code = NE; |
1805 | } | |
f2f90c63 RH |
1806 | else |
1807 | { | |
1808 | cmp = gen_reg_rtx (BImode); | |
1809 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
f90b7a5a | 1810 | gen_rtx_fmt_ee (code, BImode, *op0, *op1))); |
f2f90c63 RH |
1811 | code = NE; |
1812 | } | |
1813 | ||
f90b7a5a PB |
1814 | *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx); |
1815 | *op0 = cmp; | |
1816 | *op1 = const0_rtx; | |
f2f90c63 | 1817 | } |
2ed4af6f | 1818 | |
e934ca47 RH |
1819 | /* Generate an integral vector comparison. Return true if the condition has |
1820 | been reversed, and so the sense of the comparison should be inverted. */ | |
f61134e8 RH |
1821 | |
1822 | static bool | |
1823 | ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode, | |
1824 | rtx dest, rtx op0, rtx op1) | |
1825 | { | |
1826 | bool negate = false; | |
1827 | rtx x; | |
1828 | ||
e934ca47 | 1829 | /* Canonicalize the comparison to EQ, GT, GTU. */ |
f61134e8 RH |
1830 | switch (code) |
1831 | { | |
1832 | case EQ: | |
1833 | case GT: | |
e934ca47 | 1834 | case GTU: |
f61134e8 RH |
1835 | break; |
1836 | ||
1837 | case NE: | |
f61134e8 | 1838 | case LE: |
e934ca47 RH |
1839 | case LEU: |
1840 | code = reverse_condition (code); | |
f61134e8 RH |
1841 | negate = true; |
1842 | break; | |
1843 | ||
1844 | case GE: | |
e934ca47 RH |
1845 | case GEU: |
1846 | code = reverse_condition (code); | |
f61134e8 RH |
1847 | negate = true; |
1848 | /* FALLTHRU */ | |
1849 | ||
1850 | case LT: | |
f61134e8 | 1851 | case LTU: |
e934ca47 RH |
1852 | code = swap_condition (code); |
1853 | x = op0, op0 = op1, op1 = x; | |
1854 | break; | |
f61134e8 | 1855 | |
e934ca47 RH |
1856 | default: |
1857 | gcc_unreachable (); | |
1858 | } | |
f61134e8 | 1859 | |
e934ca47 | 1860 | /* Unsigned parallel compare is not supported by the hardware. Play some |
6283ba26 | 1861 | tricks to turn this into a signed comparison against 0. */ |
e934ca47 RH |
1862 | if (code == GTU) |
1863 | { | |
1864 | switch (mode) | |
1865 | { | |
1866 | case V2SImode: | |
f61134e8 | 1867 | { |
e934ca47 RH |
1868 | rtx t1, t2, mask; |
1869 | ||
9540f5ef SE |
1870 | /* Subtract (-(INT MAX) - 1) from both operands to make |
1871 | them signed. */ | |
1872 | mask = GEN_INT (0x80000000); | |
e934ca47 | 1873 | mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask)); |
9540f5ef SE |
1874 | mask = force_reg (mode, mask); |
1875 | t1 = gen_reg_rtx (mode); | |
1876 | emit_insn (gen_subv2si3 (t1, op0, mask)); | |
1877 | t2 = gen_reg_rtx (mode); | |
1878 | emit_insn (gen_subv2si3 (t2, op1, mask)); | |
1879 | op0 = t1; | |
1880 | op1 = t2; | |
6283ba26 | 1881 | code = GT; |
f61134e8 | 1882 | } |
e934ca47 RH |
1883 | break; |
1884 | ||
1885 | case V8QImode: | |
1886 | case V4HImode: | |
1887 | /* Perform a parallel unsigned saturating subtraction. */ | |
1888 | x = gen_reg_rtx (mode); | |
1889 | emit_insn (gen_rtx_SET (VOIDmode, x, | |
1890 | gen_rtx_US_MINUS (mode, op0, op1))); | |
6283ba26 RH |
1891 | |
1892 | code = EQ; | |
1893 | op0 = x; | |
1894 | op1 = CONST0_RTX (mode); | |
1895 | negate = !negate; | |
e934ca47 RH |
1896 | break; |
1897 | ||
1898 | default: | |
1899 | gcc_unreachable (); | |
1900 | } | |
f61134e8 RH |
1901 | } |
1902 | ||
1903 | x = gen_rtx_fmt_ee (code, mode, op0, op1); | |
1904 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
1905 | ||
1906 | return negate; | |
1907 | } | |
1908 | ||
f61134e8 RH |
1909 | /* Emit an integral vector conditional move. */ |
1910 | ||
1911 | void | |
1912 | ia64_expand_vecint_cmov (rtx operands[]) | |
1913 | { | |
1914 | enum machine_mode mode = GET_MODE (operands[0]); | |
1915 | enum rtx_code code = GET_CODE (operands[3]); | |
1916 | bool negate; | |
1917 | rtx cmp, x, ot, of; | |
1918 | ||
f61134e8 RH |
1919 | cmp = gen_reg_rtx (mode); |
1920 | negate = ia64_expand_vecint_compare (code, mode, cmp, | |
1921 | operands[4], operands[5]); | |
1922 | ||
1923 | ot = operands[1+negate]; | |
1924 | of = operands[2-negate]; | |
1925 | ||
1926 | if (ot == CONST0_RTX (mode)) | |
1927 | { | |
1928 | if (of == CONST0_RTX (mode)) | |
1929 | { | |
1930 | emit_move_insn (operands[0], ot); | |
1931 | return; | |
1932 | } | |
1933 | ||
1934 | x = gen_rtx_NOT (mode, cmp); | |
1935 | x = gen_rtx_AND (mode, x, of); | |
1936 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1937 | } | |
1938 | else if (of == CONST0_RTX (mode)) | |
1939 | { | |
1940 | x = gen_rtx_AND (mode, cmp, ot); | |
1941 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1942 | } | |
1943 | else | |
1944 | { | |
1945 | rtx t, f; | |
1946 | ||
1947 | t = gen_reg_rtx (mode); | |
1948 | x = gen_rtx_AND (mode, cmp, operands[1+negate]); | |
1949 | emit_insn (gen_rtx_SET (VOIDmode, t, x)); | |
1950 | ||
1951 | f = gen_reg_rtx (mode); | |
1952 | x = gen_rtx_NOT (mode, cmp); | |
1953 | x = gen_rtx_AND (mode, x, operands[2-negate]); | |
1954 | emit_insn (gen_rtx_SET (VOIDmode, f, x)); | |
1955 | ||
1956 | x = gen_rtx_IOR (mode, t, f); | |
1957 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1958 | } | |
1959 | } | |
1960 | ||
1961 | /* Emit an integral vector min or max operation. Return true if all done. */ | |
1962 | ||
1963 | bool | |
1964 | ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode, | |
1965 | rtx operands[]) | |
1966 | { | |
cabddb23 | 1967 | rtx xops[6]; |
f61134e8 RH |
1968 | |
1969 | /* These four combinations are supported directly. */ | |
1970 | if (mode == V8QImode && (code == UMIN || code == UMAX)) | |
1971 | return false; | |
1972 | if (mode == V4HImode && (code == SMIN || code == SMAX)) | |
1973 | return false; | |
1974 | ||
93b4080b RH |
1975 | /* This combination can be implemented with only saturating subtraction. */ |
1976 | if (mode == V4HImode && code == UMAX) | |
1977 | { | |
1978 | rtx x, tmp = gen_reg_rtx (mode); | |
1979 | ||
1980 | x = gen_rtx_US_MINUS (mode, operands[1], operands[2]); | |
1981 | emit_insn (gen_rtx_SET (VOIDmode, tmp, x)); | |
1982 | ||
1983 | emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2])); | |
1984 | return true; | |
1985 | } | |
1986 | ||
f61134e8 RH |
1987 | /* Everything else implemented via vector comparisons. */ |
1988 | xops[0] = operands[0]; | |
1989 | xops[4] = xops[1] = operands[1]; | |
1990 | xops[5] = xops[2] = operands[2]; | |
1991 | ||
1992 | switch (code) | |
1993 | { | |
1994 | case UMIN: | |
1995 | code = LTU; | |
1996 | break; | |
1997 | case UMAX: | |
1998 | code = GTU; | |
1999 | break; | |
2000 | case SMIN: | |
2001 | code = LT; | |
2002 | break; | |
2003 | case SMAX: | |
2004 | code = GT; | |
2005 | break; | |
2006 | default: | |
e820471b | 2007 | gcc_unreachable (); |
f61134e8 RH |
2008 | } |
2009 | xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]); | |
2010 | ||
2011 | ia64_expand_vecint_cmov (xops); | |
2012 | return true; | |
2013 | } | |
2014 | ||
55eaaa5b RH |
2015 | /* The vectors LO and HI each contain N halves of a double-wide vector. |
2016 | Reassemble either the first N/2 or the second N/2 elements. */ | |
604e3ff3 RH |
2017 | |
2018 | void | |
55eaaa5b | 2019 | ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp) |
604e3ff3 | 2020 | { |
e6431744 RH |
2021 | enum machine_mode vmode = GET_MODE (lo); |
2022 | unsigned int i, high, nelt = GET_MODE_NUNITS (vmode); | |
2023 | struct expand_vec_perm_d d; | |
2024 | bool ok; | |
604e3ff3 | 2025 | |
e6431744 RH |
2026 | d.target = gen_lowpart (vmode, out); |
2027 | d.op0 = (TARGET_BIG_ENDIAN ? hi : lo); | |
2028 | d.op1 = (TARGET_BIG_ENDIAN ? lo : hi); | |
2029 | d.vmode = vmode; | |
2030 | d.nelt = nelt; | |
2031 | d.one_operand_p = false; | |
2032 | d.testing_p = false; | |
2033 | ||
2034 | high = (highp ? nelt / 2 : 0); | |
2035 | for (i = 0; i < nelt / 2; ++i) | |
604e3ff3 | 2036 | { |
e6431744 RH |
2037 | d.perm[i * 2] = i + high; |
2038 | d.perm[i * 2 + 1] = i + high + nelt; | |
604e3ff3 RH |
2039 | } |
2040 | ||
e6431744 RH |
2041 | ok = ia64_expand_vec_perm_const_1 (&d); |
2042 | gcc_assert (ok); | |
604e3ff3 RH |
2043 | } |
2044 | ||
55eaaa5b | 2045 | /* Return a vector of the sign-extension of VEC. */ |
e898620c | 2046 | |
55eaaa5b RH |
2047 | static rtx |
2048 | ia64_unpack_sign (rtx vec, bool unsignedp) | |
e898620c | 2049 | { |
55eaaa5b RH |
2050 | enum machine_mode mode = GET_MODE (vec); |
2051 | rtx zero = CONST0_RTX (mode); | |
e898620c | 2052 | |
e898620c | 2053 | if (unsignedp) |
55eaaa5b | 2054 | return zero; |
e898620c RH |
2055 | else |
2056 | { | |
55eaaa5b | 2057 | rtx sign = gen_reg_rtx (mode); |
e898620c RH |
2058 | bool neg; |
2059 | ||
55eaaa5b | 2060 | neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero); |
e898620c | 2061 | gcc_assert (!neg); |
55eaaa5b RH |
2062 | |
2063 | return sign; | |
e898620c | 2064 | } |
55eaaa5b | 2065 | } |
e898620c | 2066 | |
55eaaa5b | 2067 | /* Emit an integral vector unpack operation. */ |
e898620c | 2068 | |
55eaaa5b RH |
2069 | void |
2070 | ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp) | |
2071 | { | |
2072 | rtx sign = ia64_unpack_sign (operands[1], unsignedp); | |
2073 | ia64_unpack_assemble (operands[0], operands[1], sign, highp); | |
e898620c RH |
2074 | } |
2075 | ||
55eaaa5b RH |
2076 | /* Emit an integral vector widening sum operations. */ |
2077 | ||
604e3ff3 | 2078 | void |
55eaaa5b | 2079 | ia64_expand_widen_sum (rtx operands[3], bool unsignedp) |
604e3ff3 | 2080 | { |
55eaaa5b RH |
2081 | enum machine_mode wmode; |
2082 | rtx l, h, t, sign; | |
604e3ff3 | 2083 | |
55eaaa5b RH |
2084 | sign = ia64_unpack_sign (operands[1], unsignedp); |
2085 | ||
2086 | wmode = GET_MODE (operands[0]); | |
2087 | l = gen_reg_rtx (wmode); | |
2088 | h = gen_reg_rtx (wmode); | |
604e3ff3 | 2089 | |
55eaaa5b RH |
2090 | ia64_unpack_assemble (l, operands[1], sign, false); |
2091 | ia64_unpack_assemble (h, operands[1], sign, true); | |
604e3ff3 | 2092 | |
55eaaa5b RH |
2093 | t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT); |
2094 | t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT); | |
2095 | if (t != operands[0]) | |
2096 | emit_move_insn (operands[0], t); | |
604e3ff3 RH |
2097 | } |
2098 | ||
e898620c RH |
2099 | /* Emit a signed or unsigned V8QI dot product operation. */ |
2100 | ||
2101 | void | |
2102 | ia64_expand_dot_prod_v8qi (rtx operands[4], bool unsignedp) | |
2103 | { | |
55eaaa5b RH |
2104 | rtx op1, op2, sn1, sn2, l1, l2, h1, h2; |
2105 | rtx p1, p2, p3, p4, s1, s2, s3; | |
e898620c | 2106 | |
55eaaa5b RH |
2107 | op1 = operands[1]; |
2108 | op2 = operands[2]; | |
2109 | sn1 = ia64_unpack_sign (op1, unsignedp); | |
2110 | sn2 = ia64_unpack_sign (op2, unsignedp); | |
e898620c RH |
2111 | |
2112 | l1 = gen_reg_rtx (V4HImode); | |
2113 | l2 = gen_reg_rtx (V4HImode); | |
2114 | h1 = gen_reg_rtx (V4HImode); | |
2115 | h2 = gen_reg_rtx (V4HImode); | |
55eaaa5b RH |
2116 | ia64_unpack_assemble (l1, op1, sn1, false); |
2117 | ia64_unpack_assemble (l2, op2, sn2, false); | |
2118 | ia64_unpack_assemble (h1, op1, sn1, true); | |
2119 | ia64_unpack_assemble (h2, op2, sn2, true); | |
e898620c RH |
2120 | |
2121 | p1 = gen_reg_rtx (V2SImode); | |
2122 | p2 = gen_reg_rtx (V2SImode); | |
2123 | p3 = gen_reg_rtx (V2SImode); | |
2124 | p4 = gen_reg_rtx (V2SImode); | |
55eaaa5b RH |
2125 | emit_insn (gen_pmpy2_even (p1, l1, l2)); |
2126 | emit_insn (gen_pmpy2_even (p2, h1, h2)); | |
2127 | emit_insn (gen_pmpy2_odd (p3, l1, l2)); | |
2128 | emit_insn (gen_pmpy2_odd (p4, h1, h2)); | |
e898620c RH |
2129 | |
2130 | s1 = gen_reg_rtx (V2SImode); | |
2131 | s2 = gen_reg_rtx (V2SImode); | |
2132 | s3 = gen_reg_rtx (V2SImode); | |
2133 | emit_insn (gen_addv2si3 (s1, p1, p2)); | |
2134 | emit_insn (gen_addv2si3 (s2, p3, p4)); | |
2135 | emit_insn (gen_addv2si3 (s3, s1, operands[3])); | |
2136 | emit_insn (gen_addv2si3 (operands[0], s2, s3)); | |
2137 | } | |
2138 | ||
2ed4af6f RH |
2139 | /* Emit the appropriate sequence for a call. */ |
2140 | ||
2141 | void | |
9c808aad AJ |
2142 | ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED, |
2143 | int sibcall_p) | |
2ed4af6f | 2144 | { |
599aedd9 | 2145 | rtx insn, b0; |
2ed4af6f RH |
2146 | |
2147 | addr = XEXP (addr, 0); | |
c8083186 | 2148 | addr = convert_memory_address (DImode, addr); |
2ed4af6f | 2149 | b0 = gen_rtx_REG (DImode, R_BR (0)); |
2ed4af6f | 2150 | |
599aedd9 | 2151 | /* ??? Should do this for functions known to bind local too. */ |
2ed4af6f RH |
2152 | if (TARGET_NO_PIC || TARGET_AUTO_PIC) |
2153 | { | |
2154 | if (sibcall_p) | |
599aedd9 | 2155 | insn = gen_sibcall_nogp (addr); |
2ed4af6f | 2156 | else if (! retval) |
599aedd9 | 2157 | insn = gen_call_nogp (addr, b0); |
2ed4af6f | 2158 | else |
599aedd9 RH |
2159 | insn = gen_call_value_nogp (retval, addr, b0); |
2160 | insn = emit_call_insn (insn); | |
2ed4af6f | 2161 | } |
2ed4af6f | 2162 | else |
599aedd9 RH |
2163 | { |
2164 | if (sibcall_p) | |
2165 | insn = gen_sibcall_gp (addr); | |
2166 | else if (! retval) | |
2167 | insn = gen_call_gp (addr, b0); | |
2168 | else | |
2169 | insn = gen_call_value_gp (retval, addr, b0); | |
2170 | insn = emit_call_insn (insn); | |
2ed4af6f | 2171 | |
599aedd9 RH |
2172 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2173 | } | |
6dad5a56 | 2174 | |
599aedd9 | 2175 | if (sibcall_p) |
4e14f1f9 | 2176 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0); |
f2972bf8 DR |
2177 | |
2178 | if (TARGET_ABI_OPEN_VMS) | |
2179 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2180 | gen_rtx_REG (DImode, GR_REG (25))); | |
599aedd9 RH |
2181 | } |
2182 | ||
6fb5fa3c DB |
2183 | static void |
2184 | reg_emitted (enum ia64_frame_regs r) | |
2185 | { | |
2186 | if (emitted_frame_related_regs[r] == 0) | |
2187 | emitted_frame_related_regs[r] = current_frame_info.r[r]; | |
2188 | else | |
2189 | gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]); | |
2190 | } | |
2191 | ||
2192 | static int | |
2193 | get_reg (enum ia64_frame_regs r) | |
2194 | { | |
2195 | reg_emitted (r); | |
2196 | return current_frame_info.r[r]; | |
2197 | } | |
2198 | ||
2199 | static bool | |
2200 | is_emitted (int regno) | |
2201 | { | |
09639a83 | 2202 | unsigned int r; |
6fb5fa3c DB |
2203 | |
2204 | for (r = reg_fp; r < number_of_ia64_frame_regs; r++) | |
2205 | if (emitted_frame_related_regs[r] == regno) | |
2206 | return true; | |
2207 | return false; | |
2208 | } | |
2209 | ||
599aedd9 | 2210 | void |
9c808aad | 2211 | ia64_reload_gp (void) |
599aedd9 RH |
2212 | { |
2213 | rtx tmp; | |
2214 | ||
6fb5fa3c DB |
2215 | if (current_frame_info.r[reg_save_gp]) |
2216 | { | |
2217 | tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp)); | |
2218 | } | |
2ed4af6f | 2219 | else |
599aedd9 RH |
2220 | { |
2221 | HOST_WIDE_INT offset; | |
13f70342 | 2222 | rtx offset_r; |
599aedd9 RH |
2223 | |
2224 | offset = (current_frame_info.spill_cfa_off | |
2225 | + current_frame_info.spill_size); | |
2226 | if (frame_pointer_needed) | |
2227 | { | |
2228 | tmp = hard_frame_pointer_rtx; | |
2229 | offset = -offset; | |
2230 | } | |
2231 | else | |
2232 | { | |
2233 | tmp = stack_pointer_rtx; | |
2234 | offset = current_frame_info.total_size - offset; | |
2235 | } | |
2236 | ||
13f70342 RH |
2237 | offset_r = GEN_INT (offset); |
2238 | if (satisfies_constraint_I (offset_r)) | |
2239 | emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r)); | |
599aedd9 RH |
2240 | else |
2241 | { | |
13f70342 | 2242 | emit_move_insn (pic_offset_table_rtx, offset_r); |
599aedd9 RH |
2243 | emit_insn (gen_adddi3 (pic_offset_table_rtx, |
2244 | pic_offset_table_rtx, tmp)); | |
2245 | } | |
2246 | ||
2247 | tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx); | |
2248 | } | |
2249 | ||
2250 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2251 | } | |
2252 | ||
2253 | void | |
9c808aad AJ |
2254 | ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r, |
2255 | rtx scratch_b, int noreturn_p, int sibcall_p) | |
599aedd9 RH |
2256 | { |
2257 | rtx insn; | |
2258 | bool is_desc = false; | |
2259 | ||
2260 | /* If we find we're calling through a register, then we're actually | |
2261 | calling through a descriptor, so load up the values. */ | |
4e14f1f9 | 2262 | if (REG_P (addr) && GR_REGNO_P (REGNO (addr))) |
599aedd9 RH |
2263 | { |
2264 | rtx tmp; | |
2265 | bool addr_dead_p; | |
2266 | ||
2267 | /* ??? We are currently constrained to *not* use peep2, because | |
2a43945f | 2268 | we can legitimately change the global lifetime of the GP |
9c808aad | 2269 | (in the form of killing where previously live). This is |
599aedd9 RH |
2270 | because a call through a descriptor doesn't use the previous |
2271 | value of the GP, while a direct call does, and we do not | |
2272 | commit to either form until the split here. | |
2273 | ||
2274 | That said, this means that we lack precise life info for | |
2275 | whether ADDR is dead after this call. This is not terribly | |
2276 | important, since we can fix things up essentially for free | |
2277 | with the POST_DEC below, but it's nice to not use it when we | |
2278 | can immediately tell it's not necessary. */ | |
2279 | addr_dead_p = ((noreturn_p || sibcall_p | |
2280 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, | |
2281 | REGNO (addr))) | |
2282 | && !FUNCTION_ARG_REGNO_P (REGNO (addr))); | |
2283 | ||
2284 | /* Load the code address into scratch_b. */ | |
2285 | tmp = gen_rtx_POST_INC (Pmode, addr); | |
2286 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2287 | emit_move_insn (scratch_r, tmp); | |
2288 | emit_move_insn (scratch_b, scratch_r); | |
2289 | ||
2290 | /* Load the GP address. If ADDR is not dead here, then we must | |
2291 | revert the change made above via the POST_INCREMENT. */ | |
2292 | if (!addr_dead_p) | |
2293 | tmp = gen_rtx_POST_DEC (Pmode, addr); | |
2294 | else | |
2295 | tmp = addr; | |
2296 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2297 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2298 | ||
2299 | is_desc = true; | |
2300 | addr = scratch_b; | |
2301 | } | |
2ed4af6f | 2302 | |
6dad5a56 | 2303 | if (sibcall_p) |
599aedd9 RH |
2304 | insn = gen_sibcall_nogp (addr); |
2305 | else if (retval) | |
2306 | insn = gen_call_value_nogp (retval, addr, retaddr); | |
6dad5a56 | 2307 | else |
599aedd9 | 2308 | insn = gen_call_nogp (addr, retaddr); |
6dad5a56 | 2309 | emit_call_insn (insn); |
2ed4af6f | 2310 | |
599aedd9 RH |
2311 | if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p) |
2312 | ia64_reload_gp (); | |
2ed4af6f | 2313 | } |
16df4ee6 RH |
2314 | |
2315 | /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically. | |
2316 | ||
2317 | This differs from the generic code in that we know about the zero-extending | |
2318 | properties of cmpxchg, and the zero-extending requirements of ar.ccv. We | |
2319 | also know that ld.acq+cmpxchg.rel equals a full barrier. | |
2320 | ||
2321 | The loop we want to generate looks like | |
2322 | ||
2323 | cmp_reg = mem; | |
2324 | label: | |
2325 | old_reg = cmp_reg; | |
2326 | new_reg = cmp_reg op val; | |
2327 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) | |
2328 | if (cmp_reg != old_reg) | |
2329 | goto label; | |
2330 | ||
2331 | Note that we only do the plain load from memory once. Subsequent | |
2332 | iterations use the value loaded by the compare-and-swap pattern. */ | |
2333 | ||
2334 | void | |
2335 | ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
28875d67 | 2336 | rtx old_dst, rtx new_dst, enum memmodel model) |
16df4ee6 RH |
2337 | { |
2338 | enum machine_mode mode = GET_MODE (mem); | |
2339 | rtx old_reg, new_reg, cmp_reg, ar_ccv, label; | |
2340 | enum insn_code icode; | |
2341 | ||
2342 | /* Special case for using fetchadd. */ | |
dca13767 JJ |
2343 | if ((mode == SImode || mode == DImode) |
2344 | && (code == PLUS || code == MINUS) | |
2345 | && fetchadd_operand (val, mode)) | |
16df4ee6 | 2346 | { |
dca13767 JJ |
2347 | if (code == MINUS) |
2348 | val = GEN_INT (-INTVAL (val)); | |
2349 | ||
16df4ee6 RH |
2350 | if (!old_dst) |
2351 | old_dst = gen_reg_rtx (mode); | |
2352 | ||
28875d67 RH |
2353 | switch (model) |
2354 | { | |
2355 | case MEMMODEL_ACQ_REL: | |
2356 | case MEMMODEL_SEQ_CST: | |
2357 | emit_insn (gen_memory_barrier ()); | |
2358 | /* FALLTHRU */ | |
2359 | case MEMMODEL_RELAXED: | |
2360 | case MEMMODEL_ACQUIRE: | |
2361 | case MEMMODEL_CONSUME: | |
2362 | if (mode == SImode) | |
2363 | icode = CODE_FOR_fetchadd_acq_si; | |
2364 | else | |
2365 | icode = CODE_FOR_fetchadd_acq_di; | |
2366 | break; | |
2367 | case MEMMODEL_RELEASE: | |
2368 | if (mode == SImode) | |
2369 | icode = CODE_FOR_fetchadd_rel_si; | |
2370 | else | |
2371 | icode = CODE_FOR_fetchadd_rel_di; | |
2372 | break; | |
2373 | ||
2374 | default: | |
2375 | gcc_unreachable (); | |
2376 | } | |
16df4ee6 | 2377 | |
16df4ee6 RH |
2378 | emit_insn (GEN_FCN (icode) (old_dst, mem, val)); |
2379 | ||
2380 | if (new_dst) | |
2381 | { | |
2382 | new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst, | |
2383 | true, OPTAB_WIDEN); | |
2384 | if (new_reg != new_dst) | |
2385 | emit_move_insn (new_dst, new_reg); | |
2386 | } | |
2387 | return; | |
2388 | } | |
2389 | ||
2390 | /* Because of the volatile mem read, we get an ld.acq, which is the | |
28875d67 RH |
2391 | front half of the full barrier. The end half is the cmpxchg.rel. |
2392 | For relaxed and release memory models, we don't need this. But we | |
2393 | also don't bother trying to prevent it either. */ | |
2394 | gcc_assert (model == MEMMODEL_RELAXED | |
2395 | || model == MEMMODEL_RELEASE | |
2396 | || MEM_VOLATILE_P (mem)); | |
16df4ee6 RH |
2397 | |
2398 | old_reg = gen_reg_rtx (DImode); | |
2399 | cmp_reg = gen_reg_rtx (DImode); | |
2400 | label = gen_label_rtx (); | |
2401 | ||
2402 | if (mode != DImode) | |
2403 | { | |
2404 | val = simplify_gen_subreg (DImode, val, mode, 0); | |
2405 | emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1)); | |
2406 | } | |
2407 | else | |
2408 | emit_move_insn (cmp_reg, mem); | |
2409 | ||
2410 | emit_label (label); | |
2411 | ||
2412 | ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); | |
2413 | emit_move_insn (old_reg, cmp_reg); | |
2414 | emit_move_insn (ar_ccv, cmp_reg); | |
2415 | ||
2416 | if (old_dst) | |
2417 | emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg)); | |
2418 | ||
2419 | new_reg = cmp_reg; | |
2420 | if (code == NOT) | |
2421 | { | |
974920dc UB |
2422 | new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX, |
2423 | true, OPTAB_DIRECT); | |
2424 | new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true); | |
16df4ee6 | 2425 | } |
974920dc UB |
2426 | else |
2427 | new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX, | |
2428 | true, OPTAB_DIRECT); | |
16df4ee6 RH |
2429 | |
2430 | if (mode != DImode) | |
2431 | new_reg = gen_lowpart (mode, new_reg); | |
2432 | if (new_dst) | |
2433 | emit_move_insn (new_dst, new_reg); | |
2434 | ||
28875d67 | 2435 | switch (model) |
16df4ee6 | 2436 | { |
28875d67 RH |
2437 | case MEMMODEL_RELAXED: |
2438 | case MEMMODEL_ACQUIRE: | |
2439 | case MEMMODEL_CONSUME: | |
2440 | switch (mode) | |
2441 | { | |
2442 | case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break; | |
2443 | case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break; | |
2444 | case SImode: icode = CODE_FOR_cmpxchg_acq_si; break; | |
2445 | case DImode: icode = CODE_FOR_cmpxchg_acq_di; break; | |
2446 | default: | |
2447 | gcc_unreachable (); | |
2448 | } | |
2449 | break; | |
2450 | ||
2451 | case MEMMODEL_RELEASE: | |
2452 | case MEMMODEL_ACQ_REL: | |
2453 | case MEMMODEL_SEQ_CST: | |
2454 | switch (mode) | |
2455 | { | |
2456 | case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break; | |
2457 | case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break; | |
2458 | case SImode: icode = CODE_FOR_cmpxchg_rel_si; break; | |
2459 | case DImode: icode = CODE_FOR_cmpxchg_rel_di; break; | |
2460 | default: | |
2461 | gcc_unreachable (); | |
2462 | } | |
2463 | break; | |
2464 | ||
16df4ee6 RH |
2465 | default: |
2466 | gcc_unreachable (); | |
2467 | } | |
2468 | ||
2469 | emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg)); | |
2470 | ||
6819a463 | 2471 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label); |
16df4ee6 | 2472 | } |
809d4ef1 | 2473 | \f |
3b572406 RH |
2474 | /* Begin the assembly file. */ |
2475 | ||
1bc7c5b6 | 2476 | static void |
9c808aad | 2477 | ia64_file_start (void) |
1bc7c5b6 ZW |
2478 | { |
2479 | default_file_start (); | |
2480 | emit_safe_across_calls (); | |
2481 | } | |
2482 | ||
3b572406 | 2483 | void |
9c808aad | 2484 | emit_safe_across_calls (void) |
3b572406 RH |
2485 | { |
2486 | unsigned int rs, re; | |
2487 | int out_state; | |
2488 | ||
2489 | rs = 1; | |
2490 | out_state = 0; | |
2491 | while (1) | |
2492 | { | |
2493 | while (rs < 64 && call_used_regs[PR_REG (rs)]) | |
2494 | rs++; | |
2495 | if (rs >= 64) | |
2496 | break; | |
2497 | for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++) | |
2498 | continue; | |
2499 | if (out_state == 0) | |
2500 | { | |
1bc7c5b6 | 2501 | fputs ("\t.pred.safe_across_calls ", asm_out_file); |
3b572406 RH |
2502 | out_state = 1; |
2503 | } | |
2504 | else | |
1bc7c5b6 | 2505 | fputc (',', asm_out_file); |
3b572406 | 2506 | if (re == rs + 1) |
1bc7c5b6 | 2507 | fprintf (asm_out_file, "p%u", rs); |
3b572406 | 2508 | else |
1bc7c5b6 | 2509 | fprintf (asm_out_file, "p%u-p%u", rs, re - 1); |
3b572406 RH |
2510 | rs = re + 1; |
2511 | } | |
2512 | if (out_state) | |
1bc7c5b6 | 2513 | fputc ('\n', asm_out_file); |
3b572406 RH |
2514 | } |
2515 | ||
812b587e SE |
2516 | /* Globalize a declaration. */ |
2517 | ||
2518 | static void | |
2519 | ia64_globalize_decl_name (FILE * stream, tree decl) | |
2520 | { | |
2521 | const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
2522 | tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl)); | |
2523 | if (version_attr) | |
2524 | { | |
2525 | tree v = TREE_VALUE (TREE_VALUE (version_attr)); | |
2526 | const char *p = TREE_STRING_POINTER (v); | |
2527 | fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p); | |
2528 | } | |
2529 | targetm.asm_out.globalize_label (stream, name); | |
2530 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2531 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); | |
2532 | } | |
2533 | ||
97e242b0 RH |
2534 | /* Helper function for ia64_compute_frame_size: find an appropriate general |
2535 | register to spill some special register to. SPECIAL_SPILL_MASK contains | |
2536 | bits in GR0 to GR31 that have already been allocated by this routine. | |
2537 | TRY_LOCALS is true if we should attempt to locate a local regnum. */ | |
c65ebc55 | 2538 | |
97e242b0 | 2539 | static int |
6fb5fa3c | 2540 | find_gr_spill (enum ia64_frame_regs r, int try_locals) |
97e242b0 RH |
2541 | { |
2542 | int regno; | |
2543 | ||
6fb5fa3c DB |
2544 | if (emitted_frame_related_regs[r] != 0) |
2545 | { | |
2546 | regno = emitted_frame_related_regs[r]; | |
2951f79b JJ |
2547 | if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed) |
2548 | && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1) | |
6fb5fa3c DB |
2549 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; |
2550 | else if (current_function_is_leaf | |
2551 | && regno >= GR_REG (1) && regno <= GR_REG (31)) | |
2552 | current_frame_info.gr_used_mask |= 1 << regno; | |
2553 | ||
2554 | return regno; | |
2555 | } | |
2556 | ||
97e242b0 RH |
2557 | /* If this is a leaf function, first try an otherwise unused |
2558 | call-clobbered register. */ | |
2559 | if (current_function_is_leaf) | |
2560 | { | |
2561 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) | |
6fb5fa3c | 2562 | if (! df_regs_ever_live_p (regno) |
97e242b0 RH |
2563 | && call_used_regs[regno] |
2564 | && ! fixed_regs[regno] | |
2565 | && ! global_regs[regno] | |
6fb5fa3c DB |
2566 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0 |
2567 | && ! is_emitted (regno)) | |
97e242b0 RH |
2568 | { |
2569 | current_frame_info.gr_used_mask |= 1 << regno; | |
2570 | return regno; | |
2571 | } | |
2572 | } | |
2573 | ||
2574 | if (try_locals) | |
2575 | { | |
2576 | regno = current_frame_info.n_local_regs; | |
9502c558 JW |
2577 | /* If there is a frame pointer, then we can't use loc79, because |
2578 | that is HARD_FRAME_POINTER_REGNUM. In particular, see the | |
2579 | reg_name switching code in ia64_expand_prologue. */ | |
2951f79b JJ |
2580 | while (regno < (80 - frame_pointer_needed)) |
2581 | if (! is_emitted (LOC_REG (regno++))) | |
2582 | { | |
2583 | current_frame_info.n_local_regs = regno; | |
2584 | return LOC_REG (regno - 1); | |
2585 | } | |
97e242b0 RH |
2586 | } |
2587 | ||
2588 | /* Failed to find a general register to spill to. Must use stack. */ | |
2589 | return 0; | |
2590 | } | |
2591 | ||
2592 | /* In order to make for nice schedules, we try to allocate every temporary | |
2593 | to a different register. We must of course stay away from call-saved, | |
2594 | fixed, and global registers. We must also stay away from registers | |
2595 | allocated in current_frame_info.gr_used_mask, since those include regs | |
2596 | used all through the prologue. | |
2597 | ||
2598 | Any register allocated here must be used immediately. The idea is to | |
2599 | aid scheduling, not to solve data flow problems. */ | |
2600 | ||
2601 | static int last_scratch_gr_reg; | |
2602 | ||
2603 | static int | |
9c808aad | 2604 | next_scratch_gr_reg (void) |
97e242b0 RH |
2605 | { |
2606 | int i, regno; | |
2607 | ||
2608 | for (i = 0; i < 32; ++i) | |
2609 | { | |
2610 | regno = (last_scratch_gr_reg + i + 1) & 31; | |
2611 | if (call_used_regs[regno] | |
2612 | && ! fixed_regs[regno] | |
2613 | && ! global_regs[regno] | |
2614 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0) | |
2615 | { | |
2616 | last_scratch_gr_reg = regno; | |
2617 | return regno; | |
2618 | } | |
2619 | } | |
2620 | ||
2621 | /* There must be _something_ available. */ | |
e820471b | 2622 | gcc_unreachable (); |
97e242b0 RH |
2623 | } |
2624 | ||
2625 | /* Helper function for ia64_compute_frame_size, called through | |
2626 | diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */ | |
2627 | ||
2628 | static void | |
9c808aad | 2629 | mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED) |
c65ebc55 | 2630 | { |
97e242b0 RH |
2631 | unsigned int regno = REGNO (reg); |
2632 | if (regno < 32) | |
f95e79cc | 2633 | { |
c8b622ff | 2634 | unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)]; |
f95e79cc RH |
2635 | for (i = 0; i < n; ++i) |
2636 | current_frame_info.gr_used_mask |= 1 << (regno + i); | |
2637 | } | |
c65ebc55 JW |
2638 | } |
2639 | ||
6fb5fa3c | 2640 | |
c65ebc55 JW |
2641 | /* Returns the number of bytes offset between the frame pointer and the stack |
2642 | pointer for the current function. SIZE is the number of bytes of space | |
2643 | needed for local variables. */ | |
97e242b0 RH |
2644 | |
2645 | static void | |
9c808aad | 2646 | ia64_compute_frame_size (HOST_WIDE_INT size) |
c65ebc55 | 2647 | { |
97e242b0 RH |
2648 | HOST_WIDE_INT total_size; |
2649 | HOST_WIDE_INT spill_size = 0; | |
2650 | HOST_WIDE_INT extra_spill_size = 0; | |
2651 | HOST_WIDE_INT pretend_args_size; | |
c65ebc55 | 2652 | HARD_REG_SET mask; |
97e242b0 RH |
2653 | int n_spilled = 0; |
2654 | int spilled_gr_p = 0; | |
2655 | int spilled_fr_p = 0; | |
2656 | unsigned int regno; | |
2951f79b JJ |
2657 | int min_regno; |
2658 | int max_regno; | |
97e242b0 | 2659 | int i; |
c65ebc55 | 2660 | |
97e242b0 RH |
2661 | if (current_frame_info.initialized) |
2662 | return; | |
294dac80 | 2663 | |
97e242b0 | 2664 | memset (¤t_frame_info, 0, sizeof current_frame_info); |
c65ebc55 JW |
2665 | CLEAR_HARD_REG_SET (mask); |
2666 | ||
97e242b0 RH |
2667 | /* Don't allocate scratches to the return register. */ |
2668 | diddle_return_value (mark_reg_gr_used_mask, NULL); | |
2669 | ||
2670 | /* Don't allocate scratches to the EH scratch registers. */ | |
2671 | if (cfun->machine->ia64_eh_epilogue_sp) | |
2672 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL); | |
2673 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
2674 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL); | |
c65ebc55 | 2675 | |
7b84aac0 EB |
2676 | /* Static stack checking uses r2 and r3. */ |
2677 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) | |
2678 | current_frame_info.gr_used_mask |= 0xc; | |
2679 | ||
97e242b0 RH |
2680 | /* Find the size of the register stack frame. We have only 80 local |
2681 | registers, because we reserve 8 for the inputs and 8 for the | |
2682 | outputs. */ | |
2683 | ||
2684 | /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed, | |
2685 | since we'll be adjusting that down later. */ | |
2686 | regno = LOC_REG (78) + ! frame_pointer_needed; | |
2687 | for (; regno >= LOC_REG (0); regno--) | |
6fb5fa3c | 2688 | if (df_regs_ever_live_p (regno) && !is_emitted (regno)) |
97e242b0 RH |
2689 | break; |
2690 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; | |
c65ebc55 | 2691 | |
3f67ac08 DM |
2692 | /* For functions marked with the syscall_linkage attribute, we must mark |
2693 | all eight input registers as in use, so that locals aren't visible to | |
2694 | the caller. */ | |
2695 | ||
2696 | if (cfun->machine->n_varargs > 0 | |
2697 | || lookup_attribute ("syscall_linkage", | |
2698 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
97e242b0 RH |
2699 | current_frame_info.n_input_regs = 8; |
2700 | else | |
2701 | { | |
2702 | for (regno = IN_REG (7); regno >= IN_REG (0); regno--) | |
6fb5fa3c | 2703 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2704 | break; |
2705 | current_frame_info.n_input_regs = regno - IN_REG (0) + 1; | |
2706 | } | |
2707 | ||
2708 | for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--) | |
6fb5fa3c | 2709 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2710 | break; |
2711 | i = regno - OUT_REG (0) + 1; | |
2712 | ||
d26afa4f | 2713 | #ifndef PROFILE_HOOK |
97e242b0 | 2714 | /* When -p profiling, we need one output register for the mcount argument. |
9e4f94de | 2715 | Likewise for -a profiling for the bb_init_func argument. For -ax |
97e242b0 RH |
2716 | profiling, we need two output registers for the two bb_init_trace_func |
2717 | arguments. */ | |
e3b5732b | 2718 | if (crtl->profile) |
97e242b0 | 2719 | i = MAX (i, 1); |
d26afa4f | 2720 | #endif |
97e242b0 RH |
2721 | current_frame_info.n_output_regs = i; |
2722 | ||
2723 | /* ??? No rotating register support yet. */ | |
2724 | current_frame_info.n_rotate_regs = 0; | |
2725 | ||
2726 | /* Discover which registers need spilling, and how much room that | |
9c808aad | 2727 | will take. Begin with floating point and general registers, |
97e242b0 RH |
2728 | which will always wind up on the stack. */ |
2729 | ||
2730 | for (regno = FR_REG (2); regno <= FR_REG (127); regno++) | |
6fb5fa3c | 2731 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2732 | { |
2733 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2734 | spill_size += 16; |
2735 | n_spilled += 1; | |
2736 | spilled_fr_p = 1; | |
c65ebc55 JW |
2737 | } |
2738 | ||
97e242b0 | 2739 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) |
6fb5fa3c | 2740 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2741 | { |
2742 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2743 | spill_size += 8; |
2744 | n_spilled += 1; | |
2745 | spilled_gr_p = 1; | |
c65ebc55 JW |
2746 | } |
2747 | ||
97e242b0 | 2748 | for (regno = BR_REG (1); regno <= BR_REG (7); regno++) |
6fb5fa3c | 2749 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2750 | { |
2751 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2752 | spill_size += 8; |
2753 | n_spilled += 1; | |
c65ebc55 JW |
2754 | } |
2755 | ||
97e242b0 RH |
2756 | /* Now come all special registers that might get saved in other |
2757 | general registers. */ | |
9c808aad | 2758 | |
97e242b0 RH |
2759 | if (frame_pointer_needed) |
2760 | { | |
6fb5fa3c | 2761 | current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1); |
0c35f902 JW |
2762 | /* If we did not get a register, then we take LOC79. This is guaranteed |
2763 | to be free, even if regs_ever_live is already set, because this is | |
2764 | HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs, | |
2765 | as we don't count loc79 above. */ | |
6fb5fa3c | 2766 | if (current_frame_info.r[reg_fp] == 0) |
0c35f902 | 2767 | { |
6fb5fa3c DB |
2768 | current_frame_info.r[reg_fp] = LOC_REG (79); |
2769 | current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1; | |
0c35f902 | 2770 | } |
97e242b0 RH |
2771 | } |
2772 | ||
2773 | if (! current_function_is_leaf) | |
c65ebc55 | 2774 | { |
97e242b0 RH |
2775 | /* Emit a save of BR0 if we call other functions. Do this even |
2776 | if this function doesn't return, as EH depends on this to be | |
2777 | able to unwind the stack. */ | |
2778 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
2779 | ||
6fb5fa3c DB |
2780 | current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1); |
2781 | if (current_frame_info.r[reg_save_b0] == 0) | |
97e242b0 | 2782 | { |
ae1e2d4c | 2783 | extra_spill_size += 8; |
97e242b0 RH |
2784 | n_spilled += 1; |
2785 | } | |
2786 | ||
2787 | /* Similarly for ar.pfs. */ | |
2788 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2789 | current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1); |
2790 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
97e242b0 RH |
2791 | { |
2792 | extra_spill_size += 8; | |
2793 | n_spilled += 1; | |
2794 | } | |
599aedd9 RH |
2795 | |
2796 | /* Similarly for gp. Note that if we're calling setjmp, the stacked | |
2797 | registers are clobbered, so we fall back to the stack. */ | |
6fb5fa3c | 2798 | current_frame_info.r[reg_save_gp] |
e3b5732b | 2799 | = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1)); |
6fb5fa3c | 2800 | if (current_frame_info.r[reg_save_gp] == 0) |
599aedd9 RH |
2801 | { |
2802 | SET_HARD_REG_BIT (mask, GR_REG (1)); | |
2803 | spill_size += 8; | |
2804 | n_spilled += 1; | |
2805 | } | |
c65ebc55 JW |
2806 | } |
2807 | else | |
97e242b0 | 2808 | { |
6fb5fa3c | 2809 | if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)]) |
97e242b0 RH |
2810 | { |
2811 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
ae1e2d4c | 2812 | extra_spill_size += 8; |
97e242b0 RH |
2813 | n_spilled += 1; |
2814 | } | |
f5bdba44 | 2815 | |
6fb5fa3c | 2816 | if (df_regs_ever_live_p (AR_PFS_REGNUM)) |
f5bdba44 RH |
2817 | { |
2818 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2819 | current_frame_info.r[reg_save_ar_pfs] |
2820 | = find_gr_spill (reg_save_ar_pfs, 1); | |
2821 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
f5bdba44 RH |
2822 | { |
2823 | extra_spill_size += 8; | |
2824 | n_spilled += 1; | |
2825 | } | |
2826 | } | |
97e242b0 | 2827 | } |
c65ebc55 | 2828 | |
97e242b0 RH |
2829 | /* Unwind descriptor hackery: things are most efficient if we allocate |
2830 | consecutive GR save registers for RP, PFS, FP in that order. However, | |
2831 | it is absolutely critical that FP get the only hard register that's | |
2832 | guaranteed to be free, so we allocated it first. If all three did | |
2833 | happen to be allocated hard regs, and are consecutive, rearrange them | |
6fb5fa3c DB |
2834 | into the preferred order now. |
2835 | ||
2836 | If we have already emitted code for any of those registers, | |
2837 | then it's already too late to change. */ | |
2951f79b JJ |
2838 | min_regno = MIN (current_frame_info.r[reg_fp], |
2839 | MIN (current_frame_info.r[reg_save_b0], | |
2840 | current_frame_info.r[reg_save_ar_pfs])); | |
2841 | max_regno = MAX (current_frame_info.r[reg_fp], | |
2842 | MAX (current_frame_info.r[reg_save_b0], | |
2843 | current_frame_info.r[reg_save_ar_pfs])); | |
2844 | if (min_regno > 0 | |
2845 | && min_regno + 2 == max_regno | |
2846 | && (current_frame_info.r[reg_fp] == min_regno + 1 | |
2847 | || current_frame_info.r[reg_save_b0] == min_regno + 1 | |
2848 | || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1) | |
2849 | && (emitted_frame_related_regs[reg_save_b0] == 0 | |
2850 | || emitted_frame_related_regs[reg_save_b0] == min_regno) | |
2851 | && (emitted_frame_related_regs[reg_save_ar_pfs] == 0 | |
2852 | || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1) | |
2853 | && (emitted_frame_related_regs[reg_fp] == 0 | |
2854 | || emitted_frame_related_regs[reg_fp] == min_regno + 2)) | |
5527bf14 | 2855 | { |
2951f79b JJ |
2856 | current_frame_info.r[reg_save_b0] = min_regno; |
2857 | current_frame_info.r[reg_save_ar_pfs] = min_regno + 1; | |
2858 | current_frame_info.r[reg_fp] = min_regno + 2; | |
5527bf14 RH |
2859 | } |
2860 | ||
97e242b0 RH |
2861 | /* See if we need to store the predicate register block. */ |
2862 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2863 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
97e242b0 RH |
2864 | break; |
2865 | if (regno <= PR_REG (63)) | |
c65ebc55 | 2866 | { |
97e242b0 | 2867 | SET_HARD_REG_BIT (mask, PR_REG (0)); |
6fb5fa3c DB |
2868 | current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1); |
2869 | if (current_frame_info.r[reg_save_pr] == 0) | |
97e242b0 RH |
2870 | { |
2871 | extra_spill_size += 8; | |
2872 | n_spilled += 1; | |
2873 | } | |
2874 | ||
2875 | /* ??? Mark them all as used so that register renaming and such | |
2876 | are free to use them. */ | |
2877 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2878 | df_set_regs_ever_live (regno, true); |
c65ebc55 JW |
2879 | } |
2880 | ||
97e242b0 | 2881 | /* If we're forced to use st8.spill, we're forced to save and restore |
f5bdba44 RH |
2882 | ar.unat as well. The check for existing liveness allows inline asm |
2883 | to touch ar.unat. */ | |
2884 | if (spilled_gr_p || cfun->machine->n_varargs | |
6fb5fa3c | 2885 | || df_regs_ever_live_p (AR_UNAT_REGNUM)) |
97e242b0 | 2886 | { |
6fb5fa3c | 2887 | df_set_regs_ever_live (AR_UNAT_REGNUM, true); |
97e242b0 | 2888 | SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM); |
6fb5fa3c DB |
2889 | current_frame_info.r[reg_save_ar_unat] |
2890 | = find_gr_spill (reg_save_ar_unat, spill_size == 0); | |
2891 | if (current_frame_info.r[reg_save_ar_unat] == 0) | |
97e242b0 RH |
2892 | { |
2893 | extra_spill_size += 8; | |
2894 | n_spilled += 1; | |
2895 | } | |
2896 | } | |
2897 | ||
6fb5fa3c | 2898 | if (df_regs_ever_live_p (AR_LC_REGNUM)) |
97e242b0 RH |
2899 | { |
2900 | SET_HARD_REG_BIT (mask, AR_LC_REGNUM); | |
6fb5fa3c DB |
2901 | current_frame_info.r[reg_save_ar_lc] |
2902 | = find_gr_spill (reg_save_ar_lc, spill_size == 0); | |
2903 | if (current_frame_info.r[reg_save_ar_lc] == 0) | |
97e242b0 RH |
2904 | { |
2905 | extra_spill_size += 8; | |
2906 | n_spilled += 1; | |
2907 | } | |
2908 | } | |
2909 | ||
2910 | /* If we have an odd number of words of pretend arguments written to | |
2911 | the stack, then the FR save area will be unaligned. We round the | |
2912 | size of this area up to keep things 16 byte aligned. */ | |
2913 | if (spilled_fr_p) | |
38173d38 | 2914 | pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size); |
97e242b0 | 2915 | else |
38173d38 | 2916 | pretend_args_size = crtl->args.pretend_args_size; |
97e242b0 RH |
2917 | |
2918 | total_size = (spill_size + extra_spill_size + size + pretend_args_size | |
38173d38 | 2919 | + crtl->outgoing_args_size); |
97e242b0 RH |
2920 | total_size = IA64_STACK_ALIGN (total_size); |
2921 | ||
2922 | /* We always use the 16-byte scratch area provided by the caller, but | |
2923 | if we are a leaf function, there's no one to which we need to provide | |
2924 | a scratch area. */ | |
2925 | if (current_function_is_leaf) | |
2926 | total_size = MAX (0, total_size - 16); | |
2927 | ||
c65ebc55 | 2928 | current_frame_info.total_size = total_size; |
97e242b0 RH |
2929 | current_frame_info.spill_cfa_off = pretend_args_size - 16; |
2930 | current_frame_info.spill_size = spill_size; | |
2931 | current_frame_info.extra_spill_size = extra_spill_size; | |
c65ebc55 | 2932 | COPY_HARD_REG_SET (current_frame_info.mask, mask); |
97e242b0 | 2933 | current_frame_info.n_spilled = n_spilled; |
c65ebc55 | 2934 | current_frame_info.initialized = reload_completed; |
97e242b0 RH |
2935 | } |
2936 | ||
7b5cbb57 AS |
2937 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2938 | ||
2939 | bool | |
2940 | ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
2941 | { | |
2942 | return (to == BR_REG (0) ? current_function_is_leaf : true); | |
2943 | } | |
2944 | ||
97e242b0 RH |
2945 | /* Compute the initial difference between the specified pair of registers. */ |
2946 | ||
2947 | HOST_WIDE_INT | |
9c808aad | 2948 | ia64_initial_elimination_offset (int from, int to) |
97e242b0 RH |
2949 | { |
2950 | HOST_WIDE_INT offset; | |
2951 | ||
2952 | ia64_compute_frame_size (get_frame_size ()); | |
2953 | switch (from) | |
2954 | { | |
2955 | case FRAME_POINTER_REGNUM: | |
e820471b | 2956 | switch (to) |
97e242b0 | 2957 | { |
e820471b | 2958 | case HARD_FRAME_POINTER_REGNUM: |
97e242b0 RH |
2959 | if (current_function_is_leaf) |
2960 | offset = -current_frame_info.total_size; | |
2961 | else | |
2962 | offset = -(current_frame_info.total_size | |
38173d38 | 2963 | - crtl->outgoing_args_size - 16); |
e820471b NS |
2964 | break; |
2965 | ||
2966 | case STACK_POINTER_REGNUM: | |
97e242b0 RH |
2967 | if (current_function_is_leaf) |
2968 | offset = 0; | |
2969 | else | |
38173d38 | 2970 | offset = 16 + crtl->outgoing_args_size; |
e820471b NS |
2971 | break; |
2972 | ||
2973 | default: | |
2974 | gcc_unreachable (); | |
97e242b0 | 2975 | } |
97e242b0 | 2976 | break; |
c65ebc55 | 2977 | |
97e242b0 RH |
2978 | case ARG_POINTER_REGNUM: |
2979 | /* Arguments start above the 16 byte save area, unless stdarg | |
2980 | in which case we store through the 16 byte save area. */ | |
e820471b NS |
2981 | switch (to) |
2982 | { | |
2983 | case HARD_FRAME_POINTER_REGNUM: | |
38173d38 | 2984 | offset = 16 - crtl->args.pretend_args_size; |
e820471b NS |
2985 | break; |
2986 | ||
2987 | case STACK_POINTER_REGNUM: | |
2988 | offset = (current_frame_info.total_size | |
38173d38 | 2989 | + 16 - crtl->args.pretend_args_size); |
e820471b NS |
2990 | break; |
2991 | ||
2992 | default: | |
2993 | gcc_unreachable (); | |
2994 | } | |
97e242b0 RH |
2995 | break; |
2996 | ||
97e242b0 | 2997 | default: |
e820471b | 2998 | gcc_unreachable (); |
97e242b0 RH |
2999 | } |
3000 | ||
3001 | return offset; | |
c65ebc55 JW |
3002 | } |
3003 | ||
97e242b0 RH |
3004 | /* If there are more than a trivial number of register spills, we use |
3005 | two interleaved iterators so that we can get two memory references | |
3006 | per insn group. | |
3007 | ||
3008 | In order to simplify things in the prologue and epilogue expanders, | |
3009 | we use helper functions to fix up the memory references after the | |
3010 | fact with the appropriate offsets to a POST_MODIFY memory mode. | |
3011 | The following data structure tracks the state of the two iterators | |
3012 | while insns are being emitted. */ | |
3013 | ||
3014 | struct spill_fill_data | |
c65ebc55 | 3015 | { |
d6a7951f | 3016 | rtx init_after; /* point at which to emit initializations */ |
97e242b0 RH |
3017 | rtx init_reg[2]; /* initial base register */ |
3018 | rtx iter_reg[2]; /* the iterator registers */ | |
3019 | rtx *prev_addr[2]; /* address of last memory use */ | |
703cf211 | 3020 | rtx prev_insn[2]; /* the insn corresponding to prev_addr */ |
97e242b0 RH |
3021 | HOST_WIDE_INT prev_off[2]; /* last offset */ |
3022 | int n_iter; /* number of iterators in use */ | |
3023 | int next_iter; /* next iterator to use */ | |
3024 | unsigned int save_gr_used_mask; | |
3025 | }; | |
3026 | ||
3027 | static struct spill_fill_data spill_fill_data; | |
c65ebc55 | 3028 | |
97e242b0 | 3029 | static void |
9c808aad | 3030 | setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3031 | { |
3032 | int i; | |
3033 | ||
3034 | spill_fill_data.init_after = get_last_insn (); | |
3035 | spill_fill_data.init_reg[0] = init_reg; | |
3036 | spill_fill_data.init_reg[1] = init_reg; | |
3037 | spill_fill_data.prev_addr[0] = NULL; | |
3038 | spill_fill_data.prev_addr[1] = NULL; | |
703cf211 BS |
3039 | spill_fill_data.prev_insn[0] = NULL; |
3040 | spill_fill_data.prev_insn[1] = NULL; | |
97e242b0 RH |
3041 | spill_fill_data.prev_off[0] = cfa_off; |
3042 | spill_fill_data.prev_off[1] = cfa_off; | |
3043 | spill_fill_data.next_iter = 0; | |
3044 | spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask; | |
3045 | ||
3046 | spill_fill_data.n_iter = 1 + (n_spills > 2); | |
3047 | for (i = 0; i < spill_fill_data.n_iter; ++i) | |
c65ebc55 | 3048 | { |
97e242b0 RH |
3049 | int regno = next_scratch_gr_reg (); |
3050 | spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno); | |
3051 | current_frame_info.gr_used_mask |= 1 << regno; | |
3052 | } | |
3053 | } | |
3054 | ||
3055 | static void | |
9c808aad | 3056 | finish_spill_pointers (void) |
97e242b0 RH |
3057 | { |
3058 | current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask; | |
3059 | } | |
c65ebc55 | 3060 | |
97e242b0 | 3061 | static rtx |
9c808aad | 3062 | spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3063 | { |
3064 | int iter = spill_fill_data.next_iter; | |
3065 | HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off; | |
3066 | rtx disp_rtx = GEN_INT (disp); | |
3067 | rtx mem; | |
3068 | ||
3069 | if (spill_fill_data.prev_addr[iter]) | |
3070 | { | |
13f70342 | 3071 | if (satisfies_constraint_N (disp_rtx)) |
703cf211 BS |
3072 | { |
3073 | *spill_fill_data.prev_addr[iter] | |
3074 | = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter], | |
3075 | gen_rtx_PLUS (DImode, | |
3076 | spill_fill_data.iter_reg[iter], | |
3077 | disp_rtx)); | |
bbbbb16a ILT |
3078 | add_reg_note (spill_fill_data.prev_insn[iter], |
3079 | REG_INC, spill_fill_data.iter_reg[iter]); | |
703cf211 | 3080 | } |
c65ebc55 JW |
3081 | else |
3082 | { | |
97e242b0 | 3083 | /* ??? Could use register post_modify for loads. */ |
13f70342 | 3084 | if (!satisfies_constraint_I (disp_rtx)) |
97e242b0 RH |
3085 | { |
3086 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); | |
3087 | emit_move_insn (tmp, disp_rtx); | |
3088 | disp_rtx = tmp; | |
3089 | } | |
3090 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3091 | spill_fill_data.iter_reg[iter], disp_rtx)); | |
c65ebc55 | 3092 | } |
97e242b0 RH |
3093 | } |
3094 | /* Micro-optimization: if we've created a frame pointer, it's at | |
3095 | CFA 0, which may allow the real iterator to be initialized lower, | |
3096 | slightly increasing parallelism. Also, if there are few saves | |
3097 | it may eliminate the iterator entirely. */ | |
3098 | else if (disp == 0 | |
3099 | && spill_fill_data.init_reg[iter] == stack_pointer_rtx | |
3100 | && frame_pointer_needed) | |
3101 | { | |
3102 | mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx); | |
ba4828e0 | 3103 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
97e242b0 RH |
3104 | return mem; |
3105 | } | |
3106 | else | |
3107 | { | |
892a4e60 | 3108 | rtx seq, insn; |
809d4ef1 | 3109 | |
97e242b0 RH |
3110 | if (disp == 0) |
3111 | seq = gen_movdi (spill_fill_data.iter_reg[iter], | |
3112 | spill_fill_data.init_reg[iter]); | |
3113 | else | |
c65ebc55 | 3114 | { |
97e242b0 RH |
3115 | start_sequence (); |
3116 | ||
13f70342 | 3117 | if (!satisfies_constraint_I (disp_rtx)) |
c65ebc55 | 3118 | { |
97e242b0 RH |
3119 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); |
3120 | emit_move_insn (tmp, disp_rtx); | |
3121 | disp_rtx = tmp; | |
c65ebc55 | 3122 | } |
97e242b0 RH |
3123 | |
3124 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3125 | spill_fill_data.init_reg[iter], | |
3126 | disp_rtx)); | |
3127 | ||
2f937369 | 3128 | seq = get_insns (); |
97e242b0 | 3129 | end_sequence (); |
c65ebc55 | 3130 | } |
809d4ef1 | 3131 | |
97e242b0 RH |
3132 | /* Careful for being the first insn in a sequence. */ |
3133 | if (spill_fill_data.init_after) | |
892a4e60 | 3134 | insn = emit_insn_after (seq, spill_fill_data.init_after); |
97e242b0 | 3135 | else |
bc08aefe RH |
3136 | { |
3137 | rtx first = get_insns (); | |
3138 | if (first) | |
892a4e60 | 3139 | insn = emit_insn_before (seq, first); |
bc08aefe | 3140 | else |
892a4e60 | 3141 | insn = emit_insn (seq); |
bc08aefe | 3142 | } |
892a4e60 | 3143 | spill_fill_data.init_after = insn; |
97e242b0 | 3144 | } |
c65ebc55 | 3145 | |
97e242b0 | 3146 | mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]); |
c65ebc55 | 3147 | |
97e242b0 RH |
3148 | /* ??? Not all of the spills are for varargs, but some of them are. |
3149 | The rest of the spills belong in an alias set of their own. But | |
3150 | it doesn't actually hurt to include them here. */ | |
ba4828e0 | 3151 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
809d4ef1 | 3152 | |
97e242b0 RH |
3153 | spill_fill_data.prev_addr[iter] = &XEXP (mem, 0); |
3154 | spill_fill_data.prev_off[iter] = cfa_off; | |
c65ebc55 | 3155 | |
97e242b0 RH |
3156 | if (++iter >= spill_fill_data.n_iter) |
3157 | iter = 0; | |
3158 | spill_fill_data.next_iter = iter; | |
c65ebc55 | 3159 | |
97e242b0 RH |
3160 | return mem; |
3161 | } | |
5527bf14 | 3162 | |
97e242b0 | 3163 | static void |
9c808aad AJ |
3164 | do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off, |
3165 | rtx frame_reg) | |
97e242b0 | 3166 | { |
703cf211 | 3167 | int iter = spill_fill_data.next_iter; |
97e242b0 | 3168 | rtx mem, insn; |
5527bf14 | 3169 | |
97e242b0 | 3170 | mem = spill_restore_mem (reg, cfa_off); |
870f9ec0 | 3171 | insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off))); |
703cf211 | 3172 | spill_fill_data.prev_insn[iter] = insn; |
5527bf14 | 3173 | |
97e242b0 RH |
3174 | if (frame_reg) |
3175 | { | |
3176 | rtx base; | |
3177 | HOST_WIDE_INT off; | |
3178 | ||
3179 | RTX_FRAME_RELATED_P (insn) = 1; | |
3180 | ||
9c808aad | 3181 | /* Don't even pretend that the unwind code can intuit its way |
97e242b0 RH |
3182 | through a pair of interleaved post_modify iterators. Just |
3183 | provide the correct answer. */ | |
3184 | ||
3185 | if (frame_pointer_needed) | |
3186 | { | |
3187 | base = hard_frame_pointer_rtx; | |
3188 | off = - cfa_off; | |
5527bf14 | 3189 | } |
97e242b0 RH |
3190 | else |
3191 | { | |
3192 | base = stack_pointer_rtx; | |
3193 | off = current_frame_info.total_size - cfa_off; | |
3194 | } | |
3195 | ||
5c255b57 | 3196 | add_reg_note (insn, REG_CFA_OFFSET, |
bbbbb16a ILT |
3197 | gen_rtx_SET (VOIDmode, |
3198 | gen_rtx_MEM (GET_MODE (reg), | |
0a81f074 RS |
3199 | plus_constant (Pmode, |
3200 | base, off)), | |
bbbbb16a | 3201 | frame_reg)); |
c65ebc55 JW |
3202 | } |
3203 | } | |
3204 | ||
97e242b0 | 3205 | static void |
9c808aad | 3206 | do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 | 3207 | { |
703cf211 BS |
3208 | int iter = spill_fill_data.next_iter; |
3209 | rtx insn; | |
3210 | ||
3211 | insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off), | |
3212 | GEN_INT (cfa_off))); | |
3213 | spill_fill_data.prev_insn[iter] = insn; | |
97e242b0 RH |
3214 | } |
3215 | ||
870f9ec0 RH |
3216 | /* Wrapper functions that discards the CONST_INT spill offset. These |
3217 | exist so that we can give gr_spill/gr_fill the offset they need and | |
9e4f94de | 3218 | use a consistent function interface. */ |
870f9ec0 RH |
3219 | |
3220 | static rtx | |
9c808aad | 3221 | gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3222 | { |
3223 | return gen_movdi (dest, src); | |
3224 | } | |
3225 | ||
3226 | static rtx | |
9c808aad | 3227 | gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3228 | { |
3229 | return gen_fr_spill (dest, src); | |
3230 | } | |
3231 | ||
3232 | static rtx | |
9c808aad | 3233 | gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3234 | { |
3235 | return gen_fr_restore (dest, src); | |
3236 | } | |
c65ebc55 | 3237 | |
7b84aac0 EB |
3238 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
3239 | ||
3240 | /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */ | |
3241 | #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0) | |
3242 | ||
3243 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
3244 | inclusive. These are offsets from the current stack pointer. SOL is the | |
3245 | size of local registers. ??? This clobbers r2 and r3. */ | |
3246 | ||
3247 | static void | |
3248 | ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size, int sol) | |
3249 | { | |
3250 | /* On the IA-64 there is a second stack in memory, namely the Backing Store | |
3251 | of the Register Stack Engine. We also need to probe it after checking | |
3252 | that the 2 stacks don't overlap. */ | |
3253 | const int bs_size = BACKING_STORE_SIZE (sol); | |
3254 | rtx r2 = gen_rtx_REG (Pmode, GR_REG (2)); | |
3255 | rtx r3 = gen_rtx_REG (Pmode, GR_REG (3)); | |
3256 | ||
3257 | /* Detect collision of the 2 stacks if necessary. */ | |
3258 | if (bs_size > 0 || size > 0) | |
3259 | { | |
3260 | rtx p6 = gen_rtx_REG (BImode, PR_REG (6)); | |
3261 | ||
3262 | emit_insn (gen_bsp_value (r3)); | |
3263 | emit_move_insn (r2, GEN_INT (-(first + size))); | |
3264 | ||
3265 | /* Compare current value of BSP and SP registers. */ | |
3266 | emit_insn (gen_rtx_SET (VOIDmode, p6, | |
3267 | gen_rtx_fmt_ee (LTU, BImode, | |
3268 | r3, stack_pointer_rtx))); | |
3269 | ||
3270 | /* Compute the address of the probe for the Backing Store (which grows | |
3271 | towards higher addresses). We probe only at the first offset of | |
3272 | the next page because some OS (eg Linux/ia64) only extend the | |
3273 | backing store when this specific address is hit (but generate a SEGV | |
3274 | on other address). Page size is the worst case (4KB). The reserve | |
3275 | size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough. | |
3276 | Also compute the address of the last probe for the memory stack | |
3277 | (which grows towards lower addresses). */ | |
f65e3801 | 3278 | emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095))); |
7b84aac0 EB |
3279 | emit_insn (gen_rtx_SET (VOIDmode, r2, |
3280 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3281 | ||
3282 | /* Compare them and raise SEGV if the former has topped the latter. */ | |
3283 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3284 | gen_rtx_fmt_ee (NE, VOIDmode, p6, | |
3285 | const0_rtx), | |
3286 | gen_rtx_SET (VOIDmode, p6, | |
3287 | gen_rtx_fmt_ee (GEU, BImode, | |
3288 | r3, r2)))); | |
3289 | emit_insn (gen_rtx_SET (VOIDmode, | |
3290 | gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12), | |
3291 | const0_rtx), | |
3292 | const0_rtx)); | |
3293 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3294 | gen_rtx_fmt_ee (NE, VOIDmode, p6, | |
3295 | const0_rtx), | |
3296 | gen_rtx_TRAP_IF (VOIDmode, const1_rtx, | |
3297 | GEN_INT (11)))); | |
3298 | } | |
3299 | ||
3300 | /* Probe the Backing Store if necessary. */ | |
3301 | if (bs_size > 0) | |
3302 | emit_stack_probe (r3); | |
3303 | ||
3304 | /* Probe the memory stack if necessary. */ | |
3305 | if (size == 0) | |
3306 | ; | |
3307 | ||
3308 | /* See if we have a constant small number of probes to generate. If so, | |
3309 | that's the easy case. */ | |
3310 | else if (size <= PROBE_INTERVAL) | |
3311 | emit_stack_probe (r2); | |
3312 | ||
3313 | /* The run-time loop is made up of 8 insns in the generic case while this | |
3314 | compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */ | |
3315 | else if (size <= 4 * PROBE_INTERVAL) | |
3316 | { | |
3317 | HOST_WIDE_INT i; | |
3318 | ||
3319 | emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL))); | |
3320 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3321 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3322 | emit_stack_probe (r2); | |
3323 | ||
3324 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until | |
3325 | it exceeds SIZE. If only two probes are needed, this will not | |
3326 | generate any code. Then probe at FIRST + SIZE. */ | |
3327 | for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
3328 | { | |
3329 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3330 | plus_constant (Pmode, r2, -PROBE_INTERVAL))); |
7b84aac0 EB |
3331 | emit_stack_probe (r2); |
3332 | } | |
3333 | ||
3334 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3335 | plus_constant (Pmode, r2, |
7b84aac0 EB |
3336 | (i - PROBE_INTERVAL) - size))); |
3337 | emit_stack_probe (r2); | |
3338 | } | |
3339 | ||
3340 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
3341 | extra careful with variables wrapping around because we might be at | |
3342 | the very top (or the very bottom) of the address space and we have | |
3343 | to be able to handle this case properly; in particular, we use an | |
3344 | equality test for the loop condition. */ | |
3345 | else | |
3346 | { | |
3347 | HOST_WIDE_INT rounded_size; | |
3348 | ||
3349 | emit_move_insn (r2, GEN_INT (-first)); | |
3350 | ||
3351 | ||
3352 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
3353 | ||
3354 | rounded_size = size & -PROBE_INTERVAL; | |
3355 | ||
3356 | ||
3357 | /* Step 2: compute initial and final value of the loop counter. */ | |
3358 | ||
3359 | /* TEST_ADDR = SP + FIRST. */ | |
3360 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3361 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3362 | ||
3363 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
3364 | if (rounded_size > (1 << 21)) | |
3365 | { | |
3366 | emit_move_insn (r3, GEN_INT (-rounded_size)); | |
3367 | emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3))); | |
3368 | } | |
3369 | else | |
3370 | emit_insn (gen_rtx_SET (VOIDmode, r3, | |
3371 | gen_rtx_PLUS (Pmode, r2, | |
3372 | GEN_INT (-rounded_size)))); | |
3373 | ||
3374 | ||
3375 | /* Step 3: the loop | |
3376 | ||
3377 | while (TEST_ADDR != LAST_ADDR) | |
3378 | { | |
3379 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
3380 | probe at TEST_ADDR | |
3381 | } | |
3382 | ||
3383 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
3384 | until it is equal to ROUNDED_SIZE. */ | |
3385 | ||
3386 | emit_insn (gen_probe_stack_range (r2, r2, r3)); | |
3387 | ||
3388 | ||
3389 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
3390 | that SIZE is equal to ROUNDED_SIZE. */ | |
3391 | ||
3392 | /* TEMP = SIZE - ROUNDED_SIZE. */ | |
3393 | if (size != rounded_size) | |
3394 | { | |
3395 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 TG |
3396 | plus_constant (Pmode, r2, |
3397 | rounded_size - size))); | |
7b84aac0 EB |
3398 | emit_stack_probe (r2); |
3399 | } | |
3400 | } | |
3401 | ||
3402 | /* Make sure nothing is scheduled before we are done. */ | |
3403 | emit_insn (gen_blockage ()); | |
3404 | } | |
3405 | ||
3406 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
3407 | absolute addresses. */ | |
3408 | ||
3409 | const char * | |
3410 | output_probe_stack_range (rtx reg1, rtx reg2) | |
3411 | { | |
3412 | static int labelno = 0; | |
3413 | char loop_lab[32], end_lab[32]; | |
3414 | rtx xops[3]; | |
3415 | ||
3416 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno); | |
3417 | ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++); | |
3418 | ||
3419 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
3420 | ||
3421 | /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */ | |
3422 | xops[0] = reg1; | |
3423 | xops[1] = reg2; | |
3424 | xops[2] = gen_rtx_REG (BImode, PR_REG (6)); | |
3425 | output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops); | |
3426 | fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]); | |
3427 | assemble_name_raw (asm_out_file, end_lab); | |
3428 | fputc ('\n', asm_out_file); | |
3429 | ||
3430 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ | |
3431 | xops[1] = GEN_INT (-PROBE_INTERVAL); | |
3432 | output_asm_insn ("addl %0 = %1, %0", xops); | |
3433 | fputs ("\t;;\n", asm_out_file); | |
3434 | ||
3435 | /* Probe at TEST_ADDR and branch. */ | |
3436 | output_asm_insn ("probe.w.fault %0, 0", xops); | |
3437 | fprintf (asm_out_file, "\tbr "); | |
3438 | assemble_name_raw (asm_out_file, loop_lab); | |
3439 | fputc ('\n', asm_out_file); | |
3440 | ||
3441 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab); | |
3442 | ||
3443 | return ""; | |
3444 | } | |
3445 | ||
c65ebc55 JW |
3446 | /* Called after register allocation to add any instructions needed for the |
3447 | prologue. Using a prologue insn is favored compared to putting all of the | |
08c148a8 | 3448 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3449 | to intermix instructions with the saves of the caller saved registers. In |
3450 | some cases, it might be necessary to emit a barrier instruction as the last | |
3451 | insn to prevent such scheduling. | |
3452 | ||
3453 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
97e242b0 RH |
3454 | so that the debug info generation code can handle them properly. |
3455 | ||
073a8998 | 3456 | The register save area is laid out like so: |
97e242b0 RH |
3457 | cfa+16 |
3458 | [ varargs spill area ] | |
3459 | [ fr register spill area ] | |
3460 | [ br register spill area ] | |
3461 | [ ar register spill area ] | |
3462 | [ pr register spill area ] | |
3463 | [ gr register spill area ] */ | |
c65ebc55 JW |
3464 | |
3465 | /* ??? Get inefficient code when the frame size is larger than can fit in an | |
3466 | adds instruction. */ | |
3467 | ||
c65ebc55 | 3468 | void |
9c808aad | 3469 | ia64_expand_prologue (void) |
c65ebc55 | 3470 | { |
97e242b0 RH |
3471 | rtx insn, ar_pfs_save_reg, ar_unat_save_reg; |
3472 | int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs; | |
3473 | rtx reg, alt_reg; | |
3474 | ||
3475 | ia64_compute_frame_size (get_frame_size ()); | |
3476 | last_scratch_gr_reg = 15; | |
3477 | ||
a11e0df4 | 3478 | if (flag_stack_usage_info) |
d3c12306 EB |
3479 | current_function_static_stack_size = current_frame_info.total_size; |
3480 | ||
7b84aac0 EB |
3481 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
3482 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
3483 | current_frame_info.total_size, | |
3484 | current_frame_info.n_input_regs | |
3485 | + current_frame_info.n_local_regs); | |
3486 | ||
6fb5fa3c DB |
3487 | if (dump_file) |
3488 | { | |
3489 | fprintf (dump_file, "ia64 frame related registers " | |
3490 | "recorded in current_frame_info.r[]:\n"); | |
3491 | #define PRINTREG(a) if (current_frame_info.r[a]) \ | |
3492 | fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a]) | |
3493 | PRINTREG(reg_fp); | |
3494 | PRINTREG(reg_save_b0); | |
3495 | PRINTREG(reg_save_pr); | |
3496 | PRINTREG(reg_save_ar_pfs); | |
3497 | PRINTREG(reg_save_ar_unat); | |
3498 | PRINTREG(reg_save_ar_lc); | |
3499 | PRINTREG(reg_save_gp); | |
3500 | #undef PRINTREG | |
3501 | } | |
3502 | ||
97e242b0 RH |
3503 | /* If there is no epilogue, then we don't need some prologue insns. |
3504 | We need to avoid emitting the dead prologue insns, because flow | |
3505 | will complain about them. */ | |
c65ebc55 JW |
3506 | if (optimize) |
3507 | { | |
97e242b0 | 3508 | edge e; |
9924d7d8 | 3509 | edge_iterator ei; |
97e242b0 | 3510 | |
628f6a4e | 3511 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) |
c65ebc55 JW |
3512 | if ((e->flags & EDGE_FAKE) == 0 |
3513 | && (e->flags & EDGE_FALLTHRU) != 0) | |
3514 | break; | |
3515 | epilogue_p = (e != NULL); | |
3516 | } | |
3517 | else | |
3518 | epilogue_p = 1; | |
3519 | ||
97e242b0 RH |
3520 | /* Set the local, input, and output register names. We need to do this |
3521 | for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in | |
3522 | half. If we use in/loc/out register names, then we get assembler errors | |
3523 | in crtn.S because there is no alloc insn or regstk directive in there. */ | |
3524 | if (! TARGET_REG_NAMES) | |
3525 | { | |
3526 | int inputs = current_frame_info.n_input_regs; | |
3527 | int locals = current_frame_info.n_local_regs; | |
3528 | int outputs = current_frame_info.n_output_regs; | |
3529 | ||
3530 | for (i = 0; i < inputs; i++) | |
3531 | reg_names[IN_REG (i)] = ia64_reg_numbers[i]; | |
3532 | for (i = 0; i < locals; i++) | |
3533 | reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i]; | |
3534 | for (i = 0; i < outputs; i++) | |
3535 | reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i]; | |
3536 | } | |
c65ebc55 | 3537 | |
97e242b0 RH |
3538 | /* Set the frame pointer register name. The regnum is logically loc79, |
3539 | but of course we'll not have allocated that many locals. Rather than | |
3540 | worrying about renumbering the existing rtxs, we adjust the name. */ | |
9502c558 JW |
3541 | /* ??? This code means that we can never use one local register when |
3542 | there is a frame pointer. loc79 gets wasted in this case, as it is | |
3543 | renamed to a register that will never be used. See also the try_locals | |
3544 | code in find_gr_spill. */ | |
6fb5fa3c | 3545 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
3546 | { |
3547 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
3548 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
3549 | = reg_names[current_frame_info.r[reg_fp]]; |
3550 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
97e242b0 | 3551 | } |
c65ebc55 | 3552 | |
97e242b0 RH |
3553 | /* We don't need an alloc instruction if we've used no outputs or locals. */ |
3554 | if (current_frame_info.n_local_regs == 0 | |
2ed4af6f | 3555 | && current_frame_info.n_output_regs == 0 |
38173d38 | 3556 | && current_frame_info.n_input_regs <= crtl->args.info.int_regs |
f5bdba44 | 3557 | && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
97e242b0 RH |
3558 | { |
3559 | /* If there is no alloc, but there are input registers used, then we | |
3560 | need a .regstk directive. */ | |
3561 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
3562 | ar_pfs_save_reg = NULL_RTX; | |
3563 | } | |
3564 | else | |
3565 | { | |
3566 | current_frame_info.need_regstk = 0; | |
c65ebc55 | 3567 | |
6fb5fa3c DB |
3568 | if (current_frame_info.r[reg_save_ar_pfs]) |
3569 | { | |
3570 | regno = current_frame_info.r[reg_save_ar_pfs]; | |
3571 | reg_emitted (reg_save_ar_pfs); | |
3572 | } | |
97e242b0 RH |
3573 | else |
3574 | regno = next_scratch_gr_reg (); | |
3575 | ar_pfs_save_reg = gen_rtx_REG (DImode, regno); | |
3576 | ||
9c808aad | 3577 | insn = emit_insn (gen_alloc (ar_pfs_save_reg, |
97e242b0 RH |
3578 | GEN_INT (current_frame_info.n_input_regs), |
3579 | GEN_INT (current_frame_info.n_local_regs), | |
3580 | GEN_INT (current_frame_info.n_output_regs), | |
3581 | GEN_INT (current_frame_info.n_rotate_regs))); | |
9f2ff8e5 RH |
3582 | if (current_frame_info.r[reg_save_ar_pfs]) |
3583 | { | |
3584 | RTX_FRAME_RELATED_P (insn) = 1; | |
3585 | add_reg_note (insn, REG_CFA_REGISTER, | |
3586 | gen_rtx_SET (VOIDmode, | |
3587 | ar_pfs_save_reg, | |
3588 | gen_rtx_REG (DImode, AR_PFS_REGNUM))); | |
3589 | } | |
97e242b0 | 3590 | } |
c65ebc55 | 3591 | |
97e242b0 | 3592 | /* Set up frame pointer, stack pointer, and spill iterators. */ |
c65ebc55 | 3593 | |
26a110f5 | 3594 | n_varargs = cfun->machine->n_varargs; |
97e242b0 RH |
3595 | setup_spill_pointers (current_frame_info.n_spilled + n_varargs, |
3596 | stack_pointer_rtx, 0); | |
c65ebc55 | 3597 | |
97e242b0 RH |
3598 | if (frame_pointer_needed) |
3599 | { | |
3600 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
3601 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3602 | |
3603 | /* Force the unwind info to recognize this as defining a new CFA, | |
3604 | rather than some temp register setup. */ | |
3605 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX); | |
97e242b0 | 3606 | } |
c65ebc55 | 3607 | |
97e242b0 RH |
3608 | if (current_frame_info.total_size != 0) |
3609 | { | |
3610 | rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size); | |
3611 | rtx offset; | |
c65ebc55 | 3612 | |
13f70342 | 3613 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
3614 | offset = frame_size_rtx; |
3615 | else | |
3616 | { | |
3617 | regno = next_scratch_gr_reg (); | |
9c808aad | 3618 | offset = gen_rtx_REG (DImode, regno); |
97e242b0 RH |
3619 | emit_move_insn (offset, frame_size_rtx); |
3620 | } | |
c65ebc55 | 3621 | |
97e242b0 RH |
3622 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, |
3623 | stack_pointer_rtx, offset)); | |
c65ebc55 | 3624 | |
97e242b0 RH |
3625 | if (! frame_pointer_needed) |
3626 | { | |
3627 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3628 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
3629 | gen_rtx_SET (VOIDmode, | |
3630 | stack_pointer_rtx, | |
3631 | gen_rtx_PLUS (DImode, | |
3632 | stack_pointer_rtx, | |
3633 | frame_size_rtx))); | |
97e242b0 | 3634 | } |
c65ebc55 | 3635 | |
97e242b0 RH |
3636 | /* ??? At this point we must generate a magic insn that appears to |
3637 | modify the stack pointer, the frame pointer, and all spill | |
3638 | iterators. This would allow the most scheduling freedom. For | |
3639 | now, just hard stop. */ | |
3640 | emit_insn (gen_blockage ()); | |
3641 | } | |
c65ebc55 | 3642 | |
97e242b0 RH |
3643 | /* Must copy out ar.unat before doing any integer spills. */ |
3644 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
c65ebc55 | 3645 | { |
6fb5fa3c DB |
3646 | if (current_frame_info.r[reg_save_ar_unat]) |
3647 | { | |
3648 | ar_unat_save_reg | |
3649 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3650 | reg_emitted (reg_save_ar_unat); | |
3651 | } | |
97e242b0 | 3652 | else |
c65ebc55 | 3653 | { |
97e242b0 RH |
3654 | alt_regno = next_scratch_gr_reg (); |
3655 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3656 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
c65ebc55 | 3657 | } |
c65ebc55 | 3658 | |
97e242b0 RH |
3659 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
3660 | insn = emit_move_insn (ar_unat_save_reg, reg); | |
5c255b57 RH |
3661 | if (current_frame_info.r[reg_save_ar_unat]) |
3662 | { | |
3663 | RTX_FRAME_RELATED_P (insn) = 1; | |
3664 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); | |
3665 | } | |
97e242b0 RH |
3666 | |
3667 | /* Even if we're not going to generate an epilogue, we still | |
3668 | need to save the register so that EH works. */ | |
6fb5fa3c | 3669 | if (! epilogue_p && current_frame_info.r[reg_save_ar_unat]) |
d0e82870 | 3670 | emit_insn (gen_prologue_use (ar_unat_save_reg)); |
c65ebc55 JW |
3671 | } |
3672 | else | |
97e242b0 RH |
3673 | ar_unat_save_reg = NULL_RTX; |
3674 | ||
3675 | /* Spill all varargs registers. Do this before spilling any GR registers, | |
3676 | since we want the UNAT bits for the GR registers to override the UNAT | |
3677 | bits from varargs, which we don't care about. */ | |
c65ebc55 | 3678 | |
97e242b0 RH |
3679 | cfa_off = -16; |
3680 | for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno) | |
c65ebc55 | 3681 | { |
97e242b0 | 3682 | reg = gen_rtx_REG (DImode, regno); |
870f9ec0 | 3683 | do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX); |
c65ebc55 | 3684 | } |
c65ebc55 | 3685 | |
97e242b0 RH |
3686 | /* Locate the bottom of the register save area. */ |
3687 | cfa_off = (current_frame_info.spill_cfa_off | |
3688 | + current_frame_info.spill_size | |
3689 | + current_frame_info.extra_spill_size); | |
c65ebc55 | 3690 | |
97e242b0 RH |
3691 | /* Save the predicate register block either in a register or in memory. */ |
3692 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3693 | { | |
3694 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
6fb5fa3c | 3695 | if (current_frame_info.r[reg_save_pr] != 0) |
1ff5b671 | 3696 | { |
6fb5fa3c DB |
3697 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); |
3698 | reg_emitted (reg_save_pr); | |
97e242b0 | 3699 | insn = emit_move_insn (alt_reg, reg); |
1ff5b671 | 3700 | |
97e242b0 RH |
3701 | /* ??? Denote pr spill/fill by a DImode move that modifies all |
3702 | 64 hard registers. */ | |
1ff5b671 | 3703 | RTX_FRAME_RELATED_P (insn) = 1; |
5c255b57 | 3704 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
46327bc5 | 3705 | |
97e242b0 RH |
3706 | /* Even if we're not going to generate an epilogue, we still |
3707 | need to save the register so that EH works. */ | |
3708 | if (! epilogue_p) | |
d0e82870 | 3709 | emit_insn (gen_prologue_use (alt_reg)); |
1ff5b671 JW |
3710 | } |
3711 | else | |
97e242b0 RH |
3712 | { |
3713 | alt_regno = next_scratch_gr_reg (); | |
3714 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3715 | insn = emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3716 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3717 | cfa_off -= 8; |
3718 | } | |
c65ebc55 JW |
3719 | } |
3720 | ||
97e242b0 RH |
3721 | /* Handle AR regs in numerical order. All of them get special handling. */ |
3722 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM) | |
6fb5fa3c | 3723 | && current_frame_info.r[reg_save_ar_unat] == 0) |
c65ebc55 | 3724 | { |
97e242b0 | 3725 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
870f9ec0 | 3726 | do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg); |
97e242b0 | 3727 | cfa_off -= 8; |
c65ebc55 | 3728 | } |
97e242b0 RH |
3729 | |
3730 | /* The alloc insn already copied ar.pfs into a general register. The | |
3731 | only thing we have to do now is copy that register to a stack slot | |
3732 | if we'd not allocated a local register for the job. */ | |
f5bdba44 | 3733 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM) |
6fb5fa3c | 3734 | && current_frame_info.r[reg_save_ar_pfs] == 0) |
c65ebc55 | 3735 | { |
97e242b0 | 3736 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
870f9ec0 | 3737 | do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg); |
97e242b0 RH |
3738 | cfa_off -= 8; |
3739 | } | |
3740 | ||
3741 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3742 | { | |
3743 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
6fb5fa3c | 3744 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
97e242b0 | 3745 | { |
6fb5fa3c DB |
3746 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); |
3747 | reg_emitted (reg_save_ar_lc); | |
97e242b0 RH |
3748 | insn = emit_move_insn (alt_reg, reg); |
3749 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 3750 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
97e242b0 RH |
3751 | |
3752 | /* Even if we're not going to generate an epilogue, we still | |
3753 | need to save the register so that EH works. */ | |
3754 | if (! epilogue_p) | |
d0e82870 | 3755 | emit_insn (gen_prologue_use (alt_reg)); |
97e242b0 | 3756 | } |
c65ebc55 JW |
3757 | else |
3758 | { | |
97e242b0 RH |
3759 | alt_regno = next_scratch_gr_reg (); |
3760 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3761 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3762 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3763 | cfa_off -= 8; |
3764 | } | |
3765 | } | |
3766 | ||
ae1e2d4c AS |
3767 | /* Save the return pointer. */ |
3768 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3769 | { | |
3770 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
6fb5fa3c | 3771 | if (current_frame_info.r[reg_save_b0] != 0) |
ae1e2d4c | 3772 | { |
6fb5fa3c DB |
3773 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); |
3774 | reg_emitted (reg_save_b0); | |
ae1e2d4c AS |
3775 | insn = emit_move_insn (alt_reg, reg); |
3776 | RTX_FRAME_RELATED_P (insn) = 1; | |
5f740973 RH |
3777 | add_reg_note (insn, REG_CFA_REGISTER, |
3778 | gen_rtx_SET (VOIDmode, alt_reg, pc_rtx)); | |
ae1e2d4c AS |
3779 | |
3780 | /* Even if we're not going to generate an epilogue, we still | |
3781 | need to save the register so that EH works. */ | |
3782 | if (! epilogue_p) | |
3783 | emit_insn (gen_prologue_use (alt_reg)); | |
3784 | } | |
3785 | else | |
3786 | { | |
3787 | alt_regno = next_scratch_gr_reg (); | |
3788 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3789 | emit_move_insn (alt_reg, reg); | |
3790 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); | |
3791 | cfa_off -= 8; | |
3792 | } | |
3793 | } | |
3794 | ||
6fb5fa3c | 3795 | if (current_frame_info.r[reg_save_gp]) |
599aedd9 | 3796 | { |
6fb5fa3c | 3797 | reg_emitted (reg_save_gp); |
599aedd9 | 3798 | insn = emit_move_insn (gen_rtx_REG (DImode, |
6fb5fa3c | 3799 | current_frame_info.r[reg_save_gp]), |
599aedd9 | 3800 | pic_offset_table_rtx); |
599aedd9 RH |
3801 | } |
3802 | ||
97e242b0 | 3803 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3804 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3805 | + current_frame_info.spill_size)); | |
97e242b0 RH |
3806 | |
3807 | /* Spill all general registers. */ | |
3808 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
3809 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3810 | { | |
3811 | reg = gen_rtx_REG (DImode, regno); | |
3812 | do_spill (gen_gr_spill, reg, cfa_off, reg); | |
3813 | cfa_off -= 8; | |
3814 | } | |
3815 | ||
97e242b0 RH |
3816 | /* Spill the rest of the BR registers. */ |
3817 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) | |
3818 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3819 | { | |
3820 | alt_regno = next_scratch_gr_reg (); | |
3821 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3822 | reg = gen_rtx_REG (DImode, regno); | |
3823 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3824 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3825 | cfa_off -= 8; |
3826 | } | |
3827 | ||
3828 | /* Align the frame and spill all FR registers. */ | |
3829 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
3830 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3831 | { | |
e820471b | 3832 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 3833 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 3834 | do_spill (gen_fr_spill_x, reg, cfa_off, reg); |
97e242b0 RH |
3835 | cfa_off -= 16; |
3836 | } | |
3837 | ||
e820471b | 3838 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
3839 | |
3840 | finish_spill_pointers (); | |
c65ebc55 JW |
3841 | } |
3842 | ||
8e7745dc DR |
3843 | /* Output the textual info surrounding the prologue. */ |
3844 | ||
3845 | void | |
3846 | ia64_start_function (FILE *file, const char *fnname, | |
3847 | tree decl ATTRIBUTE_UNUSED) | |
3848 | { | |
4b12e93d TG |
3849 | #if TARGET_ABI_OPEN_VMS |
3850 | vms_start_function (fnname); | |
8e7745dc DR |
3851 | #endif |
3852 | ||
3853 | fputs ("\t.proc ", file); | |
3854 | assemble_name (file, fnname); | |
3855 | fputc ('\n', file); | |
3856 | ASM_OUTPUT_LABEL (file, fnname); | |
3857 | } | |
3858 | ||
c65ebc55 | 3859 | /* Called after register allocation to add any instructions needed for the |
5519a4f9 | 3860 | epilogue. Using an epilogue insn is favored compared to putting all of the |
08c148a8 | 3861 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3862 | to intermix instructions with the saves of the caller saved registers. In |
3863 | some cases, it might be necessary to emit a barrier instruction as the last | |
3864 | insn to prevent such scheduling. */ | |
3865 | ||
3866 | void | |
9c808aad | 3867 | ia64_expand_epilogue (int sibcall_p) |
c65ebc55 | 3868 | { |
97e242b0 RH |
3869 | rtx insn, reg, alt_reg, ar_unat_save_reg; |
3870 | int regno, alt_regno, cfa_off; | |
3871 | ||
3872 | ia64_compute_frame_size (get_frame_size ()); | |
3873 | ||
3874 | /* If there is a frame pointer, then we use it instead of the stack | |
3875 | pointer, so that the stack pointer does not need to be valid when | |
3876 | the epilogue starts. See EXIT_IGNORE_STACK. */ | |
3877 | if (frame_pointer_needed) | |
3878 | setup_spill_pointers (current_frame_info.n_spilled, | |
3879 | hard_frame_pointer_rtx, 0); | |
3880 | else | |
9c808aad | 3881 | setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx, |
97e242b0 RH |
3882 | current_frame_info.total_size); |
3883 | ||
3884 | if (current_frame_info.total_size != 0) | |
3885 | { | |
3886 | /* ??? At this point we must generate a magic insn that appears to | |
3887 | modify the spill iterators and the frame pointer. This would | |
3888 | allow the most scheduling freedom. For now, just hard stop. */ | |
3889 | emit_insn (gen_blockage ()); | |
3890 | } | |
3891 | ||
3892 | /* Locate the bottom of the register save area. */ | |
3893 | cfa_off = (current_frame_info.spill_cfa_off | |
3894 | + current_frame_info.spill_size | |
3895 | + current_frame_info.extra_spill_size); | |
3896 | ||
3897 | /* Restore the predicate registers. */ | |
3898 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3899 | { | |
6fb5fa3c DB |
3900 | if (current_frame_info.r[reg_save_pr] != 0) |
3901 | { | |
3902 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); | |
3903 | reg_emitted (reg_save_pr); | |
3904 | } | |
97e242b0 RH |
3905 | else |
3906 | { | |
3907 | alt_regno = next_scratch_gr_reg (); | |
3908 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3909 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3910 | cfa_off -= 8; |
3911 | } | |
3912 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
3913 | emit_move_insn (reg, alt_reg); | |
3914 | } | |
3915 | ||
3916 | /* Restore the application registers. */ | |
3917 | ||
3918 | /* Load the saved unat from the stack, but do not restore it until | |
3919 | after the GRs have been restored. */ | |
3920 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
3921 | { | |
6fb5fa3c DB |
3922 | if (current_frame_info.r[reg_save_ar_unat] != 0) |
3923 | { | |
3924 | ar_unat_save_reg | |
3925 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3926 | reg_emitted (reg_save_ar_unat); | |
3927 | } | |
97e242b0 RH |
3928 | else |
3929 | { | |
3930 | alt_regno = next_scratch_gr_reg (); | |
3931 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3932 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
870f9ec0 | 3933 | do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off); |
97e242b0 RH |
3934 | cfa_off -= 8; |
3935 | } | |
3936 | } | |
3937 | else | |
3938 | ar_unat_save_reg = NULL_RTX; | |
9c808aad | 3939 | |
6fb5fa3c | 3940 | if (current_frame_info.r[reg_save_ar_pfs] != 0) |
97e242b0 | 3941 | { |
6fb5fa3c DB |
3942 | reg_emitted (reg_save_ar_pfs); |
3943 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]); | |
97e242b0 RH |
3944 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
3945 | emit_move_insn (reg, alt_reg); | |
3946 | } | |
4e14f1f9 | 3947 | else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
c65ebc55 | 3948 | { |
97e242b0 RH |
3949 | alt_regno = next_scratch_gr_reg (); |
3950 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3951 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3952 | cfa_off -= 8; |
3953 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); | |
3954 | emit_move_insn (reg, alt_reg); | |
3955 | } | |
3956 | ||
3957 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3958 | { | |
6fb5fa3c DB |
3959 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
3960 | { | |
3961 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); | |
3962 | reg_emitted (reg_save_ar_lc); | |
3963 | } | |
97e242b0 RH |
3964 | else |
3965 | { | |
3966 | alt_regno = next_scratch_gr_reg (); | |
3967 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3968 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3969 | cfa_off -= 8; |
3970 | } | |
3971 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
3972 | emit_move_insn (reg, alt_reg); | |
3973 | } | |
3974 | ||
ae1e2d4c AS |
3975 | /* Restore the return pointer. */ |
3976 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3977 | { | |
6fb5fa3c DB |
3978 | if (current_frame_info.r[reg_save_b0] != 0) |
3979 | { | |
3980 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
3981 | reg_emitted (reg_save_b0); | |
3982 | } | |
ae1e2d4c AS |
3983 | else |
3984 | { | |
3985 | alt_regno = next_scratch_gr_reg (); | |
3986 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3987 | do_restore (gen_movdi_x, alt_reg, cfa_off); | |
3988 | cfa_off -= 8; | |
3989 | } | |
3990 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
3991 | emit_move_insn (reg, alt_reg); | |
3992 | } | |
3993 | ||
97e242b0 | 3994 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3995 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3996 | + current_frame_info.spill_size)); | |
97e242b0 | 3997 | |
599aedd9 RH |
3998 | /* The GP may be stored on the stack in the prologue, but it's |
3999 | never restored in the epilogue. Skip the stack slot. */ | |
4000 | if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1))) | |
4001 | cfa_off -= 8; | |
4002 | ||
97e242b0 | 4003 | /* Restore all general registers. */ |
599aedd9 | 4004 | for (regno = GR_REG (2); regno <= GR_REG (31); ++regno) |
97e242b0 | 4005 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) |
0c96007e | 4006 | { |
97e242b0 RH |
4007 | reg = gen_rtx_REG (DImode, regno); |
4008 | do_restore (gen_gr_restore, reg, cfa_off); | |
4009 | cfa_off -= 8; | |
0c96007e | 4010 | } |
9c808aad | 4011 | |
ae1e2d4c | 4012 | /* Restore the branch registers. */ |
97e242b0 RH |
4013 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) |
4014 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
0c96007e | 4015 | { |
97e242b0 RH |
4016 | alt_regno = next_scratch_gr_reg (); |
4017 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4018 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4019 | cfa_off -= 8; |
4020 | reg = gen_rtx_REG (DImode, regno); | |
4021 | emit_move_insn (reg, alt_reg); | |
4022 | } | |
c65ebc55 | 4023 | |
97e242b0 RH |
4024 | /* Restore floating point registers. */ |
4025 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
4026 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4027 | { | |
e820471b | 4028 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 4029 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 4030 | do_restore (gen_fr_restore_x, reg, cfa_off); |
97e242b0 | 4031 | cfa_off -= 16; |
0c96007e | 4032 | } |
97e242b0 RH |
4033 | |
4034 | /* Restore ar.unat for real. */ | |
4035 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
4036 | { | |
4037 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); | |
4038 | emit_move_insn (reg, ar_unat_save_reg); | |
c65ebc55 JW |
4039 | } |
4040 | ||
e820471b | 4041 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
4042 | |
4043 | finish_spill_pointers (); | |
c65ebc55 | 4044 | |
c93646bd JJ |
4045 | if (current_frame_info.total_size |
4046 | || cfun->machine->ia64_eh_epilogue_sp | |
4047 | || frame_pointer_needed) | |
97e242b0 RH |
4048 | { |
4049 | /* ??? At this point we must generate a magic insn that appears to | |
4050 | modify the spill iterators, the stack pointer, and the frame | |
4051 | pointer. This would allow the most scheduling freedom. For now, | |
4052 | just hard stop. */ | |
4053 | emit_insn (gen_blockage ()); | |
4054 | } | |
c65ebc55 | 4055 | |
97e242b0 RH |
4056 | if (cfun->machine->ia64_eh_epilogue_sp) |
4057 | emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp); | |
4058 | else if (frame_pointer_needed) | |
4059 | { | |
4060 | insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
4061 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 4062 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL); |
97e242b0 RH |
4063 | } |
4064 | else if (current_frame_info.total_size) | |
0c96007e | 4065 | { |
97e242b0 RH |
4066 | rtx offset, frame_size_rtx; |
4067 | ||
4068 | frame_size_rtx = GEN_INT (current_frame_info.total_size); | |
13f70342 | 4069 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
4070 | offset = frame_size_rtx; |
4071 | else | |
4072 | { | |
4073 | regno = next_scratch_gr_reg (); | |
4074 | offset = gen_rtx_REG (DImode, regno); | |
4075 | emit_move_insn (offset, frame_size_rtx); | |
4076 | } | |
4077 | ||
4078 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
4079 | offset)); | |
4080 | ||
4081 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
4082 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
4083 | gen_rtx_SET (VOIDmode, | |
4084 | stack_pointer_rtx, | |
4085 | gen_rtx_PLUS (DImode, | |
4086 | stack_pointer_rtx, | |
4087 | frame_size_rtx))); | |
0c96007e | 4088 | } |
97e242b0 RH |
4089 | |
4090 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
4091 | emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp)); | |
9c808aad | 4092 | |
2ed4af6f RH |
4093 | if (! sibcall_p) |
4094 | emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0)))); | |
25250265 | 4095 | else |
8206fc89 AM |
4096 | { |
4097 | int fp = GR_REG (2); | |
5c255b57 RH |
4098 | /* We need a throw away register here, r0 and r1 are reserved, |
4099 | so r2 is the first available call clobbered register. If | |
4100 | there was a frame_pointer register, we may have swapped the | |
4101 | names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make | |
4102 | sure we're using the string "r2" when emitting the register | |
4103 | name for the assembler. */ | |
6fb5fa3c DB |
4104 | if (current_frame_info.r[reg_fp] |
4105 | && current_frame_info.r[reg_fp] == GR_REG (2)) | |
8206fc89 AM |
4106 | fp = HARD_FRAME_POINTER_REGNUM; |
4107 | ||
4108 | /* We must emit an alloc to force the input registers to become output | |
4109 | registers. Otherwise, if the callee tries to pass its parameters | |
4110 | through to another call without an intervening alloc, then these | |
4111 | values get lost. */ | |
4112 | /* ??? We don't need to preserve all input registers. We only need to | |
4113 | preserve those input registers used as arguments to the sibling call. | |
4114 | It is unclear how to compute that number here. */ | |
4115 | if (current_frame_info.n_input_regs != 0) | |
a8f5224e DM |
4116 | { |
4117 | rtx n_inputs = GEN_INT (current_frame_info.n_input_regs); | |
c2b40eba | 4118 | |
a8f5224e DM |
4119 | insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp), |
4120 | const0_rtx, const0_rtx, | |
4121 | n_inputs, const0_rtx)); | |
4122 | RTX_FRAME_RELATED_P (insn) = 1; | |
c2b40eba RH |
4123 | |
4124 | /* ??? We need to mark the alloc as frame-related so that it gets | |
4125 | passed into ia64_asm_unwind_emit for ia64-specific unwinding. | |
4126 | But there's nothing dwarf2 related to be done wrt the register | |
4127 | windows. If we do nothing, dwarf2out will abort on the UNSPEC; | |
4128 | the empty parallel means dwarf2out will not see anything. */ | |
4129 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
4130 | gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0))); | |
a8f5224e | 4131 | } |
8206fc89 | 4132 | } |
c65ebc55 JW |
4133 | } |
4134 | ||
97e242b0 RH |
4135 | /* Return 1 if br.ret can do all the work required to return from a |
4136 | function. */ | |
4137 | ||
4138 | int | |
9c808aad | 4139 | ia64_direct_return (void) |
97e242b0 RH |
4140 | { |
4141 | if (reload_completed && ! frame_pointer_needed) | |
4142 | { | |
4143 | ia64_compute_frame_size (get_frame_size ()); | |
4144 | ||
4145 | return (current_frame_info.total_size == 0 | |
4146 | && current_frame_info.n_spilled == 0 | |
6fb5fa3c DB |
4147 | && current_frame_info.r[reg_save_b0] == 0 |
4148 | && current_frame_info.r[reg_save_pr] == 0 | |
4149 | && current_frame_info.r[reg_save_ar_pfs] == 0 | |
4150 | && current_frame_info.r[reg_save_ar_unat] == 0 | |
4151 | && current_frame_info.r[reg_save_ar_lc] == 0); | |
97e242b0 RH |
4152 | } |
4153 | return 0; | |
4154 | } | |
4155 | ||
af1e5518 RH |
4156 | /* Return the magic cookie that we use to hold the return address |
4157 | during early compilation. */ | |
4158 | ||
4159 | rtx | |
9c808aad | 4160 | ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED) |
af1e5518 RH |
4161 | { |
4162 | if (count != 0) | |
4163 | return NULL; | |
4164 | return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR); | |
4165 | } | |
4166 | ||
4167 | /* Split this value after reload, now that we know where the return | |
4168 | address is saved. */ | |
4169 | ||
4170 | void | |
9c808aad | 4171 | ia64_split_return_addr_rtx (rtx dest) |
af1e5518 RH |
4172 | { |
4173 | rtx src; | |
4174 | ||
4175 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4176 | { | |
6fb5fa3c DB |
4177 | if (current_frame_info.r[reg_save_b0] != 0) |
4178 | { | |
4179 | src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4180 | reg_emitted (reg_save_b0); | |
4181 | } | |
af1e5518 RH |
4182 | else |
4183 | { | |
4184 | HOST_WIDE_INT off; | |
4185 | unsigned int regno; | |
13f70342 | 4186 | rtx off_r; |
af1e5518 RH |
4187 | |
4188 | /* Compute offset from CFA for BR0. */ | |
4189 | /* ??? Must be kept in sync with ia64_expand_prologue. */ | |
4190 | off = (current_frame_info.spill_cfa_off | |
4191 | + current_frame_info.spill_size); | |
4192 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
4193 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4194 | off -= 8; | |
4195 | ||
4196 | /* Convert CFA offset to a register based offset. */ | |
4197 | if (frame_pointer_needed) | |
4198 | src = hard_frame_pointer_rtx; | |
4199 | else | |
4200 | { | |
4201 | src = stack_pointer_rtx; | |
4202 | off += current_frame_info.total_size; | |
4203 | } | |
4204 | ||
4205 | /* Load address into scratch register. */ | |
13f70342 RH |
4206 | off_r = GEN_INT (off); |
4207 | if (satisfies_constraint_I (off_r)) | |
4208 | emit_insn (gen_adddi3 (dest, src, off_r)); | |
af1e5518 RH |
4209 | else |
4210 | { | |
13f70342 | 4211 | emit_move_insn (dest, off_r); |
af1e5518 RH |
4212 | emit_insn (gen_adddi3 (dest, src, dest)); |
4213 | } | |
4214 | ||
4215 | src = gen_rtx_MEM (Pmode, dest); | |
4216 | } | |
4217 | } | |
4218 | else | |
4219 | src = gen_rtx_REG (DImode, BR_REG (0)); | |
4220 | ||
4221 | emit_move_insn (dest, src); | |
4222 | } | |
4223 | ||
10c9f189 | 4224 | int |
9c808aad | 4225 | ia64_hard_regno_rename_ok (int from, int to) |
10c9f189 RH |
4226 | { |
4227 | /* Don't clobber any of the registers we reserved for the prologue. */ | |
09639a83 | 4228 | unsigned int r; |
10c9f189 | 4229 | |
6fb5fa3c DB |
4230 | for (r = reg_fp; r <= reg_save_ar_lc; r++) |
4231 | if (to == current_frame_info.r[r] | |
4232 | || from == current_frame_info.r[r] | |
4233 | || to == emitted_frame_related_regs[r] | |
4234 | || from == emitted_frame_related_regs[r]) | |
4235 | return 0; | |
2130b7fb | 4236 | |
10c9f189 RH |
4237 | /* Don't use output registers outside the register frame. */ |
4238 | if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs)) | |
4239 | return 0; | |
4240 | ||
4241 | /* Retain even/oddness on predicate register pairs. */ | |
4242 | if (PR_REGNO_P (from) && PR_REGNO_P (to)) | |
4243 | return (from & 1) == (to & 1); | |
4244 | ||
4245 | return 1; | |
4246 | } | |
4247 | ||
301d03af RS |
4248 | /* Target hook for assembling integer objects. Handle word-sized |
4249 | aligned objects and detect the cases when @fptr is needed. */ | |
4250 | ||
4251 | static bool | |
9c808aad | 4252 | ia64_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 4253 | { |
b6a41a62 | 4254 | if (size == POINTER_SIZE / BITS_PER_UNIT |
301d03af RS |
4255 | && !(TARGET_NO_PIC || TARGET_AUTO_PIC) |
4256 | && GET_CODE (x) == SYMBOL_REF | |
1cdbd630 | 4257 | && SYMBOL_REF_FUNCTION_P (x)) |
301d03af | 4258 | { |
1b79dc38 DM |
4259 | static const char * const directive[2][2] = { |
4260 | /* 64-bit pointer */ /* 32-bit pointer */ | |
4261 | { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */ | |
4262 | { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */ | |
4263 | }; | |
4264 | fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file); | |
301d03af RS |
4265 | output_addr_const (asm_out_file, x); |
4266 | fputs (")\n", asm_out_file); | |
4267 | return true; | |
4268 | } | |
4269 | return default_assemble_integer (x, size, aligned_p); | |
4270 | } | |
4271 | ||
c65ebc55 JW |
4272 | /* Emit the function prologue. */ |
4273 | ||
08c148a8 | 4274 | static void |
9c808aad | 4275 | ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
c65ebc55 | 4276 | { |
97e242b0 RH |
4277 | int mask, grsave, grsave_prev; |
4278 | ||
4279 | if (current_frame_info.need_regstk) | |
4280 | fprintf (file, "\t.regstk %d, %d, %d, %d\n", | |
4281 | current_frame_info.n_input_regs, | |
4282 | current_frame_info.n_local_regs, | |
4283 | current_frame_info.n_output_regs, | |
4284 | current_frame_info.n_rotate_regs); | |
c65ebc55 | 4285 | |
d5fabb58 | 4286 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0c96007e AM |
4287 | return; |
4288 | ||
97e242b0 | 4289 | /* Emit the .prologue directive. */ |
809d4ef1 | 4290 | |
97e242b0 RH |
4291 | mask = 0; |
4292 | grsave = grsave_prev = 0; | |
6fb5fa3c | 4293 | if (current_frame_info.r[reg_save_b0] != 0) |
0c96007e | 4294 | { |
97e242b0 | 4295 | mask |= 8; |
6fb5fa3c | 4296 | grsave = grsave_prev = current_frame_info.r[reg_save_b0]; |
97e242b0 | 4297 | } |
6fb5fa3c | 4298 | if (current_frame_info.r[reg_save_ar_pfs] != 0 |
97e242b0 | 4299 | && (grsave_prev == 0 |
6fb5fa3c | 4300 | || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1)) |
97e242b0 RH |
4301 | { |
4302 | mask |= 4; | |
4303 | if (grsave_prev == 0) | |
6fb5fa3c DB |
4304 | grsave = current_frame_info.r[reg_save_ar_pfs]; |
4305 | grsave_prev = current_frame_info.r[reg_save_ar_pfs]; | |
0c96007e | 4306 | } |
6fb5fa3c | 4307 | if (current_frame_info.r[reg_fp] != 0 |
97e242b0 | 4308 | && (grsave_prev == 0 |
6fb5fa3c | 4309 | || current_frame_info.r[reg_fp] == grsave_prev + 1)) |
97e242b0 RH |
4310 | { |
4311 | mask |= 2; | |
4312 | if (grsave_prev == 0) | |
4313 | grsave = HARD_FRAME_POINTER_REGNUM; | |
6fb5fa3c | 4314 | grsave_prev = current_frame_info.r[reg_fp]; |
97e242b0 | 4315 | } |
6fb5fa3c | 4316 | if (current_frame_info.r[reg_save_pr] != 0 |
97e242b0 | 4317 | && (grsave_prev == 0 |
6fb5fa3c | 4318 | || current_frame_info.r[reg_save_pr] == grsave_prev + 1)) |
97e242b0 RH |
4319 | { |
4320 | mask |= 1; | |
4321 | if (grsave_prev == 0) | |
6fb5fa3c | 4322 | grsave = current_frame_info.r[reg_save_pr]; |
97e242b0 RH |
4323 | } |
4324 | ||
738e7b39 | 4325 | if (mask && TARGET_GNU_AS) |
97e242b0 RH |
4326 | fprintf (file, "\t.prologue %d, %d\n", mask, |
4327 | ia64_dbx_register_number (grsave)); | |
4328 | else | |
4329 | fputs ("\t.prologue\n", file); | |
4330 | ||
4331 | /* Emit a .spill directive, if necessary, to relocate the base of | |
4332 | the register spill area. */ | |
4333 | if (current_frame_info.spill_cfa_off != -16) | |
4334 | fprintf (file, "\t.spill %ld\n", | |
4335 | (long) (current_frame_info.spill_cfa_off | |
4336 | + current_frame_info.spill_size)); | |
c65ebc55 JW |
4337 | } |
4338 | ||
0186257f JW |
4339 | /* Emit the .body directive at the scheduled end of the prologue. */ |
4340 | ||
b4c25db2 | 4341 | static void |
9c808aad | 4342 | ia64_output_function_end_prologue (FILE *file) |
0186257f | 4343 | { |
d5fabb58 | 4344 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0186257f JW |
4345 | return; |
4346 | ||
4347 | fputs ("\t.body\n", file); | |
4348 | } | |
4349 | ||
c65ebc55 JW |
4350 | /* Emit the function epilogue. */ |
4351 | ||
08c148a8 | 4352 | static void |
9c808aad AJ |
4353 | ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
4354 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
c65ebc55 | 4355 | { |
8a959ea5 RH |
4356 | int i; |
4357 | ||
6fb5fa3c | 4358 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4359 | { |
4360 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
4361 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
4362 | = reg_names[current_frame_info.r[reg_fp]]; |
4363 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
4364 | reg_emitted (reg_fp); | |
97e242b0 RH |
4365 | } |
4366 | if (! TARGET_REG_NAMES) | |
4367 | { | |
97e242b0 RH |
4368 | for (i = 0; i < current_frame_info.n_input_regs; i++) |
4369 | reg_names[IN_REG (i)] = ia64_input_reg_names[i]; | |
4370 | for (i = 0; i < current_frame_info.n_local_regs; i++) | |
4371 | reg_names[LOC_REG (i)] = ia64_local_reg_names[i]; | |
4372 | for (i = 0; i < current_frame_info.n_output_regs; i++) | |
4373 | reg_names[OUT_REG (i)] = ia64_output_reg_names[i]; | |
4374 | } | |
8a959ea5 | 4375 | |
97e242b0 RH |
4376 | current_frame_info.initialized = 0; |
4377 | } | |
c65ebc55 JW |
4378 | |
4379 | int | |
9c808aad | 4380 | ia64_dbx_register_number (int regno) |
c65ebc55 | 4381 | { |
97e242b0 RH |
4382 | /* In ia64_expand_prologue we quite literally renamed the frame pointer |
4383 | from its home at loc79 to something inside the register frame. We | |
4384 | must perform the same renumbering here for the debug info. */ | |
6fb5fa3c | 4385 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4386 | { |
4387 | if (regno == HARD_FRAME_POINTER_REGNUM) | |
6fb5fa3c DB |
4388 | regno = current_frame_info.r[reg_fp]; |
4389 | else if (regno == current_frame_info.r[reg_fp]) | |
97e242b0 RH |
4390 | regno = HARD_FRAME_POINTER_REGNUM; |
4391 | } | |
4392 | ||
4393 | if (IN_REGNO_P (regno)) | |
4394 | return 32 + regno - IN_REG (0); | |
4395 | else if (LOC_REGNO_P (regno)) | |
4396 | return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0); | |
4397 | else if (OUT_REGNO_P (regno)) | |
4398 | return (32 + current_frame_info.n_input_regs | |
4399 | + current_frame_info.n_local_regs + regno - OUT_REG (0)); | |
4400 | else | |
4401 | return regno; | |
c65ebc55 JW |
4402 | } |
4403 | ||
2a1211e5 RH |
4404 | /* Implement TARGET_TRAMPOLINE_INIT. |
4405 | ||
4406 | The trampoline should set the static chain pointer to value placed | |
4407 | into the trampoline and should branch to the specified routine. | |
4408 | To make the normal indirect-subroutine calling convention work, | |
4409 | the trampoline must look like a function descriptor; the first | |
4410 | word being the target address and the second being the target's | |
4411 | global pointer. | |
4412 | ||
4413 | We abuse the concept of a global pointer by arranging for it | |
4414 | to point to the data we need to load. The complete trampoline | |
4415 | has the following form: | |
4416 | ||
4417 | +-------------------+ \ | |
4418 | TRAMP: | __ia64_trampoline | | | |
4419 | +-------------------+ > fake function descriptor | |
4420 | | TRAMP+16 | | | |
4421 | +-------------------+ / | |
4422 | | target descriptor | | |
4423 | +-------------------+ | |
4424 | | static link | | |
4425 | +-------------------+ | |
4426 | */ | |
4427 | ||
4428 | static void | |
4429 | ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
97e242b0 | 4430 | { |
2a1211e5 RH |
4431 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
4432 | rtx addr, addr_reg, tramp, eight = GEN_INT (8); | |
97e242b0 | 4433 | |
738e7b39 RK |
4434 | /* The Intel assembler requires that the global __ia64_trampoline symbol |
4435 | be declared explicitly */ | |
4436 | if (!TARGET_GNU_AS) | |
4437 | { | |
4438 | static bool declared_ia64_trampoline = false; | |
4439 | ||
4440 | if (!declared_ia64_trampoline) | |
4441 | { | |
4442 | declared_ia64_trampoline = true; | |
b6a41a62 RK |
4443 | (*targetm.asm_out.globalize_label) (asm_out_file, |
4444 | "__ia64_trampoline"); | |
738e7b39 RK |
4445 | } |
4446 | } | |
4447 | ||
5e89a381 | 4448 | /* Make sure addresses are Pmode even if we are in ILP32 mode. */ |
2a1211e5 | 4449 | addr = convert_memory_address (Pmode, XEXP (m_tramp, 0)); |
5e89a381 SE |
4450 | fnaddr = convert_memory_address (Pmode, fnaddr); |
4451 | static_chain = convert_memory_address (Pmode, static_chain); | |
4452 | ||
97e242b0 | 4453 | /* Load up our iterator. */ |
2a1211e5 RH |
4454 | addr_reg = copy_to_reg (addr); |
4455 | m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0); | |
97e242b0 RH |
4456 | |
4457 | /* The first two words are the fake descriptor: | |
4458 | __ia64_trampoline, ADDR+16. */ | |
f2972bf8 DR |
4459 | tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"); |
4460 | if (TARGET_ABI_OPEN_VMS) | |
4461 | { | |
4462 | /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity | |
4463 | in the Macro-32 compiler) and changed the semantics of the LTOFF22 | |
4464 | relocation against function symbols to make it identical to the | |
4465 | LTOFF_FPTR22 relocation. Emit the latter directly to stay within | |
4466 | strict ELF and dereference to get the bare code address. */ | |
4467 | rtx reg = gen_reg_rtx (Pmode); | |
4468 | SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION; | |
4469 | emit_move_insn (reg, tramp); | |
4470 | emit_move_insn (reg, gen_rtx_MEM (Pmode, reg)); | |
4471 | tramp = reg; | |
4472 | } | |
2a1211e5 | 4473 | emit_move_insn (m_tramp, tramp); |
97e242b0 | 4474 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4475 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 | 4476 | |
0a81f074 | 4477 | emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16))); |
97e242b0 | 4478 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4479 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4480 | |
4481 | /* The third word is the target descriptor. */ | |
2a1211e5 | 4482 | emit_move_insn (m_tramp, force_reg (Pmode, fnaddr)); |
97e242b0 | 4483 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4484 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4485 | |
4486 | /* The fourth word is the static chain. */ | |
2a1211e5 | 4487 | emit_move_insn (m_tramp, static_chain); |
97e242b0 | 4488 | } |
c65ebc55 JW |
4489 | \f |
4490 | /* Do any needed setup for a variadic function. CUM has not been updated | |
97e242b0 RH |
4491 | for the last named argument which has type TYPE and mode MODE. |
4492 | ||
4493 | We generate the actual spill instructions during prologue generation. */ | |
4494 | ||
351a758b | 4495 | static void |
d5cc9181 | 4496 | ia64_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, |
351a758b | 4497 | tree type, int * pretend_size, |
9c808aad | 4498 | int second_time ATTRIBUTE_UNUSED) |
c65ebc55 | 4499 | { |
d5cc9181 | 4500 | CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum); |
351a758b | 4501 | |
6c535c69 | 4502 | /* Skip the current argument. */ |
d5cc9181 | 4503 | ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1); |
c65ebc55 | 4504 | |
351a758b | 4505 | if (next_cum.words < MAX_ARGUMENT_SLOTS) |
26a110f5 | 4506 | { |
351a758b | 4507 | int n = MAX_ARGUMENT_SLOTS - next_cum.words; |
26a110f5 RH |
4508 | *pretend_size = n * UNITS_PER_WORD; |
4509 | cfun->machine->n_varargs = n; | |
4510 | } | |
c65ebc55 JW |
4511 | } |
4512 | ||
4513 | /* Check whether TYPE is a homogeneous floating point aggregate. If | |
4514 | it is, return the mode of the floating point type that appears | |
4515 | in all leafs. If it is not, return VOIDmode. | |
4516 | ||
4517 | An aggregate is a homogeneous floating point aggregate is if all | |
4518 | fields/elements in it have the same floating point type (e.g, | |
3d6a9acd RH |
4519 | SFmode). 128-bit quad-precision floats are excluded. |
4520 | ||
4521 | Variable sized aggregates should never arrive here, since we should | |
4522 | have already decided to pass them by reference. Top-level zero-sized | |
4523 | aggregates are excluded because our parallels crash the middle-end. */ | |
c65ebc55 JW |
4524 | |
4525 | static enum machine_mode | |
586de218 | 4526 | hfa_element_mode (const_tree type, bool nested) |
c65ebc55 JW |
4527 | { |
4528 | enum machine_mode element_mode = VOIDmode; | |
4529 | enum machine_mode mode; | |
4530 | enum tree_code code = TREE_CODE (type); | |
4531 | int know_element_mode = 0; | |
4532 | tree t; | |
4533 | ||
3d6a9acd RH |
4534 | if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type)))) |
4535 | return VOIDmode; | |
4536 | ||
c65ebc55 JW |
4537 | switch (code) |
4538 | { | |
4539 | case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE: | |
0cc8f5c5 | 4540 | case BOOLEAN_TYPE: case POINTER_TYPE: |
c65ebc55 | 4541 | case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE: |
5662a50d | 4542 | case LANG_TYPE: case FUNCTION_TYPE: |
c65ebc55 JW |
4543 | return VOIDmode; |
4544 | ||
4545 | /* Fortran complex types are supposed to be HFAs, so we need to handle | |
4546 | gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex | |
4547 | types though. */ | |
4548 | case COMPLEX_TYPE: | |
16448fd4 | 4549 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT |
02befdf4 ZW |
4550 | && TYPE_MODE (type) != TCmode) |
4551 | return GET_MODE_INNER (TYPE_MODE (type)); | |
c65ebc55 JW |
4552 | else |
4553 | return VOIDmode; | |
4554 | ||
4555 | case REAL_TYPE: | |
4556 | /* We want to return VOIDmode for raw REAL_TYPEs, but the actual | |
4557 | mode if this is contained within an aggregate. */ | |
02befdf4 | 4558 | if (nested && TYPE_MODE (type) != TFmode) |
c65ebc55 JW |
4559 | return TYPE_MODE (type); |
4560 | else | |
4561 | return VOIDmode; | |
4562 | ||
4563 | case ARRAY_TYPE: | |
46399021 | 4564 | return hfa_element_mode (TREE_TYPE (type), 1); |
c65ebc55 JW |
4565 | |
4566 | case RECORD_TYPE: | |
4567 | case UNION_TYPE: | |
4568 | case QUAL_UNION_TYPE: | |
910ad8de | 4569 | for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t)) |
c65ebc55 JW |
4570 | { |
4571 | if (TREE_CODE (t) != FIELD_DECL) | |
4572 | continue; | |
4573 | ||
4574 | mode = hfa_element_mode (TREE_TYPE (t), 1); | |
4575 | if (know_element_mode) | |
4576 | { | |
4577 | if (mode != element_mode) | |
4578 | return VOIDmode; | |
4579 | } | |
4580 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT) | |
4581 | return VOIDmode; | |
4582 | else | |
4583 | { | |
4584 | know_element_mode = 1; | |
4585 | element_mode = mode; | |
4586 | } | |
4587 | } | |
4588 | return element_mode; | |
4589 | ||
4590 | default: | |
4591 | /* If we reach here, we probably have some front-end specific type | |
4592 | that the backend doesn't know about. This can happen via the | |
4593 | aggregate_value_p call in init_function_start. All we can do is | |
4594 | ignore unknown tree types. */ | |
4595 | return VOIDmode; | |
4596 | } | |
4597 | ||
4598 | return VOIDmode; | |
4599 | } | |
4600 | ||
f57fc998 ZW |
4601 | /* Return the number of words required to hold a quantity of TYPE and MODE |
4602 | when passed as an argument. */ | |
4603 | static int | |
ffa88471 | 4604 | ia64_function_arg_words (const_tree type, enum machine_mode mode) |
f57fc998 ZW |
4605 | { |
4606 | int words; | |
4607 | ||
4608 | if (mode == BLKmode) | |
4609 | words = int_size_in_bytes (type); | |
4610 | else | |
4611 | words = GET_MODE_SIZE (mode); | |
4612 | ||
4613 | return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */ | |
4614 | } | |
4615 | ||
4616 | /* Return the number of registers that should be skipped so the current | |
4617 | argument (described by TYPE and WORDS) will be properly aligned. | |
4618 | ||
4619 | Integer and float arguments larger than 8 bytes start at the next | |
4620 | even boundary. Aggregates larger than 8 bytes start at the next | |
4621 | even boundary if the aggregate has 16 byte alignment. Note that | |
4622 | in the 32-bit ABI, TImode and TFmode have only 8-byte alignment | |
4623 | but are still to be aligned in registers. | |
4624 | ||
4625 | ??? The ABI does not specify how to handle aggregates with | |
4626 | alignment from 9 to 15 bytes, or greater than 16. We handle them | |
4627 | all as if they had 16 byte alignment. Such aggregates can occur | |
4628 | only if gcc extensions are used. */ | |
4629 | static int | |
ffa88471 SE |
4630 | ia64_function_arg_offset (const CUMULATIVE_ARGS *cum, |
4631 | const_tree type, int words) | |
f57fc998 | 4632 | { |
f2972bf8 DR |
4633 | /* No registers are skipped on VMS. */ |
4634 | if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0) | |
f57fc998 ZW |
4635 | return 0; |
4636 | ||
4637 | if (type | |
4638 | && TREE_CODE (type) != INTEGER_TYPE | |
4639 | && TREE_CODE (type) != REAL_TYPE) | |
4640 | return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT; | |
4641 | else | |
4642 | return words > 1; | |
4643 | } | |
4644 | ||
c65ebc55 JW |
4645 | /* Return rtx for register where argument is passed, or zero if it is passed |
4646 | on the stack. */ | |
c65ebc55 JW |
4647 | /* ??? 128-bit quad-precision floats are always passed in general |
4648 | registers. */ | |
4649 | ||
ffa88471 | 4650 | static rtx |
d5cc9181 | 4651 | ia64_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, |
ffa88471 | 4652 | const_tree type, bool named, bool incoming) |
c65ebc55 | 4653 | { |
d5cc9181 JR |
4654 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4655 | ||
c65ebc55 | 4656 | int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST); |
f57fc998 ZW |
4657 | int words = ia64_function_arg_words (type, mode); |
4658 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4659 | enum machine_mode hfa_mode = VOIDmode; |
4660 | ||
f2972bf8 DR |
4661 | /* For OPEN VMS, emit the instruction setting up the argument register here, |
4662 | when we know this will be together with the other arguments setup related | |
4663 | insns. This is not the conceptually best place to do this, but this is | |
4664 | the easiest as we have convenient access to cumulative args info. */ | |
4665 | ||
4666 | if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node | |
4667 | && named == 1) | |
4668 | { | |
4669 | unsigned HOST_WIDE_INT regval = cum->words; | |
4670 | int i; | |
4671 | ||
4672 | for (i = 0; i < 8; i++) | |
4673 | regval |= ((int) cum->atypes[i]) << (i * 3 + 8); | |
4674 | ||
4675 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)), | |
4676 | GEN_INT (regval)); | |
4677 | } | |
4678 | ||
c65ebc55 JW |
4679 | /* If all argument slots are used, then it must go on the stack. */ |
4680 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4681 | return 0; | |
4682 | ||
472b8fdc TG |
4683 | /* On OpenVMS argument is either in Rn or Fn. */ |
4684 | if (TARGET_ABI_OPEN_VMS) | |
4685 | { | |
4686 | if (FLOAT_MODE_P (mode)) | |
4687 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words); | |
4688 | else | |
4689 | return gen_rtx_REG (mode, basereg + cum->words); | |
4690 | } | |
4691 | ||
c65ebc55 JW |
4692 | /* Check for and handle homogeneous FP aggregates. */ |
4693 | if (type) | |
4694 | hfa_mode = hfa_element_mode (type, 0); | |
4695 | ||
4696 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4697 | and unprototyped hfas are passed specially. */ | |
4698 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4699 | { | |
4700 | rtx loc[16]; | |
4701 | int i = 0; | |
4702 | int fp_regs = cum->fp_regs; | |
4703 | int int_regs = cum->words + offset; | |
4704 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4705 | int byte_size; | |
4706 | int args_byte_size; | |
4707 | ||
4708 | /* If prototyped, pass it in FR regs then GR regs. | |
4709 | If not prototyped, pass it in both FR and GR regs. | |
4710 | ||
4711 | If this is an SFmode aggregate, then it is possible to run out of | |
4712 | FR regs while GR regs are still left. In that case, we pass the | |
4713 | remaining part in the GR regs. */ | |
4714 | ||
4715 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4716 | of the argument, the last FP register, or the last argument slot. */ | |
4717 | ||
4718 | byte_size = ((mode == BLKmode) | |
4719 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4720 | args_byte_size = int_regs * UNITS_PER_WORD; | |
4721 | offset = 0; | |
4722 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4723 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++) | |
4724 | { | |
4725 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4726 | gen_rtx_REG (hfa_mode, (FR_ARG_FIRST | |
4727 | + fp_regs)), | |
4728 | GEN_INT (offset)); | |
c65ebc55 JW |
4729 | offset += hfa_size; |
4730 | args_byte_size += hfa_size; | |
4731 | fp_regs++; | |
4732 | } | |
4733 | ||
4734 | /* If no prototype, then the whole thing must go in GR regs. */ | |
4735 | if (! cum->prototype) | |
4736 | offset = 0; | |
4737 | /* If this is an SFmode aggregate, then we might have some left over | |
4738 | that needs to go in GR regs. */ | |
4739 | else if (byte_size != offset) | |
4740 | int_regs += offset / UNITS_PER_WORD; | |
4741 | ||
4742 | /* Fill in the GR regs. We must use DImode here, not the hfa mode. */ | |
4743 | ||
4744 | for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++) | |
4745 | { | |
4746 | enum machine_mode gr_mode = DImode; | |
826b47cc | 4747 | unsigned int gr_size; |
c65ebc55 JW |
4748 | |
4749 | /* If we have an odd 4 byte hunk because we ran out of FR regs, | |
4750 | then this goes in a GR reg left adjusted/little endian, right | |
4751 | adjusted/big endian. */ | |
4752 | /* ??? Currently this is handled wrong, because 4-byte hunks are | |
4753 | always right adjusted/little endian. */ | |
4754 | if (offset & 0x4) | |
4755 | gr_mode = SImode; | |
4756 | /* If we have an even 4 byte hunk because the aggregate is a | |
4757 | multiple of 4 bytes in size, then this goes in a GR reg right | |
4758 | adjusted/little endian. */ | |
4759 | else if (byte_size - offset == 4) | |
4760 | gr_mode = SImode; | |
4761 | ||
4762 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4763 | gen_rtx_REG (gr_mode, (basereg | |
4764 | + int_regs)), | |
4765 | GEN_INT (offset)); | |
826b47cc ZW |
4766 | |
4767 | gr_size = GET_MODE_SIZE (gr_mode); | |
4768 | offset += gr_size; | |
4769 | if (gr_size == UNITS_PER_WORD | |
4770 | || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0)) | |
4771 | int_regs++; | |
4772 | else if (gr_size > UNITS_PER_WORD) | |
4773 | int_regs += gr_size / UNITS_PER_WORD; | |
c65ebc55 | 4774 | } |
9dec91d4 | 4775 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 4776 | } |
f2972bf8 | 4777 | |
c65ebc55 JW |
4778 | /* Integral and aggregates go in general registers. If we have run out of |
4779 | FR registers, then FP values must also go in general registers. This can | |
4780 | happen when we have a SFmode HFA. */ | |
02befdf4 ZW |
4781 | else if (mode == TFmode || mode == TCmode |
4782 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
3870df96 SE |
4783 | { |
4784 | int byte_size = ((mode == BLKmode) | |
4785 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4786 | if (BYTES_BIG_ENDIAN | |
4787 | && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type))) | |
4788 | && byte_size < UNITS_PER_WORD | |
4789 | && byte_size > 0) | |
4790 | { | |
4791 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
4792 | gen_rtx_REG (DImode, | |
4793 | (basereg + cum->words | |
4794 | + offset)), | |
4795 | const0_rtx); | |
4796 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg)); | |
4797 | } | |
4798 | else | |
4799 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
4800 | ||
4801 | } | |
c65ebc55 JW |
4802 | |
4803 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4804 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4805 | else if (cum->prototype) |
4806 | { | |
f9c887ac | 4807 | if (named) |
c65ebc55 | 4808 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs); |
f9c887ac ZW |
4809 | /* In big-endian mode, an anonymous SFmode value must be represented |
4810 | as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force | |
4811 | the value into the high half of the general register. */ | |
4812 | else if (BYTES_BIG_ENDIAN && mode == SFmode) | |
4813 | return gen_rtx_PARALLEL (mode, | |
4814 | gen_rtvec (1, | |
4815 | gen_rtx_EXPR_LIST (VOIDmode, | |
4816 | gen_rtx_REG (DImode, basereg + cum->words + offset), | |
4817 | const0_rtx))); | |
4818 | else | |
4819 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
c65ebc55 JW |
4820 | } |
4821 | /* If there is no prototype, then FP values go in both FR and GR | |
4822 | registers. */ | |
4823 | else | |
4824 | { | |
f9c887ac ZW |
4825 | /* See comment above. */ |
4826 | enum machine_mode inner_mode = | |
4827 | (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode; | |
4828 | ||
c65ebc55 JW |
4829 | rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode, |
4830 | gen_rtx_REG (mode, (FR_ARG_FIRST | |
4831 | + cum->fp_regs)), | |
4832 | const0_rtx); | |
4833 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
f9c887ac | 4834 | gen_rtx_REG (inner_mode, |
c65ebc55 JW |
4835 | (basereg + cum->words |
4836 | + offset)), | |
4837 | const0_rtx); | |
809d4ef1 | 4838 | |
c65ebc55 JW |
4839 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg)); |
4840 | } | |
4841 | } | |
4842 | ||
ffa88471 SE |
4843 | /* Implement TARGET_FUNCION_ARG target hook. */ |
4844 | ||
4845 | static rtx | |
d5cc9181 | 4846 | ia64_function_arg (cumulative_args_t cum, enum machine_mode mode, |
ffa88471 SE |
4847 | const_tree type, bool named) |
4848 | { | |
4849 | return ia64_function_arg_1 (cum, mode, type, named, false); | |
4850 | } | |
4851 | ||
4852 | /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */ | |
4853 | ||
4854 | static rtx | |
d5cc9181 | 4855 | ia64_function_incoming_arg (cumulative_args_t cum, |
ffa88471 SE |
4856 | enum machine_mode mode, |
4857 | const_tree type, bool named) | |
4858 | { | |
4859 | return ia64_function_arg_1 (cum, mode, type, named, true); | |
4860 | } | |
4861 | ||
78a52f11 | 4862 | /* Return number of bytes, at the beginning of the argument, that must be |
c65ebc55 JW |
4863 | put in registers. 0 is the argument is entirely in registers or entirely |
4864 | in memory. */ | |
4865 | ||
78a52f11 | 4866 | static int |
d5cc9181 | 4867 | ia64_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, |
78a52f11 | 4868 | tree type, bool named ATTRIBUTE_UNUSED) |
c65ebc55 | 4869 | { |
d5cc9181 JR |
4870 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4871 | ||
f57fc998 ZW |
4872 | int words = ia64_function_arg_words (type, mode); |
4873 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4874 | |
4875 | /* If all argument slots are used, then it must go on the stack. */ | |
4876 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4877 | return 0; | |
4878 | ||
4879 | /* It doesn't matter whether the argument goes in FR or GR regs. If | |
4880 | it fits within the 8 argument slots, then it goes entirely in | |
4881 | registers. If it extends past the last argument slot, then the rest | |
4882 | goes on the stack. */ | |
4883 | ||
4884 | if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS) | |
4885 | return 0; | |
4886 | ||
78a52f11 | 4887 | return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD; |
c65ebc55 JW |
4888 | } |
4889 | ||
f2972bf8 DR |
4890 | /* Return ivms_arg_type based on machine_mode. */ |
4891 | ||
4892 | static enum ivms_arg_type | |
4893 | ia64_arg_type (enum machine_mode mode) | |
4894 | { | |
4895 | switch (mode) | |
4896 | { | |
4897 | case SFmode: | |
4898 | return FS; | |
4899 | case DFmode: | |
4900 | return FT; | |
4901 | default: | |
4902 | return I64; | |
4903 | } | |
4904 | } | |
4905 | ||
c65ebc55 JW |
4906 | /* Update CUM to point after this argument. This is patterned after |
4907 | ia64_function_arg. */ | |
4908 | ||
ffa88471 | 4909 | static void |
d5cc9181 | 4910 | ia64_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
ffa88471 | 4911 | const_tree type, bool named) |
c65ebc55 | 4912 | { |
d5cc9181 | 4913 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
f57fc998 ZW |
4914 | int words = ia64_function_arg_words (type, mode); |
4915 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4916 | enum machine_mode hfa_mode = VOIDmode; |
4917 | ||
4918 | /* If all arg slots are already full, then there is nothing to do. */ | |
4919 | if (cum->words >= MAX_ARGUMENT_SLOTS) | |
f2972bf8 DR |
4920 | { |
4921 | cum->words += words + offset; | |
4922 | return; | |
4923 | } | |
c65ebc55 | 4924 | |
f2972bf8 | 4925 | cum->atypes[cum->words] = ia64_arg_type (mode); |
c65ebc55 JW |
4926 | cum->words += words + offset; |
4927 | ||
472b8fdc TG |
4928 | /* On OpenVMS argument is either in Rn or Fn. */ |
4929 | if (TARGET_ABI_OPEN_VMS) | |
4930 | { | |
4931 | cum->int_regs = cum->words; | |
4932 | cum->fp_regs = cum->words; | |
4933 | return; | |
4934 | } | |
4935 | ||
c65ebc55 JW |
4936 | /* Check for and handle homogeneous FP aggregates. */ |
4937 | if (type) | |
4938 | hfa_mode = hfa_element_mode (type, 0); | |
4939 | ||
4940 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4941 | and unprototyped hfas are passed specially. */ | |
4942 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4943 | { | |
4944 | int fp_regs = cum->fp_regs; | |
4945 | /* This is the original value of cum->words + offset. */ | |
4946 | int int_regs = cum->words - words; | |
4947 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4948 | int byte_size; | |
4949 | int args_byte_size; | |
4950 | ||
4951 | /* If prototyped, pass it in FR regs then GR regs. | |
4952 | If not prototyped, pass it in both FR and GR regs. | |
4953 | ||
4954 | If this is an SFmode aggregate, then it is possible to run out of | |
4955 | FR regs while GR regs are still left. In that case, we pass the | |
4956 | remaining part in the GR regs. */ | |
4957 | ||
4958 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4959 | of the argument, the last FP register, or the last argument slot. */ | |
4960 | ||
4961 | byte_size = ((mode == BLKmode) | |
4962 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4963 | args_byte_size = int_regs * UNITS_PER_WORD; | |
4964 | offset = 0; | |
4965 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4966 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));) | |
4967 | { | |
c65ebc55 JW |
4968 | offset += hfa_size; |
4969 | args_byte_size += hfa_size; | |
4970 | fp_regs++; | |
4971 | } | |
4972 | ||
4973 | cum->fp_regs = fp_regs; | |
4974 | } | |
4975 | ||
d13256a3 SE |
4976 | /* Integral and aggregates go in general registers. So do TFmode FP values. |
4977 | If we have run out of FR registers, then other FP values must also go in | |
4978 | general registers. This can happen when we have a SFmode HFA. */ | |
4979 | else if (mode == TFmode || mode == TCmode | |
4980 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
648fe28b | 4981 | cum->int_regs = cum->words; |
c65ebc55 JW |
4982 | |
4983 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4984 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4985 | else if (cum->prototype) |
4986 | { | |
4987 | if (! named) | |
648fe28b | 4988 | cum->int_regs = cum->words; |
c65ebc55 JW |
4989 | else |
4990 | /* ??? Complex types should not reach here. */ | |
4991 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
4992 | } | |
4993 | /* If there is no prototype, then FP values go in both FR and GR | |
4994 | registers. */ | |
4995 | else | |
9c808aad | 4996 | { |
648fe28b RH |
4997 | /* ??? Complex types should not reach here. */ |
4998 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
4999 | cum->int_regs = cum->words; | |
5000 | } | |
c65ebc55 | 5001 | } |
51dcde6f | 5002 | |
d13256a3 | 5003 | /* Arguments with alignment larger than 8 bytes start at the next even |
93348822 | 5004 | boundary. On ILP32 HPUX, TFmode arguments start on next even boundary |
d13256a3 SE |
5005 | even though their normal alignment is 8 bytes. See ia64_function_arg. */ |
5006 | ||
c2ed6cf8 NF |
5007 | static unsigned int |
5008 | ia64_function_arg_boundary (enum machine_mode mode, const_tree type) | |
d13256a3 | 5009 | { |
d13256a3 SE |
5010 | if (mode == TFmode && TARGET_HPUX && TARGET_ILP32) |
5011 | return PARM_BOUNDARY * 2; | |
5012 | ||
5013 | if (type) | |
5014 | { | |
5015 | if (TYPE_ALIGN (type) > PARM_BOUNDARY) | |
5016 | return PARM_BOUNDARY * 2; | |
5017 | else | |
5018 | return PARM_BOUNDARY; | |
5019 | } | |
5020 | ||
5021 | if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY) | |
5022 | return PARM_BOUNDARY * 2; | |
5023 | else | |
5024 | return PARM_BOUNDARY; | |
5025 | } | |
5026 | ||
599aedd9 RH |
5027 | /* True if it is OK to do sibling call optimization for the specified |
5028 | call expression EXP. DECL will be the called function, or NULL if | |
5029 | this is an indirect call. */ | |
5030 | static bool | |
9c808aad | 5031 | ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
599aedd9 | 5032 | { |
097f3d48 JW |
5033 | /* We can't perform a sibcall if the current function has the syscall_linkage |
5034 | attribute. */ | |
5035 | if (lookup_attribute ("syscall_linkage", | |
5036 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
5037 | return false; | |
5038 | ||
b23ba0b8 | 5039 | /* We must always return with our current GP. This means we can |
c208436c SE |
5040 | only sibcall to functions defined in the current module unless |
5041 | TARGET_CONST_GP is set to true. */ | |
5042 | return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP; | |
599aedd9 | 5043 | } |
c65ebc55 | 5044 | \f |
c65ebc55 JW |
5045 | |
5046 | /* Implement va_arg. */ | |
5047 | ||
23a60a04 | 5048 | static tree |
726a989a RB |
5049 | ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
5050 | gimple_seq *post_p) | |
cd3ce9b4 | 5051 | { |
cd3ce9b4 | 5052 | /* Variable sized types are passed by reference. */ |
08b0dc1b | 5053 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
cd3ce9b4 | 5054 | { |
23a60a04 JM |
5055 | tree ptrtype = build_pointer_type (type); |
5056 | tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p); | |
c2433d7d | 5057 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5058 | } |
5059 | ||
5060 | /* Aggregate arguments with alignment larger than 8 bytes start at | |
5061 | the next even boundary. Integer and floating point arguments | |
5062 | do so if they are larger than 8 bytes, whether or not they are | |
5063 | also aligned larger than 8 bytes. */ | |
5064 | if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE) | |
5065 | ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT) | |
5066 | { | |
5d49b6a7 | 5067 | tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1); |
47a25a46 | 5068 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
5d49b6a7 | 5069 | build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD)); |
726a989a | 5070 | gimplify_assign (unshare_expr (valist), t, pre_p); |
cd3ce9b4 JM |
5071 | } |
5072 | ||
23a60a04 | 5073 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 | 5074 | } |
c65ebc55 JW |
5075 | \f |
5076 | /* Return 1 if function return value returned in memory. Return 0 if it is | |
5077 | in a register. */ | |
5078 | ||
351a758b | 5079 | static bool |
586de218 | 5080 | ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED) |
c65ebc55 JW |
5081 | { |
5082 | enum machine_mode mode; | |
5083 | enum machine_mode hfa_mode; | |
487b97e0 | 5084 | HOST_WIDE_INT byte_size; |
c65ebc55 JW |
5085 | |
5086 | mode = TYPE_MODE (valtype); | |
487b97e0 RH |
5087 | byte_size = GET_MODE_SIZE (mode); |
5088 | if (mode == BLKmode) | |
5089 | { | |
5090 | byte_size = int_size_in_bytes (valtype); | |
5091 | if (byte_size < 0) | |
351a758b | 5092 | return true; |
487b97e0 | 5093 | } |
c65ebc55 JW |
5094 | |
5095 | /* Hfa's with up to 8 elements are returned in the FP argument registers. */ | |
5096 | ||
5097 | hfa_mode = hfa_element_mode (valtype, 0); | |
5098 | if (hfa_mode != VOIDmode) | |
5099 | { | |
5100 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
5101 | ||
c65ebc55 | 5102 | if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS) |
351a758b | 5103 | return true; |
c65ebc55 | 5104 | else |
351a758b | 5105 | return false; |
c65ebc55 | 5106 | } |
c65ebc55 | 5107 | else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS) |
351a758b | 5108 | return true; |
c65ebc55 | 5109 | else |
351a758b | 5110 | return false; |
c65ebc55 JW |
5111 | } |
5112 | ||
5113 | /* Return rtx for register that holds the function return value. */ | |
5114 | ||
ba90d838 AS |
5115 | static rtx |
5116 | ia64_function_value (const_tree valtype, | |
5117 | const_tree fn_decl_or_type, | |
5118 | bool outgoing ATTRIBUTE_UNUSED) | |
c65ebc55 JW |
5119 | { |
5120 | enum machine_mode mode; | |
5121 | enum machine_mode hfa_mode; | |
f2972bf8 | 5122 | int unsignedp; |
ba90d838 | 5123 | const_tree func = fn_decl_or_type; |
c65ebc55 | 5124 | |
ba90d838 AS |
5125 | if (fn_decl_or_type |
5126 | && !DECL_P (fn_decl_or_type)) | |
5127 | func = NULL; | |
5128 | ||
c65ebc55 JW |
5129 | mode = TYPE_MODE (valtype); |
5130 | hfa_mode = hfa_element_mode (valtype, 0); | |
5131 | ||
5132 | if (hfa_mode != VOIDmode) | |
5133 | { | |
5134 | rtx loc[8]; | |
5135 | int i; | |
5136 | int hfa_size; | |
5137 | int byte_size; | |
5138 | int offset; | |
5139 | ||
5140 | hfa_size = GET_MODE_SIZE (hfa_mode); | |
5141 | byte_size = ((mode == BLKmode) | |
5142 | ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode)); | |
5143 | offset = 0; | |
5144 | for (i = 0; offset < byte_size; i++) | |
5145 | { | |
5146 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5147 | gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i), | |
5148 | GEN_INT (offset)); | |
c65ebc55 JW |
5149 | offset += hfa_size; |
5150 | } | |
9dec91d4 | 5151 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 5152 | } |
f57fc998 | 5153 | else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode) |
c65ebc55 JW |
5154 | return gen_rtx_REG (mode, FR_ARG_FIRST); |
5155 | else | |
3870df96 | 5156 | { |
8c5cacfd RH |
5157 | bool need_parallel = false; |
5158 | ||
5159 | /* In big-endian mode, we need to manage the layout of aggregates | |
5160 | in the registers so that we get the bits properly aligned in | |
5161 | the highpart of the registers. */ | |
3870df96 SE |
5162 | if (BYTES_BIG_ENDIAN |
5163 | && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype)))) | |
8c5cacfd RH |
5164 | need_parallel = true; |
5165 | ||
5166 | /* Something like struct S { long double x; char a[0] } is not an | |
5167 | HFA structure, and therefore doesn't go in fp registers. But | |
5168 | the middle-end will give it XFmode anyway, and XFmode values | |
5169 | don't normally fit in integer registers. So we need to smuggle | |
5170 | the value inside a parallel. */ | |
4de67c26 | 5171 | else if (mode == XFmode || mode == XCmode || mode == RFmode) |
8c5cacfd RH |
5172 | need_parallel = true; |
5173 | ||
5174 | if (need_parallel) | |
3870df96 SE |
5175 | { |
5176 | rtx loc[8]; | |
5177 | int offset; | |
5178 | int bytesize; | |
5179 | int i; | |
5180 | ||
5181 | offset = 0; | |
5182 | bytesize = int_size_in_bytes (valtype); | |
543144ed JM |
5183 | /* An empty PARALLEL is invalid here, but the return value |
5184 | doesn't matter for empty structs. */ | |
5185 | if (bytesize == 0) | |
5186 | return gen_rtx_REG (mode, GR_RET_FIRST); | |
3870df96 SE |
5187 | for (i = 0; offset < bytesize; i++) |
5188 | { | |
5189 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5190 | gen_rtx_REG (DImode, | |
5191 | GR_RET_FIRST + i), | |
5192 | GEN_INT (offset)); | |
5193 | offset += UNITS_PER_WORD; | |
5194 | } | |
5195 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); | |
5196 | } | |
8c5cacfd | 5197 | |
8ee95727 TG |
5198 | mode = promote_function_mode (valtype, mode, &unsignedp, |
5199 | func ? TREE_TYPE (func) : NULL_TREE, | |
5200 | true); | |
f2972bf8 | 5201 | |
8c5cacfd | 5202 | return gen_rtx_REG (mode, GR_RET_FIRST); |
3870df96 | 5203 | } |
c65ebc55 JW |
5204 | } |
5205 | ||
ba90d838 AS |
5206 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
5207 | ||
5208 | static rtx | |
5209 | ia64_libcall_value (enum machine_mode mode, | |
5210 | const_rtx fun ATTRIBUTE_UNUSED) | |
5211 | { | |
5212 | return gen_rtx_REG (mode, | |
5213 | (((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5214 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5215 | && (mode) != TFmode) | |
5216 | ? FR_RET_FIRST : GR_RET_FIRST)); | |
5217 | } | |
5218 | ||
5219 | /* Worker function for FUNCTION_VALUE_REGNO_P. */ | |
5220 | ||
5221 | static bool | |
5222 | ia64_function_value_regno_p (const unsigned int regno) | |
5223 | { | |
5224 | return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST) | |
5225 | || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST)); | |
5226 | } | |
5227 | ||
fdbe66f2 | 5228 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
5229 | We need to emit DTP-relative relocations. */ |
5230 | ||
fdbe66f2 | 5231 | static void |
9c808aad | 5232 | ia64_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 | 5233 | { |
6f3113ed SE |
5234 | gcc_assert (size == 4 || size == 8); |
5235 | if (size == 4) | |
5236 | fputs ("\tdata4.ua\t@dtprel(", file); | |
5237 | else | |
5238 | fputs ("\tdata8.ua\t@dtprel(", file); | |
6b2300b3 JJ |
5239 | output_addr_const (file, x); |
5240 | fputs (")", file); | |
5241 | } | |
5242 | ||
c65ebc55 JW |
5243 | /* Print a memory address as an operand to reference that memory location. */ |
5244 | ||
5245 | /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps | |
5246 | also call this from ia64_print_operand for memory addresses. */ | |
5247 | ||
5e50b799 | 5248 | static void |
9c808aad AJ |
5249 | ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED, |
5250 | rtx address ATTRIBUTE_UNUSED) | |
c65ebc55 JW |
5251 | { |
5252 | } | |
5253 | ||
3569057d | 5254 | /* Print an operand to an assembler instruction. |
c65ebc55 JW |
5255 | C Swap and print a comparison operator. |
5256 | D Print an FP comparison operator. | |
5257 | E Print 32 - constant, for SImode shifts as extract. | |
66db6b45 | 5258 | e Print 64 - constant, for DImode rotates. |
c65ebc55 JW |
5259 | F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or |
5260 | a floating point register emitted normally. | |
735b94a7 | 5261 | G A floating point constant. |
c65ebc55 | 5262 | I Invert a predicate register by adding 1. |
e5bde68a | 5263 | J Select the proper predicate register for a condition. |
6b6c1201 | 5264 | j Select the inverse predicate register for a condition. |
c65ebc55 JW |
5265 | O Append .acq for volatile load. |
5266 | P Postincrement of a MEM. | |
5267 | Q Append .rel for volatile store. | |
4883241c | 5268 | R Print .s .d or nothing for a single, double or no truncation. |
c65ebc55 JW |
5269 | S Shift amount for shladd instruction. |
5270 | T Print an 8-bit sign extended number (K) as a 32-bit unsigned number | |
5271 | for Intel assembler. | |
5272 | U Print an 8-bit sign extended number (K) as a 64-bit unsigned number | |
5273 | for Intel assembler. | |
a71aef0b | 5274 | X A pair of floating point registers. |
c65ebc55 | 5275 | r Print register name, or constant 0 as r0. HP compatibility for |
f61134e8 RH |
5276 | Linux kernel. |
5277 | v Print vector constant value as an 8-byte integer value. */ | |
5278 | ||
5e50b799 | 5279 | static void |
9c808aad | 5280 | ia64_print_operand (FILE * file, rtx x, int code) |
c65ebc55 | 5281 | { |
e57b9d65 RH |
5282 | const char *str; |
5283 | ||
c65ebc55 JW |
5284 | switch (code) |
5285 | { | |
c65ebc55 JW |
5286 | case 0: |
5287 | /* Handled below. */ | |
5288 | break; | |
809d4ef1 | 5289 | |
c65ebc55 JW |
5290 | case 'C': |
5291 | { | |
5292 | enum rtx_code c = swap_condition (GET_CODE (x)); | |
5293 | fputs (GET_RTX_NAME (c), file); | |
5294 | return; | |
5295 | } | |
5296 | ||
5297 | case 'D': | |
e57b9d65 RH |
5298 | switch (GET_CODE (x)) |
5299 | { | |
5300 | case NE: | |
5301 | str = "neq"; | |
5302 | break; | |
5303 | case UNORDERED: | |
5304 | str = "unord"; | |
5305 | break; | |
5306 | case ORDERED: | |
5307 | str = "ord"; | |
5308 | break; | |
86ad1da0 SE |
5309 | case UNLT: |
5310 | str = "nge"; | |
5311 | break; | |
5312 | case UNLE: | |
5313 | str = "ngt"; | |
5314 | break; | |
5315 | case UNGT: | |
5316 | str = "nle"; | |
5317 | break; | |
5318 | case UNGE: | |
5319 | str = "nlt"; | |
5320 | break; | |
e57b9d65 RH |
5321 | default: |
5322 | str = GET_RTX_NAME (GET_CODE (x)); | |
5323 | break; | |
5324 | } | |
5325 | fputs (str, file); | |
c65ebc55 JW |
5326 | return; |
5327 | ||
5328 | case 'E': | |
5329 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); | |
5330 | return; | |
5331 | ||
66db6b45 RH |
5332 | case 'e': |
5333 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x)); | |
5334 | return; | |
5335 | ||
c65ebc55 JW |
5336 | case 'F': |
5337 | if (x == CONST0_RTX (GET_MODE (x))) | |
e57b9d65 | 5338 | str = reg_names [FR_REG (0)]; |
c65ebc55 | 5339 | else if (x == CONST1_RTX (GET_MODE (x))) |
e57b9d65 | 5340 | str = reg_names [FR_REG (1)]; |
c65ebc55 | 5341 | else |
e820471b NS |
5342 | { |
5343 | gcc_assert (GET_CODE (x) == REG); | |
5344 | str = reg_names [REGNO (x)]; | |
5345 | } | |
e57b9d65 | 5346 | fputs (str, file); |
c65ebc55 JW |
5347 | return; |
5348 | ||
735b94a7 SE |
5349 | case 'G': |
5350 | { | |
5351 | long val[4]; | |
5352 | REAL_VALUE_TYPE rv; | |
5353 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
5354 | real_to_target (val, &rv, GET_MODE (x)); | |
5355 | if (GET_MODE (x) == SFmode) | |
5356 | fprintf (file, "0x%08lx", val[0] & 0xffffffff); | |
5357 | else if (GET_MODE (x) == DFmode) | |
5358 | fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1]) | |
5359 | & 0xffffffff, | |
5360 | (WORDS_BIG_ENDIAN ? val[1] : val[0]) | |
5361 | & 0xffffffff); | |
5362 | else | |
5363 | output_operand_lossage ("invalid %%G mode"); | |
5364 | } | |
5365 | return; | |
5366 | ||
c65ebc55 JW |
5367 | case 'I': |
5368 | fputs (reg_names [REGNO (x) + 1], file); | |
5369 | return; | |
5370 | ||
e5bde68a | 5371 | case 'J': |
6b6c1201 RH |
5372 | case 'j': |
5373 | { | |
5374 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5375 | if (GET_CODE (x) == EQ) | |
5376 | regno += 1; | |
5377 | if (code == 'j') | |
5378 | regno ^= 1; | |
5379 | fputs (reg_names [regno], file); | |
5380 | } | |
e5bde68a RH |
5381 | return; |
5382 | ||
c65ebc55 JW |
5383 | case 'O': |
5384 | if (MEM_VOLATILE_P (x)) | |
5385 | fputs(".acq", file); | |
5386 | return; | |
5387 | ||
5388 | case 'P': | |
5389 | { | |
4b983fdc | 5390 | HOST_WIDE_INT value; |
c65ebc55 | 5391 | |
4b983fdc RH |
5392 | switch (GET_CODE (XEXP (x, 0))) |
5393 | { | |
5394 | default: | |
5395 | return; | |
5396 | ||
5397 | case POST_MODIFY: | |
5398 | x = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
5399 | if (GET_CODE (x) == CONST_INT) | |
08012cda | 5400 | value = INTVAL (x); |
e820471b | 5401 | else |
4b983fdc | 5402 | { |
e820471b | 5403 | gcc_assert (GET_CODE (x) == REG); |
08012cda | 5404 | fprintf (file, ", %s", reg_names[REGNO (x)]); |
4b983fdc RH |
5405 | return; |
5406 | } | |
4b983fdc | 5407 | break; |
c65ebc55 | 5408 | |
4b983fdc RH |
5409 | case POST_INC: |
5410 | value = GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc | 5411 | break; |
c65ebc55 | 5412 | |
4b983fdc | 5413 | case POST_DEC: |
08012cda | 5414 | value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x)); |
4b983fdc RH |
5415 | break; |
5416 | } | |
809d4ef1 | 5417 | |
4a0a75dd | 5418 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value); |
c65ebc55 JW |
5419 | return; |
5420 | } | |
5421 | ||
5422 | case 'Q': | |
5423 | if (MEM_VOLATILE_P (x)) | |
5424 | fputs(".rel", file); | |
5425 | return; | |
5426 | ||
4883241c SE |
5427 | case 'R': |
5428 | if (x == CONST0_RTX (GET_MODE (x))) | |
5429 | fputs(".s", file); | |
5430 | else if (x == CONST1_RTX (GET_MODE (x))) | |
5431 | fputs(".d", file); | |
5432 | else if (x == CONST2_RTX (GET_MODE (x))) | |
5433 | ; | |
5434 | else | |
5435 | output_operand_lossage ("invalid %%R value"); | |
5436 | return; | |
5437 | ||
c65ebc55 | 5438 | case 'S': |
809d4ef1 | 5439 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
c65ebc55 JW |
5440 | return; |
5441 | ||
5442 | case 'T': | |
5443 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5444 | { | |
809d4ef1 | 5445 | fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5446 | return; |
5447 | } | |
5448 | break; | |
5449 | ||
5450 | case 'U': | |
5451 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5452 | { | |
3b572406 | 5453 | const char *prefix = "0x"; |
c65ebc55 JW |
5454 | if (INTVAL (x) & 0x80000000) |
5455 | { | |
5456 | fprintf (file, "0xffffffff"); | |
5457 | prefix = ""; | |
5458 | } | |
809d4ef1 | 5459 | fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5460 | return; |
5461 | } | |
5462 | break; | |
809d4ef1 | 5463 | |
a71aef0b JB |
5464 | case 'X': |
5465 | { | |
5466 | unsigned int regno = REGNO (x); | |
5467 | fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]); | |
5468 | } | |
5469 | return; | |
5470 | ||
c65ebc55 | 5471 | case 'r': |
18a3c539 JW |
5472 | /* If this operand is the constant zero, write it as register zero. |
5473 | Any register, zero, or CONST_INT value is OK here. */ | |
c65ebc55 JW |
5474 | if (GET_CODE (x) == REG) |
5475 | fputs (reg_names[REGNO (x)], file); | |
5476 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5477 | fputs ("r0", file); | |
18a3c539 JW |
5478 | else if (GET_CODE (x) == CONST_INT) |
5479 | output_addr_const (file, x); | |
c65ebc55 JW |
5480 | else |
5481 | output_operand_lossage ("invalid %%r value"); | |
5482 | return; | |
5483 | ||
f61134e8 RH |
5484 | case 'v': |
5485 | gcc_assert (GET_CODE (x) == CONST_VECTOR); | |
5486 | x = simplify_subreg (DImode, x, GET_MODE (x), 0); | |
5487 | break; | |
5488 | ||
85548039 RH |
5489 | case '+': |
5490 | { | |
5491 | const char *which; | |
9c808aad | 5492 | |
85548039 RH |
5493 | /* For conditional branches, returns or calls, substitute |
5494 | sptk, dptk, dpnt, or spnt for %s. */ | |
5495 | x = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
5496 | if (x) | |
5497 | { | |
5498 | int pred_val = INTVAL (XEXP (x, 0)); | |
5499 | ||
5500 | /* Guess top and bottom 10% statically predicted. */ | |
2c9e13f3 JH |
5501 | if (pred_val < REG_BR_PROB_BASE / 50 |
5502 | && br_prob_note_reliable_p (x)) | |
85548039 RH |
5503 | which = ".spnt"; |
5504 | else if (pred_val < REG_BR_PROB_BASE / 2) | |
5505 | which = ".dpnt"; | |
2c9e13f3 JH |
5506 | else if (pred_val < REG_BR_PROB_BASE / 100 * 98 |
5507 | || !br_prob_note_reliable_p (x)) | |
85548039 RH |
5508 | which = ".dptk"; |
5509 | else | |
5510 | which = ".sptk"; | |
5511 | } | |
5512 | else if (GET_CODE (current_output_insn) == CALL_INSN) | |
5513 | which = ".sptk"; | |
5514 | else | |
5515 | which = ".dptk"; | |
5516 | ||
5517 | fputs (which, file); | |
5518 | return; | |
5519 | } | |
5520 | ||
6f8aa100 RH |
5521 | case ',': |
5522 | x = current_insn_predicate; | |
5523 | if (x) | |
5524 | { | |
5525 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5526 | if (GET_CODE (x) == EQ) | |
5527 | regno += 1; | |
6f8aa100 RH |
5528 | fprintf (file, "(%s) ", reg_names [regno]); |
5529 | } | |
5530 | return; | |
5531 | ||
c65ebc55 JW |
5532 | default: |
5533 | output_operand_lossage ("ia64_print_operand: unknown code"); | |
5534 | return; | |
5535 | } | |
5536 | ||
5537 | switch (GET_CODE (x)) | |
5538 | { | |
5539 | /* This happens for the spill/restore instructions. */ | |
5540 | case POST_INC: | |
4b983fdc RH |
5541 | case POST_DEC: |
5542 | case POST_MODIFY: | |
c65ebc55 | 5543 | x = XEXP (x, 0); |
ed168e45 | 5544 | /* ... fall through ... */ |
c65ebc55 JW |
5545 | |
5546 | case REG: | |
5547 | fputs (reg_names [REGNO (x)], file); | |
5548 | break; | |
5549 | ||
5550 | case MEM: | |
5551 | { | |
5552 | rtx addr = XEXP (x, 0); | |
ec8e098d | 5553 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC) |
c65ebc55 JW |
5554 | addr = XEXP (addr, 0); |
5555 | fprintf (file, "[%s]", reg_names [REGNO (addr)]); | |
5556 | break; | |
5557 | } | |
809d4ef1 | 5558 | |
c65ebc55 JW |
5559 | default: |
5560 | output_addr_const (file, x); | |
5561 | break; | |
5562 | } | |
5563 | ||
5564 | return; | |
5565 | } | |
5e50b799 AS |
5566 | |
5567 | /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ | |
5568 | ||
5569 | static bool | |
5570 | ia64_print_operand_punct_valid_p (unsigned char code) | |
5571 | { | |
5572 | return (code == '+' || code == ','); | |
5573 | } | |
c65ebc55 | 5574 | \f |
3c50106f RH |
5575 | /* Compute a (partial) cost for rtx X. Return true if the complete |
5576 | cost has been computed, and false if subexpressions should be | |
5577 | scanned. In either case, *TOTAL contains the cost result. */ | |
5578 | /* ??? This is incomplete. */ | |
5579 | ||
5580 | static bool | |
68f932c4 RS |
5581 | ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
5582 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
5583 | { |
5584 | switch (code) | |
5585 | { | |
5586 | case CONST_INT: | |
5587 | switch (outer_code) | |
5588 | { | |
5589 | case SET: | |
13f70342 | 5590 | *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1); |
3c50106f RH |
5591 | return true; |
5592 | case PLUS: | |
13f70342 | 5593 | if (satisfies_constraint_I (x)) |
3c50106f | 5594 | *total = 0; |
13f70342 | 5595 | else if (satisfies_constraint_J (x)) |
3c50106f RH |
5596 | *total = 1; |
5597 | else | |
5598 | *total = COSTS_N_INSNS (1); | |
5599 | return true; | |
5600 | default: | |
13f70342 | 5601 | if (satisfies_constraint_K (x) || satisfies_constraint_L (x)) |
3c50106f RH |
5602 | *total = 0; |
5603 | else | |
5604 | *total = COSTS_N_INSNS (1); | |
5605 | return true; | |
5606 | } | |
5607 | ||
5608 | case CONST_DOUBLE: | |
5609 | *total = COSTS_N_INSNS (1); | |
5610 | return true; | |
5611 | ||
5612 | case CONST: | |
5613 | case SYMBOL_REF: | |
5614 | case LABEL_REF: | |
5615 | *total = COSTS_N_INSNS (3); | |
5616 | return true; | |
5617 | ||
f19f1e5e RH |
5618 | case FMA: |
5619 | *total = COSTS_N_INSNS (4); | |
5620 | return true; | |
5621 | ||
3c50106f RH |
5622 | case MULT: |
5623 | /* For multiplies wider than HImode, we have to go to the FPU, | |
5624 | which normally involves copies. Plus there's the latency | |
5625 | of the multiply itself, and the latency of the instructions to | |
5626 | transfer integer regs to FP regs. */ | |
f19f1e5e RH |
5627 | if (FLOAT_MODE_P (GET_MODE (x))) |
5628 | *total = COSTS_N_INSNS (4); | |
5629 | else if (GET_MODE_SIZE (GET_MODE (x)) > 2) | |
3c50106f RH |
5630 | *total = COSTS_N_INSNS (10); |
5631 | else | |
5632 | *total = COSTS_N_INSNS (2); | |
5633 | return true; | |
5634 | ||
5635 | case PLUS: | |
5636 | case MINUS: | |
f19f1e5e RH |
5637 | if (FLOAT_MODE_P (GET_MODE (x))) |
5638 | { | |
5639 | *total = COSTS_N_INSNS (4); | |
5640 | return true; | |
5641 | } | |
5642 | /* FALLTHRU */ | |
5643 | ||
3c50106f RH |
5644 | case ASHIFT: |
5645 | case ASHIFTRT: | |
5646 | case LSHIFTRT: | |
5647 | *total = COSTS_N_INSNS (1); | |
5648 | return true; | |
5649 | ||
5650 | case DIV: | |
5651 | case UDIV: | |
5652 | case MOD: | |
5653 | case UMOD: | |
5654 | /* We make divide expensive, so that divide-by-constant will be | |
5655 | optimized to a multiply. */ | |
5656 | *total = COSTS_N_INSNS (60); | |
5657 | return true; | |
5658 | ||
5659 | default: | |
5660 | return false; | |
5661 | } | |
5662 | } | |
5663 | ||
9e4f94de | 5664 | /* Calculate the cost of moving data from a register in class FROM to |
7109d286 | 5665 | one in class TO, using MODE. */ |
5527bf14 | 5666 | |
de8f4b07 | 5667 | static int |
6f76a878 AS |
5668 | ia64_register_move_cost (enum machine_mode mode, reg_class_t from, |
5669 | reg_class_t to) | |
a87cf97e | 5670 | { |
7109d286 RH |
5671 | /* ADDL_REGS is the same as GR_REGS for movement purposes. */ |
5672 | if (to == ADDL_REGS) | |
5673 | to = GR_REGS; | |
5674 | if (from == ADDL_REGS) | |
5675 | from = GR_REGS; | |
5676 | ||
5677 | /* All costs are symmetric, so reduce cases by putting the | |
5678 | lower number class as the destination. */ | |
5679 | if (from < to) | |
5680 | { | |
6f76a878 | 5681 | reg_class_t tmp = to; |
7109d286 RH |
5682 | to = from, from = tmp; |
5683 | } | |
5684 | ||
02befdf4 | 5685 | /* Moving from FR<->GR in XFmode must be more expensive than 2, |
7109d286 | 5686 | so that we get secondary memory reloads. Between FR_REGS, |
69e18c09 | 5687 | we have to make this at least as expensive as memory_move_cost |
7109d286 | 5688 | to avoid spectacularly poor register class preferencing. */ |
4de67c26 | 5689 | if (mode == XFmode || mode == RFmode) |
7109d286 RH |
5690 | { |
5691 | if (to != GR_REGS || from != GR_REGS) | |
69e18c09 | 5692 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5693 | else |
5694 | return 3; | |
5695 | } | |
5696 | ||
5697 | switch (to) | |
5698 | { | |
5699 | case PR_REGS: | |
5700 | /* Moving between PR registers takes two insns. */ | |
5701 | if (from == PR_REGS) | |
5702 | return 3; | |
5703 | /* Moving between PR and anything but GR is impossible. */ | |
5704 | if (from != GR_REGS) | |
69e18c09 | 5705 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5706 | break; |
5707 | ||
5708 | case BR_REGS: | |
5709 | /* Moving between BR and anything but GR is impossible. */ | |
5710 | if (from != GR_REGS && from != GR_AND_BR_REGS) | |
69e18c09 | 5711 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5712 | break; |
5713 | ||
5714 | case AR_I_REGS: | |
5715 | case AR_M_REGS: | |
5716 | /* Moving between AR and anything but GR is impossible. */ | |
5717 | if (from != GR_REGS) | |
69e18c09 | 5718 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5719 | break; |
5720 | ||
5721 | case GR_REGS: | |
5722 | case FR_REGS: | |
a71aef0b | 5723 | case FP_REGS: |
7109d286 RH |
5724 | case GR_AND_FR_REGS: |
5725 | case GR_AND_BR_REGS: | |
5726 | case ALL_REGS: | |
5727 | break; | |
5728 | ||
5729 | default: | |
e820471b | 5730 | gcc_unreachable (); |
7109d286 | 5731 | } |
3f622353 | 5732 | |
5527bf14 RH |
5733 | return 2; |
5734 | } | |
c65ebc55 | 5735 | |
69e18c09 AS |
5736 | /* Calculate the cost of moving data of MODE from a register to or from |
5737 | memory. */ | |
5738 | ||
5739 | static int | |
5740 | ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
5741 | reg_class_t rclass, | |
5742 | bool in ATTRIBUTE_UNUSED) | |
5743 | { | |
5744 | if (rclass == GENERAL_REGS | |
5745 | || rclass == FR_REGS | |
5746 | || rclass == FP_REGS | |
5747 | || rclass == GR_AND_FR_REGS) | |
5748 | return 4; | |
5749 | else | |
5750 | return 10; | |
5751 | } | |
5752 | ||
ab177ad5 AS |
5753 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions |
5754 | on RCLASS to use when copying X into that class. */ | |
f61134e8 | 5755 | |
ab177ad5 AS |
5756 | static reg_class_t |
5757 | ia64_preferred_reload_class (rtx x, reg_class_t rclass) | |
f61134e8 | 5758 | { |
0a2aaacc | 5759 | switch (rclass) |
f61134e8 RH |
5760 | { |
5761 | case FR_REGS: | |
a71aef0b | 5762 | case FP_REGS: |
f61134e8 RH |
5763 | /* Don't allow volatile mem reloads into floating point registers. |
5764 | This is defined to force reload to choose the r/m case instead | |
5765 | of the f/f case when reloading (set (reg fX) (mem/v)). */ | |
5766 | if (MEM_P (x) && MEM_VOLATILE_P (x)) | |
5767 | return NO_REGS; | |
5768 | ||
5769 | /* Force all unrecognized constants into the constant pool. */ | |
5770 | if (CONSTANT_P (x)) | |
5771 | return NO_REGS; | |
5772 | break; | |
5773 | ||
5774 | case AR_M_REGS: | |
5775 | case AR_I_REGS: | |
5776 | if (!OBJECT_P (x)) | |
5777 | return NO_REGS; | |
5778 | break; | |
5779 | ||
5780 | default: | |
5781 | break; | |
5782 | } | |
5783 | ||
0a2aaacc | 5784 | return rclass; |
f61134e8 RH |
5785 | } |
5786 | ||
c65ebc55 | 5787 | /* This function returns the register class required for a secondary |
0a2aaacc | 5788 | register when copying between one of the registers in RCLASS, and X, |
c65ebc55 JW |
5789 | using MODE. A return value of NO_REGS means that no secondary register |
5790 | is required. */ | |
5791 | ||
5792 | enum reg_class | |
0a2aaacc | 5793 | ia64_secondary_reload_class (enum reg_class rclass, |
9c808aad | 5794 | enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
c65ebc55 JW |
5795 | { |
5796 | int regno = -1; | |
5797 | ||
5798 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
5799 | regno = true_regnum (x); | |
5800 | ||
0a2aaacc | 5801 | switch (rclass) |
97e242b0 RH |
5802 | { |
5803 | case BR_REGS: | |
7109d286 RH |
5804 | case AR_M_REGS: |
5805 | case AR_I_REGS: | |
5806 | /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global | |
5807 | interaction. We end up with two pseudos with overlapping lifetimes | |
5808 | both of which are equiv to the same constant, and both which need | |
5809 | to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end | |
5810 | changes depending on the path length, which means the qty_first_reg | |
5811 | check in make_regs_eqv can give different answers at different times. | |
5812 | At some point I'll probably need a reload_indi pattern to handle | |
5813 | this. | |
5814 | ||
5815 | We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we | |
5816 | wound up with a FP register from GR_AND_FR_REGS. Extend that to all | |
5817 | non-general registers for good measure. */ | |
5818 | if (regno >= 0 && ! GENERAL_REGNO_P (regno)) | |
97e242b0 RH |
5819 | return GR_REGS; |
5820 | ||
5821 | /* This is needed if a pseudo used as a call_operand gets spilled to a | |
5822 | stack slot. */ | |
5823 | if (GET_CODE (x) == MEM) | |
5824 | return GR_REGS; | |
5825 | break; | |
5826 | ||
5827 | case FR_REGS: | |
a71aef0b | 5828 | case FP_REGS: |
c51e6d85 | 5829 | /* Need to go through general registers to get to other class regs. */ |
7109d286 RH |
5830 | if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno))) |
5831 | return GR_REGS; | |
9c808aad | 5832 | |
97e242b0 RH |
5833 | /* This can happen when a paradoxical subreg is an operand to the |
5834 | muldi3 pattern. */ | |
5835 | /* ??? This shouldn't be necessary after instruction scheduling is | |
5836 | enabled, because paradoxical subregs are not accepted by | |
5837 | register_operand when INSN_SCHEDULING is defined. Or alternatively, | |
5838 | stop the paradoxical subreg stupidity in the *_operand functions | |
5839 | in recog.c. */ | |
5840 | if (GET_CODE (x) == MEM | |
5841 | && (GET_MODE (x) == SImode || GET_MODE (x) == HImode | |
5842 | || GET_MODE (x) == QImode)) | |
5843 | return GR_REGS; | |
5844 | ||
5845 | /* This can happen because of the ior/and/etc patterns that accept FP | |
5846 | registers as operands. If the third operand is a constant, then it | |
5847 | needs to be reloaded into a FP register. */ | |
5848 | if (GET_CODE (x) == CONST_INT) | |
5849 | return GR_REGS; | |
5850 | ||
5851 | /* This can happen because of register elimination in a muldi3 insn. | |
5852 | E.g. `26107 * (unsigned long)&u'. */ | |
5853 | if (GET_CODE (x) == PLUS) | |
5854 | return GR_REGS; | |
5855 | break; | |
5856 | ||
5857 | case PR_REGS: | |
f2f90c63 | 5858 | /* ??? This happens if we cse/gcse a BImode value across a call, |
97e242b0 RH |
5859 | and the function has a nonlocal goto. This is because global |
5860 | does not allocate call crossing pseudos to hard registers when | |
e3b5732b | 5861 | crtl->has_nonlocal_goto is true. This is relatively |
97e242b0 RH |
5862 | common for C++ programs that use exceptions. To reproduce, |
5863 | return NO_REGS and compile libstdc++. */ | |
5864 | if (GET_CODE (x) == MEM) | |
5865 | return GR_REGS; | |
f2f90c63 RH |
5866 | |
5867 | /* This can happen when we take a BImode subreg of a DImode value, | |
5868 | and that DImode value winds up in some non-GR register. */ | |
5869 | if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno)) | |
5870 | return GR_REGS; | |
97e242b0 RH |
5871 | break; |
5872 | ||
5873 | default: | |
5874 | break; | |
5875 | } | |
c65ebc55 JW |
5876 | |
5877 | return NO_REGS; | |
5878 | } | |
5879 | ||
215b063c PB |
5880 | \f |
5881 | /* Implement targetm.unspec_may_trap_p hook. */ | |
5882 | static int | |
5883 | ia64_unspec_may_trap_p (const_rtx x, unsigned flags) | |
5884 | { | |
5885 | if (GET_CODE (x) == UNSPEC) | |
5886 | { | |
5887 | switch (XINT (x, 1)) | |
5888 | { | |
5889 | case UNSPEC_LDA: | |
5890 | case UNSPEC_LDS: | |
5891 | case UNSPEC_LDSA: | |
5892 | case UNSPEC_LDCCLR: | |
5893 | case UNSPEC_CHKACLR: | |
5894 | case UNSPEC_CHKS: | |
5895 | /* These unspecs are just wrappers. */ | |
5896 | return may_trap_p_1 (XVECEXP (x, 0, 0), flags); | |
5897 | } | |
5898 | } | |
5899 | ||
5900 | return default_unspec_may_trap_p (x, flags); | |
5901 | } | |
5902 | ||
c65ebc55 JW |
5903 | \f |
5904 | /* Parse the -mfixed-range= option string. */ | |
5905 | ||
5906 | static void | |
9c808aad | 5907 | fix_range (const char *const_str) |
c65ebc55 JW |
5908 | { |
5909 | int i, first, last; | |
3b572406 | 5910 | char *str, *dash, *comma; |
c65ebc55 JW |
5911 | |
5912 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
5913 | REG2 are either register names or register numbers. The effect | |
5914 | of this option is to mark the registers in the range from REG1 to | |
5915 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
5916 | used, e.g., to ensure that kernel mode code doesn't use f32-f127. */ | |
5917 | ||
3b572406 RH |
5918 | i = strlen (const_str); |
5919 | str = (char *) alloca (i + 1); | |
5920 | memcpy (str, const_str, i + 1); | |
5921 | ||
c65ebc55 JW |
5922 | while (1) |
5923 | { | |
5924 | dash = strchr (str, '-'); | |
5925 | if (!dash) | |
5926 | { | |
d4ee4d25 | 5927 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
c65ebc55 JW |
5928 | return; |
5929 | } | |
5930 | *dash = '\0'; | |
5931 | ||
5932 | comma = strchr (dash + 1, ','); | |
5933 | if (comma) | |
5934 | *comma = '\0'; | |
5935 | ||
5936 | first = decode_reg_name (str); | |
5937 | if (first < 0) | |
5938 | { | |
d4ee4d25 | 5939 | warning (0, "unknown register name: %s", str); |
c65ebc55 JW |
5940 | return; |
5941 | } | |
5942 | ||
5943 | last = decode_reg_name (dash + 1); | |
5944 | if (last < 0) | |
5945 | { | |
d4ee4d25 | 5946 | warning (0, "unknown register name: %s", dash + 1); |
c65ebc55 JW |
5947 | return; |
5948 | } | |
5949 | ||
5950 | *dash = '-'; | |
5951 | ||
5952 | if (first > last) | |
5953 | { | |
d4ee4d25 | 5954 | warning (0, "%s-%s is an empty range", str, dash + 1); |
c65ebc55 JW |
5955 | return; |
5956 | } | |
5957 | ||
5958 | for (i = first; i <= last; ++i) | |
5959 | fixed_regs[i] = call_used_regs[i] = 1; | |
5960 | ||
5961 | if (!comma) | |
5962 | break; | |
5963 | ||
5964 | *comma = ','; | |
5965 | str = comma + 1; | |
5966 | } | |
5967 | } | |
5968 | ||
930572b9 | 5969 | /* Implement TARGET_OPTION_OVERRIDE. */ |
c65ebc55 | 5970 | |
930572b9 AS |
5971 | static void |
5972 | ia64_option_override (void) | |
c65ebc55 | 5973 | { |
e6cc0c98 JM |
5974 | unsigned int i; |
5975 | cl_deferred_option *opt; | |
5976 | VEC(cl_deferred_option,heap) *vec | |
5977 | = (VEC(cl_deferred_option,heap) *) ia64_deferred_options; | |
5978 | ||
5979 | FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt) | |
5980 | { | |
5981 | switch (opt->opt_index) | |
5982 | { | |
5983 | case OPT_mfixed_range_: | |
5984 | fix_range (opt->arg); | |
5985 | break; | |
5986 | ||
5987 | default: | |
5988 | gcc_unreachable (); | |
5989 | } | |
5990 | } | |
5991 | ||
59da9a7d JW |
5992 | if (TARGET_AUTO_PIC) |
5993 | target_flags |= MASK_CONST_GP; | |
5994 | ||
7e1e7d4c VM |
5995 | /* Numerous experiment shows that IRA based loop pressure |
5996 | calculation works better for RTL loop invariant motion on targets | |
5997 | with enough (>= 32) registers. It is an expensive optimization. | |
5998 | So it is on only for peak performance. */ | |
5999 | if (optimize >= 3) | |
6000 | flag_ira_loop_pressure = 1; | |
6001 | ||
6002 | ||
fa37ed29 JM |
6003 | ia64_section_threshold = (global_options_set.x_g_switch_value |
6004 | ? g_switch_value | |
6005 | : IA64_DEFAULT_GVALUE); | |
2b7e2984 SE |
6006 | |
6007 | init_machine_status = ia64_init_machine_status; | |
6008 | ||
6009 | if (align_functions <= 0) | |
6010 | align_functions = 64; | |
6011 | if (align_loops <= 0) | |
6012 | align_loops = 32; | |
6013 | if (TARGET_ABI_OPEN_VMS) | |
6014 | flag_no_common = 1; | |
6015 | ||
6016 | ia64_override_options_after_change(); | |
6017 | } | |
6018 | ||
6019 | /* Implement targetm.override_options_after_change. */ | |
6020 | ||
6021 | static void | |
6022 | ia64_override_options_after_change (void) | |
6023 | { | |
388092d5 | 6024 | if (optimize >= 3 |
d4d24ba4 JM |
6025 | && !global_options_set.x_flag_selective_scheduling |
6026 | && !global_options_set.x_flag_selective_scheduling2) | |
388092d5 AB |
6027 | { |
6028 | flag_selective_scheduling2 = 1; | |
6029 | flag_sel_sched_pipelining = 1; | |
6030 | } | |
6031 | if (mflag_sched_control_spec == 2) | |
6032 | { | |
6033 | /* Control speculation is on by default for the selective scheduler, | |
6034 | but not for the Haifa scheduler. */ | |
6035 | mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0; | |
6036 | } | |
6037 | if (flag_sel_sched_pipelining && flag_auto_inc_dec) | |
6038 | { | |
6039 | /* FIXME: remove this when we'd implement breaking autoinsns as | |
6040 | a transformation. */ | |
6041 | flag_auto_inc_dec = 0; | |
6042 | } | |
c65ebc55 | 6043 | } |
dbdd120f | 6044 | |
6fb5fa3c DB |
6045 | /* Initialize the record of emitted frame related registers. */ |
6046 | ||
6047 | void ia64_init_expanders (void) | |
6048 | { | |
6049 | memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs)); | |
6050 | } | |
6051 | ||
dbdd120f RH |
6052 | static struct machine_function * |
6053 | ia64_init_machine_status (void) | |
6054 | { | |
a9429e29 | 6055 | return ggc_alloc_cleared_machine_function (); |
dbdd120f | 6056 | } |
c65ebc55 | 6057 | \f |
9c808aad AJ |
6058 | static enum attr_itanium_class ia64_safe_itanium_class (rtx); |
6059 | static enum attr_type ia64_safe_type (rtx); | |
2130b7fb | 6060 | |
2130b7fb | 6061 | static enum attr_itanium_class |
9c808aad | 6062 | ia64_safe_itanium_class (rtx insn) |
2130b7fb BS |
6063 | { |
6064 | if (recog_memoized (insn) >= 0) | |
6065 | return get_attr_itanium_class (insn); | |
b5b8b0ac AO |
6066 | else if (DEBUG_INSN_P (insn)) |
6067 | return ITANIUM_CLASS_IGNORE; | |
2130b7fb BS |
6068 | else |
6069 | return ITANIUM_CLASS_UNKNOWN; | |
6070 | } | |
6071 | ||
6072 | static enum attr_type | |
9c808aad | 6073 | ia64_safe_type (rtx insn) |
2130b7fb BS |
6074 | { |
6075 | if (recog_memoized (insn) >= 0) | |
6076 | return get_attr_type (insn); | |
6077 | else | |
6078 | return TYPE_UNKNOWN; | |
6079 | } | |
6080 | \f | |
c65ebc55 JW |
6081 | /* The following collection of routines emit instruction group stop bits as |
6082 | necessary to avoid dependencies. */ | |
6083 | ||
6084 | /* Need to track some additional registers as far as serialization is | |
6085 | concerned so we can properly handle br.call and br.ret. We could | |
6086 | make these registers visible to gcc, but since these registers are | |
6087 | never explicitly used in gcc generated code, it seems wasteful to | |
6088 | do so (plus it would make the call and return patterns needlessly | |
6089 | complex). */ | |
c65ebc55 | 6090 | #define REG_RP (BR_REG (0)) |
c65ebc55 | 6091 | #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1) |
c65ebc55 JW |
6092 | /* This is used for volatile asms which may require a stop bit immediately |
6093 | before and after them. */ | |
5527bf14 | 6094 | #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2) |
870f9ec0 RH |
6095 | #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3) |
6096 | #define NUM_REGS (AR_UNAT_BIT_0 + 64) | |
c65ebc55 | 6097 | |
f2f90c63 RH |
6098 | /* For each register, we keep track of how it has been written in the |
6099 | current instruction group. | |
6100 | ||
6101 | If a register is written unconditionally (no qualifying predicate), | |
6102 | WRITE_COUNT is set to 2 and FIRST_PRED is ignored. | |
6103 | ||
6104 | If a register is written if its qualifying predicate P is true, we | |
6105 | set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register | |
6106 | may be written again by the complement of P (P^1) and when this happens, | |
6107 | WRITE_COUNT gets set to 2. | |
6108 | ||
6109 | The result of this is that whenever an insn attempts to write a register | |
e03f5d43 | 6110 | whose WRITE_COUNT is two, we need to issue an insn group barrier first. |
f2f90c63 RH |
6111 | |
6112 | If a predicate register is written by a floating-point insn, we set | |
6113 | WRITTEN_BY_FP to true. | |
6114 | ||
6115 | If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND | |
6116 | to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */ | |
6117 | ||
444a356a JJ |
6118 | #if GCC_VERSION >= 4000 |
6119 | #define RWS_FIELD_TYPE __extension__ unsigned short | |
6120 | #else | |
6121 | #define RWS_FIELD_TYPE unsigned int | |
6122 | #endif | |
c65ebc55 JW |
6123 | struct reg_write_state |
6124 | { | |
444a356a JJ |
6125 | RWS_FIELD_TYPE write_count : 2; |
6126 | RWS_FIELD_TYPE first_pred : 10; | |
6127 | RWS_FIELD_TYPE written_by_fp : 1; | |
6128 | RWS_FIELD_TYPE written_by_and : 1; | |
6129 | RWS_FIELD_TYPE written_by_or : 1; | |
c65ebc55 JW |
6130 | }; |
6131 | ||
6132 | /* Cumulative info for the current instruction group. */ | |
6133 | struct reg_write_state rws_sum[NUM_REGS]; | |
444a356a JJ |
6134 | #ifdef ENABLE_CHECKING |
6135 | /* Bitmap whether a register has been written in the current insn. */ | |
6136 | HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) | |
6137 | / HOST_BITS_PER_WIDEST_FAST_INT]; | |
6138 | ||
6139 | static inline void | |
6140 | rws_insn_set (int regno) | |
6141 | { | |
6142 | gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno)); | |
6143 | SET_HARD_REG_BIT (rws_insn, regno); | |
6144 | } | |
6145 | ||
6146 | static inline int | |
6147 | rws_insn_test (int regno) | |
6148 | { | |
6149 | return TEST_HARD_REG_BIT (rws_insn, regno); | |
6150 | } | |
6151 | #else | |
6152 | /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */ | |
6153 | unsigned char rws_insn[2]; | |
6154 | ||
6155 | static inline void | |
6156 | rws_insn_set (int regno) | |
6157 | { | |
6158 | if (regno == REG_AR_CFM) | |
6159 | rws_insn[0] = 1; | |
6160 | else if (regno == REG_VOLATILE) | |
6161 | rws_insn[1] = 1; | |
6162 | } | |
6163 | ||
6164 | static inline int | |
6165 | rws_insn_test (int regno) | |
6166 | { | |
6167 | if (regno == REG_AR_CFM) | |
6168 | return rws_insn[0]; | |
6169 | if (regno == REG_VOLATILE) | |
6170 | return rws_insn[1]; | |
6171 | return 0; | |
6172 | } | |
6173 | #endif | |
c65ebc55 | 6174 | |
25250265 | 6175 | /* Indicates whether this is the first instruction after a stop bit, |
e820471b NS |
6176 | in which case we don't need another stop bit. Without this, |
6177 | ia64_variable_issue will die when scheduling an alloc. */ | |
25250265 JW |
6178 | static int first_instruction; |
6179 | ||
c65ebc55 JW |
6180 | /* Misc flags needed to compute RAW/WAW dependencies while we are traversing |
6181 | RTL for one instruction. */ | |
6182 | struct reg_flags | |
6183 | { | |
6184 | unsigned int is_write : 1; /* Is register being written? */ | |
6185 | unsigned int is_fp : 1; /* Is register used as part of an fp op? */ | |
6186 | unsigned int is_branch : 1; /* Is register used as part of a branch? */ | |
f2f90c63 RH |
6187 | unsigned int is_and : 1; /* Is register used as part of and.orcm? */ |
6188 | unsigned int is_or : 1; /* Is register used as part of or.andcm? */ | |
2ed4af6f | 6189 | unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */ |
c65ebc55 JW |
6190 | }; |
6191 | ||
444a356a | 6192 | static void rws_update (int, struct reg_flags, int); |
9c808aad AJ |
6193 | static int rws_access_regno (int, struct reg_flags, int); |
6194 | static int rws_access_reg (rtx, struct reg_flags, int); | |
c1bc6ca8 JW |
6195 | static void update_set_flags (rtx, struct reg_flags *); |
6196 | static int set_src_needs_barrier (rtx, struct reg_flags, int); | |
9c808aad AJ |
6197 | static int rtx_needs_barrier (rtx, struct reg_flags, int); |
6198 | static void init_insn_group_barriers (void); | |
c1bc6ca8 JW |
6199 | static int group_barrier_needed (rtx); |
6200 | static int safe_group_barrier_needed (rtx); | |
444a356a | 6201 | static int in_safe_group_barrier; |
3b572406 | 6202 | |
c65ebc55 JW |
6203 | /* Update *RWS for REGNO, which is being written by the current instruction, |
6204 | with predicate PRED, and associated register flags in FLAGS. */ | |
6205 | ||
6206 | static void | |
444a356a | 6207 | rws_update (int regno, struct reg_flags flags, int pred) |
c65ebc55 | 6208 | { |
3e7c7805 | 6209 | if (pred) |
444a356a | 6210 | rws_sum[regno].write_count++; |
3e7c7805 | 6211 | else |
444a356a JJ |
6212 | rws_sum[regno].write_count = 2; |
6213 | rws_sum[regno].written_by_fp |= flags.is_fp; | |
f2f90c63 | 6214 | /* ??? Not tracking and/or across differing predicates. */ |
444a356a JJ |
6215 | rws_sum[regno].written_by_and = flags.is_and; |
6216 | rws_sum[regno].written_by_or = flags.is_or; | |
6217 | rws_sum[regno].first_pred = pred; | |
c65ebc55 JW |
6218 | } |
6219 | ||
6220 | /* Handle an access to register REGNO of type FLAGS using predicate register | |
444a356a | 6221 | PRED. Update rws_sum array. Return 1 if this access creates |
c65ebc55 JW |
6222 | a dependency with an earlier instruction in the same group. */ |
6223 | ||
6224 | static int | |
9c808aad | 6225 | rws_access_regno (int regno, struct reg_flags flags, int pred) |
c65ebc55 JW |
6226 | { |
6227 | int need_barrier = 0; | |
c65ebc55 | 6228 | |
e820471b | 6229 | gcc_assert (regno < NUM_REGS); |
c65ebc55 | 6230 | |
f2f90c63 RH |
6231 | if (! PR_REGNO_P (regno)) |
6232 | flags.is_and = flags.is_or = 0; | |
6233 | ||
c65ebc55 JW |
6234 | if (flags.is_write) |
6235 | { | |
12c2c7aa JW |
6236 | int write_count; |
6237 | ||
444a356a | 6238 | rws_insn_set (regno); |
12c2c7aa | 6239 | write_count = rws_sum[regno].write_count; |
12c2c7aa JW |
6240 | |
6241 | switch (write_count) | |
c65ebc55 JW |
6242 | { |
6243 | case 0: | |
6244 | /* The register has not been written yet. */ | |
444a356a JJ |
6245 | if (!in_safe_group_barrier) |
6246 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6247 | break; |
6248 | ||
6249 | case 1: | |
89774469 SE |
6250 | /* The register has been written via a predicate. Treat |
6251 | it like a unconditional write and do not try to check | |
6252 | for complementary pred reg in earlier write. */ | |
f2f90c63 | 6253 | if (flags.is_and && rws_sum[regno].written_by_and) |
9c808aad | 6254 | ; |
f2f90c63 RH |
6255 | else if (flags.is_or && rws_sum[regno].written_by_or) |
6256 | ; | |
89774469 | 6257 | else |
c65ebc55 | 6258 | need_barrier = 1; |
444a356a JJ |
6259 | if (!in_safe_group_barrier) |
6260 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6261 | break; |
6262 | ||
6263 | case 2: | |
6264 | /* The register has been unconditionally written already. We | |
6265 | need a barrier. */ | |
f2f90c63 RH |
6266 | if (flags.is_and && rws_sum[regno].written_by_and) |
6267 | ; | |
6268 | else if (flags.is_or && rws_sum[regno].written_by_or) | |
6269 | ; | |
6270 | else | |
6271 | need_barrier = 1; | |
444a356a JJ |
6272 | if (!in_safe_group_barrier) |
6273 | { | |
6274 | rws_sum[regno].written_by_and = flags.is_and; | |
6275 | rws_sum[regno].written_by_or = flags.is_or; | |
6276 | } | |
c65ebc55 JW |
6277 | break; |
6278 | ||
6279 | default: | |
e820471b | 6280 | gcc_unreachable (); |
c65ebc55 JW |
6281 | } |
6282 | } | |
6283 | else | |
6284 | { | |
6285 | if (flags.is_branch) | |
6286 | { | |
6287 | /* Branches have several RAW exceptions that allow to avoid | |
6288 | barriers. */ | |
6289 | ||
5527bf14 | 6290 | if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM) |
c65ebc55 JW |
6291 | /* RAW dependencies on branch regs are permissible as long |
6292 | as the writer is a non-branch instruction. Since we | |
6293 | never generate code that uses a branch register written | |
6294 | by a branch instruction, handling this case is | |
6295 | easy. */ | |
5527bf14 | 6296 | return 0; |
c65ebc55 JW |
6297 | |
6298 | if (REGNO_REG_CLASS (regno) == PR_REGS | |
6299 | && ! rws_sum[regno].written_by_fp) | |
6300 | /* The predicates of a branch are available within the | |
6301 | same insn group as long as the predicate was written by | |
ed168e45 | 6302 | something other than a floating-point instruction. */ |
c65ebc55 JW |
6303 | return 0; |
6304 | } | |
6305 | ||
f2f90c63 RH |
6306 | if (flags.is_and && rws_sum[regno].written_by_and) |
6307 | return 0; | |
6308 | if (flags.is_or && rws_sum[regno].written_by_or) | |
6309 | return 0; | |
6310 | ||
c65ebc55 JW |
6311 | switch (rws_sum[regno].write_count) |
6312 | { | |
6313 | case 0: | |
6314 | /* The register has not been written yet. */ | |
6315 | break; | |
6316 | ||
6317 | case 1: | |
89774469 SE |
6318 | /* The register has been written via a predicate, assume we |
6319 | need a barrier (don't check for complementary regs). */ | |
6320 | need_barrier = 1; | |
c65ebc55 JW |
6321 | break; |
6322 | ||
6323 | case 2: | |
6324 | /* The register has been unconditionally written already. We | |
6325 | need a barrier. */ | |
6326 | need_barrier = 1; | |
6327 | break; | |
6328 | ||
6329 | default: | |
e820471b | 6330 | gcc_unreachable (); |
c65ebc55 JW |
6331 | } |
6332 | } | |
6333 | ||
6334 | return need_barrier; | |
6335 | } | |
6336 | ||
97e242b0 | 6337 | static int |
9c808aad | 6338 | rws_access_reg (rtx reg, struct reg_flags flags, int pred) |
97e242b0 RH |
6339 | { |
6340 | int regno = REGNO (reg); | |
6341 | int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); | |
6342 | ||
6343 | if (n == 1) | |
6344 | return rws_access_regno (regno, flags, pred); | |
6345 | else | |
6346 | { | |
6347 | int need_barrier = 0; | |
6348 | while (--n >= 0) | |
6349 | need_barrier |= rws_access_regno (regno + n, flags, pred); | |
6350 | return need_barrier; | |
6351 | } | |
6352 | } | |
6353 | ||
112333d3 BS |
6354 | /* Examine X, which is a SET rtx, and update the flags, the predicate, and |
6355 | the condition, stored in *PFLAGS, *PPRED and *PCOND. */ | |
6356 | ||
6357 | static void | |
c1bc6ca8 | 6358 | update_set_flags (rtx x, struct reg_flags *pflags) |
112333d3 BS |
6359 | { |
6360 | rtx src = SET_SRC (x); | |
6361 | ||
112333d3 BS |
6362 | switch (GET_CODE (src)) |
6363 | { | |
6364 | case CALL: | |
6365 | return; | |
6366 | ||
6367 | case IF_THEN_ELSE: | |
048d0d36 | 6368 | /* There are four cases here: |
c8d3810f RH |
6369 | (1) The destination is (pc), in which case this is a branch, |
6370 | nothing here applies. | |
6371 | (2) The destination is ar.lc, in which case this is a | |
6372 | doloop_end_internal, | |
6373 | (3) The destination is an fp register, in which case this is | |
6374 | an fselect instruction. | |
048d0d36 MK |
6375 | (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case |
6376 | this is a check load. | |
c8d3810f RH |
6377 | In all cases, nothing we do in this function applies. */ |
6378 | return; | |
112333d3 BS |
6379 | |
6380 | default: | |
ec8e098d | 6381 | if (COMPARISON_P (src) |
c8d3810f | 6382 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0)))) |
112333d3 BS |
6383 | /* Set pflags->is_fp to 1 so that we know we're dealing |
6384 | with a floating point comparison when processing the | |
6385 | destination of the SET. */ | |
6386 | pflags->is_fp = 1; | |
6387 | ||
6388 | /* Discover if this is a parallel comparison. We only handle | |
6389 | and.orcm and or.andcm at present, since we must retain a | |
6390 | strict inverse on the predicate pair. */ | |
6391 | else if (GET_CODE (src) == AND) | |
6392 | pflags->is_and = 1; | |
6393 | else if (GET_CODE (src) == IOR) | |
6394 | pflags->is_or = 1; | |
6395 | ||
6396 | break; | |
6397 | } | |
6398 | } | |
6399 | ||
6400 | /* Subroutine of rtx_needs_barrier; this function determines whether the | |
6401 | source of a given SET rtx found in X needs a barrier. FLAGS and PRED | |
6402 | are as in rtx_needs_barrier. COND is an rtx that holds the condition | |
6403 | for this insn. */ | |
9c808aad | 6404 | |
112333d3 | 6405 | static int |
c1bc6ca8 | 6406 | set_src_needs_barrier (rtx x, struct reg_flags flags, int pred) |
112333d3 BS |
6407 | { |
6408 | int need_barrier = 0; | |
6409 | rtx dst; | |
6410 | rtx src = SET_SRC (x); | |
6411 | ||
6412 | if (GET_CODE (src) == CALL) | |
6413 | /* We don't need to worry about the result registers that | |
6414 | get written by subroutine call. */ | |
6415 | return rtx_needs_barrier (src, flags, pred); | |
6416 | else if (SET_DEST (x) == pc_rtx) | |
6417 | { | |
6418 | /* X is a conditional branch. */ | |
6419 | /* ??? This seems redundant, as the caller sets this bit for | |
6420 | all JUMP_INSNs. */ | |
048d0d36 MK |
6421 | if (!ia64_spec_check_src_p (src)) |
6422 | flags.is_branch = 1; | |
112333d3 BS |
6423 | return rtx_needs_barrier (src, flags, pred); |
6424 | } | |
6425 | ||
048d0d36 MK |
6426 | if (ia64_spec_check_src_p (src)) |
6427 | /* Avoid checking one register twice (in condition | |
6428 | and in 'then' section) for ldc pattern. */ | |
6429 | { | |
6430 | gcc_assert (REG_P (XEXP (src, 2))); | |
6431 | need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred); | |
6432 | ||
6433 | /* We process MEM below. */ | |
6434 | src = XEXP (src, 1); | |
6435 | } | |
6436 | ||
6437 | need_barrier |= rtx_needs_barrier (src, flags, pred); | |
112333d3 | 6438 | |
112333d3 BS |
6439 | dst = SET_DEST (x); |
6440 | if (GET_CODE (dst) == ZERO_EXTRACT) | |
6441 | { | |
6442 | need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred); | |
6443 | need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred); | |
112333d3 BS |
6444 | } |
6445 | return need_barrier; | |
6446 | } | |
6447 | ||
b38ba463 ZW |
6448 | /* Handle an access to rtx X of type FLAGS using predicate register |
6449 | PRED. Return 1 if this access creates a dependency with an earlier | |
6450 | instruction in the same group. */ | |
c65ebc55 JW |
6451 | |
6452 | static int | |
9c808aad | 6453 | rtx_needs_barrier (rtx x, struct reg_flags flags, int pred) |
c65ebc55 JW |
6454 | { |
6455 | int i, j; | |
6456 | int is_complemented = 0; | |
6457 | int need_barrier = 0; | |
6458 | const char *format_ptr; | |
6459 | struct reg_flags new_flags; | |
c1bc6ca8 | 6460 | rtx cond; |
c65ebc55 JW |
6461 | |
6462 | if (! x) | |
6463 | return 0; | |
6464 | ||
6465 | new_flags = flags; | |
6466 | ||
6467 | switch (GET_CODE (x)) | |
6468 | { | |
9c808aad | 6469 | case SET: |
c1bc6ca8 JW |
6470 | update_set_flags (x, &new_flags); |
6471 | need_barrier = set_src_needs_barrier (x, new_flags, pred); | |
112333d3 | 6472 | if (GET_CODE (SET_SRC (x)) != CALL) |
c65ebc55 | 6473 | { |
112333d3 BS |
6474 | new_flags.is_write = 1; |
6475 | need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred); | |
c65ebc55 | 6476 | } |
c65ebc55 JW |
6477 | break; |
6478 | ||
6479 | case CALL: | |
6480 | new_flags.is_write = 0; | |
97e242b0 | 6481 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
c65ebc55 JW |
6482 | |
6483 | /* Avoid multiple register writes, in case this is a pattern with | |
e820471b | 6484 | multiple CALL rtx. This avoids a failure in rws_access_reg. */ |
444a356a | 6485 | if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM)) |
c65ebc55 JW |
6486 | { |
6487 | new_flags.is_write = 1; | |
97e242b0 RH |
6488 | need_barrier |= rws_access_regno (REG_RP, new_flags, pred); |
6489 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred); | |
6490 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6491 | } |
6492 | break; | |
6493 | ||
e5bde68a RH |
6494 | case COND_EXEC: |
6495 | /* X is a predicated instruction. */ | |
6496 | ||
6497 | cond = COND_EXEC_TEST (x); | |
e820471b | 6498 | gcc_assert (!pred); |
e5bde68a RH |
6499 | need_barrier = rtx_needs_barrier (cond, flags, 0); |
6500 | ||
6501 | if (GET_CODE (cond) == EQ) | |
6502 | is_complemented = 1; | |
6503 | cond = XEXP (cond, 0); | |
e820471b | 6504 | gcc_assert (GET_CODE (cond) == REG |
c1bc6ca8 | 6505 | && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS); |
e5bde68a RH |
6506 | pred = REGNO (cond); |
6507 | if (is_complemented) | |
6508 | ++pred; | |
6509 | ||
6510 | need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred); | |
6511 | return need_barrier; | |
6512 | ||
c65ebc55 | 6513 | case CLOBBER: |
c65ebc55 | 6514 | case USE: |
c65ebc55 JW |
6515 | /* Clobber & use are for earlier compiler-phases only. */ |
6516 | break; | |
6517 | ||
6518 | case ASM_OPERANDS: | |
6519 | case ASM_INPUT: | |
6520 | /* We always emit stop bits for traditional asms. We emit stop bits | |
6521 | for volatile extended asms if TARGET_VOL_ASM_STOP is true. */ | |
6522 | if (GET_CODE (x) != ASM_OPERANDS | |
6523 | || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP)) | |
6524 | { | |
6525 | /* Avoid writing the register multiple times if we have multiple | |
e820471b | 6526 | asm outputs. This avoids a failure in rws_access_reg. */ |
444a356a | 6527 | if (! rws_insn_test (REG_VOLATILE)) |
c65ebc55 JW |
6528 | { |
6529 | new_flags.is_write = 1; | |
97e242b0 | 6530 | rws_access_regno (REG_VOLATILE, new_flags, pred); |
c65ebc55 JW |
6531 | } |
6532 | return 1; | |
6533 | } | |
6534 | ||
6535 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
1e5f1716 | 6536 | We cannot just fall through here since then we would be confused |
c65ebc55 JW |
6537 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate |
6538 | traditional asms unlike their normal usage. */ | |
6539 | ||
6540 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i) | |
6541 | if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred)) | |
6542 | need_barrier = 1; | |
6543 | break; | |
6544 | ||
6545 | case PARALLEL: | |
6546 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
112333d3 BS |
6547 | { |
6548 | rtx pat = XVECEXP (x, 0, i); | |
051d8245 | 6549 | switch (GET_CODE (pat)) |
112333d3 | 6550 | { |
051d8245 | 6551 | case SET: |
c1bc6ca8 JW |
6552 | update_set_flags (pat, &new_flags); |
6553 | need_barrier |= set_src_needs_barrier (pat, new_flags, pred); | |
051d8245 RH |
6554 | break; |
6555 | ||
6556 | case USE: | |
6557 | case CALL: | |
6558 | case ASM_OPERANDS: | |
6559 | need_barrier |= rtx_needs_barrier (pat, flags, pred); | |
6560 | break; | |
6561 | ||
6562 | case CLOBBER: | |
628162ea JJ |
6563 | if (REG_P (XEXP (pat, 0)) |
6564 | && extract_asm_operands (x) != NULL_RTX | |
6565 | && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM) | |
6566 | { | |
6567 | new_flags.is_write = 1; | |
6568 | need_barrier |= rtx_needs_barrier (XEXP (pat, 0), | |
6569 | new_flags, pred); | |
6570 | new_flags = flags; | |
6571 | } | |
6572 | break; | |
6573 | ||
051d8245 RH |
6574 | case RETURN: |
6575 | break; | |
6576 | ||
6577 | default: | |
6578 | gcc_unreachable (); | |
112333d3 | 6579 | } |
112333d3 BS |
6580 | } |
6581 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
6582 | { | |
6583 | rtx pat = XVECEXP (x, 0, i); | |
6584 | if (GET_CODE (pat) == SET) | |
6585 | { | |
6586 | if (GET_CODE (SET_SRC (pat)) != CALL) | |
6587 | { | |
6588 | new_flags.is_write = 1; | |
6589 | need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags, | |
6590 | pred); | |
6591 | } | |
6592 | } | |
339cb12e | 6593 | else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN) |
112333d3 BS |
6594 | need_barrier |= rtx_needs_barrier (pat, flags, pred); |
6595 | } | |
c65ebc55 JW |
6596 | break; |
6597 | ||
6598 | case SUBREG: | |
077bc924 JM |
6599 | need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred); |
6600 | break; | |
c65ebc55 | 6601 | case REG: |
870f9ec0 RH |
6602 | if (REGNO (x) == AR_UNAT_REGNUM) |
6603 | { | |
6604 | for (i = 0; i < 64; ++i) | |
6605 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred); | |
6606 | } | |
6607 | else | |
6608 | need_barrier = rws_access_reg (x, flags, pred); | |
c65ebc55 JW |
6609 | break; |
6610 | ||
6611 | case MEM: | |
6612 | /* Find the regs used in memory address computation. */ | |
6613 | new_flags.is_write = 0; | |
6614 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6615 | break; | |
6616 | ||
051d8245 | 6617 | case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR: |
c65ebc55 JW |
6618 | case SYMBOL_REF: case LABEL_REF: case CONST: |
6619 | break; | |
6620 | ||
6621 | /* Operators with side-effects. */ | |
6622 | case POST_INC: case POST_DEC: | |
e820471b | 6623 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
c65ebc55 JW |
6624 | |
6625 | new_flags.is_write = 0; | |
97e242b0 | 6626 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 | 6627 | new_flags.is_write = 1; |
97e242b0 | 6628 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6629 | break; |
6630 | ||
6631 | case POST_MODIFY: | |
e820471b | 6632 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
4b983fdc RH |
6633 | |
6634 | new_flags.is_write = 0; | |
97e242b0 | 6635 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6636 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); |
6637 | new_flags.is_write = 1; | |
97e242b0 | 6638 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 JW |
6639 | break; |
6640 | ||
6641 | /* Handle common unary and binary ops for efficiency. */ | |
6642 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
6643 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
6644 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
6645 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
6646 | case NE: case EQ: case GE: case GT: case LE: | |
6647 | case LT: case GEU: case GTU: case LEU: case LTU: | |
6648 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6649 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); | |
6650 | break; | |
6651 | ||
6652 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
6653 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
6654 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
c407570a | 6655 | case SQRT: case FFS: case POPCOUNT: |
c65ebc55 JW |
6656 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6657 | break; | |
6658 | ||
051d8245 RH |
6659 | case VEC_SELECT: |
6660 | /* VEC_SELECT's second argument is a PARALLEL with integers that | |
6661 | describe the elements selected. On ia64, those integers are | |
6662 | always constants. Avoid walking the PARALLEL so that we don't | |
e820471b | 6663 | get confused with "normal" parallels and then die. */ |
051d8245 RH |
6664 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6665 | break; | |
6666 | ||
c65ebc55 JW |
6667 | case UNSPEC: |
6668 | switch (XINT (x, 1)) | |
6669 | { | |
7b6e506e RH |
6670 | case UNSPEC_LTOFF_DTPMOD: |
6671 | case UNSPEC_LTOFF_DTPREL: | |
6672 | case UNSPEC_DTPREL: | |
6673 | case UNSPEC_LTOFF_TPREL: | |
6674 | case UNSPEC_TPREL: | |
6675 | case UNSPEC_PRED_REL_MUTEX: | |
6676 | case UNSPEC_PIC_CALL: | |
6677 | case UNSPEC_MF: | |
6678 | case UNSPEC_FETCHADD_ACQ: | |
28875d67 | 6679 | case UNSPEC_FETCHADD_REL: |
7b6e506e RH |
6680 | case UNSPEC_BSP_VALUE: |
6681 | case UNSPEC_FLUSHRS: | |
6682 | case UNSPEC_BUNDLE_SELECTOR: | |
6683 | break; | |
6684 | ||
086c0f96 RH |
6685 | case UNSPEC_GR_SPILL: |
6686 | case UNSPEC_GR_RESTORE: | |
870f9ec0 RH |
6687 | { |
6688 | HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); | |
6689 | HOST_WIDE_INT bit = (offset >> 3) & 63; | |
6690 | ||
6691 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
83338d15 | 6692 | new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL); |
870f9ec0 RH |
6693 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit, |
6694 | new_flags, pred); | |
6695 | break; | |
6696 | } | |
9c808aad | 6697 | |
086c0f96 RH |
6698 | case UNSPEC_FR_SPILL: |
6699 | case UNSPEC_FR_RESTORE: | |
c407570a | 6700 | case UNSPEC_GETF_EXP: |
b38ba463 | 6701 | case UNSPEC_SETF_EXP: |
086c0f96 | 6702 | case UNSPEC_ADDP4: |
b38ba463 | 6703 | case UNSPEC_FR_SQRT_RECIP_APPROX: |
07acc7b3 | 6704 | case UNSPEC_FR_SQRT_RECIP_APPROX_RES: |
048d0d36 MK |
6705 | case UNSPEC_LDA: |
6706 | case UNSPEC_LDS: | |
388092d5 | 6707 | case UNSPEC_LDS_A: |
048d0d36 MK |
6708 | case UNSPEC_LDSA: |
6709 | case UNSPEC_CHKACLR: | |
6710 | case UNSPEC_CHKS: | |
6dd12198 SE |
6711 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6712 | break; | |
6713 | ||
086c0f96 | 6714 | case UNSPEC_FR_RECIP_APPROX: |
f526a3c8 | 6715 | case UNSPEC_SHRP: |
046625fa | 6716 | case UNSPEC_COPYSIGN: |
1def9c3f | 6717 | case UNSPEC_FR_RECIP_APPROX_RES: |
655f2eb9 RH |
6718 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6719 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); | |
6720 | break; | |
6721 | ||
086c0f96 | 6722 | case UNSPEC_CMPXCHG_ACQ: |
28875d67 | 6723 | case UNSPEC_CMPXCHG_REL: |
0551c32d RH |
6724 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); |
6725 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); | |
6726 | break; | |
6727 | ||
c65ebc55 | 6728 | default: |
e820471b | 6729 | gcc_unreachable (); |
c65ebc55 JW |
6730 | } |
6731 | break; | |
6732 | ||
6733 | case UNSPEC_VOLATILE: | |
6734 | switch (XINT (x, 1)) | |
6735 | { | |
086c0f96 | 6736 | case UNSPECV_ALLOC: |
25250265 JW |
6737 | /* Alloc must always be the first instruction of a group. |
6738 | We force this by always returning true. */ | |
6739 | /* ??? We might get better scheduling if we explicitly check for | |
6740 | input/local/output register dependencies, and modify the | |
6741 | scheduler so that alloc is always reordered to the start of | |
6742 | the current group. We could then eliminate all of the | |
6743 | first_instruction code. */ | |
6744 | rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6745 | |
6746 | new_flags.is_write = 1; | |
25250265 JW |
6747 | rws_access_regno (REG_AR_CFM, new_flags, pred); |
6748 | return 1; | |
c65ebc55 | 6749 | |
086c0f96 | 6750 | case UNSPECV_SET_BSP: |
7b84aac0 | 6751 | case UNSPECV_PROBE_STACK_RANGE: |
3b572406 RH |
6752 | need_barrier = 1; |
6753 | break; | |
6754 | ||
086c0f96 RH |
6755 | case UNSPECV_BLOCKAGE: |
6756 | case UNSPECV_INSN_GROUP_BARRIER: | |
6757 | case UNSPECV_BREAK: | |
6758 | case UNSPECV_PSAC_ALL: | |
6759 | case UNSPECV_PSAC_NORMAL: | |
3b572406 | 6760 | return 0; |
0c96007e | 6761 | |
7b84aac0 EB |
6762 | case UNSPECV_PROBE_STACK_ADDRESS: |
6763 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
6764 | break; | |
6765 | ||
c65ebc55 | 6766 | default: |
e820471b | 6767 | gcc_unreachable (); |
c65ebc55 JW |
6768 | } |
6769 | break; | |
6770 | ||
6771 | case RETURN: | |
6772 | new_flags.is_write = 0; | |
97e242b0 RH |
6773 | need_barrier = rws_access_regno (REG_RP, flags, pred); |
6774 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6775 | |
6776 | new_flags.is_write = 1; | |
97e242b0 RH |
6777 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
6778 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6779 | break; |
6780 | ||
6781 | default: | |
6782 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
6783 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6784 | switch (format_ptr[i]) | |
6785 | { | |
6786 | case '0': /* unused field */ | |
6787 | case 'i': /* integer */ | |
6788 | case 'n': /* note */ | |
6789 | case 'w': /* wide integer */ | |
6790 | case 's': /* pointer to string */ | |
6791 | case 'S': /* optional pointer to string */ | |
6792 | break; | |
6793 | ||
6794 | case 'e': | |
6795 | if (rtx_needs_barrier (XEXP (x, i), flags, pred)) | |
6796 | need_barrier = 1; | |
6797 | break; | |
6798 | ||
6799 | case 'E': | |
6800 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
6801 | if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred)) | |
6802 | need_barrier = 1; | |
6803 | break; | |
6804 | ||
6805 | default: | |
e820471b | 6806 | gcc_unreachable (); |
c65ebc55 | 6807 | } |
2ed4af6f | 6808 | break; |
c65ebc55 JW |
6809 | } |
6810 | return need_barrier; | |
6811 | } | |
6812 | ||
c1bc6ca8 | 6813 | /* Clear out the state for group_barrier_needed at the start of a |
2130b7fb BS |
6814 | sequence of insns. */ |
6815 | ||
6816 | static void | |
9c808aad | 6817 | init_insn_group_barriers (void) |
2130b7fb BS |
6818 | { |
6819 | memset (rws_sum, 0, sizeof (rws_sum)); | |
25250265 | 6820 | first_instruction = 1; |
2130b7fb BS |
6821 | } |
6822 | ||
c1bc6ca8 JW |
6823 | /* Given the current state, determine whether a group barrier (a stop bit) is |
6824 | necessary before INSN. Return nonzero if so. This modifies the state to | |
6825 | include the effects of INSN as a side-effect. */ | |
2130b7fb BS |
6826 | |
6827 | static int | |
c1bc6ca8 | 6828 | group_barrier_needed (rtx insn) |
2130b7fb BS |
6829 | { |
6830 | rtx pat; | |
6831 | int need_barrier = 0; | |
6832 | struct reg_flags flags; | |
6833 | ||
6834 | memset (&flags, 0, sizeof (flags)); | |
6835 | switch (GET_CODE (insn)) | |
6836 | { | |
6837 | case NOTE: | |
b5b8b0ac | 6838 | case DEBUG_INSN: |
2130b7fb BS |
6839 | break; |
6840 | ||
6841 | case BARRIER: | |
6842 | /* A barrier doesn't imply an instruction group boundary. */ | |
6843 | break; | |
6844 | ||
6845 | case CODE_LABEL: | |
6846 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6847 | return 1; | |
6848 | ||
6849 | case CALL_INSN: | |
6850 | flags.is_branch = 1; | |
6851 | flags.is_sibcall = SIBLING_CALL_P (insn); | |
6852 | memset (rws_insn, 0, sizeof (rws_insn)); | |
f12f25a7 RH |
6853 | |
6854 | /* Don't bundle a call following another call. */ | |
6855 | if ((pat = prev_active_insn (insn)) | |
6856 | && GET_CODE (pat) == CALL_INSN) | |
6857 | { | |
6858 | need_barrier = 1; | |
6859 | break; | |
6860 | } | |
6861 | ||
2130b7fb BS |
6862 | need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0); |
6863 | break; | |
6864 | ||
6865 | case JUMP_INSN: | |
048d0d36 MK |
6866 | if (!ia64_spec_check_p (insn)) |
6867 | flags.is_branch = 1; | |
f12f25a7 RH |
6868 | |
6869 | /* Don't bundle a jump following a call. */ | |
6870 | if ((pat = prev_active_insn (insn)) | |
6871 | && GET_CODE (pat) == CALL_INSN) | |
6872 | { | |
6873 | need_barrier = 1; | |
6874 | break; | |
6875 | } | |
5efb1046 | 6876 | /* FALLTHRU */ |
2130b7fb BS |
6877 | |
6878 | case INSN: | |
6879 | if (GET_CODE (PATTERN (insn)) == USE | |
6880 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
6881 | /* Don't care about USE and CLOBBER "insns"---those are used to | |
6882 | indicate to the optimizer that it shouldn't get rid of | |
6883 | certain operations. */ | |
6884 | break; | |
6885 | ||
6886 | pat = PATTERN (insn); | |
6887 | ||
6888 | /* Ug. Hack hacks hacked elsewhere. */ | |
6889 | switch (recog_memoized (insn)) | |
6890 | { | |
6891 | /* We play dependency tricks with the epilogue in order | |
6892 | to get proper schedules. Undo this for dv analysis. */ | |
6893 | case CODE_FOR_epilogue_deallocate_stack: | |
bdbe5b8d | 6894 | case CODE_FOR_prologue_allocate_stack: |
2130b7fb BS |
6895 | pat = XVECEXP (pat, 0, 0); |
6896 | break; | |
6897 | ||
6898 | /* The pattern we use for br.cloop confuses the code above. | |
6899 | The second element of the vector is representative. */ | |
6900 | case CODE_FOR_doloop_end_internal: | |
6901 | pat = XVECEXP (pat, 0, 1); | |
6902 | break; | |
6903 | ||
6904 | /* Doesn't generate code. */ | |
6905 | case CODE_FOR_pred_rel_mutex: | |
d0e82870 | 6906 | case CODE_FOR_prologue_use: |
2130b7fb BS |
6907 | return 0; |
6908 | ||
6909 | default: | |
6910 | break; | |
6911 | } | |
6912 | ||
6913 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6914 | need_barrier = rtx_needs_barrier (pat, flags, 0); | |
6915 | ||
6916 | /* Check to see if the previous instruction was a volatile | |
6917 | asm. */ | |
6918 | if (! need_barrier) | |
6919 | need_barrier = rws_access_regno (REG_VOLATILE, flags, 0); | |
388092d5 | 6920 | |
2130b7fb BS |
6921 | break; |
6922 | ||
6923 | default: | |
e820471b | 6924 | gcc_unreachable (); |
2130b7fb | 6925 | } |
25250265 | 6926 | |
7b84aac0 | 6927 | if (first_instruction && important_for_bundling_p (insn)) |
25250265 JW |
6928 | { |
6929 | need_barrier = 0; | |
6930 | first_instruction = 0; | |
6931 | } | |
6932 | ||
2130b7fb BS |
6933 | return need_barrier; |
6934 | } | |
6935 | ||
c1bc6ca8 | 6936 | /* Like group_barrier_needed, but do not clobber the current state. */ |
2130b7fb BS |
6937 | |
6938 | static int | |
c1bc6ca8 | 6939 | safe_group_barrier_needed (rtx insn) |
2130b7fb | 6940 | { |
25250265 | 6941 | int saved_first_instruction; |
2130b7fb | 6942 | int t; |
25250265 | 6943 | |
25250265 | 6944 | saved_first_instruction = first_instruction; |
444a356a | 6945 | in_safe_group_barrier = 1; |
25250265 | 6946 | |
c1bc6ca8 | 6947 | t = group_barrier_needed (insn); |
25250265 | 6948 | |
25250265 | 6949 | first_instruction = saved_first_instruction; |
444a356a | 6950 | in_safe_group_barrier = 0; |
25250265 | 6951 | |
2130b7fb BS |
6952 | return t; |
6953 | } | |
6954 | ||
18dbd950 RS |
6955 | /* Scan the current function and insert stop bits as necessary to |
6956 | eliminate dependencies. This function assumes that a final | |
6957 | instruction scheduling pass has been run which has already | |
6958 | inserted most of the necessary stop bits. This function only | |
6959 | inserts new ones at basic block boundaries, since these are | |
6960 | invisible to the scheduler. */ | |
2130b7fb BS |
6961 | |
6962 | static void | |
9c808aad | 6963 | emit_insn_group_barriers (FILE *dump) |
2130b7fb BS |
6964 | { |
6965 | rtx insn; | |
6966 | rtx last_label = 0; | |
6967 | int insns_since_last_label = 0; | |
6968 | ||
6969 | init_insn_group_barriers (); | |
6970 | ||
18dbd950 | 6971 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2130b7fb BS |
6972 | { |
6973 | if (GET_CODE (insn) == CODE_LABEL) | |
6974 | { | |
6975 | if (insns_since_last_label) | |
6976 | last_label = insn; | |
6977 | insns_since_last_label = 0; | |
6978 | } | |
6979 | else if (GET_CODE (insn) == NOTE | |
a38e7aa5 | 6980 | && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK) |
2130b7fb BS |
6981 | { |
6982 | if (insns_since_last_label) | |
6983 | last_label = insn; | |
6984 | insns_since_last_label = 0; | |
6985 | } | |
6986 | else if (GET_CODE (insn) == INSN | |
6987 | && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
086c0f96 | 6988 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) |
2130b7fb BS |
6989 | { |
6990 | init_insn_group_barriers (); | |
6991 | last_label = 0; | |
6992 | } | |
b5b8b0ac | 6993 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb BS |
6994 | { |
6995 | insns_since_last_label = 1; | |
6996 | ||
c1bc6ca8 | 6997 | if (group_barrier_needed (insn)) |
2130b7fb BS |
6998 | { |
6999 | if (last_label) | |
7000 | { | |
7001 | if (dump) | |
7002 | fprintf (dump, "Emitting stop before label %d\n", | |
7003 | INSN_UID (last_label)); | |
7004 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label); | |
7005 | insn = last_label; | |
112333d3 BS |
7006 | |
7007 | init_insn_group_barriers (); | |
7008 | last_label = 0; | |
2130b7fb | 7009 | } |
2130b7fb BS |
7010 | } |
7011 | } | |
7012 | } | |
7013 | } | |
f4d578da BS |
7014 | |
7015 | /* Like emit_insn_group_barriers, but run if no final scheduling pass was run. | |
7016 | This function has to emit all necessary group barriers. */ | |
7017 | ||
7018 | static void | |
9c808aad | 7019 | emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
f4d578da BS |
7020 | { |
7021 | rtx insn; | |
7022 | ||
7023 | init_insn_group_barriers (); | |
7024 | ||
18dbd950 | 7025 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f4d578da | 7026 | { |
bd7b9a0f RH |
7027 | if (GET_CODE (insn) == BARRIER) |
7028 | { | |
7029 | rtx last = prev_active_insn (insn); | |
7030 | ||
7031 | if (! last) | |
7032 | continue; | |
7033 | if (GET_CODE (last) == JUMP_INSN | |
7034 | && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC) | |
7035 | last = prev_active_insn (last); | |
7036 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
7037 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
7038 | ||
7039 | init_insn_group_barriers (); | |
7040 | } | |
b5b8b0ac | 7041 | else if (NONDEBUG_INSN_P (insn)) |
f4d578da | 7042 | { |
bd7b9a0f RH |
7043 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
7044 | init_insn_group_barriers (); | |
c1bc6ca8 | 7045 | else if (group_barrier_needed (insn)) |
f4d578da BS |
7046 | { |
7047 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); | |
7048 | init_insn_group_barriers (); | |
c1bc6ca8 | 7049 | group_barrier_needed (insn); |
f4d578da BS |
7050 | } |
7051 | } | |
7052 | } | |
7053 | } | |
30028c85 | 7054 | |
2130b7fb | 7055 | \f |
2130b7fb | 7056 | |
30028c85 | 7057 | /* Instruction scheduling support. */ |
2130b7fb BS |
7058 | |
7059 | #define NR_BUNDLES 10 | |
7060 | ||
30028c85 | 7061 | /* A list of names of all available bundles. */ |
2130b7fb | 7062 | |
30028c85 | 7063 | static const char *bundle_name [NR_BUNDLES] = |
2130b7fb | 7064 | { |
30028c85 VM |
7065 | ".mii", |
7066 | ".mmi", | |
7067 | ".mfi", | |
7068 | ".mmf", | |
2130b7fb | 7069 | #if NR_BUNDLES == 10 |
30028c85 VM |
7070 | ".bbb", |
7071 | ".mbb", | |
2130b7fb | 7072 | #endif |
30028c85 VM |
7073 | ".mib", |
7074 | ".mmb", | |
7075 | ".mfb", | |
7076 | ".mlx" | |
2130b7fb BS |
7077 | }; |
7078 | ||
30028c85 | 7079 | /* Nonzero if we should insert stop bits into the schedule. */ |
2130b7fb | 7080 | |
30028c85 | 7081 | int ia64_final_schedule = 0; |
2130b7fb | 7082 | |
35fd3193 | 7083 | /* Codes of the corresponding queried units: */ |
2130b7fb | 7084 | |
30028c85 VM |
7085 | static int _0mii_, _0mmi_, _0mfi_, _0mmf_; |
7086 | static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_; | |
2130b7fb | 7087 | |
30028c85 VM |
7088 | static int _1mii_, _1mmi_, _1mfi_, _1mmf_; |
7089 | static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_; | |
2130b7fb | 7090 | |
30028c85 VM |
7091 | static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6; |
7092 | ||
7093 | /* The following variable value is an insn group barrier. */ | |
7094 | ||
7095 | static rtx dfa_stop_insn; | |
7096 | ||
7097 | /* The following variable value is the last issued insn. */ | |
7098 | ||
7099 | static rtx last_scheduled_insn; | |
7100 | ||
30028c85 VM |
7101 | /* The following variable value is pointer to a DFA state used as |
7102 | temporary variable. */ | |
7103 | ||
7104 | static state_t temp_dfa_state = NULL; | |
7105 | ||
7106 | /* The following variable value is DFA state after issuing the last | |
7107 | insn. */ | |
7108 | ||
7109 | static state_t prev_cycle_state = NULL; | |
7110 | ||
7111 | /* The following array element values are TRUE if the corresponding | |
9e4f94de | 7112 | insn requires to add stop bits before it. */ |
30028c85 | 7113 | |
048d0d36 MK |
7114 | static char *stops_p = NULL; |
7115 | ||
30028c85 VM |
7116 | /* The following variable is used to set up the mentioned above array. */ |
7117 | ||
7118 | static int stop_before_p = 0; | |
7119 | ||
7120 | /* The following variable value is length of the arrays `clocks' and | |
7121 | `add_cycles'. */ | |
7122 | ||
7123 | static int clocks_length; | |
7124 | ||
048d0d36 MK |
7125 | /* The following variable value is number of data speculations in progress. */ |
7126 | static int pending_data_specs = 0; | |
7127 | ||
388092d5 AB |
7128 | /* Number of memory references on current and three future processor cycles. */ |
7129 | static char mem_ops_in_group[4]; | |
7130 | ||
7131 | /* Number of current processor cycle (from scheduler's point of view). */ | |
7132 | static int current_cycle; | |
7133 | ||
9c808aad AJ |
7134 | static rtx ia64_single_set (rtx); |
7135 | static void ia64_emit_insn_before (rtx, rtx); | |
2130b7fb BS |
7136 | |
7137 | /* Map a bundle number to its pseudo-op. */ | |
7138 | ||
7139 | const char * | |
9c808aad | 7140 | get_bundle_name (int b) |
2130b7fb | 7141 | { |
30028c85 | 7142 | return bundle_name[b]; |
2130b7fb BS |
7143 | } |
7144 | ||
2130b7fb BS |
7145 | |
7146 | /* Return the maximum number of instructions a cpu can issue. */ | |
7147 | ||
c237e94a | 7148 | static int |
9c808aad | 7149 | ia64_issue_rate (void) |
2130b7fb BS |
7150 | { |
7151 | return 6; | |
7152 | } | |
7153 | ||
7154 | /* Helper function - like single_set, but look inside COND_EXEC. */ | |
7155 | ||
7156 | static rtx | |
9c808aad | 7157 | ia64_single_set (rtx insn) |
2130b7fb | 7158 | { |
30fa7e33 | 7159 | rtx x = PATTERN (insn), ret; |
2130b7fb BS |
7160 | if (GET_CODE (x) == COND_EXEC) |
7161 | x = COND_EXEC_CODE (x); | |
7162 | if (GET_CODE (x) == SET) | |
7163 | return x; | |
bdbe5b8d RH |
7164 | |
7165 | /* Special case here prologue_allocate_stack and epilogue_deallocate_stack. | |
7166 | Although they are not classical single set, the second set is there just | |
7167 | to protect it from moving past FP-relative stack accesses. */ | |
7168 | switch (recog_memoized (insn)) | |
30fa7e33 | 7169 | { |
bdbe5b8d RH |
7170 | case CODE_FOR_prologue_allocate_stack: |
7171 | case CODE_FOR_epilogue_deallocate_stack: | |
7172 | ret = XVECEXP (x, 0, 0); | |
7173 | break; | |
7174 | ||
7175 | default: | |
7176 | ret = single_set_2 (insn, x); | |
7177 | break; | |
30fa7e33 | 7178 | } |
bdbe5b8d | 7179 | |
30fa7e33 | 7180 | return ret; |
2130b7fb BS |
7181 | } |
7182 | ||
388092d5 AB |
7183 | /* Adjust the cost of a scheduling dependency. |
7184 | Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN. | |
7185 | COST is the current cost, DW is dependency weakness. */ | |
c237e94a | 7186 | static int |
388092d5 | 7187 | ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw) |
2130b7fb | 7188 | { |
388092d5 | 7189 | enum reg_note dep_type = (enum reg_note) dep_type1; |
2130b7fb BS |
7190 | enum attr_itanium_class dep_class; |
7191 | enum attr_itanium_class insn_class; | |
2130b7fb | 7192 | |
2130b7fb | 7193 | insn_class = ia64_safe_itanium_class (insn); |
30028c85 | 7194 | dep_class = ia64_safe_itanium_class (dep_insn); |
388092d5 AB |
7195 | |
7196 | /* Treat true memory dependencies separately. Ignore apparent true | |
7197 | dependence between store and call (call has a MEM inside a SYMBOL_REF). */ | |
7198 | if (dep_type == REG_DEP_TRUE | |
7199 | && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF) | |
7200 | && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL)) | |
7201 | return 0; | |
7202 | ||
7203 | if (dw == MIN_DEP_WEAK) | |
7204 | /* Store and load are likely to alias, use higher cost to avoid stall. */ | |
7205 | return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST); | |
7206 | else if (dw > MIN_DEP_WEAK) | |
7207 | { | |
7208 | /* Store and load are less likely to alias. */ | |
7209 | if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF) | |
7210 | /* Assume there will be no cache conflict for floating-point data. | |
7211 | For integer data, L1 conflict penalty is huge (17 cycles), so we | |
7212 | never assume it will not cause a conflict. */ | |
7213 | return 0; | |
7214 | else | |
7215 | return cost; | |
7216 | } | |
7217 | ||
7218 | if (dep_type != REG_DEP_OUTPUT) | |
7219 | return cost; | |
7220 | ||
30028c85 VM |
7221 | if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF |
7222 | || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF) | |
2130b7fb BS |
7223 | return 0; |
7224 | ||
2130b7fb BS |
7225 | return cost; |
7226 | } | |
7227 | ||
14d118d6 DM |
7228 | /* Like emit_insn_before, but skip cycle_display notes. |
7229 | ??? When cycle display notes are implemented, update this. */ | |
7230 | ||
7231 | static void | |
9c808aad | 7232 | ia64_emit_insn_before (rtx insn, rtx before) |
14d118d6 DM |
7233 | { |
7234 | emit_insn_before (insn, before); | |
7235 | } | |
7236 | ||
30028c85 VM |
7237 | /* The following function marks insns who produce addresses for load |
7238 | and store insns. Such insns will be placed into M slots because it | |
7239 | decrease latency time for Itanium1 (see function | |
7240 | `ia64_produce_address_p' and the DFA descriptions). */ | |
2130b7fb BS |
7241 | |
7242 | static void | |
9c808aad | 7243 | ia64_dependencies_evaluation_hook (rtx head, rtx tail) |
2130b7fb | 7244 | { |
b198261f | 7245 | rtx insn, next, next_tail; |
9c808aad | 7246 | |
f12b785d RH |
7247 | /* Before reload, which_alternative is not set, which means that |
7248 | ia64_safe_itanium_class will produce wrong results for (at least) | |
7249 | move instructions. */ | |
7250 | if (!reload_completed) | |
7251 | return; | |
7252 | ||
30028c85 VM |
7253 | next_tail = NEXT_INSN (tail); |
7254 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7255 | if (INSN_P (insn)) | |
7256 | insn->call = 0; | |
7257 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7258 | if (INSN_P (insn) | |
7259 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU) | |
7260 | { | |
e2f6ff94 MK |
7261 | sd_iterator_def sd_it; |
7262 | dep_t dep; | |
7263 | bool has_mem_op_consumer_p = false; | |
b198261f | 7264 | |
e2f6ff94 | 7265 | FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) |
30028c85 | 7266 | { |
a71aef0b JB |
7267 | enum attr_itanium_class c; |
7268 | ||
e2f6ff94 | 7269 | if (DEP_TYPE (dep) != REG_DEP_TRUE) |
f12b785d | 7270 | continue; |
b198261f | 7271 | |
e2f6ff94 | 7272 | next = DEP_CON (dep); |
a71aef0b JB |
7273 | c = ia64_safe_itanium_class (next); |
7274 | if ((c == ITANIUM_CLASS_ST | |
7275 | || c == ITANIUM_CLASS_STF) | |
30028c85 | 7276 | && ia64_st_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7277 | { |
7278 | has_mem_op_consumer_p = true; | |
7279 | break; | |
7280 | } | |
a71aef0b JB |
7281 | else if ((c == ITANIUM_CLASS_LD |
7282 | || c == ITANIUM_CLASS_FLD | |
7283 | || c == ITANIUM_CLASS_FLDP) | |
30028c85 | 7284 | && ia64_ld_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7285 | { |
7286 | has_mem_op_consumer_p = true; | |
7287 | break; | |
7288 | } | |
30028c85 | 7289 | } |
e2f6ff94 MK |
7290 | |
7291 | insn->call = has_mem_op_consumer_p; | |
30028c85 VM |
7292 | } |
7293 | } | |
2130b7fb | 7294 | |
30028c85 | 7295 | /* We're beginning a new block. Initialize data structures as necessary. */ |
2130b7fb | 7296 | |
30028c85 | 7297 | static void |
9c808aad AJ |
7298 | ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
7299 | int sched_verbose ATTRIBUTE_UNUSED, | |
7300 | int max_ready ATTRIBUTE_UNUSED) | |
30028c85 VM |
7301 | { |
7302 | #ifdef ENABLE_CHECKING | |
7303 | rtx insn; | |
9c808aad | 7304 | |
388092d5 | 7305 | if (!sel_sched_p () && reload_completed) |
30028c85 VM |
7306 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
7307 | insn != current_sched_info->next_tail; | |
7308 | insn = NEXT_INSN (insn)) | |
e820471b | 7309 | gcc_assert (!SCHED_GROUP_P (insn)); |
30028c85 VM |
7310 | #endif |
7311 | last_scheduled_insn = NULL_RTX; | |
7312 | init_insn_group_barriers (); | |
388092d5 AB |
7313 | |
7314 | current_cycle = 0; | |
7315 | memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
2130b7fb BS |
7316 | } |
7317 | ||
048d0d36 MK |
7318 | /* We're beginning a scheduling pass. Check assertion. */ |
7319 | ||
7320 | static void | |
7321 | ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, | |
7322 | int sched_verbose ATTRIBUTE_UNUSED, | |
7323 | int max_ready ATTRIBUTE_UNUSED) | |
7324 | { | |
388092d5 | 7325 | gcc_assert (pending_data_specs == 0); |
048d0d36 MK |
7326 | } |
7327 | ||
7328 | /* Scheduling pass is now finished. Free/reset static variable. */ | |
7329 | static void | |
7330 | ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
7331 | int sched_verbose ATTRIBUTE_UNUSED) | |
7332 | { | |
388092d5 AB |
7333 | gcc_assert (pending_data_specs == 0); |
7334 | } | |
7335 | ||
7336 | /* Return TRUE if INSN is a load (either normal or speculative, but not a | |
7337 | speculation check), FALSE otherwise. */ | |
7338 | static bool | |
7339 | is_load_p (rtx insn) | |
7340 | { | |
7341 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7342 | ||
7343 | return | |
7344 | ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD) | |
7345 | && get_attr_check_load (insn) == CHECK_LOAD_NO); | |
7346 | } | |
7347 | ||
7348 | /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array | |
7349 | (taking account for 3-cycle cache reference postponing for stores: Intel | |
7350 | Itanium 2 Reference Manual for Software Development and Optimization, | |
7351 | 6.7.3.1). */ | |
7352 | static void | |
7353 | record_memory_reference (rtx insn) | |
7354 | { | |
7355 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7356 | ||
7357 | switch (insn_class) { | |
7358 | case ITANIUM_CLASS_FLD: | |
7359 | case ITANIUM_CLASS_LD: | |
7360 | mem_ops_in_group[current_cycle % 4]++; | |
7361 | break; | |
7362 | case ITANIUM_CLASS_STF: | |
7363 | case ITANIUM_CLASS_ST: | |
7364 | mem_ops_in_group[(current_cycle + 3) % 4]++; | |
7365 | break; | |
7366 | default:; | |
7367 | } | |
048d0d36 MK |
7368 | } |
7369 | ||
30028c85 VM |
7370 | /* We are about to being issuing insns for this clock cycle. |
7371 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7372 | |
30028c85 | 7373 | static int |
9c808aad | 7374 | ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, |
388092d5 | 7375 | int *pn_ready, int clock_var, |
9c808aad | 7376 | int reorder_type) |
2130b7fb | 7377 | { |
30028c85 VM |
7378 | int n_asms; |
7379 | int n_ready = *pn_ready; | |
7380 | rtx *e_ready = ready + n_ready; | |
7381 | rtx *insnp; | |
2130b7fb | 7382 | |
30028c85 VM |
7383 | if (sched_verbose) |
7384 | fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type); | |
2130b7fb | 7385 | |
30028c85 | 7386 | if (reorder_type == 0) |
2130b7fb | 7387 | { |
30028c85 VM |
7388 | /* First, move all USEs, CLOBBERs and other crud out of the way. */ |
7389 | n_asms = 0; | |
7390 | for (insnp = ready; insnp < e_ready; insnp++) | |
7391 | if (insnp < e_ready) | |
7392 | { | |
7393 | rtx insn = *insnp; | |
7394 | enum attr_type t = ia64_safe_type (insn); | |
7395 | if (t == TYPE_UNKNOWN) | |
7396 | { | |
7397 | if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
7398 | || asm_noperands (PATTERN (insn)) >= 0) | |
7399 | { | |
7400 | rtx lowest = ready[n_asms]; | |
7401 | ready[n_asms] = insn; | |
7402 | *insnp = lowest; | |
7403 | n_asms++; | |
7404 | } | |
7405 | else | |
7406 | { | |
7407 | rtx highest = ready[n_ready - 1]; | |
7408 | ready[n_ready - 1] = insn; | |
7409 | *insnp = highest; | |
7410 | return 1; | |
7411 | } | |
7412 | } | |
7413 | } | |
98d2b17e | 7414 | |
30028c85 | 7415 | if (n_asms < n_ready) |
98d2b17e | 7416 | { |
30028c85 VM |
7417 | /* Some normal insns to process. Skip the asms. */ |
7418 | ready += n_asms; | |
7419 | n_ready -= n_asms; | |
98d2b17e | 7420 | } |
30028c85 VM |
7421 | else if (n_ready > 0) |
7422 | return 1; | |
2130b7fb BS |
7423 | } |
7424 | ||
30028c85 | 7425 | if (ia64_final_schedule) |
2130b7fb | 7426 | { |
30028c85 VM |
7427 | int deleted = 0; |
7428 | int nr_need_stop = 0; | |
7429 | ||
7430 | for (insnp = ready; insnp < e_ready; insnp++) | |
c1bc6ca8 | 7431 | if (safe_group_barrier_needed (*insnp)) |
30028c85 | 7432 | nr_need_stop++; |
9c808aad | 7433 | |
30028c85 VM |
7434 | if (reorder_type == 1 && n_ready == nr_need_stop) |
7435 | return 0; | |
7436 | if (reorder_type == 0) | |
7437 | return 1; | |
7438 | insnp = e_ready; | |
7439 | /* Move down everything that needs a stop bit, preserving | |
7440 | relative order. */ | |
7441 | while (insnp-- > ready + deleted) | |
7442 | while (insnp >= ready + deleted) | |
7443 | { | |
7444 | rtx insn = *insnp; | |
c1bc6ca8 | 7445 | if (! safe_group_barrier_needed (insn)) |
30028c85 VM |
7446 | break; |
7447 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7448 | *ready = insn; | |
7449 | deleted++; | |
7450 | } | |
7451 | n_ready -= deleted; | |
7452 | ready += deleted; | |
2130b7fb | 7453 | } |
2130b7fb | 7454 | |
388092d5 AB |
7455 | current_cycle = clock_var; |
7456 | if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns) | |
7457 | { | |
7458 | int moved = 0; | |
7459 | ||
7460 | insnp = e_ready; | |
7461 | /* Move down loads/stores, preserving relative order. */ | |
7462 | while (insnp-- > ready + moved) | |
7463 | while (insnp >= ready + moved) | |
7464 | { | |
7465 | rtx insn = *insnp; | |
7466 | if (! is_load_p (insn)) | |
7467 | break; | |
7468 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7469 | *ready = insn; | |
7470 | moved++; | |
7471 | } | |
7472 | n_ready -= moved; | |
7473 | ready += moved; | |
7474 | } | |
7475 | ||
30028c85 | 7476 | return 1; |
2130b7fb | 7477 | } |
6b6c1201 | 7478 | |
30028c85 VM |
7479 | /* We are about to being issuing insns for this clock cycle. Override |
7480 | the default sort algorithm to better slot instructions. */ | |
c65ebc55 | 7481 | |
30028c85 | 7482 | static int |
9c808aad AJ |
7483 | ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready, |
7484 | int clock_var) | |
2130b7fb | 7485 | { |
30028c85 VM |
7486 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, |
7487 | pn_ready, clock_var, 0); | |
2130b7fb BS |
7488 | } |
7489 | ||
30028c85 VM |
7490 | /* Like ia64_sched_reorder, but called after issuing each insn. |
7491 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7492 | |
30028c85 | 7493 | static int |
9c808aad AJ |
7494 | ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
7495 | int sched_verbose ATTRIBUTE_UNUSED, rtx *ready, | |
7496 | int *pn_ready, int clock_var) | |
30028c85 | 7497 | { |
30028c85 VM |
7498 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready, |
7499 | clock_var, 1); | |
2130b7fb BS |
7500 | } |
7501 | ||
30028c85 VM |
7502 | /* We are about to issue INSN. Return the number of insns left on the |
7503 | ready queue that can be issued this cycle. */ | |
2130b7fb | 7504 | |
30028c85 | 7505 | static int |
9c808aad AJ |
7506 | ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
7507 | int sched_verbose ATTRIBUTE_UNUSED, | |
7508 | rtx insn ATTRIBUTE_UNUSED, | |
7509 | int can_issue_more ATTRIBUTE_UNUSED) | |
2130b7fb | 7510 | { |
388092d5 | 7511 | if (sched_deps_info->generate_spec_deps && !sel_sched_p ()) |
048d0d36 | 7512 | /* Modulo scheduling does not extend h_i_d when emitting |
388092d5 | 7513 | new instructions. Don't use h_i_d, if we don't have to. */ |
048d0d36 MK |
7514 | { |
7515 | if (DONE_SPEC (insn) & BEGIN_DATA) | |
7516 | pending_data_specs++; | |
7517 | if (CHECK_SPEC (insn) & BEGIN_DATA) | |
7518 | pending_data_specs--; | |
7519 | } | |
7520 | ||
b5b8b0ac AO |
7521 | if (DEBUG_INSN_P (insn)) |
7522 | return 1; | |
7523 | ||
30028c85 VM |
7524 | last_scheduled_insn = insn; |
7525 | memcpy (prev_cycle_state, curr_state, dfa_state_size); | |
7526 | if (reload_completed) | |
2130b7fb | 7527 | { |
c1bc6ca8 | 7528 | int needed = group_barrier_needed (insn); |
e820471b NS |
7529 | |
7530 | gcc_assert (!needed); | |
30028c85 VM |
7531 | if (GET_CODE (insn) == CALL_INSN) |
7532 | init_insn_group_barriers (); | |
7533 | stops_p [INSN_UID (insn)] = stop_before_p; | |
7534 | stop_before_p = 0; | |
388092d5 AB |
7535 | |
7536 | record_memory_reference (insn); | |
2130b7fb | 7537 | } |
30028c85 VM |
7538 | return 1; |
7539 | } | |
c65ebc55 | 7540 | |
30028c85 VM |
7541 | /* We are choosing insn from the ready queue. Return nonzero if INSN |
7542 | can be chosen. */ | |
c65ebc55 | 7543 | |
30028c85 | 7544 | static int |
9c808aad | 7545 | ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn) |
30028c85 | 7546 | { |
388092d5 | 7547 | gcc_assert (insn && INSN_P (insn)); |
048d0d36 MK |
7548 | return ((!reload_completed |
7549 | || !safe_group_barrier_needed (insn)) | |
388092d5 AB |
7550 | && ia64_first_cycle_multipass_dfa_lookahead_guard_spec (insn) |
7551 | && (!mflag_sched_mem_insns_hard_limit | |
7552 | || !is_load_p (insn) | |
7553 | || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns)); | |
048d0d36 MK |
7554 | } |
7555 | ||
7556 | /* We are choosing insn from the ready queue. Return nonzero if INSN | |
7557 | can be chosen. */ | |
7558 | ||
7559 | static bool | |
3101faab | 7560 | ia64_first_cycle_multipass_dfa_lookahead_guard_spec (const_rtx insn) |
048d0d36 MK |
7561 | { |
7562 | gcc_assert (insn && INSN_P (insn)); | |
7563 | /* Size of ALAT is 32. As far as we perform conservative data speculation, | |
7564 | we keep ALAT half-empty. */ | |
7565 | return (pending_data_specs < 16 | |
7566 | || !(TODO_SPEC (insn) & BEGIN_DATA)); | |
2130b7fb BS |
7567 | } |
7568 | ||
30028c85 VM |
7569 | /* The following variable value is pseudo-insn used by the DFA insn |
7570 | scheduler to change the DFA state when the simulated clock is | |
7571 | increased. */ | |
2130b7fb | 7572 | |
30028c85 | 7573 | static rtx dfa_pre_cycle_insn; |
2130b7fb | 7574 | |
388092d5 AB |
7575 | /* Returns 1 when a meaningful insn was scheduled between the last group |
7576 | barrier and LAST. */ | |
7577 | static int | |
7578 | scheduled_good_insn (rtx last) | |
7579 | { | |
7580 | if (last && recog_memoized (last) >= 0) | |
7581 | return 1; | |
7582 | ||
7583 | for ( ; | |
7584 | last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last) | |
7585 | && !stops_p[INSN_UID (last)]; | |
7586 | last = PREV_INSN (last)) | |
7587 | /* We could hit a NOTE_INSN_DELETED here which is actually outside | |
7588 | the ebb we're scheduling. */ | |
7589 | if (INSN_P (last) && recog_memoized (last) >= 0) | |
7590 | return 1; | |
7591 | ||
7592 | return 0; | |
7593 | } | |
7594 | ||
1e5f1716 | 7595 | /* We are about to being issuing INSN. Return nonzero if we cannot |
30028c85 VM |
7596 | issue it on given cycle CLOCK and return zero if we should not sort |
7597 | the ready queue on the next clock start. */ | |
2130b7fb BS |
7598 | |
7599 | static int | |
9c808aad AJ |
7600 | ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock, |
7601 | int clock, int *sort_p) | |
2130b7fb | 7602 | { |
e820471b | 7603 | gcc_assert (insn && INSN_P (insn)); |
b5b8b0ac AO |
7604 | |
7605 | if (DEBUG_INSN_P (insn)) | |
7606 | return 0; | |
7607 | ||
388092d5 AB |
7608 | /* When a group barrier is needed for insn, last_scheduled_insn |
7609 | should be set. */ | |
7610 | gcc_assert (!(reload_completed && safe_group_barrier_needed (insn)) | |
7611 | || last_scheduled_insn); | |
7612 | ||
7613 | if ((reload_completed | |
7614 | && (safe_group_barrier_needed (insn) | |
7615 | || (mflag_sched_stop_bits_after_every_cycle | |
7616 | && last_clock != clock | |
7617 | && last_scheduled_insn | |
7618 | && scheduled_good_insn (last_scheduled_insn)))) | |
30028c85 VM |
7619 | || (last_scheduled_insn |
7620 | && (GET_CODE (last_scheduled_insn) == CALL_INSN | |
7b84aac0 | 7621 | || unknown_for_bundling_p (last_scheduled_insn)))) |
2130b7fb | 7622 | { |
30028c85 | 7623 | init_insn_group_barriers (); |
388092d5 | 7624 | |
30028c85 VM |
7625 | if (verbose && dump) |
7626 | fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn), | |
7627 | last_clock == clock ? " + cycle advance" : ""); | |
388092d5 | 7628 | |
30028c85 | 7629 | stop_before_p = 1; |
388092d5 AB |
7630 | current_cycle = clock; |
7631 | mem_ops_in_group[current_cycle % 4] = 0; | |
7632 | ||
30028c85 | 7633 | if (last_clock == clock) |
2130b7fb | 7634 | { |
30028c85 VM |
7635 | state_transition (curr_state, dfa_stop_insn); |
7636 | if (TARGET_EARLY_STOP_BITS) | |
7637 | *sort_p = (last_scheduled_insn == NULL_RTX | |
7638 | || GET_CODE (last_scheduled_insn) != CALL_INSN); | |
7639 | else | |
7640 | *sort_p = 0; | |
7641 | return 1; | |
7642 | } | |
388092d5 AB |
7643 | |
7644 | if (last_scheduled_insn) | |
25069b42 | 7645 | { |
7b84aac0 | 7646 | if (unknown_for_bundling_p (last_scheduled_insn)) |
388092d5 AB |
7647 | state_reset (curr_state); |
7648 | else | |
7649 | { | |
7650 | memcpy (curr_state, prev_cycle_state, dfa_state_size); | |
7651 | state_transition (curr_state, dfa_stop_insn); | |
7652 | state_transition (curr_state, dfa_pre_cycle_insn); | |
7653 | state_transition (curr_state, NULL); | |
7654 | } | |
25069b42 | 7655 | } |
30028c85 | 7656 | } |
30028c85 | 7657 | return 0; |
2130b7fb BS |
7658 | } |
7659 | ||
048d0d36 MK |
7660 | /* Implement targetm.sched.h_i_d_extended hook. |
7661 | Extend internal data structures. */ | |
7662 | static void | |
7663 | ia64_h_i_d_extended (void) | |
7664 | { | |
048d0d36 MK |
7665 | if (stops_p != NULL) |
7666 | { | |
388092d5 | 7667 | int new_clocks_length = get_max_uid () * 3 / 2; |
5ead67f6 | 7668 | stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1); |
048d0d36 MK |
7669 | clocks_length = new_clocks_length; |
7670 | } | |
7671 | } | |
388092d5 AB |
7672 | \f |
7673 | ||
7674 | /* This structure describes the data used by the backend to guide scheduling. | |
7675 | When the current scheduling point is switched, this data should be saved | |
7676 | and restored later, if the scheduler returns to this point. */ | |
7677 | struct _ia64_sched_context | |
7678 | { | |
7679 | state_t prev_cycle_state; | |
7680 | rtx last_scheduled_insn; | |
7681 | struct reg_write_state rws_sum[NUM_REGS]; | |
7682 | struct reg_write_state rws_insn[NUM_REGS]; | |
7683 | int first_instruction; | |
7684 | int pending_data_specs; | |
7685 | int current_cycle; | |
7686 | char mem_ops_in_group[4]; | |
7687 | }; | |
7688 | typedef struct _ia64_sched_context *ia64_sched_context_t; | |
7689 | ||
7690 | /* Allocates a scheduling context. */ | |
7691 | static void * | |
7692 | ia64_alloc_sched_context (void) | |
7693 | { | |
7694 | return xmalloc (sizeof (struct _ia64_sched_context)); | |
7695 | } | |
7696 | ||
7697 | /* Initializes the _SC context with clean data, if CLEAN_P, and from | |
7698 | the global context otherwise. */ | |
7699 | static void | |
7700 | ia64_init_sched_context (void *_sc, bool clean_p) | |
7701 | { | |
7702 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7703 | ||
7704 | sc->prev_cycle_state = xmalloc (dfa_state_size); | |
7705 | if (clean_p) | |
7706 | { | |
7707 | state_reset (sc->prev_cycle_state); | |
7708 | sc->last_scheduled_insn = NULL_RTX; | |
7709 | memset (sc->rws_sum, 0, sizeof (rws_sum)); | |
7710 | memset (sc->rws_insn, 0, sizeof (rws_insn)); | |
7711 | sc->first_instruction = 1; | |
7712 | sc->pending_data_specs = 0; | |
7713 | sc->current_cycle = 0; | |
7714 | memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
7715 | } | |
7716 | else | |
7717 | { | |
7718 | memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size); | |
7719 | sc->last_scheduled_insn = last_scheduled_insn; | |
7720 | memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum)); | |
7721 | memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn)); | |
7722 | sc->first_instruction = first_instruction; | |
7723 | sc->pending_data_specs = pending_data_specs; | |
7724 | sc->current_cycle = current_cycle; | |
7725 | memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7726 | } | |
7727 | } | |
7728 | ||
7729 | /* Sets the global scheduling context to the one pointed to by _SC. */ | |
7730 | static void | |
7731 | ia64_set_sched_context (void *_sc) | |
7732 | { | |
7733 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7734 | ||
7735 | gcc_assert (sc != NULL); | |
7736 | ||
7737 | memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size); | |
7738 | last_scheduled_insn = sc->last_scheduled_insn; | |
7739 | memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum)); | |
7740 | memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn)); | |
7741 | first_instruction = sc->first_instruction; | |
7742 | pending_data_specs = sc->pending_data_specs; | |
7743 | current_cycle = sc->current_cycle; | |
7744 | memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7745 | } | |
7746 | ||
7747 | /* Clears the data in the _SC scheduling context. */ | |
7748 | static void | |
7749 | ia64_clear_sched_context (void *_sc) | |
7750 | { | |
7751 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7752 | ||
7753 | free (sc->prev_cycle_state); | |
7754 | sc->prev_cycle_state = NULL; | |
7755 | } | |
7756 | ||
7757 | /* Frees the _SC scheduling context. */ | |
7758 | static void | |
7759 | ia64_free_sched_context (void *_sc) | |
7760 | { | |
7761 | gcc_assert (_sc != NULL); | |
7762 | ||
7763 | free (_sc); | |
7764 | } | |
7765 | ||
7766 | typedef rtx (* gen_func_t) (rtx, rtx); | |
7767 | ||
7768 | /* Return a function that will generate a load of mode MODE_NO | |
7769 | with speculation types TS. */ | |
7770 | static gen_func_t | |
7771 | get_spec_load_gen_function (ds_t ts, int mode_no) | |
7772 | { | |
7773 | static gen_func_t gen_ld_[] = { | |
7774 | gen_movbi, | |
7775 | gen_movqi_internal, | |
7776 | gen_movhi_internal, | |
7777 | gen_movsi_internal, | |
7778 | gen_movdi_internal, | |
7779 | gen_movsf_internal, | |
7780 | gen_movdf_internal, | |
7781 | gen_movxf_internal, | |
7782 | gen_movti_internal, | |
7783 | gen_zero_extendqidi2, | |
7784 | gen_zero_extendhidi2, | |
7785 | gen_zero_extendsidi2, | |
7786 | }; | |
7787 | ||
7788 | static gen_func_t gen_ld_a[] = { | |
7789 | gen_movbi_advanced, | |
7790 | gen_movqi_advanced, | |
7791 | gen_movhi_advanced, | |
7792 | gen_movsi_advanced, | |
7793 | gen_movdi_advanced, | |
7794 | gen_movsf_advanced, | |
7795 | gen_movdf_advanced, | |
7796 | gen_movxf_advanced, | |
7797 | gen_movti_advanced, | |
7798 | gen_zero_extendqidi2_advanced, | |
7799 | gen_zero_extendhidi2_advanced, | |
7800 | gen_zero_extendsidi2_advanced, | |
7801 | }; | |
7802 | static gen_func_t gen_ld_s[] = { | |
7803 | gen_movbi_speculative, | |
7804 | gen_movqi_speculative, | |
7805 | gen_movhi_speculative, | |
7806 | gen_movsi_speculative, | |
7807 | gen_movdi_speculative, | |
7808 | gen_movsf_speculative, | |
7809 | gen_movdf_speculative, | |
7810 | gen_movxf_speculative, | |
7811 | gen_movti_speculative, | |
7812 | gen_zero_extendqidi2_speculative, | |
7813 | gen_zero_extendhidi2_speculative, | |
7814 | gen_zero_extendsidi2_speculative, | |
7815 | }; | |
7816 | static gen_func_t gen_ld_sa[] = { | |
7817 | gen_movbi_speculative_advanced, | |
7818 | gen_movqi_speculative_advanced, | |
7819 | gen_movhi_speculative_advanced, | |
7820 | gen_movsi_speculative_advanced, | |
7821 | gen_movdi_speculative_advanced, | |
7822 | gen_movsf_speculative_advanced, | |
7823 | gen_movdf_speculative_advanced, | |
7824 | gen_movxf_speculative_advanced, | |
7825 | gen_movti_speculative_advanced, | |
7826 | gen_zero_extendqidi2_speculative_advanced, | |
7827 | gen_zero_extendhidi2_speculative_advanced, | |
7828 | gen_zero_extendsidi2_speculative_advanced, | |
7829 | }; | |
7830 | static gen_func_t gen_ld_s_a[] = { | |
7831 | gen_movbi_speculative_a, | |
7832 | gen_movqi_speculative_a, | |
7833 | gen_movhi_speculative_a, | |
7834 | gen_movsi_speculative_a, | |
7835 | gen_movdi_speculative_a, | |
7836 | gen_movsf_speculative_a, | |
7837 | gen_movdf_speculative_a, | |
7838 | gen_movxf_speculative_a, | |
7839 | gen_movti_speculative_a, | |
7840 | gen_zero_extendqidi2_speculative_a, | |
7841 | gen_zero_extendhidi2_speculative_a, | |
7842 | gen_zero_extendsidi2_speculative_a, | |
7843 | }; | |
7844 | ||
7845 | gen_func_t *gen_ld; | |
7846 | ||
7847 | if (ts & BEGIN_DATA) | |
7848 | { | |
7849 | if (ts & BEGIN_CONTROL) | |
7850 | gen_ld = gen_ld_sa; | |
7851 | else | |
7852 | gen_ld = gen_ld_a; | |
7853 | } | |
7854 | else if (ts & BEGIN_CONTROL) | |
7855 | { | |
7856 | if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL) | |
7857 | || ia64_needs_block_p (ts)) | |
7858 | gen_ld = gen_ld_s; | |
7859 | else | |
7860 | gen_ld = gen_ld_s_a; | |
7861 | } | |
7862 | else if (ts == 0) | |
7863 | gen_ld = gen_ld_; | |
7864 | else | |
7865 | gcc_unreachable (); | |
7866 | ||
7867 | return gen_ld[mode_no]; | |
7868 | } | |
048d0d36 MK |
7869 | |
7870 | /* Constants that help mapping 'enum machine_mode' to int. */ | |
7871 | enum SPEC_MODES | |
7872 | { | |
7873 | SPEC_MODE_INVALID = -1, | |
7874 | SPEC_MODE_FIRST = 0, | |
7875 | SPEC_MODE_FOR_EXTEND_FIRST = 1, | |
7876 | SPEC_MODE_FOR_EXTEND_LAST = 3, | |
7877 | SPEC_MODE_LAST = 8 | |
7878 | }; | |
7879 | ||
388092d5 AB |
7880 | enum |
7881 | { | |
7882 | /* Offset to reach ZERO_EXTEND patterns. */ | |
7883 | SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1 | |
7884 | }; | |
7885 | ||
048d0d36 MK |
7886 | /* Return index of the MODE. */ |
7887 | static int | |
7888 | ia64_mode_to_int (enum machine_mode mode) | |
7889 | { | |
7890 | switch (mode) | |
7891 | { | |
7892 | case BImode: return 0; /* SPEC_MODE_FIRST */ | |
7893 | case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */ | |
7894 | case HImode: return 2; | |
7895 | case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */ | |
7896 | case DImode: return 4; | |
7897 | case SFmode: return 5; | |
7898 | case DFmode: return 6; | |
7899 | case XFmode: return 7; | |
7900 | case TImode: | |
7901 | /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not | |
7902 | mentioned in itanium[12].md. Predicate fp_register_operand also | |
7903 | needs to be defined. Bottom line: better disable for now. */ | |
7904 | return SPEC_MODE_INVALID; | |
7905 | default: return SPEC_MODE_INVALID; | |
7906 | } | |
7907 | } | |
7908 | ||
7909 | /* Provide information about speculation capabilities. */ | |
7910 | static void | |
7911 | ia64_set_sched_flags (spec_info_t spec_info) | |
7912 | { | |
7913 | unsigned int *flags = &(current_sched_info->flags); | |
7914 | ||
7915 | if (*flags & SCHED_RGN | |
388092d5 AB |
7916 | || *flags & SCHED_EBB |
7917 | || *flags & SEL_SCHED) | |
048d0d36 MK |
7918 | { |
7919 | int mask = 0; | |
7920 | ||
a57aee2a | 7921 | if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0) |
388092d5 | 7922 | || (mflag_sched_ar_data_spec && reload_completed)) |
048d0d36 MK |
7923 | { |
7924 | mask |= BEGIN_DATA; | |
388092d5 AB |
7925 | |
7926 | if (!sel_sched_p () | |
7927 | && ((mflag_sched_br_in_data_spec && !reload_completed) | |
7928 | || (mflag_sched_ar_in_data_spec && reload_completed))) | |
048d0d36 MK |
7929 | mask |= BE_IN_DATA; |
7930 | } | |
7931 | ||
388092d5 AB |
7932 | if (mflag_sched_control_spec |
7933 | && (!sel_sched_p () | |
7934 | || reload_completed)) | |
048d0d36 MK |
7935 | { |
7936 | mask |= BEGIN_CONTROL; | |
7937 | ||
388092d5 | 7938 | if (!sel_sched_p () && mflag_sched_in_control_spec) |
048d0d36 MK |
7939 | mask |= BE_IN_CONTROL; |
7940 | } | |
7941 | ||
7ab5df48 AB |
7942 | spec_info->mask = mask; |
7943 | ||
048d0d36 MK |
7944 | if (mask) |
7945 | { | |
6fb5fa3c DB |
7946 | *flags |= USE_DEPS_LIST | DO_SPECULATION; |
7947 | ||
7948 | if (mask & BE_IN_SPEC) | |
7949 | *flags |= NEW_BBS; | |
048d0d36 | 7950 | |
048d0d36 MK |
7951 | spec_info->flags = 0; |
7952 | ||
7953 | if ((mask & DATA_SPEC) && mflag_sched_prefer_non_data_spec_insns) | |
7954 | spec_info->flags |= PREFER_NON_DATA_SPEC; | |
7955 | ||
388092d5 | 7956 | if (mask & CONTROL_SPEC) |
048d0d36 | 7957 | { |
388092d5 AB |
7958 | if (mflag_sched_prefer_non_control_spec_insns) |
7959 | spec_info->flags |= PREFER_NON_CONTROL_SPEC; | |
7960 | ||
7961 | if (sel_sched_p () && mflag_sel_sched_dont_check_control_spec) | |
7962 | spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL; | |
048d0d36 | 7963 | } |
388092d5 AB |
7964 | |
7965 | if (sched_verbose >= 1) | |
7966 | spec_info->dump = sched_dump; | |
048d0d36 MK |
7967 | else |
7968 | spec_info->dump = 0; | |
7969 | ||
7970 | if (mflag_sched_count_spec_in_critical_path) | |
7971 | spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; | |
7972 | } | |
7973 | } | |
cd510f15 AM |
7974 | else |
7975 | spec_info->mask = 0; | |
048d0d36 MK |
7976 | } |
7977 | ||
388092d5 AB |
7978 | /* If INSN is an appropriate load return its mode. |
7979 | Return -1 otherwise. */ | |
048d0d36 | 7980 | static int |
388092d5 AB |
7981 | get_mode_no_for_insn (rtx insn) |
7982 | { | |
7983 | rtx reg, mem, mode_rtx; | |
7984 | int mode_no; | |
048d0d36 | 7985 | bool extend_p; |
048d0d36 | 7986 | |
388092d5 | 7987 | extract_insn_cached (insn); |
048d0d36 | 7988 | |
388092d5 AB |
7989 | /* We use WHICH_ALTERNATIVE only after reload. This will |
7990 | guarantee that reload won't touch a speculative insn. */ | |
f6ec1d11 | 7991 | |
388092d5 | 7992 | if (recog_data.n_operands != 2) |
048d0d36 MK |
7993 | return -1; |
7994 | ||
388092d5 AB |
7995 | reg = recog_data.operand[0]; |
7996 | mem = recog_data.operand[1]; | |
f6ec1d11 | 7997 | |
388092d5 AB |
7998 | /* We should use MEM's mode since REG's mode in presence of |
7999 | ZERO_EXTEND will always be DImode. */ | |
8000 | if (get_attr_speculable1 (insn) == SPECULABLE1_YES) | |
8001 | /* Process non-speculative ld. */ | |
8002 | { | |
8003 | if (!reload_completed) | |
8004 | { | |
8005 | /* Do not speculate into regs like ar.lc. */ | |
8006 | if (!REG_P (reg) || AR_REGNO_P (REGNO (reg))) | |
8007 | return -1; | |
8008 | ||
8009 | if (!MEM_P (mem)) | |
8010 | return -1; | |
8011 | ||
8012 | { | |
8013 | rtx mem_reg = XEXP (mem, 0); | |
8014 | ||
8015 | if (!REG_P (mem_reg)) | |
8016 | return -1; | |
8017 | } | |
8018 | ||
8019 | mode_rtx = mem; | |
8020 | } | |
8021 | else if (get_attr_speculable2 (insn) == SPECULABLE2_YES) | |
8022 | { | |
8023 | gcc_assert (REG_P (reg) && MEM_P (mem)); | |
8024 | mode_rtx = mem; | |
8025 | } | |
8026 | else | |
8027 | return -1; | |
8028 | } | |
8029 | else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES | |
8030 | || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES | |
8031 | || get_attr_check_load (insn) == CHECK_LOAD_YES) | |
8032 | /* Process speculative ld or ld.c. */ | |
048d0d36 | 8033 | { |
388092d5 AB |
8034 | gcc_assert (REG_P (reg) && MEM_P (mem)); |
8035 | mode_rtx = mem; | |
048d0d36 MK |
8036 | } |
8037 | else | |
048d0d36 | 8038 | { |
388092d5 | 8039 | enum attr_itanium_class attr_class = get_attr_itanium_class (insn); |
048d0d36 | 8040 | |
388092d5 AB |
8041 | if (attr_class == ITANIUM_CLASS_CHK_A |
8042 | || attr_class == ITANIUM_CLASS_CHK_S_I | |
8043 | || attr_class == ITANIUM_CLASS_CHK_S_F) | |
8044 | /* Process chk. */ | |
8045 | mode_rtx = reg; | |
8046 | else | |
8047 | return -1; | |
048d0d36 | 8048 | } |
f6ec1d11 | 8049 | |
388092d5 | 8050 | mode_no = ia64_mode_to_int (GET_MODE (mode_rtx)); |
f6ec1d11 | 8051 | |
388092d5 | 8052 | if (mode_no == SPEC_MODE_INVALID) |
048d0d36 MK |
8053 | return -1; |
8054 | ||
388092d5 AB |
8055 | extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx)); |
8056 | ||
8057 | if (extend_p) | |
8058 | { | |
8059 | if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no | |
8060 | && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)) | |
8061 | return -1; | |
f6ec1d11 | 8062 | |
388092d5 AB |
8063 | mode_no += SPEC_GEN_EXTEND_OFFSET; |
8064 | } | |
048d0d36 | 8065 | |
388092d5 | 8066 | return mode_no; |
048d0d36 MK |
8067 | } |
8068 | ||
388092d5 AB |
8069 | /* If X is an unspec part of a speculative load, return its code. |
8070 | Return -1 otherwise. */ | |
8071 | static int | |
8072 | get_spec_unspec_code (const_rtx x) | |
8073 | { | |
8074 | if (GET_CODE (x) != UNSPEC) | |
8075 | return -1; | |
048d0d36 | 8076 | |
048d0d36 | 8077 | { |
388092d5 | 8078 | int code; |
048d0d36 | 8079 | |
388092d5 | 8080 | code = XINT (x, 1); |
048d0d36 | 8081 | |
388092d5 AB |
8082 | switch (code) |
8083 | { | |
8084 | case UNSPEC_LDA: | |
8085 | case UNSPEC_LDS: | |
8086 | case UNSPEC_LDS_A: | |
8087 | case UNSPEC_LDSA: | |
8088 | return code; | |
048d0d36 | 8089 | |
388092d5 AB |
8090 | default: |
8091 | return -1; | |
8092 | } | |
8093 | } | |
8094 | } | |
048d0d36 | 8095 | |
388092d5 AB |
8096 | /* Implement skip_rtx_p hook. */ |
8097 | static bool | |
8098 | ia64_skip_rtx_p (const_rtx x) | |
8099 | { | |
8100 | return get_spec_unspec_code (x) != -1; | |
8101 | } | |
048d0d36 | 8102 | |
388092d5 AB |
8103 | /* If INSN is a speculative load, return its UNSPEC code. |
8104 | Return -1 otherwise. */ | |
8105 | static int | |
8106 | get_insn_spec_code (const_rtx insn) | |
8107 | { | |
8108 | rtx pat, reg, mem; | |
048d0d36 | 8109 | |
388092d5 | 8110 | pat = PATTERN (insn); |
048d0d36 | 8111 | |
388092d5 AB |
8112 | if (GET_CODE (pat) == COND_EXEC) |
8113 | pat = COND_EXEC_CODE (pat); | |
048d0d36 | 8114 | |
388092d5 AB |
8115 | if (GET_CODE (pat) != SET) |
8116 | return -1; | |
8117 | ||
8118 | reg = SET_DEST (pat); | |
8119 | if (!REG_P (reg)) | |
8120 | return -1; | |
8121 | ||
8122 | mem = SET_SRC (pat); | |
8123 | if (GET_CODE (mem) == ZERO_EXTEND) | |
8124 | mem = XEXP (mem, 0); | |
8125 | ||
8126 | return get_spec_unspec_code (mem); | |
8127 | } | |
8128 | ||
8129 | /* If INSN is a speculative load, return a ds with the speculation types. | |
8130 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8131 | static ds_t | |
8132 | ia64_get_insn_spec_ds (rtx insn) | |
8133 | { | |
8134 | int code = get_insn_spec_code (insn); | |
8135 | ||
8136 | switch (code) | |
048d0d36 | 8137 | { |
388092d5 AB |
8138 | case UNSPEC_LDA: |
8139 | return BEGIN_DATA; | |
048d0d36 | 8140 | |
388092d5 AB |
8141 | case UNSPEC_LDS: |
8142 | case UNSPEC_LDS_A: | |
8143 | return BEGIN_CONTROL; | |
048d0d36 | 8144 | |
388092d5 AB |
8145 | case UNSPEC_LDSA: |
8146 | return BEGIN_DATA | BEGIN_CONTROL; | |
048d0d36 | 8147 | |
388092d5 AB |
8148 | default: |
8149 | return 0; | |
048d0d36 | 8150 | } |
388092d5 AB |
8151 | } |
8152 | ||
8153 | /* If INSN is a speculative load return a ds with the speculation types that | |
8154 | will be checked. | |
8155 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8156 | static ds_t | |
8157 | ia64_get_insn_checked_ds (rtx insn) | |
8158 | { | |
8159 | int code = get_insn_spec_code (insn); | |
8160 | ||
8161 | switch (code) | |
048d0d36 | 8162 | { |
388092d5 AB |
8163 | case UNSPEC_LDA: |
8164 | return BEGIN_DATA | BEGIN_CONTROL; | |
8165 | ||
8166 | case UNSPEC_LDS: | |
8167 | return BEGIN_CONTROL; | |
8168 | ||
8169 | case UNSPEC_LDS_A: | |
8170 | case UNSPEC_LDSA: | |
8171 | return BEGIN_DATA | BEGIN_CONTROL; | |
8172 | ||
8173 | default: | |
8174 | return 0; | |
048d0d36 | 8175 | } |
388092d5 | 8176 | } |
048d0d36 | 8177 | |
388092d5 AB |
8178 | /* If GEN_P is true, calculate the index of needed speculation check and return |
8179 | speculative pattern for INSN with speculative mode TS, machine mode | |
8180 | MODE_NO and with ZERO_EXTEND (if EXTEND_P is true). | |
8181 | If GEN_P is false, just calculate the index of needed speculation check. */ | |
8182 | static rtx | |
8183 | ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no) | |
8184 | { | |
8185 | rtx pat, new_pat; | |
8186 | gen_func_t gen_load; | |
048d0d36 | 8187 | |
388092d5 | 8188 | gen_load = get_spec_load_gen_function (ts, mode_no); |
048d0d36 | 8189 | |
388092d5 AB |
8190 | new_pat = gen_load (copy_rtx (recog_data.operand[0]), |
8191 | copy_rtx (recog_data.operand[1])); | |
048d0d36 MK |
8192 | |
8193 | pat = PATTERN (insn); | |
8194 | if (GET_CODE (pat) == COND_EXEC) | |
388092d5 AB |
8195 | new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), |
8196 | new_pat); | |
048d0d36 MK |
8197 | |
8198 | return new_pat; | |
8199 | } | |
8200 | ||
048d0d36 | 8201 | static bool |
388092d5 AB |
8202 | insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED, |
8203 | ds_t ds ATTRIBUTE_UNUSED) | |
048d0d36 | 8204 | { |
388092d5 AB |
8205 | return false; |
8206 | } | |
048d0d36 | 8207 | |
388092d5 AB |
8208 | /* Implement targetm.sched.speculate_insn hook. |
8209 | Check if the INSN can be TS speculative. | |
8210 | If 'no' - return -1. | |
8211 | If 'yes' - generate speculative pattern in the NEW_PAT and return 1. | |
8212 | If current pattern of the INSN already provides TS speculation, | |
8213 | return 0. */ | |
8214 | static int | |
8215 | ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) | |
8216 | { | |
8217 | int mode_no; | |
8218 | int res; | |
8219 | ||
8220 | gcc_assert (!(ts & ~SPECULATIVE)); | |
048d0d36 | 8221 | |
388092d5 AB |
8222 | if (ia64_spec_check_p (insn)) |
8223 | return -1; | |
048d0d36 | 8224 | |
388092d5 AB |
8225 | if ((ts & BE_IN_SPEC) |
8226 | && !insn_can_be_in_speculative_p (insn, ts)) | |
8227 | return -1; | |
048d0d36 | 8228 | |
388092d5 | 8229 | mode_no = get_mode_no_for_insn (insn); |
048d0d36 | 8230 | |
388092d5 AB |
8231 | if (mode_no != SPEC_MODE_INVALID) |
8232 | { | |
8233 | if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts)) | |
8234 | res = 0; | |
8235 | else | |
8236 | { | |
8237 | res = 1; | |
8238 | *new_pat = ia64_gen_spec_load (insn, ts, mode_no); | |
8239 | } | |
8240 | } | |
8241 | else | |
8242 | res = -1; | |
048d0d36 | 8243 | |
388092d5 AB |
8244 | return res; |
8245 | } | |
048d0d36 | 8246 | |
388092d5 AB |
8247 | /* Return a function that will generate a check for speculation TS with mode |
8248 | MODE_NO. | |
8249 | If simple check is needed, pass true for SIMPLE_CHECK_P. | |
8250 | If clearing check is needed, pass true for CLEARING_CHECK_P. */ | |
8251 | static gen_func_t | |
8252 | get_spec_check_gen_function (ds_t ts, int mode_no, | |
8253 | bool simple_check_p, bool clearing_check_p) | |
8254 | { | |
8255 | static gen_func_t gen_ld_c_clr[] = { | |
048d0d36 MK |
8256 | gen_movbi_clr, |
8257 | gen_movqi_clr, | |
8258 | gen_movhi_clr, | |
8259 | gen_movsi_clr, | |
8260 | gen_movdi_clr, | |
8261 | gen_movsf_clr, | |
8262 | gen_movdf_clr, | |
8263 | gen_movxf_clr, | |
8264 | gen_movti_clr, | |
8265 | gen_zero_extendqidi2_clr, | |
8266 | gen_zero_extendhidi2_clr, | |
8267 | gen_zero_extendsidi2_clr, | |
388092d5 AB |
8268 | }; |
8269 | static gen_func_t gen_ld_c_nc[] = { | |
8270 | gen_movbi_nc, | |
8271 | gen_movqi_nc, | |
8272 | gen_movhi_nc, | |
8273 | gen_movsi_nc, | |
8274 | gen_movdi_nc, | |
8275 | gen_movsf_nc, | |
8276 | gen_movdf_nc, | |
8277 | gen_movxf_nc, | |
8278 | gen_movti_nc, | |
8279 | gen_zero_extendqidi2_nc, | |
8280 | gen_zero_extendhidi2_nc, | |
8281 | gen_zero_extendsidi2_nc, | |
8282 | }; | |
8283 | static gen_func_t gen_chk_a_clr[] = { | |
048d0d36 MK |
8284 | gen_advanced_load_check_clr_bi, |
8285 | gen_advanced_load_check_clr_qi, | |
8286 | gen_advanced_load_check_clr_hi, | |
8287 | gen_advanced_load_check_clr_si, | |
8288 | gen_advanced_load_check_clr_di, | |
8289 | gen_advanced_load_check_clr_sf, | |
8290 | gen_advanced_load_check_clr_df, | |
8291 | gen_advanced_load_check_clr_xf, | |
8292 | gen_advanced_load_check_clr_ti, | |
8293 | gen_advanced_load_check_clr_di, | |
8294 | gen_advanced_load_check_clr_di, | |
8295 | gen_advanced_load_check_clr_di, | |
388092d5 AB |
8296 | }; |
8297 | static gen_func_t gen_chk_a_nc[] = { | |
8298 | gen_advanced_load_check_nc_bi, | |
8299 | gen_advanced_load_check_nc_qi, | |
8300 | gen_advanced_load_check_nc_hi, | |
8301 | gen_advanced_load_check_nc_si, | |
8302 | gen_advanced_load_check_nc_di, | |
8303 | gen_advanced_load_check_nc_sf, | |
8304 | gen_advanced_load_check_nc_df, | |
8305 | gen_advanced_load_check_nc_xf, | |
8306 | gen_advanced_load_check_nc_ti, | |
8307 | gen_advanced_load_check_nc_di, | |
8308 | gen_advanced_load_check_nc_di, | |
8309 | gen_advanced_load_check_nc_di, | |
8310 | }; | |
8311 | static gen_func_t gen_chk_s[] = { | |
048d0d36 MK |
8312 | gen_speculation_check_bi, |
8313 | gen_speculation_check_qi, | |
8314 | gen_speculation_check_hi, | |
8315 | gen_speculation_check_si, | |
8316 | gen_speculation_check_di, | |
8317 | gen_speculation_check_sf, | |
8318 | gen_speculation_check_df, | |
8319 | gen_speculation_check_xf, | |
8320 | gen_speculation_check_ti, | |
8321 | gen_speculation_check_di, | |
8322 | gen_speculation_check_di, | |
388092d5 | 8323 | gen_speculation_check_di, |
048d0d36 MK |
8324 | }; |
8325 | ||
388092d5 | 8326 | gen_func_t *gen_check; |
048d0d36 | 8327 | |
388092d5 | 8328 | if (ts & BEGIN_DATA) |
048d0d36 | 8329 | { |
388092d5 AB |
8330 | /* We don't need recovery because even if this is ld.sa |
8331 | ALAT entry will be allocated only if NAT bit is set to zero. | |
8332 | So it is enough to use ld.c here. */ | |
8333 | ||
8334 | if (simple_check_p) | |
8335 | { | |
8336 | gcc_assert (mflag_sched_spec_ldc); | |
8337 | ||
8338 | if (clearing_check_p) | |
8339 | gen_check = gen_ld_c_clr; | |
8340 | else | |
8341 | gen_check = gen_ld_c_nc; | |
8342 | } | |
8343 | else | |
8344 | { | |
8345 | if (clearing_check_p) | |
8346 | gen_check = gen_chk_a_clr; | |
8347 | else | |
8348 | gen_check = gen_chk_a_nc; | |
8349 | } | |
048d0d36 | 8350 | } |
388092d5 | 8351 | else if (ts & BEGIN_CONTROL) |
048d0d36 | 8352 | { |
388092d5 AB |
8353 | if (simple_check_p) |
8354 | /* We might want to use ld.sa -> ld.c instead of | |
8355 | ld.s -> chk.s. */ | |
048d0d36 | 8356 | { |
388092d5 | 8357 | gcc_assert (!ia64_needs_block_p (ts)); |
048d0d36 | 8358 | |
388092d5 AB |
8359 | if (clearing_check_p) |
8360 | gen_check = gen_ld_c_clr; | |
8361 | else | |
8362 | gen_check = gen_ld_c_nc; | |
8363 | } | |
8364 | else | |
8365 | { | |
8366 | gen_check = gen_chk_s; | |
048d0d36 | 8367 | } |
388092d5 AB |
8368 | } |
8369 | else | |
8370 | gcc_unreachable (); | |
8371 | ||
8372 | gcc_assert (mode_no >= 0); | |
8373 | return gen_check[mode_no]; | |
8374 | } | |
8375 | ||
8376 | /* Return nonzero, if INSN needs branchy recovery check. */ | |
8377 | static bool | |
8378 | ia64_needs_block_p (ds_t ts) | |
8379 | { | |
8380 | if (ts & BEGIN_DATA) | |
8381 | return !mflag_sched_spec_ldc; | |
8382 | ||
8383 | gcc_assert ((ts & BEGIN_CONTROL) != 0); | |
048d0d36 | 8384 | |
388092d5 AB |
8385 | return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc); |
8386 | } | |
8387 | ||
8388 | /* Generate (or regenerate, if (MUTATE_P)) recovery check for INSN. | |
8389 | If (LABEL != 0 || MUTATE_P), generate branchy recovery check. | |
8390 | Otherwise, generate a simple check. */ | |
8391 | static rtx | |
8392 | ia64_gen_spec_check (rtx insn, rtx label, ds_t ds) | |
8393 | { | |
8394 | rtx op1, pat, check_pat; | |
8395 | gen_func_t gen_check; | |
8396 | int mode_no; | |
8397 | ||
8398 | mode_no = get_mode_no_for_insn (insn); | |
8399 | gcc_assert (mode_no >= 0); | |
8400 | ||
8401 | if (label) | |
8402 | op1 = label; | |
8403 | else | |
8404 | { | |
8405 | gcc_assert (!ia64_needs_block_p (ds)); | |
8406 | op1 = copy_rtx (recog_data.operand[1]); | |
048d0d36 | 8407 | } |
388092d5 AB |
8408 | |
8409 | gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX, | |
8410 | true); | |
048d0d36 | 8411 | |
388092d5 | 8412 | check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1); |
048d0d36 MK |
8413 | |
8414 | pat = PATTERN (insn); | |
8415 | if (GET_CODE (pat) == COND_EXEC) | |
8416 | check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), | |
8417 | check_pat); | |
8418 | ||
8419 | return check_pat; | |
8420 | } | |
8421 | ||
8422 | /* Return nonzero, if X is branchy recovery check. */ | |
8423 | static int | |
8424 | ia64_spec_check_p (rtx x) | |
8425 | { | |
8426 | x = PATTERN (x); | |
8427 | if (GET_CODE (x) == COND_EXEC) | |
8428 | x = COND_EXEC_CODE (x); | |
8429 | if (GET_CODE (x) == SET) | |
8430 | return ia64_spec_check_src_p (SET_SRC (x)); | |
8431 | return 0; | |
8432 | } | |
8433 | ||
8434 | /* Return nonzero, if SRC belongs to recovery check. */ | |
8435 | static int | |
8436 | ia64_spec_check_src_p (rtx src) | |
8437 | { | |
8438 | if (GET_CODE (src) == IF_THEN_ELSE) | |
8439 | { | |
8440 | rtx t; | |
8441 | ||
8442 | t = XEXP (src, 0); | |
8443 | if (GET_CODE (t) == NE) | |
8444 | { | |
8445 | t = XEXP (t, 0); | |
8446 | ||
8447 | if (GET_CODE (t) == UNSPEC) | |
8448 | { | |
8449 | int code; | |
8450 | ||
8451 | code = XINT (t, 1); | |
8452 | ||
388092d5 AB |
8453 | if (code == UNSPEC_LDCCLR |
8454 | || code == UNSPEC_LDCNC | |
8455 | || code == UNSPEC_CHKACLR | |
8456 | || code == UNSPEC_CHKANC | |
8457 | || code == UNSPEC_CHKS) | |
048d0d36 MK |
8458 | { |
8459 | gcc_assert (code != 0); | |
8460 | return code; | |
8461 | } | |
8462 | } | |
8463 | } | |
8464 | } | |
8465 | return 0; | |
8466 | } | |
30028c85 | 8467 | \f |
2130b7fb | 8468 | |
30028c85 VM |
8469 | /* The following page contains abstract data `bundle states' which are |
8470 | used for bundling insns (inserting nops and template generation). */ | |
8471 | ||
8472 | /* The following describes state of insn bundling. */ | |
8473 | ||
8474 | struct bundle_state | |
8475 | { | |
8476 | /* Unique bundle state number to identify them in the debugging | |
8477 | output */ | |
8478 | int unique_num; | |
8479 | rtx insn; /* corresponding insn, NULL for the 1st and the last state */ | |
8480 | /* number nops before and after the insn */ | |
8481 | short before_nops_num, after_nops_num; | |
8482 | int insn_num; /* insn number (0 - for initial state, 1 - for the 1st | |
8483 | insn */ | |
8484 | int cost; /* cost of the state in cycles */ | |
8485 | int accumulated_insns_num; /* number of all previous insns including | |
8486 | nops. L is considered as 2 insns */ | |
8487 | int branch_deviation; /* deviation of previous branches from 3rd slots */ | |
388092d5 | 8488 | int middle_bundle_stops; /* number of stop bits in the middle of bundles */ |
30028c85 VM |
8489 | struct bundle_state *next; /* next state with the same insn_num */ |
8490 | struct bundle_state *originator; /* originator (previous insn state) */ | |
8491 | /* All bundle states are in the following chain. */ | |
8492 | struct bundle_state *allocated_states_chain; | |
8493 | /* The DFA State after issuing the insn and the nops. */ | |
8494 | state_t dfa_state; | |
8495 | }; | |
2130b7fb | 8496 | |
30028c85 | 8497 | /* The following is map insn number to the corresponding bundle state. */ |
2130b7fb | 8498 | |
30028c85 | 8499 | static struct bundle_state **index_to_bundle_states; |
2130b7fb | 8500 | |
30028c85 | 8501 | /* The unique number of next bundle state. */ |
2130b7fb | 8502 | |
30028c85 | 8503 | static int bundle_states_num; |
2130b7fb | 8504 | |
30028c85 | 8505 | /* All allocated bundle states are in the following chain. */ |
2130b7fb | 8506 | |
30028c85 | 8507 | static struct bundle_state *allocated_bundle_states_chain; |
e57b9d65 | 8508 | |
30028c85 VM |
8509 | /* All allocated but not used bundle states are in the following |
8510 | chain. */ | |
870f9ec0 | 8511 | |
30028c85 | 8512 | static struct bundle_state *free_bundle_state_chain; |
2130b7fb | 8513 | |
2130b7fb | 8514 | |
30028c85 | 8515 | /* The following function returns a free bundle state. */ |
2130b7fb | 8516 | |
30028c85 | 8517 | static struct bundle_state * |
9c808aad | 8518 | get_free_bundle_state (void) |
30028c85 VM |
8519 | { |
8520 | struct bundle_state *result; | |
2130b7fb | 8521 | |
30028c85 | 8522 | if (free_bundle_state_chain != NULL) |
2130b7fb | 8523 | { |
30028c85 VM |
8524 | result = free_bundle_state_chain; |
8525 | free_bundle_state_chain = result->next; | |
2130b7fb | 8526 | } |
30028c85 | 8527 | else |
2130b7fb | 8528 | { |
5ead67f6 | 8529 | result = XNEW (struct bundle_state); |
30028c85 VM |
8530 | result->dfa_state = xmalloc (dfa_state_size); |
8531 | result->allocated_states_chain = allocated_bundle_states_chain; | |
8532 | allocated_bundle_states_chain = result; | |
2130b7fb | 8533 | } |
30028c85 VM |
8534 | result->unique_num = bundle_states_num++; |
8535 | return result; | |
9c808aad | 8536 | |
30028c85 | 8537 | } |
2130b7fb | 8538 | |
30028c85 | 8539 | /* The following function frees given bundle state. */ |
2130b7fb | 8540 | |
30028c85 | 8541 | static void |
9c808aad | 8542 | free_bundle_state (struct bundle_state *state) |
30028c85 VM |
8543 | { |
8544 | state->next = free_bundle_state_chain; | |
8545 | free_bundle_state_chain = state; | |
8546 | } | |
2130b7fb | 8547 | |
30028c85 | 8548 | /* Start work with abstract data `bundle states'. */ |
2130b7fb | 8549 | |
30028c85 | 8550 | static void |
9c808aad | 8551 | initiate_bundle_states (void) |
30028c85 VM |
8552 | { |
8553 | bundle_states_num = 0; | |
8554 | free_bundle_state_chain = NULL; | |
8555 | allocated_bundle_states_chain = NULL; | |
2130b7fb BS |
8556 | } |
8557 | ||
30028c85 | 8558 | /* Finish work with abstract data `bundle states'. */ |
2130b7fb BS |
8559 | |
8560 | static void | |
9c808aad | 8561 | finish_bundle_states (void) |
2130b7fb | 8562 | { |
30028c85 VM |
8563 | struct bundle_state *curr_state, *next_state; |
8564 | ||
8565 | for (curr_state = allocated_bundle_states_chain; | |
8566 | curr_state != NULL; | |
8567 | curr_state = next_state) | |
2130b7fb | 8568 | { |
30028c85 VM |
8569 | next_state = curr_state->allocated_states_chain; |
8570 | free (curr_state->dfa_state); | |
8571 | free (curr_state); | |
2130b7fb | 8572 | } |
2130b7fb BS |
8573 | } |
8574 | ||
30028c85 VM |
8575 | /* Hash table of the bundle states. The key is dfa_state and insn_num |
8576 | of the bundle states. */ | |
2130b7fb | 8577 | |
30028c85 | 8578 | static htab_t bundle_state_table; |
2130b7fb | 8579 | |
30028c85 | 8580 | /* The function returns hash of BUNDLE_STATE. */ |
2130b7fb | 8581 | |
30028c85 | 8582 | static unsigned |
9c808aad | 8583 | bundle_state_hash (const void *bundle_state) |
30028c85 | 8584 | { |
586de218 KG |
8585 | const struct bundle_state *const state |
8586 | = (const struct bundle_state *) bundle_state; | |
30028c85 | 8587 | unsigned result, i; |
2130b7fb | 8588 | |
30028c85 VM |
8589 | for (result = i = 0; i < dfa_state_size; i++) |
8590 | result += (((unsigned char *) state->dfa_state) [i] | |
8591 | << ((i % CHAR_BIT) * 3 + CHAR_BIT)); | |
8592 | return result + state->insn_num; | |
8593 | } | |
2130b7fb | 8594 | |
30028c85 | 8595 | /* The function returns nonzero if the bundle state keys are equal. */ |
2130b7fb | 8596 | |
30028c85 | 8597 | static int |
9c808aad | 8598 | bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2) |
30028c85 | 8599 | { |
586de218 KG |
8600 | const struct bundle_state *const state1 |
8601 | = (const struct bundle_state *) bundle_state_1; | |
8602 | const struct bundle_state *const state2 | |
8603 | = (const struct bundle_state *) bundle_state_2; | |
2130b7fb | 8604 | |
30028c85 VM |
8605 | return (state1->insn_num == state2->insn_num |
8606 | && memcmp (state1->dfa_state, state2->dfa_state, | |
8607 | dfa_state_size) == 0); | |
8608 | } | |
2130b7fb | 8609 | |
30028c85 VM |
8610 | /* The function inserts the BUNDLE_STATE into the hash table. The |
8611 | function returns nonzero if the bundle has been inserted into the | |
8612 | table. The table contains the best bundle state with given key. */ | |
2130b7fb | 8613 | |
30028c85 | 8614 | static int |
9c808aad | 8615 | insert_bundle_state (struct bundle_state *bundle_state) |
30028c85 VM |
8616 | { |
8617 | void **entry_ptr; | |
2130b7fb | 8618 | |
bbbbb16a | 8619 | entry_ptr = htab_find_slot (bundle_state_table, bundle_state, INSERT); |
30028c85 VM |
8620 | if (*entry_ptr == NULL) |
8621 | { | |
8622 | bundle_state->next = index_to_bundle_states [bundle_state->insn_num]; | |
8623 | index_to_bundle_states [bundle_state->insn_num] = bundle_state; | |
8624 | *entry_ptr = (void *) bundle_state; | |
8625 | return TRUE; | |
2130b7fb | 8626 | } |
30028c85 VM |
8627 | else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost |
8628 | || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost | |
8629 | && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num | |
8630 | > bundle_state->accumulated_insns_num | |
8631 | || (((struct bundle_state *) | |
8632 | *entry_ptr)->accumulated_insns_num | |
8633 | == bundle_state->accumulated_insns_num | |
388092d5 AB |
8634 | && (((struct bundle_state *) |
8635 | *entry_ptr)->branch_deviation | |
8636 | > bundle_state->branch_deviation | |
8637 | || (((struct bundle_state *) | |
8638 | *entry_ptr)->branch_deviation | |
8639 | == bundle_state->branch_deviation | |
8640 | && ((struct bundle_state *) | |
8641 | *entry_ptr)->middle_bundle_stops | |
8642 | > bundle_state->middle_bundle_stops)))))) | |
9c808aad | 8643 | |
2130b7fb | 8644 | { |
30028c85 VM |
8645 | struct bundle_state temp; |
8646 | ||
8647 | temp = *(struct bundle_state *) *entry_ptr; | |
8648 | *(struct bundle_state *) *entry_ptr = *bundle_state; | |
8649 | ((struct bundle_state *) *entry_ptr)->next = temp.next; | |
8650 | *bundle_state = temp; | |
2130b7fb | 8651 | } |
30028c85 VM |
8652 | return FALSE; |
8653 | } | |
2130b7fb | 8654 | |
30028c85 VM |
8655 | /* Start work with the hash table. */ |
8656 | ||
8657 | static void | |
9c808aad | 8658 | initiate_bundle_state_table (void) |
30028c85 VM |
8659 | { |
8660 | bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p, | |
8661 | (htab_del) 0); | |
2130b7fb BS |
8662 | } |
8663 | ||
30028c85 | 8664 | /* Finish work with the hash table. */ |
e4027dab BS |
8665 | |
8666 | static void | |
9c808aad | 8667 | finish_bundle_state_table (void) |
e4027dab | 8668 | { |
30028c85 | 8669 | htab_delete (bundle_state_table); |
e4027dab BS |
8670 | } |
8671 | ||
30028c85 | 8672 | \f |
a0a7b566 | 8673 | |
30028c85 VM |
8674 | /* The following variable is a insn `nop' used to check bundle states |
8675 | with different number of inserted nops. */ | |
a0a7b566 | 8676 | |
30028c85 | 8677 | static rtx ia64_nop; |
a0a7b566 | 8678 | |
30028c85 VM |
8679 | /* The following function tries to issue NOPS_NUM nops for the current |
8680 | state without advancing processor cycle. If it failed, the | |
8681 | function returns FALSE and frees the current state. */ | |
8682 | ||
8683 | static int | |
9c808aad | 8684 | try_issue_nops (struct bundle_state *curr_state, int nops_num) |
a0a7b566 | 8685 | { |
30028c85 | 8686 | int i; |
a0a7b566 | 8687 | |
30028c85 VM |
8688 | for (i = 0; i < nops_num; i++) |
8689 | if (state_transition (curr_state->dfa_state, ia64_nop) >= 0) | |
8690 | { | |
8691 | free_bundle_state (curr_state); | |
8692 | return FALSE; | |
8693 | } | |
8694 | return TRUE; | |
8695 | } | |
a0a7b566 | 8696 | |
30028c85 VM |
8697 | /* The following function tries to issue INSN for the current |
8698 | state without advancing processor cycle. If it failed, the | |
8699 | function returns FALSE and frees the current state. */ | |
a0a7b566 | 8700 | |
30028c85 | 8701 | static int |
9c808aad | 8702 | try_issue_insn (struct bundle_state *curr_state, rtx insn) |
30028c85 VM |
8703 | { |
8704 | if (insn && state_transition (curr_state->dfa_state, insn) >= 0) | |
8705 | { | |
8706 | free_bundle_state (curr_state); | |
8707 | return FALSE; | |
8708 | } | |
8709 | return TRUE; | |
8710 | } | |
a0a7b566 | 8711 | |
30028c85 VM |
8712 | /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN |
8713 | starting with ORIGINATOR without advancing processor cycle. If | |
f32360c7 VM |
8714 | TRY_BUNDLE_END_P is TRUE, the function also/only (if |
8715 | ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle. | |
8716 | If it was successful, the function creates new bundle state and | |
8717 | insert into the hash table and into `index_to_bundle_states'. */ | |
a0a7b566 | 8718 | |
30028c85 | 8719 | static void |
9c808aad AJ |
8720 | issue_nops_and_insn (struct bundle_state *originator, int before_nops_num, |
8721 | rtx insn, int try_bundle_end_p, int only_bundle_end_p) | |
30028c85 VM |
8722 | { |
8723 | struct bundle_state *curr_state; | |
8724 | ||
8725 | curr_state = get_free_bundle_state (); | |
8726 | memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size); | |
8727 | curr_state->insn = insn; | |
8728 | curr_state->insn_num = originator->insn_num + 1; | |
8729 | curr_state->cost = originator->cost; | |
8730 | curr_state->originator = originator; | |
8731 | curr_state->before_nops_num = before_nops_num; | |
8732 | curr_state->after_nops_num = 0; | |
8733 | curr_state->accumulated_insns_num | |
8734 | = originator->accumulated_insns_num + before_nops_num; | |
8735 | curr_state->branch_deviation = originator->branch_deviation; | |
388092d5 | 8736 | curr_state->middle_bundle_stops = originator->middle_bundle_stops; |
e820471b NS |
8737 | gcc_assert (insn); |
8738 | if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier) | |
30028c85 | 8739 | { |
e820471b | 8740 | gcc_assert (GET_MODE (insn) != TImode); |
30028c85 VM |
8741 | if (!try_issue_nops (curr_state, before_nops_num)) |
8742 | return; | |
8743 | if (!try_issue_insn (curr_state, insn)) | |
8744 | return; | |
8745 | memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size); | |
388092d5 AB |
8746 | if (curr_state->accumulated_insns_num % 3 != 0) |
8747 | curr_state->middle_bundle_stops++; | |
30028c85 VM |
8748 | if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0 |
8749 | && curr_state->accumulated_insns_num % 3 != 0) | |
a0a7b566 | 8750 | { |
30028c85 VM |
8751 | free_bundle_state (curr_state); |
8752 | return; | |
a0a7b566 | 8753 | } |
a0a7b566 | 8754 | } |
30028c85 | 8755 | else if (GET_MODE (insn) != TImode) |
a0a7b566 | 8756 | { |
30028c85 VM |
8757 | if (!try_issue_nops (curr_state, before_nops_num)) |
8758 | return; | |
8759 | if (!try_issue_insn (curr_state, insn)) | |
8760 | return; | |
f32360c7 | 8761 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8762 | gcc_assert (!unknown_for_bundling_p (insn)); |
e820471b | 8763 | |
30028c85 VM |
8764 | if (ia64_safe_type (insn) == TYPE_L) |
8765 | curr_state->accumulated_insns_num++; | |
8766 | } | |
8767 | else | |
8768 | { | |
68e11b42 JW |
8769 | /* If this is an insn that must be first in a group, then don't allow |
8770 | nops to be emitted before it. Currently, alloc is the only such | |
8771 | supported instruction. */ | |
8772 | /* ??? The bundling automatons should handle this for us, but they do | |
8773 | not yet have support for the first_insn attribute. */ | |
8774 | if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES) | |
8775 | { | |
8776 | free_bundle_state (curr_state); | |
8777 | return; | |
8778 | } | |
8779 | ||
30028c85 VM |
8780 | state_transition (curr_state->dfa_state, dfa_pre_cycle_insn); |
8781 | state_transition (curr_state->dfa_state, NULL); | |
8782 | curr_state->cost++; | |
8783 | if (!try_issue_nops (curr_state, before_nops_num)) | |
8784 | return; | |
8785 | if (!try_issue_insn (curr_state, insn)) | |
8786 | return; | |
f32360c7 | 8787 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8788 | if (unknown_for_bundling_p (insn)) |
f32360c7 VM |
8789 | { |
8790 | /* Finish bundle containing asm insn. */ | |
8791 | curr_state->after_nops_num | |
8792 | = 3 - curr_state->accumulated_insns_num % 3; | |
8793 | curr_state->accumulated_insns_num | |
8794 | += 3 - curr_state->accumulated_insns_num % 3; | |
8795 | } | |
8796 | else if (ia64_safe_type (insn) == TYPE_L) | |
30028c85 VM |
8797 | curr_state->accumulated_insns_num++; |
8798 | } | |
8799 | if (ia64_safe_type (insn) == TYPE_B) | |
8800 | curr_state->branch_deviation | |
8801 | += 2 - (curr_state->accumulated_insns_num - 1) % 3; | |
8802 | if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0) | |
8803 | { | |
f32360c7 | 8804 | if (!only_bundle_end_p && insert_bundle_state (curr_state)) |
a0a7b566 | 8805 | { |
30028c85 VM |
8806 | state_t dfa_state; |
8807 | struct bundle_state *curr_state1; | |
8808 | struct bundle_state *allocated_states_chain; | |
8809 | ||
8810 | curr_state1 = get_free_bundle_state (); | |
8811 | dfa_state = curr_state1->dfa_state; | |
8812 | allocated_states_chain = curr_state1->allocated_states_chain; | |
8813 | *curr_state1 = *curr_state; | |
8814 | curr_state1->dfa_state = dfa_state; | |
8815 | curr_state1->allocated_states_chain = allocated_states_chain; | |
8816 | memcpy (curr_state1->dfa_state, curr_state->dfa_state, | |
8817 | dfa_state_size); | |
8818 | curr_state = curr_state1; | |
a0a7b566 | 8819 | } |
30028c85 VM |
8820 | if (!try_issue_nops (curr_state, |
8821 | 3 - curr_state->accumulated_insns_num % 3)) | |
8822 | return; | |
8823 | curr_state->after_nops_num | |
8824 | = 3 - curr_state->accumulated_insns_num % 3; | |
8825 | curr_state->accumulated_insns_num | |
8826 | += 3 - curr_state->accumulated_insns_num % 3; | |
a0a7b566 | 8827 | } |
30028c85 VM |
8828 | if (!insert_bundle_state (curr_state)) |
8829 | free_bundle_state (curr_state); | |
8830 | return; | |
8831 | } | |
e013f3c7 | 8832 | |
30028c85 VM |
8833 | /* The following function returns position in the two window bundle |
8834 | for given STATE. */ | |
8835 | ||
8836 | static int | |
9c808aad | 8837 | get_max_pos (state_t state) |
30028c85 VM |
8838 | { |
8839 | if (cpu_unit_reservation_p (state, pos_6)) | |
8840 | return 6; | |
8841 | else if (cpu_unit_reservation_p (state, pos_5)) | |
8842 | return 5; | |
8843 | else if (cpu_unit_reservation_p (state, pos_4)) | |
8844 | return 4; | |
8845 | else if (cpu_unit_reservation_p (state, pos_3)) | |
8846 | return 3; | |
8847 | else if (cpu_unit_reservation_p (state, pos_2)) | |
8848 | return 2; | |
8849 | else if (cpu_unit_reservation_p (state, pos_1)) | |
8850 | return 1; | |
8851 | else | |
8852 | return 0; | |
a0a7b566 BS |
8853 | } |
8854 | ||
30028c85 VM |
8855 | /* The function returns code of a possible template for given position |
8856 | and state. The function should be called only with 2 values of | |
96ddf8ef VM |
8857 | position equal to 3 or 6. We avoid generating F NOPs by putting |
8858 | templates containing F insns at the end of the template search | |
8859 | because undocumented anomaly in McKinley derived cores which can | |
8860 | cause stalls if an F-unit insn (including a NOP) is issued within a | |
8861 | six-cycle window after reading certain application registers (such | |
8862 | as ar.bsp). Furthermore, power-considerations also argue against | |
8863 | the use of F-unit instructions unless they're really needed. */ | |
2130b7fb | 8864 | |
c237e94a | 8865 | static int |
9c808aad | 8866 | get_template (state_t state, int pos) |
2130b7fb | 8867 | { |
30028c85 | 8868 | switch (pos) |
2130b7fb | 8869 | { |
30028c85 | 8870 | case 3: |
96ddf8ef | 8871 | if (cpu_unit_reservation_p (state, _0mmi_)) |
30028c85 | 8872 | return 1; |
96ddf8ef VM |
8873 | else if (cpu_unit_reservation_p (state, _0mii_)) |
8874 | return 0; | |
30028c85 VM |
8875 | else if (cpu_unit_reservation_p (state, _0mmb_)) |
8876 | return 7; | |
96ddf8ef VM |
8877 | else if (cpu_unit_reservation_p (state, _0mib_)) |
8878 | return 6; | |
8879 | else if (cpu_unit_reservation_p (state, _0mbb_)) | |
8880 | return 5; | |
8881 | else if (cpu_unit_reservation_p (state, _0bbb_)) | |
8882 | return 4; | |
8883 | else if (cpu_unit_reservation_p (state, _0mmf_)) | |
8884 | return 3; | |
8885 | else if (cpu_unit_reservation_p (state, _0mfi_)) | |
8886 | return 2; | |
30028c85 VM |
8887 | else if (cpu_unit_reservation_p (state, _0mfb_)) |
8888 | return 8; | |
8889 | else if (cpu_unit_reservation_p (state, _0mlx_)) | |
8890 | return 9; | |
8891 | else | |
e820471b | 8892 | gcc_unreachable (); |
30028c85 | 8893 | case 6: |
96ddf8ef | 8894 | if (cpu_unit_reservation_p (state, _1mmi_)) |
30028c85 | 8895 | return 1; |
96ddf8ef VM |
8896 | else if (cpu_unit_reservation_p (state, _1mii_)) |
8897 | return 0; | |
30028c85 VM |
8898 | else if (cpu_unit_reservation_p (state, _1mmb_)) |
8899 | return 7; | |
96ddf8ef VM |
8900 | else if (cpu_unit_reservation_p (state, _1mib_)) |
8901 | return 6; | |
8902 | else if (cpu_unit_reservation_p (state, _1mbb_)) | |
8903 | return 5; | |
8904 | else if (cpu_unit_reservation_p (state, _1bbb_)) | |
8905 | return 4; | |
8906 | else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_)) | |
8907 | return 3; | |
8908 | else if (cpu_unit_reservation_p (state, _1mfi_)) | |
8909 | return 2; | |
30028c85 VM |
8910 | else if (cpu_unit_reservation_p (state, _1mfb_)) |
8911 | return 8; | |
8912 | else if (cpu_unit_reservation_p (state, _1mlx_)) | |
8913 | return 9; | |
8914 | else | |
e820471b | 8915 | gcc_unreachable (); |
30028c85 | 8916 | default: |
e820471b | 8917 | gcc_unreachable (); |
2130b7fb | 8918 | } |
30028c85 | 8919 | } |
2130b7fb | 8920 | |
388092d5 | 8921 | /* True when INSN is important for bundling. */ |
7b84aac0 | 8922 | |
388092d5 AB |
8923 | static bool |
8924 | important_for_bundling_p (rtx insn) | |
8925 | { | |
8926 | return (INSN_P (insn) | |
8927 | && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE | |
8928 | && GET_CODE (PATTERN (insn)) != USE | |
8929 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8930 | } | |
8931 | ||
30028c85 VM |
8932 | /* The following function returns an insn important for insn bundling |
8933 | followed by INSN and before TAIL. */ | |
a0a7b566 | 8934 | |
30028c85 | 8935 | static rtx |
9c808aad | 8936 | get_next_important_insn (rtx insn, rtx tail) |
30028c85 VM |
8937 | { |
8938 | for (; insn && insn != tail; insn = NEXT_INSN (insn)) | |
388092d5 | 8939 | if (important_for_bundling_p (insn)) |
30028c85 VM |
8940 | return insn; |
8941 | return NULL_RTX; | |
8942 | } | |
8943 | ||
7b84aac0 EB |
8944 | /* True when INSN is unknown, but important, for bundling. */ |
8945 | ||
8946 | static bool | |
8947 | unknown_for_bundling_p (rtx insn) | |
8948 | { | |
8949 | return (INSN_P (insn) | |
8950 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN | |
8951 | && GET_CODE (PATTERN (insn)) != USE | |
8952 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8953 | } | |
8954 | ||
4a4cd49c JJ |
8955 | /* Add a bundle selector TEMPLATE0 before INSN. */ |
8956 | ||
8957 | static void | |
8958 | ia64_add_bundle_selector_before (int template0, rtx insn) | |
8959 | { | |
8960 | rtx b = gen_bundle_selector (GEN_INT (template0)); | |
8961 | ||
8962 | ia64_emit_insn_before (b, insn); | |
8963 | #if NR_BUNDLES == 10 | |
8964 | if ((template0 == 4 || template0 == 5) | |
d5fabb58 | 8965 | && ia64_except_unwind_info (&global_options) == UI_TARGET) |
4a4cd49c JJ |
8966 | { |
8967 | int i; | |
8968 | rtx note = NULL_RTX; | |
8969 | ||
8970 | /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the | |
8971 | first or second slot. If it is and has REG_EH_NOTE set, copy it | |
8972 | to following nops, as br.call sets rp to the address of following | |
8973 | bundle and therefore an EH region end must be on a bundle | |
8974 | boundary. */ | |
8975 | insn = PREV_INSN (insn); | |
8976 | for (i = 0; i < 3; i++) | |
8977 | { | |
8978 | do | |
8979 | insn = next_active_insn (insn); | |
8980 | while (GET_CODE (insn) == INSN | |
8981 | && get_attr_empty (insn) == EMPTY_YES); | |
8982 | if (GET_CODE (insn) == CALL_INSN) | |
8983 | note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
8984 | else if (note) | |
8985 | { | |
8986 | int code; | |
8987 | ||
8988 | gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop | |
8989 | || code == CODE_FOR_nop_b); | |
8990 | if (find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
8991 | note = NULL_RTX; | |
8992 | else | |
bbbbb16a | 8993 | add_reg_note (insn, REG_EH_REGION, XEXP (note, 0)); |
4a4cd49c JJ |
8994 | } |
8995 | } | |
8996 | } | |
8997 | #endif | |
8998 | } | |
8999 | ||
c856f536 VM |
9000 | /* The following function does insn bundling. Bundling means |
9001 | inserting templates and nop insns to fit insn groups into permitted | |
9002 | templates. Instruction scheduling uses NDFA (non-deterministic | |
9003 | finite automata) encoding informations about the templates and the | |
9004 | inserted nops. Nondeterminism of the automata permits follows | |
9005 | all possible insn sequences very fast. | |
9006 | ||
9007 | Unfortunately it is not possible to get information about inserting | |
9008 | nop insns and used templates from the automata states. The | |
9009 | automata only says that we can issue an insn possibly inserting | |
9010 | some nops before it and using some template. Therefore insn | |
9011 | bundling in this function is implemented by using DFA | |
048d0d36 | 9012 | (deterministic finite automata). We follow all possible insn |
c856f536 VM |
9013 | sequences by inserting 0-2 nops (that is what the NDFA describe for |
9014 | insn scheduling) before/after each insn being bundled. We know the | |
9015 | start of simulated processor cycle from insn scheduling (insn | |
9016 | starting a new cycle has TImode). | |
9017 | ||
9018 | Simple implementation of insn bundling would create enormous | |
9019 | number of possible insn sequences satisfying information about new | |
9020 | cycle ticks taken from the insn scheduling. To make the algorithm | |
9021 | practical we use dynamic programming. Each decision (about | |
9022 | inserting nops and implicitly about previous decisions) is described | |
9023 | by structure bundle_state (see above). If we generate the same | |
9024 | bundle state (key is automaton state after issuing the insns and | |
9025 | nops for it), we reuse already generated one. As consequence we | |
1e5f1716 | 9026 | reject some decisions which cannot improve the solution and |
c856f536 VM |
9027 | reduce memory for the algorithm. |
9028 | ||
9029 | When we reach the end of EBB (extended basic block), we choose the | |
9030 | best sequence and then, moving back in EBB, insert templates for | |
9031 | the best alternative. The templates are taken from querying | |
9032 | automaton state for each insn in chosen bundle states. | |
9033 | ||
9034 | So the algorithm makes two (forward and backward) passes through | |
7400e46b | 9035 | EBB. */ |
a0a7b566 | 9036 | |
30028c85 | 9037 | static void |
9c808aad | 9038 | bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail) |
30028c85 VM |
9039 | { |
9040 | struct bundle_state *curr_state, *next_state, *best_state; | |
9041 | rtx insn, next_insn; | |
9042 | int insn_num; | |
f32360c7 | 9043 | int i, bundle_end_p, only_bundle_end_p, asm_p; |
74601584 | 9044 | int pos = 0, max_pos, template0, template1; |
30028c85 VM |
9045 | rtx b; |
9046 | rtx nop; | |
9047 | enum attr_type type; | |
2d1b811d | 9048 | |
30028c85 | 9049 | insn_num = 0; |
c856f536 | 9050 | /* Count insns in the EBB. */ |
30028c85 VM |
9051 | for (insn = NEXT_INSN (prev_head_insn); |
9052 | insn && insn != tail; | |
9053 | insn = NEXT_INSN (insn)) | |
9054 | if (INSN_P (insn)) | |
9055 | insn_num++; | |
9056 | if (insn_num == 0) | |
9057 | return; | |
9058 | bundling_p = 1; | |
9059 | dfa_clean_insn_cache (); | |
9060 | initiate_bundle_state_table (); | |
5ead67f6 | 9061 | index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2); |
ff482c8d | 9062 | /* First (forward) pass -- generation of bundle states. */ |
30028c85 VM |
9063 | curr_state = get_free_bundle_state (); |
9064 | curr_state->insn = NULL; | |
9065 | curr_state->before_nops_num = 0; | |
9066 | curr_state->after_nops_num = 0; | |
9067 | curr_state->insn_num = 0; | |
9068 | curr_state->cost = 0; | |
9069 | curr_state->accumulated_insns_num = 0; | |
9070 | curr_state->branch_deviation = 0; | |
388092d5 | 9071 | curr_state->middle_bundle_stops = 0; |
30028c85 VM |
9072 | curr_state->next = NULL; |
9073 | curr_state->originator = NULL; | |
9074 | state_reset (curr_state->dfa_state); | |
9075 | index_to_bundle_states [0] = curr_state; | |
9076 | insn_num = 0; | |
c856f536 | 9077 | /* Shift cycle mark if it is put on insn which could be ignored. */ |
30028c85 VM |
9078 | for (insn = NEXT_INSN (prev_head_insn); |
9079 | insn != tail; | |
9080 | insn = NEXT_INSN (insn)) | |
9081 | if (INSN_P (insn) | |
7b84aac0 | 9082 | && !important_for_bundling_p (insn) |
30028c85 | 9083 | && GET_MODE (insn) == TImode) |
2130b7fb | 9084 | { |
30028c85 VM |
9085 | PUT_MODE (insn, VOIDmode); |
9086 | for (next_insn = NEXT_INSN (insn); | |
9087 | next_insn != tail; | |
9088 | next_insn = NEXT_INSN (next_insn)) | |
7b84aac0 | 9089 | if (important_for_bundling_p (next_insn) |
388092d5 | 9090 | && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier) |
30028c85 VM |
9091 | { |
9092 | PUT_MODE (next_insn, TImode); | |
9093 | break; | |
9094 | } | |
2130b7fb | 9095 | } |
048d0d36 | 9096 | /* Forward pass: generation of bundle states. */ |
30028c85 VM |
9097 | for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail); |
9098 | insn != NULL_RTX; | |
9099 | insn = next_insn) | |
1ad72cef | 9100 | { |
7b84aac0 | 9101 | gcc_assert (important_for_bundling_p (insn)); |
f32360c7 | 9102 | type = ia64_safe_type (insn); |
30028c85 VM |
9103 | next_insn = get_next_important_insn (NEXT_INSN (insn), tail); |
9104 | insn_num++; | |
9105 | index_to_bundle_states [insn_num] = NULL; | |
9106 | for (curr_state = index_to_bundle_states [insn_num - 1]; | |
9107 | curr_state != NULL; | |
9108 | curr_state = next_state) | |
f83594c4 | 9109 | { |
30028c85 | 9110 | pos = curr_state->accumulated_insns_num % 3; |
30028c85 | 9111 | next_state = curr_state->next; |
c856f536 VM |
9112 | /* We must fill up the current bundle in order to start a |
9113 | subsequent asm insn in a new bundle. Asm insn is always | |
9114 | placed in a separate bundle. */ | |
f32360c7 VM |
9115 | only_bundle_end_p |
9116 | = (next_insn != NULL_RTX | |
9117 | && INSN_CODE (insn) == CODE_FOR_insn_group_barrier | |
7b84aac0 | 9118 | && unknown_for_bundling_p (next_insn)); |
c856f536 VM |
9119 | /* We may fill up the current bundle if it is the cycle end |
9120 | without a group barrier. */ | |
30028c85 | 9121 | bundle_end_p |
f32360c7 | 9122 | = (only_bundle_end_p || next_insn == NULL_RTX |
30028c85 VM |
9123 | || (GET_MODE (next_insn) == TImode |
9124 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier)); | |
9125 | if (type == TYPE_F || type == TYPE_B || type == TYPE_L | |
7400e46b | 9126 | || type == TYPE_S) |
f32360c7 VM |
9127 | issue_nops_and_insn (curr_state, 2, insn, bundle_end_p, |
9128 | only_bundle_end_p); | |
9129 | issue_nops_and_insn (curr_state, 1, insn, bundle_end_p, | |
9130 | only_bundle_end_p); | |
9131 | issue_nops_and_insn (curr_state, 0, insn, bundle_end_p, | |
9132 | only_bundle_end_p); | |
f83594c4 | 9133 | } |
e820471b | 9134 | gcc_assert (index_to_bundle_states [insn_num]); |
30028c85 VM |
9135 | for (curr_state = index_to_bundle_states [insn_num]; |
9136 | curr_state != NULL; | |
9137 | curr_state = curr_state->next) | |
9138 | if (verbose >= 2 && dump) | |
9139 | { | |
c856f536 VM |
9140 | /* This structure is taken from generated code of the |
9141 | pipeline hazard recognizer (see file insn-attrtab.c). | |
9142 | Please don't forget to change the structure if a new | |
9143 | automaton is added to .md file. */ | |
30028c85 VM |
9144 | struct DFA_chip |
9145 | { | |
9146 | unsigned short one_automaton_state; | |
9147 | unsigned short oneb_automaton_state; | |
9148 | unsigned short two_automaton_state; | |
9149 | unsigned short twob_automaton_state; | |
9150 | }; | |
9c808aad | 9151 | |
30028c85 VM |
9152 | fprintf |
9153 | (dump, | |
388092d5 | 9154 | "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n", |
30028c85 VM |
9155 | curr_state->unique_num, |
9156 | (curr_state->originator == NULL | |
9157 | ? -1 : curr_state->originator->unique_num), | |
9158 | curr_state->cost, | |
9159 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9160 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9161 | curr_state->middle_bundle_stops, |
7400e46b | 9162 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 VM |
9163 | INSN_UID (insn)); |
9164 | } | |
1ad72cef | 9165 | } |
e820471b NS |
9166 | |
9167 | /* We should find a solution because the 2nd insn scheduling has | |
9168 | found one. */ | |
9169 | gcc_assert (index_to_bundle_states [insn_num]); | |
c856f536 | 9170 | /* Find a state corresponding to the best insn sequence. */ |
30028c85 VM |
9171 | best_state = NULL; |
9172 | for (curr_state = index_to_bundle_states [insn_num]; | |
9173 | curr_state != NULL; | |
9174 | curr_state = curr_state->next) | |
c856f536 VM |
9175 | /* We are just looking at the states with fully filled up last |
9176 | bundle. The first we prefer insn sequences with minimal cost | |
9177 | then with minimal inserted nops and finally with branch insns | |
9178 | placed in the 3rd slots. */ | |
30028c85 VM |
9179 | if (curr_state->accumulated_insns_num % 3 == 0 |
9180 | && (best_state == NULL || best_state->cost > curr_state->cost | |
9181 | || (best_state->cost == curr_state->cost | |
9182 | && (curr_state->accumulated_insns_num | |
9183 | < best_state->accumulated_insns_num | |
9184 | || (curr_state->accumulated_insns_num | |
9185 | == best_state->accumulated_insns_num | |
388092d5 AB |
9186 | && (curr_state->branch_deviation |
9187 | < best_state->branch_deviation | |
9188 | || (curr_state->branch_deviation | |
9189 | == best_state->branch_deviation | |
9190 | && curr_state->middle_bundle_stops | |
9191 | < best_state->middle_bundle_stops))))))) | |
30028c85 | 9192 | best_state = curr_state; |
c856f536 | 9193 | /* Second (backward) pass: adding nops and templates. */ |
388092d5 | 9194 | gcc_assert (best_state); |
30028c85 VM |
9195 | insn_num = best_state->before_nops_num; |
9196 | template0 = template1 = -1; | |
9197 | for (curr_state = best_state; | |
9198 | curr_state->originator != NULL; | |
9199 | curr_state = curr_state->originator) | |
9200 | { | |
9201 | insn = curr_state->insn; | |
7b84aac0 | 9202 | asm_p = unknown_for_bundling_p (insn); |
30028c85 VM |
9203 | insn_num++; |
9204 | if (verbose >= 2 && dump) | |
2130b7fb | 9205 | { |
30028c85 VM |
9206 | struct DFA_chip |
9207 | { | |
9208 | unsigned short one_automaton_state; | |
9209 | unsigned short oneb_automaton_state; | |
9210 | unsigned short two_automaton_state; | |
9211 | unsigned short twob_automaton_state; | |
9212 | }; | |
9c808aad | 9213 | |
30028c85 VM |
9214 | fprintf |
9215 | (dump, | |
388092d5 | 9216 | "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n", |
30028c85 VM |
9217 | curr_state->unique_num, |
9218 | (curr_state->originator == NULL | |
9219 | ? -1 : curr_state->originator->unique_num), | |
9220 | curr_state->cost, | |
9221 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9222 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9223 | curr_state->middle_bundle_stops, |
7400e46b | 9224 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 | 9225 | INSN_UID (insn)); |
2130b7fb | 9226 | } |
c856f536 VM |
9227 | /* Find the position in the current bundle window. The window can |
9228 | contain at most two bundles. Two bundle window means that | |
9229 | the processor will make two bundle rotation. */ | |
30028c85 | 9230 | max_pos = get_max_pos (curr_state->dfa_state); |
c856f536 VM |
9231 | if (max_pos == 6 |
9232 | /* The following (negative template number) means that the | |
9233 | processor did one bundle rotation. */ | |
9234 | || (max_pos == 3 && template0 < 0)) | |
2130b7fb | 9235 | { |
c856f536 VM |
9236 | /* We are at the end of the window -- find template(s) for |
9237 | its bundle(s). */ | |
30028c85 VM |
9238 | pos = max_pos; |
9239 | if (max_pos == 3) | |
9240 | template0 = get_template (curr_state->dfa_state, 3); | |
9241 | else | |
9242 | { | |
9243 | template1 = get_template (curr_state->dfa_state, 3); | |
9244 | template0 = get_template (curr_state->dfa_state, 6); | |
9245 | } | |
9246 | } | |
9247 | if (max_pos > 3 && template1 < 0) | |
c856f536 | 9248 | /* It may happen when we have the stop inside a bundle. */ |
30028c85 | 9249 | { |
e820471b | 9250 | gcc_assert (pos <= 3); |
30028c85 VM |
9251 | template1 = get_template (curr_state->dfa_state, 3); |
9252 | pos += 3; | |
9253 | } | |
f32360c7 | 9254 | if (!asm_p) |
c856f536 | 9255 | /* Emit nops after the current insn. */ |
f32360c7 VM |
9256 | for (i = 0; i < curr_state->after_nops_num; i++) |
9257 | { | |
9258 | nop = gen_nop (); | |
9259 | emit_insn_after (nop, insn); | |
9260 | pos--; | |
e820471b | 9261 | gcc_assert (pos >= 0); |
f32360c7 VM |
9262 | if (pos % 3 == 0) |
9263 | { | |
c856f536 VM |
9264 | /* We are at the start of a bundle: emit the template |
9265 | (it should be defined). */ | |
e820471b | 9266 | gcc_assert (template0 >= 0); |
4a4cd49c | 9267 | ia64_add_bundle_selector_before (template0, nop); |
c856f536 VM |
9268 | /* If we have two bundle window, we make one bundle |
9269 | rotation. Otherwise template0 will be undefined | |
9270 | (negative value). */ | |
f32360c7 VM |
9271 | template0 = template1; |
9272 | template1 = -1; | |
9273 | } | |
9274 | } | |
c856f536 VM |
9275 | /* Move the position backward in the window. Group barrier has |
9276 | no slot. Asm insn takes all bundle. */ | |
30028c85 | 9277 | if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier |
7b84aac0 | 9278 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9279 | pos--; |
c856f536 | 9280 | /* Long insn takes 2 slots. */ |
30028c85 VM |
9281 | if (ia64_safe_type (insn) == TYPE_L) |
9282 | pos--; | |
e820471b | 9283 | gcc_assert (pos >= 0); |
30028c85 VM |
9284 | if (pos % 3 == 0 |
9285 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier | |
7b84aac0 | 9286 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9287 | { |
c856f536 VM |
9288 | /* The current insn is at the bundle start: emit the |
9289 | template. */ | |
e820471b | 9290 | gcc_assert (template0 >= 0); |
4a4cd49c | 9291 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9292 | b = PREV_INSN (insn); |
9293 | insn = b; | |
68776c43 | 9294 | /* See comment above in analogous place for emitting nops |
c856f536 | 9295 | after the insn. */ |
30028c85 VM |
9296 | template0 = template1; |
9297 | template1 = -1; | |
9298 | } | |
c856f536 | 9299 | /* Emit nops after the current insn. */ |
30028c85 VM |
9300 | for (i = 0; i < curr_state->before_nops_num; i++) |
9301 | { | |
9302 | nop = gen_nop (); | |
9303 | ia64_emit_insn_before (nop, insn); | |
9304 | nop = PREV_INSN (insn); | |
9305 | insn = nop; | |
9306 | pos--; | |
e820471b | 9307 | gcc_assert (pos >= 0); |
30028c85 VM |
9308 | if (pos % 3 == 0) |
9309 | { | |
68776c43 | 9310 | /* See comment above in analogous place for emitting nops |
c856f536 | 9311 | after the insn. */ |
e820471b | 9312 | gcc_assert (template0 >= 0); |
4a4cd49c | 9313 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9314 | b = PREV_INSN (insn); |
9315 | insn = b; | |
9316 | template0 = template1; | |
9317 | template1 = -1; | |
9318 | } | |
2130b7fb BS |
9319 | } |
9320 | } | |
388092d5 AB |
9321 | |
9322 | #ifdef ENABLE_CHECKING | |
9323 | { | |
9324 | /* Assert right calculation of middle_bundle_stops. */ | |
9325 | int num = best_state->middle_bundle_stops; | |
9326 | bool start_bundle = true, end_bundle = false; | |
9327 | ||
9328 | for (insn = NEXT_INSN (prev_head_insn); | |
9329 | insn && insn != tail; | |
9330 | insn = NEXT_INSN (insn)) | |
9331 | { | |
9332 | if (!INSN_P (insn)) | |
9333 | continue; | |
9334 | if (recog_memoized (insn) == CODE_FOR_bundle_selector) | |
9335 | start_bundle = true; | |
9336 | else | |
9337 | { | |
9338 | rtx next_insn; | |
9339 | ||
9340 | for (next_insn = NEXT_INSN (insn); | |
9341 | next_insn && next_insn != tail; | |
9342 | next_insn = NEXT_INSN (next_insn)) | |
9343 | if (INSN_P (next_insn) | |
9344 | && (ia64_safe_itanium_class (next_insn) | |
9345 | != ITANIUM_CLASS_IGNORE | |
9346 | || recog_memoized (next_insn) | |
9347 | == CODE_FOR_bundle_selector) | |
9348 | && GET_CODE (PATTERN (next_insn)) != USE | |
9349 | && GET_CODE (PATTERN (next_insn)) != CLOBBER) | |
9350 | break; | |
9351 | ||
9352 | end_bundle = next_insn == NULL_RTX | |
9353 | || next_insn == tail | |
9354 | || (INSN_P (next_insn) | |
9355 | && recog_memoized (next_insn) | |
9356 | == CODE_FOR_bundle_selector); | |
9357 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier | |
9358 | && !start_bundle && !end_bundle | |
9359 | && next_insn | |
7b84aac0 | 9360 | && !unknown_for_bundling_p (next_insn)) |
388092d5 AB |
9361 | num--; |
9362 | ||
9363 | start_bundle = false; | |
9364 | } | |
9365 | } | |
9366 | ||
9367 | gcc_assert (num == 0); | |
9368 | } | |
9369 | #endif | |
9370 | ||
30028c85 VM |
9371 | free (index_to_bundle_states); |
9372 | finish_bundle_state_table (); | |
9373 | bundling_p = 0; | |
9374 | dfa_clean_insn_cache (); | |
2130b7fb | 9375 | } |
c65ebc55 | 9376 | |
30028c85 VM |
9377 | /* The following function is called at the end of scheduling BB or |
9378 | EBB. After reload, it inserts stop bits and does insn bundling. */ | |
9379 | ||
9380 | static void | |
9c808aad | 9381 | ia64_sched_finish (FILE *dump, int sched_verbose) |
c237e94a | 9382 | { |
30028c85 VM |
9383 | if (sched_verbose) |
9384 | fprintf (dump, "// Finishing schedule.\n"); | |
9385 | if (!reload_completed) | |
9386 | return; | |
9387 | if (reload_completed) | |
9388 | { | |
9389 | final_emit_insn_group_barriers (dump); | |
9390 | bundling (dump, sched_verbose, current_sched_info->prev_head, | |
9391 | current_sched_info->next_tail); | |
9392 | if (sched_verbose && dump) | |
9393 | fprintf (dump, "// finishing %d-%d\n", | |
9394 | INSN_UID (NEXT_INSN (current_sched_info->prev_head)), | |
9395 | INSN_UID (PREV_INSN (current_sched_info->next_tail))); | |
9c808aad | 9396 | |
30028c85 VM |
9397 | return; |
9398 | } | |
c237e94a ZW |
9399 | } |
9400 | ||
30028c85 | 9401 | /* The following function inserts stop bits in scheduled BB or EBB. */ |
2130b7fb | 9402 | |
30028c85 | 9403 | static void |
9c808aad | 9404 | final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
2130b7fb | 9405 | { |
30028c85 VM |
9406 | rtx insn; |
9407 | int need_barrier_p = 0; | |
388092d5 | 9408 | int seen_good_insn = 0; |
2130b7fb | 9409 | |
30028c85 | 9410 | init_insn_group_barriers (); |
2130b7fb | 9411 | |
30028c85 VM |
9412 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
9413 | insn != current_sched_info->next_tail; | |
9414 | insn = NEXT_INSN (insn)) | |
9415 | { | |
9416 | if (GET_CODE (insn) == BARRIER) | |
b395ddbe | 9417 | { |
30028c85 | 9418 | rtx last = prev_active_insn (insn); |
14d118d6 | 9419 | |
30028c85 | 9420 | if (! last) |
b395ddbe | 9421 | continue; |
30028c85 VM |
9422 | if (GET_CODE (last) == JUMP_INSN |
9423 | && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC) | |
9424 | last = prev_active_insn (last); | |
9425 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9426 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
2130b7fb | 9427 | |
30028c85 | 9428 | init_insn_group_barriers (); |
388092d5 | 9429 | seen_good_insn = 0; |
30028c85 | 9430 | need_barrier_p = 0; |
b395ddbe | 9431 | } |
b5b8b0ac | 9432 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb | 9433 | { |
30028c85 | 9434 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
2130b7fb | 9435 | { |
30028c85 | 9436 | init_insn_group_barriers (); |
388092d5 | 9437 | seen_good_insn = 0; |
30028c85 | 9438 | need_barrier_p = 0; |
c65ebc55 | 9439 | } |
388092d5 AB |
9440 | else if (need_barrier_p || group_barrier_needed (insn) |
9441 | || (mflag_sched_stop_bits_after_every_cycle | |
9442 | && GET_MODE (insn) == TImode | |
9443 | && seen_good_insn)) | |
2130b7fb | 9444 | { |
30028c85 VM |
9445 | if (TARGET_EARLY_STOP_BITS) |
9446 | { | |
9447 | rtx last; | |
9c808aad | 9448 | |
30028c85 VM |
9449 | for (last = insn; |
9450 | last != current_sched_info->prev_head; | |
9451 | last = PREV_INSN (last)) | |
9452 | if (INSN_P (last) && GET_MODE (last) == TImode | |
9453 | && stops_p [INSN_UID (last)]) | |
9454 | break; | |
9455 | if (last == current_sched_info->prev_head) | |
9456 | last = insn; | |
9457 | last = prev_active_insn (last); | |
9458 | if (last | |
9459 | && recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9460 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), | |
9461 | last); | |
9462 | init_insn_group_barriers (); | |
9463 | for (last = NEXT_INSN (last); | |
9464 | last != insn; | |
9465 | last = NEXT_INSN (last)) | |
9466 | if (INSN_P (last)) | |
388092d5 AB |
9467 | { |
9468 | group_barrier_needed (last); | |
9469 | if (recog_memoized (last) >= 0 | |
9470 | && important_for_bundling_p (last)) | |
9471 | seen_good_insn = 1; | |
9472 | } | |
30028c85 VM |
9473 | } |
9474 | else | |
9475 | { | |
9476 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), | |
9477 | insn); | |
9478 | init_insn_group_barriers (); | |
388092d5 | 9479 | seen_good_insn = 0; |
30028c85 | 9480 | } |
c1bc6ca8 | 9481 | group_barrier_needed (insn); |
388092d5 AB |
9482 | if (recog_memoized (insn) >= 0 |
9483 | && important_for_bundling_p (insn)) | |
9484 | seen_good_insn = 1; | |
2130b7fb | 9485 | } |
388092d5 AB |
9486 | else if (recog_memoized (insn) >= 0 |
9487 | && important_for_bundling_p (insn)) | |
034288ef | 9488 | seen_good_insn = 1; |
30028c85 | 9489 | need_barrier_p = (GET_CODE (insn) == CALL_INSN |
7b84aac0 | 9490 | || unknown_for_bundling_p (insn)); |
c65ebc55 | 9491 | } |
2130b7fb | 9492 | } |
30028c85 | 9493 | } |
2130b7fb | 9494 | |
30028c85 | 9495 | \f |
2130b7fb | 9496 | |
a4d05547 | 9497 | /* If the following function returns TRUE, we will use the DFA |
30028c85 | 9498 | insn scheduler. */ |
2130b7fb | 9499 | |
c237e94a | 9500 | static int |
9c808aad | 9501 | ia64_first_cycle_multipass_dfa_lookahead (void) |
2130b7fb | 9502 | { |
30028c85 VM |
9503 | return (reload_completed ? 6 : 4); |
9504 | } | |
2130b7fb | 9505 | |
30028c85 | 9506 | /* The following function initiates variable `dfa_pre_cycle_insn'. */ |
2130b7fb | 9507 | |
30028c85 | 9508 | static void |
9c808aad | 9509 | ia64_init_dfa_pre_cycle_insn (void) |
30028c85 VM |
9510 | { |
9511 | if (temp_dfa_state == NULL) | |
2130b7fb | 9512 | { |
30028c85 VM |
9513 | dfa_state_size = state_size (); |
9514 | temp_dfa_state = xmalloc (dfa_state_size); | |
9515 | prev_cycle_state = xmalloc (dfa_state_size); | |
2130b7fb | 9516 | } |
30028c85 VM |
9517 | dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ()); |
9518 | PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX; | |
9519 | recog_memoized (dfa_pre_cycle_insn); | |
9520 | dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3))); | |
9521 | PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX; | |
9522 | recog_memoized (dfa_stop_insn); | |
9523 | } | |
2130b7fb | 9524 | |
30028c85 VM |
9525 | /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN |
9526 | used by the DFA insn scheduler. */ | |
2130b7fb | 9527 | |
30028c85 | 9528 | static rtx |
9c808aad | 9529 | ia64_dfa_pre_cycle_insn (void) |
30028c85 VM |
9530 | { |
9531 | return dfa_pre_cycle_insn; | |
9532 | } | |
2130b7fb | 9533 | |
30028c85 VM |
9534 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9535 | ld) produces address for CONSUMER (of type st or stf). */ | |
2130b7fb | 9536 | |
30028c85 | 9537 | int |
9c808aad | 9538 | ia64_st_address_bypass_p (rtx producer, rtx consumer) |
30028c85 VM |
9539 | { |
9540 | rtx dest, reg, mem; | |
2130b7fb | 9541 | |
e820471b | 9542 | gcc_assert (producer && consumer); |
30028c85 | 9543 | dest = ia64_single_set (producer); |
e820471b NS |
9544 | gcc_assert (dest); |
9545 | reg = SET_DEST (dest); | |
9546 | gcc_assert (reg); | |
30028c85 VM |
9547 | if (GET_CODE (reg) == SUBREG) |
9548 | reg = SUBREG_REG (reg); | |
e820471b NS |
9549 | gcc_assert (GET_CODE (reg) == REG); |
9550 | ||
30028c85 | 9551 | dest = ia64_single_set (consumer); |
e820471b NS |
9552 | gcc_assert (dest); |
9553 | mem = SET_DEST (dest); | |
9554 | gcc_assert (mem && GET_CODE (mem) == MEM); | |
30028c85 | 9555 | return reg_mentioned_p (reg, mem); |
2130b7fb BS |
9556 | } |
9557 | ||
30028c85 VM |
9558 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9559 | ld) produces address for CONSUMER (of type ld or fld). */ | |
2130b7fb | 9560 | |
30028c85 | 9561 | int |
9c808aad | 9562 | ia64_ld_address_bypass_p (rtx producer, rtx consumer) |
2130b7fb | 9563 | { |
30028c85 VM |
9564 | rtx dest, src, reg, mem; |
9565 | ||
e820471b | 9566 | gcc_assert (producer && consumer); |
30028c85 | 9567 | dest = ia64_single_set (producer); |
e820471b NS |
9568 | gcc_assert (dest); |
9569 | reg = SET_DEST (dest); | |
9570 | gcc_assert (reg); | |
30028c85 VM |
9571 | if (GET_CODE (reg) == SUBREG) |
9572 | reg = SUBREG_REG (reg); | |
e820471b NS |
9573 | gcc_assert (GET_CODE (reg) == REG); |
9574 | ||
30028c85 | 9575 | src = ia64_single_set (consumer); |
e820471b NS |
9576 | gcc_assert (src); |
9577 | mem = SET_SRC (src); | |
9578 | gcc_assert (mem); | |
048d0d36 | 9579 | |
30028c85 VM |
9580 | if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0) |
9581 | mem = XVECEXP (mem, 0, 0); | |
048d0d36 | 9582 | else if (GET_CODE (mem) == IF_THEN_ELSE) |
917f1b7e | 9583 | /* ??? Is this bypass necessary for ld.c? */ |
048d0d36 MK |
9584 | { |
9585 | gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR); | |
9586 | mem = XEXP (mem, 1); | |
9587 | } | |
9588 | ||
30028c85 VM |
9589 | while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND) |
9590 | mem = XEXP (mem, 0); | |
ef1ecf87 | 9591 | |
048d0d36 MK |
9592 | if (GET_CODE (mem) == UNSPEC) |
9593 | { | |
9594 | int c = XINT (mem, 1); | |
9595 | ||
388092d5 AB |
9596 | gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A |
9597 | || c == UNSPEC_LDSA); | |
048d0d36 MK |
9598 | mem = XVECEXP (mem, 0, 0); |
9599 | } | |
9600 | ||
ef1ecf87 | 9601 | /* Note that LO_SUM is used for GOT loads. */ |
e820471b | 9602 | gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM); |
ef1ecf87 | 9603 | |
30028c85 VM |
9604 | return reg_mentioned_p (reg, mem); |
9605 | } | |
9606 | ||
9607 | /* The following function returns TRUE if INSN produces address for a | |
9608 | load/store insn. We will place such insns into M slot because it | |
ff482c8d | 9609 | decreases its latency time. */ |
30028c85 VM |
9610 | |
9611 | int | |
9c808aad | 9612 | ia64_produce_address_p (rtx insn) |
30028c85 VM |
9613 | { |
9614 | return insn->call; | |
2130b7fb | 9615 | } |
30028c85 | 9616 | |
2130b7fb | 9617 | \f |
3b572406 RH |
9618 | /* Emit pseudo-ops for the assembler to describe predicate relations. |
9619 | At present this assumes that we only consider predicate pairs to | |
9620 | be mutex, and that the assembler can deduce proper values from | |
9621 | straight-line code. */ | |
9622 | ||
9623 | static void | |
9c808aad | 9624 | emit_predicate_relation_info (void) |
3b572406 | 9625 | { |
e0082a72 | 9626 | basic_block bb; |
3b572406 | 9627 | |
e0082a72 | 9628 | FOR_EACH_BB_REVERSE (bb) |
3b572406 | 9629 | { |
3b572406 | 9630 | int r; |
a813c111 | 9631 | rtx head = BB_HEAD (bb); |
3b572406 RH |
9632 | |
9633 | /* We only need such notes at code labels. */ | |
9634 | if (GET_CODE (head) != CODE_LABEL) | |
9635 | continue; | |
740aeb38 | 9636 | if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head))) |
3b572406 RH |
9637 | head = NEXT_INSN (head); |
9638 | ||
9f3b8452 RH |
9639 | /* Skip p0, which may be thought to be live due to (reg:DI p0) |
9640 | grabbing the entire block of predicate registers. */ | |
9641 | for (r = PR_REG (2); r < PR_REG (64); r += 2) | |
6fb5fa3c | 9642 | if (REGNO_REG_SET_P (df_get_live_in (bb), r)) |
3b572406 | 9643 | { |
f2f90c63 | 9644 | rtx p = gen_rtx_REG (BImode, r); |
054451ea | 9645 | rtx n = emit_insn_after (gen_pred_rel_mutex (p), head); |
a813c111 SB |
9646 | if (head == BB_END (bb)) |
9647 | BB_END (bb) = n; | |
3b572406 RH |
9648 | head = n; |
9649 | } | |
9650 | } | |
ca3920ad JW |
9651 | |
9652 | /* Look for conditional calls that do not return, and protect predicate | |
9653 | relations around them. Otherwise the assembler will assume the call | |
9654 | returns, and complain about uses of call-clobbered predicates after | |
9655 | the call. */ | |
e0082a72 | 9656 | FOR_EACH_BB_REVERSE (bb) |
ca3920ad | 9657 | { |
a813c111 | 9658 | rtx insn = BB_HEAD (bb); |
9c808aad | 9659 | |
ca3920ad JW |
9660 | while (1) |
9661 | { | |
9662 | if (GET_CODE (insn) == CALL_INSN | |
9663 | && GET_CODE (PATTERN (insn)) == COND_EXEC | |
9664 | && find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
9665 | { | |
9666 | rtx b = emit_insn_before (gen_safe_across_calls_all (), insn); | |
9667 | rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn); | |
a813c111 SB |
9668 | if (BB_HEAD (bb) == insn) |
9669 | BB_HEAD (bb) = b; | |
9670 | if (BB_END (bb) == insn) | |
9671 | BB_END (bb) = a; | |
ca3920ad | 9672 | } |
9c808aad | 9673 | |
a813c111 | 9674 | if (insn == BB_END (bb)) |
ca3920ad JW |
9675 | break; |
9676 | insn = NEXT_INSN (insn); | |
9677 | } | |
9678 | } | |
3b572406 RH |
9679 | } |
9680 | ||
c65ebc55 JW |
9681 | /* Perform machine dependent operations on the rtl chain INSNS. */ |
9682 | ||
18dbd950 | 9683 | static void |
9c808aad | 9684 | ia64_reorg (void) |
c65ebc55 | 9685 | { |
1e3881c2 JH |
9686 | /* We are freeing block_for_insn in the toplev to keep compatibility |
9687 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
852c6ec7 | 9688 | compute_bb_for_insn (); |
a00fe19f RH |
9689 | |
9690 | /* If optimizing, we'll have split before scheduling. */ | |
9691 | if (optimize == 0) | |
6fb5fa3c | 9692 | split_all_insns (); |
2130b7fb | 9693 | |
2ba42841 | 9694 | if (optimize && flag_schedule_insns_after_reload |
388092d5 | 9695 | && dbg_cnt (ia64_sched2)) |
f4d578da | 9696 | { |
547fdef8 | 9697 | basic_block bb; |
eced69b5 | 9698 | timevar_push (TV_SCHED2); |
f4d578da | 9699 | ia64_final_schedule = 1; |
30028c85 | 9700 | |
547fdef8 BS |
9701 | /* We can't let modulo-sched prevent us from scheduling any bbs, |
9702 | since we need the final schedule to produce bundle information. */ | |
9703 | FOR_EACH_BB (bb) | |
9704 | bb->flags &= ~BB_DISABLE_SCHEDULE; | |
9705 | ||
30028c85 VM |
9706 | initiate_bundle_states (); |
9707 | ia64_nop = make_insn_raw (gen_nop ()); | |
9708 | PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX; | |
9709 | recog_memoized (ia64_nop); | |
9710 | clocks_length = get_max_uid () + 1; | |
5ead67f6 | 9711 | stops_p = XCNEWVEC (char, clocks_length); |
7400e46b | 9712 | |
30028c85 VM |
9713 | if (ia64_tune == PROCESSOR_ITANIUM2) |
9714 | { | |
9715 | pos_1 = get_cpu_unit_code ("2_1"); | |
9716 | pos_2 = get_cpu_unit_code ("2_2"); | |
9717 | pos_3 = get_cpu_unit_code ("2_3"); | |
9718 | pos_4 = get_cpu_unit_code ("2_4"); | |
9719 | pos_5 = get_cpu_unit_code ("2_5"); | |
9720 | pos_6 = get_cpu_unit_code ("2_6"); | |
9721 | _0mii_ = get_cpu_unit_code ("2b_0mii."); | |
9722 | _0mmi_ = get_cpu_unit_code ("2b_0mmi."); | |
9723 | _0mfi_ = get_cpu_unit_code ("2b_0mfi."); | |
9724 | _0mmf_ = get_cpu_unit_code ("2b_0mmf."); | |
9725 | _0bbb_ = get_cpu_unit_code ("2b_0bbb."); | |
9726 | _0mbb_ = get_cpu_unit_code ("2b_0mbb."); | |
9727 | _0mib_ = get_cpu_unit_code ("2b_0mib."); | |
9728 | _0mmb_ = get_cpu_unit_code ("2b_0mmb."); | |
9729 | _0mfb_ = get_cpu_unit_code ("2b_0mfb."); | |
9730 | _0mlx_ = get_cpu_unit_code ("2b_0mlx."); | |
9731 | _1mii_ = get_cpu_unit_code ("2b_1mii."); | |
9732 | _1mmi_ = get_cpu_unit_code ("2b_1mmi."); | |
9733 | _1mfi_ = get_cpu_unit_code ("2b_1mfi."); | |
9734 | _1mmf_ = get_cpu_unit_code ("2b_1mmf."); | |
9735 | _1bbb_ = get_cpu_unit_code ("2b_1bbb."); | |
9736 | _1mbb_ = get_cpu_unit_code ("2b_1mbb."); | |
9737 | _1mib_ = get_cpu_unit_code ("2b_1mib."); | |
9738 | _1mmb_ = get_cpu_unit_code ("2b_1mmb."); | |
9739 | _1mfb_ = get_cpu_unit_code ("2b_1mfb."); | |
9740 | _1mlx_ = get_cpu_unit_code ("2b_1mlx."); | |
9741 | } | |
9742 | else | |
9743 | { | |
9744 | pos_1 = get_cpu_unit_code ("1_1"); | |
9745 | pos_2 = get_cpu_unit_code ("1_2"); | |
9746 | pos_3 = get_cpu_unit_code ("1_3"); | |
9747 | pos_4 = get_cpu_unit_code ("1_4"); | |
9748 | pos_5 = get_cpu_unit_code ("1_5"); | |
9749 | pos_6 = get_cpu_unit_code ("1_6"); | |
9750 | _0mii_ = get_cpu_unit_code ("1b_0mii."); | |
9751 | _0mmi_ = get_cpu_unit_code ("1b_0mmi."); | |
9752 | _0mfi_ = get_cpu_unit_code ("1b_0mfi."); | |
9753 | _0mmf_ = get_cpu_unit_code ("1b_0mmf."); | |
9754 | _0bbb_ = get_cpu_unit_code ("1b_0bbb."); | |
9755 | _0mbb_ = get_cpu_unit_code ("1b_0mbb."); | |
9756 | _0mib_ = get_cpu_unit_code ("1b_0mib."); | |
9757 | _0mmb_ = get_cpu_unit_code ("1b_0mmb."); | |
9758 | _0mfb_ = get_cpu_unit_code ("1b_0mfb."); | |
9759 | _0mlx_ = get_cpu_unit_code ("1b_0mlx."); | |
9760 | _1mii_ = get_cpu_unit_code ("1b_1mii."); | |
9761 | _1mmi_ = get_cpu_unit_code ("1b_1mmi."); | |
9762 | _1mfi_ = get_cpu_unit_code ("1b_1mfi."); | |
9763 | _1mmf_ = get_cpu_unit_code ("1b_1mmf."); | |
9764 | _1bbb_ = get_cpu_unit_code ("1b_1bbb."); | |
9765 | _1mbb_ = get_cpu_unit_code ("1b_1mbb."); | |
9766 | _1mib_ = get_cpu_unit_code ("1b_1mib."); | |
9767 | _1mmb_ = get_cpu_unit_code ("1b_1mmb."); | |
9768 | _1mfb_ = get_cpu_unit_code ("1b_1mfb."); | |
9769 | _1mlx_ = get_cpu_unit_code ("1b_1mlx."); | |
9770 | } | |
388092d5 AB |
9771 | |
9772 | if (flag_selective_scheduling2 | |
9773 | && !maybe_skip_selective_scheduling ()) | |
9774 | run_selective_scheduling (); | |
9775 | else | |
9776 | schedule_ebbs (); | |
9777 | ||
9778 | /* Redo alignment computation, as it might gone wrong. */ | |
9779 | compute_alignments (); | |
9780 | ||
6fb5fa3c DB |
9781 | /* We cannot reuse this one because it has been corrupted by the |
9782 | evil glat. */ | |
30028c85 | 9783 | finish_bundle_states (); |
30028c85 | 9784 | free (stops_p); |
048d0d36 | 9785 | stops_p = NULL; |
c263766c | 9786 | emit_insn_group_barriers (dump_file); |
30028c85 | 9787 | |
f4d578da | 9788 | ia64_final_schedule = 0; |
eced69b5 | 9789 | timevar_pop (TV_SCHED2); |
f4d578da BS |
9790 | } |
9791 | else | |
c263766c | 9792 | emit_all_insn_group_barriers (dump_file); |
f2f90c63 | 9793 | |
6fb5fa3c DB |
9794 | df_analyze (); |
9795 | ||
f12f25a7 RH |
9796 | /* A call must not be the last instruction in a function, so that the |
9797 | return address is still within the function, so that unwinding works | |
9798 | properly. Note that IA-64 differs from dwarf2 on this point. */ | |
d5fabb58 | 9799 | if (ia64_except_unwind_info (&global_options) == UI_TARGET) |
f12f25a7 RH |
9800 | { |
9801 | rtx insn; | |
9802 | int saw_stop = 0; | |
9803 | ||
9804 | insn = get_last_insn (); | |
9805 | if (! INSN_P (insn)) | |
9806 | insn = prev_active_insn (insn); | |
2ca57608 | 9807 | if (insn) |
f12f25a7 | 9808 | { |
2ca57608 L |
9809 | /* Skip over insns that expand to nothing. */ |
9810 | while (GET_CODE (insn) == INSN | |
9811 | && get_attr_empty (insn) == EMPTY_YES) | |
9812 | { | |
9813 | if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
9814 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) | |
9815 | saw_stop = 1; | |
9816 | insn = prev_active_insn (insn); | |
9817 | } | |
9818 | if (GET_CODE (insn) == CALL_INSN) | |
9819 | { | |
9820 | if (! saw_stop) | |
9821 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9822 | emit_insn (gen_break_f ()); | |
9823 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9824 | } | |
f12f25a7 RH |
9825 | } |
9826 | } | |
9827 | ||
f2f90c63 | 9828 | emit_predicate_relation_info (); |
014a1138 | 9829 | |
2ba42841 | 9830 | if (flag_var_tracking) |
014a1138 JZ |
9831 | { |
9832 | timevar_push (TV_VAR_TRACKING); | |
9833 | variable_tracking_main (); | |
9834 | timevar_pop (TV_VAR_TRACKING); | |
9835 | } | |
0d475361 | 9836 | df_finish_pass (false); |
c65ebc55 JW |
9837 | } |
9838 | \f | |
9839 | /* Return true if REGNO is used by the epilogue. */ | |
9840 | ||
9841 | int | |
9c808aad | 9842 | ia64_epilogue_uses (int regno) |
c65ebc55 | 9843 | { |
6ca3c22f RH |
9844 | switch (regno) |
9845 | { | |
9846 | case R_GR (1): | |
b23ba0b8 RH |
9847 | /* With a call to a function in another module, we will write a new |
9848 | value to "gp". After returning from such a call, we need to make | |
9849 | sure the function restores the original gp-value, even if the | |
9850 | function itself does not use the gp anymore. */ | |
9851 | return !(TARGET_AUTO_PIC || TARGET_NO_PIC); | |
6ca3c22f RH |
9852 | |
9853 | case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3): | |
9854 | case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7): | |
9855 | /* For functions defined with the syscall_linkage attribute, all | |
9856 | input registers are marked as live at all function exits. This | |
9857 | prevents the register allocator from using the input registers, | |
9858 | which in turn makes it possible to restart a system call after | |
9859 | an interrupt without having to save/restore the input registers. | |
9860 | This also prevents kernel data from leaking to application code. */ | |
9861 | return lookup_attribute ("syscall_linkage", | |
9862 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL; | |
9863 | ||
9864 | case R_BR (0): | |
9865 | /* Conditional return patterns can't represent the use of `b0' as | |
9866 | the return address, so we force the value live this way. */ | |
9867 | return 1; | |
6b6c1201 | 9868 | |
6ca3c22f RH |
9869 | case AR_PFS_REGNUM: |
9870 | /* Likewise for ar.pfs, which is used by br.ret. */ | |
9871 | return 1; | |
5527bf14 | 9872 | |
6ca3c22f RH |
9873 | default: |
9874 | return 0; | |
9875 | } | |
c65ebc55 | 9876 | } |
15b5aef3 RH |
9877 | |
9878 | /* Return true if REGNO is used by the frame unwinder. */ | |
9879 | ||
9880 | int | |
9c808aad | 9881 | ia64_eh_uses (int regno) |
15b5aef3 | 9882 | { |
09639a83 | 9883 | unsigned int r; |
6fb5fa3c | 9884 | |
15b5aef3 RH |
9885 | if (! reload_completed) |
9886 | return 0; | |
9887 | ||
6fb5fa3c DB |
9888 | if (regno == 0) |
9889 | return 0; | |
9890 | ||
9891 | for (r = reg_save_b0; r <= reg_save_ar_lc; r++) | |
9892 | if (regno == current_frame_info.r[r] | |
9893 | || regno == emitted_frame_related_regs[r]) | |
9894 | return 1; | |
15b5aef3 RH |
9895 | |
9896 | return 0; | |
9897 | } | |
c65ebc55 | 9898 | \f |
1cdbd630 | 9899 | /* Return true if this goes in small data/bss. */ |
c65ebc55 JW |
9900 | |
9901 | /* ??? We could also support own long data here. Generating movl/add/ld8 | |
9902 | instead of addl,ld8/ld8. This makes the code bigger, but should make the | |
9903 | code faster because there is one less load. This also includes incomplete | |
9904 | types which can't go in sdata/sbss. */ | |
9905 | ||
ae46c4e0 | 9906 | static bool |
3101faab | 9907 | ia64_in_small_data_p (const_tree exp) |
ae46c4e0 RH |
9908 | { |
9909 | if (TARGET_NO_SDATA) | |
9910 | return false; | |
9911 | ||
3907500b RH |
9912 | /* We want to merge strings, so we never consider them small data. */ |
9913 | if (TREE_CODE (exp) == STRING_CST) | |
9914 | return false; | |
9915 | ||
4c494a15 ZW |
9916 | /* Functions are never small data. */ |
9917 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
9918 | return false; | |
9919 | ||
ae46c4e0 RH |
9920 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
9921 | { | |
9922 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); | |
826eb7ed | 9923 | |
ae46c4e0 | 9924 | if (strcmp (section, ".sdata") == 0 |
826eb7ed JB |
9925 | || strncmp (section, ".sdata.", 7) == 0 |
9926 | || strncmp (section, ".gnu.linkonce.s.", 16) == 0 | |
9927 | || strcmp (section, ".sbss") == 0 | |
9928 | || strncmp (section, ".sbss.", 6) == 0 | |
9929 | || strncmp (section, ".gnu.linkonce.sb.", 17) == 0) | |
ae46c4e0 RH |
9930 | return true; |
9931 | } | |
9932 | else | |
9933 | { | |
9934 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
9935 | ||
9936 | /* If this is an incomplete type with size 0, then we can't put it | |
9937 | in sdata because it might be too big when completed. */ | |
9938 | if (size > 0 && size <= ia64_section_threshold) | |
9939 | return true; | |
9940 | } | |
9941 | ||
9942 | return false; | |
9943 | } | |
0c96007e | 9944 | \f |
ad0fc698 JW |
9945 | /* Output assembly directives for prologue regions. */ |
9946 | ||
9947 | /* The current basic block number. */ | |
9948 | ||
e0082a72 | 9949 | static bool last_block; |
ad0fc698 JW |
9950 | |
9951 | /* True if we need a copy_state command at the start of the next block. */ | |
9952 | ||
e0082a72 | 9953 | static bool need_copy_state; |
ad0fc698 | 9954 | |
658f32fd AO |
9955 | #ifndef MAX_ARTIFICIAL_LABEL_BYTES |
9956 | # define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
9957 | #endif | |
9958 | ||
ad0fc698 JW |
9959 | /* The function emits unwind directives for the start of an epilogue. */ |
9960 | ||
9961 | static void | |
7d3c6cd8 RH |
9962 | process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED, |
9963 | bool unwind, bool frame ATTRIBUTE_UNUSED) | |
ad0fc698 JW |
9964 | { |
9965 | /* If this isn't the last block of the function, then we need to label the | |
9966 | current state, and copy it back in at the start of the next block. */ | |
9967 | ||
e0082a72 | 9968 | if (!last_block) |
ad0fc698 | 9969 | { |
658f32fd AO |
9970 | if (unwind) |
9971 | fprintf (asm_out_file, "\t.label_state %d\n", | |
9972 | ++cfun->machine->state_num); | |
e0082a72 | 9973 | need_copy_state = true; |
ad0fc698 JW |
9974 | } |
9975 | ||
658f32fd AO |
9976 | if (unwind) |
9977 | fprintf (asm_out_file, "\t.restore sp\n"); | |
ad0fc698 | 9978 | } |
0c96007e | 9979 | |
5c255b57 | 9980 | /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */ |
97e242b0 | 9981 | |
5c255b57 RH |
9982 | static void |
9983 | process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn, | |
9984 | bool unwind, bool frame) | |
0c96007e | 9985 | { |
0c96007e | 9986 | rtx dest = SET_DEST (pat); |
5c255b57 | 9987 | rtx src = SET_SRC (pat); |
0c96007e | 9988 | |
5c255b57 | 9989 | if (dest == stack_pointer_rtx) |
0c96007e AM |
9990 | { |
9991 | if (GET_CODE (src) == PLUS) | |
5c255b57 | 9992 | { |
0c96007e AM |
9993 | rtx op0 = XEXP (src, 0); |
9994 | rtx op1 = XEXP (src, 1); | |
e820471b NS |
9995 | |
9996 | gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT); | |
9997 | ||
9998 | if (INTVAL (op1) < 0) | |
658f32fd AO |
9999 | { |
10000 | gcc_assert (!frame_pointer_needed); | |
10001 | if (unwind) | |
5c255b57 RH |
10002 | fprintf (asm_out_file, |
10003 | "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n", | |
658f32fd | 10004 | -INTVAL (op1)); |
658f32fd | 10005 | } |
0186257f | 10006 | else |
658f32fd | 10007 | process_epilogue (asm_out_file, insn, unwind, frame); |
0c96007e | 10008 | } |
0186257f | 10009 | else |
e820471b | 10010 | { |
5c255b57 | 10011 | gcc_assert (src == hard_frame_pointer_rtx); |
658f32fd | 10012 | process_epilogue (asm_out_file, insn, unwind, frame); |
e820471b | 10013 | } |
5c255b57 RH |
10014 | } |
10015 | else if (dest == hard_frame_pointer_rtx) | |
10016 | { | |
10017 | gcc_assert (src == stack_pointer_rtx); | |
10018 | gcc_assert (frame_pointer_needed); | |
0186257f | 10019 | |
5c255b57 RH |
10020 | if (unwind) |
10021 | fprintf (asm_out_file, "\t.vframe r%d\n", | |
10022 | ia64_dbx_register_number (REGNO (dest))); | |
0c96007e | 10023 | } |
5c255b57 RH |
10024 | else |
10025 | gcc_unreachable (); | |
10026 | } | |
0c96007e | 10027 | |
5c255b57 | 10028 | /* This function processes a SET pattern for REG_CFA_REGISTER. */ |
97e242b0 | 10029 | |
5c255b57 RH |
10030 | static void |
10031 | process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind) | |
10032 | { | |
10033 | rtx dest = SET_DEST (pat); | |
10034 | rtx src = SET_SRC (pat); | |
5c255b57 | 10035 | int dest_regno = REGNO (dest); |
5f740973 | 10036 | int src_regno; |
97e242b0 | 10037 | |
5f740973 | 10038 | if (src == pc_rtx) |
5c255b57 | 10039 | { |
5c255b57 | 10040 | /* Saving return address pointer. */ |
5c255b57 RH |
10041 | if (unwind) |
10042 | fprintf (asm_out_file, "\t.save rp, r%d\n", | |
10043 | ia64_dbx_register_number (dest_regno)); | |
5f740973 RH |
10044 | return; |
10045 | } | |
10046 | ||
10047 | src_regno = REGNO (src); | |
97e242b0 | 10048 | |
5f740973 RH |
10049 | switch (src_regno) |
10050 | { | |
5c255b57 RH |
10051 | case PR_REG (0): |
10052 | gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]); | |
10053 | if (unwind) | |
10054 | fprintf (asm_out_file, "\t.save pr, r%d\n", | |
10055 | ia64_dbx_register_number (dest_regno)); | |
10056 | break; | |
97e242b0 | 10057 | |
5c255b57 RH |
10058 | case AR_UNAT_REGNUM: |
10059 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]); | |
10060 | if (unwind) | |
10061 | fprintf (asm_out_file, "\t.save ar.unat, r%d\n", | |
10062 | ia64_dbx_register_number (dest_regno)); | |
10063 | break; | |
97e242b0 | 10064 | |
5c255b57 RH |
10065 | case AR_LC_REGNUM: |
10066 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]); | |
10067 | if (unwind) | |
10068 | fprintf (asm_out_file, "\t.save ar.lc, r%d\n", | |
10069 | ia64_dbx_register_number (dest_regno)); | |
10070 | break; | |
10071 | ||
10072 | default: | |
10073 | /* Everything else should indicate being stored to memory. */ | |
10074 | gcc_unreachable (); | |
0c96007e | 10075 | } |
5c255b57 | 10076 | } |
97e242b0 | 10077 | |
5c255b57 | 10078 | /* This function processes a SET pattern for REG_CFA_OFFSET. */ |
97e242b0 | 10079 | |
5c255b57 RH |
10080 | static void |
10081 | process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind) | |
10082 | { | |
10083 | rtx dest = SET_DEST (pat); | |
10084 | rtx src = SET_SRC (pat); | |
10085 | int src_regno = REGNO (src); | |
10086 | const char *saveop; | |
10087 | HOST_WIDE_INT off; | |
10088 | rtx base; | |
0c96007e | 10089 | |
5c255b57 RH |
10090 | gcc_assert (MEM_P (dest)); |
10091 | if (GET_CODE (XEXP (dest, 0)) == REG) | |
10092 | { | |
10093 | base = XEXP (dest, 0); | |
10094 | off = 0; | |
10095 | } | |
10096 | else | |
10097 | { | |
10098 | gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS | |
10099 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT); | |
10100 | base = XEXP (XEXP (dest, 0), 0); | |
10101 | off = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
10102 | } | |
97e242b0 | 10103 | |
5c255b57 RH |
10104 | if (base == hard_frame_pointer_rtx) |
10105 | { | |
10106 | saveop = ".savepsp"; | |
10107 | off = - off; | |
10108 | } | |
10109 | else | |
10110 | { | |
10111 | gcc_assert (base == stack_pointer_rtx); | |
10112 | saveop = ".savesp"; | |
10113 | } | |
97e242b0 | 10114 | |
5c255b57 RH |
10115 | src_regno = REGNO (src); |
10116 | switch (src_regno) | |
10117 | { | |
10118 | case BR_REG (0): | |
10119 | gcc_assert (!current_frame_info.r[reg_save_b0]); | |
10120 | if (unwind) | |
10121 | fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10122 | saveop, off); | |
10123 | break; | |
97e242b0 | 10124 | |
5c255b57 RH |
10125 | case PR_REG (0): |
10126 | gcc_assert (!current_frame_info.r[reg_save_pr]); | |
10127 | if (unwind) | |
10128 | fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10129 | saveop, off); | |
10130 | break; | |
97e242b0 | 10131 | |
5c255b57 RH |
10132 | case AR_LC_REGNUM: |
10133 | gcc_assert (!current_frame_info.r[reg_save_ar_lc]); | |
10134 | if (unwind) | |
10135 | fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10136 | saveop, off); | |
10137 | break; | |
97e242b0 | 10138 | |
5c255b57 RH |
10139 | case AR_PFS_REGNUM: |
10140 | gcc_assert (!current_frame_info.r[reg_save_ar_pfs]); | |
10141 | if (unwind) | |
10142 | fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10143 | saveop, off); | |
10144 | break; | |
97e242b0 | 10145 | |
5c255b57 RH |
10146 | case AR_UNAT_REGNUM: |
10147 | gcc_assert (!current_frame_info.r[reg_save_ar_unat]); | |
10148 | if (unwind) | |
10149 | fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10150 | saveop, off); | |
10151 | break; | |
97e242b0 | 10152 | |
5c255b57 RH |
10153 | case GR_REG (4): |
10154 | case GR_REG (5): | |
10155 | case GR_REG (6): | |
10156 | case GR_REG (7): | |
10157 | if (unwind) | |
10158 | fprintf (asm_out_file, "\t.save.g 0x%x\n", | |
10159 | 1 << (src_regno - GR_REG (4))); | |
10160 | break; | |
97e242b0 | 10161 | |
5c255b57 RH |
10162 | case BR_REG (1): |
10163 | case BR_REG (2): | |
10164 | case BR_REG (3): | |
10165 | case BR_REG (4): | |
10166 | case BR_REG (5): | |
10167 | if (unwind) | |
10168 | fprintf (asm_out_file, "\t.save.b 0x%x\n", | |
10169 | 1 << (src_regno - BR_REG (1))); | |
10170 | break; | |
97e242b0 | 10171 | |
5c255b57 RH |
10172 | case FR_REG (2): |
10173 | case FR_REG (3): | |
10174 | case FR_REG (4): | |
10175 | case FR_REG (5): | |
10176 | if (unwind) | |
10177 | fprintf (asm_out_file, "\t.save.f 0x%x\n", | |
10178 | 1 << (src_regno - FR_REG (2))); | |
10179 | break; | |
97e242b0 | 10180 | |
5c255b57 RH |
10181 | case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19): |
10182 | case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23): | |
10183 | case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27): | |
10184 | case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31): | |
10185 | if (unwind) | |
10186 | fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n", | |
10187 | 1 << (src_regno - FR_REG (12))); | |
10188 | break; | |
97e242b0 | 10189 | |
5c255b57 RH |
10190 | default: |
10191 | /* ??? For some reason we mark other general registers, even those | |
10192 | we can't represent in the unwind info. Ignore them. */ | |
10193 | break; | |
10194 | } | |
0c96007e AM |
10195 | } |
10196 | ||
0c96007e AM |
10197 | /* This function looks at a single insn and emits any directives |
10198 | required to unwind this insn. */ | |
5c255b57 | 10199 | |
a68b5e52 RH |
10200 | static void |
10201 | ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn) | |
0c96007e | 10202 | { |
d5fabb58 | 10203 | bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET; |
658f32fd | 10204 | bool frame = dwarf2out_do_frame (); |
5c255b57 RH |
10205 | rtx note, pat; |
10206 | bool handled_one; | |
10207 | ||
10208 | if (!unwind && !frame) | |
10209 | return; | |
658f32fd | 10210 | |
5c255b57 | 10211 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
0c96007e | 10212 | { |
5c255b57 | 10213 | last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR; |
97e242b0 | 10214 | |
5c255b57 RH |
10215 | /* Restore unwind state from immediately before the epilogue. */ |
10216 | if (need_copy_state) | |
ad0fc698 | 10217 | { |
5c255b57 | 10218 | if (unwind) |
ad0fc698 | 10219 | { |
5c255b57 RH |
10220 | fprintf (asm_out_file, "\t.body\n"); |
10221 | fprintf (asm_out_file, "\t.copy_state %d\n", | |
10222 | cfun->machine->state_num); | |
ad0fc698 | 10223 | } |
5c255b57 | 10224 | need_copy_state = false; |
ad0fc698 | 10225 | } |
5c255b57 | 10226 | } |
ad0fc698 | 10227 | |
5c255b57 RH |
10228 | if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn)) |
10229 | return; | |
10230 | ||
10231 | /* Look for the ALLOC insn. */ | |
10232 | if (INSN_CODE (insn) == CODE_FOR_alloc) | |
10233 | { | |
10234 | rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
10235 | int dest_regno = REGNO (dest); | |
ad0fc698 | 10236 | |
5c255b57 RH |
10237 | /* If this is the final destination for ar.pfs, then this must |
10238 | be the alloc in the prologue. */ | |
10239 | if (dest_regno == current_frame_info.r[reg_save_ar_pfs]) | |
10240 | { | |
10241 | if (unwind) | |
10242 | fprintf (asm_out_file, "\t.save ar.pfs, r%d\n", | |
10243 | ia64_dbx_register_number (dest_regno)); | |
10244 | } | |
97e242b0 | 10245 | else |
5c255b57 RH |
10246 | { |
10247 | /* This must be an alloc before a sibcall. We must drop the | |
10248 | old frame info. The easiest way to drop the old frame | |
10249 | info is to ensure we had a ".restore sp" directive | |
10250 | followed by a new prologue. If the procedure doesn't | |
10251 | have a memory-stack frame, we'll issue a dummy ".restore | |
10252 | sp" now. */ | |
10253 | if (current_frame_info.total_size == 0 && !frame_pointer_needed) | |
10254 | /* if haven't done process_epilogue() yet, do it now */ | |
10255 | process_epilogue (asm_out_file, insn, unwind, frame); | |
10256 | if (unwind) | |
10257 | fprintf (asm_out_file, "\t.prologue\n"); | |
10258 | } | |
10259 | return; | |
10260 | } | |
0c96007e | 10261 | |
5c255b57 RH |
10262 | handled_one = false; |
10263 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
10264 | switch (REG_NOTE_KIND (note)) | |
10265 | { | |
10266 | case REG_CFA_ADJUST_CFA: | |
10267 | pat = XEXP (note, 0); | |
10268 | if (pat == NULL) | |
10269 | pat = PATTERN (insn); | |
10270 | process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame); | |
10271 | handled_one = true; | |
10272 | break; | |
809d4ef1 | 10273 | |
5c255b57 RH |
10274 | case REG_CFA_OFFSET: |
10275 | pat = XEXP (note, 0); | |
10276 | if (pat == NULL) | |
10277 | pat = PATTERN (insn); | |
10278 | process_cfa_offset (asm_out_file, pat, unwind); | |
10279 | handled_one = true; | |
10280 | break; | |
809d4ef1 | 10281 | |
5c255b57 RH |
10282 | case REG_CFA_REGISTER: |
10283 | pat = XEXP (note, 0); | |
10284 | if (pat == NULL) | |
10285 | pat = PATTERN (insn); | |
10286 | process_cfa_register (asm_out_file, pat, unwind); | |
10287 | handled_one = true; | |
10288 | break; | |
10289 | ||
10290 | case REG_FRAME_RELATED_EXPR: | |
10291 | case REG_CFA_DEF_CFA: | |
10292 | case REG_CFA_EXPRESSION: | |
10293 | case REG_CFA_RESTORE: | |
10294 | case REG_CFA_SET_VDRAP: | |
10295 | /* Not used in the ia64 port. */ | |
10296 | gcc_unreachable (); | |
10297 | ||
10298 | default: | |
10299 | /* Not a frame-related note. */ | |
10300 | break; | |
10301 | } | |
10302 | ||
10303 | /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the | |
10304 | explicit action to take. No guessing required. */ | |
10305 | gcc_assert (handled_one); | |
0c96007e | 10306 | } |
c65ebc55 | 10307 | |
a68b5e52 RH |
10308 | /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */ |
10309 | ||
10310 | static void | |
10311 | ia64_asm_emit_except_personality (rtx personality) | |
10312 | { | |
10313 | fputs ("\t.personality\t", asm_out_file); | |
10314 | output_addr_const (asm_out_file, personality); | |
10315 | fputc ('\n', asm_out_file); | |
10316 | } | |
10317 | ||
10318 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */ | |
10319 | ||
10320 | static void | |
10321 | ia64_asm_init_sections (void) | |
10322 | { | |
10323 | exception_section = get_unnamed_section (0, output_section_asm_op, | |
10324 | "\t.handlerdata"); | |
10325 | } | |
f0a0390e RH |
10326 | |
10327 | /* Implement TARGET_DEBUG_UNWIND_INFO. */ | |
10328 | ||
10329 | static enum unwind_info_type | |
10330 | ia64_debug_unwind_info (void) | |
10331 | { | |
10332 | return UI_TARGET; | |
10333 | } | |
0551c32d | 10334 | \f |
af795c3c RH |
10335 | enum ia64_builtins |
10336 | { | |
10337 | IA64_BUILTIN_BSP, | |
c252db20 L |
10338 | IA64_BUILTIN_COPYSIGNQ, |
10339 | IA64_BUILTIN_FABSQ, | |
10340 | IA64_BUILTIN_FLUSHRS, | |
fcb82ab0 | 10341 | IA64_BUILTIN_INFQ, |
b14446e2 SE |
10342 | IA64_BUILTIN_HUGE_VALQ, |
10343 | IA64_BUILTIN_max | |
af795c3c RH |
10344 | }; |
10345 | ||
b14446e2 SE |
10346 | static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max]; |
10347 | ||
c65ebc55 | 10348 | void |
9c808aad | 10349 | ia64_init_builtins (void) |
c65ebc55 | 10350 | { |
9649812a | 10351 | tree fpreg_type; |
bf9ab6b6 | 10352 | tree float80_type; |
b14446e2 | 10353 | tree decl; |
9649812a MM |
10354 | |
10355 | /* The __fpreg type. */ | |
10356 | fpreg_type = make_node (REAL_TYPE); | |
4de67c26 | 10357 | TYPE_PRECISION (fpreg_type) = 82; |
9649812a MM |
10358 | layout_type (fpreg_type); |
10359 | (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg"); | |
10360 | ||
10361 | /* The __float80 type. */ | |
bf9ab6b6 | 10362 | float80_type = make_node (REAL_TYPE); |
968a7562 | 10363 | TYPE_PRECISION (float80_type) = 80; |
bf9ab6b6 MM |
10364 | layout_type (float80_type); |
10365 | (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); | |
9649812a MM |
10366 | |
10367 | /* The __float128 type. */ | |
02befdf4 | 10368 | if (!TARGET_HPUX) |
9649812a | 10369 | { |
b14446e2 | 10370 | tree ftype; |
9649812a | 10371 | tree float128_type = make_node (REAL_TYPE); |
c252db20 | 10372 | |
9649812a MM |
10373 | TYPE_PRECISION (float128_type) = 128; |
10374 | layout_type (float128_type); | |
10375 | (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); | |
c252db20 L |
10376 | |
10377 | /* TFmode support builtins. */ | |
c0676219 | 10378 | ftype = build_function_type_list (float128_type, NULL_TREE); |
b14446e2 SE |
10379 | decl = add_builtin_function ("__builtin_infq", ftype, |
10380 | IA64_BUILTIN_INFQ, BUILT_IN_MD, | |
10381 | NULL, NULL_TREE); | |
10382 | ia64_builtins[IA64_BUILTIN_INFQ] = decl; | |
c252db20 | 10383 | |
b14446e2 SE |
10384 | decl = add_builtin_function ("__builtin_huge_valq", ftype, |
10385 | IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
10386 | NULL, NULL_TREE); | |
10387 | ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl; | |
fcb82ab0 | 10388 | |
c252db20 L |
10389 | ftype = build_function_type_list (float128_type, |
10390 | float128_type, | |
10391 | NULL_TREE); | |
10392 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
10393 | IA64_BUILTIN_FABSQ, BUILT_IN_MD, | |
10394 | "__fabstf2", NULL_TREE); | |
10395 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10396 | ia64_builtins[IA64_BUILTIN_FABSQ] = decl; |
c252db20 L |
10397 | |
10398 | ftype = build_function_type_list (float128_type, | |
10399 | float128_type, | |
10400 | float128_type, | |
10401 | NULL_TREE); | |
10402 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
10403 | IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
10404 | "__copysigntf3", NULL_TREE); | |
10405 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10406 | ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl; |
9649812a MM |
10407 | } |
10408 | else | |
02befdf4 | 10409 | /* Under HPUX, this is a synonym for "long double". */ |
9649812a MM |
10410 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, |
10411 | "__float128"); | |
10412 | ||
f2972bf8 | 10413 | /* Fwrite on VMS is non-standard. */ |
171da07a RH |
10414 | #if TARGET_ABI_OPEN_VMS |
10415 | vms_patch_builtins (); | |
10416 | #endif | |
f2972bf8 | 10417 | |
6e34d3a3 | 10418 | #define def_builtin(name, type, code) \ |
c79efc4d RÁE |
10419 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, \ |
10420 | NULL, NULL_TREE) | |
0551c32d | 10421 | |
b14446e2 | 10422 | decl = def_builtin ("__builtin_ia64_bsp", |
c0676219 NF |
10423 | build_function_type_list (ptr_type_node, NULL_TREE), |
10424 | IA64_BUILTIN_BSP); | |
b14446e2 | 10425 | ia64_builtins[IA64_BUILTIN_BSP] = decl; |
ce152ef8 | 10426 | |
b14446e2 | 10427 | decl = def_builtin ("__builtin_ia64_flushrs", |
c0676219 NF |
10428 | build_function_type_list (void_type_node, NULL_TREE), |
10429 | IA64_BUILTIN_FLUSHRS); | |
b14446e2 | 10430 | ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl; |
ce152ef8 | 10431 | |
0551c32d | 10432 | #undef def_builtin |
7d522000 SE |
10433 | |
10434 | if (TARGET_HPUX) | |
10435 | { | |
ccea4a27 | 10436 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) |
e79983f4 | 10437 | set_user_assembler_name (decl, "_Isfinite"); |
ccea4a27 | 10438 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) |
e79983f4 | 10439 | set_user_assembler_name (decl, "_Isfinitef"); |
ccea4a27 | 10440 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE) |
e79983f4 | 10441 | set_user_assembler_name (decl, "_Isfinitef128"); |
7d522000 | 10442 | } |
c65ebc55 JW |
10443 | } |
10444 | ||
c65ebc55 | 10445 | rtx |
9c808aad AJ |
10446 | ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
10447 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
10448 | int ignore ATTRIBUTE_UNUSED) | |
c65ebc55 | 10449 | { |
767fad4c | 10450 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
97e242b0 | 10451 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
c65ebc55 JW |
10452 | |
10453 | switch (fcode) | |
10454 | { | |
ce152ef8 | 10455 | case IA64_BUILTIN_BSP: |
0551c32d RH |
10456 | if (! target || ! register_operand (target, DImode)) |
10457 | target = gen_reg_rtx (DImode); | |
10458 | emit_insn (gen_bsp_value (target)); | |
8419b675 RK |
10459 | #ifdef POINTERS_EXTEND_UNSIGNED |
10460 | target = convert_memory_address (ptr_mode, target); | |
10461 | #endif | |
0551c32d | 10462 | return target; |
ce152ef8 AM |
10463 | |
10464 | case IA64_BUILTIN_FLUSHRS: | |
3b572406 RH |
10465 | emit_insn (gen_flushrs ()); |
10466 | return const0_rtx; | |
ce152ef8 | 10467 | |
c252db20 | 10468 | case IA64_BUILTIN_INFQ: |
fcb82ab0 | 10469 | case IA64_BUILTIN_HUGE_VALQ: |
c252db20 | 10470 | { |
6aad068a | 10471 | enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); |
c252db20 L |
10472 | REAL_VALUE_TYPE inf; |
10473 | rtx tmp; | |
10474 | ||
10475 | real_inf (&inf); | |
6aad068a | 10476 | tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode); |
c252db20 | 10477 | |
6aad068a | 10478 | tmp = validize_mem (force_const_mem (target_mode, tmp)); |
c252db20 L |
10479 | |
10480 | if (target == 0) | |
6aad068a | 10481 | target = gen_reg_rtx (target_mode); |
c252db20 L |
10482 | |
10483 | emit_move_insn (target, tmp); | |
10484 | return target; | |
10485 | } | |
10486 | ||
10487 | case IA64_BUILTIN_FABSQ: | |
10488 | case IA64_BUILTIN_COPYSIGNQ: | |
10489 | return expand_call (exp, target, ignore); | |
10490 | ||
c65ebc55 | 10491 | default: |
c252db20 | 10492 | gcc_unreachable (); |
c65ebc55 JW |
10493 | } |
10494 | ||
0551c32d | 10495 | return NULL_RTX; |
c65ebc55 | 10496 | } |
0d7839da | 10497 | |
b14446e2 SE |
10498 | /* Return the ia64 builtin for CODE. */ |
10499 | ||
10500 | static tree | |
10501 | ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
10502 | { | |
10503 | if (code >= IA64_BUILTIN_max) | |
10504 | return error_mark_node; | |
10505 | ||
10506 | return ia64_builtins[code]; | |
10507 | } | |
10508 | ||
0d7839da SE |
10509 | /* For the HP-UX IA64 aggregate parameters are passed stored in the |
10510 | most significant bits of the stack slot. */ | |
10511 | ||
10512 | enum direction | |
586de218 | 10513 | ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type) |
0d7839da | 10514 | { |
ed168e45 | 10515 | /* Exception to normal case for structures/unions/etc. */ |
0d7839da SE |
10516 | |
10517 | if (type && AGGREGATE_TYPE_P (type) | |
10518 | && int_size_in_bytes (type) < UNITS_PER_WORD) | |
10519 | return upward; | |
10520 | ||
d3704c46 KH |
10521 | /* Fall back to the default. */ |
10522 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
0d7839da | 10523 | } |
686f3bf0 | 10524 | |
c47c29c8 L |
10525 | /* Emit text to declare externally defined variables and functions, because |
10526 | the Intel assembler does not support undefined externals. */ | |
686f3bf0 | 10527 | |
c47c29c8 L |
10528 | void |
10529 | ia64_asm_output_external (FILE *file, tree decl, const char *name) | |
686f3bf0 | 10530 | { |
c47c29c8 L |
10531 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
10532 | set in order to avoid putting out names that are never really | |
10533 | used. */ | |
10534 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
686f3bf0 | 10535 | { |
c47c29c8 | 10536 | /* maybe_assemble_visibility will return 1 if the assembler |
2e226e66 | 10537 | visibility directive is output. */ |
c47c29c8 L |
10538 | int need_visibility = ((*targetm.binds_local_p) (decl) |
10539 | && maybe_assemble_visibility (decl)); | |
57d4f65c | 10540 | |
c47c29c8 L |
10541 | /* GNU as does not need anything here, but the HP linker does |
10542 | need something for external functions. */ | |
10543 | if ((TARGET_HPUX_LD || !TARGET_GNU_AS) | |
10544 | && TREE_CODE (decl) == FUNCTION_DECL) | |
812b587e | 10545 | (*targetm.asm_out.globalize_decl_name) (file, decl); |
c47c29c8 L |
10546 | else if (need_visibility && !TARGET_GNU_AS) |
10547 | (*targetm.asm_out.globalize_label) (file, name); | |
686f3bf0 SE |
10548 | } |
10549 | } | |
10550 | ||
1f7aa7cd | 10551 | /* Set SImode div/mod functions, init_integral_libfuncs only initializes |
6bc709c1 L |
10552 | modes of word_mode and larger. Rename the TFmode libfuncs using the |
10553 | HPUX conventions. __divtf3 is used for XFmode. We need to keep it for | |
10554 | backward compatibility. */ | |
1f7aa7cd SE |
10555 | |
10556 | static void | |
10557 | ia64_init_libfuncs (void) | |
10558 | { | |
10559 | set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); | |
10560 | set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); | |
10561 | set_optab_libfunc (smod_optab, SImode, "__modsi3"); | |
10562 | set_optab_libfunc (umod_optab, SImode, "__umodsi3"); | |
6bc709c1 L |
10563 | |
10564 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
10565 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
10566 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
10567 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
10568 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
10569 | ||
10570 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); | |
10571 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
10572 | set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad"); | |
10573 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
10574 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
10575 | set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80"); | |
10576 | ||
10577 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl"); | |
10578 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
4a73d865 | 10579 | set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad"); |
6bc709c1 L |
10580 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl"); |
10581 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl"); | |
10582 | ||
10583 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
10584 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
4a73d865 | 10585 | set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad"); |
2a3ebe77 JM |
10586 | /* HP-UX 11.23 libc does not have a function for unsigned |
10587 | SImode-to-TFmode conversion. */ | |
10588 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad"); | |
1f7aa7cd SE |
10589 | } |
10590 | ||
c15c90bb | 10591 | /* Rename all the TFmode libfuncs using the HPUX conventions. */ |
738e7b39 | 10592 | |
c15c90bb ZW |
10593 | static void |
10594 | ia64_hpux_init_libfuncs (void) | |
10595 | { | |
1f7aa7cd SE |
10596 | ia64_init_libfuncs (); |
10597 | ||
bdbba3c2 SE |
10598 | /* The HP SI millicode division and mod functions expect DI arguments. |
10599 | By turning them off completely we avoid using both libgcc and the | |
10600 | non-standard millicode routines and use the HP DI millicode routines | |
10601 | instead. */ | |
10602 | ||
10603 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10604 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10605 | set_optab_libfunc (smod_optab, SImode, 0); | |
10606 | set_optab_libfunc (umod_optab, SImode, 0); | |
10607 | ||
10608 | set_optab_libfunc (sdiv_optab, DImode, "__milli_divI"); | |
10609 | set_optab_libfunc (udiv_optab, DImode, "__milli_divU"); | |
10610 | set_optab_libfunc (smod_optab, DImode, "__milli_remI"); | |
10611 | set_optab_libfunc (umod_optab, DImode, "__milli_remU"); | |
10612 | ||
10613 | /* HP-UX libc has TF min/max/abs routines in it. */ | |
c15c90bb ZW |
10614 | set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin"); |
10615 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
10616 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
c15c90bb | 10617 | |
24ea7948 ZW |
10618 | /* ia64_expand_compare uses this. */ |
10619 | cmptf_libfunc = init_one_libfunc ("_U_Qfcmp"); | |
10620 | ||
10621 | /* These should never be used. */ | |
10622 | set_optab_libfunc (eq_optab, TFmode, 0); | |
10623 | set_optab_libfunc (ne_optab, TFmode, 0); | |
10624 | set_optab_libfunc (gt_optab, TFmode, 0); | |
10625 | set_optab_libfunc (ge_optab, TFmode, 0); | |
10626 | set_optab_libfunc (lt_optab, TFmode, 0); | |
10627 | set_optab_libfunc (le_optab, TFmode, 0); | |
c15c90bb | 10628 | } |
738e7b39 RK |
10629 | |
10630 | /* Rename the division and modulus functions in VMS. */ | |
10631 | ||
10632 | static void | |
10633 | ia64_vms_init_libfuncs (void) | |
10634 | { | |
10635 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
10636 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
10637 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
10638 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
10639 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
10640 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
10641 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
10642 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
f2972bf8 DR |
10643 | abort_libfunc = init_one_libfunc ("decc$abort"); |
10644 | memcmp_libfunc = init_one_libfunc ("decc$memcmp"); | |
10645 | #ifdef MEM_LIBFUNCS_INIT | |
10646 | MEM_LIBFUNCS_INIT; | |
10647 | #endif | |
738e7b39 | 10648 | } |
6bc709c1 L |
10649 | |
10650 | /* Rename the TFmode libfuncs available from soft-fp in glibc using | |
10651 | the HPUX conventions. */ | |
10652 | ||
10653 | static void | |
10654 | ia64_sysv4_init_libfuncs (void) | |
10655 | { | |
10656 | ia64_init_libfuncs (); | |
10657 | ||
10658 | /* These functions are not part of the HPUX TFmode interface. We | |
10659 | use them instead of _U_Qfcmp, which doesn't work the way we | |
10660 | expect. */ | |
10661 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); | |
10662 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
10663 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
10664 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
10665 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
10666 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
10667 | ||
10668 | /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in | |
10669 | glibc doesn't have them. */ | |
10670 | } | |
c252db20 L |
10671 | |
10672 | /* Use soft-fp. */ | |
10673 | ||
10674 | static void | |
10675 | ia64_soft_fp_init_libfuncs (void) | |
10676 | { | |
10677 | } | |
f2972bf8 DR |
10678 | |
10679 | static bool | |
10680 | ia64_vms_valid_pointer_mode (enum machine_mode mode) | |
10681 | { | |
10682 | return (mode == SImode || mode == DImode); | |
10683 | } | |
ae46c4e0 | 10684 | \f |
9b580a0b RH |
10685 | /* For HPUX, it is illegal to have relocations in shared segments. */ |
10686 | ||
10687 | static int | |
10688 | ia64_hpux_reloc_rw_mask (void) | |
10689 | { | |
10690 | return 3; | |
10691 | } | |
10692 | ||
10693 | /* For others, relax this so that relocations to local data goes in | |
10694 | read-only segments, but we still cannot allow global relocations | |
10695 | in read-only segments. */ | |
10696 | ||
10697 | static int | |
10698 | ia64_reloc_rw_mask (void) | |
10699 | { | |
10700 | return flag_pic ? 3 : 2; | |
10701 | } | |
10702 | ||
d6b5193b RS |
10703 | /* Return the section to use for X. The only special thing we do here |
10704 | is to honor small data. */ | |
b64a1b53 | 10705 | |
d6b5193b | 10706 | static section * |
9c808aad AJ |
10707 | ia64_select_rtx_section (enum machine_mode mode, rtx x, |
10708 | unsigned HOST_WIDE_INT align) | |
b64a1b53 RH |
10709 | { |
10710 | if (GET_MODE_SIZE (mode) > 0 | |
1f4a2e84 SE |
10711 | && GET_MODE_SIZE (mode) <= ia64_section_threshold |
10712 | && !TARGET_NO_SDATA) | |
d6b5193b | 10713 | return sdata_section; |
b64a1b53 | 10714 | else |
d6b5193b | 10715 | return default_elf_select_rtx_section (mode, x, align); |
b64a1b53 RH |
10716 | } |
10717 | ||
1e1bd14e | 10718 | static unsigned int |
abb8b19a AM |
10719 | ia64_section_type_flags (tree decl, const char *name, int reloc) |
10720 | { | |
10721 | unsigned int flags = 0; | |
10722 | ||
10723 | if (strcmp (name, ".sdata") == 0 | |
10724 | || strncmp (name, ".sdata.", 7) == 0 | |
10725 | || strncmp (name, ".gnu.linkonce.s.", 16) == 0 | |
10726 | || strncmp (name, ".sdata2.", 8) == 0 | |
10727 | || strncmp (name, ".gnu.linkonce.s2.", 17) == 0 | |
10728 | || strcmp (name, ".sbss") == 0 | |
10729 | || strncmp (name, ".sbss.", 6) == 0 | |
10730 | || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) | |
10731 | flags = SECTION_SMALL; | |
10732 | ||
9b580a0b | 10733 | flags |= default_section_type_flags (decl, name, reloc); |
abb8b19a | 10734 | return flags; |
1e1bd14e RH |
10735 | } |
10736 | ||
57782ad8 MM |
10737 | /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a |
10738 | structure type and that the address of that type should be passed | |
10739 | in out0, rather than in r8. */ | |
10740 | ||
10741 | static bool | |
10742 | ia64_struct_retval_addr_is_first_parm_p (tree fntype) | |
10743 | { | |
10744 | tree ret_type = TREE_TYPE (fntype); | |
10745 | ||
10746 | /* The Itanium C++ ABI requires that out0, rather than r8, be used | |
10747 | as the structure return address parameter, if the return value | |
10748 | type has a non-trivial copy constructor or destructor. It is not | |
10749 | clear if this same convention should be used for other | |
10750 | programming languages. Until G++ 3.4, we incorrectly used r8 for | |
10751 | these return values. */ | |
10752 | return (abi_version_at_least (2) | |
10753 | && ret_type | |
10754 | && TYPE_MODE (ret_type) == BLKmode | |
10755 | && TREE_ADDRESSABLE (ret_type) | |
10756 | && strcmp (lang_hooks.name, "GNU C++") == 0); | |
10757 | } | |
1e1bd14e | 10758 | |
5f13cfc6 RH |
10759 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
10760 | declaration for the thunk function itself, FUNCTION is the decl for | |
10761 | the target function. DELTA is an immediate constant offset to be | |
272d0bee | 10762 | added to THIS. If VCALL_OFFSET is nonzero, the word at |
5f13cfc6 RH |
10763 | *(*this + vcall_offset) should be added to THIS. */ |
10764 | ||
c590b625 | 10765 | static void |
9c808aad AJ |
10766 | ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
10767 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
10768 | tree function) | |
483ab821 | 10769 | { |
0a2aaacc | 10770 | rtx this_rtx, insn, funexp; |
57782ad8 MM |
10771 | unsigned int this_parmno; |
10772 | unsigned int this_regno; | |
13f70342 | 10773 | rtx delta_rtx; |
5f13cfc6 | 10774 | |
599aedd9 | 10775 | reload_completed = 1; |
fe3ad572 | 10776 | epilogue_completed = 1; |
599aedd9 | 10777 | |
5f13cfc6 RH |
10778 | /* Set things up as ia64_expand_prologue might. */ |
10779 | last_scratch_gr_reg = 15; | |
10780 | ||
10781 | memset (¤t_frame_info, 0, sizeof (current_frame_info)); | |
10782 | current_frame_info.spill_cfa_off = -16; | |
10783 | current_frame_info.n_input_regs = 1; | |
10784 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
10785 | ||
5f13cfc6 | 10786 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 10787 | emit_note (NOTE_INSN_PROLOGUE_END); |
5f13cfc6 | 10788 | |
57782ad8 MM |
10789 | /* Figure out whether "this" will be the first parameter (the |
10790 | typical case) or the second parameter (as happens when the | |
10791 | virtual function returns certain class objects). */ | |
10792 | this_parmno | |
10793 | = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk)) | |
10794 | ? 1 : 0); | |
10795 | this_regno = IN_REG (this_parmno); | |
10796 | if (!TARGET_REG_NAMES) | |
10797 | reg_names[this_regno] = ia64_reg_numbers[this_parmno]; | |
10798 | ||
0a2aaacc | 10799 | this_rtx = gen_rtx_REG (Pmode, this_regno); |
13f70342 RH |
10800 | |
10801 | /* Apply the constant offset, if required. */ | |
10802 | delta_rtx = GEN_INT (delta); | |
36c216e5 MM |
10803 | if (TARGET_ILP32) |
10804 | { | |
57782ad8 | 10805 | rtx tmp = gen_rtx_REG (ptr_mode, this_regno); |
36c216e5 | 10806 | REG_POINTER (tmp) = 1; |
13f70342 | 10807 | if (delta && satisfies_constraint_I (delta_rtx)) |
36c216e5 | 10808 | { |
0a2aaacc | 10809 | emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx)); |
36c216e5 MM |
10810 | delta = 0; |
10811 | } | |
10812 | else | |
0a2aaacc | 10813 | emit_insn (gen_ptr_extend (this_rtx, tmp)); |
36c216e5 | 10814 | } |
5f13cfc6 RH |
10815 | if (delta) |
10816 | { | |
13f70342 | 10817 | if (!satisfies_constraint_I (delta_rtx)) |
5f13cfc6 RH |
10818 | { |
10819 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10820 | emit_move_insn (tmp, delta_rtx); | |
10821 | delta_rtx = tmp; | |
10822 | } | |
0a2aaacc | 10823 | emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx)); |
5f13cfc6 RH |
10824 | } |
10825 | ||
10826 | /* Apply the offset from the vtable, if required. */ | |
10827 | if (vcall_offset) | |
10828 | { | |
10829 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
10830 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10831 | ||
36c216e5 MM |
10832 | if (TARGET_ILP32) |
10833 | { | |
10834 | rtx t = gen_rtx_REG (ptr_mode, 2); | |
10835 | REG_POINTER (t) = 1; | |
0a2aaacc | 10836 | emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx)); |
13f70342 | 10837 | if (satisfies_constraint_I (vcall_offset_rtx)) |
36c216e5 | 10838 | { |
13f70342 | 10839 | emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx)); |
36c216e5 MM |
10840 | vcall_offset = 0; |
10841 | } | |
10842 | else | |
10843 | emit_insn (gen_ptr_extend (tmp, t)); | |
10844 | } | |
10845 | else | |
0a2aaacc | 10846 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
5f13cfc6 | 10847 | |
36c216e5 | 10848 | if (vcall_offset) |
5f13cfc6 | 10849 | { |
13f70342 | 10850 | if (!satisfies_constraint_J (vcall_offset_rtx)) |
36c216e5 MM |
10851 | { |
10852 | rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ()); | |
10853 | emit_move_insn (tmp2, vcall_offset_rtx); | |
10854 | vcall_offset_rtx = tmp2; | |
10855 | } | |
10856 | emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
5f13cfc6 | 10857 | } |
5f13cfc6 | 10858 | |
36c216e5 | 10859 | if (TARGET_ILP32) |
13f70342 | 10860 | emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp))); |
36c216e5 MM |
10861 | else |
10862 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
5f13cfc6 | 10863 | |
0a2aaacc | 10864 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
5f13cfc6 RH |
10865 | } |
10866 | ||
10867 | /* Generate a tail call to the target function. */ | |
10868 | if (! TREE_USED (function)) | |
10869 | { | |
10870 | assemble_external (function); | |
10871 | TREE_USED (function) = 1; | |
10872 | } | |
10873 | funexp = XEXP (DECL_RTL (function), 0); | |
10874 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
10875 | ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1); | |
10876 | insn = get_last_insn (); | |
10877 | SIBLING_CALL_P (insn) = 1; | |
599aedd9 RH |
10878 | |
10879 | /* Code generation for calls relies on splitting. */ | |
10880 | reload_completed = 1; | |
fe3ad572 | 10881 | epilogue_completed = 1; |
599aedd9 RH |
10882 | try_split (PATTERN (insn), insn, 0); |
10883 | ||
5f13cfc6 RH |
10884 | emit_barrier (); |
10885 | ||
10886 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
10887 | There's not really enough bulk here to make other passes such as | |
10888 | instruction scheduling worth while. Note that use_thunk calls | |
10889 | assemble_start_function and assemble_end_function. */ | |
599aedd9 | 10890 | |
55e092c4 | 10891 | insn_locators_alloc (); |
18dbd950 | 10892 | emit_all_insn_group_barriers (NULL); |
5f13cfc6 | 10893 | insn = get_insns (); |
5f13cfc6 RH |
10894 | shorten_branches (insn); |
10895 | final_start_function (insn, file, 1); | |
c9d691e9 | 10896 | final (insn, file, 1); |
5f13cfc6 | 10897 | final_end_function (); |
599aedd9 RH |
10898 | |
10899 | reload_completed = 0; | |
fe3ad572 | 10900 | epilogue_completed = 0; |
483ab821 MM |
10901 | } |
10902 | ||
351a758b KH |
10903 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
10904 | ||
10905 | static rtx | |
57782ad8 | 10906 | ia64_struct_value_rtx (tree fntype, |
351a758b KH |
10907 | int incoming ATTRIBUTE_UNUSED) |
10908 | { | |
f2972bf8 DR |
10909 | if (TARGET_ABI_OPEN_VMS || |
10910 | (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))) | |
57782ad8 | 10911 | return NULL_RTX; |
351a758b KH |
10912 | return gen_rtx_REG (Pmode, GR_REG (8)); |
10913 | } | |
10914 | ||
88ed5ef5 SE |
10915 | static bool |
10916 | ia64_scalar_mode_supported_p (enum machine_mode mode) | |
10917 | { | |
10918 | switch (mode) | |
10919 | { | |
10920 | case QImode: | |
10921 | case HImode: | |
10922 | case SImode: | |
10923 | case DImode: | |
10924 | case TImode: | |
10925 | return true; | |
10926 | ||
10927 | case SFmode: | |
10928 | case DFmode: | |
10929 | case XFmode: | |
4de67c26 | 10930 | case RFmode: |
88ed5ef5 SE |
10931 | return true; |
10932 | ||
10933 | case TFmode: | |
c252db20 | 10934 | return true; |
88ed5ef5 SE |
10935 | |
10936 | default: | |
10937 | return false; | |
10938 | } | |
10939 | } | |
10940 | ||
f61134e8 RH |
10941 | static bool |
10942 | ia64_vector_mode_supported_p (enum machine_mode mode) | |
10943 | { | |
10944 | switch (mode) | |
10945 | { | |
10946 | case V8QImode: | |
10947 | case V4HImode: | |
10948 | case V2SImode: | |
10949 | return true; | |
10950 | ||
10951 | case V2SFmode: | |
10952 | return true; | |
10953 | ||
10954 | default: | |
10955 | return false; | |
10956 | } | |
10957 | } | |
10958 | ||
694a2f6e EB |
10959 | /* Implement the FUNCTION_PROFILER macro. */ |
10960 | ||
2b4f149b RH |
10961 | void |
10962 | ia64_output_function_profiler (FILE *file, int labelno) | |
10963 | { | |
694a2f6e EB |
10964 | bool indirect_call; |
10965 | ||
10966 | /* If the function needs a static chain and the static chain | |
10967 | register is r15, we use an indirect call so as to bypass | |
10968 | the PLT stub in case the executable is dynamically linked, | |
10969 | because the stub clobbers r15 as per 5.3.6 of the psABI. | |
10970 | We don't need to do that in non canonical PIC mode. */ | |
10971 | ||
10972 | if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC) | |
10973 | { | |
10974 | gcc_assert (STATIC_CHAIN_REGNUM == 15); | |
10975 | indirect_call = true; | |
10976 | } | |
10977 | else | |
10978 | indirect_call = false; | |
10979 | ||
2b4f149b RH |
10980 | if (TARGET_GNU_AS) |
10981 | fputs ("\t.prologue 4, r40\n", file); | |
10982 | else | |
10983 | fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file); | |
10984 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file); | |
bd8633a3 RH |
10985 | |
10986 | if (NO_PROFILE_COUNTERS) | |
694a2f6e | 10987 | fputs ("\tmov out3 = r0\n", file); |
bd8633a3 RH |
10988 | else |
10989 | { | |
10990 | char buf[20]; | |
10991 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
10992 | ||
10993 | if (TARGET_AUTO_PIC) | |
10994 | fputs ("\tmovl out3 = @gprel(", file); | |
10995 | else | |
10996 | fputs ("\taddl out3 = @ltoff(", file); | |
10997 | assemble_name (file, buf); | |
10998 | if (TARGET_AUTO_PIC) | |
694a2f6e | 10999 | fputs (")\n", file); |
bd8633a3 | 11000 | else |
694a2f6e | 11001 | fputs ("), r1\n", file); |
bd8633a3 RH |
11002 | } |
11003 | ||
694a2f6e EB |
11004 | if (indirect_call) |
11005 | fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file); | |
11006 | fputs ("\t;;\n", file); | |
11007 | ||
2b4f149b | 11008 | fputs ("\t.save rp, r42\n", file); |
bd8633a3 | 11009 | fputs ("\tmov out2 = b0\n", file); |
694a2f6e EB |
11010 | if (indirect_call) |
11011 | fputs ("\tld8 r14 = [r14]\n\t;;\n", file); | |
2b4f149b | 11012 | fputs ("\t.body\n", file); |
2b4f149b | 11013 | fputs ("\tmov out1 = r1\n", file); |
694a2f6e EB |
11014 | if (indirect_call) |
11015 | { | |
11016 | fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file); | |
11017 | fputs ("\tmov b6 = r16\n", file); | |
11018 | fputs ("\tld8 r1 = [r14]\n", file); | |
11019 | fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file); | |
11020 | } | |
11021 | else | |
11022 | fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file); | |
2b4f149b RH |
11023 | } |
11024 | ||
d26afa4f SE |
11025 | static GTY(()) rtx mcount_func_rtx; |
11026 | static rtx | |
11027 | gen_mcount_func_rtx (void) | |
11028 | { | |
11029 | if (!mcount_func_rtx) | |
11030 | mcount_func_rtx = init_one_libfunc ("_mcount"); | |
11031 | return mcount_func_rtx; | |
11032 | } | |
11033 | ||
11034 | void | |
11035 | ia64_profile_hook (int labelno) | |
11036 | { | |
11037 | rtx label, ip; | |
11038 | ||
11039 | if (NO_PROFILE_COUNTERS) | |
11040 | label = const0_rtx; | |
11041 | else | |
11042 | { | |
11043 | char buf[30]; | |
11044 | const char *label_name; | |
11045 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
55504c7c | 11046 | label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf)); |
d26afa4f SE |
11047 | label = gen_rtx_SYMBOL_REF (Pmode, label_name); |
11048 | SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL; | |
11049 | } | |
11050 | ip = gen_reg_rtx (Pmode); | |
11051 | emit_insn (gen_ip_value (ip)); | |
11052 | emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL, | |
11053 | VOIDmode, 3, | |
11054 | gen_rtx_REG (Pmode, BR_REG (0)), Pmode, | |
11055 | ip, Pmode, | |
11056 | label, Pmode); | |
11057 | } | |
11058 | ||
cac24f06 JM |
11059 | /* Return the mangling of TYPE if it is an extended fundamental type. */ |
11060 | ||
11061 | static const char * | |
3101faab | 11062 | ia64_mangle_type (const_tree type) |
cac24f06 | 11063 | { |
608063c3 JB |
11064 | type = TYPE_MAIN_VARIANT (type); |
11065 | ||
11066 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
11067 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
11068 | return NULL; | |
11069 | ||
cac24f06 JM |
11070 | /* On HP-UX, "long double" is mangled as "e" so __float128 is |
11071 | mangled as "e". */ | |
11072 | if (!TARGET_HPUX && TYPE_MODE (type) == TFmode) | |
11073 | return "g"; | |
11074 | /* On HP-UX, "e" is not available as a mangling of __float80 so use | |
11075 | an extended mangling. Elsewhere, "e" is available since long | |
11076 | double is 80 bits. */ | |
11077 | if (TYPE_MODE (type) == XFmode) | |
11078 | return TARGET_HPUX ? "u9__float80" : "e"; | |
4de67c26 JM |
11079 | if (TYPE_MODE (type) == RFmode) |
11080 | return "u7__fpreg"; | |
11081 | return NULL; | |
11082 | } | |
11083 | ||
11084 | /* Return the diagnostic message string if conversion from FROMTYPE to | |
11085 | TOTYPE is not allowed, NULL otherwise. */ | |
11086 | static const char * | |
3101faab | 11087 | ia64_invalid_conversion (const_tree fromtype, const_tree totype) |
4de67c26 JM |
11088 | { |
11089 | /* Reject nontrivial conversion to or from __fpreg. */ | |
11090 | if (TYPE_MODE (fromtype) == RFmode | |
11091 | && TYPE_MODE (totype) != RFmode | |
11092 | && TYPE_MODE (totype) != VOIDmode) | |
11093 | return N_("invalid conversion from %<__fpreg%>"); | |
11094 | if (TYPE_MODE (totype) == RFmode | |
11095 | && TYPE_MODE (fromtype) != RFmode) | |
11096 | return N_("invalid conversion to %<__fpreg%>"); | |
11097 | return NULL; | |
11098 | } | |
11099 | ||
11100 | /* Return the diagnostic message string if the unary operation OP is | |
11101 | not permitted on TYPE, NULL otherwise. */ | |
11102 | static const char * | |
3101faab | 11103 | ia64_invalid_unary_op (int op, const_tree type) |
4de67c26 JM |
11104 | { |
11105 | /* Reject operations on __fpreg other than unary + or &. */ | |
11106 | if (TYPE_MODE (type) == RFmode | |
11107 | && op != CONVERT_EXPR | |
11108 | && op != ADDR_EXPR) | |
11109 | return N_("invalid operation on %<__fpreg%>"); | |
11110 | return NULL; | |
11111 | } | |
11112 | ||
11113 | /* Return the diagnostic message string if the binary operation OP is | |
11114 | not permitted on TYPE1 and TYPE2, NULL otherwise. */ | |
11115 | static const char * | |
3101faab | 11116 | ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2) |
4de67c26 JM |
11117 | { |
11118 | /* Reject operations on __fpreg. */ | |
11119 | if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode) | |
11120 | return N_("invalid operation on %<__fpreg%>"); | |
cac24f06 JM |
11121 | return NULL; |
11122 | } | |
11123 | ||
812b587e SE |
11124 | /* HP-UX version_id attribute. |
11125 | For object foo, if the version_id is set to 1234 put out an alias | |
11126 | of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything | |
11127 | other than an alias statement because it is an illegal symbol name. */ | |
11128 | ||
11129 | static tree | |
11130 | ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED, | |
11131 | tree name ATTRIBUTE_UNUSED, | |
11132 | tree args, | |
11133 | int flags ATTRIBUTE_UNUSED, | |
11134 | bool *no_add_attrs) | |
11135 | { | |
11136 | tree arg = TREE_VALUE (args); | |
11137 | ||
11138 | if (TREE_CODE (arg) != STRING_CST) | |
11139 | { | |
11140 | error("version attribute is not a string"); | |
11141 | *no_add_attrs = true; | |
11142 | return NULL_TREE; | |
11143 | } | |
11144 | return NULL_TREE; | |
11145 | } | |
11146 | ||
a31fa2e0 SE |
11147 | /* Target hook for c_mode_for_suffix. */ |
11148 | ||
11149 | static enum machine_mode | |
11150 | ia64_c_mode_for_suffix (char suffix) | |
11151 | { | |
11152 | if (suffix == 'q') | |
11153 | return TFmode; | |
11154 | if (suffix == 'w') | |
11155 | return XFmode; | |
11156 | ||
11157 | return VOIDmode; | |
11158 | } | |
11159 | ||
f3a83111 SE |
11160 | static GTY(()) rtx ia64_dconst_0_5_rtx; |
11161 | ||
11162 | rtx | |
11163 | ia64_dconst_0_5 (void) | |
11164 | { | |
11165 | if (! ia64_dconst_0_5_rtx) | |
11166 | { | |
11167 | REAL_VALUE_TYPE rv; | |
11168 | real_from_string (&rv, "0.5"); | |
11169 | ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode); | |
11170 | } | |
11171 | return ia64_dconst_0_5_rtx; | |
11172 | } | |
11173 | ||
11174 | static GTY(()) rtx ia64_dconst_0_375_rtx; | |
11175 | ||
11176 | rtx | |
11177 | ia64_dconst_0_375 (void) | |
11178 | { | |
11179 | if (! ia64_dconst_0_375_rtx) | |
11180 | { | |
11181 | REAL_VALUE_TYPE rv; | |
11182 | real_from_string (&rv, "0.375"); | |
11183 | ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode); | |
11184 | } | |
11185 | return ia64_dconst_0_375_rtx; | |
11186 | } | |
11187 | ||
ffa88471 SE |
11188 | static enum machine_mode |
11189 | ia64_get_reg_raw_mode (int regno) | |
11190 | { | |
11191 | if (FR_REGNO_P (regno)) | |
11192 | return XFmode; | |
11193 | return default_get_reg_raw_mode(regno); | |
11194 | } | |
f3a83111 | 11195 | |
f16d3f39 JH |
11196 | /* Always default to .text section until HP-UX linker is fixed. */ |
11197 | ||
11198 | ATTRIBUTE_UNUSED static section * | |
11199 | ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED, | |
11200 | enum node_frequency freq ATTRIBUTE_UNUSED, | |
11201 | bool startup ATTRIBUTE_UNUSED, | |
11202 | bool exit ATTRIBUTE_UNUSED) | |
11203 | { | |
11204 | return NULL; | |
11205 | } | |
e6431744 RH |
11206 | \f |
11207 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
11208 | return true if that's a valid instruction in the active ISA. */ | |
11209 | ||
11210 | static bool | |
11211 | expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt) | |
11212 | { | |
11213 | rtx rperm[MAX_VECT_LEN], x; | |
11214 | unsigned i; | |
11215 | ||
11216 | for (i = 0; i < nelt; ++i) | |
11217 | rperm[i] = GEN_INT (perm[i]); | |
11218 | ||
11219 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
11220 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
11221 | x = gen_rtx_SET (VOIDmode, target, x); | |
11222 | ||
11223 | x = emit_insn (x); | |
11224 | if (recog_memoized (x) < 0) | |
11225 | { | |
11226 | remove_insn (x); | |
11227 | return false; | |
11228 | } | |
11229 | return true; | |
11230 | } | |
11231 | ||
11232 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
11233 | ||
11234 | static bool | |
11235 | expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
11236 | const unsigned char *perm, unsigned nelt) | |
11237 | { | |
11238 | enum machine_mode v2mode; | |
11239 | rtx x; | |
11240 | ||
11241 | v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); | |
11242 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); | |
11243 | return expand_vselect (target, x, perm, nelt); | |
11244 | } | |
11245 | ||
11246 | /* Try to expand a no-op permutation. */ | |
11247 | ||
11248 | static bool | |
11249 | expand_vec_perm_identity (struct expand_vec_perm_d *d) | |
11250 | { | |
11251 | unsigned i, nelt = d->nelt; | |
11252 | ||
11253 | for (i = 0; i < nelt; ++i) | |
11254 | if (d->perm[i] != i) | |
11255 | return false; | |
11256 | ||
11257 | if (!d->testing_p) | |
11258 | emit_move_insn (d->target, d->op0); | |
11259 | ||
11260 | return true; | |
11261 | } | |
11262 | ||
11263 | /* Try to expand D via a shrp instruction. */ | |
11264 | ||
11265 | static bool | |
11266 | expand_vec_perm_shrp (struct expand_vec_perm_d *d) | |
11267 | { | |
11268 | unsigned i, nelt = d->nelt, shift, mask; | |
2d130b31 | 11269 | rtx tmp, hi, lo; |
e6431744 RH |
11270 | |
11271 | /* ??? Don't force V2SFmode into the integer registers. */ | |
11272 | if (d->vmode == V2SFmode) | |
11273 | return false; | |
11274 | ||
11275 | mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1); | |
11276 | ||
11277 | shift = d->perm[0]; | |
2d130b31 UB |
11278 | if (BYTES_BIG_ENDIAN && shift > nelt) |
11279 | return false; | |
11280 | ||
e6431744 RH |
11281 | for (i = 1; i < nelt; ++i) |
11282 | if (d->perm[i] != ((shift + i) & mask)) | |
11283 | return false; | |
11284 | ||
11285 | if (d->testing_p) | |
11286 | return true; | |
11287 | ||
2d130b31 UB |
11288 | hi = shift < nelt ? d->op1 : d->op0; |
11289 | lo = shift < nelt ? d->op0 : d->op1; | |
11290 | ||
11291 | shift %= nelt; | |
11292 | ||
e6431744 RH |
11293 | shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT; |
11294 | ||
11295 | /* We've eliminated the shift 0 case via expand_vec_perm_identity. */ | |
11296 | gcc_assert (IN_RANGE (shift, 1, 63)); | |
11297 | ||
11298 | /* Recall that big-endian elements are numbered starting at the top of | |
11299 | the register. Ideally we'd have a shift-left-pair. But since we | |
11300 | don't, convert to a shift the other direction. */ | |
11301 | if (BYTES_BIG_ENDIAN) | |
11302 | shift = 64 - shift; | |
11303 | ||
11304 | tmp = gen_reg_rtx (DImode); | |
2d130b31 UB |
11305 | hi = gen_lowpart (DImode, hi); |
11306 | lo = gen_lowpart (DImode, lo); | |
11307 | emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift))); | |
e6431744 RH |
11308 | |
11309 | emit_move_insn (d->target, gen_lowpart (d->vmode, tmp)); | |
11310 | return true; | |
11311 | } | |
11312 | ||
11313 | /* Try to instantiate D in a single instruction. */ | |
11314 | ||
11315 | static bool | |
11316 | expand_vec_perm_1 (struct expand_vec_perm_d *d) | |
11317 | { | |
11318 | unsigned i, nelt = d->nelt; | |
11319 | unsigned char perm2[MAX_VECT_LEN]; | |
11320 | ||
11321 | /* Try single-operand selections. */ | |
11322 | if (d->one_operand_p) | |
11323 | { | |
11324 | if (expand_vec_perm_identity (d)) | |
11325 | return true; | |
11326 | if (expand_vselect (d->target, d->op0, d->perm, nelt)) | |
11327 | return true; | |
11328 | } | |
11329 | ||
11330 | /* Try two operand selections. */ | |
11331 | if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt)) | |
11332 | return true; | |
11333 | ||
11334 | /* Recognize interleave style patterns with reversed operands. */ | |
11335 | if (!d->one_operand_p) | |
11336 | { | |
11337 | for (i = 0; i < nelt; ++i) | |
11338 | { | |
11339 | unsigned e = d->perm[i]; | |
11340 | if (e >= nelt) | |
11341 | e -= nelt; | |
11342 | else | |
11343 | e += nelt; | |
11344 | perm2[i] = e; | |
11345 | } | |
11346 | ||
11347 | if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
11348 | return true; | |
11349 | } | |
11350 | ||
11351 | if (expand_vec_perm_shrp (d)) | |
11352 | return true; | |
11353 | ||
11354 | /* ??? Look for deposit-like permutations where most of the result | |
11355 | comes from one vector unchanged and the rest comes from a | |
11356 | sequential hunk of the other vector. */ | |
11357 | ||
11358 | return false; | |
11359 | } | |
11360 | ||
11361 | /* Pattern match broadcast permutations. */ | |
11362 | ||
11363 | static bool | |
11364 | expand_vec_perm_broadcast (struct expand_vec_perm_d *d) | |
11365 | { | |
11366 | unsigned i, elt, nelt = d->nelt; | |
11367 | unsigned char perm2[2]; | |
11368 | rtx temp; | |
11369 | bool ok; | |
11370 | ||
11371 | if (!d->one_operand_p) | |
11372 | return false; | |
11373 | ||
11374 | elt = d->perm[0]; | |
11375 | for (i = 1; i < nelt; ++i) | |
11376 | if (d->perm[i] != elt) | |
11377 | return false; | |
11378 | ||
11379 | switch (d->vmode) | |
11380 | { | |
11381 | case V2SImode: | |
11382 | case V2SFmode: | |
11383 | /* Implementable by interleave. */ | |
11384 | perm2[0] = elt; | |
11385 | perm2[1] = elt + 2; | |
11386 | ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2); | |
11387 | gcc_assert (ok); | |
11388 | break; | |
11389 | ||
11390 | case V8QImode: | |
11391 | /* Implementable by extract + broadcast. */ | |
11392 | if (BYTES_BIG_ENDIAN) | |
11393 | elt = 7 - elt; | |
11394 | elt *= BITS_PER_UNIT; | |
11395 | temp = gen_reg_rtx (DImode); | |
11396 | emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0), | |
96fda42c | 11397 | GEN_INT (8), GEN_INT (elt))); |
e6431744 RH |
11398 | emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp))); |
11399 | break; | |
11400 | ||
11401 | case V4HImode: | |
11402 | /* Should have been matched directly by vec_select. */ | |
11403 | default: | |
11404 | gcc_unreachable (); | |
11405 | } | |
11406 | ||
11407 | return true; | |
11408 | } | |
11409 | ||
11410 | /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a | |
11411 | two vector permutation into a single vector permutation by using | |
11412 | an interleave operation to merge the vectors. */ | |
11413 | ||
11414 | static bool | |
11415 | expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d) | |
11416 | { | |
11417 | struct expand_vec_perm_d dremap, dfinal; | |
11418 | unsigned char remap[2 * MAX_VECT_LEN]; | |
11419 | unsigned contents, i, nelt, nelt2; | |
11420 | unsigned h0, h1, h2, h3; | |
11421 | rtx seq; | |
11422 | bool ok; | |
11423 | ||
11424 | if (d->one_operand_p) | |
11425 | return false; | |
11426 | ||
11427 | nelt = d->nelt; | |
11428 | nelt2 = nelt / 2; | |
11429 | ||
11430 | /* Examine from whence the elements come. */ | |
11431 | contents = 0; | |
11432 | for (i = 0; i < nelt; ++i) | |
11433 | contents |= 1u << d->perm[i]; | |
11434 | ||
11435 | memset (remap, 0xff, sizeof (remap)); | |
11436 | dremap = *d; | |
11437 | ||
11438 | h0 = (1u << nelt2) - 1; | |
11439 | h1 = h0 << nelt2; | |
11440 | h2 = h0 << nelt; | |
11441 | h3 = h0 << (nelt + nelt2); | |
11442 | ||
11443 | if ((contents & (h0 | h2)) == contents) /* punpck even halves */ | |
11444 | { | |
11445 | for (i = 0; i < nelt; ++i) | |
11446 | { | |
11447 | unsigned which = i / 2 + (i & 1 ? nelt : 0); | |
11448 | remap[which] = i; | |
11449 | dremap.perm[i] = which; | |
11450 | } | |
11451 | } | |
11452 | else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */ | |
11453 | { | |
11454 | for (i = 0; i < nelt; ++i) | |
11455 | { | |
11456 | unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0); | |
11457 | remap[which] = i; | |
11458 | dremap.perm[i] = which; | |
11459 | } | |
11460 | } | |
11461 | else if ((contents & 0x5555) == contents) /* mix even elements */ | |
11462 | { | |
11463 | for (i = 0; i < nelt; ++i) | |
11464 | { | |
11465 | unsigned which = (i & ~1) + (i & 1 ? nelt : 0); | |
11466 | remap[which] = i; | |
11467 | dremap.perm[i] = which; | |
11468 | } | |
11469 | } | |
11470 | else if ((contents & 0xaaaa) == contents) /* mix odd elements */ | |
11471 | { | |
11472 | for (i = 0; i < nelt; ++i) | |
11473 | { | |
11474 | unsigned which = (i | 1) + (i & 1 ? nelt : 0); | |
11475 | remap[which] = i; | |
11476 | dremap.perm[i] = which; | |
11477 | } | |
11478 | } | |
11479 | else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */ | |
11480 | { | |
11481 | unsigned shift = ctz_hwi (contents); | |
11482 | for (i = 0; i < nelt; ++i) | |
11483 | { | |
11484 | unsigned which = (i + shift) & (2 * nelt - 1); | |
11485 | remap[which] = i; | |
11486 | dremap.perm[i] = which; | |
11487 | } | |
11488 | } | |
11489 | else | |
11490 | return false; | |
11491 | ||
11492 | /* Use the remapping array set up above to move the elements from their | |
11493 | swizzled locations into their final destinations. */ | |
11494 | dfinal = *d; | |
11495 | for (i = 0; i < nelt; ++i) | |
11496 | { | |
11497 | unsigned e = remap[d->perm[i]]; | |
11498 | gcc_assert (e < nelt); | |
11499 | dfinal.perm[i] = e; | |
11500 | } | |
11501 | dfinal.op0 = gen_reg_rtx (dfinal.vmode); | |
11502 | dfinal.op1 = dfinal.op0; | |
11503 | dfinal.one_operand_p = true; | |
11504 | dremap.target = dfinal.op0; | |
11505 | ||
11506 | /* Test if the final remap can be done with a single insn. For V4HImode | |
11507 | this *will* succeed. For V8QImode or V2SImode it may not. */ | |
11508 | start_sequence (); | |
11509 | ok = expand_vec_perm_1 (&dfinal); | |
11510 | seq = get_insns (); | |
11511 | end_sequence (); | |
11512 | if (!ok) | |
11513 | return false; | |
11514 | if (d->testing_p) | |
11515 | return true; | |
11516 | ||
11517 | ok = expand_vec_perm_1 (&dremap); | |
11518 | gcc_assert (ok); | |
11519 | ||
11520 | emit_insn (seq); | |
11521 | return true; | |
11522 | } | |
11523 | ||
11524 | /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode | |
11525 | constant permutation via two mux2 and a merge. */ | |
11526 | ||
11527 | static bool | |
11528 | expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d) | |
11529 | { | |
11530 | unsigned char perm2[4]; | |
11531 | rtx rmask[4]; | |
11532 | unsigned i; | |
11533 | rtx t0, t1, mask, x; | |
11534 | bool ok; | |
11535 | ||
11536 | if (d->vmode != V4HImode || d->one_operand_p) | |
11537 | return false; | |
11538 | if (d->testing_p) | |
11539 | return true; | |
11540 | ||
11541 | for (i = 0; i < 4; ++i) | |
11542 | { | |
11543 | perm2[i] = d->perm[i] & 3; | |
11544 | rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx); | |
11545 | } | |
11546 | mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask)); | |
11547 | mask = force_reg (V4HImode, mask); | |
11548 | ||
11549 | t0 = gen_reg_rtx (V4HImode); | |
11550 | t1 = gen_reg_rtx (V4HImode); | |
11551 | ||
11552 | ok = expand_vselect (t0, d->op0, perm2, 4); | |
11553 | gcc_assert (ok); | |
11554 | ok = expand_vselect (t1, d->op1, perm2, 4); | |
11555 | gcc_assert (ok); | |
11556 | ||
11557 | x = gen_rtx_AND (V4HImode, mask, t0); | |
11558 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
11559 | ||
11560 | x = gen_rtx_NOT (V4HImode, mask); | |
11561 | x = gen_rtx_AND (V4HImode, x, t1); | |
11562 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
11563 | ||
11564 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
11565 | emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); | |
11566 | ||
11567 | return true; | |
11568 | } | |
11569 | ||
11570 | /* The guts of ia64_expand_vec_perm_const, also used by the ok hook. | |
11571 | With all of the interface bits taken care of, perform the expansion | |
11572 | in D and return true on success. */ | |
11573 | ||
11574 | static bool | |
11575 | ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
11576 | { | |
11577 | if (expand_vec_perm_1 (d)) | |
11578 | return true; | |
11579 | if (expand_vec_perm_broadcast (d)) | |
11580 | return true; | |
11581 | if (expand_vec_perm_interleave_2 (d)) | |
11582 | return true; | |
11583 | if (expand_vec_perm_v4hi_5 (d)) | |
11584 | return true; | |
11585 | return false; | |
11586 | } | |
11587 | ||
11588 | bool | |
11589 | ia64_expand_vec_perm_const (rtx operands[4]) | |
11590 | { | |
11591 | struct expand_vec_perm_d d; | |
11592 | unsigned char perm[MAX_VECT_LEN]; | |
11593 | int i, nelt, which; | |
11594 | rtx sel; | |
11595 | ||
11596 | d.target = operands[0]; | |
11597 | d.op0 = operands[1]; | |
11598 | d.op1 = operands[2]; | |
11599 | sel = operands[3]; | |
11600 | ||
11601 | d.vmode = GET_MODE (d.target); | |
11602 | gcc_assert (VECTOR_MODE_P (d.vmode)); | |
11603 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11604 | d.testing_p = false; | |
11605 | ||
11606 | gcc_assert (GET_CODE (sel) == CONST_VECTOR); | |
11607 | gcc_assert (XVECLEN (sel, 0) == nelt); | |
11608 | gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); | |
11609 | ||
11610 | for (i = which = 0; i < nelt; ++i) | |
11611 | { | |
11612 | rtx e = XVECEXP (sel, 0, i); | |
11613 | int ei = INTVAL (e) & (2 * nelt - 1); | |
11614 | ||
11615 | which |= (ei < nelt ? 1 : 2); | |
11616 | d.perm[i] = ei; | |
11617 | perm[i] = ei; | |
11618 | } | |
11619 | ||
11620 | switch (which) | |
11621 | { | |
11622 | default: | |
11623 | gcc_unreachable(); | |
11624 | ||
11625 | case 3: | |
11626 | if (!rtx_equal_p (d.op0, d.op1)) | |
11627 | { | |
11628 | d.one_operand_p = false; | |
11629 | break; | |
11630 | } | |
11631 | ||
11632 | /* The elements of PERM do not suggest that only the first operand | |
11633 | is used, but both operands are identical. Allow easier matching | |
11634 | of the permutation by folding the permutation into the single | |
11635 | input vector. */ | |
11636 | for (i = 0; i < nelt; ++i) | |
11637 | if (d.perm[i] >= nelt) | |
11638 | d.perm[i] -= nelt; | |
11639 | /* FALLTHRU */ | |
11640 | ||
11641 | case 1: | |
11642 | d.op1 = d.op0; | |
11643 | d.one_operand_p = true; | |
11644 | break; | |
11645 | ||
11646 | case 2: | |
11647 | for (i = 0; i < nelt; ++i) | |
11648 | d.perm[i] -= nelt; | |
11649 | d.op0 = d.op1; | |
11650 | d.one_operand_p = true; | |
11651 | break; | |
11652 | } | |
11653 | ||
11654 | if (ia64_expand_vec_perm_const_1 (&d)) | |
11655 | return true; | |
11656 | ||
11657 | /* If the mask says both arguments are needed, but they are the same, | |
11658 | the above tried to expand with one_operand_p true. If that didn't | |
11659 | work, retry with one_operand_p false, as that's what we used in _ok. */ | |
11660 | if (which == 3 && d.one_operand_p) | |
11661 | { | |
11662 | memcpy (d.perm, perm, sizeof (perm)); | |
11663 | d.one_operand_p = false; | |
11664 | return ia64_expand_vec_perm_const_1 (&d); | |
11665 | } | |
11666 | ||
11667 | return false; | |
11668 | } | |
11669 | ||
11670 | /* Implement targetm.vectorize.vec_perm_const_ok. */ | |
11671 | ||
11672 | static bool | |
11673 | ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode, | |
11674 | const unsigned char *sel) | |
11675 | { | |
11676 | struct expand_vec_perm_d d; | |
11677 | unsigned int i, nelt, which; | |
11678 | bool ret; | |
11679 | ||
11680 | d.vmode = vmode; | |
11681 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11682 | d.testing_p = true; | |
11683 | ||
11684 | /* Extract the values from the vector CST into the permutation | |
11685 | array in D. */ | |
11686 | memcpy (d.perm, sel, nelt); | |
11687 | for (i = which = 0; i < nelt; ++i) | |
11688 | { | |
11689 | unsigned char e = d.perm[i]; | |
11690 | gcc_assert (e < 2 * nelt); | |
11691 | which |= (e < nelt ? 1 : 2); | |
11692 | } | |
11693 | ||
11694 | /* For all elements from second vector, fold the elements to first. */ | |
11695 | if (which == 2) | |
11696 | for (i = 0; i < nelt; ++i) | |
11697 | d.perm[i] -= nelt; | |
11698 | ||
11699 | /* Check whether the mask can be applied to the vector type. */ | |
11700 | d.one_operand_p = (which != 3); | |
11701 | ||
11702 | /* Otherwise we have to go through the motions and see if we can | |
11703 | figure out how to generate the requested permutation. */ | |
11704 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11705 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
11706 | if (!d.one_operand_p) | |
11707 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
11708 | ||
11709 | start_sequence (); | |
11710 | ret = ia64_expand_vec_perm_const_1 (&d); | |
11711 | end_sequence (); | |
11712 | ||
11713 | return ret; | |
11714 | } | |
11715 | ||
11716 | void | |
11717 | ia64_expand_vec_setv2sf (rtx operands[3]) | |
11718 | { | |
11719 | struct expand_vec_perm_d d; | |
11720 | unsigned int which; | |
11721 | bool ok; | |
11722 | ||
11723 | d.target = operands[0]; | |
11724 | d.op0 = operands[0]; | |
11725 | d.op1 = gen_reg_rtx (V2SFmode); | |
11726 | d.vmode = V2SFmode; | |
11727 | d.nelt = 2; | |
11728 | d.one_operand_p = false; | |
11729 | d.testing_p = false; | |
11730 | ||
11731 | which = INTVAL (operands[2]); | |
11732 | gcc_assert (which <= 1); | |
11733 | d.perm[0] = 1 - which; | |
11734 | d.perm[1] = which + 2; | |
11735 | ||
11736 | emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode))); | |
11737 | ||
11738 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11739 | gcc_assert (ok); | |
11740 | } | |
11741 | ||
11742 | void | |
11743 | ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd) | |
11744 | { | |
11745 | struct expand_vec_perm_d d; | |
11746 | enum machine_mode vmode = GET_MODE (target); | |
11747 | unsigned int i, nelt = GET_MODE_NUNITS (vmode); | |
11748 | bool ok; | |
11749 | ||
11750 | d.target = target; | |
11751 | d.op0 = op0; | |
11752 | d.op1 = op1; | |
11753 | d.vmode = vmode; | |
11754 | d.nelt = nelt; | |
11755 | d.one_operand_p = false; | |
11756 | d.testing_p = false; | |
11757 | ||
11758 | for (i = 0; i < nelt; ++i) | |
11759 | d.perm[i] = i * 2 + odd; | |
11760 | ||
11761 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11762 | gcc_assert (ok); | |
11763 | } | |
f16d3f39 | 11764 | |
e2500fed | 11765 | #include "gt-ia64.h" |