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c65ebc55 | 1 | /* Definitions of target machine for GNU compiler. |
23a5b65a | 2 | Copyright (C) 1999-2014 Free Software Foundation, Inc. |
c65ebc55 | 3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
9c808aad | 4 | David Mosberger <davidm@hpl.hp.com>. |
c65ebc55 | 5 | |
3bed2930 | 6 | This file is part of GCC. |
c65ebc55 | 7 | |
3bed2930 | 8 | GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
11 | any later version. |
12 | ||
3bed2930 | 13 | GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
c65ebc55 | 21 | |
c65ebc55 | 22 | #include "config.h" |
ed9ccd8a | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
c65ebc55 JW |
26 | #include "rtl.h" |
27 | #include "tree.h" | |
d8a2d370 DN |
28 | #include "stringpool.h" |
29 | #include "stor-layout.h" | |
30 | #include "calls.h" | |
31 | #include "varasm.h" | |
c65ebc55 JW |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
c65ebc55 JW |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
c65ebc55 JW |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
39 | #include "recog.h" | |
40 | #include "expr.h" | |
e78d8e51 | 41 | #include "optabs.h" |
c65ebc55 JW |
42 | #include "except.h" |
43 | #include "function.h" | |
44 | #include "ggc.h" | |
45 | #include "basic-block.h" | |
f2972bf8 | 46 | #include "libfuncs.h" |
718f9c0f | 47 | #include "diagnostic-core.h" |
2130b7fb | 48 | #include "sched-int.h" |
eced69b5 | 49 | #include "timevar.h" |
672a6f42 NB |
50 | #include "target.h" |
51 | #include "target-def.h" | |
7b84aac0 | 52 | #include "common/common-target.h" |
98d2b17e | 53 | #include "tm_p.h" |
3a4f280b | 54 | #include "hash-table.h" |
08744705 | 55 | #include "langhooks.h" |
2fb9a547 AM |
56 | #include "pointer-set.h" |
57 | #include "vec.h" | |
58 | #include "basic-block.h" | |
59 | #include "tree-ssa-alias.h" | |
60 | #include "internal-fn.h" | |
61 | #include "gimple-fold.h" | |
62 | #include "tree-eh.h" | |
63 | #include "gimple-expr.h" | |
64 | #include "is-a.h" | |
18f429e2 | 65 | #include "gimple.h" |
45b0be94 | 66 | #include "gimplify.h" |
4de67c26 | 67 | #include "intl.h" |
6fb5fa3c | 68 | #include "df.h" |
658f32fd | 69 | #include "debug.h" |
bb83aa4b | 70 | #include "params.h" |
6fb5fa3c | 71 | #include "dbgcnt.h" |
13f70342 | 72 | #include "tm-constrs.h" |
388092d5 | 73 | #include "sel-sched.h" |
69e18c09 | 74 | #include "reload.h" |
96e45421 | 75 | #include "opts.h" |
7ee2468b | 76 | #include "dumpfile.h" |
9b2b7279 | 77 | #include "builtins.h" |
c65ebc55 JW |
78 | |
79 | /* This is used for communication between ASM_OUTPUT_LABEL and | |
80 | ASM_OUTPUT_LABELREF. */ | |
81 | int ia64_asm_output_label = 0; | |
82 | ||
c65ebc55 | 83 | /* Register names for ia64_expand_prologue. */ |
3b572406 | 84 | static const char * const ia64_reg_numbers[96] = |
c65ebc55 JW |
85 | { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", |
86 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
87 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
88 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
89 | "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", | |
90 | "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", | |
91 | "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", | |
92 | "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", | |
93 | "r96", "r97", "r98", "r99", "r100","r101","r102","r103", | |
94 | "r104","r105","r106","r107","r108","r109","r110","r111", | |
95 | "r112","r113","r114","r115","r116","r117","r118","r119", | |
96 | "r120","r121","r122","r123","r124","r125","r126","r127"}; | |
97 | ||
98 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 99 | static const char * const ia64_input_reg_names[8] = |
c65ebc55 JW |
100 | { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" }; |
101 | ||
102 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 103 | static const char * const ia64_local_reg_names[80] = |
c65ebc55 JW |
104 | { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", |
105 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", | |
106 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", | |
107 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", | |
108 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", | |
109 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", | |
110 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", | |
111 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", | |
112 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", | |
113 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" }; | |
114 | ||
115 | /* ??? These strings could be shared with REGISTER_NAMES. */ | |
3b572406 | 116 | static const char * const ia64_output_reg_names[8] = |
c65ebc55 JW |
117 | { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" }; |
118 | ||
c65ebc55 JW |
119 | /* Variables which are this size or smaller are put in the sdata/sbss |
120 | sections. */ | |
121 | ||
3b572406 | 122 | unsigned int ia64_section_threshold; |
30028c85 VM |
123 | |
124 | /* The following variable is used by the DFA insn scheduler. The value is | |
125 | TRUE if we do insn bundling instead of insn scheduling. */ | |
126 | int bundling_p = 0; | |
127 | ||
6fb5fa3c DB |
128 | enum ia64_frame_regs |
129 | { | |
130 | reg_fp, | |
131 | reg_save_b0, | |
132 | reg_save_pr, | |
133 | reg_save_ar_pfs, | |
134 | reg_save_ar_unat, | |
135 | reg_save_ar_lc, | |
136 | reg_save_gp, | |
137 | number_of_ia64_frame_regs | |
138 | }; | |
139 | ||
599aedd9 RH |
140 | /* Structure to be filled in by ia64_compute_frame_size with register |
141 | save masks and offsets for the current function. */ | |
142 | ||
143 | struct ia64_frame_info | |
144 | { | |
145 | HOST_WIDE_INT total_size; /* size of the stack frame, not including | |
146 | the caller's scratch area. */ | |
147 | HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */ | |
148 | HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */ | |
149 | HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */ | |
150 | HARD_REG_SET mask; /* mask of saved registers. */ | |
9c808aad | 151 | unsigned int gr_used_mask; /* mask of registers in use as gr spill |
599aedd9 RH |
152 | registers or long-term scratches. */ |
153 | int n_spilled; /* number of spilled registers. */ | |
6fb5fa3c | 154 | int r[number_of_ia64_frame_regs]; /* Frame related registers. */ |
599aedd9 RH |
155 | int n_input_regs; /* number of input registers used. */ |
156 | int n_local_regs; /* number of local registers used. */ | |
157 | int n_output_regs; /* number of output registers used. */ | |
158 | int n_rotate_regs; /* number of rotating registers used. */ | |
159 | ||
160 | char need_regstk; /* true if a .regstk directive needed. */ | |
161 | char initialized; /* true if the data is finalized. */ | |
162 | }; | |
163 | ||
164 | /* Current frame information calculated by ia64_compute_frame_size. */ | |
165 | static struct ia64_frame_info current_frame_info; | |
6fb5fa3c DB |
166 | /* The actual registers that are emitted. */ |
167 | static int emitted_frame_related_regs[number_of_ia64_frame_regs]; | |
3b572406 | 168 | \f |
9c808aad AJ |
169 | static int ia64_first_cycle_multipass_dfa_lookahead (void); |
170 | static void ia64_dependencies_evaluation_hook (rtx, rtx); | |
171 | static void ia64_init_dfa_pre_cycle_insn (void); | |
172 | static rtx ia64_dfa_pre_cycle_insn (void); | |
4960a0cb | 173 | static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx, int); |
9c808aad | 174 | static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *); |
048d0d36 | 175 | static void ia64_h_i_d_extended (void); |
388092d5 AB |
176 | static void * ia64_alloc_sched_context (void); |
177 | static void ia64_init_sched_context (void *, bool); | |
178 | static void ia64_set_sched_context (void *); | |
179 | static void ia64_clear_sched_context (void *); | |
180 | static void ia64_free_sched_context (void *); | |
048d0d36 MK |
181 | static int ia64_mode_to_int (enum machine_mode); |
182 | static void ia64_set_sched_flags (spec_info_t); | |
388092d5 AB |
183 | static ds_t ia64_get_insn_spec_ds (rtx); |
184 | static ds_t ia64_get_insn_checked_ds (rtx); | |
185 | static bool ia64_skip_rtx_p (const_rtx); | |
048d0d36 | 186 | static int ia64_speculate_insn (rtx, ds_t, rtx *); |
8e90de43 | 187 | static bool ia64_needs_block_p (ds_t); |
388092d5 | 188 | static rtx ia64_gen_spec_check (rtx, rtx, ds_t); |
048d0d36 MK |
189 | static int ia64_spec_check_p (rtx); |
190 | static int ia64_spec_check_src_p (rtx); | |
9c808aad AJ |
191 | static rtx gen_tls_get_addr (void); |
192 | static rtx gen_thread_pointer (void); | |
6fb5fa3c | 193 | static int find_gr_spill (enum ia64_frame_regs, int); |
9c808aad AJ |
194 | static int next_scratch_gr_reg (void); |
195 | static void mark_reg_gr_used_mask (rtx, void *); | |
196 | static void ia64_compute_frame_size (HOST_WIDE_INT); | |
197 | static void setup_spill_pointers (int, rtx, HOST_WIDE_INT); | |
198 | static void finish_spill_pointers (void); | |
199 | static rtx spill_restore_mem (rtx, HOST_WIDE_INT); | |
200 | static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx); | |
201 | static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT); | |
202 | static rtx gen_movdi_x (rtx, rtx, rtx); | |
203 | static rtx gen_fr_spill_x (rtx, rtx, rtx); | |
204 | static rtx gen_fr_restore_x (rtx, rtx, rtx); | |
205 | ||
930572b9 | 206 | static void ia64_option_override (void); |
7b5cbb57 | 207 | static bool ia64_can_eliminate (const int, const int); |
586de218 | 208 | static enum machine_mode hfa_element_mode (const_tree, bool); |
d5cc9181 | 209 | static void ia64_setup_incoming_varargs (cumulative_args_t, enum machine_mode, |
351a758b | 210 | tree, int *, int); |
d5cc9181 | 211 | static int ia64_arg_partial_bytes (cumulative_args_t, enum machine_mode, |
78a52f11 | 212 | tree, bool); |
d5cc9181 | 213 | static rtx ia64_function_arg_1 (cumulative_args_t, enum machine_mode, |
ffa88471 | 214 | const_tree, bool, bool); |
d5cc9181 | 215 | static rtx ia64_function_arg (cumulative_args_t, enum machine_mode, |
ffa88471 | 216 | const_tree, bool); |
d5cc9181 | 217 | static rtx ia64_function_incoming_arg (cumulative_args_t, |
ffa88471 | 218 | enum machine_mode, const_tree, bool); |
d5cc9181 | 219 | static void ia64_function_arg_advance (cumulative_args_t, enum machine_mode, |
ffa88471 | 220 | const_tree, bool); |
c2ed6cf8 NF |
221 | static unsigned int ia64_function_arg_boundary (enum machine_mode, |
222 | const_tree); | |
9c808aad | 223 | static bool ia64_function_ok_for_sibcall (tree, tree); |
586de218 | 224 | static bool ia64_return_in_memory (const_tree, const_tree); |
ba90d838 AS |
225 | static rtx ia64_function_value (const_tree, const_tree, bool); |
226 | static rtx ia64_libcall_value (enum machine_mode, const_rtx); | |
227 | static bool ia64_function_value_regno_p (const unsigned int); | |
c21fc181 JR |
228 | static int ia64_register_move_cost (enum machine_mode, reg_class_t, |
229 | reg_class_t); | |
69e18c09 AS |
230 | static int ia64_memory_move_cost (enum machine_mode mode, reg_class_t, |
231 | bool); | |
68f932c4 | 232 | static bool ia64_rtx_costs (rtx, int, int, int, int *, bool); |
215b063c | 233 | static int ia64_unspec_may_trap_p (const_rtx, unsigned); |
9c808aad AJ |
234 | static void fix_range (const char *); |
235 | static struct machine_function * ia64_init_machine_status (void); | |
236 | static void emit_insn_group_barriers (FILE *); | |
237 | static void emit_all_insn_group_barriers (FILE *); | |
238 | static void final_emit_insn_group_barriers (FILE *); | |
239 | static void emit_predicate_relation_info (void); | |
240 | static void ia64_reorg (void); | |
3101faab | 241 | static bool ia64_in_small_data_p (const_tree); |
658f32fd | 242 | static void process_epilogue (FILE *, rtx, bool, bool); |
9c808aad | 243 | |
9c808aad AJ |
244 | static bool ia64_assemble_integer (rtx, unsigned int, int); |
245 | static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT); | |
246 | static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
247 | static void ia64_output_function_end_prologue (FILE *); | |
248 | ||
5e50b799 AS |
249 | static void ia64_print_operand (FILE *, rtx, int); |
250 | static void ia64_print_operand_address (FILE *, rtx); | |
251 | static bool ia64_print_operand_punct_valid_p (unsigned char code); | |
252 | ||
9c808aad | 253 | static int ia64_issue_rate (void); |
388092d5 | 254 | static int ia64_adjust_cost_2 (rtx, int, rtx, int, dw_t); |
9c808aad | 255 | static void ia64_sched_init (FILE *, int, int); |
048d0d36 MK |
256 | static void ia64_sched_init_global (FILE *, int, int); |
257 | static void ia64_sched_finish_global (FILE *, int); | |
9c808aad AJ |
258 | static void ia64_sched_finish (FILE *, int); |
259 | static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int); | |
260 | static int ia64_sched_reorder (FILE *, int, rtx *, int *, int); | |
261 | static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int); | |
262 | static int ia64_variable_issue (FILE *, int, rtx, int); | |
263 | ||
a68b5e52 RH |
264 | static void ia64_asm_unwind_emit (FILE *, rtx); |
265 | static void ia64_asm_emit_except_personality (rtx); | |
266 | static void ia64_asm_init_sections (void); | |
267 | ||
f0a0390e | 268 | static enum unwind_info_type ia64_debug_unwind_info (void); |
f0a0390e | 269 | |
9c808aad AJ |
270 | static struct bundle_state *get_free_bundle_state (void); |
271 | static void free_bundle_state (struct bundle_state *); | |
272 | static void initiate_bundle_states (void); | |
273 | static void finish_bundle_states (void); | |
9c808aad AJ |
274 | static int insert_bundle_state (struct bundle_state *); |
275 | static void initiate_bundle_state_table (void); | |
276 | static void finish_bundle_state_table (void); | |
277 | static int try_issue_nops (struct bundle_state *, int); | |
278 | static int try_issue_insn (struct bundle_state *, rtx); | |
279 | static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int); | |
280 | static int get_max_pos (state_t); | |
281 | static int get_template (state_t, int); | |
282 | ||
283 | static rtx get_next_important_insn (rtx, rtx); | |
388092d5 | 284 | static bool important_for_bundling_p (rtx); |
7b84aac0 | 285 | static bool unknown_for_bundling_p (rtx); |
9c808aad AJ |
286 | static void bundling (FILE *, int, rtx, rtx); |
287 | ||
288 | static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
289 | HOST_WIDE_INT, tree); | |
290 | static void ia64_file_start (void); | |
812b587e | 291 | static void ia64_globalize_decl_name (FILE *, tree); |
9c808aad | 292 | |
9b580a0b RH |
293 | static int ia64_hpux_reloc_rw_mask (void) ATTRIBUTE_UNUSED; |
294 | static int ia64_reloc_rw_mask (void) ATTRIBUTE_UNUSED; | |
d6b5193b RS |
295 | static section *ia64_select_rtx_section (enum machine_mode, rtx, |
296 | unsigned HOST_WIDE_INT); | |
fdbe66f2 EB |
297 | static void ia64_output_dwarf_dtprel (FILE *, int, rtx) |
298 | ATTRIBUTE_UNUSED; | |
abb8b19a | 299 | static unsigned int ia64_section_type_flags (tree, const char *, int); |
1f7aa7cd SE |
300 | static void ia64_init_libfuncs (void) |
301 | ATTRIBUTE_UNUSED; | |
c15c90bb ZW |
302 | static void ia64_hpux_init_libfuncs (void) |
303 | ATTRIBUTE_UNUSED; | |
6bc709c1 L |
304 | static void ia64_sysv4_init_libfuncs (void) |
305 | ATTRIBUTE_UNUSED; | |
738e7b39 RK |
306 | static void ia64_vms_init_libfuncs (void) |
307 | ATTRIBUTE_UNUSED; | |
c252db20 L |
308 | static void ia64_soft_fp_init_libfuncs (void) |
309 | ATTRIBUTE_UNUSED; | |
f2972bf8 DR |
310 | static bool ia64_vms_valid_pointer_mode (enum machine_mode mode) |
311 | ATTRIBUTE_UNUSED; | |
30ed9d3d TG |
312 | static tree ia64_vms_common_object_attribute (tree *, tree, tree, int, bool *) |
313 | ATTRIBUTE_UNUSED; | |
a5fe455b | 314 | |
a32767e4 | 315 | static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *); |
812b587e | 316 | static tree ia64_handle_version_id_attribute (tree *, tree, tree, int, bool *); |
a32767e4 | 317 | static void ia64_encode_section_info (tree, rtx, int); |
351a758b | 318 | static rtx ia64_struct_value_rtx (tree, int); |
726a989a | 319 | static tree ia64_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); |
88ed5ef5 | 320 | static bool ia64_scalar_mode_supported_p (enum machine_mode mode); |
f61134e8 | 321 | static bool ia64_vector_mode_supported_p (enum machine_mode mode); |
1a627b35 | 322 | static bool ia64_legitimate_constant_p (enum machine_mode, rtx); |
903a9601 | 323 | static bool ia64_legitimate_address_p (enum machine_mode, rtx, bool); |
fbbf66e7 | 324 | static bool ia64_cannot_force_const_mem (enum machine_mode, rtx); |
3101faab KG |
325 | static const char *ia64_mangle_type (const_tree); |
326 | static const char *ia64_invalid_conversion (const_tree, const_tree); | |
327 | static const char *ia64_invalid_unary_op (int, const_tree); | |
328 | static const char *ia64_invalid_binary_op (int, const_tree, const_tree); | |
a31fa2e0 | 329 | static enum machine_mode ia64_c_mode_for_suffix (char); |
2a1211e5 | 330 | static void ia64_trampoline_init (rtx, tree, rtx); |
2b7e2984 | 331 | static void ia64_override_options_after_change (void); |
d9886a9e | 332 | static bool ia64_member_type_forces_blk (const_tree, enum machine_mode); |
5c255b57 | 333 | |
b14446e2 | 334 | static tree ia64_builtin_decl (unsigned, bool); |
ab177ad5 AS |
335 | |
336 | static reg_class_t ia64_preferred_reload_class (rtx, reg_class_t); | |
ffa88471 | 337 | static enum machine_mode ia64_get_reg_raw_mode (int regno); |
f16d3f39 JH |
338 | static section * ia64_hpux_function_section (tree, enum node_frequency, |
339 | bool, bool); | |
e6431744 RH |
340 | |
341 | static bool ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode, | |
342 | const unsigned char *sel); | |
343 | ||
344 | #define MAX_VECT_LEN 8 | |
345 | ||
346 | struct expand_vec_perm_d | |
347 | { | |
348 | rtx target, op0, op1; | |
349 | unsigned char perm[MAX_VECT_LEN]; | |
350 | enum machine_mode vmode; | |
351 | unsigned char nelt; | |
352 | bool one_operand_p; | |
353 | bool testing_p; | |
354 | }; | |
355 | ||
356 | static bool ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d); | |
357 | ||
672a6f42 | 358 | \f |
e6542f4e RH |
359 | /* Table of valid machine attributes. */ |
360 | static const struct attribute_spec ia64_attribute_table[] = | |
361 | { | |
62d784f7 KT |
362 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, |
363 | affects_type_identity } */ | |
364 | { "syscall_linkage", 0, 0, false, true, true, NULL, false }, | |
365 | { "model", 1, 1, true, false, false, ia64_handle_model_attribute, | |
366 | false }, | |
30ed9d3d | 367 | #if TARGET_ABI_OPEN_VMS |
62d784f7 KT |
368 | { "common_object", 1, 1, true, false, false, |
369 | ia64_vms_common_object_attribute, false }, | |
30ed9d3d | 370 | #endif |
812b587e | 371 | { "version_id", 1, 1, true, false, false, |
62d784f7 KT |
372 | ia64_handle_version_id_attribute, false }, |
373 | { NULL, 0, 0, false, false, false, NULL, false } | |
e6542f4e RH |
374 | }; |
375 | ||
672a6f42 | 376 | /* Initialize the GCC target structure. */ |
91d231cb JM |
377 | #undef TARGET_ATTRIBUTE_TABLE |
378 | #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table | |
672a6f42 | 379 | |
f6155fda SS |
380 | #undef TARGET_INIT_BUILTINS |
381 | #define TARGET_INIT_BUILTINS ia64_init_builtins | |
382 | ||
383 | #undef TARGET_EXPAND_BUILTIN | |
384 | #define TARGET_EXPAND_BUILTIN ia64_expand_builtin | |
385 | ||
b14446e2 SE |
386 | #undef TARGET_BUILTIN_DECL |
387 | #define TARGET_BUILTIN_DECL ia64_builtin_decl | |
388 | ||
301d03af RS |
389 | #undef TARGET_ASM_BYTE_OP |
390 | #define TARGET_ASM_BYTE_OP "\tdata1\t" | |
391 | #undef TARGET_ASM_ALIGNED_HI_OP | |
392 | #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t" | |
393 | #undef TARGET_ASM_ALIGNED_SI_OP | |
394 | #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t" | |
395 | #undef TARGET_ASM_ALIGNED_DI_OP | |
396 | #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t" | |
397 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
398 | #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t" | |
399 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
400 | #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t" | |
401 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
402 | #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t" | |
403 | #undef TARGET_ASM_INTEGER | |
404 | #define TARGET_ASM_INTEGER ia64_assemble_integer | |
405 | ||
930572b9 AS |
406 | #undef TARGET_OPTION_OVERRIDE |
407 | #define TARGET_OPTION_OVERRIDE ia64_option_override | |
408 | ||
08c148a8 NB |
409 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
410 | #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue | |
b4c25db2 NB |
411 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE |
412 | #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue | |
08c148a8 NB |
413 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
414 | #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue | |
415 | ||
5e50b799 AS |
416 | #undef TARGET_PRINT_OPERAND |
417 | #define TARGET_PRINT_OPERAND ia64_print_operand | |
418 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
419 | #define TARGET_PRINT_OPERAND_ADDRESS ia64_print_operand_address | |
420 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
421 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ia64_print_operand_punct_valid_p | |
422 | ||
ae46c4e0 RH |
423 | #undef TARGET_IN_SMALL_DATA_P |
424 | #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p | |
425 | ||
388092d5 AB |
426 | #undef TARGET_SCHED_ADJUST_COST_2 |
427 | #define TARGET_SCHED_ADJUST_COST_2 ia64_adjust_cost_2 | |
c237e94a ZW |
428 | #undef TARGET_SCHED_ISSUE_RATE |
429 | #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate | |
430 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
431 | #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue | |
432 | #undef TARGET_SCHED_INIT | |
433 | #define TARGET_SCHED_INIT ia64_sched_init | |
434 | #undef TARGET_SCHED_FINISH | |
435 | #define TARGET_SCHED_FINISH ia64_sched_finish | |
048d0d36 MK |
436 | #undef TARGET_SCHED_INIT_GLOBAL |
437 | #define TARGET_SCHED_INIT_GLOBAL ia64_sched_init_global | |
438 | #undef TARGET_SCHED_FINISH_GLOBAL | |
439 | #define TARGET_SCHED_FINISH_GLOBAL ia64_sched_finish_global | |
c237e94a ZW |
440 | #undef TARGET_SCHED_REORDER |
441 | #define TARGET_SCHED_REORDER ia64_sched_reorder | |
442 | #undef TARGET_SCHED_REORDER2 | |
443 | #define TARGET_SCHED_REORDER2 ia64_sched_reorder2 | |
c237e94a | 444 | |
30028c85 VM |
445 | #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK |
446 | #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook | |
447 | ||
30028c85 VM |
448 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
449 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead | |
450 | ||
451 | #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN | |
452 | #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn | |
453 | #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN | |
454 | #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn | |
455 | ||
456 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD | |
457 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\ | |
458 | ia64_first_cycle_multipass_dfa_lookahead_guard | |
459 | ||
460 | #undef TARGET_SCHED_DFA_NEW_CYCLE | |
461 | #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle | |
462 | ||
048d0d36 MK |
463 | #undef TARGET_SCHED_H_I_D_EXTENDED |
464 | #define TARGET_SCHED_H_I_D_EXTENDED ia64_h_i_d_extended | |
465 | ||
388092d5 AB |
466 | #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT |
467 | #define TARGET_SCHED_ALLOC_SCHED_CONTEXT ia64_alloc_sched_context | |
468 | ||
469 | #undef TARGET_SCHED_INIT_SCHED_CONTEXT | |
470 | #define TARGET_SCHED_INIT_SCHED_CONTEXT ia64_init_sched_context | |
471 | ||
472 | #undef TARGET_SCHED_SET_SCHED_CONTEXT | |
473 | #define TARGET_SCHED_SET_SCHED_CONTEXT ia64_set_sched_context | |
474 | ||
475 | #undef TARGET_SCHED_CLEAR_SCHED_CONTEXT | |
476 | #define TARGET_SCHED_CLEAR_SCHED_CONTEXT ia64_clear_sched_context | |
477 | ||
478 | #undef TARGET_SCHED_FREE_SCHED_CONTEXT | |
479 | #define TARGET_SCHED_FREE_SCHED_CONTEXT ia64_free_sched_context | |
480 | ||
048d0d36 MK |
481 | #undef TARGET_SCHED_SET_SCHED_FLAGS |
482 | #define TARGET_SCHED_SET_SCHED_FLAGS ia64_set_sched_flags | |
483 | ||
388092d5 AB |
484 | #undef TARGET_SCHED_GET_INSN_SPEC_DS |
485 | #define TARGET_SCHED_GET_INSN_SPEC_DS ia64_get_insn_spec_ds | |
486 | ||
487 | #undef TARGET_SCHED_GET_INSN_CHECKED_DS | |
488 | #define TARGET_SCHED_GET_INSN_CHECKED_DS ia64_get_insn_checked_ds | |
489 | ||
048d0d36 MK |
490 | #undef TARGET_SCHED_SPECULATE_INSN |
491 | #define TARGET_SCHED_SPECULATE_INSN ia64_speculate_insn | |
492 | ||
493 | #undef TARGET_SCHED_NEEDS_BLOCK_P | |
494 | #define TARGET_SCHED_NEEDS_BLOCK_P ia64_needs_block_p | |
495 | ||
e855c69d | 496 | #undef TARGET_SCHED_GEN_SPEC_CHECK |
388092d5 | 497 | #define TARGET_SCHED_GEN_SPEC_CHECK ia64_gen_spec_check |
048d0d36 | 498 | |
388092d5 AB |
499 | #undef TARGET_SCHED_SKIP_RTX_P |
500 | #define TARGET_SCHED_SKIP_RTX_P ia64_skip_rtx_p | |
501 | ||
599aedd9 RH |
502 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
503 | #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall | |
78a52f11 RH |
504 | #undef TARGET_ARG_PARTIAL_BYTES |
505 | #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes | |
ffa88471 SE |
506 | #undef TARGET_FUNCTION_ARG |
507 | #define TARGET_FUNCTION_ARG ia64_function_arg | |
508 | #undef TARGET_FUNCTION_INCOMING_ARG | |
509 | #define TARGET_FUNCTION_INCOMING_ARG ia64_function_incoming_arg | |
510 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
511 | #define TARGET_FUNCTION_ARG_ADVANCE ia64_function_arg_advance | |
c2ed6cf8 NF |
512 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
513 | #define TARGET_FUNCTION_ARG_BOUNDARY ia64_function_arg_boundary | |
599aedd9 | 514 | |
c590b625 RH |
515 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
516 | #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk | |
3961e8fe | 517 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3101faab | 518 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
c590b625 | 519 | |
1bc7c5b6 ZW |
520 | #undef TARGET_ASM_FILE_START |
521 | #define TARGET_ASM_FILE_START ia64_file_start | |
522 | ||
812b587e SE |
523 | #undef TARGET_ASM_GLOBALIZE_DECL_NAME |
524 | #define TARGET_ASM_GLOBALIZE_DECL_NAME ia64_globalize_decl_name | |
525 | ||
de8f4b07 AS |
526 | #undef TARGET_REGISTER_MOVE_COST |
527 | #define TARGET_REGISTER_MOVE_COST ia64_register_move_cost | |
69e18c09 AS |
528 | #undef TARGET_MEMORY_MOVE_COST |
529 | #define TARGET_MEMORY_MOVE_COST ia64_memory_move_cost | |
3c50106f RH |
530 | #undef TARGET_RTX_COSTS |
531 | #define TARGET_RTX_COSTS ia64_rtx_costs | |
dcefdf67 | 532 | #undef TARGET_ADDRESS_COST |
b413068c | 533 | #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 |
3c50106f | 534 | |
215b063c PB |
535 | #undef TARGET_UNSPEC_MAY_TRAP_P |
536 | #define TARGET_UNSPEC_MAY_TRAP_P ia64_unspec_may_trap_p | |
537 | ||
18dbd950 RS |
538 | #undef TARGET_MACHINE_DEPENDENT_REORG |
539 | #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg | |
540 | ||
a32767e4 DM |
541 | #undef TARGET_ENCODE_SECTION_INFO |
542 | #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info | |
543 | ||
abb8b19a AM |
544 | #undef TARGET_SECTION_TYPE_FLAGS |
545 | #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags | |
546 | ||
fdbe66f2 EB |
547 | #ifdef HAVE_AS_TLS |
548 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
549 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel | |
550 | #endif | |
551 | ||
351a758b KH |
552 | /* ??? Investigate. */ |
553 | #if 0 | |
554 | #undef TARGET_PROMOTE_PROTOTYPES | |
555 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
556 | #endif | |
557 | ||
ba90d838 AS |
558 | #undef TARGET_FUNCTION_VALUE |
559 | #define TARGET_FUNCTION_VALUE ia64_function_value | |
560 | #undef TARGET_LIBCALL_VALUE | |
561 | #define TARGET_LIBCALL_VALUE ia64_libcall_value | |
562 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
563 | #define TARGET_FUNCTION_VALUE_REGNO_P ia64_function_value_regno_p | |
564 | ||
351a758b KH |
565 | #undef TARGET_STRUCT_VALUE_RTX |
566 | #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx | |
567 | #undef TARGET_RETURN_IN_MEMORY | |
568 | #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory | |
351a758b KH |
569 | #undef TARGET_SETUP_INCOMING_VARARGS |
570 | #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs | |
571 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
572 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
fe984136 RH |
573 | #undef TARGET_MUST_PASS_IN_STACK |
574 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
ffa88471 SE |
575 | #undef TARGET_GET_RAW_RESULT_MODE |
576 | #define TARGET_GET_RAW_RESULT_MODE ia64_get_reg_raw_mode | |
577 | #undef TARGET_GET_RAW_ARG_MODE | |
578 | #define TARGET_GET_RAW_ARG_MODE ia64_get_reg_raw_mode | |
351a758b | 579 | |
d9886a9e L |
580 | #undef TARGET_MEMBER_TYPE_FORCES_BLK |
581 | #define TARGET_MEMBER_TYPE_FORCES_BLK ia64_member_type_forces_blk | |
582 | ||
cd3ce9b4 JM |
583 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
584 | #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg | |
585 | ||
38f8b050 | 586 | #undef TARGET_ASM_UNWIND_EMIT |
a68b5e52 RH |
587 | #define TARGET_ASM_UNWIND_EMIT ia64_asm_unwind_emit |
588 | #undef TARGET_ASM_EMIT_EXCEPT_PERSONALITY | |
589 | #define TARGET_ASM_EMIT_EXCEPT_PERSONALITY ia64_asm_emit_except_personality | |
590 | #undef TARGET_ASM_INIT_SECTIONS | |
591 | #define TARGET_ASM_INIT_SECTIONS ia64_asm_init_sections | |
951120ea | 592 | |
f0a0390e RH |
593 | #undef TARGET_DEBUG_UNWIND_INFO |
594 | #define TARGET_DEBUG_UNWIND_INFO ia64_debug_unwind_info | |
f0a0390e | 595 | |
88ed5ef5 SE |
596 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
597 | #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p | |
f61134e8 RH |
598 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
599 | #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p | |
88ed5ef5 | 600 | |
445cf5eb JM |
601 | /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur |
602 | in an order different from the specified program order. */ | |
603 | #undef TARGET_RELAXED_ORDERING | |
604 | #define TARGET_RELAXED_ORDERING true | |
605 | ||
1a627b35 RS |
606 | #undef TARGET_LEGITIMATE_CONSTANT_P |
607 | #define TARGET_LEGITIMATE_CONSTANT_P ia64_legitimate_constant_p | |
903a9601 AS |
608 | #undef TARGET_LEGITIMATE_ADDRESS_P |
609 | #define TARGET_LEGITIMATE_ADDRESS_P ia64_legitimate_address_p | |
1a627b35 | 610 | |
5e6c8b64 RH |
611 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
612 | #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem | |
613 | ||
608063c3 JB |
614 | #undef TARGET_MANGLE_TYPE |
615 | #define TARGET_MANGLE_TYPE ia64_mangle_type | |
cac24f06 | 616 | |
4de67c26 JM |
617 | #undef TARGET_INVALID_CONVERSION |
618 | #define TARGET_INVALID_CONVERSION ia64_invalid_conversion | |
619 | #undef TARGET_INVALID_UNARY_OP | |
620 | #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op | |
621 | #undef TARGET_INVALID_BINARY_OP | |
622 | #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op | |
623 | ||
a31fa2e0 SE |
624 | #undef TARGET_C_MODE_FOR_SUFFIX |
625 | #define TARGET_C_MODE_FOR_SUFFIX ia64_c_mode_for_suffix | |
626 | ||
7b5cbb57 AS |
627 | #undef TARGET_CAN_ELIMINATE |
628 | #define TARGET_CAN_ELIMINATE ia64_can_eliminate | |
629 | ||
2a1211e5 RH |
630 | #undef TARGET_TRAMPOLINE_INIT |
631 | #define TARGET_TRAMPOLINE_INIT ia64_trampoline_init | |
632 | ||
1d0216c8 RS |
633 | #undef TARGET_CAN_USE_DOLOOP_P |
634 | #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost | |
810d71d0 JW |
635 | #undef TARGET_INVALID_WITHIN_DOLOOP |
636 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null | |
637 | ||
2b7e2984 SE |
638 | #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE |
639 | #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ia64_override_options_after_change | |
640 | ||
ab177ad5 AS |
641 | #undef TARGET_PREFERRED_RELOAD_CLASS |
642 | #define TARGET_PREFERRED_RELOAD_CLASS ia64_preferred_reload_class | |
643 | ||
2ba42841 AO |
644 | #undef TARGET_DELAY_SCHED2 |
645 | #define TARGET_DELAY_SCHED2 true | |
646 | ||
647 | /* Variable tracking should be run after all optimizations which | |
648 | change order of insns. It also needs a valid CFG. */ | |
649 | #undef TARGET_DELAY_VARTRACK | |
650 | #define TARGET_DELAY_VARTRACK true | |
651 | ||
e6431744 RH |
652 | #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK |
653 | #define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok | |
654 | ||
f6897b10 | 655 | struct gcc_target targetm = TARGET_INITIALIZER; |
3b572406 | 656 | \f |
a32767e4 DM |
657 | typedef enum |
658 | { | |
659 | ADDR_AREA_NORMAL, /* normal address area */ | |
660 | ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */ | |
661 | } | |
662 | ia64_addr_area; | |
663 | ||
664 | static GTY(()) tree small_ident1; | |
665 | static GTY(()) tree small_ident2; | |
666 | ||
667 | static void | |
668 | init_idents (void) | |
669 | { | |
670 | if (small_ident1 == 0) | |
671 | { | |
672 | small_ident1 = get_identifier ("small"); | |
673 | small_ident2 = get_identifier ("__small__"); | |
674 | } | |
675 | } | |
676 | ||
677 | /* Retrieve the address area that has been chosen for the given decl. */ | |
678 | ||
679 | static ia64_addr_area | |
680 | ia64_get_addr_area (tree decl) | |
681 | { | |
682 | tree model_attr; | |
683 | ||
684 | model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); | |
685 | if (model_attr) | |
686 | { | |
687 | tree id; | |
688 | ||
689 | init_idents (); | |
690 | id = TREE_VALUE (TREE_VALUE (model_attr)); | |
691 | if (id == small_ident1 || id == small_ident2) | |
692 | return ADDR_AREA_SMALL; | |
693 | } | |
694 | return ADDR_AREA_NORMAL; | |
695 | } | |
696 | ||
697 | static tree | |
f61134e8 RH |
698 | ia64_handle_model_attribute (tree *node, tree name, tree args, |
699 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
a32767e4 DM |
700 | { |
701 | ia64_addr_area addr_area = ADDR_AREA_NORMAL; | |
702 | ia64_addr_area area; | |
703 | tree arg, decl = *node; | |
704 | ||
705 | init_idents (); | |
706 | arg = TREE_VALUE (args); | |
707 | if (arg == small_ident1 || arg == small_ident2) | |
708 | { | |
709 | addr_area = ADDR_AREA_SMALL; | |
710 | } | |
711 | else | |
712 | { | |
29d08eba JM |
713 | warning (OPT_Wattributes, "invalid argument of %qE attribute", |
714 | name); | |
a32767e4 DM |
715 | *no_add_attrs = true; |
716 | } | |
717 | ||
718 | switch (TREE_CODE (decl)) | |
719 | { | |
720 | case VAR_DECL: | |
721 | if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) | |
722 | == FUNCTION_DECL) | |
723 | && !TREE_STATIC (decl)) | |
724 | { | |
c5d75364 MLI |
725 | error_at (DECL_SOURCE_LOCATION (decl), |
726 | "an address area attribute cannot be specified for " | |
727 | "local variables"); | |
a32767e4 DM |
728 | *no_add_attrs = true; |
729 | } | |
730 | area = ia64_get_addr_area (decl); | |
731 | if (area != ADDR_AREA_NORMAL && addr_area != area) | |
732 | { | |
dee15844 JM |
733 | error ("address area of %q+D conflicts with previous " |
734 | "declaration", decl); | |
a32767e4 DM |
735 | *no_add_attrs = true; |
736 | } | |
737 | break; | |
738 | ||
739 | case FUNCTION_DECL: | |
c5d75364 | 740 | error_at (DECL_SOURCE_LOCATION (decl), |
d575725b L |
741 | "address area attribute cannot be specified for " |
742 | "functions"); | |
a32767e4 DM |
743 | *no_add_attrs = true; |
744 | break; | |
745 | ||
746 | default: | |
29d08eba JM |
747 | warning (OPT_Wattributes, "%qE attribute ignored", |
748 | name); | |
a32767e4 DM |
749 | *no_add_attrs = true; |
750 | break; | |
751 | } | |
752 | ||
753 | return NULL_TREE; | |
754 | } | |
755 | ||
30ed9d3d TG |
756 | /* Part of the low level implementation of DEC Ada pragma Common_Object which |
757 | enables the shared use of variables stored in overlaid linker areas | |
758 | corresponding to the use of Fortran COMMON. */ | |
759 | ||
760 | static tree | |
761 | ia64_vms_common_object_attribute (tree *node, tree name, tree args, | |
762 | int flags ATTRIBUTE_UNUSED, | |
763 | bool *no_add_attrs) | |
764 | { | |
765 | tree decl = *node; | |
fe5798c0 TG |
766 | tree id; |
767 | ||
768 | gcc_assert (DECL_P (decl)); | |
30ed9d3d TG |
769 | |
770 | DECL_COMMON (decl) = 1; | |
771 | id = TREE_VALUE (args); | |
fe5798c0 | 772 | if (TREE_CODE (id) != IDENTIFIER_NODE && TREE_CODE (id) != STRING_CST) |
30ed9d3d | 773 | { |
fe5798c0 | 774 | error ("%qE attribute requires a string constant argument", name); |
30ed9d3d TG |
775 | *no_add_attrs = true; |
776 | return NULL_TREE; | |
777 | } | |
30ed9d3d TG |
778 | return NULL_TREE; |
779 | } | |
780 | ||
781 | /* Part of the low level implementation of DEC Ada pragma Common_Object. */ | |
782 | ||
783 | void | |
784 | ia64_vms_output_aligned_decl_common (FILE *file, tree decl, const char *name, | |
785 | unsigned HOST_WIDE_INT size, | |
786 | unsigned int align) | |
787 | { | |
788 | tree attr = DECL_ATTRIBUTES (decl); | |
789 | ||
fe5798c0 | 790 | if (attr) |
30ed9d3d | 791 | attr = lookup_attribute ("common_object", attr); |
fe5798c0 | 792 | if (attr) |
30ed9d3d | 793 | { |
fe5798c0 TG |
794 | tree id = TREE_VALUE (TREE_VALUE (attr)); |
795 | const char *name; | |
30ed9d3d | 796 | |
fe5798c0 TG |
797 | if (TREE_CODE (id) == IDENTIFIER_NODE) |
798 | name = IDENTIFIER_POINTER (id); | |
799 | else if (TREE_CODE (id) == STRING_CST) | |
800 | name = TREE_STRING_POINTER (id); | |
801 | else | |
802 | abort (); | |
30ed9d3d | 803 | |
fe5798c0 | 804 | fprintf (file, "\t.vms_common\t\"%s\",", name); |
30ed9d3d | 805 | } |
fe5798c0 TG |
806 | else |
807 | fprintf (file, "%s", COMMON_ASM_OP); | |
30ed9d3d | 808 | |
fe5798c0 TG |
809 | /* Code from elfos.h. */ |
810 | assemble_name (file, name); | |
811 | fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u", | |
812 | size, align / BITS_PER_UNIT); | |
30ed9d3d | 813 | |
fe5798c0 | 814 | fputc ('\n', file); |
30ed9d3d TG |
815 | } |
816 | ||
a32767e4 DM |
817 | static void |
818 | ia64_encode_addr_area (tree decl, rtx symbol) | |
819 | { | |
820 | int flags; | |
821 | ||
822 | flags = SYMBOL_REF_FLAGS (symbol); | |
823 | switch (ia64_get_addr_area (decl)) | |
824 | { | |
825 | case ADDR_AREA_NORMAL: break; | |
826 | case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break; | |
e820471b | 827 | default: gcc_unreachable (); |
a32767e4 DM |
828 | } |
829 | SYMBOL_REF_FLAGS (symbol) = flags; | |
830 | } | |
831 | ||
832 | static void | |
833 | ia64_encode_section_info (tree decl, rtx rtl, int first) | |
834 | { | |
835 | default_encode_section_info (decl, rtl, first); | |
836 | ||
2897f1d4 | 837 | /* Careful not to prod global register variables. */ |
a32767e4 | 838 | if (TREE_CODE (decl) == VAR_DECL |
2897f1d4 L |
839 | && GET_CODE (DECL_RTL (decl)) == MEM |
840 | && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF | |
a32767e4 DM |
841 | && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) |
842 | ia64_encode_addr_area (decl, XEXP (rtl, 0)); | |
843 | } | |
844 | \f | |
557b9df5 RH |
845 | /* Return 1 if the operands of a move are ok. */ |
846 | ||
847 | int | |
9c808aad | 848 | ia64_move_ok (rtx dst, rtx src) |
557b9df5 RH |
849 | { |
850 | /* If we're under init_recog_no_volatile, we'll not be able to use | |
851 | memory_operand. So check the code directly and don't worry about | |
852 | the validity of the underlying address, which should have been | |
853 | checked elsewhere anyway. */ | |
854 | if (GET_CODE (dst) != MEM) | |
855 | return 1; | |
856 | if (GET_CODE (src) == MEM) | |
857 | return 0; | |
858 | if (register_operand (src, VOIDmode)) | |
859 | return 1; | |
860 | ||
861 | /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */ | |
862 | if (INTEGRAL_MODE_P (GET_MODE (dst))) | |
863 | return src == const0_rtx; | |
864 | else | |
13f70342 | 865 | return satisfies_constraint_G (src); |
557b9df5 | 866 | } |
9b7bf67d | 867 | |
a71aef0b JB |
868 | /* Return 1 if the operands are ok for a floating point load pair. */ |
869 | ||
870 | int | |
871 | ia64_load_pair_ok (rtx dst, rtx src) | |
872 | { | |
22be5918 EB |
873 | /* ??? There is a thinko in the implementation of the "x" constraint and the |
874 | FP_REGS class. The constraint will also reject (reg f30:TI) so we must | |
875 | also return false for it. */ | |
876 | if (GET_CODE (dst) != REG | |
877 | || !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1))) | |
a71aef0b JB |
878 | return 0; |
879 | if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src)) | |
880 | return 0; | |
881 | switch (GET_CODE (XEXP (src, 0))) | |
882 | { | |
883 | case REG: | |
884 | case POST_INC: | |
885 | break; | |
886 | case POST_DEC: | |
887 | return 0; | |
888 | case POST_MODIFY: | |
889 | { | |
890 | rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1); | |
891 | ||
892 | if (GET_CODE (adjust) != CONST_INT | |
893 | || INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src))) | |
894 | return 0; | |
895 | } | |
896 | break; | |
897 | default: | |
898 | abort (); | |
899 | } | |
900 | return 1; | |
901 | } | |
902 | ||
08744705 | 903 | int |
9c808aad | 904 | addp4_optimize_ok (rtx op1, rtx op2) |
08744705 | 905 | { |
08744705 SE |
906 | return (basereg_operand (op1, GET_MODE(op1)) != |
907 | basereg_operand (op2, GET_MODE(op2))); | |
908 | } | |
909 | ||
9e4f94de | 910 | /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction. |
041f25e6 RH |
911 | Return the length of the field, or <= 0 on failure. */ |
912 | ||
913 | int | |
9c808aad | 914 | ia64_depz_field_mask (rtx rop, rtx rshift) |
041f25e6 RH |
915 | { |
916 | unsigned HOST_WIDE_INT op = INTVAL (rop); | |
917 | unsigned HOST_WIDE_INT shift = INTVAL (rshift); | |
918 | ||
919 | /* Get rid of the zero bits we're shifting in. */ | |
920 | op >>= shift; | |
921 | ||
922 | /* We must now have a solid block of 1's at bit 0. */ | |
923 | return exact_log2 (op + 1); | |
924 | } | |
925 | ||
5e6c8b64 RH |
926 | /* Return the TLS model to use for ADDR. */ |
927 | ||
928 | static enum tls_model | |
929 | tls_symbolic_operand_type (rtx addr) | |
930 | { | |
81f40b79 | 931 | enum tls_model tls_kind = TLS_MODEL_NONE; |
5e6c8b64 RH |
932 | |
933 | if (GET_CODE (addr) == CONST) | |
934 | { | |
935 | if (GET_CODE (XEXP (addr, 0)) == PLUS | |
936 | && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF) | |
937 | tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0)); | |
938 | } | |
939 | else if (GET_CODE (addr) == SYMBOL_REF) | |
940 | tls_kind = SYMBOL_REF_TLS_MODEL (addr); | |
941 | ||
942 | return tls_kind; | |
943 | } | |
944 | ||
903a9601 AS |
945 | /* Returns true if REG (assumed to be a `reg' RTX) is valid for use |
946 | as a base register. */ | |
947 | ||
948 | static inline bool | |
949 | ia64_reg_ok_for_base_p (const_rtx reg, bool strict) | |
950 | { | |
951 | if (strict | |
952 | && REGNO_OK_FOR_BASE_P (REGNO (reg))) | |
953 | return true; | |
954 | else if (!strict | |
955 | && (GENERAL_REGNO_P (REGNO (reg)) | |
956 | || !HARD_REGISTER_P (reg))) | |
957 | return true; | |
958 | else | |
959 | return false; | |
960 | } | |
961 | ||
962 | static bool | |
963 | ia64_legitimate_address_reg (const_rtx reg, bool strict) | |
964 | { | |
965 | if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict)) | |
966 | || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0)) | |
967 | && ia64_reg_ok_for_base_p (XEXP (reg, 0), strict))) | |
968 | return true; | |
969 | ||
970 | return false; | |
971 | } | |
972 | ||
973 | static bool | |
974 | ia64_legitimate_address_disp (const_rtx reg, const_rtx disp, bool strict) | |
975 | { | |
976 | if (GET_CODE (disp) == PLUS | |
977 | && rtx_equal_p (reg, XEXP (disp, 0)) | |
978 | && (ia64_legitimate_address_reg (XEXP (disp, 1), strict) | |
979 | || (CONST_INT_P (XEXP (disp, 1)) | |
980 | && IN_RANGE (INTVAL (XEXP (disp, 1)), -256, 255)))) | |
981 | return true; | |
982 | ||
983 | return false; | |
984 | } | |
985 | ||
986 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ | |
987 | ||
988 | static bool | |
989 | ia64_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
990 | rtx x, bool strict) | |
991 | { | |
992 | if (ia64_legitimate_address_reg (x, strict)) | |
993 | return true; | |
994 | else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
995 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
996 | && XEXP (x, 0) != arg_pointer_rtx) | |
997 | return true; | |
998 | else if (GET_CODE (x) == POST_MODIFY | |
999 | && ia64_legitimate_address_reg (XEXP (x, 0), strict) | |
1000 | && XEXP (x, 0) != arg_pointer_rtx | |
1001 | && ia64_legitimate_address_disp (XEXP (x, 0), XEXP (x, 1), strict)) | |
1002 | return true; | |
1003 | else | |
1004 | return false; | |
1005 | } | |
1006 | ||
5e6c8b64 RH |
1007 | /* Return true if X is a constant that is valid for some immediate |
1008 | field in an instruction. */ | |
1009 | ||
1a627b35 RS |
1010 | static bool |
1011 | ia64_legitimate_constant_p (enum machine_mode mode, rtx x) | |
5e6c8b64 RH |
1012 | { |
1013 | switch (GET_CODE (x)) | |
1014 | { | |
1015 | case CONST_INT: | |
1016 | case LABEL_REF: | |
1017 | return true; | |
1018 | ||
1019 | case CONST_DOUBLE: | |
1a627b35 | 1020 | if (GET_MODE (x) == VOIDmode || mode == SFmode || mode == DFmode) |
5e6c8b64 | 1021 | return true; |
13f70342 | 1022 | return satisfies_constraint_G (x); |
5e6c8b64 RH |
1023 | |
1024 | case CONST: | |
1025 | case SYMBOL_REF: | |
d0970db2 JW |
1026 | /* ??? Short term workaround for PR 28490. We must make the code here |
1027 | match the code in ia64_expand_move and move_operand, even though they | |
1028 | are both technically wrong. */ | |
1029 | if (tls_symbolic_operand_type (x) == 0) | |
1030 | { | |
1031 | HOST_WIDE_INT addend = 0; | |
1032 | rtx op = x; | |
1033 | ||
1034 | if (GET_CODE (op) == CONST | |
1035 | && GET_CODE (XEXP (op, 0)) == PLUS | |
1036 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) | |
1037 | { | |
1038 | addend = INTVAL (XEXP (XEXP (op, 0), 1)); | |
1039 | op = XEXP (XEXP (op, 0), 0); | |
1040 | } | |
1041 | ||
1a627b35 RS |
1042 | if (any_offset_symbol_operand (op, mode) |
1043 | || function_operand (op, mode)) | |
7ab62966 | 1044 | return true; |
1a627b35 | 1045 | if (aligned_offset_symbol_operand (op, mode)) |
d0970db2 JW |
1046 | return (addend & 0x3fff) == 0; |
1047 | return false; | |
1048 | } | |
1049 | return false; | |
5e6c8b64 | 1050 | |
b4e3537b | 1051 | case CONST_VECTOR: |
1a627b35 RS |
1052 | if (mode == V2SFmode) |
1053 | return satisfies_constraint_Y (x); | |
b4e3537b | 1054 | |
1a627b35 RS |
1055 | return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT |
1056 | && GET_MODE_SIZE (mode) <= 8); | |
b4e3537b | 1057 | |
5e6c8b64 RH |
1058 | default: |
1059 | return false; | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | /* Don't allow TLS addresses to get spilled to memory. */ | |
1064 | ||
1065 | static bool | |
fbbf66e7 | 1066 | ia64_cannot_force_const_mem (enum machine_mode mode, rtx x) |
5e6c8b64 | 1067 | { |
fbbf66e7 | 1068 | if (mode == RFmode) |
103a6411 | 1069 | return true; |
5e6c8b64 RH |
1070 | return tls_symbolic_operand_type (x) != 0; |
1071 | } | |
1072 | ||
9b7bf67d | 1073 | /* Expand a symbolic constant load. */ |
9b7bf67d | 1074 | |
5e6c8b64 | 1075 | bool |
9c808aad | 1076 | ia64_expand_load_address (rtx dest, rtx src) |
9b7bf67d | 1077 | { |
e820471b | 1078 | gcc_assert (GET_CODE (dest) == REG); |
7b6e506e | 1079 | |
ae49d6e5 RH |
1080 | /* ILP32 mode still loads 64-bits of data from the GOT. This avoids |
1081 | having to pointer-extend the value afterward. Other forms of address | |
1082 | computation below are also more natural to compute as 64-bit quantities. | |
1083 | If we've been given an SImode destination register, change it. */ | |
1084 | if (GET_MODE (dest) != Pmode) | |
38ae7651 RS |
1085 | dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), |
1086 | byte_lowpart_offset (Pmode, GET_MODE (dest))); | |
ae49d6e5 | 1087 | |
5e6c8b64 RH |
1088 | if (TARGET_NO_PIC) |
1089 | return false; | |
1090 | if (small_addr_symbolic_operand (src, VOIDmode)) | |
1091 | return false; | |
1092 | ||
1093 | if (TARGET_AUTO_PIC) | |
1094 | emit_insn (gen_load_gprel64 (dest, src)); | |
1cdbd630 | 1095 | else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src)) |
5e6c8b64 | 1096 | emit_insn (gen_load_fptr (dest, src)); |
21515593 | 1097 | else if (sdata_symbolic_operand (src, VOIDmode)) |
5e6c8b64 RH |
1098 | emit_insn (gen_load_gprel (dest, src)); |
1099 | else | |
21515593 | 1100 | { |
5e6c8b64 RH |
1101 | HOST_WIDE_INT addend = 0; |
1102 | rtx tmp; | |
21515593 | 1103 | |
5e6c8b64 RH |
1104 | /* We did split constant offsets in ia64_expand_move, and we did try |
1105 | to keep them split in move_operand, but we also allowed reload to | |
1106 | rematerialize arbitrary constants rather than spill the value to | |
1107 | the stack and reload it. So we have to be prepared here to split | |
1108 | them apart again. */ | |
1109 | if (GET_CODE (src) == CONST) | |
1110 | { | |
1111 | HOST_WIDE_INT hi, lo; | |
9b7bf67d | 1112 | |
5e6c8b64 RH |
1113 | hi = INTVAL (XEXP (XEXP (src, 0), 1)); |
1114 | lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000; | |
1115 | hi = hi - lo; | |
9b7bf67d | 1116 | |
5e6c8b64 RH |
1117 | if (lo != 0) |
1118 | { | |
1119 | addend = lo; | |
0a81f074 | 1120 | src = plus_constant (Pmode, XEXP (XEXP (src, 0), 0), hi); |
5e6c8b64 RH |
1121 | } |
1122 | } | |
ae49d6e5 RH |
1123 | |
1124 | tmp = gen_rtx_HIGH (Pmode, src); | |
1125 | tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx); | |
1126 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1127 | ||
1f88caaa | 1128 | tmp = gen_rtx_LO_SUM (Pmode, gen_const_mem (Pmode, dest), src); |
ae49d6e5 | 1129 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); |
5e6c8b64 RH |
1130 | |
1131 | if (addend) | |
1132 | { | |
1133 | tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend)); | |
1134 | emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); | |
1135 | } | |
ae49d6e5 | 1136 | } |
5e6c8b64 RH |
1137 | |
1138 | return true; | |
9b7bf67d | 1139 | } |
97e242b0 | 1140 | |
e2500fed | 1141 | static GTY(()) rtx gen_tls_tga; |
7b6e506e | 1142 | static rtx |
9c808aad | 1143 | gen_tls_get_addr (void) |
7b6e506e | 1144 | { |
e2500fed | 1145 | if (!gen_tls_tga) |
21515593 | 1146 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); |
e2500fed | 1147 | return gen_tls_tga; |
7b6e506e RH |
1148 | } |
1149 | ||
e2500fed | 1150 | static GTY(()) rtx thread_pointer_rtx; |
7b6e506e | 1151 | static rtx |
9c808aad | 1152 | gen_thread_pointer (void) |
7b6e506e | 1153 | { |
e2500fed | 1154 | if (!thread_pointer_rtx) |
389fdba0 | 1155 | thread_pointer_rtx = gen_rtx_REG (Pmode, 13); |
135ca7b2 | 1156 | return thread_pointer_rtx; |
7b6e506e RH |
1157 | } |
1158 | ||
21515593 | 1159 | static rtx |
5e6c8b64 | 1160 | ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1, |
b15b83fb | 1161 | rtx orig_op1, HOST_WIDE_INT addend) |
21515593 RH |
1162 | { |
1163 | rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns; | |
b15b83fb | 1164 | rtx orig_op0 = op0; |
5e6c8b64 RH |
1165 | HOST_WIDE_INT addend_lo, addend_hi; |
1166 | ||
21515593 RH |
1167 | switch (tls_kind) |
1168 | { | |
1169 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
1170 | start_sequence (); | |
1171 | ||
1172 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1173 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1174 | |
1175 | tga_op2 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1176 | emit_insn (gen_load_dtprel (tga_op2, op1)); |
9c808aad | 1177 | |
21515593 RH |
1178 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, |
1179 | LCT_CONST, Pmode, 2, tga_op1, | |
1180 | Pmode, tga_op2, Pmode); | |
1181 | ||
1182 | insns = get_insns (); | |
1183 | end_sequence (); | |
1184 | ||
0d433a6a RH |
1185 | if (GET_MODE (op0) != Pmode) |
1186 | op0 = tga_ret; | |
21515593 | 1187 | emit_libcall_block (insns, op0, tga_ret, op1); |
0d433a6a | 1188 | break; |
21515593 RH |
1189 | |
1190 | case TLS_MODEL_LOCAL_DYNAMIC: | |
1191 | /* ??? This isn't the completely proper way to do local-dynamic | |
1192 | If the call to __tls_get_addr is used only by a single symbol, | |
1193 | then we should (somehow) move the dtprel to the second arg | |
1194 | to avoid the extra add. */ | |
1195 | start_sequence (); | |
1196 | ||
1197 | tga_op1 = gen_reg_rtx (Pmode); | |
5e6c8b64 | 1198 | emit_insn (gen_load_dtpmod (tga_op1, op1)); |
21515593 RH |
1199 | |
1200 | tga_op2 = const0_rtx; | |
1201 | ||
1202 | tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX, | |
1203 | LCT_CONST, Pmode, 2, tga_op1, | |
1204 | Pmode, tga_op2, Pmode); | |
1205 | ||
1206 | insns = get_insns (); | |
1207 | end_sequence (); | |
1208 | ||
1209 | tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
1210 | UNSPEC_LD_BASE); | |
1211 | tmp = gen_reg_rtx (Pmode); | |
1212 | emit_libcall_block (insns, tmp, tga_ret, tga_eqv); | |
1213 | ||
0d433a6a RH |
1214 | if (!register_operand (op0, Pmode)) |
1215 | op0 = gen_reg_rtx (Pmode); | |
21515593 RH |
1216 | if (TARGET_TLS64) |
1217 | { | |
0d433a6a RH |
1218 | emit_insn (gen_load_dtprel (op0, op1)); |
1219 | emit_insn (gen_adddi3 (op0, tmp, op0)); | |
21515593 RH |
1220 | } |
1221 | else | |
5e6c8b64 | 1222 | emit_insn (gen_add_dtprel (op0, op1, tmp)); |
0d433a6a | 1223 | break; |
21515593 RH |
1224 | |
1225 | case TLS_MODEL_INITIAL_EXEC: | |
b15b83fb JJ |
1226 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; |
1227 | addend_hi = addend - addend_lo; | |
1228 | ||
0a81f074 | 1229 | op1 = plus_constant (Pmode, op1, addend_hi); |
5e6c8b64 RH |
1230 | addend = addend_lo; |
1231 | ||
21515593 | 1232 | tmp = gen_reg_rtx (Pmode); |
5e6c8b64 | 1233 | emit_insn (gen_load_tprel (tmp, op1)); |
21515593 | 1234 | |
0d433a6a RH |
1235 | if (!register_operand (op0, Pmode)) |
1236 | op0 = gen_reg_rtx (Pmode); | |
1237 | emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ())); | |
1238 | break; | |
21515593 RH |
1239 | |
1240 | case TLS_MODEL_LOCAL_EXEC: | |
0d433a6a RH |
1241 | if (!register_operand (op0, Pmode)) |
1242 | op0 = gen_reg_rtx (Pmode); | |
5e6c8b64 RH |
1243 | |
1244 | op1 = orig_op1; | |
1245 | addend = 0; | |
21515593 RH |
1246 | if (TARGET_TLS64) |
1247 | { | |
0d433a6a | 1248 | emit_insn (gen_load_tprel (op0, op1)); |
5e6c8b64 | 1249 | emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ())); |
21515593 RH |
1250 | } |
1251 | else | |
5e6c8b64 | 1252 | emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ())); |
0d433a6a | 1253 | break; |
21515593 RH |
1254 | |
1255 | default: | |
e820471b | 1256 | gcc_unreachable (); |
21515593 | 1257 | } |
0d433a6a | 1258 | |
5e6c8b64 RH |
1259 | if (addend) |
1260 | op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend), | |
1261 | orig_op0, 1, OPTAB_DIRECT); | |
0d433a6a RH |
1262 | if (orig_op0 == op0) |
1263 | return NULL_RTX; | |
1264 | if (GET_MODE (orig_op0) == Pmode) | |
1265 | return op0; | |
1266 | return gen_lowpart (GET_MODE (orig_op0), op0); | |
21515593 RH |
1267 | } |
1268 | ||
7b6e506e | 1269 | rtx |
9c808aad | 1270 | ia64_expand_move (rtx op0, rtx op1) |
7b6e506e RH |
1271 | { |
1272 | enum machine_mode mode = GET_MODE (op0); | |
1273 | ||
1274 | if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1)) | |
1275 | op1 = force_reg (mode, op1); | |
1276 | ||
21515593 | 1277 | if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode)) |
7b6e506e | 1278 | { |
5e6c8b64 | 1279 | HOST_WIDE_INT addend = 0; |
7b6e506e | 1280 | enum tls_model tls_kind; |
5e6c8b64 RH |
1281 | rtx sym = op1; |
1282 | ||
1283 | if (GET_CODE (op1) == CONST | |
1284 | && GET_CODE (XEXP (op1, 0)) == PLUS | |
1285 | && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT) | |
1286 | { | |
1287 | addend = INTVAL (XEXP (XEXP (op1, 0), 1)); | |
1288 | sym = XEXP (XEXP (op1, 0), 0); | |
1289 | } | |
1290 | ||
1291 | tls_kind = tls_symbolic_operand_type (sym); | |
1292 | if (tls_kind) | |
b15b83fb | 1293 | return ia64_expand_tls_address (tls_kind, op0, sym, op1, addend); |
5e6c8b64 RH |
1294 | |
1295 | if (any_offset_symbol_operand (sym, mode)) | |
1296 | addend = 0; | |
1297 | else if (aligned_offset_symbol_operand (sym, mode)) | |
1298 | { | |
1299 | HOST_WIDE_INT addend_lo, addend_hi; | |
1300 | ||
1301 | addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000; | |
1302 | addend_hi = addend - addend_lo; | |
1303 | ||
1304 | if (addend_lo != 0) | |
1305 | { | |
0a81f074 | 1306 | op1 = plus_constant (mode, sym, addend_hi); |
5e6c8b64 RH |
1307 | addend = addend_lo; |
1308 | } | |
21e43850 L |
1309 | else |
1310 | addend = 0; | |
5e6c8b64 RH |
1311 | } |
1312 | else | |
1313 | op1 = sym; | |
1314 | ||
1315 | if (reload_completed) | |
1316 | { | |
1317 | /* We really should have taken care of this offset earlier. */ | |
1318 | gcc_assert (addend == 0); | |
1319 | if (ia64_expand_load_address (op0, op1)) | |
1320 | return NULL_RTX; | |
1321 | } | |
21515593 | 1322 | |
5e6c8b64 | 1323 | if (addend) |
7b6e506e | 1324 | { |
b3a13419 | 1325 | rtx subtarget = !can_create_pseudo_p () ? op0 : gen_reg_rtx (mode); |
5e6c8b64 RH |
1326 | |
1327 | emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1)); | |
1328 | ||
1329 | op1 = expand_simple_binop (mode, PLUS, subtarget, | |
1330 | GEN_INT (addend), op0, 1, OPTAB_DIRECT); | |
1331 | if (op0 == op1) | |
1332 | return NULL_RTX; | |
7b6e506e RH |
1333 | } |
1334 | } | |
1335 | ||
1336 | return op1; | |
1337 | } | |
1338 | ||
21515593 RH |
1339 | /* Split a move from OP1 to OP0 conditional on COND. */ |
1340 | ||
1341 | void | |
9c808aad | 1342 | ia64_emit_cond_move (rtx op0, rtx op1, rtx cond) |
21515593 RH |
1343 | { |
1344 | rtx insn, first = get_last_insn (); | |
1345 | ||
1346 | emit_move_insn (op0, op1); | |
1347 | ||
1348 | for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn)) | |
1349 | if (INSN_P (insn)) | |
1350 | PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), | |
1351 | PATTERN (insn)); | |
1352 | } | |
1353 | ||
f57fc998 | 1354 | /* Split a post-reload TImode or TFmode reference into two DImode |
2ffe0e02 ZW |
1355 | components. This is made extra difficult by the fact that we do |
1356 | not get any scratch registers to work with, because reload cannot | |
1357 | be prevented from giving us a scratch that overlaps the register | |
1358 | pair involved. So instead, when addressing memory, we tweak the | |
1359 | pointer register up and back down with POST_INCs. Or up and not | |
1360 | back down when we can get away with it. | |
1361 | ||
1362 | REVERSED is true when the loads must be done in reversed order | |
1363 | (high word first) for correctness. DEAD is true when the pointer | |
1364 | dies with the second insn we generate and therefore the second | |
1365 | address must not carry a postmodify. | |
1366 | ||
1367 | May return an insn which is to be emitted after the moves. */ | |
3f622353 | 1368 | |
f57fc998 | 1369 | static rtx |
2ffe0e02 | 1370 | ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead) |
3f622353 | 1371 | { |
2ffe0e02 ZW |
1372 | rtx fixup = 0; |
1373 | ||
3f622353 RH |
1374 | switch (GET_CODE (in)) |
1375 | { | |
1376 | case REG: | |
2ffe0e02 ZW |
1377 | out[reversed] = gen_rtx_REG (DImode, REGNO (in)); |
1378 | out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1); | |
1379 | break; | |
3f622353 RH |
1380 | |
1381 | case CONST_INT: | |
1382 | case CONST_DOUBLE: | |
2ffe0e02 | 1383 | /* Cannot occur reversed. */ |
e820471b | 1384 | gcc_assert (!reversed); |
2ffe0e02 | 1385 | |
f57fc998 ZW |
1386 | if (GET_MODE (in) != TFmode) |
1387 | split_double (in, &out[0], &out[1]); | |
1388 | else | |
1389 | /* split_double does not understand how to split a TFmode | |
1390 | quantity into a pair of DImode constants. */ | |
1391 | { | |
1392 | REAL_VALUE_TYPE r; | |
1393 | unsigned HOST_WIDE_INT p[2]; | |
1394 | long l[4]; /* TFmode is 128 bits */ | |
1395 | ||
1396 | REAL_VALUE_FROM_CONST_DOUBLE (r, in); | |
1397 | real_to_target (l, &r, TFmode); | |
1398 | ||
1399 | if (FLOAT_WORDS_BIG_ENDIAN) | |
1400 | { | |
1401 | p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1]; | |
1402 | p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3]; | |
1403 | } | |
1404 | else | |
1405 | { | |
9eb578c8 L |
1406 | p[0] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0]; |
1407 | p[1] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2]; | |
f57fc998 ZW |
1408 | } |
1409 | out[0] = GEN_INT (p[0]); | |
1410 | out[1] = GEN_INT (p[1]); | |
1411 | } | |
2ffe0e02 ZW |
1412 | break; |
1413 | ||
1414 | case MEM: | |
1415 | { | |
1416 | rtx base = XEXP (in, 0); | |
1417 | rtx offset; | |
1418 | ||
1419 | switch (GET_CODE (base)) | |
1420 | { | |
1421 | case REG: | |
1422 | if (!reversed) | |
1423 | { | |
1424 | out[0] = adjust_automodify_address | |
1425 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1426 | out[1] = adjust_automodify_address | |
1427 | (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8); | |
1428 | } | |
1429 | else | |
1430 | { | |
1431 | /* Reversal requires a pre-increment, which can only | |
1432 | be done as a separate insn. */ | |
1433 | emit_insn (gen_adddi3 (base, base, GEN_INT (8))); | |
1434 | out[0] = adjust_automodify_address | |
1435 | (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8); | |
1436 | out[1] = adjust_address (in, DImode, 0); | |
1437 | } | |
1438 | break; | |
1439 | ||
1440 | case POST_INC: | |
e820471b NS |
1441 | gcc_assert (!reversed && !dead); |
1442 | ||
2ffe0e02 ZW |
1443 | /* Just do the increment in two steps. */ |
1444 | out[0] = adjust_automodify_address (in, DImode, 0, 0); | |
1445 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1446 | break; | |
1447 | ||
1448 | case POST_DEC: | |
e820471b NS |
1449 | gcc_assert (!reversed && !dead); |
1450 | ||
2ffe0e02 ZW |
1451 | /* Add 8, subtract 24. */ |
1452 | base = XEXP (base, 0); | |
1453 | out[0] = adjust_automodify_address | |
1454 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1455 | out[1] = adjust_automodify_address | |
1456 | (in, DImode, | |
0a81f074 RS |
1457 | gen_rtx_POST_MODIFY (Pmode, base, |
1458 | plus_constant (Pmode, base, -24)), | |
2ffe0e02 ZW |
1459 | 8); |
1460 | break; | |
1461 | ||
1462 | case POST_MODIFY: | |
e820471b NS |
1463 | gcc_assert (!reversed && !dead); |
1464 | ||
2ffe0e02 ZW |
1465 | /* Extract and adjust the modification. This case is |
1466 | trickier than the others, because we might have an | |
1467 | index register, or we might have a combined offset that | |
1468 | doesn't fit a signed 9-bit displacement field. We can | |
1469 | assume the incoming expression is already legitimate. */ | |
1470 | offset = XEXP (base, 1); | |
1471 | base = XEXP (base, 0); | |
1472 | ||
1473 | out[0] = adjust_automodify_address | |
1474 | (in, DImode, gen_rtx_POST_INC (Pmode, base), 0); | |
1475 | ||
1476 | if (GET_CODE (XEXP (offset, 1)) == REG) | |
1477 | { | |
1478 | /* Can't adjust the postmodify to match. Emit the | |
1479 | original, then a separate addition insn. */ | |
1480 | out[1] = adjust_automodify_address (in, DImode, 0, 8); | |
1481 | fixup = gen_adddi3 (base, base, GEN_INT (-8)); | |
1482 | } | |
2ffe0e02 ZW |
1483 | else |
1484 | { | |
e820471b NS |
1485 | gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT); |
1486 | if (INTVAL (XEXP (offset, 1)) < -256 + 8) | |
1487 | { | |
1488 | /* Again the postmodify cannot be made to match, | |
1489 | but in this case it's more efficient to get rid | |
1490 | of the postmodify entirely and fix up with an | |
1491 | add insn. */ | |
1492 | out[1] = adjust_automodify_address (in, DImode, base, 8); | |
1493 | fixup = gen_adddi3 | |
1494 | (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8)); | |
1495 | } | |
1496 | else | |
1497 | { | |
1498 | /* Combined offset still fits in the displacement field. | |
1499 | (We cannot overflow it at the high end.) */ | |
1500 | out[1] = adjust_automodify_address | |
1501 | (in, DImode, gen_rtx_POST_MODIFY | |
1502 | (Pmode, base, gen_rtx_PLUS | |
1503 | (Pmode, base, | |
1504 | GEN_INT (INTVAL (XEXP (offset, 1)) - 8))), | |
1505 | 8); | |
1506 | } | |
2ffe0e02 ZW |
1507 | } |
1508 | break; | |
1509 | ||
1510 | default: | |
e820471b | 1511 | gcc_unreachable (); |
2ffe0e02 ZW |
1512 | } |
1513 | break; | |
1514 | } | |
3f622353 RH |
1515 | |
1516 | default: | |
e820471b | 1517 | gcc_unreachable (); |
3f622353 | 1518 | } |
2ffe0e02 ZW |
1519 | |
1520 | return fixup; | |
3f622353 RH |
1521 | } |
1522 | ||
f57fc998 ZW |
1523 | /* Split a TImode or TFmode move instruction after reload. |
1524 | This is used by *movtf_internal and *movti_internal. */ | |
1525 | void | |
1526 | ia64_split_tmode_move (rtx operands[]) | |
1527 | { | |
2ffe0e02 ZW |
1528 | rtx in[2], out[2], insn; |
1529 | rtx fixup[2]; | |
1530 | bool dead = false; | |
1531 | bool reversed = false; | |
1532 | ||
1533 | /* It is possible for reload to decide to overwrite a pointer with | |
1534 | the value it points to. In that case we have to do the loads in | |
1535 | the appropriate order so that the pointer is not destroyed too | |
1536 | early. Also we must not generate a postmodify for that second | |
6d3f673c KY |
1537 | load, or rws_access_regno will die. And we must not generate a |
1538 | postmodify for the second load if the destination register | |
1539 | overlaps with the base register. */ | |
2ffe0e02 ZW |
1540 | if (GET_CODE (operands[1]) == MEM |
1541 | && reg_overlap_mentioned_p (operands[0], operands[1])) | |
f57fc998 | 1542 | { |
2ffe0e02 ZW |
1543 | rtx base = XEXP (operands[1], 0); |
1544 | while (GET_CODE (base) != REG) | |
1545 | base = XEXP (base, 0); | |
f57fc998 | 1546 | |
2ffe0e02 | 1547 | if (REGNO (base) == REGNO (operands[0])) |
6d3f673c | 1548 | reversed = true; |
2430d1e2 | 1549 | |
6d3f673c KY |
1550 | if (refers_to_regno_p (REGNO (operands[0]), |
1551 | REGNO (operands[0])+2, | |
1552 | base, 0)) | |
2430d1e2 | 1553 | dead = true; |
2ffe0e02 ZW |
1554 | } |
1555 | /* Another reason to do the moves in reversed order is if the first | |
1556 | element of the target register pair is also the second element of | |
1557 | the source register pair. */ | |
1558 | if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG | |
1559 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
1560 | reversed = true; | |
1561 | ||
1562 | fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead); | |
1563 | fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead); | |
1564 | ||
1565 | #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \ | |
1566 | if (GET_CODE (EXP) == MEM \ | |
1567 | && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \ | |
1568 | || GET_CODE (XEXP (EXP, 0)) == POST_INC \ | |
1569 | || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \ | |
bbbbb16a | 1570 | add_reg_note (insn, REG_INC, XEXP (XEXP (EXP, 0), 0)) |
2ffe0e02 ZW |
1571 | |
1572 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0])); | |
1573 | MAYBE_ADD_REG_INC_NOTE (insn, in[0]); | |
1574 | MAYBE_ADD_REG_INC_NOTE (insn, out[0]); | |
1575 | ||
1576 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1])); | |
1577 | MAYBE_ADD_REG_INC_NOTE (insn, in[1]); | |
1578 | MAYBE_ADD_REG_INC_NOTE (insn, out[1]); | |
1579 | ||
1580 | if (fixup[0]) | |
1581 | emit_insn (fixup[0]); | |
1582 | if (fixup[1]) | |
1583 | emit_insn (fixup[1]); | |
1584 | ||
1585 | #undef MAYBE_ADD_REG_INC_NOTE | |
f57fc998 ZW |
1586 | } |
1587 | ||
02befdf4 | 1588 | /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go |
3f622353 RH |
1589 | through memory plus an extra GR scratch register. Except that you can |
1590 | either get the first from SECONDARY_MEMORY_NEEDED or the second from | |
1591 | SECONDARY_RELOAD_CLASS, but not both. | |
1592 | ||
1593 | We got into problems in the first place by allowing a construct like | |
02befdf4 | 1594 | (subreg:XF (reg:TI)), which we got from a union containing a long double. |
f5143c46 | 1595 | This solution attempts to prevent this situation from occurring. When |
3f622353 RH |
1596 | we see something like the above, we spill the inner register to memory. */ |
1597 | ||
4de67c26 JM |
1598 | static rtx |
1599 | spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode) | |
3f622353 RH |
1600 | { |
1601 | if (GET_CODE (in) == SUBREG | |
1602 | && GET_MODE (SUBREG_REG (in)) == TImode | |
1603 | && GET_CODE (SUBREG_REG (in)) == REG) | |
1604 | { | |
9474e8ab | 1605 | rtx memt = assign_stack_temp (TImode, 16); |
68d22aa5 | 1606 | emit_move_insn (memt, SUBREG_REG (in)); |
4de67c26 | 1607 | return adjust_address (memt, mode, 0); |
3f622353 RH |
1608 | } |
1609 | else if (force && GET_CODE (in) == REG) | |
1610 | { | |
9474e8ab | 1611 | rtx memx = assign_stack_temp (mode, 16); |
68d22aa5 RH |
1612 | emit_move_insn (memx, in); |
1613 | return memx; | |
3f622353 | 1614 | } |
3f622353 RH |
1615 | else |
1616 | return in; | |
1617 | } | |
f2f90c63 | 1618 | |
4de67c26 JM |
1619 | /* Expand the movxf or movrf pattern (MODE says which) with the given |
1620 | OPERANDS, returning true if the pattern should then invoke | |
1621 | DONE. */ | |
1622 | ||
1623 | bool | |
1624 | ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[]) | |
1625 | { | |
1626 | rtx op0 = operands[0]; | |
1627 | ||
1628 | if (GET_CODE (op0) == SUBREG) | |
1629 | op0 = SUBREG_REG (op0); | |
1630 | ||
1631 | /* We must support XFmode loads into general registers for stdarg/vararg, | |
1632 | unprototyped calls, and a rare case where a long double is passed as | |
1633 | an argument after a float HFA fills the FP registers. We split them into | |
1634 | DImode loads for convenience. We also need to support XFmode stores | |
1635 | for the last case. This case does not happen for stdarg/vararg routines, | |
1636 | because we do a block store to memory of unnamed arguments. */ | |
1637 | ||
1638 | if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) | |
1639 | { | |
1640 | rtx out[2]; | |
1641 | ||
1642 | /* We're hoping to transform everything that deals with XFmode | |
1643 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1644 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1645 | |
1646 | /* Struct to register can just use TImode instead. */ | |
1647 | if ((GET_CODE (operands[1]) == SUBREG | |
1648 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
1649 | || (GET_CODE (operands[1]) == REG | |
1650 | && GR_REGNO_P (REGNO (operands[1])))) | |
1651 | { | |
1652 | rtx op1 = operands[1]; | |
1653 | ||
1654 | if (GET_CODE (op1) == SUBREG) | |
1655 | op1 = SUBREG_REG (op1); | |
1656 | else | |
1657 | op1 = gen_rtx_REG (TImode, REGNO (op1)); | |
1658 | ||
1659 | emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); | |
1660 | return true; | |
1661 | } | |
1662 | ||
1663 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1664 | { | |
ae4d3291 | 1665 | /* Don't word-swap when reading in the constant. */ |
4de67c26 | 1666 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), |
ae4d3291 JW |
1667 | operand_subword (operands[1], WORDS_BIG_ENDIAN, |
1668 | 0, mode)); | |
4de67c26 | 1669 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), |
ae4d3291 JW |
1670 | operand_subword (operands[1], !WORDS_BIG_ENDIAN, |
1671 | 0, mode)); | |
4de67c26 JM |
1672 | return true; |
1673 | } | |
1674 | ||
1675 | /* If the quantity is in a register not known to be GR, spill it. */ | |
1676 | if (register_operand (operands[1], mode)) | |
1677 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode); | |
1678 | ||
1679 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
1680 | ||
ae4d3291 JW |
1681 | /* Don't word-swap when reading in the value. */ |
1682 | out[0] = gen_rtx_REG (DImode, REGNO (op0)); | |
1683 | out[1] = gen_rtx_REG (DImode, REGNO (op0) + 1); | |
4de67c26 JM |
1684 | |
1685 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); | |
1686 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
1687 | return true; | |
1688 | } | |
1689 | ||
1690 | if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1]))) | |
1691 | { | |
1692 | /* We're hoping to transform everything that deals with XFmode | |
1693 | quantities and GR registers early in the compiler. */ | |
b3a13419 | 1694 | gcc_assert (can_create_pseudo_p ()); |
4de67c26 JM |
1695 | |
1696 | /* Op0 can't be a GR_REG here, as that case is handled above. | |
1697 | If op0 is a register, then we spill op1, so that we now have a | |
1698 | MEM operand. This requires creating an XFmode subreg of a TImode reg | |
1699 | to force the spill. */ | |
1700 | if (register_operand (operands[0], mode)) | |
1701 | { | |
1702 | rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1])); | |
1703 | op1 = gen_rtx_SUBREG (mode, op1, 0); | |
1704 | operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode); | |
1705 | } | |
1706 | ||
1707 | else | |
1708 | { | |
1709 | rtx in[2]; | |
1710 | ||
ae4d3291 JW |
1711 | gcc_assert (GET_CODE (operands[0]) == MEM); |
1712 | ||
1713 | /* Don't word-swap when writing out the value. */ | |
1714 | in[0] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1715 | in[1] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1); | |
4de67c26 JM |
1716 | |
1717 | emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]); | |
1718 | emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]); | |
1719 | return true; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | if (!reload_in_progress && !reload_completed) | |
1724 | { | |
1725 | operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode); | |
1726 | ||
1727 | if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG) | |
1728 | { | |
1729 | rtx memt, memx, in = operands[1]; | |
1730 | if (CONSTANT_P (in)) | |
1731 | in = validize_mem (force_const_mem (mode, in)); | |
1732 | if (GET_CODE (in) == MEM) | |
1733 | memt = adjust_address (in, TImode, 0); | |
1734 | else | |
1735 | { | |
9474e8ab | 1736 | memt = assign_stack_temp (TImode, 16); |
4de67c26 JM |
1737 | memx = adjust_address (memt, mode, 0); |
1738 | emit_move_insn (memx, in); | |
1739 | } | |
1740 | emit_move_insn (op0, memt); | |
1741 | return true; | |
1742 | } | |
1743 | ||
1744 | if (!ia64_move_ok (operands[0], operands[1])) | |
1745 | operands[1] = force_reg (mode, operands[1]); | |
1746 | } | |
1747 | ||
1748 | return false; | |
1749 | } | |
1750 | ||
f90b7a5a PB |
1751 | /* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1 |
1752 | with the expression that holds the compare result (in VOIDmode). */ | |
f2f90c63 | 1753 | |
24ea7948 ZW |
1754 | static GTY(()) rtx cmptf_libfunc; |
1755 | ||
f90b7a5a PB |
1756 | void |
1757 | ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1) | |
f2f90c63 | 1758 | { |
f90b7a5a | 1759 | enum rtx_code code = GET_CODE (*expr); |
f2f90c63 RH |
1760 | rtx cmp; |
1761 | ||
1762 | /* If we have a BImode input, then we already have a compare result, and | |
1763 | do not need to emit another comparison. */ | |
f90b7a5a | 1764 | if (GET_MODE (*op0) == BImode) |
f2f90c63 | 1765 | { |
f90b7a5a PB |
1766 | gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx); |
1767 | cmp = *op0; | |
f2f90c63 | 1768 | } |
24ea7948 ZW |
1769 | /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a |
1770 | magic number as its third argument, that indicates what to do. | |
1771 | The return value is an integer to be compared against zero. */ | |
f90b7a5a | 1772 | else if (TARGET_HPUX && GET_MODE (*op0) == TFmode) |
24ea7948 ZW |
1773 | { |
1774 | enum qfcmp_magic { | |
8fc53a5f | 1775 | QCMP_INV = 1, /* Raise FP_INVALID on NaNs as a side effect. */ |
24ea7948 ZW |
1776 | QCMP_UNORD = 2, |
1777 | QCMP_EQ = 4, | |
1778 | QCMP_LT = 8, | |
1779 | QCMP_GT = 16 | |
32e8bb8e ILT |
1780 | }; |
1781 | int magic; | |
24ea7948 ZW |
1782 | enum rtx_code ncode; |
1783 | rtx ret, insns; | |
e820471b | 1784 | |
f90b7a5a | 1785 | gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode); |
24ea7948 ZW |
1786 | switch (code) |
1787 | { | |
1788 | /* 1 = equal, 0 = not equal. Equality operators do | |
8fc53a5f | 1789 | not raise FP_INVALID when given a NaN operand. */ |
24ea7948 ZW |
1790 | case EQ: magic = QCMP_EQ; ncode = NE; break; |
1791 | case NE: magic = QCMP_EQ; ncode = EQ; break; | |
1792 | /* isunordered() from C99. */ | |
1793 | case UNORDERED: magic = QCMP_UNORD; ncode = NE; break; | |
b1346fa3 | 1794 | case ORDERED: magic = QCMP_UNORD; ncode = EQ; break; |
24ea7948 | 1795 | /* Relational operators raise FP_INVALID when given |
8fc53a5f | 1796 | a NaN operand. */ |
24ea7948 ZW |
1797 | case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break; |
1798 | case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
1799 | case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break; | |
1800 | case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break; | |
8fc53a5f EB |
1801 | /* Unordered relational operators do not raise FP_INVALID |
1802 | when given a NaN operand. */ | |
1803 | case UNLT: magic = QCMP_LT |QCMP_UNORD; ncode = NE; break; | |
1804 | case UNLE: magic = QCMP_LT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1805 | case UNGT: magic = QCMP_GT |QCMP_UNORD; ncode = NE; break; | |
1806 | case UNGE: magic = QCMP_GT|QCMP_EQ|QCMP_UNORD; ncode = NE; break; | |
1807 | /* Not supported. */ | |
1808 | case UNEQ: | |
1809 | case LTGT: | |
e820471b | 1810 | default: gcc_unreachable (); |
24ea7948 ZW |
1811 | } |
1812 | ||
1813 | start_sequence (); | |
1814 | ||
1815 | ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3, | |
f90b7a5a | 1816 | *op0, TFmode, *op1, TFmode, |
24ea7948 ZW |
1817 | GEN_INT (magic), DImode); |
1818 | cmp = gen_reg_rtx (BImode); | |
1819 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
1820 | gen_rtx_fmt_ee (ncode, BImode, | |
1821 | ret, const0_rtx))); | |
1822 | ||
1823 | insns = get_insns (); | |
1824 | end_sequence (); | |
1825 | ||
1826 | emit_libcall_block (insns, cmp, cmp, | |
f90b7a5a | 1827 | gen_rtx_fmt_ee (code, BImode, *op0, *op1)); |
24ea7948 ZW |
1828 | code = NE; |
1829 | } | |
f2f90c63 RH |
1830 | else |
1831 | { | |
1832 | cmp = gen_reg_rtx (BImode); | |
1833 | emit_insn (gen_rtx_SET (VOIDmode, cmp, | |
f90b7a5a | 1834 | gen_rtx_fmt_ee (code, BImode, *op0, *op1))); |
f2f90c63 RH |
1835 | code = NE; |
1836 | } | |
1837 | ||
f90b7a5a PB |
1838 | *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx); |
1839 | *op0 = cmp; | |
1840 | *op1 = const0_rtx; | |
f2f90c63 | 1841 | } |
2ed4af6f | 1842 | |
e934ca47 RH |
1843 | /* Generate an integral vector comparison. Return true if the condition has |
1844 | been reversed, and so the sense of the comparison should be inverted. */ | |
f61134e8 RH |
1845 | |
1846 | static bool | |
1847 | ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode, | |
1848 | rtx dest, rtx op0, rtx op1) | |
1849 | { | |
1850 | bool negate = false; | |
1851 | rtx x; | |
1852 | ||
e934ca47 | 1853 | /* Canonicalize the comparison to EQ, GT, GTU. */ |
f61134e8 RH |
1854 | switch (code) |
1855 | { | |
1856 | case EQ: | |
1857 | case GT: | |
e934ca47 | 1858 | case GTU: |
f61134e8 RH |
1859 | break; |
1860 | ||
1861 | case NE: | |
f61134e8 | 1862 | case LE: |
e934ca47 RH |
1863 | case LEU: |
1864 | code = reverse_condition (code); | |
f61134e8 RH |
1865 | negate = true; |
1866 | break; | |
1867 | ||
1868 | case GE: | |
e934ca47 RH |
1869 | case GEU: |
1870 | code = reverse_condition (code); | |
f61134e8 RH |
1871 | negate = true; |
1872 | /* FALLTHRU */ | |
1873 | ||
1874 | case LT: | |
f61134e8 | 1875 | case LTU: |
e934ca47 RH |
1876 | code = swap_condition (code); |
1877 | x = op0, op0 = op1, op1 = x; | |
1878 | break; | |
f61134e8 | 1879 | |
e934ca47 RH |
1880 | default: |
1881 | gcc_unreachable (); | |
1882 | } | |
f61134e8 | 1883 | |
e934ca47 | 1884 | /* Unsigned parallel compare is not supported by the hardware. Play some |
6283ba26 | 1885 | tricks to turn this into a signed comparison against 0. */ |
e934ca47 RH |
1886 | if (code == GTU) |
1887 | { | |
1888 | switch (mode) | |
1889 | { | |
1890 | case V2SImode: | |
f61134e8 | 1891 | { |
e934ca47 RH |
1892 | rtx t1, t2, mask; |
1893 | ||
9540f5ef SE |
1894 | /* Subtract (-(INT MAX) - 1) from both operands to make |
1895 | them signed. */ | |
1896 | mask = GEN_INT (0x80000000); | |
e934ca47 | 1897 | mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask)); |
9540f5ef SE |
1898 | mask = force_reg (mode, mask); |
1899 | t1 = gen_reg_rtx (mode); | |
1900 | emit_insn (gen_subv2si3 (t1, op0, mask)); | |
1901 | t2 = gen_reg_rtx (mode); | |
1902 | emit_insn (gen_subv2si3 (t2, op1, mask)); | |
1903 | op0 = t1; | |
1904 | op1 = t2; | |
6283ba26 | 1905 | code = GT; |
f61134e8 | 1906 | } |
e934ca47 RH |
1907 | break; |
1908 | ||
1909 | case V8QImode: | |
1910 | case V4HImode: | |
1911 | /* Perform a parallel unsigned saturating subtraction. */ | |
1912 | x = gen_reg_rtx (mode); | |
1913 | emit_insn (gen_rtx_SET (VOIDmode, x, | |
1914 | gen_rtx_US_MINUS (mode, op0, op1))); | |
6283ba26 RH |
1915 | |
1916 | code = EQ; | |
1917 | op0 = x; | |
1918 | op1 = CONST0_RTX (mode); | |
1919 | negate = !negate; | |
e934ca47 RH |
1920 | break; |
1921 | ||
1922 | default: | |
1923 | gcc_unreachable (); | |
1924 | } | |
f61134e8 RH |
1925 | } |
1926 | ||
1927 | x = gen_rtx_fmt_ee (code, mode, op0, op1); | |
1928 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
1929 | ||
1930 | return negate; | |
1931 | } | |
1932 | ||
f61134e8 RH |
1933 | /* Emit an integral vector conditional move. */ |
1934 | ||
1935 | void | |
1936 | ia64_expand_vecint_cmov (rtx operands[]) | |
1937 | { | |
1938 | enum machine_mode mode = GET_MODE (operands[0]); | |
1939 | enum rtx_code code = GET_CODE (operands[3]); | |
1940 | bool negate; | |
1941 | rtx cmp, x, ot, of; | |
1942 | ||
f61134e8 RH |
1943 | cmp = gen_reg_rtx (mode); |
1944 | negate = ia64_expand_vecint_compare (code, mode, cmp, | |
1945 | operands[4], operands[5]); | |
1946 | ||
1947 | ot = operands[1+negate]; | |
1948 | of = operands[2-negate]; | |
1949 | ||
1950 | if (ot == CONST0_RTX (mode)) | |
1951 | { | |
1952 | if (of == CONST0_RTX (mode)) | |
1953 | { | |
1954 | emit_move_insn (operands[0], ot); | |
1955 | return; | |
1956 | } | |
1957 | ||
1958 | x = gen_rtx_NOT (mode, cmp); | |
1959 | x = gen_rtx_AND (mode, x, of); | |
1960 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1961 | } | |
1962 | else if (of == CONST0_RTX (mode)) | |
1963 | { | |
1964 | x = gen_rtx_AND (mode, cmp, ot); | |
1965 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1966 | } | |
1967 | else | |
1968 | { | |
1969 | rtx t, f; | |
1970 | ||
1971 | t = gen_reg_rtx (mode); | |
1972 | x = gen_rtx_AND (mode, cmp, operands[1+negate]); | |
1973 | emit_insn (gen_rtx_SET (VOIDmode, t, x)); | |
1974 | ||
1975 | f = gen_reg_rtx (mode); | |
1976 | x = gen_rtx_NOT (mode, cmp); | |
1977 | x = gen_rtx_AND (mode, x, operands[2-negate]); | |
1978 | emit_insn (gen_rtx_SET (VOIDmode, f, x)); | |
1979 | ||
1980 | x = gen_rtx_IOR (mode, t, f); | |
1981 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1982 | } | |
1983 | } | |
1984 | ||
1985 | /* Emit an integral vector min or max operation. Return true if all done. */ | |
1986 | ||
1987 | bool | |
1988 | ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode, | |
1989 | rtx operands[]) | |
1990 | { | |
cabddb23 | 1991 | rtx xops[6]; |
f61134e8 RH |
1992 | |
1993 | /* These four combinations are supported directly. */ | |
1994 | if (mode == V8QImode && (code == UMIN || code == UMAX)) | |
1995 | return false; | |
1996 | if (mode == V4HImode && (code == SMIN || code == SMAX)) | |
1997 | return false; | |
1998 | ||
93b4080b RH |
1999 | /* This combination can be implemented with only saturating subtraction. */ |
2000 | if (mode == V4HImode && code == UMAX) | |
2001 | { | |
2002 | rtx x, tmp = gen_reg_rtx (mode); | |
2003 | ||
2004 | x = gen_rtx_US_MINUS (mode, operands[1], operands[2]); | |
2005 | emit_insn (gen_rtx_SET (VOIDmode, tmp, x)); | |
2006 | ||
2007 | emit_insn (gen_addv4hi3 (operands[0], tmp, operands[2])); | |
2008 | return true; | |
2009 | } | |
2010 | ||
f61134e8 RH |
2011 | /* Everything else implemented via vector comparisons. */ |
2012 | xops[0] = operands[0]; | |
2013 | xops[4] = xops[1] = operands[1]; | |
2014 | xops[5] = xops[2] = operands[2]; | |
2015 | ||
2016 | switch (code) | |
2017 | { | |
2018 | case UMIN: | |
2019 | code = LTU; | |
2020 | break; | |
2021 | case UMAX: | |
2022 | code = GTU; | |
2023 | break; | |
2024 | case SMIN: | |
2025 | code = LT; | |
2026 | break; | |
2027 | case SMAX: | |
2028 | code = GT; | |
2029 | break; | |
2030 | default: | |
e820471b | 2031 | gcc_unreachable (); |
f61134e8 RH |
2032 | } |
2033 | xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]); | |
2034 | ||
2035 | ia64_expand_vecint_cmov (xops); | |
2036 | return true; | |
2037 | } | |
2038 | ||
55eaaa5b RH |
2039 | /* The vectors LO and HI each contain N halves of a double-wide vector. |
2040 | Reassemble either the first N/2 or the second N/2 elements. */ | |
604e3ff3 RH |
2041 | |
2042 | void | |
55eaaa5b | 2043 | ia64_unpack_assemble (rtx out, rtx lo, rtx hi, bool highp) |
604e3ff3 | 2044 | { |
e6431744 RH |
2045 | enum machine_mode vmode = GET_MODE (lo); |
2046 | unsigned int i, high, nelt = GET_MODE_NUNITS (vmode); | |
2047 | struct expand_vec_perm_d d; | |
2048 | bool ok; | |
604e3ff3 | 2049 | |
e6431744 RH |
2050 | d.target = gen_lowpart (vmode, out); |
2051 | d.op0 = (TARGET_BIG_ENDIAN ? hi : lo); | |
2052 | d.op1 = (TARGET_BIG_ENDIAN ? lo : hi); | |
2053 | d.vmode = vmode; | |
2054 | d.nelt = nelt; | |
2055 | d.one_operand_p = false; | |
2056 | d.testing_p = false; | |
2057 | ||
2058 | high = (highp ? nelt / 2 : 0); | |
2059 | for (i = 0; i < nelt / 2; ++i) | |
604e3ff3 | 2060 | { |
e6431744 RH |
2061 | d.perm[i * 2] = i + high; |
2062 | d.perm[i * 2 + 1] = i + high + nelt; | |
604e3ff3 RH |
2063 | } |
2064 | ||
e6431744 RH |
2065 | ok = ia64_expand_vec_perm_const_1 (&d); |
2066 | gcc_assert (ok); | |
604e3ff3 RH |
2067 | } |
2068 | ||
55eaaa5b | 2069 | /* Return a vector of the sign-extension of VEC. */ |
e898620c | 2070 | |
55eaaa5b RH |
2071 | static rtx |
2072 | ia64_unpack_sign (rtx vec, bool unsignedp) | |
e898620c | 2073 | { |
55eaaa5b RH |
2074 | enum machine_mode mode = GET_MODE (vec); |
2075 | rtx zero = CONST0_RTX (mode); | |
e898620c | 2076 | |
e898620c | 2077 | if (unsignedp) |
55eaaa5b | 2078 | return zero; |
e898620c RH |
2079 | else |
2080 | { | |
55eaaa5b | 2081 | rtx sign = gen_reg_rtx (mode); |
e898620c RH |
2082 | bool neg; |
2083 | ||
55eaaa5b | 2084 | neg = ia64_expand_vecint_compare (LT, mode, sign, vec, zero); |
e898620c | 2085 | gcc_assert (!neg); |
55eaaa5b RH |
2086 | |
2087 | return sign; | |
e898620c | 2088 | } |
55eaaa5b | 2089 | } |
e898620c | 2090 | |
55eaaa5b | 2091 | /* Emit an integral vector unpack operation. */ |
e898620c | 2092 | |
55eaaa5b RH |
2093 | void |
2094 | ia64_expand_unpack (rtx operands[3], bool unsignedp, bool highp) | |
2095 | { | |
2096 | rtx sign = ia64_unpack_sign (operands[1], unsignedp); | |
2097 | ia64_unpack_assemble (operands[0], operands[1], sign, highp); | |
e898620c RH |
2098 | } |
2099 | ||
55eaaa5b RH |
2100 | /* Emit an integral vector widening sum operations. */ |
2101 | ||
604e3ff3 | 2102 | void |
55eaaa5b | 2103 | ia64_expand_widen_sum (rtx operands[3], bool unsignedp) |
604e3ff3 | 2104 | { |
55eaaa5b RH |
2105 | enum machine_mode wmode; |
2106 | rtx l, h, t, sign; | |
604e3ff3 | 2107 | |
55eaaa5b RH |
2108 | sign = ia64_unpack_sign (operands[1], unsignedp); |
2109 | ||
2110 | wmode = GET_MODE (operands[0]); | |
2111 | l = gen_reg_rtx (wmode); | |
2112 | h = gen_reg_rtx (wmode); | |
604e3ff3 | 2113 | |
55eaaa5b RH |
2114 | ia64_unpack_assemble (l, operands[1], sign, false); |
2115 | ia64_unpack_assemble (h, operands[1], sign, true); | |
604e3ff3 | 2116 | |
55eaaa5b RH |
2117 | t = expand_binop (wmode, add_optab, l, operands[2], NULL, 0, OPTAB_DIRECT); |
2118 | t = expand_binop (wmode, add_optab, h, t, operands[0], 0, OPTAB_DIRECT); | |
2119 | if (t != operands[0]) | |
2120 | emit_move_insn (operands[0], t); | |
604e3ff3 RH |
2121 | } |
2122 | ||
2ed4af6f RH |
2123 | /* Emit the appropriate sequence for a call. */ |
2124 | ||
2125 | void | |
9c808aad AJ |
2126 | ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED, |
2127 | int sibcall_p) | |
2ed4af6f | 2128 | { |
599aedd9 | 2129 | rtx insn, b0; |
2ed4af6f RH |
2130 | |
2131 | addr = XEXP (addr, 0); | |
c8083186 | 2132 | addr = convert_memory_address (DImode, addr); |
2ed4af6f | 2133 | b0 = gen_rtx_REG (DImode, R_BR (0)); |
2ed4af6f | 2134 | |
599aedd9 | 2135 | /* ??? Should do this for functions known to bind local too. */ |
2ed4af6f RH |
2136 | if (TARGET_NO_PIC || TARGET_AUTO_PIC) |
2137 | { | |
2138 | if (sibcall_p) | |
599aedd9 | 2139 | insn = gen_sibcall_nogp (addr); |
2ed4af6f | 2140 | else if (! retval) |
599aedd9 | 2141 | insn = gen_call_nogp (addr, b0); |
2ed4af6f | 2142 | else |
599aedd9 RH |
2143 | insn = gen_call_value_nogp (retval, addr, b0); |
2144 | insn = emit_call_insn (insn); | |
2ed4af6f | 2145 | } |
2ed4af6f | 2146 | else |
599aedd9 RH |
2147 | { |
2148 | if (sibcall_p) | |
2149 | insn = gen_sibcall_gp (addr); | |
2150 | else if (! retval) | |
2151 | insn = gen_call_gp (addr, b0); | |
2152 | else | |
2153 | insn = gen_call_value_gp (retval, addr, b0); | |
2154 | insn = emit_call_insn (insn); | |
2ed4af6f | 2155 | |
599aedd9 RH |
2156 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2157 | } | |
6dad5a56 | 2158 | |
599aedd9 | 2159 | if (sibcall_p) |
4e14f1f9 | 2160 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0); |
f2972bf8 DR |
2161 | |
2162 | if (TARGET_ABI_OPEN_VMS) | |
2163 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2164 | gen_rtx_REG (DImode, GR_REG (25))); | |
599aedd9 RH |
2165 | } |
2166 | ||
6fb5fa3c DB |
2167 | static void |
2168 | reg_emitted (enum ia64_frame_regs r) | |
2169 | { | |
2170 | if (emitted_frame_related_regs[r] == 0) | |
2171 | emitted_frame_related_regs[r] = current_frame_info.r[r]; | |
2172 | else | |
2173 | gcc_assert (emitted_frame_related_regs[r] == current_frame_info.r[r]); | |
2174 | } | |
2175 | ||
2176 | static int | |
2177 | get_reg (enum ia64_frame_regs r) | |
2178 | { | |
2179 | reg_emitted (r); | |
2180 | return current_frame_info.r[r]; | |
2181 | } | |
2182 | ||
2183 | static bool | |
2184 | is_emitted (int regno) | |
2185 | { | |
09639a83 | 2186 | unsigned int r; |
6fb5fa3c DB |
2187 | |
2188 | for (r = reg_fp; r < number_of_ia64_frame_regs; r++) | |
2189 | if (emitted_frame_related_regs[r] == regno) | |
2190 | return true; | |
2191 | return false; | |
2192 | } | |
2193 | ||
599aedd9 | 2194 | void |
9c808aad | 2195 | ia64_reload_gp (void) |
599aedd9 RH |
2196 | { |
2197 | rtx tmp; | |
2198 | ||
6fb5fa3c DB |
2199 | if (current_frame_info.r[reg_save_gp]) |
2200 | { | |
2201 | tmp = gen_rtx_REG (DImode, get_reg (reg_save_gp)); | |
2202 | } | |
2ed4af6f | 2203 | else |
599aedd9 RH |
2204 | { |
2205 | HOST_WIDE_INT offset; | |
13f70342 | 2206 | rtx offset_r; |
599aedd9 RH |
2207 | |
2208 | offset = (current_frame_info.spill_cfa_off | |
2209 | + current_frame_info.spill_size); | |
2210 | if (frame_pointer_needed) | |
2211 | { | |
2212 | tmp = hard_frame_pointer_rtx; | |
2213 | offset = -offset; | |
2214 | } | |
2215 | else | |
2216 | { | |
2217 | tmp = stack_pointer_rtx; | |
2218 | offset = current_frame_info.total_size - offset; | |
2219 | } | |
2220 | ||
13f70342 RH |
2221 | offset_r = GEN_INT (offset); |
2222 | if (satisfies_constraint_I (offset_r)) | |
2223 | emit_insn (gen_adddi3 (pic_offset_table_rtx, tmp, offset_r)); | |
599aedd9 RH |
2224 | else |
2225 | { | |
13f70342 | 2226 | emit_move_insn (pic_offset_table_rtx, offset_r); |
599aedd9 RH |
2227 | emit_insn (gen_adddi3 (pic_offset_table_rtx, |
2228 | pic_offset_table_rtx, tmp)); | |
2229 | } | |
2230 | ||
2231 | tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx); | |
2232 | } | |
2233 | ||
2234 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2235 | } | |
2236 | ||
2237 | void | |
9c808aad AJ |
2238 | ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r, |
2239 | rtx scratch_b, int noreturn_p, int sibcall_p) | |
599aedd9 RH |
2240 | { |
2241 | rtx insn; | |
2242 | bool is_desc = false; | |
2243 | ||
2244 | /* If we find we're calling through a register, then we're actually | |
2245 | calling through a descriptor, so load up the values. */ | |
4e14f1f9 | 2246 | if (REG_P (addr) && GR_REGNO_P (REGNO (addr))) |
599aedd9 RH |
2247 | { |
2248 | rtx tmp; | |
2249 | bool addr_dead_p; | |
2250 | ||
2251 | /* ??? We are currently constrained to *not* use peep2, because | |
2a43945f | 2252 | we can legitimately change the global lifetime of the GP |
9c808aad | 2253 | (in the form of killing where previously live). This is |
599aedd9 RH |
2254 | because a call through a descriptor doesn't use the previous |
2255 | value of the GP, while a direct call does, and we do not | |
2256 | commit to either form until the split here. | |
2257 | ||
2258 | That said, this means that we lack precise life info for | |
2259 | whether ADDR is dead after this call. This is not terribly | |
2260 | important, since we can fix things up essentially for free | |
2261 | with the POST_DEC below, but it's nice to not use it when we | |
2262 | can immediately tell it's not necessary. */ | |
2263 | addr_dead_p = ((noreturn_p || sibcall_p | |
2264 | || TEST_HARD_REG_BIT (regs_invalidated_by_call, | |
2265 | REGNO (addr))) | |
2266 | && !FUNCTION_ARG_REGNO_P (REGNO (addr))); | |
2267 | ||
2268 | /* Load the code address into scratch_b. */ | |
2269 | tmp = gen_rtx_POST_INC (Pmode, addr); | |
2270 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2271 | emit_move_insn (scratch_r, tmp); | |
2272 | emit_move_insn (scratch_b, scratch_r); | |
2273 | ||
2274 | /* Load the GP address. If ADDR is not dead here, then we must | |
2275 | revert the change made above via the POST_INCREMENT. */ | |
2276 | if (!addr_dead_p) | |
2277 | tmp = gen_rtx_POST_DEC (Pmode, addr); | |
2278 | else | |
2279 | tmp = addr; | |
2280 | tmp = gen_rtx_MEM (Pmode, tmp); | |
2281 | emit_move_insn (pic_offset_table_rtx, tmp); | |
2282 | ||
2283 | is_desc = true; | |
2284 | addr = scratch_b; | |
2285 | } | |
2ed4af6f | 2286 | |
6dad5a56 | 2287 | if (sibcall_p) |
599aedd9 RH |
2288 | insn = gen_sibcall_nogp (addr); |
2289 | else if (retval) | |
2290 | insn = gen_call_value_nogp (retval, addr, retaddr); | |
6dad5a56 | 2291 | else |
599aedd9 | 2292 | insn = gen_call_nogp (addr, retaddr); |
6dad5a56 | 2293 | emit_call_insn (insn); |
2ed4af6f | 2294 | |
599aedd9 RH |
2295 | if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p) |
2296 | ia64_reload_gp (); | |
2ed4af6f | 2297 | } |
16df4ee6 RH |
2298 | |
2299 | /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically. | |
2300 | ||
2301 | This differs from the generic code in that we know about the zero-extending | |
2302 | properties of cmpxchg, and the zero-extending requirements of ar.ccv. We | |
2303 | also know that ld.acq+cmpxchg.rel equals a full barrier. | |
2304 | ||
2305 | The loop we want to generate looks like | |
2306 | ||
2307 | cmp_reg = mem; | |
2308 | label: | |
2309 | old_reg = cmp_reg; | |
2310 | new_reg = cmp_reg op val; | |
2311 | cmp_reg = compare-and-swap(mem, old_reg, new_reg) | |
2312 | if (cmp_reg != old_reg) | |
2313 | goto label; | |
2314 | ||
2315 | Note that we only do the plain load from memory once. Subsequent | |
2316 | iterations use the value loaded by the compare-and-swap pattern. */ | |
2317 | ||
2318 | void | |
2319 | ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val, | |
28875d67 | 2320 | rtx old_dst, rtx new_dst, enum memmodel model) |
16df4ee6 RH |
2321 | { |
2322 | enum machine_mode mode = GET_MODE (mem); | |
2323 | rtx old_reg, new_reg, cmp_reg, ar_ccv, label; | |
2324 | enum insn_code icode; | |
2325 | ||
2326 | /* Special case for using fetchadd. */ | |
dca13767 JJ |
2327 | if ((mode == SImode || mode == DImode) |
2328 | && (code == PLUS || code == MINUS) | |
2329 | && fetchadd_operand (val, mode)) | |
16df4ee6 | 2330 | { |
dca13767 JJ |
2331 | if (code == MINUS) |
2332 | val = GEN_INT (-INTVAL (val)); | |
2333 | ||
16df4ee6 RH |
2334 | if (!old_dst) |
2335 | old_dst = gen_reg_rtx (mode); | |
2336 | ||
28875d67 RH |
2337 | switch (model) |
2338 | { | |
2339 | case MEMMODEL_ACQ_REL: | |
2340 | case MEMMODEL_SEQ_CST: | |
2341 | emit_insn (gen_memory_barrier ()); | |
2342 | /* FALLTHRU */ | |
2343 | case MEMMODEL_RELAXED: | |
2344 | case MEMMODEL_ACQUIRE: | |
2345 | case MEMMODEL_CONSUME: | |
2346 | if (mode == SImode) | |
2347 | icode = CODE_FOR_fetchadd_acq_si; | |
2348 | else | |
2349 | icode = CODE_FOR_fetchadd_acq_di; | |
2350 | break; | |
2351 | case MEMMODEL_RELEASE: | |
2352 | if (mode == SImode) | |
2353 | icode = CODE_FOR_fetchadd_rel_si; | |
2354 | else | |
2355 | icode = CODE_FOR_fetchadd_rel_di; | |
2356 | break; | |
2357 | ||
2358 | default: | |
2359 | gcc_unreachable (); | |
2360 | } | |
16df4ee6 | 2361 | |
16df4ee6 RH |
2362 | emit_insn (GEN_FCN (icode) (old_dst, mem, val)); |
2363 | ||
2364 | if (new_dst) | |
2365 | { | |
2366 | new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst, | |
2367 | true, OPTAB_WIDEN); | |
2368 | if (new_reg != new_dst) | |
2369 | emit_move_insn (new_dst, new_reg); | |
2370 | } | |
2371 | return; | |
2372 | } | |
2373 | ||
2374 | /* Because of the volatile mem read, we get an ld.acq, which is the | |
28875d67 RH |
2375 | front half of the full barrier. The end half is the cmpxchg.rel. |
2376 | For relaxed and release memory models, we don't need this. But we | |
2377 | also don't bother trying to prevent it either. */ | |
2378 | gcc_assert (model == MEMMODEL_RELAXED | |
2379 | || model == MEMMODEL_RELEASE | |
2380 | || MEM_VOLATILE_P (mem)); | |
16df4ee6 RH |
2381 | |
2382 | old_reg = gen_reg_rtx (DImode); | |
2383 | cmp_reg = gen_reg_rtx (DImode); | |
2384 | label = gen_label_rtx (); | |
2385 | ||
2386 | if (mode != DImode) | |
2387 | { | |
2388 | val = simplify_gen_subreg (DImode, val, mode, 0); | |
2389 | emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1)); | |
2390 | } | |
2391 | else | |
2392 | emit_move_insn (cmp_reg, mem); | |
2393 | ||
2394 | emit_label (label); | |
2395 | ||
2396 | ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM); | |
2397 | emit_move_insn (old_reg, cmp_reg); | |
2398 | emit_move_insn (ar_ccv, cmp_reg); | |
2399 | ||
2400 | if (old_dst) | |
2401 | emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg)); | |
2402 | ||
2403 | new_reg = cmp_reg; | |
2404 | if (code == NOT) | |
2405 | { | |
974920dc UB |
2406 | new_reg = expand_simple_binop (DImode, AND, new_reg, val, NULL_RTX, |
2407 | true, OPTAB_DIRECT); | |
2408 | new_reg = expand_simple_unop (DImode, code, new_reg, NULL_RTX, true); | |
16df4ee6 | 2409 | } |
974920dc UB |
2410 | else |
2411 | new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX, | |
2412 | true, OPTAB_DIRECT); | |
16df4ee6 RH |
2413 | |
2414 | if (mode != DImode) | |
2415 | new_reg = gen_lowpart (mode, new_reg); | |
2416 | if (new_dst) | |
2417 | emit_move_insn (new_dst, new_reg); | |
2418 | ||
28875d67 | 2419 | switch (model) |
16df4ee6 | 2420 | { |
28875d67 RH |
2421 | case MEMMODEL_RELAXED: |
2422 | case MEMMODEL_ACQUIRE: | |
2423 | case MEMMODEL_CONSUME: | |
2424 | switch (mode) | |
2425 | { | |
2426 | case QImode: icode = CODE_FOR_cmpxchg_acq_qi; break; | |
2427 | case HImode: icode = CODE_FOR_cmpxchg_acq_hi; break; | |
2428 | case SImode: icode = CODE_FOR_cmpxchg_acq_si; break; | |
2429 | case DImode: icode = CODE_FOR_cmpxchg_acq_di; break; | |
2430 | default: | |
2431 | gcc_unreachable (); | |
2432 | } | |
2433 | break; | |
2434 | ||
2435 | case MEMMODEL_RELEASE: | |
2436 | case MEMMODEL_ACQ_REL: | |
2437 | case MEMMODEL_SEQ_CST: | |
2438 | switch (mode) | |
2439 | { | |
2440 | case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break; | |
2441 | case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break; | |
2442 | case SImode: icode = CODE_FOR_cmpxchg_rel_si; break; | |
2443 | case DImode: icode = CODE_FOR_cmpxchg_rel_di; break; | |
2444 | default: | |
2445 | gcc_unreachable (); | |
2446 | } | |
2447 | break; | |
2448 | ||
16df4ee6 RH |
2449 | default: |
2450 | gcc_unreachable (); | |
2451 | } | |
2452 | ||
2453 | emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg)); | |
2454 | ||
6819a463 | 2455 | emit_cmp_and_jump_insns (cmp_reg, old_reg, NE, NULL, DImode, true, label); |
16df4ee6 | 2456 | } |
809d4ef1 | 2457 | \f |
3b572406 RH |
2458 | /* Begin the assembly file. */ |
2459 | ||
1bc7c5b6 | 2460 | static void |
9c808aad | 2461 | ia64_file_start (void) |
1bc7c5b6 ZW |
2462 | { |
2463 | default_file_start (); | |
2464 | emit_safe_across_calls (); | |
2465 | } | |
2466 | ||
3b572406 | 2467 | void |
9c808aad | 2468 | emit_safe_across_calls (void) |
3b572406 RH |
2469 | { |
2470 | unsigned int rs, re; | |
2471 | int out_state; | |
2472 | ||
2473 | rs = 1; | |
2474 | out_state = 0; | |
2475 | while (1) | |
2476 | { | |
2477 | while (rs < 64 && call_used_regs[PR_REG (rs)]) | |
2478 | rs++; | |
2479 | if (rs >= 64) | |
2480 | break; | |
2481 | for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++) | |
2482 | continue; | |
2483 | if (out_state == 0) | |
2484 | { | |
1bc7c5b6 | 2485 | fputs ("\t.pred.safe_across_calls ", asm_out_file); |
3b572406 RH |
2486 | out_state = 1; |
2487 | } | |
2488 | else | |
1bc7c5b6 | 2489 | fputc (',', asm_out_file); |
3b572406 | 2490 | if (re == rs + 1) |
1bc7c5b6 | 2491 | fprintf (asm_out_file, "p%u", rs); |
3b572406 | 2492 | else |
1bc7c5b6 | 2493 | fprintf (asm_out_file, "p%u-p%u", rs, re - 1); |
3b572406 RH |
2494 | rs = re + 1; |
2495 | } | |
2496 | if (out_state) | |
1bc7c5b6 | 2497 | fputc ('\n', asm_out_file); |
3b572406 RH |
2498 | } |
2499 | ||
812b587e SE |
2500 | /* Globalize a declaration. */ |
2501 | ||
2502 | static void | |
2503 | ia64_globalize_decl_name (FILE * stream, tree decl) | |
2504 | { | |
2505 | const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
2506 | tree version_attr = lookup_attribute ("version_id", DECL_ATTRIBUTES (decl)); | |
2507 | if (version_attr) | |
2508 | { | |
2509 | tree v = TREE_VALUE (TREE_VALUE (version_attr)); | |
2510 | const char *p = TREE_STRING_POINTER (v); | |
2511 | fprintf (stream, "\t.alias %s#, \"%s{%s}\"\n", name, name, p); | |
2512 | } | |
2513 | targetm.asm_out.globalize_label (stream, name); | |
2514 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2515 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "function"); | |
2516 | } | |
2517 | ||
97e242b0 RH |
2518 | /* Helper function for ia64_compute_frame_size: find an appropriate general |
2519 | register to spill some special register to. SPECIAL_SPILL_MASK contains | |
2520 | bits in GR0 to GR31 that have already been allocated by this routine. | |
2521 | TRY_LOCALS is true if we should attempt to locate a local regnum. */ | |
c65ebc55 | 2522 | |
97e242b0 | 2523 | static int |
6fb5fa3c | 2524 | find_gr_spill (enum ia64_frame_regs r, int try_locals) |
97e242b0 RH |
2525 | { |
2526 | int regno; | |
2527 | ||
6fb5fa3c DB |
2528 | if (emitted_frame_related_regs[r] != 0) |
2529 | { | |
2530 | regno = emitted_frame_related_regs[r]; | |
2951f79b JJ |
2531 | if (regno >= LOC_REG (0) && regno < LOC_REG (80 - frame_pointer_needed) |
2532 | && current_frame_info.n_local_regs < regno - LOC_REG (0) + 1) | |
6fb5fa3c | 2533 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; |
416ff32e | 2534 | else if (crtl->is_leaf |
6fb5fa3c DB |
2535 | && regno >= GR_REG (1) && regno <= GR_REG (31)) |
2536 | current_frame_info.gr_used_mask |= 1 << regno; | |
2537 | ||
2538 | return regno; | |
2539 | } | |
2540 | ||
97e242b0 RH |
2541 | /* If this is a leaf function, first try an otherwise unused |
2542 | call-clobbered register. */ | |
416ff32e | 2543 | if (crtl->is_leaf) |
97e242b0 RH |
2544 | { |
2545 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) | |
6fb5fa3c | 2546 | if (! df_regs_ever_live_p (regno) |
97e242b0 RH |
2547 | && call_used_regs[regno] |
2548 | && ! fixed_regs[regno] | |
2549 | && ! global_regs[regno] | |
6fb5fa3c DB |
2550 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0 |
2551 | && ! is_emitted (regno)) | |
97e242b0 RH |
2552 | { |
2553 | current_frame_info.gr_used_mask |= 1 << regno; | |
2554 | return regno; | |
2555 | } | |
2556 | } | |
2557 | ||
2558 | if (try_locals) | |
2559 | { | |
2560 | regno = current_frame_info.n_local_regs; | |
9502c558 JW |
2561 | /* If there is a frame pointer, then we can't use loc79, because |
2562 | that is HARD_FRAME_POINTER_REGNUM. In particular, see the | |
2563 | reg_name switching code in ia64_expand_prologue. */ | |
2951f79b JJ |
2564 | while (regno < (80 - frame_pointer_needed)) |
2565 | if (! is_emitted (LOC_REG (regno++))) | |
2566 | { | |
2567 | current_frame_info.n_local_regs = regno; | |
2568 | return LOC_REG (regno - 1); | |
2569 | } | |
97e242b0 RH |
2570 | } |
2571 | ||
2572 | /* Failed to find a general register to spill to. Must use stack. */ | |
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | /* In order to make for nice schedules, we try to allocate every temporary | |
2577 | to a different register. We must of course stay away from call-saved, | |
2578 | fixed, and global registers. We must also stay away from registers | |
2579 | allocated in current_frame_info.gr_used_mask, since those include regs | |
2580 | used all through the prologue. | |
2581 | ||
2582 | Any register allocated here must be used immediately. The idea is to | |
2583 | aid scheduling, not to solve data flow problems. */ | |
2584 | ||
2585 | static int last_scratch_gr_reg; | |
2586 | ||
2587 | static int | |
9c808aad | 2588 | next_scratch_gr_reg (void) |
97e242b0 RH |
2589 | { |
2590 | int i, regno; | |
2591 | ||
2592 | for (i = 0; i < 32; ++i) | |
2593 | { | |
2594 | regno = (last_scratch_gr_reg + i + 1) & 31; | |
2595 | if (call_used_regs[regno] | |
2596 | && ! fixed_regs[regno] | |
2597 | && ! global_regs[regno] | |
2598 | && ((current_frame_info.gr_used_mask >> regno) & 1) == 0) | |
2599 | { | |
2600 | last_scratch_gr_reg = regno; | |
2601 | return regno; | |
2602 | } | |
2603 | } | |
2604 | ||
2605 | /* There must be _something_ available. */ | |
e820471b | 2606 | gcc_unreachable (); |
97e242b0 RH |
2607 | } |
2608 | ||
2609 | /* Helper function for ia64_compute_frame_size, called through | |
2610 | diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */ | |
2611 | ||
2612 | static void | |
9c808aad | 2613 | mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED) |
c65ebc55 | 2614 | { |
97e242b0 RH |
2615 | unsigned int regno = REGNO (reg); |
2616 | if (regno < 32) | |
f95e79cc | 2617 | { |
c8b622ff | 2618 | unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)]; |
f95e79cc RH |
2619 | for (i = 0; i < n; ++i) |
2620 | current_frame_info.gr_used_mask |= 1 << (regno + i); | |
2621 | } | |
c65ebc55 JW |
2622 | } |
2623 | ||
6fb5fa3c | 2624 | |
c65ebc55 JW |
2625 | /* Returns the number of bytes offset between the frame pointer and the stack |
2626 | pointer for the current function. SIZE is the number of bytes of space | |
2627 | needed for local variables. */ | |
97e242b0 RH |
2628 | |
2629 | static void | |
9c808aad | 2630 | ia64_compute_frame_size (HOST_WIDE_INT size) |
c65ebc55 | 2631 | { |
97e242b0 RH |
2632 | HOST_WIDE_INT total_size; |
2633 | HOST_WIDE_INT spill_size = 0; | |
2634 | HOST_WIDE_INT extra_spill_size = 0; | |
2635 | HOST_WIDE_INT pretend_args_size; | |
c65ebc55 | 2636 | HARD_REG_SET mask; |
97e242b0 RH |
2637 | int n_spilled = 0; |
2638 | int spilled_gr_p = 0; | |
2639 | int spilled_fr_p = 0; | |
2640 | unsigned int regno; | |
2951f79b JJ |
2641 | int min_regno; |
2642 | int max_regno; | |
97e242b0 | 2643 | int i; |
c65ebc55 | 2644 | |
97e242b0 RH |
2645 | if (current_frame_info.initialized) |
2646 | return; | |
294dac80 | 2647 | |
97e242b0 | 2648 | memset (¤t_frame_info, 0, sizeof current_frame_info); |
c65ebc55 JW |
2649 | CLEAR_HARD_REG_SET (mask); |
2650 | ||
97e242b0 RH |
2651 | /* Don't allocate scratches to the return register. */ |
2652 | diddle_return_value (mark_reg_gr_used_mask, NULL); | |
2653 | ||
2654 | /* Don't allocate scratches to the EH scratch registers. */ | |
2655 | if (cfun->machine->ia64_eh_epilogue_sp) | |
2656 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL); | |
2657 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
2658 | mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL); | |
c65ebc55 | 2659 | |
7b84aac0 EB |
2660 | /* Static stack checking uses r2 and r3. */ |
2661 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) | |
2662 | current_frame_info.gr_used_mask |= 0xc; | |
2663 | ||
97e242b0 RH |
2664 | /* Find the size of the register stack frame. We have only 80 local |
2665 | registers, because we reserve 8 for the inputs and 8 for the | |
2666 | outputs. */ | |
2667 | ||
2668 | /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed, | |
2669 | since we'll be adjusting that down later. */ | |
2670 | regno = LOC_REG (78) + ! frame_pointer_needed; | |
2671 | for (; regno >= LOC_REG (0); regno--) | |
6fb5fa3c | 2672 | if (df_regs_ever_live_p (regno) && !is_emitted (regno)) |
97e242b0 RH |
2673 | break; |
2674 | current_frame_info.n_local_regs = regno - LOC_REG (0) + 1; | |
c65ebc55 | 2675 | |
3f67ac08 DM |
2676 | /* For functions marked with the syscall_linkage attribute, we must mark |
2677 | all eight input registers as in use, so that locals aren't visible to | |
2678 | the caller. */ | |
2679 | ||
2680 | if (cfun->machine->n_varargs > 0 | |
2681 | || lookup_attribute ("syscall_linkage", | |
2682 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
97e242b0 RH |
2683 | current_frame_info.n_input_regs = 8; |
2684 | else | |
2685 | { | |
2686 | for (regno = IN_REG (7); regno >= IN_REG (0); regno--) | |
6fb5fa3c | 2687 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2688 | break; |
2689 | current_frame_info.n_input_regs = regno - IN_REG (0) + 1; | |
2690 | } | |
2691 | ||
2692 | for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--) | |
6fb5fa3c | 2693 | if (df_regs_ever_live_p (regno)) |
97e242b0 RH |
2694 | break; |
2695 | i = regno - OUT_REG (0) + 1; | |
2696 | ||
d26afa4f | 2697 | #ifndef PROFILE_HOOK |
97e242b0 | 2698 | /* When -p profiling, we need one output register for the mcount argument. |
9e4f94de | 2699 | Likewise for -a profiling for the bb_init_func argument. For -ax |
97e242b0 RH |
2700 | profiling, we need two output registers for the two bb_init_trace_func |
2701 | arguments. */ | |
e3b5732b | 2702 | if (crtl->profile) |
97e242b0 | 2703 | i = MAX (i, 1); |
d26afa4f | 2704 | #endif |
97e242b0 RH |
2705 | current_frame_info.n_output_regs = i; |
2706 | ||
2707 | /* ??? No rotating register support yet. */ | |
2708 | current_frame_info.n_rotate_regs = 0; | |
2709 | ||
2710 | /* Discover which registers need spilling, and how much room that | |
9c808aad | 2711 | will take. Begin with floating point and general registers, |
97e242b0 RH |
2712 | which will always wind up on the stack. */ |
2713 | ||
2714 | for (regno = FR_REG (2); regno <= FR_REG (127); regno++) | |
6fb5fa3c | 2715 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2716 | { |
2717 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2718 | spill_size += 16; |
2719 | n_spilled += 1; | |
2720 | spilled_fr_p = 1; | |
c65ebc55 JW |
2721 | } |
2722 | ||
97e242b0 | 2723 | for (regno = GR_REG (1); regno <= GR_REG (31); regno++) |
6fb5fa3c | 2724 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2725 | { |
2726 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2727 | spill_size += 8; |
2728 | n_spilled += 1; | |
2729 | spilled_gr_p = 1; | |
c65ebc55 JW |
2730 | } |
2731 | ||
97e242b0 | 2732 | for (regno = BR_REG (1); regno <= BR_REG (7); regno++) |
6fb5fa3c | 2733 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
c65ebc55 JW |
2734 | { |
2735 | SET_HARD_REG_BIT (mask, regno); | |
97e242b0 RH |
2736 | spill_size += 8; |
2737 | n_spilled += 1; | |
c65ebc55 JW |
2738 | } |
2739 | ||
97e242b0 RH |
2740 | /* Now come all special registers that might get saved in other |
2741 | general registers. */ | |
9c808aad | 2742 | |
97e242b0 RH |
2743 | if (frame_pointer_needed) |
2744 | { | |
6fb5fa3c | 2745 | current_frame_info.r[reg_fp] = find_gr_spill (reg_fp, 1); |
0c35f902 JW |
2746 | /* If we did not get a register, then we take LOC79. This is guaranteed |
2747 | to be free, even if regs_ever_live is already set, because this is | |
2748 | HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs, | |
2749 | as we don't count loc79 above. */ | |
6fb5fa3c | 2750 | if (current_frame_info.r[reg_fp] == 0) |
0c35f902 | 2751 | { |
6fb5fa3c DB |
2752 | current_frame_info.r[reg_fp] = LOC_REG (79); |
2753 | current_frame_info.n_local_regs = LOC_REG (79) - LOC_REG (0) + 1; | |
0c35f902 | 2754 | } |
97e242b0 RH |
2755 | } |
2756 | ||
416ff32e | 2757 | if (! crtl->is_leaf) |
c65ebc55 | 2758 | { |
97e242b0 RH |
2759 | /* Emit a save of BR0 if we call other functions. Do this even |
2760 | if this function doesn't return, as EH depends on this to be | |
2761 | able to unwind the stack. */ | |
2762 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
2763 | ||
6fb5fa3c DB |
2764 | current_frame_info.r[reg_save_b0] = find_gr_spill (reg_save_b0, 1); |
2765 | if (current_frame_info.r[reg_save_b0] == 0) | |
97e242b0 | 2766 | { |
ae1e2d4c | 2767 | extra_spill_size += 8; |
97e242b0 RH |
2768 | n_spilled += 1; |
2769 | } | |
2770 | ||
2771 | /* Similarly for ar.pfs. */ | |
2772 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2773 | current_frame_info.r[reg_save_ar_pfs] = find_gr_spill (reg_save_ar_pfs, 1); |
2774 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
97e242b0 RH |
2775 | { |
2776 | extra_spill_size += 8; | |
2777 | n_spilled += 1; | |
2778 | } | |
599aedd9 RH |
2779 | |
2780 | /* Similarly for gp. Note that if we're calling setjmp, the stacked | |
2781 | registers are clobbered, so we fall back to the stack. */ | |
6fb5fa3c | 2782 | current_frame_info.r[reg_save_gp] |
e3b5732b | 2783 | = (cfun->calls_setjmp ? 0 : find_gr_spill (reg_save_gp, 1)); |
6fb5fa3c | 2784 | if (current_frame_info.r[reg_save_gp] == 0) |
599aedd9 RH |
2785 | { |
2786 | SET_HARD_REG_BIT (mask, GR_REG (1)); | |
2787 | spill_size += 8; | |
2788 | n_spilled += 1; | |
2789 | } | |
c65ebc55 JW |
2790 | } |
2791 | else | |
97e242b0 | 2792 | { |
6fb5fa3c | 2793 | if (df_regs_ever_live_p (BR_REG (0)) && ! call_used_regs[BR_REG (0)]) |
97e242b0 RH |
2794 | { |
2795 | SET_HARD_REG_BIT (mask, BR_REG (0)); | |
ae1e2d4c | 2796 | extra_spill_size += 8; |
97e242b0 RH |
2797 | n_spilled += 1; |
2798 | } | |
f5bdba44 | 2799 | |
6fb5fa3c | 2800 | if (df_regs_ever_live_p (AR_PFS_REGNUM)) |
f5bdba44 RH |
2801 | { |
2802 | SET_HARD_REG_BIT (mask, AR_PFS_REGNUM); | |
6fb5fa3c DB |
2803 | current_frame_info.r[reg_save_ar_pfs] |
2804 | = find_gr_spill (reg_save_ar_pfs, 1); | |
2805 | if (current_frame_info.r[reg_save_ar_pfs] == 0) | |
f5bdba44 RH |
2806 | { |
2807 | extra_spill_size += 8; | |
2808 | n_spilled += 1; | |
2809 | } | |
2810 | } | |
97e242b0 | 2811 | } |
c65ebc55 | 2812 | |
97e242b0 RH |
2813 | /* Unwind descriptor hackery: things are most efficient if we allocate |
2814 | consecutive GR save registers for RP, PFS, FP in that order. However, | |
2815 | it is absolutely critical that FP get the only hard register that's | |
2816 | guaranteed to be free, so we allocated it first. If all three did | |
2817 | happen to be allocated hard regs, and are consecutive, rearrange them | |
6fb5fa3c DB |
2818 | into the preferred order now. |
2819 | ||
2820 | If we have already emitted code for any of those registers, | |
2821 | then it's already too late to change. */ | |
2951f79b JJ |
2822 | min_regno = MIN (current_frame_info.r[reg_fp], |
2823 | MIN (current_frame_info.r[reg_save_b0], | |
2824 | current_frame_info.r[reg_save_ar_pfs])); | |
2825 | max_regno = MAX (current_frame_info.r[reg_fp], | |
2826 | MAX (current_frame_info.r[reg_save_b0], | |
2827 | current_frame_info.r[reg_save_ar_pfs])); | |
2828 | if (min_regno > 0 | |
2829 | && min_regno + 2 == max_regno | |
2830 | && (current_frame_info.r[reg_fp] == min_regno + 1 | |
2831 | || current_frame_info.r[reg_save_b0] == min_regno + 1 | |
2832 | || current_frame_info.r[reg_save_ar_pfs] == min_regno + 1) | |
2833 | && (emitted_frame_related_regs[reg_save_b0] == 0 | |
2834 | || emitted_frame_related_regs[reg_save_b0] == min_regno) | |
2835 | && (emitted_frame_related_regs[reg_save_ar_pfs] == 0 | |
2836 | || emitted_frame_related_regs[reg_save_ar_pfs] == min_regno + 1) | |
2837 | && (emitted_frame_related_regs[reg_fp] == 0 | |
2838 | || emitted_frame_related_regs[reg_fp] == min_regno + 2)) | |
5527bf14 | 2839 | { |
2951f79b JJ |
2840 | current_frame_info.r[reg_save_b0] = min_regno; |
2841 | current_frame_info.r[reg_save_ar_pfs] = min_regno + 1; | |
2842 | current_frame_info.r[reg_fp] = min_regno + 2; | |
5527bf14 RH |
2843 | } |
2844 | ||
97e242b0 RH |
2845 | /* See if we need to store the predicate register block. */ |
2846 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2847 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
97e242b0 RH |
2848 | break; |
2849 | if (regno <= PR_REG (63)) | |
c65ebc55 | 2850 | { |
97e242b0 | 2851 | SET_HARD_REG_BIT (mask, PR_REG (0)); |
6fb5fa3c DB |
2852 | current_frame_info.r[reg_save_pr] = find_gr_spill (reg_save_pr, 1); |
2853 | if (current_frame_info.r[reg_save_pr] == 0) | |
97e242b0 RH |
2854 | { |
2855 | extra_spill_size += 8; | |
2856 | n_spilled += 1; | |
2857 | } | |
2858 | ||
2859 | /* ??? Mark them all as used so that register renaming and such | |
2860 | are free to use them. */ | |
2861 | for (regno = PR_REG (0); regno <= PR_REG (63); regno++) | |
6fb5fa3c | 2862 | df_set_regs_ever_live (regno, true); |
c65ebc55 JW |
2863 | } |
2864 | ||
97e242b0 | 2865 | /* If we're forced to use st8.spill, we're forced to save and restore |
f5bdba44 RH |
2866 | ar.unat as well. The check for existing liveness allows inline asm |
2867 | to touch ar.unat. */ | |
2868 | if (spilled_gr_p || cfun->machine->n_varargs | |
6fb5fa3c | 2869 | || df_regs_ever_live_p (AR_UNAT_REGNUM)) |
97e242b0 | 2870 | { |
6fb5fa3c | 2871 | df_set_regs_ever_live (AR_UNAT_REGNUM, true); |
97e242b0 | 2872 | SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM); |
6fb5fa3c DB |
2873 | current_frame_info.r[reg_save_ar_unat] |
2874 | = find_gr_spill (reg_save_ar_unat, spill_size == 0); | |
2875 | if (current_frame_info.r[reg_save_ar_unat] == 0) | |
97e242b0 RH |
2876 | { |
2877 | extra_spill_size += 8; | |
2878 | n_spilled += 1; | |
2879 | } | |
2880 | } | |
2881 | ||
6fb5fa3c | 2882 | if (df_regs_ever_live_p (AR_LC_REGNUM)) |
97e242b0 RH |
2883 | { |
2884 | SET_HARD_REG_BIT (mask, AR_LC_REGNUM); | |
6fb5fa3c DB |
2885 | current_frame_info.r[reg_save_ar_lc] |
2886 | = find_gr_spill (reg_save_ar_lc, spill_size == 0); | |
2887 | if (current_frame_info.r[reg_save_ar_lc] == 0) | |
97e242b0 RH |
2888 | { |
2889 | extra_spill_size += 8; | |
2890 | n_spilled += 1; | |
2891 | } | |
2892 | } | |
2893 | ||
2894 | /* If we have an odd number of words of pretend arguments written to | |
2895 | the stack, then the FR save area will be unaligned. We round the | |
2896 | size of this area up to keep things 16 byte aligned. */ | |
2897 | if (spilled_fr_p) | |
38173d38 | 2898 | pretend_args_size = IA64_STACK_ALIGN (crtl->args.pretend_args_size); |
97e242b0 | 2899 | else |
38173d38 | 2900 | pretend_args_size = crtl->args.pretend_args_size; |
97e242b0 RH |
2901 | |
2902 | total_size = (spill_size + extra_spill_size + size + pretend_args_size | |
38173d38 | 2903 | + crtl->outgoing_args_size); |
97e242b0 RH |
2904 | total_size = IA64_STACK_ALIGN (total_size); |
2905 | ||
2906 | /* We always use the 16-byte scratch area provided by the caller, but | |
2907 | if we are a leaf function, there's no one to which we need to provide | |
44bd7f65 EB |
2908 | a scratch area. However, if the function allocates dynamic stack space, |
2909 | the dynamic offset is computed early and contains STACK_POINTER_OFFSET, | |
2910 | so we need to cope. */ | |
2911 | if (crtl->is_leaf && !cfun->calls_alloca) | |
97e242b0 RH |
2912 | total_size = MAX (0, total_size - 16); |
2913 | ||
c65ebc55 | 2914 | current_frame_info.total_size = total_size; |
97e242b0 RH |
2915 | current_frame_info.spill_cfa_off = pretend_args_size - 16; |
2916 | current_frame_info.spill_size = spill_size; | |
2917 | current_frame_info.extra_spill_size = extra_spill_size; | |
c65ebc55 | 2918 | COPY_HARD_REG_SET (current_frame_info.mask, mask); |
97e242b0 | 2919 | current_frame_info.n_spilled = n_spilled; |
c65ebc55 | 2920 | current_frame_info.initialized = reload_completed; |
97e242b0 RH |
2921 | } |
2922 | ||
7b5cbb57 AS |
2923 | /* Worker function for TARGET_CAN_ELIMINATE. */ |
2924 | ||
2925 | bool | |
2926 | ia64_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
2927 | { | |
416ff32e | 2928 | return (to == BR_REG (0) ? crtl->is_leaf : true); |
7b5cbb57 AS |
2929 | } |
2930 | ||
97e242b0 RH |
2931 | /* Compute the initial difference between the specified pair of registers. */ |
2932 | ||
2933 | HOST_WIDE_INT | |
9c808aad | 2934 | ia64_initial_elimination_offset (int from, int to) |
97e242b0 RH |
2935 | { |
2936 | HOST_WIDE_INT offset; | |
2937 | ||
2938 | ia64_compute_frame_size (get_frame_size ()); | |
2939 | switch (from) | |
2940 | { | |
2941 | case FRAME_POINTER_REGNUM: | |
e820471b | 2942 | switch (to) |
97e242b0 | 2943 | { |
e820471b | 2944 | case HARD_FRAME_POINTER_REGNUM: |
44bd7f65 EB |
2945 | offset = -current_frame_info.total_size; |
2946 | if (!crtl->is_leaf || cfun->calls_alloca) | |
2947 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
2948 | break; |
2949 | ||
2950 | case STACK_POINTER_REGNUM: | |
44bd7f65 EB |
2951 | offset = 0; |
2952 | if (!crtl->is_leaf || cfun->calls_alloca) | |
2953 | offset += 16 + crtl->outgoing_args_size; | |
e820471b NS |
2954 | break; |
2955 | ||
2956 | default: | |
2957 | gcc_unreachable (); | |
97e242b0 | 2958 | } |
97e242b0 | 2959 | break; |
c65ebc55 | 2960 | |
97e242b0 RH |
2961 | case ARG_POINTER_REGNUM: |
2962 | /* Arguments start above the 16 byte save area, unless stdarg | |
2963 | in which case we store through the 16 byte save area. */ | |
e820471b NS |
2964 | switch (to) |
2965 | { | |
2966 | case HARD_FRAME_POINTER_REGNUM: | |
38173d38 | 2967 | offset = 16 - crtl->args.pretend_args_size; |
e820471b NS |
2968 | break; |
2969 | ||
2970 | case STACK_POINTER_REGNUM: | |
2971 | offset = (current_frame_info.total_size | |
38173d38 | 2972 | + 16 - crtl->args.pretend_args_size); |
e820471b NS |
2973 | break; |
2974 | ||
2975 | default: | |
2976 | gcc_unreachable (); | |
2977 | } | |
97e242b0 RH |
2978 | break; |
2979 | ||
97e242b0 | 2980 | default: |
e820471b | 2981 | gcc_unreachable (); |
97e242b0 RH |
2982 | } |
2983 | ||
2984 | return offset; | |
c65ebc55 JW |
2985 | } |
2986 | ||
97e242b0 RH |
2987 | /* If there are more than a trivial number of register spills, we use |
2988 | two interleaved iterators so that we can get two memory references | |
2989 | per insn group. | |
2990 | ||
2991 | In order to simplify things in the prologue and epilogue expanders, | |
2992 | we use helper functions to fix up the memory references after the | |
2993 | fact with the appropriate offsets to a POST_MODIFY memory mode. | |
2994 | The following data structure tracks the state of the two iterators | |
2995 | while insns are being emitted. */ | |
2996 | ||
2997 | struct spill_fill_data | |
c65ebc55 | 2998 | { |
d6a7951f | 2999 | rtx init_after; /* point at which to emit initializations */ |
97e242b0 RH |
3000 | rtx init_reg[2]; /* initial base register */ |
3001 | rtx iter_reg[2]; /* the iterator registers */ | |
3002 | rtx *prev_addr[2]; /* address of last memory use */ | |
703cf211 | 3003 | rtx prev_insn[2]; /* the insn corresponding to prev_addr */ |
97e242b0 RH |
3004 | HOST_WIDE_INT prev_off[2]; /* last offset */ |
3005 | int n_iter; /* number of iterators in use */ | |
3006 | int next_iter; /* next iterator to use */ | |
3007 | unsigned int save_gr_used_mask; | |
3008 | }; | |
3009 | ||
3010 | static struct spill_fill_data spill_fill_data; | |
c65ebc55 | 3011 | |
97e242b0 | 3012 | static void |
9c808aad | 3013 | setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3014 | { |
3015 | int i; | |
3016 | ||
3017 | spill_fill_data.init_after = get_last_insn (); | |
3018 | spill_fill_data.init_reg[0] = init_reg; | |
3019 | spill_fill_data.init_reg[1] = init_reg; | |
3020 | spill_fill_data.prev_addr[0] = NULL; | |
3021 | spill_fill_data.prev_addr[1] = NULL; | |
703cf211 BS |
3022 | spill_fill_data.prev_insn[0] = NULL; |
3023 | spill_fill_data.prev_insn[1] = NULL; | |
97e242b0 RH |
3024 | spill_fill_data.prev_off[0] = cfa_off; |
3025 | spill_fill_data.prev_off[1] = cfa_off; | |
3026 | spill_fill_data.next_iter = 0; | |
3027 | spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask; | |
3028 | ||
3029 | spill_fill_data.n_iter = 1 + (n_spills > 2); | |
3030 | for (i = 0; i < spill_fill_data.n_iter; ++i) | |
c65ebc55 | 3031 | { |
97e242b0 RH |
3032 | int regno = next_scratch_gr_reg (); |
3033 | spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno); | |
3034 | current_frame_info.gr_used_mask |= 1 << regno; | |
3035 | } | |
3036 | } | |
3037 | ||
3038 | static void | |
9c808aad | 3039 | finish_spill_pointers (void) |
97e242b0 RH |
3040 | { |
3041 | current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask; | |
3042 | } | |
c65ebc55 | 3043 | |
97e242b0 | 3044 | static rtx |
9c808aad | 3045 | spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 RH |
3046 | { |
3047 | int iter = spill_fill_data.next_iter; | |
3048 | HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off; | |
3049 | rtx disp_rtx = GEN_INT (disp); | |
3050 | rtx mem; | |
3051 | ||
3052 | if (spill_fill_data.prev_addr[iter]) | |
3053 | { | |
13f70342 | 3054 | if (satisfies_constraint_N (disp_rtx)) |
703cf211 BS |
3055 | { |
3056 | *spill_fill_data.prev_addr[iter] | |
3057 | = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter], | |
3058 | gen_rtx_PLUS (DImode, | |
3059 | spill_fill_data.iter_reg[iter], | |
3060 | disp_rtx)); | |
bbbbb16a ILT |
3061 | add_reg_note (spill_fill_data.prev_insn[iter], |
3062 | REG_INC, spill_fill_data.iter_reg[iter]); | |
703cf211 | 3063 | } |
c65ebc55 JW |
3064 | else |
3065 | { | |
97e242b0 | 3066 | /* ??? Could use register post_modify for loads. */ |
13f70342 | 3067 | if (!satisfies_constraint_I (disp_rtx)) |
97e242b0 RH |
3068 | { |
3069 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); | |
3070 | emit_move_insn (tmp, disp_rtx); | |
3071 | disp_rtx = tmp; | |
3072 | } | |
3073 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3074 | spill_fill_data.iter_reg[iter], disp_rtx)); | |
c65ebc55 | 3075 | } |
97e242b0 RH |
3076 | } |
3077 | /* Micro-optimization: if we've created a frame pointer, it's at | |
3078 | CFA 0, which may allow the real iterator to be initialized lower, | |
3079 | slightly increasing parallelism. Also, if there are few saves | |
3080 | it may eliminate the iterator entirely. */ | |
3081 | else if (disp == 0 | |
3082 | && spill_fill_data.init_reg[iter] == stack_pointer_rtx | |
3083 | && frame_pointer_needed) | |
3084 | { | |
3085 | mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx); | |
ba4828e0 | 3086 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
97e242b0 RH |
3087 | return mem; |
3088 | } | |
3089 | else | |
3090 | { | |
892a4e60 | 3091 | rtx seq, insn; |
809d4ef1 | 3092 | |
97e242b0 RH |
3093 | if (disp == 0) |
3094 | seq = gen_movdi (spill_fill_data.iter_reg[iter], | |
3095 | spill_fill_data.init_reg[iter]); | |
3096 | else | |
c65ebc55 | 3097 | { |
97e242b0 RH |
3098 | start_sequence (); |
3099 | ||
13f70342 | 3100 | if (!satisfies_constraint_I (disp_rtx)) |
c65ebc55 | 3101 | { |
97e242b0 RH |
3102 | rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ()); |
3103 | emit_move_insn (tmp, disp_rtx); | |
3104 | disp_rtx = tmp; | |
c65ebc55 | 3105 | } |
97e242b0 RH |
3106 | |
3107 | emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter], | |
3108 | spill_fill_data.init_reg[iter], | |
3109 | disp_rtx)); | |
3110 | ||
2f937369 | 3111 | seq = get_insns (); |
97e242b0 | 3112 | end_sequence (); |
c65ebc55 | 3113 | } |
809d4ef1 | 3114 | |
97e242b0 RH |
3115 | /* Careful for being the first insn in a sequence. */ |
3116 | if (spill_fill_data.init_after) | |
892a4e60 | 3117 | insn = emit_insn_after (seq, spill_fill_data.init_after); |
97e242b0 | 3118 | else |
bc08aefe RH |
3119 | { |
3120 | rtx first = get_insns (); | |
3121 | if (first) | |
892a4e60 | 3122 | insn = emit_insn_before (seq, first); |
bc08aefe | 3123 | else |
892a4e60 | 3124 | insn = emit_insn (seq); |
bc08aefe | 3125 | } |
892a4e60 | 3126 | spill_fill_data.init_after = insn; |
97e242b0 | 3127 | } |
c65ebc55 | 3128 | |
97e242b0 | 3129 | mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]); |
c65ebc55 | 3130 | |
97e242b0 RH |
3131 | /* ??? Not all of the spills are for varargs, but some of them are. |
3132 | The rest of the spills belong in an alias set of their own. But | |
3133 | it doesn't actually hurt to include them here. */ | |
ba4828e0 | 3134 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
809d4ef1 | 3135 | |
97e242b0 RH |
3136 | spill_fill_data.prev_addr[iter] = &XEXP (mem, 0); |
3137 | spill_fill_data.prev_off[iter] = cfa_off; | |
c65ebc55 | 3138 | |
97e242b0 RH |
3139 | if (++iter >= spill_fill_data.n_iter) |
3140 | iter = 0; | |
3141 | spill_fill_data.next_iter = iter; | |
c65ebc55 | 3142 | |
97e242b0 RH |
3143 | return mem; |
3144 | } | |
5527bf14 | 3145 | |
97e242b0 | 3146 | static void |
9c808aad AJ |
3147 | do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off, |
3148 | rtx frame_reg) | |
97e242b0 | 3149 | { |
703cf211 | 3150 | int iter = spill_fill_data.next_iter; |
97e242b0 | 3151 | rtx mem, insn; |
5527bf14 | 3152 | |
97e242b0 | 3153 | mem = spill_restore_mem (reg, cfa_off); |
870f9ec0 | 3154 | insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off))); |
703cf211 | 3155 | spill_fill_data.prev_insn[iter] = insn; |
5527bf14 | 3156 | |
97e242b0 RH |
3157 | if (frame_reg) |
3158 | { | |
3159 | rtx base; | |
3160 | HOST_WIDE_INT off; | |
3161 | ||
3162 | RTX_FRAME_RELATED_P (insn) = 1; | |
3163 | ||
9c808aad | 3164 | /* Don't even pretend that the unwind code can intuit its way |
97e242b0 RH |
3165 | through a pair of interleaved post_modify iterators. Just |
3166 | provide the correct answer. */ | |
3167 | ||
3168 | if (frame_pointer_needed) | |
3169 | { | |
3170 | base = hard_frame_pointer_rtx; | |
3171 | off = - cfa_off; | |
5527bf14 | 3172 | } |
97e242b0 RH |
3173 | else |
3174 | { | |
3175 | base = stack_pointer_rtx; | |
3176 | off = current_frame_info.total_size - cfa_off; | |
3177 | } | |
3178 | ||
5c255b57 | 3179 | add_reg_note (insn, REG_CFA_OFFSET, |
bbbbb16a ILT |
3180 | gen_rtx_SET (VOIDmode, |
3181 | gen_rtx_MEM (GET_MODE (reg), | |
0a81f074 RS |
3182 | plus_constant (Pmode, |
3183 | base, off)), | |
bbbbb16a | 3184 | frame_reg)); |
c65ebc55 JW |
3185 | } |
3186 | } | |
3187 | ||
97e242b0 | 3188 | static void |
9c808aad | 3189 | do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off) |
97e242b0 | 3190 | { |
703cf211 BS |
3191 | int iter = spill_fill_data.next_iter; |
3192 | rtx insn; | |
3193 | ||
3194 | insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off), | |
3195 | GEN_INT (cfa_off))); | |
3196 | spill_fill_data.prev_insn[iter] = insn; | |
97e242b0 RH |
3197 | } |
3198 | ||
870f9ec0 RH |
3199 | /* Wrapper functions that discards the CONST_INT spill offset. These |
3200 | exist so that we can give gr_spill/gr_fill the offset they need and | |
9e4f94de | 3201 | use a consistent function interface. */ |
870f9ec0 RH |
3202 | |
3203 | static rtx | |
9c808aad | 3204 | gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3205 | { |
3206 | return gen_movdi (dest, src); | |
3207 | } | |
3208 | ||
3209 | static rtx | |
9c808aad | 3210 | gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3211 | { |
3212 | return gen_fr_spill (dest, src); | |
3213 | } | |
3214 | ||
3215 | static rtx | |
9c808aad | 3216 | gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED) |
870f9ec0 RH |
3217 | { |
3218 | return gen_fr_restore (dest, src); | |
3219 | } | |
c65ebc55 | 3220 | |
7b84aac0 EB |
3221 | #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) |
3222 | ||
3223 | /* See Table 6.2 of the IA-64 Software Developer Manual, Volume 2. */ | |
3224 | #define BACKING_STORE_SIZE(N) ((N) > 0 ? ((N) + (N)/63 + 1) * 8 : 0) | |
3225 | ||
3226 | /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, | |
0dca9cd8 EB |
3227 | inclusive. These are offsets from the current stack pointer. BS_SIZE |
3228 | is the size of the backing store. ??? This clobbers r2 and r3. */ | |
7b84aac0 EB |
3229 | |
3230 | static void | |
0dca9cd8 EB |
3231 | ia64_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size, |
3232 | int bs_size) | |
7b84aac0 | 3233 | { |
7b84aac0 EB |
3234 | rtx r2 = gen_rtx_REG (Pmode, GR_REG (2)); |
3235 | rtx r3 = gen_rtx_REG (Pmode, GR_REG (3)); | |
0dca9cd8 EB |
3236 | rtx p6 = gen_rtx_REG (BImode, PR_REG (6)); |
3237 | ||
3238 | /* On the IA-64 there is a second stack in memory, namely the Backing Store | |
3239 | of the Register Stack Engine. We also need to probe it after checking | |
3240 | that the 2 stacks don't overlap. */ | |
3241 | emit_insn (gen_bsp_value (r3)); | |
3242 | emit_move_insn (r2, GEN_INT (-(first + size))); | |
3243 | ||
3244 | /* Compare current value of BSP and SP registers. */ | |
3245 | emit_insn (gen_rtx_SET (VOIDmode, p6, | |
3246 | gen_rtx_fmt_ee (LTU, BImode, | |
3247 | r3, stack_pointer_rtx))); | |
3248 | ||
3249 | /* Compute the address of the probe for the Backing Store (which grows | |
3250 | towards higher addresses). We probe only at the first offset of | |
3251 | the next page because some OS (eg Linux/ia64) only extend the | |
3252 | backing store when this specific address is hit (but generate a SEGV | |
3253 | on other address). Page size is the worst case (4KB). The reserve | |
3254 | size is at least 4096 - (96 + 2) * 8 = 3312 bytes, which is enough. | |
3255 | Also compute the address of the last probe for the memory stack | |
3256 | (which grows towards lower addresses). */ | |
3257 | emit_insn (gen_rtx_SET (VOIDmode, r3, plus_constant (Pmode, r3, 4095))); | |
3258 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3259 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3260 | ||
3261 | /* Compare them and raise SEGV if the former has topped the latter. */ | |
3262 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3263 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
3264 | gen_rtx_SET (VOIDmode, p6, | |
3265 | gen_rtx_fmt_ee (GEU, BImode, | |
3266 | r3, r2)))); | |
3267 | emit_insn (gen_rtx_SET (VOIDmode, | |
3268 | gen_rtx_ZERO_EXTRACT (DImode, r3, GEN_INT (12), | |
3269 | const0_rtx), | |
3270 | const0_rtx)); | |
3271 | emit_insn (gen_rtx_COND_EXEC (VOIDmode, | |
3272 | gen_rtx_fmt_ee (NE, VOIDmode, p6, const0_rtx), | |
3273 | gen_rtx_TRAP_IF (VOIDmode, const1_rtx, | |
3274 | GEN_INT (11)))); | |
7b84aac0 EB |
3275 | |
3276 | /* Probe the Backing Store if necessary. */ | |
3277 | if (bs_size > 0) | |
3278 | emit_stack_probe (r3); | |
3279 | ||
3280 | /* Probe the memory stack if necessary. */ | |
3281 | if (size == 0) | |
3282 | ; | |
3283 | ||
3284 | /* See if we have a constant small number of probes to generate. If so, | |
3285 | that's the easy case. */ | |
3286 | else if (size <= PROBE_INTERVAL) | |
3287 | emit_stack_probe (r2); | |
3288 | ||
3289 | /* The run-time loop is made up of 8 insns in the generic case while this | |
3290 | compile-time loop is made up of 5+2*(n-2) insns for n # of intervals. */ | |
3291 | else if (size <= 4 * PROBE_INTERVAL) | |
3292 | { | |
3293 | HOST_WIDE_INT i; | |
3294 | ||
3295 | emit_move_insn (r2, GEN_INT (-(first + PROBE_INTERVAL))); | |
3296 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3297 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3298 | emit_stack_probe (r2); | |
3299 | ||
3300 | /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until | |
3301 | it exceeds SIZE. If only two probes are needed, this will not | |
3302 | generate any code. Then probe at FIRST + SIZE. */ | |
3303 | for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) | |
3304 | { | |
3305 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3306 | plus_constant (Pmode, r2, -PROBE_INTERVAL))); |
7b84aac0 EB |
3307 | emit_stack_probe (r2); |
3308 | } | |
3309 | ||
3310 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 | 3311 | plus_constant (Pmode, r2, |
7b84aac0 EB |
3312 | (i - PROBE_INTERVAL) - size))); |
3313 | emit_stack_probe (r2); | |
3314 | } | |
3315 | ||
3316 | /* Otherwise, do the same as above, but in a loop. Note that we must be | |
3317 | extra careful with variables wrapping around because we might be at | |
3318 | the very top (or the very bottom) of the address space and we have | |
3319 | to be able to handle this case properly; in particular, we use an | |
3320 | equality test for the loop condition. */ | |
3321 | else | |
3322 | { | |
3323 | HOST_WIDE_INT rounded_size; | |
3324 | ||
3325 | emit_move_insn (r2, GEN_INT (-first)); | |
3326 | ||
3327 | ||
3328 | /* Step 1: round SIZE to the previous multiple of the interval. */ | |
3329 | ||
3330 | rounded_size = size & -PROBE_INTERVAL; | |
3331 | ||
3332 | ||
3333 | /* Step 2: compute initial and final value of the loop counter. */ | |
3334 | ||
3335 | /* TEST_ADDR = SP + FIRST. */ | |
3336 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
3337 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, r2))); | |
3338 | ||
3339 | /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ | |
3340 | if (rounded_size > (1 << 21)) | |
3341 | { | |
3342 | emit_move_insn (r3, GEN_INT (-rounded_size)); | |
3343 | emit_insn (gen_rtx_SET (VOIDmode, r3, gen_rtx_PLUS (Pmode, r2, r3))); | |
3344 | } | |
3345 | else | |
3346 | emit_insn (gen_rtx_SET (VOIDmode, r3, | |
3347 | gen_rtx_PLUS (Pmode, r2, | |
3348 | GEN_INT (-rounded_size)))); | |
3349 | ||
3350 | ||
3351 | /* Step 3: the loop | |
3352 | ||
3353 | while (TEST_ADDR != LAST_ADDR) | |
3354 | { | |
3355 | TEST_ADDR = TEST_ADDR + PROBE_INTERVAL | |
3356 | probe at TEST_ADDR | |
3357 | } | |
3358 | ||
3359 | probes at FIRST + N * PROBE_INTERVAL for values of N from 1 | |
3360 | until it is equal to ROUNDED_SIZE. */ | |
3361 | ||
3362 | emit_insn (gen_probe_stack_range (r2, r2, r3)); | |
3363 | ||
3364 | ||
3365 | /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time | |
3366 | that SIZE is equal to ROUNDED_SIZE. */ | |
3367 | ||
3368 | /* TEMP = SIZE - ROUNDED_SIZE. */ | |
3369 | if (size != rounded_size) | |
3370 | { | |
3371 | emit_insn (gen_rtx_SET (VOIDmode, r2, | |
f65e3801 TG |
3372 | plus_constant (Pmode, r2, |
3373 | rounded_size - size))); | |
7b84aac0 EB |
3374 | emit_stack_probe (r2); |
3375 | } | |
3376 | } | |
3377 | ||
3378 | /* Make sure nothing is scheduled before we are done. */ | |
3379 | emit_insn (gen_blockage ()); | |
3380 | } | |
3381 | ||
3382 | /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are | |
3383 | absolute addresses. */ | |
3384 | ||
3385 | const char * | |
3386 | output_probe_stack_range (rtx reg1, rtx reg2) | |
3387 | { | |
3388 | static int labelno = 0; | |
3389 | char loop_lab[32], end_lab[32]; | |
3390 | rtx xops[3]; | |
3391 | ||
3392 | ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno); | |
3393 | ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++); | |
3394 | ||
3395 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); | |
3396 | ||
3397 | /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */ | |
3398 | xops[0] = reg1; | |
3399 | xops[1] = reg2; | |
3400 | xops[2] = gen_rtx_REG (BImode, PR_REG (6)); | |
3401 | output_asm_insn ("cmp.eq %2, %I2 = %0, %1", xops); | |
3402 | fprintf (asm_out_file, "\t(%s) br.cond.dpnt ", reg_names [REGNO (xops[2])]); | |
3403 | assemble_name_raw (asm_out_file, end_lab); | |
3404 | fputc ('\n', asm_out_file); | |
3405 | ||
3406 | /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ | |
3407 | xops[1] = GEN_INT (-PROBE_INTERVAL); | |
3408 | output_asm_insn ("addl %0 = %1, %0", xops); | |
3409 | fputs ("\t;;\n", asm_out_file); | |
3410 | ||
3411 | /* Probe at TEST_ADDR and branch. */ | |
3412 | output_asm_insn ("probe.w.fault %0, 0", xops); | |
3413 | fprintf (asm_out_file, "\tbr "); | |
3414 | assemble_name_raw (asm_out_file, loop_lab); | |
3415 | fputc ('\n', asm_out_file); | |
3416 | ||
3417 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab); | |
3418 | ||
3419 | return ""; | |
3420 | } | |
3421 | ||
c65ebc55 JW |
3422 | /* Called after register allocation to add any instructions needed for the |
3423 | prologue. Using a prologue insn is favored compared to putting all of the | |
08c148a8 | 3424 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3425 | to intermix instructions with the saves of the caller saved registers. In |
3426 | some cases, it might be necessary to emit a barrier instruction as the last | |
3427 | insn to prevent such scheduling. | |
3428 | ||
3429 | Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1 | |
97e242b0 RH |
3430 | so that the debug info generation code can handle them properly. |
3431 | ||
073a8998 | 3432 | The register save area is laid out like so: |
97e242b0 RH |
3433 | cfa+16 |
3434 | [ varargs spill area ] | |
3435 | [ fr register spill area ] | |
3436 | [ br register spill area ] | |
3437 | [ ar register spill area ] | |
3438 | [ pr register spill area ] | |
3439 | [ gr register spill area ] */ | |
c65ebc55 JW |
3440 | |
3441 | /* ??? Get inefficient code when the frame size is larger than can fit in an | |
3442 | adds instruction. */ | |
3443 | ||
c65ebc55 | 3444 | void |
9c808aad | 3445 | ia64_expand_prologue (void) |
c65ebc55 | 3446 | { |
97e242b0 RH |
3447 | rtx insn, ar_pfs_save_reg, ar_unat_save_reg; |
3448 | int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs; | |
3449 | rtx reg, alt_reg; | |
3450 | ||
3451 | ia64_compute_frame_size (get_frame_size ()); | |
3452 | last_scratch_gr_reg = 15; | |
3453 | ||
a11e0df4 | 3454 | if (flag_stack_usage_info) |
d3c12306 EB |
3455 | current_function_static_stack_size = current_frame_info.total_size; |
3456 | ||
7b84aac0 | 3457 | if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) |
0dca9cd8 EB |
3458 | { |
3459 | HOST_WIDE_INT size = current_frame_info.total_size; | |
3460 | int bs_size = BACKING_STORE_SIZE (current_frame_info.n_input_regs | |
3461 | + current_frame_info.n_local_regs); | |
3462 | ||
3463 | if (crtl->is_leaf && !cfun->calls_alloca) | |
3464 | { | |
3465 | if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) | |
3466 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, | |
3467 | size - STACK_CHECK_PROTECT, | |
3468 | bs_size); | |
3469 | else if (size + bs_size > STACK_CHECK_PROTECT) | |
3470 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, 0, bs_size); | |
3471 | } | |
3472 | else if (size + bs_size > 0) | |
3473 | ia64_emit_probe_stack_range (STACK_CHECK_PROTECT, size, bs_size); | |
3474 | } | |
7b84aac0 | 3475 | |
6fb5fa3c DB |
3476 | if (dump_file) |
3477 | { | |
3478 | fprintf (dump_file, "ia64 frame related registers " | |
3479 | "recorded in current_frame_info.r[]:\n"); | |
3480 | #define PRINTREG(a) if (current_frame_info.r[a]) \ | |
3481 | fprintf(dump_file, "%s = %d\n", #a, current_frame_info.r[a]) | |
3482 | PRINTREG(reg_fp); | |
3483 | PRINTREG(reg_save_b0); | |
3484 | PRINTREG(reg_save_pr); | |
3485 | PRINTREG(reg_save_ar_pfs); | |
3486 | PRINTREG(reg_save_ar_unat); | |
3487 | PRINTREG(reg_save_ar_lc); | |
3488 | PRINTREG(reg_save_gp); | |
3489 | #undef PRINTREG | |
3490 | } | |
3491 | ||
97e242b0 RH |
3492 | /* If there is no epilogue, then we don't need some prologue insns. |
3493 | We need to avoid emitting the dead prologue insns, because flow | |
3494 | will complain about them. */ | |
c65ebc55 JW |
3495 | if (optimize) |
3496 | { | |
97e242b0 | 3497 | edge e; |
9924d7d8 | 3498 | edge_iterator ei; |
97e242b0 | 3499 | |
fefa31b5 | 3500 | FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) |
c65ebc55 JW |
3501 | if ((e->flags & EDGE_FAKE) == 0 |
3502 | && (e->flags & EDGE_FALLTHRU) != 0) | |
3503 | break; | |
3504 | epilogue_p = (e != NULL); | |
3505 | } | |
3506 | else | |
3507 | epilogue_p = 1; | |
3508 | ||
97e242b0 RH |
3509 | /* Set the local, input, and output register names. We need to do this |
3510 | for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in | |
3511 | half. If we use in/loc/out register names, then we get assembler errors | |
3512 | in crtn.S because there is no alloc insn or regstk directive in there. */ | |
3513 | if (! TARGET_REG_NAMES) | |
3514 | { | |
3515 | int inputs = current_frame_info.n_input_regs; | |
3516 | int locals = current_frame_info.n_local_regs; | |
3517 | int outputs = current_frame_info.n_output_regs; | |
3518 | ||
3519 | for (i = 0; i < inputs; i++) | |
3520 | reg_names[IN_REG (i)] = ia64_reg_numbers[i]; | |
3521 | for (i = 0; i < locals; i++) | |
3522 | reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i]; | |
3523 | for (i = 0; i < outputs; i++) | |
3524 | reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i]; | |
3525 | } | |
c65ebc55 | 3526 | |
97e242b0 RH |
3527 | /* Set the frame pointer register name. The regnum is logically loc79, |
3528 | but of course we'll not have allocated that many locals. Rather than | |
3529 | worrying about renumbering the existing rtxs, we adjust the name. */ | |
9502c558 JW |
3530 | /* ??? This code means that we can never use one local register when |
3531 | there is a frame pointer. loc79 gets wasted in this case, as it is | |
3532 | renamed to a register that will never be used. See also the try_locals | |
3533 | code in find_gr_spill. */ | |
6fb5fa3c | 3534 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
3535 | { |
3536 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
3537 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
3538 | = reg_names[current_frame_info.r[reg_fp]]; |
3539 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
97e242b0 | 3540 | } |
c65ebc55 | 3541 | |
97e242b0 RH |
3542 | /* We don't need an alloc instruction if we've used no outputs or locals. */ |
3543 | if (current_frame_info.n_local_regs == 0 | |
2ed4af6f | 3544 | && current_frame_info.n_output_regs == 0 |
38173d38 | 3545 | && current_frame_info.n_input_regs <= crtl->args.info.int_regs |
f5bdba44 | 3546 | && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
97e242b0 RH |
3547 | { |
3548 | /* If there is no alloc, but there are input registers used, then we | |
3549 | need a .regstk directive. */ | |
3550 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
3551 | ar_pfs_save_reg = NULL_RTX; | |
3552 | } | |
3553 | else | |
3554 | { | |
3555 | current_frame_info.need_regstk = 0; | |
c65ebc55 | 3556 | |
6fb5fa3c DB |
3557 | if (current_frame_info.r[reg_save_ar_pfs]) |
3558 | { | |
3559 | regno = current_frame_info.r[reg_save_ar_pfs]; | |
3560 | reg_emitted (reg_save_ar_pfs); | |
3561 | } | |
97e242b0 RH |
3562 | else |
3563 | regno = next_scratch_gr_reg (); | |
3564 | ar_pfs_save_reg = gen_rtx_REG (DImode, regno); | |
3565 | ||
9c808aad | 3566 | insn = emit_insn (gen_alloc (ar_pfs_save_reg, |
97e242b0 RH |
3567 | GEN_INT (current_frame_info.n_input_regs), |
3568 | GEN_INT (current_frame_info.n_local_regs), | |
3569 | GEN_INT (current_frame_info.n_output_regs), | |
3570 | GEN_INT (current_frame_info.n_rotate_regs))); | |
9f2ff8e5 RH |
3571 | if (current_frame_info.r[reg_save_ar_pfs]) |
3572 | { | |
3573 | RTX_FRAME_RELATED_P (insn) = 1; | |
3574 | add_reg_note (insn, REG_CFA_REGISTER, | |
3575 | gen_rtx_SET (VOIDmode, | |
3576 | ar_pfs_save_reg, | |
3577 | gen_rtx_REG (DImode, AR_PFS_REGNUM))); | |
3578 | } | |
97e242b0 | 3579 | } |
c65ebc55 | 3580 | |
97e242b0 | 3581 | /* Set up frame pointer, stack pointer, and spill iterators. */ |
c65ebc55 | 3582 | |
26a110f5 | 3583 | n_varargs = cfun->machine->n_varargs; |
97e242b0 RH |
3584 | setup_spill_pointers (current_frame_info.n_spilled + n_varargs, |
3585 | stack_pointer_rtx, 0); | |
c65ebc55 | 3586 | |
97e242b0 RH |
3587 | if (frame_pointer_needed) |
3588 | { | |
3589 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
3590 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3591 | |
3592 | /* Force the unwind info to recognize this as defining a new CFA, | |
3593 | rather than some temp register setup. */ | |
3594 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL_RTX); | |
97e242b0 | 3595 | } |
c65ebc55 | 3596 | |
97e242b0 RH |
3597 | if (current_frame_info.total_size != 0) |
3598 | { | |
3599 | rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size); | |
3600 | rtx offset; | |
c65ebc55 | 3601 | |
13f70342 | 3602 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
3603 | offset = frame_size_rtx; |
3604 | else | |
3605 | { | |
3606 | regno = next_scratch_gr_reg (); | |
9c808aad | 3607 | offset = gen_rtx_REG (DImode, regno); |
97e242b0 RH |
3608 | emit_move_insn (offset, frame_size_rtx); |
3609 | } | |
c65ebc55 | 3610 | |
97e242b0 RH |
3611 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, |
3612 | stack_pointer_rtx, offset)); | |
c65ebc55 | 3613 | |
97e242b0 RH |
3614 | if (! frame_pointer_needed) |
3615 | { | |
3616 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
3617 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
3618 | gen_rtx_SET (VOIDmode, | |
3619 | stack_pointer_rtx, | |
3620 | gen_rtx_PLUS (DImode, | |
3621 | stack_pointer_rtx, | |
3622 | frame_size_rtx))); | |
97e242b0 | 3623 | } |
c65ebc55 | 3624 | |
97e242b0 RH |
3625 | /* ??? At this point we must generate a magic insn that appears to |
3626 | modify the stack pointer, the frame pointer, and all spill | |
3627 | iterators. This would allow the most scheduling freedom. For | |
3628 | now, just hard stop. */ | |
3629 | emit_insn (gen_blockage ()); | |
3630 | } | |
c65ebc55 | 3631 | |
97e242b0 RH |
3632 | /* Must copy out ar.unat before doing any integer spills. */ |
3633 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
c65ebc55 | 3634 | { |
6fb5fa3c DB |
3635 | if (current_frame_info.r[reg_save_ar_unat]) |
3636 | { | |
3637 | ar_unat_save_reg | |
3638 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3639 | reg_emitted (reg_save_ar_unat); | |
3640 | } | |
97e242b0 | 3641 | else |
c65ebc55 | 3642 | { |
97e242b0 RH |
3643 | alt_regno = next_scratch_gr_reg (); |
3644 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3645 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
c65ebc55 | 3646 | } |
c65ebc55 | 3647 | |
97e242b0 RH |
3648 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
3649 | insn = emit_move_insn (ar_unat_save_reg, reg); | |
5c255b57 RH |
3650 | if (current_frame_info.r[reg_save_ar_unat]) |
3651 | { | |
3652 | RTX_FRAME_RELATED_P (insn) = 1; | |
3653 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); | |
3654 | } | |
97e242b0 RH |
3655 | |
3656 | /* Even if we're not going to generate an epilogue, we still | |
3657 | need to save the register so that EH works. */ | |
6fb5fa3c | 3658 | if (! epilogue_p && current_frame_info.r[reg_save_ar_unat]) |
d0e82870 | 3659 | emit_insn (gen_prologue_use (ar_unat_save_reg)); |
c65ebc55 JW |
3660 | } |
3661 | else | |
97e242b0 RH |
3662 | ar_unat_save_reg = NULL_RTX; |
3663 | ||
3664 | /* Spill all varargs registers. Do this before spilling any GR registers, | |
3665 | since we want the UNAT bits for the GR registers to override the UNAT | |
3666 | bits from varargs, which we don't care about. */ | |
c65ebc55 | 3667 | |
97e242b0 RH |
3668 | cfa_off = -16; |
3669 | for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno) | |
c65ebc55 | 3670 | { |
97e242b0 | 3671 | reg = gen_rtx_REG (DImode, regno); |
870f9ec0 | 3672 | do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX); |
c65ebc55 | 3673 | } |
c65ebc55 | 3674 | |
97e242b0 RH |
3675 | /* Locate the bottom of the register save area. */ |
3676 | cfa_off = (current_frame_info.spill_cfa_off | |
3677 | + current_frame_info.spill_size | |
3678 | + current_frame_info.extra_spill_size); | |
c65ebc55 | 3679 | |
97e242b0 RH |
3680 | /* Save the predicate register block either in a register or in memory. */ |
3681 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3682 | { | |
3683 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
6fb5fa3c | 3684 | if (current_frame_info.r[reg_save_pr] != 0) |
1ff5b671 | 3685 | { |
6fb5fa3c DB |
3686 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); |
3687 | reg_emitted (reg_save_pr); | |
97e242b0 | 3688 | insn = emit_move_insn (alt_reg, reg); |
1ff5b671 | 3689 | |
97e242b0 RH |
3690 | /* ??? Denote pr spill/fill by a DImode move that modifies all |
3691 | 64 hard registers. */ | |
1ff5b671 | 3692 | RTX_FRAME_RELATED_P (insn) = 1; |
5c255b57 | 3693 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
46327bc5 | 3694 | |
97e242b0 RH |
3695 | /* Even if we're not going to generate an epilogue, we still |
3696 | need to save the register so that EH works. */ | |
3697 | if (! epilogue_p) | |
d0e82870 | 3698 | emit_insn (gen_prologue_use (alt_reg)); |
1ff5b671 JW |
3699 | } |
3700 | else | |
97e242b0 RH |
3701 | { |
3702 | alt_regno = next_scratch_gr_reg (); | |
3703 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3704 | insn = emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3705 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3706 | cfa_off -= 8; |
3707 | } | |
c65ebc55 JW |
3708 | } |
3709 | ||
97e242b0 RH |
3710 | /* Handle AR regs in numerical order. All of them get special handling. */ |
3711 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM) | |
6fb5fa3c | 3712 | && current_frame_info.r[reg_save_ar_unat] == 0) |
c65ebc55 | 3713 | { |
97e242b0 | 3714 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); |
870f9ec0 | 3715 | do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg); |
97e242b0 | 3716 | cfa_off -= 8; |
c65ebc55 | 3717 | } |
97e242b0 RH |
3718 | |
3719 | /* The alloc insn already copied ar.pfs into a general register. The | |
3720 | only thing we have to do now is copy that register to a stack slot | |
3721 | if we'd not allocated a local register for the job. */ | |
f5bdba44 | 3722 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM) |
6fb5fa3c | 3723 | && current_frame_info.r[reg_save_ar_pfs] == 0) |
c65ebc55 | 3724 | { |
97e242b0 | 3725 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
870f9ec0 | 3726 | do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg); |
97e242b0 RH |
3727 | cfa_off -= 8; |
3728 | } | |
3729 | ||
3730 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3731 | { | |
3732 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
6fb5fa3c | 3733 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
97e242b0 | 3734 | { |
6fb5fa3c DB |
3735 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); |
3736 | reg_emitted (reg_save_ar_lc); | |
97e242b0 RH |
3737 | insn = emit_move_insn (alt_reg, reg); |
3738 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 3739 | add_reg_note (insn, REG_CFA_REGISTER, NULL_RTX); |
97e242b0 RH |
3740 | |
3741 | /* Even if we're not going to generate an epilogue, we still | |
3742 | need to save the register so that EH works. */ | |
3743 | if (! epilogue_p) | |
d0e82870 | 3744 | emit_insn (gen_prologue_use (alt_reg)); |
97e242b0 | 3745 | } |
c65ebc55 JW |
3746 | else |
3747 | { | |
97e242b0 RH |
3748 | alt_regno = next_scratch_gr_reg (); |
3749 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3750 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3751 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3752 | cfa_off -= 8; |
3753 | } | |
3754 | } | |
3755 | ||
ae1e2d4c AS |
3756 | /* Save the return pointer. */ |
3757 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3758 | { | |
3759 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
6fb5fa3c | 3760 | if (current_frame_info.r[reg_save_b0] != 0) |
ae1e2d4c | 3761 | { |
6fb5fa3c DB |
3762 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); |
3763 | reg_emitted (reg_save_b0); | |
ae1e2d4c AS |
3764 | insn = emit_move_insn (alt_reg, reg); |
3765 | RTX_FRAME_RELATED_P (insn) = 1; | |
5f740973 RH |
3766 | add_reg_note (insn, REG_CFA_REGISTER, |
3767 | gen_rtx_SET (VOIDmode, alt_reg, pc_rtx)); | |
ae1e2d4c AS |
3768 | |
3769 | /* Even if we're not going to generate an epilogue, we still | |
3770 | need to save the register so that EH works. */ | |
3771 | if (! epilogue_p) | |
3772 | emit_insn (gen_prologue_use (alt_reg)); | |
3773 | } | |
3774 | else | |
3775 | { | |
3776 | alt_regno = next_scratch_gr_reg (); | |
3777 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3778 | emit_move_insn (alt_reg, reg); | |
3779 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); | |
3780 | cfa_off -= 8; | |
3781 | } | |
3782 | } | |
3783 | ||
6fb5fa3c | 3784 | if (current_frame_info.r[reg_save_gp]) |
599aedd9 | 3785 | { |
6fb5fa3c | 3786 | reg_emitted (reg_save_gp); |
599aedd9 | 3787 | insn = emit_move_insn (gen_rtx_REG (DImode, |
6fb5fa3c | 3788 | current_frame_info.r[reg_save_gp]), |
599aedd9 | 3789 | pic_offset_table_rtx); |
599aedd9 RH |
3790 | } |
3791 | ||
97e242b0 | 3792 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3793 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3794 | + current_frame_info.spill_size)); | |
97e242b0 RH |
3795 | |
3796 | /* Spill all general registers. */ | |
3797 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
3798 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3799 | { | |
3800 | reg = gen_rtx_REG (DImode, regno); | |
3801 | do_spill (gen_gr_spill, reg, cfa_off, reg); | |
3802 | cfa_off -= 8; | |
3803 | } | |
3804 | ||
97e242b0 RH |
3805 | /* Spill the rest of the BR registers. */ |
3806 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) | |
3807 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3808 | { | |
3809 | alt_regno = next_scratch_gr_reg (); | |
3810 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3811 | reg = gen_rtx_REG (DImode, regno); | |
3812 | emit_move_insn (alt_reg, reg); | |
870f9ec0 | 3813 | do_spill (gen_movdi_x, alt_reg, cfa_off, reg); |
97e242b0 RH |
3814 | cfa_off -= 8; |
3815 | } | |
3816 | ||
3817 | /* Align the frame and spill all FR registers. */ | |
3818 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
3819 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
3820 | { | |
e820471b | 3821 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 3822 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 3823 | do_spill (gen_fr_spill_x, reg, cfa_off, reg); |
97e242b0 RH |
3824 | cfa_off -= 16; |
3825 | } | |
3826 | ||
e820471b | 3827 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
3828 | |
3829 | finish_spill_pointers (); | |
c65ebc55 JW |
3830 | } |
3831 | ||
8e7745dc DR |
3832 | /* Output the textual info surrounding the prologue. */ |
3833 | ||
3834 | void | |
3835 | ia64_start_function (FILE *file, const char *fnname, | |
3836 | tree decl ATTRIBUTE_UNUSED) | |
3837 | { | |
4b12e93d TG |
3838 | #if TARGET_ABI_OPEN_VMS |
3839 | vms_start_function (fnname); | |
8e7745dc DR |
3840 | #endif |
3841 | ||
3842 | fputs ("\t.proc ", file); | |
3843 | assemble_name (file, fnname); | |
3844 | fputc ('\n', file); | |
3845 | ASM_OUTPUT_LABEL (file, fnname); | |
3846 | } | |
3847 | ||
c65ebc55 | 3848 | /* Called after register allocation to add any instructions needed for the |
5519a4f9 | 3849 | epilogue. Using an epilogue insn is favored compared to putting all of the |
08c148a8 | 3850 | instructions in output_function_prologue(), since it allows the scheduler |
c65ebc55 JW |
3851 | to intermix instructions with the saves of the caller saved registers. In |
3852 | some cases, it might be necessary to emit a barrier instruction as the last | |
3853 | insn to prevent such scheduling. */ | |
3854 | ||
3855 | void | |
9c808aad | 3856 | ia64_expand_epilogue (int sibcall_p) |
c65ebc55 | 3857 | { |
97e242b0 RH |
3858 | rtx insn, reg, alt_reg, ar_unat_save_reg; |
3859 | int regno, alt_regno, cfa_off; | |
3860 | ||
3861 | ia64_compute_frame_size (get_frame_size ()); | |
3862 | ||
3863 | /* If there is a frame pointer, then we use it instead of the stack | |
3864 | pointer, so that the stack pointer does not need to be valid when | |
3865 | the epilogue starts. See EXIT_IGNORE_STACK. */ | |
3866 | if (frame_pointer_needed) | |
3867 | setup_spill_pointers (current_frame_info.n_spilled, | |
3868 | hard_frame_pointer_rtx, 0); | |
3869 | else | |
9c808aad | 3870 | setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx, |
97e242b0 RH |
3871 | current_frame_info.total_size); |
3872 | ||
3873 | if (current_frame_info.total_size != 0) | |
3874 | { | |
3875 | /* ??? At this point we must generate a magic insn that appears to | |
3876 | modify the spill iterators and the frame pointer. This would | |
3877 | allow the most scheduling freedom. For now, just hard stop. */ | |
3878 | emit_insn (gen_blockage ()); | |
3879 | } | |
3880 | ||
3881 | /* Locate the bottom of the register save area. */ | |
3882 | cfa_off = (current_frame_info.spill_cfa_off | |
3883 | + current_frame_info.spill_size | |
3884 | + current_frame_info.extra_spill_size); | |
3885 | ||
3886 | /* Restore the predicate registers. */ | |
3887 | if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0))) | |
3888 | { | |
6fb5fa3c DB |
3889 | if (current_frame_info.r[reg_save_pr] != 0) |
3890 | { | |
3891 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_pr]); | |
3892 | reg_emitted (reg_save_pr); | |
3893 | } | |
97e242b0 RH |
3894 | else |
3895 | { | |
3896 | alt_regno = next_scratch_gr_reg (); | |
3897 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3898 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3899 | cfa_off -= 8; |
3900 | } | |
3901 | reg = gen_rtx_REG (DImode, PR_REG (0)); | |
3902 | emit_move_insn (reg, alt_reg); | |
3903 | } | |
3904 | ||
3905 | /* Restore the application registers. */ | |
3906 | ||
3907 | /* Load the saved unat from the stack, but do not restore it until | |
3908 | after the GRs have been restored. */ | |
3909 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
3910 | { | |
6fb5fa3c DB |
3911 | if (current_frame_info.r[reg_save_ar_unat] != 0) |
3912 | { | |
3913 | ar_unat_save_reg | |
3914 | = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_unat]); | |
3915 | reg_emitted (reg_save_ar_unat); | |
3916 | } | |
97e242b0 RH |
3917 | else |
3918 | { | |
3919 | alt_regno = next_scratch_gr_reg (); | |
3920 | ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno); | |
3921 | current_frame_info.gr_used_mask |= 1 << alt_regno; | |
870f9ec0 | 3922 | do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off); |
97e242b0 RH |
3923 | cfa_off -= 8; |
3924 | } | |
3925 | } | |
3926 | else | |
3927 | ar_unat_save_reg = NULL_RTX; | |
9c808aad | 3928 | |
6fb5fa3c | 3929 | if (current_frame_info.r[reg_save_ar_pfs] != 0) |
97e242b0 | 3930 | { |
6fb5fa3c DB |
3931 | reg_emitted (reg_save_ar_pfs); |
3932 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_pfs]); | |
97e242b0 RH |
3933 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); |
3934 | emit_move_insn (reg, alt_reg); | |
3935 | } | |
4e14f1f9 | 3936 | else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)) |
c65ebc55 | 3937 | { |
97e242b0 RH |
3938 | alt_regno = next_scratch_gr_reg (); |
3939 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3940 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3941 | cfa_off -= 8; |
3942 | reg = gen_rtx_REG (DImode, AR_PFS_REGNUM); | |
3943 | emit_move_insn (reg, alt_reg); | |
3944 | } | |
3945 | ||
3946 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM)) | |
3947 | { | |
6fb5fa3c DB |
3948 | if (current_frame_info.r[reg_save_ar_lc] != 0) |
3949 | { | |
3950 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_ar_lc]); | |
3951 | reg_emitted (reg_save_ar_lc); | |
3952 | } | |
97e242b0 RH |
3953 | else |
3954 | { | |
3955 | alt_regno = next_scratch_gr_reg (); | |
3956 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 3957 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
3958 | cfa_off -= 8; |
3959 | } | |
3960 | reg = gen_rtx_REG (DImode, AR_LC_REGNUM); | |
3961 | emit_move_insn (reg, alt_reg); | |
3962 | } | |
3963 | ||
ae1e2d4c AS |
3964 | /* Restore the return pointer. */ |
3965 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
3966 | { | |
6fb5fa3c DB |
3967 | if (current_frame_info.r[reg_save_b0] != 0) |
3968 | { | |
3969 | alt_reg = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
3970 | reg_emitted (reg_save_b0); | |
3971 | } | |
ae1e2d4c AS |
3972 | else |
3973 | { | |
3974 | alt_regno = next_scratch_gr_reg (); | |
3975 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
3976 | do_restore (gen_movdi_x, alt_reg, cfa_off); | |
3977 | cfa_off -= 8; | |
3978 | } | |
3979 | reg = gen_rtx_REG (DImode, BR_REG (0)); | |
3980 | emit_move_insn (reg, alt_reg); | |
3981 | } | |
3982 | ||
97e242b0 | 3983 | /* We should now be at the base of the gr/br/fr spill area. */ |
e820471b NS |
3984 | gcc_assert (cfa_off == (current_frame_info.spill_cfa_off |
3985 | + current_frame_info.spill_size)); | |
97e242b0 | 3986 | |
599aedd9 RH |
3987 | /* The GP may be stored on the stack in the prologue, but it's |
3988 | never restored in the epilogue. Skip the stack slot. */ | |
3989 | if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1))) | |
3990 | cfa_off -= 8; | |
3991 | ||
97e242b0 | 3992 | /* Restore all general registers. */ |
599aedd9 | 3993 | for (regno = GR_REG (2); regno <= GR_REG (31); ++regno) |
97e242b0 | 3994 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) |
0c96007e | 3995 | { |
97e242b0 RH |
3996 | reg = gen_rtx_REG (DImode, regno); |
3997 | do_restore (gen_gr_restore, reg, cfa_off); | |
3998 | cfa_off -= 8; | |
0c96007e | 3999 | } |
9c808aad | 4000 | |
ae1e2d4c | 4001 | /* Restore the branch registers. */ |
97e242b0 RH |
4002 | for (regno = BR_REG (1); regno <= BR_REG (7); ++regno) |
4003 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
0c96007e | 4004 | { |
97e242b0 RH |
4005 | alt_regno = next_scratch_gr_reg (); |
4006 | alt_reg = gen_rtx_REG (DImode, alt_regno); | |
870f9ec0 | 4007 | do_restore (gen_movdi_x, alt_reg, cfa_off); |
97e242b0 RH |
4008 | cfa_off -= 8; |
4009 | reg = gen_rtx_REG (DImode, regno); | |
4010 | emit_move_insn (reg, alt_reg); | |
4011 | } | |
c65ebc55 | 4012 | |
97e242b0 RH |
4013 | /* Restore floating point registers. */ |
4014 | for (regno = FR_REG (2); regno <= FR_REG (127); ++regno) | |
4015 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4016 | { | |
e820471b | 4017 | gcc_assert (!(cfa_off & 15)); |
02befdf4 | 4018 | reg = gen_rtx_REG (XFmode, regno); |
870f9ec0 | 4019 | do_restore (gen_fr_restore_x, reg, cfa_off); |
97e242b0 | 4020 | cfa_off -= 16; |
0c96007e | 4021 | } |
97e242b0 RH |
4022 | |
4023 | /* Restore ar.unat for real. */ | |
4024 | if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)) | |
4025 | { | |
4026 | reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM); | |
4027 | emit_move_insn (reg, ar_unat_save_reg); | |
c65ebc55 JW |
4028 | } |
4029 | ||
e820471b | 4030 | gcc_assert (cfa_off == current_frame_info.spill_cfa_off); |
97e242b0 RH |
4031 | |
4032 | finish_spill_pointers (); | |
c65ebc55 | 4033 | |
c93646bd JJ |
4034 | if (current_frame_info.total_size |
4035 | || cfun->machine->ia64_eh_epilogue_sp | |
4036 | || frame_pointer_needed) | |
97e242b0 RH |
4037 | { |
4038 | /* ??? At this point we must generate a magic insn that appears to | |
4039 | modify the spill iterators, the stack pointer, and the frame | |
4040 | pointer. This would allow the most scheduling freedom. For now, | |
4041 | just hard stop. */ | |
4042 | emit_insn (gen_blockage ()); | |
4043 | } | |
c65ebc55 | 4044 | |
97e242b0 RH |
4045 | if (cfun->machine->ia64_eh_epilogue_sp) |
4046 | emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp); | |
4047 | else if (frame_pointer_needed) | |
4048 | { | |
4049 | insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); | |
4050 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 | 4051 | add_reg_note (insn, REG_CFA_ADJUST_CFA, NULL); |
97e242b0 RH |
4052 | } |
4053 | else if (current_frame_info.total_size) | |
0c96007e | 4054 | { |
97e242b0 RH |
4055 | rtx offset, frame_size_rtx; |
4056 | ||
4057 | frame_size_rtx = GEN_INT (current_frame_info.total_size); | |
13f70342 | 4058 | if (satisfies_constraint_I (frame_size_rtx)) |
97e242b0 RH |
4059 | offset = frame_size_rtx; |
4060 | else | |
4061 | { | |
4062 | regno = next_scratch_gr_reg (); | |
4063 | offset = gen_rtx_REG (DImode, regno); | |
4064 | emit_move_insn (offset, frame_size_rtx); | |
4065 | } | |
4066 | ||
4067 | insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, | |
4068 | offset)); | |
4069 | ||
4070 | RTX_FRAME_RELATED_P (insn) = 1; | |
5c255b57 RH |
4071 | add_reg_note (insn, REG_CFA_ADJUST_CFA, |
4072 | gen_rtx_SET (VOIDmode, | |
4073 | stack_pointer_rtx, | |
4074 | gen_rtx_PLUS (DImode, | |
4075 | stack_pointer_rtx, | |
4076 | frame_size_rtx))); | |
0c96007e | 4077 | } |
97e242b0 RH |
4078 | |
4079 | if (cfun->machine->ia64_eh_epilogue_bsp) | |
4080 | emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp)); | |
9c808aad | 4081 | |
2ed4af6f RH |
4082 | if (! sibcall_p) |
4083 | emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0)))); | |
25250265 | 4084 | else |
8206fc89 AM |
4085 | { |
4086 | int fp = GR_REG (2); | |
5c255b57 RH |
4087 | /* We need a throw away register here, r0 and r1 are reserved, |
4088 | so r2 is the first available call clobbered register. If | |
4089 | there was a frame_pointer register, we may have swapped the | |
4090 | names of r2 and HARD_FRAME_POINTER_REGNUM, so we have to make | |
4091 | sure we're using the string "r2" when emitting the register | |
4092 | name for the assembler. */ | |
6fb5fa3c DB |
4093 | if (current_frame_info.r[reg_fp] |
4094 | && current_frame_info.r[reg_fp] == GR_REG (2)) | |
8206fc89 AM |
4095 | fp = HARD_FRAME_POINTER_REGNUM; |
4096 | ||
4097 | /* We must emit an alloc to force the input registers to become output | |
4098 | registers. Otherwise, if the callee tries to pass its parameters | |
4099 | through to another call without an intervening alloc, then these | |
4100 | values get lost. */ | |
4101 | /* ??? We don't need to preserve all input registers. We only need to | |
4102 | preserve those input registers used as arguments to the sibling call. | |
4103 | It is unclear how to compute that number here. */ | |
4104 | if (current_frame_info.n_input_regs != 0) | |
a8f5224e DM |
4105 | { |
4106 | rtx n_inputs = GEN_INT (current_frame_info.n_input_regs); | |
c2b40eba | 4107 | |
a8f5224e DM |
4108 | insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp), |
4109 | const0_rtx, const0_rtx, | |
4110 | n_inputs, const0_rtx)); | |
4111 | RTX_FRAME_RELATED_P (insn) = 1; | |
c2b40eba RH |
4112 | |
4113 | /* ??? We need to mark the alloc as frame-related so that it gets | |
4114 | passed into ia64_asm_unwind_emit for ia64-specific unwinding. | |
4115 | But there's nothing dwarf2 related to be done wrt the register | |
4116 | windows. If we do nothing, dwarf2out will abort on the UNSPEC; | |
4117 | the empty parallel means dwarf2out will not see anything. */ | |
4118 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
4119 | gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (0))); | |
a8f5224e | 4120 | } |
8206fc89 | 4121 | } |
c65ebc55 JW |
4122 | } |
4123 | ||
97e242b0 RH |
4124 | /* Return 1 if br.ret can do all the work required to return from a |
4125 | function. */ | |
4126 | ||
4127 | int | |
9c808aad | 4128 | ia64_direct_return (void) |
97e242b0 RH |
4129 | { |
4130 | if (reload_completed && ! frame_pointer_needed) | |
4131 | { | |
4132 | ia64_compute_frame_size (get_frame_size ()); | |
4133 | ||
4134 | return (current_frame_info.total_size == 0 | |
4135 | && current_frame_info.n_spilled == 0 | |
6fb5fa3c DB |
4136 | && current_frame_info.r[reg_save_b0] == 0 |
4137 | && current_frame_info.r[reg_save_pr] == 0 | |
4138 | && current_frame_info.r[reg_save_ar_pfs] == 0 | |
4139 | && current_frame_info.r[reg_save_ar_unat] == 0 | |
4140 | && current_frame_info.r[reg_save_ar_lc] == 0); | |
97e242b0 RH |
4141 | } |
4142 | return 0; | |
4143 | } | |
4144 | ||
af1e5518 RH |
4145 | /* Return the magic cookie that we use to hold the return address |
4146 | during early compilation. */ | |
4147 | ||
4148 | rtx | |
9c808aad | 4149 | ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED) |
af1e5518 RH |
4150 | { |
4151 | if (count != 0) | |
4152 | return NULL; | |
4153 | return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR); | |
4154 | } | |
4155 | ||
4156 | /* Split this value after reload, now that we know where the return | |
4157 | address is saved. */ | |
4158 | ||
4159 | void | |
9c808aad | 4160 | ia64_split_return_addr_rtx (rtx dest) |
af1e5518 RH |
4161 | { |
4162 | rtx src; | |
4163 | ||
4164 | if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0))) | |
4165 | { | |
6fb5fa3c DB |
4166 | if (current_frame_info.r[reg_save_b0] != 0) |
4167 | { | |
4168 | src = gen_rtx_REG (DImode, current_frame_info.r[reg_save_b0]); | |
4169 | reg_emitted (reg_save_b0); | |
4170 | } | |
af1e5518 RH |
4171 | else |
4172 | { | |
4173 | HOST_WIDE_INT off; | |
4174 | unsigned int regno; | |
13f70342 | 4175 | rtx off_r; |
af1e5518 RH |
4176 | |
4177 | /* Compute offset from CFA for BR0. */ | |
4178 | /* ??? Must be kept in sync with ia64_expand_prologue. */ | |
4179 | off = (current_frame_info.spill_cfa_off | |
4180 | + current_frame_info.spill_size); | |
4181 | for (regno = GR_REG (1); regno <= GR_REG (31); ++regno) | |
4182 | if (TEST_HARD_REG_BIT (current_frame_info.mask, regno)) | |
4183 | off -= 8; | |
4184 | ||
4185 | /* Convert CFA offset to a register based offset. */ | |
4186 | if (frame_pointer_needed) | |
4187 | src = hard_frame_pointer_rtx; | |
4188 | else | |
4189 | { | |
4190 | src = stack_pointer_rtx; | |
4191 | off += current_frame_info.total_size; | |
4192 | } | |
4193 | ||
4194 | /* Load address into scratch register. */ | |
13f70342 RH |
4195 | off_r = GEN_INT (off); |
4196 | if (satisfies_constraint_I (off_r)) | |
4197 | emit_insn (gen_adddi3 (dest, src, off_r)); | |
af1e5518 RH |
4198 | else |
4199 | { | |
13f70342 | 4200 | emit_move_insn (dest, off_r); |
af1e5518 RH |
4201 | emit_insn (gen_adddi3 (dest, src, dest)); |
4202 | } | |
4203 | ||
4204 | src = gen_rtx_MEM (Pmode, dest); | |
4205 | } | |
4206 | } | |
4207 | else | |
4208 | src = gen_rtx_REG (DImode, BR_REG (0)); | |
4209 | ||
4210 | emit_move_insn (dest, src); | |
4211 | } | |
4212 | ||
10c9f189 | 4213 | int |
9c808aad | 4214 | ia64_hard_regno_rename_ok (int from, int to) |
10c9f189 RH |
4215 | { |
4216 | /* Don't clobber any of the registers we reserved for the prologue. */ | |
09639a83 | 4217 | unsigned int r; |
10c9f189 | 4218 | |
6fb5fa3c DB |
4219 | for (r = reg_fp; r <= reg_save_ar_lc; r++) |
4220 | if (to == current_frame_info.r[r] | |
4221 | || from == current_frame_info.r[r] | |
4222 | || to == emitted_frame_related_regs[r] | |
4223 | || from == emitted_frame_related_regs[r]) | |
4224 | return 0; | |
2130b7fb | 4225 | |
10c9f189 RH |
4226 | /* Don't use output registers outside the register frame. */ |
4227 | if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs)) | |
4228 | return 0; | |
4229 | ||
4230 | /* Retain even/oddness on predicate register pairs. */ | |
4231 | if (PR_REGNO_P (from) && PR_REGNO_P (to)) | |
4232 | return (from & 1) == (to & 1); | |
4233 | ||
4234 | return 1; | |
4235 | } | |
4236 | ||
301d03af RS |
4237 | /* Target hook for assembling integer objects. Handle word-sized |
4238 | aligned objects and detect the cases when @fptr is needed. */ | |
4239 | ||
4240 | static bool | |
9c808aad | 4241 | ia64_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 4242 | { |
b6a41a62 | 4243 | if (size == POINTER_SIZE / BITS_PER_UNIT |
301d03af RS |
4244 | && !(TARGET_NO_PIC || TARGET_AUTO_PIC) |
4245 | && GET_CODE (x) == SYMBOL_REF | |
1cdbd630 | 4246 | && SYMBOL_REF_FUNCTION_P (x)) |
301d03af | 4247 | { |
1b79dc38 DM |
4248 | static const char * const directive[2][2] = { |
4249 | /* 64-bit pointer */ /* 32-bit pointer */ | |
4250 | { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */ | |
4251 | { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */ | |
4252 | }; | |
4253 | fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file); | |
301d03af RS |
4254 | output_addr_const (asm_out_file, x); |
4255 | fputs (")\n", asm_out_file); | |
4256 | return true; | |
4257 | } | |
4258 | return default_assemble_integer (x, size, aligned_p); | |
4259 | } | |
4260 | ||
c65ebc55 JW |
4261 | /* Emit the function prologue. */ |
4262 | ||
08c148a8 | 4263 | static void |
9c808aad | 4264 | ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
c65ebc55 | 4265 | { |
97e242b0 RH |
4266 | int mask, grsave, grsave_prev; |
4267 | ||
4268 | if (current_frame_info.need_regstk) | |
4269 | fprintf (file, "\t.regstk %d, %d, %d, %d\n", | |
4270 | current_frame_info.n_input_regs, | |
4271 | current_frame_info.n_local_regs, | |
4272 | current_frame_info.n_output_regs, | |
4273 | current_frame_info.n_rotate_regs); | |
c65ebc55 | 4274 | |
d5fabb58 | 4275 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0c96007e AM |
4276 | return; |
4277 | ||
97e242b0 | 4278 | /* Emit the .prologue directive. */ |
809d4ef1 | 4279 | |
97e242b0 RH |
4280 | mask = 0; |
4281 | grsave = grsave_prev = 0; | |
6fb5fa3c | 4282 | if (current_frame_info.r[reg_save_b0] != 0) |
0c96007e | 4283 | { |
97e242b0 | 4284 | mask |= 8; |
6fb5fa3c | 4285 | grsave = grsave_prev = current_frame_info.r[reg_save_b0]; |
97e242b0 | 4286 | } |
6fb5fa3c | 4287 | if (current_frame_info.r[reg_save_ar_pfs] != 0 |
97e242b0 | 4288 | && (grsave_prev == 0 |
6fb5fa3c | 4289 | || current_frame_info.r[reg_save_ar_pfs] == grsave_prev + 1)) |
97e242b0 RH |
4290 | { |
4291 | mask |= 4; | |
4292 | if (grsave_prev == 0) | |
6fb5fa3c DB |
4293 | grsave = current_frame_info.r[reg_save_ar_pfs]; |
4294 | grsave_prev = current_frame_info.r[reg_save_ar_pfs]; | |
0c96007e | 4295 | } |
6fb5fa3c | 4296 | if (current_frame_info.r[reg_fp] != 0 |
97e242b0 | 4297 | && (grsave_prev == 0 |
6fb5fa3c | 4298 | || current_frame_info.r[reg_fp] == grsave_prev + 1)) |
97e242b0 RH |
4299 | { |
4300 | mask |= 2; | |
4301 | if (grsave_prev == 0) | |
4302 | grsave = HARD_FRAME_POINTER_REGNUM; | |
6fb5fa3c | 4303 | grsave_prev = current_frame_info.r[reg_fp]; |
97e242b0 | 4304 | } |
6fb5fa3c | 4305 | if (current_frame_info.r[reg_save_pr] != 0 |
97e242b0 | 4306 | && (grsave_prev == 0 |
6fb5fa3c | 4307 | || current_frame_info.r[reg_save_pr] == grsave_prev + 1)) |
97e242b0 RH |
4308 | { |
4309 | mask |= 1; | |
4310 | if (grsave_prev == 0) | |
6fb5fa3c | 4311 | grsave = current_frame_info.r[reg_save_pr]; |
97e242b0 RH |
4312 | } |
4313 | ||
738e7b39 | 4314 | if (mask && TARGET_GNU_AS) |
97e242b0 RH |
4315 | fprintf (file, "\t.prologue %d, %d\n", mask, |
4316 | ia64_dbx_register_number (grsave)); | |
4317 | else | |
4318 | fputs ("\t.prologue\n", file); | |
4319 | ||
4320 | /* Emit a .spill directive, if necessary, to relocate the base of | |
4321 | the register spill area. */ | |
4322 | if (current_frame_info.spill_cfa_off != -16) | |
4323 | fprintf (file, "\t.spill %ld\n", | |
4324 | (long) (current_frame_info.spill_cfa_off | |
4325 | + current_frame_info.spill_size)); | |
c65ebc55 JW |
4326 | } |
4327 | ||
0186257f JW |
4328 | /* Emit the .body directive at the scheduled end of the prologue. */ |
4329 | ||
b4c25db2 | 4330 | static void |
9c808aad | 4331 | ia64_output_function_end_prologue (FILE *file) |
0186257f | 4332 | { |
d5fabb58 | 4333 | if (ia64_except_unwind_info (&global_options) != UI_TARGET) |
0186257f JW |
4334 | return; |
4335 | ||
4336 | fputs ("\t.body\n", file); | |
4337 | } | |
4338 | ||
c65ebc55 JW |
4339 | /* Emit the function epilogue. */ |
4340 | ||
08c148a8 | 4341 | static void |
9c808aad AJ |
4342 | ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
4343 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
c65ebc55 | 4344 | { |
8a959ea5 RH |
4345 | int i; |
4346 | ||
6fb5fa3c | 4347 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4348 | { |
4349 | const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM]; | |
4350 | reg_names[HARD_FRAME_POINTER_REGNUM] | |
6fb5fa3c DB |
4351 | = reg_names[current_frame_info.r[reg_fp]]; |
4352 | reg_names[current_frame_info.r[reg_fp]] = tmp; | |
4353 | reg_emitted (reg_fp); | |
97e242b0 RH |
4354 | } |
4355 | if (! TARGET_REG_NAMES) | |
4356 | { | |
97e242b0 RH |
4357 | for (i = 0; i < current_frame_info.n_input_regs; i++) |
4358 | reg_names[IN_REG (i)] = ia64_input_reg_names[i]; | |
4359 | for (i = 0; i < current_frame_info.n_local_regs; i++) | |
4360 | reg_names[LOC_REG (i)] = ia64_local_reg_names[i]; | |
4361 | for (i = 0; i < current_frame_info.n_output_regs; i++) | |
4362 | reg_names[OUT_REG (i)] = ia64_output_reg_names[i]; | |
4363 | } | |
8a959ea5 | 4364 | |
97e242b0 RH |
4365 | current_frame_info.initialized = 0; |
4366 | } | |
c65ebc55 JW |
4367 | |
4368 | int | |
9c808aad | 4369 | ia64_dbx_register_number (int regno) |
c65ebc55 | 4370 | { |
97e242b0 RH |
4371 | /* In ia64_expand_prologue we quite literally renamed the frame pointer |
4372 | from its home at loc79 to something inside the register frame. We | |
4373 | must perform the same renumbering here for the debug info. */ | |
6fb5fa3c | 4374 | if (current_frame_info.r[reg_fp]) |
97e242b0 RH |
4375 | { |
4376 | if (regno == HARD_FRAME_POINTER_REGNUM) | |
6fb5fa3c DB |
4377 | regno = current_frame_info.r[reg_fp]; |
4378 | else if (regno == current_frame_info.r[reg_fp]) | |
97e242b0 RH |
4379 | regno = HARD_FRAME_POINTER_REGNUM; |
4380 | } | |
4381 | ||
4382 | if (IN_REGNO_P (regno)) | |
4383 | return 32 + regno - IN_REG (0); | |
4384 | else if (LOC_REGNO_P (regno)) | |
4385 | return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0); | |
4386 | else if (OUT_REGNO_P (regno)) | |
4387 | return (32 + current_frame_info.n_input_regs | |
4388 | + current_frame_info.n_local_regs + regno - OUT_REG (0)); | |
4389 | else | |
4390 | return regno; | |
c65ebc55 JW |
4391 | } |
4392 | ||
2a1211e5 RH |
4393 | /* Implement TARGET_TRAMPOLINE_INIT. |
4394 | ||
4395 | The trampoline should set the static chain pointer to value placed | |
4396 | into the trampoline and should branch to the specified routine. | |
4397 | To make the normal indirect-subroutine calling convention work, | |
4398 | the trampoline must look like a function descriptor; the first | |
4399 | word being the target address and the second being the target's | |
4400 | global pointer. | |
4401 | ||
4402 | We abuse the concept of a global pointer by arranging for it | |
4403 | to point to the data we need to load. The complete trampoline | |
4404 | has the following form: | |
4405 | ||
4406 | +-------------------+ \ | |
4407 | TRAMP: | __ia64_trampoline | | | |
4408 | +-------------------+ > fake function descriptor | |
4409 | | TRAMP+16 | | | |
4410 | +-------------------+ / | |
4411 | | target descriptor | | |
4412 | +-------------------+ | |
4413 | | static link | | |
4414 | +-------------------+ | |
4415 | */ | |
4416 | ||
4417 | static void | |
4418 | ia64_trampoline_init (rtx m_tramp, tree fndecl, rtx static_chain) | |
97e242b0 | 4419 | { |
2a1211e5 RH |
4420 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
4421 | rtx addr, addr_reg, tramp, eight = GEN_INT (8); | |
97e242b0 | 4422 | |
738e7b39 RK |
4423 | /* The Intel assembler requires that the global __ia64_trampoline symbol |
4424 | be declared explicitly */ | |
4425 | if (!TARGET_GNU_AS) | |
4426 | { | |
4427 | static bool declared_ia64_trampoline = false; | |
4428 | ||
4429 | if (!declared_ia64_trampoline) | |
4430 | { | |
4431 | declared_ia64_trampoline = true; | |
b6a41a62 RK |
4432 | (*targetm.asm_out.globalize_label) (asm_out_file, |
4433 | "__ia64_trampoline"); | |
738e7b39 RK |
4434 | } |
4435 | } | |
4436 | ||
5e89a381 | 4437 | /* Make sure addresses are Pmode even if we are in ILP32 mode. */ |
2a1211e5 | 4438 | addr = convert_memory_address (Pmode, XEXP (m_tramp, 0)); |
5e89a381 SE |
4439 | fnaddr = convert_memory_address (Pmode, fnaddr); |
4440 | static_chain = convert_memory_address (Pmode, static_chain); | |
4441 | ||
97e242b0 | 4442 | /* Load up our iterator. */ |
2a1211e5 RH |
4443 | addr_reg = copy_to_reg (addr); |
4444 | m_tramp = adjust_automodify_address (m_tramp, Pmode, addr_reg, 0); | |
97e242b0 RH |
4445 | |
4446 | /* The first two words are the fake descriptor: | |
4447 | __ia64_trampoline, ADDR+16. */ | |
f2972bf8 DR |
4448 | tramp = gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"); |
4449 | if (TARGET_ABI_OPEN_VMS) | |
4450 | { | |
4451 | /* HP decided to break the ELF ABI on VMS (to deal with an ambiguity | |
4452 | in the Macro-32 compiler) and changed the semantics of the LTOFF22 | |
4453 | relocation against function symbols to make it identical to the | |
4454 | LTOFF_FPTR22 relocation. Emit the latter directly to stay within | |
4455 | strict ELF and dereference to get the bare code address. */ | |
4456 | rtx reg = gen_reg_rtx (Pmode); | |
4457 | SYMBOL_REF_FLAGS (tramp) |= SYMBOL_FLAG_FUNCTION; | |
4458 | emit_move_insn (reg, tramp); | |
4459 | emit_move_insn (reg, gen_rtx_MEM (Pmode, reg)); | |
4460 | tramp = reg; | |
4461 | } | |
2a1211e5 | 4462 | emit_move_insn (m_tramp, tramp); |
97e242b0 | 4463 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4464 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 | 4465 | |
0a81f074 | 4466 | emit_move_insn (m_tramp, force_reg (Pmode, plus_constant (Pmode, addr, 16))); |
97e242b0 | 4467 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4468 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4469 | |
4470 | /* The third word is the target descriptor. */ | |
2a1211e5 | 4471 | emit_move_insn (m_tramp, force_reg (Pmode, fnaddr)); |
97e242b0 | 4472 | emit_insn (gen_adddi3 (addr_reg, addr_reg, eight)); |
2a1211e5 | 4473 | m_tramp = adjust_automodify_address (m_tramp, VOIDmode, NULL, 8); |
97e242b0 RH |
4474 | |
4475 | /* The fourth word is the static chain. */ | |
2a1211e5 | 4476 | emit_move_insn (m_tramp, static_chain); |
97e242b0 | 4477 | } |
c65ebc55 JW |
4478 | \f |
4479 | /* Do any needed setup for a variadic function. CUM has not been updated | |
97e242b0 RH |
4480 | for the last named argument which has type TYPE and mode MODE. |
4481 | ||
4482 | We generate the actual spill instructions during prologue generation. */ | |
4483 | ||
351a758b | 4484 | static void |
d5cc9181 | 4485 | ia64_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, |
351a758b | 4486 | tree type, int * pretend_size, |
9c808aad | 4487 | int second_time ATTRIBUTE_UNUSED) |
c65ebc55 | 4488 | { |
d5cc9181 | 4489 | CUMULATIVE_ARGS next_cum = *get_cumulative_args (cum); |
351a758b | 4490 | |
6c535c69 | 4491 | /* Skip the current argument. */ |
d5cc9181 | 4492 | ia64_function_arg_advance (pack_cumulative_args (&next_cum), mode, type, 1); |
c65ebc55 | 4493 | |
351a758b | 4494 | if (next_cum.words < MAX_ARGUMENT_SLOTS) |
26a110f5 | 4495 | { |
351a758b | 4496 | int n = MAX_ARGUMENT_SLOTS - next_cum.words; |
26a110f5 RH |
4497 | *pretend_size = n * UNITS_PER_WORD; |
4498 | cfun->machine->n_varargs = n; | |
4499 | } | |
c65ebc55 JW |
4500 | } |
4501 | ||
4502 | /* Check whether TYPE is a homogeneous floating point aggregate. If | |
4503 | it is, return the mode of the floating point type that appears | |
4504 | in all leafs. If it is not, return VOIDmode. | |
4505 | ||
4506 | An aggregate is a homogeneous floating point aggregate is if all | |
4507 | fields/elements in it have the same floating point type (e.g, | |
3d6a9acd RH |
4508 | SFmode). 128-bit quad-precision floats are excluded. |
4509 | ||
4510 | Variable sized aggregates should never arrive here, since we should | |
4511 | have already decided to pass them by reference. Top-level zero-sized | |
4512 | aggregates are excluded because our parallels crash the middle-end. */ | |
c65ebc55 JW |
4513 | |
4514 | static enum machine_mode | |
586de218 | 4515 | hfa_element_mode (const_tree type, bool nested) |
c65ebc55 JW |
4516 | { |
4517 | enum machine_mode element_mode = VOIDmode; | |
4518 | enum machine_mode mode; | |
4519 | enum tree_code code = TREE_CODE (type); | |
4520 | int know_element_mode = 0; | |
4521 | tree t; | |
4522 | ||
3d6a9acd RH |
4523 | if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type)))) |
4524 | return VOIDmode; | |
4525 | ||
c65ebc55 JW |
4526 | switch (code) |
4527 | { | |
4528 | case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE: | |
0cc8f5c5 | 4529 | case BOOLEAN_TYPE: case POINTER_TYPE: |
c65ebc55 | 4530 | case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE: |
5662a50d | 4531 | case LANG_TYPE: case FUNCTION_TYPE: |
c65ebc55 JW |
4532 | return VOIDmode; |
4533 | ||
4534 | /* Fortran complex types are supposed to be HFAs, so we need to handle | |
4535 | gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex | |
4536 | types though. */ | |
4537 | case COMPLEX_TYPE: | |
16448fd4 | 4538 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT |
02befdf4 ZW |
4539 | && TYPE_MODE (type) != TCmode) |
4540 | return GET_MODE_INNER (TYPE_MODE (type)); | |
c65ebc55 JW |
4541 | else |
4542 | return VOIDmode; | |
4543 | ||
4544 | case REAL_TYPE: | |
4545 | /* We want to return VOIDmode for raw REAL_TYPEs, but the actual | |
4546 | mode if this is contained within an aggregate. */ | |
02befdf4 | 4547 | if (nested && TYPE_MODE (type) != TFmode) |
c65ebc55 JW |
4548 | return TYPE_MODE (type); |
4549 | else | |
4550 | return VOIDmode; | |
4551 | ||
4552 | case ARRAY_TYPE: | |
46399021 | 4553 | return hfa_element_mode (TREE_TYPE (type), 1); |
c65ebc55 JW |
4554 | |
4555 | case RECORD_TYPE: | |
4556 | case UNION_TYPE: | |
4557 | case QUAL_UNION_TYPE: | |
910ad8de | 4558 | for (t = TYPE_FIELDS (type); t; t = DECL_CHAIN (t)) |
c65ebc55 JW |
4559 | { |
4560 | if (TREE_CODE (t) != FIELD_DECL) | |
4561 | continue; | |
4562 | ||
4563 | mode = hfa_element_mode (TREE_TYPE (t), 1); | |
4564 | if (know_element_mode) | |
4565 | { | |
4566 | if (mode != element_mode) | |
4567 | return VOIDmode; | |
4568 | } | |
4569 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT) | |
4570 | return VOIDmode; | |
4571 | else | |
4572 | { | |
4573 | know_element_mode = 1; | |
4574 | element_mode = mode; | |
4575 | } | |
4576 | } | |
4577 | return element_mode; | |
4578 | ||
4579 | default: | |
4580 | /* If we reach here, we probably have some front-end specific type | |
4581 | that the backend doesn't know about. This can happen via the | |
4582 | aggregate_value_p call in init_function_start. All we can do is | |
4583 | ignore unknown tree types. */ | |
4584 | return VOIDmode; | |
4585 | } | |
4586 | ||
4587 | return VOIDmode; | |
4588 | } | |
4589 | ||
f57fc998 ZW |
4590 | /* Return the number of words required to hold a quantity of TYPE and MODE |
4591 | when passed as an argument. */ | |
4592 | static int | |
ffa88471 | 4593 | ia64_function_arg_words (const_tree type, enum machine_mode mode) |
f57fc998 ZW |
4594 | { |
4595 | int words; | |
4596 | ||
4597 | if (mode == BLKmode) | |
4598 | words = int_size_in_bytes (type); | |
4599 | else | |
4600 | words = GET_MODE_SIZE (mode); | |
4601 | ||
4602 | return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */ | |
4603 | } | |
4604 | ||
4605 | /* Return the number of registers that should be skipped so the current | |
4606 | argument (described by TYPE and WORDS) will be properly aligned. | |
4607 | ||
4608 | Integer and float arguments larger than 8 bytes start at the next | |
4609 | even boundary. Aggregates larger than 8 bytes start at the next | |
4610 | even boundary if the aggregate has 16 byte alignment. Note that | |
4611 | in the 32-bit ABI, TImode and TFmode have only 8-byte alignment | |
4612 | but are still to be aligned in registers. | |
4613 | ||
4614 | ??? The ABI does not specify how to handle aggregates with | |
4615 | alignment from 9 to 15 bytes, or greater than 16. We handle them | |
4616 | all as if they had 16 byte alignment. Such aggregates can occur | |
4617 | only if gcc extensions are used. */ | |
4618 | static int | |
ffa88471 SE |
4619 | ia64_function_arg_offset (const CUMULATIVE_ARGS *cum, |
4620 | const_tree type, int words) | |
f57fc998 | 4621 | { |
f2972bf8 DR |
4622 | /* No registers are skipped on VMS. */ |
4623 | if (TARGET_ABI_OPEN_VMS || (cum->words & 1) == 0) | |
f57fc998 ZW |
4624 | return 0; |
4625 | ||
4626 | if (type | |
4627 | && TREE_CODE (type) != INTEGER_TYPE | |
4628 | && TREE_CODE (type) != REAL_TYPE) | |
4629 | return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT; | |
4630 | else | |
4631 | return words > 1; | |
4632 | } | |
4633 | ||
c65ebc55 JW |
4634 | /* Return rtx for register where argument is passed, or zero if it is passed |
4635 | on the stack. */ | |
c65ebc55 JW |
4636 | /* ??? 128-bit quad-precision floats are always passed in general |
4637 | registers. */ | |
4638 | ||
ffa88471 | 4639 | static rtx |
d5cc9181 | 4640 | ia64_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, |
ffa88471 | 4641 | const_tree type, bool named, bool incoming) |
c65ebc55 | 4642 | { |
d5cc9181 JR |
4643 | const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4644 | ||
c65ebc55 | 4645 | int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST); |
f57fc998 ZW |
4646 | int words = ia64_function_arg_words (type, mode); |
4647 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4648 | enum machine_mode hfa_mode = VOIDmode; |
4649 | ||
f2972bf8 DR |
4650 | /* For OPEN VMS, emit the instruction setting up the argument register here, |
4651 | when we know this will be together with the other arguments setup related | |
4652 | insns. This is not the conceptually best place to do this, but this is | |
4653 | the easiest as we have convenient access to cumulative args info. */ | |
4654 | ||
4655 | if (TARGET_ABI_OPEN_VMS && mode == VOIDmode && type == void_type_node | |
4656 | && named == 1) | |
4657 | { | |
4658 | unsigned HOST_WIDE_INT regval = cum->words; | |
4659 | int i; | |
4660 | ||
4661 | for (i = 0; i < 8; i++) | |
4662 | regval |= ((int) cum->atypes[i]) << (i * 3 + 8); | |
4663 | ||
4664 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (25)), | |
4665 | GEN_INT (regval)); | |
4666 | } | |
4667 | ||
c65ebc55 JW |
4668 | /* If all argument slots are used, then it must go on the stack. */ |
4669 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4670 | return 0; | |
4671 | ||
472b8fdc TG |
4672 | /* On OpenVMS argument is either in Rn or Fn. */ |
4673 | if (TARGET_ABI_OPEN_VMS) | |
4674 | { | |
4675 | if (FLOAT_MODE_P (mode)) | |
4676 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->words); | |
4677 | else | |
4678 | return gen_rtx_REG (mode, basereg + cum->words); | |
4679 | } | |
4680 | ||
c65ebc55 JW |
4681 | /* Check for and handle homogeneous FP aggregates. */ |
4682 | if (type) | |
4683 | hfa_mode = hfa_element_mode (type, 0); | |
4684 | ||
4685 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4686 | and unprototyped hfas are passed specially. */ | |
4687 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4688 | { | |
4689 | rtx loc[16]; | |
4690 | int i = 0; | |
4691 | int fp_regs = cum->fp_regs; | |
4692 | int int_regs = cum->words + offset; | |
4693 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4694 | int byte_size; | |
4695 | int args_byte_size; | |
4696 | ||
4697 | /* If prototyped, pass it in FR regs then GR regs. | |
4698 | If not prototyped, pass it in both FR and GR regs. | |
4699 | ||
4700 | If this is an SFmode aggregate, then it is possible to run out of | |
4701 | FR regs while GR regs are still left. In that case, we pass the | |
4702 | remaining part in the GR regs. */ | |
4703 | ||
4704 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4705 | of the argument, the last FP register, or the last argument slot. */ | |
4706 | ||
4707 | byte_size = ((mode == BLKmode) | |
4708 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4709 | args_byte_size = int_regs * UNITS_PER_WORD; | |
4710 | offset = 0; | |
4711 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4712 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++) | |
4713 | { | |
4714 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4715 | gen_rtx_REG (hfa_mode, (FR_ARG_FIRST | |
4716 | + fp_regs)), | |
4717 | GEN_INT (offset)); | |
c65ebc55 JW |
4718 | offset += hfa_size; |
4719 | args_byte_size += hfa_size; | |
4720 | fp_regs++; | |
4721 | } | |
4722 | ||
4723 | /* If no prototype, then the whole thing must go in GR regs. */ | |
4724 | if (! cum->prototype) | |
4725 | offset = 0; | |
4726 | /* If this is an SFmode aggregate, then we might have some left over | |
4727 | that needs to go in GR regs. */ | |
4728 | else if (byte_size != offset) | |
4729 | int_regs += offset / UNITS_PER_WORD; | |
4730 | ||
4731 | /* Fill in the GR regs. We must use DImode here, not the hfa mode. */ | |
4732 | ||
4733 | for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++) | |
4734 | { | |
4735 | enum machine_mode gr_mode = DImode; | |
826b47cc | 4736 | unsigned int gr_size; |
c65ebc55 JW |
4737 | |
4738 | /* If we have an odd 4 byte hunk because we ran out of FR regs, | |
4739 | then this goes in a GR reg left adjusted/little endian, right | |
4740 | adjusted/big endian. */ | |
4741 | /* ??? Currently this is handled wrong, because 4-byte hunks are | |
4742 | always right adjusted/little endian. */ | |
4743 | if (offset & 0x4) | |
4744 | gr_mode = SImode; | |
4745 | /* If we have an even 4 byte hunk because the aggregate is a | |
4746 | multiple of 4 bytes in size, then this goes in a GR reg right | |
4747 | adjusted/little endian. */ | |
4748 | else if (byte_size - offset == 4) | |
4749 | gr_mode = SImode; | |
4750 | ||
4751 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
4752 | gen_rtx_REG (gr_mode, (basereg | |
4753 | + int_regs)), | |
4754 | GEN_INT (offset)); | |
826b47cc ZW |
4755 | |
4756 | gr_size = GET_MODE_SIZE (gr_mode); | |
4757 | offset += gr_size; | |
4758 | if (gr_size == UNITS_PER_WORD | |
4759 | || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0)) | |
4760 | int_regs++; | |
4761 | else if (gr_size > UNITS_PER_WORD) | |
4762 | int_regs += gr_size / UNITS_PER_WORD; | |
c65ebc55 | 4763 | } |
9dec91d4 | 4764 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 4765 | } |
f2972bf8 | 4766 | |
c65ebc55 JW |
4767 | /* Integral and aggregates go in general registers. If we have run out of |
4768 | FR registers, then FP values must also go in general registers. This can | |
4769 | happen when we have a SFmode HFA. */ | |
02befdf4 ZW |
4770 | else if (mode == TFmode || mode == TCmode |
4771 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
3870df96 SE |
4772 | { |
4773 | int byte_size = ((mode == BLKmode) | |
4774 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4775 | if (BYTES_BIG_ENDIAN | |
4776 | && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type))) | |
4777 | && byte_size < UNITS_PER_WORD | |
4778 | && byte_size > 0) | |
4779 | { | |
4780 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
4781 | gen_rtx_REG (DImode, | |
4782 | (basereg + cum->words | |
4783 | + offset)), | |
4784 | const0_rtx); | |
4785 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg)); | |
4786 | } | |
4787 | else | |
4788 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
4789 | ||
4790 | } | |
c65ebc55 JW |
4791 | |
4792 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4793 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4794 | else if (cum->prototype) |
4795 | { | |
f9c887ac | 4796 | if (named) |
c65ebc55 | 4797 | return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs); |
f9c887ac ZW |
4798 | /* In big-endian mode, an anonymous SFmode value must be represented |
4799 | as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force | |
4800 | the value into the high half of the general register. */ | |
4801 | else if (BYTES_BIG_ENDIAN && mode == SFmode) | |
4802 | return gen_rtx_PARALLEL (mode, | |
4803 | gen_rtvec (1, | |
4804 | gen_rtx_EXPR_LIST (VOIDmode, | |
4805 | gen_rtx_REG (DImode, basereg + cum->words + offset), | |
4806 | const0_rtx))); | |
4807 | else | |
4808 | return gen_rtx_REG (mode, basereg + cum->words + offset); | |
c65ebc55 JW |
4809 | } |
4810 | /* If there is no prototype, then FP values go in both FR and GR | |
4811 | registers. */ | |
4812 | else | |
4813 | { | |
f9c887ac ZW |
4814 | /* See comment above. */ |
4815 | enum machine_mode inner_mode = | |
4816 | (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode; | |
4817 | ||
c65ebc55 JW |
4818 | rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode, |
4819 | gen_rtx_REG (mode, (FR_ARG_FIRST | |
4820 | + cum->fp_regs)), | |
4821 | const0_rtx); | |
4822 | rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode, | |
f9c887ac | 4823 | gen_rtx_REG (inner_mode, |
c65ebc55 JW |
4824 | (basereg + cum->words |
4825 | + offset)), | |
4826 | const0_rtx); | |
809d4ef1 | 4827 | |
c65ebc55 JW |
4828 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg)); |
4829 | } | |
4830 | } | |
4831 | ||
ffa88471 SE |
4832 | /* Implement TARGET_FUNCION_ARG target hook. */ |
4833 | ||
4834 | static rtx | |
d5cc9181 | 4835 | ia64_function_arg (cumulative_args_t cum, enum machine_mode mode, |
ffa88471 SE |
4836 | const_tree type, bool named) |
4837 | { | |
4838 | return ia64_function_arg_1 (cum, mode, type, named, false); | |
4839 | } | |
4840 | ||
4841 | /* Implement TARGET_FUNCION_INCOMING_ARG target hook. */ | |
4842 | ||
4843 | static rtx | |
d5cc9181 | 4844 | ia64_function_incoming_arg (cumulative_args_t cum, |
ffa88471 SE |
4845 | enum machine_mode mode, |
4846 | const_tree type, bool named) | |
4847 | { | |
4848 | return ia64_function_arg_1 (cum, mode, type, named, true); | |
4849 | } | |
4850 | ||
78a52f11 | 4851 | /* Return number of bytes, at the beginning of the argument, that must be |
c65ebc55 JW |
4852 | put in registers. 0 is the argument is entirely in registers or entirely |
4853 | in memory. */ | |
4854 | ||
78a52f11 | 4855 | static int |
d5cc9181 | 4856 | ia64_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, |
78a52f11 | 4857 | tree type, bool named ATTRIBUTE_UNUSED) |
c65ebc55 | 4858 | { |
d5cc9181 JR |
4859 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
4860 | ||
f57fc998 ZW |
4861 | int words = ia64_function_arg_words (type, mode); |
4862 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4863 | |
4864 | /* If all argument slots are used, then it must go on the stack. */ | |
4865 | if (cum->words + offset >= MAX_ARGUMENT_SLOTS) | |
4866 | return 0; | |
4867 | ||
4868 | /* It doesn't matter whether the argument goes in FR or GR regs. If | |
4869 | it fits within the 8 argument slots, then it goes entirely in | |
4870 | registers. If it extends past the last argument slot, then the rest | |
4871 | goes on the stack. */ | |
4872 | ||
4873 | if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS) | |
4874 | return 0; | |
4875 | ||
78a52f11 | 4876 | return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD; |
c65ebc55 JW |
4877 | } |
4878 | ||
f2972bf8 DR |
4879 | /* Return ivms_arg_type based on machine_mode. */ |
4880 | ||
4881 | static enum ivms_arg_type | |
4882 | ia64_arg_type (enum machine_mode mode) | |
4883 | { | |
4884 | switch (mode) | |
4885 | { | |
4886 | case SFmode: | |
4887 | return FS; | |
4888 | case DFmode: | |
4889 | return FT; | |
4890 | default: | |
4891 | return I64; | |
4892 | } | |
4893 | } | |
4894 | ||
c65ebc55 JW |
4895 | /* Update CUM to point after this argument. This is patterned after |
4896 | ia64_function_arg. */ | |
4897 | ||
ffa88471 | 4898 | static void |
d5cc9181 | 4899 | ia64_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
ffa88471 | 4900 | const_tree type, bool named) |
c65ebc55 | 4901 | { |
d5cc9181 | 4902 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
f57fc998 ZW |
4903 | int words = ia64_function_arg_words (type, mode); |
4904 | int offset = ia64_function_arg_offset (cum, type, words); | |
c65ebc55 JW |
4905 | enum machine_mode hfa_mode = VOIDmode; |
4906 | ||
4907 | /* If all arg slots are already full, then there is nothing to do. */ | |
4908 | if (cum->words >= MAX_ARGUMENT_SLOTS) | |
f2972bf8 DR |
4909 | { |
4910 | cum->words += words + offset; | |
4911 | return; | |
4912 | } | |
c65ebc55 | 4913 | |
f2972bf8 | 4914 | cum->atypes[cum->words] = ia64_arg_type (mode); |
c65ebc55 JW |
4915 | cum->words += words + offset; |
4916 | ||
472b8fdc TG |
4917 | /* On OpenVMS argument is either in Rn or Fn. */ |
4918 | if (TARGET_ABI_OPEN_VMS) | |
4919 | { | |
4920 | cum->int_regs = cum->words; | |
4921 | cum->fp_regs = cum->words; | |
4922 | return; | |
4923 | } | |
4924 | ||
c65ebc55 JW |
4925 | /* Check for and handle homogeneous FP aggregates. */ |
4926 | if (type) | |
4927 | hfa_mode = hfa_element_mode (type, 0); | |
4928 | ||
4929 | /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas | |
4930 | and unprototyped hfas are passed specially. */ | |
4931 | if (hfa_mode != VOIDmode && (! cum->prototype || named)) | |
4932 | { | |
4933 | int fp_regs = cum->fp_regs; | |
4934 | /* This is the original value of cum->words + offset. */ | |
4935 | int int_regs = cum->words - words; | |
4936 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
4937 | int byte_size; | |
4938 | int args_byte_size; | |
4939 | ||
4940 | /* If prototyped, pass it in FR regs then GR regs. | |
4941 | If not prototyped, pass it in both FR and GR regs. | |
4942 | ||
4943 | If this is an SFmode aggregate, then it is possible to run out of | |
4944 | FR regs while GR regs are still left. In that case, we pass the | |
4945 | remaining part in the GR regs. */ | |
4946 | ||
4947 | /* Fill the FP regs. We do this always. We stop if we reach the end | |
4948 | of the argument, the last FP register, or the last argument slot. */ | |
4949 | ||
4950 | byte_size = ((mode == BLKmode) | |
4951 | ? int_size_in_bytes (type) : GET_MODE_SIZE (mode)); | |
4952 | args_byte_size = int_regs * UNITS_PER_WORD; | |
4953 | offset = 0; | |
4954 | for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS | |
4955 | && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));) | |
4956 | { | |
c65ebc55 JW |
4957 | offset += hfa_size; |
4958 | args_byte_size += hfa_size; | |
4959 | fp_regs++; | |
4960 | } | |
4961 | ||
4962 | cum->fp_regs = fp_regs; | |
4963 | } | |
4964 | ||
d13256a3 SE |
4965 | /* Integral and aggregates go in general registers. So do TFmode FP values. |
4966 | If we have run out of FR registers, then other FP values must also go in | |
4967 | general registers. This can happen when we have a SFmode HFA. */ | |
4968 | else if (mode == TFmode || mode == TCmode | |
4969 | || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)) | |
648fe28b | 4970 | cum->int_regs = cum->words; |
c65ebc55 JW |
4971 | |
4972 | /* If there is a prototype, then FP values go in a FR register when | |
9e4f94de | 4973 | named, and in a GR register when unnamed. */ |
c65ebc55 JW |
4974 | else if (cum->prototype) |
4975 | { | |
4976 | if (! named) | |
648fe28b | 4977 | cum->int_regs = cum->words; |
c65ebc55 JW |
4978 | else |
4979 | /* ??? Complex types should not reach here. */ | |
4980 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
4981 | } | |
4982 | /* If there is no prototype, then FP values go in both FR and GR | |
4983 | registers. */ | |
4984 | else | |
9c808aad | 4985 | { |
648fe28b RH |
4986 | /* ??? Complex types should not reach here. */ |
4987 | cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1); | |
4988 | cum->int_regs = cum->words; | |
4989 | } | |
c65ebc55 | 4990 | } |
51dcde6f | 4991 | |
d13256a3 | 4992 | /* Arguments with alignment larger than 8 bytes start at the next even |
93348822 | 4993 | boundary. On ILP32 HPUX, TFmode arguments start on next even boundary |
d13256a3 SE |
4994 | even though their normal alignment is 8 bytes. See ia64_function_arg. */ |
4995 | ||
c2ed6cf8 NF |
4996 | static unsigned int |
4997 | ia64_function_arg_boundary (enum machine_mode mode, const_tree type) | |
d13256a3 | 4998 | { |
d13256a3 SE |
4999 | if (mode == TFmode && TARGET_HPUX && TARGET_ILP32) |
5000 | return PARM_BOUNDARY * 2; | |
5001 | ||
5002 | if (type) | |
5003 | { | |
5004 | if (TYPE_ALIGN (type) > PARM_BOUNDARY) | |
5005 | return PARM_BOUNDARY * 2; | |
5006 | else | |
5007 | return PARM_BOUNDARY; | |
5008 | } | |
5009 | ||
5010 | if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY) | |
5011 | return PARM_BOUNDARY * 2; | |
5012 | else | |
5013 | return PARM_BOUNDARY; | |
5014 | } | |
5015 | ||
599aedd9 RH |
5016 | /* True if it is OK to do sibling call optimization for the specified |
5017 | call expression EXP. DECL will be the called function, or NULL if | |
5018 | this is an indirect call. */ | |
5019 | static bool | |
9c808aad | 5020 | ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
599aedd9 | 5021 | { |
097f3d48 JW |
5022 | /* We can't perform a sibcall if the current function has the syscall_linkage |
5023 | attribute. */ | |
5024 | if (lookup_attribute ("syscall_linkage", | |
5025 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))) | |
5026 | return false; | |
5027 | ||
b23ba0b8 | 5028 | /* We must always return with our current GP. This means we can |
c208436c SE |
5029 | only sibcall to functions defined in the current module unless |
5030 | TARGET_CONST_GP is set to true. */ | |
5031 | return (decl && (*targetm.binds_local_p) (decl)) || TARGET_CONST_GP; | |
599aedd9 | 5032 | } |
c65ebc55 | 5033 | \f |
c65ebc55 JW |
5034 | |
5035 | /* Implement va_arg. */ | |
5036 | ||
23a60a04 | 5037 | static tree |
726a989a RB |
5038 | ia64_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
5039 | gimple_seq *post_p) | |
cd3ce9b4 | 5040 | { |
cd3ce9b4 | 5041 | /* Variable sized types are passed by reference. */ |
08b0dc1b | 5042 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
cd3ce9b4 | 5043 | { |
23a60a04 JM |
5044 | tree ptrtype = build_pointer_type (type); |
5045 | tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p); | |
c2433d7d | 5046 | return build_va_arg_indirect_ref (addr); |
cd3ce9b4 JM |
5047 | } |
5048 | ||
5049 | /* Aggregate arguments with alignment larger than 8 bytes start at | |
5050 | the next even boundary. Integer and floating point arguments | |
5051 | do so if they are larger than 8 bytes, whether or not they are | |
5052 | also aligned larger than 8 bytes. */ | |
5053 | if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE) | |
5054 | ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT) | |
5055 | { | |
5d49b6a7 | 5056 | tree t = fold_build_pointer_plus_hwi (valist, 2 * UNITS_PER_WORD - 1); |
47a25a46 | 5057 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, |
5d49b6a7 | 5058 | build_int_cst (TREE_TYPE (t), -2 * UNITS_PER_WORD)); |
726a989a | 5059 | gimplify_assign (unshare_expr (valist), t, pre_p); |
cd3ce9b4 JM |
5060 | } |
5061 | ||
23a60a04 | 5062 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
cd3ce9b4 | 5063 | } |
c65ebc55 JW |
5064 | \f |
5065 | /* Return 1 if function return value returned in memory. Return 0 if it is | |
5066 | in a register. */ | |
5067 | ||
351a758b | 5068 | static bool |
586de218 | 5069 | ia64_return_in_memory (const_tree valtype, const_tree fntype ATTRIBUTE_UNUSED) |
c65ebc55 JW |
5070 | { |
5071 | enum machine_mode mode; | |
5072 | enum machine_mode hfa_mode; | |
487b97e0 | 5073 | HOST_WIDE_INT byte_size; |
c65ebc55 JW |
5074 | |
5075 | mode = TYPE_MODE (valtype); | |
487b97e0 RH |
5076 | byte_size = GET_MODE_SIZE (mode); |
5077 | if (mode == BLKmode) | |
5078 | { | |
5079 | byte_size = int_size_in_bytes (valtype); | |
5080 | if (byte_size < 0) | |
351a758b | 5081 | return true; |
487b97e0 | 5082 | } |
c65ebc55 JW |
5083 | |
5084 | /* Hfa's with up to 8 elements are returned in the FP argument registers. */ | |
5085 | ||
5086 | hfa_mode = hfa_element_mode (valtype, 0); | |
5087 | if (hfa_mode != VOIDmode) | |
5088 | { | |
5089 | int hfa_size = GET_MODE_SIZE (hfa_mode); | |
5090 | ||
c65ebc55 | 5091 | if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS) |
351a758b | 5092 | return true; |
c65ebc55 | 5093 | else |
351a758b | 5094 | return false; |
c65ebc55 | 5095 | } |
c65ebc55 | 5096 | else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS) |
351a758b | 5097 | return true; |
c65ebc55 | 5098 | else |
351a758b | 5099 | return false; |
c65ebc55 JW |
5100 | } |
5101 | ||
5102 | /* Return rtx for register that holds the function return value. */ | |
5103 | ||
ba90d838 AS |
5104 | static rtx |
5105 | ia64_function_value (const_tree valtype, | |
5106 | const_tree fn_decl_or_type, | |
5107 | bool outgoing ATTRIBUTE_UNUSED) | |
c65ebc55 JW |
5108 | { |
5109 | enum machine_mode mode; | |
5110 | enum machine_mode hfa_mode; | |
f2972bf8 | 5111 | int unsignedp; |
ba90d838 | 5112 | const_tree func = fn_decl_or_type; |
c65ebc55 | 5113 | |
ba90d838 AS |
5114 | if (fn_decl_or_type |
5115 | && !DECL_P (fn_decl_or_type)) | |
5116 | func = NULL; | |
5117 | ||
c65ebc55 JW |
5118 | mode = TYPE_MODE (valtype); |
5119 | hfa_mode = hfa_element_mode (valtype, 0); | |
5120 | ||
5121 | if (hfa_mode != VOIDmode) | |
5122 | { | |
5123 | rtx loc[8]; | |
5124 | int i; | |
5125 | int hfa_size; | |
5126 | int byte_size; | |
5127 | int offset; | |
5128 | ||
5129 | hfa_size = GET_MODE_SIZE (hfa_mode); | |
5130 | byte_size = ((mode == BLKmode) | |
5131 | ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode)); | |
5132 | offset = 0; | |
5133 | for (i = 0; offset < byte_size; i++) | |
5134 | { | |
5135 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5136 | gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i), | |
5137 | GEN_INT (offset)); | |
c65ebc55 JW |
5138 | offset += hfa_size; |
5139 | } | |
9dec91d4 | 5140 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); |
c65ebc55 | 5141 | } |
f57fc998 | 5142 | else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode) |
c65ebc55 JW |
5143 | return gen_rtx_REG (mode, FR_ARG_FIRST); |
5144 | else | |
3870df96 | 5145 | { |
8c5cacfd RH |
5146 | bool need_parallel = false; |
5147 | ||
5148 | /* In big-endian mode, we need to manage the layout of aggregates | |
5149 | in the registers so that we get the bits properly aligned in | |
5150 | the highpart of the registers. */ | |
3870df96 SE |
5151 | if (BYTES_BIG_ENDIAN |
5152 | && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype)))) | |
8c5cacfd RH |
5153 | need_parallel = true; |
5154 | ||
5155 | /* Something like struct S { long double x; char a[0] } is not an | |
5156 | HFA structure, and therefore doesn't go in fp registers. But | |
5157 | the middle-end will give it XFmode anyway, and XFmode values | |
5158 | don't normally fit in integer registers. So we need to smuggle | |
5159 | the value inside a parallel. */ | |
4de67c26 | 5160 | else if (mode == XFmode || mode == XCmode || mode == RFmode) |
8c5cacfd RH |
5161 | need_parallel = true; |
5162 | ||
5163 | if (need_parallel) | |
3870df96 SE |
5164 | { |
5165 | rtx loc[8]; | |
5166 | int offset; | |
5167 | int bytesize; | |
5168 | int i; | |
5169 | ||
5170 | offset = 0; | |
5171 | bytesize = int_size_in_bytes (valtype); | |
543144ed JM |
5172 | /* An empty PARALLEL is invalid here, but the return value |
5173 | doesn't matter for empty structs. */ | |
5174 | if (bytesize == 0) | |
5175 | return gen_rtx_REG (mode, GR_RET_FIRST); | |
3870df96 SE |
5176 | for (i = 0; offset < bytesize; i++) |
5177 | { | |
5178 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
5179 | gen_rtx_REG (DImode, | |
5180 | GR_RET_FIRST + i), | |
5181 | GEN_INT (offset)); | |
5182 | offset += UNITS_PER_WORD; | |
5183 | } | |
5184 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc)); | |
5185 | } | |
8c5cacfd | 5186 | |
8ee95727 TG |
5187 | mode = promote_function_mode (valtype, mode, &unsignedp, |
5188 | func ? TREE_TYPE (func) : NULL_TREE, | |
5189 | true); | |
f2972bf8 | 5190 | |
8c5cacfd | 5191 | return gen_rtx_REG (mode, GR_RET_FIRST); |
3870df96 | 5192 | } |
c65ebc55 JW |
5193 | } |
5194 | ||
ba90d838 AS |
5195 | /* Worker function for TARGET_LIBCALL_VALUE. */ |
5196 | ||
5197 | static rtx | |
5198 | ia64_libcall_value (enum machine_mode mode, | |
5199 | const_rtx fun ATTRIBUTE_UNUSED) | |
5200 | { | |
5201 | return gen_rtx_REG (mode, | |
5202 | (((GET_MODE_CLASS (mode) == MODE_FLOAT | |
5203 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5204 | && (mode) != TFmode) | |
5205 | ? FR_RET_FIRST : GR_RET_FIRST)); | |
5206 | } | |
5207 | ||
5208 | /* Worker function for FUNCTION_VALUE_REGNO_P. */ | |
5209 | ||
5210 | static bool | |
5211 | ia64_function_value_regno_p (const unsigned int regno) | |
5212 | { | |
5213 | return ((regno >= GR_RET_FIRST && regno <= GR_RET_LAST) | |
5214 | || (regno >= FR_RET_FIRST && regno <= FR_RET_LAST)); | |
5215 | } | |
5216 | ||
fdbe66f2 | 5217 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
5218 | We need to emit DTP-relative relocations. */ |
5219 | ||
fdbe66f2 | 5220 | static void |
9c808aad | 5221 | ia64_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 | 5222 | { |
6f3113ed SE |
5223 | gcc_assert (size == 4 || size == 8); |
5224 | if (size == 4) | |
5225 | fputs ("\tdata4.ua\t@dtprel(", file); | |
5226 | else | |
5227 | fputs ("\tdata8.ua\t@dtprel(", file); | |
6b2300b3 JJ |
5228 | output_addr_const (file, x); |
5229 | fputs (")", file); | |
5230 | } | |
5231 | ||
c65ebc55 JW |
5232 | /* Print a memory address as an operand to reference that memory location. */ |
5233 | ||
5234 | /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps | |
5235 | also call this from ia64_print_operand for memory addresses. */ | |
5236 | ||
5e50b799 | 5237 | static void |
9c808aad AJ |
5238 | ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED, |
5239 | rtx address ATTRIBUTE_UNUSED) | |
c65ebc55 JW |
5240 | { |
5241 | } | |
5242 | ||
3569057d | 5243 | /* Print an operand to an assembler instruction. |
c65ebc55 JW |
5244 | C Swap and print a comparison operator. |
5245 | D Print an FP comparison operator. | |
5246 | E Print 32 - constant, for SImode shifts as extract. | |
66db6b45 | 5247 | e Print 64 - constant, for DImode rotates. |
c65ebc55 JW |
5248 | F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or |
5249 | a floating point register emitted normally. | |
735b94a7 | 5250 | G A floating point constant. |
c65ebc55 | 5251 | I Invert a predicate register by adding 1. |
e5bde68a | 5252 | J Select the proper predicate register for a condition. |
6b6c1201 | 5253 | j Select the inverse predicate register for a condition. |
c65ebc55 JW |
5254 | O Append .acq for volatile load. |
5255 | P Postincrement of a MEM. | |
5256 | Q Append .rel for volatile store. | |
4883241c | 5257 | R Print .s .d or nothing for a single, double or no truncation. |
c65ebc55 JW |
5258 | S Shift amount for shladd instruction. |
5259 | T Print an 8-bit sign extended number (K) as a 32-bit unsigned number | |
5260 | for Intel assembler. | |
5261 | U Print an 8-bit sign extended number (K) as a 64-bit unsigned number | |
5262 | for Intel assembler. | |
a71aef0b | 5263 | X A pair of floating point registers. |
c65ebc55 | 5264 | r Print register name, or constant 0 as r0. HP compatibility for |
f61134e8 RH |
5265 | Linux kernel. |
5266 | v Print vector constant value as an 8-byte integer value. */ | |
5267 | ||
5e50b799 | 5268 | static void |
9c808aad | 5269 | ia64_print_operand (FILE * file, rtx x, int code) |
c65ebc55 | 5270 | { |
e57b9d65 RH |
5271 | const char *str; |
5272 | ||
c65ebc55 JW |
5273 | switch (code) |
5274 | { | |
c65ebc55 JW |
5275 | case 0: |
5276 | /* Handled below. */ | |
5277 | break; | |
809d4ef1 | 5278 | |
c65ebc55 JW |
5279 | case 'C': |
5280 | { | |
5281 | enum rtx_code c = swap_condition (GET_CODE (x)); | |
5282 | fputs (GET_RTX_NAME (c), file); | |
5283 | return; | |
5284 | } | |
5285 | ||
5286 | case 'D': | |
e57b9d65 RH |
5287 | switch (GET_CODE (x)) |
5288 | { | |
5289 | case NE: | |
5290 | str = "neq"; | |
5291 | break; | |
5292 | case UNORDERED: | |
5293 | str = "unord"; | |
5294 | break; | |
5295 | case ORDERED: | |
5296 | str = "ord"; | |
5297 | break; | |
86ad1da0 SE |
5298 | case UNLT: |
5299 | str = "nge"; | |
5300 | break; | |
5301 | case UNLE: | |
5302 | str = "ngt"; | |
5303 | break; | |
5304 | case UNGT: | |
5305 | str = "nle"; | |
5306 | break; | |
5307 | case UNGE: | |
5308 | str = "nlt"; | |
5309 | break; | |
8fc53a5f EB |
5310 | case UNEQ: |
5311 | case LTGT: | |
5312 | gcc_unreachable (); | |
e57b9d65 RH |
5313 | default: |
5314 | str = GET_RTX_NAME (GET_CODE (x)); | |
5315 | break; | |
5316 | } | |
5317 | fputs (str, file); | |
c65ebc55 JW |
5318 | return; |
5319 | ||
5320 | case 'E': | |
5321 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); | |
5322 | return; | |
5323 | ||
66db6b45 RH |
5324 | case 'e': |
5325 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x)); | |
5326 | return; | |
5327 | ||
c65ebc55 JW |
5328 | case 'F': |
5329 | if (x == CONST0_RTX (GET_MODE (x))) | |
e57b9d65 | 5330 | str = reg_names [FR_REG (0)]; |
c65ebc55 | 5331 | else if (x == CONST1_RTX (GET_MODE (x))) |
e57b9d65 | 5332 | str = reg_names [FR_REG (1)]; |
c65ebc55 | 5333 | else |
e820471b NS |
5334 | { |
5335 | gcc_assert (GET_CODE (x) == REG); | |
5336 | str = reg_names [REGNO (x)]; | |
5337 | } | |
e57b9d65 | 5338 | fputs (str, file); |
c65ebc55 JW |
5339 | return; |
5340 | ||
735b94a7 SE |
5341 | case 'G': |
5342 | { | |
5343 | long val[4]; | |
5344 | REAL_VALUE_TYPE rv; | |
5345 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
5346 | real_to_target (val, &rv, GET_MODE (x)); | |
5347 | if (GET_MODE (x) == SFmode) | |
5348 | fprintf (file, "0x%08lx", val[0] & 0xffffffff); | |
5349 | else if (GET_MODE (x) == DFmode) | |
5350 | fprintf (file, "0x%08lx%08lx", (WORDS_BIG_ENDIAN ? val[0] : val[1]) | |
5351 | & 0xffffffff, | |
5352 | (WORDS_BIG_ENDIAN ? val[1] : val[0]) | |
5353 | & 0xffffffff); | |
5354 | else | |
5355 | output_operand_lossage ("invalid %%G mode"); | |
5356 | } | |
5357 | return; | |
5358 | ||
c65ebc55 JW |
5359 | case 'I': |
5360 | fputs (reg_names [REGNO (x) + 1], file); | |
5361 | return; | |
5362 | ||
e5bde68a | 5363 | case 'J': |
6b6c1201 RH |
5364 | case 'j': |
5365 | { | |
5366 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5367 | if (GET_CODE (x) == EQ) | |
5368 | regno += 1; | |
5369 | if (code == 'j') | |
5370 | regno ^= 1; | |
5371 | fputs (reg_names [regno], file); | |
5372 | } | |
e5bde68a RH |
5373 | return; |
5374 | ||
c65ebc55 JW |
5375 | case 'O': |
5376 | if (MEM_VOLATILE_P (x)) | |
5377 | fputs(".acq", file); | |
5378 | return; | |
5379 | ||
5380 | case 'P': | |
5381 | { | |
4b983fdc | 5382 | HOST_WIDE_INT value; |
c65ebc55 | 5383 | |
4b983fdc RH |
5384 | switch (GET_CODE (XEXP (x, 0))) |
5385 | { | |
5386 | default: | |
5387 | return; | |
5388 | ||
5389 | case POST_MODIFY: | |
5390 | x = XEXP (XEXP (XEXP (x, 0), 1), 1); | |
5391 | if (GET_CODE (x) == CONST_INT) | |
08012cda | 5392 | value = INTVAL (x); |
e820471b | 5393 | else |
4b983fdc | 5394 | { |
e820471b | 5395 | gcc_assert (GET_CODE (x) == REG); |
08012cda | 5396 | fprintf (file, ", %s", reg_names[REGNO (x)]); |
4b983fdc RH |
5397 | return; |
5398 | } | |
4b983fdc | 5399 | break; |
c65ebc55 | 5400 | |
4b983fdc RH |
5401 | case POST_INC: |
5402 | value = GET_MODE_SIZE (GET_MODE (x)); | |
4b983fdc | 5403 | break; |
c65ebc55 | 5404 | |
4b983fdc | 5405 | case POST_DEC: |
08012cda | 5406 | value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x)); |
4b983fdc RH |
5407 | break; |
5408 | } | |
809d4ef1 | 5409 | |
4a0a75dd | 5410 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value); |
c65ebc55 JW |
5411 | return; |
5412 | } | |
5413 | ||
5414 | case 'Q': | |
5415 | if (MEM_VOLATILE_P (x)) | |
5416 | fputs(".rel", file); | |
5417 | return; | |
5418 | ||
4883241c SE |
5419 | case 'R': |
5420 | if (x == CONST0_RTX (GET_MODE (x))) | |
5421 | fputs(".s", file); | |
5422 | else if (x == CONST1_RTX (GET_MODE (x))) | |
5423 | fputs(".d", file); | |
5424 | else if (x == CONST2_RTX (GET_MODE (x))) | |
5425 | ; | |
5426 | else | |
5427 | output_operand_lossage ("invalid %%R value"); | |
5428 | return; | |
5429 | ||
c65ebc55 | 5430 | case 'S': |
809d4ef1 | 5431 | fprintf (file, "%d", exact_log2 (INTVAL (x))); |
c65ebc55 JW |
5432 | return; |
5433 | ||
5434 | case 'T': | |
5435 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5436 | { | |
809d4ef1 | 5437 | fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5438 | return; |
5439 | } | |
5440 | break; | |
5441 | ||
5442 | case 'U': | |
5443 | if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT) | |
5444 | { | |
3b572406 | 5445 | const char *prefix = "0x"; |
c65ebc55 JW |
5446 | if (INTVAL (x) & 0x80000000) |
5447 | { | |
5448 | fprintf (file, "0xffffffff"); | |
5449 | prefix = ""; | |
5450 | } | |
809d4ef1 | 5451 | fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff); |
c65ebc55 JW |
5452 | return; |
5453 | } | |
5454 | break; | |
809d4ef1 | 5455 | |
a71aef0b JB |
5456 | case 'X': |
5457 | { | |
5458 | unsigned int regno = REGNO (x); | |
5459 | fprintf (file, "%s, %s", reg_names [regno], reg_names [regno + 1]); | |
5460 | } | |
5461 | return; | |
5462 | ||
c65ebc55 | 5463 | case 'r': |
18a3c539 JW |
5464 | /* If this operand is the constant zero, write it as register zero. |
5465 | Any register, zero, or CONST_INT value is OK here. */ | |
c65ebc55 JW |
5466 | if (GET_CODE (x) == REG) |
5467 | fputs (reg_names[REGNO (x)], file); | |
5468 | else if (x == CONST0_RTX (GET_MODE (x))) | |
5469 | fputs ("r0", file); | |
18a3c539 JW |
5470 | else if (GET_CODE (x) == CONST_INT) |
5471 | output_addr_const (file, x); | |
c65ebc55 JW |
5472 | else |
5473 | output_operand_lossage ("invalid %%r value"); | |
5474 | return; | |
5475 | ||
f61134e8 RH |
5476 | case 'v': |
5477 | gcc_assert (GET_CODE (x) == CONST_VECTOR); | |
5478 | x = simplify_subreg (DImode, x, GET_MODE (x), 0); | |
5479 | break; | |
5480 | ||
85548039 RH |
5481 | case '+': |
5482 | { | |
5483 | const char *which; | |
9c808aad | 5484 | |
85548039 RH |
5485 | /* For conditional branches, returns or calls, substitute |
5486 | sptk, dptk, dpnt, or spnt for %s. */ | |
5487 | x = find_reg_note (current_output_insn, REG_BR_PROB, 0); | |
5488 | if (x) | |
5489 | { | |
e5af9ddd | 5490 | int pred_val = XINT (x, 0); |
85548039 RH |
5491 | |
5492 | /* Guess top and bottom 10% statically predicted. */ | |
2c9e13f3 JH |
5493 | if (pred_val < REG_BR_PROB_BASE / 50 |
5494 | && br_prob_note_reliable_p (x)) | |
85548039 RH |
5495 | which = ".spnt"; |
5496 | else if (pred_val < REG_BR_PROB_BASE / 2) | |
5497 | which = ".dpnt"; | |
2c9e13f3 JH |
5498 | else if (pred_val < REG_BR_PROB_BASE / 100 * 98 |
5499 | || !br_prob_note_reliable_p (x)) | |
85548039 RH |
5500 | which = ".dptk"; |
5501 | else | |
5502 | which = ".sptk"; | |
5503 | } | |
b64925dc | 5504 | else if (CALL_P (current_output_insn)) |
85548039 RH |
5505 | which = ".sptk"; |
5506 | else | |
5507 | which = ".dptk"; | |
5508 | ||
5509 | fputs (which, file); | |
5510 | return; | |
5511 | } | |
5512 | ||
6f8aa100 RH |
5513 | case ',': |
5514 | x = current_insn_predicate; | |
5515 | if (x) | |
5516 | { | |
5517 | unsigned int regno = REGNO (XEXP (x, 0)); | |
5518 | if (GET_CODE (x) == EQ) | |
5519 | regno += 1; | |
6f8aa100 RH |
5520 | fprintf (file, "(%s) ", reg_names [regno]); |
5521 | } | |
5522 | return; | |
5523 | ||
c65ebc55 JW |
5524 | default: |
5525 | output_operand_lossage ("ia64_print_operand: unknown code"); | |
5526 | return; | |
5527 | } | |
5528 | ||
5529 | switch (GET_CODE (x)) | |
5530 | { | |
5531 | /* This happens for the spill/restore instructions. */ | |
5532 | case POST_INC: | |
4b983fdc RH |
5533 | case POST_DEC: |
5534 | case POST_MODIFY: | |
c65ebc55 | 5535 | x = XEXP (x, 0); |
ed168e45 | 5536 | /* ... fall through ... */ |
c65ebc55 JW |
5537 | |
5538 | case REG: | |
5539 | fputs (reg_names [REGNO (x)], file); | |
5540 | break; | |
5541 | ||
5542 | case MEM: | |
5543 | { | |
5544 | rtx addr = XEXP (x, 0); | |
ec8e098d | 5545 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC) |
c65ebc55 JW |
5546 | addr = XEXP (addr, 0); |
5547 | fprintf (file, "[%s]", reg_names [REGNO (addr)]); | |
5548 | break; | |
5549 | } | |
809d4ef1 | 5550 | |
c65ebc55 JW |
5551 | default: |
5552 | output_addr_const (file, x); | |
5553 | break; | |
5554 | } | |
5555 | ||
5556 | return; | |
5557 | } | |
5e50b799 AS |
5558 | |
5559 | /* Worker function for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ | |
5560 | ||
5561 | static bool | |
5562 | ia64_print_operand_punct_valid_p (unsigned char code) | |
5563 | { | |
5564 | return (code == '+' || code == ','); | |
5565 | } | |
c65ebc55 | 5566 | \f |
3c50106f RH |
5567 | /* Compute a (partial) cost for rtx X. Return true if the complete |
5568 | cost has been computed, and false if subexpressions should be | |
5569 | scanned. In either case, *TOTAL contains the cost result. */ | |
5570 | /* ??? This is incomplete. */ | |
5571 | ||
5572 | static bool | |
68f932c4 RS |
5573 | ia64_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
5574 | int *total, bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
5575 | { |
5576 | switch (code) | |
5577 | { | |
5578 | case CONST_INT: | |
5579 | switch (outer_code) | |
5580 | { | |
5581 | case SET: | |
13f70342 | 5582 | *total = satisfies_constraint_J (x) ? 0 : COSTS_N_INSNS (1); |
3c50106f RH |
5583 | return true; |
5584 | case PLUS: | |
13f70342 | 5585 | if (satisfies_constraint_I (x)) |
3c50106f | 5586 | *total = 0; |
13f70342 | 5587 | else if (satisfies_constraint_J (x)) |
3c50106f RH |
5588 | *total = 1; |
5589 | else | |
5590 | *total = COSTS_N_INSNS (1); | |
5591 | return true; | |
5592 | default: | |
13f70342 | 5593 | if (satisfies_constraint_K (x) || satisfies_constraint_L (x)) |
3c50106f RH |
5594 | *total = 0; |
5595 | else | |
5596 | *total = COSTS_N_INSNS (1); | |
5597 | return true; | |
5598 | } | |
5599 | ||
5600 | case CONST_DOUBLE: | |
5601 | *total = COSTS_N_INSNS (1); | |
5602 | return true; | |
5603 | ||
5604 | case CONST: | |
5605 | case SYMBOL_REF: | |
5606 | case LABEL_REF: | |
5607 | *total = COSTS_N_INSNS (3); | |
5608 | return true; | |
5609 | ||
f19f1e5e RH |
5610 | case FMA: |
5611 | *total = COSTS_N_INSNS (4); | |
5612 | return true; | |
5613 | ||
3c50106f RH |
5614 | case MULT: |
5615 | /* For multiplies wider than HImode, we have to go to the FPU, | |
5616 | which normally involves copies. Plus there's the latency | |
5617 | of the multiply itself, and the latency of the instructions to | |
5618 | transfer integer regs to FP regs. */ | |
f19f1e5e RH |
5619 | if (FLOAT_MODE_P (GET_MODE (x))) |
5620 | *total = COSTS_N_INSNS (4); | |
5621 | else if (GET_MODE_SIZE (GET_MODE (x)) > 2) | |
3c50106f RH |
5622 | *total = COSTS_N_INSNS (10); |
5623 | else | |
5624 | *total = COSTS_N_INSNS (2); | |
5625 | return true; | |
5626 | ||
5627 | case PLUS: | |
5628 | case MINUS: | |
f19f1e5e RH |
5629 | if (FLOAT_MODE_P (GET_MODE (x))) |
5630 | { | |
5631 | *total = COSTS_N_INSNS (4); | |
5632 | return true; | |
5633 | } | |
5634 | /* FALLTHRU */ | |
5635 | ||
3c50106f RH |
5636 | case ASHIFT: |
5637 | case ASHIFTRT: | |
5638 | case LSHIFTRT: | |
5639 | *total = COSTS_N_INSNS (1); | |
5640 | return true; | |
5641 | ||
5642 | case DIV: | |
5643 | case UDIV: | |
5644 | case MOD: | |
5645 | case UMOD: | |
5646 | /* We make divide expensive, so that divide-by-constant will be | |
5647 | optimized to a multiply. */ | |
5648 | *total = COSTS_N_INSNS (60); | |
5649 | return true; | |
5650 | ||
5651 | default: | |
5652 | return false; | |
5653 | } | |
5654 | } | |
5655 | ||
9e4f94de | 5656 | /* Calculate the cost of moving data from a register in class FROM to |
7109d286 | 5657 | one in class TO, using MODE. */ |
5527bf14 | 5658 | |
de8f4b07 | 5659 | static int |
6f76a878 AS |
5660 | ia64_register_move_cost (enum machine_mode mode, reg_class_t from, |
5661 | reg_class_t to) | |
a87cf97e | 5662 | { |
7109d286 RH |
5663 | /* ADDL_REGS is the same as GR_REGS for movement purposes. */ |
5664 | if (to == ADDL_REGS) | |
5665 | to = GR_REGS; | |
5666 | if (from == ADDL_REGS) | |
5667 | from = GR_REGS; | |
5668 | ||
5669 | /* All costs are symmetric, so reduce cases by putting the | |
5670 | lower number class as the destination. */ | |
5671 | if (from < to) | |
5672 | { | |
6f76a878 | 5673 | reg_class_t tmp = to; |
7109d286 RH |
5674 | to = from, from = tmp; |
5675 | } | |
5676 | ||
02befdf4 | 5677 | /* Moving from FR<->GR in XFmode must be more expensive than 2, |
7109d286 | 5678 | so that we get secondary memory reloads. Between FR_REGS, |
69e18c09 | 5679 | we have to make this at least as expensive as memory_move_cost |
7109d286 | 5680 | to avoid spectacularly poor register class preferencing. */ |
4de67c26 | 5681 | if (mode == XFmode || mode == RFmode) |
7109d286 RH |
5682 | { |
5683 | if (to != GR_REGS || from != GR_REGS) | |
69e18c09 | 5684 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5685 | else |
5686 | return 3; | |
5687 | } | |
5688 | ||
5689 | switch (to) | |
5690 | { | |
5691 | case PR_REGS: | |
5692 | /* Moving between PR registers takes two insns. */ | |
5693 | if (from == PR_REGS) | |
5694 | return 3; | |
5695 | /* Moving between PR and anything but GR is impossible. */ | |
5696 | if (from != GR_REGS) | |
69e18c09 | 5697 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5698 | break; |
5699 | ||
5700 | case BR_REGS: | |
5701 | /* Moving between BR and anything but GR is impossible. */ | |
5702 | if (from != GR_REGS && from != GR_AND_BR_REGS) | |
69e18c09 | 5703 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5704 | break; |
5705 | ||
5706 | case AR_I_REGS: | |
5707 | case AR_M_REGS: | |
5708 | /* Moving between AR and anything but GR is impossible. */ | |
5709 | if (from != GR_REGS) | |
69e18c09 | 5710 | return memory_move_cost (mode, to, false); |
7109d286 RH |
5711 | break; |
5712 | ||
5713 | case GR_REGS: | |
5714 | case FR_REGS: | |
a71aef0b | 5715 | case FP_REGS: |
7109d286 RH |
5716 | case GR_AND_FR_REGS: |
5717 | case GR_AND_BR_REGS: | |
5718 | case ALL_REGS: | |
5719 | break; | |
5720 | ||
5721 | default: | |
e820471b | 5722 | gcc_unreachable (); |
7109d286 | 5723 | } |
3f622353 | 5724 | |
5527bf14 RH |
5725 | return 2; |
5726 | } | |
c65ebc55 | 5727 | |
69e18c09 AS |
5728 | /* Calculate the cost of moving data of MODE from a register to or from |
5729 | memory. */ | |
5730 | ||
5731 | static int | |
5732 | ia64_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
5733 | reg_class_t rclass, | |
5734 | bool in ATTRIBUTE_UNUSED) | |
5735 | { | |
5736 | if (rclass == GENERAL_REGS | |
5737 | || rclass == FR_REGS | |
5738 | || rclass == FP_REGS | |
5739 | || rclass == GR_AND_FR_REGS) | |
5740 | return 4; | |
5741 | else | |
5742 | return 10; | |
5743 | } | |
5744 | ||
ab177ad5 AS |
5745 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. Place additional restrictions |
5746 | on RCLASS to use when copying X into that class. */ | |
f61134e8 | 5747 | |
ab177ad5 AS |
5748 | static reg_class_t |
5749 | ia64_preferred_reload_class (rtx x, reg_class_t rclass) | |
f61134e8 | 5750 | { |
0a2aaacc | 5751 | switch (rclass) |
f61134e8 RH |
5752 | { |
5753 | case FR_REGS: | |
a71aef0b | 5754 | case FP_REGS: |
f61134e8 RH |
5755 | /* Don't allow volatile mem reloads into floating point registers. |
5756 | This is defined to force reload to choose the r/m case instead | |
5757 | of the f/f case when reloading (set (reg fX) (mem/v)). */ | |
5758 | if (MEM_P (x) && MEM_VOLATILE_P (x)) | |
5759 | return NO_REGS; | |
5760 | ||
5761 | /* Force all unrecognized constants into the constant pool. */ | |
5762 | if (CONSTANT_P (x)) | |
5763 | return NO_REGS; | |
5764 | break; | |
5765 | ||
5766 | case AR_M_REGS: | |
5767 | case AR_I_REGS: | |
5768 | if (!OBJECT_P (x)) | |
5769 | return NO_REGS; | |
5770 | break; | |
5771 | ||
5772 | default: | |
5773 | break; | |
5774 | } | |
5775 | ||
0a2aaacc | 5776 | return rclass; |
f61134e8 RH |
5777 | } |
5778 | ||
c65ebc55 | 5779 | /* This function returns the register class required for a secondary |
0a2aaacc | 5780 | register when copying between one of the registers in RCLASS, and X, |
c65ebc55 JW |
5781 | using MODE. A return value of NO_REGS means that no secondary register |
5782 | is required. */ | |
5783 | ||
5784 | enum reg_class | |
0a2aaacc | 5785 | ia64_secondary_reload_class (enum reg_class rclass, |
9c808aad | 5786 | enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) |
c65ebc55 JW |
5787 | { |
5788 | int regno = -1; | |
5789 | ||
5790 | if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) | |
5791 | regno = true_regnum (x); | |
5792 | ||
0a2aaacc | 5793 | switch (rclass) |
97e242b0 RH |
5794 | { |
5795 | case BR_REGS: | |
7109d286 RH |
5796 | case AR_M_REGS: |
5797 | case AR_I_REGS: | |
5798 | /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global | |
5799 | interaction. We end up with two pseudos with overlapping lifetimes | |
5800 | both of which are equiv to the same constant, and both which need | |
5801 | to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end | |
5802 | changes depending on the path length, which means the qty_first_reg | |
5803 | check in make_regs_eqv can give different answers at different times. | |
5804 | At some point I'll probably need a reload_indi pattern to handle | |
5805 | this. | |
5806 | ||
5807 | We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we | |
5808 | wound up with a FP register from GR_AND_FR_REGS. Extend that to all | |
5809 | non-general registers for good measure. */ | |
5810 | if (regno >= 0 && ! GENERAL_REGNO_P (regno)) | |
97e242b0 RH |
5811 | return GR_REGS; |
5812 | ||
5813 | /* This is needed if a pseudo used as a call_operand gets spilled to a | |
5814 | stack slot. */ | |
5815 | if (GET_CODE (x) == MEM) | |
5816 | return GR_REGS; | |
5817 | break; | |
5818 | ||
5819 | case FR_REGS: | |
a71aef0b | 5820 | case FP_REGS: |
c51e6d85 | 5821 | /* Need to go through general registers to get to other class regs. */ |
7109d286 RH |
5822 | if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno))) |
5823 | return GR_REGS; | |
9c808aad | 5824 | |
97e242b0 RH |
5825 | /* This can happen when a paradoxical subreg is an operand to the |
5826 | muldi3 pattern. */ | |
5827 | /* ??? This shouldn't be necessary after instruction scheduling is | |
5828 | enabled, because paradoxical subregs are not accepted by | |
5829 | register_operand when INSN_SCHEDULING is defined. Or alternatively, | |
5830 | stop the paradoxical subreg stupidity in the *_operand functions | |
5831 | in recog.c. */ | |
5832 | if (GET_CODE (x) == MEM | |
5833 | && (GET_MODE (x) == SImode || GET_MODE (x) == HImode | |
5834 | || GET_MODE (x) == QImode)) | |
5835 | return GR_REGS; | |
5836 | ||
5837 | /* This can happen because of the ior/and/etc patterns that accept FP | |
5838 | registers as operands. If the third operand is a constant, then it | |
5839 | needs to be reloaded into a FP register. */ | |
5840 | if (GET_CODE (x) == CONST_INT) | |
5841 | return GR_REGS; | |
5842 | ||
5843 | /* This can happen because of register elimination in a muldi3 insn. | |
5844 | E.g. `26107 * (unsigned long)&u'. */ | |
5845 | if (GET_CODE (x) == PLUS) | |
5846 | return GR_REGS; | |
5847 | break; | |
5848 | ||
5849 | case PR_REGS: | |
f2f90c63 | 5850 | /* ??? This happens if we cse/gcse a BImode value across a call, |
97e242b0 RH |
5851 | and the function has a nonlocal goto. This is because global |
5852 | does not allocate call crossing pseudos to hard registers when | |
e3b5732b | 5853 | crtl->has_nonlocal_goto is true. This is relatively |
97e242b0 RH |
5854 | common for C++ programs that use exceptions. To reproduce, |
5855 | return NO_REGS and compile libstdc++. */ | |
5856 | if (GET_CODE (x) == MEM) | |
5857 | return GR_REGS; | |
f2f90c63 RH |
5858 | |
5859 | /* This can happen when we take a BImode subreg of a DImode value, | |
5860 | and that DImode value winds up in some non-GR register. */ | |
5861 | if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno)) | |
5862 | return GR_REGS; | |
97e242b0 RH |
5863 | break; |
5864 | ||
5865 | default: | |
5866 | break; | |
5867 | } | |
c65ebc55 JW |
5868 | |
5869 | return NO_REGS; | |
5870 | } | |
5871 | ||
215b063c PB |
5872 | \f |
5873 | /* Implement targetm.unspec_may_trap_p hook. */ | |
5874 | static int | |
5875 | ia64_unspec_may_trap_p (const_rtx x, unsigned flags) | |
5876 | { | |
c84a808e EB |
5877 | switch (XINT (x, 1)) |
5878 | { | |
5879 | case UNSPEC_LDA: | |
5880 | case UNSPEC_LDS: | |
5881 | case UNSPEC_LDSA: | |
5882 | case UNSPEC_LDCCLR: | |
5883 | case UNSPEC_CHKACLR: | |
5884 | case UNSPEC_CHKS: | |
5885 | /* These unspecs are just wrappers. */ | |
5886 | return may_trap_p_1 (XVECEXP (x, 0, 0), flags); | |
215b063c PB |
5887 | } |
5888 | ||
5889 | return default_unspec_may_trap_p (x, flags); | |
5890 | } | |
5891 | ||
c65ebc55 JW |
5892 | \f |
5893 | /* Parse the -mfixed-range= option string. */ | |
5894 | ||
5895 | static void | |
9c808aad | 5896 | fix_range (const char *const_str) |
c65ebc55 JW |
5897 | { |
5898 | int i, first, last; | |
3b572406 | 5899 | char *str, *dash, *comma; |
c65ebc55 JW |
5900 | |
5901 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
5902 | REG2 are either register names or register numbers. The effect | |
5903 | of this option is to mark the registers in the range from REG1 to | |
5904 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
5905 | used, e.g., to ensure that kernel mode code doesn't use f32-f127. */ | |
5906 | ||
3b572406 RH |
5907 | i = strlen (const_str); |
5908 | str = (char *) alloca (i + 1); | |
5909 | memcpy (str, const_str, i + 1); | |
5910 | ||
c65ebc55 JW |
5911 | while (1) |
5912 | { | |
5913 | dash = strchr (str, '-'); | |
5914 | if (!dash) | |
5915 | { | |
d4ee4d25 | 5916 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
c65ebc55 JW |
5917 | return; |
5918 | } | |
5919 | *dash = '\0'; | |
5920 | ||
5921 | comma = strchr (dash + 1, ','); | |
5922 | if (comma) | |
5923 | *comma = '\0'; | |
5924 | ||
5925 | first = decode_reg_name (str); | |
5926 | if (first < 0) | |
5927 | { | |
d4ee4d25 | 5928 | warning (0, "unknown register name: %s", str); |
c65ebc55 JW |
5929 | return; |
5930 | } | |
5931 | ||
5932 | last = decode_reg_name (dash + 1); | |
5933 | if (last < 0) | |
5934 | { | |
d4ee4d25 | 5935 | warning (0, "unknown register name: %s", dash + 1); |
c65ebc55 JW |
5936 | return; |
5937 | } | |
5938 | ||
5939 | *dash = '-'; | |
5940 | ||
5941 | if (first > last) | |
5942 | { | |
d4ee4d25 | 5943 | warning (0, "%s-%s is an empty range", str, dash + 1); |
c65ebc55 JW |
5944 | return; |
5945 | } | |
5946 | ||
5947 | for (i = first; i <= last; ++i) | |
5948 | fixed_regs[i] = call_used_regs[i] = 1; | |
5949 | ||
5950 | if (!comma) | |
5951 | break; | |
5952 | ||
5953 | *comma = ','; | |
5954 | str = comma + 1; | |
5955 | } | |
5956 | } | |
5957 | ||
930572b9 | 5958 | /* Implement TARGET_OPTION_OVERRIDE. */ |
c65ebc55 | 5959 | |
930572b9 AS |
5960 | static void |
5961 | ia64_option_override (void) | |
c65ebc55 | 5962 | { |
e6cc0c98 JM |
5963 | unsigned int i; |
5964 | cl_deferred_option *opt; | |
9771b263 DN |
5965 | vec<cl_deferred_option> *v |
5966 | = (vec<cl_deferred_option> *) ia64_deferred_options; | |
e6cc0c98 | 5967 | |
9771b263 DN |
5968 | if (v) |
5969 | FOR_EACH_VEC_ELT (*v, i, opt) | |
5970 | { | |
5971 | switch (opt->opt_index) | |
5972 | { | |
5973 | case OPT_mfixed_range_: | |
5974 | fix_range (opt->arg); | |
5975 | break; | |
e6cc0c98 | 5976 | |
9771b263 DN |
5977 | default: |
5978 | gcc_unreachable (); | |
5979 | } | |
5980 | } | |
e6cc0c98 | 5981 | |
59da9a7d JW |
5982 | if (TARGET_AUTO_PIC) |
5983 | target_flags |= MASK_CONST_GP; | |
5984 | ||
7e1e7d4c VM |
5985 | /* Numerous experiment shows that IRA based loop pressure |
5986 | calculation works better for RTL loop invariant motion on targets | |
5987 | with enough (>= 32) registers. It is an expensive optimization. | |
5988 | So it is on only for peak performance. */ | |
5989 | if (optimize >= 3) | |
5990 | flag_ira_loop_pressure = 1; | |
5991 | ||
5992 | ||
fa37ed29 JM |
5993 | ia64_section_threshold = (global_options_set.x_g_switch_value |
5994 | ? g_switch_value | |
5995 | : IA64_DEFAULT_GVALUE); | |
2b7e2984 SE |
5996 | |
5997 | init_machine_status = ia64_init_machine_status; | |
5998 | ||
5999 | if (align_functions <= 0) | |
6000 | align_functions = 64; | |
6001 | if (align_loops <= 0) | |
6002 | align_loops = 32; | |
6003 | if (TARGET_ABI_OPEN_VMS) | |
6004 | flag_no_common = 1; | |
6005 | ||
6006 | ia64_override_options_after_change(); | |
6007 | } | |
6008 | ||
6009 | /* Implement targetm.override_options_after_change. */ | |
6010 | ||
6011 | static void | |
6012 | ia64_override_options_after_change (void) | |
6013 | { | |
388092d5 | 6014 | if (optimize >= 3 |
d4d24ba4 JM |
6015 | && !global_options_set.x_flag_selective_scheduling |
6016 | && !global_options_set.x_flag_selective_scheduling2) | |
388092d5 AB |
6017 | { |
6018 | flag_selective_scheduling2 = 1; | |
6019 | flag_sel_sched_pipelining = 1; | |
6020 | } | |
6021 | if (mflag_sched_control_spec == 2) | |
6022 | { | |
6023 | /* Control speculation is on by default for the selective scheduler, | |
6024 | but not for the Haifa scheduler. */ | |
6025 | mflag_sched_control_spec = flag_selective_scheduling2 ? 1 : 0; | |
6026 | } | |
6027 | if (flag_sel_sched_pipelining && flag_auto_inc_dec) | |
6028 | { | |
6029 | /* FIXME: remove this when we'd implement breaking autoinsns as | |
6030 | a transformation. */ | |
6031 | flag_auto_inc_dec = 0; | |
6032 | } | |
c65ebc55 | 6033 | } |
dbdd120f | 6034 | |
6fb5fa3c DB |
6035 | /* Initialize the record of emitted frame related registers. */ |
6036 | ||
6037 | void ia64_init_expanders (void) | |
6038 | { | |
6039 | memset (&emitted_frame_related_regs, 0, sizeof (emitted_frame_related_regs)); | |
6040 | } | |
6041 | ||
dbdd120f RH |
6042 | static struct machine_function * |
6043 | ia64_init_machine_status (void) | |
6044 | { | |
766090c2 | 6045 | return ggc_cleared_alloc<machine_function> (); |
dbdd120f | 6046 | } |
c65ebc55 | 6047 | \f |
9c808aad AJ |
6048 | static enum attr_itanium_class ia64_safe_itanium_class (rtx); |
6049 | static enum attr_type ia64_safe_type (rtx); | |
2130b7fb | 6050 | |
2130b7fb | 6051 | static enum attr_itanium_class |
9c808aad | 6052 | ia64_safe_itanium_class (rtx insn) |
2130b7fb BS |
6053 | { |
6054 | if (recog_memoized (insn) >= 0) | |
6055 | return get_attr_itanium_class (insn); | |
b5b8b0ac AO |
6056 | else if (DEBUG_INSN_P (insn)) |
6057 | return ITANIUM_CLASS_IGNORE; | |
2130b7fb BS |
6058 | else |
6059 | return ITANIUM_CLASS_UNKNOWN; | |
6060 | } | |
6061 | ||
6062 | static enum attr_type | |
9c808aad | 6063 | ia64_safe_type (rtx insn) |
2130b7fb BS |
6064 | { |
6065 | if (recog_memoized (insn) >= 0) | |
6066 | return get_attr_type (insn); | |
6067 | else | |
6068 | return TYPE_UNKNOWN; | |
6069 | } | |
6070 | \f | |
c65ebc55 JW |
6071 | /* The following collection of routines emit instruction group stop bits as |
6072 | necessary to avoid dependencies. */ | |
6073 | ||
6074 | /* Need to track some additional registers as far as serialization is | |
6075 | concerned so we can properly handle br.call and br.ret. We could | |
6076 | make these registers visible to gcc, but since these registers are | |
6077 | never explicitly used in gcc generated code, it seems wasteful to | |
6078 | do so (plus it would make the call and return patterns needlessly | |
6079 | complex). */ | |
c65ebc55 | 6080 | #define REG_RP (BR_REG (0)) |
c65ebc55 | 6081 | #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1) |
c65ebc55 JW |
6082 | /* This is used for volatile asms which may require a stop bit immediately |
6083 | before and after them. */ | |
5527bf14 | 6084 | #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2) |
870f9ec0 RH |
6085 | #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3) |
6086 | #define NUM_REGS (AR_UNAT_BIT_0 + 64) | |
c65ebc55 | 6087 | |
f2f90c63 RH |
6088 | /* For each register, we keep track of how it has been written in the |
6089 | current instruction group. | |
6090 | ||
6091 | If a register is written unconditionally (no qualifying predicate), | |
6092 | WRITE_COUNT is set to 2 and FIRST_PRED is ignored. | |
6093 | ||
6094 | If a register is written if its qualifying predicate P is true, we | |
6095 | set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register | |
6096 | may be written again by the complement of P (P^1) and when this happens, | |
6097 | WRITE_COUNT gets set to 2. | |
6098 | ||
6099 | The result of this is that whenever an insn attempts to write a register | |
e03f5d43 | 6100 | whose WRITE_COUNT is two, we need to issue an insn group barrier first. |
f2f90c63 RH |
6101 | |
6102 | If a predicate register is written by a floating-point insn, we set | |
6103 | WRITTEN_BY_FP to true. | |
6104 | ||
6105 | If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND | |
6106 | to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */ | |
6107 | ||
444a356a JJ |
6108 | #if GCC_VERSION >= 4000 |
6109 | #define RWS_FIELD_TYPE __extension__ unsigned short | |
6110 | #else | |
6111 | #define RWS_FIELD_TYPE unsigned int | |
6112 | #endif | |
c65ebc55 JW |
6113 | struct reg_write_state |
6114 | { | |
444a356a JJ |
6115 | RWS_FIELD_TYPE write_count : 2; |
6116 | RWS_FIELD_TYPE first_pred : 10; | |
6117 | RWS_FIELD_TYPE written_by_fp : 1; | |
6118 | RWS_FIELD_TYPE written_by_and : 1; | |
6119 | RWS_FIELD_TYPE written_by_or : 1; | |
c65ebc55 JW |
6120 | }; |
6121 | ||
6122 | /* Cumulative info for the current instruction group. */ | |
6123 | struct reg_write_state rws_sum[NUM_REGS]; | |
444a356a JJ |
6124 | #ifdef ENABLE_CHECKING |
6125 | /* Bitmap whether a register has been written in the current insn. */ | |
6126 | HARD_REG_ELT_TYPE rws_insn[(NUM_REGS + HOST_BITS_PER_WIDEST_FAST_INT - 1) | |
6127 | / HOST_BITS_PER_WIDEST_FAST_INT]; | |
6128 | ||
6129 | static inline void | |
6130 | rws_insn_set (int regno) | |
6131 | { | |
6132 | gcc_assert (!TEST_HARD_REG_BIT (rws_insn, regno)); | |
6133 | SET_HARD_REG_BIT (rws_insn, regno); | |
6134 | } | |
6135 | ||
6136 | static inline int | |
6137 | rws_insn_test (int regno) | |
6138 | { | |
6139 | return TEST_HARD_REG_BIT (rws_insn, regno); | |
6140 | } | |
6141 | #else | |
6142 | /* When not checking, track just REG_AR_CFM and REG_VOLATILE. */ | |
6143 | unsigned char rws_insn[2]; | |
6144 | ||
6145 | static inline void | |
6146 | rws_insn_set (int regno) | |
6147 | { | |
6148 | if (regno == REG_AR_CFM) | |
6149 | rws_insn[0] = 1; | |
6150 | else if (regno == REG_VOLATILE) | |
6151 | rws_insn[1] = 1; | |
6152 | } | |
6153 | ||
6154 | static inline int | |
6155 | rws_insn_test (int regno) | |
6156 | { | |
6157 | if (regno == REG_AR_CFM) | |
6158 | return rws_insn[0]; | |
6159 | if (regno == REG_VOLATILE) | |
6160 | return rws_insn[1]; | |
6161 | return 0; | |
6162 | } | |
6163 | #endif | |
c65ebc55 | 6164 | |
25250265 | 6165 | /* Indicates whether this is the first instruction after a stop bit, |
e820471b NS |
6166 | in which case we don't need another stop bit. Without this, |
6167 | ia64_variable_issue will die when scheduling an alloc. */ | |
25250265 JW |
6168 | static int first_instruction; |
6169 | ||
c65ebc55 JW |
6170 | /* Misc flags needed to compute RAW/WAW dependencies while we are traversing |
6171 | RTL for one instruction. */ | |
6172 | struct reg_flags | |
6173 | { | |
6174 | unsigned int is_write : 1; /* Is register being written? */ | |
6175 | unsigned int is_fp : 1; /* Is register used as part of an fp op? */ | |
6176 | unsigned int is_branch : 1; /* Is register used as part of a branch? */ | |
f2f90c63 RH |
6177 | unsigned int is_and : 1; /* Is register used as part of and.orcm? */ |
6178 | unsigned int is_or : 1; /* Is register used as part of or.andcm? */ | |
2ed4af6f | 6179 | unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */ |
c65ebc55 JW |
6180 | }; |
6181 | ||
444a356a | 6182 | static void rws_update (int, struct reg_flags, int); |
9c808aad AJ |
6183 | static int rws_access_regno (int, struct reg_flags, int); |
6184 | static int rws_access_reg (rtx, struct reg_flags, int); | |
c1bc6ca8 JW |
6185 | static void update_set_flags (rtx, struct reg_flags *); |
6186 | static int set_src_needs_barrier (rtx, struct reg_flags, int); | |
9c808aad AJ |
6187 | static int rtx_needs_barrier (rtx, struct reg_flags, int); |
6188 | static void init_insn_group_barriers (void); | |
c1bc6ca8 JW |
6189 | static int group_barrier_needed (rtx); |
6190 | static int safe_group_barrier_needed (rtx); | |
444a356a | 6191 | static int in_safe_group_barrier; |
3b572406 | 6192 | |
c65ebc55 JW |
6193 | /* Update *RWS for REGNO, which is being written by the current instruction, |
6194 | with predicate PRED, and associated register flags in FLAGS. */ | |
6195 | ||
6196 | static void | |
444a356a | 6197 | rws_update (int regno, struct reg_flags flags, int pred) |
c65ebc55 | 6198 | { |
3e7c7805 | 6199 | if (pred) |
444a356a | 6200 | rws_sum[regno].write_count++; |
3e7c7805 | 6201 | else |
444a356a JJ |
6202 | rws_sum[regno].write_count = 2; |
6203 | rws_sum[regno].written_by_fp |= flags.is_fp; | |
f2f90c63 | 6204 | /* ??? Not tracking and/or across differing predicates. */ |
444a356a JJ |
6205 | rws_sum[regno].written_by_and = flags.is_and; |
6206 | rws_sum[regno].written_by_or = flags.is_or; | |
6207 | rws_sum[regno].first_pred = pred; | |
c65ebc55 JW |
6208 | } |
6209 | ||
6210 | /* Handle an access to register REGNO of type FLAGS using predicate register | |
444a356a | 6211 | PRED. Update rws_sum array. Return 1 if this access creates |
c65ebc55 JW |
6212 | a dependency with an earlier instruction in the same group. */ |
6213 | ||
6214 | static int | |
9c808aad | 6215 | rws_access_regno (int regno, struct reg_flags flags, int pred) |
c65ebc55 JW |
6216 | { |
6217 | int need_barrier = 0; | |
c65ebc55 | 6218 | |
e820471b | 6219 | gcc_assert (regno < NUM_REGS); |
c65ebc55 | 6220 | |
f2f90c63 RH |
6221 | if (! PR_REGNO_P (regno)) |
6222 | flags.is_and = flags.is_or = 0; | |
6223 | ||
c65ebc55 JW |
6224 | if (flags.is_write) |
6225 | { | |
12c2c7aa JW |
6226 | int write_count; |
6227 | ||
444a356a | 6228 | rws_insn_set (regno); |
12c2c7aa | 6229 | write_count = rws_sum[regno].write_count; |
12c2c7aa JW |
6230 | |
6231 | switch (write_count) | |
c65ebc55 JW |
6232 | { |
6233 | case 0: | |
6234 | /* The register has not been written yet. */ | |
444a356a JJ |
6235 | if (!in_safe_group_barrier) |
6236 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6237 | break; |
6238 | ||
6239 | case 1: | |
89774469 SE |
6240 | /* The register has been written via a predicate. Treat |
6241 | it like a unconditional write and do not try to check | |
6242 | for complementary pred reg in earlier write. */ | |
f2f90c63 | 6243 | if (flags.is_and && rws_sum[regno].written_by_and) |
9c808aad | 6244 | ; |
f2f90c63 RH |
6245 | else if (flags.is_or && rws_sum[regno].written_by_or) |
6246 | ; | |
89774469 | 6247 | else |
c65ebc55 | 6248 | need_barrier = 1; |
444a356a JJ |
6249 | if (!in_safe_group_barrier) |
6250 | rws_update (regno, flags, pred); | |
c65ebc55 JW |
6251 | break; |
6252 | ||
6253 | case 2: | |
6254 | /* The register has been unconditionally written already. We | |
6255 | need a barrier. */ | |
f2f90c63 RH |
6256 | if (flags.is_and && rws_sum[regno].written_by_and) |
6257 | ; | |
6258 | else if (flags.is_or && rws_sum[regno].written_by_or) | |
6259 | ; | |
6260 | else | |
6261 | need_barrier = 1; | |
444a356a JJ |
6262 | if (!in_safe_group_barrier) |
6263 | { | |
6264 | rws_sum[regno].written_by_and = flags.is_and; | |
6265 | rws_sum[regno].written_by_or = flags.is_or; | |
6266 | } | |
c65ebc55 JW |
6267 | break; |
6268 | ||
6269 | default: | |
e820471b | 6270 | gcc_unreachable (); |
c65ebc55 JW |
6271 | } |
6272 | } | |
6273 | else | |
6274 | { | |
6275 | if (flags.is_branch) | |
6276 | { | |
6277 | /* Branches have several RAW exceptions that allow to avoid | |
6278 | barriers. */ | |
6279 | ||
5527bf14 | 6280 | if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM) |
c65ebc55 JW |
6281 | /* RAW dependencies on branch regs are permissible as long |
6282 | as the writer is a non-branch instruction. Since we | |
6283 | never generate code that uses a branch register written | |
6284 | by a branch instruction, handling this case is | |
6285 | easy. */ | |
5527bf14 | 6286 | return 0; |
c65ebc55 JW |
6287 | |
6288 | if (REGNO_REG_CLASS (regno) == PR_REGS | |
6289 | && ! rws_sum[regno].written_by_fp) | |
6290 | /* The predicates of a branch are available within the | |
6291 | same insn group as long as the predicate was written by | |
ed168e45 | 6292 | something other than a floating-point instruction. */ |
c65ebc55 JW |
6293 | return 0; |
6294 | } | |
6295 | ||
f2f90c63 RH |
6296 | if (flags.is_and && rws_sum[regno].written_by_and) |
6297 | return 0; | |
6298 | if (flags.is_or && rws_sum[regno].written_by_or) | |
6299 | return 0; | |
6300 | ||
c65ebc55 JW |
6301 | switch (rws_sum[regno].write_count) |
6302 | { | |
6303 | case 0: | |
6304 | /* The register has not been written yet. */ | |
6305 | break; | |
6306 | ||
6307 | case 1: | |
89774469 SE |
6308 | /* The register has been written via a predicate, assume we |
6309 | need a barrier (don't check for complementary regs). */ | |
6310 | need_barrier = 1; | |
c65ebc55 JW |
6311 | break; |
6312 | ||
6313 | case 2: | |
6314 | /* The register has been unconditionally written already. We | |
6315 | need a barrier. */ | |
6316 | need_barrier = 1; | |
6317 | break; | |
6318 | ||
6319 | default: | |
e820471b | 6320 | gcc_unreachable (); |
c65ebc55 JW |
6321 | } |
6322 | } | |
6323 | ||
6324 | return need_barrier; | |
6325 | } | |
6326 | ||
97e242b0 | 6327 | static int |
9c808aad | 6328 | rws_access_reg (rtx reg, struct reg_flags flags, int pred) |
97e242b0 RH |
6329 | { |
6330 | int regno = REGNO (reg); | |
6331 | int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); | |
6332 | ||
6333 | if (n == 1) | |
6334 | return rws_access_regno (regno, flags, pred); | |
6335 | else | |
6336 | { | |
6337 | int need_barrier = 0; | |
6338 | while (--n >= 0) | |
6339 | need_barrier |= rws_access_regno (regno + n, flags, pred); | |
6340 | return need_barrier; | |
6341 | } | |
6342 | } | |
6343 | ||
112333d3 BS |
6344 | /* Examine X, which is a SET rtx, and update the flags, the predicate, and |
6345 | the condition, stored in *PFLAGS, *PPRED and *PCOND. */ | |
6346 | ||
6347 | static void | |
c1bc6ca8 | 6348 | update_set_flags (rtx x, struct reg_flags *pflags) |
112333d3 BS |
6349 | { |
6350 | rtx src = SET_SRC (x); | |
6351 | ||
112333d3 BS |
6352 | switch (GET_CODE (src)) |
6353 | { | |
6354 | case CALL: | |
6355 | return; | |
6356 | ||
6357 | case IF_THEN_ELSE: | |
048d0d36 | 6358 | /* There are four cases here: |
c8d3810f RH |
6359 | (1) The destination is (pc), in which case this is a branch, |
6360 | nothing here applies. | |
6361 | (2) The destination is ar.lc, in which case this is a | |
6362 | doloop_end_internal, | |
6363 | (3) The destination is an fp register, in which case this is | |
6364 | an fselect instruction. | |
048d0d36 MK |
6365 | (4) The condition has (unspec [(reg)] UNSPEC_LDC), in which case |
6366 | this is a check load. | |
c8d3810f RH |
6367 | In all cases, nothing we do in this function applies. */ |
6368 | return; | |
112333d3 BS |
6369 | |
6370 | default: | |
ec8e098d | 6371 | if (COMPARISON_P (src) |
c8d3810f | 6372 | && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0)))) |
112333d3 BS |
6373 | /* Set pflags->is_fp to 1 so that we know we're dealing |
6374 | with a floating point comparison when processing the | |
6375 | destination of the SET. */ | |
6376 | pflags->is_fp = 1; | |
6377 | ||
6378 | /* Discover if this is a parallel comparison. We only handle | |
6379 | and.orcm and or.andcm at present, since we must retain a | |
6380 | strict inverse on the predicate pair. */ | |
6381 | else if (GET_CODE (src) == AND) | |
6382 | pflags->is_and = 1; | |
6383 | else if (GET_CODE (src) == IOR) | |
6384 | pflags->is_or = 1; | |
6385 | ||
6386 | break; | |
6387 | } | |
6388 | } | |
6389 | ||
6390 | /* Subroutine of rtx_needs_barrier; this function determines whether the | |
6391 | source of a given SET rtx found in X needs a barrier. FLAGS and PRED | |
6392 | are as in rtx_needs_barrier. COND is an rtx that holds the condition | |
6393 | for this insn. */ | |
9c808aad | 6394 | |
112333d3 | 6395 | static int |
c1bc6ca8 | 6396 | set_src_needs_barrier (rtx x, struct reg_flags flags, int pred) |
112333d3 BS |
6397 | { |
6398 | int need_barrier = 0; | |
6399 | rtx dst; | |
6400 | rtx src = SET_SRC (x); | |
6401 | ||
6402 | if (GET_CODE (src) == CALL) | |
6403 | /* We don't need to worry about the result registers that | |
6404 | get written by subroutine call. */ | |
6405 | return rtx_needs_barrier (src, flags, pred); | |
6406 | else if (SET_DEST (x) == pc_rtx) | |
6407 | { | |
6408 | /* X is a conditional branch. */ | |
6409 | /* ??? This seems redundant, as the caller sets this bit for | |
6410 | all JUMP_INSNs. */ | |
048d0d36 MK |
6411 | if (!ia64_spec_check_src_p (src)) |
6412 | flags.is_branch = 1; | |
112333d3 BS |
6413 | return rtx_needs_barrier (src, flags, pred); |
6414 | } | |
6415 | ||
048d0d36 MK |
6416 | if (ia64_spec_check_src_p (src)) |
6417 | /* Avoid checking one register twice (in condition | |
6418 | and in 'then' section) for ldc pattern. */ | |
6419 | { | |
6420 | gcc_assert (REG_P (XEXP (src, 2))); | |
6421 | need_barrier = rtx_needs_barrier (XEXP (src, 2), flags, pred); | |
6422 | ||
6423 | /* We process MEM below. */ | |
6424 | src = XEXP (src, 1); | |
6425 | } | |
6426 | ||
6427 | need_barrier |= rtx_needs_barrier (src, flags, pred); | |
112333d3 | 6428 | |
112333d3 BS |
6429 | dst = SET_DEST (x); |
6430 | if (GET_CODE (dst) == ZERO_EXTRACT) | |
6431 | { | |
6432 | need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred); | |
6433 | need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred); | |
112333d3 BS |
6434 | } |
6435 | return need_barrier; | |
6436 | } | |
6437 | ||
b38ba463 ZW |
6438 | /* Handle an access to rtx X of type FLAGS using predicate register |
6439 | PRED. Return 1 if this access creates a dependency with an earlier | |
6440 | instruction in the same group. */ | |
c65ebc55 JW |
6441 | |
6442 | static int | |
9c808aad | 6443 | rtx_needs_barrier (rtx x, struct reg_flags flags, int pred) |
c65ebc55 JW |
6444 | { |
6445 | int i, j; | |
6446 | int is_complemented = 0; | |
6447 | int need_barrier = 0; | |
6448 | const char *format_ptr; | |
6449 | struct reg_flags new_flags; | |
c1bc6ca8 | 6450 | rtx cond; |
c65ebc55 JW |
6451 | |
6452 | if (! x) | |
6453 | return 0; | |
6454 | ||
6455 | new_flags = flags; | |
6456 | ||
6457 | switch (GET_CODE (x)) | |
6458 | { | |
9c808aad | 6459 | case SET: |
c1bc6ca8 JW |
6460 | update_set_flags (x, &new_flags); |
6461 | need_barrier = set_src_needs_barrier (x, new_flags, pred); | |
112333d3 | 6462 | if (GET_CODE (SET_SRC (x)) != CALL) |
c65ebc55 | 6463 | { |
112333d3 BS |
6464 | new_flags.is_write = 1; |
6465 | need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred); | |
c65ebc55 | 6466 | } |
c65ebc55 JW |
6467 | break; |
6468 | ||
6469 | case CALL: | |
6470 | new_flags.is_write = 0; | |
97e242b0 | 6471 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
c65ebc55 JW |
6472 | |
6473 | /* Avoid multiple register writes, in case this is a pattern with | |
e820471b | 6474 | multiple CALL rtx. This avoids a failure in rws_access_reg. */ |
444a356a | 6475 | if (! flags.is_sibcall && ! rws_insn_test (REG_AR_CFM)) |
c65ebc55 JW |
6476 | { |
6477 | new_flags.is_write = 1; | |
97e242b0 RH |
6478 | need_barrier |= rws_access_regno (REG_RP, new_flags, pred); |
6479 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred); | |
6480 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6481 | } |
6482 | break; | |
6483 | ||
e5bde68a RH |
6484 | case COND_EXEC: |
6485 | /* X is a predicated instruction. */ | |
6486 | ||
6487 | cond = COND_EXEC_TEST (x); | |
e820471b | 6488 | gcc_assert (!pred); |
e5bde68a RH |
6489 | need_barrier = rtx_needs_barrier (cond, flags, 0); |
6490 | ||
6491 | if (GET_CODE (cond) == EQ) | |
6492 | is_complemented = 1; | |
6493 | cond = XEXP (cond, 0); | |
e820471b | 6494 | gcc_assert (GET_CODE (cond) == REG |
c1bc6ca8 | 6495 | && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS); |
e5bde68a RH |
6496 | pred = REGNO (cond); |
6497 | if (is_complemented) | |
6498 | ++pred; | |
6499 | ||
6500 | need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred); | |
6501 | return need_barrier; | |
6502 | ||
c65ebc55 | 6503 | case CLOBBER: |
c65ebc55 | 6504 | case USE: |
c65ebc55 JW |
6505 | /* Clobber & use are for earlier compiler-phases only. */ |
6506 | break; | |
6507 | ||
6508 | case ASM_OPERANDS: | |
6509 | case ASM_INPUT: | |
6510 | /* We always emit stop bits for traditional asms. We emit stop bits | |
6511 | for volatile extended asms if TARGET_VOL_ASM_STOP is true. */ | |
6512 | if (GET_CODE (x) != ASM_OPERANDS | |
6513 | || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP)) | |
6514 | { | |
6515 | /* Avoid writing the register multiple times if we have multiple | |
e820471b | 6516 | asm outputs. This avoids a failure in rws_access_reg. */ |
444a356a | 6517 | if (! rws_insn_test (REG_VOLATILE)) |
c65ebc55 JW |
6518 | { |
6519 | new_flags.is_write = 1; | |
97e242b0 | 6520 | rws_access_regno (REG_VOLATILE, new_flags, pred); |
c65ebc55 JW |
6521 | } |
6522 | return 1; | |
6523 | } | |
6524 | ||
6525 | /* For all ASM_OPERANDS, we must traverse the vector of input operands. | |
1e5f1716 | 6526 | We cannot just fall through here since then we would be confused |
c65ebc55 JW |
6527 | by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate |
6528 | traditional asms unlike their normal usage. */ | |
6529 | ||
6530 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i) | |
6531 | if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred)) | |
6532 | need_barrier = 1; | |
6533 | break; | |
6534 | ||
6535 | case PARALLEL: | |
6536 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
112333d3 BS |
6537 | { |
6538 | rtx pat = XVECEXP (x, 0, i); | |
051d8245 | 6539 | switch (GET_CODE (pat)) |
112333d3 | 6540 | { |
051d8245 | 6541 | case SET: |
c1bc6ca8 JW |
6542 | update_set_flags (pat, &new_flags); |
6543 | need_barrier |= set_src_needs_barrier (pat, new_flags, pred); | |
051d8245 RH |
6544 | break; |
6545 | ||
6546 | case USE: | |
6547 | case CALL: | |
6548 | case ASM_OPERANDS: | |
6549 | need_barrier |= rtx_needs_barrier (pat, flags, pred); | |
6550 | break; | |
6551 | ||
6552 | case CLOBBER: | |
628162ea JJ |
6553 | if (REG_P (XEXP (pat, 0)) |
6554 | && extract_asm_operands (x) != NULL_RTX | |
6555 | && REGNO (XEXP (pat, 0)) != AR_UNAT_REGNUM) | |
6556 | { | |
6557 | new_flags.is_write = 1; | |
6558 | need_barrier |= rtx_needs_barrier (XEXP (pat, 0), | |
6559 | new_flags, pred); | |
6560 | new_flags = flags; | |
6561 | } | |
6562 | break; | |
6563 | ||
051d8245 RH |
6564 | case RETURN: |
6565 | break; | |
6566 | ||
6567 | default: | |
6568 | gcc_unreachable (); | |
112333d3 | 6569 | } |
112333d3 BS |
6570 | } |
6571 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) | |
6572 | { | |
6573 | rtx pat = XVECEXP (x, 0, i); | |
6574 | if (GET_CODE (pat) == SET) | |
6575 | { | |
6576 | if (GET_CODE (SET_SRC (pat)) != CALL) | |
6577 | { | |
6578 | new_flags.is_write = 1; | |
6579 | need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags, | |
6580 | pred); | |
6581 | } | |
6582 | } | |
339cb12e | 6583 | else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN) |
112333d3 BS |
6584 | need_barrier |= rtx_needs_barrier (pat, flags, pred); |
6585 | } | |
c65ebc55 JW |
6586 | break; |
6587 | ||
6588 | case SUBREG: | |
077bc924 JM |
6589 | need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred); |
6590 | break; | |
c65ebc55 | 6591 | case REG: |
870f9ec0 RH |
6592 | if (REGNO (x) == AR_UNAT_REGNUM) |
6593 | { | |
6594 | for (i = 0; i < 64; ++i) | |
6595 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred); | |
6596 | } | |
6597 | else | |
6598 | need_barrier = rws_access_reg (x, flags, pred); | |
c65ebc55 JW |
6599 | break; |
6600 | ||
6601 | case MEM: | |
6602 | /* Find the regs used in memory address computation. */ | |
6603 | new_flags.is_write = 0; | |
6604 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6605 | break; | |
6606 | ||
051d8245 | 6607 | case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR: |
c65ebc55 JW |
6608 | case SYMBOL_REF: case LABEL_REF: case CONST: |
6609 | break; | |
6610 | ||
6611 | /* Operators with side-effects. */ | |
6612 | case POST_INC: case POST_DEC: | |
e820471b | 6613 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
c65ebc55 JW |
6614 | |
6615 | new_flags.is_write = 0; | |
97e242b0 | 6616 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 | 6617 | new_flags.is_write = 1; |
97e242b0 | 6618 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6619 | break; |
6620 | ||
6621 | case POST_MODIFY: | |
e820471b | 6622 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); |
4b983fdc RH |
6623 | |
6624 | new_flags.is_write = 0; | |
97e242b0 | 6625 | need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred); |
4b983fdc RH |
6626 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); |
6627 | new_flags.is_write = 1; | |
97e242b0 | 6628 | need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred); |
c65ebc55 JW |
6629 | break; |
6630 | ||
6631 | /* Handle common unary and binary ops for efficiency. */ | |
6632 | case COMPARE: case PLUS: case MINUS: case MULT: case DIV: | |
6633 | case MOD: case UDIV: case UMOD: case AND: case IOR: | |
6634 | case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT: | |
6635 | case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX: | |
6636 | case NE: case EQ: case GE: case GT: case LE: | |
6637 | case LT: case GEU: case GTU: case LEU: case LTU: | |
6638 | need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred); | |
6639 | need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred); | |
6640 | break; | |
6641 | ||
6642 | case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND: | |
6643 | case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT: | |
6644 | case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS: | |
c407570a | 6645 | case SQRT: case FFS: case POPCOUNT: |
c65ebc55 JW |
6646 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6647 | break; | |
6648 | ||
051d8245 RH |
6649 | case VEC_SELECT: |
6650 | /* VEC_SELECT's second argument is a PARALLEL with integers that | |
6651 | describe the elements selected. On ia64, those integers are | |
6652 | always constants. Avoid walking the PARALLEL so that we don't | |
e820471b | 6653 | get confused with "normal" parallels and then die. */ |
051d8245 RH |
6654 | need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred); |
6655 | break; | |
6656 | ||
c65ebc55 JW |
6657 | case UNSPEC: |
6658 | switch (XINT (x, 1)) | |
6659 | { | |
7b6e506e RH |
6660 | case UNSPEC_LTOFF_DTPMOD: |
6661 | case UNSPEC_LTOFF_DTPREL: | |
6662 | case UNSPEC_DTPREL: | |
6663 | case UNSPEC_LTOFF_TPREL: | |
6664 | case UNSPEC_TPREL: | |
6665 | case UNSPEC_PRED_REL_MUTEX: | |
6666 | case UNSPEC_PIC_CALL: | |
6667 | case UNSPEC_MF: | |
6668 | case UNSPEC_FETCHADD_ACQ: | |
28875d67 | 6669 | case UNSPEC_FETCHADD_REL: |
7b6e506e RH |
6670 | case UNSPEC_BSP_VALUE: |
6671 | case UNSPEC_FLUSHRS: | |
6672 | case UNSPEC_BUNDLE_SELECTOR: | |
6673 | break; | |
6674 | ||
086c0f96 RH |
6675 | case UNSPEC_GR_SPILL: |
6676 | case UNSPEC_GR_RESTORE: | |
870f9ec0 RH |
6677 | { |
6678 | HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1)); | |
6679 | HOST_WIDE_INT bit = (offset >> 3) & 63; | |
6680 | ||
6681 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
83338d15 | 6682 | new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL); |
870f9ec0 RH |
6683 | need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit, |
6684 | new_flags, pred); | |
6685 | break; | |
6686 | } | |
9c808aad | 6687 | |
086c0f96 RH |
6688 | case UNSPEC_FR_SPILL: |
6689 | case UNSPEC_FR_RESTORE: | |
c407570a | 6690 | case UNSPEC_GETF_EXP: |
b38ba463 | 6691 | case UNSPEC_SETF_EXP: |
086c0f96 | 6692 | case UNSPEC_ADDP4: |
b38ba463 | 6693 | case UNSPEC_FR_SQRT_RECIP_APPROX: |
07acc7b3 | 6694 | case UNSPEC_FR_SQRT_RECIP_APPROX_RES: |
048d0d36 MK |
6695 | case UNSPEC_LDA: |
6696 | case UNSPEC_LDS: | |
388092d5 | 6697 | case UNSPEC_LDS_A: |
048d0d36 MK |
6698 | case UNSPEC_LDSA: |
6699 | case UNSPEC_CHKACLR: | |
6700 | case UNSPEC_CHKS: | |
6dd12198 SE |
6701 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6702 | break; | |
6703 | ||
086c0f96 | 6704 | case UNSPEC_FR_RECIP_APPROX: |
f526a3c8 | 6705 | case UNSPEC_SHRP: |
046625fa | 6706 | case UNSPEC_COPYSIGN: |
1def9c3f | 6707 | case UNSPEC_FR_RECIP_APPROX_RES: |
655f2eb9 RH |
6708 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); |
6709 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); | |
6710 | break; | |
6711 | ||
086c0f96 | 6712 | case UNSPEC_CMPXCHG_ACQ: |
28875d67 | 6713 | case UNSPEC_CMPXCHG_REL: |
0551c32d RH |
6714 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred); |
6715 | need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred); | |
6716 | break; | |
6717 | ||
c65ebc55 | 6718 | default: |
e820471b | 6719 | gcc_unreachable (); |
c65ebc55 JW |
6720 | } |
6721 | break; | |
6722 | ||
6723 | case UNSPEC_VOLATILE: | |
6724 | switch (XINT (x, 1)) | |
6725 | { | |
086c0f96 | 6726 | case UNSPECV_ALLOC: |
25250265 JW |
6727 | /* Alloc must always be the first instruction of a group. |
6728 | We force this by always returning true. */ | |
6729 | /* ??? We might get better scheduling if we explicitly check for | |
6730 | input/local/output register dependencies, and modify the | |
6731 | scheduler so that alloc is always reordered to the start of | |
6732 | the current group. We could then eliminate all of the | |
6733 | first_instruction code. */ | |
6734 | rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6735 | |
6736 | new_flags.is_write = 1; | |
25250265 JW |
6737 | rws_access_regno (REG_AR_CFM, new_flags, pred); |
6738 | return 1; | |
c65ebc55 | 6739 | |
086c0f96 | 6740 | case UNSPECV_SET_BSP: |
7b84aac0 | 6741 | case UNSPECV_PROBE_STACK_RANGE: |
3b572406 RH |
6742 | need_barrier = 1; |
6743 | break; | |
6744 | ||
086c0f96 RH |
6745 | case UNSPECV_BLOCKAGE: |
6746 | case UNSPECV_INSN_GROUP_BARRIER: | |
6747 | case UNSPECV_BREAK: | |
6748 | case UNSPECV_PSAC_ALL: | |
6749 | case UNSPECV_PSAC_NORMAL: | |
3b572406 | 6750 | return 0; |
0c96007e | 6751 | |
7b84aac0 EB |
6752 | case UNSPECV_PROBE_STACK_ADDRESS: |
6753 | need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred); | |
6754 | break; | |
6755 | ||
c65ebc55 | 6756 | default: |
e820471b | 6757 | gcc_unreachable (); |
c65ebc55 JW |
6758 | } |
6759 | break; | |
6760 | ||
6761 | case RETURN: | |
6762 | new_flags.is_write = 0; | |
97e242b0 RH |
6763 | need_barrier = rws_access_regno (REG_RP, flags, pred); |
6764 | need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred); | |
c65ebc55 JW |
6765 | |
6766 | new_flags.is_write = 1; | |
97e242b0 RH |
6767 | need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred); |
6768 | need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred); | |
c65ebc55 JW |
6769 | break; |
6770 | ||
6771 | default: | |
6772 | format_ptr = GET_RTX_FORMAT (GET_CODE (x)); | |
6773 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
6774 | switch (format_ptr[i]) | |
6775 | { | |
6776 | case '0': /* unused field */ | |
6777 | case 'i': /* integer */ | |
6778 | case 'n': /* note */ | |
6779 | case 'w': /* wide integer */ | |
6780 | case 's': /* pointer to string */ | |
6781 | case 'S': /* optional pointer to string */ | |
6782 | break; | |
6783 | ||
6784 | case 'e': | |
6785 | if (rtx_needs_barrier (XEXP (x, i), flags, pred)) | |
6786 | need_barrier = 1; | |
6787 | break; | |
6788 | ||
6789 | case 'E': | |
6790 | for (j = XVECLEN (x, i) - 1; j >= 0; --j) | |
6791 | if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred)) | |
6792 | need_barrier = 1; | |
6793 | break; | |
6794 | ||
6795 | default: | |
e820471b | 6796 | gcc_unreachable (); |
c65ebc55 | 6797 | } |
2ed4af6f | 6798 | break; |
c65ebc55 JW |
6799 | } |
6800 | return need_barrier; | |
6801 | } | |
6802 | ||
c1bc6ca8 | 6803 | /* Clear out the state for group_barrier_needed at the start of a |
2130b7fb BS |
6804 | sequence of insns. */ |
6805 | ||
6806 | static void | |
9c808aad | 6807 | init_insn_group_barriers (void) |
2130b7fb BS |
6808 | { |
6809 | memset (rws_sum, 0, sizeof (rws_sum)); | |
25250265 | 6810 | first_instruction = 1; |
2130b7fb BS |
6811 | } |
6812 | ||
c1bc6ca8 JW |
6813 | /* Given the current state, determine whether a group barrier (a stop bit) is |
6814 | necessary before INSN. Return nonzero if so. This modifies the state to | |
6815 | include the effects of INSN as a side-effect. */ | |
2130b7fb BS |
6816 | |
6817 | static int | |
c1bc6ca8 | 6818 | group_barrier_needed (rtx insn) |
2130b7fb BS |
6819 | { |
6820 | rtx pat; | |
6821 | int need_barrier = 0; | |
6822 | struct reg_flags flags; | |
6823 | ||
6824 | memset (&flags, 0, sizeof (flags)); | |
6825 | switch (GET_CODE (insn)) | |
6826 | { | |
6827 | case NOTE: | |
b5b8b0ac | 6828 | case DEBUG_INSN: |
2130b7fb BS |
6829 | break; |
6830 | ||
6831 | case BARRIER: | |
6832 | /* A barrier doesn't imply an instruction group boundary. */ | |
6833 | break; | |
6834 | ||
6835 | case CODE_LABEL: | |
6836 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6837 | return 1; | |
6838 | ||
6839 | case CALL_INSN: | |
6840 | flags.is_branch = 1; | |
6841 | flags.is_sibcall = SIBLING_CALL_P (insn); | |
6842 | memset (rws_insn, 0, sizeof (rws_insn)); | |
f12f25a7 RH |
6843 | |
6844 | /* Don't bundle a call following another call. */ | |
b64925dc | 6845 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6846 | { |
6847 | need_barrier = 1; | |
6848 | break; | |
6849 | } | |
6850 | ||
2130b7fb BS |
6851 | need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0); |
6852 | break; | |
6853 | ||
6854 | case JUMP_INSN: | |
048d0d36 MK |
6855 | if (!ia64_spec_check_p (insn)) |
6856 | flags.is_branch = 1; | |
f12f25a7 RH |
6857 | |
6858 | /* Don't bundle a jump following a call. */ | |
b64925dc | 6859 | if ((pat = prev_active_insn (insn)) && CALL_P (pat)) |
f12f25a7 RH |
6860 | { |
6861 | need_barrier = 1; | |
6862 | break; | |
6863 | } | |
5efb1046 | 6864 | /* FALLTHRU */ |
2130b7fb BS |
6865 | |
6866 | case INSN: | |
6867 | if (GET_CODE (PATTERN (insn)) == USE | |
6868 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
6869 | /* Don't care about USE and CLOBBER "insns"---those are used to | |
6870 | indicate to the optimizer that it shouldn't get rid of | |
6871 | certain operations. */ | |
6872 | break; | |
6873 | ||
6874 | pat = PATTERN (insn); | |
6875 | ||
6876 | /* Ug. Hack hacks hacked elsewhere. */ | |
6877 | switch (recog_memoized (insn)) | |
6878 | { | |
6879 | /* We play dependency tricks with the epilogue in order | |
6880 | to get proper schedules. Undo this for dv analysis. */ | |
6881 | case CODE_FOR_epilogue_deallocate_stack: | |
bdbe5b8d | 6882 | case CODE_FOR_prologue_allocate_stack: |
2130b7fb BS |
6883 | pat = XVECEXP (pat, 0, 0); |
6884 | break; | |
6885 | ||
6886 | /* The pattern we use for br.cloop confuses the code above. | |
6887 | The second element of the vector is representative. */ | |
6888 | case CODE_FOR_doloop_end_internal: | |
6889 | pat = XVECEXP (pat, 0, 1); | |
6890 | break; | |
6891 | ||
6892 | /* Doesn't generate code. */ | |
6893 | case CODE_FOR_pred_rel_mutex: | |
d0e82870 | 6894 | case CODE_FOR_prologue_use: |
2130b7fb BS |
6895 | return 0; |
6896 | ||
6897 | default: | |
6898 | break; | |
6899 | } | |
6900 | ||
6901 | memset (rws_insn, 0, sizeof (rws_insn)); | |
6902 | need_barrier = rtx_needs_barrier (pat, flags, 0); | |
6903 | ||
6904 | /* Check to see if the previous instruction was a volatile | |
6905 | asm. */ | |
6906 | if (! need_barrier) | |
6907 | need_barrier = rws_access_regno (REG_VOLATILE, flags, 0); | |
388092d5 | 6908 | |
2130b7fb BS |
6909 | break; |
6910 | ||
6911 | default: | |
e820471b | 6912 | gcc_unreachable (); |
2130b7fb | 6913 | } |
25250265 | 6914 | |
7b84aac0 | 6915 | if (first_instruction && important_for_bundling_p (insn)) |
25250265 JW |
6916 | { |
6917 | need_barrier = 0; | |
6918 | first_instruction = 0; | |
6919 | } | |
6920 | ||
2130b7fb BS |
6921 | return need_barrier; |
6922 | } | |
6923 | ||
c1bc6ca8 | 6924 | /* Like group_barrier_needed, but do not clobber the current state. */ |
2130b7fb BS |
6925 | |
6926 | static int | |
c1bc6ca8 | 6927 | safe_group_barrier_needed (rtx insn) |
2130b7fb | 6928 | { |
25250265 | 6929 | int saved_first_instruction; |
2130b7fb | 6930 | int t; |
25250265 | 6931 | |
25250265 | 6932 | saved_first_instruction = first_instruction; |
444a356a | 6933 | in_safe_group_barrier = 1; |
25250265 | 6934 | |
c1bc6ca8 | 6935 | t = group_barrier_needed (insn); |
25250265 | 6936 | |
25250265 | 6937 | first_instruction = saved_first_instruction; |
444a356a | 6938 | in_safe_group_barrier = 0; |
25250265 | 6939 | |
2130b7fb BS |
6940 | return t; |
6941 | } | |
6942 | ||
18dbd950 RS |
6943 | /* Scan the current function and insert stop bits as necessary to |
6944 | eliminate dependencies. This function assumes that a final | |
6945 | instruction scheduling pass has been run which has already | |
6946 | inserted most of the necessary stop bits. This function only | |
6947 | inserts new ones at basic block boundaries, since these are | |
6948 | invisible to the scheduler. */ | |
2130b7fb BS |
6949 | |
6950 | static void | |
9c808aad | 6951 | emit_insn_group_barriers (FILE *dump) |
2130b7fb BS |
6952 | { |
6953 | rtx insn; | |
6954 | rtx last_label = 0; | |
6955 | int insns_since_last_label = 0; | |
6956 | ||
6957 | init_insn_group_barriers (); | |
6958 | ||
18dbd950 | 6959 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
2130b7fb | 6960 | { |
b64925dc | 6961 | if (LABEL_P (insn)) |
2130b7fb BS |
6962 | { |
6963 | if (insns_since_last_label) | |
6964 | last_label = insn; | |
6965 | insns_since_last_label = 0; | |
6966 | } | |
b64925dc | 6967 | else if (NOTE_P (insn) |
a38e7aa5 | 6968 | && NOTE_KIND (insn) == NOTE_INSN_BASIC_BLOCK) |
2130b7fb BS |
6969 | { |
6970 | if (insns_since_last_label) | |
6971 | last_label = insn; | |
6972 | insns_since_last_label = 0; | |
6973 | } | |
b64925dc | 6974 | else if (NONJUMP_INSN_P (insn) |
2130b7fb | 6975 | && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE |
086c0f96 | 6976 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) |
2130b7fb BS |
6977 | { |
6978 | init_insn_group_barriers (); | |
6979 | last_label = 0; | |
6980 | } | |
b5b8b0ac | 6981 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb BS |
6982 | { |
6983 | insns_since_last_label = 1; | |
6984 | ||
c1bc6ca8 | 6985 | if (group_barrier_needed (insn)) |
2130b7fb BS |
6986 | { |
6987 | if (last_label) | |
6988 | { | |
6989 | if (dump) | |
6990 | fprintf (dump, "Emitting stop before label %d\n", | |
6991 | INSN_UID (last_label)); | |
6992 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label); | |
6993 | insn = last_label; | |
112333d3 BS |
6994 | |
6995 | init_insn_group_barriers (); | |
6996 | last_label = 0; | |
2130b7fb | 6997 | } |
2130b7fb BS |
6998 | } |
6999 | } | |
7000 | } | |
7001 | } | |
f4d578da BS |
7002 | |
7003 | /* Like emit_insn_group_barriers, but run if no final scheduling pass was run. | |
7004 | This function has to emit all necessary group barriers. */ | |
7005 | ||
7006 | static void | |
9c808aad | 7007 | emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
f4d578da BS |
7008 | { |
7009 | rtx insn; | |
7010 | ||
7011 | init_insn_group_barriers (); | |
7012 | ||
18dbd950 | 7013 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f4d578da | 7014 | { |
b64925dc | 7015 | if (BARRIER_P (insn)) |
bd7b9a0f RH |
7016 | { |
7017 | rtx last = prev_active_insn (insn); | |
7018 | ||
7019 | if (! last) | |
7020 | continue; | |
34f0d87a | 7021 | if (JUMP_TABLE_DATA_P (last)) |
bd7b9a0f RH |
7022 | last = prev_active_insn (last); |
7023 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
7024 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
7025 | ||
7026 | init_insn_group_barriers (); | |
7027 | } | |
b5b8b0ac | 7028 | else if (NONDEBUG_INSN_P (insn)) |
f4d578da | 7029 | { |
bd7b9a0f RH |
7030 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
7031 | init_insn_group_barriers (); | |
c1bc6ca8 | 7032 | else if (group_barrier_needed (insn)) |
f4d578da BS |
7033 | { |
7034 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); | |
7035 | init_insn_group_barriers (); | |
c1bc6ca8 | 7036 | group_barrier_needed (insn); |
f4d578da BS |
7037 | } |
7038 | } | |
7039 | } | |
7040 | } | |
30028c85 | 7041 | |
2130b7fb | 7042 | \f |
2130b7fb | 7043 | |
30028c85 | 7044 | /* Instruction scheduling support. */ |
2130b7fb BS |
7045 | |
7046 | #define NR_BUNDLES 10 | |
7047 | ||
30028c85 | 7048 | /* A list of names of all available bundles. */ |
2130b7fb | 7049 | |
30028c85 | 7050 | static const char *bundle_name [NR_BUNDLES] = |
2130b7fb | 7051 | { |
30028c85 VM |
7052 | ".mii", |
7053 | ".mmi", | |
7054 | ".mfi", | |
7055 | ".mmf", | |
2130b7fb | 7056 | #if NR_BUNDLES == 10 |
30028c85 VM |
7057 | ".bbb", |
7058 | ".mbb", | |
2130b7fb | 7059 | #endif |
30028c85 VM |
7060 | ".mib", |
7061 | ".mmb", | |
7062 | ".mfb", | |
7063 | ".mlx" | |
2130b7fb BS |
7064 | }; |
7065 | ||
30028c85 | 7066 | /* Nonzero if we should insert stop bits into the schedule. */ |
2130b7fb | 7067 | |
30028c85 | 7068 | int ia64_final_schedule = 0; |
2130b7fb | 7069 | |
35fd3193 | 7070 | /* Codes of the corresponding queried units: */ |
2130b7fb | 7071 | |
30028c85 VM |
7072 | static int _0mii_, _0mmi_, _0mfi_, _0mmf_; |
7073 | static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_; | |
2130b7fb | 7074 | |
30028c85 VM |
7075 | static int _1mii_, _1mmi_, _1mfi_, _1mmf_; |
7076 | static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_; | |
2130b7fb | 7077 | |
30028c85 VM |
7078 | static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6; |
7079 | ||
7080 | /* The following variable value is an insn group barrier. */ | |
7081 | ||
7082 | static rtx dfa_stop_insn; | |
7083 | ||
7084 | /* The following variable value is the last issued insn. */ | |
7085 | ||
7086 | static rtx last_scheduled_insn; | |
7087 | ||
30028c85 VM |
7088 | /* The following variable value is pointer to a DFA state used as |
7089 | temporary variable. */ | |
7090 | ||
7091 | static state_t temp_dfa_state = NULL; | |
7092 | ||
7093 | /* The following variable value is DFA state after issuing the last | |
7094 | insn. */ | |
7095 | ||
7096 | static state_t prev_cycle_state = NULL; | |
7097 | ||
7098 | /* The following array element values are TRUE if the corresponding | |
9e4f94de | 7099 | insn requires to add stop bits before it. */ |
30028c85 | 7100 | |
048d0d36 MK |
7101 | static char *stops_p = NULL; |
7102 | ||
30028c85 VM |
7103 | /* The following variable is used to set up the mentioned above array. */ |
7104 | ||
7105 | static int stop_before_p = 0; | |
7106 | ||
7107 | /* The following variable value is length of the arrays `clocks' and | |
7108 | `add_cycles'. */ | |
7109 | ||
7110 | static int clocks_length; | |
7111 | ||
048d0d36 MK |
7112 | /* The following variable value is number of data speculations in progress. */ |
7113 | static int pending_data_specs = 0; | |
7114 | ||
388092d5 AB |
7115 | /* Number of memory references on current and three future processor cycles. */ |
7116 | static char mem_ops_in_group[4]; | |
7117 | ||
7118 | /* Number of current processor cycle (from scheduler's point of view). */ | |
7119 | static int current_cycle; | |
7120 | ||
9c808aad AJ |
7121 | static rtx ia64_single_set (rtx); |
7122 | static void ia64_emit_insn_before (rtx, rtx); | |
2130b7fb BS |
7123 | |
7124 | /* Map a bundle number to its pseudo-op. */ | |
7125 | ||
7126 | const char * | |
9c808aad | 7127 | get_bundle_name (int b) |
2130b7fb | 7128 | { |
30028c85 | 7129 | return bundle_name[b]; |
2130b7fb BS |
7130 | } |
7131 | ||
2130b7fb BS |
7132 | |
7133 | /* Return the maximum number of instructions a cpu can issue. */ | |
7134 | ||
c237e94a | 7135 | static int |
9c808aad | 7136 | ia64_issue_rate (void) |
2130b7fb BS |
7137 | { |
7138 | return 6; | |
7139 | } | |
7140 | ||
7141 | /* Helper function - like single_set, but look inside COND_EXEC. */ | |
7142 | ||
7143 | static rtx | |
9c808aad | 7144 | ia64_single_set (rtx insn) |
2130b7fb | 7145 | { |
30fa7e33 | 7146 | rtx x = PATTERN (insn), ret; |
2130b7fb BS |
7147 | if (GET_CODE (x) == COND_EXEC) |
7148 | x = COND_EXEC_CODE (x); | |
7149 | if (GET_CODE (x) == SET) | |
7150 | return x; | |
bdbe5b8d RH |
7151 | |
7152 | /* Special case here prologue_allocate_stack and epilogue_deallocate_stack. | |
7153 | Although they are not classical single set, the second set is there just | |
7154 | to protect it from moving past FP-relative stack accesses. */ | |
7155 | switch (recog_memoized (insn)) | |
30fa7e33 | 7156 | { |
bdbe5b8d | 7157 | case CODE_FOR_prologue_allocate_stack: |
9eb8c09f | 7158 | case CODE_FOR_prologue_allocate_stack_pr: |
bdbe5b8d | 7159 | case CODE_FOR_epilogue_deallocate_stack: |
9eb8c09f | 7160 | case CODE_FOR_epilogue_deallocate_stack_pr: |
bdbe5b8d RH |
7161 | ret = XVECEXP (x, 0, 0); |
7162 | break; | |
7163 | ||
7164 | default: | |
7165 | ret = single_set_2 (insn, x); | |
7166 | break; | |
30fa7e33 | 7167 | } |
bdbe5b8d | 7168 | |
30fa7e33 | 7169 | return ret; |
2130b7fb BS |
7170 | } |
7171 | ||
388092d5 AB |
7172 | /* Adjust the cost of a scheduling dependency. |
7173 | Return the new cost of a dependency of type DEP_TYPE or INSN on DEP_INSN. | |
7174 | COST is the current cost, DW is dependency weakness. */ | |
c237e94a | 7175 | static int |
388092d5 | 7176 | ia64_adjust_cost_2 (rtx insn, int dep_type1, rtx dep_insn, int cost, dw_t dw) |
2130b7fb | 7177 | { |
388092d5 | 7178 | enum reg_note dep_type = (enum reg_note) dep_type1; |
2130b7fb BS |
7179 | enum attr_itanium_class dep_class; |
7180 | enum attr_itanium_class insn_class; | |
2130b7fb | 7181 | |
2130b7fb | 7182 | insn_class = ia64_safe_itanium_class (insn); |
30028c85 | 7183 | dep_class = ia64_safe_itanium_class (dep_insn); |
388092d5 AB |
7184 | |
7185 | /* Treat true memory dependencies separately. Ignore apparent true | |
7186 | dependence between store and call (call has a MEM inside a SYMBOL_REF). */ | |
7187 | if (dep_type == REG_DEP_TRUE | |
7188 | && (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF) | |
7189 | && (insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL)) | |
7190 | return 0; | |
7191 | ||
7192 | if (dw == MIN_DEP_WEAK) | |
7193 | /* Store and load are likely to alias, use higher cost to avoid stall. */ | |
7194 | return PARAM_VALUE (PARAM_SCHED_MEM_TRUE_DEP_COST); | |
7195 | else if (dw > MIN_DEP_WEAK) | |
7196 | { | |
7197 | /* Store and load are less likely to alias. */ | |
7198 | if (mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF) | |
7199 | /* Assume there will be no cache conflict for floating-point data. | |
7200 | For integer data, L1 conflict penalty is huge (17 cycles), so we | |
7201 | never assume it will not cause a conflict. */ | |
7202 | return 0; | |
7203 | else | |
7204 | return cost; | |
7205 | } | |
7206 | ||
7207 | if (dep_type != REG_DEP_OUTPUT) | |
7208 | return cost; | |
7209 | ||
30028c85 VM |
7210 | if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF |
7211 | || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF) | |
2130b7fb BS |
7212 | return 0; |
7213 | ||
2130b7fb BS |
7214 | return cost; |
7215 | } | |
7216 | ||
14d118d6 DM |
7217 | /* Like emit_insn_before, but skip cycle_display notes. |
7218 | ??? When cycle display notes are implemented, update this. */ | |
7219 | ||
7220 | static void | |
9c808aad | 7221 | ia64_emit_insn_before (rtx insn, rtx before) |
14d118d6 DM |
7222 | { |
7223 | emit_insn_before (insn, before); | |
7224 | } | |
7225 | ||
30028c85 VM |
7226 | /* The following function marks insns who produce addresses for load |
7227 | and store insns. Such insns will be placed into M slots because it | |
7228 | decrease latency time for Itanium1 (see function | |
7229 | `ia64_produce_address_p' and the DFA descriptions). */ | |
2130b7fb BS |
7230 | |
7231 | static void | |
9c808aad | 7232 | ia64_dependencies_evaluation_hook (rtx head, rtx tail) |
2130b7fb | 7233 | { |
b198261f | 7234 | rtx insn, next, next_tail; |
9c808aad | 7235 | |
f12b785d RH |
7236 | /* Before reload, which_alternative is not set, which means that |
7237 | ia64_safe_itanium_class will produce wrong results for (at least) | |
7238 | move instructions. */ | |
7239 | if (!reload_completed) | |
7240 | return; | |
7241 | ||
30028c85 VM |
7242 | next_tail = NEXT_INSN (tail); |
7243 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7244 | if (INSN_P (insn)) | |
7245 | insn->call = 0; | |
7246 | for (insn = head; insn != next_tail; insn = NEXT_INSN (insn)) | |
7247 | if (INSN_P (insn) | |
7248 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU) | |
7249 | { | |
e2f6ff94 MK |
7250 | sd_iterator_def sd_it; |
7251 | dep_t dep; | |
7252 | bool has_mem_op_consumer_p = false; | |
b198261f | 7253 | |
e2f6ff94 | 7254 | FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep) |
30028c85 | 7255 | { |
a71aef0b JB |
7256 | enum attr_itanium_class c; |
7257 | ||
e2f6ff94 | 7258 | if (DEP_TYPE (dep) != REG_DEP_TRUE) |
f12b785d | 7259 | continue; |
b198261f | 7260 | |
e2f6ff94 | 7261 | next = DEP_CON (dep); |
a71aef0b JB |
7262 | c = ia64_safe_itanium_class (next); |
7263 | if ((c == ITANIUM_CLASS_ST | |
7264 | || c == ITANIUM_CLASS_STF) | |
30028c85 | 7265 | && ia64_st_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7266 | { |
7267 | has_mem_op_consumer_p = true; | |
7268 | break; | |
7269 | } | |
a71aef0b JB |
7270 | else if ((c == ITANIUM_CLASS_LD |
7271 | || c == ITANIUM_CLASS_FLD | |
7272 | || c == ITANIUM_CLASS_FLDP) | |
30028c85 | 7273 | && ia64_ld_address_bypass_p (insn, next)) |
e2f6ff94 MK |
7274 | { |
7275 | has_mem_op_consumer_p = true; | |
7276 | break; | |
7277 | } | |
30028c85 | 7278 | } |
e2f6ff94 MK |
7279 | |
7280 | insn->call = has_mem_op_consumer_p; | |
30028c85 VM |
7281 | } |
7282 | } | |
2130b7fb | 7283 | |
30028c85 | 7284 | /* We're beginning a new block. Initialize data structures as necessary. */ |
2130b7fb | 7285 | |
30028c85 | 7286 | static void |
9c808aad AJ |
7287 | ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED, |
7288 | int sched_verbose ATTRIBUTE_UNUSED, | |
7289 | int max_ready ATTRIBUTE_UNUSED) | |
30028c85 VM |
7290 | { |
7291 | #ifdef ENABLE_CHECKING | |
7292 | rtx insn; | |
9c808aad | 7293 | |
388092d5 | 7294 | if (!sel_sched_p () && reload_completed) |
30028c85 VM |
7295 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
7296 | insn != current_sched_info->next_tail; | |
7297 | insn = NEXT_INSN (insn)) | |
e820471b | 7298 | gcc_assert (!SCHED_GROUP_P (insn)); |
30028c85 VM |
7299 | #endif |
7300 | last_scheduled_insn = NULL_RTX; | |
7301 | init_insn_group_barriers (); | |
388092d5 AB |
7302 | |
7303 | current_cycle = 0; | |
7304 | memset (mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
2130b7fb BS |
7305 | } |
7306 | ||
048d0d36 MK |
7307 | /* We're beginning a scheduling pass. Check assertion. */ |
7308 | ||
7309 | static void | |
7310 | ia64_sched_init_global (FILE *dump ATTRIBUTE_UNUSED, | |
7311 | int sched_verbose ATTRIBUTE_UNUSED, | |
7312 | int max_ready ATTRIBUTE_UNUSED) | |
7313 | { | |
388092d5 | 7314 | gcc_assert (pending_data_specs == 0); |
048d0d36 MK |
7315 | } |
7316 | ||
7317 | /* Scheduling pass is now finished. Free/reset static variable. */ | |
7318 | static void | |
7319 | ia64_sched_finish_global (FILE *dump ATTRIBUTE_UNUSED, | |
7320 | int sched_verbose ATTRIBUTE_UNUSED) | |
7321 | { | |
388092d5 AB |
7322 | gcc_assert (pending_data_specs == 0); |
7323 | } | |
7324 | ||
7325 | /* Return TRUE if INSN is a load (either normal or speculative, but not a | |
7326 | speculation check), FALSE otherwise. */ | |
7327 | static bool | |
7328 | is_load_p (rtx insn) | |
7329 | { | |
7330 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7331 | ||
7332 | return | |
7333 | ((insn_class == ITANIUM_CLASS_LD || insn_class == ITANIUM_CLASS_FLD) | |
7334 | && get_attr_check_load (insn) == CHECK_LOAD_NO); | |
7335 | } | |
7336 | ||
7337 | /* If INSN is a memory reference, memoize it in MEM_OPS_IN_GROUP global array | |
7338 | (taking account for 3-cycle cache reference postponing for stores: Intel | |
7339 | Itanium 2 Reference Manual for Software Development and Optimization, | |
7340 | 6.7.3.1). */ | |
7341 | static void | |
7342 | record_memory_reference (rtx insn) | |
7343 | { | |
7344 | enum attr_itanium_class insn_class = ia64_safe_itanium_class (insn); | |
7345 | ||
7346 | switch (insn_class) { | |
7347 | case ITANIUM_CLASS_FLD: | |
7348 | case ITANIUM_CLASS_LD: | |
7349 | mem_ops_in_group[current_cycle % 4]++; | |
7350 | break; | |
7351 | case ITANIUM_CLASS_STF: | |
7352 | case ITANIUM_CLASS_ST: | |
7353 | mem_ops_in_group[(current_cycle + 3) % 4]++; | |
7354 | break; | |
7355 | default:; | |
7356 | } | |
048d0d36 MK |
7357 | } |
7358 | ||
30028c85 VM |
7359 | /* We are about to being issuing insns for this clock cycle. |
7360 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7361 | |
30028c85 | 7362 | static int |
9c808aad | 7363 | ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, |
388092d5 | 7364 | int *pn_ready, int clock_var, |
9c808aad | 7365 | int reorder_type) |
2130b7fb | 7366 | { |
30028c85 VM |
7367 | int n_asms; |
7368 | int n_ready = *pn_ready; | |
7369 | rtx *e_ready = ready + n_ready; | |
7370 | rtx *insnp; | |
2130b7fb | 7371 | |
30028c85 VM |
7372 | if (sched_verbose) |
7373 | fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type); | |
2130b7fb | 7374 | |
30028c85 | 7375 | if (reorder_type == 0) |
2130b7fb | 7376 | { |
30028c85 VM |
7377 | /* First, move all USEs, CLOBBERs and other crud out of the way. */ |
7378 | n_asms = 0; | |
7379 | for (insnp = ready; insnp < e_ready; insnp++) | |
7380 | if (insnp < e_ready) | |
7381 | { | |
7382 | rtx insn = *insnp; | |
7383 | enum attr_type t = ia64_safe_type (insn); | |
7384 | if (t == TYPE_UNKNOWN) | |
7385 | { | |
7386 | if (GET_CODE (PATTERN (insn)) == ASM_INPUT | |
7387 | || asm_noperands (PATTERN (insn)) >= 0) | |
7388 | { | |
7389 | rtx lowest = ready[n_asms]; | |
7390 | ready[n_asms] = insn; | |
7391 | *insnp = lowest; | |
7392 | n_asms++; | |
7393 | } | |
7394 | else | |
7395 | { | |
7396 | rtx highest = ready[n_ready - 1]; | |
7397 | ready[n_ready - 1] = insn; | |
7398 | *insnp = highest; | |
7399 | return 1; | |
7400 | } | |
7401 | } | |
7402 | } | |
98d2b17e | 7403 | |
30028c85 | 7404 | if (n_asms < n_ready) |
98d2b17e | 7405 | { |
30028c85 VM |
7406 | /* Some normal insns to process. Skip the asms. */ |
7407 | ready += n_asms; | |
7408 | n_ready -= n_asms; | |
98d2b17e | 7409 | } |
30028c85 VM |
7410 | else if (n_ready > 0) |
7411 | return 1; | |
2130b7fb BS |
7412 | } |
7413 | ||
30028c85 | 7414 | if (ia64_final_schedule) |
2130b7fb | 7415 | { |
30028c85 VM |
7416 | int deleted = 0; |
7417 | int nr_need_stop = 0; | |
7418 | ||
7419 | for (insnp = ready; insnp < e_ready; insnp++) | |
c1bc6ca8 | 7420 | if (safe_group_barrier_needed (*insnp)) |
30028c85 | 7421 | nr_need_stop++; |
9c808aad | 7422 | |
30028c85 VM |
7423 | if (reorder_type == 1 && n_ready == nr_need_stop) |
7424 | return 0; | |
7425 | if (reorder_type == 0) | |
7426 | return 1; | |
7427 | insnp = e_ready; | |
7428 | /* Move down everything that needs a stop bit, preserving | |
7429 | relative order. */ | |
7430 | while (insnp-- > ready + deleted) | |
7431 | while (insnp >= ready + deleted) | |
7432 | { | |
7433 | rtx insn = *insnp; | |
c1bc6ca8 | 7434 | if (! safe_group_barrier_needed (insn)) |
30028c85 VM |
7435 | break; |
7436 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7437 | *ready = insn; | |
7438 | deleted++; | |
7439 | } | |
7440 | n_ready -= deleted; | |
7441 | ready += deleted; | |
2130b7fb | 7442 | } |
2130b7fb | 7443 | |
388092d5 AB |
7444 | current_cycle = clock_var; |
7445 | if (reload_completed && mem_ops_in_group[clock_var % 4] >= ia64_max_memory_insns) | |
7446 | { | |
7447 | int moved = 0; | |
7448 | ||
7449 | insnp = e_ready; | |
7450 | /* Move down loads/stores, preserving relative order. */ | |
7451 | while (insnp-- > ready + moved) | |
7452 | while (insnp >= ready + moved) | |
7453 | { | |
7454 | rtx insn = *insnp; | |
7455 | if (! is_load_p (insn)) | |
7456 | break; | |
7457 | memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx)); | |
7458 | *ready = insn; | |
7459 | moved++; | |
7460 | } | |
7461 | n_ready -= moved; | |
7462 | ready += moved; | |
7463 | } | |
7464 | ||
30028c85 | 7465 | return 1; |
2130b7fb | 7466 | } |
6b6c1201 | 7467 | |
30028c85 VM |
7468 | /* We are about to being issuing insns for this clock cycle. Override |
7469 | the default sort algorithm to better slot instructions. */ | |
c65ebc55 | 7470 | |
30028c85 | 7471 | static int |
9c808aad AJ |
7472 | ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready, |
7473 | int clock_var) | |
2130b7fb | 7474 | { |
30028c85 VM |
7475 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, |
7476 | pn_ready, clock_var, 0); | |
2130b7fb BS |
7477 | } |
7478 | ||
30028c85 VM |
7479 | /* Like ia64_sched_reorder, but called after issuing each insn. |
7480 | Override the default sort algorithm to better slot instructions. */ | |
2130b7fb | 7481 | |
30028c85 | 7482 | static int |
9c808aad AJ |
7483 | ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED, |
7484 | int sched_verbose ATTRIBUTE_UNUSED, rtx *ready, | |
7485 | int *pn_ready, int clock_var) | |
30028c85 | 7486 | { |
30028c85 VM |
7487 | return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready, |
7488 | clock_var, 1); | |
2130b7fb BS |
7489 | } |
7490 | ||
30028c85 VM |
7491 | /* We are about to issue INSN. Return the number of insns left on the |
7492 | ready queue that can be issued this cycle. */ | |
2130b7fb | 7493 | |
30028c85 | 7494 | static int |
9c808aad AJ |
7495 | ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED, |
7496 | int sched_verbose ATTRIBUTE_UNUSED, | |
7497 | rtx insn ATTRIBUTE_UNUSED, | |
7498 | int can_issue_more ATTRIBUTE_UNUSED) | |
2130b7fb | 7499 | { |
388092d5 | 7500 | if (sched_deps_info->generate_spec_deps && !sel_sched_p ()) |
048d0d36 | 7501 | /* Modulo scheduling does not extend h_i_d when emitting |
388092d5 | 7502 | new instructions. Don't use h_i_d, if we don't have to. */ |
048d0d36 MK |
7503 | { |
7504 | if (DONE_SPEC (insn) & BEGIN_DATA) | |
7505 | pending_data_specs++; | |
7506 | if (CHECK_SPEC (insn) & BEGIN_DATA) | |
7507 | pending_data_specs--; | |
7508 | } | |
7509 | ||
b5b8b0ac AO |
7510 | if (DEBUG_INSN_P (insn)) |
7511 | return 1; | |
7512 | ||
30028c85 VM |
7513 | last_scheduled_insn = insn; |
7514 | memcpy (prev_cycle_state, curr_state, dfa_state_size); | |
7515 | if (reload_completed) | |
2130b7fb | 7516 | { |
c1bc6ca8 | 7517 | int needed = group_barrier_needed (insn); |
e820471b NS |
7518 | |
7519 | gcc_assert (!needed); | |
b64925dc | 7520 | if (CALL_P (insn)) |
30028c85 VM |
7521 | init_insn_group_barriers (); |
7522 | stops_p [INSN_UID (insn)] = stop_before_p; | |
7523 | stop_before_p = 0; | |
388092d5 AB |
7524 | |
7525 | record_memory_reference (insn); | |
2130b7fb | 7526 | } |
30028c85 VM |
7527 | return 1; |
7528 | } | |
c65ebc55 | 7529 | |
4960a0cb | 7530 | /* We are choosing insn from the ready queue. Return zero if INSN |
30028c85 | 7531 | can be chosen. */ |
c65ebc55 | 7532 | |
30028c85 | 7533 | static int |
4960a0cb | 7534 | ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn, int ready_index) |
30028c85 | 7535 | { |
388092d5 | 7536 | gcc_assert (insn && INSN_P (insn)); |
048d0d36 | 7537 | |
4960a0cb MK |
7538 | /* Size of ALAT is 32. As far as we perform conservative |
7539 | data speculation, we keep ALAT half-empty. */ | |
31815ed7 | 7540 | if (pending_data_specs >= 16 && (TODO_SPEC (insn) & BEGIN_DATA)) |
4960a0cb | 7541 | return ready_index == 0 ? -1 : 1; |
048d0d36 | 7542 | |
4960a0cb MK |
7543 | if (ready_index == 0) |
7544 | return 0; | |
7545 | ||
7546 | if ((!reload_completed | |
7547 | || !safe_group_barrier_needed (insn)) | |
7548 | && (!mflag_sched_mem_insns_hard_limit | |
7549 | || !is_load_p (insn) | |
7550 | || mem_ops_in_group[current_cycle % 4] < ia64_max_memory_insns)) | |
7551 | return 0; | |
676cad4d MK |
7552 | |
7553 | return 1; | |
2130b7fb BS |
7554 | } |
7555 | ||
30028c85 VM |
7556 | /* The following variable value is pseudo-insn used by the DFA insn |
7557 | scheduler to change the DFA state when the simulated clock is | |
7558 | increased. */ | |
2130b7fb | 7559 | |
30028c85 | 7560 | static rtx dfa_pre_cycle_insn; |
2130b7fb | 7561 | |
388092d5 AB |
7562 | /* Returns 1 when a meaningful insn was scheduled between the last group |
7563 | barrier and LAST. */ | |
7564 | static int | |
7565 | scheduled_good_insn (rtx last) | |
7566 | { | |
7567 | if (last && recog_memoized (last) >= 0) | |
7568 | return 1; | |
7569 | ||
7570 | for ( ; | |
7571 | last != NULL && !NOTE_INSN_BASIC_BLOCK_P (last) | |
7572 | && !stops_p[INSN_UID (last)]; | |
7573 | last = PREV_INSN (last)) | |
7574 | /* We could hit a NOTE_INSN_DELETED here which is actually outside | |
7575 | the ebb we're scheduling. */ | |
7576 | if (INSN_P (last) && recog_memoized (last) >= 0) | |
7577 | return 1; | |
7578 | ||
7579 | return 0; | |
7580 | } | |
7581 | ||
1e5f1716 | 7582 | /* We are about to being issuing INSN. Return nonzero if we cannot |
30028c85 VM |
7583 | issue it on given cycle CLOCK and return zero if we should not sort |
7584 | the ready queue on the next clock start. */ | |
2130b7fb BS |
7585 | |
7586 | static int | |
9c808aad AJ |
7587 | ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock, |
7588 | int clock, int *sort_p) | |
2130b7fb | 7589 | { |
e820471b | 7590 | gcc_assert (insn && INSN_P (insn)); |
b5b8b0ac AO |
7591 | |
7592 | if (DEBUG_INSN_P (insn)) | |
7593 | return 0; | |
7594 | ||
388092d5 AB |
7595 | /* When a group barrier is needed for insn, last_scheduled_insn |
7596 | should be set. */ | |
7597 | gcc_assert (!(reload_completed && safe_group_barrier_needed (insn)) | |
7598 | || last_scheduled_insn); | |
7599 | ||
7600 | if ((reload_completed | |
7601 | && (safe_group_barrier_needed (insn) | |
7602 | || (mflag_sched_stop_bits_after_every_cycle | |
7603 | && last_clock != clock | |
7604 | && last_scheduled_insn | |
7605 | && scheduled_good_insn (last_scheduled_insn)))) | |
30028c85 | 7606 | || (last_scheduled_insn |
b64925dc | 7607 | && (CALL_P (last_scheduled_insn) |
7b84aac0 | 7608 | || unknown_for_bundling_p (last_scheduled_insn)))) |
2130b7fb | 7609 | { |
30028c85 | 7610 | init_insn_group_barriers (); |
388092d5 | 7611 | |
30028c85 VM |
7612 | if (verbose && dump) |
7613 | fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn), | |
7614 | last_clock == clock ? " + cycle advance" : ""); | |
388092d5 | 7615 | |
30028c85 | 7616 | stop_before_p = 1; |
388092d5 AB |
7617 | current_cycle = clock; |
7618 | mem_ops_in_group[current_cycle % 4] = 0; | |
7619 | ||
30028c85 | 7620 | if (last_clock == clock) |
2130b7fb | 7621 | { |
30028c85 VM |
7622 | state_transition (curr_state, dfa_stop_insn); |
7623 | if (TARGET_EARLY_STOP_BITS) | |
7624 | *sort_p = (last_scheduled_insn == NULL_RTX | |
b64925dc | 7625 | || ! CALL_P (last_scheduled_insn)); |
30028c85 VM |
7626 | else |
7627 | *sort_p = 0; | |
7628 | return 1; | |
7629 | } | |
388092d5 AB |
7630 | |
7631 | if (last_scheduled_insn) | |
25069b42 | 7632 | { |
7b84aac0 | 7633 | if (unknown_for_bundling_p (last_scheduled_insn)) |
388092d5 AB |
7634 | state_reset (curr_state); |
7635 | else | |
7636 | { | |
7637 | memcpy (curr_state, prev_cycle_state, dfa_state_size); | |
7638 | state_transition (curr_state, dfa_stop_insn); | |
7639 | state_transition (curr_state, dfa_pre_cycle_insn); | |
7640 | state_transition (curr_state, NULL); | |
7641 | } | |
25069b42 | 7642 | } |
30028c85 | 7643 | } |
30028c85 | 7644 | return 0; |
2130b7fb BS |
7645 | } |
7646 | ||
048d0d36 MK |
7647 | /* Implement targetm.sched.h_i_d_extended hook. |
7648 | Extend internal data structures. */ | |
7649 | static void | |
7650 | ia64_h_i_d_extended (void) | |
7651 | { | |
048d0d36 MK |
7652 | if (stops_p != NULL) |
7653 | { | |
388092d5 | 7654 | int new_clocks_length = get_max_uid () * 3 / 2; |
5ead67f6 | 7655 | stops_p = (char *) xrecalloc (stops_p, new_clocks_length, clocks_length, 1); |
048d0d36 MK |
7656 | clocks_length = new_clocks_length; |
7657 | } | |
7658 | } | |
388092d5 AB |
7659 | \f |
7660 | ||
7661 | /* This structure describes the data used by the backend to guide scheduling. | |
7662 | When the current scheduling point is switched, this data should be saved | |
7663 | and restored later, if the scheduler returns to this point. */ | |
7664 | struct _ia64_sched_context | |
7665 | { | |
7666 | state_t prev_cycle_state; | |
7667 | rtx last_scheduled_insn; | |
7668 | struct reg_write_state rws_sum[NUM_REGS]; | |
7669 | struct reg_write_state rws_insn[NUM_REGS]; | |
7670 | int first_instruction; | |
7671 | int pending_data_specs; | |
7672 | int current_cycle; | |
7673 | char mem_ops_in_group[4]; | |
7674 | }; | |
7675 | typedef struct _ia64_sched_context *ia64_sched_context_t; | |
7676 | ||
7677 | /* Allocates a scheduling context. */ | |
7678 | static void * | |
7679 | ia64_alloc_sched_context (void) | |
7680 | { | |
7681 | return xmalloc (sizeof (struct _ia64_sched_context)); | |
7682 | } | |
7683 | ||
7684 | /* Initializes the _SC context with clean data, if CLEAN_P, and from | |
7685 | the global context otherwise. */ | |
7686 | static void | |
7687 | ia64_init_sched_context (void *_sc, bool clean_p) | |
7688 | { | |
7689 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7690 | ||
7691 | sc->prev_cycle_state = xmalloc (dfa_state_size); | |
7692 | if (clean_p) | |
7693 | { | |
7694 | state_reset (sc->prev_cycle_state); | |
7695 | sc->last_scheduled_insn = NULL_RTX; | |
7696 | memset (sc->rws_sum, 0, sizeof (rws_sum)); | |
7697 | memset (sc->rws_insn, 0, sizeof (rws_insn)); | |
7698 | sc->first_instruction = 1; | |
7699 | sc->pending_data_specs = 0; | |
7700 | sc->current_cycle = 0; | |
7701 | memset (sc->mem_ops_in_group, 0, sizeof (mem_ops_in_group)); | |
7702 | } | |
7703 | else | |
7704 | { | |
7705 | memcpy (sc->prev_cycle_state, prev_cycle_state, dfa_state_size); | |
7706 | sc->last_scheduled_insn = last_scheduled_insn; | |
7707 | memcpy (sc->rws_sum, rws_sum, sizeof (rws_sum)); | |
7708 | memcpy (sc->rws_insn, rws_insn, sizeof (rws_insn)); | |
7709 | sc->first_instruction = first_instruction; | |
7710 | sc->pending_data_specs = pending_data_specs; | |
7711 | sc->current_cycle = current_cycle; | |
7712 | memcpy (sc->mem_ops_in_group, mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7713 | } | |
7714 | } | |
7715 | ||
7716 | /* Sets the global scheduling context to the one pointed to by _SC. */ | |
7717 | static void | |
7718 | ia64_set_sched_context (void *_sc) | |
7719 | { | |
7720 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7721 | ||
7722 | gcc_assert (sc != NULL); | |
7723 | ||
7724 | memcpy (prev_cycle_state, sc->prev_cycle_state, dfa_state_size); | |
7725 | last_scheduled_insn = sc->last_scheduled_insn; | |
7726 | memcpy (rws_sum, sc->rws_sum, sizeof (rws_sum)); | |
7727 | memcpy (rws_insn, sc->rws_insn, sizeof (rws_insn)); | |
7728 | first_instruction = sc->first_instruction; | |
7729 | pending_data_specs = sc->pending_data_specs; | |
7730 | current_cycle = sc->current_cycle; | |
7731 | memcpy (mem_ops_in_group, sc->mem_ops_in_group, sizeof (mem_ops_in_group)); | |
7732 | } | |
7733 | ||
7734 | /* Clears the data in the _SC scheduling context. */ | |
7735 | static void | |
7736 | ia64_clear_sched_context (void *_sc) | |
7737 | { | |
7738 | ia64_sched_context_t sc = (ia64_sched_context_t) _sc; | |
7739 | ||
7740 | free (sc->prev_cycle_state); | |
7741 | sc->prev_cycle_state = NULL; | |
7742 | } | |
7743 | ||
7744 | /* Frees the _SC scheduling context. */ | |
7745 | static void | |
7746 | ia64_free_sched_context (void *_sc) | |
7747 | { | |
7748 | gcc_assert (_sc != NULL); | |
7749 | ||
7750 | free (_sc); | |
7751 | } | |
7752 | ||
7753 | typedef rtx (* gen_func_t) (rtx, rtx); | |
7754 | ||
7755 | /* Return a function that will generate a load of mode MODE_NO | |
7756 | with speculation types TS. */ | |
7757 | static gen_func_t | |
7758 | get_spec_load_gen_function (ds_t ts, int mode_no) | |
7759 | { | |
7760 | static gen_func_t gen_ld_[] = { | |
7761 | gen_movbi, | |
7762 | gen_movqi_internal, | |
7763 | gen_movhi_internal, | |
7764 | gen_movsi_internal, | |
7765 | gen_movdi_internal, | |
7766 | gen_movsf_internal, | |
7767 | gen_movdf_internal, | |
7768 | gen_movxf_internal, | |
7769 | gen_movti_internal, | |
7770 | gen_zero_extendqidi2, | |
7771 | gen_zero_extendhidi2, | |
7772 | gen_zero_extendsidi2, | |
7773 | }; | |
7774 | ||
7775 | static gen_func_t gen_ld_a[] = { | |
7776 | gen_movbi_advanced, | |
7777 | gen_movqi_advanced, | |
7778 | gen_movhi_advanced, | |
7779 | gen_movsi_advanced, | |
7780 | gen_movdi_advanced, | |
7781 | gen_movsf_advanced, | |
7782 | gen_movdf_advanced, | |
7783 | gen_movxf_advanced, | |
7784 | gen_movti_advanced, | |
7785 | gen_zero_extendqidi2_advanced, | |
7786 | gen_zero_extendhidi2_advanced, | |
7787 | gen_zero_extendsidi2_advanced, | |
7788 | }; | |
7789 | static gen_func_t gen_ld_s[] = { | |
7790 | gen_movbi_speculative, | |
7791 | gen_movqi_speculative, | |
7792 | gen_movhi_speculative, | |
7793 | gen_movsi_speculative, | |
7794 | gen_movdi_speculative, | |
7795 | gen_movsf_speculative, | |
7796 | gen_movdf_speculative, | |
7797 | gen_movxf_speculative, | |
7798 | gen_movti_speculative, | |
7799 | gen_zero_extendqidi2_speculative, | |
7800 | gen_zero_extendhidi2_speculative, | |
7801 | gen_zero_extendsidi2_speculative, | |
7802 | }; | |
7803 | static gen_func_t gen_ld_sa[] = { | |
7804 | gen_movbi_speculative_advanced, | |
7805 | gen_movqi_speculative_advanced, | |
7806 | gen_movhi_speculative_advanced, | |
7807 | gen_movsi_speculative_advanced, | |
7808 | gen_movdi_speculative_advanced, | |
7809 | gen_movsf_speculative_advanced, | |
7810 | gen_movdf_speculative_advanced, | |
7811 | gen_movxf_speculative_advanced, | |
7812 | gen_movti_speculative_advanced, | |
7813 | gen_zero_extendqidi2_speculative_advanced, | |
7814 | gen_zero_extendhidi2_speculative_advanced, | |
7815 | gen_zero_extendsidi2_speculative_advanced, | |
7816 | }; | |
7817 | static gen_func_t gen_ld_s_a[] = { | |
7818 | gen_movbi_speculative_a, | |
7819 | gen_movqi_speculative_a, | |
7820 | gen_movhi_speculative_a, | |
7821 | gen_movsi_speculative_a, | |
7822 | gen_movdi_speculative_a, | |
7823 | gen_movsf_speculative_a, | |
7824 | gen_movdf_speculative_a, | |
7825 | gen_movxf_speculative_a, | |
7826 | gen_movti_speculative_a, | |
7827 | gen_zero_extendqidi2_speculative_a, | |
7828 | gen_zero_extendhidi2_speculative_a, | |
7829 | gen_zero_extendsidi2_speculative_a, | |
7830 | }; | |
7831 | ||
7832 | gen_func_t *gen_ld; | |
7833 | ||
7834 | if (ts & BEGIN_DATA) | |
7835 | { | |
7836 | if (ts & BEGIN_CONTROL) | |
7837 | gen_ld = gen_ld_sa; | |
7838 | else | |
7839 | gen_ld = gen_ld_a; | |
7840 | } | |
7841 | else if (ts & BEGIN_CONTROL) | |
7842 | { | |
7843 | if ((spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL) | |
7844 | || ia64_needs_block_p (ts)) | |
7845 | gen_ld = gen_ld_s; | |
7846 | else | |
7847 | gen_ld = gen_ld_s_a; | |
7848 | } | |
7849 | else if (ts == 0) | |
7850 | gen_ld = gen_ld_; | |
7851 | else | |
7852 | gcc_unreachable (); | |
7853 | ||
7854 | return gen_ld[mode_no]; | |
7855 | } | |
048d0d36 MK |
7856 | |
7857 | /* Constants that help mapping 'enum machine_mode' to int. */ | |
7858 | enum SPEC_MODES | |
7859 | { | |
7860 | SPEC_MODE_INVALID = -1, | |
7861 | SPEC_MODE_FIRST = 0, | |
7862 | SPEC_MODE_FOR_EXTEND_FIRST = 1, | |
7863 | SPEC_MODE_FOR_EXTEND_LAST = 3, | |
7864 | SPEC_MODE_LAST = 8 | |
7865 | }; | |
7866 | ||
388092d5 AB |
7867 | enum |
7868 | { | |
7869 | /* Offset to reach ZERO_EXTEND patterns. */ | |
7870 | SPEC_GEN_EXTEND_OFFSET = SPEC_MODE_LAST - SPEC_MODE_FOR_EXTEND_FIRST + 1 | |
7871 | }; | |
7872 | ||
048d0d36 MK |
7873 | /* Return index of the MODE. */ |
7874 | static int | |
7875 | ia64_mode_to_int (enum machine_mode mode) | |
7876 | { | |
7877 | switch (mode) | |
7878 | { | |
7879 | case BImode: return 0; /* SPEC_MODE_FIRST */ | |
7880 | case QImode: return 1; /* SPEC_MODE_FOR_EXTEND_FIRST */ | |
7881 | case HImode: return 2; | |
7882 | case SImode: return 3; /* SPEC_MODE_FOR_EXTEND_LAST */ | |
7883 | case DImode: return 4; | |
7884 | case SFmode: return 5; | |
7885 | case DFmode: return 6; | |
7886 | case XFmode: return 7; | |
7887 | case TImode: | |
7888 | /* ??? This mode needs testing. Bypasses for ldfp8 instruction are not | |
7889 | mentioned in itanium[12].md. Predicate fp_register_operand also | |
7890 | needs to be defined. Bottom line: better disable for now. */ | |
7891 | return SPEC_MODE_INVALID; | |
7892 | default: return SPEC_MODE_INVALID; | |
7893 | } | |
7894 | } | |
7895 | ||
7896 | /* Provide information about speculation capabilities. */ | |
7897 | static void | |
7898 | ia64_set_sched_flags (spec_info_t spec_info) | |
7899 | { | |
7900 | unsigned int *flags = &(current_sched_info->flags); | |
7901 | ||
7902 | if (*flags & SCHED_RGN | |
388092d5 AB |
7903 | || *flags & SCHED_EBB |
7904 | || *flags & SEL_SCHED) | |
048d0d36 MK |
7905 | { |
7906 | int mask = 0; | |
7907 | ||
a57aee2a | 7908 | if ((mflag_sched_br_data_spec && !reload_completed && optimize > 0) |
388092d5 | 7909 | || (mflag_sched_ar_data_spec && reload_completed)) |
048d0d36 MK |
7910 | { |
7911 | mask |= BEGIN_DATA; | |
388092d5 AB |
7912 | |
7913 | if (!sel_sched_p () | |
7914 | && ((mflag_sched_br_in_data_spec && !reload_completed) | |
7915 | || (mflag_sched_ar_in_data_spec && reload_completed))) | |
048d0d36 MK |
7916 | mask |= BE_IN_DATA; |
7917 | } | |
7918 | ||
388092d5 AB |
7919 | if (mflag_sched_control_spec |
7920 | && (!sel_sched_p () | |
7921 | || reload_completed)) | |
048d0d36 MK |
7922 | { |
7923 | mask |= BEGIN_CONTROL; | |
7924 | ||
388092d5 | 7925 | if (!sel_sched_p () && mflag_sched_in_control_spec) |
048d0d36 MK |
7926 | mask |= BE_IN_CONTROL; |
7927 | } | |
7928 | ||
7ab5df48 AB |
7929 | spec_info->mask = mask; |
7930 | ||
048d0d36 MK |
7931 | if (mask) |
7932 | { | |
6fb5fa3c DB |
7933 | *flags |= USE_DEPS_LIST | DO_SPECULATION; |
7934 | ||
7935 | if (mask & BE_IN_SPEC) | |
7936 | *flags |= NEW_BBS; | |
048d0d36 | 7937 | |
048d0d36 MK |
7938 | spec_info->flags = 0; |
7939 | ||
16d83dd6 MK |
7940 | if ((mask & CONTROL_SPEC) |
7941 | && sel_sched_p () && mflag_sel_sched_dont_check_control_spec) | |
7942 | spec_info->flags |= SEL_SCHED_SPEC_DONT_CHECK_CONTROL; | |
388092d5 AB |
7943 | |
7944 | if (sched_verbose >= 1) | |
7945 | spec_info->dump = sched_dump; | |
048d0d36 MK |
7946 | else |
7947 | spec_info->dump = 0; | |
7948 | ||
7949 | if (mflag_sched_count_spec_in_critical_path) | |
7950 | spec_info->flags |= COUNT_SPEC_IN_CRITICAL_PATH; | |
7951 | } | |
7952 | } | |
cd510f15 AM |
7953 | else |
7954 | spec_info->mask = 0; | |
048d0d36 MK |
7955 | } |
7956 | ||
388092d5 AB |
7957 | /* If INSN is an appropriate load return its mode. |
7958 | Return -1 otherwise. */ | |
048d0d36 | 7959 | static int |
388092d5 AB |
7960 | get_mode_no_for_insn (rtx insn) |
7961 | { | |
7962 | rtx reg, mem, mode_rtx; | |
7963 | int mode_no; | |
048d0d36 | 7964 | bool extend_p; |
048d0d36 | 7965 | |
388092d5 | 7966 | extract_insn_cached (insn); |
048d0d36 | 7967 | |
388092d5 AB |
7968 | /* We use WHICH_ALTERNATIVE only after reload. This will |
7969 | guarantee that reload won't touch a speculative insn. */ | |
f6ec1d11 | 7970 | |
388092d5 | 7971 | if (recog_data.n_operands != 2) |
048d0d36 MK |
7972 | return -1; |
7973 | ||
388092d5 AB |
7974 | reg = recog_data.operand[0]; |
7975 | mem = recog_data.operand[1]; | |
f6ec1d11 | 7976 | |
388092d5 AB |
7977 | /* We should use MEM's mode since REG's mode in presence of |
7978 | ZERO_EXTEND will always be DImode. */ | |
7979 | if (get_attr_speculable1 (insn) == SPECULABLE1_YES) | |
7980 | /* Process non-speculative ld. */ | |
7981 | { | |
7982 | if (!reload_completed) | |
7983 | { | |
7984 | /* Do not speculate into regs like ar.lc. */ | |
7985 | if (!REG_P (reg) || AR_REGNO_P (REGNO (reg))) | |
7986 | return -1; | |
7987 | ||
7988 | if (!MEM_P (mem)) | |
7989 | return -1; | |
7990 | ||
7991 | { | |
7992 | rtx mem_reg = XEXP (mem, 0); | |
7993 | ||
7994 | if (!REG_P (mem_reg)) | |
7995 | return -1; | |
7996 | } | |
7997 | ||
7998 | mode_rtx = mem; | |
7999 | } | |
8000 | else if (get_attr_speculable2 (insn) == SPECULABLE2_YES) | |
8001 | { | |
8002 | gcc_assert (REG_P (reg) && MEM_P (mem)); | |
8003 | mode_rtx = mem; | |
8004 | } | |
8005 | else | |
8006 | return -1; | |
8007 | } | |
8008 | else if (get_attr_data_speculative (insn) == DATA_SPECULATIVE_YES | |
8009 | || get_attr_control_speculative (insn) == CONTROL_SPECULATIVE_YES | |
8010 | || get_attr_check_load (insn) == CHECK_LOAD_YES) | |
8011 | /* Process speculative ld or ld.c. */ | |
048d0d36 | 8012 | { |
388092d5 AB |
8013 | gcc_assert (REG_P (reg) && MEM_P (mem)); |
8014 | mode_rtx = mem; | |
048d0d36 MK |
8015 | } |
8016 | else | |
048d0d36 | 8017 | { |
388092d5 | 8018 | enum attr_itanium_class attr_class = get_attr_itanium_class (insn); |
048d0d36 | 8019 | |
388092d5 AB |
8020 | if (attr_class == ITANIUM_CLASS_CHK_A |
8021 | || attr_class == ITANIUM_CLASS_CHK_S_I | |
8022 | || attr_class == ITANIUM_CLASS_CHK_S_F) | |
8023 | /* Process chk. */ | |
8024 | mode_rtx = reg; | |
8025 | else | |
8026 | return -1; | |
048d0d36 | 8027 | } |
f6ec1d11 | 8028 | |
388092d5 | 8029 | mode_no = ia64_mode_to_int (GET_MODE (mode_rtx)); |
f6ec1d11 | 8030 | |
388092d5 | 8031 | if (mode_no == SPEC_MODE_INVALID) |
048d0d36 MK |
8032 | return -1; |
8033 | ||
388092d5 AB |
8034 | extend_p = (GET_MODE (reg) != GET_MODE (mode_rtx)); |
8035 | ||
8036 | if (extend_p) | |
8037 | { | |
8038 | if (!(SPEC_MODE_FOR_EXTEND_FIRST <= mode_no | |
8039 | && mode_no <= SPEC_MODE_FOR_EXTEND_LAST)) | |
8040 | return -1; | |
f6ec1d11 | 8041 | |
388092d5 AB |
8042 | mode_no += SPEC_GEN_EXTEND_OFFSET; |
8043 | } | |
048d0d36 | 8044 | |
388092d5 | 8045 | return mode_no; |
048d0d36 MK |
8046 | } |
8047 | ||
388092d5 AB |
8048 | /* If X is an unspec part of a speculative load, return its code. |
8049 | Return -1 otherwise. */ | |
8050 | static int | |
8051 | get_spec_unspec_code (const_rtx x) | |
8052 | { | |
8053 | if (GET_CODE (x) != UNSPEC) | |
8054 | return -1; | |
048d0d36 | 8055 | |
048d0d36 | 8056 | { |
388092d5 | 8057 | int code; |
048d0d36 | 8058 | |
388092d5 | 8059 | code = XINT (x, 1); |
048d0d36 | 8060 | |
388092d5 AB |
8061 | switch (code) |
8062 | { | |
8063 | case UNSPEC_LDA: | |
8064 | case UNSPEC_LDS: | |
8065 | case UNSPEC_LDS_A: | |
8066 | case UNSPEC_LDSA: | |
8067 | return code; | |
048d0d36 | 8068 | |
388092d5 AB |
8069 | default: |
8070 | return -1; | |
8071 | } | |
8072 | } | |
8073 | } | |
048d0d36 | 8074 | |
388092d5 AB |
8075 | /* Implement skip_rtx_p hook. */ |
8076 | static bool | |
8077 | ia64_skip_rtx_p (const_rtx x) | |
8078 | { | |
8079 | return get_spec_unspec_code (x) != -1; | |
8080 | } | |
048d0d36 | 8081 | |
388092d5 AB |
8082 | /* If INSN is a speculative load, return its UNSPEC code. |
8083 | Return -1 otherwise. */ | |
8084 | static int | |
8085 | get_insn_spec_code (const_rtx insn) | |
8086 | { | |
8087 | rtx pat, reg, mem; | |
048d0d36 | 8088 | |
388092d5 | 8089 | pat = PATTERN (insn); |
048d0d36 | 8090 | |
388092d5 AB |
8091 | if (GET_CODE (pat) == COND_EXEC) |
8092 | pat = COND_EXEC_CODE (pat); | |
048d0d36 | 8093 | |
388092d5 AB |
8094 | if (GET_CODE (pat) != SET) |
8095 | return -1; | |
8096 | ||
8097 | reg = SET_DEST (pat); | |
8098 | if (!REG_P (reg)) | |
8099 | return -1; | |
8100 | ||
8101 | mem = SET_SRC (pat); | |
8102 | if (GET_CODE (mem) == ZERO_EXTEND) | |
8103 | mem = XEXP (mem, 0); | |
8104 | ||
8105 | return get_spec_unspec_code (mem); | |
8106 | } | |
8107 | ||
8108 | /* If INSN is a speculative load, return a ds with the speculation types. | |
8109 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8110 | static ds_t | |
8111 | ia64_get_insn_spec_ds (rtx insn) | |
8112 | { | |
8113 | int code = get_insn_spec_code (insn); | |
8114 | ||
8115 | switch (code) | |
048d0d36 | 8116 | { |
388092d5 AB |
8117 | case UNSPEC_LDA: |
8118 | return BEGIN_DATA; | |
048d0d36 | 8119 | |
388092d5 AB |
8120 | case UNSPEC_LDS: |
8121 | case UNSPEC_LDS_A: | |
8122 | return BEGIN_CONTROL; | |
048d0d36 | 8123 | |
388092d5 AB |
8124 | case UNSPEC_LDSA: |
8125 | return BEGIN_DATA | BEGIN_CONTROL; | |
048d0d36 | 8126 | |
388092d5 AB |
8127 | default: |
8128 | return 0; | |
048d0d36 | 8129 | } |
388092d5 AB |
8130 | } |
8131 | ||
8132 | /* If INSN is a speculative load return a ds with the speculation types that | |
8133 | will be checked. | |
8134 | Otherwise [if INSN is a normal instruction] return 0. */ | |
8135 | static ds_t | |
8136 | ia64_get_insn_checked_ds (rtx insn) | |
8137 | { | |
8138 | int code = get_insn_spec_code (insn); | |
8139 | ||
8140 | switch (code) | |
048d0d36 | 8141 | { |
388092d5 AB |
8142 | case UNSPEC_LDA: |
8143 | return BEGIN_DATA | BEGIN_CONTROL; | |
8144 | ||
8145 | case UNSPEC_LDS: | |
8146 | return BEGIN_CONTROL; | |
8147 | ||
8148 | case UNSPEC_LDS_A: | |
8149 | case UNSPEC_LDSA: | |
8150 | return BEGIN_DATA | BEGIN_CONTROL; | |
8151 | ||
8152 | default: | |
8153 | return 0; | |
048d0d36 | 8154 | } |
388092d5 | 8155 | } |
048d0d36 | 8156 | |
388092d5 AB |
8157 | /* If GEN_P is true, calculate the index of needed speculation check and return |
8158 | speculative pattern for INSN with speculative mode TS, machine mode | |
8159 | MODE_NO and with ZERO_EXTEND (if EXTEND_P is true). | |
8160 | If GEN_P is false, just calculate the index of needed speculation check. */ | |
8161 | static rtx | |
8162 | ia64_gen_spec_load (rtx insn, ds_t ts, int mode_no) | |
8163 | { | |
8164 | rtx pat, new_pat; | |
8165 | gen_func_t gen_load; | |
048d0d36 | 8166 | |
388092d5 | 8167 | gen_load = get_spec_load_gen_function (ts, mode_no); |
048d0d36 | 8168 | |
388092d5 AB |
8169 | new_pat = gen_load (copy_rtx (recog_data.operand[0]), |
8170 | copy_rtx (recog_data.operand[1])); | |
048d0d36 MK |
8171 | |
8172 | pat = PATTERN (insn); | |
8173 | if (GET_CODE (pat) == COND_EXEC) | |
388092d5 AB |
8174 | new_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), |
8175 | new_pat); | |
048d0d36 MK |
8176 | |
8177 | return new_pat; | |
8178 | } | |
8179 | ||
048d0d36 | 8180 | static bool |
388092d5 AB |
8181 | insn_can_be_in_speculative_p (rtx insn ATTRIBUTE_UNUSED, |
8182 | ds_t ds ATTRIBUTE_UNUSED) | |
048d0d36 | 8183 | { |
388092d5 AB |
8184 | return false; |
8185 | } | |
048d0d36 | 8186 | |
388092d5 AB |
8187 | /* Implement targetm.sched.speculate_insn hook. |
8188 | Check if the INSN can be TS speculative. | |
8189 | If 'no' - return -1. | |
8190 | If 'yes' - generate speculative pattern in the NEW_PAT and return 1. | |
8191 | If current pattern of the INSN already provides TS speculation, | |
8192 | return 0. */ | |
8193 | static int | |
8194 | ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) | |
8195 | { | |
8196 | int mode_no; | |
8197 | int res; | |
8198 | ||
8199 | gcc_assert (!(ts & ~SPECULATIVE)); | |
048d0d36 | 8200 | |
388092d5 AB |
8201 | if (ia64_spec_check_p (insn)) |
8202 | return -1; | |
048d0d36 | 8203 | |
388092d5 AB |
8204 | if ((ts & BE_IN_SPEC) |
8205 | && !insn_can_be_in_speculative_p (insn, ts)) | |
8206 | return -1; | |
048d0d36 | 8207 | |
388092d5 | 8208 | mode_no = get_mode_no_for_insn (insn); |
048d0d36 | 8209 | |
388092d5 AB |
8210 | if (mode_no != SPEC_MODE_INVALID) |
8211 | { | |
8212 | if (ia64_get_insn_spec_ds (insn) == ds_get_speculation_types (ts)) | |
8213 | res = 0; | |
8214 | else | |
8215 | { | |
8216 | res = 1; | |
8217 | *new_pat = ia64_gen_spec_load (insn, ts, mode_no); | |
8218 | } | |
8219 | } | |
8220 | else | |
8221 | res = -1; | |
048d0d36 | 8222 | |
388092d5 AB |
8223 | return res; |
8224 | } | |
048d0d36 | 8225 | |
388092d5 AB |
8226 | /* Return a function that will generate a check for speculation TS with mode |
8227 | MODE_NO. | |
8228 | If simple check is needed, pass true for SIMPLE_CHECK_P. | |
8229 | If clearing check is needed, pass true for CLEARING_CHECK_P. */ | |
8230 | static gen_func_t | |
8231 | get_spec_check_gen_function (ds_t ts, int mode_no, | |
8232 | bool simple_check_p, bool clearing_check_p) | |
8233 | { | |
8234 | static gen_func_t gen_ld_c_clr[] = { | |
048d0d36 MK |
8235 | gen_movbi_clr, |
8236 | gen_movqi_clr, | |
8237 | gen_movhi_clr, | |
8238 | gen_movsi_clr, | |
8239 | gen_movdi_clr, | |
8240 | gen_movsf_clr, | |
8241 | gen_movdf_clr, | |
8242 | gen_movxf_clr, | |
8243 | gen_movti_clr, | |
8244 | gen_zero_extendqidi2_clr, | |
8245 | gen_zero_extendhidi2_clr, | |
8246 | gen_zero_extendsidi2_clr, | |
388092d5 AB |
8247 | }; |
8248 | static gen_func_t gen_ld_c_nc[] = { | |
8249 | gen_movbi_nc, | |
8250 | gen_movqi_nc, | |
8251 | gen_movhi_nc, | |
8252 | gen_movsi_nc, | |
8253 | gen_movdi_nc, | |
8254 | gen_movsf_nc, | |
8255 | gen_movdf_nc, | |
8256 | gen_movxf_nc, | |
8257 | gen_movti_nc, | |
8258 | gen_zero_extendqidi2_nc, | |
8259 | gen_zero_extendhidi2_nc, | |
8260 | gen_zero_extendsidi2_nc, | |
8261 | }; | |
8262 | static gen_func_t gen_chk_a_clr[] = { | |
048d0d36 MK |
8263 | gen_advanced_load_check_clr_bi, |
8264 | gen_advanced_load_check_clr_qi, | |
8265 | gen_advanced_load_check_clr_hi, | |
8266 | gen_advanced_load_check_clr_si, | |
8267 | gen_advanced_load_check_clr_di, | |
8268 | gen_advanced_load_check_clr_sf, | |
8269 | gen_advanced_load_check_clr_df, | |
8270 | gen_advanced_load_check_clr_xf, | |
8271 | gen_advanced_load_check_clr_ti, | |
8272 | gen_advanced_load_check_clr_di, | |
8273 | gen_advanced_load_check_clr_di, | |
8274 | gen_advanced_load_check_clr_di, | |
388092d5 AB |
8275 | }; |
8276 | static gen_func_t gen_chk_a_nc[] = { | |
8277 | gen_advanced_load_check_nc_bi, | |
8278 | gen_advanced_load_check_nc_qi, | |
8279 | gen_advanced_load_check_nc_hi, | |
8280 | gen_advanced_load_check_nc_si, | |
8281 | gen_advanced_load_check_nc_di, | |
8282 | gen_advanced_load_check_nc_sf, | |
8283 | gen_advanced_load_check_nc_df, | |
8284 | gen_advanced_load_check_nc_xf, | |
8285 | gen_advanced_load_check_nc_ti, | |
8286 | gen_advanced_load_check_nc_di, | |
8287 | gen_advanced_load_check_nc_di, | |
8288 | gen_advanced_load_check_nc_di, | |
8289 | }; | |
8290 | static gen_func_t gen_chk_s[] = { | |
048d0d36 MK |
8291 | gen_speculation_check_bi, |
8292 | gen_speculation_check_qi, | |
8293 | gen_speculation_check_hi, | |
8294 | gen_speculation_check_si, | |
8295 | gen_speculation_check_di, | |
8296 | gen_speculation_check_sf, | |
8297 | gen_speculation_check_df, | |
8298 | gen_speculation_check_xf, | |
8299 | gen_speculation_check_ti, | |
8300 | gen_speculation_check_di, | |
8301 | gen_speculation_check_di, | |
388092d5 | 8302 | gen_speculation_check_di, |
048d0d36 MK |
8303 | }; |
8304 | ||
388092d5 | 8305 | gen_func_t *gen_check; |
048d0d36 | 8306 | |
388092d5 | 8307 | if (ts & BEGIN_DATA) |
048d0d36 | 8308 | { |
388092d5 AB |
8309 | /* We don't need recovery because even if this is ld.sa |
8310 | ALAT entry will be allocated only if NAT bit is set to zero. | |
8311 | So it is enough to use ld.c here. */ | |
8312 | ||
8313 | if (simple_check_p) | |
8314 | { | |
8315 | gcc_assert (mflag_sched_spec_ldc); | |
8316 | ||
8317 | if (clearing_check_p) | |
8318 | gen_check = gen_ld_c_clr; | |
8319 | else | |
8320 | gen_check = gen_ld_c_nc; | |
8321 | } | |
8322 | else | |
8323 | { | |
8324 | if (clearing_check_p) | |
8325 | gen_check = gen_chk_a_clr; | |
8326 | else | |
8327 | gen_check = gen_chk_a_nc; | |
8328 | } | |
048d0d36 | 8329 | } |
388092d5 | 8330 | else if (ts & BEGIN_CONTROL) |
048d0d36 | 8331 | { |
388092d5 AB |
8332 | if (simple_check_p) |
8333 | /* We might want to use ld.sa -> ld.c instead of | |
8334 | ld.s -> chk.s. */ | |
048d0d36 | 8335 | { |
388092d5 | 8336 | gcc_assert (!ia64_needs_block_p (ts)); |
048d0d36 | 8337 | |
388092d5 AB |
8338 | if (clearing_check_p) |
8339 | gen_check = gen_ld_c_clr; | |
8340 | else | |
8341 | gen_check = gen_ld_c_nc; | |
8342 | } | |
8343 | else | |
8344 | { | |
8345 | gen_check = gen_chk_s; | |
048d0d36 | 8346 | } |
388092d5 AB |
8347 | } |
8348 | else | |
8349 | gcc_unreachable (); | |
8350 | ||
8351 | gcc_assert (mode_no >= 0); | |
8352 | return gen_check[mode_no]; | |
8353 | } | |
8354 | ||
8355 | /* Return nonzero, if INSN needs branchy recovery check. */ | |
8356 | static bool | |
8357 | ia64_needs_block_p (ds_t ts) | |
8358 | { | |
8359 | if (ts & BEGIN_DATA) | |
8360 | return !mflag_sched_spec_ldc; | |
8361 | ||
8362 | gcc_assert ((ts & BEGIN_CONTROL) != 0); | |
048d0d36 | 8363 | |
388092d5 AB |
8364 | return !(mflag_sched_spec_control_ldc && mflag_sched_spec_ldc); |
8365 | } | |
8366 | ||
8e90de43 | 8367 | /* Generate (or regenerate) a recovery check for INSN. */ |
388092d5 AB |
8368 | static rtx |
8369 | ia64_gen_spec_check (rtx insn, rtx label, ds_t ds) | |
8370 | { | |
8371 | rtx op1, pat, check_pat; | |
8372 | gen_func_t gen_check; | |
8373 | int mode_no; | |
8374 | ||
8375 | mode_no = get_mode_no_for_insn (insn); | |
8376 | gcc_assert (mode_no >= 0); | |
8377 | ||
8378 | if (label) | |
8379 | op1 = label; | |
8380 | else | |
8381 | { | |
8382 | gcc_assert (!ia64_needs_block_p (ds)); | |
8383 | op1 = copy_rtx (recog_data.operand[1]); | |
048d0d36 | 8384 | } |
388092d5 AB |
8385 | |
8386 | gen_check = get_spec_check_gen_function (ds, mode_no, label == NULL_RTX, | |
8387 | true); | |
048d0d36 | 8388 | |
388092d5 | 8389 | check_pat = gen_check (copy_rtx (recog_data.operand[0]), op1); |
048d0d36 MK |
8390 | |
8391 | pat = PATTERN (insn); | |
8392 | if (GET_CODE (pat) == COND_EXEC) | |
8393 | check_pat = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (COND_EXEC_TEST (pat)), | |
8394 | check_pat); | |
8395 | ||
8396 | return check_pat; | |
8397 | } | |
8398 | ||
8399 | /* Return nonzero, if X is branchy recovery check. */ | |
8400 | static int | |
8401 | ia64_spec_check_p (rtx x) | |
8402 | { | |
8403 | x = PATTERN (x); | |
8404 | if (GET_CODE (x) == COND_EXEC) | |
8405 | x = COND_EXEC_CODE (x); | |
8406 | if (GET_CODE (x) == SET) | |
8407 | return ia64_spec_check_src_p (SET_SRC (x)); | |
8408 | return 0; | |
8409 | } | |
8410 | ||
8411 | /* Return nonzero, if SRC belongs to recovery check. */ | |
8412 | static int | |
8413 | ia64_spec_check_src_p (rtx src) | |
8414 | { | |
8415 | if (GET_CODE (src) == IF_THEN_ELSE) | |
8416 | { | |
8417 | rtx t; | |
8418 | ||
8419 | t = XEXP (src, 0); | |
8420 | if (GET_CODE (t) == NE) | |
8421 | { | |
8422 | t = XEXP (t, 0); | |
8423 | ||
8424 | if (GET_CODE (t) == UNSPEC) | |
8425 | { | |
8426 | int code; | |
8427 | ||
8428 | code = XINT (t, 1); | |
8429 | ||
388092d5 AB |
8430 | if (code == UNSPEC_LDCCLR |
8431 | || code == UNSPEC_LDCNC | |
8432 | || code == UNSPEC_CHKACLR | |
8433 | || code == UNSPEC_CHKANC | |
8434 | || code == UNSPEC_CHKS) | |
048d0d36 MK |
8435 | { |
8436 | gcc_assert (code != 0); | |
8437 | return code; | |
8438 | } | |
8439 | } | |
8440 | } | |
8441 | } | |
8442 | return 0; | |
8443 | } | |
30028c85 | 8444 | \f |
2130b7fb | 8445 | |
30028c85 VM |
8446 | /* The following page contains abstract data `bundle states' which are |
8447 | used for bundling insns (inserting nops and template generation). */ | |
8448 | ||
8449 | /* The following describes state of insn bundling. */ | |
8450 | ||
8451 | struct bundle_state | |
8452 | { | |
8453 | /* Unique bundle state number to identify them in the debugging | |
8454 | output */ | |
8455 | int unique_num; | |
8456 | rtx insn; /* corresponding insn, NULL for the 1st and the last state */ | |
8457 | /* number nops before and after the insn */ | |
8458 | short before_nops_num, after_nops_num; | |
8459 | int insn_num; /* insn number (0 - for initial state, 1 - for the 1st | |
8460 | insn */ | |
8461 | int cost; /* cost of the state in cycles */ | |
8462 | int accumulated_insns_num; /* number of all previous insns including | |
8463 | nops. L is considered as 2 insns */ | |
8464 | int branch_deviation; /* deviation of previous branches from 3rd slots */ | |
388092d5 | 8465 | int middle_bundle_stops; /* number of stop bits in the middle of bundles */ |
30028c85 VM |
8466 | struct bundle_state *next; /* next state with the same insn_num */ |
8467 | struct bundle_state *originator; /* originator (previous insn state) */ | |
8468 | /* All bundle states are in the following chain. */ | |
8469 | struct bundle_state *allocated_states_chain; | |
8470 | /* The DFA State after issuing the insn and the nops. */ | |
8471 | state_t dfa_state; | |
8472 | }; | |
2130b7fb | 8473 | |
30028c85 | 8474 | /* The following is map insn number to the corresponding bundle state. */ |
2130b7fb | 8475 | |
30028c85 | 8476 | static struct bundle_state **index_to_bundle_states; |
2130b7fb | 8477 | |
30028c85 | 8478 | /* The unique number of next bundle state. */ |
2130b7fb | 8479 | |
30028c85 | 8480 | static int bundle_states_num; |
2130b7fb | 8481 | |
30028c85 | 8482 | /* All allocated bundle states are in the following chain. */ |
2130b7fb | 8483 | |
30028c85 | 8484 | static struct bundle_state *allocated_bundle_states_chain; |
e57b9d65 | 8485 | |
30028c85 VM |
8486 | /* All allocated but not used bundle states are in the following |
8487 | chain. */ | |
870f9ec0 | 8488 | |
30028c85 | 8489 | static struct bundle_state *free_bundle_state_chain; |
2130b7fb | 8490 | |
2130b7fb | 8491 | |
30028c85 | 8492 | /* The following function returns a free bundle state. */ |
2130b7fb | 8493 | |
30028c85 | 8494 | static struct bundle_state * |
9c808aad | 8495 | get_free_bundle_state (void) |
30028c85 VM |
8496 | { |
8497 | struct bundle_state *result; | |
2130b7fb | 8498 | |
30028c85 | 8499 | if (free_bundle_state_chain != NULL) |
2130b7fb | 8500 | { |
30028c85 VM |
8501 | result = free_bundle_state_chain; |
8502 | free_bundle_state_chain = result->next; | |
2130b7fb | 8503 | } |
30028c85 | 8504 | else |
2130b7fb | 8505 | { |
5ead67f6 | 8506 | result = XNEW (struct bundle_state); |
30028c85 VM |
8507 | result->dfa_state = xmalloc (dfa_state_size); |
8508 | result->allocated_states_chain = allocated_bundle_states_chain; | |
8509 | allocated_bundle_states_chain = result; | |
2130b7fb | 8510 | } |
30028c85 VM |
8511 | result->unique_num = bundle_states_num++; |
8512 | return result; | |
9c808aad | 8513 | |
30028c85 | 8514 | } |
2130b7fb | 8515 | |
30028c85 | 8516 | /* The following function frees given bundle state. */ |
2130b7fb | 8517 | |
30028c85 | 8518 | static void |
9c808aad | 8519 | free_bundle_state (struct bundle_state *state) |
30028c85 VM |
8520 | { |
8521 | state->next = free_bundle_state_chain; | |
8522 | free_bundle_state_chain = state; | |
8523 | } | |
2130b7fb | 8524 | |
30028c85 | 8525 | /* Start work with abstract data `bundle states'. */ |
2130b7fb | 8526 | |
30028c85 | 8527 | static void |
9c808aad | 8528 | initiate_bundle_states (void) |
30028c85 VM |
8529 | { |
8530 | bundle_states_num = 0; | |
8531 | free_bundle_state_chain = NULL; | |
8532 | allocated_bundle_states_chain = NULL; | |
2130b7fb BS |
8533 | } |
8534 | ||
30028c85 | 8535 | /* Finish work with abstract data `bundle states'. */ |
2130b7fb BS |
8536 | |
8537 | static void | |
9c808aad | 8538 | finish_bundle_states (void) |
2130b7fb | 8539 | { |
30028c85 VM |
8540 | struct bundle_state *curr_state, *next_state; |
8541 | ||
8542 | for (curr_state = allocated_bundle_states_chain; | |
8543 | curr_state != NULL; | |
8544 | curr_state = next_state) | |
2130b7fb | 8545 | { |
30028c85 VM |
8546 | next_state = curr_state->allocated_states_chain; |
8547 | free (curr_state->dfa_state); | |
8548 | free (curr_state); | |
2130b7fb | 8549 | } |
2130b7fb BS |
8550 | } |
8551 | ||
3a4f280b | 8552 | /* Hashtable helpers. */ |
2130b7fb | 8553 | |
3a4f280b LC |
8554 | struct bundle_state_hasher : typed_noop_remove <bundle_state> |
8555 | { | |
8556 | typedef bundle_state value_type; | |
8557 | typedef bundle_state compare_type; | |
8558 | static inline hashval_t hash (const value_type *); | |
8559 | static inline bool equal (const value_type *, const compare_type *); | |
8560 | }; | |
2130b7fb | 8561 | |
30028c85 | 8562 | /* The function returns hash of BUNDLE_STATE. */ |
2130b7fb | 8563 | |
3a4f280b LC |
8564 | inline hashval_t |
8565 | bundle_state_hasher::hash (const value_type *state) | |
30028c85 | 8566 | { |
30028c85 | 8567 | unsigned result, i; |
2130b7fb | 8568 | |
30028c85 VM |
8569 | for (result = i = 0; i < dfa_state_size; i++) |
8570 | result += (((unsigned char *) state->dfa_state) [i] | |
8571 | << ((i % CHAR_BIT) * 3 + CHAR_BIT)); | |
8572 | return result + state->insn_num; | |
8573 | } | |
2130b7fb | 8574 | |
30028c85 | 8575 | /* The function returns nonzero if the bundle state keys are equal. */ |
2130b7fb | 8576 | |
3a4f280b LC |
8577 | inline bool |
8578 | bundle_state_hasher::equal (const value_type *state1, | |
8579 | const compare_type *state2) | |
30028c85 | 8580 | { |
30028c85 VM |
8581 | return (state1->insn_num == state2->insn_num |
8582 | && memcmp (state1->dfa_state, state2->dfa_state, | |
8583 | dfa_state_size) == 0); | |
8584 | } | |
2130b7fb | 8585 | |
3a4f280b LC |
8586 | /* Hash table of the bundle states. The key is dfa_state and insn_num |
8587 | of the bundle states. */ | |
8588 | ||
8589 | static hash_table <bundle_state_hasher> bundle_state_table; | |
8590 | ||
30028c85 VM |
8591 | /* The function inserts the BUNDLE_STATE into the hash table. The |
8592 | function returns nonzero if the bundle has been inserted into the | |
8593 | table. The table contains the best bundle state with given key. */ | |
2130b7fb | 8594 | |
30028c85 | 8595 | static int |
9c808aad | 8596 | insert_bundle_state (struct bundle_state *bundle_state) |
30028c85 | 8597 | { |
3a4f280b | 8598 | struct bundle_state **entry_ptr; |
2130b7fb | 8599 | |
3a4f280b | 8600 | entry_ptr = bundle_state_table.find_slot (bundle_state, INSERT); |
30028c85 VM |
8601 | if (*entry_ptr == NULL) |
8602 | { | |
8603 | bundle_state->next = index_to_bundle_states [bundle_state->insn_num]; | |
8604 | index_to_bundle_states [bundle_state->insn_num] = bundle_state; | |
3a4f280b | 8605 | *entry_ptr = bundle_state; |
30028c85 | 8606 | return TRUE; |
2130b7fb | 8607 | } |
3a4f280b LC |
8608 | else if (bundle_state->cost < (*entry_ptr)->cost |
8609 | || (bundle_state->cost == (*entry_ptr)->cost | |
8610 | && ((*entry_ptr)->accumulated_insns_num | |
30028c85 | 8611 | > bundle_state->accumulated_insns_num |
3a4f280b | 8612 | || ((*entry_ptr)->accumulated_insns_num |
30028c85 | 8613 | == bundle_state->accumulated_insns_num |
3a4f280b | 8614 | && ((*entry_ptr)->branch_deviation |
388092d5 | 8615 | > bundle_state->branch_deviation |
3a4f280b | 8616 | || ((*entry_ptr)->branch_deviation |
388092d5 | 8617 | == bundle_state->branch_deviation |
3a4f280b | 8618 | && (*entry_ptr)->middle_bundle_stops |
388092d5 | 8619 | > bundle_state->middle_bundle_stops)))))) |
9c808aad | 8620 | |
2130b7fb | 8621 | { |
30028c85 VM |
8622 | struct bundle_state temp; |
8623 | ||
3a4f280b LC |
8624 | temp = **entry_ptr; |
8625 | **entry_ptr = *bundle_state; | |
8626 | (*entry_ptr)->next = temp.next; | |
30028c85 | 8627 | *bundle_state = temp; |
2130b7fb | 8628 | } |
30028c85 VM |
8629 | return FALSE; |
8630 | } | |
2130b7fb | 8631 | |
30028c85 VM |
8632 | /* Start work with the hash table. */ |
8633 | ||
8634 | static void | |
9c808aad | 8635 | initiate_bundle_state_table (void) |
30028c85 | 8636 | { |
3a4f280b | 8637 | bundle_state_table.create (50); |
2130b7fb BS |
8638 | } |
8639 | ||
30028c85 | 8640 | /* Finish work with the hash table. */ |
e4027dab BS |
8641 | |
8642 | static void | |
9c808aad | 8643 | finish_bundle_state_table (void) |
e4027dab | 8644 | { |
3a4f280b | 8645 | bundle_state_table.dispose (); |
e4027dab BS |
8646 | } |
8647 | ||
30028c85 | 8648 | \f |
a0a7b566 | 8649 | |
30028c85 VM |
8650 | /* The following variable is a insn `nop' used to check bundle states |
8651 | with different number of inserted nops. */ | |
a0a7b566 | 8652 | |
30028c85 | 8653 | static rtx ia64_nop; |
a0a7b566 | 8654 | |
30028c85 VM |
8655 | /* The following function tries to issue NOPS_NUM nops for the current |
8656 | state without advancing processor cycle. If it failed, the | |
8657 | function returns FALSE and frees the current state. */ | |
8658 | ||
8659 | static int | |
9c808aad | 8660 | try_issue_nops (struct bundle_state *curr_state, int nops_num) |
a0a7b566 | 8661 | { |
30028c85 | 8662 | int i; |
a0a7b566 | 8663 | |
30028c85 VM |
8664 | for (i = 0; i < nops_num; i++) |
8665 | if (state_transition (curr_state->dfa_state, ia64_nop) >= 0) | |
8666 | { | |
8667 | free_bundle_state (curr_state); | |
8668 | return FALSE; | |
8669 | } | |
8670 | return TRUE; | |
8671 | } | |
a0a7b566 | 8672 | |
30028c85 VM |
8673 | /* The following function tries to issue INSN for the current |
8674 | state without advancing processor cycle. If it failed, the | |
8675 | function returns FALSE and frees the current state. */ | |
a0a7b566 | 8676 | |
30028c85 | 8677 | static int |
9c808aad | 8678 | try_issue_insn (struct bundle_state *curr_state, rtx insn) |
30028c85 VM |
8679 | { |
8680 | if (insn && state_transition (curr_state->dfa_state, insn) >= 0) | |
8681 | { | |
8682 | free_bundle_state (curr_state); | |
8683 | return FALSE; | |
8684 | } | |
8685 | return TRUE; | |
8686 | } | |
a0a7b566 | 8687 | |
30028c85 VM |
8688 | /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN |
8689 | starting with ORIGINATOR without advancing processor cycle. If | |
f32360c7 VM |
8690 | TRY_BUNDLE_END_P is TRUE, the function also/only (if |
8691 | ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle. | |
8692 | If it was successful, the function creates new bundle state and | |
8693 | insert into the hash table and into `index_to_bundle_states'. */ | |
a0a7b566 | 8694 | |
30028c85 | 8695 | static void |
9c808aad AJ |
8696 | issue_nops_and_insn (struct bundle_state *originator, int before_nops_num, |
8697 | rtx insn, int try_bundle_end_p, int only_bundle_end_p) | |
30028c85 VM |
8698 | { |
8699 | struct bundle_state *curr_state; | |
8700 | ||
8701 | curr_state = get_free_bundle_state (); | |
8702 | memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size); | |
8703 | curr_state->insn = insn; | |
8704 | curr_state->insn_num = originator->insn_num + 1; | |
8705 | curr_state->cost = originator->cost; | |
8706 | curr_state->originator = originator; | |
8707 | curr_state->before_nops_num = before_nops_num; | |
8708 | curr_state->after_nops_num = 0; | |
8709 | curr_state->accumulated_insns_num | |
8710 | = originator->accumulated_insns_num + before_nops_num; | |
8711 | curr_state->branch_deviation = originator->branch_deviation; | |
388092d5 | 8712 | curr_state->middle_bundle_stops = originator->middle_bundle_stops; |
e820471b NS |
8713 | gcc_assert (insn); |
8714 | if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier) | |
30028c85 | 8715 | { |
e820471b | 8716 | gcc_assert (GET_MODE (insn) != TImode); |
30028c85 VM |
8717 | if (!try_issue_nops (curr_state, before_nops_num)) |
8718 | return; | |
8719 | if (!try_issue_insn (curr_state, insn)) | |
8720 | return; | |
8721 | memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size); | |
388092d5 AB |
8722 | if (curr_state->accumulated_insns_num % 3 != 0) |
8723 | curr_state->middle_bundle_stops++; | |
30028c85 VM |
8724 | if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0 |
8725 | && curr_state->accumulated_insns_num % 3 != 0) | |
a0a7b566 | 8726 | { |
30028c85 VM |
8727 | free_bundle_state (curr_state); |
8728 | return; | |
a0a7b566 | 8729 | } |
a0a7b566 | 8730 | } |
30028c85 | 8731 | else if (GET_MODE (insn) != TImode) |
a0a7b566 | 8732 | { |
30028c85 VM |
8733 | if (!try_issue_nops (curr_state, before_nops_num)) |
8734 | return; | |
8735 | if (!try_issue_insn (curr_state, insn)) | |
8736 | return; | |
f32360c7 | 8737 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8738 | gcc_assert (!unknown_for_bundling_p (insn)); |
e820471b | 8739 | |
30028c85 VM |
8740 | if (ia64_safe_type (insn) == TYPE_L) |
8741 | curr_state->accumulated_insns_num++; | |
8742 | } | |
8743 | else | |
8744 | { | |
68e11b42 JW |
8745 | /* If this is an insn that must be first in a group, then don't allow |
8746 | nops to be emitted before it. Currently, alloc is the only such | |
8747 | supported instruction. */ | |
8748 | /* ??? The bundling automatons should handle this for us, but they do | |
8749 | not yet have support for the first_insn attribute. */ | |
8750 | if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES) | |
8751 | { | |
8752 | free_bundle_state (curr_state); | |
8753 | return; | |
8754 | } | |
8755 | ||
30028c85 VM |
8756 | state_transition (curr_state->dfa_state, dfa_pre_cycle_insn); |
8757 | state_transition (curr_state->dfa_state, NULL); | |
8758 | curr_state->cost++; | |
8759 | if (!try_issue_nops (curr_state, before_nops_num)) | |
8760 | return; | |
8761 | if (!try_issue_insn (curr_state, insn)) | |
8762 | return; | |
f32360c7 | 8763 | curr_state->accumulated_insns_num++; |
7b84aac0 | 8764 | if (unknown_for_bundling_p (insn)) |
f32360c7 VM |
8765 | { |
8766 | /* Finish bundle containing asm insn. */ | |
8767 | curr_state->after_nops_num | |
8768 | = 3 - curr_state->accumulated_insns_num % 3; | |
8769 | curr_state->accumulated_insns_num | |
8770 | += 3 - curr_state->accumulated_insns_num % 3; | |
8771 | } | |
8772 | else if (ia64_safe_type (insn) == TYPE_L) | |
30028c85 VM |
8773 | curr_state->accumulated_insns_num++; |
8774 | } | |
8775 | if (ia64_safe_type (insn) == TYPE_B) | |
8776 | curr_state->branch_deviation | |
8777 | += 2 - (curr_state->accumulated_insns_num - 1) % 3; | |
8778 | if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0) | |
8779 | { | |
f32360c7 | 8780 | if (!only_bundle_end_p && insert_bundle_state (curr_state)) |
a0a7b566 | 8781 | { |
30028c85 VM |
8782 | state_t dfa_state; |
8783 | struct bundle_state *curr_state1; | |
8784 | struct bundle_state *allocated_states_chain; | |
8785 | ||
8786 | curr_state1 = get_free_bundle_state (); | |
8787 | dfa_state = curr_state1->dfa_state; | |
8788 | allocated_states_chain = curr_state1->allocated_states_chain; | |
8789 | *curr_state1 = *curr_state; | |
8790 | curr_state1->dfa_state = dfa_state; | |
8791 | curr_state1->allocated_states_chain = allocated_states_chain; | |
8792 | memcpy (curr_state1->dfa_state, curr_state->dfa_state, | |
8793 | dfa_state_size); | |
8794 | curr_state = curr_state1; | |
a0a7b566 | 8795 | } |
30028c85 VM |
8796 | if (!try_issue_nops (curr_state, |
8797 | 3 - curr_state->accumulated_insns_num % 3)) | |
8798 | return; | |
8799 | curr_state->after_nops_num | |
8800 | = 3 - curr_state->accumulated_insns_num % 3; | |
8801 | curr_state->accumulated_insns_num | |
8802 | += 3 - curr_state->accumulated_insns_num % 3; | |
a0a7b566 | 8803 | } |
30028c85 VM |
8804 | if (!insert_bundle_state (curr_state)) |
8805 | free_bundle_state (curr_state); | |
8806 | return; | |
8807 | } | |
e013f3c7 | 8808 | |
30028c85 VM |
8809 | /* The following function returns position in the two window bundle |
8810 | for given STATE. */ | |
8811 | ||
8812 | static int | |
9c808aad | 8813 | get_max_pos (state_t state) |
30028c85 VM |
8814 | { |
8815 | if (cpu_unit_reservation_p (state, pos_6)) | |
8816 | return 6; | |
8817 | else if (cpu_unit_reservation_p (state, pos_5)) | |
8818 | return 5; | |
8819 | else if (cpu_unit_reservation_p (state, pos_4)) | |
8820 | return 4; | |
8821 | else if (cpu_unit_reservation_p (state, pos_3)) | |
8822 | return 3; | |
8823 | else if (cpu_unit_reservation_p (state, pos_2)) | |
8824 | return 2; | |
8825 | else if (cpu_unit_reservation_p (state, pos_1)) | |
8826 | return 1; | |
8827 | else | |
8828 | return 0; | |
a0a7b566 BS |
8829 | } |
8830 | ||
30028c85 VM |
8831 | /* The function returns code of a possible template for given position |
8832 | and state. The function should be called only with 2 values of | |
96ddf8ef VM |
8833 | position equal to 3 or 6. We avoid generating F NOPs by putting |
8834 | templates containing F insns at the end of the template search | |
8835 | because undocumented anomaly in McKinley derived cores which can | |
8836 | cause stalls if an F-unit insn (including a NOP) is issued within a | |
8837 | six-cycle window after reading certain application registers (such | |
8838 | as ar.bsp). Furthermore, power-considerations also argue against | |
8839 | the use of F-unit instructions unless they're really needed. */ | |
2130b7fb | 8840 | |
c237e94a | 8841 | static int |
9c808aad | 8842 | get_template (state_t state, int pos) |
2130b7fb | 8843 | { |
30028c85 | 8844 | switch (pos) |
2130b7fb | 8845 | { |
30028c85 | 8846 | case 3: |
96ddf8ef | 8847 | if (cpu_unit_reservation_p (state, _0mmi_)) |
30028c85 | 8848 | return 1; |
96ddf8ef VM |
8849 | else if (cpu_unit_reservation_p (state, _0mii_)) |
8850 | return 0; | |
30028c85 VM |
8851 | else if (cpu_unit_reservation_p (state, _0mmb_)) |
8852 | return 7; | |
96ddf8ef VM |
8853 | else if (cpu_unit_reservation_p (state, _0mib_)) |
8854 | return 6; | |
8855 | else if (cpu_unit_reservation_p (state, _0mbb_)) | |
8856 | return 5; | |
8857 | else if (cpu_unit_reservation_p (state, _0bbb_)) | |
8858 | return 4; | |
8859 | else if (cpu_unit_reservation_p (state, _0mmf_)) | |
8860 | return 3; | |
8861 | else if (cpu_unit_reservation_p (state, _0mfi_)) | |
8862 | return 2; | |
30028c85 VM |
8863 | else if (cpu_unit_reservation_p (state, _0mfb_)) |
8864 | return 8; | |
8865 | else if (cpu_unit_reservation_p (state, _0mlx_)) | |
8866 | return 9; | |
8867 | else | |
e820471b | 8868 | gcc_unreachable (); |
30028c85 | 8869 | case 6: |
96ddf8ef | 8870 | if (cpu_unit_reservation_p (state, _1mmi_)) |
30028c85 | 8871 | return 1; |
96ddf8ef VM |
8872 | else if (cpu_unit_reservation_p (state, _1mii_)) |
8873 | return 0; | |
30028c85 VM |
8874 | else if (cpu_unit_reservation_p (state, _1mmb_)) |
8875 | return 7; | |
96ddf8ef VM |
8876 | else if (cpu_unit_reservation_p (state, _1mib_)) |
8877 | return 6; | |
8878 | else if (cpu_unit_reservation_p (state, _1mbb_)) | |
8879 | return 5; | |
8880 | else if (cpu_unit_reservation_p (state, _1bbb_)) | |
8881 | return 4; | |
8882 | else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_)) | |
8883 | return 3; | |
8884 | else if (cpu_unit_reservation_p (state, _1mfi_)) | |
8885 | return 2; | |
30028c85 VM |
8886 | else if (cpu_unit_reservation_p (state, _1mfb_)) |
8887 | return 8; | |
8888 | else if (cpu_unit_reservation_p (state, _1mlx_)) | |
8889 | return 9; | |
8890 | else | |
e820471b | 8891 | gcc_unreachable (); |
30028c85 | 8892 | default: |
e820471b | 8893 | gcc_unreachable (); |
2130b7fb | 8894 | } |
30028c85 | 8895 | } |
2130b7fb | 8896 | |
388092d5 | 8897 | /* True when INSN is important for bundling. */ |
7b84aac0 | 8898 | |
388092d5 AB |
8899 | static bool |
8900 | important_for_bundling_p (rtx insn) | |
8901 | { | |
8902 | return (INSN_P (insn) | |
8903 | && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE | |
8904 | && GET_CODE (PATTERN (insn)) != USE | |
8905 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8906 | } | |
8907 | ||
30028c85 VM |
8908 | /* The following function returns an insn important for insn bundling |
8909 | followed by INSN and before TAIL. */ | |
a0a7b566 | 8910 | |
30028c85 | 8911 | static rtx |
9c808aad | 8912 | get_next_important_insn (rtx insn, rtx tail) |
30028c85 VM |
8913 | { |
8914 | for (; insn && insn != tail; insn = NEXT_INSN (insn)) | |
388092d5 | 8915 | if (important_for_bundling_p (insn)) |
30028c85 VM |
8916 | return insn; |
8917 | return NULL_RTX; | |
8918 | } | |
8919 | ||
7b84aac0 EB |
8920 | /* True when INSN is unknown, but important, for bundling. */ |
8921 | ||
8922 | static bool | |
8923 | unknown_for_bundling_p (rtx insn) | |
8924 | { | |
8925 | return (INSN_P (insn) | |
8926 | && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_UNKNOWN | |
8927 | && GET_CODE (PATTERN (insn)) != USE | |
8928 | && GET_CODE (PATTERN (insn)) != CLOBBER); | |
8929 | } | |
8930 | ||
4a4cd49c JJ |
8931 | /* Add a bundle selector TEMPLATE0 before INSN. */ |
8932 | ||
8933 | static void | |
8934 | ia64_add_bundle_selector_before (int template0, rtx insn) | |
8935 | { | |
8936 | rtx b = gen_bundle_selector (GEN_INT (template0)); | |
8937 | ||
8938 | ia64_emit_insn_before (b, insn); | |
8939 | #if NR_BUNDLES == 10 | |
8940 | if ((template0 == 4 || template0 == 5) | |
d5fabb58 | 8941 | && ia64_except_unwind_info (&global_options) == UI_TARGET) |
4a4cd49c JJ |
8942 | { |
8943 | int i; | |
8944 | rtx note = NULL_RTX; | |
8945 | ||
8946 | /* In .mbb and .bbb bundles, check if CALL_INSN isn't in the | |
8947 | first or second slot. If it is and has REG_EH_NOTE set, copy it | |
8948 | to following nops, as br.call sets rp to the address of following | |
8949 | bundle and therefore an EH region end must be on a bundle | |
8950 | boundary. */ | |
8951 | insn = PREV_INSN (insn); | |
8952 | for (i = 0; i < 3; i++) | |
8953 | { | |
8954 | do | |
8955 | insn = next_active_insn (insn); | |
b64925dc | 8956 | while (NONJUMP_INSN_P (insn) |
4a4cd49c | 8957 | && get_attr_empty (insn) == EMPTY_YES); |
b64925dc | 8958 | if (CALL_P (insn)) |
4a4cd49c JJ |
8959 | note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); |
8960 | else if (note) | |
8961 | { | |
8962 | int code; | |
8963 | ||
8964 | gcc_assert ((code = recog_memoized (insn)) == CODE_FOR_nop | |
8965 | || code == CODE_FOR_nop_b); | |
8966 | if (find_reg_note (insn, REG_EH_REGION, NULL_RTX)) | |
8967 | note = NULL_RTX; | |
8968 | else | |
bbbbb16a | 8969 | add_reg_note (insn, REG_EH_REGION, XEXP (note, 0)); |
4a4cd49c JJ |
8970 | } |
8971 | } | |
8972 | } | |
8973 | #endif | |
8974 | } | |
8975 | ||
c856f536 VM |
8976 | /* The following function does insn bundling. Bundling means |
8977 | inserting templates and nop insns to fit insn groups into permitted | |
8978 | templates. Instruction scheduling uses NDFA (non-deterministic | |
8979 | finite automata) encoding informations about the templates and the | |
8980 | inserted nops. Nondeterminism of the automata permits follows | |
8981 | all possible insn sequences very fast. | |
8982 | ||
8983 | Unfortunately it is not possible to get information about inserting | |
8984 | nop insns and used templates from the automata states. The | |
8985 | automata only says that we can issue an insn possibly inserting | |
8986 | some nops before it and using some template. Therefore insn | |
8987 | bundling in this function is implemented by using DFA | |
048d0d36 | 8988 | (deterministic finite automata). We follow all possible insn |
c856f536 VM |
8989 | sequences by inserting 0-2 nops (that is what the NDFA describe for |
8990 | insn scheduling) before/after each insn being bundled. We know the | |
8991 | start of simulated processor cycle from insn scheduling (insn | |
8992 | starting a new cycle has TImode). | |
8993 | ||
8994 | Simple implementation of insn bundling would create enormous | |
8995 | number of possible insn sequences satisfying information about new | |
8996 | cycle ticks taken from the insn scheduling. To make the algorithm | |
8997 | practical we use dynamic programming. Each decision (about | |
8998 | inserting nops and implicitly about previous decisions) is described | |
8999 | by structure bundle_state (see above). If we generate the same | |
9000 | bundle state (key is automaton state after issuing the insns and | |
9001 | nops for it), we reuse already generated one. As consequence we | |
1e5f1716 | 9002 | reject some decisions which cannot improve the solution and |
c856f536 VM |
9003 | reduce memory for the algorithm. |
9004 | ||
9005 | When we reach the end of EBB (extended basic block), we choose the | |
9006 | best sequence and then, moving back in EBB, insert templates for | |
9007 | the best alternative. The templates are taken from querying | |
9008 | automaton state for each insn in chosen bundle states. | |
9009 | ||
9010 | So the algorithm makes two (forward and backward) passes through | |
7400e46b | 9011 | EBB. */ |
a0a7b566 | 9012 | |
30028c85 | 9013 | static void |
9c808aad | 9014 | bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail) |
30028c85 VM |
9015 | { |
9016 | struct bundle_state *curr_state, *next_state, *best_state; | |
9017 | rtx insn, next_insn; | |
9018 | int insn_num; | |
f32360c7 | 9019 | int i, bundle_end_p, only_bundle_end_p, asm_p; |
74601584 | 9020 | int pos = 0, max_pos, template0, template1; |
30028c85 VM |
9021 | rtx b; |
9022 | rtx nop; | |
9023 | enum attr_type type; | |
2d1b811d | 9024 | |
30028c85 | 9025 | insn_num = 0; |
c856f536 | 9026 | /* Count insns in the EBB. */ |
30028c85 VM |
9027 | for (insn = NEXT_INSN (prev_head_insn); |
9028 | insn && insn != tail; | |
9029 | insn = NEXT_INSN (insn)) | |
9030 | if (INSN_P (insn)) | |
9031 | insn_num++; | |
9032 | if (insn_num == 0) | |
9033 | return; | |
9034 | bundling_p = 1; | |
9035 | dfa_clean_insn_cache (); | |
9036 | initiate_bundle_state_table (); | |
5ead67f6 | 9037 | index_to_bundle_states = XNEWVEC (struct bundle_state *, insn_num + 2); |
ff482c8d | 9038 | /* First (forward) pass -- generation of bundle states. */ |
30028c85 VM |
9039 | curr_state = get_free_bundle_state (); |
9040 | curr_state->insn = NULL; | |
9041 | curr_state->before_nops_num = 0; | |
9042 | curr_state->after_nops_num = 0; | |
9043 | curr_state->insn_num = 0; | |
9044 | curr_state->cost = 0; | |
9045 | curr_state->accumulated_insns_num = 0; | |
9046 | curr_state->branch_deviation = 0; | |
388092d5 | 9047 | curr_state->middle_bundle_stops = 0; |
30028c85 VM |
9048 | curr_state->next = NULL; |
9049 | curr_state->originator = NULL; | |
9050 | state_reset (curr_state->dfa_state); | |
9051 | index_to_bundle_states [0] = curr_state; | |
9052 | insn_num = 0; | |
c856f536 | 9053 | /* Shift cycle mark if it is put on insn which could be ignored. */ |
30028c85 VM |
9054 | for (insn = NEXT_INSN (prev_head_insn); |
9055 | insn != tail; | |
9056 | insn = NEXT_INSN (insn)) | |
9057 | if (INSN_P (insn) | |
7b84aac0 | 9058 | && !important_for_bundling_p (insn) |
30028c85 | 9059 | && GET_MODE (insn) == TImode) |
2130b7fb | 9060 | { |
30028c85 VM |
9061 | PUT_MODE (insn, VOIDmode); |
9062 | for (next_insn = NEXT_INSN (insn); | |
9063 | next_insn != tail; | |
9064 | next_insn = NEXT_INSN (next_insn)) | |
7b84aac0 | 9065 | if (important_for_bundling_p (next_insn) |
388092d5 | 9066 | && INSN_CODE (next_insn) != CODE_FOR_insn_group_barrier) |
30028c85 VM |
9067 | { |
9068 | PUT_MODE (next_insn, TImode); | |
9069 | break; | |
9070 | } | |
2130b7fb | 9071 | } |
048d0d36 | 9072 | /* Forward pass: generation of bundle states. */ |
30028c85 VM |
9073 | for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail); |
9074 | insn != NULL_RTX; | |
9075 | insn = next_insn) | |
1ad72cef | 9076 | { |
7b84aac0 | 9077 | gcc_assert (important_for_bundling_p (insn)); |
f32360c7 | 9078 | type = ia64_safe_type (insn); |
30028c85 VM |
9079 | next_insn = get_next_important_insn (NEXT_INSN (insn), tail); |
9080 | insn_num++; | |
9081 | index_to_bundle_states [insn_num] = NULL; | |
9082 | for (curr_state = index_to_bundle_states [insn_num - 1]; | |
9083 | curr_state != NULL; | |
9084 | curr_state = next_state) | |
f83594c4 | 9085 | { |
30028c85 | 9086 | pos = curr_state->accumulated_insns_num % 3; |
30028c85 | 9087 | next_state = curr_state->next; |
c856f536 VM |
9088 | /* We must fill up the current bundle in order to start a |
9089 | subsequent asm insn in a new bundle. Asm insn is always | |
9090 | placed in a separate bundle. */ | |
f32360c7 VM |
9091 | only_bundle_end_p |
9092 | = (next_insn != NULL_RTX | |
9093 | && INSN_CODE (insn) == CODE_FOR_insn_group_barrier | |
7b84aac0 | 9094 | && unknown_for_bundling_p (next_insn)); |
c856f536 VM |
9095 | /* We may fill up the current bundle if it is the cycle end |
9096 | without a group barrier. */ | |
30028c85 | 9097 | bundle_end_p |
f32360c7 | 9098 | = (only_bundle_end_p || next_insn == NULL_RTX |
30028c85 VM |
9099 | || (GET_MODE (next_insn) == TImode |
9100 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier)); | |
9101 | if (type == TYPE_F || type == TYPE_B || type == TYPE_L | |
7400e46b | 9102 | || type == TYPE_S) |
f32360c7 VM |
9103 | issue_nops_and_insn (curr_state, 2, insn, bundle_end_p, |
9104 | only_bundle_end_p); | |
9105 | issue_nops_and_insn (curr_state, 1, insn, bundle_end_p, | |
9106 | only_bundle_end_p); | |
9107 | issue_nops_and_insn (curr_state, 0, insn, bundle_end_p, | |
9108 | only_bundle_end_p); | |
f83594c4 | 9109 | } |
e820471b | 9110 | gcc_assert (index_to_bundle_states [insn_num]); |
30028c85 VM |
9111 | for (curr_state = index_to_bundle_states [insn_num]; |
9112 | curr_state != NULL; | |
9113 | curr_state = curr_state->next) | |
9114 | if (verbose >= 2 && dump) | |
9115 | { | |
c856f536 VM |
9116 | /* This structure is taken from generated code of the |
9117 | pipeline hazard recognizer (see file insn-attrtab.c). | |
9118 | Please don't forget to change the structure if a new | |
9119 | automaton is added to .md file. */ | |
30028c85 VM |
9120 | struct DFA_chip |
9121 | { | |
9122 | unsigned short one_automaton_state; | |
9123 | unsigned short oneb_automaton_state; | |
9124 | unsigned short two_automaton_state; | |
9125 | unsigned short twob_automaton_state; | |
9126 | }; | |
9c808aad | 9127 | |
30028c85 VM |
9128 | fprintf |
9129 | (dump, | |
388092d5 | 9130 | "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d state %d) for %d\n", |
30028c85 VM |
9131 | curr_state->unique_num, |
9132 | (curr_state->originator == NULL | |
9133 | ? -1 : curr_state->originator->unique_num), | |
9134 | curr_state->cost, | |
9135 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9136 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9137 | curr_state->middle_bundle_stops, |
7400e46b | 9138 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 VM |
9139 | INSN_UID (insn)); |
9140 | } | |
1ad72cef | 9141 | } |
e820471b NS |
9142 | |
9143 | /* We should find a solution because the 2nd insn scheduling has | |
9144 | found one. */ | |
9145 | gcc_assert (index_to_bundle_states [insn_num]); | |
c856f536 | 9146 | /* Find a state corresponding to the best insn sequence. */ |
30028c85 VM |
9147 | best_state = NULL; |
9148 | for (curr_state = index_to_bundle_states [insn_num]; | |
9149 | curr_state != NULL; | |
9150 | curr_state = curr_state->next) | |
c856f536 VM |
9151 | /* We are just looking at the states with fully filled up last |
9152 | bundle. The first we prefer insn sequences with minimal cost | |
9153 | then with minimal inserted nops and finally with branch insns | |
9154 | placed in the 3rd slots. */ | |
30028c85 VM |
9155 | if (curr_state->accumulated_insns_num % 3 == 0 |
9156 | && (best_state == NULL || best_state->cost > curr_state->cost | |
9157 | || (best_state->cost == curr_state->cost | |
9158 | && (curr_state->accumulated_insns_num | |
9159 | < best_state->accumulated_insns_num | |
9160 | || (curr_state->accumulated_insns_num | |
9161 | == best_state->accumulated_insns_num | |
388092d5 AB |
9162 | && (curr_state->branch_deviation |
9163 | < best_state->branch_deviation | |
9164 | || (curr_state->branch_deviation | |
9165 | == best_state->branch_deviation | |
9166 | && curr_state->middle_bundle_stops | |
9167 | < best_state->middle_bundle_stops))))))) | |
30028c85 | 9168 | best_state = curr_state; |
c856f536 | 9169 | /* Second (backward) pass: adding nops and templates. */ |
388092d5 | 9170 | gcc_assert (best_state); |
30028c85 VM |
9171 | insn_num = best_state->before_nops_num; |
9172 | template0 = template1 = -1; | |
9173 | for (curr_state = best_state; | |
9174 | curr_state->originator != NULL; | |
9175 | curr_state = curr_state->originator) | |
9176 | { | |
9177 | insn = curr_state->insn; | |
7b84aac0 | 9178 | asm_p = unknown_for_bundling_p (insn); |
30028c85 VM |
9179 | insn_num++; |
9180 | if (verbose >= 2 && dump) | |
2130b7fb | 9181 | { |
30028c85 VM |
9182 | struct DFA_chip |
9183 | { | |
9184 | unsigned short one_automaton_state; | |
9185 | unsigned short oneb_automaton_state; | |
9186 | unsigned short two_automaton_state; | |
9187 | unsigned short twob_automaton_state; | |
9188 | }; | |
9c808aad | 9189 | |
30028c85 VM |
9190 | fprintf |
9191 | (dump, | |
388092d5 | 9192 | "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, mid.stops %d, state %d) for %d\n", |
30028c85 VM |
9193 | curr_state->unique_num, |
9194 | (curr_state->originator == NULL | |
9195 | ? -1 : curr_state->originator->unique_num), | |
9196 | curr_state->cost, | |
9197 | curr_state->before_nops_num, curr_state->after_nops_num, | |
9198 | curr_state->accumulated_insns_num, curr_state->branch_deviation, | |
388092d5 | 9199 | curr_state->middle_bundle_stops, |
7400e46b | 9200 | ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state, |
30028c85 | 9201 | INSN_UID (insn)); |
2130b7fb | 9202 | } |
c856f536 VM |
9203 | /* Find the position in the current bundle window. The window can |
9204 | contain at most two bundles. Two bundle window means that | |
9205 | the processor will make two bundle rotation. */ | |
30028c85 | 9206 | max_pos = get_max_pos (curr_state->dfa_state); |
c856f536 VM |
9207 | if (max_pos == 6 |
9208 | /* The following (negative template number) means that the | |
9209 | processor did one bundle rotation. */ | |
9210 | || (max_pos == 3 && template0 < 0)) | |
2130b7fb | 9211 | { |
c856f536 VM |
9212 | /* We are at the end of the window -- find template(s) for |
9213 | its bundle(s). */ | |
30028c85 VM |
9214 | pos = max_pos; |
9215 | if (max_pos == 3) | |
9216 | template0 = get_template (curr_state->dfa_state, 3); | |
9217 | else | |
9218 | { | |
9219 | template1 = get_template (curr_state->dfa_state, 3); | |
9220 | template0 = get_template (curr_state->dfa_state, 6); | |
9221 | } | |
9222 | } | |
9223 | if (max_pos > 3 && template1 < 0) | |
c856f536 | 9224 | /* It may happen when we have the stop inside a bundle. */ |
30028c85 | 9225 | { |
e820471b | 9226 | gcc_assert (pos <= 3); |
30028c85 VM |
9227 | template1 = get_template (curr_state->dfa_state, 3); |
9228 | pos += 3; | |
9229 | } | |
f32360c7 | 9230 | if (!asm_p) |
c856f536 | 9231 | /* Emit nops after the current insn. */ |
f32360c7 VM |
9232 | for (i = 0; i < curr_state->after_nops_num; i++) |
9233 | { | |
9234 | nop = gen_nop (); | |
9235 | emit_insn_after (nop, insn); | |
9236 | pos--; | |
e820471b | 9237 | gcc_assert (pos >= 0); |
f32360c7 VM |
9238 | if (pos % 3 == 0) |
9239 | { | |
c856f536 VM |
9240 | /* We are at the start of a bundle: emit the template |
9241 | (it should be defined). */ | |
e820471b | 9242 | gcc_assert (template0 >= 0); |
4a4cd49c | 9243 | ia64_add_bundle_selector_before (template0, nop); |
c856f536 VM |
9244 | /* If we have two bundle window, we make one bundle |
9245 | rotation. Otherwise template0 will be undefined | |
9246 | (negative value). */ | |
f32360c7 VM |
9247 | template0 = template1; |
9248 | template1 = -1; | |
9249 | } | |
9250 | } | |
c856f536 VM |
9251 | /* Move the position backward in the window. Group barrier has |
9252 | no slot. Asm insn takes all bundle. */ | |
30028c85 | 9253 | if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier |
7b84aac0 | 9254 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9255 | pos--; |
c856f536 | 9256 | /* Long insn takes 2 slots. */ |
30028c85 VM |
9257 | if (ia64_safe_type (insn) == TYPE_L) |
9258 | pos--; | |
e820471b | 9259 | gcc_assert (pos >= 0); |
30028c85 VM |
9260 | if (pos % 3 == 0 |
9261 | && INSN_CODE (insn) != CODE_FOR_insn_group_barrier | |
7b84aac0 | 9262 | && !unknown_for_bundling_p (insn)) |
30028c85 | 9263 | { |
c856f536 VM |
9264 | /* The current insn is at the bundle start: emit the |
9265 | template. */ | |
e820471b | 9266 | gcc_assert (template0 >= 0); |
4a4cd49c | 9267 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9268 | b = PREV_INSN (insn); |
9269 | insn = b; | |
68776c43 | 9270 | /* See comment above in analogous place for emitting nops |
c856f536 | 9271 | after the insn. */ |
30028c85 VM |
9272 | template0 = template1; |
9273 | template1 = -1; | |
9274 | } | |
c856f536 | 9275 | /* Emit nops after the current insn. */ |
30028c85 VM |
9276 | for (i = 0; i < curr_state->before_nops_num; i++) |
9277 | { | |
9278 | nop = gen_nop (); | |
9279 | ia64_emit_insn_before (nop, insn); | |
9280 | nop = PREV_INSN (insn); | |
9281 | insn = nop; | |
9282 | pos--; | |
e820471b | 9283 | gcc_assert (pos >= 0); |
30028c85 VM |
9284 | if (pos % 3 == 0) |
9285 | { | |
68776c43 | 9286 | /* See comment above in analogous place for emitting nops |
c856f536 | 9287 | after the insn. */ |
e820471b | 9288 | gcc_assert (template0 >= 0); |
4a4cd49c | 9289 | ia64_add_bundle_selector_before (template0, insn); |
30028c85 VM |
9290 | b = PREV_INSN (insn); |
9291 | insn = b; | |
9292 | template0 = template1; | |
9293 | template1 = -1; | |
9294 | } | |
2130b7fb BS |
9295 | } |
9296 | } | |
388092d5 AB |
9297 | |
9298 | #ifdef ENABLE_CHECKING | |
9299 | { | |
9300 | /* Assert right calculation of middle_bundle_stops. */ | |
9301 | int num = best_state->middle_bundle_stops; | |
9302 | bool start_bundle = true, end_bundle = false; | |
9303 | ||
9304 | for (insn = NEXT_INSN (prev_head_insn); | |
9305 | insn && insn != tail; | |
9306 | insn = NEXT_INSN (insn)) | |
9307 | { | |
9308 | if (!INSN_P (insn)) | |
9309 | continue; | |
9310 | if (recog_memoized (insn) == CODE_FOR_bundle_selector) | |
9311 | start_bundle = true; | |
9312 | else | |
9313 | { | |
9314 | rtx next_insn; | |
9315 | ||
9316 | for (next_insn = NEXT_INSN (insn); | |
9317 | next_insn && next_insn != tail; | |
9318 | next_insn = NEXT_INSN (next_insn)) | |
9319 | if (INSN_P (next_insn) | |
9320 | && (ia64_safe_itanium_class (next_insn) | |
9321 | != ITANIUM_CLASS_IGNORE | |
9322 | || recog_memoized (next_insn) | |
9323 | == CODE_FOR_bundle_selector) | |
9324 | && GET_CODE (PATTERN (next_insn)) != USE | |
9325 | && GET_CODE (PATTERN (next_insn)) != CLOBBER) | |
9326 | break; | |
9327 | ||
9328 | end_bundle = next_insn == NULL_RTX | |
9329 | || next_insn == tail | |
9330 | || (INSN_P (next_insn) | |
9331 | && recog_memoized (next_insn) | |
9332 | == CODE_FOR_bundle_selector); | |
9333 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier | |
9334 | && !start_bundle && !end_bundle | |
9335 | && next_insn | |
7b84aac0 | 9336 | && !unknown_for_bundling_p (next_insn)) |
388092d5 AB |
9337 | num--; |
9338 | ||
9339 | start_bundle = false; | |
9340 | } | |
9341 | } | |
9342 | ||
9343 | gcc_assert (num == 0); | |
9344 | } | |
9345 | #endif | |
9346 | ||
30028c85 VM |
9347 | free (index_to_bundle_states); |
9348 | finish_bundle_state_table (); | |
9349 | bundling_p = 0; | |
9350 | dfa_clean_insn_cache (); | |
2130b7fb | 9351 | } |
c65ebc55 | 9352 | |
30028c85 VM |
9353 | /* The following function is called at the end of scheduling BB or |
9354 | EBB. After reload, it inserts stop bits and does insn bundling. */ | |
9355 | ||
9356 | static void | |
9c808aad | 9357 | ia64_sched_finish (FILE *dump, int sched_verbose) |
c237e94a | 9358 | { |
30028c85 VM |
9359 | if (sched_verbose) |
9360 | fprintf (dump, "// Finishing schedule.\n"); | |
9361 | if (!reload_completed) | |
9362 | return; | |
9363 | if (reload_completed) | |
9364 | { | |
9365 | final_emit_insn_group_barriers (dump); | |
9366 | bundling (dump, sched_verbose, current_sched_info->prev_head, | |
9367 | current_sched_info->next_tail); | |
9368 | if (sched_verbose && dump) | |
9369 | fprintf (dump, "// finishing %d-%d\n", | |
9370 | INSN_UID (NEXT_INSN (current_sched_info->prev_head)), | |
9371 | INSN_UID (PREV_INSN (current_sched_info->next_tail))); | |
9c808aad | 9372 | |
30028c85 VM |
9373 | return; |
9374 | } | |
c237e94a ZW |
9375 | } |
9376 | ||
30028c85 | 9377 | /* The following function inserts stop bits in scheduled BB or EBB. */ |
2130b7fb | 9378 | |
30028c85 | 9379 | static void |
9c808aad | 9380 | final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED) |
2130b7fb | 9381 | { |
30028c85 VM |
9382 | rtx insn; |
9383 | int need_barrier_p = 0; | |
388092d5 | 9384 | int seen_good_insn = 0; |
2130b7fb | 9385 | |
30028c85 | 9386 | init_insn_group_barriers (); |
2130b7fb | 9387 | |
30028c85 VM |
9388 | for (insn = NEXT_INSN (current_sched_info->prev_head); |
9389 | insn != current_sched_info->next_tail; | |
9390 | insn = NEXT_INSN (insn)) | |
9391 | { | |
b64925dc | 9392 | if (BARRIER_P (insn)) |
b395ddbe | 9393 | { |
30028c85 | 9394 | rtx last = prev_active_insn (insn); |
14d118d6 | 9395 | |
30028c85 | 9396 | if (! last) |
b395ddbe | 9397 | continue; |
34f0d87a | 9398 | if (JUMP_TABLE_DATA_P (last)) |
30028c85 VM |
9399 | last = prev_active_insn (last); |
9400 | if (recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9401 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last); | |
2130b7fb | 9402 | |
30028c85 | 9403 | init_insn_group_barriers (); |
388092d5 | 9404 | seen_good_insn = 0; |
30028c85 | 9405 | need_barrier_p = 0; |
b395ddbe | 9406 | } |
b5b8b0ac | 9407 | else if (NONDEBUG_INSN_P (insn)) |
2130b7fb | 9408 | { |
30028c85 | 9409 | if (recog_memoized (insn) == CODE_FOR_insn_group_barrier) |
2130b7fb | 9410 | { |
30028c85 | 9411 | init_insn_group_barriers (); |
388092d5 | 9412 | seen_good_insn = 0; |
30028c85 | 9413 | need_barrier_p = 0; |
c65ebc55 | 9414 | } |
388092d5 AB |
9415 | else if (need_barrier_p || group_barrier_needed (insn) |
9416 | || (mflag_sched_stop_bits_after_every_cycle | |
9417 | && GET_MODE (insn) == TImode | |
9418 | && seen_good_insn)) | |
2130b7fb | 9419 | { |
30028c85 VM |
9420 | if (TARGET_EARLY_STOP_BITS) |
9421 | { | |
9422 | rtx last; | |
9c808aad | 9423 | |
30028c85 VM |
9424 | for (last = insn; |
9425 | last != current_sched_info->prev_head; | |
9426 | last = PREV_INSN (last)) | |
9427 | if (INSN_P (last) && GET_MODE (last) == TImode | |
9428 | && stops_p [INSN_UID (last)]) | |
9429 | break; | |
9430 | if (last == current_sched_info->prev_head) | |
9431 | last = insn; | |
9432 | last = prev_active_insn (last); | |
9433 | if (last | |
9434 | && recog_memoized (last) != CODE_FOR_insn_group_barrier) | |
9435 | emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), | |
9436 | last); | |
9437 | init_insn_group_barriers (); | |
9438 | for (last = NEXT_INSN (last); | |
9439 | last != insn; | |
9440 | last = NEXT_INSN (last)) | |
9441 | if (INSN_P (last)) | |
388092d5 AB |
9442 | { |
9443 | group_barrier_needed (last); | |
9444 | if (recog_memoized (last) >= 0 | |
9445 | && important_for_bundling_p (last)) | |
9446 | seen_good_insn = 1; | |
9447 | } | |
30028c85 VM |
9448 | } |
9449 | else | |
9450 | { | |
9451 | emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), | |
9452 | insn); | |
9453 | init_insn_group_barriers (); | |
388092d5 | 9454 | seen_good_insn = 0; |
30028c85 | 9455 | } |
c1bc6ca8 | 9456 | group_barrier_needed (insn); |
388092d5 AB |
9457 | if (recog_memoized (insn) >= 0 |
9458 | && important_for_bundling_p (insn)) | |
9459 | seen_good_insn = 1; | |
2130b7fb | 9460 | } |
388092d5 AB |
9461 | else if (recog_memoized (insn) >= 0 |
9462 | && important_for_bundling_p (insn)) | |
034288ef | 9463 | seen_good_insn = 1; |
b64925dc | 9464 | need_barrier_p = (CALL_P (insn) || unknown_for_bundling_p (insn)); |
c65ebc55 | 9465 | } |
2130b7fb | 9466 | } |
30028c85 | 9467 | } |
2130b7fb | 9468 | |
30028c85 | 9469 | \f |
2130b7fb | 9470 | |
a4d05547 | 9471 | /* If the following function returns TRUE, we will use the DFA |
30028c85 | 9472 | insn scheduler. */ |
2130b7fb | 9473 | |
c237e94a | 9474 | static int |
9c808aad | 9475 | ia64_first_cycle_multipass_dfa_lookahead (void) |
2130b7fb | 9476 | { |
30028c85 VM |
9477 | return (reload_completed ? 6 : 4); |
9478 | } | |
2130b7fb | 9479 | |
30028c85 | 9480 | /* The following function initiates variable `dfa_pre_cycle_insn'. */ |
2130b7fb | 9481 | |
30028c85 | 9482 | static void |
9c808aad | 9483 | ia64_init_dfa_pre_cycle_insn (void) |
30028c85 VM |
9484 | { |
9485 | if (temp_dfa_state == NULL) | |
2130b7fb | 9486 | { |
30028c85 VM |
9487 | dfa_state_size = state_size (); |
9488 | temp_dfa_state = xmalloc (dfa_state_size); | |
9489 | prev_cycle_state = xmalloc (dfa_state_size); | |
2130b7fb | 9490 | } |
30028c85 VM |
9491 | dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ()); |
9492 | PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX; | |
9493 | recog_memoized (dfa_pre_cycle_insn); | |
9494 | dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3))); | |
9495 | PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX; | |
9496 | recog_memoized (dfa_stop_insn); | |
9497 | } | |
2130b7fb | 9498 | |
30028c85 VM |
9499 | /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN |
9500 | used by the DFA insn scheduler. */ | |
2130b7fb | 9501 | |
30028c85 | 9502 | static rtx |
9c808aad | 9503 | ia64_dfa_pre_cycle_insn (void) |
30028c85 VM |
9504 | { |
9505 | return dfa_pre_cycle_insn; | |
9506 | } | |
2130b7fb | 9507 | |
30028c85 VM |
9508 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9509 | ld) produces address for CONSUMER (of type st or stf). */ | |
2130b7fb | 9510 | |
30028c85 | 9511 | int |
9c808aad | 9512 | ia64_st_address_bypass_p (rtx producer, rtx consumer) |
30028c85 VM |
9513 | { |
9514 | rtx dest, reg, mem; | |
2130b7fb | 9515 | |
e820471b | 9516 | gcc_assert (producer && consumer); |
30028c85 | 9517 | dest = ia64_single_set (producer); |
e820471b NS |
9518 | gcc_assert (dest); |
9519 | reg = SET_DEST (dest); | |
9520 | gcc_assert (reg); | |
30028c85 VM |
9521 | if (GET_CODE (reg) == SUBREG) |
9522 | reg = SUBREG_REG (reg); | |
e820471b NS |
9523 | gcc_assert (GET_CODE (reg) == REG); |
9524 | ||
30028c85 | 9525 | dest = ia64_single_set (consumer); |
e820471b NS |
9526 | gcc_assert (dest); |
9527 | mem = SET_DEST (dest); | |
9528 | gcc_assert (mem && GET_CODE (mem) == MEM); | |
30028c85 | 9529 | return reg_mentioned_p (reg, mem); |
2130b7fb BS |
9530 | } |
9531 | ||
30028c85 VM |
9532 | /* The following function returns TRUE if PRODUCER (of type ilog or |
9533 | ld) produces address for CONSUMER (of type ld or fld). */ | |
2130b7fb | 9534 | |
30028c85 | 9535 | int |
9c808aad | 9536 | ia64_ld_address_bypass_p (rtx producer, rtx consumer) |
2130b7fb | 9537 | { |
30028c85 VM |
9538 | rtx dest, src, reg, mem; |
9539 | ||
e820471b | 9540 | gcc_assert (producer && consumer); |
30028c85 | 9541 | dest = ia64_single_set (producer); |
e820471b NS |
9542 | gcc_assert (dest); |
9543 | reg = SET_DEST (dest); | |
9544 | gcc_assert (reg); | |
30028c85 VM |
9545 | if (GET_CODE (reg) == SUBREG) |
9546 | reg = SUBREG_REG (reg); | |
e820471b NS |
9547 | gcc_assert (GET_CODE (reg) == REG); |
9548 | ||
30028c85 | 9549 | src = ia64_single_set (consumer); |
e820471b NS |
9550 | gcc_assert (src); |
9551 | mem = SET_SRC (src); | |
9552 | gcc_assert (mem); | |
048d0d36 | 9553 | |
30028c85 VM |
9554 | if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0) |
9555 | mem = XVECEXP (mem, 0, 0); | |
048d0d36 | 9556 | else if (GET_CODE (mem) == IF_THEN_ELSE) |
917f1b7e | 9557 | /* ??? Is this bypass necessary for ld.c? */ |
048d0d36 MK |
9558 | { |
9559 | gcc_assert (XINT (XEXP (XEXP (mem, 0), 0), 1) == UNSPEC_LDCCLR); | |
9560 | mem = XEXP (mem, 1); | |
9561 | } | |
9562 | ||
30028c85 VM |
9563 | while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND) |
9564 | mem = XEXP (mem, 0); | |
ef1ecf87 | 9565 | |
048d0d36 MK |
9566 | if (GET_CODE (mem) == UNSPEC) |
9567 | { | |
9568 | int c = XINT (mem, 1); | |
9569 | ||
388092d5 AB |
9570 | gcc_assert (c == UNSPEC_LDA || c == UNSPEC_LDS || c == UNSPEC_LDS_A |
9571 | || c == UNSPEC_LDSA); | |
048d0d36 MK |
9572 | mem = XVECEXP (mem, 0, 0); |
9573 | } | |
9574 | ||
ef1ecf87 | 9575 | /* Note that LO_SUM is used for GOT loads. */ |
e820471b | 9576 | gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM); |
ef1ecf87 | 9577 | |
30028c85 VM |
9578 | return reg_mentioned_p (reg, mem); |
9579 | } | |
9580 | ||
9581 | /* The following function returns TRUE if INSN produces address for a | |
9582 | load/store insn. We will place such insns into M slot because it | |
ff482c8d | 9583 | decreases its latency time. */ |
30028c85 VM |
9584 | |
9585 | int | |
9c808aad | 9586 | ia64_produce_address_p (rtx insn) |
30028c85 VM |
9587 | { |
9588 | return insn->call; | |
2130b7fb | 9589 | } |
30028c85 | 9590 | |
2130b7fb | 9591 | \f |
3b572406 RH |
9592 | /* Emit pseudo-ops for the assembler to describe predicate relations. |
9593 | At present this assumes that we only consider predicate pairs to | |
9594 | be mutex, and that the assembler can deduce proper values from | |
9595 | straight-line code. */ | |
9596 | ||
9597 | static void | |
9c808aad | 9598 | emit_predicate_relation_info (void) |
3b572406 | 9599 | { |
e0082a72 | 9600 | basic_block bb; |
3b572406 | 9601 | |
4f42035e | 9602 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
3b572406 | 9603 | { |
3b572406 | 9604 | int r; |
a813c111 | 9605 | rtx head = BB_HEAD (bb); |
3b572406 RH |
9606 | |
9607 | /* We only need such notes at code labels. */ | |
b64925dc | 9608 | if (! LABEL_P (head)) |
3b572406 | 9609 | continue; |
740aeb38 | 9610 | if (NOTE_INSN_BASIC_BLOCK_P (NEXT_INSN (head))) |
3b572406 RH |
9611 | head = NEXT_INSN (head); |
9612 | ||
9f3b8452 RH |
9613 | /* Skip p0, which may be thought to be live due to (reg:DI p0) |
9614 | grabbing the entire block of predicate registers. */ | |
9615 | for (r = PR_REG (2); r < PR_REG (64); r += 2) | |
6fb5fa3c | 9616 | if (REGNO_REG_SET_P (df_get_live_in (bb), r)) |
3b572406 | 9617 | { |
f2f90c63 | 9618 | rtx p = gen_rtx_REG (BImode, r); |
054451ea | 9619 | rtx n = emit_insn_after (gen_pred_rel_mutex (p), head); |
a813c111 SB |
9620 | if (head == BB_END (bb)) |
9621 | BB_END (bb) = n; | |
3b572406 RH |
9622 | head = n; |
9623 | } | |
9624 | } | |
ca3920ad JW |
9625 | |
9626 | /* Look for conditional calls that do not return, and protect predicate | |
9627 | relations around them. Otherwise the assembler will assume the call | |
9628 | returns, and complain about uses of call-clobbered predicates after | |
9629 | the call. */ | |
4f42035e | 9630 | FOR_EACH_BB_REVERSE_FN (bb, cfun) |
ca3920ad | 9631 | { |
a813c111 | 9632 | rtx insn = BB_HEAD (bb); |
9c808aad | 9633 | |
ca3920ad JW |
9634 | while (1) |
9635 | { | |
b64925dc | 9636 | if (CALL_P (insn) |
ca3920ad JW |
9637 | && GET_CODE (PATTERN (insn)) == COND_EXEC |
9638 | && find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
9639 | { | |
9640 | rtx b = emit_insn_before (gen_safe_across_calls_all (), insn); | |
9641 | rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn); | |
a813c111 SB |
9642 | if (BB_HEAD (bb) == insn) |
9643 | BB_HEAD (bb) = b; | |
9644 | if (BB_END (bb) == insn) | |
9645 | BB_END (bb) = a; | |
ca3920ad | 9646 | } |
9c808aad | 9647 | |
a813c111 | 9648 | if (insn == BB_END (bb)) |
ca3920ad JW |
9649 | break; |
9650 | insn = NEXT_INSN (insn); | |
9651 | } | |
9652 | } | |
3b572406 RH |
9653 | } |
9654 | ||
c65ebc55 JW |
9655 | /* Perform machine dependent operations on the rtl chain INSNS. */ |
9656 | ||
18dbd950 | 9657 | static void |
9c808aad | 9658 | ia64_reorg (void) |
c65ebc55 | 9659 | { |
1e3881c2 JH |
9660 | /* We are freeing block_for_insn in the toplev to keep compatibility |
9661 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
852c6ec7 | 9662 | compute_bb_for_insn (); |
a00fe19f RH |
9663 | |
9664 | /* If optimizing, we'll have split before scheduling. */ | |
9665 | if (optimize == 0) | |
6fb5fa3c | 9666 | split_all_insns (); |
2130b7fb | 9667 | |
2ba42841 | 9668 | if (optimize && flag_schedule_insns_after_reload |
388092d5 | 9669 | && dbg_cnt (ia64_sched2)) |
f4d578da | 9670 | { |
547fdef8 | 9671 | basic_block bb; |
eced69b5 | 9672 | timevar_push (TV_SCHED2); |
f4d578da | 9673 | ia64_final_schedule = 1; |
30028c85 | 9674 | |
547fdef8 BS |
9675 | /* We can't let modulo-sched prevent us from scheduling any bbs, |
9676 | since we need the final schedule to produce bundle information. */ | |
11cd3bed | 9677 | FOR_EACH_BB_FN (bb, cfun) |
547fdef8 BS |
9678 | bb->flags &= ~BB_DISABLE_SCHEDULE; |
9679 | ||
30028c85 VM |
9680 | initiate_bundle_states (); |
9681 | ia64_nop = make_insn_raw (gen_nop ()); | |
9682 | PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX; | |
9683 | recog_memoized (ia64_nop); | |
9684 | clocks_length = get_max_uid () + 1; | |
5ead67f6 | 9685 | stops_p = XCNEWVEC (char, clocks_length); |
7400e46b | 9686 | |
30028c85 VM |
9687 | if (ia64_tune == PROCESSOR_ITANIUM2) |
9688 | { | |
9689 | pos_1 = get_cpu_unit_code ("2_1"); | |
9690 | pos_2 = get_cpu_unit_code ("2_2"); | |
9691 | pos_3 = get_cpu_unit_code ("2_3"); | |
9692 | pos_4 = get_cpu_unit_code ("2_4"); | |
9693 | pos_5 = get_cpu_unit_code ("2_5"); | |
9694 | pos_6 = get_cpu_unit_code ("2_6"); | |
9695 | _0mii_ = get_cpu_unit_code ("2b_0mii."); | |
9696 | _0mmi_ = get_cpu_unit_code ("2b_0mmi."); | |
9697 | _0mfi_ = get_cpu_unit_code ("2b_0mfi."); | |
9698 | _0mmf_ = get_cpu_unit_code ("2b_0mmf."); | |
9699 | _0bbb_ = get_cpu_unit_code ("2b_0bbb."); | |
9700 | _0mbb_ = get_cpu_unit_code ("2b_0mbb."); | |
9701 | _0mib_ = get_cpu_unit_code ("2b_0mib."); | |
9702 | _0mmb_ = get_cpu_unit_code ("2b_0mmb."); | |
9703 | _0mfb_ = get_cpu_unit_code ("2b_0mfb."); | |
9704 | _0mlx_ = get_cpu_unit_code ("2b_0mlx."); | |
9705 | _1mii_ = get_cpu_unit_code ("2b_1mii."); | |
9706 | _1mmi_ = get_cpu_unit_code ("2b_1mmi."); | |
9707 | _1mfi_ = get_cpu_unit_code ("2b_1mfi."); | |
9708 | _1mmf_ = get_cpu_unit_code ("2b_1mmf."); | |
9709 | _1bbb_ = get_cpu_unit_code ("2b_1bbb."); | |
9710 | _1mbb_ = get_cpu_unit_code ("2b_1mbb."); | |
9711 | _1mib_ = get_cpu_unit_code ("2b_1mib."); | |
9712 | _1mmb_ = get_cpu_unit_code ("2b_1mmb."); | |
9713 | _1mfb_ = get_cpu_unit_code ("2b_1mfb."); | |
9714 | _1mlx_ = get_cpu_unit_code ("2b_1mlx."); | |
9715 | } | |
9716 | else | |
9717 | { | |
9718 | pos_1 = get_cpu_unit_code ("1_1"); | |
9719 | pos_2 = get_cpu_unit_code ("1_2"); | |
9720 | pos_3 = get_cpu_unit_code ("1_3"); | |
9721 | pos_4 = get_cpu_unit_code ("1_4"); | |
9722 | pos_5 = get_cpu_unit_code ("1_5"); | |
9723 | pos_6 = get_cpu_unit_code ("1_6"); | |
9724 | _0mii_ = get_cpu_unit_code ("1b_0mii."); | |
9725 | _0mmi_ = get_cpu_unit_code ("1b_0mmi."); | |
9726 | _0mfi_ = get_cpu_unit_code ("1b_0mfi."); | |
9727 | _0mmf_ = get_cpu_unit_code ("1b_0mmf."); | |
9728 | _0bbb_ = get_cpu_unit_code ("1b_0bbb."); | |
9729 | _0mbb_ = get_cpu_unit_code ("1b_0mbb."); | |
9730 | _0mib_ = get_cpu_unit_code ("1b_0mib."); | |
9731 | _0mmb_ = get_cpu_unit_code ("1b_0mmb."); | |
9732 | _0mfb_ = get_cpu_unit_code ("1b_0mfb."); | |
9733 | _0mlx_ = get_cpu_unit_code ("1b_0mlx."); | |
9734 | _1mii_ = get_cpu_unit_code ("1b_1mii."); | |
9735 | _1mmi_ = get_cpu_unit_code ("1b_1mmi."); | |
9736 | _1mfi_ = get_cpu_unit_code ("1b_1mfi."); | |
9737 | _1mmf_ = get_cpu_unit_code ("1b_1mmf."); | |
9738 | _1bbb_ = get_cpu_unit_code ("1b_1bbb."); | |
9739 | _1mbb_ = get_cpu_unit_code ("1b_1mbb."); | |
9740 | _1mib_ = get_cpu_unit_code ("1b_1mib."); | |
9741 | _1mmb_ = get_cpu_unit_code ("1b_1mmb."); | |
9742 | _1mfb_ = get_cpu_unit_code ("1b_1mfb."); | |
9743 | _1mlx_ = get_cpu_unit_code ("1b_1mlx."); | |
9744 | } | |
388092d5 AB |
9745 | |
9746 | if (flag_selective_scheduling2 | |
9747 | && !maybe_skip_selective_scheduling ()) | |
9748 | run_selective_scheduling (); | |
9749 | else | |
9750 | schedule_ebbs (); | |
9751 | ||
9752 | /* Redo alignment computation, as it might gone wrong. */ | |
9753 | compute_alignments (); | |
9754 | ||
6fb5fa3c DB |
9755 | /* We cannot reuse this one because it has been corrupted by the |
9756 | evil glat. */ | |
30028c85 | 9757 | finish_bundle_states (); |
30028c85 | 9758 | free (stops_p); |
048d0d36 | 9759 | stops_p = NULL; |
c263766c | 9760 | emit_insn_group_barriers (dump_file); |
30028c85 | 9761 | |
f4d578da | 9762 | ia64_final_schedule = 0; |
eced69b5 | 9763 | timevar_pop (TV_SCHED2); |
f4d578da BS |
9764 | } |
9765 | else | |
c263766c | 9766 | emit_all_insn_group_barriers (dump_file); |
f2f90c63 | 9767 | |
6fb5fa3c DB |
9768 | df_analyze (); |
9769 | ||
f12f25a7 RH |
9770 | /* A call must not be the last instruction in a function, so that the |
9771 | return address is still within the function, so that unwinding works | |
9772 | properly. Note that IA-64 differs from dwarf2 on this point. */ | |
d5fabb58 | 9773 | if (ia64_except_unwind_info (&global_options) == UI_TARGET) |
f12f25a7 RH |
9774 | { |
9775 | rtx insn; | |
9776 | int saw_stop = 0; | |
9777 | ||
9778 | insn = get_last_insn (); | |
9779 | if (! INSN_P (insn)) | |
9780 | insn = prev_active_insn (insn); | |
2ca57608 | 9781 | if (insn) |
f12f25a7 | 9782 | { |
2ca57608 | 9783 | /* Skip over insns that expand to nothing. */ |
b64925dc | 9784 | while (NONJUMP_INSN_P (insn) |
2ca57608 L |
9785 | && get_attr_empty (insn) == EMPTY_YES) |
9786 | { | |
9787 | if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE | |
9788 | && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER) | |
9789 | saw_stop = 1; | |
9790 | insn = prev_active_insn (insn); | |
9791 | } | |
b64925dc | 9792 | if (CALL_P (insn)) |
2ca57608 L |
9793 | { |
9794 | if (! saw_stop) | |
9795 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9796 | emit_insn (gen_break_f ()); | |
9797 | emit_insn (gen_insn_group_barrier (GEN_INT (3))); | |
9798 | } | |
f12f25a7 RH |
9799 | } |
9800 | } | |
9801 | ||
f2f90c63 | 9802 | emit_predicate_relation_info (); |
014a1138 | 9803 | |
2ba42841 | 9804 | if (flag_var_tracking) |
014a1138 JZ |
9805 | { |
9806 | timevar_push (TV_VAR_TRACKING); | |
9807 | variable_tracking_main (); | |
9808 | timevar_pop (TV_VAR_TRACKING); | |
9809 | } | |
0d475361 | 9810 | df_finish_pass (false); |
c65ebc55 JW |
9811 | } |
9812 | \f | |
9813 | /* Return true if REGNO is used by the epilogue. */ | |
9814 | ||
9815 | int | |
9c808aad | 9816 | ia64_epilogue_uses (int regno) |
c65ebc55 | 9817 | { |
6ca3c22f RH |
9818 | switch (regno) |
9819 | { | |
9820 | case R_GR (1): | |
b23ba0b8 RH |
9821 | /* With a call to a function in another module, we will write a new |
9822 | value to "gp". After returning from such a call, we need to make | |
9823 | sure the function restores the original gp-value, even if the | |
9824 | function itself does not use the gp anymore. */ | |
9825 | return !(TARGET_AUTO_PIC || TARGET_NO_PIC); | |
6ca3c22f RH |
9826 | |
9827 | case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3): | |
9828 | case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7): | |
9829 | /* For functions defined with the syscall_linkage attribute, all | |
9830 | input registers are marked as live at all function exits. This | |
9831 | prevents the register allocator from using the input registers, | |
9832 | which in turn makes it possible to restart a system call after | |
9833 | an interrupt without having to save/restore the input registers. | |
9834 | This also prevents kernel data from leaking to application code. */ | |
9835 | return lookup_attribute ("syscall_linkage", | |
9836 | TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL; | |
9837 | ||
9838 | case R_BR (0): | |
9839 | /* Conditional return patterns can't represent the use of `b0' as | |
9840 | the return address, so we force the value live this way. */ | |
9841 | return 1; | |
6b6c1201 | 9842 | |
6ca3c22f RH |
9843 | case AR_PFS_REGNUM: |
9844 | /* Likewise for ar.pfs, which is used by br.ret. */ | |
9845 | return 1; | |
5527bf14 | 9846 | |
6ca3c22f RH |
9847 | default: |
9848 | return 0; | |
9849 | } | |
c65ebc55 | 9850 | } |
15b5aef3 RH |
9851 | |
9852 | /* Return true if REGNO is used by the frame unwinder. */ | |
9853 | ||
9854 | int | |
9c808aad | 9855 | ia64_eh_uses (int regno) |
15b5aef3 | 9856 | { |
09639a83 | 9857 | unsigned int r; |
6fb5fa3c | 9858 | |
15b5aef3 RH |
9859 | if (! reload_completed) |
9860 | return 0; | |
9861 | ||
6fb5fa3c DB |
9862 | if (regno == 0) |
9863 | return 0; | |
9864 | ||
9865 | for (r = reg_save_b0; r <= reg_save_ar_lc; r++) | |
9866 | if (regno == current_frame_info.r[r] | |
9867 | || regno == emitted_frame_related_regs[r]) | |
9868 | return 1; | |
15b5aef3 RH |
9869 | |
9870 | return 0; | |
9871 | } | |
c65ebc55 | 9872 | \f |
1cdbd630 | 9873 | /* Return true if this goes in small data/bss. */ |
c65ebc55 JW |
9874 | |
9875 | /* ??? We could also support own long data here. Generating movl/add/ld8 | |
9876 | instead of addl,ld8/ld8. This makes the code bigger, but should make the | |
9877 | code faster because there is one less load. This also includes incomplete | |
9878 | types which can't go in sdata/sbss. */ | |
9879 | ||
ae46c4e0 | 9880 | static bool |
3101faab | 9881 | ia64_in_small_data_p (const_tree exp) |
ae46c4e0 RH |
9882 | { |
9883 | if (TARGET_NO_SDATA) | |
9884 | return false; | |
9885 | ||
3907500b RH |
9886 | /* We want to merge strings, so we never consider them small data. */ |
9887 | if (TREE_CODE (exp) == STRING_CST) | |
9888 | return false; | |
9889 | ||
4c494a15 ZW |
9890 | /* Functions are never small data. */ |
9891 | if (TREE_CODE (exp) == FUNCTION_DECL) | |
9892 | return false; | |
9893 | ||
ae46c4e0 RH |
9894 | if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) |
9895 | { | |
9896 | const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); | |
826eb7ed | 9897 | |
ae46c4e0 | 9898 | if (strcmp (section, ".sdata") == 0 |
826eb7ed JB |
9899 | || strncmp (section, ".sdata.", 7) == 0 |
9900 | || strncmp (section, ".gnu.linkonce.s.", 16) == 0 | |
9901 | || strcmp (section, ".sbss") == 0 | |
9902 | || strncmp (section, ".sbss.", 6) == 0 | |
9903 | || strncmp (section, ".gnu.linkonce.sb.", 17) == 0) | |
ae46c4e0 RH |
9904 | return true; |
9905 | } | |
9906 | else | |
9907 | { | |
9908 | HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); | |
9909 | ||
9910 | /* If this is an incomplete type with size 0, then we can't put it | |
9911 | in sdata because it might be too big when completed. */ | |
9912 | if (size > 0 && size <= ia64_section_threshold) | |
9913 | return true; | |
9914 | } | |
9915 | ||
9916 | return false; | |
9917 | } | |
0c96007e | 9918 | \f |
ad0fc698 JW |
9919 | /* Output assembly directives for prologue regions. */ |
9920 | ||
9921 | /* The current basic block number. */ | |
9922 | ||
e0082a72 | 9923 | static bool last_block; |
ad0fc698 JW |
9924 | |
9925 | /* True if we need a copy_state command at the start of the next block. */ | |
9926 | ||
e0082a72 | 9927 | static bool need_copy_state; |
ad0fc698 | 9928 | |
658f32fd AO |
9929 | #ifndef MAX_ARTIFICIAL_LABEL_BYTES |
9930 | # define MAX_ARTIFICIAL_LABEL_BYTES 30 | |
9931 | #endif | |
9932 | ||
ad0fc698 JW |
9933 | /* The function emits unwind directives for the start of an epilogue. */ |
9934 | ||
9935 | static void | |
7d3c6cd8 RH |
9936 | process_epilogue (FILE *asm_out_file, rtx insn ATTRIBUTE_UNUSED, |
9937 | bool unwind, bool frame ATTRIBUTE_UNUSED) | |
ad0fc698 JW |
9938 | { |
9939 | /* If this isn't the last block of the function, then we need to label the | |
9940 | current state, and copy it back in at the start of the next block. */ | |
9941 | ||
e0082a72 | 9942 | if (!last_block) |
ad0fc698 | 9943 | { |
658f32fd AO |
9944 | if (unwind) |
9945 | fprintf (asm_out_file, "\t.label_state %d\n", | |
9946 | ++cfun->machine->state_num); | |
e0082a72 | 9947 | need_copy_state = true; |
ad0fc698 JW |
9948 | } |
9949 | ||
658f32fd AO |
9950 | if (unwind) |
9951 | fprintf (asm_out_file, "\t.restore sp\n"); | |
ad0fc698 | 9952 | } |
0c96007e | 9953 | |
5c255b57 | 9954 | /* This function processes a SET pattern for REG_CFA_ADJUST_CFA. */ |
97e242b0 | 9955 | |
5c255b57 RH |
9956 | static void |
9957 | process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn, | |
9958 | bool unwind, bool frame) | |
0c96007e | 9959 | { |
0c96007e | 9960 | rtx dest = SET_DEST (pat); |
5c255b57 | 9961 | rtx src = SET_SRC (pat); |
0c96007e | 9962 | |
5c255b57 | 9963 | if (dest == stack_pointer_rtx) |
0c96007e AM |
9964 | { |
9965 | if (GET_CODE (src) == PLUS) | |
5c255b57 | 9966 | { |
0c96007e AM |
9967 | rtx op0 = XEXP (src, 0); |
9968 | rtx op1 = XEXP (src, 1); | |
e820471b NS |
9969 | |
9970 | gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT); | |
9971 | ||
9972 | if (INTVAL (op1) < 0) | |
658f32fd AO |
9973 | { |
9974 | gcc_assert (!frame_pointer_needed); | |
9975 | if (unwind) | |
5c255b57 RH |
9976 | fprintf (asm_out_file, |
9977 | "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n", | |
658f32fd | 9978 | -INTVAL (op1)); |
658f32fd | 9979 | } |
0186257f | 9980 | else |
658f32fd | 9981 | process_epilogue (asm_out_file, insn, unwind, frame); |
0c96007e | 9982 | } |
0186257f | 9983 | else |
e820471b | 9984 | { |
5c255b57 | 9985 | gcc_assert (src == hard_frame_pointer_rtx); |
658f32fd | 9986 | process_epilogue (asm_out_file, insn, unwind, frame); |
e820471b | 9987 | } |
5c255b57 RH |
9988 | } |
9989 | else if (dest == hard_frame_pointer_rtx) | |
9990 | { | |
9991 | gcc_assert (src == stack_pointer_rtx); | |
9992 | gcc_assert (frame_pointer_needed); | |
0186257f | 9993 | |
5c255b57 RH |
9994 | if (unwind) |
9995 | fprintf (asm_out_file, "\t.vframe r%d\n", | |
9996 | ia64_dbx_register_number (REGNO (dest))); | |
0c96007e | 9997 | } |
5c255b57 RH |
9998 | else |
9999 | gcc_unreachable (); | |
10000 | } | |
0c96007e | 10001 | |
5c255b57 | 10002 | /* This function processes a SET pattern for REG_CFA_REGISTER. */ |
97e242b0 | 10003 | |
5c255b57 RH |
10004 | static void |
10005 | process_cfa_register (FILE *asm_out_file, rtx pat, bool unwind) | |
10006 | { | |
10007 | rtx dest = SET_DEST (pat); | |
10008 | rtx src = SET_SRC (pat); | |
5c255b57 | 10009 | int dest_regno = REGNO (dest); |
5f740973 | 10010 | int src_regno; |
97e242b0 | 10011 | |
5f740973 | 10012 | if (src == pc_rtx) |
5c255b57 | 10013 | { |
5c255b57 | 10014 | /* Saving return address pointer. */ |
5c255b57 RH |
10015 | if (unwind) |
10016 | fprintf (asm_out_file, "\t.save rp, r%d\n", | |
10017 | ia64_dbx_register_number (dest_regno)); | |
5f740973 RH |
10018 | return; |
10019 | } | |
10020 | ||
10021 | src_regno = REGNO (src); | |
97e242b0 | 10022 | |
5f740973 RH |
10023 | switch (src_regno) |
10024 | { | |
5c255b57 RH |
10025 | case PR_REG (0): |
10026 | gcc_assert (dest_regno == current_frame_info.r[reg_save_pr]); | |
10027 | if (unwind) | |
10028 | fprintf (asm_out_file, "\t.save pr, r%d\n", | |
10029 | ia64_dbx_register_number (dest_regno)); | |
10030 | break; | |
97e242b0 | 10031 | |
5c255b57 RH |
10032 | case AR_UNAT_REGNUM: |
10033 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_unat]); | |
10034 | if (unwind) | |
10035 | fprintf (asm_out_file, "\t.save ar.unat, r%d\n", | |
10036 | ia64_dbx_register_number (dest_regno)); | |
10037 | break; | |
97e242b0 | 10038 | |
5c255b57 RH |
10039 | case AR_LC_REGNUM: |
10040 | gcc_assert (dest_regno == current_frame_info.r[reg_save_ar_lc]); | |
10041 | if (unwind) | |
10042 | fprintf (asm_out_file, "\t.save ar.lc, r%d\n", | |
10043 | ia64_dbx_register_number (dest_regno)); | |
10044 | break; | |
10045 | ||
10046 | default: | |
10047 | /* Everything else should indicate being stored to memory. */ | |
10048 | gcc_unreachable (); | |
0c96007e | 10049 | } |
5c255b57 | 10050 | } |
97e242b0 | 10051 | |
5c255b57 | 10052 | /* This function processes a SET pattern for REG_CFA_OFFSET. */ |
97e242b0 | 10053 | |
5c255b57 RH |
10054 | static void |
10055 | process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind) | |
10056 | { | |
10057 | rtx dest = SET_DEST (pat); | |
10058 | rtx src = SET_SRC (pat); | |
10059 | int src_regno = REGNO (src); | |
10060 | const char *saveop; | |
10061 | HOST_WIDE_INT off; | |
10062 | rtx base; | |
0c96007e | 10063 | |
5c255b57 RH |
10064 | gcc_assert (MEM_P (dest)); |
10065 | if (GET_CODE (XEXP (dest, 0)) == REG) | |
10066 | { | |
10067 | base = XEXP (dest, 0); | |
10068 | off = 0; | |
10069 | } | |
10070 | else | |
10071 | { | |
10072 | gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS | |
10073 | && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT); | |
10074 | base = XEXP (XEXP (dest, 0), 0); | |
10075 | off = INTVAL (XEXP (XEXP (dest, 0), 1)); | |
10076 | } | |
97e242b0 | 10077 | |
5c255b57 RH |
10078 | if (base == hard_frame_pointer_rtx) |
10079 | { | |
10080 | saveop = ".savepsp"; | |
10081 | off = - off; | |
10082 | } | |
10083 | else | |
10084 | { | |
10085 | gcc_assert (base == stack_pointer_rtx); | |
10086 | saveop = ".savesp"; | |
10087 | } | |
97e242b0 | 10088 | |
5c255b57 RH |
10089 | src_regno = REGNO (src); |
10090 | switch (src_regno) | |
10091 | { | |
10092 | case BR_REG (0): | |
10093 | gcc_assert (!current_frame_info.r[reg_save_b0]); | |
10094 | if (unwind) | |
10095 | fprintf (asm_out_file, "\t%s rp, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10096 | saveop, off); | |
10097 | break; | |
97e242b0 | 10098 | |
5c255b57 RH |
10099 | case PR_REG (0): |
10100 | gcc_assert (!current_frame_info.r[reg_save_pr]); | |
10101 | if (unwind) | |
10102 | fprintf (asm_out_file, "\t%s pr, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10103 | saveop, off); | |
10104 | break; | |
97e242b0 | 10105 | |
5c255b57 RH |
10106 | case AR_LC_REGNUM: |
10107 | gcc_assert (!current_frame_info.r[reg_save_ar_lc]); | |
10108 | if (unwind) | |
10109 | fprintf (asm_out_file, "\t%s ar.lc, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10110 | saveop, off); | |
10111 | break; | |
97e242b0 | 10112 | |
5c255b57 RH |
10113 | case AR_PFS_REGNUM: |
10114 | gcc_assert (!current_frame_info.r[reg_save_ar_pfs]); | |
10115 | if (unwind) | |
10116 | fprintf (asm_out_file, "\t%s ar.pfs, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10117 | saveop, off); | |
10118 | break; | |
97e242b0 | 10119 | |
5c255b57 RH |
10120 | case AR_UNAT_REGNUM: |
10121 | gcc_assert (!current_frame_info.r[reg_save_ar_unat]); | |
10122 | if (unwind) | |
10123 | fprintf (asm_out_file, "\t%s ar.unat, " HOST_WIDE_INT_PRINT_DEC "\n", | |
10124 | saveop, off); | |
10125 | break; | |
97e242b0 | 10126 | |
5c255b57 RH |
10127 | case GR_REG (4): |
10128 | case GR_REG (5): | |
10129 | case GR_REG (6): | |
10130 | case GR_REG (7): | |
10131 | if (unwind) | |
10132 | fprintf (asm_out_file, "\t.save.g 0x%x\n", | |
10133 | 1 << (src_regno - GR_REG (4))); | |
10134 | break; | |
97e242b0 | 10135 | |
5c255b57 RH |
10136 | case BR_REG (1): |
10137 | case BR_REG (2): | |
10138 | case BR_REG (3): | |
10139 | case BR_REG (4): | |
10140 | case BR_REG (5): | |
10141 | if (unwind) | |
10142 | fprintf (asm_out_file, "\t.save.b 0x%x\n", | |
10143 | 1 << (src_regno - BR_REG (1))); | |
10144 | break; | |
97e242b0 | 10145 | |
5c255b57 RH |
10146 | case FR_REG (2): |
10147 | case FR_REG (3): | |
10148 | case FR_REG (4): | |
10149 | case FR_REG (5): | |
10150 | if (unwind) | |
10151 | fprintf (asm_out_file, "\t.save.f 0x%x\n", | |
10152 | 1 << (src_regno - FR_REG (2))); | |
10153 | break; | |
97e242b0 | 10154 | |
5c255b57 RH |
10155 | case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19): |
10156 | case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23): | |
10157 | case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27): | |
10158 | case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31): | |
10159 | if (unwind) | |
10160 | fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n", | |
10161 | 1 << (src_regno - FR_REG (12))); | |
10162 | break; | |
97e242b0 | 10163 | |
5c255b57 RH |
10164 | default: |
10165 | /* ??? For some reason we mark other general registers, even those | |
10166 | we can't represent in the unwind info. Ignore them. */ | |
10167 | break; | |
10168 | } | |
0c96007e AM |
10169 | } |
10170 | ||
0c96007e AM |
10171 | /* This function looks at a single insn and emits any directives |
10172 | required to unwind this insn. */ | |
5c255b57 | 10173 | |
a68b5e52 RH |
10174 | static void |
10175 | ia64_asm_unwind_emit (FILE *asm_out_file, rtx insn) | |
0c96007e | 10176 | { |
d5fabb58 | 10177 | bool unwind = ia64_except_unwind_info (&global_options) == UI_TARGET; |
658f32fd | 10178 | bool frame = dwarf2out_do_frame (); |
5c255b57 RH |
10179 | rtx note, pat; |
10180 | bool handled_one; | |
10181 | ||
10182 | if (!unwind && !frame) | |
10183 | return; | |
658f32fd | 10184 | |
5c255b57 | 10185 | if (NOTE_INSN_BASIC_BLOCK_P (insn)) |
0c96007e | 10186 | { |
fefa31b5 DM |
10187 | last_block = NOTE_BASIC_BLOCK (insn)->next_bb |
10188 | == EXIT_BLOCK_PTR_FOR_FN (cfun); | |
97e242b0 | 10189 | |
5c255b57 RH |
10190 | /* Restore unwind state from immediately before the epilogue. */ |
10191 | if (need_copy_state) | |
ad0fc698 | 10192 | { |
5c255b57 | 10193 | if (unwind) |
ad0fc698 | 10194 | { |
5c255b57 RH |
10195 | fprintf (asm_out_file, "\t.body\n"); |
10196 | fprintf (asm_out_file, "\t.copy_state %d\n", | |
10197 | cfun->machine->state_num); | |
ad0fc698 | 10198 | } |
5c255b57 | 10199 | need_copy_state = false; |
ad0fc698 | 10200 | } |
5c255b57 | 10201 | } |
ad0fc698 | 10202 | |
b64925dc | 10203 | if (NOTE_P (insn) || ! RTX_FRAME_RELATED_P (insn)) |
5c255b57 RH |
10204 | return; |
10205 | ||
10206 | /* Look for the ALLOC insn. */ | |
10207 | if (INSN_CODE (insn) == CODE_FOR_alloc) | |
10208 | { | |
10209 | rtx dest = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); | |
10210 | int dest_regno = REGNO (dest); | |
ad0fc698 | 10211 | |
5c255b57 RH |
10212 | /* If this is the final destination for ar.pfs, then this must |
10213 | be the alloc in the prologue. */ | |
10214 | if (dest_regno == current_frame_info.r[reg_save_ar_pfs]) | |
10215 | { | |
10216 | if (unwind) | |
10217 | fprintf (asm_out_file, "\t.save ar.pfs, r%d\n", | |
10218 | ia64_dbx_register_number (dest_regno)); | |
10219 | } | |
97e242b0 | 10220 | else |
5c255b57 RH |
10221 | { |
10222 | /* This must be an alloc before a sibcall. We must drop the | |
10223 | old frame info. The easiest way to drop the old frame | |
10224 | info is to ensure we had a ".restore sp" directive | |
10225 | followed by a new prologue. If the procedure doesn't | |
10226 | have a memory-stack frame, we'll issue a dummy ".restore | |
10227 | sp" now. */ | |
10228 | if (current_frame_info.total_size == 0 && !frame_pointer_needed) | |
10229 | /* if haven't done process_epilogue() yet, do it now */ | |
10230 | process_epilogue (asm_out_file, insn, unwind, frame); | |
10231 | if (unwind) | |
10232 | fprintf (asm_out_file, "\t.prologue\n"); | |
10233 | } | |
10234 | return; | |
10235 | } | |
0c96007e | 10236 | |
5c255b57 RH |
10237 | handled_one = false; |
10238 | for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) | |
10239 | switch (REG_NOTE_KIND (note)) | |
10240 | { | |
10241 | case REG_CFA_ADJUST_CFA: | |
10242 | pat = XEXP (note, 0); | |
10243 | if (pat == NULL) | |
10244 | pat = PATTERN (insn); | |
10245 | process_cfa_adjust_cfa (asm_out_file, pat, insn, unwind, frame); | |
10246 | handled_one = true; | |
10247 | break; | |
809d4ef1 | 10248 | |
5c255b57 RH |
10249 | case REG_CFA_OFFSET: |
10250 | pat = XEXP (note, 0); | |
10251 | if (pat == NULL) | |
10252 | pat = PATTERN (insn); | |
10253 | process_cfa_offset (asm_out_file, pat, unwind); | |
10254 | handled_one = true; | |
10255 | break; | |
809d4ef1 | 10256 | |
5c255b57 RH |
10257 | case REG_CFA_REGISTER: |
10258 | pat = XEXP (note, 0); | |
10259 | if (pat == NULL) | |
10260 | pat = PATTERN (insn); | |
10261 | process_cfa_register (asm_out_file, pat, unwind); | |
10262 | handled_one = true; | |
10263 | break; | |
10264 | ||
10265 | case REG_FRAME_RELATED_EXPR: | |
10266 | case REG_CFA_DEF_CFA: | |
10267 | case REG_CFA_EXPRESSION: | |
10268 | case REG_CFA_RESTORE: | |
10269 | case REG_CFA_SET_VDRAP: | |
10270 | /* Not used in the ia64 port. */ | |
10271 | gcc_unreachable (); | |
10272 | ||
10273 | default: | |
10274 | /* Not a frame-related note. */ | |
10275 | break; | |
10276 | } | |
10277 | ||
10278 | /* All REG_FRAME_RELATED_P insns, besides ALLOC, are marked with the | |
10279 | explicit action to take. No guessing required. */ | |
10280 | gcc_assert (handled_one); | |
0c96007e | 10281 | } |
c65ebc55 | 10282 | |
a68b5e52 RH |
10283 | /* Implement TARGET_ASM_EMIT_EXCEPT_PERSONALITY. */ |
10284 | ||
10285 | static void | |
10286 | ia64_asm_emit_except_personality (rtx personality) | |
10287 | { | |
10288 | fputs ("\t.personality\t", asm_out_file); | |
10289 | output_addr_const (asm_out_file, personality); | |
10290 | fputc ('\n', asm_out_file); | |
10291 | } | |
10292 | ||
10293 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS. */ | |
10294 | ||
10295 | static void | |
10296 | ia64_asm_init_sections (void) | |
10297 | { | |
10298 | exception_section = get_unnamed_section (0, output_section_asm_op, | |
10299 | "\t.handlerdata"); | |
10300 | } | |
f0a0390e RH |
10301 | |
10302 | /* Implement TARGET_DEBUG_UNWIND_INFO. */ | |
10303 | ||
10304 | static enum unwind_info_type | |
10305 | ia64_debug_unwind_info (void) | |
10306 | { | |
10307 | return UI_TARGET; | |
10308 | } | |
0551c32d | 10309 | \f |
af795c3c RH |
10310 | enum ia64_builtins |
10311 | { | |
10312 | IA64_BUILTIN_BSP, | |
c252db20 L |
10313 | IA64_BUILTIN_COPYSIGNQ, |
10314 | IA64_BUILTIN_FABSQ, | |
10315 | IA64_BUILTIN_FLUSHRS, | |
fcb82ab0 | 10316 | IA64_BUILTIN_INFQ, |
b14446e2 SE |
10317 | IA64_BUILTIN_HUGE_VALQ, |
10318 | IA64_BUILTIN_max | |
af795c3c RH |
10319 | }; |
10320 | ||
b14446e2 SE |
10321 | static GTY(()) tree ia64_builtins[(int) IA64_BUILTIN_max]; |
10322 | ||
c65ebc55 | 10323 | void |
9c808aad | 10324 | ia64_init_builtins (void) |
c65ebc55 | 10325 | { |
9649812a | 10326 | tree fpreg_type; |
bf9ab6b6 | 10327 | tree float80_type; |
b14446e2 | 10328 | tree decl; |
9649812a MM |
10329 | |
10330 | /* The __fpreg type. */ | |
10331 | fpreg_type = make_node (REAL_TYPE); | |
4de67c26 | 10332 | TYPE_PRECISION (fpreg_type) = 82; |
9649812a MM |
10333 | layout_type (fpreg_type); |
10334 | (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg"); | |
10335 | ||
10336 | /* The __float80 type. */ | |
bf9ab6b6 | 10337 | float80_type = make_node (REAL_TYPE); |
968a7562 | 10338 | TYPE_PRECISION (float80_type) = 80; |
bf9ab6b6 MM |
10339 | layout_type (float80_type); |
10340 | (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); | |
9649812a MM |
10341 | |
10342 | /* The __float128 type. */ | |
02befdf4 | 10343 | if (!TARGET_HPUX) |
9649812a | 10344 | { |
b14446e2 | 10345 | tree ftype; |
9649812a | 10346 | tree float128_type = make_node (REAL_TYPE); |
c252db20 | 10347 | |
9649812a MM |
10348 | TYPE_PRECISION (float128_type) = 128; |
10349 | layout_type (float128_type); | |
10350 | (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); | |
c252db20 L |
10351 | |
10352 | /* TFmode support builtins. */ | |
c0676219 | 10353 | ftype = build_function_type_list (float128_type, NULL_TREE); |
b14446e2 SE |
10354 | decl = add_builtin_function ("__builtin_infq", ftype, |
10355 | IA64_BUILTIN_INFQ, BUILT_IN_MD, | |
10356 | NULL, NULL_TREE); | |
10357 | ia64_builtins[IA64_BUILTIN_INFQ] = decl; | |
c252db20 | 10358 | |
b14446e2 SE |
10359 | decl = add_builtin_function ("__builtin_huge_valq", ftype, |
10360 | IA64_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
10361 | NULL, NULL_TREE); | |
10362 | ia64_builtins[IA64_BUILTIN_HUGE_VALQ] = decl; | |
fcb82ab0 | 10363 | |
c252db20 L |
10364 | ftype = build_function_type_list (float128_type, |
10365 | float128_type, | |
10366 | NULL_TREE); | |
10367 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
10368 | IA64_BUILTIN_FABSQ, BUILT_IN_MD, | |
10369 | "__fabstf2", NULL_TREE); | |
10370 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10371 | ia64_builtins[IA64_BUILTIN_FABSQ] = decl; |
c252db20 L |
10372 | |
10373 | ftype = build_function_type_list (float128_type, | |
10374 | float128_type, | |
10375 | float128_type, | |
10376 | NULL_TREE); | |
10377 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
10378 | IA64_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
10379 | "__copysigntf3", NULL_TREE); | |
10380 | TREE_READONLY (decl) = 1; | |
b14446e2 | 10381 | ia64_builtins[IA64_BUILTIN_COPYSIGNQ] = decl; |
9649812a MM |
10382 | } |
10383 | else | |
02befdf4 | 10384 | /* Under HPUX, this is a synonym for "long double". */ |
9649812a MM |
10385 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, |
10386 | "__float128"); | |
10387 | ||
f2972bf8 | 10388 | /* Fwrite on VMS is non-standard. */ |
171da07a RH |
10389 | #if TARGET_ABI_OPEN_VMS |
10390 | vms_patch_builtins (); | |
10391 | #endif | |
f2972bf8 | 10392 | |
6e34d3a3 | 10393 | #define def_builtin(name, type, code) \ |
c79efc4d RÁE |
10394 | add_builtin_function ((name), (type), (code), BUILT_IN_MD, \ |
10395 | NULL, NULL_TREE) | |
0551c32d | 10396 | |
b14446e2 | 10397 | decl = def_builtin ("__builtin_ia64_bsp", |
c0676219 NF |
10398 | build_function_type_list (ptr_type_node, NULL_TREE), |
10399 | IA64_BUILTIN_BSP); | |
b14446e2 | 10400 | ia64_builtins[IA64_BUILTIN_BSP] = decl; |
ce152ef8 | 10401 | |
b14446e2 | 10402 | decl = def_builtin ("__builtin_ia64_flushrs", |
c0676219 NF |
10403 | build_function_type_list (void_type_node, NULL_TREE), |
10404 | IA64_BUILTIN_FLUSHRS); | |
b14446e2 | 10405 | ia64_builtins[IA64_BUILTIN_FLUSHRS] = decl; |
ce152ef8 | 10406 | |
0551c32d | 10407 | #undef def_builtin |
7d522000 SE |
10408 | |
10409 | if (TARGET_HPUX) | |
10410 | { | |
ccea4a27 | 10411 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) |
e79983f4 | 10412 | set_user_assembler_name (decl, "_Isfinite"); |
ccea4a27 | 10413 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) |
e79983f4 | 10414 | set_user_assembler_name (decl, "_Isfinitef"); |
ccea4a27 | 10415 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEL)) != NULL_TREE) |
e79983f4 | 10416 | set_user_assembler_name (decl, "_Isfinitef128"); |
7d522000 | 10417 | } |
c65ebc55 JW |
10418 | } |
10419 | ||
c65ebc55 | 10420 | rtx |
9c808aad AJ |
10421 | ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, |
10422 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
10423 | int ignore ATTRIBUTE_UNUSED) | |
c65ebc55 | 10424 | { |
767fad4c | 10425 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
97e242b0 | 10426 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
c65ebc55 JW |
10427 | |
10428 | switch (fcode) | |
10429 | { | |
ce152ef8 | 10430 | case IA64_BUILTIN_BSP: |
0551c32d RH |
10431 | if (! target || ! register_operand (target, DImode)) |
10432 | target = gen_reg_rtx (DImode); | |
10433 | emit_insn (gen_bsp_value (target)); | |
8419b675 RK |
10434 | #ifdef POINTERS_EXTEND_UNSIGNED |
10435 | target = convert_memory_address (ptr_mode, target); | |
10436 | #endif | |
0551c32d | 10437 | return target; |
ce152ef8 AM |
10438 | |
10439 | case IA64_BUILTIN_FLUSHRS: | |
3b572406 RH |
10440 | emit_insn (gen_flushrs ()); |
10441 | return const0_rtx; | |
ce152ef8 | 10442 | |
c252db20 | 10443 | case IA64_BUILTIN_INFQ: |
fcb82ab0 | 10444 | case IA64_BUILTIN_HUGE_VALQ: |
c252db20 | 10445 | { |
6aad068a | 10446 | enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); |
c252db20 L |
10447 | REAL_VALUE_TYPE inf; |
10448 | rtx tmp; | |
10449 | ||
10450 | real_inf (&inf); | |
6aad068a | 10451 | tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode); |
c252db20 | 10452 | |
6aad068a | 10453 | tmp = validize_mem (force_const_mem (target_mode, tmp)); |
c252db20 L |
10454 | |
10455 | if (target == 0) | |
6aad068a | 10456 | target = gen_reg_rtx (target_mode); |
c252db20 L |
10457 | |
10458 | emit_move_insn (target, tmp); | |
10459 | return target; | |
10460 | } | |
10461 | ||
10462 | case IA64_BUILTIN_FABSQ: | |
10463 | case IA64_BUILTIN_COPYSIGNQ: | |
10464 | return expand_call (exp, target, ignore); | |
10465 | ||
c65ebc55 | 10466 | default: |
c252db20 | 10467 | gcc_unreachable (); |
c65ebc55 JW |
10468 | } |
10469 | ||
0551c32d | 10470 | return NULL_RTX; |
c65ebc55 | 10471 | } |
0d7839da | 10472 | |
b14446e2 SE |
10473 | /* Return the ia64 builtin for CODE. */ |
10474 | ||
10475 | static tree | |
10476 | ia64_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) | |
10477 | { | |
10478 | if (code >= IA64_BUILTIN_max) | |
10479 | return error_mark_node; | |
10480 | ||
10481 | return ia64_builtins[code]; | |
10482 | } | |
10483 | ||
0d7839da SE |
10484 | /* For the HP-UX IA64 aggregate parameters are passed stored in the |
10485 | most significant bits of the stack slot. */ | |
10486 | ||
10487 | enum direction | |
586de218 | 10488 | ia64_hpux_function_arg_padding (enum machine_mode mode, const_tree type) |
0d7839da | 10489 | { |
ed168e45 | 10490 | /* Exception to normal case for structures/unions/etc. */ |
0d7839da SE |
10491 | |
10492 | if (type && AGGREGATE_TYPE_P (type) | |
10493 | && int_size_in_bytes (type) < UNITS_PER_WORD) | |
10494 | return upward; | |
10495 | ||
d3704c46 KH |
10496 | /* Fall back to the default. */ |
10497 | return DEFAULT_FUNCTION_ARG_PADDING (mode, type); | |
0d7839da | 10498 | } |
686f3bf0 | 10499 | |
c47c29c8 L |
10500 | /* Emit text to declare externally defined variables and functions, because |
10501 | the Intel assembler does not support undefined externals. */ | |
686f3bf0 | 10502 | |
c47c29c8 L |
10503 | void |
10504 | ia64_asm_output_external (FILE *file, tree decl, const char *name) | |
686f3bf0 | 10505 | { |
c47c29c8 L |
10506 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
10507 | set in order to avoid putting out names that are never really | |
10508 | used. */ | |
10509 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
686f3bf0 | 10510 | { |
c47c29c8 | 10511 | /* maybe_assemble_visibility will return 1 if the assembler |
2e226e66 | 10512 | visibility directive is output. */ |
c47c29c8 L |
10513 | int need_visibility = ((*targetm.binds_local_p) (decl) |
10514 | && maybe_assemble_visibility (decl)); | |
57d4f65c | 10515 | |
c47c29c8 L |
10516 | /* GNU as does not need anything here, but the HP linker does |
10517 | need something for external functions. */ | |
10518 | if ((TARGET_HPUX_LD || !TARGET_GNU_AS) | |
10519 | && TREE_CODE (decl) == FUNCTION_DECL) | |
812b587e | 10520 | (*targetm.asm_out.globalize_decl_name) (file, decl); |
c47c29c8 L |
10521 | else if (need_visibility && !TARGET_GNU_AS) |
10522 | (*targetm.asm_out.globalize_label) (file, name); | |
686f3bf0 SE |
10523 | } |
10524 | } | |
10525 | ||
1f7aa7cd | 10526 | /* Set SImode div/mod functions, init_integral_libfuncs only initializes |
6bc709c1 L |
10527 | modes of word_mode and larger. Rename the TFmode libfuncs using the |
10528 | HPUX conventions. __divtf3 is used for XFmode. We need to keep it for | |
10529 | backward compatibility. */ | |
1f7aa7cd SE |
10530 | |
10531 | static void | |
10532 | ia64_init_libfuncs (void) | |
10533 | { | |
10534 | set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); | |
10535 | set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); | |
10536 | set_optab_libfunc (smod_optab, SImode, "__modsi3"); | |
10537 | set_optab_libfunc (umod_optab, SImode, "__umodsi3"); | |
6bc709c1 L |
10538 | |
10539 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
10540 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
10541 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
10542 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
10543 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
10544 | ||
10545 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); | |
10546 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
10547 | set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad"); | |
10548 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
10549 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
10550 | set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80"); | |
10551 | ||
10552 | set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl"); | |
10553 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
4a73d865 | 10554 | set_conv_libfunc (sfix_optab, TImode, TFmode, "_U_Qfcnvfxt_quad_to_quad"); |
6bc709c1 L |
10555 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl"); |
10556 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl"); | |
10557 | ||
10558 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
10559 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
4a73d865 | 10560 | set_conv_libfunc (sfloat_optab, TFmode, TImode, "_U_Qfcnvxf_quad_to_quad"); |
2a3ebe77 JM |
10561 | /* HP-UX 11.23 libc does not have a function for unsigned |
10562 | SImode-to-TFmode conversion. */ | |
10563 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxuf_dbl_to_quad"); | |
1f7aa7cd SE |
10564 | } |
10565 | ||
c15c90bb | 10566 | /* Rename all the TFmode libfuncs using the HPUX conventions. */ |
738e7b39 | 10567 | |
c15c90bb ZW |
10568 | static void |
10569 | ia64_hpux_init_libfuncs (void) | |
10570 | { | |
1f7aa7cd SE |
10571 | ia64_init_libfuncs (); |
10572 | ||
bdbba3c2 SE |
10573 | /* The HP SI millicode division and mod functions expect DI arguments. |
10574 | By turning them off completely we avoid using both libgcc and the | |
10575 | non-standard millicode routines and use the HP DI millicode routines | |
10576 | instead. */ | |
10577 | ||
10578 | set_optab_libfunc (sdiv_optab, SImode, 0); | |
10579 | set_optab_libfunc (udiv_optab, SImode, 0); | |
10580 | set_optab_libfunc (smod_optab, SImode, 0); | |
10581 | set_optab_libfunc (umod_optab, SImode, 0); | |
10582 | ||
10583 | set_optab_libfunc (sdiv_optab, DImode, "__milli_divI"); | |
10584 | set_optab_libfunc (udiv_optab, DImode, "__milli_divU"); | |
10585 | set_optab_libfunc (smod_optab, DImode, "__milli_remI"); | |
10586 | set_optab_libfunc (umod_optab, DImode, "__milli_remU"); | |
10587 | ||
10588 | /* HP-UX libc has TF min/max/abs routines in it. */ | |
c15c90bb ZW |
10589 | set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin"); |
10590 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
10591 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
c15c90bb | 10592 | |
24ea7948 ZW |
10593 | /* ia64_expand_compare uses this. */ |
10594 | cmptf_libfunc = init_one_libfunc ("_U_Qfcmp"); | |
10595 | ||
10596 | /* These should never be used. */ | |
10597 | set_optab_libfunc (eq_optab, TFmode, 0); | |
10598 | set_optab_libfunc (ne_optab, TFmode, 0); | |
10599 | set_optab_libfunc (gt_optab, TFmode, 0); | |
10600 | set_optab_libfunc (ge_optab, TFmode, 0); | |
10601 | set_optab_libfunc (lt_optab, TFmode, 0); | |
10602 | set_optab_libfunc (le_optab, TFmode, 0); | |
c15c90bb | 10603 | } |
738e7b39 RK |
10604 | |
10605 | /* Rename the division and modulus functions in VMS. */ | |
10606 | ||
10607 | static void | |
10608 | ia64_vms_init_libfuncs (void) | |
10609 | { | |
10610 | set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I"); | |
10611 | set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L"); | |
10612 | set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI"); | |
10613 | set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL"); | |
10614 | set_optab_libfunc (smod_optab, SImode, "OTS$REM_I"); | |
10615 | set_optab_libfunc (smod_optab, DImode, "OTS$REM_L"); | |
10616 | set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI"); | |
10617 | set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL"); | |
f2972bf8 DR |
10618 | abort_libfunc = init_one_libfunc ("decc$abort"); |
10619 | memcmp_libfunc = init_one_libfunc ("decc$memcmp"); | |
10620 | #ifdef MEM_LIBFUNCS_INIT | |
10621 | MEM_LIBFUNCS_INIT; | |
10622 | #endif | |
738e7b39 | 10623 | } |
6bc709c1 L |
10624 | |
10625 | /* Rename the TFmode libfuncs available from soft-fp in glibc using | |
10626 | the HPUX conventions. */ | |
10627 | ||
10628 | static void | |
10629 | ia64_sysv4_init_libfuncs (void) | |
10630 | { | |
10631 | ia64_init_libfuncs (); | |
10632 | ||
10633 | /* These functions are not part of the HPUX TFmode interface. We | |
10634 | use them instead of _U_Qfcmp, which doesn't work the way we | |
10635 | expect. */ | |
10636 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); | |
10637 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
10638 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
10639 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
10640 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
10641 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
10642 | ||
10643 | /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in | |
10644 | glibc doesn't have them. */ | |
10645 | } | |
c252db20 L |
10646 | |
10647 | /* Use soft-fp. */ | |
10648 | ||
10649 | static void | |
10650 | ia64_soft_fp_init_libfuncs (void) | |
10651 | { | |
10652 | } | |
f2972bf8 DR |
10653 | |
10654 | static bool | |
10655 | ia64_vms_valid_pointer_mode (enum machine_mode mode) | |
10656 | { | |
10657 | return (mode == SImode || mode == DImode); | |
10658 | } | |
ae46c4e0 | 10659 | \f |
9b580a0b RH |
10660 | /* For HPUX, it is illegal to have relocations in shared segments. */ |
10661 | ||
10662 | static int | |
10663 | ia64_hpux_reloc_rw_mask (void) | |
10664 | { | |
10665 | return 3; | |
10666 | } | |
10667 | ||
10668 | /* For others, relax this so that relocations to local data goes in | |
10669 | read-only segments, but we still cannot allow global relocations | |
10670 | in read-only segments. */ | |
10671 | ||
10672 | static int | |
10673 | ia64_reloc_rw_mask (void) | |
10674 | { | |
10675 | return flag_pic ? 3 : 2; | |
10676 | } | |
10677 | ||
d6b5193b RS |
10678 | /* Return the section to use for X. The only special thing we do here |
10679 | is to honor small data. */ | |
b64a1b53 | 10680 | |
d6b5193b | 10681 | static section * |
9c808aad AJ |
10682 | ia64_select_rtx_section (enum machine_mode mode, rtx x, |
10683 | unsigned HOST_WIDE_INT align) | |
b64a1b53 RH |
10684 | { |
10685 | if (GET_MODE_SIZE (mode) > 0 | |
1f4a2e84 SE |
10686 | && GET_MODE_SIZE (mode) <= ia64_section_threshold |
10687 | && !TARGET_NO_SDATA) | |
d6b5193b | 10688 | return sdata_section; |
b64a1b53 | 10689 | else |
d6b5193b | 10690 | return default_elf_select_rtx_section (mode, x, align); |
b64a1b53 RH |
10691 | } |
10692 | ||
1e1bd14e | 10693 | static unsigned int |
abb8b19a AM |
10694 | ia64_section_type_flags (tree decl, const char *name, int reloc) |
10695 | { | |
10696 | unsigned int flags = 0; | |
10697 | ||
10698 | if (strcmp (name, ".sdata") == 0 | |
10699 | || strncmp (name, ".sdata.", 7) == 0 | |
10700 | || strncmp (name, ".gnu.linkonce.s.", 16) == 0 | |
10701 | || strncmp (name, ".sdata2.", 8) == 0 | |
10702 | || strncmp (name, ".gnu.linkonce.s2.", 17) == 0 | |
10703 | || strcmp (name, ".sbss") == 0 | |
10704 | || strncmp (name, ".sbss.", 6) == 0 | |
10705 | || strncmp (name, ".gnu.linkonce.sb.", 17) == 0) | |
10706 | flags = SECTION_SMALL; | |
10707 | ||
9b580a0b | 10708 | flags |= default_section_type_flags (decl, name, reloc); |
abb8b19a | 10709 | return flags; |
1e1bd14e RH |
10710 | } |
10711 | ||
57782ad8 MM |
10712 | /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a |
10713 | structure type and that the address of that type should be passed | |
10714 | in out0, rather than in r8. */ | |
10715 | ||
10716 | static bool | |
10717 | ia64_struct_retval_addr_is_first_parm_p (tree fntype) | |
10718 | { | |
10719 | tree ret_type = TREE_TYPE (fntype); | |
10720 | ||
10721 | /* The Itanium C++ ABI requires that out0, rather than r8, be used | |
10722 | as the structure return address parameter, if the return value | |
10723 | type has a non-trivial copy constructor or destructor. It is not | |
10724 | clear if this same convention should be used for other | |
10725 | programming languages. Until G++ 3.4, we incorrectly used r8 for | |
10726 | these return values. */ | |
10727 | return (abi_version_at_least (2) | |
10728 | && ret_type | |
10729 | && TYPE_MODE (ret_type) == BLKmode | |
10730 | && TREE_ADDRESSABLE (ret_type) | |
10731 | && strcmp (lang_hooks.name, "GNU C++") == 0); | |
10732 | } | |
1e1bd14e | 10733 | |
5f13cfc6 RH |
10734 | /* Output the assembler code for a thunk function. THUNK_DECL is the |
10735 | declaration for the thunk function itself, FUNCTION is the decl for | |
10736 | the target function. DELTA is an immediate constant offset to be | |
272d0bee | 10737 | added to THIS. If VCALL_OFFSET is nonzero, the word at |
5f13cfc6 RH |
10738 | *(*this + vcall_offset) should be added to THIS. */ |
10739 | ||
c590b625 | 10740 | static void |
9c808aad AJ |
10741 | ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
10742 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
10743 | tree function) | |
483ab821 | 10744 | { |
0a2aaacc | 10745 | rtx this_rtx, insn, funexp; |
57782ad8 MM |
10746 | unsigned int this_parmno; |
10747 | unsigned int this_regno; | |
13f70342 | 10748 | rtx delta_rtx; |
5f13cfc6 | 10749 | |
599aedd9 | 10750 | reload_completed = 1; |
fe3ad572 | 10751 | epilogue_completed = 1; |
599aedd9 | 10752 | |
5f13cfc6 RH |
10753 | /* Set things up as ia64_expand_prologue might. */ |
10754 | last_scratch_gr_reg = 15; | |
10755 | ||
10756 | memset (¤t_frame_info, 0, sizeof (current_frame_info)); | |
10757 | current_frame_info.spill_cfa_off = -16; | |
10758 | current_frame_info.n_input_regs = 1; | |
10759 | current_frame_info.need_regstk = (TARGET_REG_NAMES != 0); | |
10760 | ||
5f13cfc6 | 10761 | /* Mark the end of the (empty) prologue. */ |
2e040219 | 10762 | emit_note (NOTE_INSN_PROLOGUE_END); |
5f13cfc6 | 10763 | |
57782ad8 MM |
10764 | /* Figure out whether "this" will be the first parameter (the |
10765 | typical case) or the second parameter (as happens when the | |
10766 | virtual function returns certain class objects). */ | |
10767 | this_parmno | |
10768 | = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk)) | |
10769 | ? 1 : 0); | |
10770 | this_regno = IN_REG (this_parmno); | |
10771 | if (!TARGET_REG_NAMES) | |
10772 | reg_names[this_regno] = ia64_reg_numbers[this_parmno]; | |
10773 | ||
0a2aaacc | 10774 | this_rtx = gen_rtx_REG (Pmode, this_regno); |
13f70342 RH |
10775 | |
10776 | /* Apply the constant offset, if required. */ | |
10777 | delta_rtx = GEN_INT (delta); | |
36c216e5 MM |
10778 | if (TARGET_ILP32) |
10779 | { | |
57782ad8 | 10780 | rtx tmp = gen_rtx_REG (ptr_mode, this_regno); |
36c216e5 | 10781 | REG_POINTER (tmp) = 1; |
13f70342 | 10782 | if (delta && satisfies_constraint_I (delta_rtx)) |
36c216e5 | 10783 | { |
0a2aaacc | 10784 | emit_insn (gen_ptr_extend_plus_imm (this_rtx, tmp, delta_rtx)); |
36c216e5 MM |
10785 | delta = 0; |
10786 | } | |
10787 | else | |
0a2aaacc | 10788 | emit_insn (gen_ptr_extend (this_rtx, tmp)); |
36c216e5 | 10789 | } |
5f13cfc6 RH |
10790 | if (delta) |
10791 | { | |
13f70342 | 10792 | if (!satisfies_constraint_I (delta_rtx)) |
5f13cfc6 RH |
10793 | { |
10794 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10795 | emit_move_insn (tmp, delta_rtx); | |
10796 | delta_rtx = tmp; | |
10797 | } | |
0a2aaacc | 10798 | emit_insn (gen_adddi3 (this_rtx, this_rtx, delta_rtx)); |
5f13cfc6 RH |
10799 | } |
10800 | ||
10801 | /* Apply the offset from the vtable, if required. */ | |
10802 | if (vcall_offset) | |
10803 | { | |
10804 | rtx vcall_offset_rtx = GEN_INT (vcall_offset); | |
10805 | rtx tmp = gen_rtx_REG (Pmode, 2); | |
10806 | ||
36c216e5 MM |
10807 | if (TARGET_ILP32) |
10808 | { | |
10809 | rtx t = gen_rtx_REG (ptr_mode, 2); | |
10810 | REG_POINTER (t) = 1; | |
0a2aaacc | 10811 | emit_move_insn (t, gen_rtx_MEM (ptr_mode, this_rtx)); |
13f70342 | 10812 | if (satisfies_constraint_I (vcall_offset_rtx)) |
36c216e5 | 10813 | { |
13f70342 | 10814 | emit_insn (gen_ptr_extend_plus_imm (tmp, t, vcall_offset_rtx)); |
36c216e5 MM |
10815 | vcall_offset = 0; |
10816 | } | |
10817 | else | |
10818 | emit_insn (gen_ptr_extend (tmp, t)); | |
10819 | } | |
10820 | else | |
0a2aaacc | 10821 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx)); |
5f13cfc6 | 10822 | |
36c216e5 | 10823 | if (vcall_offset) |
5f13cfc6 | 10824 | { |
13f70342 | 10825 | if (!satisfies_constraint_J (vcall_offset_rtx)) |
36c216e5 MM |
10826 | { |
10827 | rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ()); | |
10828 | emit_move_insn (tmp2, vcall_offset_rtx); | |
10829 | vcall_offset_rtx = tmp2; | |
10830 | } | |
10831 | emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx)); | |
5f13cfc6 | 10832 | } |
5f13cfc6 | 10833 | |
36c216e5 | 10834 | if (TARGET_ILP32) |
13f70342 | 10835 | emit_insn (gen_zero_extendsidi2 (tmp, gen_rtx_MEM (ptr_mode, tmp))); |
36c216e5 MM |
10836 | else |
10837 | emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); | |
5f13cfc6 | 10838 | |
0a2aaacc | 10839 | emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp)); |
5f13cfc6 RH |
10840 | } |
10841 | ||
10842 | /* Generate a tail call to the target function. */ | |
10843 | if (! TREE_USED (function)) | |
10844 | { | |
10845 | assemble_external (function); | |
10846 | TREE_USED (function) = 1; | |
10847 | } | |
10848 | funexp = XEXP (DECL_RTL (function), 0); | |
10849 | funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); | |
10850 | ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1); | |
10851 | insn = get_last_insn (); | |
10852 | SIBLING_CALL_P (insn) = 1; | |
599aedd9 RH |
10853 | |
10854 | /* Code generation for calls relies on splitting. */ | |
10855 | reload_completed = 1; | |
fe3ad572 | 10856 | epilogue_completed = 1; |
599aedd9 RH |
10857 | try_split (PATTERN (insn), insn, 0); |
10858 | ||
5f13cfc6 RH |
10859 | emit_barrier (); |
10860 | ||
10861 | /* Run just enough of rest_of_compilation to get the insns emitted. | |
10862 | There's not really enough bulk here to make other passes such as | |
10863 | instruction scheduling worth while. Note that use_thunk calls | |
10864 | assemble_start_function and assemble_end_function. */ | |
599aedd9 | 10865 | |
18dbd950 | 10866 | emit_all_insn_group_barriers (NULL); |
5f13cfc6 | 10867 | insn = get_insns (); |
5f13cfc6 RH |
10868 | shorten_branches (insn); |
10869 | final_start_function (insn, file, 1); | |
c9d691e9 | 10870 | final (insn, file, 1); |
5f13cfc6 | 10871 | final_end_function (); |
599aedd9 RH |
10872 | |
10873 | reload_completed = 0; | |
fe3ad572 | 10874 | epilogue_completed = 0; |
483ab821 MM |
10875 | } |
10876 | ||
351a758b KH |
10877 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
10878 | ||
10879 | static rtx | |
57782ad8 | 10880 | ia64_struct_value_rtx (tree fntype, |
351a758b KH |
10881 | int incoming ATTRIBUTE_UNUSED) |
10882 | { | |
f2972bf8 DR |
10883 | if (TARGET_ABI_OPEN_VMS || |
10884 | (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))) | |
57782ad8 | 10885 | return NULL_RTX; |
351a758b KH |
10886 | return gen_rtx_REG (Pmode, GR_REG (8)); |
10887 | } | |
10888 | ||
88ed5ef5 SE |
10889 | static bool |
10890 | ia64_scalar_mode_supported_p (enum machine_mode mode) | |
10891 | { | |
10892 | switch (mode) | |
10893 | { | |
10894 | case QImode: | |
10895 | case HImode: | |
10896 | case SImode: | |
10897 | case DImode: | |
10898 | case TImode: | |
10899 | return true; | |
10900 | ||
10901 | case SFmode: | |
10902 | case DFmode: | |
10903 | case XFmode: | |
4de67c26 | 10904 | case RFmode: |
88ed5ef5 SE |
10905 | return true; |
10906 | ||
10907 | case TFmode: | |
c252db20 | 10908 | return true; |
88ed5ef5 SE |
10909 | |
10910 | default: | |
10911 | return false; | |
10912 | } | |
10913 | } | |
10914 | ||
f61134e8 RH |
10915 | static bool |
10916 | ia64_vector_mode_supported_p (enum machine_mode mode) | |
10917 | { | |
10918 | switch (mode) | |
10919 | { | |
10920 | case V8QImode: | |
10921 | case V4HImode: | |
10922 | case V2SImode: | |
10923 | return true; | |
10924 | ||
10925 | case V2SFmode: | |
10926 | return true; | |
10927 | ||
10928 | default: | |
10929 | return false; | |
10930 | } | |
10931 | } | |
10932 | ||
694a2f6e EB |
10933 | /* Implement the FUNCTION_PROFILER macro. */ |
10934 | ||
2b4f149b RH |
10935 | void |
10936 | ia64_output_function_profiler (FILE *file, int labelno) | |
10937 | { | |
694a2f6e EB |
10938 | bool indirect_call; |
10939 | ||
10940 | /* If the function needs a static chain and the static chain | |
10941 | register is r15, we use an indirect call so as to bypass | |
10942 | the PLT stub in case the executable is dynamically linked, | |
10943 | because the stub clobbers r15 as per 5.3.6 of the psABI. | |
10944 | We don't need to do that in non canonical PIC mode. */ | |
10945 | ||
10946 | if (cfun->static_chain_decl && !TARGET_NO_PIC && !TARGET_AUTO_PIC) | |
10947 | { | |
10948 | gcc_assert (STATIC_CHAIN_REGNUM == 15); | |
10949 | indirect_call = true; | |
10950 | } | |
10951 | else | |
10952 | indirect_call = false; | |
10953 | ||
2b4f149b RH |
10954 | if (TARGET_GNU_AS) |
10955 | fputs ("\t.prologue 4, r40\n", file); | |
10956 | else | |
10957 | fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file); | |
10958 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file); | |
bd8633a3 RH |
10959 | |
10960 | if (NO_PROFILE_COUNTERS) | |
694a2f6e | 10961 | fputs ("\tmov out3 = r0\n", file); |
bd8633a3 RH |
10962 | else |
10963 | { | |
10964 | char buf[20]; | |
10965 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
10966 | ||
10967 | if (TARGET_AUTO_PIC) | |
10968 | fputs ("\tmovl out3 = @gprel(", file); | |
10969 | else | |
10970 | fputs ("\taddl out3 = @ltoff(", file); | |
10971 | assemble_name (file, buf); | |
10972 | if (TARGET_AUTO_PIC) | |
694a2f6e | 10973 | fputs (")\n", file); |
bd8633a3 | 10974 | else |
694a2f6e | 10975 | fputs ("), r1\n", file); |
bd8633a3 RH |
10976 | } |
10977 | ||
694a2f6e EB |
10978 | if (indirect_call) |
10979 | fputs ("\taddl r14 = @ltoff(@fptr(_mcount)), r1\n", file); | |
10980 | fputs ("\t;;\n", file); | |
10981 | ||
2b4f149b | 10982 | fputs ("\t.save rp, r42\n", file); |
bd8633a3 | 10983 | fputs ("\tmov out2 = b0\n", file); |
694a2f6e EB |
10984 | if (indirect_call) |
10985 | fputs ("\tld8 r14 = [r14]\n\t;;\n", file); | |
2b4f149b | 10986 | fputs ("\t.body\n", file); |
2b4f149b | 10987 | fputs ("\tmov out1 = r1\n", file); |
694a2f6e EB |
10988 | if (indirect_call) |
10989 | { | |
10990 | fputs ("\tld8 r16 = [r14], 8\n\t;;\n", file); | |
10991 | fputs ("\tmov b6 = r16\n", file); | |
10992 | fputs ("\tld8 r1 = [r14]\n", file); | |
10993 | fputs ("\tbr.call.sptk.many b0 = b6\n\t;;\n", file); | |
10994 | } | |
10995 | else | |
10996 | fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file); | |
2b4f149b RH |
10997 | } |
10998 | ||
d26afa4f SE |
10999 | static GTY(()) rtx mcount_func_rtx; |
11000 | static rtx | |
11001 | gen_mcount_func_rtx (void) | |
11002 | { | |
11003 | if (!mcount_func_rtx) | |
11004 | mcount_func_rtx = init_one_libfunc ("_mcount"); | |
11005 | return mcount_func_rtx; | |
11006 | } | |
11007 | ||
11008 | void | |
11009 | ia64_profile_hook (int labelno) | |
11010 | { | |
11011 | rtx label, ip; | |
11012 | ||
11013 | if (NO_PROFILE_COUNTERS) | |
11014 | label = const0_rtx; | |
11015 | else | |
11016 | { | |
11017 | char buf[30]; | |
11018 | const char *label_name; | |
11019 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); | |
55504c7c | 11020 | label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf)); |
d26afa4f SE |
11021 | label = gen_rtx_SYMBOL_REF (Pmode, label_name); |
11022 | SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL; | |
11023 | } | |
11024 | ip = gen_reg_rtx (Pmode); | |
11025 | emit_insn (gen_ip_value (ip)); | |
11026 | emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL, | |
11027 | VOIDmode, 3, | |
11028 | gen_rtx_REG (Pmode, BR_REG (0)), Pmode, | |
11029 | ip, Pmode, | |
11030 | label, Pmode); | |
11031 | } | |
11032 | ||
cac24f06 JM |
11033 | /* Return the mangling of TYPE if it is an extended fundamental type. */ |
11034 | ||
11035 | static const char * | |
3101faab | 11036 | ia64_mangle_type (const_tree type) |
cac24f06 | 11037 | { |
608063c3 JB |
11038 | type = TYPE_MAIN_VARIANT (type); |
11039 | ||
11040 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
11041 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
11042 | return NULL; | |
11043 | ||
cac24f06 JM |
11044 | /* On HP-UX, "long double" is mangled as "e" so __float128 is |
11045 | mangled as "e". */ | |
11046 | if (!TARGET_HPUX && TYPE_MODE (type) == TFmode) | |
11047 | return "g"; | |
11048 | /* On HP-UX, "e" is not available as a mangling of __float80 so use | |
11049 | an extended mangling. Elsewhere, "e" is available since long | |
11050 | double is 80 bits. */ | |
11051 | if (TYPE_MODE (type) == XFmode) | |
11052 | return TARGET_HPUX ? "u9__float80" : "e"; | |
4de67c26 JM |
11053 | if (TYPE_MODE (type) == RFmode) |
11054 | return "u7__fpreg"; | |
11055 | return NULL; | |
11056 | } | |
11057 | ||
11058 | /* Return the diagnostic message string if conversion from FROMTYPE to | |
11059 | TOTYPE is not allowed, NULL otherwise. */ | |
11060 | static const char * | |
3101faab | 11061 | ia64_invalid_conversion (const_tree fromtype, const_tree totype) |
4de67c26 JM |
11062 | { |
11063 | /* Reject nontrivial conversion to or from __fpreg. */ | |
11064 | if (TYPE_MODE (fromtype) == RFmode | |
11065 | && TYPE_MODE (totype) != RFmode | |
11066 | && TYPE_MODE (totype) != VOIDmode) | |
11067 | return N_("invalid conversion from %<__fpreg%>"); | |
11068 | if (TYPE_MODE (totype) == RFmode | |
11069 | && TYPE_MODE (fromtype) != RFmode) | |
11070 | return N_("invalid conversion to %<__fpreg%>"); | |
11071 | return NULL; | |
11072 | } | |
11073 | ||
11074 | /* Return the diagnostic message string if the unary operation OP is | |
11075 | not permitted on TYPE, NULL otherwise. */ | |
11076 | static const char * | |
3101faab | 11077 | ia64_invalid_unary_op (int op, const_tree type) |
4de67c26 JM |
11078 | { |
11079 | /* Reject operations on __fpreg other than unary + or &. */ | |
11080 | if (TYPE_MODE (type) == RFmode | |
11081 | && op != CONVERT_EXPR | |
11082 | && op != ADDR_EXPR) | |
11083 | return N_("invalid operation on %<__fpreg%>"); | |
11084 | return NULL; | |
11085 | } | |
11086 | ||
11087 | /* Return the diagnostic message string if the binary operation OP is | |
11088 | not permitted on TYPE1 and TYPE2, NULL otherwise. */ | |
11089 | static const char * | |
3101faab | 11090 | ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2) |
4de67c26 JM |
11091 | { |
11092 | /* Reject operations on __fpreg. */ | |
11093 | if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode) | |
11094 | return N_("invalid operation on %<__fpreg%>"); | |
cac24f06 JM |
11095 | return NULL; |
11096 | } | |
11097 | ||
812b587e SE |
11098 | /* HP-UX version_id attribute. |
11099 | For object foo, if the version_id is set to 1234 put out an alias | |
11100 | of '.alias foo "foo{1234}" We can't use "foo{1234}" in anything | |
11101 | other than an alias statement because it is an illegal symbol name. */ | |
11102 | ||
11103 | static tree | |
11104 | ia64_handle_version_id_attribute (tree *node ATTRIBUTE_UNUSED, | |
11105 | tree name ATTRIBUTE_UNUSED, | |
11106 | tree args, | |
11107 | int flags ATTRIBUTE_UNUSED, | |
11108 | bool *no_add_attrs) | |
11109 | { | |
11110 | tree arg = TREE_VALUE (args); | |
11111 | ||
11112 | if (TREE_CODE (arg) != STRING_CST) | |
11113 | { | |
11114 | error("version attribute is not a string"); | |
11115 | *no_add_attrs = true; | |
11116 | return NULL_TREE; | |
11117 | } | |
11118 | return NULL_TREE; | |
11119 | } | |
11120 | ||
a31fa2e0 SE |
11121 | /* Target hook for c_mode_for_suffix. */ |
11122 | ||
11123 | static enum machine_mode | |
11124 | ia64_c_mode_for_suffix (char suffix) | |
11125 | { | |
11126 | if (suffix == 'q') | |
11127 | return TFmode; | |
11128 | if (suffix == 'w') | |
11129 | return XFmode; | |
11130 | ||
11131 | return VOIDmode; | |
11132 | } | |
11133 | ||
f3a83111 SE |
11134 | static GTY(()) rtx ia64_dconst_0_5_rtx; |
11135 | ||
11136 | rtx | |
11137 | ia64_dconst_0_5 (void) | |
11138 | { | |
11139 | if (! ia64_dconst_0_5_rtx) | |
11140 | { | |
11141 | REAL_VALUE_TYPE rv; | |
11142 | real_from_string (&rv, "0.5"); | |
11143 | ia64_dconst_0_5_rtx = const_double_from_real_value (rv, DFmode); | |
11144 | } | |
11145 | return ia64_dconst_0_5_rtx; | |
11146 | } | |
11147 | ||
11148 | static GTY(()) rtx ia64_dconst_0_375_rtx; | |
11149 | ||
11150 | rtx | |
11151 | ia64_dconst_0_375 (void) | |
11152 | { | |
11153 | if (! ia64_dconst_0_375_rtx) | |
11154 | { | |
11155 | REAL_VALUE_TYPE rv; | |
11156 | real_from_string (&rv, "0.375"); | |
11157 | ia64_dconst_0_375_rtx = const_double_from_real_value (rv, DFmode); | |
11158 | } | |
11159 | return ia64_dconst_0_375_rtx; | |
11160 | } | |
11161 | ||
ffa88471 SE |
11162 | static enum machine_mode |
11163 | ia64_get_reg_raw_mode (int regno) | |
11164 | { | |
11165 | if (FR_REGNO_P (regno)) | |
11166 | return XFmode; | |
11167 | return default_get_reg_raw_mode(regno); | |
11168 | } | |
f3a83111 | 11169 | |
d9886a9e L |
11170 | /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. ??? Might not be needed |
11171 | anymore. */ | |
11172 | ||
11173 | bool | |
11174 | ia64_member_type_forces_blk (const_tree, enum machine_mode mode) | |
11175 | { | |
11176 | return TARGET_HPUX && mode == TFmode; | |
11177 | } | |
11178 | ||
f16d3f39 JH |
11179 | /* Always default to .text section until HP-UX linker is fixed. */ |
11180 | ||
11181 | ATTRIBUTE_UNUSED static section * | |
11182 | ia64_hpux_function_section (tree decl ATTRIBUTE_UNUSED, | |
11183 | enum node_frequency freq ATTRIBUTE_UNUSED, | |
11184 | bool startup ATTRIBUTE_UNUSED, | |
11185 | bool exit ATTRIBUTE_UNUSED) | |
11186 | { | |
11187 | return NULL; | |
11188 | } | |
e6431744 RH |
11189 | \f |
11190 | /* Construct (set target (vec_select op0 (parallel perm))) and | |
11191 | return true if that's a valid instruction in the active ISA. */ | |
11192 | ||
11193 | static bool | |
11194 | expand_vselect (rtx target, rtx op0, const unsigned char *perm, unsigned nelt) | |
11195 | { | |
11196 | rtx rperm[MAX_VECT_LEN], x; | |
11197 | unsigned i; | |
11198 | ||
11199 | for (i = 0; i < nelt; ++i) | |
11200 | rperm[i] = GEN_INT (perm[i]); | |
11201 | ||
11202 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm)); | |
11203 | x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x); | |
11204 | x = gen_rtx_SET (VOIDmode, target, x); | |
11205 | ||
11206 | x = emit_insn (x); | |
11207 | if (recog_memoized (x) < 0) | |
11208 | { | |
11209 | remove_insn (x); | |
11210 | return false; | |
11211 | } | |
11212 | return true; | |
11213 | } | |
11214 | ||
11215 | /* Similar, but generate a vec_concat from op0 and op1 as well. */ | |
11216 | ||
11217 | static bool | |
11218 | expand_vselect_vconcat (rtx target, rtx op0, rtx op1, | |
11219 | const unsigned char *perm, unsigned nelt) | |
11220 | { | |
11221 | enum machine_mode v2mode; | |
11222 | rtx x; | |
11223 | ||
11224 | v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0)); | |
11225 | x = gen_rtx_VEC_CONCAT (v2mode, op0, op1); | |
11226 | return expand_vselect (target, x, perm, nelt); | |
11227 | } | |
11228 | ||
11229 | /* Try to expand a no-op permutation. */ | |
11230 | ||
11231 | static bool | |
11232 | expand_vec_perm_identity (struct expand_vec_perm_d *d) | |
11233 | { | |
11234 | unsigned i, nelt = d->nelt; | |
11235 | ||
11236 | for (i = 0; i < nelt; ++i) | |
11237 | if (d->perm[i] != i) | |
11238 | return false; | |
11239 | ||
11240 | if (!d->testing_p) | |
11241 | emit_move_insn (d->target, d->op0); | |
11242 | ||
11243 | return true; | |
11244 | } | |
11245 | ||
11246 | /* Try to expand D via a shrp instruction. */ | |
11247 | ||
11248 | static bool | |
11249 | expand_vec_perm_shrp (struct expand_vec_perm_d *d) | |
11250 | { | |
11251 | unsigned i, nelt = d->nelt, shift, mask; | |
2d130b31 | 11252 | rtx tmp, hi, lo; |
e6431744 RH |
11253 | |
11254 | /* ??? Don't force V2SFmode into the integer registers. */ | |
11255 | if (d->vmode == V2SFmode) | |
11256 | return false; | |
11257 | ||
11258 | mask = (d->one_operand_p ? nelt - 1 : 2 * nelt - 1); | |
11259 | ||
11260 | shift = d->perm[0]; | |
2d130b31 UB |
11261 | if (BYTES_BIG_ENDIAN && shift > nelt) |
11262 | return false; | |
11263 | ||
e6431744 RH |
11264 | for (i = 1; i < nelt; ++i) |
11265 | if (d->perm[i] != ((shift + i) & mask)) | |
11266 | return false; | |
11267 | ||
11268 | if (d->testing_p) | |
11269 | return true; | |
11270 | ||
2d130b31 UB |
11271 | hi = shift < nelt ? d->op1 : d->op0; |
11272 | lo = shift < nelt ? d->op0 : d->op1; | |
11273 | ||
11274 | shift %= nelt; | |
11275 | ||
e6431744 RH |
11276 | shift *= GET_MODE_UNIT_SIZE (d->vmode) * BITS_PER_UNIT; |
11277 | ||
11278 | /* We've eliminated the shift 0 case via expand_vec_perm_identity. */ | |
11279 | gcc_assert (IN_RANGE (shift, 1, 63)); | |
11280 | ||
11281 | /* Recall that big-endian elements are numbered starting at the top of | |
11282 | the register. Ideally we'd have a shift-left-pair. But since we | |
11283 | don't, convert to a shift the other direction. */ | |
11284 | if (BYTES_BIG_ENDIAN) | |
11285 | shift = 64 - shift; | |
11286 | ||
11287 | tmp = gen_reg_rtx (DImode); | |
2d130b31 UB |
11288 | hi = gen_lowpart (DImode, hi); |
11289 | lo = gen_lowpart (DImode, lo); | |
11290 | emit_insn (gen_shrp (tmp, hi, lo, GEN_INT (shift))); | |
e6431744 RH |
11291 | |
11292 | emit_move_insn (d->target, gen_lowpart (d->vmode, tmp)); | |
11293 | return true; | |
11294 | } | |
11295 | ||
11296 | /* Try to instantiate D in a single instruction. */ | |
11297 | ||
11298 | static bool | |
11299 | expand_vec_perm_1 (struct expand_vec_perm_d *d) | |
11300 | { | |
11301 | unsigned i, nelt = d->nelt; | |
11302 | unsigned char perm2[MAX_VECT_LEN]; | |
11303 | ||
11304 | /* Try single-operand selections. */ | |
11305 | if (d->one_operand_p) | |
11306 | { | |
11307 | if (expand_vec_perm_identity (d)) | |
11308 | return true; | |
11309 | if (expand_vselect (d->target, d->op0, d->perm, nelt)) | |
11310 | return true; | |
11311 | } | |
11312 | ||
11313 | /* Try two operand selections. */ | |
11314 | if (expand_vselect_vconcat (d->target, d->op0, d->op1, d->perm, nelt)) | |
11315 | return true; | |
11316 | ||
11317 | /* Recognize interleave style patterns with reversed operands. */ | |
11318 | if (!d->one_operand_p) | |
11319 | { | |
11320 | for (i = 0; i < nelt; ++i) | |
11321 | { | |
11322 | unsigned e = d->perm[i]; | |
11323 | if (e >= nelt) | |
11324 | e -= nelt; | |
11325 | else | |
11326 | e += nelt; | |
11327 | perm2[i] = e; | |
11328 | } | |
11329 | ||
11330 | if (expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt)) | |
11331 | return true; | |
11332 | } | |
11333 | ||
11334 | if (expand_vec_perm_shrp (d)) | |
11335 | return true; | |
11336 | ||
11337 | /* ??? Look for deposit-like permutations where most of the result | |
11338 | comes from one vector unchanged and the rest comes from a | |
11339 | sequential hunk of the other vector. */ | |
11340 | ||
11341 | return false; | |
11342 | } | |
11343 | ||
11344 | /* Pattern match broadcast permutations. */ | |
11345 | ||
11346 | static bool | |
11347 | expand_vec_perm_broadcast (struct expand_vec_perm_d *d) | |
11348 | { | |
11349 | unsigned i, elt, nelt = d->nelt; | |
11350 | unsigned char perm2[2]; | |
11351 | rtx temp; | |
11352 | bool ok; | |
11353 | ||
11354 | if (!d->one_operand_p) | |
11355 | return false; | |
11356 | ||
11357 | elt = d->perm[0]; | |
11358 | for (i = 1; i < nelt; ++i) | |
11359 | if (d->perm[i] != elt) | |
11360 | return false; | |
11361 | ||
11362 | switch (d->vmode) | |
11363 | { | |
11364 | case V2SImode: | |
11365 | case V2SFmode: | |
11366 | /* Implementable by interleave. */ | |
11367 | perm2[0] = elt; | |
11368 | perm2[1] = elt + 2; | |
11369 | ok = expand_vselect_vconcat (d->target, d->op0, d->op0, perm2, 2); | |
11370 | gcc_assert (ok); | |
11371 | break; | |
11372 | ||
11373 | case V8QImode: | |
11374 | /* Implementable by extract + broadcast. */ | |
11375 | if (BYTES_BIG_ENDIAN) | |
11376 | elt = 7 - elt; | |
11377 | elt *= BITS_PER_UNIT; | |
11378 | temp = gen_reg_rtx (DImode); | |
11379 | emit_insn (gen_extzv (temp, gen_lowpart (DImode, d->op0), | |
96fda42c | 11380 | GEN_INT (8), GEN_INT (elt))); |
e6431744 RH |
11381 | emit_insn (gen_mux1_brcst_qi (d->target, gen_lowpart (QImode, temp))); |
11382 | break; | |
11383 | ||
11384 | case V4HImode: | |
11385 | /* Should have been matched directly by vec_select. */ | |
11386 | default: | |
11387 | gcc_unreachable (); | |
11388 | } | |
11389 | ||
11390 | return true; | |
11391 | } | |
11392 | ||
11393 | /* A subroutine of ia64_expand_vec_perm_const_1. Try to simplify a | |
11394 | two vector permutation into a single vector permutation by using | |
11395 | an interleave operation to merge the vectors. */ | |
11396 | ||
11397 | static bool | |
11398 | expand_vec_perm_interleave_2 (struct expand_vec_perm_d *d) | |
11399 | { | |
11400 | struct expand_vec_perm_d dremap, dfinal; | |
11401 | unsigned char remap[2 * MAX_VECT_LEN]; | |
11402 | unsigned contents, i, nelt, nelt2; | |
11403 | unsigned h0, h1, h2, h3; | |
11404 | rtx seq; | |
11405 | bool ok; | |
11406 | ||
11407 | if (d->one_operand_p) | |
11408 | return false; | |
11409 | ||
11410 | nelt = d->nelt; | |
11411 | nelt2 = nelt / 2; | |
11412 | ||
11413 | /* Examine from whence the elements come. */ | |
11414 | contents = 0; | |
11415 | for (i = 0; i < nelt; ++i) | |
11416 | contents |= 1u << d->perm[i]; | |
11417 | ||
11418 | memset (remap, 0xff, sizeof (remap)); | |
11419 | dremap = *d; | |
11420 | ||
11421 | h0 = (1u << nelt2) - 1; | |
11422 | h1 = h0 << nelt2; | |
11423 | h2 = h0 << nelt; | |
11424 | h3 = h0 << (nelt + nelt2); | |
11425 | ||
11426 | if ((contents & (h0 | h2)) == contents) /* punpck even halves */ | |
11427 | { | |
11428 | for (i = 0; i < nelt; ++i) | |
11429 | { | |
11430 | unsigned which = i / 2 + (i & 1 ? nelt : 0); | |
11431 | remap[which] = i; | |
11432 | dremap.perm[i] = which; | |
11433 | } | |
11434 | } | |
11435 | else if ((contents & (h1 | h3)) == contents) /* punpck odd halves */ | |
11436 | { | |
11437 | for (i = 0; i < nelt; ++i) | |
11438 | { | |
11439 | unsigned which = i / 2 + nelt2 + (i & 1 ? nelt : 0); | |
11440 | remap[which] = i; | |
11441 | dremap.perm[i] = which; | |
11442 | } | |
11443 | } | |
11444 | else if ((contents & 0x5555) == contents) /* mix even elements */ | |
11445 | { | |
11446 | for (i = 0; i < nelt; ++i) | |
11447 | { | |
11448 | unsigned which = (i & ~1) + (i & 1 ? nelt : 0); | |
11449 | remap[which] = i; | |
11450 | dremap.perm[i] = which; | |
11451 | } | |
11452 | } | |
11453 | else if ((contents & 0xaaaa) == contents) /* mix odd elements */ | |
11454 | { | |
11455 | for (i = 0; i < nelt; ++i) | |
11456 | { | |
11457 | unsigned which = (i | 1) + (i & 1 ? nelt : 0); | |
11458 | remap[which] = i; | |
11459 | dremap.perm[i] = which; | |
11460 | } | |
11461 | } | |
11462 | else if (floor_log2 (contents) - ctz_hwi (contents) < (int)nelt) /* shrp */ | |
11463 | { | |
11464 | unsigned shift = ctz_hwi (contents); | |
11465 | for (i = 0; i < nelt; ++i) | |
11466 | { | |
11467 | unsigned which = (i + shift) & (2 * nelt - 1); | |
11468 | remap[which] = i; | |
11469 | dremap.perm[i] = which; | |
11470 | } | |
11471 | } | |
11472 | else | |
11473 | return false; | |
11474 | ||
11475 | /* Use the remapping array set up above to move the elements from their | |
11476 | swizzled locations into their final destinations. */ | |
11477 | dfinal = *d; | |
11478 | for (i = 0; i < nelt; ++i) | |
11479 | { | |
11480 | unsigned e = remap[d->perm[i]]; | |
11481 | gcc_assert (e < nelt); | |
11482 | dfinal.perm[i] = e; | |
11483 | } | |
11484 | dfinal.op0 = gen_reg_rtx (dfinal.vmode); | |
11485 | dfinal.op1 = dfinal.op0; | |
11486 | dfinal.one_operand_p = true; | |
11487 | dremap.target = dfinal.op0; | |
11488 | ||
11489 | /* Test if the final remap can be done with a single insn. For V4HImode | |
11490 | this *will* succeed. For V8QImode or V2SImode it may not. */ | |
11491 | start_sequence (); | |
11492 | ok = expand_vec_perm_1 (&dfinal); | |
11493 | seq = get_insns (); | |
11494 | end_sequence (); | |
11495 | if (!ok) | |
11496 | return false; | |
11497 | if (d->testing_p) | |
11498 | return true; | |
11499 | ||
11500 | ok = expand_vec_perm_1 (&dremap); | |
11501 | gcc_assert (ok); | |
11502 | ||
11503 | emit_insn (seq); | |
11504 | return true; | |
11505 | } | |
11506 | ||
11507 | /* A subroutine of ia64_expand_vec_perm_const_1. Emit a full V4HImode | |
11508 | constant permutation via two mux2 and a merge. */ | |
11509 | ||
11510 | static bool | |
11511 | expand_vec_perm_v4hi_5 (struct expand_vec_perm_d *d) | |
11512 | { | |
11513 | unsigned char perm2[4]; | |
11514 | rtx rmask[4]; | |
11515 | unsigned i; | |
11516 | rtx t0, t1, mask, x; | |
11517 | bool ok; | |
11518 | ||
11519 | if (d->vmode != V4HImode || d->one_operand_p) | |
11520 | return false; | |
11521 | if (d->testing_p) | |
11522 | return true; | |
11523 | ||
11524 | for (i = 0; i < 4; ++i) | |
11525 | { | |
11526 | perm2[i] = d->perm[i] & 3; | |
11527 | rmask[i] = (d->perm[i] & 4 ? const0_rtx : constm1_rtx); | |
11528 | } | |
11529 | mask = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmask)); | |
11530 | mask = force_reg (V4HImode, mask); | |
11531 | ||
11532 | t0 = gen_reg_rtx (V4HImode); | |
11533 | t1 = gen_reg_rtx (V4HImode); | |
11534 | ||
11535 | ok = expand_vselect (t0, d->op0, perm2, 4); | |
11536 | gcc_assert (ok); | |
11537 | ok = expand_vselect (t1, d->op1, perm2, 4); | |
11538 | gcc_assert (ok); | |
11539 | ||
11540 | x = gen_rtx_AND (V4HImode, mask, t0); | |
11541 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
11542 | ||
11543 | x = gen_rtx_NOT (V4HImode, mask); | |
11544 | x = gen_rtx_AND (V4HImode, x, t1); | |
11545 | emit_insn (gen_rtx_SET (VOIDmode, t1, x)); | |
11546 | ||
11547 | x = gen_rtx_IOR (V4HImode, t0, t1); | |
11548 | emit_insn (gen_rtx_SET (VOIDmode, d->target, x)); | |
11549 | ||
11550 | return true; | |
11551 | } | |
11552 | ||
11553 | /* The guts of ia64_expand_vec_perm_const, also used by the ok hook. | |
11554 | With all of the interface bits taken care of, perform the expansion | |
11555 | in D and return true on success. */ | |
11556 | ||
11557 | static bool | |
11558 | ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) | |
11559 | { | |
11560 | if (expand_vec_perm_1 (d)) | |
11561 | return true; | |
11562 | if (expand_vec_perm_broadcast (d)) | |
11563 | return true; | |
11564 | if (expand_vec_perm_interleave_2 (d)) | |
11565 | return true; | |
11566 | if (expand_vec_perm_v4hi_5 (d)) | |
11567 | return true; | |
11568 | return false; | |
11569 | } | |
11570 | ||
11571 | bool | |
11572 | ia64_expand_vec_perm_const (rtx operands[4]) | |
11573 | { | |
11574 | struct expand_vec_perm_d d; | |
11575 | unsigned char perm[MAX_VECT_LEN]; | |
11576 | int i, nelt, which; | |
11577 | rtx sel; | |
11578 | ||
11579 | d.target = operands[0]; | |
11580 | d.op0 = operands[1]; | |
11581 | d.op1 = operands[2]; | |
11582 | sel = operands[3]; | |
11583 | ||
11584 | d.vmode = GET_MODE (d.target); | |
11585 | gcc_assert (VECTOR_MODE_P (d.vmode)); | |
11586 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11587 | d.testing_p = false; | |
11588 | ||
11589 | gcc_assert (GET_CODE (sel) == CONST_VECTOR); | |
11590 | gcc_assert (XVECLEN (sel, 0) == nelt); | |
11591 | gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); | |
11592 | ||
11593 | for (i = which = 0; i < nelt; ++i) | |
11594 | { | |
11595 | rtx e = XVECEXP (sel, 0, i); | |
11596 | int ei = INTVAL (e) & (2 * nelt - 1); | |
11597 | ||
11598 | which |= (ei < nelt ? 1 : 2); | |
11599 | d.perm[i] = ei; | |
11600 | perm[i] = ei; | |
11601 | } | |
11602 | ||
11603 | switch (which) | |
11604 | { | |
11605 | default: | |
11606 | gcc_unreachable(); | |
11607 | ||
11608 | case 3: | |
11609 | if (!rtx_equal_p (d.op0, d.op1)) | |
11610 | { | |
11611 | d.one_operand_p = false; | |
11612 | break; | |
11613 | } | |
11614 | ||
11615 | /* The elements of PERM do not suggest that only the first operand | |
11616 | is used, but both operands are identical. Allow easier matching | |
11617 | of the permutation by folding the permutation into the single | |
11618 | input vector. */ | |
11619 | for (i = 0; i < nelt; ++i) | |
11620 | if (d.perm[i] >= nelt) | |
11621 | d.perm[i] -= nelt; | |
11622 | /* FALLTHRU */ | |
11623 | ||
11624 | case 1: | |
11625 | d.op1 = d.op0; | |
11626 | d.one_operand_p = true; | |
11627 | break; | |
11628 | ||
11629 | case 2: | |
11630 | for (i = 0; i < nelt; ++i) | |
11631 | d.perm[i] -= nelt; | |
11632 | d.op0 = d.op1; | |
11633 | d.one_operand_p = true; | |
11634 | break; | |
11635 | } | |
11636 | ||
11637 | if (ia64_expand_vec_perm_const_1 (&d)) | |
11638 | return true; | |
11639 | ||
11640 | /* If the mask says both arguments are needed, but they are the same, | |
11641 | the above tried to expand with one_operand_p true. If that didn't | |
11642 | work, retry with one_operand_p false, as that's what we used in _ok. */ | |
11643 | if (which == 3 && d.one_operand_p) | |
11644 | { | |
11645 | memcpy (d.perm, perm, sizeof (perm)); | |
11646 | d.one_operand_p = false; | |
11647 | return ia64_expand_vec_perm_const_1 (&d); | |
11648 | } | |
11649 | ||
11650 | return false; | |
11651 | } | |
11652 | ||
11653 | /* Implement targetm.vectorize.vec_perm_const_ok. */ | |
11654 | ||
11655 | static bool | |
11656 | ia64_vectorize_vec_perm_const_ok (enum machine_mode vmode, | |
11657 | const unsigned char *sel) | |
11658 | { | |
11659 | struct expand_vec_perm_d d; | |
11660 | unsigned int i, nelt, which; | |
11661 | bool ret; | |
11662 | ||
11663 | d.vmode = vmode; | |
11664 | d.nelt = nelt = GET_MODE_NUNITS (d.vmode); | |
11665 | d.testing_p = true; | |
11666 | ||
11667 | /* Extract the values from the vector CST into the permutation | |
11668 | array in D. */ | |
11669 | memcpy (d.perm, sel, nelt); | |
11670 | for (i = which = 0; i < nelt; ++i) | |
11671 | { | |
11672 | unsigned char e = d.perm[i]; | |
11673 | gcc_assert (e < 2 * nelt); | |
11674 | which |= (e < nelt ? 1 : 2); | |
11675 | } | |
11676 | ||
11677 | /* For all elements from second vector, fold the elements to first. */ | |
11678 | if (which == 2) | |
11679 | for (i = 0; i < nelt; ++i) | |
11680 | d.perm[i] -= nelt; | |
11681 | ||
11682 | /* Check whether the mask can be applied to the vector type. */ | |
11683 | d.one_operand_p = (which != 3); | |
11684 | ||
11685 | /* Otherwise we have to go through the motions and see if we can | |
11686 | figure out how to generate the requested permutation. */ | |
11687 | d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); | |
11688 | d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); | |
11689 | if (!d.one_operand_p) | |
11690 | d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); | |
11691 | ||
11692 | start_sequence (); | |
11693 | ret = ia64_expand_vec_perm_const_1 (&d); | |
11694 | end_sequence (); | |
11695 | ||
11696 | return ret; | |
11697 | } | |
11698 | ||
11699 | void | |
11700 | ia64_expand_vec_setv2sf (rtx operands[3]) | |
11701 | { | |
11702 | struct expand_vec_perm_d d; | |
11703 | unsigned int which; | |
11704 | bool ok; | |
11705 | ||
11706 | d.target = operands[0]; | |
11707 | d.op0 = operands[0]; | |
11708 | d.op1 = gen_reg_rtx (V2SFmode); | |
11709 | d.vmode = V2SFmode; | |
11710 | d.nelt = 2; | |
11711 | d.one_operand_p = false; | |
11712 | d.testing_p = false; | |
11713 | ||
11714 | which = INTVAL (operands[2]); | |
11715 | gcc_assert (which <= 1); | |
11716 | d.perm[0] = 1 - which; | |
11717 | d.perm[1] = which + 2; | |
11718 | ||
11719 | emit_insn (gen_fpack (d.op1, operands[1], CONST0_RTX (SFmode))); | |
11720 | ||
11721 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11722 | gcc_assert (ok); | |
11723 | } | |
11724 | ||
11725 | void | |
11726 | ia64_expand_vec_perm_even_odd (rtx target, rtx op0, rtx op1, int odd) | |
11727 | { | |
11728 | struct expand_vec_perm_d d; | |
11729 | enum machine_mode vmode = GET_MODE (target); | |
11730 | unsigned int i, nelt = GET_MODE_NUNITS (vmode); | |
11731 | bool ok; | |
11732 | ||
11733 | d.target = target; | |
11734 | d.op0 = op0; | |
11735 | d.op1 = op1; | |
11736 | d.vmode = vmode; | |
11737 | d.nelt = nelt; | |
11738 | d.one_operand_p = false; | |
11739 | d.testing_p = false; | |
11740 | ||
11741 | for (i = 0; i < nelt; ++i) | |
11742 | d.perm[i] = i * 2 + odd; | |
11743 | ||
11744 | ok = ia64_expand_vec_perm_const_1 (&d); | |
11745 | gcc_assert (ok); | |
11746 | } | |
f16d3f39 | 11747 | |
e2500fed | 11748 | #include "gt-ia64.h" |