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e65271be | 1 | /* Definitions of target machine GNU compiler. IA-64 version. |
00530a21 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
3bed2930 | 6 | This file is part of GCC. |
c65ebc55 | 7 | |
3bed2930 | 8 | GCC is free software; you can redistribute it and/or modify |
c65ebc55 JW |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
3bed2930 | 13 | GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
3bed2930 | 19 | along with GCC; see the file COPYING. If not, write to |
c65ebc55 JW |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
c65ebc55 JW |
23 | /* ??? Look at ABI group documents for list of preprocessor macros and |
24 | other features required for ABI compliance. */ | |
25 | ||
26 | /* ??? Functions containing a non-local goto target save many registers. Why? | |
27 | See for instance execute/920428-2.c. */ | |
28 | ||
c65ebc55 JW |
29 | /* ??? Add support for short data/bss sections. */ |
30 | ||
31 | \f | |
32 | /* Run-time target specifications */ | |
33 | ||
57016b47 SE |
34 | /* Target CPU builtins. */ |
35 | #define TARGET_CPU_CPP_BUILTINS() \ | |
36 | do { \ | |
37 | builtin_assert("cpu=ia64"); \ | |
38 | builtin_assert("machine=ia64"); \ | |
39 | builtin_define("__ia64"); \ | |
40 | builtin_define("__ia64__"); \ | |
41 | builtin_define("__itanium__"); \ | |
57016b47 SE |
42 | if (TARGET_BIG_ENDIAN) \ |
43 | builtin_define("__BIG_ENDIAN__"); \ | |
44 | } while (0) | |
45 | ||
5b8fcab6 | 46 | #define EXTRA_SPECS \ |
5b8fcab6 DB |
47 | { "asm_extra", ASM_EXTRA_SPEC }, |
48 | ||
243a7070 | 49 | #define CC1_SPEC "%(cc1_cpu) " |
c65ebc55 | 50 | |
5b8fcab6 DB |
51 | #define ASM_EXTRA_SPEC "" |
52 | ||
5b8fcab6 | 53 | |
c65ebc55 JW |
54 | /* This declaration should be present. */ |
55 | extern int target_flags; | |
56 | ||
57 | /* This series of macros is to allow compiler command arguments to enable or | |
58 | disable the use of optional features of the target machine. */ | |
59 | ||
60 | #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */ | |
61 | ||
62 | #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */ | |
63 | ||
64 | #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */ | |
65 | ||
66 | #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */ | |
67 | ||
68 | #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */ | |
69 | ||
ed168e45 | 70 | #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */ |
c65ebc55 | 71 | |
099dde21 | 72 | #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */ |
c65ebc55 | 73 | |
099dde21 | 74 | #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */ |
c65ebc55 | 75 | |
099dde21 | 76 | #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */ |
59da9a7d | 77 | |
099dde21 BS |
78 | #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */ |
79 | ||
80 | #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */ | |
59da9a7d | 81 | |
dcffbade | 82 | #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */ |
655f2eb9 | 83 | |
dcffbade SE |
84 | #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */ |
85 | ||
86 | #define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */ | |
87 | ||
88 | #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */ | |
655f2eb9 | 89 | |
c65ebc55 JW |
90 | #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */ |
91 | ||
30028c85 VM |
92 | #define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */ |
93 | ||
c65ebc55 JW |
94 | #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) |
95 | ||
96 | #define TARGET_GNU_AS (target_flags & MASK_GNU_AS) | |
97 | ||
98 | #define TARGET_GNU_LD (target_flags & MASK_GNU_LD) | |
99 | ||
100 | #define TARGET_NO_PIC (target_flags & MASK_NO_PIC) | |
101 | ||
102 | #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP) | |
103 | ||
6dd12198 SE |
104 | #define TARGET_ILP32 (target_flags & MASK_ILP32) |
105 | ||
099dde21 BS |
106 | #define TARGET_B_STEP (target_flags & MASK_B_STEP) |
107 | ||
c65ebc55 JW |
108 | #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES) |
109 | ||
110 | #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA) | |
111 | ||
59da9a7d JW |
112 | #define TARGET_CONST_GP (target_flags & MASK_CONST_GP) |
113 | ||
114 | #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC) | |
115 | ||
dcffbade SE |
116 | #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT) |
117 | ||
118 | #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR) | |
119 | ||
120 | #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT) | |
121 | ||
122 | #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR) | |
655f2eb9 | 123 | |
dcffbade SE |
124 | #define TARGET_INLINE_FLOAT_DIV \ |
125 | (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR)) | |
655f2eb9 | 126 | |
dcffbade SE |
127 | #define TARGET_INLINE_INT_DIV \ |
128 | (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR)) | |
655f2eb9 | 129 | |
c65ebc55 JW |
130 | #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM) |
131 | ||
7b6e506e RH |
132 | extern int ia64_tls_size; |
133 | #define TARGET_TLS14 (ia64_tls_size == 14) | |
134 | #define TARGET_TLS22 (ia64_tls_size == 22) | |
135 | #define TARGET_TLS64 (ia64_tls_size == 64) | |
30028c85 | 136 | #define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS) |
7b6e506e | 137 | |
686f3bf0 SE |
138 | #define TARGET_HPUX_LD 0 |
139 | ||
568d661d RH |
140 | #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS |
141 | #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 | |
142 | #endif | |
143 | ||
c65ebc55 JW |
144 | /* This macro defines names of command options to set and clear bits in |
145 | `target_flags'. Its definition is an initializer with a subgrouping for | |
146 | each command option. */ | |
147 | ||
59da9a7d | 148 | #define TARGET_SWITCHES \ |
c65ebc55 JW |
149 | { \ |
150 | { "big-endian", MASK_BIG_ENDIAN, \ | |
047142d3 | 151 | N_("Generate big endian code") }, \ |
c65ebc55 | 152 | { "little-endian", -MASK_BIG_ENDIAN, \ |
047142d3 | 153 | N_("Generate little endian code") }, \ |
c65ebc55 | 154 | { "gnu-as", MASK_GNU_AS, \ |
047142d3 | 155 | N_("Generate code for GNU as") }, \ |
c65ebc55 | 156 | { "no-gnu-as", -MASK_GNU_AS, \ |
047142d3 | 157 | N_("Generate code for Intel as") }, \ |
c65ebc55 | 158 | { "gnu-ld", MASK_GNU_LD, \ |
047142d3 | 159 | N_("Generate code for GNU ld") }, \ |
c65ebc55 | 160 | { "no-gnu-ld", -MASK_GNU_LD, \ |
047142d3 | 161 | N_("Generate code for Intel ld") }, \ |
c65ebc55 | 162 | { "no-pic", MASK_NO_PIC, \ |
047142d3 | 163 | N_("Generate code without GP reg") }, \ |
c65ebc55 | 164 | { "volatile-asm-stop", MASK_VOL_ASM_STOP, \ |
047142d3 | 165 | N_("Emit stop bits before and after volatile extended asms") }, \ |
c65ebc55 | 166 | { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \ |
047142d3 | 167 | N_("Don't emit stop bits before and after volatile extended asms") }, \ |
099dde21 BS |
168 | { "b-step", MASK_B_STEP, \ |
169 | N_("Emit code for Itanium (TM) processor B step")}, \ | |
c65ebc55 | 170 | { "register-names", MASK_REG_NAMES, \ |
047142d3 | 171 | N_("Use in/loc/out register names")}, \ |
c65ebc55 | 172 | { "no-sdata", MASK_NO_SDATA, \ |
047142d3 | 173 | N_("Disable use of sdata/scommon/sbss")}, \ |
c65ebc55 | 174 | { "sdata", -MASK_NO_SDATA, \ |
047142d3 | 175 | N_("Enable use of sdata/scommon/sbss")}, \ |
59da9a7d | 176 | { "constant-gp", MASK_CONST_GP, \ |
047142d3 | 177 | N_("gp is constant (but save/restore gp on indirect calls)") }, \ |
59da9a7d | 178 | { "auto-pic", MASK_AUTO_PIC, \ |
047142d3 | 179 | N_("Generate self-relocatable code") }, \ |
dcffbade SE |
180 | { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \ |
181 | N_("Generate inline floating point division, optimize for latency") },\ | |
182 | { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \ | |
183 | N_("Generate inline floating point division, optimize for throughput") },\ | |
184 | { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \ | |
185 | N_("Generate inline integer division, optimize for latency") }, \ | |
186 | { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \ | |
187 | N_("Generate inline integer division, optimize for throughput") },\ | |
c65ebc55 | 188 | { "dwarf2-asm", MASK_DWARF2_ASM, \ |
047142d3 | 189 | N_("Enable Dwarf 2 line debug info via GNU as")}, \ |
c65ebc55 | 190 | { "no-dwarf2-asm", -MASK_DWARF2_ASM, \ |
047142d3 | 191 | N_("Disable Dwarf 2 line debug info via GNU as")}, \ |
30028c85 VM |
192 | { "early-stop-bits", MASK_EARLY_STOP_BITS, \ |
193 | N_("Enable earlier placing stop bits for better scheduling")}, \ | |
194 | { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \ | |
195 | N_("Disable earlier placing stop bits")}, \ | |
6dd12198 | 196 | SUBTARGET_SWITCHES \ |
c65ebc55 JW |
197 | { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \ |
198 | NULL } \ | |
199 | } | |
200 | ||
201 | /* Default target_flags if no switches are specified */ | |
202 | ||
203 | #ifndef TARGET_DEFAULT | |
204 | #define TARGET_DEFAULT MASK_DWARF2_ASM | |
205 | #endif | |
206 | ||
207 | #ifndef TARGET_CPU_DEFAULT | |
208 | #define TARGET_CPU_DEFAULT 0 | |
209 | #endif | |
210 | ||
6dd12198 SE |
211 | #ifndef SUBTARGET_SWITCHES |
212 | #define SUBTARGET_SWITCHES | |
213 | #endif | |
214 | ||
c65ebc55 JW |
215 | /* This macro is similar to `TARGET_SWITCHES' but defines names of command |
216 | options that have values. Its definition is an initializer with a | |
217 | subgrouping for each command option. */ | |
218 | ||
219 | extern const char *ia64_fixed_range_string; | |
7b6e506e | 220 | extern const char *ia64_tls_size_string; |
30028c85 VM |
221 | |
222 | /* Which processor to schedule for. The cpu attribute defines a list | |
223 | that mirrors this list, so changes to i64.md must be made at the | |
224 | same time. */ | |
225 | ||
226 | enum processor_type | |
227 | { | |
228 | PROCESSOR_ITANIUM, /* Original Itanium. */ | |
229 | PROCESSOR_ITANIUM2, | |
230 | PROCESSOR_max | |
231 | }; | |
232 | ||
233 | extern enum processor_type ia64_tune; | |
234 | ||
235 | extern const char *ia64_tune_string; | |
236 | ||
c65ebc55 JW |
237 | #define TARGET_OPTIONS \ |
238 | { \ | |
239 | { "fixed-range=", &ia64_fixed_range_string, \ | |
c409ea0d | 240 | N_("Specify range of registers to make fixed"), 0}, \ |
7b6e506e | 241 | { "tls-size=", &ia64_tls_size_string, \ |
c409ea0d | 242 | N_("Specify bit size of immediate TLS offsets"), 0}, \ |
30028c85 | 243 | { "tune=", &ia64_tune_string, \ |
c409ea0d | 244 | N_("Schedule code for given CPU"), 0}, \ |
c65ebc55 JW |
245 | } |
246 | ||
c65ebc55 JW |
247 | /* Sometimes certain combinations of command options do not make sense on a |
248 | particular target machine. You can define a macro `OVERRIDE_OPTIONS' to | |
249 | take account of this. This macro, if defined, is executed once just after | |
250 | all the command options have been parsed. */ | |
251 | ||
252 | #define OVERRIDE_OPTIONS ia64_override_options () | |
253 | ||
254 | /* Some machines may desire to change what optimizations are performed for | |
255 | various optimization levels. This macro, if defined, is executed once just | |
256 | after the optimization level is determined and before the remainder of the | |
257 | command options have been parsed. Values set in this macro are used as the | |
258 | default values for the other command line options. */ | |
259 | ||
260 | /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */ | |
c65ebc55 JW |
261 | \f |
262 | /* Driver configuration */ | |
263 | ||
7ec022b2 KC |
264 | /* A C string constant that tells the GCC driver program options to pass to |
265 | `cc1'. It can also specify how to translate options you give to GCC into | |
266 | options for GCC to pass to the `cc1'. */ | |
c65ebc55 | 267 | |
ad5042df JJ |
268 | #undef CC1_SPEC |
269 | #define CC1_SPEC "%{G*}" | |
c65ebc55 | 270 | |
7ec022b2 KC |
271 | /* A C string constant that tells the GCC driver program options to pass to |
272 | `cc1plus'. It can also specify how to translate options you give to GCC | |
273 | into options for GCC to pass to the `cc1plus'. */ | |
c65ebc55 JW |
274 | |
275 | /* #define CC1PLUS_SPEC "" */ | |
c65ebc55 JW |
276 | \f |
277 | /* Storage Layout */ | |
278 | ||
279 | /* Define this macro to have the value 1 if the most significant bit in a byte | |
280 | has the lowest number; otherwise define it to have the value zero. */ | |
281 | ||
282 | #define BITS_BIG_ENDIAN 0 | |
283 | ||
c65ebc55 JW |
284 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
285 | ||
286 | /* Define this macro to have the value 1 if, in a multiword object, the most | |
287 | significant word has the lowest number. */ | |
288 | ||
289 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
290 | ||
c65ebc55 JW |
291 | #if defined(__BIG_ENDIAN__) |
292 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
293 | #else | |
294 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
295 | #endif | |
296 | ||
c65ebc55 JW |
297 | #define UNITS_PER_WORD 8 |
298 | ||
6dd12198 | 299 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) |
c65ebc55 | 300 | |
6dd12198 SE |
301 | /* A C expression whose value is zero if pointers that need to be extended |
302 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if | |
5bdc5878 | 303 | they are zero-extended and negative one if there is a ptr_extend operation. |
c65ebc55 JW |
304 | |
305 | You need not define this macro if the `POINTER_SIZE' is equal to the width | |
306 | of `Pmode'. */ | |
6dd12198 | 307 | /* Need this for 32 bit pointers, see hpux.h for setting it. */ |
c65ebc55 JW |
308 | /* #define POINTERS_EXTEND_UNSIGNED */ |
309 | ||
310 | /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and | |
311 | which has the specified mode and signedness is to be stored in a register. | |
312 | This macro is only called when TYPE is a scalar type. */ | |
c65ebc55 JW |
313 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
314 | do \ | |
315 | { \ | |
316 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
dcf6e674 RH |
317 | && GET_MODE_SIZE (MODE) < 4) \ |
318 | (MODE) = SImode; \ | |
c65ebc55 JW |
319 | } \ |
320 | while (0) | |
321 | ||
c65ebc55 JW |
322 | /* ??? ABI doesn't allow us to define this. */ |
323 | /* #define PROMOTE_FUNCTION_ARGS */ | |
324 | ||
c65ebc55 JW |
325 | /* ??? ABI doesn't allow us to define this. */ |
326 | /* #define PROMOTE_FUNCTION_RETURN */ | |
327 | ||
c65ebc55 JW |
328 | #define PARM_BOUNDARY 64 |
329 | ||
330 | /* Define this macro if you wish to preserve a certain alignment for the stack | |
331 | pointer. The definition is a C expression for the desired alignment | |
332 | (measured in bits). */ | |
333 | ||
334 | #define STACK_BOUNDARY 128 | |
335 | ||
336 | /* Align frames on double word boundaries */ | |
337 | #ifndef IA64_STACK_ALIGN | |
338 | #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) | |
339 | #endif | |
340 | ||
c65ebc55 JW |
341 | #define FUNCTION_BOUNDARY 128 |
342 | ||
c65ebc55 JW |
343 | /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word |
344 | 128 bit integers all require 128 bit alignment. */ | |
345 | #define BIGGEST_ALIGNMENT 128 | |
346 | ||
347 | /* If defined, a C expression to compute the alignment for a static variable. | |
348 | TYPE is the data type, and ALIGN is the alignment that the object | |
349 | would ordinarily have. The value of this macro is used instead of that | |
350 | alignment to align the object. */ | |
351 | ||
352 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
353 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
354 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
355 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
356 | ||
357 | /* If defined, a C expression to compute the alignment given to a constant that | |
358 | is being placed in memory. CONSTANT is the constant and ALIGN is the | |
359 | alignment that the object would ordinarily have. The value of this macro is | |
360 | used instead of that alignment to align the object. */ | |
361 | ||
362 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
363 | (TREE_CODE (EXP) == STRING_CST \ | |
364 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
365 | ||
c65ebc55 JW |
366 | #define STRICT_ALIGNMENT 1 |
367 | ||
368 | /* Define this if you wish to imitate the way many other C compilers handle | |
369 | alignment of bitfields and the structures that contain them. | |
43a88a8c | 370 | The behavior is that the type written for a bit-field (`int', `short', or |
c65ebc55 JW |
371 | other integer type) imposes an alignment for the entire structure, as if the |
372 | structure really did contain an ordinary field of that type. In addition, | |
43a88a8c | 373 | the bit-field is placed within the structure so that it would fit within such |
c65ebc55 JW |
374 | a field, not crossing a boundary for it. */ |
375 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
376 | ||
c65ebc55 JW |
377 | /* An integer expression for the size in bits of the largest integer machine |
378 | mode that should actually be used. */ | |
379 | ||
380 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
381 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
382 | ||
67231816 | 383 | /* By default, the C++ compiler will use function addresses in the |
9cd10576 | 384 | vtable entries. Setting this nonzero tells the compiler to use |
67231816 | 385 | function descriptors instead. The value of this macro says how |
5b8fcab6 | 386 | many words wide the descriptor is (normally 2). It is assumed |
67231816 | 387 | that the address of a function descriptor may be treated as a |
a6f5e048 RH |
388 | pointer to a function. |
389 | ||
390 | For reasons known only to HP, the vtable entries (as opposed to | |
391 | normal function descriptors) are 16 bytes wide in 32-bit mode as | |
392 | well, even though the 3rd and 4th words are unused. */ | |
393 | #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) | |
394 | ||
395 | /* Due to silliness in the HPUX linker, vtable entries must be | |
396 | 8-byte aligned even in 32-bit mode. Rather than create multiple | |
397 | ABIs, force this restriction on everyone else too. */ | |
398 | #define TARGET_VTABLE_ENTRY_ALIGN 64 | |
399 | ||
400 | /* Due to the above, we need extra padding for the data entries below 0 | |
401 | to retain the alignment of the descriptors. */ | |
402 | #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) | |
c65ebc55 JW |
403 | \f |
404 | /* Layout of Source Language Data Types */ | |
405 | ||
c65ebc55 JW |
406 | #define INT_TYPE_SIZE 32 |
407 | ||
c65ebc55 JW |
408 | #define SHORT_TYPE_SIZE 16 |
409 | ||
6dd12198 | 410 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
c65ebc55 | 411 | |
6dd12198 | 412 | #define MAX_LONG_TYPE_SIZE 64 |
c65ebc55 | 413 | |
c65ebc55 JW |
414 | #define LONG_LONG_TYPE_SIZE 64 |
415 | ||
c65ebc55 JW |
416 | #define FLOAT_TYPE_SIZE 32 |
417 | ||
c65ebc55 JW |
418 | #define DOUBLE_TYPE_SIZE 64 |
419 | ||
3f622353 RH |
420 | #define LONG_DOUBLE_TYPE_SIZE 128 |
421 | ||
3dc85dfb RH |
422 | /* By default we use the 80-bit Intel extended float format packaged |
423 | in a 128-bit entity. */ | |
23c108af | 424 | #define INTEL_EXTENDED_IEEE_FORMAT 1 |
c65ebc55 | 425 | |
c65ebc55 JW |
426 | #define DEFAULT_SIGNED_CHAR 1 |
427 | ||
428 | /* A C expression for a string describing the name of the data type to use for | |
429 | size values. The typedef name `size_t' is defined using the contents of the | |
430 | string. */ | |
431 | /* ??? Needs to be defined for P64 code. */ | |
432 | /* #define SIZE_TYPE */ | |
433 | ||
434 | /* A C expression for a string describing the name of the data type to use for | |
435 | the result of subtracting two pointers. The typedef name `ptrdiff_t' is | |
436 | defined using the contents of the string. See `SIZE_TYPE' above for more | |
437 | information. */ | |
438 | /* ??? Needs to be defined for P64 code. */ | |
439 | /* #define PTRDIFF_TYPE */ | |
440 | ||
441 | /* A C expression for a string describing the name of the data type to use for | |
442 | wide characters. The typedef name `wchar_t' is defined using the contents | |
443 | of the string. See `SIZE_TYPE' above for more information. */ | |
444 | /* #define WCHAR_TYPE */ | |
445 | ||
446 | /* A C expression for the size in bits of the data type for wide characters. | |
447 | This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ | |
448 | /* #define WCHAR_TYPE_SIZE */ | |
449 | ||
c65ebc55 JW |
450 | \f |
451 | /* Register Basics */ | |
452 | ||
5b8fcab6 | 453 | /* Number of hardware registers known to the compiler. |
5527bf14 RH |
454 | We have 128 general registers, 128 floating point registers, |
455 | 64 predicate registers, 8 branch registers, one frame pointer, | |
456 | and several "application" registers. */ | |
c65ebc55 | 457 | |
af1e5518 | 458 | #define FIRST_PSEUDO_REGISTER 334 |
c65ebc55 JW |
459 | |
460 | /* Ranges for the various kinds of registers. */ | |
3b572406 RH |
461 | #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) |
462 | #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) | |
c65ebc55 JW |
463 | #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) |
464 | #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) | |
465 | #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) | |
466 | #define GENERAL_REGNO_P(REGNO) \ | |
af1e5518 | 467 | (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) |
c65ebc55 JW |
468 | |
469 | #define GR_REG(REGNO) ((REGNO) + 0) | |
470 | #define FR_REG(REGNO) ((REGNO) + 128) | |
471 | #define PR_REG(REGNO) ((REGNO) + 256) | |
472 | #define BR_REG(REGNO) ((REGNO) + 320) | |
473 | #define OUT_REG(REGNO) ((REGNO) + 120) | |
474 | #define IN_REG(REGNO) ((REGNO) + 112) | |
475 | #define LOC_REG(REGNO) ((REGNO) + 32) | |
476 | ||
af1e5518 RH |
477 | #define AR_CCV_REGNUM 329 |
478 | #define AR_UNAT_REGNUM 330 | |
479 | #define AR_PFS_REGNUM 331 | |
480 | #define AR_LC_REGNUM 332 | |
481 | #define AR_EC_REGNUM 333 | |
5527bf14 | 482 | |
c65ebc55 JW |
483 | #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) |
484 | #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) | |
485 | #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) | |
486 | ||
97e242b0 RH |
487 | #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ |
488 | || (REGNO) == AR_UNAT_REGNUM) | |
489 | #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ | |
5527bf14 RH |
490 | && (REGNO) < FIRST_PSEUDO_REGISTER) |
491 | #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ | |
492 | && (REGNO) < FIRST_PSEUDO_REGISTER) | |
493 | ||
494 | ||
c65ebc55 JW |
495 | /* ??? Don't really need two sets of macros. I like this one better because |
496 | it is less typing. */ | |
497 | #define R_GR(REGNO) GR_REG (REGNO) | |
498 | #define R_FR(REGNO) FR_REG (REGNO) | |
499 | #define R_PR(REGNO) PR_REG (REGNO) | |
500 | #define R_BR(REGNO) BR_REG (REGNO) | |
501 | ||
502 | /* An initializer that says which registers are used for fixed purposes all | |
503 | throughout the compiled code and are therefore not available for general | |
504 | allocation. | |
505 | ||
506 | r0: constant 0 | |
507 | r1: global pointer (gp) | |
508 | r12: stack pointer (sp) | |
509 | r13: thread pointer (tp) | |
510 | f0: constant 0.0 | |
511 | f1: constant 1.0 | |
512 | p0: constant true | |
5b8fcab6 | 513 | fp: eliminable frame pointer */ |
c65ebc55 | 514 | |
1ff5b671 JW |
515 | /* The last 16 stacked regs are reserved for the 8 input and 8 output |
516 | registers. */ | |
c65ebc55 | 517 | |
c65ebc55 JW |
518 | #define FIXED_REGISTERS \ |
519 | { /* General registers. */ \ | |
520 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ | |
521 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
522 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
523 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
524 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
525 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
97e242b0 | 526 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1ff5b671 | 527 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
c65ebc55 JW |
528 | /* Floating-point registers. */ \ |
529 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
530 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
531 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
532 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
533 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
534 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
535 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
536 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
537 | /* Predicate registers. */ \ | |
538 | 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
539 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
540 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
541 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
542 | /* Branch registers. */ \ | |
543 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
af1e5518 RH |
544 | /*FP CCV UNAT PFS LC EC */ \ |
545 | 1, 1, 1, 1, 0, 1 \ | |
c65ebc55 JW |
546 | } |
547 | ||
5527bf14 RH |
548 | /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered |
549 | (in general) by function calls as well as for fixed registers. This | |
550 | macro therefore identifies the registers that are not available for | |
551 | general allocation of values that must live across function calls. */ | |
c65ebc55 | 552 | |
c65ebc55 JW |
553 | #define CALL_USED_REGISTERS \ |
554 | { /* General registers. */ \ | |
555 | 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
556 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
557 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
558 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
559 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
560 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
97e242b0 | 561 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1ff5b671 | 562 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ |
c65ebc55 JW |
563 | /* Floating-point registers. */ \ |
564 | 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
565 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
566 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
567 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
568 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
569 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
570 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
571 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
572 | /* Predicate registers. */ \ | |
573 | 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
574 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
575 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
576 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
577 | /* Branch registers. */ \ | |
578 | 1, 0, 0, 0, 0, 0, 1, 1, \ | |
af1e5518 RH |
579 | /*FP CCV UNAT PFS LC EC */ \ |
580 | 1, 1, 1, 1, 0, 1 \ | |
c65ebc55 JW |
581 | } |
582 | ||
5b8fcab6 | 583 | /* Like `CALL_USED_REGISTERS' but used to overcome a historical |
fc1296b7 | 584 | problem which makes CALL_USED_REGISTERS *always* include |
5b8fcab6 | 585 | all the FIXED_REGISTERS. Until this problem has been |
fc1296b7 | 586 | resolved this macro can be used to overcome this situation. |
5b8fcab6 | 587 | In particular, block_propagate() requires this list |
9e4f94de | 588 | be accurate, or we can remove registers which should be live. |
6ca3c22f | 589 | This macro is used in regs_invalidated_by_call. */ |
fc1296b7 AM |
590 | |
591 | #define CALL_REALLY_USED_REGISTERS \ | |
592 | { /* General registers. */ \ | |
593 | 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \ | |
594 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
595 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
596 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
597 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
598 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
599 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
600 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
601 | /* Floating-point registers. */ \ | |
602 | 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
603 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
604 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
605 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
606 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
607 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
608 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
609 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
610 | /* Predicate registers. */ \ | |
611 | 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
612 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
613 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
614 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
615 | /* Branch registers. */ \ | |
616 | 1, 0, 0, 0, 0, 0, 1, 1, \ | |
af1e5518 RH |
617 | /*FP CCV UNAT PFS LC EC */ \ |
618 | 0, 1, 0, 1, 0, 0 \ | |
fc1296b7 AM |
619 | } |
620 | ||
621 | ||
c65ebc55 JW |
622 | /* Define this macro if the target machine has register windows. This C |
623 | expression returns the register number as seen by the called function | |
624 | corresponding to the register number OUT as seen by the calling function. | |
625 | Return OUT if register number OUT is not an outbound register. */ | |
626 | ||
627 | #define INCOMING_REGNO(OUT) \ | |
628 | ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) | |
629 | ||
630 | /* Define this macro if the target machine has register windows. This C | |
631 | expression returns the register number as seen by the calling function | |
632 | corresponding to the register number IN as seen by the called function. | |
633 | Return IN if register number IN is not an inbound register. */ | |
634 | ||
635 | #define OUTGOING_REGNO(IN) \ | |
636 | ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) | |
637 | ||
2a3e384f RH |
638 | /* Define this macro if the target machine has register windows. This |
639 | C expression returns true if the register is call-saved but is in the | |
640 | register window. */ | |
641 | ||
642 | #define LOCAL_REGNO(REGNO) \ | |
643 | (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) | |
97e242b0 | 644 | |
97e242b0 RH |
645 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
646 | return the mode to be used for the comparison. Must be defined if | |
647 | EXTRA_CC_MODES is defined. */ | |
648 | ||
649 | #define SELECT_CC_MODE(OP,X,Y) CCmode | |
c65ebc55 JW |
650 | \f |
651 | /* Order of allocation of registers */ | |
652 | ||
653 | /* If defined, an initializer for a vector of integers, containing the numbers | |
7ec022b2 | 654 | of hard registers in the order in which GCC should prefer to use them |
c65ebc55 JW |
655 | (from most preferred to least). |
656 | ||
657 | If this macro is not defined, registers are used lowest numbered first (all | |
658 | else being equal). | |
659 | ||
660 | One use of this macro is on machines where the highest numbered registers | |
661 | must always be saved and the save-multiple-registers instruction supports | |
662 | only sequences of consecutive registers. On such machines, define | |
663 | `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered | |
664 | allocatable register first. */ | |
665 | ||
666 | /* ??? Should the GR return value registers come before or after the rest | |
667 | of the caller-save GRs? */ | |
668 | ||
97e242b0 | 669 | #define REG_ALLOC_ORDER \ |
c65ebc55 JW |
670 | { \ |
671 | /* Caller-saved general registers. */ \ | |
97e242b0 RH |
672 | R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ |
673 | R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ | |
674 | R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ | |
c65ebc55 | 675 | R_GR (30), R_GR (31), \ |
1ff5b671 JW |
676 | /* Output registers. */ \ |
677 | R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ | |
97e242b0 | 678 | R_GR (126), R_GR (127), \ |
c65ebc55 | 679 | /* Caller-saved general registers, also used for return values. */ \ |
97e242b0 | 680 | R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ |
c65ebc55 JW |
681 | /* addl caller-saved general registers. */ \ |
682 | R_GR (2), R_GR (3), \ | |
683 | /* Caller-saved FP registers. */ \ | |
684 | R_FR (6), R_FR (7), \ | |
685 | /* Caller-saved FP registers, used for parameters and return values. */ \ | |
97e242b0 RH |
686 | R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ |
687 | R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ | |
c65ebc55 | 688 | /* Rotating caller-saved FP registers. */ \ |
97e242b0 RH |
689 | R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ |
690 | R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ | |
691 | R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ | |
692 | R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ | |
693 | R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ | |
694 | R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ | |
695 | R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ | |
696 | R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ | |
697 | R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ | |
698 | R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ | |
699 | R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ | |
700 | R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ | |
c65ebc55 JW |
701 | R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ |
702 | R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ | |
703 | R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ | |
704 | R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ | |
97e242b0 | 705 | R_FR (126), R_FR (127), \ |
c65ebc55 | 706 | /* Caller-saved predicate registers. */ \ |
97e242b0 | 707 | R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ |
c65ebc55 JW |
708 | R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ |
709 | /* Rotating caller-saved predicate registers. */ \ | |
97e242b0 RH |
710 | R_PR (16), R_PR (17), \ |
711 | R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ | |
712 | R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ | |
713 | R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ | |
714 | R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ | |
715 | R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ | |
716 | R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ | |
717 | R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ | |
718 | R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ | |
c65ebc55 JW |
719 | /* Caller-saved branch registers. */ \ |
720 | R_BR (6), R_BR (7), \ | |
721 | \ | |
722 | /* Stacked callee-saved general registers. */ \ | |
97e242b0 RH |
723 | R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ |
724 | R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ | |
725 | R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ | |
726 | R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ | |
727 | R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ | |
728 | R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ | |
729 | R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ | |
730 | R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ | |
731 | R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ | |
732 | R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ | |
733 | R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ | |
734 | R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ | |
c65ebc55 JW |
735 | R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ |
736 | R_GR (108), \ | |
1ff5b671 JW |
737 | /* Input registers. */ \ |
738 | R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ | |
739 | R_GR (118), R_GR (119), \ | |
c65ebc55 JW |
740 | /* Callee-saved general registers. */ \ |
741 | R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ | |
742 | /* Callee-saved FP registers. */ \ | |
97e242b0 RH |
743 | R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ |
744 | R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ | |
745 | R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ | |
c65ebc55 JW |
746 | R_FR (30), R_FR (31), \ |
747 | /* Callee-saved predicate registers. */ \ | |
97e242b0 | 748 | R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ |
c65ebc55 JW |
749 | /* Callee-saved branch registers. */ \ |
750 | R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ | |
751 | \ | |
752 | /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ | |
753 | R_GR (109), R_GR (110), R_GR (111), \ | |
c65ebc55 JW |
754 | \ |
755 | /* Special general registers. */ \ | |
97e242b0 | 756 | R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ |
c65ebc55 JW |
757 | /* Special FP registers. */ \ |
758 | R_FR (0), R_FR (1), \ | |
759 | /* Special predicate registers. */ \ | |
760 | R_PR (0), \ | |
761 | /* Special branch registers. */ \ | |
762 | R_BR (0), \ | |
5527bf14 | 763 | /* Other fixed registers. */ \ |
af1e5518 | 764 | FRAME_POINTER_REGNUM, \ |
97e242b0 RH |
765 | AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ |
766 | AR_EC_REGNUM \ | |
c65ebc55 | 767 | } |
c65ebc55 JW |
768 | \f |
769 | /* How Values Fit in Registers */ | |
770 | ||
771 | /* A C expression for the number of consecutive hard registers, starting at | |
772 | register number REGNO, required to hold a value of mode MODE. */ | |
773 | ||
f2f90c63 | 774 | /* ??? We say that BImode PR values require two registers. This allows us to |
97e242b0 RH |
775 | easily store the normal and inverted values. We use CCImode to indicate |
776 | a single predicate register. */ | |
c65ebc55 | 777 | |
97e242b0 RH |
778 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
779 | ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ | |
f2f90c63 | 780 | : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ |
97e242b0 | 781 | : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ |
23c108af | 782 | : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \ |
c65ebc55 JW |
783 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
784 | ||
785 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
786 | MODE in hard register number REGNO (or in several registers starting with | |
787 | that one). */ | |
0ea1e106 | 788 | |
f2f90c63 RH |
789 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
790 | (FR_REGNO_P (REGNO) ? \ | |
23c108af SE |
791 | GET_MODE_CLASS (MODE) != MODE_CC && \ |
792 | (MODE) != TImode && \ | |
793 | (MODE) != BImode && \ | |
794 | ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \ | |
f2f90c63 RH |
795 | : PR_REGNO_P (REGNO) ? \ |
796 | (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ | |
797 | : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \ | |
798 | : AR_REGNO_P (REGNO) ? (MODE) == DImode \ | |
799 | : BR_REGNO_P (REGNO) ? (MODE) == DImode \ | |
3f622353 | 800 | : 0) |
c65ebc55 JW |
801 | |
802 | /* A C expression that is nonzero if it is desirable to choose register | |
803 | allocation so as to avoid move instructions between a value of mode MODE1 | |
804 | and a value of mode MODE2. | |
805 | ||
806 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are | |
807 | ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be | |
808 | zero. */ | |
ad06f2e3 | 809 | /* Don't tie integer and FP modes, as that causes us to get integer registers |
3f622353 RH |
810 | allocated for FP instructions. TFmode only supported in FP registers so |
811 | we can't tie it with any other modes. */ | |
f2f90c63 RH |
812 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
813 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
814 | && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \ | |
815 | && (((MODE1) == BImode) == ((MODE2) == BImode))) | |
c65ebc55 JW |
816 | \f |
817 | /* Handling Leaf Functions */ | |
818 | ||
819 | /* A C initializer for a vector, indexed by hard register number, which | |
820 | contains 1 for a register that is allowable in a candidate for leaf function | |
821 | treatment. */ | |
822 | /* ??? This might be useful. */ | |
823 | /* #define LEAF_REGISTERS */ | |
824 | ||
825 | /* A C expression whose value is the register number to which REGNO should be | |
826 | renumbered, when a function is treated as a leaf function. */ | |
827 | /* ??? This might be useful. */ | |
828 | /* #define LEAF_REG_REMAP(REGNO) */ | |
829 | ||
830 | \f | |
831 | /* Register Classes */ | |
832 | ||
833 | /* An enumeral type that must be defined with all the register class names as | |
834 | enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last | |
835 | register class, followed by one more enumeral value, `LIM_REG_CLASSES', | |
836 | which is not a register class but rather tells how many classes there | |
837 | are. */ | |
c65ebc55 JW |
838 | /* ??? When compiling without optimization, it is possible for the only use of |
839 | a pseudo to be a parameter load from the stack with a REG_EQUIV note. | |
840 | Regclass handles this case specially and does not assign any costs to the | |
841 | pseudo. The pseudo then ends up using the last class before ALL_REGS. | |
842 | Thus we must not let either PR_REGS or BR_REGS be the last class. The | |
843 | testcase for this is gcc.c-torture/execute/va-arg-7.c. */ | |
844 | enum reg_class | |
845 | { | |
846 | NO_REGS, | |
847 | PR_REGS, | |
848 | BR_REGS, | |
7109d286 RH |
849 | AR_M_REGS, |
850 | AR_I_REGS, | |
c65ebc55 JW |
851 | ADDL_REGS, |
852 | GR_REGS, | |
c65ebc55 | 853 | FR_REGS, |
7109d286 | 854 | GR_AND_BR_REGS, |
c65ebc55 JW |
855 | GR_AND_FR_REGS, |
856 | ALL_REGS, | |
857 | LIM_REG_CLASSES | |
858 | }; | |
859 | ||
860 | #define GENERAL_REGS GR_REGS | |
861 | ||
862 | /* The number of distinct register classes. */ | |
863 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
864 | ||
865 | /* An initializer containing the names of the register classes as C string | |
866 | constants. These names are used in writing some of the debugging dumps. */ | |
867 | #define REG_CLASS_NAMES \ | |
7109d286 RH |
868 | { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ |
869 | "ADDL_REGS", "GR_REGS", "FR_REGS", \ | |
870 | "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } | |
c65ebc55 JW |
871 | |
872 | /* An initializer containing the contents of the register classes, as integers | |
873 | which are bit masks. The Nth integer specifies the contents of class N. | |
874 | The way the integer MASK is interpreted is that register R is in the class | |
875 | if `MASK & (1 << R)' is 1. */ | |
876 | #define REG_CLASS_CONTENTS \ | |
877 | { \ | |
878 | /* NO_REGS. */ \ | |
879 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
880 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 881 | 0x00000000, 0x00000000, 0x0000 }, \ |
c65ebc55 JW |
882 | /* PR_REGS. */ \ |
883 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
884 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 885 | 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ |
c65ebc55 JW |
886 | /* BR_REGS. */ \ |
887 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
888 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 889 | 0x00000000, 0x00000000, 0x00FF }, \ |
7109d286 RH |
890 | /* AR_M_REGS. */ \ |
891 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
892 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
af1e5518 | 893 | 0x00000000, 0x00000000, 0x0600 }, \ |
7109d286 RH |
894 | /* AR_I_REGS. */ \ |
895 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
896 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
af1e5518 | 897 | 0x00000000, 0x00000000, 0x3800 }, \ |
c65ebc55 JW |
898 | /* ADDL_REGS. */ \ |
899 | { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ | |
900 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 901 | 0x00000000, 0x00000000, 0x0000 }, \ |
c65ebc55 JW |
902 | /* GR_REGS. */ \ |
903 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
904 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
af1e5518 | 905 | 0x00000000, 0x00000000, 0x0100 }, \ |
c65ebc55 JW |
906 | /* FR_REGS. */ \ |
907 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
908 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
5527bf14 | 909 | 0x00000000, 0x00000000, 0x0000 }, \ |
7109d286 RH |
910 | /* GR_AND_BR_REGS. */ \ |
911 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
912 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
af1e5518 | 913 | 0x00000000, 0x00000000, 0x01FF }, \ |
c65ebc55 JW |
914 | /* GR_AND_FR_REGS. */ \ |
915 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
916 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
af1e5518 | 917 | 0x00000000, 0x00000000, 0x0100 }, \ |
c65ebc55 JW |
918 | /* ALL_REGS. */ \ |
919 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
920 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
af1e5518 | 921 | 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ |
c65ebc55 JW |
922 | } |
923 | ||
924 | /* A C expression whose value is a register class containing hard register | |
925 | REGNO. In general there is more than one such class; choose a class which | |
926 | is "minimal", meaning that no smaller class also contains the register. */ | |
927 | /* The NO_REGS case is primarily for the benefit of rws_access_reg, which | |
928 | may call here with private (invalid) register numbers, such as | |
929 | REG_VOLATILE. */ | |
930 | #define REGNO_REG_CLASS(REGNO) \ | |
931 | (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ | |
932 | : GENERAL_REGNO_P (REGNO) ? GR_REGS \ | |
13da91fd | 933 | : FR_REGNO_P (REGNO) ? FR_REGS \ |
c65ebc55 JW |
934 | : PR_REGNO_P (REGNO) ? PR_REGS \ |
935 | : BR_REGNO_P (REGNO) ? BR_REGS \ | |
97e242b0 RH |
936 | : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ |
937 | : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ | |
c65ebc55 JW |
938 | : NO_REGS) |
939 | ||
940 | /* A macro whose definition is the name of the class to which a valid base | |
941 | register must belong. A base register is one used in an address which is | |
942 | the register value plus a displacement. */ | |
943 | #define BASE_REG_CLASS GENERAL_REGS | |
944 | ||
945 | /* A macro whose definition is the name of the class to which a valid index | |
946 | register must belong. An index register is one used in an address where its | |
947 | value is either multiplied by a scale factor or added to another register | |
cf606f45 JW |
948 | (as well as added to a displacement). This is needed for POST_MODIFY. */ |
949 | #define INDEX_REG_CLASS GENERAL_REGS | |
c65ebc55 JW |
950 | |
951 | /* A C expression which defines the machine-dependent operand constraint | |
952 | letters for register classes. If CHAR is such a letter, the value should be | |
953 | the register class corresponding to it. Otherwise, the value should be | |
954 | `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS', | |
955 | will not be passed to this macro; you do not need to handle it. */ | |
956 | ||
957 | #define REG_CLASS_FROM_LETTER(CHAR) \ | |
13da91fd | 958 | ((CHAR) == 'f' ? FR_REGS \ |
c65ebc55 JW |
959 | : (CHAR) == 'a' ? ADDL_REGS \ |
960 | : (CHAR) == 'b' ? BR_REGS \ | |
961 | : (CHAR) == 'c' ? PR_REGS \ | |
5527bf14 RH |
962 | : (CHAR) == 'd' ? AR_M_REGS \ |
963 | : (CHAR) == 'e' ? AR_I_REGS \ | |
c65ebc55 JW |
964 | : NO_REGS) |
965 | ||
966 | /* A C expression which is nonzero if register number NUM is suitable for use | |
967 | as a base register in operand addresses. It may be either a suitable hard | |
968 | register or a pseudo register that has been allocated such a hard reg. */ | |
969 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
970 | (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) | |
971 | ||
972 | /* A C expression which is nonzero if register number NUM is suitable for use | |
973 | as an index register in operand addresses. It may be either a suitable hard | |
cf606f45 JW |
974 | register or a pseudo register that has been allocated such a hard reg. |
975 | This is needed for POST_MODIFY. */ | |
976 | #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) | |
c65ebc55 JW |
977 | |
978 | /* A C expression that places additional restrictions on the register class to | |
979 | use when it is necessary to copy value X into a register in class CLASS. | |
980 | The value is a register class; perhaps CLASS, or perhaps another, smaller | |
981 | class. */ | |
982 | ||
ffaff414 JW |
983 | /* Don't allow volatile mem reloads into floating point registers. This |
984 | is defined to force reload to choose the r/m case instead of the f/f case | |
f2f90c63 RH |
985 | when reloading (set (reg fX) (mem/v)). |
986 | ||
987 | Do not reload expressions into AR regs. */ | |
ffaff414 JW |
988 | |
989 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
f2f90c63 | 990 | (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \ |
036099eb | 991 | : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \ |
7109d286 RH |
992 | : GET_RTX_CLASS (GET_CODE (X)) != 'o' \ |
993 | && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \ | |
ffaff414 | 994 | : CLASS) |
c65ebc55 JW |
995 | |
996 | /* You should define this macro to indicate to the reload phase that it may | |
997 | need to allocate at least one register for a reload in addition to the | |
998 | register to contain the data. Specifically, if copying X to a register | |
999 | CLASS in MODE requires an intermediate register, you should define this | |
1000 | to return the largest register class all of whose registers can be used | |
1001 | as intermediate registers or scratch registers. */ | |
1002 | ||
1003 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
1004 | ia64_secondary_reload_class (CLASS, MODE, X) | |
1005 | ||
1006 | /* Certain machines have the property that some registers cannot be copied to | |
1007 | some other registers without using memory. Define this macro on those | |
9cd10576 | 1008 | machines to be a C expression that is nonzero if objects of mode M in |
c65ebc55 JW |
1009 | registers of CLASS1 can only be copied to registers of class CLASS2 by |
1010 | storing a register of CLASS1 into memory and loading that memory location | |
1011 | into a register of CLASS2. */ | |
3f622353 RH |
1012 | |
1013 | #if 0 | |
1014 | /* ??? May need this, but since we've disallowed TFmode in GR_REGS, | |
1015 | I'm not quite sure how it could be invoked. The normal problems | |
1016 | with unions should be solved with the addressof fiddling done by | |
1017 | movtf and friends. */ | |
1018 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
1019 | ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ | |
1020 | || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) | |
1021 | #endif | |
c65ebc55 JW |
1022 | |
1023 | /* A C expression for the maximum number of consecutive registers of | |
1024 | class CLASS needed to hold a value of mode MODE. | |
1025 | This is closely related to the macro `HARD_REGNO_NREGS'. */ | |
1026 | ||
1027 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
f2f90c63 | 1028 | ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ |
3f622353 | 1029 | : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \ |
c65ebc55 JW |
1030 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1031 | ||
cff9f8d5 | 1032 | /* In FP regs, we can't change FP values to integer values and vice |
46146529 | 1033 | versa, but we can change e.g. DImode to SImode. */ |
02188693 | 1034 | |
b0c42aed JH |
1035 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
1036 | (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \ | |
1037 | ? reg_classes_intersect_p (CLASS, FR_REGS) : 0) | |
02188693 | 1038 | |
97e242b0 RH |
1039 | /* A C expression that defines the machine-dependent operand constraint |
1040 | letters (`I', `J', `K', .. 'P') that specify particular ranges of | |
1041 | integer values. */ | |
c65ebc55 JW |
1042 | |
1043 | /* 14 bit signed immediate for arithmetic instructions. */ | |
1044 | #define CONST_OK_FOR_I(VALUE) \ | |
1045 | ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000) | |
1046 | /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */ | |
1047 | #define CONST_OK_FOR_J(VALUE) \ | |
1048 | ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000) | |
1049 | /* 8 bit signed immediate for logical instructions. */ | |
1050 | #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100) | |
1051 | /* 8 bit adjusted signed immediate for compare pseudo-ops. */ | |
1052 | #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100) | |
1053 | /* 6 bit unsigned immediate for shift counts. */ | |
1054 | #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40) | |
1055 | /* 9 bit signed immediate for load/store post-increments. */ | |
c65ebc55 JW |
1056 | #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200) |
1057 | /* 0 for r0. Used by Linux kernel, do not change. */ | |
1058 | #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0) | |
1059 | /* 0 or -1 for dep instruction. */ | |
1060 | #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1) | |
1061 | ||
1062 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1063 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
1064 | : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ | |
1065 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
1066 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
1067 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
1068 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
1069 | : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ | |
1070 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ | |
1071 | : 0) | |
1072 | ||
1073 | /* A C expression that defines the machine-dependent operand constraint letters | |
1074 | (`G', `H') that specify particular ranges of `const_double' values. */ | |
1075 | ||
1076 | /* 0.0 and 1.0 for fr0 and fr1. */ | |
1077 | #define CONST_DOUBLE_OK_FOR_G(VALUE) \ | |
1078 | ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \ | |
1079 | || (VALUE) == CONST1_RTX (GET_MODE (VALUE))) | |
1080 | ||
1081 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
1082 | ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0) | |
1083 | ||
1084 | /* A C expression that defines the optional machine-dependent constraint | |
1085 | letters (`Q', `R', `S', `T', `U') that can be used to segregate specific | |
1086 | types of operands, usually memory references, for the target machine. */ | |
3b572406 | 1087 | |
041f25e6 | 1088 | /* Non-volatile memory for FP_REG loads/stores. */ |
3b572406 RH |
1089 | #define CONSTRAINT_OK_FOR_Q(VALUE) \ |
1090 | (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE)) | |
041f25e6 RH |
1091 | /* 1..4 for shladd arguments. */ |
1092 | #define CONSTRAINT_OK_FOR_R(VALUE) \ | |
1093 | (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4) | |
0551c32d RH |
1094 | /* Non-post-inc memory for asms and other unsavory creatures. */ |
1095 | #define CONSTRAINT_OK_FOR_S(VALUE) \ | |
1096 | (GET_CODE (VALUE) == MEM \ | |
1097 | && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \ | |
1098 | && (reload_in_progress || memory_operand ((VALUE), VOIDmode))) | |
a32767e4 DM |
1099 | /* Symbol ref to small-address-area: */ |
1100 | #define CONSTRAINT_OK_FOR_T(VALUE) \ | |
1101 | (GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE)) | |
3b572406 RH |
1102 | |
1103 | #define EXTRA_CONSTRAINT(VALUE, C) \ | |
041f25e6 RH |
1104 | ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \ |
1105 | : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \ | |
0551c32d | 1106 | : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \ |
a32767e4 | 1107 | : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \ |
041f25e6 | 1108 | : 0) |
c65ebc55 JW |
1109 | \f |
1110 | /* Basic Stack Layout */ | |
1111 | ||
1112 | /* Define this macro if pushing a word onto the stack moves the stack pointer | |
1113 | to a smaller address. */ | |
1114 | #define STACK_GROWS_DOWNWARD 1 | |
1115 | ||
1116 | /* Define this macro if the addresses of local variable slots are at negative | |
1117 | offsets from the frame pointer. */ | |
97e242b0 RH |
1118 | /* #define FRAME_GROWS_DOWNWARD */ |
1119 | ||
1120 | /* Offset from the frame pointer to the first local variable slot to | |
1121 | be allocated. */ | |
1122 | #define STARTING_FRAME_OFFSET 0 | |
c65ebc55 JW |
1123 | |
1124 | /* Offset from the stack pointer register to the first location at which | |
1125 | outgoing arguments are placed. If not specified, the default value of zero | |
1126 | is used. This is the proper value for most machines. */ | |
1127 | /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ | |
1128 | #define STACK_POINTER_OFFSET 16 | |
1129 | ||
1130 | /* Offset from the argument pointer register to the first argument's address. | |
1131 | On some machines it may depend on the data type of the function. */ | |
1132 | #define FIRST_PARM_OFFSET(FUNDECL) 0 | |
1133 | ||
1134 | /* A C expression whose value is RTL representing the value of the return | |
1135 | address for the frame COUNT steps up from the current frame, after the | |
1136 | prologue. */ | |
1137 | ||
1138 | /* ??? Frames other than zero would likely require interpreting the frame | |
1139 | unwind info, so we don't try to support them. We would also need to define | |
1140 | DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ | |
1141 | ||
46327bc5 | 1142 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
af1e5518 | 1143 | ia64_return_addr_rtx (COUNT, FRAME) |
c65ebc55 JW |
1144 | |
1145 | /* A C expression whose value is RTL representing the location of the incoming | |
1146 | return address at the beginning of any function, before the prologue. This | |
1147 | RTL is either a `REG', indicating that the return value is saved in `REG', | |
1148 | or a `MEM' representing a location in the stack. This enables DWARF2 | |
1149 | unwind info for C++ EH. */ | |
1150 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) | |
13da91fd | 1151 | |
c65ebc55 JW |
1152 | /* ??? This is not defined because of three problems. |
1153 | 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte. | |
1154 | The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be | |
1155 | worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise | |
1156 | unused register number. | |
1157 | 2) dwarf2out_frame_debug core dumps while processing prologue insns. We | |
1158 | need to refine which insns have RTX_FRAME_RELATED_P set and which don't. | |
1159 | 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO | |
1160 | to zero, despite what the documentation implies, because it is tested in | |
1161 | a few places with #ifdef instead of #if. */ | |
1162 | #undef INCOMING_RETURN_ADDR_RTX | |
1163 | ||
1164 | /* A C expression whose value is an integer giving the offset, in bytes, from | |
1165 | the value of the stack pointer register to the top of the stack frame at the | |
1166 | beginning of any function, before the prologue. The top of the frame is | |
1167 | defined to be the value of the stack pointer in the previous frame, just | |
1168 | before the call instruction. */ | |
1169 | #define INCOMING_FRAME_SP_OFFSET 0 | |
1170 | ||
1171 | \f | |
1172 | /* Register That Address the Stack Frame. */ | |
1173 | ||
1174 | /* The register number of the stack pointer register, which must also be a | |
1175 | fixed register according to `FIXED_REGISTERS'. On most machines, the | |
1176 | hardware determines which register this is. */ | |
1177 | ||
1178 | #define STACK_POINTER_REGNUM 12 | |
1179 | ||
1180 | /* The register number of the frame pointer register, which is used to access | |
1181 | automatic variables in the stack frame. On some machines, the hardware | |
1182 | determines which register this is. On other machines, you can choose any | |
1183 | register you wish for this purpose. */ | |
1184 | ||
1185 | #define FRAME_POINTER_REGNUM 328 | |
1186 | ||
97e242b0 RH |
1187 | /* Base register for access to local variables of the function. */ |
1188 | #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) | |
c65ebc55 JW |
1189 | |
1190 | /* The register number of the arg pointer register, which is used to access the | |
1191 | function's argument list. */ | |
1192 | /* r0 won't otherwise be used, so put the always eliminated argument pointer | |
1193 | in it. */ | |
1194 | #define ARG_POINTER_REGNUM R_GR(0) | |
1195 | ||
ebf0e888 RH |
1196 | /* Due to the way varargs and argument spilling happens, the argument |
1197 | pointer is not 16-byte aligned like the stack pointer. */ | |
1198 | #define INIT_EXPANDERS \ | |
1199 | do { \ | |
1200 | if (cfun && cfun->emit->regno_pointer_align) \ | |
1201 | REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ | |
1202 | } while (0) | |
1203 | ||
c65ebc55 | 1204 | /* Register numbers used for passing a function's static chain pointer. */ |
97e242b0 | 1205 | /* ??? The ABI sez the static chain should be passed as a normal parameter. */ |
c65ebc55 | 1206 | #define STATIC_CHAIN_REGNUM 15 |
c65ebc55 JW |
1207 | \f |
1208 | /* Eliminating the Frame Pointer and the Arg Pointer */ | |
1209 | ||
1210 | /* A C expression which is nonzero if a function must have and use a frame | |
1211 | pointer. This expression is evaluated in the reload pass. If its value is | |
1212 | nonzero the function will have a frame pointer. */ | |
c65ebc55 JW |
1213 | #define FRAME_POINTER_REQUIRED 0 |
1214 | ||
97e242b0 RH |
1215 | /* Show we can debug even without a frame pointer. */ |
1216 | #define CAN_DEBUG_WITHOUT_FP | |
1217 | ||
c65ebc55 JW |
1218 | /* If defined, this macro specifies a table of register pairs used to eliminate |
1219 | unneeded registers that point into the stack frame. */ | |
1220 | ||
1221 | #define ELIMINABLE_REGS \ | |
1222 | { \ | |
1223 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
97e242b0 | 1224 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
46327bc5 | 1225 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
97e242b0 | 1226 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
c65ebc55 JW |
1227 | } |
1228 | ||
9cd10576 | 1229 | /* A C expression that returns nonzero if the compiler is allowed to try to |
97e242b0 RH |
1230 | replace register number FROM with register number TO. The frame pointer |
1231 | is automatically handled. */ | |
c65ebc55 | 1232 | |
46327bc5 RH |
1233 | #define CAN_ELIMINATE(FROM, TO) \ |
1234 | (TO == BR_REG (0) ? current_function_is_leaf : 1) | |
c65ebc55 | 1235 | |
97e242b0 RH |
1236 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It |
1237 | specifies the initial difference between the specified pair of | |
1238 | registers. This macro must be defined if `ELIMINABLE_REGS' is | |
1239 | defined. */ | |
1240 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1241 | ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) | |
c65ebc55 JW |
1242 | \f |
1243 | /* Passing Function Arguments on the Stack */ | |
1244 | ||
1245 | /* Define this macro if an argument declared in a prototype as an integral type | |
1246 | smaller than `int' should actually be passed as an `int'. In addition to | |
1247 | avoiding errors in certain cases of mismatch, it also makes for better code | |
1248 | on certain machines. */ | |
1249 | /* ??? Investigate. */ | |
1250 | /* #define PROMOTE_PROTOTYPES */ | |
1251 | ||
1252 | /* If defined, the maximum amount of space required for outgoing arguments will | |
1253 | be computed and placed into the variable | |
1254 | `current_function_outgoing_args_size'. */ | |
1255 | ||
f73ad30e | 1256 | #define ACCUMULATE_OUTGOING_ARGS 1 |
c65ebc55 JW |
1257 | |
1258 | /* A C expression that should indicate the number of bytes of its own arguments | |
1259 | that a function pops on returning, or 0 if the function pops no arguments | |
1260 | and the caller must therefore pop them all after the function returns. */ | |
1261 | ||
1262 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 | |
1263 | ||
1264 | \f | |
1265 | /* Function Arguments in Registers */ | |
1266 | ||
1267 | #define MAX_ARGUMENT_SLOTS 8 | |
1268 | #define MAX_INT_RETURN_SLOTS 4 | |
1269 | #define GR_ARG_FIRST IN_REG (0) | |
1270 | #define GR_RET_FIRST GR_REG (8) | |
1271 | #define GR_RET_LAST GR_REG (11) | |
1272 | #define FR_ARG_FIRST FR_REG (8) | |
1273 | #define FR_RET_FIRST FR_REG (8) | |
1274 | #define FR_RET_LAST FR_REG (15) | |
1275 | #define AR_ARG_FIRST OUT_REG (0) | |
1276 | ||
1277 | /* A C expression that controls whether a function argument is passed in a | |
1278 | register, and which register. */ | |
1279 | ||
1280 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1281 | ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0) | |
1282 | ||
1283 | /* Define this macro if the target machine has "register windows", so that the | |
1284 | register in which a function sees an arguments is not necessarily the same | |
1285 | as the one in which the caller passed the argument. */ | |
1286 | ||
1287 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
1288 | ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1) | |
1289 | ||
1290 | /* A C expression for the number of words, at the beginning of an argument, | |
1291 | must be put in registers. The value must be zero for arguments that are | |
1292 | passed entirely in registers or that are entirely pushed on the stack. */ | |
1293 | ||
1294 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1295 | ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
1296 | ||
1297 | /* A C expression that indicates when an argument must be passed by reference. | |
1298 | If nonzero for an argument, a copy of that argument is made in memory and a | |
1299 | pointer to the argument is passed instead of the argument itself. The | |
1300 | pointer is passed in whatever way is appropriate for passing a pointer to | |
1301 | that type. */ | |
1302 | ||
51dcde6f RH |
1303 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
1304 | ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) | |
c65ebc55 JW |
1305 | |
1306 | /* A C type for declaring a variable that is used as the first argument of | |
1307 | `FUNCTION_ARG' and other related values. For some target machines, the type | |
1308 | `int' suffices and can hold the number of bytes of argument so far. */ | |
1309 | ||
1310 | typedef struct ia64_args | |
1311 | { | |
1312 | int words; /* # words of arguments so far */ | |
648fe28b | 1313 | int int_regs; /* # GR registers used so far */ |
c65ebc55 JW |
1314 | int fp_regs; /* # FR registers used so far */ |
1315 | int prototype; /* whether function prototyped */ | |
1316 | } CUMULATIVE_ARGS; | |
1317 | ||
1318 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
1319 | state at the beginning of the argument list. */ | |
1320 | ||
1321 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
1322 | do { \ | |
1323 | (CUM).words = 0; \ | |
648fe28b | 1324 | (CUM).int_regs = 0; \ |
c65ebc55 JW |
1325 | (CUM).fp_regs = 0; \ |
1326 | (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \ | |
1327 | } while (0) | |
1328 | ||
1329 | /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the | |
1330 | arguments for the function being compiled. If this macro is undefined, | |
1331 | `INIT_CUMULATIVE_ARGS' is used instead. */ | |
1332 | ||
1333 | /* We set prototype to true so that we never try to return a PARALLEL from | |
1334 | function_arg. */ | |
1335 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
1336 | do { \ | |
1337 | (CUM).words = 0; \ | |
648fe28b | 1338 | (CUM).int_regs = 0; \ |
c65ebc55 JW |
1339 | (CUM).fp_regs = 0; \ |
1340 | (CUM).prototype = 1; \ | |
1341 | } while (0) | |
1342 | ||
1343 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
1344 | advance past an argument in the argument list. The values MODE, TYPE and | |
1345 | NAMED describe that argument. Once this is done, the variable CUM is | |
1346 | suitable for analyzing the *following* argument with `FUNCTION_ARG'. */ | |
1347 | ||
1348 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1349 | ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED) | |
1350 | ||
1351 | /* If defined, a C expression that gives the alignment boundary, in bits, of an | |
1352 | argument with the specified mode and type. */ | |
1353 | ||
93dd6255 JW |
1354 | /* Arguments with alignment larger than 8 bytes start at the next even |
1355 | boundary. See ia64_function_arg. */ | |
c65ebc55 JW |
1356 | |
1357 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
93dd6255 JW |
1358 | (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \ |
1359 | : (((((MODE) == BLKmode \ | |
1360 | ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
1361 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \ | |
1362 | ? 128 : PARM_BOUNDARY) | |
c65ebc55 JW |
1363 | |
1364 | /* A C expression that is nonzero if REGNO is the number of a hard register in | |
1365 | which function arguments are sometimes passed. This does *not* include | |
1366 | implicit arguments such as the static chain and the structure-value address. | |
1367 | On many machines, no registers can be used for this purpose since all | |
1368 | function arguments are pushed on the stack. */ | |
1369 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1370 | (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ | |
1371 | || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) | |
1372 | \f | |
c65ebc55 JW |
1373 | /* Implement `va_arg'. */ |
1374 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1375 | ia64_va_arg (valist, type) | |
1376 | \f | |
1377 | /* How Scalar Function Values are Returned */ | |
1378 | ||
1379 | /* A C expression to create an RTX representing the place where a function | |
1380 | returns a value of data type VALTYPE. */ | |
1381 | ||
1382 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1383 | ia64_function_value (VALTYPE, FUNC) | |
1384 | ||
1385 | /* A C expression to create an RTX representing the place where a library | |
1386 | function returns a value of mode MODE. */ | |
1387 | ||
1388 | #define LIBCALL_VALUE(MODE) \ | |
1389 | gen_rtx_REG (MODE, \ | |
23c108af SE |
1390 | (((GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1391 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \ | |
1392 | ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \ | |
c65ebc55 JW |
1393 | ? FR_RET_FIRST : GR_RET_FIRST)) |
1394 | ||
1395 | /* A C expression that is nonzero if REGNO is the number of a hard register in | |
1396 | which the values of called function may come back. */ | |
1397 | ||
1398 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
1399 | (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \ | |
5b8fcab6 | 1400 | || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST)) |
c65ebc55 JW |
1401 | |
1402 | \f | |
1403 | /* How Large Values are Returned */ | |
1404 | ||
1405 | /* A nonzero value says to return the function value in memory, just as large | |
1406 | structures are always returned. */ | |
1407 | ||
1408 | #define RETURN_IN_MEMORY(TYPE) \ | |
1409 | ia64_return_in_memory (TYPE) | |
1410 | ||
1411 | /* If you define this macro to be 0, then the conventions used for structure | |
1412 | and union return values are decided by the `RETURN_IN_MEMORY' macro. */ | |
1413 | ||
1414 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1415 | ||
1416 | /* If the structure value address is passed in a register, then | |
1417 | `STRUCT_VALUE_REGNUM' should be the number of that register. */ | |
1418 | ||
1419 | #define STRUCT_VALUE_REGNUM GR_REG (8) | |
1420 | ||
1421 | \f | |
1422 | /* Caller-Saves Register Allocation */ | |
1423 | ||
1424 | /* A C expression to determine whether it is worthwhile to consider placing a | |
1425 | pseudo-register in a call-clobbered hard register and saving and restoring | |
1426 | it around each function call. The expression should be 1 when this is worth | |
1427 | doing, and 0 otherwise. | |
1428 | ||
1429 | If you don't define this macro, a default is used which is good on most | |
1430 | machines: `4 * CALLS < REFS'. */ | |
1431 | /* ??? Investigate. */ | |
1432 | /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ | |
1433 | ||
1434 | \f | |
1435 | /* Function Entry and Exit */ | |
1436 | ||
c65ebc55 JW |
1437 | /* Define this macro as a C expression that is nonzero if the return |
1438 | instruction or the function epilogue ignores the value of the stack pointer; | |
1439 | in other words, if it is safe to delete an instruction to adjust the stack | |
1440 | pointer before a return from the function. */ | |
1441 | ||
1442 | #define EXIT_IGNORE_STACK 1 | |
1443 | ||
1444 | /* Define this macro as a C expression that is nonzero for registers | |
1445 | used by the epilogue or the `return' pattern. */ | |
1446 | ||
1447 | #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) | |
1448 | ||
15b5aef3 RH |
1449 | /* Nonzero for registers used by the exception handling mechanism. */ |
1450 | ||
1451 | #define EH_USES(REGNO) ia64_eh_uses (REGNO) | |
1452 | ||
67231816 RH |
1453 | /* Output part N of a function descriptor for DECL. For ia64, both |
1454 | words are emitted with a single relocation, so ignore N > 0. */ | |
1455 | #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ | |
1456 | do { \ | |
1457 | if ((PART) == 0) \ | |
1458 | { \ | |
a6f5e048 RH |
1459 | if (TARGET_ILP32) \ |
1460 | fputs ("\tdata8.ua @iplt(", FILE); \ | |
1461 | else \ | |
1462 | fputs ("\tdata16.ua @iplt(", FILE); \ | |
67231816 RH |
1463 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ |
1464 | fputs (")\n", FILE); \ | |
a6f5e048 RH |
1465 | if (TARGET_ILP32) \ |
1466 | fputs ("\tdata8.ua 0\n", FILE); \ | |
67231816 RH |
1467 | } \ |
1468 | } while (0) | |
c65ebc55 JW |
1469 | \f |
1470 | /* Generating Code for Profiling. */ | |
1471 | ||
1472 | /* A C statement or compound statement to output to FILE some assembler code to | |
1473 | call the profiling subroutine `mcount'. */ | |
1474 | ||
243a7070 DB |
1475 | #undef FUNCTION_PROFILER |
1476 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
c65ebc55 JW |
1477 | do { \ |
1478 | char buf[20]; \ | |
1479 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \ | |
243a7070 DB |
1480 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \ |
1481 | if (TARGET_AUTO_PIC) \ | |
1482 | fputs ("\tmovl out3 = @gprel(", FILE); \ | |
1483 | else \ | |
1484 | fputs ("\taddl out3 = @ltoff(", FILE); \ | |
c65ebc55 | 1485 | assemble_name (FILE, buf); \ |
243a7070 DB |
1486 | if (TARGET_AUTO_PIC) \ |
1487 | fputs (");;\n", FILE); \ | |
1488 | else \ | |
1489 | fputs ("), r1;;\n", FILE); \ | |
1490 | fputs ("\tmov out1 = r1\n", FILE); \ | |
1491 | fputs ("\tmov out2 = b0\n", FILE); \ | |
1492 | fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \ | |
c65ebc55 | 1493 | } while (0) |
c65ebc55 JW |
1494 | \f |
1495 | /* Implementing the Varargs Macros. */ | |
1496 | ||
1497 | /* Define this macro to store the anonymous register arguments into the stack | |
1498 | so that all the arguments appear to have been passed consecutively on the | |
1499 | stack. */ | |
1500 | ||
1501 | #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \ | |
1502 | ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME) | |
1503 | ||
1504 | /* Define this macro if the location where a function argument is passed | |
1505 | depends on whether or not it is a named argument. */ | |
1506 | ||
1507 | #define STRICT_ARGUMENT_NAMING 1 | |
1508 | ||
1509 | \f | |
1510 | /* Trampolines for Nested Functions. */ | |
1511 | ||
1512 | /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of | |
1513 | the function containing a non-local goto target. */ | |
1514 | ||
1515 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
1516 | ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) | |
1517 | ||
1518 | /* Output assembler code for a block containing the constant parts of | |
1519 | a trampoline, leaving space for the variable parts. | |
1520 | ||
1521 | The trampoline should set the static chain pointer to value placed | |
97e242b0 RH |
1522 | into the trampoline and should branch to the specified routine. |
1523 | To make the normal indirect-subroutine calling convention work, | |
1524 | the trampoline must look like a function descriptor; the first | |
1525 | word being the target address and the second being the target's | |
1526 | global pointer. | |
1527 | ||
1528 | We abuse the concept of a global pointer by arranging for it | |
1529 | to point to the data we need to load. The complete trampoline | |
c65ebc55 JW |
1530 | has the following form: |
1531 | ||
97e242b0 RH |
1532 | +-------------------+ \ |
1533 | TRAMP: | __ia64_trampoline | | | |
1534 | +-------------------+ > fake function descriptor | |
1535 | | TRAMP+16 | | | |
1536 | +-------------------+ / | |
1537 | | target descriptor | | |
1538 | +-------------------+ | |
1539 | | static link | | |
1540 | +-------------------+ | |
c65ebc55 JW |
1541 | */ |
1542 | ||
c65ebc55 JW |
1543 | /* A C expression for the size in bytes of the trampoline, as an integer. */ |
1544 | ||
97e242b0 | 1545 | #define TRAMPOLINE_SIZE 32 |
c65ebc55 JW |
1546 | |
1547 | /* Alignment required for trampolines, in bits. */ | |
1548 | ||
97e242b0 | 1549 | #define TRAMPOLINE_ALIGNMENT 64 |
c65ebc55 JW |
1550 | |
1551 | /* A C statement to initialize the variable parts of a trampoline. */ | |
1552 | ||
1553 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \ | |
97e242b0 | 1554 | ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN)) |
c65ebc55 JW |
1555 | \f |
1556 | /* Implicit Calls to Library Routines */ | |
1557 | ||
7ec022b2 | 1558 | /* Define this macro if GCC should generate calls to the System V (and ANSI |
c65ebc55 JW |
1559 | C) library functions `memcpy' and `memset' rather than the BSD functions |
1560 | `bcopy' and `bzero'. */ | |
1561 | ||
1562 | #define TARGET_MEM_FUNCTIONS | |
1563 | ||
1564 | \f | |
1565 | /* Addressing Modes */ | |
1566 | ||
1567 | /* Define this macro if the machine supports post-increment addressing. */ | |
1568 | ||
1569 | #define HAVE_POST_INCREMENT 1 | |
1570 | #define HAVE_POST_DECREMENT 1 | |
4b983fdc RH |
1571 | #define HAVE_POST_MODIFY_DISP 1 |
1572 | #define HAVE_POST_MODIFY_REG 1 | |
c65ebc55 JW |
1573 | |
1574 | /* A C expression that is 1 if the RTX X is a constant which is a valid | |
1575 | address. */ | |
1576 | ||
1577 | #define CONSTANT_ADDRESS_P(X) 0 | |
1578 | ||
1579 | /* The max number of registers that can appear in a valid memory address. */ | |
1580 | ||
4b983fdc | 1581 | #define MAX_REGS_PER_ADDRESS 2 |
c65ebc55 JW |
1582 | |
1583 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
1584 | RTX) is a legitimate memory address on the target machine for a memory | |
1585 | operand of mode MODE. */ | |
1586 | ||
4b983fdc RH |
1587 | #define LEGITIMATE_ADDRESS_REG(X) \ |
1588 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1589 | || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \ | |
1590 | && REG_OK_FOR_BASE_P (XEXP (X, 0)))) | |
1591 | ||
1592 | #define LEGITIMATE_ADDRESS_DISP(R, X) \ | |
1593 | (GET_CODE (X) == PLUS \ | |
1594 | && rtx_equal_p (R, XEXP (X, 0)) \ | |
cf606f45 | 1595 | && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \ |
4b983fdc | 1596 | || (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
5527bf14 RH |
1597 | && INTVAL (XEXP (X, 1)) >= -256 \ |
1598 | && INTVAL (XEXP (X, 1)) < 256))) | |
c65ebc55 JW |
1599 | |
1600 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
1601 | do { \ | |
4b983fdc | 1602 | if (LEGITIMATE_ADDRESS_REG (X)) \ |
c65ebc55 | 1603 | goto LABEL; \ |
4b983fdc RH |
1604 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ |
1605 | && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ | |
1606 | && XEXP (X, 0) != arg_pointer_rtx) \ | |
1607 | goto LABEL; \ | |
1608 | else if (GET_CODE (X) == POST_MODIFY \ | |
1609 | && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ | |
1610 | && XEXP (X, 0) != arg_pointer_rtx \ | |
1611 | && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \ | |
c65ebc55 | 1612 | goto LABEL; \ |
c65ebc55 JW |
1613 | } while (0) |
1614 | ||
1615 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
1616 | use as a base register. */ | |
1617 | ||
1618 | #ifdef REG_OK_STRICT | |
1619 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1620 | #else | |
1621 | #define REG_OK_FOR_BASE_P(X) \ | |
1622 | (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1623 | #endif | |
1624 | ||
1625 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
cf606f45 | 1626 | use as an index register. This is needed for POST_MODIFY. */ |
c65ebc55 | 1627 | |
cf606f45 | 1628 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) |
c65ebc55 JW |
1629 | |
1630 | /* A C compound statement that attempts to replace X with a valid memory | |
1631 | address for an operand of mode MODE. | |
1632 | ||
1633 | This must be present, but there is nothing useful to be done here. */ | |
1634 | ||
1635 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) | |
1636 | ||
1637 | /* A C statement or compound statement with a conditional `goto LABEL;' | |
1638 | executed if memory address X (an RTX) can have different meanings depending | |
1639 | on the machine mode of the memory reference it is used for or if the address | |
1640 | is valid for some modes but not others. */ | |
1641 | ||
3f622353 | 1642 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
c65ebc55 JW |
1643 | if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \ |
1644 | goto LABEL; | |
1645 | ||
1646 | /* A C expression that is nonzero if X is a legitimate constant for an | |
1647 | immediate operand on the target machine. */ | |
1648 | ||
1649 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1650 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ | |
1651 | || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \ | |
1652 | ||
1653 | \f | |
1654 | /* Condition Code Status */ | |
1655 | ||
1656 | /* One some machines not all possible comparisons are defined, but you can | |
1657 | convert an invalid comparison into a valid one. */ | |
1658 | /* ??? Investigate. See the alpha definition. */ | |
1659 | /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ | |
1660 | ||
1661 | \f | |
1662 | /* Describing Relative Costs of Operations */ | |
1663 | ||
c65ebc55 | 1664 | /* A C expression for the cost of moving data from a register in class FROM to |
7109d286 | 1665 | one in class TO, using MODE. */ |
c65ebc55 | 1666 | |
7109d286 | 1667 | #define REGISTER_MOVE_COST ia64_register_move_cost |
c65ebc55 | 1668 | |
f2f90c63 RH |
1669 | /* A C expression for the cost of moving data of mode M between a |
1670 | register and memory. */ | |
1671 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
7109d286 RH |
1672 | ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \ |
1673 | || (CLASS) == GR_AND_FR_REGS ? 4 : 10) | |
c65ebc55 JW |
1674 | |
1675 | /* A C expression for the cost of a branch instruction. A value of 1 is the | |
5b8fcab6 | 1676 | default; other values are interpreted relative to that. Used by the |
e5bde68a RH |
1677 | if-conversion code as max instruction count. */ |
1678 | /* ??? This requires investigation. The primary effect might be how | |
1679 | many additional insn groups we run into, vs how good the dynamic | |
1680 | branch predictor is. */ | |
1681 | ||
1682 | #define BRANCH_COST 6 | |
c65ebc55 JW |
1683 | |
1684 | /* Define this macro as a C expression which is nonzero if accessing less than | |
1685 | a word of memory (i.e. a `char' or a `short') is no faster than accessing a | |
1686 | word of memory. */ | |
1687 | ||
1688 | #define SLOW_BYTE_ACCESS 1 | |
1689 | ||
1690 | /* Define this macro if it is as good or better to call a constant function | |
1691 | address than to call an address kept in a register. | |
1692 | ||
1693 | Indirect function calls are more expensive that direct function calls, so | |
1694 | don't cse function addresses. */ | |
1695 | ||
1696 | #define NO_FUNCTION_CSE | |
1697 | ||
c65ebc55 JW |
1698 | \f |
1699 | /* Dividing the output into sections. */ | |
1700 | ||
1701 | /* A C expression whose value is a string containing the assembler operation | |
1702 | that should precede instructions and read-only data. */ | |
1703 | ||
de323aa1 | 1704 | #define TEXT_SECTION_ASM_OP "\t.text" |
c65ebc55 JW |
1705 | |
1706 | /* A C expression whose value is a string containing the assembler operation to | |
1707 | identify the following data as writable initialized data. */ | |
1708 | ||
de323aa1 | 1709 | #define DATA_SECTION_ASM_OP "\t.data" |
c65ebc55 JW |
1710 | |
1711 | /* If defined, a C expression whose value is a string containing the assembler | |
1712 | operation to identify the following data as uninitialized global data. */ | |
1713 | ||
de323aa1 | 1714 | #define BSS_SECTION_ASM_OP "\t.bss" |
c65ebc55 | 1715 | |
c65ebc55 | 1716 | #define IA64_DEFAULT_GVALUE 8 |
c65ebc55 JW |
1717 | \f |
1718 | /* Position Independent Code. */ | |
1719 | ||
1720 | /* The register number of the register used to address a table of static data | |
1721 | addresses in memory. */ | |
1722 | ||
1723 | /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of | |
1724 | gen_rtx_REG (DImode, 1). */ | |
1725 | ||
1726 | /* ??? Should we set flag_pic? Probably need to define | |
1727 | LEGITIMIZE_PIC_OPERAND_P to make that work. */ | |
1728 | ||
1729 | #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) | |
1730 | ||
1731 | /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is | |
1732 | clobbered by calls. */ | |
1733 | ||
1734 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
1735 | ||
1736 | \f | |
1737 | /* The Overall Framework of an Assembler File. */ | |
1738 | ||
1739 | /* A C string constant describing how to begin a comment in the target | |
1740 | assembler language. The compiler assumes that the comment will end at the | |
1741 | end of the line. */ | |
1742 | ||
1743 | #define ASM_COMMENT_START "//" | |
1744 | ||
1745 | /* A C string constant for text to be output before each `asm' statement or | |
1746 | group of consecutive ones. */ | |
1747 | ||
1748 | /* ??? This won't work with the Intel assembler, because it does not accept | |
1749 | # as a comment start character. However, //APP does not work in gas, so we | |
1750 | can't use that either. Same problem for ASM_APP_OFF below. */ | |
1751 | ||
1752 | #define ASM_APP_ON "#APP\n" | |
1753 | ||
1754 | /* A C string constant for text to be output after each `asm' statement or | |
1755 | group of consecutive ones. */ | |
1756 | ||
1757 | #define ASM_APP_OFF "#NO_APP\n" | |
1758 | ||
c65ebc55 JW |
1759 | \f |
1760 | /* Output of Uninitialized Variables. */ | |
1761 | ||
1762 | /* This is all handled by svr4.h. */ | |
1763 | ||
1764 | \f | |
1765 | /* Output and Generation of Labels. */ | |
1766 | ||
1767 | /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
1768 | assembler definition of a label named NAME. */ | |
1769 | ||
1770 | /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of | |
1771 | why ia64_asm_output_label exists. */ | |
1772 | ||
1773 | extern int ia64_asm_output_label; | |
1774 | #define ASM_OUTPUT_LABEL(STREAM, NAME) \ | |
1775 | do { \ | |
1776 | ia64_asm_output_label = 1; \ | |
1777 | assemble_name (STREAM, NAME); \ | |
1778 | fputs (":\n", STREAM); \ | |
1779 | ia64_asm_output_label = 0; \ | |
1780 | } while (0) | |
1781 | ||
506a61b1 KG |
1782 | /* Globalizing directive for a label. */ |
1783 | #define GLOBAL_ASM_OP "\t.global " | |
c65ebc55 JW |
1784 | |
1785 | /* A C statement (sans semicolon) to output to the stdio stream STREAM any text | |
1786 | necessary for declaring the name of an external symbol named NAME which is | |
1787 | referenced in this compilation but not defined. */ | |
1788 | ||
1789 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ | |
1790 | ia64_asm_output_external (FILE, DECL, NAME) | |
1791 | ||
1792 | /* A C statement to store into the string STRING a label whose name is made | |
1793 | from the string PREFIX and the number NUM. */ | |
1794 | ||
1795 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ | |
1796 | do { \ | |
1797 | sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ | |
1798 | } while (0) | |
1799 | ||
c65ebc55 JW |
1800 | /* ??? Not sure if using a ? in the name for Intel as is safe. */ |
1801 | ||
4977bab6 | 1802 | #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") |
c65ebc55 JW |
1803 | |
1804 | /* A C statement to output to the stdio stream STREAM assembler code which | |
1805 | defines (equates) the symbol NAME to have the value VALUE. */ | |
1806 | ||
1807 | #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ | |
1808 | do { \ | |
1809 | assemble_name (STREAM, NAME); \ | |
1810 | fputs (" = ", STREAM); \ | |
1811 | assemble_name (STREAM, VALUE); \ | |
1812 | fputc ('\n', STREAM); \ | |
1813 | } while (0) | |
1814 | ||
1815 | \f | |
1816 | /* Macros Controlling Initialization Routines. */ | |
1817 | ||
1818 | /* This is handled by svr4.h and sysv4.h. */ | |
1819 | ||
1820 | \f | |
1821 | /* Output of Assembler Instructions. */ | |
1822 | ||
1823 | /* A C initializer containing the assembler's names for the machine registers, | |
1824 | each one as a C string constant. */ | |
1825 | ||
1826 | #define REGISTER_NAMES \ | |
1827 | { \ | |
1828 | /* General registers. */ \ | |
49b83932 | 1829 | "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ |
c65ebc55 JW |
1830 | "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ |
1831 | "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ | |
1832 | "r30", "r31", \ | |
1833 | /* Local registers. */ \ | |
1834 | "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ | |
1835 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ | |
1836 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ | |
1837 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ | |
1838 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ | |
1839 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ | |
1840 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ | |
1841 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ | |
1842 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ | |
1843 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ | |
1844 | /* Input registers. */ \ | |
1845 | "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ | |
1846 | /* Output registers. */ \ | |
1847 | "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ | |
1848 | /* Floating-point registers. */ \ | |
1849 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ | |
1850 | "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ | |
1851 | "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ | |
1852 | "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ | |
1853 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ | |
1854 | "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ | |
1855 | "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ | |
1856 | "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ | |
1857 | "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ | |
1858 | "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ | |
1859 | "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ | |
1860 | "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ | |
1861 | "f120","f121","f122","f123","f124","f125","f126","f127", \ | |
1862 | /* Predicate registers. */ \ | |
1863 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ | |
1864 | "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ | |
1865 | "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ | |
1866 | "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ | |
1867 | "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ | |
1868 | "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ | |
1869 | "p60", "p61", "p62", "p63", \ | |
1870 | /* Branch registers. */ \ | |
1871 | "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ | |
af1e5518 RH |
1872 | /* Frame pointer. Application registers. */ \ |
1873 | "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ | |
c65ebc55 JW |
1874 | } |
1875 | ||
1876 | /* If defined, a C initializer for an array of structures containing a name and | |
1877 | a register number. This macro defines additional names for hard registers, | |
1878 | thus allowing the `asm' option in declarations to refer to registers using | |
1879 | alternate names. */ | |
1880 | ||
1881 | #define ADDITIONAL_REGISTER_NAMES \ | |
1882 | { \ | |
1883 | { "gp", R_GR (1) }, \ | |
1884 | { "sp", R_GR (12) }, \ | |
1885 | { "in0", IN_REG (0) }, \ | |
1886 | { "in1", IN_REG (1) }, \ | |
1887 | { "in2", IN_REG (2) }, \ | |
1888 | { "in3", IN_REG (3) }, \ | |
1889 | { "in4", IN_REG (4) }, \ | |
1890 | { "in5", IN_REG (5) }, \ | |
1891 | { "in6", IN_REG (6) }, \ | |
1892 | { "in7", IN_REG (7) }, \ | |
1893 | { "out0", OUT_REG (0) }, \ | |
1894 | { "out1", OUT_REG (1) }, \ | |
1895 | { "out2", OUT_REG (2) }, \ | |
1896 | { "out3", OUT_REG (3) }, \ | |
1897 | { "out4", OUT_REG (4) }, \ | |
1898 | { "out5", OUT_REG (5) }, \ | |
1899 | { "out6", OUT_REG (6) }, \ | |
1900 | { "out7", OUT_REG (7) }, \ | |
1901 | { "loc0", LOC_REG (0) }, \ | |
1902 | { "loc1", LOC_REG (1) }, \ | |
1903 | { "loc2", LOC_REG (2) }, \ | |
1904 | { "loc3", LOC_REG (3) }, \ | |
1905 | { "loc4", LOC_REG (4) }, \ | |
1906 | { "loc5", LOC_REG (5) }, \ | |
1907 | { "loc6", LOC_REG (6) }, \ | |
1908 | { "loc7", LOC_REG (7) }, \ | |
1909 | { "loc8", LOC_REG (8) }, \ | |
1910 | { "loc9", LOC_REG (9) }, \ | |
1911 | { "loc10", LOC_REG (10) }, \ | |
1912 | { "loc11", LOC_REG (11) }, \ | |
1913 | { "loc12", LOC_REG (12) }, \ | |
1914 | { "loc13", LOC_REG (13) }, \ | |
1915 | { "loc14", LOC_REG (14) }, \ | |
1916 | { "loc15", LOC_REG (15) }, \ | |
1917 | { "loc16", LOC_REG (16) }, \ | |
1918 | { "loc17", LOC_REG (17) }, \ | |
1919 | { "loc18", LOC_REG (18) }, \ | |
1920 | { "loc19", LOC_REG (19) }, \ | |
1921 | { "loc20", LOC_REG (20) }, \ | |
1922 | { "loc21", LOC_REG (21) }, \ | |
1923 | { "loc22", LOC_REG (22) }, \ | |
1924 | { "loc23", LOC_REG (23) }, \ | |
1925 | { "loc24", LOC_REG (24) }, \ | |
1926 | { "loc25", LOC_REG (25) }, \ | |
1927 | { "loc26", LOC_REG (26) }, \ | |
1928 | { "loc27", LOC_REG (27) }, \ | |
1929 | { "loc28", LOC_REG (28) }, \ | |
1930 | { "loc29", LOC_REG (29) }, \ | |
1931 | { "loc30", LOC_REG (30) }, \ | |
1932 | { "loc31", LOC_REG (31) }, \ | |
1933 | { "loc32", LOC_REG (32) }, \ | |
1934 | { "loc33", LOC_REG (33) }, \ | |
1935 | { "loc34", LOC_REG (34) }, \ | |
1936 | { "loc35", LOC_REG (35) }, \ | |
1937 | { "loc36", LOC_REG (36) }, \ | |
1938 | { "loc37", LOC_REG (37) }, \ | |
1939 | { "loc38", LOC_REG (38) }, \ | |
1940 | { "loc39", LOC_REG (39) }, \ | |
1941 | { "loc40", LOC_REG (40) }, \ | |
1942 | { "loc41", LOC_REG (41) }, \ | |
1943 | { "loc42", LOC_REG (42) }, \ | |
1944 | { "loc43", LOC_REG (43) }, \ | |
1945 | { "loc44", LOC_REG (44) }, \ | |
1946 | { "loc45", LOC_REG (45) }, \ | |
1947 | { "loc46", LOC_REG (46) }, \ | |
1948 | { "loc47", LOC_REG (47) }, \ | |
1949 | { "loc48", LOC_REG (48) }, \ | |
1950 | { "loc49", LOC_REG (49) }, \ | |
1951 | { "loc50", LOC_REG (50) }, \ | |
1952 | { "loc51", LOC_REG (51) }, \ | |
1953 | { "loc52", LOC_REG (52) }, \ | |
1954 | { "loc53", LOC_REG (53) }, \ | |
1955 | { "loc54", LOC_REG (54) }, \ | |
1956 | { "loc55", LOC_REG (55) }, \ | |
1957 | { "loc56", LOC_REG (56) }, \ | |
1958 | { "loc57", LOC_REG (57) }, \ | |
1959 | { "loc58", LOC_REG (58) }, \ | |
1960 | { "loc59", LOC_REG (59) }, \ | |
1961 | { "loc60", LOC_REG (60) }, \ | |
1962 | { "loc61", LOC_REG (61) }, \ | |
1963 | { "loc62", LOC_REG (62) }, \ | |
1964 | { "loc63", LOC_REG (63) }, \ | |
1965 | { "loc64", LOC_REG (64) }, \ | |
1966 | { "loc65", LOC_REG (65) }, \ | |
1967 | { "loc66", LOC_REG (66) }, \ | |
1968 | { "loc67", LOC_REG (67) }, \ | |
1969 | { "loc68", LOC_REG (68) }, \ | |
1970 | { "loc69", LOC_REG (69) }, \ | |
1971 | { "loc70", LOC_REG (70) }, \ | |
1972 | { "loc71", LOC_REG (71) }, \ | |
1973 | { "loc72", LOC_REG (72) }, \ | |
1974 | { "loc73", LOC_REG (73) }, \ | |
1975 | { "loc74", LOC_REG (74) }, \ | |
1976 | { "loc75", LOC_REG (75) }, \ | |
1977 | { "loc76", LOC_REG (76) }, \ | |
1978 | { "loc77", LOC_REG (77) }, \ | |
1979 | { "loc78", LOC_REG (78) }, \ | |
794eefd9 | 1980 | { "loc79", LOC_REG (79) }, \ |
c65ebc55 JW |
1981 | } |
1982 | ||
6b2300b3 JJ |
1983 | /* Emit a dtp-relative reference to a TLS variable. */ |
1984 | ||
1985 | #ifdef HAVE_AS_TLS | |
1986 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
1987 | ia64_output_dwarf_dtprel (FILE, SIZE, X) | |
1988 | #endif | |
1989 | ||
c65ebc55 JW |
1990 | /* A C compound statement to output to stdio stream STREAM the assembler syntax |
1991 | for an instruction operand X. X is an RTL expression. */ | |
1992 | ||
1993 | #define PRINT_OPERAND(STREAM, X, CODE) \ | |
1994 | ia64_print_operand (STREAM, X, CODE) | |
1995 | ||
1996 | /* A C expression which evaluates to true if CODE is a valid punctuation | |
1997 | character for use in the `PRINT_OPERAND' macro. */ | |
1998 | ||
1999 | /* ??? Keep this around for now, as we might need it later. */ | |
2000 | ||
6f8aa100 RH |
2001 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
2002 | ((CODE) == '+' || (CODE) == ',') | |
c65ebc55 JW |
2003 | |
2004 | /* A C compound statement to output to stdio stream STREAM the assembler syntax | |
2005 | for an instruction operand that is a memory reference whose address is X. X | |
2006 | is an RTL expression. */ | |
2007 | ||
2008 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2009 | ia64_print_operand_address (STREAM, X) | |
2010 | ||
2011 | /* If defined, C string expressions to be used for the `%R', `%L', `%U', and | |
2012 | `%I' options of `asm_fprintf' (see `final.c'). */ | |
2013 | ||
2014 | #define REGISTER_PREFIX "" | |
2015 | #define LOCAL_LABEL_PREFIX "." | |
2016 | #define USER_LABEL_PREFIX "" | |
2017 | #define IMMEDIATE_PREFIX "" | |
2018 | ||
2019 | \f | |
2020 | /* Output of dispatch tables. */ | |
2021 | ||
2022 | /* This macro should be provided on machines where the addresses in a dispatch | |
2023 | table are relative to the table's own address. */ | |
2024 | ||
2025 | /* ??? Depends on the pointer size. */ | |
2026 | ||
03d0dce1 SE |
2027 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
2028 | do { \ | |
2029 | if (TARGET_ILP32) \ | |
2030 | fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ | |
2031 | else \ | |
2032 | fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ | |
2033 | } while (0) | |
c65ebc55 JW |
2034 | |
2035 | /* This is how to output an element of a case-vector that is absolute. | |
2036 | (Ia64 does not use such vectors, but we must define this macro anyway.) */ | |
2037 | ||
2038 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort () | |
2039 | ||
c65ebc55 JW |
2040 | /* Jump tables only need 8 byte alignment. */ |
2041 | ||
2042 | #define ADDR_VEC_ALIGN(ADDR_VEC) 3 | |
2043 | ||
2044 | \f | |
2045 | /* Assembler Commands for Exception Regions. */ | |
2046 | ||
2a1ee410 RH |
2047 | /* Select a format to encode pointers in exception handling data. CODE |
2048 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2049 | true if the symbol may be affected by dynamic relocations. */ | |
2050 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
2051 | (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ | |
03d0dce1 SE |
2052 | | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ |
2053 | | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) | |
2a1ee410 RH |
2054 | |
2055 | /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
2056 | indirect are handled automatically. */ | |
2057 | #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
2058 | do { \ | |
2059 | const char *reltag = NULL; \ | |
2060 | if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ | |
2061 | reltag = "@segrel("; \ | |
2062 | else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ | |
2063 | reltag = "@gprel("; \ | |
2064 | if (reltag) \ | |
2065 | { \ | |
301d03af | 2066 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
2a1ee410 RH |
2067 | fputs (reltag, FILE); \ |
2068 | assemble_name (FILE, XSTR (ADDR, 0)); \ | |
2069 | fputc (')', FILE); \ | |
2070 | goto DONE; \ | |
2071 | } \ | |
2072 | } while (0) | |
c65ebc55 | 2073 | |
c65ebc55 JW |
2074 | \f |
2075 | /* Assembler Commands for Alignment. */ | |
2076 | ||
c65ebc55 JW |
2077 | /* ??? Investigate. */ |
2078 | ||
340f7e7c RH |
2079 | /* The alignment (log base 2) to put in front of LABEL, which follows |
2080 | a BARRIER. */ | |
c65ebc55 JW |
2081 | |
2082 | /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ | |
2083 | ||
2084 | /* The desired alignment for the location counter at the beginning | |
2085 | of a loop. */ | |
2086 | ||
c65ebc55 JW |
2087 | /* #define LOOP_ALIGN(LABEL) */ |
2088 | ||
2089 | /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text | |
2090 | section because it fails put zeros in the bytes that are skipped. */ | |
2091 | ||
2092 | #define ASM_NO_SKIP_IN_TEXT 1 | |
2093 | ||
2094 | /* A C statement to output to the stdio stream STREAM an assembler command to | |
2095 | advance the location counter to a multiple of 2 to the POWER bytes. */ | |
2096 | ||
2097 | #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ | |
2098 | fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) | |
2099 | ||
2100 | \f | |
2101 | /* Macros Affecting all Debug Formats. */ | |
2102 | ||
2103 | /* This is handled in svr4.h and sysv4.h. */ | |
2104 | ||
2105 | \f | |
2106 | /* Specific Options for DBX Output. */ | |
2107 | ||
2108 | /* This is handled by dbxelf.h which is included by svr4.h. */ | |
2109 | ||
2110 | \f | |
2111 | /* Open ended Hooks for DBX Output. */ | |
2112 | ||
2113 | /* Likewise. */ | |
2114 | ||
2115 | \f | |
2116 | /* File names in DBX format. */ | |
2117 | ||
2118 | /* Likewise. */ | |
2119 | ||
2120 | \f | |
2121 | /* Macros for SDB and Dwarf Output. */ | |
2122 | ||
7ec022b2 | 2123 | /* Define this macro if GCC should produce dwarf version 2 format debugging |
c65ebc55 JW |
2124 | output in response to the `-g' option. */ |
2125 | ||
23532de9 | 2126 | #define DWARF2_DEBUGGING_INFO 1 |
c65ebc55 | 2127 | |
c65ebc55 JW |
2128 | #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) |
2129 | ||
8215347e JW |
2130 | /* Use tags for debug info labels, so that they don't break instruction |
2131 | bundles. This also avoids getting spurious DV warnings from the | |
4977bab6 | 2132 | assembler. This is similar to (*targetm.asm_out.internal_label), except that we |
8215347e JW |
2133 | add brackets around the label. */ |
2134 | ||
2135 | #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
7426e9a2 | 2136 | fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM) |
8215347e | 2137 | |
7426e9a2 | 2138 | /* Use section-relative relocations for debugging offsets. Unlike other |
5b8fcab6 | 2139 | targets that fake this by putting the section VMA at 0, IA-64 has |
7426e9a2 RH |
2140 | proper relocations for them. */ |
2141 | #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \ | |
2142 | do { \ | |
301d03af | 2143 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
7426e9a2 RH |
2144 | fputs ("@secrel(", FILE); \ |
2145 | assemble_name (FILE, LABEL); \ | |
2146 | fputc (')', FILE); \ | |
2147 | } while (0) | |
2148 | ||
2149 | /* Emit a PC-relative relocation. */ | |
2150 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
2151 | do { \ | |
301d03af | 2152 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
7426e9a2 RH |
2153 | fputs ("@pcrel(", FILE); \ |
2154 | assemble_name (FILE, LABEL); \ | |
2155 | fputc (')', FILE); \ | |
2156 | } while (0) | |
7b82b5da SC |
2157 | \f |
2158 | /* Register Renaming Parameters. */ | |
2159 | ||
2160 | /* A C expression that is nonzero if hard register number REGNO2 can be | |
2161 | considered for use as a rename register for REGNO1 */ | |
2162 | ||
2163 | #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ | |
10c9f189 | 2164 | ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) |
7b82b5da | 2165 | |
c65ebc55 JW |
2166 | \f |
2167 | /* Miscellaneous Parameters. */ | |
2168 | ||
a32767e4 DM |
2169 | /* Flag to mark data that is in the small address area (addressable |
2170 | via "addl", that is, within a 2MByte offset of 0. */ | |
2171 | #define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2172 | #define SYMBOL_REF_SMALL_ADDR_P(X) \ | |
2173 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) | |
2174 | ||
c65ebc55 JW |
2175 | /* Define this if you have defined special-purpose predicates in the file |
2176 | `MACHINE.c'. For each predicate, list all rtl codes that can be in | |
2177 | expressions matched by the predicate. */ | |
2178 | ||
2179 | #define PREDICATE_CODES \ | |
2180 | { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \ | |
ec039e3c | 2181 | { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
c65ebc55 | 2182 | { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \ |
a32767e4 | 2183 | { "small_addr_symbolic_operand", {SYMBOL_REF}}, \ |
c65ebc55 JW |
2184 | { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
2185 | { "function_operand", {SYMBOL_REF}}, \ | |
2186 | { "setjmp_operand", {SYMBOL_REF}}, \ | |
4b983fdc | 2187 | { "destination_operand", {SUBREG, REG, MEM}}, \ |
0551c32d | 2188 | { "not_postinc_memory_operand", {MEM}}, \ |
c65ebc55 JW |
2189 | { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
2190 | CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \ | |
0551c32d RH |
2191 | { "gr_register_operand", {SUBREG, REG}}, \ |
2192 | { "fr_register_operand", {SUBREG, REG}}, \ | |
2193 | { "grfr_register_operand", {SUBREG, REG}}, \ | |
2194 | { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ | |
655f2eb9 | 2195 | { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ |
0551c32d RH |
2196 | { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ |
2197 | { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
2198 | { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2199 | { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2200 | { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2201 | { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2202 | { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \ | |
c65ebc55 | 2203 | CONSTANT_P_RTX}}, \ |
0551c32d | 2204 | { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \ |
c65ebc55 | 2205 | CONSTANT_P_RTX}}, \ |
0551c32d RH |
2206 | { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ |
2207 | { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
c65ebc55 JW |
2208 | { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ |
2209 | { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \ | |
2210 | CONSTANT_P_RTX}}, \ | |
2211 | { "shladd_operand", {CONST_INT}}, \ | |
2212 | { "fetchadd_operand", {CONST_INT}}, \ | |
0551c32d | 2213 | { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |
c65ebc55 JW |
2214 | { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \ |
2215 | { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \ | |
f2f90c63 | 2216 | { "signed_inequality_operator", {GE, GT, LE, LT}}, \ |
5527bf14 | 2217 | { "predicate_operator", {NE, EQ}}, \ |
acb0638d | 2218 | { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \ |
97e242b0 | 2219 | { "ar_lc_reg_operand", {REG}}, \ |
3f622353 | 2220 | { "ar_ccv_reg_operand", {REG}}, \ |
6ca3c22f | 2221 | { "ar_pfs_reg_operand", {REG}}, \ |
3f622353 RH |
2222 | { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ |
2223 | { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ | |
e206a74f SE |
2224 | { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \ |
2225 | { "basereg_operand", {SUBREG, REG}}, | |
c65ebc55 JW |
2226 | |
2227 | /* An alias for a machine mode name. This is the machine mode that elements of | |
2228 | a jump-table should have. */ | |
2229 | ||
03d0dce1 | 2230 | #define CASE_VECTOR_MODE ptr_mode |
c65ebc55 JW |
2231 | |
2232 | /* Define as C expression which evaluates to nonzero if the tablejump | |
2233 | instruction expects the table to contain offsets from the address of the | |
2234 | table. */ | |
2235 | ||
2236 | #define CASE_VECTOR_PC_RELATIVE 1 | |
2237 | ||
2238 | /* Define this macro if operations between registers with integral mode smaller | |
2239 | than a word are always performed on the entire register. */ | |
2240 | ||
2241 | #define WORD_REGISTER_OPERATIONS | |
2242 | ||
2243 | /* Define this macro to be a C expression indicating when insns that read | |
2244 | memory in MODE, an integral mode narrower than a word, set the bits outside | |
2245 | of MODE to be either the sign-extension or the zero-extension of the data | |
2246 | read. */ | |
2247 | ||
2248 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
2249 | ||
c65ebc55 JW |
2250 | /* The maximum number of bytes that a single instruction can move quickly from |
2251 | memory to memory. */ | |
2252 | #define MOVE_MAX 8 | |
2253 | ||
2254 | /* A C expression which is nonzero if on this machine it is safe to "convert" | |
2255 | an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller | |
2256 | than INPREC) by merely operating on it as if it had only OUTPREC bits. */ | |
2257 | ||
2258 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2259 | ||
2260 | /* A C expression describing the value returned by a comparison operator with | |
2261 | an integral mode and stored by a store-flag instruction (`sCOND') when the | |
2262 | condition is true. */ | |
2263 | ||
06f31100 | 2264 | /* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ |
c65ebc55 JW |
2265 | |
2266 | /* An alias for the machine mode for pointers. */ | |
2267 | ||
2268 | /* ??? This would change if we had ILP32 support. */ | |
2269 | ||
2270 | #define Pmode DImode | |
2271 | ||
2272 | /* An alias for the machine mode used for memory references to functions being | |
2273 | called, in `call' RTL expressions. */ | |
2274 | ||
2275 | #define FUNCTION_MODE Pmode | |
2276 | ||
2277 | /* Define this macro to handle System V style pragmas: #pragma pack and | |
2278 | #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is | |
2279 | defined. */ | |
2280 | ||
8527852a JJ |
2281 | /* If this architecture supports prefetch, define this to be the number of |
2282 | prefetch commands that can be executed in parallel. | |
2283 | ||
2284 | ??? This number is bogus and needs to be replaced before the value is | |
2285 | actually used in optimizations. */ | |
2286 | ||
2287 | #define SIMULTANEOUS_PREFETCHES 6 | |
2288 | ||
2289 | /* If this architecture supports prefetch, define this to be the size of | |
2290 | the cache line that is prefetched. */ | |
2291 | ||
2292 | #define PREFETCH_BLOCK 32 | |
2293 | ||
32f0ffb3 | 2294 | #define HANDLE_SYSV_PRAGMA 1 |
c65ebc55 | 2295 | |
c65ebc55 JW |
2296 | /* A C expression for the maximum number of instructions to execute via |
2297 | conditional execution instructions instead of a branch. A value of | |
2298 | BRANCH_COST+1 is the default if the machine does not use | |
2299 | cc0, and 1 if it does use cc0. */ | |
2300 | /* ??? Investigate. */ | |
2130b7fb BS |
2301 | #define MAX_CONDITIONAL_EXECUTE 12 |
2302 | ||
2130b7fb | 2303 | extern int ia64_final_schedule; |
c65ebc55 | 2304 | |
0c96007e | 2305 | #define IA64_UNWIND_INFO 1 |
0c96007e AM |
2306 | #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i) |
2307 | ||
2a1ee410 RH |
2308 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) |
2309 | ||
0c96007e | 2310 | /* This function contains machine specific function data. */ |
e2500fed | 2311 | struct machine_function GTY(()) |
0c96007e AM |
2312 | { |
2313 | /* The new stack pointer when unwinding from EH. */ | |
e2500fed | 2314 | rtx ia64_eh_epilogue_sp; |
0c96007e | 2315 | |
ed168e45 | 2316 | /* The new bsp value when unwinding from EH. */ |
e2500fed | 2317 | rtx ia64_eh_epilogue_bsp; |
97e242b0 RH |
2318 | |
2319 | /* The GP value save register. */ | |
e2500fed | 2320 | rtx ia64_gp_save; |
26a110f5 RH |
2321 | |
2322 | /* The number of varargs registers to save. */ | |
2323 | int n_varargs; | |
0c96007e AM |
2324 | }; |
2325 | ||
2326 | ||
c65ebc55 JW |
2327 | enum ia64_builtins |
2328 | { | |
2329 | IA64_BUILTIN_SYNCHRONIZE, | |
2330 | ||
2331 | IA64_BUILTIN_FETCH_AND_ADD_SI, | |
2332 | IA64_BUILTIN_FETCH_AND_SUB_SI, | |
2333 | IA64_BUILTIN_FETCH_AND_OR_SI, | |
2334 | IA64_BUILTIN_FETCH_AND_AND_SI, | |
2335 | IA64_BUILTIN_FETCH_AND_XOR_SI, | |
2336 | IA64_BUILTIN_FETCH_AND_NAND_SI, | |
2337 | ||
2338 | IA64_BUILTIN_ADD_AND_FETCH_SI, | |
2339 | IA64_BUILTIN_SUB_AND_FETCH_SI, | |
2340 | IA64_BUILTIN_OR_AND_FETCH_SI, | |
2341 | IA64_BUILTIN_AND_AND_FETCH_SI, | |
2342 | IA64_BUILTIN_XOR_AND_FETCH_SI, | |
2343 | IA64_BUILTIN_NAND_AND_FETCH_SI, | |
2344 | ||
2345 | IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI, | |
2346 | IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI, | |
2347 | ||
2348 | IA64_BUILTIN_SYNCHRONIZE_SI, | |
2349 | ||
2350 | IA64_BUILTIN_LOCK_TEST_AND_SET_SI, | |
2351 | ||
2352 | IA64_BUILTIN_LOCK_RELEASE_SI, | |
2353 | ||
2354 | IA64_BUILTIN_FETCH_AND_ADD_DI, | |
2355 | IA64_BUILTIN_FETCH_AND_SUB_DI, | |
2356 | IA64_BUILTIN_FETCH_AND_OR_DI, | |
2357 | IA64_BUILTIN_FETCH_AND_AND_DI, | |
2358 | IA64_BUILTIN_FETCH_AND_XOR_DI, | |
2359 | IA64_BUILTIN_FETCH_AND_NAND_DI, | |
2360 | ||
2361 | IA64_BUILTIN_ADD_AND_FETCH_DI, | |
2362 | IA64_BUILTIN_SUB_AND_FETCH_DI, | |
2363 | IA64_BUILTIN_OR_AND_FETCH_DI, | |
2364 | IA64_BUILTIN_AND_AND_FETCH_DI, | |
2365 | IA64_BUILTIN_XOR_AND_FETCH_DI, | |
2366 | IA64_BUILTIN_NAND_AND_FETCH_DI, | |
2367 | ||
2368 | IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI, | |
2369 | IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI, | |
2370 | ||
2371 | IA64_BUILTIN_SYNCHRONIZE_DI, | |
2372 | ||
2373 | IA64_BUILTIN_LOCK_TEST_AND_SET_DI, | |
2374 | ||
ce152ef8 AM |
2375 | IA64_BUILTIN_LOCK_RELEASE_DI, |
2376 | ||
2377 | IA64_BUILTIN_BSP, | |
2378 | IA64_BUILTIN_FLUSHRS | |
c65ebc55 JW |
2379 | }; |
2380 | ||
ed168e45 | 2381 | /* Codes for expand_compare_and_swap and expand_swap_and_compare. */ |
c65ebc55 JW |
2382 | enum fetchop_code { |
2383 | IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP | |
2384 | }; | |
2385 | ||
5b8fcab6 DB |
2386 | #define DONT_USE_BUILTIN_SETJMP |
2387 | ||
2388 | /* Output any profiling code before the prologue. */ | |
2389 | ||
2390 | #undef PROFILE_BEFORE_PROLOGUE | |
2391 | #define PROFILE_BEFORE_PROLOGUE 1 | |
2392 | ||
30028c85 VM |
2393 | \f |
2394 | ||
2395 | /* Switch on code for querying unit reservations. */ | |
2396 | #define CPU_UNITS_QUERY 1 | |
2397 | ||
c65ebc55 | 2398 | /* End of ia64.h */ |