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e65271be | 1 | /* Definitions of target machine GNU compiler. IA-64 version. |
16c484c7 | 2 | Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
c65ebc55 JW |
23 | /* ??? Look at ABI group documents for list of preprocessor macros and |
24 | other features required for ABI compliance. */ | |
25 | ||
26 | /* ??? Functions containing a non-local goto target save many registers. Why? | |
27 | See for instance execute/920428-2.c. */ | |
28 | ||
c65ebc55 JW |
29 | /* ??? Add support for short data/bss sections. */ |
30 | ||
31 | \f | |
32 | /* Run-time target specifications */ | |
33 | ||
243a7070 DB |
34 | #define CPP_CPU_SPEC "\ |
35 | -Acpu=ia64 -Amachine=ia64 \ | |
36 | %{!ansi:%{!std=c*:%{!std=i*:-Dia64}}} -D__ia64 -D__ia64__" | |
37 | ||
38 | #define CC1_SPEC "%(cc1_cpu) " | |
c65ebc55 JW |
39 | |
40 | /* This declaration should be present. */ | |
41 | extern int target_flags; | |
42 | ||
43 | /* This series of macros is to allow compiler command arguments to enable or | |
44 | disable the use of optional features of the target machine. */ | |
45 | ||
46 | #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */ | |
47 | ||
48 | #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */ | |
49 | ||
50 | #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */ | |
51 | ||
52 | #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */ | |
53 | ||
54 | #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */ | |
55 | ||
ed168e45 | 56 | #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */ |
c65ebc55 | 57 | |
099dde21 | 58 | #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */ |
c65ebc55 | 59 | |
099dde21 | 60 | #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */ |
c65ebc55 | 61 | |
099dde21 | 62 | #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */ |
59da9a7d | 63 | |
099dde21 BS |
64 | #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */ |
65 | ||
66 | #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */ | |
59da9a7d | 67 | |
35d9f39d | 68 | #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */ |
655f2eb9 | 69 | |
35d9f39d | 70 | #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */ |
655f2eb9 | 71 | |
c65ebc55 JW |
72 | #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */ |
73 | ||
74 | #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) | |
75 | ||
76 | #define TARGET_GNU_AS (target_flags & MASK_GNU_AS) | |
77 | ||
78 | #define TARGET_GNU_LD (target_flags & MASK_GNU_LD) | |
79 | ||
80 | #define TARGET_NO_PIC (target_flags & MASK_NO_PIC) | |
81 | ||
82 | #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP) | |
83 | ||
6dd12198 SE |
84 | #define TARGET_ILP32 (target_flags & MASK_ILP32) |
85 | ||
099dde21 BS |
86 | #define TARGET_B_STEP (target_flags & MASK_B_STEP) |
87 | ||
c65ebc55 JW |
88 | #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES) |
89 | ||
90 | #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA) | |
91 | ||
59da9a7d JW |
92 | #define TARGET_CONST_GP (target_flags & MASK_CONST_GP) |
93 | ||
94 | #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC) | |
95 | ||
655f2eb9 RH |
96 | #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT) |
97 | ||
98 | #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR) | |
99 | ||
100 | #define TARGET_INLINE_DIV \ | |
101 | (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR)) | |
102 | ||
c65ebc55 JW |
103 | #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM) |
104 | ||
105 | /* This macro defines names of command options to set and clear bits in | |
106 | `target_flags'. Its definition is an initializer with a subgrouping for | |
107 | each command option. */ | |
108 | ||
59da9a7d | 109 | #define TARGET_SWITCHES \ |
c65ebc55 JW |
110 | { \ |
111 | { "big-endian", MASK_BIG_ENDIAN, \ | |
047142d3 | 112 | N_("Generate big endian code") }, \ |
c65ebc55 | 113 | { "little-endian", -MASK_BIG_ENDIAN, \ |
047142d3 | 114 | N_("Generate little endian code") }, \ |
c65ebc55 | 115 | { "gnu-as", MASK_GNU_AS, \ |
047142d3 | 116 | N_("Generate code for GNU as") }, \ |
c65ebc55 | 117 | { "no-gnu-as", -MASK_GNU_AS, \ |
047142d3 | 118 | N_("Generate code for Intel as") }, \ |
c65ebc55 | 119 | { "gnu-ld", MASK_GNU_LD, \ |
047142d3 | 120 | N_("Generate code for GNU ld") }, \ |
c65ebc55 | 121 | { "no-gnu-ld", -MASK_GNU_LD, \ |
047142d3 | 122 | N_("Generate code for Intel ld") }, \ |
c65ebc55 | 123 | { "no-pic", MASK_NO_PIC, \ |
047142d3 | 124 | N_("Generate code without GP reg") }, \ |
c65ebc55 | 125 | { "volatile-asm-stop", MASK_VOL_ASM_STOP, \ |
047142d3 | 126 | N_("Emit stop bits before and after volatile extended asms") }, \ |
c65ebc55 | 127 | { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \ |
047142d3 | 128 | N_("Don't emit stop bits before and after volatile extended asms") }, \ |
099dde21 BS |
129 | { "b-step", MASK_B_STEP, \ |
130 | N_("Emit code for Itanium (TM) processor B step")}, \ | |
c65ebc55 | 131 | { "register-names", MASK_REG_NAMES, \ |
047142d3 | 132 | N_("Use in/loc/out register names")}, \ |
c65ebc55 | 133 | { "no-sdata", MASK_NO_SDATA, \ |
047142d3 | 134 | N_("Disable use of sdata/scommon/sbss")}, \ |
c65ebc55 | 135 | { "sdata", -MASK_NO_SDATA, \ |
047142d3 | 136 | N_("Enable use of sdata/scommon/sbss")}, \ |
59da9a7d | 137 | { "constant-gp", MASK_CONST_GP, \ |
047142d3 | 138 | N_("gp is constant (but save/restore gp on indirect calls)") }, \ |
59da9a7d | 139 | { "auto-pic", MASK_AUTO_PIC, \ |
047142d3 | 140 | N_("Generate self-relocatable code") }, \ |
655f2eb9 RH |
141 | { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \ |
142 | N_("Generate inline division, optimize for latency") }, \ | |
143 | { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \ | |
144 | N_("Generate inline division, optimize for throughput") }, \ | |
c65ebc55 | 145 | { "dwarf2-asm", MASK_DWARF2_ASM, \ |
047142d3 | 146 | N_("Enable Dwarf 2 line debug info via GNU as")}, \ |
c65ebc55 | 147 | { "no-dwarf2-asm", -MASK_DWARF2_ASM, \ |
047142d3 | 148 | N_("Disable Dwarf 2 line debug info via GNU as")}, \ |
6dd12198 | 149 | SUBTARGET_SWITCHES \ |
c65ebc55 JW |
150 | { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \ |
151 | NULL } \ | |
152 | } | |
153 | ||
154 | /* Default target_flags if no switches are specified */ | |
155 | ||
156 | #ifndef TARGET_DEFAULT | |
157 | #define TARGET_DEFAULT MASK_DWARF2_ASM | |
158 | #endif | |
159 | ||
160 | #ifndef TARGET_CPU_DEFAULT | |
161 | #define TARGET_CPU_DEFAULT 0 | |
162 | #endif | |
163 | ||
6dd12198 SE |
164 | #ifndef SUBTARGET_SWITCHES |
165 | #define SUBTARGET_SWITCHES | |
166 | #endif | |
167 | ||
c65ebc55 JW |
168 | /* This macro is similar to `TARGET_SWITCHES' but defines names of command |
169 | options that have values. Its definition is an initializer with a | |
170 | subgrouping for each command option. */ | |
171 | ||
172 | extern const char *ia64_fixed_range_string; | |
173 | #define TARGET_OPTIONS \ | |
174 | { \ | |
175 | { "fixed-range=", &ia64_fixed_range_string, \ | |
c725bd79 | 176 | N_("Specify range of registers to make fixed")}, \ |
c65ebc55 JW |
177 | } |
178 | ||
c65ebc55 JW |
179 | /* Sometimes certain combinations of command options do not make sense on a |
180 | particular target machine. You can define a macro `OVERRIDE_OPTIONS' to | |
181 | take account of this. This macro, if defined, is executed once just after | |
182 | all the command options have been parsed. */ | |
183 | ||
184 | #define OVERRIDE_OPTIONS ia64_override_options () | |
185 | ||
186 | /* Some machines may desire to change what optimizations are performed for | |
187 | various optimization levels. This macro, if defined, is executed once just | |
188 | after the optimization level is determined and before the remainder of the | |
189 | command options have been parsed. Values set in this macro are used as the | |
190 | default values for the other command line options. */ | |
191 | ||
192 | /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */ | |
c65ebc55 JW |
193 | \f |
194 | /* Driver configuration */ | |
195 | ||
196 | /* A C string constant that tells the GNU CC driver program options to pass to | |
197 | CPP. It can also specify how to translate options you give to GNU CC into | |
198 | options for GNU CC to pass to the CPP. */ | |
199 | ||
200 | /* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */ | |
201 | /* ??? An alternative is to modify glimits.h to check for __LP64__ instead | |
202 | of checked for CPU specific defines. We could also get rid of all LONG_MAX | |
203 | defines in other tm.h files. */ | |
204 | #define CPP_SPEC \ | |
205 | "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \ | |
206 | -D__LONG_MAX__=9223372036854775807L" | |
207 | ||
6dd12198 | 208 | /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */ |
c65ebc55 JW |
209 | /* #define NO_BUILTIN_SIZE_TYPE */ |
210 | ||
6dd12198 | 211 | /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */ |
c65ebc55 JW |
212 | /* #define NO_BUILTIN_PTRDIFF_TYPE */ |
213 | ||
214 | /* A C string constant that tells the GNU CC driver program options to pass to | |
215 | `cc1'. It can also specify how to translate options you give to GNU CC into | |
216 | options for GNU CC to pass to the `cc1'. */ | |
217 | ||
ad5042df JJ |
218 | #undef CC1_SPEC |
219 | #define CC1_SPEC "%{G*}" | |
c65ebc55 JW |
220 | |
221 | /* A C string constant that tells the GNU CC driver program options to pass to | |
222 | `cc1plus'. It can also specify how to translate options you give to GNU CC | |
223 | into options for GNU CC to pass to the `cc1plus'. */ | |
224 | ||
225 | /* #define CC1PLUS_SPEC "" */ | |
c65ebc55 JW |
226 | \f |
227 | /* Storage Layout */ | |
228 | ||
229 | /* Define this macro to have the value 1 if the most significant bit in a byte | |
230 | has the lowest number; otherwise define it to have the value zero. */ | |
231 | ||
232 | #define BITS_BIG_ENDIAN 0 | |
233 | ||
c65ebc55 JW |
234 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
235 | ||
236 | /* Define this macro to have the value 1 if, in a multiword object, the most | |
237 | significant word has the lowest number. */ | |
238 | ||
239 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) | |
240 | ||
c65ebc55 JW |
241 | #if defined(__BIG_ENDIAN__) |
242 | #define LIBGCC2_WORDS_BIG_ENDIAN 1 | |
243 | #else | |
244 | #define LIBGCC2_WORDS_BIG_ENDIAN 0 | |
245 | #endif | |
246 | ||
c65ebc55 JW |
247 | #define BITS_PER_UNIT 8 |
248 | ||
c65ebc55 JW |
249 | #define BITS_PER_WORD 64 |
250 | ||
c65ebc55 JW |
251 | #define UNITS_PER_WORD 8 |
252 | ||
6dd12198 | 253 | #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) |
c65ebc55 | 254 | |
6dd12198 SE |
255 | /* A C expression whose value is zero if pointers that need to be extended |
256 | from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if | |
257 | they are zero-extended and negative one if there is an ptr_extend operation. | |
c65ebc55 JW |
258 | |
259 | You need not define this macro if the `POINTER_SIZE' is equal to the width | |
260 | of `Pmode'. */ | |
6dd12198 | 261 | /* Need this for 32 bit pointers, see hpux.h for setting it. */ |
c65ebc55 JW |
262 | /* #define POINTERS_EXTEND_UNSIGNED */ |
263 | ||
264 | /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and | |
265 | which has the specified mode and signedness is to be stored in a register. | |
266 | This macro is only called when TYPE is a scalar type. */ | |
c65ebc55 JW |
267 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
268 | do \ | |
269 | { \ | |
270 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
dcf6e674 RH |
271 | && GET_MODE_SIZE (MODE) < 4) \ |
272 | (MODE) = SImode; \ | |
c65ebc55 JW |
273 | } \ |
274 | while (0) | |
275 | ||
c65ebc55 JW |
276 | /* ??? ABI doesn't allow us to define this. */ |
277 | /* #define PROMOTE_FUNCTION_ARGS */ | |
278 | ||
c65ebc55 JW |
279 | /* ??? ABI doesn't allow us to define this. */ |
280 | /* #define PROMOTE_FUNCTION_RETURN */ | |
281 | ||
c65ebc55 JW |
282 | #define PARM_BOUNDARY 64 |
283 | ||
284 | /* Define this macro if you wish to preserve a certain alignment for the stack | |
285 | pointer. The definition is a C expression for the desired alignment | |
286 | (measured in bits). */ | |
287 | ||
288 | #define STACK_BOUNDARY 128 | |
289 | ||
290 | /* Align frames on double word boundaries */ | |
291 | #ifndef IA64_STACK_ALIGN | |
292 | #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) | |
293 | #endif | |
294 | ||
c65ebc55 JW |
295 | #define FUNCTION_BOUNDARY 128 |
296 | ||
c65ebc55 JW |
297 | /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word |
298 | 128 bit integers all require 128 bit alignment. */ | |
299 | #define BIGGEST_ALIGNMENT 128 | |
300 | ||
301 | /* If defined, a C expression to compute the alignment for a static variable. | |
302 | TYPE is the data type, and ALIGN is the alignment that the object | |
303 | would ordinarily have. The value of this macro is used instead of that | |
304 | alignment to align the object. */ | |
305 | ||
306 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
307 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
308 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
309 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
310 | ||
311 | /* If defined, a C expression to compute the alignment given to a constant that | |
312 | is being placed in memory. CONSTANT is the constant and ALIGN is the | |
313 | alignment that the object would ordinarily have. The value of this macro is | |
314 | used instead of that alignment to align the object. */ | |
315 | ||
316 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
317 | (TREE_CODE (EXP) == STRING_CST \ | |
318 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
319 | ||
c65ebc55 JW |
320 | #define STRICT_ALIGNMENT 1 |
321 | ||
322 | /* Define this if you wish to imitate the way many other C compilers handle | |
323 | alignment of bitfields and the structures that contain them. | |
324 | The behavior is that the type written for a bitfield (`int', `short', or | |
325 | other integer type) imposes an alignment for the entire structure, as if the | |
326 | structure really did contain an ordinary field of that type. In addition, | |
327 | the bitfield is placed within the structure so that it would fit within such | |
328 | a field, not crossing a boundary for it. */ | |
329 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
330 | ||
c65ebc55 JW |
331 | /* An integer expression for the size in bits of the largest integer machine |
332 | mode that should actually be used. */ | |
333 | ||
334 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
335 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
336 | ||
337 | /* A code distinguishing the floating point format of the target machine. */ | |
338 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT | |
339 | ||
67231816 RH |
340 | /* By default, the C++ compiler will use function addresses in the |
341 | vtable entries. Setting this non-zero tells the compiler to use | |
342 | function descriptors instead. The value of this macro says how | |
343 | many words wide the descriptor is (normally 2). It is assumed | |
344 | that the address of a function descriptor may be treated as a | |
345 | pointer to a function. */ | |
346 | #define TARGET_VTABLE_USES_DESCRIPTORS 2 | |
c65ebc55 JW |
347 | \f |
348 | /* Layout of Source Language Data Types */ | |
349 | ||
c65ebc55 JW |
350 | #define INT_TYPE_SIZE 32 |
351 | ||
c65ebc55 JW |
352 | #define SHORT_TYPE_SIZE 16 |
353 | ||
6dd12198 | 354 | #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) |
c65ebc55 | 355 | |
6dd12198 | 356 | #define MAX_LONG_TYPE_SIZE 64 |
c65ebc55 | 357 | |
c65ebc55 JW |
358 | #define LONG_LONG_TYPE_SIZE 64 |
359 | ||
c65ebc55 JW |
360 | #define CHAR_TYPE_SIZE 8 |
361 | ||
c65ebc55 JW |
362 | #define FLOAT_TYPE_SIZE 32 |
363 | ||
c65ebc55 JW |
364 | #define DOUBLE_TYPE_SIZE 64 |
365 | ||
3f622353 RH |
366 | #define LONG_DOUBLE_TYPE_SIZE 128 |
367 | ||
368 | /* Tell real.c that this is the 80-bit Intel extended float format | |
369 | packaged in a 128-bit entity. */ | |
23c108af SE |
370 | |
371 | #define INTEL_EXTENDED_IEEE_FORMAT 1 | |
c65ebc55 | 372 | |
c65ebc55 JW |
373 | #define DEFAULT_SIGNED_CHAR 1 |
374 | ||
375 | /* A C expression for a string describing the name of the data type to use for | |
376 | size values. The typedef name `size_t' is defined using the contents of the | |
377 | string. */ | |
378 | /* ??? Needs to be defined for P64 code. */ | |
379 | /* #define SIZE_TYPE */ | |
380 | ||
381 | /* A C expression for a string describing the name of the data type to use for | |
382 | the result of subtracting two pointers. The typedef name `ptrdiff_t' is | |
383 | defined using the contents of the string. See `SIZE_TYPE' above for more | |
384 | information. */ | |
385 | /* ??? Needs to be defined for P64 code. */ | |
386 | /* #define PTRDIFF_TYPE */ | |
387 | ||
388 | /* A C expression for a string describing the name of the data type to use for | |
389 | wide characters. The typedef name `wchar_t' is defined using the contents | |
390 | of the string. See `SIZE_TYPE' above for more information. */ | |
391 | /* #define WCHAR_TYPE */ | |
392 | ||
393 | /* A C expression for the size in bits of the data type for wide characters. | |
394 | This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ | |
395 | /* #define WCHAR_TYPE_SIZE */ | |
396 | ||
c65ebc55 JW |
397 | \f |
398 | /* Register Basics */ | |
399 | ||
400 | /* Number of hardware registers known to the compiler. | |
5527bf14 RH |
401 | We have 128 general registers, 128 floating point registers, |
402 | 64 predicate registers, 8 branch registers, one frame pointer, | |
403 | and several "application" registers. */ | |
c65ebc55 | 404 | |
97e242b0 | 405 | #define FIRST_PSEUDO_REGISTER 335 |
c65ebc55 JW |
406 | |
407 | /* Ranges for the various kinds of registers. */ | |
3b572406 RH |
408 | #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) |
409 | #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) | |
c65ebc55 JW |
410 | #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) |
411 | #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) | |
412 | #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) | |
413 | #define GENERAL_REGNO_P(REGNO) \ | |
414 | (GR_REGNO_P (REGNO) \ | |
415 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
46327bc5 | 416 | || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM) |
c65ebc55 JW |
417 | |
418 | #define GR_REG(REGNO) ((REGNO) + 0) | |
419 | #define FR_REG(REGNO) ((REGNO) + 128) | |
420 | #define PR_REG(REGNO) ((REGNO) + 256) | |
421 | #define BR_REG(REGNO) ((REGNO) + 320) | |
422 | #define OUT_REG(REGNO) ((REGNO) + 120) | |
423 | #define IN_REG(REGNO) ((REGNO) + 112) | |
424 | #define LOC_REG(REGNO) ((REGNO) + 32) | |
425 | ||
5527bf14 | 426 | #define AR_CCV_REGNUM 330 |
97e242b0 RH |
427 | #define AR_UNAT_REGNUM 331 |
428 | #define AR_PFS_REGNUM 332 | |
429 | #define AR_LC_REGNUM 333 | |
430 | #define AR_EC_REGNUM 334 | |
5527bf14 | 431 | |
c65ebc55 JW |
432 | #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) |
433 | #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) | |
434 | #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) | |
435 | ||
97e242b0 RH |
436 | #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ |
437 | || (REGNO) == AR_UNAT_REGNUM) | |
438 | #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ | |
5527bf14 RH |
439 | && (REGNO) < FIRST_PSEUDO_REGISTER) |
440 | #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ | |
441 | && (REGNO) < FIRST_PSEUDO_REGISTER) | |
442 | ||
443 | ||
c65ebc55 JW |
444 | /* ??? Don't really need two sets of macros. I like this one better because |
445 | it is less typing. */ | |
446 | #define R_GR(REGNO) GR_REG (REGNO) | |
447 | #define R_FR(REGNO) FR_REG (REGNO) | |
448 | #define R_PR(REGNO) PR_REG (REGNO) | |
449 | #define R_BR(REGNO) BR_REG (REGNO) | |
450 | ||
451 | /* An initializer that says which registers are used for fixed purposes all | |
452 | throughout the compiled code and are therefore not available for general | |
453 | allocation. | |
454 | ||
455 | r0: constant 0 | |
456 | r1: global pointer (gp) | |
457 | r12: stack pointer (sp) | |
458 | r13: thread pointer (tp) | |
459 | f0: constant 0.0 | |
460 | f1: constant 1.0 | |
461 | p0: constant true | |
462 | fp: eliminable frame pointer */ | |
463 | ||
1ff5b671 JW |
464 | /* The last 16 stacked regs are reserved for the 8 input and 8 output |
465 | registers. */ | |
c65ebc55 | 466 | |
c65ebc55 JW |
467 | #define FIXED_REGISTERS \ |
468 | { /* General registers. */ \ | |
469 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ | |
470 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
471 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
472 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
473 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
474 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
97e242b0 | 475 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1ff5b671 | 476 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
c65ebc55 JW |
477 | /* Floating-point registers. */ \ |
478 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
479 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
480 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
481 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
482 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
483 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
484 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
485 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
486 | /* Predicate registers. */ \ | |
487 | 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
488 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
489 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
490 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
491 | /* Branch registers. */ \ | |
492 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
97e242b0 RH |
493 | /*FP RA CCV UNAT PFS LC EC */ \ |
494 | 1, 1, 1, 1, 1, 0, 1 \ | |
c65ebc55 JW |
495 | } |
496 | ||
5527bf14 RH |
497 | /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered |
498 | (in general) by function calls as well as for fixed registers. This | |
499 | macro therefore identifies the registers that are not available for | |
500 | general allocation of values that must live across function calls. */ | |
c65ebc55 | 501 | |
c65ebc55 JW |
502 | #define CALL_USED_REGISTERS \ |
503 | { /* General registers. */ \ | |
504 | 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
505 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
506 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
507 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
508 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
509 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
97e242b0 | 510 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1ff5b671 | 511 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ |
c65ebc55 JW |
512 | /* Floating-point registers. */ \ |
513 | 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
514 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
515 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
516 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
517 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
518 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
519 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
520 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
521 | /* Predicate registers. */ \ | |
522 | 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
523 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
524 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
525 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
526 | /* Branch registers. */ \ | |
527 | 1, 0, 0, 0, 0, 0, 1, 1, \ | |
97e242b0 RH |
528 | /*FP RA CCV UNAT PFS LC EC */ \ |
529 | 1, 1, 1, 1, 1, 0, 1 \ | |
c65ebc55 JW |
530 | } |
531 | ||
fc1296b7 AM |
532 | /* Like `CALL_USED_REGISTERS' but used to overcome a historical |
533 | problem which makes CALL_USED_REGISTERS *always* include | |
6ca3c22f | 534 | all the FIXED_REGISTERS. Until this problem has been |
fc1296b7 AM |
535 | resolved this macro can be used to overcome this situation. |
536 | In particular, block_propagate() requires this list | |
537 | be acurate, or we can remove registers which should be live. | |
6ca3c22f | 538 | This macro is used in regs_invalidated_by_call. */ |
fc1296b7 AM |
539 | |
540 | #define CALL_REALLY_USED_REGISTERS \ | |
541 | { /* General registers. */ \ | |
542 | 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \ | |
543 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
544 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
545 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
546 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
547 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
548 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
549 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
550 | /* Floating-point registers. */ \ | |
551 | 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
552 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
553 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
554 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
555 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
556 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
557 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
558 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
559 | /* Predicate registers. */ \ | |
560 | 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
561 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
562 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
563 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
564 | /* Branch registers. */ \ | |
565 | 1, 0, 0, 0, 0, 0, 1, 1, \ | |
566 | /*FP RA CCV UNAT PFS LC EC */ \ | |
6ca3c22f | 567 | 0, 0, 1, 0, 1, 0, 0 \ |
fc1296b7 AM |
568 | } |
569 | ||
570 | ||
c65ebc55 JW |
571 | /* Define this macro if the target machine has register windows. This C |
572 | expression returns the register number as seen by the called function | |
573 | corresponding to the register number OUT as seen by the calling function. | |
574 | Return OUT if register number OUT is not an outbound register. */ | |
575 | ||
576 | #define INCOMING_REGNO(OUT) \ | |
577 | ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) | |
578 | ||
579 | /* Define this macro if the target machine has register windows. This C | |
580 | expression returns the register number as seen by the calling function | |
581 | corresponding to the register number IN as seen by the called function. | |
582 | Return IN if register number IN is not an inbound register. */ | |
583 | ||
584 | #define OUTGOING_REGNO(IN) \ | |
585 | ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) | |
586 | ||
2a3e384f RH |
587 | /* Define this macro if the target machine has register windows. This |
588 | C expression returns true if the register is call-saved but is in the | |
589 | register window. */ | |
590 | ||
591 | #define LOCAL_REGNO(REGNO) \ | |
592 | (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) | |
97e242b0 RH |
593 | |
594 | /* Add any extra modes needed to represent the condition code. | |
595 | ||
596 | CCImode is used to mark a single predicate register instead | |
597 | of a register pair. This is currently only used in reg_raw_mode | |
598 | so that flow doesn't do something stupid. */ | |
599 | ||
600 | #define EXTRA_CC_MODES CC(CCImode, "CCI") | |
601 | ||
602 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
603 | return the mode to be used for the comparison. Must be defined if | |
604 | EXTRA_CC_MODES is defined. */ | |
605 | ||
606 | #define SELECT_CC_MODE(OP,X,Y) CCmode | |
c65ebc55 JW |
607 | \f |
608 | /* Order of allocation of registers */ | |
609 | ||
610 | /* If defined, an initializer for a vector of integers, containing the numbers | |
611 | of hard registers in the order in which GNU CC should prefer to use them | |
612 | (from most preferred to least). | |
613 | ||
614 | If this macro is not defined, registers are used lowest numbered first (all | |
615 | else being equal). | |
616 | ||
617 | One use of this macro is on machines where the highest numbered registers | |
618 | must always be saved and the save-multiple-registers instruction supports | |
619 | only sequences of consecutive registers. On such machines, define | |
620 | `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered | |
621 | allocatable register first. */ | |
622 | ||
623 | /* ??? Should the GR return value registers come before or after the rest | |
624 | of the caller-save GRs? */ | |
625 | ||
97e242b0 | 626 | #define REG_ALLOC_ORDER \ |
c65ebc55 JW |
627 | { \ |
628 | /* Caller-saved general registers. */ \ | |
97e242b0 RH |
629 | R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ |
630 | R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ | |
631 | R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ | |
c65ebc55 | 632 | R_GR (30), R_GR (31), \ |
1ff5b671 JW |
633 | /* Output registers. */ \ |
634 | R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ | |
97e242b0 | 635 | R_GR (126), R_GR (127), \ |
c65ebc55 | 636 | /* Caller-saved general registers, also used for return values. */ \ |
97e242b0 | 637 | R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ |
c65ebc55 JW |
638 | /* addl caller-saved general registers. */ \ |
639 | R_GR (2), R_GR (3), \ | |
640 | /* Caller-saved FP registers. */ \ | |
641 | R_FR (6), R_FR (7), \ | |
642 | /* Caller-saved FP registers, used for parameters and return values. */ \ | |
97e242b0 RH |
643 | R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ |
644 | R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ | |
c65ebc55 | 645 | /* Rotating caller-saved FP registers. */ \ |
97e242b0 RH |
646 | R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ |
647 | R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ | |
648 | R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ | |
649 | R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ | |
650 | R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ | |
651 | R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ | |
652 | R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ | |
653 | R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ | |
654 | R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ | |
655 | R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ | |
656 | R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ | |
657 | R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ | |
c65ebc55 JW |
658 | R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ |
659 | R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ | |
660 | R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ | |
661 | R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ | |
97e242b0 | 662 | R_FR (126), R_FR (127), \ |
c65ebc55 | 663 | /* Caller-saved predicate registers. */ \ |
97e242b0 | 664 | R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ |
c65ebc55 JW |
665 | R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ |
666 | /* Rotating caller-saved predicate registers. */ \ | |
97e242b0 RH |
667 | R_PR (16), R_PR (17), \ |
668 | R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ | |
669 | R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ | |
670 | R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ | |
671 | R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ | |
672 | R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ | |
673 | R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ | |
674 | R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ | |
675 | R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ | |
c65ebc55 JW |
676 | /* Caller-saved branch registers. */ \ |
677 | R_BR (6), R_BR (7), \ | |
678 | \ | |
679 | /* Stacked callee-saved general registers. */ \ | |
97e242b0 RH |
680 | R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ |
681 | R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ | |
682 | R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ | |
683 | R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ | |
684 | R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ | |
685 | R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ | |
686 | R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ | |
687 | R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ | |
688 | R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ | |
689 | R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ | |
690 | R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ | |
691 | R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ | |
c65ebc55 JW |
692 | R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ |
693 | R_GR (108), \ | |
1ff5b671 JW |
694 | /* Input registers. */ \ |
695 | R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ | |
696 | R_GR (118), R_GR (119), \ | |
c65ebc55 JW |
697 | /* Callee-saved general registers. */ \ |
698 | R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ | |
699 | /* Callee-saved FP registers. */ \ | |
97e242b0 RH |
700 | R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ |
701 | R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ | |
702 | R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ | |
c65ebc55 JW |
703 | R_FR (30), R_FR (31), \ |
704 | /* Callee-saved predicate registers. */ \ | |
97e242b0 | 705 | R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ |
c65ebc55 JW |
706 | /* Callee-saved branch registers. */ \ |
707 | R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ | |
708 | \ | |
709 | /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ | |
710 | R_GR (109), R_GR (110), R_GR (111), \ | |
c65ebc55 JW |
711 | \ |
712 | /* Special general registers. */ \ | |
97e242b0 | 713 | R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ |
c65ebc55 JW |
714 | /* Special FP registers. */ \ |
715 | R_FR (0), R_FR (1), \ | |
716 | /* Special predicate registers. */ \ | |
717 | R_PR (0), \ | |
718 | /* Special branch registers. */ \ | |
719 | R_BR (0), \ | |
5527bf14 | 720 | /* Other fixed registers. */ \ |
46327bc5 | 721 | FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \ |
97e242b0 RH |
722 | AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ |
723 | AR_EC_REGNUM \ | |
c65ebc55 | 724 | } |
c65ebc55 JW |
725 | \f |
726 | /* How Values Fit in Registers */ | |
727 | ||
728 | /* A C expression for the number of consecutive hard registers, starting at | |
729 | register number REGNO, required to hold a value of mode MODE. */ | |
730 | ||
f2f90c63 | 731 | /* ??? We say that BImode PR values require two registers. This allows us to |
97e242b0 RH |
732 | easily store the normal and inverted values. We use CCImode to indicate |
733 | a single predicate register. */ | |
c65ebc55 | 734 | |
97e242b0 RH |
735 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
736 | ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ | |
f2f90c63 | 737 | : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ |
97e242b0 | 738 | : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ |
23c108af | 739 | : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \ |
c65ebc55 JW |
740 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
741 | ||
742 | /* A C expression that is nonzero if it is permissible to store a value of mode | |
743 | MODE in hard register number REGNO (or in several registers starting with | |
744 | that one). */ | |
0ea1e106 | 745 | |
f2f90c63 RH |
746 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
747 | (FR_REGNO_P (REGNO) ? \ | |
23c108af SE |
748 | GET_MODE_CLASS (MODE) != MODE_CC && \ |
749 | (MODE) != TImode && \ | |
750 | (MODE) != BImode && \ | |
751 | ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \ | |
f2f90c63 RH |
752 | : PR_REGNO_P (REGNO) ? \ |
753 | (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ | |
754 | : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \ | |
755 | : AR_REGNO_P (REGNO) ? (MODE) == DImode \ | |
756 | : BR_REGNO_P (REGNO) ? (MODE) == DImode \ | |
3f622353 | 757 | : 0) |
c65ebc55 JW |
758 | |
759 | /* A C expression that is nonzero if it is desirable to choose register | |
760 | allocation so as to avoid move instructions between a value of mode MODE1 | |
761 | and a value of mode MODE2. | |
762 | ||
763 | If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are | |
764 | ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be | |
765 | zero. */ | |
ad06f2e3 | 766 | /* Don't tie integer and FP modes, as that causes us to get integer registers |
3f622353 RH |
767 | allocated for FP instructions. TFmode only supported in FP registers so |
768 | we can't tie it with any other modes. */ | |
f2f90c63 RH |
769 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
770 | (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
771 | && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \ | |
772 | && (((MODE1) == BImode) == ((MODE2) == BImode))) | |
c65ebc55 JW |
773 | \f |
774 | /* Handling Leaf Functions */ | |
775 | ||
776 | /* A C initializer for a vector, indexed by hard register number, which | |
777 | contains 1 for a register that is allowable in a candidate for leaf function | |
778 | treatment. */ | |
779 | /* ??? This might be useful. */ | |
780 | /* #define LEAF_REGISTERS */ | |
781 | ||
782 | /* A C expression whose value is the register number to which REGNO should be | |
783 | renumbered, when a function is treated as a leaf function. */ | |
784 | /* ??? This might be useful. */ | |
785 | /* #define LEAF_REG_REMAP(REGNO) */ | |
786 | ||
787 | \f | |
788 | /* Register Classes */ | |
789 | ||
790 | /* An enumeral type that must be defined with all the register class names as | |
791 | enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last | |
792 | register class, followed by one more enumeral value, `LIM_REG_CLASSES', | |
793 | which is not a register class but rather tells how many classes there | |
794 | are. */ | |
c65ebc55 JW |
795 | /* ??? When compiling without optimization, it is possible for the only use of |
796 | a pseudo to be a parameter load from the stack with a REG_EQUIV note. | |
797 | Regclass handles this case specially and does not assign any costs to the | |
798 | pseudo. The pseudo then ends up using the last class before ALL_REGS. | |
799 | Thus we must not let either PR_REGS or BR_REGS be the last class. The | |
800 | testcase for this is gcc.c-torture/execute/va-arg-7.c. */ | |
801 | enum reg_class | |
802 | { | |
803 | NO_REGS, | |
804 | PR_REGS, | |
805 | BR_REGS, | |
7109d286 RH |
806 | AR_M_REGS, |
807 | AR_I_REGS, | |
c65ebc55 JW |
808 | ADDL_REGS, |
809 | GR_REGS, | |
c65ebc55 | 810 | FR_REGS, |
7109d286 | 811 | GR_AND_BR_REGS, |
c65ebc55 JW |
812 | GR_AND_FR_REGS, |
813 | ALL_REGS, | |
814 | LIM_REG_CLASSES | |
815 | }; | |
816 | ||
817 | #define GENERAL_REGS GR_REGS | |
818 | ||
819 | /* The number of distinct register classes. */ | |
820 | #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
821 | ||
822 | /* An initializer containing the names of the register classes as C string | |
823 | constants. These names are used in writing some of the debugging dumps. */ | |
824 | #define REG_CLASS_NAMES \ | |
7109d286 RH |
825 | { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ |
826 | "ADDL_REGS", "GR_REGS", "FR_REGS", \ | |
827 | "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } | |
c65ebc55 JW |
828 | |
829 | /* An initializer containing the contents of the register classes, as integers | |
830 | which are bit masks. The Nth integer specifies the contents of class N. | |
831 | The way the integer MASK is interpreted is that register R is in the class | |
832 | if `MASK & (1 << R)' is 1. */ | |
833 | #define REG_CLASS_CONTENTS \ | |
834 | { \ | |
835 | /* NO_REGS. */ \ | |
836 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
837 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 838 | 0x00000000, 0x00000000, 0x0000 }, \ |
c65ebc55 JW |
839 | /* PR_REGS. */ \ |
840 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
841 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 842 | 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ |
c65ebc55 JW |
843 | /* BR_REGS. */ \ |
844 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
845 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 846 | 0x00000000, 0x00000000, 0x00FF }, \ |
7109d286 RH |
847 | /* AR_M_REGS. */ \ |
848 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
849 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
850 | 0x00000000, 0x00000000, 0x0C00 }, \ | |
851 | /* AR_I_REGS. */ \ | |
852 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
853 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
854 | 0x00000000, 0x00000000, 0x7000 }, \ | |
c65ebc55 JW |
855 | /* ADDL_REGS. */ \ |
856 | { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ | |
857 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 858 | 0x00000000, 0x00000000, 0x0000 }, \ |
c65ebc55 JW |
859 | /* GR_REGS. */ \ |
860 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
861 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
5527bf14 | 862 | 0x00000000, 0x00000000, 0x0300 }, \ |
c65ebc55 JW |
863 | /* FR_REGS. */ \ |
864 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
865 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
5527bf14 | 866 | 0x00000000, 0x00000000, 0x0000 }, \ |
7109d286 RH |
867 | /* GR_AND_BR_REGS. */ \ |
868 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
869 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ | |
870 | 0x00000000, 0x00000000, 0x03FF }, \ | |
c65ebc55 JW |
871 | /* GR_AND_FR_REGS. */ \ |
872 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
873 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
5527bf14 | 874 | 0x00000000, 0x00000000, 0x0300 }, \ |
c65ebc55 JW |
875 | /* ALL_REGS. */ \ |
876 | { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
877 | 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ | |
97e242b0 | 878 | 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \ |
c65ebc55 JW |
879 | } |
880 | ||
881 | /* A C expression whose value is a register class containing hard register | |
882 | REGNO. In general there is more than one such class; choose a class which | |
883 | is "minimal", meaning that no smaller class also contains the register. */ | |
884 | /* The NO_REGS case is primarily for the benefit of rws_access_reg, which | |
885 | may call here with private (invalid) register numbers, such as | |
886 | REG_VOLATILE. */ | |
887 | #define REGNO_REG_CLASS(REGNO) \ | |
888 | (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ | |
889 | : GENERAL_REGNO_P (REGNO) ? GR_REGS \ | |
13da91fd | 890 | : FR_REGNO_P (REGNO) ? FR_REGS \ |
c65ebc55 JW |
891 | : PR_REGNO_P (REGNO) ? PR_REGS \ |
892 | : BR_REGNO_P (REGNO) ? BR_REGS \ | |
97e242b0 RH |
893 | : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ |
894 | : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ | |
c65ebc55 JW |
895 | : NO_REGS) |
896 | ||
897 | /* A macro whose definition is the name of the class to which a valid base | |
898 | register must belong. A base register is one used in an address which is | |
899 | the register value plus a displacement. */ | |
900 | #define BASE_REG_CLASS GENERAL_REGS | |
901 | ||
902 | /* A macro whose definition is the name of the class to which a valid index | |
903 | register must belong. An index register is one used in an address where its | |
904 | value is either multiplied by a scale factor or added to another register | |
cf606f45 JW |
905 | (as well as added to a displacement). This is needed for POST_MODIFY. */ |
906 | #define INDEX_REG_CLASS GENERAL_REGS | |
c65ebc55 JW |
907 | |
908 | /* A C expression which defines the machine-dependent operand constraint | |
909 | letters for register classes. If CHAR is such a letter, the value should be | |
910 | the register class corresponding to it. Otherwise, the value should be | |
911 | `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS', | |
912 | will not be passed to this macro; you do not need to handle it. */ | |
913 | ||
914 | #define REG_CLASS_FROM_LETTER(CHAR) \ | |
13da91fd | 915 | ((CHAR) == 'f' ? FR_REGS \ |
c65ebc55 JW |
916 | : (CHAR) == 'a' ? ADDL_REGS \ |
917 | : (CHAR) == 'b' ? BR_REGS \ | |
918 | : (CHAR) == 'c' ? PR_REGS \ | |
5527bf14 RH |
919 | : (CHAR) == 'd' ? AR_M_REGS \ |
920 | : (CHAR) == 'e' ? AR_I_REGS \ | |
c65ebc55 JW |
921 | : NO_REGS) |
922 | ||
923 | /* A C expression which is nonzero if register number NUM is suitable for use | |
924 | as a base register in operand addresses. It may be either a suitable hard | |
925 | register or a pseudo register that has been allocated such a hard reg. */ | |
926 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
927 | (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) | |
928 | ||
929 | /* A C expression which is nonzero if register number NUM is suitable for use | |
930 | as an index register in operand addresses. It may be either a suitable hard | |
cf606f45 JW |
931 | register or a pseudo register that has been allocated such a hard reg. |
932 | This is needed for POST_MODIFY. */ | |
933 | #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) | |
c65ebc55 JW |
934 | |
935 | /* A C expression that places additional restrictions on the register class to | |
936 | use when it is necessary to copy value X into a register in class CLASS. | |
937 | The value is a register class; perhaps CLASS, or perhaps another, smaller | |
938 | class. */ | |
939 | ||
ffaff414 JW |
940 | /* Don't allow volatile mem reloads into floating point registers. This |
941 | is defined to force reload to choose the r/m case instead of the f/f case | |
f2f90c63 RH |
942 | when reloading (set (reg fX) (mem/v)). |
943 | ||
944 | Do not reload expressions into AR regs. */ | |
ffaff414 JW |
945 | |
946 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
f2f90c63 | 947 | (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \ |
036099eb | 948 | : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \ |
7109d286 RH |
949 | : GET_RTX_CLASS (GET_CODE (X)) != 'o' \ |
950 | && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \ | |
ffaff414 | 951 | : CLASS) |
c65ebc55 JW |
952 | |
953 | /* You should define this macro to indicate to the reload phase that it may | |
954 | need to allocate at least one register for a reload in addition to the | |
955 | register to contain the data. Specifically, if copying X to a register | |
956 | CLASS in MODE requires an intermediate register, you should define this | |
957 | to return the largest register class all of whose registers can be used | |
958 | as intermediate registers or scratch registers. */ | |
959 | ||
960 | #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ | |
961 | ia64_secondary_reload_class (CLASS, MODE, X) | |
962 | ||
963 | /* Certain machines have the property that some registers cannot be copied to | |
964 | some other registers without using memory. Define this macro on those | |
965 | machines to be a C expression that is non-zero if objects of mode M in | |
966 | registers of CLASS1 can only be copied to registers of class CLASS2 by | |
967 | storing a register of CLASS1 into memory and loading that memory location | |
968 | into a register of CLASS2. */ | |
3f622353 RH |
969 | |
970 | #if 0 | |
971 | /* ??? May need this, but since we've disallowed TFmode in GR_REGS, | |
972 | I'm not quite sure how it could be invoked. The normal problems | |
973 | with unions should be solved with the addressof fiddling done by | |
974 | movtf and friends. */ | |
975 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
976 | ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ | |
977 | || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) | |
978 | #endif | |
c65ebc55 JW |
979 | |
980 | /* A C expression for the maximum number of consecutive registers of | |
981 | class CLASS needed to hold a value of mode MODE. | |
982 | This is closely related to the macro `HARD_REGNO_NREGS'. */ | |
983 | ||
984 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
f2f90c63 | 985 | ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ |
3f622353 | 986 | : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \ |
c65ebc55 JW |
987 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
988 | ||
02188693 RH |
989 | /* If defined, gives a class of registers that cannot be used as the |
990 | operand of a SUBREG that changes the mode of the object illegally. */ | |
991 | ||
992 | #define CLASS_CANNOT_CHANGE_MODE FR_REGS | |
993 | ||
46146529 JW |
994 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. |
995 | In FP regs, we can't change FP values to integer values and vice | |
996 | versa, but we can change e.g. DImode to SImode. */ | |
02188693 | 997 | |
46146529 JW |
998 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ |
999 | (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO)) | |
02188693 | 1000 | |
97e242b0 RH |
1001 | /* A C expression that defines the machine-dependent operand constraint |
1002 | letters (`I', `J', `K', .. 'P') that specify particular ranges of | |
1003 | integer values. */ | |
c65ebc55 JW |
1004 | |
1005 | /* 14 bit signed immediate for arithmetic instructions. */ | |
1006 | #define CONST_OK_FOR_I(VALUE) \ | |
1007 | ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000) | |
1008 | /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */ | |
1009 | #define CONST_OK_FOR_J(VALUE) \ | |
1010 | ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000) | |
1011 | /* 8 bit signed immediate for logical instructions. */ | |
1012 | #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100) | |
1013 | /* 8 bit adjusted signed immediate for compare pseudo-ops. */ | |
1014 | #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100) | |
1015 | /* 6 bit unsigned immediate for shift counts. */ | |
1016 | #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40) | |
1017 | /* 9 bit signed immediate for load/store post-increments. */ | |
c65ebc55 JW |
1018 | #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200) |
1019 | /* 0 for r0. Used by Linux kernel, do not change. */ | |
1020 | #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0) | |
1021 | /* 0 or -1 for dep instruction. */ | |
1022 | #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1) | |
1023 | ||
1024 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
1025 | ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ | |
1026 | : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ | |
1027 | : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ | |
1028 | : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ | |
1029 | : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ | |
1030 | : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ | |
1031 | : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ | |
1032 | : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ | |
1033 | : 0) | |
1034 | ||
1035 | /* A C expression that defines the machine-dependent operand constraint letters | |
1036 | (`G', `H') that specify particular ranges of `const_double' values. */ | |
1037 | ||
1038 | /* 0.0 and 1.0 for fr0 and fr1. */ | |
1039 | #define CONST_DOUBLE_OK_FOR_G(VALUE) \ | |
1040 | ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \ | |
1041 | || (VALUE) == CONST1_RTX (GET_MODE (VALUE))) | |
1042 | ||
1043 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
1044 | ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0) | |
1045 | ||
1046 | /* A C expression that defines the optional machine-dependent constraint | |
1047 | letters (`Q', `R', `S', `T', `U') that can be used to segregate specific | |
1048 | types of operands, usually memory references, for the target machine. */ | |
3b572406 | 1049 | |
041f25e6 | 1050 | /* Non-volatile memory for FP_REG loads/stores. */ |
3b572406 RH |
1051 | #define CONSTRAINT_OK_FOR_Q(VALUE) \ |
1052 | (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE)) | |
041f25e6 RH |
1053 | /* 1..4 for shladd arguments. */ |
1054 | #define CONSTRAINT_OK_FOR_R(VALUE) \ | |
1055 | (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4) | |
0551c32d RH |
1056 | /* Non-post-inc memory for asms and other unsavory creatures. */ |
1057 | #define CONSTRAINT_OK_FOR_S(VALUE) \ | |
1058 | (GET_CODE (VALUE) == MEM \ | |
1059 | && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \ | |
1060 | && (reload_in_progress || memory_operand ((VALUE), VOIDmode))) | |
3b572406 RH |
1061 | |
1062 | #define EXTRA_CONSTRAINT(VALUE, C) \ | |
041f25e6 RH |
1063 | ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \ |
1064 | : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \ | |
0551c32d | 1065 | : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \ |
041f25e6 | 1066 | : 0) |
c65ebc55 JW |
1067 | \f |
1068 | /* Basic Stack Layout */ | |
1069 | ||
1070 | /* Define this macro if pushing a word onto the stack moves the stack pointer | |
1071 | to a smaller address. */ | |
1072 | #define STACK_GROWS_DOWNWARD 1 | |
1073 | ||
1074 | /* Define this macro if the addresses of local variable slots are at negative | |
1075 | offsets from the frame pointer. */ | |
97e242b0 RH |
1076 | /* #define FRAME_GROWS_DOWNWARD */ |
1077 | ||
1078 | /* Offset from the frame pointer to the first local variable slot to | |
1079 | be allocated. */ | |
1080 | #define STARTING_FRAME_OFFSET 0 | |
c65ebc55 JW |
1081 | |
1082 | /* Offset from the stack pointer register to the first location at which | |
1083 | outgoing arguments are placed. If not specified, the default value of zero | |
1084 | is used. This is the proper value for most machines. */ | |
1085 | /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ | |
1086 | #define STACK_POINTER_OFFSET 16 | |
1087 | ||
1088 | /* Offset from the argument pointer register to the first argument's address. | |
1089 | On some machines it may depend on the data type of the function. */ | |
1090 | #define FIRST_PARM_OFFSET(FUNDECL) 0 | |
1091 | ||
1092 | /* A C expression whose value is RTL representing the value of the return | |
1093 | address for the frame COUNT steps up from the current frame, after the | |
1094 | prologue. */ | |
1095 | ||
1096 | /* ??? Frames other than zero would likely require interpreting the frame | |
1097 | unwind info, so we don't try to support them. We would also need to define | |
1098 | DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ | |
1099 | ||
46327bc5 RH |
1100 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1101 | ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx) | |
c65ebc55 JW |
1102 | |
1103 | /* A C expression whose value is RTL representing the location of the incoming | |
1104 | return address at the beginning of any function, before the prologue. This | |
1105 | RTL is either a `REG', indicating that the return value is saved in `REG', | |
1106 | or a `MEM' representing a location in the stack. This enables DWARF2 | |
1107 | unwind info for C++ EH. */ | |
1108 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) | |
13da91fd | 1109 | |
c65ebc55 JW |
1110 | /* ??? This is not defined because of three problems. |
1111 | 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte. | |
1112 | The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be | |
1113 | worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise | |
1114 | unused register number. | |
1115 | 2) dwarf2out_frame_debug core dumps while processing prologue insns. We | |
1116 | need to refine which insns have RTX_FRAME_RELATED_P set and which don't. | |
1117 | 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO | |
1118 | to zero, despite what the documentation implies, because it is tested in | |
1119 | a few places with #ifdef instead of #if. */ | |
1120 | #undef INCOMING_RETURN_ADDR_RTX | |
1121 | ||
1122 | /* A C expression whose value is an integer giving the offset, in bytes, from | |
1123 | the value of the stack pointer register to the top of the stack frame at the | |
1124 | beginning of any function, before the prologue. The top of the frame is | |
1125 | defined to be the value of the stack pointer in the previous frame, just | |
1126 | before the call instruction. */ | |
1127 | #define INCOMING_FRAME_SP_OFFSET 0 | |
1128 | ||
1129 | \f | |
1130 | /* Register That Address the Stack Frame. */ | |
1131 | ||
1132 | /* The register number of the stack pointer register, which must also be a | |
1133 | fixed register according to `FIXED_REGISTERS'. On most machines, the | |
1134 | hardware determines which register this is. */ | |
1135 | ||
1136 | #define STACK_POINTER_REGNUM 12 | |
1137 | ||
1138 | /* The register number of the frame pointer register, which is used to access | |
1139 | automatic variables in the stack frame. On some machines, the hardware | |
1140 | determines which register this is. On other machines, you can choose any | |
1141 | register you wish for this purpose. */ | |
1142 | ||
1143 | #define FRAME_POINTER_REGNUM 328 | |
1144 | ||
97e242b0 RH |
1145 | /* Base register for access to local variables of the function. */ |
1146 | #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) | |
c65ebc55 JW |
1147 | |
1148 | /* The register number of the arg pointer register, which is used to access the | |
1149 | function's argument list. */ | |
1150 | /* r0 won't otherwise be used, so put the always eliminated argument pointer | |
1151 | in it. */ | |
1152 | #define ARG_POINTER_REGNUM R_GR(0) | |
1153 | ||
97e242b0 RH |
1154 | /* The register number for the return address register. For IA-64, this |
1155 | is not actually a pointer as the name suggests, but that's a name that | |
1156 | gen_rtx_REG already takes care to keep unique. We modify | |
1157 | return_address_pointer_rtx in ia64_expand_prologue to reference the | |
1158 | final output regnum. */ | |
46327bc5 | 1159 | #define RETURN_ADDRESS_POINTER_REGNUM 329 |
c65ebc55 JW |
1160 | |
1161 | /* Register numbers used for passing a function's static chain pointer. */ | |
97e242b0 | 1162 | /* ??? The ABI sez the static chain should be passed as a normal parameter. */ |
c65ebc55 | 1163 | #define STATIC_CHAIN_REGNUM 15 |
c65ebc55 JW |
1164 | \f |
1165 | /* Eliminating the Frame Pointer and the Arg Pointer */ | |
1166 | ||
1167 | /* A C expression which is nonzero if a function must have and use a frame | |
1168 | pointer. This expression is evaluated in the reload pass. If its value is | |
1169 | nonzero the function will have a frame pointer. */ | |
c65ebc55 JW |
1170 | #define FRAME_POINTER_REQUIRED 0 |
1171 | ||
97e242b0 RH |
1172 | /* Show we can debug even without a frame pointer. */ |
1173 | #define CAN_DEBUG_WITHOUT_FP | |
1174 | ||
c65ebc55 JW |
1175 | /* If defined, this macro specifies a table of register pairs used to eliminate |
1176 | unneeded registers that point into the stack frame. */ | |
1177 | ||
1178 | #define ELIMINABLE_REGS \ | |
1179 | { \ | |
1180 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
97e242b0 | 1181 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
46327bc5 | 1182 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
97e242b0 RH |
1183 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
1184 | {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \ | |
c65ebc55 JW |
1185 | } |
1186 | ||
1187 | /* A C expression that returns non-zero if the compiler is allowed to try to | |
97e242b0 RH |
1188 | replace register number FROM with register number TO. The frame pointer |
1189 | is automatically handled. */ | |
c65ebc55 | 1190 | |
46327bc5 RH |
1191 | #define CAN_ELIMINATE(FROM, TO) \ |
1192 | (TO == BR_REG (0) ? current_function_is_leaf : 1) | |
c65ebc55 | 1193 | |
97e242b0 RH |
1194 | /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It |
1195 | specifies the initial difference between the specified pair of | |
1196 | registers. This macro must be defined if `ELIMINABLE_REGS' is | |
1197 | defined. */ | |
1198 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1199 | ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) | |
c65ebc55 JW |
1200 | \f |
1201 | /* Passing Function Arguments on the Stack */ | |
1202 | ||
1203 | /* Define this macro if an argument declared in a prototype as an integral type | |
1204 | smaller than `int' should actually be passed as an `int'. In addition to | |
1205 | avoiding errors in certain cases of mismatch, it also makes for better code | |
1206 | on certain machines. */ | |
1207 | /* ??? Investigate. */ | |
1208 | /* #define PROMOTE_PROTOTYPES */ | |
1209 | ||
1210 | /* If defined, the maximum amount of space required for outgoing arguments will | |
1211 | be computed and placed into the variable | |
1212 | `current_function_outgoing_args_size'. */ | |
1213 | ||
f73ad30e | 1214 | #define ACCUMULATE_OUTGOING_ARGS 1 |
c65ebc55 JW |
1215 | |
1216 | /* A C expression that should indicate the number of bytes of its own arguments | |
1217 | that a function pops on returning, or 0 if the function pops no arguments | |
1218 | and the caller must therefore pop them all after the function returns. */ | |
1219 | ||
1220 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 | |
1221 | ||
1222 | \f | |
1223 | /* Function Arguments in Registers */ | |
1224 | ||
1225 | #define MAX_ARGUMENT_SLOTS 8 | |
1226 | #define MAX_INT_RETURN_SLOTS 4 | |
1227 | #define GR_ARG_FIRST IN_REG (0) | |
1228 | #define GR_RET_FIRST GR_REG (8) | |
1229 | #define GR_RET_LAST GR_REG (11) | |
1230 | #define FR_ARG_FIRST FR_REG (8) | |
1231 | #define FR_RET_FIRST FR_REG (8) | |
1232 | #define FR_RET_LAST FR_REG (15) | |
1233 | #define AR_ARG_FIRST OUT_REG (0) | |
1234 | ||
1235 | /* A C expression that controls whether a function argument is passed in a | |
1236 | register, and which register. */ | |
1237 | ||
1238 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1239 | ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0) | |
1240 | ||
1241 | /* Define this macro if the target machine has "register windows", so that the | |
1242 | register in which a function sees an arguments is not necessarily the same | |
1243 | as the one in which the caller passed the argument. */ | |
1244 | ||
1245 | #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ | |
1246 | ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1) | |
1247 | ||
1248 | /* A C expression for the number of words, at the beginning of an argument, | |
1249 | must be put in registers. The value must be zero for arguments that are | |
1250 | passed entirely in registers or that are entirely pushed on the stack. */ | |
1251 | ||
1252 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1253 | ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) | |
1254 | ||
1255 | /* A C expression that indicates when an argument must be passed by reference. | |
1256 | If nonzero for an argument, a copy of that argument is made in memory and a | |
1257 | pointer to the argument is passed instead of the argument itself. The | |
1258 | pointer is passed in whatever way is appropriate for passing a pointer to | |
1259 | that type. */ | |
1260 | ||
1261 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0 | |
1262 | ||
1263 | /* A C type for declaring a variable that is used as the first argument of | |
1264 | `FUNCTION_ARG' and other related values. For some target machines, the type | |
1265 | `int' suffices and can hold the number of bytes of argument so far. */ | |
1266 | ||
1267 | typedef struct ia64_args | |
1268 | { | |
1269 | int words; /* # words of arguments so far */ | |
1270 | int fp_regs; /* # FR registers used so far */ | |
1271 | int prototype; /* whether function prototyped */ | |
1272 | } CUMULATIVE_ARGS; | |
1273 | ||
1274 | /* A C statement (sans semicolon) for initializing the variable CUM for the | |
1275 | state at the beginning of the argument list. */ | |
1276 | ||
1277 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ | |
1278 | do { \ | |
1279 | (CUM).words = 0; \ | |
1280 | (CUM).fp_regs = 0; \ | |
1281 | (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \ | |
1282 | } while (0) | |
1283 | ||
1284 | /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the | |
1285 | arguments for the function being compiled. If this macro is undefined, | |
1286 | `INIT_CUMULATIVE_ARGS' is used instead. */ | |
1287 | ||
1288 | /* We set prototype to true so that we never try to return a PARALLEL from | |
1289 | function_arg. */ | |
1290 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
1291 | do { \ | |
1292 | (CUM).words = 0; \ | |
1293 | (CUM).fp_regs = 0; \ | |
1294 | (CUM).prototype = 1; \ | |
1295 | } while (0) | |
1296 | ||
1297 | /* A C statement (sans semicolon) to update the summarizer variable CUM to | |
1298 | advance past an argument in the argument list. The values MODE, TYPE and | |
1299 | NAMED describe that argument. Once this is done, the variable CUM is | |
1300 | suitable for analyzing the *following* argument with `FUNCTION_ARG'. */ | |
1301 | ||
1302 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1303 | ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED) | |
1304 | ||
1305 | /* If defined, a C expression that gives the alignment boundary, in bits, of an | |
1306 | argument with the specified mode and type. */ | |
1307 | ||
93dd6255 JW |
1308 | /* Arguments with alignment larger than 8 bytes start at the next even |
1309 | boundary. See ia64_function_arg. */ | |
c65ebc55 JW |
1310 | |
1311 | #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
93dd6255 JW |
1312 | (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \ |
1313 | : (((((MODE) == BLKmode \ | |
1314 | ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
1315 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \ | |
1316 | ? 128 : PARM_BOUNDARY) | |
c65ebc55 JW |
1317 | |
1318 | /* A C expression that is nonzero if REGNO is the number of a hard register in | |
1319 | which function arguments are sometimes passed. This does *not* include | |
1320 | implicit arguments such as the static chain and the structure-value address. | |
1321 | On many machines, no registers can be used for this purpose since all | |
1322 | function arguments are pushed on the stack. */ | |
1323 | #define FUNCTION_ARG_REGNO_P(REGNO) \ | |
1324 | (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ | |
1325 | || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) | |
1326 | \f | |
1327 | /* Implement `va_start' for varargs and stdarg. */ | |
1328 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
1329 | ia64_va_start (stdarg, valist, nextarg) | |
1330 | ||
1331 | /* Implement `va_arg'. */ | |
1332 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
1333 | ia64_va_arg (valist, type) | |
1334 | \f | |
1335 | /* How Scalar Function Values are Returned */ | |
1336 | ||
1337 | /* A C expression to create an RTX representing the place where a function | |
1338 | returns a value of data type VALTYPE. */ | |
1339 | ||
1340 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
1341 | ia64_function_value (VALTYPE, FUNC) | |
1342 | ||
1343 | /* A C expression to create an RTX representing the place where a library | |
1344 | function returns a value of mode MODE. */ | |
1345 | ||
1346 | #define LIBCALL_VALUE(MODE) \ | |
1347 | gen_rtx_REG (MODE, \ | |
23c108af SE |
1348 | (((GET_MODE_CLASS (MODE) == MODE_FLOAT \ |
1349 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \ | |
1350 | ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \ | |
c65ebc55 JW |
1351 | ? FR_RET_FIRST : GR_RET_FIRST)) |
1352 | ||
1353 | /* A C expression that is nonzero if REGNO is the number of a hard register in | |
1354 | which the values of called function may come back. */ | |
1355 | ||
1356 | #define FUNCTION_VALUE_REGNO_P(REGNO) \ | |
1357 | (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \ | |
1358 | || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST)) | |
1359 | ||
1360 | \f | |
1361 | /* How Large Values are Returned */ | |
1362 | ||
1363 | /* A nonzero value says to return the function value in memory, just as large | |
1364 | structures are always returned. */ | |
1365 | ||
1366 | #define RETURN_IN_MEMORY(TYPE) \ | |
1367 | ia64_return_in_memory (TYPE) | |
1368 | ||
1369 | /* If you define this macro to be 0, then the conventions used for structure | |
1370 | and union return values are decided by the `RETURN_IN_MEMORY' macro. */ | |
1371 | ||
1372 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
1373 | ||
1374 | /* If the structure value address is passed in a register, then | |
1375 | `STRUCT_VALUE_REGNUM' should be the number of that register. */ | |
1376 | ||
1377 | #define STRUCT_VALUE_REGNUM GR_REG (8) | |
1378 | ||
1379 | \f | |
1380 | /* Caller-Saves Register Allocation */ | |
1381 | ||
1382 | /* A C expression to determine whether it is worthwhile to consider placing a | |
1383 | pseudo-register in a call-clobbered hard register and saving and restoring | |
1384 | it around each function call. The expression should be 1 when this is worth | |
1385 | doing, and 0 otherwise. | |
1386 | ||
1387 | If you don't define this macro, a default is used which is good on most | |
1388 | machines: `4 * CALLS < REFS'. */ | |
1389 | /* ??? Investigate. */ | |
1390 | /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ | |
1391 | ||
1392 | \f | |
1393 | /* Function Entry and Exit */ | |
1394 | ||
c65ebc55 JW |
1395 | /* Define this macro as a C expression that is nonzero if the return |
1396 | instruction or the function epilogue ignores the value of the stack pointer; | |
1397 | in other words, if it is safe to delete an instruction to adjust the stack | |
1398 | pointer before a return from the function. */ | |
1399 | ||
1400 | #define EXIT_IGNORE_STACK 1 | |
1401 | ||
1402 | /* Define this macro as a C expression that is nonzero for registers | |
1403 | used by the epilogue or the `return' pattern. */ | |
1404 | ||
1405 | #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) | |
1406 | ||
3b572406 RH |
1407 | /* Output at beginning of assembler file. */ |
1408 | ||
1409 | #define ASM_FILE_START(FILE) \ | |
ca3920ad | 1410 | emit_safe_across_calls (FILE) |
3b572406 | 1411 | |
c65ebc55 JW |
1412 | /* A C compound statement that outputs the assembler code for a thunk function, |
1413 | used to implement C++ virtual function calls with multiple inheritance. */ | |
1414 | ||
c65ebc55 JW |
1415 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
1416 | do { \ | |
591eb4ba | 1417 | if (CONST_OK_FOR_I (DELTA)) \ |
55710451 KG |
1418 | { \ |
1419 | fprintf (FILE, "\tadds r32 = "); \ | |
1420 | fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \ | |
1421 | fprintf (FILE, ", r32\n"); \ | |
1422 | } \ | |
591eb4ba JW |
1423 | else \ |
1424 | { \ | |
1425 | if (CONST_OK_FOR_J (DELTA)) \ | |
55710451 KG |
1426 | { \ |
1427 | fprintf (FILE, "\taddl r2 = "); \ | |
1428 | fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \ | |
1429 | fprintf (FILE, ", r0\n"); \ | |
1430 | } \ | |
591eb4ba | 1431 | else \ |
55710451 KG |
1432 | { \ |
1433 | fprintf (FILE, "\tmovl r2 = "); \ | |
1434 | fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \ | |
1435 | fprintf (FILE, "\n"); \ | |
1436 | } \ | |
591eb4ba JW |
1437 | fprintf (FILE, "\t;;\n"); \ |
1438 | fprintf (FILE, "\tadd r32 = r2, r32\n"); \ | |
1439 | } \ | |
c65ebc55 JW |
1440 | fprintf (FILE, "\tbr "); \ |
1441 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \ | |
1442 | fprintf (FILE, "\n"); \ | |
1443 | } while (0) | |
1444 | ||
67231816 RH |
1445 | /* Output part N of a function descriptor for DECL. For ia64, both |
1446 | words are emitted with a single relocation, so ignore N > 0. */ | |
1447 | #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ | |
1448 | do { \ | |
1449 | if ((PART) == 0) \ | |
1450 | { \ | |
1451 | fputs ("\tdata16.ua @iplt(", FILE); \ | |
1452 | assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ | |
1453 | fputs (")\n", FILE); \ | |
1454 | } \ | |
1455 | } while (0) | |
c65ebc55 JW |
1456 | \f |
1457 | /* Generating Code for Profiling. */ | |
1458 | ||
1459 | /* A C statement or compound statement to output to FILE some assembler code to | |
1460 | call the profiling subroutine `mcount'. */ | |
1461 | ||
243a7070 DB |
1462 | #undef FUNCTION_PROFILER |
1463 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
c65ebc55 JW |
1464 | do { \ |
1465 | char buf[20]; \ | |
1466 | ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \ | |
243a7070 DB |
1467 | fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \ |
1468 | if (TARGET_AUTO_PIC) \ | |
1469 | fputs ("\tmovl out3 = @gprel(", FILE); \ | |
1470 | else \ | |
1471 | fputs ("\taddl out3 = @ltoff(", FILE); \ | |
c65ebc55 | 1472 | assemble_name (FILE, buf); \ |
243a7070 DB |
1473 | if (TARGET_AUTO_PIC) \ |
1474 | fputs (");;\n", FILE); \ | |
1475 | else \ | |
1476 | fputs ("), r1;;\n", FILE); \ | |
1477 | fputs ("\tmov out1 = r1\n", FILE); \ | |
1478 | fputs ("\tmov out2 = b0\n", FILE); \ | |
1479 | fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \ | |
c65ebc55 | 1480 | } while (0) |
c65ebc55 JW |
1481 | \f |
1482 | /* Implementing the Varargs Macros. */ | |
1483 | ||
1484 | /* Define this macro to store the anonymous register arguments into the stack | |
1485 | so that all the arguments appear to have been passed consecutively on the | |
1486 | stack. */ | |
1487 | ||
1488 | #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \ | |
1489 | ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME) | |
1490 | ||
1491 | /* Define this macro if the location where a function argument is passed | |
1492 | depends on whether or not it is a named argument. */ | |
1493 | ||
1494 | #define STRICT_ARGUMENT_NAMING 1 | |
1495 | ||
1496 | \f | |
1497 | /* Trampolines for Nested Functions. */ | |
1498 | ||
1499 | /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of | |
1500 | the function containing a non-local goto target. */ | |
1501 | ||
1502 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
1503 | ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) | |
1504 | ||
1505 | /* Output assembler code for a block containing the constant parts of | |
1506 | a trampoline, leaving space for the variable parts. | |
1507 | ||
1508 | The trampoline should set the static chain pointer to value placed | |
97e242b0 RH |
1509 | into the trampoline and should branch to the specified routine. |
1510 | To make the normal indirect-subroutine calling convention work, | |
1511 | the trampoline must look like a function descriptor; the first | |
1512 | word being the target address and the second being the target's | |
1513 | global pointer. | |
1514 | ||
1515 | We abuse the concept of a global pointer by arranging for it | |
1516 | to point to the data we need to load. The complete trampoline | |
c65ebc55 JW |
1517 | has the following form: |
1518 | ||
97e242b0 RH |
1519 | +-------------------+ \ |
1520 | TRAMP: | __ia64_trampoline | | | |
1521 | +-------------------+ > fake function descriptor | |
1522 | | TRAMP+16 | | | |
1523 | +-------------------+ / | |
1524 | | target descriptor | | |
1525 | +-------------------+ | |
1526 | | static link | | |
1527 | +-------------------+ | |
c65ebc55 JW |
1528 | */ |
1529 | ||
c65ebc55 JW |
1530 | /* A C expression for the size in bytes of the trampoline, as an integer. */ |
1531 | ||
97e242b0 | 1532 | #define TRAMPOLINE_SIZE 32 |
c65ebc55 JW |
1533 | |
1534 | /* Alignment required for trampolines, in bits. */ | |
1535 | ||
97e242b0 | 1536 | #define TRAMPOLINE_ALIGNMENT 64 |
c65ebc55 JW |
1537 | |
1538 | /* A C statement to initialize the variable parts of a trampoline. */ | |
1539 | ||
1540 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \ | |
97e242b0 | 1541 | ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN)) |
c65ebc55 JW |
1542 | \f |
1543 | /* Implicit Calls to Library Routines */ | |
1544 | ||
c65ebc55 JW |
1545 | /* Define this macro if GNU CC should generate calls to the System V (and ANSI |
1546 | C) library functions `memcpy' and `memset' rather than the BSD functions | |
1547 | `bcopy' and `bzero'. */ | |
1548 | ||
1549 | #define TARGET_MEM_FUNCTIONS | |
1550 | ||
1551 | \f | |
1552 | /* Addressing Modes */ | |
1553 | ||
1554 | /* Define this macro if the machine supports post-increment addressing. */ | |
1555 | ||
1556 | #define HAVE_POST_INCREMENT 1 | |
1557 | #define HAVE_POST_DECREMENT 1 | |
4b983fdc RH |
1558 | #define HAVE_POST_MODIFY_DISP 1 |
1559 | #define HAVE_POST_MODIFY_REG 1 | |
c65ebc55 JW |
1560 | |
1561 | /* A C expression that is 1 if the RTX X is a constant which is a valid | |
1562 | address. */ | |
1563 | ||
1564 | #define CONSTANT_ADDRESS_P(X) 0 | |
1565 | ||
1566 | /* The max number of registers that can appear in a valid memory address. */ | |
1567 | ||
4b983fdc | 1568 | #define MAX_REGS_PER_ADDRESS 2 |
c65ebc55 JW |
1569 | |
1570 | /* A C compound statement with a conditional `goto LABEL;' executed if X (an | |
1571 | RTX) is a legitimate memory address on the target machine for a memory | |
1572 | operand of mode MODE. */ | |
1573 | ||
4b983fdc RH |
1574 | #define LEGITIMATE_ADDRESS_REG(X) \ |
1575 | ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ | |
1576 | || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \ | |
1577 | && REG_OK_FOR_BASE_P (XEXP (X, 0)))) | |
1578 | ||
1579 | #define LEGITIMATE_ADDRESS_DISP(R, X) \ | |
1580 | (GET_CODE (X) == PLUS \ | |
1581 | && rtx_equal_p (R, XEXP (X, 0)) \ | |
cf606f45 | 1582 | && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \ |
4b983fdc | 1583 | || (GET_CODE (XEXP (X, 1)) == CONST_INT \ |
5527bf14 RH |
1584 | && INTVAL (XEXP (X, 1)) >= -256 \ |
1585 | && INTVAL (XEXP (X, 1)) < 256))) | |
c65ebc55 JW |
1586 | |
1587 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ | |
1588 | do { \ | |
4b983fdc | 1589 | if (LEGITIMATE_ADDRESS_REG (X)) \ |
c65ebc55 | 1590 | goto LABEL; \ |
4b983fdc RH |
1591 | else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ |
1592 | && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ | |
1593 | && XEXP (X, 0) != arg_pointer_rtx) \ | |
1594 | goto LABEL; \ | |
1595 | else if (GET_CODE (X) == POST_MODIFY \ | |
1596 | && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ | |
1597 | && XEXP (X, 0) != arg_pointer_rtx \ | |
1598 | && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \ | |
c65ebc55 | 1599 | goto LABEL; \ |
c65ebc55 JW |
1600 | } while (0) |
1601 | ||
1602 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
1603 | use as a base register. */ | |
1604 | ||
1605 | #ifdef REG_OK_STRICT | |
1606 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1607 | #else | |
1608 | #define REG_OK_FOR_BASE_P(X) \ | |
1609 | (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) | |
1610 | #endif | |
1611 | ||
1612 | /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for | |
cf606f45 | 1613 | use as an index register. This is needed for POST_MODIFY. */ |
c65ebc55 | 1614 | |
cf606f45 | 1615 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) |
c65ebc55 JW |
1616 | |
1617 | /* A C compound statement that attempts to replace X with a valid memory | |
1618 | address for an operand of mode MODE. | |
1619 | ||
1620 | This must be present, but there is nothing useful to be done here. */ | |
1621 | ||
1622 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) | |
1623 | ||
1624 | /* A C statement or compound statement with a conditional `goto LABEL;' | |
1625 | executed if memory address X (an RTX) can have different meanings depending | |
1626 | on the machine mode of the memory reference it is used for or if the address | |
1627 | is valid for some modes but not others. */ | |
1628 | ||
3f622353 | 1629 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ |
c65ebc55 JW |
1630 | if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \ |
1631 | goto LABEL; | |
1632 | ||
1633 | /* A C expression that is nonzero if X is a legitimate constant for an | |
1634 | immediate operand on the target machine. */ | |
1635 | ||
1636 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1637 | (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ | |
1638 | || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \ | |
1639 | ||
1640 | \f | |
1641 | /* Condition Code Status */ | |
1642 | ||
1643 | /* One some machines not all possible comparisons are defined, but you can | |
1644 | convert an invalid comparison into a valid one. */ | |
1645 | /* ??? Investigate. See the alpha definition. */ | |
1646 | /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ | |
1647 | ||
1648 | \f | |
1649 | /* Describing Relative Costs of Operations */ | |
1650 | ||
1651 | /* A part of a C `switch' statement that describes the relative costs of | |
1652 | constant RTL expressions. */ | |
1653 | ||
1654 | /* ??? This is incomplete. */ | |
1655 | ||
f2f90c63 | 1656 | #define CONST_COSTS(X, CODE, OUTER_CODE) \ |
c65ebc55 JW |
1657 | case CONST_INT: \ |
1658 | if ((X) == const0_rtx) \ | |
1659 | return 0; \ | |
f2f90c63 RH |
1660 | switch (OUTER_CODE) \ |
1661 | { \ | |
1662 | case SET: \ | |
1663 | return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \ | |
1664 | case PLUS: \ | |
1665 | if (CONST_OK_FOR_I (INTVAL (X))) \ | |
1666 | return 0; \ | |
1667 | if (CONST_OK_FOR_J (INTVAL (X))) \ | |
1668 | return 1; \ | |
1669 | return COSTS_N_INSNS (1); \ | |
1670 | default: \ | |
1671 | if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \ | |
1672 | return 0; \ | |
1673 | return COSTS_N_INSNS (1); \ | |
1674 | } \ | |
c65ebc55 | 1675 | case CONST_DOUBLE: \ |
f2f90c63 | 1676 | return COSTS_N_INSNS (1); \ |
c65ebc55 JW |
1677 | case CONST: \ |
1678 | case SYMBOL_REF: \ | |
1679 | case LABEL_REF: \ | |
2130b7fb | 1680 | return COSTS_N_INSNS (3); |
c65ebc55 JW |
1681 | |
1682 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */ | |
1683 | ||
f2f90c63 RH |
1684 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ |
1685 | case MULT: \ | |
1686 | /* For multiplies wider than HImode, we have to go to the FPU, \ | |
1687 | which normally involves copies. Plus there's the latency \ | |
005f39ce BS |
1688 | of the multiply itself, and the latency of the instructions to \ |
1689 | transfer integer regs to FP regs. */ \ | |
f2f90c63 | 1690 | if (GET_MODE_SIZE (GET_MODE (X)) > 2) \ |
005f39ce BS |
1691 | return COSTS_N_INSNS (10); \ |
1692 | return COSTS_N_INSNS (2); \ | |
1693 | case PLUS: \ | |
1694 | case MINUS: \ | |
1695 | case ASHIFT: \ | |
1696 | case ASHIFTRT: \ | |
1697 | case LSHIFTRT: \ | |
f2f90c63 | 1698 | return COSTS_N_INSNS (1); \ |
c65ebc55 JW |
1699 | case DIV: \ |
1700 | case UDIV: \ | |
1701 | case MOD: \ | |
1702 | case UMOD: \ | |
f2f90c63 RH |
1703 | /* We make divide expensive, so that divide-by-constant will be \ |
1704 | optimized to a multiply. */ \ | |
1705 | return COSTS_N_INSNS (60); | |
c65ebc55 JW |
1706 | |
1707 | /* An expression giving the cost of an addressing mode that contains ADDRESS. | |
1708 | If not defined, the cost is computed from the ADDRESS expression and the | |
1709 | `CONST_COSTS' values. */ | |
1710 | ||
1711 | #define ADDRESS_COST(ADDRESS) 0 | |
1712 | ||
1713 | /* A C expression for the cost of moving data from a register in class FROM to | |
7109d286 | 1714 | one in class TO, using MODE. */ |
c65ebc55 | 1715 | |
7109d286 | 1716 | #define REGISTER_MOVE_COST ia64_register_move_cost |
c65ebc55 | 1717 | |
f2f90c63 RH |
1718 | /* A C expression for the cost of moving data of mode M between a |
1719 | register and memory. */ | |
1720 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ | |
7109d286 RH |
1721 | ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \ |
1722 | || (CLASS) == GR_AND_FR_REGS ? 4 : 10) | |
c65ebc55 JW |
1723 | |
1724 | /* A C expression for the cost of a branch instruction. A value of 1 is the | |
e5bde68a RH |
1725 | default; other values are interpreted relative to that. Used by the |
1726 | if-conversion code as max instruction count. */ | |
1727 | /* ??? This requires investigation. The primary effect might be how | |
1728 | many additional insn groups we run into, vs how good the dynamic | |
1729 | branch predictor is. */ | |
1730 | ||
1731 | #define BRANCH_COST 6 | |
c65ebc55 JW |
1732 | |
1733 | /* Define this macro as a C expression which is nonzero if accessing less than | |
1734 | a word of memory (i.e. a `char' or a `short') is no faster than accessing a | |
1735 | word of memory. */ | |
1736 | ||
1737 | #define SLOW_BYTE_ACCESS 1 | |
1738 | ||
1739 | /* Define this macro if it is as good or better to call a constant function | |
1740 | address than to call an address kept in a register. | |
1741 | ||
1742 | Indirect function calls are more expensive that direct function calls, so | |
1743 | don't cse function addresses. */ | |
1744 | ||
1745 | #define NO_FUNCTION_CSE | |
1746 | ||
c65ebc55 JW |
1747 | \f |
1748 | /* Dividing the output into sections. */ | |
1749 | ||
1750 | /* A C expression whose value is a string containing the assembler operation | |
1751 | that should precede instructions and read-only data. */ | |
1752 | ||
de323aa1 | 1753 | #define TEXT_SECTION_ASM_OP "\t.text" |
c65ebc55 JW |
1754 | |
1755 | /* A C expression whose value is a string containing the assembler operation to | |
1756 | identify the following data as writable initialized data. */ | |
1757 | ||
de323aa1 | 1758 | #define DATA_SECTION_ASM_OP "\t.data" |
c65ebc55 JW |
1759 | |
1760 | /* If defined, a C expression whose value is a string containing the assembler | |
1761 | operation to identify the following data as uninitialized global data. */ | |
1762 | ||
de323aa1 | 1763 | #define BSS_SECTION_ASM_OP "\t.bss" |
c65ebc55 | 1764 | |
c65ebc55 JW |
1765 | /* Define this macro if references to a symbol must be treated differently |
1766 | depending on something about the variable or function named by the symbol | |
1767 | (such as what section it is in). */ | |
1768 | ||
1769 | #define ENCODE_SECTION_INFO(DECL) ia64_encode_section_info (DECL) | |
1770 | ||
32adf8e6 AH |
1771 | /* If a variable is weakened, made one only or moved into a different |
1772 | section, it may be necessary to redo the section info to move the | |
ed168e45 | 1773 | variable out of sdata. */ |
32adf8e6 AH |
1774 | |
1775 | #define REDO_SECTION_INFO_P(DECL) \ | |
1776 | ((TREE_CODE (DECL) == VAR_DECL) \ | |
94c21c17 GS |
1777 | && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \ |
1778 | || DECL_SECTION_NAME (DECL) != 0)) | |
32adf8e6 | 1779 | |
c65ebc55 JW |
1780 | #define SDATA_NAME_FLAG_CHAR '@' |
1781 | ||
1782 | #define IA64_DEFAULT_GVALUE 8 | |
1783 | ||
1784 | /* Decode SYM_NAME and store the real name part in VAR, sans the characters | |
1785 | that encode section info. */ | |
1786 | ||
c45632b7 RH |
1787 | #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \ |
1788 | do { \ | |
1789 | (VAR) = (SYMBOL_NAME); \ | |
1790 | if ((VAR)[0] == SDATA_NAME_FLAG_CHAR) \ | |
1791 | (VAR)++; \ | |
1792 | if ((VAR)[0] == '*') \ | |
1793 | (VAR)++; \ | |
1794 | } while (0) | |
c65ebc55 JW |
1795 | \f |
1796 | /* Position Independent Code. */ | |
1797 | ||
1798 | /* The register number of the register used to address a table of static data | |
1799 | addresses in memory. */ | |
1800 | ||
1801 | /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of | |
1802 | gen_rtx_REG (DImode, 1). */ | |
1803 | ||
1804 | /* ??? Should we set flag_pic? Probably need to define | |
1805 | LEGITIMIZE_PIC_OPERAND_P to make that work. */ | |
1806 | ||
1807 | #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) | |
1808 | ||
1809 | /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is | |
1810 | clobbered by calls. */ | |
1811 | ||
1812 | #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED | |
1813 | ||
1814 | \f | |
1815 | /* The Overall Framework of an Assembler File. */ | |
1816 | ||
1817 | /* A C string constant describing how to begin a comment in the target | |
1818 | assembler language. The compiler assumes that the comment will end at the | |
1819 | end of the line. */ | |
1820 | ||
1821 | #define ASM_COMMENT_START "//" | |
1822 | ||
1823 | /* A C string constant for text to be output before each `asm' statement or | |
1824 | group of consecutive ones. */ | |
1825 | ||
1826 | /* ??? This won't work with the Intel assembler, because it does not accept | |
1827 | # as a comment start character. However, //APP does not work in gas, so we | |
1828 | can't use that either. Same problem for ASM_APP_OFF below. */ | |
1829 | ||
1830 | #define ASM_APP_ON "#APP\n" | |
1831 | ||
1832 | /* A C string constant for text to be output after each `asm' statement or | |
1833 | group of consecutive ones. */ | |
1834 | ||
1835 | #define ASM_APP_OFF "#NO_APP\n" | |
1836 | ||
1837 | \f | |
1838 | /* Output of Data. */ | |
1839 | ||
0c96007e AM |
1840 | /* This is how to output an assembler line defining a `char' constant |
1841 | to an xdata segment. */ | |
1842 | ||
1843 | #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \ | |
1844 | do { \ | |
1845 | fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \ | |
1846 | output_addr_const (FILE, (VALUE)); \ | |
1847 | fprintf (FILE, "\n"); \ | |
1848 | } while (0) | |
1849 | ||
1850 | /* This is how to output an assembler line defining a `short' constant | |
1851 | to an xdata segment. */ | |
1852 | ||
1853 | #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \ | |
1854 | do { \ | |
1855 | fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \ | |
1856 | output_addr_const (FILE, (VALUE)); \ | |
1857 | fprintf (FILE, "\n"); \ | |
1858 | } while (0) | |
1859 | ||
1860 | /* This is how to output an assembler line defining an `int' constant | |
1861 | to an xdata segment. We also handle symbol output here. */ | |
1862 | ||
1863 | /* ??? For ILP32, also need to handle function addresses here. */ | |
1864 | ||
1865 | #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \ | |
1866 | do { \ | |
1867 | fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \ | |
1868 | output_addr_const (FILE, (VALUE)); \ | |
1869 | fprintf (FILE, "\n"); \ | |
1870 | } while (0) | |
1871 | ||
1872 | /* This is how to output an assembler line defining a `long' constant | |
1873 | to an xdata segment. We also handle symbol output here. */ | |
1874 | ||
1875 | #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \ | |
1876 | do { \ | |
59da9a7d | 1877 | int need_closing_paren = 0; \ |
0c96007e | 1878 | fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \ |
59da9a7d JW |
1879 | if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \ |
1880 | && GET_CODE (VALUE) == SYMBOL_REF) \ | |
0c96007e | 1881 | { \ |
59da9a7d JW |
1882 | fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \ |
1883 | need_closing_paren = 1; \ | |
0c96007e | 1884 | } \ |
59da9a7d JW |
1885 | output_addr_const (FILE, VALUE); \ |
1886 | if (need_closing_paren) \ | |
0c96007e AM |
1887 | fprintf (FILE, ")"); \ |
1888 | fprintf (FILE, "\n"); \ | |
1889 | } while (0) | |
1890 | ||
1891 | ||
c65ebc55 JW |
1892 | \f |
1893 | /* Output of Uninitialized Variables. */ | |
1894 | ||
1895 | /* This is all handled by svr4.h. */ | |
1896 | ||
1897 | \f | |
1898 | /* Output and Generation of Labels. */ | |
1899 | ||
1900 | /* A C statement (sans semicolon) to output to the stdio stream STREAM the | |
1901 | assembler definition of a label named NAME. */ | |
1902 | ||
1903 | /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of | |
1904 | why ia64_asm_output_label exists. */ | |
1905 | ||
1906 | extern int ia64_asm_output_label; | |
1907 | #define ASM_OUTPUT_LABEL(STREAM, NAME) \ | |
1908 | do { \ | |
1909 | ia64_asm_output_label = 1; \ | |
1910 | assemble_name (STREAM, NAME); \ | |
1911 | fputs (":\n", STREAM); \ | |
1912 | ia64_asm_output_label = 0; \ | |
1913 | } while (0) | |
1914 | ||
1915 | /* A C statement (sans semicolon) to output to the stdio stream STREAM some | |
1916 | commands that will make the label NAME global; that is, available for | |
1917 | reference from other files. */ | |
1918 | ||
1919 | #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \ | |
1920 | do { \ | |
1921 | fputs ("\t.global ", STREAM); \ | |
1922 | assemble_name (STREAM, NAME); \ | |
1923 | fputs ("\n", STREAM); \ | |
1924 | } while (0) | |
1925 | ||
1926 | /* A C statement (sans semicolon) to output to the stdio stream STREAM any text | |
1927 | necessary for declaring the name of an external symbol named NAME which is | |
1928 | referenced in this compilation but not defined. */ | |
1929 | ||
1930 | #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ | |
1931 | ia64_asm_output_external (FILE, DECL, NAME) | |
1932 | ||
1933 | /* A C statement to store into the string STRING a label whose name is made | |
1934 | from the string PREFIX and the number NUM. */ | |
1935 | ||
1936 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ | |
1937 | do { \ | |
1938 | sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ | |
1939 | } while (0) | |
1940 | ||
1941 | /* A C expression to assign to OUTVAR (which is a variable of type `char *') a | |
1942 | newly allocated string made from the string NAME and the number NUMBER, with | |
1943 | some suitable punctuation added. */ | |
1944 | ||
1945 | /* ??? Not sure if using a ? in the name for Intel as is safe. */ | |
1946 | ||
1947 | #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ | |
1948 | do { \ | |
1949 | (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \ | |
1950 | sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \ | |
1951 | (long)(NUMBER)); \ | |
1952 | } while (0) | |
1953 | ||
1954 | /* A C statement to output to the stdio stream STREAM assembler code which | |
1955 | defines (equates) the symbol NAME to have the value VALUE. */ | |
1956 | ||
1957 | #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ | |
1958 | do { \ | |
1959 | assemble_name (STREAM, NAME); \ | |
1960 | fputs (" = ", STREAM); \ | |
1961 | assemble_name (STREAM, VALUE); \ | |
1962 | fputc ('\n', STREAM); \ | |
1963 | } while (0) | |
1964 | ||
1965 | \f | |
1966 | /* Macros Controlling Initialization Routines. */ | |
1967 | ||
1968 | /* This is handled by svr4.h and sysv4.h. */ | |
1969 | ||
1970 | \f | |
1971 | /* Output of Assembler Instructions. */ | |
1972 | ||
1973 | /* A C initializer containing the assembler's names for the machine registers, | |
1974 | each one as a C string constant. */ | |
1975 | ||
1976 | #define REGISTER_NAMES \ | |
1977 | { \ | |
1978 | /* General registers. */ \ | |
1979 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ | |
1980 | "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ | |
1981 | "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ | |
1982 | "r30", "r31", \ | |
1983 | /* Local registers. */ \ | |
1984 | "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ | |
1985 | "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ | |
1986 | "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ | |
1987 | "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ | |
1988 | "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ | |
1989 | "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ | |
1990 | "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ | |
1991 | "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ | |
1992 | "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ | |
1993 | "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ | |
1994 | /* Input registers. */ \ | |
1995 | "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ | |
1996 | /* Output registers. */ \ | |
1997 | "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ | |
1998 | /* Floating-point registers. */ \ | |
1999 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ | |
2000 | "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ | |
2001 | "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ | |
2002 | "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ | |
2003 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ | |
2004 | "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ | |
2005 | "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ | |
2006 | "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ | |
2007 | "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ | |
2008 | "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ | |
2009 | "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ | |
2010 | "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ | |
2011 | "f120","f121","f122","f123","f124","f125","f126","f127", \ | |
2012 | /* Predicate registers. */ \ | |
2013 | "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ | |
2014 | "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ | |
2015 | "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ | |
2016 | "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ | |
2017 | "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ | |
2018 | "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ | |
2019 | "p60", "p61", "p62", "p63", \ | |
2020 | /* Branch registers. */ \ | |
2021 | "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ | |
2022 | /* Frame pointer. Return address. */ \ | |
97e242b0 | 2023 | "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ |
c65ebc55 JW |
2024 | } |
2025 | ||
2026 | /* If defined, a C initializer for an array of structures containing a name and | |
2027 | a register number. This macro defines additional names for hard registers, | |
2028 | thus allowing the `asm' option in declarations to refer to registers using | |
2029 | alternate names. */ | |
2030 | ||
2031 | #define ADDITIONAL_REGISTER_NAMES \ | |
2032 | { \ | |
2033 | { "gp", R_GR (1) }, \ | |
2034 | { "sp", R_GR (12) }, \ | |
2035 | { "in0", IN_REG (0) }, \ | |
2036 | { "in1", IN_REG (1) }, \ | |
2037 | { "in2", IN_REG (2) }, \ | |
2038 | { "in3", IN_REG (3) }, \ | |
2039 | { "in4", IN_REG (4) }, \ | |
2040 | { "in5", IN_REG (5) }, \ | |
2041 | { "in6", IN_REG (6) }, \ | |
2042 | { "in7", IN_REG (7) }, \ | |
2043 | { "out0", OUT_REG (0) }, \ | |
2044 | { "out1", OUT_REG (1) }, \ | |
2045 | { "out2", OUT_REG (2) }, \ | |
2046 | { "out3", OUT_REG (3) }, \ | |
2047 | { "out4", OUT_REG (4) }, \ | |
2048 | { "out5", OUT_REG (5) }, \ | |
2049 | { "out6", OUT_REG (6) }, \ | |
2050 | { "out7", OUT_REG (7) }, \ | |
2051 | { "loc0", LOC_REG (0) }, \ | |
2052 | { "loc1", LOC_REG (1) }, \ | |
2053 | { "loc2", LOC_REG (2) }, \ | |
2054 | { "loc3", LOC_REG (3) }, \ | |
2055 | { "loc4", LOC_REG (4) }, \ | |
2056 | { "loc5", LOC_REG (5) }, \ | |
2057 | { "loc6", LOC_REG (6) }, \ | |
2058 | { "loc7", LOC_REG (7) }, \ | |
2059 | { "loc8", LOC_REG (8) }, \ | |
2060 | { "loc9", LOC_REG (9) }, \ | |
2061 | { "loc10", LOC_REG (10) }, \ | |
2062 | { "loc11", LOC_REG (11) }, \ | |
2063 | { "loc12", LOC_REG (12) }, \ | |
2064 | { "loc13", LOC_REG (13) }, \ | |
2065 | { "loc14", LOC_REG (14) }, \ | |
2066 | { "loc15", LOC_REG (15) }, \ | |
2067 | { "loc16", LOC_REG (16) }, \ | |
2068 | { "loc17", LOC_REG (17) }, \ | |
2069 | { "loc18", LOC_REG (18) }, \ | |
2070 | { "loc19", LOC_REG (19) }, \ | |
2071 | { "loc20", LOC_REG (20) }, \ | |
2072 | { "loc21", LOC_REG (21) }, \ | |
2073 | { "loc22", LOC_REG (22) }, \ | |
2074 | { "loc23", LOC_REG (23) }, \ | |
2075 | { "loc24", LOC_REG (24) }, \ | |
2076 | { "loc25", LOC_REG (25) }, \ | |
2077 | { "loc26", LOC_REG (26) }, \ | |
2078 | { "loc27", LOC_REG (27) }, \ | |
2079 | { "loc28", LOC_REG (28) }, \ | |
2080 | { "loc29", LOC_REG (29) }, \ | |
2081 | { "loc30", LOC_REG (30) }, \ | |
2082 | { "loc31", LOC_REG (31) }, \ | |
2083 | { "loc32", LOC_REG (32) }, \ | |
2084 | { "loc33", LOC_REG (33) }, \ | |
2085 | { "loc34", LOC_REG (34) }, \ | |
2086 | { "loc35", LOC_REG (35) }, \ | |
2087 | { "loc36", LOC_REG (36) }, \ | |
2088 | { "loc37", LOC_REG (37) }, \ | |
2089 | { "loc38", LOC_REG (38) }, \ | |
2090 | { "loc39", LOC_REG (39) }, \ | |
2091 | { "loc40", LOC_REG (40) }, \ | |
2092 | { "loc41", LOC_REG (41) }, \ | |
2093 | { "loc42", LOC_REG (42) }, \ | |
2094 | { "loc43", LOC_REG (43) }, \ | |
2095 | { "loc44", LOC_REG (44) }, \ | |
2096 | { "loc45", LOC_REG (45) }, \ | |
2097 | { "loc46", LOC_REG (46) }, \ | |
2098 | { "loc47", LOC_REG (47) }, \ | |
2099 | { "loc48", LOC_REG (48) }, \ | |
2100 | { "loc49", LOC_REG (49) }, \ | |
2101 | { "loc50", LOC_REG (50) }, \ | |
2102 | { "loc51", LOC_REG (51) }, \ | |
2103 | { "loc52", LOC_REG (52) }, \ | |
2104 | { "loc53", LOC_REG (53) }, \ | |
2105 | { "loc54", LOC_REG (54) }, \ | |
2106 | { "loc55", LOC_REG (55) }, \ | |
2107 | { "loc56", LOC_REG (56) }, \ | |
2108 | { "loc57", LOC_REG (57) }, \ | |
2109 | { "loc58", LOC_REG (58) }, \ | |
2110 | { "loc59", LOC_REG (59) }, \ | |
2111 | { "loc60", LOC_REG (60) }, \ | |
2112 | { "loc61", LOC_REG (61) }, \ | |
2113 | { "loc62", LOC_REG (62) }, \ | |
2114 | { "loc63", LOC_REG (63) }, \ | |
2115 | { "loc64", LOC_REG (64) }, \ | |
2116 | { "loc65", LOC_REG (65) }, \ | |
2117 | { "loc66", LOC_REG (66) }, \ | |
2118 | { "loc67", LOC_REG (67) }, \ | |
2119 | { "loc68", LOC_REG (68) }, \ | |
2120 | { "loc69", LOC_REG (69) }, \ | |
2121 | { "loc70", LOC_REG (70) }, \ | |
2122 | { "loc71", LOC_REG (71) }, \ | |
2123 | { "loc72", LOC_REG (72) }, \ | |
2124 | { "loc73", LOC_REG (73) }, \ | |
2125 | { "loc74", LOC_REG (74) }, \ | |
2126 | { "loc75", LOC_REG (75) }, \ | |
2127 | { "loc76", LOC_REG (76) }, \ | |
2128 | { "loc77", LOC_REG (77) }, \ | |
2129 | { "loc78", LOC_REG (78) }, \ | |
794eefd9 | 2130 | { "loc79", LOC_REG (79) }, \ |
c65ebc55 JW |
2131 | } |
2132 | ||
2133 | /* A C compound statement to output to stdio stream STREAM the assembler syntax | |
2134 | for an instruction operand X. X is an RTL expression. */ | |
2135 | ||
2136 | #define PRINT_OPERAND(STREAM, X, CODE) \ | |
2137 | ia64_print_operand (STREAM, X, CODE) | |
2138 | ||
2139 | /* A C expression which evaluates to true if CODE is a valid punctuation | |
2140 | character for use in the `PRINT_OPERAND' macro. */ | |
2141 | ||
2142 | /* ??? Keep this around for now, as we might need it later. */ | |
2143 | ||
6f8aa100 RH |
2144 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
2145 | ((CODE) == '+' || (CODE) == ',') | |
c65ebc55 JW |
2146 | |
2147 | /* A C compound statement to output to stdio stream STREAM the assembler syntax | |
2148 | for an instruction operand that is a memory reference whose address is X. X | |
2149 | is an RTL expression. */ | |
2150 | ||
2151 | #define PRINT_OPERAND_ADDRESS(STREAM, X) \ | |
2152 | ia64_print_operand_address (STREAM, X) | |
2153 | ||
2154 | /* If defined, C string expressions to be used for the `%R', `%L', `%U', and | |
2155 | `%I' options of `asm_fprintf' (see `final.c'). */ | |
2156 | ||
2157 | #define REGISTER_PREFIX "" | |
2158 | #define LOCAL_LABEL_PREFIX "." | |
2159 | #define USER_LABEL_PREFIX "" | |
2160 | #define IMMEDIATE_PREFIX "" | |
2161 | ||
2162 | \f | |
2163 | /* Output of dispatch tables. */ | |
2164 | ||
2165 | /* This macro should be provided on machines where the addresses in a dispatch | |
2166 | table are relative to the table's own address. */ | |
2167 | ||
2168 | /* ??? Depends on the pointer size. */ | |
2169 | ||
2170 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
340f7e7c | 2171 | fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE) |
c65ebc55 JW |
2172 | |
2173 | /* This is how to output an element of a case-vector that is absolute. | |
2174 | (Ia64 does not use such vectors, but we must define this macro anyway.) */ | |
2175 | ||
2176 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort () | |
2177 | ||
c65ebc55 JW |
2178 | /* Jump tables only need 8 byte alignment. */ |
2179 | ||
2180 | #define ADDR_VEC_ALIGN(ADDR_VEC) 3 | |
2181 | ||
2182 | \f | |
2183 | /* Assembler Commands for Exception Regions. */ | |
2184 | ||
2a1ee410 RH |
2185 | /* Select a format to encode pointers in exception handling data. CODE |
2186 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2187 | true if the symbol may be affected by dynamic relocations. */ | |
2188 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
2189 | (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ | |
2190 | | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8) | |
2191 | ||
2192 | /* Handle special EH pointer encodings. Absolute, pc-relative, and | |
2193 | indirect are handled automatically. */ | |
2194 | #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ | |
2195 | do { \ | |
2196 | const char *reltag = NULL; \ | |
2197 | if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ | |
2198 | reltag = "@segrel("; \ | |
2199 | else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ | |
2200 | reltag = "@gprel("; \ | |
2201 | if (reltag) \ | |
2202 | { \ | |
301d03af | 2203 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
2a1ee410 RH |
2204 | fputs (reltag, FILE); \ |
2205 | assemble_name (FILE, XSTR (ADDR, 0)); \ | |
2206 | fputc (')', FILE); \ | |
2207 | goto DONE; \ | |
2208 | } \ | |
2209 | } while (0) | |
c65ebc55 | 2210 | |
c65ebc55 JW |
2211 | \f |
2212 | /* Assembler Commands for Alignment. */ | |
2213 | ||
c65ebc55 JW |
2214 | /* ??? Investigate. */ |
2215 | ||
340f7e7c RH |
2216 | /* The alignment (log base 2) to put in front of LABEL, which follows |
2217 | a BARRIER. */ | |
c65ebc55 JW |
2218 | |
2219 | /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ | |
2220 | ||
2221 | /* The desired alignment for the location counter at the beginning | |
2222 | of a loop. */ | |
2223 | ||
c65ebc55 JW |
2224 | /* #define LOOP_ALIGN(LABEL) */ |
2225 | ||
2226 | /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text | |
2227 | section because it fails put zeros in the bytes that are skipped. */ | |
2228 | ||
2229 | #define ASM_NO_SKIP_IN_TEXT 1 | |
2230 | ||
2231 | /* A C statement to output to the stdio stream STREAM an assembler command to | |
2232 | advance the location counter to a multiple of 2 to the POWER bytes. */ | |
2233 | ||
2234 | #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ | |
2235 | fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) | |
2236 | ||
2237 | \f | |
2238 | /* Macros Affecting all Debug Formats. */ | |
2239 | ||
2240 | /* This is handled in svr4.h and sysv4.h. */ | |
2241 | ||
2242 | \f | |
2243 | /* Specific Options for DBX Output. */ | |
2244 | ||
2245 | /* This is handled by dbxelf.h which is included by svr4.h. */ | |
2246 | ||
2247 | \f | |
2248 | /* Open ended Hooks for DBX Output. */ | |
2249 | ||
2250 | /* Likewise. */ | |
2251 | ||
2252 | \f | |
2253 | /* File names in DBX format. */ | |
2254 | ||
2255 | /* Likewise. */ | |
2256 | ||
2257 | \f | |
2258 | /* Macros for SDB and Dwarf Output. */ | |
2259 | ||
2260 | /* Define this macro if GNU CC should produce dwarf version 2 format debugging | |
2261 | output in response to the `-g' option. */ | |
2262 | ||
2263 | #define DWARF2_DEBUGGING_INFO | |
2264 | ||
c65ebc55 JW |
2265 | #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) |
2266 | ||
8215347e JW |
2267 | /* Use tags for debug info labels, so that they don't break instruction |
2268 | bundles. This also avoids getting spurious DV warnings from the | |
2269 | assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we | |
2270 | add brackets around the label. */ | |
2271 | ||
2272 | #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
7426e9a2 | 2273 | fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM) |
8215347e | 2274 | |
7426e9a2 RH |
2275 | /* Use section-relative relocations for debugging offsets. Unlike other |
2276 | targets that fake this by putting the section VMA at 0, IA-64 has | |
2277 | proper relocations for them. */ | |
2278 | #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \ | |
2279 | do { \ | |
301d03af | 2280 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
7426e9a2 RH |
2281 | fputs ("@secrel(", FILE); \ |
2282 | assemble_name (FILE, LABEL); \ | |
2283 | fputc (')', FILE); \ | |
2284 | } while (0) | |
2285 | ||
2286 | /* Emit a PC-relative relocation. */ | |
2287 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
2288 | do { \ | |
301d03af | 2289 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ |
7426e9a2 RH |
2290 | fputs ("@pcrel(", FILE); \ |
2291 | assemble_name (FILE, LABEL); \ | |
2292 | fputc (')', FILE); \ | |
2293 | } while (0) | |
c65ebc55 JW |
2294 | \f |
2295 | /* Cross Compilation and Floating Point. */ | |
2296 | ||
ed168e45 | 2297 | /* Define to enable software floating point emulation. */ |
c65ebc55 JW |
2298 | #define REAL_ARITHMETIC |
2299 | ||
7b82b5da SC |
2300 | \f |
2301 | /* Register Renaming Parameters. */ | |
2302 | ||
2303 | /* A C expression that is nonzero if hard register number REGNO2 can be | |
2304 | considered for use as a rename register for REGNO1 */ | |
2305 | ||
2306 | #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ | |
10c9f189 | 2307 | ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) |
7b82b5da | 2308 | |
c65ebc55 JW |
2309 | \f |
2310 | /* Miscellaneous Parameters. */ | |
2311 | ||
2312 | /* Define this if you have defined special-purpose predicates in the file | |
2313 | `MACHINE.c'. For each predicate, list all rtl codes that can be in | |
2314 | expressions matched by the predicate. */ | |
2315 | ||
2316 | #define PREDICATE_CODES \ | |
2317 | { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \ | |
ec039e3c | 2318 | { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ |
c65ebc55 JW |
2319 | { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \ |
2320 | { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ | |
2321 | { "function_operand", {SYMBOL_REF}}, \ | |
2322 | { "setjmp_operand", {SYMBOL_REF}}, \ | |
4b983fdc | 2323 | { "destination_operand", {SUBREG, REG, MEM}}, \ |
0551c32d | 2324 | { "not_postinc_memory_operand", {MEM}}, \ |
c65ebc55 JW |
2325 | { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
2326 | CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \ | |
0551c32d RH |
2327 | { "gr_register_operand", {SUBREG, REG}}, \ |
2328 | { "fr_register_operand", {SUBREG, REG}}, \ | |
2329 | { "grfr_register_operand", {SUBREG, REG}}, \ | |
2330 | { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ | |
655f2eb9 | 2331 | { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ |
0551c32d RH |
2332 | { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ |
2333 | { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
2334 | { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2335 | { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2336 | { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2337 | { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
2338 | { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \ | |
c65ebc55 | 2339 | CONSTANT_P_RTX}}, \ |
0551c32d | 2340 | { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \ |
c65ebc55 | 2341 | CONSTANT_P_RTX}}, \ |
0551c32d RH |
2342 | { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ |
2343 | { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ | |
c65ebc55 JW |
2344 | { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ |
2345 | { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \ | |
2346 | CONSTANT_P_RTX}}, \ | |
2347 | { "shladd_operand", {CONST_INT}}, \ | |
2348 | { "fetchadd_operand", {CONST_INT}}, \ | |
0551c32d | 2349 | { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \ |
c65ebc55 JW |
2350 | { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \ |
2351 | { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \ | |
f2f90c63 | 2352 | { "signed_inequality_operator", {GE, GT, LE, LT}}, \ |
5527bf14 | 2353 | { "predicate_operator", {NE, EQ}}, \ |
acb0638d | 2354 | { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \ |
97e242b0 | 2355 | { "ar_lc_reg_operand", {REG}}, \ |
3f622353 | 2356 | { "ar_ccv_reg_operand", {REG}}, \ |
6ca3c22f | 2357 | { "ar_pfs_reg_operand", {REG}}, \ |
3f622353 RH |
2358 | { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ |
2359 | { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ | |
2360 | { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, | |
c65ebc55 JW |
2361 | |
2362 | /* An alias for a machine mode name. This is the machine mode that elements of | |
2363 | a jump-table should have. */ | |
2364 | ||
2365 | #define CASE_VECTOR_MODE Pmode | |
2366 | ||
2367 | /* Define as C expression which evaluates to nonzero if the tablejump | |
2368 | instruction expects the table to contain offsets from the address of the | |
2369 | table. */ | |
2370 | ||
2371 | #define CASE_VECTOR_PC_RELATIVE 1 | |
2372 | ||
2373 | /* Define this macro if operations between registers with integral mode smaller | |
2374 | than a word are always performed on the entire register. */ | |
2375 | ||
2376 | #define WORD_REGISTER_OPERATIONS | |
2377 | ||
2378 | /* Define this macro to be a C expression indicating when insns that read | |
2379 | memory in MODE, an integral mode narrower than a word, set the bits outside | |
2380 | of MODE to be either the sign-extension or the zero-extension of the data | |
2381 | read. */ | |
2382 | ||
2383 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
2384 | ||
c65ebc55 JW |
2385 | /* The maximum number of bytes that a single instruction can move quickly from |
2386 | memory to memory. */ | |
2387 | #define MOVE_MAX 8 | |
2388 | ||
2389 | /* A C expression which is nonzero if on this machine it is safe to "convert" | |
2390 | an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller | |
2391 | than INPREC) by merely operating on it as if it had only OUTPREC bits. */ | |
2392 | ||
2393 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
2394 | ||
2395 | /* A C expression describing the value returned by a comparison operator with | |
2396 | an integral mode and stored by a store-flag instruction (`sCOND') when the | |
2397 | condition is true. */ | |
2398 | ||
2399 | /* ??? Investigate using -1 instead of 1. */ | |
2400 | ||
2401 | #define STORE_FLAG_VALUE 1 | |
2402 | ||
2403 | /* An alias for the machine mode for pointers. */ | |
2404 | ||
2405 | /* ??? This would change if we had ILP32 support. */ | |
2406 | ||
2407 | #define Pmode DImode | |
2408 | ||
2409 | /* An alias for the machine mode used for memory references to functions being | |
2410 | called, in `call' RTL expressions. */ | |
2411 | ||
2412 | #define FUNCTION_MODE Pmode | |
2413 | ||
2414 | /* Define this macro to handle System V style pragmas: #pragma pack and | |
2415 | #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is | |
2416 | defined. */ | |
2417 | ||
8527852a JJ |
2418 | /* If this architecture supports prefetch, define this to be the number of |
2419 | prefetch commands that can be executed in parallel. | |
2420 | ||
2421 | ??? This number is bogus and needs to be replaced before the value is | |
2422 | actually used in optimizations. */ | |
2423 | ||
2424 | #define SIMULTANEOUS_PREFETCHES 6 | |
2425 | ||
2426 | /* If this architecture supports prefetch, define this to be the size of | |
2427 | the cache line that is prefetched. */ | |
2428 | ||
2429 | #define PREFETCH_BLOCK 32 | |
2430 | ||
c65ebc55 JW |
2431 | #define HANDLE_SYSV_PRAGMA |
2432 | ||
c65ebc55 JW |
2433 | /* In rare cases, correct code generation requires extra machine dependent |
2434 | processing between the second jump optimization pass and delayed branch | |
2435 | scheduling. On those machines, define this macro as a C statement to act on | |
2436 | the code starting at INSN. */ | |
2437 | ||
2438 | #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN) | |
2439 | ||
2440 | /* A C expression for the maximum number of instructions to execute via | |
2441 | conditional execution instructions instead of a branch. A value of | |
2442 | BRANCH_COST+1 is the default if the machine does not use | |
2443 | cc0, and 1 if it does use cc0. */ | |
2444 | /* ??? Investigate. */ | |
2130b7fb BS |
2445 | #define MAX_CONDITIONAL_EXECUTE 12 |
2446 | ||
2130b7fb | 2447 | extern int ia64_final_schedule; |
c65ebc55 | 2448 | |
0c96007e | 2449 | #define IA64_UNWIND_INFO 1 |
0c96007e AM |
2450 | #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i) |
2451 | ||
2a1ee410 RH |
2452 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) |
2453 | ||
0c96007e AM |
2454 | /* This function contains machine specific function data. */ |
2455 | struct machine_function | |
2456 | { | |
2457 | /* The new stack pointer when unwinding from EH. */ | |
2458 | struct rtx_def* ia64_eh_epilogue_sp; | |
2459 | ||
ed168e45 | 2460 | /* The new bsp value when unwinding from EH. */ |
0c96007e | 2461 | struct rtx_def* ia64_eh_epilogue_bsp; |
97e242b0 RH |
2462 | |
2463 | /* The GP value save register. */ | |
2464 | struct rtx_def* ia64_gp_save; | |
26a110f5 RH |
2465 | |
2466 | /* The number of varargs registers to save. */ | |
2467 | int n_varargs; | |
0c96007e AM |
2468 | }; |
2469 | ||
2470 | ||
c65ebc55 JW |
2471 | enum ia64_builtins |
2472 | { | |
2473 | IA64_BUILTIN_SYNCHRONIZE, | |
2474 | ||
2475 | IA64_BUILTIN_FETCH_AND_ADD_SI, | |
2476 | IA64_BUILTIN_FETCH_AND_SUB_SI, | |
2477 | IA64_BUILTIN_FETCH_AND_OR_SI, | |
2478 | IA64_BUILTIN_FETCH_AND_AND_SI, | |
2479 | IA64_BUILTIN_FETCH_AND_XOR_SI, | |
2480 | IA64_BUILTIN_FETCH_AND_NAND_SI, | |
2481 | ||
2482 | IA64_BUILTIN_ADD_AND_FETCH_SI, | |
2483 | IA64_BUILTIN_SUB_AND_FETCH_SI, | |
2484 | IA64_BUILTIN_OR_AND_FETCH_SI, | |
2485 | IA64_BUILTIN_AND_AND_FETCH_SI, | |
2486 | IA64_BUILTIN_XOR_AND_FETCH_SI, | |
2487 | IA64_BUILTIN_NAND_AND_FETCH_SI, | |
2488 | ||
2489 | IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI, | |
2490 | IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI, | |
2491 | ||
2492 | IA64_BUILTIN_SYNCHRONIZE_SI, | |
2493 | ||
2494 | IA64_BUILTIN_LOCK_TEST_AND_SET_SI, | |
2495 | ||
2496 | IA64_BUILTIN_LOCK_RELEASE_SI, | |
2497 | ||
2498 | IA64_BUILTIN_FETCH_AND_ADD_DI, | |
2499 | IA64_BUILTIN_FETCH_AND_SUB_DI, | |
2500 | IA64_BUILTIN_FETCH_AND_OR_DI, | |
2501 | IA64_BUILTIN_FETCH_AND_AND_DI, | |
2502 | IA64_BUILTIN_FETCH_AND_XOR_DI, | |
2503 | IA64_BUILTIN_FETCH_AND_NAND_DI, | |
2504 | ||
2505 | IA64_BUILTIN_ADD_AND_FETCH_DI, | |
2506 | IA64_BUILTIN_SUB_AND_FETCH_DI, | |
2507 | IA64_BUILTIN_OR_AND_FETCH_DI, | |
2508 | IA64_BUILTIN_AND_AND_FETCH_DI, | |
2509 | IA64_BUILTIN_XOR_AND_FETCH_DI, | |
2510 | IA64_BUILTIN_NAND_AND_FETCH_DI, | |
2511 | ||
2512 | IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI, | |
2513 | IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI, | |
2514 | ||
2515 | IA64_BUILTIN_SYNCHRONIZE_DI, | |
2516 | ||
2517 | IA64_BUILTIN_LOCK_TEST_AND_SET_DI, | |
2518 | ||
ce152ef8 AM |
2519 | IA64_BUILTIN_LOCK_RELEASE_DI, |
2520 | ||
2521 | IA64_BUILTIN_BSP, | |
2522 | IA64_BUILTIN_FLUSHRS | |
c65ebc55 JW |
2523 | }; |
2524 | ||
ed168e45 | 2525 | /* Codes for expand_compare_and_swap and expand_swap_and_compare. */ |
c65ebc55 JW |
2526 | enum fetchop_code { |
2527 | IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP | |
2528 | }; | |
2529 | ||
c65ebc55 | 2530 | /* End of ia64.h */ |