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c65ebc55 | 1 | ;; IA-64 Machine description template |
f4ef873c | 2 | ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
e5bde68a RH |
51 | ;; Unspec usage: |
52 | ;; | |
53 | ;; unspec: | |
54 | ;; 1 gr_spill | |
55 | ;; 2 gr_restore | |
56 | ;; 3 fr_spill | |
57 | ;; 4 fr_restore | |
655f2eb9 | 58 | ;; 5 recip_approx |
f2f90c63 | 59 | ;; 7 pred_rel_mutex |
e5bde68a | 60 | ;; 8 popcnt |
2ed4af6f | 61 | ;; 9 pic call |
97e242b0 | 62 | ;; 12 mf |
e5bde68a | 63 | ;; 13 cmpxchg_acq |
e5bde68a RH |
64 | ;; 19 fetchadd_acq |
65 | ;; 20 bsp_value | |
ce152ef8 | 66 | ;; 21 flushrs |
2130b7fb BS |
67 | ;; 22 bundle selector |
68 | ;; 23 cycle display | |
e5bde68a RH |
69 | ;; |
70 | ;; unspec_volatile: | |
71 | ;; 0 alloc | |
72 | ;; 1 blockage | |
73 | ;; 2 insn_group_barrier | |
f12f25a7 | 74 | ;; 3 break |
e5bde68a | 75 | ;; 5 set_bsp |
ca3920ad JW |
76 | ;; 8 pred.safe_across_calls all |
77 | ;; 9 pred.safe_across_calls normal | |
c65ebc55 JW |
78 | \f |
79 | ;; :::::::::::::::::::: | |
80 | ;; :: | |
81 | ;; :: Attributes | |
82 | ;; :: | |
83 | ;; :::::::::::::::::::: | |
84 | ||
85 | ;; Instruction type. This primarily determines how instructions can be | |
86 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
87 | ||
88 | ;; A alu, can go in I or M syllable of a bundle | |
89 | ;; I integer | |
90 | ;; M memory | |
91 | ;; F floating-point | |
92 | ;; B branch | |
93 | ;; L long immediate, takes two syllables | |
94 | ;; S stop bit | |
95 | ||
96 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
97 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
98 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
99 | ;; which emit instruction that can go in any slot (e.g. nop). | |
100 | ||
2130b7fb | 101 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x" |
52e12ad0 BS |
102 | (const_string "unknown")) |
103 | ||
2130b7fb BS |
104 | ;; chk_s has an I and an M form; use type A for convenience. |
105 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
106 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
107 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
108 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
2130b7fb BS |
109 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
110 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
111 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
112 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
113 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
114 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
115 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 116 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 117 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
118 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
119 | (const_string "unknown"))) | |
c65ebc55 | 120 | |
2130b7fb BS |
121 | (define_attr "itanium_requires_unit0" "no,yes" |
122 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
123 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
124 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
125 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
126 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
127 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
128 | (const_string "no"))) | |
129 | ||
e5bde68a RH |
130 | ;; Predication. True iff this instruction can be predicated. |
131 | ||
132 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
133 | ||
c65ebc55 JW |
134 | \f |
135 | ;; :::::::::::::::::::: | |
136 | ;; :: | |
137 | ;; :: Function Units | |
138 | ;; :: | |
139 | ;; :::::::::::::::::::: | |
140 | ||
2130b7fb BS |
141 | ;; We define 6 "dummy" functional units. All the real work to decide which |
142 | ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only | |
143 | ;; have to ensure here that there are enough copies of the dummy unit so | |
144 | ;; that the scheduler doesn't get confused by MD_SCHED_REORDER. | |
145 | ;; Other than the 6 dummies for normal insns, we also add a single dummy unit | |
146 | ;; for stop bits. | |
147 | ||
148 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0) | |
149 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0) | |
150 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0) | |
151 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0) | |
152 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0) | |
153 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0) | |
154 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0) | |
155 | ||
156 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
157 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0) | |
158 | ;; There is only ony insn `mov = ar.unat' for frar_m: | |
159 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0) | |
160 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0) | |
161 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0) | |
162 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0) | |
163 | ||
164 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0) | |
165 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0) | |
166 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0) | |
167 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0) | |
168 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0) | |
169 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0) | |
170 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0) | |
171 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0) | |
172 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0) | |
173 | ||
174 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
175 | ;; is the 1st syllable of the bundle after stop bit. | |
176 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0) | |
177 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0) | |
178 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0) | |
179 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0) | |
180 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0) | |
181 | ;; Now we use only one insn `mf'. Therfore latency time is set up to 0. | |
182 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0) | |
183 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0) | |
184 | ||
185 | ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use | |
186 | ;; latency time equal to 0: | |
187 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0) | |
188 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
189 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0) | |
190 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0) | |
191 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0) | |
192 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0) | |
193 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0) | |
194 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0) | |
195 | ||
196 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0) | |
197 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0) | |
198 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0) | |
199 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0) | |
200 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0) | |
201 | ||
202 | (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0) | |
203 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0) | |
204 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0) | |
c65ebc55 JW |
205 | \f |
206 | ;; :::::::::::::::::::: | |
207 | ;; :: | |
208 | ;; :: Moves | |
209 | ;; :: | |
210 | ;; :::::::::::::::::::: | |
211 | ||
f2f90c63 RH |
212 | ;; Set of a single predicate register. This is only used to implement |
213 | ;; pr-to-pr move and complement. | |
214 | ||
215 | (define_insn "*movcci" | |
216 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
217 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
218 | "" | |
219 | "@ | |
220 | cmp.ne %0, p0 = r0, r0 | |
221 | cmp.eq %0, p0 = r0, r0 | |
222 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 223 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
224 | (set_attr "predicable" "no")]) |
225 | ||
226 | (define_insn "movbi" | |
cd5c4048 RH |
227 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
228 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
229 | "" |
230 | "@ | |
231 | cmp.ne %0, %I0 = r0, r0 | |
232 | cmp.eq %0, %I0 = r0, r0 | |
233 | # | |
234 | # | |
235 | tbit.nz %0, %I0 = %1, 0 | |
236 | adds %0 = %1, r0 | |
237 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
238 | st1%Q0 %0 = %1%P0 |
239 | mov %0 = %1" | |
52e12ad0 | 240 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
241 | |
242 | (define_split | |
243 | [(set (match_operand:BI 0 "register_operand" "") | |
244 | (match_operand:BI 1 "register_operand" ""))] | |
245 | "reload_completed | |
246 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
247 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
248 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
249 | (set (match_dup 0) (const_int 1))) | |
250 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
251 | (set (match_dup 0) (const_int 0)))] | |
252 | "") | |
253 | ||
254 | (define_split | |
255 | [(set (match_operand:BI 0 "register_operand" "") | |
256 | (match_operand:BI 1 "register_operand" ""))] | |
257 | "reload_completed | |
258 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
259 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
260 | [(set (match_dup 2) (match_dup 4)) | |
261 | (set (match_dup 3) (match_dup 5)) | |
262 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
263 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); | |
264 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
265 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
266 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
267 | ||
c65ebc55 JW |
268 | (define_expand "movqi" |
269 | [(set (match_operand:QI 0 "general_operand" "") | |
270 | (match_operand:QI 1 "general_operand" ""))] | |
271 | "" | |
272 | " | |
273 | { | |
274 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
275 | && ! ia64_move_ok (operands[0], operands[1])) |
276 | operands[1] = force_reg (QImode, operands[1]); | |
c65ebc55 JW |
277 | }") |
278 | ||
279 | (define_insn "*movqi_internal" | |
4b983fdc RH |
280 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
281 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 282 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 283 | "@ |
13da91fd | 284 | mov %0 = %r1 |
c65ebc55 JW |
285 | addl %0 = %1, r0 |
286 | ld1%O1 %0 = %1%P1 | |
13da91fd | 287 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 288 | getf.sig %0 = %1 |
13da91fd RH |
289 | setf.sig %0 = %r1 |
290 | mov %0 = %1" | |
52e12ad0 | 291 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
292 | |
293 | (define_expand "movhi" | |
294 | [(set (match_operand:HI 0 "general_operand" "") | |
295 | (match_operand:HI 1 "general_operand" ""))] | |
296 | "" | |
297 | " | |
298 | { | |
299 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
300 | && ! ia64_move_ok (operands[0], operands[1])) |
301 | operands[1] = force_reg (HImode, operands[1]); | |
c65ebc55 JW |
302 | }") |
303 | ||
304 | (define_insn "*movhi_internal" | |
4b983fdc RH |
305 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
306 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 307 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 308 | "@ |
13da91fd | 309 | mov %0 = %r1 |
c65ebc55 JW |
310 | addl %0 = %1, r0 |
311 | ld2%O1 %0 = %1%P1 | |
13da91fd | 312 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 313 | getf.sig %0 = %1 |
13da91fd RH |
314 | setf.sig %0 = %r1 |
315 | mov %0 = %1" | |
52e12ad0 | 316 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
317 | |
318 | (define_expand "movsi" | |
319 | [(set (match_operand:SI 0 "general_operand" "") | |
320 | (match_operand:SI 1 "general_operand" ""))] | |
321 | "" | |
322 | " | |
323 | { | |
324 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
325 | && ! ia64_move_ok (operands[0], operands[1])) |
326 | operands[1] = force_reg (SImode, operands[1]); | |
c65ebc55 JW |
327 | }") |
328 | ||
329 | (define_insn "*movsi_internal" | |
97e242b0 | 330 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 331 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 332 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 333 | "@ |
13da91fd | 334 | mov %0 = %r1 |
c65ebc55 JW |
335 | addl %0 = %1, r0 |
336 | movl %0 = %1 | |
337 | ld4%O1 %0 = %1%P1 | |
13da91fd | 338 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 339 | getf.sig %0 = %1 |
13da91fd | 340 | setf.sig %0 = %r1 |
97e242b0 RH |
341 | mov %0 = %1 |
342 | mov %0 = %1 | |
343 | mov %0 = %r1" | |
52e12ad0 BS |
344 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
345 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) | |
c65ebc55 JW |
346 | |
347 | (define_expand "movdi" | |
348 | [(set (match_operand:DI 0 "general_operand" "") | |
349 | (match_operand:DI 1 "general_operand" ""))] | |
350 | "" | |
351 | " | |
352 | { | |
9a89adb8 RH |
353 | if (! reload_in_progress && ! reload_completed |
354 | && ! ia64_move_ok (operands[0], operands[1])) | |
355 | operands[1] = force_reg (DImode, operands[1]); | |
ec039e3c | 356 | if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode)) |
c65ebc55 | 357 | { |
9a89adb8 RH |
358 | /* Before optimization starts, delay committing to any particular |
359 | type of PIC address load. If this function gets deferred, we | |
360 | may acquire information that changes the value of the | |
361 | sdata_symbolic_operand predicate. */ | |
7c866fb5 JW |
362 | /* But don't delay for function pointers. Loading a function address |
363 | actually loads the address of the descriptor not the function. | |
364 | If we represent these as SYMBOL_REFs, then they get cse'd with | |
365 | calls, and we end up with calls to the descriptor address instead of | |
366 | calls to the function address. Functions are not candidates for | |
367 | sdata anyways. */ | |
368 | if (rtx_equal_function_value_matters | |
369 | && ! (GET_CODE (operands[1]) == SYMBOL_REF | |
370 | && SYMBOL_REF_FLAG (operands[1]))) | |
b5d37c6f | 371 | emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode))); |
9a89adb8 | 372 | else |
b5d37c6f | 373 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d | 374 | DONE; |
c65ebc55 | 375 | } |
c65ebc55 JW |
376 | }") |
377 | ||
9a89adb8 RH |
378 | ;; This is used during early compilation to delay the decision on |
379 | ;; how to refer to a variable as long as possible. This is especially | |
380 | ;; important between initial rtl generation and optimization for | |
381 | ;; deferred functions, since we may acquire additional information | |
382 | ;; on the variables used in the meantime. | |
383 | ||
ef375129 JW |
384 | ;; ??? This causes us to lose REG_LABEL notes, because the insn splitter |
385 | ;; does not attempt to preserve any REG_NOTES on the input instruction. | |
386 | ||
9a89adb8 RH |
387 | (define_insn_and_split "movdi_symbolic" |
388 | [(set (match_operand:DI 0 "register_operand" "=r") | |
389 | (match_operand:DI 1 "symbolic_operand" "s")) | |
b5d37c6f | 390 | (clobber (match_operand:DI 2 "register_operand" "+r")) |
9a89adb8 RH |
391 | (use (reg:DI 1))] |
392 | "" | |
393 | "* abort ();" | |
394 | "" | |
395 | [(const_int 0)] | |
b5d37c6f | 396 | "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;") |
9a89adb8 | 397 | |
c65ebc55 | 398 | (define_insn "*movdi_internal" |
4b983fdc | 399 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 400 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 401 | (match_operand:DI 1 "move_operand" |
52e12ad0 | 402 | "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 403 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
404 | "* |
405 | { | |
406 | static const char * const alt[] = { | |
6f8aa100 RH |
407 | \"%,mov %0 = %r1\", |
408 | \"%,addl %0 = %1, r0\", | |
409 | \"%,movl %0 = %1\", | |
410 | \"%,ld8%O1 %0 = %1%P1\", | |
411 | \"%,st8%Q0 %0 = %r1%P0\", | |
412 | \"%,getf.sig %0 = %1\", | |
413 | \"%,setf.sig %0 = %r1\", | |
414 | \"%,mov %0 = %1\", | |
415 | \"%,ldf8 %0 = %1%P1\", | |
416 | \"%,stf8 %0 = %1%P0\", | |
417 | \"%,mov %0 = %1\", | |
5527bf14 RH |
418 | \"%,mov %0 = %r1\", |
419 | \"%,mov %0 = %1\", | |
514f96e6 RH |
420 | \"%,mov %0 = %1\", |
421 | \"%,mov %0 = %1\", | |
52e12ad0 | 422 | \"%,mov %0 = %1\", |
97e242b0 RH |
423 | \"mov %0 = pr\", |
424 | \"mov pr = %1, -1\" | |
9b7bf67d RH |
425 | }; |
426 | ||
9b7bf67d RH |
427 | if (which_alternative == 2 && ! TARGET_NO_PIC |
428 | && symbolic_operand (operands[1], VOIDmode)) | |
429 | abort (); | |
430 | ||
431 | return alt[which_alternative]; | |
432 | }" | |
52e12ad0 | 433 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 434 | |
9b7bf67d RH |
435 | (define_split |
436 | [(set (match_operand:DI 0 "register_operand" "") | |
437 | (match_operand:DI 1 "symbolic_operand" ""))] | |
438 | "reload_completed && ! TARGET_NO_PIC" | |
439 | [(const_int 0)] | |
440 | " | |
441 | { | |
b5d37c6f | 442 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d RH |
443 | DONE; |
444 | }") | |
445 | ||
c65ebc55 JW |
446 | (define_expand "load_fptr" |
447 | [(set (match_dup 2) | |
448 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" ""))) | |
ec039e3c | 449 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
450 | "" |
451 | " | |
452 | { | |
ec039e3c RH |
453 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
454 | operands[3] = gen_rtx_MEM (DImode, operands[2]); | |
455 | RTX_UNCHANGING_P (operands[3]) = 1; | |
c65ebc55 JW |
456 | }") |
457 | ||
458 | (define_insn "*load_fptr_internal1" | |
459 | [(set (match_operand:DI 0 "register_operand" "=r") | |
460 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))] | |
461 | "" | |
462 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 463 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
464 | |
465 | (define_insn "load_gprel" | |
466 | [(set (match_operand:DI 0 "register_operand" "=r") | |
467 | (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))] | |
468 | "" | |
469 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 470 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 471 | |
59da9a7d JW |
472 | (define_insn "gprel64_offset" |
473 | [(set (match_operand:DI 0 "register_operand" "=r") | |
474 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
475 | "" | |
476 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 477 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
478 | |
479 | (define_expand "load_gprel64" | |
480 | [(set (match_dup 2) | |
b5d37c6f | 481 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 482 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 483 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 484 | "" |
ec039e3c RH |
485 | " |
486 | { | |
487 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 488 | operands[3] = pic_offset_table_rtx; |
59da9a7d JW |
489 | }") |
490 | ||
c65ebc55 | 491 | (define_expand "load_symptr" |
b5d37c6f BS |
492 | [(set (match_operand:DI 2 "register_operand" "") |
493 | (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) | |
dee4095a | 494 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
495 | "" |
496 | " | |
497 | { | |
dee4095a | 498 | operands[3] = gen_rtx_MEM (DImode, operands[2]); |
b5d37c6f | 499 | operands[4] = pic_offset_table_rtx; |
dee4095a | 500 | RTX_UNCHANGING_P (operands[3]) = 1; |
c65ebc55 JW |
501 | }") |
502 | ||
503 | (define_insn "*load_symptr_internal1" | |
504 | [(set (match_operand:DI 0 "register_operand" "=r") | |
ec039e3c | 505 | (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))] |
c65ebc55 JW |
506 | "" |
507 | "addl %0 = @ltoff(%1), gp" | |
52e12ad0 | 508 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 509 | |
3f622353 RH |
510 | ;; With no offsettable memory references, we've got to have a scratch |
511 | ;; around to play with the second word. | |
512 | (define_expand "movti" | |
513 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
514 | (match_operand:TI 1 "general_operand" "")) | |
515 | (clobber (match_scratch:DI 2 ""))])] | |
516 | "" | |
517 | " | |
518 | { | |
519 | if (! reload_in_progress && ! reload_completed | |
520 | && ! ia64_move_ok (operands[0], operands[1])) | |
521 | operands[1] = force_reg (TImode, operands[1]); | |
522 | }") | |
523 | ||
524 | (define_insn_and_split "*movti_internal" | |
525 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
526 | (match_operand:TI 1 "general_operand" "ri,m,r")) | |
527 | (clobber (match_scratch:DI 2 "=X,&r,&r"))] | |
528 | "ia64_move_ok (operands[0], operands[1])" | |
529 | "#" | |
530 | "reload_completed" | |
531 | [(const_int 0)] | |
532 | " | |
533 | { | |
534 | rtx adj1, adj2, in[2], out[2]; | |
535 | int first; | |
536 | ||
537 | adj1 = ia64_split_timode (in, operands[1], operands[2]); | |
538 | adj2 = ia64_split_timode (out, operands[0], operands[2]); | |
539 | ||
540 | first = 0; | |
541 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
542 | { | |
543 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
544 | abort (); | |
545 | first = 1; | |
546 | } | |
547 | ||
548 | if (adj1 && adj2) | |
549 | abort (); | |
550 | if (adj1) | |
551 | emit_insn (adj1); | |
552 | if (adj2) | |
553 | emit_insn (adj2); | |
554 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
555 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
556 | DONE; | |
557 | }" | |
52e12ad0 | 558 | [(set_attr "itanium_class" "unknown") |
3f622353 | 559 | (set_attr "predicable" "no")]) |
e314e331 | 560 | |
3f622353 RH |
561 | ;; ??? SSA creates these. Can't allow memories since we don't have |
562 | ;; the scratch register. Fortunately combine will know how to add | |
563 | ;; the clobber and scratch. | |
564 | (define_insn_and_split "*movti_internal_reg" | |
565 | [(set (match_operand:TI 0 "register_operand" "=r") | |
566 | (match_operand:TI 1 "nonmemory_operand" "ri"))] | |
567 | "" | |
e314e331 | 568 | "#" |
3f622353 RH |
569 | "reload_completed" |
570 | [(const_int 0)] | |
571 | " | |
572 | { | |
573 | rtx in[2], out[2]; | |
574 | int first; | |
575 | ||
576 | ia64_split_timode (in, operands[1], NULL_RTX); | |
577 | ia64_split_timode (out, operands[0], NULL_RTX); | |
578 | ||
579 | first = 0; | |
580 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
581 | { | |
582 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
583 | abort (); | |
584 | first = 1; | |
585 | } | |
586 | ||
587 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
588 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
589 | DONE; | |
590 | }" | |
52e12ad0 | 591 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
592 | (set_attr "predicable" "no")]) |
593 | ||
3f622353 RH |
594 | (define_expand "reload_inti" |
595 | [(parallel [(set (match_operand:TI 0 "register_operand" "=r") | |
596 | (match_operand:TI 1 "" "m")) | |
60a3c181 | 597 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
598 | "" |
599 | " | |
600 | { | |
60a3c181 RH |
601 | unsigned int s_regno = REGNO (operands[2]); |
602 | if (s_regno == REGNO (operands[0])) | |
603 | s_regno += 1; | |
604 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 RH |
605 | }") |
606 | ||
607 | (define_expand "reload_outti" | |
608 | [(parallel [(set (match_operand:TI 0 "" "=m") | |
609 | (match_operand:TI 1 "register_operand" "r")) | |
60a3c181 | 610 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
611 | "" |
612 | " | |
613 | { | |
60a3c181 RH |
614 | unsigned int s_regno = REGNO (operands[2]); |
615 | if (s_regno == REGNO (operands[1])) | |
616 | s_regno += 1; | |
617 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 | 618 | }") |
e314e331 | 619 | |
c65ebc55 JW |
620 | ;; Floating Point Moves |
621 | ;; | |
622 | ;; Note - Patterns for SF mode moves are compulsory, but | |
623 | ;; patterns for DF are optional, as GCC can synthesise them. | |
624 | ||
625 | (define_expand "movsf" | |
626 | [(set (match_operand:SF 0 "general_operand" "") | |
627 | (match_operand:SF 1 "general_operand" ""))] | |
628 | "" | |
629 | " | |
630 | { | |
631 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
632 | && ! ia64_move_ok (operands[0], operands[1])) |
633 | operands[1] = force_reg (SFmode, operands[1]); | |
c65ebc55 JW |
634 | }") |
635 | ||
c65ebc55 | 636 | (define_insn "*movsf_internal" |
4b983fdc RH |
637 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
638 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 639 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
640 | "@ |
641 | mov %0 = %F1 | |
642 | ldfs %0 = %1%P1 | |
643 | stfs %0 = %F1%P0 | |
644 | getf.s %0 = %F1 | |
645 | setf.s %0 = %1 | |
646 | mov %0 = %1 | |
13da91fd RH |
647 | ld4%O1 %0 = %1%P1 |
648 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 649 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
650 | |
651 | (define_expand "movdf" | |
652 | [(set (match_operand:DF 0 "general_operand" "") | |
653 | (match_operand:DF 1 "general_operand" ""))] | |
654 | "" | |
655 | " | |
656 | { | |
657 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
658 | && ! ia64_move_ok (operands[0], operands[1])) |
659 | operands[1] = force_reg (DFmode, operands[1]); | |
c65ebc55 JW |
660 | }") |
661 | ||
c65ebc55 | 662 | (define_insn "*movdf_internal" |
4b983fdc RH |
663 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
664 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 665 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
666 | "@ |
667 | mov %0 = %F1 | |
668 | ldfd %0 = %1%P1 | |
669 | stfd %0 = %F1%P0 | |
670 | getf.d %0 = %F1 | |
671 | setf.d %0 = %1 | |
13da91fd RH |
672 | mov %0 = %1 |
673 | ld8%O1 %0 = %1%P1 | |
674 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 675 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 676 | |
3f622353 RH |
677 | ;; With no offsettable memory references, we've got to have a scratch |
678 | ;; around to play with the second word if the variable winds up in GRs. | |
679 | (define_expand "movtf" | |
680 | [(set (match_operand:TF 0 "general_operand" "") | |
681 | (match_operand:TF 1 "general_operand" ""))] | |
23c108af | 682 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a RH |
683 | " |
684 | { | |
3f622353 RH |
685 | /* We must support TFmode loads into general registers for stdarg/vararg |
686 | and unprototyped calls. We split them into DImode loads for convenience. | |
687 | We don't need TFmode stores from general regs, because a stdarg/vararg | |
688 | routine does a block store to memory of unnamed arguments. */ | |
689 | if (GET_CODE (operands[0]) == REG | |
690 | && GR_REGNO_P (REGNO (operands[0]))) | |
691 | { | |
692 | /* We're hoping to transform everything that deals with TFmode | |
693 | quantities and GR registers early in the compiler. */ | |
694 | if (no_new_pseudos) | |
695 | abort (); | |
696 | ||
697 | /* Struct to register can just use TImode instead. */ | |
698 | if ((GET_CODE (operands[1]) == SUBREG | |
699 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
700 | || (GET_CODE (operands[1]) == REG | |
701 | && GR_REGNO_P (REGNO (operands[1])))) | |
702 | { | |
703 | emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), | |
704 | SUBREG_REG (operands[1])); | |
705 | DONE; | |
706 | } | |
707 | ||
708 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
709 | { | |
710 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), | |
2bf47a10 | 711 | operand_subword (operands[1], 0, 0, TFmode)); |
3f622353 | 712 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), |
2bf47a10 | 713 | operand_subword (operands[1], 1, 0, TFmode)); |
3f622353 RH |
714 | DONE; |
715 | } | |
716 | ||
717 | /* If the quantity is in a register not known to be GR, spill it. */ | |
718 | if (register_operand (operands[1], TFmode)) | |
719 | operands[1] = spill_tfmode_operand (operands[1], 1); | |
720 | ||
721 | if (GET_CODE (operands[1]) == MEM) | |
722 | { | |
723 | rtx out[2]; | |
724 | ||
725 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
726 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); | |
727 | ||
f4ef873c RK |
728 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
729 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
730 | DONE; |
731 | } | |
732 | ||
733 | abort (); | |
734 | } | |
735 | ||
736 | if (! reload_in_progress && ! reload_completed) | |
737 | { | |
738 | operands[0] = spill_tfmode_operand (operands[0], 0); | |
739 | operands[1] = spill_tfmode_operand (operands[1], 0); | |
740 | ||
741 | if (! ia64_move_ok (operands[0], operands[1])) | |
742 | operands[1] = force_reg (TFmode, operands[1]); | |
743 | } | |
e5bde68a RH |
744 | }") |
745 | ||
3b572406 | 746 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 747 | |
3f622353 RH |
748 | (define_insn "*movtf_internal" |
749 | [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m") | |
750 | (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] | |
23c108af | 751 | "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" |
e5bde68a RH |
752 | "@ |
753 | mov %0 = %F1 | |
46b1ac3f JW |
754 | ldfe %0 = %1%P1 |
755 | stfe %0 = %F1%P0" | |
52e12ad0 | 756 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
c65ebc55 JW |
757 | \f |
758 | ;; :::::::::::::::::::: | |
759 | ;; :: | |
760 | ;; :: Conversions | |
761 | ;; :: | |
762 | ;; :::::::::::::::::::: | |
763 | ||
764 | ;; Signed conversions from a smaller integer to a larger integer | |
765 | ||
766 | (define_insn "extendqidi2" | |
0551c32d RH |
767 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
768 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
769 | "" |
770 | "sxt1 %0 = %1" | |
52e12ad0 | 771 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
772 | |
773 | (define_insn "extendhidi2" | |
0551c32d RH |
774 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
775 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
776 | "" |
777 | "sxt2 %0 = %1" | |
52e12ad0 | 778 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
779 | |
780 | (define_insn "extendsidi2" | |
655f2eb9 RH |
781 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
782 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
783 | "" |
784 | "@ | |
785 | sxt4 %0 = %1 | |
aebf2462 | 786 | fsxt.r %0 = %1, %1" |
52e12ad0 | 787 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
788 | |
789 | ;; Unsigned conversions from a smaller integer to a larger integer | |
790 | ||
791 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
792 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
793 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
794 | "" |
795 | "@ | |
796 | zxt1 %0 = %1 | |
797 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 798 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
799 | |
800 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
801 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
802 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
803 | "" |
804 | "@ | |
805 | zxt2 %0 = %1 | |
806 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 807 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
808 | |
809 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 810 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 811 | (zero_extend:DI |
655f2eb9 | 812 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
813 | "" |
814 | "@ | |
815 | zxt4 %0 = %1 | |
816 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 817 | fmix.r %0 = f0, %1" |
52e12ad0 | 818 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
819 | |
820 | ;; Convert between floating point types of different sizes. | |
821 | ||
640cea5f JW |
822 | ;; At first glance, it would appear that emitting fnorm for an extending |
823 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
824 | ;; correctly only if the input is properly rounded for its type. In | |
825 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
826 | ;; denorm single. Since we don't know what the next instruction will be, we | |
827 | ;; have to emit an fnorm. | |
828 | ||
e8e20f18 RH |
829 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
830 | ;; when we can. Should probably use a scheme like has been proposed | |
831 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
832 | ;; would let combine merge the thing into adjacent insns. See also how the |
833 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
834 | ;; se_register_operand. | |
c65ebc55 | 835 | |
640cea5f JW |
836 | (define_insn "extendsfdf2" |
837 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
838 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 839 | "" |
640cea5f JW |
840 | "fnorm.d %0 = %1" |
841 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 842 | |
640cea5f JW |
843 | (define_insn "extendsftf2" |
844 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
845 | (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))] | |
23c108af | 846 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
847 | "fnorm %0 = %1" |
848 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 849 | |
640cea5f JW |
850 | (define_insn "extenddftf2" |
851 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
852 | (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))] | |
23c108af | 853 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
854 | "fnorm %0 = %1" |
855 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 856 | |
c65ebc55 | 857 | (define_insn "truncdfsf2" |
0551c32d RH |
858 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
859 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 860 | "" |
aebf2462 | 861 | "fnorm.s %0 = %1" |
52e12ad0 | 862 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 863 | |
3f622353 | 864 | (define_insn "trunctfsf2" |
0551c32d RH |
865 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
866 | (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 867 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 868 | "fnorm.s %0 = %1" |
52e12ad0 | 869 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 870 | |
3f622353 | 871 | (define_insn "trunctfdf2" |
0551c32d RH |
872 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
873 | (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 874 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 875 | "fnorm.d %0 = %1" |
52e12ad0 | 876 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
877 | |
878 | ;; Convert between signed integer types and floating point. | |
879 | ||
3f622353 | 880 | (define_insn "floatditf2" |
0551c32d RH |
881 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
882 | (float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 883 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 884 | "fcvt.xf %0 = %1" |
52e12ad0 | 885 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 886 | |
23c108af SE |
887 | ;; ??? Suboptimal. This should be split somehow. |
888 | (define_insn "floatdidf2" | |
889 | [(set (match_operand:DF 0 "register_operand" "=f") | |
890 | (float:DF (match_operand:DI 1 "register_operand" "f")))] | |
891 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
892 | "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0" | |
893 | [(set_attr "itanium_class" "fcvtfx")]) | |
894 | ||
895 | ;; ??? Suboptimal. This should be split somehow. | |
896 | (define_insn "floatdisf2" | |
897 | [(set (match_operand:SF 0 "register_operand" "=f") | |
898 | (float:SF (match_operand:DI 1 "register_operand" "f")))] | |
899 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
900 | "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0" | |
901 | [(set_attr "itanium_class" "fcvtfx")]) | |
902 | ||
c65ebc55 | 903 | (define_insn "fix_truncsfdi2" |
0551c32d RH |
904 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
905 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 906 | "" |
aebf2462 | 907 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 908 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
909 | |
910 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
911 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
912 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 913 | "" |
aebf2462 | 914 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 915 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 916 | |
3f622353 | 917 | (define_insn "fix_trunctfdi2" |
0551c32d RH |
918 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
919 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 920 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 921 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 922 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 923 | |
655f2eb9 RH |
924 | (define_insn "fix_trunctfdi2_alts" |
925 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
926 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
927 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 928 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 929 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 930 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 931 | |
c65ebc55 JW |
932 | ;; Convert between unsigned integer types and floating point. |
933 | ||
934 | (define_insn "floatunsdisf2" | |
0551c32d RH |
935 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
936 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 937 | "" |
aebf2462 | 938 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 939 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
940 | |
941 | (define_insn "floatunsdidf2" | |
0551c32d RH |
942 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
943 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 944 | "" |
aebf2462 | 945 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 946 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 947 | |
3f622353 | 948 | (define_insn "floatunsditf2" |
0551c32d RH |
949 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
950 | (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 951 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 952 | "fcvt.xuf %0 = %1" |
52e12ad0 | 953 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 954 | |
c65ebc55 | 955 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
956 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
957 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 958 | "" |
aebf2462 | 959 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 960 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
961 | |
962 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
963 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
964 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 965 | "" |
aebf2462 | 966 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 967 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 968 | |
3f622353 | 969 | (define_insn "fixuns_trunctfdi2" |
0551c32d RH |
970 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
971 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 972 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 973 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 974 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 RH |
975 | |
976 | (define_insn "fixuns_trunctfdi2_alts" | |
977 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
978 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
979 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 980 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 981 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 982 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
983 | \f |
984 | ;; :::::::::::::::::::: | |
985 | ;; :: | |
986 | ;; :: Bit field extraction | |
987 | ;; :: | |
988 | ;; :::::::::::::::::::: | |
989 | ||
c65ebc55 | 990 | (define_insn "extv" |
0551c32d RH |
991 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
992 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
993 | (match_operand:DI 2 "const_int_operand" "n") |
994 | (match_operand:DI 3 "const_int_operand" "n")))] | |
995 | "" | |
996 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 997 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
998 | |
999 | (define_insn "extzv" | |
0551c32d RH |
1000 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1001 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1002 | (match_operand:DI 2 "const_int_operand" "n") |
1003 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1004 | "" | |
1005 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1006 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1007 | |
1008 | ;; Insert a bit field. | |
1009 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1010 | ;; Source1 can be 0 or -1. | |
1011 | ;; Source2 can be 0. | |
1012 | ||
1013 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1014 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1015 | ;; where source2 != dest. | |
1016 | ||
1017 | (define_expand "insv" | |
0551c32d | 1018 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1019 | (match_operand:DI 1 "const_int_operand" "") |
1020 | (match_operand:DI 2 "const_int_operand" "")) | |
1021 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1022 | "" | |
1023 | " | |
1024 | { | |
1025 | int width = INTVAL (operands[1]); | |
1026 | int shift = INTVAL (operands[2]); | |
1027 | ||
1028 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1029 | pseudo. */ | |
1030 | if (! register_operand (operands[3], DImode) | |
1031 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1032 | operands[3] = force_reg (DImode, operands[3]); | |
1033 | ||
1034 | /* If this is a single dep instruction, we have nothing to do. */ | |
1035 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1036 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1037 | { | |
1038 | /* Check for cases that can be implemented with a mix instruction. */ | |
1039 | if (width == 32 && shift == 0) | |
1040 | { | |
1041 | /* Directly generating the mix4left instruction confuses | |
1042 | optimize_bit_field in function.c. Since this is performing | |
1043 | a useful optimization, we defer generation of the complicated | |
1044 | mix4left RTL to the first splitting phase. */ | |
1045 | rtx tmp = gen_reg_rtx (DImode); | |
1046 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1047 | DONE; | |
1048 | } | |
1049 | else if (width == 32 && shift == 32) | |
1050 | { | |
1051 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1052 | DONE; | |
1053 | } | |
1054 | ||
d2ba6dcf JW |
1055 | /* We could handle remaining cases by emitting multiple dep |
1056 | instructions. | |
1057 | ||
1058 | If we need more than two dep instructions then we lose. A 6 | |
1059 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1060 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1061 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1062 | only one function unit that can execute dep and shr immed. | |
1063 | ||
1064 | If we only need two dep instruction, then we still lose. | |
1065 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1066 | the unnecessary mov, this is still undesirable because it will be | |
1067 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1068 | function unit. */ | |
1069 | ||
c65ebc55 JW |
1070 | FAIL; |
1071 | ||
1072 | #if 0 | |
1073 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1074 | for now. */ | |
1075 | while (width > 16) | |
1076 | { | |
1077 | rtx tmp; | |
1078 | ||
1079 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1080 | operands[3])); | |
1081 | shift += 16; | |
1082 | width -= 16; | |
1083 | tmp = gen_reg_rtx (DImode); | |
1084 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1085 | operands[3] = tmp; | |
1086 | } | |
1087 | operands[1] = GEN_INT (width); | |
1088 | operands[2] = GEN_INT (shift); | |
1089 | #endif | |
1090 | } | |
1091 | }") | |
1092 | ||
1093 | (define_insn "*insv_internal" | |
0551c32d | 1094 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1095 | (match_operand:DI 1 "const_int_operand" "n") |
1096 | (match_operand:DI 2 "const_int_operand" "n")) | |
1097 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1098 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1099 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1100 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1101 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1102 | |
041f25e6 RH |
1103 | ;; Combine doesn't like to create bitfield insertions into zero. |
1104 | (define_insn "*depz_internal" | |
0551c32d RH |
1105 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1106 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1107 | (match_operand:DI 2 "const_int_operand" "n")) |
1108 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1109 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1110 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
1111 | "* | |
1112 | { | |
1113 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1114 | return \"%,dep.z %0 = %1, %2, %3\"; | |
1115 | }" | |
52e12ad0 | 1116 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1117 | |
c65ebc55 | 1118 | (define_insn "shift_mix4left" |
0551c32d | 1119 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1120 | (const_int 32) (const_int 0)) |
0551c32d RH |
1121 | (match_operand:DI 1 "gr_register_operand" "r")) |
1122 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1123 | "" |
1124 | "#" | |
52e12ad0 | 1125 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1126 | |
c65ebc55 JW |
1127 | (define_split |
1128 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1129 | (const_int 32) (const_int 0)) | |
1130 | (match_operand:DI 1 "register_operand" "")) | |
1131 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1132 | "reload_completed" | |
1133 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
c65ebc55 JW |
1134 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) |
1135 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1136 | "operands[3] = operands[2];") | |
1137 | ||
1138 | (define_split | |
1139 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1140 | (const_int 32) (const_int 0)) | |
1141 | (match_operand:DI 1 "register_operand" "")) | |
1142 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1143 | "! reload_completed" | |
1144 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
1145 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1146 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1147 | "operands[3] = operands[2];") | |
1148 | ||
1149 | (define_insn "*mix4left" | |
0551c32d | 1150 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1151 | (const_int 32) (const_int 0)) |
0551c32d | 1152 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1153 | (const_int 32)))] |
1154 | "" | |
1155 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1156 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1157 | |
1158 | (define_insn "mix4right" | |
0551c32d | 1159 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1160 | (const_int 32) (const_int 32)) |
0551c32d | 1161 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1162 | "" |
1163 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1164 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1165 | |
1166 | ;; This is used by the rotrsi3 pattern. | |
1167 | ||
1168 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1169 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1170 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1171 | (ashift:DI (zero_extend:DI | |
1172 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1173 | (const_int 32))))] |
1174 | "" | |
fa9a44e8 | 1175 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1176 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1177 | |
1178 | \f | |
1179 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1180 | ;; :: |
f2f90c63 RH |
1181 | ;; :: 1 bit Integer arithmetic |
1182 | ;; :: | |
1183 | ;; :::::::::::::::::::: | |
1184 | ||
1185 | (define_insn_and_split "andbi3" | |
1186 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1187 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1188 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1189 | "" | |
1190 | "@ | |
1191 | # | |
1192 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1193 | and %0 = %2, %1" | |
1194 | "reload_completed | |
1195 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1196 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1197 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1198 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1199 | (match_dup 0))))] | |
1200 | "" | |
52e12ad0 | 1201 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1202 | |
1203 | (define_insn_and_split "*andcmbi3" | |
1204 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1205 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1206 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1207 | "" | |
1208 | "@ | |
1209 | # | |
1210 | tbit.z.and.orcm %0, %I0 = %2, 0 | |
1211 | andcm %0 = %2, %1" | |
1212 | "reload_completed | |
1213 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1214 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1215 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1216 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1217 | (match_dup 0))))] | |
1218 | "" | |
52e12ad0 | 1219 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1220 | |
1221 | (define_insn_and_split "iorbi3" | |
1222 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1223 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1224 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1225 | "" | |
1226 | "@ | |
1227 | # | |
1228 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1229 | or %0 = %2, %1" | |
1230 | "reload_completed | |
1231 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1232 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1233 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1234 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1235 | (match_dup 0))))] | |
1236 | "" | |
52e12ad0 | 1237 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1238 | |
1239 | (define_insn_and_split "*iorcmbi3" | |
1240 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1241 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1242 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1243 | "" | |
1244 | "@ | |
1245 | # | |
1246 | tbit.z.or.andcm %0, %I0 = %2, 0" | |
1247 | "reload_completed | |
1248 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1249 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1250 | [(cond_exec (eq (match_dup 1) (const_int 0)) | |
1251 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1252 | (match_dup 0))))] | |
1253 | "" | |
52e12ad0 | 1254 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1255 | |
1256 | (define_insn "one_cmplbi2" | |
1257 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1258 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1259 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1260 | "" | |
1261 | "@ | |
1262 | tbit.z %0, %I0 = %1, 0 | |
1263 | xor %0 = 1, %1 | |
1264 | # | |
1265 | #" | |
52e12ad0 | 1266 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1267 | |
1268 | (define_split | |
1269 | [(set (match_operand:BI 0 "register_operand" "") | |
1270 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1271 | (clobber (match_scratch:BI 2 ""))] | |
1272 | "reload_completed | |
1273 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1274 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1275 | && rtx_equal_p (operands[0], operands[1])" | |
1276 | [(set (match_dup 4) (match_dup 3)) | |
1277 | (set (match_dup 0) (const_int 1)) | |
1278 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1279 | (set (match_dup 0) (const_int 0))) | |
1280 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1281 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
1282 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1283 | ||
1284 | (define_split | |
1285 | [(set (match_operand:BI 0 "register_operand" "") | |
1286 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1287 | (clobber (match_scratch:BI 2 ""))] | |
1288 | "reload_completed | |
1289 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1290 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1291 | && ! rtx_equal_p (operands[0], operands[1])" | |
1292 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1293 | (set (match_dup 0) (const_int 0))) | |
1294 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1295 | (set (match_dup 0) (const_int 1))) | |
1296 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1297 | "") | |
1298 | ||
1299 | (define_insn "*cmpsi_and_0" | |
1300 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1301 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1302 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1303 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1304 | (match_operand:BI 1 "register_operand" "0")))] | |
1305 | "" | |
1306 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1307 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1308 | |
1309 | (define_insn "*cmpsi_and_1" | |
1310 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1311 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1312 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1313 | (const_int 0)]) | |
1314 | (match_operand:BI 1 "register_operand" "0")))] | |
1315 | "" | |
1316 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1317 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1318 | |
1319 | (define_insn "*cmpsi_andnot_0" | |
1320 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1321 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1322 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1323 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1324 | (match_operand:BI 1 "register_operand" "0")))] | |
1325 | "" | |
1326 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1327 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1328 | |
1329 | (define_insn "*cmpsi_andnot_1" | |
1330 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1331 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1332 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1333 | (const_int 0)])) | |
1334 | (match_operand:BI 1 "register_operand" "0")))] | |
1335 | "" | |
1336 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1337 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1338 | |
1339 | (define_insn "*cmpdi_and_0" | |
1340 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1341 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1342 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1343 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1344 | (match_operand:BI 1 "register_operand" "0")))] | |
1345 | "" | |
1346 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1347 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1348 | |
1349 | (define_insn "*cmpdi_and_1" | |
1350 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1351 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1352 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1353 | (const_int 0)]) | |
1354 | (match_operand:BI 1 "register_operand" "0")))] | |
1355 | "" | |
1356 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1357 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1358 | |
1359 | (define_insn "*cmpdi_andnot_0" | |
1360 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1361 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1362 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1363 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1364 | (match_operand:BI 1 "register_operand" "0")))] | |
1365 | "" | |
1366 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1367 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1368 | |
1369 | (define_insn "*cmpdi_andnot_1" | |
1370 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1371 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1372 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1373 | (const_int 0)])) | |
1374 | (match_operand:BI 1 "register_operand" "0")))] | |
1375 | "" | |
1376 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1377 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1378 | |
1379 | (define_insn "*tbit_and_0" | |
1380 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1381 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1382 | (const_int 1)) | |
1383 | (const_int 0)) | |
c77e04ae | 1384 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1385 | "" |
1386 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1387 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1388 | |
1389 | (define_insn "*tbit_and_1" | |
1390 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1391 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1392 | (const_int 1)) | |
1393 | (const_int 0)) | |
c77e04ae | 1394 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1395 | "" |
1396 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1397 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1398 | |
1399 | (define_insn "*tbit_and_2" | |
1400 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1401 | (and:BI (ne:BI (zero_extract:DI | |
1402 | (match_operand:DI 1 "gr_register_operand" "r") | |
1403 | (const_int 1) | |
1404 | (match_operand:DI 2 "const_int_operand" "n")) | |
1405 | (const_int 0)) | |
1406 | (match_operand:BI 3 "register_operand" "0")))] | |
1407 | "" | |
1408 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1409 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1410 | |
1411 | (define_insn "*tbit_and_3" | |
1412 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1413 | (and:BI (eq:BI (zero_extract:DI | |
1414 | (match_operand:DI 1 "gr_register_operand" "r") | |
1415 | (const_int 1) | |
1416 | (match_operand:DI 2 "const_int_operand" "n")) | |
1417 | (const_int 0)) | |
1418 | (match_operand:BI 3 "register_operand" "0")))] | |
1419 | "" | |
1420 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1421 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1422 | |
1423 | (define_insn "*cmpsi_or_0" | |
1424 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1425 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1426 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1427 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1428 | (match_operand:BI 1 "register_operand" "0")))] | |
1429 | "" | |
1430 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1431 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1432 | |
1433 | (define_insn "*cmpsi_or_1" | |
1434 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1435 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1436 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1437 | (const_int 0)]) | |
1438 | (match_operand:BI 1 "register_operand" "0")))] | |
1439 | "" | |
1440 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1441 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1442 | |
1443 | (define_insn "*cmpsi_orcm_0" | |
1444 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1445 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1446 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1447 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1448 | (match_operand:BI 1 "register_operand" "0")))] | |
1449 | "" | |
1450 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1451 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1452 | |
1453 | (define_insn "*cmpsi_orcm_1" | |
1454 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1455 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1456 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1457 | (const_int 0)])) | |
1458 | (match_operand:BI 1 "register_operand" "0")))] | |
1459 | "" | |
1460 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1461 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1462 | |
1463 | (define_insn "*cmpdi_or_0" | |
1464 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1465 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1466 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1467 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1468 | (match_operand:BI 1 "register_operand" "0")))] | |
1469 | "" | |
1470 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1471 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1472 | |
1473 | (define_insn "*cmpdi_or_1" | |
1474 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1475 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1476 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1477 | (const_int 0)]) | |
1478 | (match_operand:BI 1 "register_operand" "0")))] | |
1479 | "" | |
1480 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1481 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1482 | |
1483 | (define_insn "*cmpdi_orcm_0" | |
1484 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1485 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1486 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1487 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1488 | (match_operand:BI 1 "register_operand" "0")))] | |
1489 | "" | |
1490 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1491 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1492 | |
1493 | (define_insn "*cmpdi_orcm_1" | |
1494 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1495 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1496 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1497 | (const_int 0)])) | |
1498 | (match_operand:BI 1 "register_operand" "0")))] | |
1499 | "" | |
1500 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1501 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1502 | |
1503 | (define_insn "*tbit_or_0" | |
1504 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1505 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1506 | (const_int 1)) | |
1507 | (const_int 0)) | |
c77e04ae | 1508 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1509 | "" |
1510 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1511 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1512 | |
1513 | (define_insn "*tbit_or_1" | |
1514 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1515 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1516 | (const_int 1)) | |
1517 | (const_int 0)) | |
c77e04ae | 1518 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1519 | "" |
1520 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1521 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1522 | |
1523 | (define_insn "*tbit_or_2" | |
1524 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1525 | (ior:BI (ne:BI (zero_extract:DI | |
1526 | (match_operand:DI 1 "gr_register_operand" "r") | |
1527 | (const_int 1) | |
1528 | (match_operand:DI 2 "const_int_operand" "n")) | |
1529 | (const_int 0)) | |
1530 | (match_operand:BI 3 "register_operand" "0")))] | |
1531 | "" | |
1532 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1533 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1534 | |
1535 | (define_insn "*tbit_or_3" | |
1536 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1537 | (ior:BI (eq:BI (zero_extract:DI | |
1538 | (match_operand:DI 1 "gr_register_operand" "r") | |
1539 | (const_int 1) | |
1540 | (match_operand:DI 2 "const_int_operand" "n")) | |
1541 | (const_int 0)) | |
1542 | (match_operand:BI 3 "register_operand" "0")))] | |
1543 | "" | |
1544 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1545 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1546 | |
1547 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1548 | ||
1549 | (define_split | |
1550 | [(set (match_operand:BI 0 "register_operand" "") | |
1551 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1552 | (const_int 0)) | |
1553 | (match_operand:DI 3 "register_operand" "")) | |
1554 | (const_int 0)))] | |
1555 | "" | |
1556 | [(set (match_dup 0) | |
1557 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1558 | (match_dup 2)))] | |
1559 | "") | |
1560 | ||
1561 | (define_split | |
1562 | [(set (match_operand:BI 0 "register_operand" "") | |
1563 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1564 | (const_int 0)) | |
1565 | (match_operand:DI 3 "register_operand" "")) | |
1566 | (const_int 0)))] | |
1567 | "" | |
1568 | [(set (match_dup 0) | |
1569 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1570 | (match_dup 2))) | |
1571 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1572 | (clobber (scratch))])] | |
1573 | "") | |
1574 | ||
1575 | (define_split | |
1576 | [(set (match_operand:BI 0 "register_operand" "") | |
1577 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1578 | (const_int 0)) | |
1579 | (match_operand:DI 3 "register_operand" "")) | |
1580 | (const_int 0)))] | |
1581 | "" | |
1582 | [(set (match_dup 0) | |
1583 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1584 | (match_dup 2)))] | |
1585 | "") | |
1586 | ||
1587 | (define_split | |
1588 | [(set (match_operand:BI 0 "register_operand" "") | |
1589 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1590 | (const_int 0)) | |
1591 | (match_operand:DI 3 "register_operand" "")) | |
1592 | (const_int 0)))] | |
1593 | "" | |
1594 | [(set (match_dup 0) | |
1595 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1596 | (match_dup 2))) | |
1597 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1598 | (clobber (scratch))])] | |
1599 | "") | |
1600 | ||
1601 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1602 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1603 | ;; nothing bad happens to the comparisons in the meantime. | |
1604 | ;; | |
1605 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1606 | ;; that we're doing height reduction. | |
1607 | ; | |
1608 | ;(define_insn_and_split "" | |
1609 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1610 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1611 | ; [(match_operand 2 "" "") | |
1612 | ; (match_operand 3 "" "")]) | |
1613 | ; (match_operator:BI 4 "comparison_operator" | |
1614 | ; [(match_operand 5 "" "") | |
1615 | ; (match_operand 6 "" "")])) | |
1616 | ; (match_dup 0)))] | |
1617 | ; "flag_schedule_insns" | |
1618 | ; "#" | |
1619 | ; "" | |
1620 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1621 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1622 | ; "") | |
1623 | ; | |
1624 | ;(define_insn_and_split "" | |
1625 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1626 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1627 | ; [(match_operand 2 "" "") | |
1628 | ; (match_operand 3 "" "")]) | |
1629 | ; (match_operator:BI 4 "comparison_operator" | |
1630 | ; [(match_operand 5 "" "") | |
1631 | ; (match_operand 6 "" "")])) | |
1632 | ; (match_dup 0)))] | |
1633 | ; "flag_schedule_insns" | |
1634 | ; "#" | |
1635 | ; "" | |
1636 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1637 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1638 | ; "") | |
1639 | ; | |
1640 | ;(define_split | |
1641 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1642 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1643 | ; [(match_operand 2 "" "") | |
1644 | ; (match_operand 3 "" "")]) | |
1645 | ; (match_operand:BI 7 "register_operand" "")) | |
1646 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1647 | ; [(match_operand 5 "" "") | |
1648 | ; (match_operand 6 "" "")]) | |
1649 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1650 | ; "" | |
1651 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1652 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1653 | ; (match_dup 0)))] | |
1654 | ; "") | |
1655 | ; | |
1656 | ;(define_split | |
1657 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1658 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1659 | ; [(match_operand 2 "" "") | |
1660 | ; (match_operand 3 "" "")]) | |
1661 | ; (match_operand:BI 7 "register_operand" "")) | |
1662 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1663 | ; [(match_operand 5 "" "") | |
1664 | ; (match_operand 6 "" "")]) | |
1665 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1666 | ; "" | |
1667 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1668 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1669 | ; (match_dup 0)))] | |
1670 | ; "") | |
1671 | ||
1672 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1673 | ;; Note that we'll have already split the predicate copy, which | |
1674 | ;; is kind of a pain, but oh well. | |
1675 | ||
1676 | (define_peephole2 | |
1677 | [(set (match_operand:BI 0 "register_operand" "") | |
1678 | (match_operand:BI 1 "comparison_operator" "")) | |
1679 | (set (match_operand:CCI 2 "register_operand" "") | |
1680 | (match_operand:CCI 3 "register_operand" "")) | |
1681 | (set (match_operand:CCI 4 "register_operand" "") | |
1682 | (match_operand:CCI 5 "register_operand" "")) | |
1683 | (set (match_operand:BI 6 "register_operand" "") | |
1684 | (unspec:BI [(match_dup 6)] 7))] | |
1685 | "REGNO (operands[3]) == REGNO (operands[0]) | |
1686 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1687 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1688 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1689 | [(set (match_dup 0) (match_dup 1)) | |
1690 | (set (match_dup 6) (match_dup 7))] | |
1691 | "operands[7] = copy_rtx (operands[1]);") | |
1692 | \f | |
1693 | ;; :::::::::::::::::::: | |
1694 | ;; :: | |
cf1f6ae3 RH |
1695 | ;; :: 16 bit Integer arithmetic |
1696 | ;; :: | |
1697 | ;; :::::::::::::::::::: | |
1698 | ||
1699 | (define_insn "mulhi3" | |
1700 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1701 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1702 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1703 | "" | |
2a7ffc85 | 1704 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1705 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1706 | |
1707 | \f | |
1708 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1709 | ;; :: |
1710 | ;; :: 32 bit Integer arithmetic | |
1711 | ;; :: | |
1712 | ;; :::::::::::::::::::: | |
1713 | ||
058557c4 | 1714 | (define_insn "addsi3" |
0551c32d RH |
1715 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1716 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1717 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1718 | "" |
1719 | "@ | |
1720 | add %0 = %1, %2 | |
1721 | adds %0 = %2, %1 | |
1722 | addl %0 = %2, %1" | |
52e12ad0 | 1723 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1724 | |
1725 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1726 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1727 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1728 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1729 | (const_int 1)))] |
1730 | "" | |
1731 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1732 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1733 | |
5527bf14 | 1734 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1735 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1736 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1737 | (const_int 2)) |
1738 | (const_int 1)))] | |
1739 | "" | |
1740 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1741 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1742 | |
058557c4 | 1743 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1744 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1745 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1746 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1747 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1748 | "" |
058557c4 | 1749 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1750 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1751 | |
058557c4 | 1752 | (define_insn "subsi3" |
0551c32d RH |
1753 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1754 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1755 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1756 | "" |
1757 | "sub %0 = %1, %2" | |
52e12ad0 | 1758 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1759 | |
1760 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1761 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1762 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1763 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1764 | "" |
1765 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1766 | [(set_attr "itanium_class" "ialu")]) |
1767 | ||
1768 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1769 | |
058557c4 | 1770 | (define_insn "mulsi3" |
0551c32d | 1771 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1772 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1773 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1774 | "" |
aebf2462 | 1775 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1776 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1777 | |
655f2eb9 | 1778 | (define_insn "maddsi4" |
11a13704 RH |
1779 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1780 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1781 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1782 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1783 | "" | |
aebf2462 | 1784 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1785 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1786 | |
058557c4 | 1787 | (define_insn "negsi2" |
0551c32d RH |
1788 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1789 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1790 | "" |
1791 | "sub %0 = r0, %1" | |
52e12ad0 | 1792 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1793 | |
1794 | (define_expand "abssi2" | |
1795 | [(set (match_dup 2) | |
f2f90c63 | 1796 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1797 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1798 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1799 | (neg:SI (match_dup 1)) |
1800 | (match_dup 1)))] | |
c65ebc55 JW |
1801 | "" |
1802 | " | |
1803 | { | |
f2f90c63 | 1804 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1805 | }") |
1806 | ||
1807 | (define_expand "sminsi3" | |
1808 | [(set (match_dup 3) | |
f2f90c63 | 1809 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1810 | (match_operand:SI 2 "gr_register_operand" ""))) |
1811 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1812 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1813 | (match_dup 2) (match_dup 1)))] |
1814 | "" | |
1815 | " | |
1816 | { | |
f2f90c63 | 1817 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1818 | }") |
1819 | ||
1820 | (define_expand "smaxsi3" | |
1821 | [(set (match_dup 3) | |
f2f90c63 | 1822 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1823 | (match_operand:SI 2 "gr_register_operand" ""))) |
1824 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1825 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1826 | (match_dup 1) (match_dup 2)))] |
1827 | "" | |
1828 | " | |
1829 | { | |
f2f90c63 | 1830 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1831 | }") |
1832 | ||
1833 | (define_expand "uminsi3" | |
1834 | [(set (match_dup 3) | |
f2f90c63 | 1835 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1836 | (match_operand:SI 2 "gr_register_operand" ""))) |
1837 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1838 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1839 | (match_dup 2) (match_dup 1)))] |
1840 | "" | |
1841 | " | |
1842 | { | |
f2f90c63 | 1843 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1844 | }") |
1845 | ||
1846 | (define_expand "umaxsi3" | |
1847 | [(set (match_dup 3) | |
f2f90c63 | 1848 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1849 | (match_operand:SI 2 "gr_register_operand" ""))) |
1850 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1851 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1852 | (match_dup 1) (match_dup 2)))] |
1853 | "" | |
1854 | " | |
1855 | { | |
f2f90c63 | 1856 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1857 | }") |
1858 | ||
655f2eb9 RH |
1859 | (define_expand "divsi3" |
1860 | [(set (match_operand:SI 0 "register_operand" "") | |
1861 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1862 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1863 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1864 | " |
1865 | { | |
1866 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1867 | ||
1868 | op0_tf = gen_reg_rtx (TFmode); | |
1869 | op0_di = gen_reg_rtx (DImode); | |
1870 | ||
1871 | if (CONSTANT_P (operands[1])) | |
1872 | operands[1] = force_reg (SImode, operands[1]); | |
1873 | op1_tf = gen_reg_rtx (TFmode); | |
1874 | expand_float (op1_tf, operands[1], 0); | |
1875 | ||
1876 | if (CONSTANT_P (operands[2])) | |
1877 | operands[2] = force_reg (SImode, operands[2]); | |
1878 | op2_tf = gen_reg_rtx (TFmode); | |
1879 | expand_float (op2_tf, operands[2], 0); | |
1880 | ||
1881 | /* 2^-34 */ | |
1882 | #if 0 | |
1883 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1884 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1885 | twon34 = force_reg (TFmode, twon34); | |
1886 | #else | |
1887 | twon34 = gen_reg_rtx (TFmode); | |
1888 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1889 | #endif | |
1890 | ||
1891 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1892 | ||
1893 | emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1894 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1895 | DONE; | |
1896 | }") | |
1897 | ||
1898 | (define_expand "modsi3" | |
1899 | [(set (match_operand:SI 0 "register_operand" "") | |
1900 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
1901 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1902 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1903 | " |
1904 | { | |
1905 | rtx op2_neg, op1_di, div; | |
1906 | ||
1907 | div = gen_reg_rtx (SImode); | |
1908 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
1909 | ||
1910 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1911 | ||
1912 | /* This is a trick to get us to reuse the value that we're sure to | |
1913 | have already copied to the FP regs. */ | |
1914 | op1_di = gen_reg_rtx (DImode); | |
1915 | convert_move (op1_di, operands[1], 0); | |
1916 | ||
1917 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1918 | gen_lowpart (SImode, op1_di))); | |
1919 | DONE; | |
1920 | }") | |
1921 | ||
1922 | (define_expand "udivsi3" | |
1923 | [(set (match_operand:SI 0 "register_operand" "") | |
1924 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
1925 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1926 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1927 | " |
1928 | { | |
1929 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1930 | ||
1931 | op0_tf = gen_reg_rtx (TFmode); | |
1932 | op0_di = gen_reg_rtx (DImode); | |
1933 | ||
1934 | if (CONSTANT_P (operands[1])) | |
1935 | operands[1] = force_reg (SImode, operands[1]); | |
1936 | op1_tf = gen_reg_rtx (TFmode); | |
1937 | expand_float (op1_tf, operands[1], 1); | |
1938 | ||
1939 | if (CONSTANT_P (operands[2])) | |
1940 | operands[2] = force_reg (SImode, operands[2]); | |
1941 | op2_tf = gen_reg_rtx (TFmode); | |
1942 | expand_float (op2_tf, operands[2], 1); | |
1943 | ||
1944 | /* 2^-34 */ | |
1945 | #if 0 | |
1946 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1947 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1948 | twon34 = force_reg (TFmode, twon34); | |
1949 | #else | |
1950 | twon34 = gen_reg_rtx (TFmode); | |
1951 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1952 | #endif | |
1953 | ||
1954 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1955 | ||
1956 | emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1957 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1958 | DONE; | |
1959 | }") | |
1960 | ||
1961 | (define_expand "umodsi3" | |
1962 | [(set (match_operand:SI 0 "register_operand" "") | |
1963 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
1964 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1965 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1966 | " |
1967 | { | |
1968 | rtx op2_neg, op1_di, div; | |
1969 | ||
1970 | div = gen_reg_rtx (SImode); | |
1971 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
1972 | ||
1973 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1974 | ||
1975 | /* This is a trick to get us to reuse the value that we're sure to | |
1976 | have already copied to the FP regs. */ | |
1977 | op1_di = gen_reg_rtx (DImode); | |
1978 | convert_move (op1_di, operands[1], 1); | |
1979 | ||
1980 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1981 | gen_lowpart (SImode, op1_di))); | |
1982 | DONE; | |
1983 | }") | |
1984 | ||
1985 | (define_insn_and_split "divsi3_internal" | |
1986 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
1987 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
1988 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
1989 | (clobber (match_scratch:TF 4 "=&f")) | |
1990 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 1991 | (clobber (match_scratch:BI 6 "=c")) |
655f2eb9 | 1992 | (use (match_operand:TF 3 "fr_register_operand" "f"))] |
23c108af | 1993 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1994 | "#" |
1995 | "&& reload_completed" | |
1996 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 1997 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
1998 | (use (const_int 1))]) |
1999 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2000 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2001 | (use (const_int 1))])) | |
2002 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2003 | (parallel [(set (match_dup 5) | |
2004 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2005 | (match_dup 7))) | |
2006 | (use (const_int 1))])) | |
2007 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2008 | (parallel [(set (match_dup 4) | |
2009 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2010 | (match_dup 4))) | |
2011 | (use (const_int 1))])) | |
2012 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2013 | (parallel [(set (match_dup 5) | |
2014 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
2015 | (match_dup 3))) | |
2016 | (use (const_int 1))])) | |
2017 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2018 | (parallel [(set (match_dup 0) | |
2019 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2020 | (match_dup 4))) | |
2021 | (use (const_int 1))])) | |
2022 | ] | |
2023 | "operands[7] = CONST1_RTX (TFmode);" | |
2024 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2025 | \f |
2026 | ;; :::::::::::::::::::: | |
2027 | ;; :: | |
2028 | ;; :: 64 bit Integer arithmetic | |
2029 | ;; :: | |
2030 | ;; :::::::::::::::::::: | |
2031 | ||
2032 | (define_insn "adddi3" | |
0551c32d RH |
2033 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2034 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2035 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2036 | "" |
2037 | "@ | |
2038 | add %0 = %1, %2 | |
2039 | adds %0 = %2, %1 | |
2040 | addl %0 = %2, %1" | |
52e12ad0 | 2041 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2042 | |
2043 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2044 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2045 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2046 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2047 | (const_int 1)))] |
2048 | "" | |
2049 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2050 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2051 | |
5527bf14 RH |
2052 | ;; This has some of the same problems as shladd. We let the shladd |
2053 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2054 | ;; a register, but not more ugliness here. | |
2055 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2056 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2057 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2058 | (const_int 2)) |
2059 | (const_int 1)))] | |
2060 | "" | |
2061 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2062 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2063 | |
c65ebc55 | 2064 | (define_insn "subdi3" |
0551c32d RH |
2065 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2066 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2067 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2068 | "" |
2069 | "sub %0 = %1, %2" | |
52e12ad0 | 2070 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2071 | |
2072 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2073 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2074 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2075 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2076 | "" |
2077 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2078 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2079 | |
cee58bc0 RH |
2080 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2081 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2082 | (define_insn "muldi3" |
0551c32d | 2083 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2084 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2085 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2086 | "" |
aebf2462 | 2087 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2088 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2089 | |
2090 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2091 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2092 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2093 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2094 | ;; here so that it will be present just in case register elimination gives us | |
2095 | ;; the funny result. | |
2096 | ||
2097 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2098 | ||
2099 | ;; ??? Maybe we should change how adds are canonicalized. | |
2100 | ||
655f2eb9 | 2101 | (define_insn "madddi4" |
0551c32d | 2102 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2103 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2104 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2105 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2106 | (clobber (match_scratch:DI 4 "=X"))] |
2107 | "" | |
aebf2462 | 2108 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2109 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2110 | |
2111 | ;; This can be created by register elimination if operand3 of shladd is an | |
2112 | ;; eliminable register or has reg_equiv_constant set. | |
2113 | ||
2114 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2115 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2116 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2117 | ;; incorrectly. |
2118 | ||
655f2eb9 | 2119 | (define_insn "*madddi4_elim" |
c65ebc55 | 2120 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2121 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2122 | (match_operand:DI 2 "register_operand" "f")) | |
2123 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2124 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2125 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2126 | "reload_in_progress" |
2127 | "#" | |
52e12ad0 | 2128 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2129 | |
c65ebc55 JW |
2130 | (define_split |
2131 | [(set (match_operand:DI 0 "register_operand" "") | |
2132 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2133 | (match_operand:DI 2 "register_operand" "")) | |
2134 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2135 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2136 | (clobber (match_scratch:DI 5 ""))] |
2137 | "reload_completed" | |
2138 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2139 | (match_dup 3))) | |
2140 | (clobber (match_dup 0))]) | |
c65ebc55 | 2141 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2142 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2143 | "") | |
2144 | ||
2145 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2146 | ;; to generate them. | |
2147 | ||
2148 | (define_insn "smuldi3_highpart" | |
0551c32d | 2149 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2150 | (truncate:DI |
2151 | (lshiftrt:TI | |
0551c32d RH |
2152 | (mult:TI (sign_extend:TI |
2153 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2154 | (sign_extend:TI | |
2155 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2156 | (const_int 64))))] |
2157 | "" | |
aebf2462 | 2158 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2159 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2160 | |
2161 | (define_insn "umuldi3_highpart" | |
0551c32d | 2162 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2163 | (truncate:DI |
2164 | (lshiftrt:TI | |
0551c32d RH |
2165 | (mult:TI (zero_extend:TI |
2166 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2167 | (zero_extend:TI | |
2168 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2169 | (const_int 64))))] |
2170 | "" | |
aebf2462 | 2171 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2172 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2173 | |
2174 | (define_insn "negdi2" | |
0551c32d RH |
2175 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2176 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2177 | "" |
2178 | "sub %0 = r0, %1" | |
52e12ad0 | 2179 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2180 | |
2181 | (define_expand "absdi2" | |
2182 | [(set (match_dup 2) | |
f2f90c63 | 2183 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2184 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2185 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2186 | (neg:DI (match_dup 1)) |
2187 | (match_dup 1)))] | |
c65ebc55 JW |
2188 | "" |
2189 | " | |
2190 | { | |
f2f90c63 | 2191 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2192 | }") |
2193 | ||
2194 | (define_expand "smindi3" | |
2195 | [(set (match_dup 3) | |
f2f90c63 | 2196 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2197 | (match_operand:DI 2 "gr_register_operand" ""))) |
2198 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2199 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2200 | (match_dup 2) (match_dup 1)))] |
2201 | "" | |
2202 | " | |
2203 | { | |
f2f90c63 | 2204 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2205 | }") |
2206 | ||
2207 | (define_expand "smaxdi3" | |
2208 | [(set (match_dup 3) | |
f2f90c63 | 2209 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2210 | (match_operand:DI 2 "gr_register_operand" ""))) |
2211 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2212 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2213 | (match_dup 1) (match_dup 2)))] |
2214 | "" | |
2215 | " | |
2216 | { | |
f2f90c63 | 2217 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2218 | }") |
2219 | ||
2220 | (define_expand "umindi3" | |
2221 | [(set (match_dup 3) | |
f2f90c63 | 2222 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2223 | (match_operand:DI 2 "gr_register_operand" ""))) |
2224 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2225 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2226 | (match_dup 2) (match_dup 1)))] |
2227 | "" | |
2228 | " | |
2229 | { | |
f2f90c63 | 2230 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2231 | }") |
2232 | ||
2233 | (define_expand "umaxdi3" | |
2234 | [(set (match_dup 3) | |
f2f90c63 | 2235 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2236 | (match_operand:DI 2 "gr_register_operand" ""))) |
2237 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2238 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2239 | (match_dup 1) (match_dup 2)))] |
2240 | "" | |
2241 | " | |
2242 | { | |
f2f90c63 | 2243 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2244 | }") |
2245 | ||
2246 | (define_expand "ffsdi2" | |
2247 | [(set (match_dup 6) | |
f2f90c63 | 2248 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2249 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2250 | (set (match_dup 5) (const_int 0)) | |
2251 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
2252 | (set (match_dup 4) (unspec:DI [(match_dup 3)] 8)) | |
0551c32d | 2253 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2254 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2255 | (match_dup 5) (match_dup 4)))] |
2256 | "" | |
2257 | " | |
2258 | { | |
2259 | operands[2] = gen_reg_rtx (DImode); | |
2260 | operands[3] = gen_reg_rtx (DImode); | |
2261 | operands[4] = gen_reg_rtx (DImode); | |
2262 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2263 | operands[6] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2264 | }") |
2265 | ||
2266 | (define_insn "*popcnt" | |
0551c32d RH |
2267 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2268 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))] | |
c65ebc55 JW |
2269 | "" |
2270 | "popcnt %0 = %1" | |
52e12ad0 | 2271 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2272 | |
655f2eb9 RH |
2273 | (define_expand "divdi3" |
2274 | [(set (match_operand:DI 0 "register_operand" "") | |
2275 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2276 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2277 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2278 | " |
2279 | { | |
2280 | rtx op1_tf, op2_tf, op0_tf; | |
2281 | ||
2282 | op0_tf = gen_reg_rtx (TFmode); | |
2283 | ||
2284 | if (CONSTANT_P (operands[1])) | |
2285 | operands[1] = force_reg (DImode, operands[1]); | |
2286 | op1_tf = gen_reg_rtx (TFmode); | |
2287 | expand_float (op1_tf, operands[1], 0); | |
2288 | ||
2289 | if (CONSTANT_P (operands[2])) | |
2290 | operands[2] = force_reg (DImode, operands[2]); | |
2291 | op2_tf = gen_reg_rtx (TFmode); | |
2292 | expand_float (op2_tf, operands[2], 0); | |
2293 | ||
2294 | if (TARGET_INLINE_DIV_LAT) | |
2295 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2296 | else | |
2297 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2298 | ||
2299 | emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2300 | DONE; | |
2301 | }") | |
2302 | ||
2303 | (define_expand "moddi3" | |
2304 | [(set (match_operand:DI 0 "register_operand" "") | |
2305 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2306 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2307 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2308 | " |
2309 | { | |
2310 | rtx op2_neg, div; | |
2311 | ||
2312 | div = gen_reg_rtx (DImode); | |
2313 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2314 | ||
2315 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2316 | ||
2317 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2318 | DONE; | |
2319 | }") | |
2320 | ||
2321 | (define_expand "udivdi3" | |
2322 | [(set (match_operand:DI 0 "register_operand" "") | |
2323 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2324 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2325 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2326 | " |
2327 | { | |
2328 | rtx op1_tf, op2_tf, op0_tf; | |
2329 | ||
2330 | op0_tf = gen_reg_rtx (TFmode); | |
2331 | ||
2332 | if (CONSTANT_P (operands[1])) | |
2333 | operands[1] = force_reg (DImode, operands[1]); | |
2334 | op1_tf = gen_reg_rtx (TFmode); | |
2335 | expand_float (op1_tf, operands[1], 1); | |
2336 | ||
2337 | if (CONSTANT_P (operands[2])) | |
2338 | operands[2] = force_reg (DImode, operands[2]); | |
2339 | op2_tf = gen_reg_rtx (TFmode); | |
2340 | expand_float (op2_tf, operands[2], 1); | |
2341 | ||
2342 | if (TARGET_INLINE_DIV_LAT) | |
2343 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2344 | else | |
2345 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2346 | ||
2347 | emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2348 | DONE; | |
2349 | }") | |
2350 | ||
2351 | (define_expand "umoddi3" | |
2352 | [(set (match_operand:DI 0 "register_operand" "") | |
2353 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2354 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2355 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2356 | " |
2357 | { | |
2358 | rtx op2_neg, div; | |
2359 | ||
2360 | div = gen_reg_rtx (DImode); | |
2361 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2362 | ||
2363 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2364 | ||
2365 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2366 | DONE; | |
2367 | }") | |
2368 | ||
2369 | (define_insn_and_split "divdi3_internal_lat" | |
2370 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2371 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2372 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2373 | (clobber (match_scratch:TF 3 "=&f")) | |
2374 | (clobber (match_scratch:TF 4 "=&f")) | |
2375 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2376 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2377 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
655f2eb9 RH |
2378 | "#" |
2379 | "&& reload_completed" | |
2380 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2381 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2382 | (use (const_int 1))]) |
2383 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2384 | (parallel [(set (match_dup 3) | |
2385 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2386 | (match_dup 7))) | |
2387 | (use (const_int 1))])) | |
2388 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2389 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2390 | (use (const_int 1))])) | |
2391 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2392 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
2393 | (use (const_int 1))])) | |
2394 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2395 | (parallel [(set (match_dup 4) | |
2396 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
2397 | (match_dup 4))) | |
2398 | (use (const_int 1))])) | |
2399 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2400 | (parallel [(set (match_dup 0) | |
2401 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2402 | (match_dup 0))) | |
2403 | (use (const_int 1))])) | |
2404 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2405 | (parallel [(set (match_dup 3) | |
2406 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2407 | (match_dup 4))) | |
2408 | (use (const_int 1))])) | |
2409 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2410 | (parallel [(set (match_dup 0) | |
2411 | (plus:TF (mult:TF (match_dup 5) (match_dup 0)) | |
2412 | (match_dup 0))) | |
2413 | (use (const_int 1))])) | |
2414 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2415 | (parallel [(set (match_dup 4) | |
2416 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2417 | (match_dup 1))) | |
2418 | (use (const_int 1))])) | |
2419 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2420 | (parallel [(set (match_dup 0) | |
2421 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2422 | (match_dup 3))) | |
2423 | (use (const_int 1))])) | |
2424 | ] | |
2425 | "operands[7] = CONST1_RTX (TFmode);" | |
2426 | [(set_attr "predicable" "no")]) | |
2427 | ||
2428 | (define_insn_and_split "divdi3_internal_thr" | |
2429 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2430 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2431 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2432 | (clobber (match_scratch:TF 3 "=&f")) | |
2433 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2434 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2435 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
655f2eb9 RH |
2436 | "#" |
2437 | "&& reload_completed" | |
2438 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2439 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2440 | (use (const_int 1))]) |
2441 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2442 | (parallel [(set (match_dup 3) | |
2443 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2444 | (match_dup 6))) | |
2445 | (use (const_int 1))])) | |
2446 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2447 | (parallel [(set (match_dup 0) | |
2448 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2449 | (match_dup 0))) | |
2450 | (use (const_int 1))])) | |
2451 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2452 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
2453 | (use (const_int 1))])) | |
2454 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2455 | (parallel [(set (match_dup 0) | |
2456 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2457 | (match_dup 0))) | |
2458 | (use (const_int 1))])) | |
2459 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2460 | (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1))) | |
2461 | (use (const_int 1))])) | |
2462 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2463 | (parallel [(set (match_dup 4) | |
2464 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2465 | (match_dup 1))) | |
2466 | (use (const_int 1))])) | |
2467 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2468 | (parallel [(set (match_dup 0) | |
2469 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2470 | (match_dup 3))) | |
2471 | (use (const_int 1))])) | |
2472 | ] | |
2473 | "operands[6] = CONST1_RTX (TFmode);" | |
2474 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2475 | \f |
2476 | ;; :::::::::::::::::::: | |
2477 | ;; :: | |
2478 | ;; :: 32 bit floating point arithmetic | |
2479 | ;; :: | |
2480 | ;; :::::::::::::::::::: | |
2481 | ||
2482 | (define_insn "addsf3" | |
0551c32d RH |
2483 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2484 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2485 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2486 | "" |
aebf2462 | 2487 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2488 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2489 | |
2490 | (define_insn "subsf3" | |
0551c32d RH |
2491 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2492 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2493 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2494 | "" |
aebf2462 | 2495 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2496 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2497 | |
2498 | (define_insn "mulsf3" | |
0551c32d RH |
2499 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2500 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2501 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2502 | "" |
aebf2462 | 2503 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2504 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2505 | |
2506 | (define_insn "abssf2" | |
0551c32d RH |
2507 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2508 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2509 | "" |
aebf2462 | 2510 | "fabs %0 = %1" |
52e12ad0 | 2511 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2512 | |
2513 | (define_insn "negsf2" | |
0551c32d RH |
2514 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2515 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2516 | "" |
aebf2462 | 2517 | "fneg %0 = %1" |
52e12ad0 | 2518 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2519 | |
2520 | (define_insn "*nabssf2" | |
0551c32d RH |
2521 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2522 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2523 | "" |
aebf2462 | 2524 | "fnegabs %0 = %1" |
52e12ad0 | 2525 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2526 | |
2527 | (define_insn "minsf3" | |
0551c32d RH |
2528 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2529 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2530 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2531 | "" |
aebf2462 | 2532 | "fmin %0 = %1, %F2" |
52e12ad0 | 2533 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2534 | |
2535 | (define_insn "maxsf3" | |
0551c32d RH |
2536 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2537 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2538 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2539 | "" |
aebf2462 | 2540 | "fmax %0 = %1, %F2" |
52e12ad0 | 2541 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2542 | |
655f2eb9 | 2543 | (define_insn "*maddsf4" |
0551c32d RH |
2544 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2545 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2546 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2547 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2548 | "" |
aebf2462 | 2549 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2550 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2551 | |
655f2eb9 | 2552 | (define_insn "*msubsf4" |
0551c32d RH |
2553 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2554 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2555 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2556 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2557 | "" |
aebf2462 | 2558 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2559 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2560 | |
2561 | (define_insn "*nmulsf3" | |
0551c32d RH |
2562 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2563 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2564 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2565 | "" |
aebf2462 | 2566 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2567 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2568 | |
2569 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? | |
2570 | ||
655f2eb9 | 2571 | (define_insn "*nmaddsf4" |
0551c32d | 2572 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
26102535 RH |
2573 | (plus:SF (neg:SF (mult:SF |
2574 | (match_operand:SF 1 "fr_register_operand" "f") | |
2575 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
0551c32d | 2576 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2577 | "" |
aebf2462 | 2578 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2579 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2580 | |
26102535 RH |
2581 | (define_expand "divsf3" |
2582 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2583 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2584 | (match_operand:SF 2 "fr_register_operand" "")))] | |
23c108af | 2585 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2586 | " |
2587 | { | |
2588 | rtx insn; | |
2589 | if (TARGET_INLINE_DIV_LAT) | |
2590 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); | |
2591 | else | |
2592 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2593 | emit_insn (insn); | |
2594 | DONE; | |
2595 | }") | |
2596 | ||
2597 | (define_insn_and_split "divsf3_internal_lat" | |
2598 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2599 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2600 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2601 | (clobber (match_scratch:TF 3 "=&f")) | |
2602 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2603 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2604 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2605 | "#" |
2606 | "&& reload_completed" | |
2607 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2608 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2609 | (use (const_int 1))]) |
2610 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2611 | (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) | |
2612 | (use (const_int 1))])) | |
2613 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2614 | (parallel [(set (match_dup 4) | |
2615 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2616 | (match_dup 10))) | |
2617 | (use (const_int 1))])) | |
2618 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2619 | (parallel [(set (match_dup 3) | |
2620 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2621 | (match_dup 3))) | |
2622 | (use (const_int 1))])) | |
2623 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2624 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2625 | (use (const_int 1))])) | |
2626 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2627 | (parallel [(set (match_dup 3) | |
2628 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2629 | (match_dup 3))) | |
2630 | (use (const_int 1))])) | |
2631 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2632 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2633 | (use (const_int 1))])) | |
2634 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2635 | (parallel [(set (match_dup 9) | |
2636 | (float_truncate:DF | |
2637 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2638 | (match_dup 3)))) | |
2639 | (use (const_int 1))])) | |
2640 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2641 | (set (match_dup 0) | |
2642 | (float_truncate:SF (match_dup 6)))) | |
2643 | ] | |
2644 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2645 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2646 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2647 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); | |
2648 | operands[10] = CONST1_RTX (TFmode);" | |
2649 | [(set_attr "predicable" "no")]) | |
2650 | ||
2651 | (define_insn_and_split "divsf3_internal_thr" | |
2652 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2653 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2654 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2655 | (clobber (match_scratch:TF 3 "=&f")) | |
2656 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2657 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2658 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2659 | "#" |
2660 | "&& reload_completed" | |
2661 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2662 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2663 | (use (const_int 1))]) |
2664 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2665 | (parallel [(set (match_dup 3) | |
2666 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2667 | (match_dup 10))) | |
2668 | (use (const_int 1))])) | |
2669 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2670 | (parallel [(set (match_dup 3) | |
2671 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
2672 | (match_dup 3))) | |
2673 | (use (const_int 1))])) | |
2674 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2675 | (parallel [(set (match_dup 6) | |
2676 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
2677 | (match_dup 6))) | |
2678 | (use (const_int 1))])) | |
2679 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2680 | (parallel [(set (match_dup 9) | |
2681 | (float_truncate:SF | |
2682 | (mult:TF (match_dup 7) (match_dup 6)))) | |
2683 | (use (const_int 1))])) | |
2684 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2685 | (parallel [(set (match_dup 4) | |
2686 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3))) | |
2687 | (match_dup 7))) | |
2688 | (use (const_int 1))])) | |
2689 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2690 | (set (match_dup 0) | |
2691 | (float_truncate:SF | |
2692 | (plus:TF (mult:TF (match_dup 4) (match_dup 6)) | |
2693 | (match_dup 3))))) | |
2694 | ] | |
2695 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2696 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2697 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2698 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); | |
2699 | operands[10] = CONST1_RTX (TFmode);" | |
2700 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2701 | \f |
2702 | ;; :::::::::::::::::::: | |
2703 | ;; :: | |
2704 | ;; :: 64 bit floating point arithmetic | |
2705 | ;; :: | |
2706 | ;; :::::::::::::::::::: | |
2707 | ||
2708 | (define_insn "adddf3" | |
0551c32d RH |
2709 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2710 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2711 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2712 | "" |
aebf2462 | 2713 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2714 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2715 | |
26102535 RH |
2716 | (define_insn "*adddf3_trunc" |
2717 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2718 | (float_truncate:SF | |
2719 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2720 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2721 | "" | |
aebf2462 | 2722 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2723 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2724 | |
c65ebc55 | 2725 | (define_insn "subdf3" |
0551c32d RH |
2726 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2727 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2728 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2729 | "" |
aebf2462 | 2730 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2731 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2732 | |
26102535 RH |
2733 | (define_insn "*subdf3_trunc" |
2734 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2735 | (float_truncate:SF | |
2736 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2737 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2738 | "" | |
aebf2462 | 2739 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2740 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2741 | |
c65ebc55 | 2742 | (define_insn "muldf3" |
0551c32d RH |
2743 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2744 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2745 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2746 | "" |
aebf2462 | 2747 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2748 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2749 | |
26102535 RH |
2750 | (define_insn "*muldf3_trunc" |
2751 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2752 | (float_truncate:SF | |
2753 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2754 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2755 | "" | |
aebf2462 | 2756 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2757 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2758 | |
c65ebc55 | 2759 | (define_insn "absdf2" |
0551c32d RH |
2760 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2761 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2762 | "" |
aebf2462 | 2763 | "fabs %0 = %1" |
52e12ad0 | 2764 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2765 | |
2766 | (define_insn "negdf2" | |
0551c32d RH |
2767 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2768 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2769 | "" |
aebf2462 | 2770 | "fneg %0 = %1" |
52e12ad0 | 2771 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2772 | |
2773 | (define_insn "*nabsdf2" | |
0551c32d RH |
2774 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2775 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2776 | "" |
aebf2462 | 2777 | "fnegabs %0 = %1" |
52e12ad0 | 2778 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2779 | |
2780 | (define_insn "mindf3" | |
0551c32d RH |
2781 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2782 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2783 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2784 | "" |
aebf2462 | 2785 | "fmin %0 = %1, %F2" |
52e12ad0 | 2786 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2787 | |
2788 | (define_insn "maxdf3" | |
0551c32d RH |
2789 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2790 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2791 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2792 | "" |
aebf2462 | 2793 | "fmax %0 = %1, %F2" |
52e12ad0 | 2794 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2795 | |
655f2eb9 | 2796 | (define_insn "*madddf4" |
0551c32d RH |
2797 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2798 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2799 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2800 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2801 | "" |
aebf2462 | 2802 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 2803 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2804 | |
26102535 RH |
2805 | (define_insn "*madddf4_trunc" |
2806 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2807 | (float_truncate:SF | |
2808 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2809 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2810 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2811 | "" | |
aebf2462 | 2812 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2813 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2814 | |
655f2eb9 | 2815 | (define_insn "*msubdf4" |
0551c32d RH |
2816 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2817 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2818 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2819 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2820 | "" |
aebf2462 | 2821 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 2822 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2823 | |
26102535 RH |
2824 | (define_insn "*msubdf4_trunc" |
2825 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2826 | (float_truncate:SF | |
2827 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2828 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2829 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2830 | "" | |
aebf2462 | 2831 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2832 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2833 | |
c65ebc55 | 2834 | (define_insn "*nmuldf3" |
0551c32d RH |
2835 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2836 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2837 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2838 | "" |
aebf2462 | 2839 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 2840 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2841 | |
26102535 RH |
2842 | (define_insn "*nmuldf3_trunc" |
2843 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2844 | (float_truncate:SF | |
2845 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2846 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
2847 | "" | |
aebf2462 | 2848 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2849 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2850 | |
c65ebc55 JW |
2851 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
2852 | ||
655f2eb9 | 2853 | (define_insn "*nmadddf4" |
0551c32d | 2854 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
26102535 RH |
2855 | (plus:DF (neg:DF (mult:DF |
2856 | (match_operand:DF 1 "fr_register_operand" "f") | |
2857 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
0551c32d | 2858 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2859 | "" |
aebf2462 | 2860 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 2861 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2862 | |
2863 | (define_insn "*nmadddf4_alts" | |
2864 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2865 | (plus:DF (neg:DF (mult:DF | |
2866 | (match_operand:DF 1 "fr_register_operand" "f") | |
2867 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2868 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))) | |
2869 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2870 | "" | |
aebf2462 | 2871 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 2872 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2873 | |
2874 | (define_insn "*nmadddf4_trunc" | |
2875 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2876 | (float_truncate:SF | |
2877 | (plus:DF (neg:DF (mult:DF | |
2878 | (match_operand:DF 1 "fr_register_operand" "f") | |
2879 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2880 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2881 | "" | |
aebf2462 | 2882 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2883 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2884 | |
2885 | (define_expand "divdf3" | |
2886 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
2887 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
2888 | (match_operand:DF 2 "fr_register_operand" "")))] | |
23c108af | 2889 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2890 | " |
2891 | { | |
2892 | rtx insn; | |
2893 | if (TARGET_INLINE_DIV_LAT) | |
2894 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); | |
2895 | else | |
2896 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
2897 | emit_insn (insn); | |
2898 | DONE; | |
2899 | }") | |
2900 | ||
2901 | (define_insn_and_split "divdf3_internal_lat" | |
2902 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2903 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2904 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2905 | (clobber (match_scratch:TF 3 "=&f")) | |
2906 | (clobber (match_scratch:TF 4 "=&f")) | |
2907 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2908 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2909 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2910 | "#" |
2911 | "&& reload_completed" | |
2912 | [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) | |
f2f90c63 | 2913 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5)) |
26102535 RH |
2914 | (use (const_int 1))]) |
2915 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2916 | (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) | |
2917 | (use (const_int 1))])) | |
2918 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2919 | (parallel [(set (match_dup 4) | |
2920 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7))) | |
2921 | (match_dup 12))) | |
2922 | (use (const_int 1))])) | |
2923 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2924 | (parallel [(set (match_dup 3) | |
2925 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2926 | (match_dup 3))) | |
2927 | (use (const_int 1))])) | |
2928 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2929 | (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4))) | |
2930 | (use (const_int 1))])) | |
2931 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2932 | (parallel [(set (match_dup 7) | |
2933 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2934 | (match_dup 7))) | |
2935 | (use (const_int 1))])) | |
2936 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2937 | (parallel [(set (match_dup 3) | |
2938 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
2939 | (match_dup 3))) | |
2940 | (use (const_int 1))])) | |
2941 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2942 | (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5))) | |
2943 | (use (const_int 1))])) | |
2944 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2945 | (parallel [(set (match_dup 7) | |
2946 | (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2947 | (match_dup 7))) | |
2948 | (use (const_int 1))])) | |
2949 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2950 | (parallel [(set (match_dup 10) | |
2951 | (float_truncate:DF | |
2952 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2953 | (match_dup 3)))) | |
2954 | (use (const_int 1))])) | |
2955 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2956 | (parallel [(set (match_dup 7) | |
2957 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2958 | (match_dup 7))) | |
2959 | (use (const_int 1))])) | |
2960 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2961 | (parallel [(set (match_dup 11) | |
2962 | (float_truncate:DF | |
2963 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3))) | |
2964 | (match_dup 8)))) | |
2965 | (use (const_int 1))])) | |
2966 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2967 | (set (match_dup 0) | |
2968 | (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2969 | (match_dup 3))))) | |
2970 | ] | |
2971 | "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2972 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2973 | operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2974 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
2975 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
2976 | operands[12] = CONST1_RTX (TFmode);" | |
2977 | [(set_attr "predicable" "no")]) | |
2978 | ||
2979 | (define_insn_and_split "divdf3_internal_thr" | |
2980 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2981 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2982 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2983 | (clobber (match_scratch:TF 3 "=&f")) | |
2984 | (clobber (match_scratch:DF 4 "=f")) | |
f2f90c63 | 2985 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2986 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2987 | "#" |
2988 | "&& reload_completed" | |
2989 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2990 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2991 | (use (const_int 1))]) |
2992 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2993 | (parallel [(set (match_dup 3) | |
2994 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2995 | (match_dup 10))) | |
2996 | (use (const_int 1))])) | |
2997 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2998 | (parallel [(set (match_dup 6) | |
2999 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3000 | (match_dup 6))) | |
3001 | (use (const_int 1))])) | |
3002 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3003 | (parallel [(set (match_dup 3) | |
3004 | (mult:TF (match_dup 3) (match_dup 3))) | |
3005 | (use (const_int 1))])) | |
3006 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3007 | (parallel [(set (match_dup 6) | |
3008 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3009 | (match_dup 6))) | |
3010 | (use (const_int 1))])) | |
3011 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3012 | (parallel [(set (match_dup 3) | |
3013 | (mult:TF (match_dup 3) (match_dup 3))) | |
3014 | (use (const_int 1))])) | |
3015 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3016 | (parallel [(set (match_dup 6) | |
3017 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3018 | (match_dup 6))) | |
3019 | (use (const_int 1))])) | |
3020 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3021 | (parallel [(set (match_dup 9) | |
3022 | (float_truncate:DF | |
3023 | (mult:TF (match_dup 7) (match_dup 3)))) | |
3024 | (use (const_int 1))])) | |
3025 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3026 | (parallel [(set (match_dup 4) | |
3027 | (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9))) | |
3028 | (match_dup 1))) | |
3029 | (use (const_int 1))])) | |
3030 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3031 | (set (match_dup 0) | |
3032 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3033 | (match_dup 9)))) | |
3034 | ] | |
3035 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3036 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3037 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3038 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3039 | operands[10] = CONST1_RTX (TFmode);" | |
3040 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3041 | \f |
3042 | ;; :::::::::::::::::::: | |
3043 | ;; :: | |
3044 | ;; :: 80 bit floating point arithmetic | |
3045 | ;; :: | |
3046 | ;; :::::::::::::::::::: | |
3047 | ||
3048 | (define_insn "addtf3" | |
0551c32d | 3049 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3050 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3051 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3052 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3053 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3054 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3055 | |
26102535 RH |
3056 | (define_insn "*addtf3_truncsf" |
3057 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3058 | (float_truncate:SF | |
3059 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3060 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3061 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3062 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3063 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3064 | |
3065 | (define_insn "*addtf3_truncdf" | |
3066 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3067 | (float_truncate:DF | |
3068 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3069 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3070 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3071 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3072 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3073 | |
3f622353 | 3074 | (define_insn "subtf3" |
0551c32d | 3075 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3076 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3077 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3078 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3079 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3080 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3081 | |
26102535 RH |
3082 | (define_insn "*subtf3_truncsf" |
3083 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3084 | (float_truncate:SF | |
3085 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3086 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3087 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3088 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3089 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3090 | |
3091 | (define_insn "*subtf3_truncdf" | |
3092 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3093 | (float_truncate:DF | |
3094 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3095 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3096 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3097 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3098 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3099 | |
3f622353 | 3100 | (define_insn "multf3" |
0551c32d | 3101 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3102 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3103 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3104 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3105 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3106 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3107 | |
26102535 RH |
3108 | (define_insn "*multf3_truncsf" |
3109 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3110 | (float_truncate:SF | |
3111 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3112 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3113 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3114 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3115 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3116 | |
3117 | (define_insn "*multf3_truncdf" | |
3118 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3119 | (float_truncate:DF | |
3120 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3121 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3122 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3123 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3124 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3125 | |
655f2eb9 RH |
3126 | (define_insn "*multf3_alts" |
3127 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3128 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3129 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3130 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3131 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3132 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3133 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3134 | |
26102535 RH |
3135 | (define_insn "*multf3_truncsf_alts" |
3136 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3137 | (float_truncate:SF | |
3138 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3139 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3140 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3141 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3142 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3143 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3144 | |
3145 | (define_insn "*multf3_truncdf_alts" | |
3146 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3147 | (float_truncate:DF | |
3148 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3149 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3150 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3151 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3152 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3153 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3154 | |
3f622353 | 3155 | (define_insn "abstf2" |
0551c32d | 3156 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3157 | (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3158 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3159 | "fabs %0 = %F1" |
52e12ad0 | 3160 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3161 | |
3162 | (define_insn "negtf2" | |
0551c32d | 3163 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3164 | (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3165 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3166 | "fneg %0 = %F1" |
52e12ad0 | 3167 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3168 | |
3169 | (define_insn "*nabstf2" | |
0551c32d | 3170 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3171 | (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))] |
23c108af | 3172 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3173 | "fnegabs %0 = %F1" |
52e12ad0 | 3174 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3175 | |
3176 | (define_insn "mintf3" | |
0551c32d | 3177 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3178 | (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3179 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3180 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3181 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3182 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3183 | |
3184 | (define_insn "maxtf3" | |
0551c32d | 3185 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3186 | (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3187 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3188 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3189 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3190 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3191 | |
655f2eb9 | 3192 | (define_insn "*maddtf4" |
0551c32d | 3193 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3194 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3195 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3196 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3197 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3198 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3199 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3200 | |
26102535 RH |
3201 | (define_insn "*maddtf4_truncsf" |
3202 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3203 | (float_truncate:SF | |
3204 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3205 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3206 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3207 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3208 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3209 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3210 | |
3211 | (define_insn "*maddtf4_truncdf" | |
3212 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3213 | (float_truncate:DF | |
3214 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3215 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3216 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3217 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3218 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3219 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3220 | |
655f2eb9 RH |
3221 | (define_insn "*maddtf4_alts" |
3222 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3223 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3224 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3225 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3226 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3227 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3228 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3229 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3230 | |
26102535 RH |
3231 | (define_insn "*maddtf4_alts_truncdf" |
3232 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3233 | (float_truncate:DF | |
3234 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3235 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3236 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3237 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3238 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3239 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3240 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3241 | |
655f2eb9 | 3242 | (define_insn "*msubtf4" |
0551c32d | 3243 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3244 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3245 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3246 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3247 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3248 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3249 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3250 | |
26102535 RH |
3251 | (define_insn "*msubtf4_truncsf" |
3252 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3253 | (float_truncate:SF | |
3254 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3255 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3256 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3257 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3258 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3259 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3260 | |
3261 | (define_insn "*msubtf4_truncdf" | |
3262 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3263 | (float_truncate:DF | |
3264 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3265 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3266 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3267 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3268 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3269 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3270 | |
3f622353 | 3271 | (define_insn "*nmultf3" |
0551c32d | 3272 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3273 | (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3274 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3275 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3276 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3277 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3278 | |
26102535 RH |
3279 | (define_insn "*nmultf3_truncsf" |
3280 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3281 | (float_truncate:SF | |
3282 | (neg:TF (mult:TF | |
3283 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3284 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3285 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3286 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3287 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3288 | |
3289 | (define_insn "*nmultf3_truncdf" | |
3290 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3291 | (float_truncate:DF | |
3292 | (neg:TF (mult:TF | |
3293 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3294 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3295 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3296 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3297 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3298 | |
3f622353 RH |
3299 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
3300 | ||
655f2eb9 | 3301 | (define_insn "*nmaddtf4" |
0551c32d | 3302 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3303 | (plus:TF (neg:TF (mult:TF |
3304 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3305 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3306 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3307 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3308 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3309 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3310 | |
26102535 RH |
3311 | (define_insn "*nmaddtf4_truncsf" |
3312 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3313 | (float_truncate:SF | |
3314 | (plus:TF (neg:TF (mult:TF | |
3315 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3316 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3317 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3318 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3319 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3320 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3321 | |
3322 | (define_insn "*nmaddtf4_truncdf" | |
3323 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3324 | (float_truncate:DF | |
3325 | (plus:TF (neg:TF (mult:TF | |
3326 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3327 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3328 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3329 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3330 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3331 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3332 | |
655f2eb9 RH |
3333 | (define_insn "*nmaddtf4_alts" |
3334 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3335 | (plus:TF (neg:TF (mult:TF | |
3336 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3337 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3338 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3339 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3340 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3341 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3342 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3343 | |
26102535 RH |
3344 | (define_insn "*nmaddtf4_truncdf_alts" |
3345 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3346 | (float_truncate:DF | |
3347 | (plus:TF (neg:TF | |
3348 | (mult:TF | |
3349 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3350 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3351 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3352 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3353 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3354 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3355 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3356 | |
3357 | (define_expand "divtf3" | |
3358 | [(set (match_operand:TF 0 "fr_register_operand" "") | |
3359 | (div:TF (match_operand:TF 1 "fr_register_operand" "") | |
3360 | (match_operand:TF 2 "fr_register_operand" "")))] | |
23c108af | 3361 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3362 | " |
3363 | { | |
3364 | rtx insn; | |
3365 | if (TARGET_INLINE_DIV_LAT) | |
3366 | insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]); | |
3367 | else | |
3368 | insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); | |
3369 | emit_insn (insn); | |
3370 | DONE; | |
3371 | }") | |
3372 | ||
3373 | (define_insn_and_split "divtf3_internal_lat" | |
3374 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3375 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3376 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3377 | (clobber (match_scratch:TF 3 "=&f")) | |
3378 | (clobber (match_scratch:TF 4 "=&f")) | |
3379 | (clobber (match_scratch:TF 5 "=&f")) | |
3380 | (clobber (match_scratch:TF 6 "=&f")) | |
f2f90c63 | 3381 | (clobber (match_scratch:BI 7 "=c"))] |
23c108af | 3382 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3383 | "#" |
3384 | "&& reload_completed" | |
3385 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3386 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3387 | (use (const_int 1))]) |
3388 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3389 | (parallel [(set (match_dup 3) | |
3390 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3391 | (match_dup 8))) | |
3392 | (use (const_int 1))])) | |
3393 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3394 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3395 | (use (const_int 1))])) | |
3396 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3397 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
3398 | (use (const_int 1))])) | |
3399 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3400 | (parallel [(set (match_dup 6) | |
3401 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
3402 | (match_dup 3))) | |
3403 | (use (const_int 1))])) | |
3404 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3405 | (parallel [(set (match_dup 3) | |
3406 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
3407 | (match_dup 3))) | |
3408 | (use (const_int 1))])) | |
3409 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3410 | (parallel [(set (match_dup 5) | |
3411 | (plus:TF (mult:TF (match_dup 6) (match_dup 0)) | |
3412 | (match_dup 0))) | |
3413 | (use (const_int 1))])) | |
3414 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3415 | (parallel [(set (match_dup 0) | |
3416 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3417 | (match_dup 0))) | |
3418 | (use (const_int 1))])) | |
3419 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3420 | (parallel [(set (match_dup 4) | |
3421 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3422 | (match_dup 1))) | |
3423 | (use (const_int 1))])) | |
3424 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3425 | (parallel [(set (match_dup 3) | |
3426 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3427 | (match_dup 4))) | |
3428 | (use (const_int 1))])) | |
3429 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3430 | (parallel [(set (match_dup 5) | |
3431 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3432 | (match_dup 8))) | |
3433 | (use (const_int 1))])) | |
3434 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3435 | (parallel [(set (match_dup 0) | |
3436 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3437 | (match_dup 0))) | |
3438 | (use (const_int 1))])) | |
3439 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3440 | (parallel [(set (match_dup 4) | |
3441 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3442 | (match_dup 1))) | |
3443 | (use (const_int 1))])) | |
3444 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3445 | (set (match_dup 0) | |
3446 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3447 | (match_dup 3)))) | |
3448 | ] | |
3449 | "operands[8] = CONST1_RTX (TFmode);" | |
3450 | [(set_attr "predicable" "no")]) | |
3451 | ||
3452 | (define_insn_and_split "divtf3_internal_thr" | |
3453 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3454 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3455 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3456 | (clobber (match_scratch:TF 3 "=&f")) | |
3457 | (clobber (match_scratch:TF 4 "=&f")) | |
f2f90c63 | 3458 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3459 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3460 | "#" |
3461 | "&& reload_completed" | |
3462 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3463 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3464 | (use (const_int 1))]) |
3465 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3466 | (parallel [(set (match_dup 3) | |
3467 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3468 | (match_dup 6))) | |
3469 | (use (const_int 1))])) | |
3470 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3471 | (parallel [(set (match_dup 4) | |
3472 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3473 | (match_dup 0))) | |
3474 | (use (const_int 1))])) | |
3475 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3476 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
3477 | (use (const_int 1))])) | |
3478 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3479 | (parallel [(set (match_dup 3) | |
3480 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
3481 | (match_dup 4))) | |
3482 | (use (const_int 1))])) | |
3483 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3484 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3485 | (use (const_int 1))])) | |
3486 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3487 | (parallel [(set (match_dup 0) | |
3488 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3489 | (match_dup 6))) | |
3490 | (use (const_int 1))])) | |
3491 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3492 | (parallel [(set (match_dup 0) | |
3493 | (plus:TF (mult:TF (match_dup 0) (match_dup 3)) | |
3494 | (match_dup 3))) | |
3495 | (use (const_int 1))])) | |
3496 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3497 | (parallel [(set (match_dup 3) | |
3498 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3499 | (match_dup 1))) | |
3500 | (use (const_int 1))])) | |
3501 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3502 | (parallel [(set (match_dup 3) | |
3503 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3504 | (match_dup 4))) | |
3505 | (use (const_int 1))])) | |
3506 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3507 | (parallel [(set (match_dup 4) | |
3508 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3509 | (match_dup 6))) | |
3510 | (use (const_int 1))])) | |
3511 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3512 | (parallel [(set (match_dup 0) | |
3513 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3514 | (match_dup 0))) | |
3515 | (use (const_int 1))])) | |
3516 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3517 | (parallel [(set (match_dup 4) | |
3518 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3519 | (match_dup 1))) | |
3520 | (use (const_int 1))])) | |
3521 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3522 | (set (match_dup 0) | |
3523 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3524 | (match_dup 3)))) | |
3525 | ] | |
3526 | "operands[6] = CONST1_RTX (TFmode);" | |
3527 | [(set_attr "predicable" "no")]) | |
3528 | ||
3529 | ;; ??? frcpa works like cmp.foo.unc. | |
3530 | ||
655f2eb9 RH |
3531 | (define_insn "*recip_approx" |
3532 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3533 | (div:TF (const_int 1) | |
3534 | (match_operand:TF 3 "fr_register_operand" "f"))) | |
f2f90c63 RH |
3535 | (set (match_operand:BI 1 "register_operand" "=c") |
3536 | (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") | |
655f2eb9 RH |
3537 | (match_dup 3)] 5)) |
3538 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3539 | "INTEL_EXTENDED_IEEE_FORMAT" |
655f2eb9 | 3540 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 3541 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3542 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3543 | \f |
3544 | ;; :::::::::::::::::::: | |
3545 | ;; :: | |
3546 | ;; :: 32 bit Integer Shifts and Rotates | |
3547 | ;; :: | |
3548 | ;; :::::::::::::::::::: | |
3549 | ||
9c668921 | 3550 | (define_expand "ashlsi3" |
0551c32d RH |
3551 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3552 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3553 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 RH |
3554 | "" |
3555 | " | |
3556 | { | |
3557 | if (GET_CODE (operands[2]) != CONST_INT) | |
3558 | { | |
3559 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3560 | we've got to get rid of stray bits outside the SImode register. */ | |
3561 | rtx subshift = gen_reg_rtx (DImode); | |
3562 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3563 | operands[2] = subshift; | |
3564 | } | |
3565 | }") | |
3566 | ||
3567 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3568 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3569 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3570 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3571 | "" |
041f25e6 RH |
3572 | "@ |
3573 | shladd %0 = %1, %2, r0 | |
3574 | dep.z %0 = %1, %2, %E2 | |
3575 | shl %0 = %1, %2" | |
52e12ad0 | 3576 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3577 | |
3578 | (define_expand "ashrsi3" | |
0551c32d RH |
3579 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3580 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3581 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3582 | "" |
3583 | " | |
3584 | { | |
041f25e6 RH |
3585 | rtx subtarget = gen_reg_rtx (DImode); |
3586 | if (GET_CODE (operands[2]) == CONST_INT) | |
3587 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3588 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3589 | else | |
3590 | { | |
9c668921 | 3591 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3592 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3593 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3594 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3595 | } |
3596 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3597 | DONE; | |
c65ebc55 JW |
3598 | }") |
3599 | ||
c65ebc55 | 3600 | (define_expand "lshrsi3" |
0551c32d RH |
3601 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3602 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3603 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3604 | "" |
3605 | " | |
3606 | { | |
041f25e6 RH |
3607 | rtx subtarget = gen_reg_rtx (DImode); |
3608 | if (GET_CODE (operands[2]) == CONST_INT) | |
3609 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3610 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3611 | else | |
3612 | { | |
9c668921 | 3613 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3614 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3615 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3616 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3617 | } |
3618 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3619 | DONE; | |
c65ebc55 JW |
3620 | }") |
3621 | ||
c65ebc55 | 3622 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3623 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3624 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3625 | |
3626 | (define_expand "rotrsi3" | |
66db6b45 RH |
3627 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3628 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3629 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3630 | "" | |
3631 | " | |
3632 | { | |
3633 | if (GET_MODE (operands[2]) != VOIDmode) | |
3634 | { | |
3635 | rtx tmp = gen_reg_rtx (DImode); | |
3636 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3637 | operands[2] = tmp; | |
3638 | } | |
3639 | }") | |
3640 | ||
3641 | (define_insn_and_split "*rotrsi3_internal" | |
3642 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3643 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3644 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3645 | "" | |
3646 | "#" | |
3647 | "reload_completed" | |
c65ebc55 | 3648 | [(set (match_dup 3) |
66db6b45 | 3649 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3650 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3651 | (set (match_dup 3) | |
66db6b45 RH |
3652 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3653 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3654 | ||
3655 | (define_expand "rotlsi3" | |
3656 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3657 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3658 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3659 | "" |
3660 | " | |
3661 | { | |
3662 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3663 | { |
3664 | rtx tmp = gen_reg_rtx (SImode); | |
3665 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3666 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3667 | DONE; | |
3668 | } | |
c65ebc55 | 3669 | }") |
66db6b45 RH |
3670 | |
3671 | (define_insn_and_split "*rotlsi3_internal" | |
3672 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3673 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3674 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3675 | "" | |
3676 | "#" | |
3677 | "reload_completed" | |
3678 | [(set (match_dup 3) | |
3679 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3680 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3681 | (set (match_dup 3) | |
3682 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
3683 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3684 | operands[2] = GEN_INT (32 - INTVAL (operands[2]));") | |
c65ebc55 JW |
3685 | \f |
3686 | ;; :::::::::::::::::::: | |
3687 | ;; :: | |
3688 | ;; :: 64 bit Integer Shifts and Rotates | |
3689 | ;; :: | |
3690 | ;; :::::::::::::::::::: | |
3691 | ||
3692 | (define_insn "ashldi3" | |
52e12ad0 BS |
3693 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3694 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3695 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3696 | "" |
041f25e6 RH |
3697 | "@ |
3698 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3699 | shl %0 = %1, %2 |
041f25e6 | 3700 | shl %0 = %1, %2" |
52e12ad0 | 3701 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3702 | |
3703 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3704 | ||
3705 | (define_insn "*shladd" | |
0551c32d RH |
3706 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3707 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3708 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3709 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3710 | "" |
3711 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3712 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3713 | |
3714 | ;; This can be created by register elimination if operand3 of shladd is an | |
3715 | ;; eliminable register or has reg_equiv_constant set. | |
3716 | ||
3717 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3718 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3719 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3720 | ;; incorrectly. | |
3721 | ||
5527bf14 | 3722 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3723 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3724 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3725 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3726 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3727 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3728 | "reload_in_progress" | |
5527bf14 | 3729 | "* abort ();" |
c65ebc55 JW |
3730 | "reload_completed" |
3731 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3732 | (match_dup 3))) | |
c65ebc55 | 3733 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3734 | "" |
52e12ad0 | 3735 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3736 | |
3737 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3738 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3739 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3740 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3741 | "" |
52e12ad0 BS |
3742 | "@ |
3743 | shr %0 = %1, %2 | |
3744 | shr %0 = %1, %2" | |
3745 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3746 | |
3747 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3748 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3749 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3750 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3751 | "" |
52e12ad0 BS |
3752 | "@ |
3753 | shr.u %0 = %1, %2 | |
3754 | shr.u %0 = %1, %2" | |
3755 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3756 | |
3757 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3758 | ;; will load the operand into a register and call the pattern if the predicate | |
3759 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3760 | ;; verify that we have an appropriate constant in the expander. | |
3761 | ||
3762 | (define_expand "rotrdi3" | |
0551c32d RH |
3763 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3764 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3765 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3766 | "" | |
3767 | " | |
3768 | { | |
3769 | if (! shift_count_operand (operands[2], DImode)) | |
3770 | FAIL; | |
3771 | }") | |
3772 | ||
3773 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3774 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3775 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3776 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3777 | "" | |
3778 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3779 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3780 | |
66db6b45 RH |
3781 | (define_expand "rotldi3" |
3782 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3783 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3784 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3785 | "" | |
3786 | " | |
3787 | { | |
3788 | if (! shift_count_operand (operands[2], DImode)) | |
3789 | FAIL; | |
3790 | }") | |
3791 | ||
3792 | (define_insn "*rotldi3_internal" | |
3793 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3794 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3795 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3796 | "" | |
3797 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3798 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
3799 | \f |
3800 | ;; :::::::::::::::::::: | |
3801 | ;; :: | |
058557c4 | 3802 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
3803 | ;; :: |
3804 | ;; :::::::::::::::::::: | |
3805 | ||
3806 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3807 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3808 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3809 | ;; This doesn't work for unary logical operations, because we don't call | |
3810 | ;; apply_distributive_law for them. | |
3811 | ||
3812 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3813 | ;; apply_distributive_law. We get inefficient code for | |
3814 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3815 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3816 | ;; (zero_extend (and (not A) B)) in combine. | |
3817 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3818 | ;; one_cmplsi2 pattern. | |
3819 | ||
058557c4 | 3820 | (define_insn "one_cmplsi2" |
0551c32d RH |
3821 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3822 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3823 | "" |
3824 | "andcm %0 = -1, %1" | |
52e12ad0 | 3825 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3826 | \f |
3827 | ;; :::::::::::::::::::: | |
3828 | ;; :: | |
058557c4 | 3829 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
3830 | ;; :: |
3831 | ;; :::::::::::::::::::: | |
3832 | ||
3833 | (define_insn "anddi3" | |
0551c32d RH |
3834 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3835 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3836 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3837 | "" |
3838 | "@ | |
3839 | and %0 = %2, %1 | |
aebf2462 | 3840 | fand %0 = %2, %1" |
52e12ad0 | 3841 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3842 | |
3843 | (define_insn "*andnot" | |
0551c32d RH |
3844 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3845 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3846 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3847 | "" |
3848 | "@ | |
3849 | andcm %0 = %2, %1 | |
aebf2462 | 3850 | fandcm %0 = %2, %1" |
52e12ad0 | 3851 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3852 | |
3853 | (define_insn "iordi3" | |
0551c32d RH |
3854 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3855 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3856 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3857 | "" |
3858 | "@ | |
3859 | or %0 = %2, %1 | |
aebf2462 | 3860 | for %0 = %2, %1" |
52e12ad0 | 3861 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3862 | |
3863 | (define_insn "xordi3" | |
0551c32d RH |
3864 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3865 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3866 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3867 | "" |
3868 | "@ | |
3869 | xor %0 = %2, %1 | |
aebf2462 | 3870 | fxor %0 = %2, %1" |
52e12ad0 | 3871 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3872 | |
3873 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3874 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3875 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3876 | "" |
3877 | "andcm %0 = -1, %1" | |
52e12ad0 | 3878 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3879 | \f |
3880 | ;; :::::::::::::::::::: | |
3881 | ;; :: | |
3882 | ;; :: Comparisons | |
3883 | ;; :: | |
3884 | ;; :::::::::::::::::::: | |
3885 | ||
f2f90c63 RH |
3886 | (define_expand "cmpbi" |
3887 | [(set (cc0) | |
3888 | (compare (match_operand:BI 0 "register_operand" "") | |
3889 | (match_operand:BI 1 "const_int_operand" "")))] | |
3890 | "" | |
3891 | " | |
3892 | { | |
3893 | ia64_compare_op0 = operands[0]; | |
3894 | ia64_compare_op1 = operands[1]; | |
3895 | DONE; | |
3896 | }") | |
3897 | ||
c65ebc55 JW |
3898 | (define_expand "cmpsi" |
3899 | [(set (cc0) | |
0551c32d RH |
3900 | (compare (match_operand:SI 0 "gr_register_operand" "") |
3901 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3902 | "" |
3903 | " | |
3904 | { | |
3905 | ia64_compare_op0 = operands[0]; | |
3906 | ia64_compare_op1 = operands[1]; | |
3907 | DONE; | |
3908 | }") | |
3909 | ||
3910 | (define_expand "cmpdi" | |
3911 | [(set (cc0) | |
0551c32d RH |
3912 | (compare (match_operand:DI 0 "gr_register_operand" "") |
3913 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3914 | "" |
3915 | " | |
3916 | { | |
3917 | ia64_compare_op0 = operands[0]; | |
3918 | ia64_compare_op1 = operands[1]; | |
3919 | DONE; | |
3920 | }") | |
3921 | ||
3922 | (define_expand "cmpsf" | |
3923 | [(set (cc0) | |
0551c32d RH |
3924 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
3925 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3926 | "" |
3927 | " | |
3928 | { | |
3929 | ia64_compare_op0 = operands[0]; | |
3930 | ia64_compare_op1 = operands[1]; | |
3931 | DONE; | |
3932 | }") | |
3933 | ||
3934 | (define_expand "cmpdf" | |
3935 | [(set (cc0) | |
0551c32d RH |
3936 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
3937 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3938 | "" |
3939 | " | |
3940 | { | |
3941 | ia64_compare_op0 = operands[0]; | |
3942 | ia64_compare_op1 = operands[1]; | |
3943 | DONE; | |
3944 | }") | |
3945 | ||
3f622353 | 3946 | (define_expand "cmptf" |
c65ebc55 | 3947 | [(set (cc0) |
3f622353 RH |
3948 | (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") |
3949 | (match_operand:TF 1 "tfreg_or_fp01_operand" "")))] | |
23c108af | 3950 | "INTEL_EXTENDED_IEEE_FORMAT" |
c65ebc55 JW |
3951 | " |
3952 | { | |
3953 | ia64_compare_op0 = operands[0]; | |
3954 | ia64_compare_op1 = operands[1]; | |
3955 | DONE; | |
3956 | }") | |
3957 | ||
3958 | (define_insn "*cmpsi_normal" | |
f2f90c63 RH |
3959 | [(set (match_operand:BI 0 "register_operand" "=c") |
3960 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
3961 | [(match_operand:SI 2 "gr_register_operand" "r") |
3962 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
3963 | "" |
3964 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 3965 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3966 | |
18a3c539 JW |
3967 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3968 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3969 | ||
c65ebc55 | 3970 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
3971 | [(set (match_operand:BI 0 "register_operand" "=c") |
3972 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3973 | [(match_operand:SI 2 "gr_register_operand" "r") |
3974 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3975 | "" |
18a3c539 | 3976 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3977 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3978 | |
3979 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
3980 | [(set (match_operand:BI 0 "register_operand" "=c") |
3981 | (match_operator:BI 1 "normal_comparison_operator" | |
3982 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 3983 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 3984 | "" |
f2f90c63 | 3985 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 3986 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3987 | |
18a3c539 JW |
3988 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3989 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3990 | ||
c65ebc55 | 3991 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
3992 | [(set (match_operand:BI 0 "register_operand" "=c") |
3993 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3994 | [(match_operand:DI 2 "gr_register_operand" "r") |
3995 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3996 | "" |
18a3c539 | 3997 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3998 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3999 | |
4000 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4001 | [(set (match_operand:BI 0 "register_operand" "=c") |
4002 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4003 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4004 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4005 | "" |
4006 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4007 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4008 | |
4009 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4010 | [(set (match_operand:BI 0 "register_operand" "=c") |
4011 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4012 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4013 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4014 | "" |
4015 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4016 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4017 | |
3f622353 | 4018 | (define_insn "*cmptf_internal" |
f2f90c63 RH |
4019 | [(set (match_operand:BI 0 "register_operand" "=c") |
4020 | (match_operator:BI 1 "comparison_operator" | |
3f622353 RH |
4021 | [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG") |
4022 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))] | |
23c108af | 4023 | "INTEL_EXTENDED_IEEE_FORMAT" |
3f622353 | 4024 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4025 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4026 | |
c65ebc55 JW |
4027 | ;; ??? Can this pattern be generated? |
4028 | ||
4029 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4030 | [(set (match_operand:BI 0 "register_operand" "=c") |
4031 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4032 | (const_int 1) |
4033 | (match_operand:DI 2 "immediate_operand" "n")) | |
4034 | (const_int 0)))] | |
4035 | "" | |
4036 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4037 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4038 | |
4039 | (define_insn "*bit_one" | |
f2f90c63 RH |
4040 | [(set (match_operand:BI 0 "register_operand" "=c") |
4041 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4042 | (const_int 1) |
4043 | (match_operand:DI 2 "immediate_operand" "n")) | |
4044 | (const_int 0)))] | |
4045 | "" | |
4046 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4047 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4048 | \f |
4049 | ;; :::::::::::::::::::: | |
4050 | ;; :: | |
4051 | ;; :: Branches | |
4052 | ;; :: | |
4053 | ;; :::::::::::::::::::: | |
4054 | ||
4055 | (define_expand "beq" | |
f2f90c63 RH |
4056 | [(set (pc) |
4057 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4058 | (label_ref (match_operand 0 "" "")) |
4059 | (pc)))] | |
4060 | "" | |
f2f90c63 | 4061 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4062 | |
4063 | (define_expand "bne" | |
f2f90c63 RH |
4064 | [(set (pc) |
4065 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4066 | (label_ref (match_operand 0 "" "")) |
4067 | (pc)))] | |
4068 | "" | |
f2f90c63 | 4069 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4070 | |
4071 | (define_expand "blt" | |
f2f90c63 RH |
4072 | [(set (pc) |
4073 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4074 | (label_ref (match_operand 0 "" "")) |
4075 | (pc)))] | |
4076 | "" | |
f2f90c63 | 4077 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4078 | |
4079 | (define_expand "ble" | |
f2f90c63 RH |
4080 | [(set (pc) |
4081 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4082 | (label_ref (match_operand 0 "" "")) |
4083 | (pc)))] | |
4084 | "" | |
f2f90c63 | 4085 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4086 | |
4087 | (define_expand "bgt" | |
f2f90c63 RH |
4088 | [(set (pc) |
4089 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4090 | (label_ref (match_operand 0 "" "")) |
4091 | (pc)))] | |
4092 | "" | |
f2f90c63 | 4093 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4094 | |
4095 | (define_expand "bge" | |
f2f90c63 RH |
4096 | [(set (pc) |
4097 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4098 | (label_ref (match_operand 0 "" "")) |
4099 | (pc)))] | |
4100 | "" | |
f2f90c63 | 4101 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4102 | |
4103 | (define_expand "bltu" | |
f2f90c63 RH |
4104 | [(set (pc) |
4105 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4106 | (label_ref (match_operand 0 "" "")) |
4107 | (pc)))] | |
4108 | "" | |
f2f90c63 | 4109 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4110 | |
4111 | (define_expand "bleu" | |
f2f90c63 RH |
4112 | [(set (pc) |
4113 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4114 | (label_ref (match_operand 0 "" "")) |
4115 | (pc)))] | |
4116 | "" | |
f2f90c63 | 4117 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4118 | |
4119 | (define_expand "bgtu" | |
f2f90c63 RH |
4120 | [(set (pc) |
4121 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4122 | (label_ref (match_operand 0 "" "")) |
4123 | (pc)))] | |
4124 | "" | |
f2f90c63 | 4125 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4126 | |
4127 | (define_expand "bgeu" | |
f2f90c63 RH |
4128 | [(set (pc) |
4129 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4130 | (label_ref (match_operand 0 "" "")) |
4131 | (pc)))] | |
4132 | "" | |
f2f90c63 | 4133 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4134 | |
e57b9d65 | 4135 | (define_expand "bunordered" |
f2f90c63 RH |
4136 | [(set (pc) |
4137 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4138 | (label_ref (match_operand 0 "" "")) |
4139 | (pc)))] | |
4140 | "" | |
f2f90c63 | 4141 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4142 | |
4143 | (define_expand "bordered" | |
f2f90c63 RH |
4144 | [(set (pc) |
4145 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4146 | (label_ref (match_operand 0 "" "")) |
4147 | (pc)))] | |
4148 | "" | |
f2f90c63 | 4149 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4150 | |
6b6c1201 | 4151 | (define_insn "*br_true" |
c65ebc55 | 4152 | [(set (pc) |
6b6c1201 | 4153 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4154 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4155 | (const_int 0)]) |
4156 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4157 | (pc)))] |
4158 | "" | |
85548039 | 4159 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4160 | [(set_attr "itanium_class" "br") |
e5bde68a | 4161 | (set_attr "predicable" "no")]) |
c65ebc55 | 4162 | |
6b6c1201 | 4163 | (define_insn "*br_false" |
c65ebc55 | 4164 | [(set (pc) |
6b6c1201 | 4165 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4166 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4167 | (const_int 0)]) |
c65ebc55 | 4168 | (pc) |
6b6c1201 | 4169 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4170 | "" |
85548039 | 4171 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4172 | [(set_attr "itanium_class" "br") |
e5bde68a | 4173 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4174 | \f |
4175 | ;; :::::::::::::::::::: | |
4176 | ;; :: | |
5527bf14 RH |
4177 | ;; :: Counted loop operations |
4178 | ;; :: | |
4179 | ;; :::::::::::::::::::: | |
4180 | ||
4181 | (define_expand "doloop_end" | |
4182 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4183 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4184 | (use (match_operand 2 "" "")) ; max iterations | |
4185 | (use (match_operand 3 "" "")) ; loop level | |
4186 | (use (match_operand 4 "" ""))] ; label | |
4187 | "" | |
4188 | " | |
4189 | { | |
4190 | /* Only use cloop on innermost loops. */ | |
4191 | if (INTVAL (operands[3]) > 1) | |
4192 | FAIL; | |
4193 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4194 | operands[4])); | |
4195 | DONE; | |
4196 | }") | |
4197 | ||
4198 | (define_insn "doloop_end_internal" | |
4199 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4200 | (const_int 0)) | |
4201 | (label_ref (match_operand 1 "" "")) | |
4202 | (pc))) | |
4203 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
4204 | (match_dup 0) | |
4205 | (plus:DI (match_dup 0) (const_int -1))))] | |
4206 | "" | |
4207 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4208 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4209 | (set_attr "predicable" "no")]) |
4210 | \f | |
4211 | ;; :::::::::::::::::::: | |
4212 | ;; :: | |
c65ebc55 JW |
4213 | ;; :: Set flag operations |
4214 | ;; :: | |
4215 | ;; :::::::::::::::::::: | |
4216 | ||
4217 | (define_expand "seq" | |
f2f90c63 | 4218 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4219 | "" |
f2f90c63 | 4220 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4221 | |
4222 | (define_expand "sne" | |
f2f90c63 | 4223 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4224 | "" |
f2f90c63 | 4225 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4226 | |
4227 | (define_expand "slt" | |
f2f90c63 | 4228 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4229 | "" |
f2f90c63 | 4230 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4231 | |
4232 | (define_expand "sle" | |
f2f90c63 | 4233 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4234 | "" |
f2f90c63 | 4235 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4236 | |
4237 | (define_expand "sgt" | |
f2f90c63 | 4238 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4239 | "" |
f2f90c63 | 4240 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4241 | |
4242 | (define_expand "sge" | |
f2f90c63 | 4243 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4244 | "" |
f2f90c63 | 4245 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4246 | |
4247 | (define_expand "sltu" | |
f2f90c63 | 4248 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4249 | "" |
f2f90c63 | 4250 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4251 | |
4252 | (define_expand "sleu" | |
f2f90c63 | 4253 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4254 | "" |
f2f90c63 | 4255 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4256 | |
4257 | (define_expand "sgtu" | |
f2f90c63 | 4258 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4259 | "" |
f2f90c63 | 4260 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4261 | |
4262 | (define_expand "sgeu" | |
f2f90c63 | 4263 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4264 | "" |
f2f90c63 | 4265 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4266 | |
e57b9d65 | 4267 | (define_expand "sunordered" |
f2f90c63 | 4268 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4269 | "" |
f2f90c63 | 4270 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4271 | |
4272 | (define_expand "sordered" | |
f2f90c63 | 4273 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4274 | "" |
f2f90c63 | 4275 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4276 | |
c65ebc55 JW |
4277 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4278 | ;; efficient than mov/mov/cst/cst. | |
4279 | ||
0551c32d RH |
4280 | (define_insn_and_split "*sne_internal" |
4281 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4282 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4283 | (const_int 0)))] |
4284 | "" | |
4285 | "#" | |
c65ebc55 | 4286 | "reload_completed" |
f2f90c63 RH |
4287 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4288 | (set (match_dup 0) (const_int 1))) | |
4289 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4290 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4291 | "" |
52e12ad0 | 4292 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4293 | |
0551c32d RH |
4294 | (define_insn_and_split "*seq_internal" |
4295 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4296 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4297 | (const_int 0)))] |
4298 | "" | |
4299 | "#" | |
c65ebc55 | 4300 | "reload_completed" |
f2f90c63 RH |
4301 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4302 | (set (match_dup 0) (const_int 0))) | |
4303 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4304 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4305 | "" |
52e12ad0 | 4306 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4307 | \f |
4308 | ;; :::::::::::::::::::: | |
4309 | ;; :: | |
4310 | ;; :: Conditional move instructions. | |
4311 | ;; :: | |
4312 | ;; :::::::::::::::::::: | |
4313 | ||
4314 | ;; ??? Add movXXcc patterns? | |
4315 | ||
c65ebc55 JW |
4316 | ;; |
4317 | ;; DImode if_then_else patterns. | |
4318 | ;; | |
4319 | ||
75cdbeb8 | 4320 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4321 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4322 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4323 | (if_then_else:DI |
f2f90c63 RH |
4324 | (match_operator 4 "predicate_operator" |
4325 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4326 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4327 | (const_int 0)]) |
f2f90c63 | 4328 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4329 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4330 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4331 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4332 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4333 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 RH |
4334 | "* abort ();" |
4335 | [(set_attr "predicable" "no")]) | |
4336 | ||
4337 | (define_split | |
f2f90c63 | 4338 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4339 | (if_then_else |
f2f90c63 RH |
4340 | (match_operator 4 "predicate_operator" |
4341 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4342 | (const_int 0)]) |
f2f90c63 RH |
4343 | (match_operand 2 "move_operand" "") |
4344 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4345 | "reload_completed" |
4346 | [(const_int 0)] | |
e5bde68a RH |
4347 | " |
4348 | { | |
3b572406 RH |
4349 | rtx tmp; |
4350 | if (! rtx_equal_p (operands[0], operands[2])) | |
e5bde68a | 4351 | { |
3b572406 RH |
4352 | tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]); |
4353 | tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp); | |
4354 | emit_insn (tmp); | |
e5bde68a | 4355 | } |
3b572406 RH |
4356 | if (! rtx_equal_p (operands[0], operands[3])) |
4357 | { | |
4358 | tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4359 | VOIDmode, operands[1], const0_rtx); |
3b572406 RH |
4360 | tmp = gen_rtx_COND_EXEC (VOIDmode, tmp, |
4361 | gen_rtx_SET (VOIDmode, operands[0], | |
4362 | operands[3])); | |
4363 | emit_insn (tmp); | |
4364 | } | |
4365 | DONE; | |
75cdbeb8 | 4366 | }") |
c65ebc55 JW |
4367 | |
4368 | ;; Absolute value pattern. | |
4369 | ||
4370 | (define_insn "*absdi2_internal" | |
0551c32d | 4371 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4372 | (if_then_else:DI |
f2f90c63 RH |
4373 | (match_operator 4 "predicate_operator" |
4374 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4375 | (const_int 0)]) |
0551c32d RH |
4376 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4377 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4378 | "" |
e5bde68a | 4379 | "#" |
52e12ad0 | 4380 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4381 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4382 | |
4383 | (define_split | |
4384 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4385 | (if_then_else:DI |
f2f90c63 RH |
4386 | (match_operator 4 "predicate_operator" |
4387 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4388 | (const_int 0)]) |
0551c32d RH |
4389 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4390 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4391 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4392 | [(cond_exec | |
4393 | (match_dup 4) | |
4394 | (set (match_dup 0) | |
4395 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4396 | "") |
4397 | ||
e5bde68a RH |
4398 | (define_split |
4399 | [(set (match_operand:DI 0 "register_operand" "") | |
4400 | (if_then_else:DI | |
f2f90c63 RH |
4401 | (match_operator 4 "predicate_operator" |
4402 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4403 | (const_int 0)]) |
0551c32d RH |
4404 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4405 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4406 | "reload_completed" |
4407 | [(cond_exec | |
4408 | (match_dup 4) | |
4409 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4410 | (cond_exec | |
4411 | (match_dup 5) | |
4412 | (set (match_dup 0) (match_dup 3)))] | |
4413 | " | |
4414 | { | |
4415 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4416 | VOIDmode, operands[1], const0_rtx); |
e5bde68a | 4417 | }") |
c65ebc55 JW |
4418 | |
4419 | ;; | |
4420 | ;; SImode if_then_else patterns. | |
4421 | ;; | |
4422 | ||
75cdbeb8 | 4423 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4424 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4425 | (if_then_else:SI |
f2f90c63 RH |
4426 | (match_operator 4 "predicate_operator" |
4427 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4428 | (const_int 0)]) |
f2f90c63 | 4429 | (match_operand:SI 2 "move_operand" |
3b572406 | 4430 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4431 | (match_operand:SI 3 "move_operand" |
3b572406 | 4432 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4433 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4434 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 | 4435 | "* abort ();" |
3b572406 | 4436 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4437 | |
4438 | (define_insn "*abssi2_internal" | |
0551c32d | 4439 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4440 | (if_then_else:SI |
f2f90c63 RH |
4441 | (match_operator 4 "predicate_operator" |
4442 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4443 | (const_int 0)]) |
0551c32d RH |
4444 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4445 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4446 | "" |
e5bde68a | 4447 | "#" |
52e12ad0 | 4448 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4449 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4450 | |
4451 | (define_split | |
4452 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4453 | (if_then_else:SI |
f2f90c63 RH |
4454 | (match_operator 4 "predicate_operator" |
4455 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4456 | (const_int 0)]) |
0551c32d RH |
4457 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4458 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4459 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4460 | [(cond_exec | |
4461 | (match_dup 4) | |
4462 | (set (match_dup 0) | |
4463 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4464 | "") |
4465 | ||
e5bde68a RH |
4466 | (define_split |
4467 | [(set (match_operand:SI 0 "register_operand" "") | |
4468 | (if_then_else:SI | |
f2f90c63 RH |
4469 | (match_operator 4 "predicate_operator" |
4470 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4471 | (const_int 0)]) |
0551c32d RH |
4472 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4473 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4474 | "reload_completed" |
4475 | [(cond_exec | |
4476 | (match_dup 4) | |
4477 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4478 | (cond_exec | |
4479 | (match_dup 5) | |
4480 | (set (match_dup 0) (match_dup 3)))] | |
4481 | " | |
4482 | { | |
4483 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4484 | VOIDmode, operands[1], const0_rtx); |
e5bde68a RH |
4485 | }") |
4486 | ||
c65ebc55 JW |
4487 | \f |
4488 | ;; :::::::::::::::::::: | |
4489 | ;; :: | |
4490 | ;; :: Call and branch instructions | |
4491 | ;; :: | |
4492 | ;; :::::::::::::::::::: | |
4493 | ||
4494 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4495 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4496 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4497 | ;; registers used as operands. | |
4498 | ||
4499 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4500 | ;; is supplied for the sake of some RISC machines which need to put this | |
4501 | ;; information into the assembler code; they can put it in the RTL instead of | |
4502 | ;; operand 1. | |
4503 | ||
4504 | (define_expand "call" | |
4505 | [(use (match_operand:DI 0 "" "")) | |
4506 | (use (match_operand 1 "" "")) | |
4507 | (use (match_operand 2 "" "")) | |
4508 | (use (match_operand 3 "" ""))] | |
4509 | "" | |
4510 | " | |
4511 | { | |
2ed4af6f | 4512 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); |
c65ebc55 JW |
4513 | DONE; |
4514 | }") | |
4515 | ||
2ed4af6f RH |
4516 | (define_expand "sibcall" |
4517 | [(use (match_operand:DI 0 "" "")) | |
4518 | (use (match_operand 1 "" "")) | |
4519 | (use (match_operand 2 "" "")) | |
4520 | (use (match_operand 3 "" ""))] | |
c65ebc55 JW |
4521 | "" |
4522 | " | |
4523 | { | |
2ed4af6f RH |
4524 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); |
4525 | DONE; | |
c65ebc55 JW |
4526 | }") |
4527 | ||
c65ebc55 | 4528 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4529 | ;; register in which the value is returned. There are three more operands, |
4530 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4531 | ;; increased by one). |
2ed4af6f | 4532 | ;; |
c65ebc55 JW |
4533 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4534 | ||
4535 | (define_expand "call_value" | |
4536 | [(use (match_operand 0 "" "")) | |
4537 | (use (match_operand:DI 1 "" "")) | |
4538 | (use (match_operand 2 "" "")) | |
4539 | (use (match_operand 3 "" "")) | |
4540 | (use (match_operand 4 "" ""))] | |
4541 | "" | |
4542 | " | |
4543 | { | |
2ed4af6f | 4544 | ia64_expand_call (operands[0], operands[1], operands[3], 0); |
c65ebc55 JW |
4545 | DONE; |
4546 | }") | |
4547 | ||
2ed4af6f RH |
4548 | (define_expand "sibcall_value" |
4549 | [(use (match_operand 0 "" "")) | |
4550 | (use (match_operand:DI 1 "" "")) | |
4551 | (use (match_operand 2 "" "")) | |
4552 | (use (match_operand 3 "" "")) | |
4553 | (use (match_operand 4 "" ""))] | |
c65ebc55 JW |
4554 | "" |
4555 | " | |
4556 | { | |
2ed4af6f RH |
4557 | ia64_expand_call (operands[0], operands[1], operands[3], 1); |
4558 | DONE; | |
c65ebc55 JW |
4559 | }") |
4560 | ||
c65ebc55 JW |
4561 | ;; Call subroutine returning any type. |
4562 | ||
4563 | (define_expand "untyped_call" | |
4564 | [(parallel [(call (match_operand 0 "" "") | |
4565 | (const_int 0)) | |
4566 | (match_operand 1 "" "") | |
4567 | (match_operand 2 "" "")])] | |
4568 | "" | |
4569 | " | |
4570 | { | |
4571 | int i; | |
4572 | ||
4573 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4574 | ||
4575 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4576 | { | |
4577 | rtx set = XVECEXP (operands[2], 0, i); | |
4578 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4579 | } | |
4580 | ||
4581 | /* The optimizer does not know that the call sets the function value | |
4582 | registers we stored in the result block. We avoid problems by | |
4583 | claiming that all hard registers are used and clobbered at this | |
4584 | point. */ | |
4585 | emit_insn (gen_blockage ()); | |
4586 | ||
4587 | DONE; | |
4588 | }") | |
4589 | ||
2ed4af6f | 4590 | (define_insn "call_nopic" |
52e12ad0 | 4591 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4592 | (match_operand 1 "" "")) |
52e12ad0 | 4593 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4594 | "" |
4595 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4596 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4597 | |
4598 | (define_insn "call_value_nopic" | |
4599 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4600 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4601 | (match_operand 2 "" ""))) |
52e12ad0 | 4602 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4603 | "" |
4604 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4605 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4606 | |
4607 | (define_insn "sibcall_nopic" | |
52e12ad0 | 4608 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4609 | (match_operand 1 "" "")) |
52e12ad0 | 4610 | (use (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4611 | "" |
4612 | "br%+.many %0" | |
52e12ad0 | 4613 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4614 | |
4615 | (define_insn "call_pic" | |
52e12ad0 | 4616 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f RH |
4617 | (match_operand 1 "" "")) |
4618 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4619 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4620 | "" |
4621 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4622 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4623 | |
4624 | (define_insn "call_value_pic" | |
4625 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4626 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f RH |
4627 | (match_operand 2 "" ""))) |
4628 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4629 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4630 | "" |
4631 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4632 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4633 | |
4634 | (define_insn "sibcall_pic" | |
4635 | [(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) | |
4636 | (match_operand 1 "" "")) | |
4637 | (use (unspec [(reg:DI 1)] 9)) | |
4638 | (use (match_operand:DI 2 "register_operand" "=b"))] | |
4639 | "" | |
4640 | "br%+.many %0" | |
52e12ad0 | 4641 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4642 | |
c65ebc55 JW |
4643 | (define_insn "return_internal" |
4644 | [(return) | |
4645 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4646 | "" | |
4647 | "br.ret.sptk.many %0" | |
52e12ad0 | 4648 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4649 | |
4650 | (define_insn "return" | |
4651 | [(return)] | |
4652 | "ia64_direct_return ()" | |
4653 | "br.ret.sptk.many rp" | |
52e12ad0 | 4654 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4655 | |
6b6c1201 | 4656 | (define_insn "*return_true" |
c65ebc55 | 4657 | [(set (pc) |
6b6c1201 | 4658 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4659 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4660 | (const_int 0)]) |
c65ebc55 JW |
4661 | (return) |
4662 | (pc)))] | |
4663 | "ia64_direct_return ()" | |
13da91fd | 4664 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4665 | [(set_attr "itanium_class" "br") |
e5bde68a | 4666 | (set_attr "predicable" "no")]) |
c65ebc55 | 4667 | |
6b6c1201 | 4668 | (define_insn "*return_false" |
c65ebc55 | 4669 | [(set (pc) |
6b6c1201 | 4670 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4671 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4672 | (const_int 0)]) |
c65ebc55 JW |
4673 | (pc) |
4674 | (return)))] | |
4675 | "ia64_direct_return ()" | |
13da91fd | 4676 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4677 | [(set_attr "itanium_class" "br") |
e5bde68a | 4678 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4679 | |
4680 | (define_insn "jump" | |
4681 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4682 | "" | |
4683 | "br %l0" | |
52e12ad0 | 4684 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4685 | |
4686 | (define_insn "indirect_jump" | |
4687 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4688 | "" | |
4689 | "br %0" | |
52e12ad0 | 4690 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4691 | |
4692 | (define_expand "tablejump" | |
4693 | [(match_operand:DI 0 "register_operand" "") | |
4694 | (match_operand 1 "" "")] | |
4695 | "" | |
4696 | " | |
4697 | { | |
4698 | rtx tmp1 = gen_reg_rtx (DImode); | |
4699 | rtx tmp2 = gen_reg_rtx (DImode); | |
4700 | ||
4701 | emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[1])); | |
4702 | emit_insn (gen_adddi3 (tmp2, operands[0], tmp1)); | |
4703 | emit_jump_insn (gen_tablejump_internal (tmp2, operands[1])); | |
4704 | DONE; | |
4705 | }") | |
4706 | ||
4707 | (define_insn "tablejump_internal" | |
4708 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) | |
4709 | (use (label_ref (match_operand 1 "" "")))] | |
4710 | "" | |
4711 | "br %0" | |
52e12ad0 | 4712 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4713 | |
4714 | \f | |
4715 | ;; :::::::::::::::::::: | |
4716 | ;; :: | |
4717 | ;; :: Prologue and Epilogue instructions | |
4718 | ;; :: | |
4719 | ;; :::::::::::::::::::: | |
4720 | ||
4721 | (define_expand "prologue" | |
4722 | [(const_int 1)] | |
4723 | "" | |
4724 | " | |
4725 | { | |
4726 | ia64_expand_prologue (); | |
4727 | DONE; | |
4728 | }") | |
4729 | ||
4730 | (define_expand "epilogue" | |
2ed4af6f RH |
4731 | [(return)] |
4732 | "" | |
4733 | " | |
4734 | { | |
4735 | ia64_expand_epilogue (0); | |
4736 | DONE; | |
4737 | }") | |
4738 | ||
4739 | (define_expand "sibcall_epilogue" | |
4740 | [(return)] | |
c65ebc55 JW |
4741 | "" |
4742 | " | |
4743 | { | |
2ed4af6f | 4744 | ia64_expand_epilogue (1); |
c65ebc55 JW |
4745 | DONE; |
4746 | }") | |
4747 | ||
4748 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4749 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4750 | ||
4751 | (define_insn "prologue_allocate_stack" | |
4752 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4753 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4754 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
c65ebc55 JW |
4755 | (set (match_operand:DI 3 "register_operand" "=r,r,r") |
4756 | (match_dup 3))] | |
4757 | "" | |
4758 | "@ | |
4759 | add %0 = %1, %2 | |
4760 | adds %0 = %2, %1 | |
4761 | addl %0 = %2, %1" | |
52e12ad0 | 4762 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4763 | |
4764 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4765 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4766 | ||
4767 | (define_insn "epilogue_deallocate_stack" | |
4768 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4769 | (match_operand:DI 1 "register_operand" "+r")) | |
4770 | (set (match_dup 1) (match_dup 1))] | |
4771 | "" | |
4772 | "mov %0 = %1" | |
52e12ad0 | 4773 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4774 | |
4775 | ;; Allocate a new register frame. | |
4776 | ||
4777 | (define_insn "alloc" | |
4778 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4779 | (unspec_volatile:DI [(const_int 0)] 0)) | |
4780 | (use (match_operand:DI 1 "const_int_operand" "i")) | |
4781 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4782 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4783 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4784 | "" | |
4785 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4786 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 4787 | (set_attr "predicable" "no")]) |
c65ebc55 | 4788 | |
97e242b0 RH |
4789 | ;; Modifies ar.unat |
4790 | (define_expand "gr_spill" | |
870f9ec0 RH |
4791 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4792 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
4793 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4794 | (clobber (match_dup 3))])] | |
97e242b0 | 4795 | "" |
870f9ec0 | 4796 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4797 | |
870f9ec0 | 4798 | (define_insn "gr_spill_internal" |
c65ebc55 | 4799 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 RH |
4800 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
4801 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4802 | (clobber (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4803 | "" |
2130b7fb BS |
4804 | "* |
4805 | { | |
4806 | return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\"; | |
4807 | }" | |
52e12ad0 | 4808 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4809 | |
97e242b0 RH |
4810 | ;; Reads ar.unat |
4811 | (define_expand "gr_restore" | |
870f9ec0 RH |
4812 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4813 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
4814 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4815 | (use (match_dup 3))])] | |
97e242b0 | 4816 | "" |
870f9ec0 | 4817 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4818 | |
870f9ec0 | 4819 | (define_insn "gr_restore_internal" |
c65ebc55 | 4820 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 RH |
4821 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
4822 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4823 | (use (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4824 | "" |
2130b7fb BS |
4825 | "* |
4826 | { | |
4827 | return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\"; | |
4828 | }" | |
52e12ad0 | 4829 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4830 | |
4831 | (define_insn "fr_spill" | |
3f622353 RH |
4832 | [(set (match_operand:TF 0 "memory_operand" "=m") |
4833 | (unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))] | |
c65ebc55 JW |
4834 | "" |
4835 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 4836 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
4837 | |
4838 | (define_insn "fr_restore" | |
3f622353 RH |
4839 | [(set (match_operand:TF 0 "register_operand" "=f") |
4840 | (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))] | |
c65ebc55 JW |
4841 | "" |
4842 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 4843 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 4844 | |
0024a804 JW |
4845 | ;; ??? The explicit stop is not ideal. It would be better if |
4846 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4847 | ;; fixed later. This avoids an RSE DV. | |
4848 | ||
0c96007e AM |
4849 | (define_insn "bsp_value" |
4850 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4851 | (unspec:DI [(const_int 0)] 20))] | |
4852 | "" | |
0024a804 | 4853 | ";;\;mov %0 = ar.bsp" |
52e12ad0 | 4854 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
4855 | |
4856 | (define_insn "set_bsp" | |
2ed4af6f | 4857 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)] |
0c96007e | 4858 | "" |
13da91fd | 4859 | "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19" |
52e12ad0 | 4860 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 4861 | (set_attr "predicable" "no")]) |
ce152ef8 | 4862 | |
0024a804 JW |
4863 | ;; ??? The explicit stops are not ideal. It would be better if |
4864 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4865 | ;; fixed later. This avoids an RSE DV. | |
4866 | ||
ce152ef8 AM |
4867 | (define_insn "flushrs" |
4868 | [(unspec [(const_int 0)] 21)] | |
4869 | "" | |
0024a804 | 4870 | ";;\;flushrs\;;;" |
52e12ad0 | 4871 | [(set_attr "itanium_class" "rse_m")]) |
c65ebc55 JW |
4872 | \f |
4873 | ;; :::::::::::::::::::: | |
4874 | ;; :: | |
4875 | ;; :: Miscellaneous instructions | |
4876 | ;; :: | |
4877 | ;; :::::::::::::::::::: | |
4878 | ||
4879 | ;; ??? Emiting a NOP instruction isn't very useful. This should probably | |
4880 | ;; be emitting ";;" to force a break in the instruction packing. | |
4881 | ||
4882 | ;; No operation, needed in case the user uses -g but not -O. | |
4883 | (define_insn "nop" | |
4884 | [(const_int 0)] | |
4885 | "" | |
4886 | "nop 0" | |
52e12ad0 | 4887 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4888 | |
2130b7fb BS |
4889 | (define_insn "nop_m" |
4890 | [(const_int 1)] | |
4891 | "" | |
4892 | "nop.m 0" | |
4893 | [(set_attr "itanium_class" "nop_m")]) | |
4894 | ||
4895 | (define_insn "nop_i" | |
4896 | [(const_int 2)] | |
4897 | "" | |
4898 | "nop.i 0" | |
4899 | [(set_attr "itanium_class" "nop_i")]) | |
4900 | ||
4901 | (define_insn "nop_f" | |
4902 | [(const_int 3)] | |
4903 | "" | |
4904 | "nop.f 0" | |
4905 | [(set_attr "itanium_class" "nop_f")]) | |
4906 | ||
4907 | (define_insn "nop_b" | |
4908 | [(const_int 4)] | |
4909 | "" | |
4910 | "nop.b 0" | |
4911 | [(set_attr "itanium_class" "nop_b")]) | |
4912 | ||
4913 | (define_insn "nop_x" | |
4914 | [(const_int 5)] | |
4915 | "" | |
4916 | "" | |
4917 | [(set_attr "itanium_class" "nop_x")]) | |
4918 | ||
4919 | (define_expand "cycle_display" | |
4920 | [(unspec [(match_operand 0 "const_int_operand" "")] 23)] | |
4921 | "ia64_final_schedule" | |
4922 | "") | |
4923 | ||
4924 | (define_insn "*cycle_display_1" | |
4925 | [(unspec [(match_operand 0 "const_int_operand" "")] 23)] | |
4926 | "" | |
4927 | "// cycle %0" | |
4928 | [(set_attr "itanium_class" "ignore") | |
4929 | (set_attr "predicable" "no")]) | |
4930 | ||
4931 | (define_insn "bundle_selector" | |
4932 | [(unspec [(match_operand 0 "const_int_operand" "")] 22)] | |
4933 | "" | |
4934 | "* | |
4935 | { | |
4936 | return get_bundle_name (INTVAL (operands[0])); | |
4937 | }" | |
4938 | [(set_attr "itanium_class" "ignore") | |
4939 | (set_attr "predicable" "no")]) | |
4940 | ||
c65ebc55 JW |
4941 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
4942 | ;; point. | |
4943 | (define_insn "blockage" | |
4944 | [(unspec_volatile [(const_int 0)] 1)] | |
4945 | "" | |
4946 | "" | |
52e12ad0 | 4947 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 4948 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4949 | |
4950 | (define_insn "insn_group_barrier" | |
2130b7fb | 4951 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)] |
c65ebc55 JW |
4952 | "" |
4953 | ";;" | |
52e12ad0 | 4954 | [(set_attr "itanium_class" "stop_bit") |
e5bde68a | 4955 | (set_attr "predicable" "no")]) |
c65ebc55 | 4956 | |
f12f25a7 RH |
4957 | (define_insn "break_f" |
4958 | [(unspec_volatile [(const_int 0)] 3)] | |
4959 | "" | |
4960 | "break.f 0" | |
4961 | [(set_attr "itanium_class" "nop_f")]) | |
c65ebc55 JW |
4962 | \f |
4963 | ;; Non-local goto support. | |
4964 | ||
4965 | (define_expand "save_stack_nonlocal" | |
4966 | [(use (match_operand:OI 0 "memory_operand" "")) | |
4967 | (use (match_operand:DI 1 "register_operand" ""))] | |
4968 | "" | |
4969 | " | |
4970 | { | |
4971 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
4972 | \"__ia64_save_stack_nonlocal\"), | |
4973 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
4974 | operands[1], Pmode); | |
4975 | DONE; | |
4976 | }") | |
4977 | ||
4978 | (define_expand "nonlocal_goto" | |
4979 | [(use (match_operand 0 "general_operand" "")) | |
4980 | (use (match_operand 1 "general_operand" "")) | |
4981 | (use (match_operand 2 "general_operand" "")) | |
4982 | (use (match_operand 3 "general_operand" ""))] | |
4983 | "" | |
4984 | " | |
4985 | { | |
c65ebc55 | 4986 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 AM |
4987 | LCT_NORETURN, VOIDmode, 3, |
4988 | operands[3], Pmode, | |
c65ebc55 | 4989 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
8206fc89 | 4990 | operands[1], Pmode); |
c65ebc55 JW |
4991 | emit_barrier (); |
4992 | DONE; | |
4993 | }") | |
4994 | ||
97e242b0 RH |
4995 | ;; The rest of the setjmp processing happens with the nonlocal_goto expander. |
4996 | ;; ??? This is not tested. | |
4997 | (define_expand "builtin_setjmp_setup" | |
4998 | [(use (match_operand:DI 0 "" ""))] | |
c65ebc55 JW |
4999 | "" |
5000 | " | |
5001 | { | |
97e242b0 RH |
5002 | emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); |
5003 | DONE; | |
5004 | }") | |
5005 | ||
5006 | (define_expand "builtin_setjmp_receiver" | |
5007 | [(use (match_operand:DI 0 "" ""))] | |
5008 | "" | |
5009 | " | |
5010 | { | |
5011 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); | |
c65ebc55 JW |
5012 | DONE; |
5013 | }") | |
5014 | ||
0c96007e AM |
5015 | (define_expand "eh_epilogue" |
5016 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5017 | (use (match_operand:DI 1 "register_operand" "r")) | |
5018 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5019 | "" | |
5020 | " | |
5021 | { | |
5022 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5023 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5024 | ||
5025 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5026 | { | |
5027 | emit_move_insn (bsp, operands[0]); | |
5028 | operands[0] = bsp; | |
5029 | } | |
5030 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5031 | { | |
5032 | emit_move_insn (sp, operands[2]); | |
5033 | operands[2] = sp; | |
5034 | } | |
5035 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5036 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5037 | ||
5038 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5039 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
0c96007e | 5040 | }") |
9525c690 JW |
5041 | \f |
5042 | ;; Builtin apply support. | |
5043 | ||
5044 | (define_expand "restore_stack_nonlocal" | |
5045 | [(use (match_operand:DI 0 "register_operand" "")) | |
5046 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5047 | "" | |
5048 | " | |
5049 | { | |
5050 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5051 | \"__ia64_restore_stack_nonlocal\"), | |
5052 | 0, VOIDmode, 1, | |
5053 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5054 | DONE; | |
5055 | }") | |
5056 | ||
5057 | \f | |
5058 | ;;; Intrinsics support. | |
c65ebc55 | 5059 | |
0551c32d RH |
5060 | (define_expand "mf" |
5061 | [(set (mem:BLK (match_dup 0)) | |
5062 | (unspec:BLK [(mem:BLK (match_dup 0))] 12))] | |
5063 | "" | |
5064 | " | |
5065 | { | |
5066 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
5067 | MEM_VOLATILE_P (operands[0]) = 1; | |
5068 | }") | |
5069 | ||
5070 | (define_insn "*mf_internal" | |
5071 | [(set (match_operand:BLK 0 "" "") | |
5072 | (unspec:BLK [(match_operand:BLK 1 "" "")] 12))] | |
c65ebc55 JW |
5073 | "" |
5074 | "mf" | |
52e12ad0 | 5075 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
5076 | |
5077 | (define_insn "fetchadd_acq_si" | |
0551c32d RH |
5078 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5079 | (match_dup 1)) | |
5080 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5081 | (unspec:SI [(match_dup 1) | |
5082 | (match_operand:SI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5083 | "" |
5084 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 5085 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5086 | |
5087 | (define_insn "fetchadd_acq_di" | |
0551c32d RH |
5088 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5089 | (match_dup 1)) | |
5090 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5091 | (unspec:DI [(match_dup 1) | |
5092 | (match_operand:DI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5093 | "" |
5094 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 5095 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5096 | |
5097 | (define_insn "cmpxchg_acq_si" | |
0551c32d RH |
5098 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5099 | (match_dup 1)) | |
5100 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5101 | (unspec:SI [(match_dup 1) | |
5102 | (match_operand:SI 2 "gr_register_operand" "r") | |
97e242b0 | 5103 | (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))] |
c65ebc55 | 5104 | "" |
97e242b0 | 5105 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 5106 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5107 | |
5108 | (define_insn "cmpxchg_acq_di" | |
0551c32d RH |
5109 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5110 | (match_dup 1)) | |
5111 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5112 | (unspec:DI [(match_dup 1) | |
5113 | (match_operand:DI 2 "gr_register_operand" "r") | |
5114 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))] | |
c65ebc55 | 5115 | "" |
97e242b0 | 5116 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 5117 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 5118 | |
c65ebc55 | 5119 | (define_insn "xchgsi" |
0551c32d RH |
5120 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5121 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5122 | (set (match_dup 1) |
0551c32d | 5123 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5124 | "" |
5125 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 5126 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5127 | |
5128 | (define_insn "xchgdi" | |
0551c32d RH |
5129 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5130 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5131 | (set (match_dup 1) |
0551c32d | 5132 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5133 | "" |
5134 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 5135 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
5136 | \f |
5137 | ;; Predication. | |
5138 | ||
5139 | (define_cond_exec | |
5140 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5141 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5142 | (const_int 0)])] |
5143 | "" | |
5144 | "(%J0)") | |
3b572406 RH |
5145 | |
5146 | (define_insn "pred_rel_mutex" | |
f2f90c63 RH |
5147 | [(set (match_operand:BI 0 "register_operand" "+c") |
5148 | (unspec:BI [(match_dup 0)] 7))] | |
3b572406 | 5149 | "" |
054451ea | 5150 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5151 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5152 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5153 | |
5154 | (define_insn "safe_across_calls_all" | |
5155 | [(unspec_volatile [(const_int 0)] 8)] | |
5156 | "" | |
5157 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5158 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5159 | (set_attr "predicable" "no")]) |
5160 | ||
5161 | (define_insn "safe_across_calls_normal" | |
5162 | [(unspec_volatile [(const_int 0)] 9)] | |
5163 | "" | |
5164 | "* | |
5165 | { | |
5166 | emit_safe_across_calls (asm_out_file); | |
5167 | return \"\"; | |
5168 | }" | |
52e12ad0 | 5169 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5170 | (set_attr "predicable" "no")]) |
5171 |