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c65ebc55 | 1 | ;; IA-64 Machine description template |
5da4f548 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
58 | ||
59 | (UNSPEC_LD_BASE 9) | |
60 | (UNSPEC_GR_SPILL 10) | |
61 | (UNSPEC_GR_RESTORE 11) | |
62 | (UNSPEC_FR_SPILL 12) | |
63 | (UNSPEC_FR_RESTORE 13) | |
64 | (UNSPEC_FR_RECIP_APPROX 14) | |
65 | (UNSPEC_PRED_REL_MUTEX 15) | |
66 | (UNSPEC_POPCNT 16) | |
67 | (UNSPEC_PIC_CALL 17) | |
68 | (UNSPEC_MF 18) | |
69 | (UNSPEC_CMPXCHG_ACQ 19) | |
70 | (UNSPEC_FETCHADD_ACQ 20) | |
71 | (UNSPEC_BSP_VALUE 21) | |
72 | (UNSPEC_FLUSHRS 22) | |
73 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
74 | (UNSPEC_ADDP4 24) |
75 | (UNSPEC_PROLOGUE_USE 25) | |
76 | ]) | |
77 | ||
78 | (define_constants | |
79 | [(UNSPECV_ALLOC 0) | |
80 | (UNSPECV_BLOCKAGE 1) | |
81 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
82 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
83 | (UNSPECV_SET_BSP 4) |
84 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
85 | (UNSPECV_PSAC_NORMAL 6) | |
086c0f96 | 86 | ]) |
c65ebc55 JW |
87 | \f |
88 | ;; :::::::::::::::::::: | |
89 | ;; :: | |
90 | ;; :: Attributes | |
91 | ;; :: | |
92 | ;; :::::::::::::::::::: | |
93 | ||
94 | ;; Instruction type. This primarily determines how instructions can be | |
95 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
96 | ||
97 | ;; A alu, can go in I or M syllable of a bundle | |
98 | ;; I integer | |
99 | ;; M memory | |
100 | ;; F floating-point | |
101 | ;; B branch | |
102 | ;; L long immediate, takes two syllables | |
103 | ;; S stop bit | |
104 | ||
105 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
106 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
107 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
108 | ;; which emit instruction that can go in any slot (e.g. nop). | |
109 | ||
1d5d7a21 RH |
110 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
111 | fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld, | |
112 | chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0, | |
113 | syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f, | |
114 | nop_i,nop_m,nop_x,lfetch" | |
115 | (const_string "unknown")) | |
52e12ad0 | 116 | |
2130b7fb BS |
117 | ;; chk_s has an I and an M form; use type A for convenience. |
118 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
119 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
120 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
121 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 122 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
2130b7fb BS |
123 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
124 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
125 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
126 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
127 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
128 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
129 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 130 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 131 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
132 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
133 | (const_string "unknown"))) | |
c65ebc55 | 134 | |
2130b7fb BS |
135 | (define_attr "itanium_requires_unit0" "no,yes" |
136 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
137 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
138 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
139 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
140 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
141 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
142 | (const_string "no"))) | |
143 | ||
e5bde68a RH |
144 | ;; Predication. True iff this instruction can be predicated. |
145 | ||
146 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
147 | ||
c65ebc55 JW |
148 | \f |
149 | ;; :::::::::::::::::::: | |
150 | ;; :: | |
151 | ;; :: Function Units | |
152 | ;; :: | |
153 | ;; :::::::::::::::::::: | |
154 | ||
2130b7fb BS |
155 | ;; We define 6 "dummy" functional units. All the real work to decide which |
156 | ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only | |
157 | ;; have to ensure here that there are enough copies of the dummy unit so | |
158 | ;; that the scheduler doesn't get confused by MD_SCHED_REORDER. | |
159 | ;; Other than the 6 dummies for normal insns, we also add a single dummy unit | |
160 | ;; for stop bits. | |
161 | ||
162 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0) | |
163 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0) | |
164 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0) | |
165 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0) | |
166 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0) | |
167 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0) | |
168 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0) | |
169 | ||
170 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
171 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0) | |
172 | ;; There is only ony insn `mov = ar.unat' for frar_m: | |
173 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0) | |
174 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0) | |
175 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0) | |
176 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0) | |
177 | ||
178 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0) | |
179 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0) | |
180 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0) | |
181 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0) | |
182 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0) | |
183 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0) | |
184 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0) | |
185 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0) | |
186 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0) | |
187 | ||
188 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
189 | ;; is the 1st syllable of the bundle after stop bit. | |
190 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0) | |
191 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0) | |
192 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0) | |
193 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0) | |
194 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0) | |
195 | ;; Now we use only one insn `mf'. Therfore latency time is set up to 0. | |
196 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0) | |
197 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0) | |
198 | ||
199 | ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use | |
200 | ;; latency time equal to 0: | |
201 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0) | |
202 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
203 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0) | |
204 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0) | |
205 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0) | |
206 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0) | |
207 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0) | |
208 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0) | |
209 | ||
210 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0) | |
211 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0) | |
212 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0) | |
213 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0) | |
214 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0) | |
215 | ||
216 | (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0) | |
217 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0) | |
218 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0) | |
c65ebc55 JW |
219 | \f |
220 | ;; :::::::::::::::::::: | |
221 | ;; :: | |
222 | ;; :: Moves | |
223 | ;; :: | |
224 | ;; :::::::::::::::::::: | |
225 | ||
f2f90c63 RH |
226 | ;; Set of a single predicate register. This is only used to implement |
227 | ;; pr-to-pr move and complement. | |
228 | ||
229 | (define_insn "*movcci" | |
230 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
231 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
232 | "" | |
233 | "@ | |
234 | cmp.ne %0, p0 = r0, r0 | |
235 | cmp.eq %0, p0 = r0, r0 | |
236 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 237 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
238 | (set_attr "predicable" "no")]) |
239 | ||
240 | (define_insn "movbi" | |
cd5c4048 RH |
241 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
242 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
243 | "" |
244 | "@ | |
245 | cmp.ne %0, %I0 = r0, r0 | |
246 | cmp.eq %0, %I0 = r0, r0 | |
247 | # | |
248 | # | |
249 | tbit.nz %0, %I0 = %1, 0 | |
250 | adds %0 = %1, r0 | |
251 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
252 | st1%Q0 %0 = %1%P0 |
253 | mov %0 = %1" | |
52e12ad0 | 254 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
255 | |
256 | (define_split | |
257 | [(set (match_operand:BI 0 "register_operand" "") | |
258 | (match_operand:BI 1 "register_operand" ""))] | |
259 | "reload_completed | |
260 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
261 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
262 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
263 | (set (match_dup 0) (const_int 1))) | |
264 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
265 | (set (match_dup 0) (const_int 0)))] | |
266 | "") | |
267 | ||
268 | (define_split | |
269 | [(set (match_operand:BI 0 "register_operand" "") | |
270 | (match_operand:BI 1 "register_operand" ""))] | |
271 | "reload_completed | |
272 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
273 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
274 | [(set (match_dup 2) (match_dup 4)) | |
275 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 276 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
277 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
278 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
279 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
280 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
281 | ||
c65ebc55 JW |
282 | (define_expand "movqi" |
283 | [(set (match_operand:QI 0 "general_operand" "") | |
284 | (match_operand:QI 1 "general_operand" ""))] | |
285 | "" | |
c65ebc55 | 286 | { |
7b6e506e RH |
287 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
288 | if (!op1) | |
289 | DONE; | |
290 | operands[1] = op1; | |
1d5d7a21 | 291 | }) |
c65ebc55 JW |
292 | |
293 | (define_insn "*movqi_internal" | |
4b983fdc RH |
294 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
295 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 296 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 297 | "@ |
13da91fd | 298 | mov %0 = %r1 |
c65ebc55 JW |
299 | addl %0 = %1, r0 |
300 | ld1%O1 %0 = %1%P1 | |
13da91fd | 301 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 302 | getf.sig %0 = %1 |
13da91fd RH |
303 | setf.sig %0 = %r1 |
304 | mov %0 = %1" | |
52e12ad0 | 305 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
306 | |
307 | (define_expand "movhi" | |
308 | [(set (match_operand:HI 0 "general_operand" "") | |
309 | (match_operand:HI 1 "general_operand" ""))] | |
310 | "" | |
c65ebc55 | 311 | { |
7b6e506e RH |
312 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
313 | if (!op1) | |
314 | DONE; | |
315 | operands[1] = op1; | |
1d5d7a21 | 316 | }) |
c65ebc55 JW |
317 | |
318 | (define_insn "*movhi_internal" | |
4b983fdc RH |
319 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
320 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 321 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 322 | "@ |
13da91fd | 323 | mov %0 = %r1 |
c65ebc55 JW |
324 | addl %0 = %1, r0 |
325 | ld2%O1 %0 = %1%P1 | |
13da91fd | 326 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 327 | getf.sig %0 = %1 |
13da91fd RH |
328 | setf.sig %0 = %r1 |
329 | mov %0 = %1" | |
52e12ad0 | 330 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
331 | |
332 | (define_expand "movsi" | |
333 | [(set (match_operand:SI 0 "general_operand" "") | |
334 | (match_operand:SI 1 "general_operand" ""))] | |
335 | "" | |
c65ebc55 | 336 | { |
7b6e506e RH |
337 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
338 | if (!op1) | |
339 | DONE; | |
340 | operands[1] = op1; | |
1d5d7a21 | 341 | }) |
c65ebc55 | 342 | |
5da4f548 SE |
343 | ;; This is used during early compilation to delay the decision on |
344 | ;; how to refer to a variable as long as possible. This is especially | |
345 | ;; important between initial rtl generation and optimization for | |
346 | ;; deferred functions, since we may acquire additional information | |
347 | ;; on the variables used in the meantime. | |
348 | ||
349 | (define_insn_and_split "movsi_symbolic" | |
350 | [(set (match_operand:SI 0 "register_operand" "=r") | |
351 | (match_operand:SI 1 "symbolic_operand" "s")) | |
352 | (clobber (match_scratch:DI 2 "=r")) | |
353 | (use (reg:DI 1))] | |
354 | "" | |
355 | "* abort ();" | |
356 | "!no_new_pseudos || reload_completed" | |
357 | [(const_int 0)] | |
358 | { | |
359 | rtx scratch = operands[2]; | |
360 | if (!reload_completed) | |
361 | scratch = gen_reg_rtx (Pmode); | |
362 | ia64_expand_load_address (operands[0], operands[1], scratch); | |
363 | DONE; | |
364 | }) | |
365 | ||
c65ebc55 | 366 | (define_insn "*movsi_internal" |
97e242b0 | 367 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 368 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 369 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 370 | "@ |
13da91fd | 371 | mov %0 = %r1 |
c65ebc55 JW |
372 | addl %0 = %1, r0 |
373 | movl %0 = %1 | |
374 | ld4%O1 %0 = %1%P1 | |
13da91fd | 375 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 376 | getf.sig %0 = %1 |
13da91fd | 377 | setf.sig %0 = %r1 |
97e242b0 RH |
378 | mov %0 = %1 |
379 | mov %0 = %1 | |
380 | mov %0 = %r1" | |
1d5d7a21 | 381 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 382 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
383 | |
384 | (define_expand "movdi" | |
385 | [(set (match_operand:DI 0 "general_operand" "") | |
386 | (match_operand:DI 1 "general_operand" ""))] | |
387 | "" | |
c65ebc55 | 388 | { |
7b6e506e RH |
389 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
390 | if (!op1) | |
391 | DONE; | |
392 | operands[1] = op1; | |
1d5d7a21 | 393 | }) |
c65ebc55 | 394 | |
9a89adb8 RH |
395 | ;; This is used during early compilation to delay the decision on |
396 | ;; how to refer to a variable as long as possible. This is especially | |
397 | ;; important between initial rtl generation and optimization for | |
398 | ;; deferred functions, since we may acquire additional information | |
399 | ;; on the variables used in the meantime. | |
400 | ||
401 | (define_insn_and_split "movdi_symbolic" | |
402 | [(set (match_operand:DI 0 "register_operand" "=r") | |
403 | (match_operand:DI 1 "symbolic_operand" "s")) | |
7b6e506e | 404 | (clobber (match_scratch:DI 2 "=r")) |
9a89adb8 RH |
405 | (use (reg:DI 1))] |
406 | "" | |
407 | "* abort ();" | |
7b6e506e | 408 | "!no_new_pseudos || reload_completed" |
9a89adb8 | 409 | [(const_int 0)] |
7b6e506e RH |
410 | { |
411 | rtx scratch = operands[2]; | |
412 | if (!reload_completed) | |
5da4f548 | 413 | scratch = gen_reg_rtx (Pmode); |
7b6e506e RH |
414 | ia64_expand_load_address (operands[0], operands[1], scratch); |
415 | DONE; | |
416 | }) | |
9a89adb8 | 417 | |
c65ebc55 | 418 | (define_insn "*movdi_internal" |
4b983fdc | 419 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 420 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 421 | (match_operand:DI 1 "move_operand" |
52e12ad0 | 422 | "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 423 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
424 | { |
425 | static const char * const alt[] = { | |
1d5d7a21 RH |
426 | "%,mov %0 = %r1", |
427 | "%,addl %0 = %1, r0", | |
428 | "%,movl %0 = %1", | |
429 | "%,ld8%O1 %0 = %1%P1", | |
430 | "%,st8%Q0 %0 = %r1%P0", | |
431 | "%,getf.sig %0 = %1", | |
432 | "%,setf.sig %0 = %r1", | |
433 | "%,mov %0 = %1", | |
434 | "%,ldf8 %0 = %1%P1", | |
435 | "%,stf8 %0 = %1%P0", | |
436 | "%,mov %0 = %1", | |
437 | "%,mov %0 = %r1", | |
438 | "%,mov %0 = %1", | |
439 | "%,mov %0 = %1", | |
440 | "%,mov %0 = %1", | |
441 | "%,mov %0 = %1", | |
442 | "mov %0 = pr", | |
443 | "mov pr = %1, -1" | |
9b7bf67d RH |
444 | }; |
445 | ||
9b7bf67d RH |
446 | if (which_alternative == 2 && ! TARGET_NO_PIC |
447 | && symbolic_operand (operands[1], VOIDmode)) | |
448 | abort (); | |
449 | ||
450 | return alt[which_alternative]; | |
1d5d7a21 | 451 | } |
52e12ad0 | 452 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 453 | |
9b7bf67d RH |
454 | (define_split |
455 | [(set (match_operand:DI 0 "register_operand" "") | |
456 | (match_operand:DI 1 "symbolic_operand" ""))] | |
457 | "reload_completed && ! TARGET_NO_PIC" | |
458 | [(const_int 0)] | |
9b7bf67d | 459 | { |
b5d37c6f | 460 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d | 461 | DONE; |
1d5d7a21 | 462 | }) |
9b7bf67d | 463 | |
c65ebc55 JW |
464 | (define_expand "load_fptr" |
465 | [(set (match_dup 2) | |
5da4f548 | 466 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" ""))) |
ec039e3c | 467 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 | 468 | "" |
c65ebc55 | 469 | { |
ec039e3c RH |
470 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
471 | operands[3] = gen_rtx_MEM (DImode, operands[2]); | |
472 | RTX_UNCHANGING_P (operands[3]) = 1; | |
1d5d7a21 | 473 | }) |
c65ebc55 JW |
474 | |
475 | (define_insn "*load_fptr_internal1" | |
476 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 477 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
c65ebc55 JW |
478 | "" |
479 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 480 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
481 | |
482 | (define_insn "load_gprel" | |
483 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 484 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
c65ebc55 JW |
485 | "" |
486 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 487 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 488 | |
59da9a7d JW |
489 | (define_insn "gprel64_offset" |
490 | [(set (match_operand:DI 0 "register_operand" "=r") | |
491 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
492 | "" | |
493 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 494 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
495 | |
496 | (define_expand "load_gprel64" | |
497 | [(set (match_dup 2) | |
b5d37c6f | 498 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 499 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 500 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 501 | "" |
ec039e3c RH |
502 | { |
503 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 504 | operands[3] = pic_offset_table_rtx; |
1d5d7a21 | 505 | }) |
59da9a7d | 506 | |
c65ebc55 | 507 | (define_expand "load_symptr" |
b5d37c6f BS |
508 | [(set (match_operand:DI 2 "register_operand" "") |
509 | (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) | |
dee4095a | 510 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 | 511 | "" |
c65ebc55 | 512 | { |
dee4095a | 513 | operands[3] = gen_rtx_MEM (DImode, operands[2]); |
b5d37c6f | 514 | operands[4] = pic_offset_table_rtx; |
dee4095a | 515 | RTX_UNCHANGING_P (operands[3]) = 1; |
1d5d7a21 | 516 | }) |
c65ebc55 JW |
517 | |
518 | (define_insn "*load_symptr_internal1" | |
519 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 520 | (plus:DI (reg:DI 1) (match_operand 1 "got_symbolic_operand" "s")))] |
c65ebc55 JW |
521 | "" |
522 | "addl %0 = @ltoff(%1), gp" | |
52e12ad0 | 523 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 524 | |
7b6e506e RH |
525 | (define_insn "load_ltoff_dtpmod" |
526 | [(set (match_operand:DI 0 "register_operand" "=r") | |
527 | (plus:DI (reg:DI 1) | |
528 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
529 | UNSPEC_LTOFF_DTPMOD)))] | |
530 | "" | |
531 | "addl %0 = @ltoff(@dtpmod(%1)), gp" | |
532 | [(set_attr "itanium_class" "ialu")]) | |
533 | ||
534 | (define_insn "load_ltoff_dtprel" | |
535 | [(set (match_operand:DI 0 "register_operand" "=r") | |
536 | (plus:DI (reg:DI 1) | |
537 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
538 | UNSPEC_LTOFF_DTPREL)))] | |
539 | "" | |
540 | "addl %0 = @ltoff(@dtprel(%1)), gp" | |
541 | [(set_attr "itanium_class" "ialu")]) | |
542 | ||
543 | (define_expand "load_dtprel" | |
544 | [(set (match_operand:DI 0 "register_operand" "") | |
545 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
546 | UNSPEC_DTPREL))] | |
547 | "" | |
548 | "") | |
549 | ||
550 | (define_insn "*load_dtprel64" | |
551 | [(set (match_operand:DI 0 "register_operand" "=r") | |
552 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
553 | UNSPEC_DTPREL))] | |
554 | "TARGET_TLS64" | |
555 | "movl %0 = @dtprel(%1)" | |
556 | [(set_attr "itanium_class" "long_i")]) | |
557 | ||
558 | (define_insn "*load_dtprel22" | |
559 | [(set (match_operand:DI 0 "register_operand" "=r") | |
560 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
561 | UNSPEC_DTPREL))] | |
562 | "" | |
563 | "addl %0 = @dtprel(%1), r0" | |
564 | [(set_attr "itanium_class" "ialu")]) | |
565 | ||
566 | (define_expand "add_dtprel" | |
567 | [(set (match_operand:DI 0 "register_operand" "") | |
568 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
569 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
570 | UNSPEC_DTPREL)))] | |
571 | "!TARGET_TLS64" | |
572 | "") | |
573 | ||
574 | (define_insn "*add_dtprel14" | |
575 | [(set (match_operand:DI 0 "register_operand" "=r") | |
576 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
577 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
578 | UNSPEC_DTPREL)))] | |
579 | "TARGET_TLS14" | |
580 | "adds %0 = @dtprel(%2), %1" | |
581 | [(set_attr "itanium_class" "ialu")]) | |
582 | ||
583 | (define_insn "*add_dtprel22" | |
584 | [(set (match_operand:DI 0 "register_operand" "=r") | |
585 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
586 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
587 | UNSPEC_DTPREL)))] | |
588 | "TARGET_TLS22" | |
589 | "addl %0 = @dtprel(%2), %1" | |
590 | [(set_attr "itanium_class" "ialu")]) | |
591 | ||
592 | (define_insn "load_ltoff_tprel" | |
593 | [(set (match_operand:DI 0 "register_operand" "=r") | |
594 | (plus:DI (reg:DI 1) | |
595 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
596 | UNSPEC_LTOFF_TPREL)))] | |
597 | "" | |
598 | "addl %0 = @ltoff(@tprel(%1)), gp" | |
599 | [(set_attr "itanium_class" "ialu")]) | |
600 | ||
601 | (define_expand "load_tprel" | |
602 | [(set (match_operand:DI 0 "register_operand" "") | |
603 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
604 | UNSPEC_TPREL))] | |
605 | "" | |
606 | "") | |
607 | ||
608 | (define_insn "*load_tprel64" | |
609 | [(set (match_operand:DI 0 "register_operand" "=r") | |
610 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
611 | UNSPEC_TPREL))] | |
612 | "TARGET_TLS64" | |
613 | "movl %0 = @tprel(%1)" | |
614 | [(set_attr "itanium_class" "long_i")]) | |
615 | ||
616 | (define_insn "*load_tprel22" | |
617 | [(set (match_operand:DI 0 "register_operand" "=r") | |
618 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
619 | UNSPEC_TPREL))] | |
620 | "" | |
621 | "addl %0 = @tprel(%1), r0" | |
622 | [(set_attr "itanium_class" "ialu")]) | |
623 | ||
624 | (define_expand "add_tprel" | |
625 | [(set (match_operand:DI 0 "register_operand" "") | |
626 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
627 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
628 | UNSPEC_TPREL)))] | |
629 | "!TARGET_TLS64" | |
630 | "") | |
631 | ||
632 | (define_insn "*add_tprel14" | |
633 | [(set (match_operand:DI 0 "register_operand" "=r") | |
634 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
635 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
636 | UNSPEC_TPREL)))] | |
637 | "TARGET_TLS14" | |
638 | "adds %0 = @tprel(%2), %1" | |
639 | [(set_attr "itanium_class" "ialu")]) | |
640 | ||
641 | (define_insn "*add_tprel22" | |
642 | [(set (match_operand:DI 0 "register_operand" "=r") | |
643 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
644 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
645 | UNSPEC_TPREL)))] | |
646 | "TARGET_TLS22" | |
647 | "addl %0 = @tprel(%2), %1" | |
648 | [(set_attr "itanium_class" "ialu")]) | |
649 | ||
3f622353 RH |
650 | ;; With no offsettable memory references, we've got to have a scratch |
651 | ;; around to play with the second word. | |
652 | (define_expand "movti" | |
653 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
654 | (match_operand:TI 1 "general_operand" "")) | |
655 | (clobber (match_scratch:DI 2 ""))])] | |
656 | "" | |
3f622353 | 657 | { |
7b6e506e RH |
658 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
659 | if (!op1) | |
660 | DONE; | |
661 | operands[1] = op1; | |
1d5d7a21 | 662 | }) |
3f622353 RH |
663 | |
664 | (define_insn_and_split "*movti_internal" | |
665 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
666 | (match_operand:TI 1 "general_operand" "ri,m,r")) | |
667 | (clobber (match_scratch:DI 2 "=X,&r,&r"))] | |
668 | "ia64_move_ok (operands[0], operands[1])" | |
669 | "#" | |
670 | "reload_completed" | |
671 | [(const_int 0)] | |
3f622353 | 672 | { |
703cf211 | 673 | rtx adj1, adj2, in[2], out[2], insn; |
3f622353 RH |
674 | int first; |
675 | ||
676 | adj1 = ia64_split_timode (in, operands[1], operands[2]); | |
677 | adj2 = ia64_split_timode (out, operands[0], operands[2]); | |
678 | ||
679 | first = 0; | |
680 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
681 | { | |
682 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
683 | abort (); | |
684 | first = 1; | |
685 | } | |
686 | ||
687 | if (adj1 && adj2) | |
688 | abort (); | |
689 | if (adj1) | |
690 | emit_insn (adj1); | |
691 | if (adj2) | |
692 | emit_insn (adj2); | |
703cf211 BS |
693 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); |
694 | if (GET_CODE (out[first]) == MEM | |
695 | && GET_CODE (XEXP (out[first], 0)) == POST_MODIFY) | |
696 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
697 | XEXP (XEXP (out[first], 0), 0), | |
698 | REG_NOTES (insn)); | |
699 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
700 | if (GET_CODE (out[!first]) == MEM | |
701 | && GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY) | |
702 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
703 | XEXP (XEXP (out[!first], 0), 0), | |
704 | REG_NOTES (insn)); | |
3f622353 | 705 | DONE; |
1d5d7a21 | 706 | } |
52e12ad0 | 707 | [(set_attr "itanium_class" "unknown") |
3f622353 | 708 | (set_attr "predicable" "no")]) |
e314e331 | 709 | |
3f622353 RH |
710 | ;; ??? SSA creates these. Can't allow memories since we don't have |
711 | ;; the scratch register. Fortunately combine will know how to add | |
712 | ;; the clobber and scratch. | |
713 | (define_insn_and_split "*movti_internal_reg" | |
714 | [(set (match_operand:TI 0 "register_operand" "=r") | |
715 | (match_operand:TI 1 "nonmemory_operand" "ri"))] | |
716 | "" | |
e314e331 | 717 | "#" |
3f622353 RH |
718 | "reload_completed" |
719 | [(const_int 0)] | |
3f622353 RH |
720 | { |
721 | rtx in[2], out[2]; | |
722 | int first; | |
723 | ||
724 | ia64_split_timode (in, operands[1], NULL_RTX); | |
725 | ia64_split_timode (out, operands[0], NULL_RTX); | |
726 | ||
727 | first = 0; | |
728 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
729 | { | |
730 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
731 | abort (); | |
732 | first = 1; | |
733 | } | |
734 | ||
735 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
736 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
737 | DONE; | |
1d5d7a21 | 738 | } |
52e12ad0 | 739 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
740 | (set_attr "predicable" "no")]) |
741 | ||
3f622353 RH |
742 | (define_expand "reload_inti" |
743 | [(parallel [(set (match_operand:TI 0 "register_operand" "=r") | |
744 | (match_operand:TI 1 "" "m")) | |
60a3c181 | 745 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 | 746 | "" |
3f622353 | 747 | { |
60a3c181 RH |
748 | unsigned int s_regno = REGNO (operands[2]); |
749 | if (s_regno == REGNO (operands[0])) | |
750 | s_regno += 1; | |
751 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
1d5d7a21 | 752 | }) |
3f622353 RH |
753 | |
754 | (define_expand "reload_outti" | |
755 | [(parallel [(set (match_operand:TI 0 "" "=m") | |
756 | (match_operand:TI 1 "register_operand" "r")) | |
60a3c181 | 757 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 | 758 | "" |
3f622353 | 759 | { |
60a3c181 RH |
760 | unsigned int s_regno = REGNO (operands[2]); |
761 | if (s_regno == REGNO (operands[1])) | |
762 | s_regno += 1; | |
763 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
1d5d7a21 | 764 | }) |
e314e331 | 765 | |
c65ebc55 JW |
766 | ;; Floating Point Moves |
767 | ;; | |
768 | ;; Note - Patterns for SF mode moves are compulsory, but | |
769 | ;; patterns for DF are optional, as GCC can synthesise them. | |
770 | ||
771 | (define_expand "movsf" | |
772 | [(set (match_operand:SF 0 "general_operand" "") | |
773 | (match_operand:SF 1 "general_operand" ""))] | |
774 | "" | |
c65ebc55 | 775 | { |
7b6e506e RH |
776 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
777 | if (!op1) | |
778 | DONE; | |
779 | operands[1] = op1; | |
1d5d7a21 | 780 | }) |
c65ebc55 | 781 | |
c65ebc55 | 782 | (define_insn "*movsf_internal" |
4b983fdc RH |
783 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
784 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 785 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 786 | "@ |
1d5d7a21 RH |
787 | mov %0 = %F1 |
788 | ldfs %0 = %1%P1 | |
789 | stfs %0 = %F1%P0 | |
790 | getf.s %0 = %F1 | |
791 | setf.s %0 = %1 | |
792 | mov %0 = %1 | |
793 | ld4%O1 %0 = %1%P1 | |
794 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 795 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
796 | |
797 | (define_expand "movdf" | |
798 | [(set (match_operand:DF 0 "general_operand" "") | |
799 | (match_operand:DF 1 "general_operand" ""))] | |
800 | "" | |
c65ebc55 | 801 | { |
7b6e506e RH |
802 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
803 | if (!op1) | |
804 | DONE; | |
805 | operands[1] = op1; | |
1d5d7a21 | 806 | }) |
c65ebc55 | 807 | |
c65ebc55 | 808 | (define_insn "*movdf_internal" |
4b983fdc RH |
809 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
810 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 811 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 812 | "@ |
1d5d7a21 RH |
813 | mov %0 = %F1 |
814 | ldfd %0 = %1%P1 | |
815 | stfd %0 = %F1%P0 | |
816 | getf.d %0 = %F1 | |
817 | setf.d %0 = %1 | |
818 | mov %0 = %1 | |
819 | ld8%O1 %0 = %1%P1 | |
820 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 821 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 822 | |
3f622353 RH |
823 | ;; With no offsettable memory references, we've got to have a scratch |
824 | ;; around to play with the second word if the variable winds up in GRs. | |
825 | (define_expand "movtf" | |
826 | [(set (match_operand:TF 0 "general_operand" "") | |
827 | (match_operand:TF 1 "general_operand" ""))] | |
23c108af | 828 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 829 | { |
3f622353 RH |
830 | /* We must support TFmode loads into general registers for stdarg/vararg |
831 | and unprototyped calls. We split them into DImode loads for convenience. | |
832 | We don't need TFmode stores from general regs, because a stdarg/vararg | |
833 | routine does a block store to memory of unnamed arguments. */ | |
834 | if (GET_CODE (operands[0]) == REG | |
835 | && GR_REGNO_P (REGNO (operands[0]))) | |
836 | { | |
837 | /* We're hoping to transform everything that deals with TFmode | |
838 | quantities and GR registers early in the compiler. */ | |
839 | if (no_new_pseudos) | |
840 | abort (); | |
841 | ||
842 | /* Struct to register can just use TImode instead. */ | |
843 | if ((GET_CODE (operands[1]) == SUBREG | |
844 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
845 | || (GET_CODE (operands[1]) == REG | |
846 | && GR_REGNO_P (REGNO (operands[1])))) | |
847 | { | |
848 | emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), | |
849 | SUBREG_REG (operands[1])); | |
850 | DONE; | |
851 | } | |
852 | ||
853 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
854 | { | |
855 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), | |
2bf47a10 | 856 | operand_subword (operands[1], 0, 0, TFmode)); |
3f622353 | 857 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), |
2bf47a10 | 858 | operand_subword (operands[1], 1, 0, TFmode)); |
3f622353 RH |
859 | DONE; |
860 | } | |
861 | ||
862 | /* If the quantity is in a register not known to be GR, spill it. */ | |
863 | if (register_operand (operands[1], TFmode)) | |
864 | operands[1] = spill_tfmode_operand (operands[1], 1); | |
865 | ||
866 | if (GET_CODE (operands[1]) == MEM) | |
867 | { | |
868 | rtx out[2]; | |
869 | ||
870 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
871 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); | |
872 | ||
f4ef873c RK |
873 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
874 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
875 | DONE; |
876 | } | |
877 | ||
878 | abort (); | |
879 | } | |
880 | ||
881 | if (! reload_in_progress && ! reload_completed) | |
882 | { | |
883 | operands[0] = spill_tfmode_operand (operands[0], 0); | |
884 | operands[1] = spill_tfmode_operand (operands[1], 0); | |
885 | ||
886 | if (! ia64_move_ok (operands[0], operands[1])) | |
887 | operands[1] = force_reg (TFmode, operands[1]); | |
888 | } | |
1d5d7a21 | 889 | }) |
e5bde68a | 890 | |
3b572406 | 891 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 892 | |
3f622353 RH |
893 | (define_insn "*movtf_internal" |
894 | [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m") | |
895 | (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] | |
23c108af | 896 | "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 897 | "@ |
1d5d7a21 RH |
898 | mov %0 = %F1 |
899 | ldfe %0 = %1%P1 | |
900 | stfe %0 = %F1%P0" | |
52e12ad0 | 901 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
c65ebc55 JW |
902 | \f |
903 | ;; :::::::::::::::::::: | |
904 | ;; :: | |
905 | ;; :: Conversions | |
906 | ;; :: | |
907 | ;; :::::::::::::::::::: | |
908 | ||
909 | ;; Signed conversions from a smaller integer to a larger integer | |
910 | ||
911 | (define_insn "extendqidi2" | |
0551c32d RH |
912 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
913 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
914 | "" |
915 | "sxt1 %0 = %1" | |
52e12ad0 | 916 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
917 | |
918 | (define_insn "extendhidi2" | |
0551c32d RH |
919 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
920 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
921 | "" |
922 | "sxt2 %0 = %1" | |
52e12ad0 | 923 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
924 | |
925 | (define_insn "extendsidi2" | |
655f2eb9 RH |
926 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
927 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
928 | "" |
929 | "@ | |
930 | sxt4 %0 = %1 | |
aebf2462 | 931 | fsxt.r %0 = %1, %1" |
52e12ad0 | 932 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
933 | |
934 | ;; Unsigned conversions from a smaller integer to a larger integer | |
935 | ||
936 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
937 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
938 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
939 | "" |
940 | "@ | |
941 | zxt1 %0 = %1 | |
942 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 943 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
944 | |
945 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
946 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
947 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
948 | "" |
949 | "@ | |
950 | zxt2 %0 = %1 | |
951 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 952 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
953 | |
954 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 955 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 956 | (zero_extend:DI |
655f2eb9 | 957 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
958 | "" |
959 | "@ | |
960 | zxt4 %0 = %1 | |
961 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 962 | fmix.r %0 = f0, %1" |
52e12ad0 | 963 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
964 | |
965 | ;; Convert between floating point types of different sizes. | |
966 | ||
640cea5f JW |
967 | ;; At first glance, it would appear that emitting fnorm for an extending |
968 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
969 | ;; correctly only if the input is properly rounded for its type. In | |
970 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
971 | ;; denorm single. Since we don't know what the next instruction will be, we | |
972 | ;; have to emit an fnorm. | |
973 | ||
e8e20f18 RH |
974 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
975 | ;; when we can. Should probably use a scheme like has been proposed | |
976 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
977 | ;; would let combine merge the thing into adjacent insns. See also how the |
978 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
979 | ;; se_register_operand. | |
c65ebc55 | 980 | |
640cea5f JW |
981 | (define_insn "extendsfdf2" |
982 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
983 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 984 | "" |
640cea5f JW |
985 | "fnorm.d %0 = %1" |
986 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 987 | |
640cea5f JW |
988 | (define_insn "extendsftf2" |
989 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
990 | (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))] | |
23c108af | 991 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
992 | "fnorm %0 = %1" |
993 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 994 | |
640cea5f JW |
995 | (define_insn "extenddftf2" |
996 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
997 | (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))] | |
23c108af | 998 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
999 | "fnorm %0 = %1" |
1000 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1001 | |
c65ebc55 | 1002 | (define_insn "truncdfsf2" |
0551c32d RH |
1003 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1004 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1005 | "" |
aebf2462 | 1006 | "fnorm.s %0 = %1" |
52e12ad0 | 1007 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1008 | |
3f622353 | 1009 | (define_insn "trunctfsf2" |
0551c32d RH |
1010 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1011 | (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1012 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1013 | "fnorm.s %0 = %1" |
52e12ad0 | 1014 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1015 | |
3f622353 | 1016 | (define_insn "trunctfdf2" |
0551c32d RH |
1017 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1018 | (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1019 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1020 | "fnorm.d %0 = %1" |
52e12ad0 | 1021 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1022 | |
1023 | ;; Convert between signed integer types and floating point. | |
1024 | ||
3f622353 | 1025 | (define_insn "floatditf2" |
0551c32d RH |
1026 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
1027 | (float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 1028 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 1029 | "fcvt.xf %0 = %1" |
52e12ad0 | 1030 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1031 | |
23c108af SE |
1032 | ;; ??? Suboptimal. This should be split somehow. |
1033 | (define_insn "floatdidf2" | |
1034 | [(set (match_operand:DF 0 "register_operand" "=f") | |
1035 | (float:DF (match_operand:DI 1 "register_operand" "f")))] | |
1036 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
1037 | "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0" | |
1038 | [(set_attr "itanium_class" "fcvtfx")]) | |
1039 | ||
1040 | ;; ??? Suboptimal. This should be split somehow. | |
1041 | (define_insn "floatdisf2" | |
1042 | [(set (match_operand:SF 0 "register_operand" "=f") | |
1043 | (float:SF (match_operand:DI 1 "register_operand" "f")))] | |
1044 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
1045 | "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0" | |
1046 | [(set_attr "itanium_class" "fcvtfx")]) | |
1047 | ||
c65ebc55 | 1048 | (define_insn "fix_truncsfdi2" |
0551c32d RH |
1049 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1050 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1051 | "" |
aebf2462 | 1052 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1053 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1054 | |
1055 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1056 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1057 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1058 | "" |
aebf2462 | 1059 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1060 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1061 | |
3f622353 | 1062 | (define_insn "fix_trunctfdi2" |
0551c32d RH |
1063 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1064 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1065 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1066 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1067 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1068 | |
655f2eb9 RH |
1069 | (define_insn "fix_trunctfdi2_alts" |
1070 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
1071 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
1072 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 1073 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1074 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1075 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1076 | |
c65ebc55 JW |
1077 | ;; Convert between unsigned integer types and floating point. |
1078 | ||
1079 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1080 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1081 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1082 | "" |
aebf2462 | 1083 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1084 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1085 | |
1086 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1087 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1088 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1089 | "" |
aebf2462 | 1090 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1091 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1092 | |
3f622353 | 1093 | (define_insn "floatunsditf2" |
0551c32d RH |
1094 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
1095 | (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 1096 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1097 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1098 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1099 | |
c65ebc55 | 1100 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1101 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1102 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1103 | "" |
aebf2462 | 1104 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1105 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1106 | |
1107 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1108 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1109 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1110 | "" |
aebf2462 | 1111 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1112 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1113 | |
3f622353 | 1114 | (define_insn "fixuns_trunctfdi2" |
0551c32d RH |
1115 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1116 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1117 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1118 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1119 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 RH |
1120 | |
1121 | (define_insn "fixuns_trunctfdi2_alts" | |
1122 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
1123 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
1124 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 1125 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1126 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1127 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1128 | \f |
1129 | ;; :::::::::::::::::::: | |
1130 | ;; :: | |
1131 | ;; :: Bit field extraction | |
1132 | ;; :: | |
1133 | ;; :::::::::::::::::::: | |
1134 | ||
c65ebc55 | 1135 | (define_insn "extv" |
0551c32d RH |
1136 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1137 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1138 | (match_operand:DI 2 "const_int_operand" "n") |
1139 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1140 | "" | |
1141 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1142 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1143 | |
1144 | (define_insn "extzv" | |
0551c32d RH |
1145 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1146 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1147 | (match_operand:DI 2 "const_int_operand" "n") |
1148 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1149 | "" | |
1150 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1151 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1152 | |
1153 | ;; Insert a bit field. | |
1154 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1155 | ;; Source1 can be 0 or -1. | |
1156 | ;; Source2 can be 0. | |
1157 | ||
1158 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1159 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1160 | ;; where source2 != dest. | |
1161 | ||
1162 | (define_expand "insv" | |
0551c32d | 1163 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1164 | (match_operand:DI 1 "const_int_operand" "") |
1165 | (match_operand:DI 2 "const_int_operand" "")) | |
1166 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1167 | "" | |
c65ebc55 JW |
1168 | { |
1169 | int width = INTVAL (operands[1]); | |
1170 | int shift = INTVAL (operands[2]); | |
1171 | ||
1172 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1173 | pseudo. */ | |
1174 | if (! register_operand (operands[3], DImode) | |
1175 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1176 | operands[3] = force_reg (DImode, operands[3]); | |
1177 | ||
1178 | /* If this is a single dep instruction, we have nothing to do. */ | |
1179 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1180 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1181 | { | |
1182 | /* Check for cases that can be implemented with a mix instruction. */ | |
1183 | if (width == 32 && shift == 0) | |
1184 | { | |
1185 | /* Directly generating the mix4left instruction confuses | |
1186 | optimize_bit_field in function.c. Since this is performing | |
1187 | a useful optimization, we defer generation of the complicated | |
1188 | mix4left RTL to the first splitting phase. */ | |
1189 | rtx tmp = gen_reg_rtx (DImode); | |
1190 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1191 | DONE; | |
1192 | } | |
1193 | else if (width == 32 && shift == 32) | |
1194 | { | |
1195 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1196 | DONE; | |
1197 | } | |
1198 | ||
d2ba6dcf JW |
1199 | /* We could handle remaining cases by emitting multiple dep |
1200 | instructions. | |
1201 | ||
1202 | If we need more than two dep instructions then we lose. A 6 | |
1203 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1204 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1205 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1206 | only one function unit that can execute dep and shr immed. | |
1207 | ||
1208 | If we only need two dep instruction, then we still lose. | |
1209 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1210 | the unnecessary mov, this is still undesirable because it will be | |
1211 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1212 | function unit. */ | |
1213 | ||
c65ebc55 JW |
1214 | FAIL; |
1215 | ||
1216 | #if 0 | |
1217 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1218 | for now. */ | |
1219 | while (width > 16) | |
1220 | { | |
1221 | rtx tmp; | |
1222 | ||
1223 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1224 | operands[3])); | |
1225 | shift += 16; | |
1226 | width -= 16; | |
1227 | tmp = gen_reg_rtx (DImode); | |
1228 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1229 | operands[3] = tmp; | |
1230 | } | |
1231 | operands[1] = GEN_INT (width); | |
1232 | operands[2] = GEN_INT (shift); | |
1233 | #endif | |
1234 | } | |
1d5d7a21 | 1235 | }) |
c65ebc55 JW |
1236 | |
1237 | (define_insn "*insv_internal" | |
0551c32d | 1238 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1239 | (match_operand:DI 1 "const_int_operand" "n") |
1240 | (match_operand:DI 2 "const_int_operand" "n")) | |
1241 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1242 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1243 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1244 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1245 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1246 | |
041f25e6 RH |
1247 | ;; Combine doesn't like to create bitfield insertions into zero. |
1248 | (define_insn "*depz_internal" | |
0551c32d RH |
1249 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1250 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1251 | (match_operand:DI 2 "const_int_operand" "n")) |
1252 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1253 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1254 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
041f25e6 RH |
1255 | { |
1256 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1257 | return "%,dep.z %0 = %1, %2, %3"; |
1258 | } | |
52e12ad0 | 1259 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1260 | |
c65ebc55 | 1261 | (define_insn "shift_mix4left" |
0551c32d | 1262 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1263 | (const_int 32) (const_int 0)) |
0551c32d RH |
1264 | (match_operand:DI 1 "gr_register_operand" "r")) |
1265 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1266 | "" |
1267 | "#" | |
52e12ad0 | 1268 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1269 | |
c65ebc55 JW |
1270 | (define_split |
1271 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1272 | (const_int 32) (const_int 0)) | |
1273 | (match_operand:DI 1 "register_operand" "")) | |
1274 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1275 | "reload_completed" | |
1276 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
c65ebc55 JW |
1277 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) |
1278 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1279 | "operands[3] = operands[2];") | |
1280 | ||
1281 | (define_split | |
1282 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1283 | (const_int 32) (const_int 0)) | |
1284 | (match_operand:DI 1 "register_operand" "")) | |
1285 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1286 | "! reload_completed" | |
1287 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
1288 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1289 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1290 | "operands[3] = operands[2];") | |
1291 | ||
1292 | (define_insn "*mix4left" | |
0551c32d | 1293 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1294 | (const_int 32) (const_int 0)) |
0551c32d | 1295 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1296 | (const_int 32)))] |
1297 | "" | |
1298 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1299 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1300 | |
1301 | (define_insn "mix4right" | |
0551c32d | 1302 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1303 | (const_int 32) (const_int 32)) |
0551c32d | 1304 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1305 | "" |
1306 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1307 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1308 | |
1309 | ;; This is used by the rotrsi3 pattern. | |
1310 | ||
1311 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1312 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1313 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1314 | (ashift:DI (zero_extend:DI | |
1315 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1316 | (const_int 32))))] |
1317 | "" | |
fa9a44e8 | 1318 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1319 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1320 | |
1321 | \f | |
1322 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1323 | ;; :: |
f2f90c63 RH |
1324 | ;; :: 1 bit Integer arithmetic |
1325 | ;; :: | |
1326 | ;; :::::::::::::::::::: | |
1327 | ||
1328 | (define_insn_and_split "andbi3" | |
1329 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1330 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1331 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1332 | "" | |
1333 | "@ | |
1334 | # | |
1335 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1336 | and %0 = %2, %1" | |
1337 | "reload_completed | |
1338 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1339 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1340 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1341 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1342 | (match_dup 0))))] | |
1343 | "" | |
52e12ad0 | 1344 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1345 | |
1346 | (define_insn_and_split "*andcmbi3" | |
1347 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1348 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1349 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1350 | "" | |
1351 | "@ | |
1352 | # | |
967603ef | 1353 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1354 | andcm %0 = %2, %1" |
1355 | "reload_completed | |
1356 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1357 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1358 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1359 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1360 | (match_dup 0))))] | |
1361 | "" | |
52e12ad0 | 1362 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1363 | |
1364 | (define_insn_and_split "iorbi3" | |
1365 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1366 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1367 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1368 | "" | |
1369 | "@ | |
1370 | # | |
1371 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1372 | or %0 = %2, %1" | |
1373 | "reload_completed | |
1374 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1375 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1376 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1377 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1378 | (match_dup 0))))] | |
1379 | "" | |
52e12ad0 | 1380 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1381 | |
1382 | (define_insn_and_split "*iorcmbi3" | |
1383 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1384 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1385 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1386 | "" | |
1387 | "@ | |
1388 | # | |
967603ef | 1389 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1390 | "reload_completed |
1391 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1392 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1393 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1394 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1395 | (match_dup 0))))] | |
1396 | "" | |
52e12ad0 | 1397 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1398 | |
1399 | (define_insn "one_cmplbi2" | |
1400 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1401 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1402 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1403 | "" | |
1404 | "@ | |
1405 | tbit.z %0, %I0 = %1, 0 | |
1406 | xor %0 = 1, %1 | |
1407 | # | |
1408 | #" | |
52e12ad0 | 1409 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1410 | |
1411 | (define_split | |
1412 | [(set (match_operand:BI 0 "register_operand" "") | |
1413 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1414 | (clobber (match_scratch:BI 2 ""))] | |
1415 | "reload_completed | |
1416 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1417 | && rtx_equal_p (operands[0], operands[1])" |
1418 | [(set (match_dup 4) (match_dup 3)) | |
1419 | (set (match_dup 0) (const_int 1)) | |
1420 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1421 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1422 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1423 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1424 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1425 | ||
1426 | (define_split | |
1427 | [(set (match_operand:BI 0 "register_operand" "") | |
1428 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1429 | (clobber (match_scratch:BI 2 ""))] | |
1430 | "reload_completed | |
1431 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1432 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1433 | && ! rtx_equal_p (operands[0], operands[1])" | |
1434 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1435 | (set (match_dup 0) (const_int 0))) | |
1436 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1437 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1438 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1439 | "") |
1440 | ||
1441 | (define_insn "*cmpsi_and_0" | |
1442 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1443 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1444 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1445 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1446 | (match_operand:BI 1 "register_operand" "0")))] | |
1447 | "" | |
1448 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1449 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1450 | |
1451 | (define_insn "*cmpsi_and_1" | |
1452 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1453 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1454 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1455 | (const_int 0)]) | |
1456 | (match_operand:BI 1 "register_operand" "0")))] | |
1457 | "" | |
1458 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1459 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1460 | |
1461 | (define_insn "*cmpsi_andnot_0" | |
1462 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1463 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1464 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1465 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1466 | (match_operand:BI 1 "register_operand" "0")))] | |
1467 | "" | |
1468 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1469 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1470 | |
1471 | (define_insn "*cmpsi_andnot_1" | |
1472 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1473 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1474 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1475 | (const_int 0)])) | |
1476 | (match_operand:BI 1 "register_operand" "0")))] | |
1477 | "" | |
1478 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1479 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1480 | |
1481 | (define_insn "*cmpdi_and_0" | |
1482 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1483 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1484 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1485 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1486 | (match_operand:BI 1 "register_operand" "0")))] | |
1487 | "" | |
1488 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1489 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1490 | |
1491 | (define_insn "*cmpdi_and_1" | |
1492 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1493 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1494 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1495 | (const_int 0)]) | |
1496 | (match_operand:BI 1 "register_operand" "0")))] | |
1497 | "" | |
1498 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1499 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1500 | |
1501 | (define_insn "*cmpdi_andnot_0" | |
1502 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1503 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1504 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1505 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1506 | (match_operand:BI 1 "register_operand" "0")))] | |
1507 | "" | |
1508 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1509 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1510 | |
1511 | (define_insn "*cmpdi_andnot_1" | |
1512 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1513 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1514 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1515 | (const_int 0)])) | |
1516 | (match_operand:BI 1 "register_operand" "0")))] | |
1517 | "" | |
1518 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1519 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1520 | |
1521 | (define_insn "*tbit_and_0" | |
1522 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1523 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1524 | (const_int 1)) | |
1525 | (const_int 0)) | |
c77e04ae | 1526 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1527 | "" |
1528 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1529 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1530 | |
1531 | (define_insn "*tbit_and_1" | |
1532 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1533 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1534 | (const_int 1)) | |
1535 | (const_int 0)) | |
c77e04ae | 1536 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1537 | "" |
1538 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1539 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1540 | |
1541 | (define_insn "*tbit_and_2" | |
1542 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1543 | (and:BI (ne:BI (zero_extract:DI | |
1544 | (match_operand:DI 1 "gr_register_operand" "r") | |
1545 | (const_int 1) | |
1546 | (match_operand:DI 2 "const_int_operand" "n")) | |
1547 | (const_int 0)) | |
1548 | (match_operand:BI 3 "register_operand" "0")))] | |
1549 | "" | |
1550 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1551 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1552 | |
1553 | (define_insn "*tbit_and_3" | |
1554 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1555 | (and:BI (eq:BI (zero_extract:DI | |
1556 | (match_operand:DI 1 "gr_register_operand" "r") | |
1557 | (const_int 1) | |
1558 | (match_operand:DI 2 "const_int_operand" "n")) | |
1559 | (const_int 0)) | |
1560 | (match_operand:BI 3 "register_operand" "0")))] | |
1561 | "" | |
1562 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1563 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1564 | |
1565 | (define_insn "*cmpsi_or_0" | |
1566 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1567 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1568 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1569 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1570 | (match_operand:BI 1 "register_operand" "0")))] | |
1571 | "" | |
1572 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1573 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1574 | |
1575 | (define_insn "*cmpsi_or_1" | |
1576 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1577 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1578 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1579 | (const_int 0)]) | |
1580 | (match_operand:BI 1 "register_operand" "0")))] | |
1581 | "" | |
1582 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1583 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1584 | |
1585 | (define_insn "*cmpsi_orcm_0" | |
1586 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1587 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1588 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1589 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1590 | (match_operand:BI 1 "register_operand" "0")))] | |
1591 | "" | |
1592 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1593 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1594 | |
1595 | (define_insn "*cmpsi_orcm_1" | |
1596 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1597 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1598 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1599 | (const_int 0)])) | |
1600 | (match_operand:BI 1 "register_operand" "0")))] | |
1601 | "" | |
1602 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1603 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1604 | |
1605 | (define_insn "*cmpdi_or_0" | |
1606 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1607 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1608 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1609 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1610 | (match_operand:BI 1 "register_operand" "0")))] | |
1611 | "" | |
1612 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1613 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1614 | |
1615 | (define_insn "*cmpdi_or_1" | |
1616 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1617 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1618 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1619 | (const_int 0)]) | |
1620 | (match_operand:BI 1 "register_operand" "0")))] | |
1621 | "" | |
1622 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1623 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1624 | |
1625 | (define_insn "*cmpdi_orcm_0" | |
1626 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1627 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1628 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1629 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1630 | (match_operand:BI 1 "register_operand" "0")))] | |
1631 | "" | |
1632 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1633 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1634 | |
1635 | (define_insn "*cmpdi_orcm_1" | |
1636 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1637 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1638 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1639 | (const_int 0)])) | |
1640 | (match_operand:BI 1 "register_operand" "0")))] | |
1641 | "" | |
1642 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1643 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1644 | |
1645 | (define_insn "*tbit_or_0" | |
1646 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1647 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1648 | (const_int 1)) | |
1649 | (const_int 0)) | |
c77e04ae | 1650 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1651 | "" |
1652 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1653 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1654 | |
1655 | (define_insn "*tbit_or_1" | |
1656 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1657 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1658 | (const_int 1)) | |
1659 | (const_int 0)) | |
c77e04ae | 1660 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1661 | "" |
1662 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1663 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1664 | |
1665 | (define_insn "*tbit_or_2" | |
1666 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1667 | (ior:BI (ne:BI (zero_extract:DI | |
1668 | (match_operand:DI 1 "gr_register_operand" "r") | |
1669 | (const_int 1) | |
1670 | (match_operand:DI 2 "const_int_operand" "n")) | |
1671 | (const_int 0)) | |
1672 | (match_operand:BI 3 "register_operand" "0")))] | |
1673 | "" | |
1674 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1675 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1676 | |
1677 | (define_insn "*tbit_or_3" | |
1678 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1679 | (ior:BI (eq:BI (zero_extract:DI | |
1680 | (match_operand:DI 1 "gr_register_operand" "r") | |
1681 | (const_int 1) | |
1682 | (match_operand:DI 2 "const_int_operand" "n")) | |
1683 | (const_int 0)) | |
1684 | (match_operand:BI 3 "register_operand" "0")))] | |
1685 | "" | |
1686 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1687 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1688 | |
1689 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1690 | ||
1691 | (define_split | |
1692 | [(set (match_operand:BI 0 "register_operand" "") | |
1693 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1694 | (const_int 0)) | |
1695 | (match_operand:DI 3 "register_operand" "")) | |
1696 | (const_int 0)))] | |
1697 | "" | |
1698 | [(set (match_dup 0) | |
1699 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1700 | (match_dup 2)))] | |
1701 | "") | |
1702 | ||
1703 | (define_split | |
1704 | [(set (match_operand:BI 0 "register_operand" "") | |
1705 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1706 | (const_int 0)) | |
1707 | (match_operand:DI 3 "register_operand" "")) | |
1708 | (const_int 0)))] | |
1709 | "" | |
1710 | [(set (match_dup 0) | |
1711 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1712 | (match_dup 2))) | |
1713 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1714 | (clobber (scratch))])] | |
1715 | "") | |
1716 | ||
1717 | (define_split | |
1718 | [(set (match_operand:BI 0 "register_operand" "") | |
1719 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1720 | (const_int 0)) | |
1721 | (match_operand:DI 3 "register_operand" "")) | |
1722 | (const_int 0)))] | |
1723 | "" | |
1724 | [(set (match_dup 0) | |
1725 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1726 | (match_dup 2)))] | |
1727 | "") | |
1728 | ||
1729 | (define_split | |
1730 | [(set (match_operand:BI 0 "register_operand" "") | |
1731 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1732 | (const_int 0)) | |
1733 | (match_operand:DI 3 "register_operand" "")) | |
1734 | (const_int 0)))] | |
1735 | "" | |
1736 | [(set (match_dup 0) | |
1737 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1738 | (match_dup 2))) | |
1739 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1740 | (clobber (scratch))])] | |
1741 | "") | |
1742 | ||
1743 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1744 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1745 | ;; nothing bad happens to the comparisons in the meantime. | |
1746 | ;; | |
1747 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1748 | ;; that we're doing height reduction. | |
1749 | ; | |
1750 | ;(define_insn_and_split "" | |
1751 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1752 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1753 | ; [(match_operand 2 "" "") | |
1754 | ; (match_operand 3 "" "")]) | |
1755 | ; (match_operator:BI 4 "comparison_operator" | |
1756 | ; [(match_operand 5 "" "") | |
1757 | ; (match_operand 6 "" "")])) | |
1758 | ; (match_dup 0)))] | |
1759 | ; "flag_schedule_insns" | |
1760 | ; "#" | |
1761 | ; "" | |
1762 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1763 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1764 | ; "") | |
1765 | ; | |
1766 | ;(define_insn_and_split "" | |
1767 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1768 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1769 | ; [(match_operand 2 "" "") | |
1770 | ; (match_operand 3 "" "")]) | |
1771 | ; (match_operator:BI 4 "comparison_operator" | |
1772 | ; [(match_operand 5 "" "") | |
1773 | ; (match_operand 6 "" "")])) | |
1774 | ; (match_dup 0)))] | |
1775 | ; "flag_schedule_insns" | |
1776 | ; "#" | |
1777 | ; "" | |
1778 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1779 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1780 | ; "") | |
1781 | ; | |
1782 | ;(define_split | |
1783 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1784 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1785 | ; [(match_operand 2 "" "") | |
1786 | ; (match_operand 3 "" "")]) | |
1787 | ; (match_operand:BI 7 "register_operand" "")) | |
1788 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1789 | ; [(match_operand 5 "" "") | |
1790 | ; (match_operand 6 "" "")]) | |
1791 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1792 | ; "" | |
1793 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1794 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1795 | ; (match_dup 0)))] | |
1796 | ; "") | |
1797 | ; | |
1798 | ;(define_split | |
1799 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1800 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1801 | ; [(match_operand 2 "" "") | |
1802 | ; (match_operand 3 "" "")]) | |
1803 | ; (match_operand:BI 7 "register_operand" "")) | |
1804 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1805 | ; [(match_operand 5 "" "") | |
1806 | ; (match_operand 6 "" "")]) | |
1807 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1808 | ; "" | |
1809 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1810 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1811 | ; (match_dup 0)))] | |
1812 | ; "") | |
1813 | ||
1814 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1815 | ;; Note that we'll have already split the predicate copy, which | |
1816 | ;; is kind of a pain, but oh well. | |
1817 | ||
1818 | (define_peephole2 | |
1819 | [(set (match_operand:BI 0 "register_operand" "") | |
1820 | (match_operand:BI 1 "comparison_operator" "")) | |
1821 | (set (match_operand:CCI 2 "register_operand" "") | |
1822 | (match_operand:CCI 3 "register_operand" "")) | |
1823 | (set (match_operand:CCI 4 "register_operand" "") | |
1824 | (match_operand:CCI 5 "register_operand" "")) | |
1825 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1826 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1827 | "REGNO (operands[3]) == REGNO (operands[0]) |
1828 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1829 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1830 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1831 | [(set (match_dup 0) (match_dup 1)) | |
1832 | (set (match_dup 6) (match_dup 7))] | |
1833 | "operands[7] = copy_rtx (operands[1]);") | |
1834 | \f | |
1835 | ;; :::::::::::::::::::: | |
1836 | ;; :: | |
cf1f6ae3 RH |
1837 | ;; :: 16 bit Integer arithmetic |
1838 | ;; :: | |
1839 | ;; :::::::::::::::::::: | |
1840 | ||
1841 | (define_insn "mulhi3" | |
1842 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1843 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1844 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1845 | "" | |
2a7ffc85 | 1846 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1847 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1848 | |
1849 | \f | |
1850 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1851 | ;; :: |
1852 | ;; :: 32 bit Integer arithmetic | |
1853 | ;; :: | |
1854 | ;; :::::::::::::::::::: | |
1855 | ||
058557c4 | 1856 | (define_insn "addsi3" |
0551c32d RH |
1857 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1858 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1859 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1860 | "" |
1861 | "@ | |
1d5d7a21 RH |
1862 | add %0 = %1, %2 |
1863 | adds %0 = %2, %1 | |
1864 | addl %0 = %2, %1" | |
52e12ad0 | 1865 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1866 | |
1867 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1868 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1869 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1870 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1871 | (const_int 1)))] |
1872 | "" | |
1873 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1874 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1875 | |
5527bf14 | 1876 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1877 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1878 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1879 | (const_int 2)) |
1880 | (const_int 1)))] | |
1881 | "" | |
1882 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1883 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1884 | |
058557c4 | 1885 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1886 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1887 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1888 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1889 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1890 | "" |
058557c4 | 1891 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1892 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1893 | |
058557c4 | 1894 | (define_insn "subsi3" |
0551c32d RH |
1895 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1896 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1897 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1898 | "" |
1899 | "sub %0 = %1, %2" | |
52e12ad0 | 1900 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1901 | |
1902 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1903 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1904 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1905 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1906 | "" |
1907 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1908 | [(set_attr "itanium_class" "ialu")]) |
1909 | ||
1910 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1911 | |
058557c4 | 1912 | (define_insn "mulsi3" |
0551c32d | 1913 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1914 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1915 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1916 | "" |
aebf2462 | 1917 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1918 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1919 | |
655f2eb9 | 1920 | (define_insn "maddsi4" |
11a13704 RH |
1921 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1922 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1923 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1924 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1925 | "" | |
aebf2462 | 1926 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1927 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1928 | |
058557c4 | 1929 | (define_insn "negsi2" |
0551c32d RH |
1930 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1931 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1932 | "" |
1933 | "sub %0 = r0, %1" | |
52e12ad0 | 1934 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1935 | |
1936 | (define_expand "abssi2" | |
1937 | [(set (match_dup 2) | |
f2f90c63 | 1938 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1939 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1940 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1941 | (neg:SI (match_dup 1)) |
1942 | (match_dup 1)))] | |
c65ebc55 | 1943 | "" |
1d5d7a21 | 1944 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1945 | |
1946 | (define_expand "sminsi3" | |
1947 | [(set (match_dup 3) | |
f2f90c63 | 1948 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1949 | (match_operand:SI 2 "gr_register_operand" ""))) |
1950 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1951 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1952 | (match_dup 2) (match_dup 1)))] |
1953 | "" | |
1d5d7a21 | 1954 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1955 | |
1956 | (define_expand "smaxsi3" | |
1957 | [(set (match_dup 3) | |
f2f90c63 | 1958 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1959 | (match_operand:SI 2 "gr_register_operand" ""))) |
1960 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1961 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1962 | (match_dup 1) (match_dup 2)))] |
1963 | "" | |
1d5d7a21 | 1964 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1965 | |
1966 | (define_expand "uminsi3" | |
1967 | [(set (match_dup 3) | |
f2f90c63 | 1968 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1969 | (match_operand:SI 2 "gr_register_operand" ""))) |
1970 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1971 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1972 | (match_dup 2) (match_dup 1)))] |
1973 | "" | |
1d5d7a21 | 1974 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1975 | |
1976 | (define_expand "umaxsi3" | |
1977 | [(set (match_dup 3) | |
f2f90c63 | 1978 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1979 | (match_operand:SI 2 "gr_register_operand" ""))) |
1980 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1981 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1982 | (match_dup 1) (match_dup 2)))] |
1983 | "" | |
1d5d7a21 | 1984 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 1985 | |
655f2eb9 RH |
1986 | (define_expand "divsi3" |
1987 | [(set (match_operand:SI 0 "register_operand" "") | |
1988 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1989 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1990 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1991 | { |
1992 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1993 | ||
1994 | op0_tf = gen_reg_rtx (TFmode); | |
1995 | op0_di = gen_reg_rtx (DImode); | |
1996 | ||
1997 | if (CONSTANT_P (operands[1])) | |
1998 | operands[1] = force_reg (SImode, operands[1]); | |
1999 | op1_tf = gen_reg_rtx (TFmode); | |
2000 | expand_float (op1_tf, operands[1], 0); | |
2001 | ||
2002 | if (CONSTANT_P (operands[2])) | |
2003 | operands[2] = force_reg (SImode, operands[2]); | |
2004 | op2_tf = gen_reg_rtx (TFmode); | |
2005 | expand_float (op2_tf, operands[2], 0); | |
2006 | ||
2007 | /* 2^-34 */ | |
2008 | #if 0 | |
2009 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
2010 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
2011 | twon34 = force_reg (TFmode, twon34); | |
2012 | #else | |
2013 | twon34 = gen_reg_rtx (TFmode); | |
2014 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
2015 | #endif | |
2016 | ||
2017 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
2018 | ||
2019 | emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
2020 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
2021 | DONE; | |
1d5d7a21 | 2022 | }) |
655f2eb9 RH |
2023 | |
2024 | (define_expand "modsi3" | |
2025 | [(set (match_operand:SI 0 "register_operand" "") | |
2026 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2027 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2028 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2029 | { |
2030 | rtx op2_neg, op1_di, div; | |
2031 | ||
2032 | div = gen_reg_rtx (SImode); | |
2033 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2034 | ||
2035 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2036 | ||
2037 | /* This is a trick to get us to reuse the value that we're sure to | |
2038 | have already copied to the FP regs. */ | |
2039 | op1_di = gen_reg_rtx (DImode); | |
2040 | convert_move (op1_di, operands[1], 0); | |
2041 | ||
2042 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2043 | gen_lowpart (SImode, op1_di))); | |
2044 | DONE; | |
1d5d7a21 | 2045 | }) |
655f2eb9 RH |
2046 | |
2047 | (define_expand "udivsi3" | |
2048 | [(set (match_operand:SI 0 "register_operand" "") | |
2049 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2050 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2051 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2052 | { |
2053 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
2054 | ||
2055 | op0_tf = gen_reg_rtx (TFmode); | |
2056 | op0_di = gen_reg_rtx (DImode); | |
2057 | ||
2058 | if (CONSTANT_P (operands[1])) | |
2059 | operands[1] = force_reg (SImode, operands[1]); | |
2060 | op1_tf = gen_reg_rtx (TFmode); | |
2061 | expand_float (op1_tf, operands[1], 1); | |
2062 | ||
2063 | if (CONSTANT_P (operands[2])) | |
2064 | operands[2] = force_reg (SImode, operands[2]); | |
2065 | op2_tf = gen_reg_rtx (TFmode); | |
2066 | expand_float (op2_tf, operands[2], 1); | |
2067 | ||
2068 | /* 2^-34 */ | |
2069 | #if 0 | |
2070 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
2071 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
2072 | twon34 = force_reg (TFmode, twon34); | |
2073 | #else | |
2074 | twon34 = gen_reg_rtx (TFmode); | |
2075 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
2076 | #endif | |
2077 | ||
2078 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
2079 | ||
2080 | emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
2081 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
2082 | DONE; | |
1d5d7a21 | 2083 | }) |
655f2eb9 RH |
2084 | |
2085 | (define_expand "umodsi3" | |
2086 | [(set (match_operand:SI 0 "register_operand" "") | |
2087 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2088 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2089 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2090 | { |
2091 | rtx op2_neg, op1_di, div; | |
2092 | ||
2093 | div = gen_reg_rtx (SImode); | |
2094 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2095 | ||
2096 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2097 | ||
2098 | /* This is a trick to get us to reuse the value that we're sure to | |
2099 | have already copied to the FP regs. */ | |
2100 | op1_di = gen_reg_rtx (DImode); | |
2101 | convert_move (op1_di, operands[1], 1); | |
2102 | ||
2103 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2104 | gen_lowpart (SImode, op1_di))); | |
2105 | DONE; | |
1d5d7a21 | 2106 | }) |
655f2eb9 RH |
2107 | |
2108 | (define_insn_and_split "divsi3_internal" | |
2109 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2110 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2111 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2112 | (clobber (match_scratch:TF 4 "=&f")) | |
2113 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2114 | (clobber (match_scratch:BI 6 "=c")) |
655f2eb9 | 2115 | (use (match_operand:TF 3 "fr_register_operand" "f"))] |
23c108af | 2116 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2117 | "#" |
2118 | "&& reload_completed" | |
2119 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2120 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2121 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2122 | (use (const_int 1))]) |
2123 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2124 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2125 | (use (const_int 1))])) | |
2126 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2127 | (parallel [(set (match_dup 5) | |
2128 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2129 | (match_dup 7))) | |
2130 | (use (const_int 1))])) | |
2131 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2132 | (parallel [(set (match_dup 4) | |
2133 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2134 | (match_dup 4))) | |
2135 | (use (const_int 1))])) | |
2136 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2137 | (parallel [(set (match_dup 5) | |
2138 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
2139 | (match_dup 3))) | |
2140 | (use (const_int 1))])) | |
2141 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2142 | (parallel [(set (match_dup 0) | |
2143 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2144 | (match_dup 4))) | |
2145 | (use (const_int 1))])) | |
2146 | ] | |
2147 | "operands[7] = CONST1_RTX (TFmode);" | |
2148 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2149 | \f |
2150 | ;; :::::::::::::::::::: | |
2151 | ;; :: | |
2152 | ;; :: 64 bit Integer arithmetic | |
2153 | ;; :: | |
2154 | ;; :::::::::::::::::::: | |
2155 | ||
2156 | (define_insn "adddi3" | |
0551c32d RH |
2157 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2158 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2159 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2160 | "" |
2161 | "@ | |
1d5d7a21 RH |
2162 | add %0 = %1, %2 |
2163 | adds %0 = %2, %1 | |
2164 | addl %0 = %2, %1" | |
52e12ad0 | 2165 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2166 | |
2167 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2168 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2169 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2170 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2171 | (const_int 1)))] |
2172 | "" | |
2173 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2174 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2175 | |
5527bf14 RH |
2176 | ;; This has some of the same problems as shladd. We let the shladd |
2177 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2178 | ;; a register, but not more ugliness here. | |
2179 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2180 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2181 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2182 | (const_int 2)) |
2183 | (const_int 1)))] | |
2184 | "" | |
2185 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2186 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2187 | |
c65ebc55 | 2188 | (define_insn "subdi3" |
0551c32d RH |
2189 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2190 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2191 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2192 | "" |
2193 | "sub %0 = %1, %2" | |
52e12ad0 | 2194 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2195 | |
2196 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2197 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2198 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2199 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2200 | "" |
2201 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2202 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2203 | |
cee58bc0 RH |
2204 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2205 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2206 | (define_insn "muldi3" |
0551c32d | 2207 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2208 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2209 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2210 | "" |
aebf2462 | 2211 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2212 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2213 | |
2214 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2215 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2216 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2217 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2218 | ;; here so that it will be present just in case register elimination gives us | |
2219 | ;; the funny result. | |
2220 | ||
2221 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2222 | ||
2223 | ;; ??? Maybe we should change how adds are canonicalized. | |
2224 | ||
655f2eb9 | 2225 | (define_insn "madddi4" |
0551c32d | 2226 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2227 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2228 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2229 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2230 | (clobber (match_scratch:DI 4 "=X"))] |
2231 | "" | |
aebf2462 | 2232 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2233 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2234 | |
2235 | ;; This can be created by register elimination if operand3 of shladd is an | |
2236 | ;; eliminable register or has reg_equiv_constant set. | |
2237 | ||
2238 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2239 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2240 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2241 | ;; incorrectly. |
2242 | ||
655f2eb9 | 2243 | (define_insn "*madddi4_elim" |
c65ebc55 | 2244 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2245 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2246 | (match_operand:DI 2 "register_operand" "f")) | |
2247 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2248 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2249 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2250 | "reload_in_progress" |
2251 | "#" | |
52e12ad0 | 2252 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2253 | |
c65ebc55 JW |
2254 | (define_split |
2255 | [(set (match_operand:DI 0 "register_operand" "") | |
2256 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2257 | (match_operand:DI 2 "register_operand" "")) | |
2258 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2259 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2260 | (clobber (match_scratch:DI 5 ""))] |
2261 | "reload_completed" | |
2262 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2263 | (match_dup 3))) | |
2264 | (clobber (match_dup 0))]) | |
c65ebc55 | 2265 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2266 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2267 | "") | |
2268 | ||
2269 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2270 | ;; to generate them. | |
2271 | ||
2272 | (define_insn "smuldi3_highpart" | |
0551c32d | 2273 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2274 | (truncate:DI |
2275 | (lshiftrt:TI | |
0551c32d RH |
2276 | (mult:TI (sign_extend:TI |
2277 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2278 | (sign_extend:TI | |
2279 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2280 | (const_int 64))))] |
2281 | "" | |
aebf2462 | 2282 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2283 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2284 | |
2285 | (define_insn "umuldi3_highpart" | |
0551c32d | 2286 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2287 | (truncate:DI |
2288 | (lshiftrt:TI | |
0551c32d RH |
2289 | (mult:TI (zero_extend:TI |
2290 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2291 | (zero_extend:TI | |
2292 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2293 | (const_int 64))))] |
2294 | "" | |
aebf2462 | 2295 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2296 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2297 | |
2298 | (define_insn "negdi2" | |
0551c32d RH |
2299 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2300 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2301 | "" |
2302 | "sub %0 = r0, %1" | |
52e12ad0 | 2303 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2304 | |
2305 | (define_expand "absdi2" | |
2306 | [(set (match_dup 2) | |
f2f90c63 | 2307 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2308 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2309 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2310 | (neg:DI (match_dup 1)) |
2311 | (match_dup 1)))] | |
c65ebc55 | 2312 | "" |
1d5d7a21 | 2313 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2314 | |
2315 | (define_expand "smindi3" | |
2316 | [(set (match_dup 3) | |
f2f90c63 | 2317 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2318 | (match_operand:DI 2 "gr_register_operand" ""))) |
2319 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2320 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2321 | (match_dup 2) (match_dup 1)))] |
2322 | "" | |
1d5d7a21 | 2323 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2324 | |
2325 | (define_expand "smaxdi3" | |
2326 | [(set (match_dup 3) | |
f2f90c63 | 2327 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2328 | (match_operand:DI 2 "gr_register_operand" ""))) |
2329 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2330 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2331 | (match_dup 1) (match_dup 2)))] |
2332 | "" | |
1d5d7a21 | 2333 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2334 | |
2335 | (define_expand "umindi3" | |
2336 | [(set (match_dup 3) | |
f2f90c63 | 2337 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2338 | (match_operand:DI 2 "gr_register_operand" ""))) |
2339 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2340 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2341 | (match_dup 2) (match_dup 1)))] |
2342 | "" | |
1d5d7a21 | 2343 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2344 | |
2345 | (define_expand "umaxdi3" | |
2346 | [(set (match_dup 3) | |
f2f90c63 | 2347 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2348 | (match_operand:DI 2 "gr_register_operand" ""))) |
2349 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2350 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2351 | (match_dup 1) (match_dup 2)))] |
2352 | "" | |
1d5d7a21 | 2353 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2354 | |
2355 | (define_expand "ffsdi2" | |
2356 | [(set (match_dup 6) | |
f2f90c63 | 2357 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2358 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2359 | (set (match_dup 5) (const_int 0)) | |
2360 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
086c0f96 | 2361 | (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_POPCNT)) |
0551c32d | 2362 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2363 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2364 | (match_dup 5) (match_dup 4)))] |
2365 | "" | |
c65ebc55 JW |
2366 | { |
2367 | operands[2] = gen_reg_rtx (DImode); | |
2368 | operands[3] = gen_reg_rtx (DImode); | |
2369 | operands[4] = gen_reg_rtx (DImode); | |
2370 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2371 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2372 | }) |
c65ebc55 JW |
2373 | |
2374 | (define_insn "*popcnt" | |
0551c32d | 2375 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
086c0f96 RH |
2376 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] |
2377 | UNSPEC_POPCNT))] | |
c65ebc55 JW |
2378 | "" |
2379 | "popcnt %0 = %1" | |
52e12ad0 | 2380 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2381 | |
655f2eb9 RH |
2382 | (define_expand "divdi3" |
2383 | [(set (match_operand:DI 0 "register_operand" "") | |
2384 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2385 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2386 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2387 | { |
2388 | rtx op1_tf, op2_tf, op0_tf; | |
2389 | ||
2390 | op0_tf = gen_reg_rtx (TFmode); | |
2391 | ||
2392 | if (CONSTANT_P (operands[1])) | |
2393 | operands[1] = force_reg (DImode, operands[1]); | |
2394 | op1_tf = gen_reg_rtx (TFmode); | |
2395 | expand_float (op1_tf, operands[1], 0); | |
2396 | ||
2397 | if (CONSTANT_P (operands[2])) | |
2398 | operands[2] = force_reg (DImode, operands[2]); | |
2399 | op2_tf = gen_reg_rtx (TFmode); | |
2400 | expand_float (op2_tf, operands[2], 0); | |
2401 | ||
2402 | if (TARGET_INLINE_DIV_LAT) | |
2403 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2404 | else | |
2405 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2406 | ||
2407 | emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2408 | DONE; | |
1d5d7a21 | 2409 | }) |
655f2eb9 RH |
2410 | |
2411 | (define_expand "moddi3" | |
2412 | [(set (match_operand:DI 0 "register_operand" "") | |
2413 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2414 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2415 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2416 | { |
2417 | rtx op2_neg, div; | |
2418 | ||
2419 | div = gen_reg_rtx (DImode); | |
2420 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2421 | ||
2422 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2423 | ||
2424 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2425 | DONE; | |
1d5d7a21 | 2426 | }) |
655f2eb9 RH |
2427 | |
2428 | (define_expand "udivdi3" | |
2429 | [(set (match_operand:DI 0 "register_operand" "") | |
2430 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2431 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2432 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2433 | { |
2434 | rtx op1_tf, op2_tf, op0_tf; | |
2435 | ||
2436 | op0_tf = gen_reg_rtx (TFmode); | |
2437 | ||
2438 | if (CONSTANT_P (operands[1])) | |
2439 | operands[1] = force_reg (DImode, operands[1]); | |
2440 | op1_tf = gen_reg_rtx (TFmode); | |
2441 | expand_float (op1_tf, operands[1], 1); | |
2442 | ||
2443 | if (CONSTANT_P (operands[2])) | |
2444 | operands[2] = force_reg (DImode, operands[2]); | |
2445 | op2_tf = gen_reg_rtx (TFmode); | |
2446 | expand_float (op2_tf, operands[2], 1); | |
2447 | ||
2448 | if (TARGET_INLINE_DIV_LAT) | |
2449 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2450 | else | |
2451 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2452 | ||
2453 | emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2454 | DONE; | |
1d5d7a21 | 2455 | }) |
655f2eb9 RH |
2456 | |
2457 | (define_expand "umoddi3" | |
2458 | [(set (match_operand:DI 0 "register_operand" "") | |
2459 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2460 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2461 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2462 | { |
2463 | rtx op2_neg, div; | |
2464 | ||
2465 | div = gen_reg_rtx (DImode); | |
2466 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2467 | ||
2468 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2469 | ||
2470 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2471 | DONE; | |
1d5d7a21 | 2472 | }) |
655f2eb9 RH |
2473 | |
2474 | (define_insn_and_split "divdi3_internal_lat" | |
2475 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2476 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2477 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2478 | (clobber (match_scratch:TF 3 "=&f")) | |
2479 | (clobber (match_scratch:TF 4 "=&f")) | |
2480 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2481 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2482 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
655f2eb9 RH |
2483 | "#" |
2484 | "&& reload_completed" | |
2485 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2486 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2487 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2488 | (use (const_int 1))]) |
2489 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2490 | (parallel [(set (match_dup 3) | |
2491 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2492 | (match_dup 7))) | |
2493 | (use (const_int 1))])) | |
2494 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2495 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2496 | (use (const_int 1))])) | |
2497 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2498 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
2499 | (use (const_int 1))])) | |
2500 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2501 | (parallel [(set (match_dup 4) | |
2502 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
2503 | (match_dup 4))) | |
2504 | (use (const_int 1))])) | |
2505 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2506 | (parallel [(set (match_dup 0) | |
2507 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2508 | (match_dup 0))) | |
2509 | (use (const_int 1))])) | |
2510 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2511 | (parallel [(set (match_dup 3) | |
2512 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2513 | (match_dup 4))) | |
2514 | (use (const_int 1))])) | |
2515 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2516 | (parallel [(set (match_dup 0) | |
2517 | (plus:TF (mult:TF (match_dup 5) (match_dup 0)) | |
2518 | (match_dup 0))) | |
2519 | (use (const_int 1))])) | |
2520 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2521 | (parallel [(set (match_dup 4) | |
2522 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2523 | (match_dup 1))) | |
2524 | (use (const_int 1))])) | |
2525 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2526 | (parallel [(set (match_dup 0) | |
2527 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2528 | (match_dup 3))) | |
2529 | (use (const_int 1))])) | |
2530 | ] | |
2531 | "operands[7] = CONST1_RTX (TFmode);" | |
2532 | [(set_attr "predicable" "no")]) | |
2533 | ||
2534 | (define_insn_and_split "divdi3_internal_thr" | |
2535 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2536 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2537 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2538 | (clobber (match_scratch:TF 3 "=&f")) | |
2539 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2540 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2541 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
655f2eb9 RH |
2542 | "#" |
2543 | "&& reload_completed" | |
2544 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2545 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2546 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2547 | (use (const_int 1))]) |
2548 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2549 | (parallel [(set (match_dup 3) | |
2550 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2551 | (match_dup 6))) | |
2552 | (use (const_int 1))])) | |
2553 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2554 | (parallel [(set (match_dup 0) | |
2555 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2556 | (match_dup 0))) | |
2557 | (use (const_int 1))])) | |
2558 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2559 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
2560 | (use (const_int 1))])) | |
2561 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2562 | (parallel [(set (match_dup 0) | |
2563 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2564 | (match_dup 0))) | |
2565 | (use (const_int 1))])) | |
2566 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2567 | (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1))) | |
2568 | (use (const_int 1))])) | |
2569 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2570 | (parallel [(set (match_dup 4) | |
2571 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2572 | (match_dup 1))) | |
2573 | (use (const_int 1))])) | |
2574 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2575 | (parallel [(set (match_dup 0) | |
2576 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2577 | (match_dup 3))) | |
2578 | (use (const_int 1))])) | |
2579 | ] | |
2580 | "operands[6] = CONST1_RTX (TFmode);" | |
2581 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2582 | \f |
2583 | ;; :::::::::::::::::::: | |
2584 | ;; :: | |
2585 | ;; :: 32 bit floating point arithmetic | |
2586 | ;; :: | |
2587 | ;; :::::::::::::::::::: | |
2588 | ||
2589 | (define_insn "addsf3" | |
0551c32d RH |
2590 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2591 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2592 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2593 | "" |
aebf2462 | 2594 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2595 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2596 | |
2597 | (define_insn "subsf3" | |
0551c32d RH |
2598 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2599 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2600 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2601 | "" |
aebf2462 | 2602 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2603 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2604 | |
2605 | (define_insn "mulsf3" | |
0551c32d RH |
2606 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2607 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2608 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2609 | "" |
aebf2462 | 2610 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2611 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2612 | |
2613 | (define_insn "abssf2" | |
0551c32d RH |
2614 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2615 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2616 | "" |
aebf2462 | 2617 | "fabs %0 = %1" |
52e12ad0 | 2618 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2619 | |
2620 | (define_insn "negsf2" | |
0551c32d RH |
2621 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2622 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2623 | "" |
aebf2462 | 2624 | "fneg %0 = %1" |
52e12ad0 | 2625 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2626 | |
2627 | (define_insn "*nabssf2" | |
0551c32d RH |
2628 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2629 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2630 | "" |
aebf2462 | 2631 | "fnegabs %0 = %1" |
52e12ad0 | 2632 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2633 | |
2634 | (define_insn "minsf3" | |
0551c32d RH |
2635 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2636 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2637 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2638 | "" |
aebf2462 | 2639 | "fmin %0 = %1, %F2" |
52e12ad0 | 2640 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2641 | |
2642 | (define_insn "maxsf3" | |
0551c32d RH |
2643 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2644 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2645 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2646 | "" |
aebf2462 | 2647 | "fmax %0 = %1, %F2" |
52e12ad0 | 2648 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2649 | |
655f2eb9 | 2650 | (define_insn "*maddsf4" |
0551c32d RH |
2651 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2652 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2653 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2654 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2655 | "" |
aebf2462 | 2656 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2657 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2658 | |
655f2eb9 | 2659 | (define_insn "*msubsf4" |
0551c32d RH |
2660 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2661 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2662 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2663 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2664 | "" |
aebf2462 | 2665 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2666 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2667 | |
2668 | (define_insn "*nmulsf3" | |
0551c32d RH |
2669 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2670 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2671 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2672 | "" |
aebf2462 | 2673 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2674 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2675 | |
2676 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? | |
2677 | ||
655f2eb9 | 2678 | (define_insn "*nmaddsf4" |
0551c32d | 2679 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
26102535 RH |
2680 | (plus:SF (neg:SF (mult:SF |
2681 | (match_operand:SF 1 "fr_register_operand" "f") | |
2682 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
0551c32d | 2683 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2684 | "" |
aebf2462 | 2685 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2686 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2687 | |
26102535 RH |
2688 | (define_expand "divsf3" |
2689 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2690 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2691 | (match_operand:SF 2 "fr_register_operand" "")))] | |
23c108af | 2692 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2693 | { |
2694 | rtx insn; | |
2695 | if (TARGET_INLINE_DIV_LAT) | |
2696 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); | |
2697 | else | |
2698 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2699 | emit_insn (insn); | |
2700 | DONE; | |
1d5d7a21 | 2701 | }) |
26102535 RH |
2702 | |
2703 | (define_insn_and_split "divsf3_internal_lat" | |
2704 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2705 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2706 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2707 | (clobber (match_scratch:TF 3 "=&f")) | |
2708 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2709 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2710 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2711 | "#" |
2712 | "&& reload_completed" | |
2713 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
2714 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2715 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
2716 | (use (const_int 1))]) |
2717 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2718 | (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) | |
2719 | (use (const_int 1))])) | |
2720 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2721 | (parallel [(set (match_dup 4) | |
2722 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2723 | (match_dup 10))) | |
2724 | (use (const_int 1))])) | |
2725 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2726 | (parallel [(set (match_dup 3) | |
2727 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2728 | (match_dup 3))) | |
2729 | (use (const_int 1))])) | |
2730 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2731 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2732 | (use (const_int 1))])) | |
2733 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2734 | (parallel [(set (match_dup 3) | |
2735 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2736 | (match_dup 3))) | |
2737 | (use (const_int 1))])) | |
2738 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2739 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2740 | (use (const_int 1))])) | |
2741 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2742 | (parallel [(set (match_dup 9) | |
2743 | (float_truncate:DF | |
2744 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2745 | (match_dup 3)))) | |
2746 | (use (const_int 1))])) | |
2747 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2748 | (set (match_dup 0) | |
2749 | (float_truncate:SF (match_dup 6)))) | |
2750 | ] | |
1d5d7a21 RH |
2751 | { |
2752 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2753 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2754 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2755 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); | |
2756 | operands[10] = CONST1_RTX (TFmode); | |
2757 | } | |
26102535 RH |
2758 | [(set_attr "predicable" "no")]) |
2759 | ||
2760 | (define_insn_and_split "divsf3_internal_thr" | |
2761 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2762 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2763 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2764 | (clobber (match_scratch:TF 3 "=&f")) | |
2765 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2766 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2767 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2768 | "#" |
2769 | "&& reload_completed" | |
2770 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
2771 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2772 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
2773 | (use (const_int 1))]) |
2774 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2775 | (parallel [(set (match_dup 3) | |
2776 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2777 | (match_dup 10))) | |
2778 | (use (const_int 1))])) | |
2779 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2780 | (parallel [(set (match_dup 3) | |
2781 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
2782 | (match_dup 3))) | |
2783 | (use (const_int 1))])) | |
2784 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2785 | (parallel [(set (match_dup 6) | |
2786 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
2787 | (match_dup 6))) | |
2788 | (use (const_int 1))])) | |
2789 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2790 | (parallel [(set (match_dup 9) | |
2791 | (float_truncate:SF | |
2792 | (mult:TF (match_dup 7) (match_dup 6)))) | |
2793 | (use (const_int 1))])) | |
2794 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2795 | (parallel [(set (match_dup 4) | |
2796 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3))) | |
2797 | (match_dup 7))) | |
2798 | (use (const_int 1))])) | |
2799 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2800 | (set (match_dup 0) | |
2801 | (float_truncate:SF | |
2802 | (plus:TF (mult:TF (match_dup 4) (match_dup 6)) | |
2803 | (match_dup 3))))) | |
2804 | ] | |
1d5d7a21 RH |
2805 | { |
2806 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2807 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2808 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2809 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); | |
2810 | operands[10] = CONST1_RTX (TFmode); | |
2811 | } | |
26102535 | 2812 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2813 | \f |
2814 | ;; :::::::::::::::::::: | |
2815 | ;; :: | |
2816 | ;; :: 64 bit floating point arithmetic | |
2817 | ;; :: | |
2818 | ;; :::::::::::::::::::: | |
2819 | ||
2820 | (define_insn "adddf3" | |
0551c32d RH |
2821 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2822 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2823 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2824 | "" |
aebf2462 | 2825 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2826 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2827 | |
26102535 RH |
2828 | (define_insn "*adddf3_trunc" |
2829 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2830 | (float_truncate:SF | |
2831 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2832 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2833 | "" | |
aebf2462 | 2834 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2835 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2836 | |
c65ebc55 | 2837 | (define_insn "subdf3" |
0551c32d RH |
2838 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2839 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2840 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2841 | "" |
aebf2462 | 2842 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2843 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2844 | |
26102535 RH |
2845 | (define_insn "*subdf3_trunc" |
2846 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2847 | (float_truncate:SF | |
2848 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2849 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2850 | "" | |
aebf2462 | 2851 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2852 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2853 | |
c65ebc55 | 2854 | (define_insn "muldf3" |
0551c32d RH |
2855 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2856 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2857 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2858 | "" |
aebf2462 | 2859 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2860 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2861 | |
26102535 RH |
2862 | (define_insn "*muldf3_trunc" |
2863 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2864 | (float_truncate:SF | |
2865 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2866 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2867 | "" | |
aebf2462 | 2868 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2869 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2870 | |
c65ebc55 | 2871 | (define_insn "absdf2" |
0551c32d RH |
2872 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2873 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2874 | "" |
aebf2462 | 2875 | "fabs %0 = %1" |
52e12ad0 | 2876 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2877 | |
2878 | (define_insn "negdf2" | |
0551c32d RH |
2879 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2880 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2881 | "" |
aebf2462 | 2882 | "fneg %0 = %1" |
52e12ad0 | 2883 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2884 | |
2885 | (define_insn "*nabsdf2" | |
0551c32d RH |
2886 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2887 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2888 | "" |
aebf2462 | 2889 | "fnegabs %0 = %1" |
52e12ad0 | 2890 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2891 | |
2892 | (define_insn "mindf3" | |
0551c32d RH |
2893 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2894 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2895 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2896 | "" |
aebf2462 | 2897 | "fmin %0 = %1, %F2" |
52e12ad0 | 2898 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2899 | |
2900 | (define_insn "maxdf3" | |
0551c32d RH |
2901 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2902 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2903 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2904 | "" |
aebf2462 | 2905 | "fmax %0 = %1, %F2" |
52e12ad0 | 2906 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2907 | |
655f2eb9 | 2908 | (define_insn "*madddf4" |
0551c32d RH |
2909 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2910 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2911 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2912 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2913 | "" |
aebf2462 | 2914 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 2915 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2916 | |
26102535 RH |
2917 | (define_insn "*madddf4_trunc" |
2918 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2919 | (float_truncate:SF | |
2920 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2921 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2922 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2923 | "" | |
aebf2462 | 2924 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2925 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2926 | |
655f2eb9 | 2927 | (define_insn "*msubdf4" |
0551c32d RH |
2928 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2929 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2930 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2931 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2932 | "" |
aebf2462 | 2933 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 2934 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2935 | |
26102535 RH |
2936 | (define_insn "*msubdf4_trunc" |
2937 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2938 | (float_truncate:SF | |
2939 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2940 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2941 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2942 | "" | |
aebf2462 | 2943 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2944 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2945 | |
c65ebc55 | 2946 | (define_insn "*nmuldf3" |
0551c32d RH |
2947 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2948 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2949 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2950 | "" |
aebf2462 | 2951 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 2952 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2953 | |
26102535 RH |
2954 | (define_insn "*nmuldf3_trunc" |
2955 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2956 | (float_truncate:SF | |
2957 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2958 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
2959 | "" | |
aebf2462 | 2960 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2961 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2962 | |
c65ebc55 JW |
2963 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
2964 | ||
655f2eb9 | 2965 | (define_insn "*nmadddf4" |
0551c32d | 2966 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
26102535 RH |
2967 | (plus:DF (neg:DF (mult:DF |
2968 | (match_operand:DF 1 "fr_register_operand" "f") | |
2969 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
0551c32d | 2970 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2971 | "" |
aebf2462 | 2972 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 2973 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2974 | |
2975 | (define_insn "*nmadddf4_alts" | |
2976 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2977 | (plus:DF (neg:DF (mult:DF | |
2978 | (match_operand:DF 1 "fr_register_operand" "f") | |
2979 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2980 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))) | |
2981 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2982 | "" | |
aebf2462 | 2983 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 2984 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2985 | |
2986 | (define_insn "*nmadddf4_trunc" | |
2987 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2988 | (float_truncate:SF | |
2989 | (plus:DF (neg:DF (mult:DF | |
2990 | (match_operand:DF 1 "fr_register_operand" "f") | |
2991 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2992 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2993 | "" | |
aebf2462 | 2994 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2995 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2996 | |
2997 | (define_expand "divdf3" | |
2998 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
2999 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3000 | (match_operand:DF 2 "fr_register_operand" "")))] | |
23c108af | 3001 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3002 | { |
3003 | rtx insn; | |
3004 | if (TARGET_INLINE_DIV_LAT) | |
3005 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); | |
3006 | else | |
3007 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3008 | emit_insn (insn); | |
3009 | DONE; | |
1d5d7a21 | 3010 | }) |
26102535 RH |
3011 | |
3012 | (define_insn_and_split "divdf3_internal_lat" | |
3013 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3014 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3015 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
3016 | (clobber (match_scratch:TF 3 "=&f")) | |
3017 | (clobber (match_scratch:TF 4 "=&f")) | |
3018 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 3019 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 3020 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3021 | "#" |
3022 | "&& reload_completed" | |
3023 | [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) | |
086c0f96 RH |
3024 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3025 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3026 | (use (const_int 1))]) |
3027 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3028 | (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) | |
3029 | (use (const_int 1))])) | |
3030 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3031 | (parallel [(set (match_dup 4) | |
3032 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7))) | |
3033 | (match_dup 12))) | |
3034 | (use (const_int 1))])) | |
3035 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3036 | (parallel [(set (match_dup 3) | |
3037 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
3038 | (match_dup 3))) | |
3039 | (use (const_int 1))])) | |
3040 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3041 | (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4))) | |
3042 | (use (const_int 1))])) | |
3043 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3044 | (parallel [(set (match_dup 7) | |
3045 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
3046 | (match_dup 7))) | |
3047 | (use (const_int 1))])) | |
3048 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3049 | (parallel [(set (match_dup 3) | |
3050 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3051 | (match_dup 3))) | |
3052 | (use (const_int 1))])) | |
3053 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3054 | (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5))) | |
3055 | (use (const_int 1))])) | |
3056 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3057 | (parallel [(set (match_dup 7) | |
3058 | (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
3059 | (match_dup 7))) | |
3060 | (use (const_int 1))])) | |
3061 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3062 | (parallel [(set (match_dup 10) | |
3063 | (float_truncate:DF | |
3064 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
3065 | (match_dup 3)))) | |
3066 | (use (const_int 1))])) | |
3067 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3068 | (parallel [(set (match_dup 7) | |
3069 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
3070 | (match_dup 7))) | |
3071 | (use (const_int 1))])) | |
3072 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3073 | (parallel [(set (match_dup 11) | |
3074 | (float_truncate:DF | |
3075 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3))) | |
3076 | (match_dup 8)))) | |
3077 | (use (const_int 1))])) | |
3078 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3079 | (set (match_dup 0) | |
3080 | (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
3081 | (match_dup 3))))) | |
3082 | ] | |
1d5d7a21 RH |
3083 | { |
3084 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3085 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3086 | operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3087 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3088 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
3089 | operands[12] = CONST1_RTX (TFmode); | |
3090 | } | |
26102535 RH |
3091 | [(set_attr "predicable" "no")]) |
3092 | ||
3093 | (define_insn_and_split "divdf3_internal_thr" | |
3094 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3095 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3096 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
3097 | (clobber (match_scratch:TF 3 "=&f")) | |
3098 | (clobber (match_scratch:DF 4 "=f")) | |
f2f90c63 | 3099 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3100 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3101 | "#" |
3102 | "&& reload_completed" | |
3103 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
3104 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3105 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3106 | (use (const_int 1))]) |
3107 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3108 | (parallel [(set (match_dup 3) | |
3109 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
3110 | (match_dup 10))) | |
3111 | (use (const_int 1))])) | |
3112 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3113 | (parallel [(set (match_dup 6) | |
3114 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3115 | (match_dup 6))) | |
3116 | (use (const_int 1))])) | |
3117 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3118 | (parallel [(set (match_dup 3) | |
3119 | (mult:TF (match_dup 3) (match_dup 3))) | |
3120 | (use (const_int 1))])) | |
3121 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3122 | (parallel [(set (match_dup 6) | |
3123 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3124 | (match_dup 6))) | |
3125 | (use (const_int 1))])) | |
3126 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3127 | (parallel [(set (match_dup 3) | |
3128 | (mult:TF (match_dup 3) (match_dup 3))) | |
3129 | (use (const_int 1))])) | |
3130 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3131 | (parallel [(set (match_dup 6) | |
3132 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3133 | (match_dup 6))) | |
3134 | (use (const_int 1))])) | |
3135 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3136 | (parallel [(set (match_dup 9) | |
3137 | (float_truncate:DF | |
3138 | (mult:TF (match_dup 7) (match_dup 3)))) | |
3139 | (use (const_int 1))])) | |
3140 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3141 | (parallel [(set (match_dup 4) | |
3142 | (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9))) | |
3143 | (match_dup 1))) | |
3144 | (use (const_int 1))])) | |
3145 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3146 | (set (match_dup 0) | |
3147 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3148 | (match_dup 9)))) | |
3149 | ] | |
1d5d7a21 RH |
3150 | { |
3151 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3152 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3153 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3154 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3155 | operands[10] = CONST1_RTX (TFmode); | |
3156 | } | |
26102535 | 3157 | [(set_attr "predicable" "no")]) |
3f622353 RH |
3158 | \f |
3159 | ;; :::::::::::::::::::: | |
3160 | ;; :: | |
3161 | ;; :: 80 bit floating point arithmetic | |
3162 | ;; :: | |
3163 | ;; :::::::::::::::::::: | |
3164 | ||
3165 | (define_insn "addtf3" | |
0551c32d | 3166 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3167 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3168 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3169 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3170 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3171 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3172 | |
26102535 RH |
3173 | (define_insn "*addtf3_truncsf" |
3174 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3175 | (float_truncate:SF | |
3176 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3177 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3178 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3179 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3180 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3181 | |
3182 | (define_insn "*addtf3_truncdf" | |
3183 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3184 | (float_truncate:DF | |
3185 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3186 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3187 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3188 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3189 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3190 | |
3f622353 | 3191 | (define_insn "subtf3" |
0551c32d | 3192 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3193 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3194 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3195 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3196 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3197 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3198 | |
26102535 RH |
3199 | (define_insn "*subtf3_truncsf" |
3200 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3201 | (float_truncate:SF | |
3202 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3203 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3204 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3205 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3206 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3207 | |
3208 | (define_insn "*subtf3_truncdf" | |
3209 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3210 | (float_truncate:DF | |
3211 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3212 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3213 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3214 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3215 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3216 | |
3f622353 | 3217 | (define_insn "multf3" |
0551c32d | 3218 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3219 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3220 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3221 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3222 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3223 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3224 | |
26102535 RH |
3225 | (define_insn "*multf3_truncsf" |
3226 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3227 | (float_truncate:SF | |
3228 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3229 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3230 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3231 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3232 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3233 | |
3234 | (define_insn "*multf3_truncdf" | |
3235 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3236 | (float_truncate:DF | |
3237 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3238 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3239 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3240 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3241 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3242 | |
655f2eb9 RH |
3243 | (define_insn "*multf3_alts" |
3244 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3245 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3246 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3247 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3248 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3249 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3250 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3251 | |
26102535 RH |
3252 | (define_insn "*multf3_truncsf_alts" |
3253 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3254 | (float_truncate:SF | |
3255 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3256 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3257 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3258 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3259 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3260 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3261 | |
3262 | (define_insn "*multf3_truncdf_alts" | |
3263 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3264 | (float_truncate:DF | |
3265 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3266 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3267 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3268 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3269 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3270 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3271 | |
3f622353 | 3272 | (define_insn "abstf2" |
0551c32d | 3273 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3274 | (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3275 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3276 | "fabs %0 = %F1" |
52e12ad0 | 3277 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3278 | |
3279 | (define_insn "negtf2" | |
0551c32d | 3280 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3281 | (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3282 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3283 | "fneg %0 = %F1" |
52e12ad0 | 3284 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3285 | |
3286 | (define_insn "*nabstf2" | |
0551c32d | 3287 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3288 | (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))] |
23c108af | 3289 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3290 | "fnegabs %0 = %F1" |
52e12ad0 | 3291 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3292 | |
3293 | (define_insn "mintf3" | |
0551c32d | 3294 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3295 | (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3296 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3297 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3298 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3299 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3300 | |
3301 | (define_insn "maxtf3" | |
0551c32d | 3302 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3303 | (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3304 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3305 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3306 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3307 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3308 | |
655f2eb9 | 3309 | (define_insn "*maddtf4" |
0551c32d | 3310 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3311 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3312 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3313 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3314 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3315 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3316 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3317 | |
26102535 RH |
3318 | (define_insn "*maddtf4_truncsf" |
3319 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3320 | (float_truncate:SF | |
3321 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3322 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3323 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3324 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3325 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3326 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3327 | |
3328 | (define_insn "*maddtf4_truncdf" | |
3329 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3330 | (float_truncate:DF | |
3331 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3332 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3333 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3334 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3335 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3336 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3337 | |
655f2eb9 RH |
3338 | (define_insn "*maddtf4_alts" |
3339 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3340 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3341 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3342 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3343 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3344 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3345 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3346 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3347 | |
26102535 RH |
3348 | (define_insn "*maddtf4_alts_truncdf" |
3349 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3350 | (float_truncate:DF | |
3351 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3352 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3353 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3354 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3355 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3356 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3357 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3358 | |
655f2eb9 | 3359 | (define_insn "*msubtf4" |
0551c32d | 3360 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3361 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3362 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3363 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3364 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3365 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3366 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3367 | |
26102535 RH |
3368 | (define_insn "*msubtf4_truncsf" |
3369 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3370 | (float_truncate:SF | |
3371 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3372 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3373 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3374 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3375 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3376 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3377 | |
3378 | (define_insn "*msubtf4_truncdf" | |
3379 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3380 | (float_truncate:DF | |
3381 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3382 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3383 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3384 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3385 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3386 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3387 | |
3f622353 | 3388 | (define_insn "*nmultf3" |
0551c32d | 3389 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3390 | (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3391 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3392 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3393 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3394 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3395 | |
26102535 RH |
3396 | (define_insn "*nmultf3_truncsf" |
3397 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3398 | (float_truncate:SF | |
3399 | (neg:TF (mult:TF | |
3400 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3401 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3402 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3403 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3404 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3405 | |
3406 | (define_insn "*nmultf3_truncdf" | |
3407 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3408 | (float_truncate:DF | |
3409 | (neg:TF (mult:TF | |
3410 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3411 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3412 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3413 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3414 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3415 | |
3f622353 RH |
3416 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
3417 | ||
655f2eb9 | 3418 | (define_insn "*nmaddtf4" |
0551c32d | 3419 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3420 | (plus:TF (neg:TF (mult:TF |
3421 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3422 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3423 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3424 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3425 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3426 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3427 | |
26102535 RH |
3428 | (define_insn "*nmaddtf4_truncsf" |
3429 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3430 | (float_truncate:SF | |
3431 | (plus:TF (neg:TF (mult:TF | |
3432 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3433 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3434 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3435 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3436 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3437 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3438 | |
3439 | (define_insn "*nmaddtf4_truncdf" | |
3440 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3441 | (float_truncate:DF | |
3442 | (plus:TF (neg:TF (mult:TF | |
3443 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3444 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3445 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3446 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3447 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3448 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3449 | |
655f2eb9 RH |
3450 | (define_insn "*nmaddtf4_alts" |
3451 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3452 | (plus:TF (neg:TF (mult:TF | |
3453 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3454 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3455 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3456 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3457 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3458 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3459 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3460 | |
26102535 RH |
3461 | (define_insn "*nmaddtf4_truncdf_alts" |
3462 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3463 | (float_truncate:DF | |
3464 | (plus:TF (neg:TF | |
3465 | (mult:TF | |
3466 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3467 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3468 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3469 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3470 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3471 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3472 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3473 | |
3474 | (define_expand "divtf3" | |
3475 | [(set (match_operand:TF 0 "fr_register_operand" "") | |
3476 | (div:TF (match_operand:TF 1 "fr_register_operand" "") | |
3477 | (match_operand:TF 2 "fr_register_operand" "")))] | |
23c108af | 3478 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3479 | { |
3480 | rtx insn; | |
3481 | if (TARGET_INLINE_DIV_LAT) | |
3482 | insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]); | |
3483 | else | |
3484 | insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); | |
3485 | emit_insn (insn); | |
3486 | DONE; | |
1d5d7a21 | 3487 | }) |
26102535 RH |
3488 | |
3489 | (define_insn_and_split "divtf3_internal_lat" | |
3490 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3491 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3492 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3493 | (clobber (match_scratch:TF 3 "=&f")) | |
3494 | (clobber (match_scratch:TF 4 "=&f")) | |
3495 | (clobber (match_scratch:TF 5 "=&f")) | |
3496 | (clobber (match_scratch:TF 6 "=&f")) | |
f2f90c63 | 3497 | (clobber (match_scratch:BI 7 "=c"))] |
23c108af | 3498 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3499 | "#" |
3500 | "&& reload_completed" | |
3501 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
3502 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
3503 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3504 | (use (const_int 1))]) |
3505 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3506 | (parallel [(set (match_dup 3) | |
3507 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3508 | (match_dup 8))) | |
3509 | (use (const_int 1))])) | |
3510 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3511 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3512 | (use (const_int 1))])) | |
3513 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3514 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
3515 | (use (const_int 1))])) | |
3516 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3517 | (parallel [(set (match_dup 6) | |
3518 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
3519 | (match_dup 3))) | |
3520 | (use (const_int 1))])) | |
3521 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3522 | (parallel [(set (match_dup 3) | |
3523 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
3524 | (match_dup 3))) | |
3525 | (use (const_int 1))])) | |
3526 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3527 | (parallel [(set (match_dup 5) | |
3528 | (plus:TF (mult:TF (match_dup 6) (match_dup 0)) | |
3529 | (match_dup 0))) | |
3530 | (use (const_int 1))])) | |
3531 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3532 | (parallel [(set (match_dup 0) | |
3533 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3534 | (match_dup 0))) | |
3535 | (use (const_int 1))])) | |
3536 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3537 | (parallel [(set (match_dup 4) | |
3538 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3539 | (match_dup 1))) | |
3540 | (use (const_int 1))])) | |
3541 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3542 | (parallel [(set (match_dup 3) | |
3543 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3544 | (match_dup 4))) | |
3545 | (use (const_int 1))])) | |
3546 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3547 | (parallel [(set (match_dup 5) | |
3548 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3549 | (match_dup 8))) | |
3550 | (use (const_int 1))])) | |
3551 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3552 | (parallel [(set (match_dup 0) | |
3553 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3554 | (match_dup 0))) | |
3555 | (use (const_int 1))])) | |
3556 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3557 | (parallel [(set (match_dup 4) | |
3558 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3559 | (match_dup 1))) | |
3560 | (use (const_int 1))])) | |
3561 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3562 | (set (match_dup 0) | |
3563 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3564 | (match_dup 3)))) | |
3565 | ] | |
3566 | "operands[8] = CONST1_RTX (TFmode);" | |
3567 | [(set_attr "predicable" "no")]) | |
3568 | ||
3569 | (define_insn_and_split "divtf3_internal_thr" | |
3570 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3571 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3572 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3573 | (clobber (match_scratch:TF 3 "=&f")) | |
3574 | (clobber (match_scratch:TF 4 "=&f")) | |
f2f90c63 | 3575 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3576 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3577 | "#" |
3578 | "&& reload_completed" | |
3579 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
3580 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
3581 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3582 | (use (const_int 1))]) |
3583 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3584 | (parallel [(set (match_dup 3) | |
3585 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3586 | (match_dup 6))) | |
3587 | (use (const_int 1))])) | |
3588 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3589 | (parallel [(set (match_dup 4) | |
3590 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3591 | (match_dup 0))) | |
3592 | (use (const_int 1))])) | |
3593 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3594 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
3595 | (use (const_int 1))])) | |
3596 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3597 | (parallel [(set (match_dup 3) | |
3598 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
3599 | (match_dup 4))) | |
3600 | (use (const_int 1))])) | |
3601 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3602 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3603 | (use (const_int 1))])) | |
3604 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3605 | (parallel [(set (match_dup 0) | |
3606 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3607 | (match_dup 6))) | |
3608 | (use (const_int 1))])) | |
3609 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3610 | (parallel [(set (match_dup 0) | |
3611 | (plus:TF (mult:TF (match_dup 0) (match_dup 3)) | |
3612 | (match_dup 3))) | |
3613 | (use (const_int 1))])) | |
3614 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3615 | (parallel [(set (match_dup 3) | |
3616 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3617 | (match_dup 1))) | |
3618 | (use (const_int 1))])) | |
3619 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3620 | (parallel [(set (match_dup 3) | |
3621 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3622 | (match_dup 4))) | |
3623 | (use (const_int 1))])) | |
3624 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3625 | (parallel [(set (match_dup 4) | |
3626 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3627 | (match_dup 6))) | |
3628 | (use (const_int 1))])) | |
3629 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3630 | (parallel [(set (match_dup 0) | |
3631 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3632 | (match_dup 0))) | |
3633 | (use (const_int 1))])) | |
3634 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3635 | (parallel [(set (match_dup 4) | |
3636 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3637 | (match_dup 1))) | |
3638 | (use (const_int 1))])) | |
3639 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3640 | (set (match_dup 0) | |
3641 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3642 | (match_dup 3)))) | |
3643 | ] | |
3644 | "operands[6] = CONST1_RTX (TFmode);" | |
3645 | [(set_attr "predicable" "no")]) | |
3646 | ||
3647 | ;; ??? frcpa works like cmp.foo.unc. | |
3648 | ||
655f2eb9 RH |
3649 | (define_insn "*recip_approx" |
3650 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3651 | (div:TF (const_int 1) | |
3652 | (match_operand:TF 3 "fr_register_operand" "f"))) | |
f2f90c63 RH |
3653 | (set (match_operand:BI 1 "register_operand" "=c") |
3654 | (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") | |
086c0f96 | 3655 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 3656 | (use (match_operand:SI 4 "const_int_operand" ""))] |
23c108af | 3657 | "INTEL_EXTENDED_IEEE_FORMAT" |
655f2eb9 | 3658 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 3659 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3660 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3661 | \f |
3662 | ;; :::::::::::::::::::: | |
3663 | ;; :: | |
3664 | ;; :: 32 bit Integer Shifts and Rotates | |
3665 | ;; :: | |
3666 | ;; :::::::::::::::::::: | |
3667 | ||
9c668921 | 3668 | (define_expand "ashlsi3" |
0551c32d RH |
3669 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3670 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3671 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 3672 | "" |
9c668921 RH |
3673 | { |
3674 | if (GET_CODE (operands[2]) != CONST_INT) | |
3675 | { | |
3676 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3677 | we've got to get rid of stray bits outside the SImode register. */ | |
3678 | rtx subshift = gen_reg_rtx (DImode); | |
3679 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3680 | operands[2] = subshift; | |
3681 | } | |
1d5d7a21 | 3682 | }) |
9c668921 RH |
3683 | |
3684 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3685 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3686 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3687 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3688 | "" |
041f25e6 RH |
3689 | "@ |
3690 | shladd %0 = %1, %2, r0 | |
3691 | dep.z %0 = %1, %2, %E2 | |
3692 | shl %0 = %1, %2" | |
52e12ad0 | 3693 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3694 | |
3695 | (define_expand "ashrsi3" | |
0551c32d RH |
3696 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3697 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3698 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3699 | "" |
c65ebc55 | 3700 | { |
041f25e6 RH |
3701 | rtx subtarget = gen_reg_rtx (DImode); |
3702 | if (GET_CODE (operands[2]) == CONST_INT) | |
3703 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3704 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3705 | else | |
3706 | { | |
9c668921 | 3707 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3708 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3709 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3710 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3711 | } |
3712 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3713 | DONE; | |
1d5d7a21 | 3714 | }) |
c65ebc55 | 3715 | |
c65ebc55 | 3716 | (define_expand "lshrsi3" |
0551c32d RH |
3717 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3718 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3719 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3720 | "" |
c65ebc55 | 3721 | { |
041f25e6 RH |
3722 | rtx subtarget = gen_reg_rtx (DImode); |
3723 | if (GET_CODE (operands[2]) == CONST_INT) | |
3724 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3725 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3726 | else | |
3727 | { | |
9c668921 | 3728 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3729 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3730 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3731 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3732 | } |
3733 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3734 | DONE; | |
1d5d7a21 | 3735 | }) |
c65ebc55 | 3736 | |
c65ebc55 | 3737 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3738 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3739 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3740 | |
3741 | (define_expand "rotrsi3" | |
66db6b45 RH |
3742 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3743 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3744 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3745 | "" | |
66db6b45 RH |
3746 | { |
3747 | if (GET_MODE (operands[2]) != VOIDmode) | |
3748 | { | |
3749 | rtx tmp = gen_reg_rtx (DImode); | |
3750 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3751 | operands[2] = tmp; | |
3752 | } | |
1d5d7a21 | 3753 | }) |
66db6b45 RH |
3754 | |
3755 | (define_insn_and_split "*rotrsi3_internal" | |
3756 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3757 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3758 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3759 | "" | |
3760 | "#" | |
3761 | "reload_completed" | |
c65ebc55 | 3762 | [(set (match_dup 3) |
66db6b45 | 3763 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3764 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3765 | (set (match_dup 3) | |
66db6b45 RH |
3766 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3767 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3768 | ||
3769 | (define_expand "rotlsi3" | |
3770 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3771 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3772 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3773 | "" |
c65ebc55 JW |
3774 | { |
3775 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3776 | { |
3777 | rtx tmp = gen_reg_rtx (SImode); | |
3778 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3779 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3780 | DONE; | |
3781 | } | |
1d5d7a21 | 3782 | }) |
66db6b45 RH |
3783 | |
3784 | (define_insn_and_split "*rotlsi3_internal" | |
3785 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3786 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3787 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3788 | "" | |
3789 | "#" | |
3790 | "reload_completed" | |
3791 | [(set (match_dup 3) | |
3792 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3793 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3794 | (set (match_dup 3) | |
3795 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
3796 | { |
3797 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3798 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
3799 | }) | |
c65ebc55 JW |
3800 | \f |
3801 | ;; :::::::::::::::::::: | |
3802 | ;; :: | |
3803 | ;; :: 64 bit Integer Shifts and Rotates | |
3804 | ;; :: | |
3805 | ;; :::::::::::::::::::: | |
3806 | ||
3807 | (define_insn "ashldi3" | |
52e12ad0 BS |
3808 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3809 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3810 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3811 | "" |
041f25e6 RH |
3812 | "@ |
3813 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3814 | shl %0 = %1, %2 |
041f25e6 | 3815 | shl %0 = %1, %2" |
52e12ad0 | 3816 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3817 | |
3818 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3819 | ||
3820 | (define_insn "*shladd" | |
0551c32d RH |
3821 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3822 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3823 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3824 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3825 | "" |
3826 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3827 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3828 | |
3829 | ;; This can be created by register elimination if operand3 of shladd is an | |
3830 | ;; eliminable register or has reg_equiv_constant set. | |
3831 | ||
3832 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3833 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3834 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3835 | ;; incorrectly. | |
3836 | ||
5527bf14 | 3837 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3838 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3839 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3840 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3841 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3842 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3843 | "reload_in_progress" | |
5527bf14 | 3844 | "* abort ();" |
c65ebc55 JW |
3845 | "reload_completed" |
3846 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3847 | (match_dup 3))) | |
c65ebc55 | 3848 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3849 | "" |
52e12ad0 | 3850 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3851 | |
3852 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3853 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3854 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3855 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3856 | "" |
52e12ad0 BS |
3857 | "@ |
3858 | shr %0 = %1, %2 | |
3859 | shr %0 = %1, %2" | |
3860 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3861 | |
3862 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3863 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3864 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3865 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3866 | "" |
52e12ad0 BS |
3867 | "@ |
3868 | shr.u %0 = %1, %2 | |
3869 | shr.u %0 = %1, %2" | |
3870 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3871 | |
3872 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3873 | ;; will load the operand into a register and call the pattern if the predicate | |
3874 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3875 | ;; verify that we have an appropriate constant in the expander. | |
3876 | ||
3877 | (define_expand "rotrdi3" | |
0551c32d RH |
3878 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3879 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3880 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3881 | "" | |
c65ebc55 JW |
3882 | { |
3883 | if (! shift_count_operand (operands[2], DImode)) | |
3884 | FAIL; | |
1d5d7a21 | 3885 | }) |
c65ebc55 JW |
3886 | |
3887 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3888 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3889 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3890 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3891 | "" | |
3892 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3893 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3894 | |
66db6b45 RH |
3895 | (define_expand "rotldi3" |
3896 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3897 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3898 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3899 | "" | |
66db6b45 RH |
3900 | { |
3901 | if (! shift_count_operand (operands[2], DImode)) | |
3902 | FAIL; | |
1d5d7a21 | 3903 | }) |
66db6b45 RH |
3904 | |
3905 | (define_insn "*rotldi3_internal" | |
3906 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3907 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3908 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3909 | "" | |
3910 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3911 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
3912 | \f |
3913 | ;; :::::::::::::::::::: | |
3914 | ;; :: | |
058557c4 | 3915 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
3916 | ;; :: |
3917 | ;; :::::::::::::::::::: | |
3918 | ||
3919 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3920 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3921 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3922 | ;; This doesn't work for unary logical operations, because we don't call | |
3923 | ;; apply_distributive_law for them. | |
3924 | ||
3925 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3926 | ;; apply_distributive_law. We get inefficient code for | |
3927 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3928 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3929 | ;; (zero_extend (and (not A) B)) in combine. | |
3930 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3931 | ;; one_cmplsi2 pattern. | |
3932 | ||
058557c4 | 3933 | (define_insn "one_cmplsi2" |
0551c32d RH |
3934 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3935 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3936 | "" |
3937 | "andcm %0 = -1, %1" | |
52e12ad0 | 3938 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3939 | \f |
3940 | ;; :::::::::::::::::::: | |
3941 | ;; :: | |
058557c4 | 3942 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
3943 | ;; :: |
3944 | ;; :::::::::::::::::::: | |
3945 | ||
3946 | (define_insn "anddi3" | |
0551c32d RH |
3947 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3948 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3949 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3950 | "" |
3951 | "@ | |
3952 | and %0 = %2, %1 | |
aebf2462 | 3953 | fand %0 = %2, %1" |
52e12ad0 | 3954 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3955 | |
3956 | (define_insn "*andnot" | |
0551c32d RH |
3957 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3958 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3959 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3960 | "" |
3961 | "@ | |
3962 | andcm %0 = %2, %1 | |
aebf2462 | 3963 | fandcm %0 = %2, %1" |
52e12ad0 | 3964 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3965 | |
3966 | (define_insn "iordi3" | |
0551c32d RH |
3967 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3968 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3969 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3970 | "" |
3971 | "@ | |
3972 | or %0 = %2, %1 | |
aebf2462 | 3973 | for %0 = %2, %1" |
52e12ad0 | 3974 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3975 | |
3976 | (define_insn "xordi3" | |
0551c32d RH |
3977 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3978 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3979 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3980 | "" |
3981 | "@ | |
3982 | xor %0 = %2, %1 | |
aebf2462 | 3983 | fxor %0 = %2, %1" |
52e12ad0 | 3984 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3985 | |
3986 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3987 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3988 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3989 | "" |
3990 | "andcm %0 = -1, %1" | |
52e12ad0 | 3991 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3992 | \f |
3993 | ;; :::::::::::::::::::: | |
3994 | ;; :: | |
3995 | ;; :: Comparisons | |
3996 | ;; :: | |
3997 | ;; :::::::::::::::::::: | |
3998 | ||
f2f90c63 RH |
3999 | (define_expand "cmpbi" |
4000 | [(set (cc0) | |
4001 | (compare (match_operand:BI 0 "register_operand" "") | |
4002 | (match_operand:BI 1 "const_int_operand" "")))] | |
4003 | "" | |
f2f90c63 RH |
4004 | { |
4005 | ia64_compare_op0 = operands[0]; | |
4006 | ia64_compare_op1 = operands[1]; | |
4007 | DONE; | |
1d5d7a21 | 4008 | }) |
f2f90c63 | 4009 | |
c65ebc55 JW |
4010 | (define_expand "cmpsi" |
4011 | [(set (cc0) | |
0551c32d RH |
4012 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4013 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4014 | "" |
c65ebc55 JW |
4015 | { |
4016 | ia64_compare_op0 = operands[0]; | |
4017 | ia64_compare_op1 = operands[1]; | |
4018 | DONE; | |
1d5d7a21 | 4019 | }) |
c65ebc55 JW |
4020 | |
4021 | (define_expand "cmpdi" | |
4022 | [(set (cc0) | |
0551c32d RH |
4023 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4024 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4025 | "" |
c65ebc55 JW |
4026 | { |
4027 | ia64_compare_op0 = operands[0]; | |
4028 | ia64_compare_op1 = operands[1]; | |
4029 | DONE; | |
1d5d7a21 | 4030 | }) |
c65ebc55 JW |
4031 | |
4032 | (define_expand "cmpsf" | |
4033 | [(set (cc0) | |
0551c32d RH |
4034 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4035 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4036 | "" |
c65ebc55 JW |
4037 | { |
4038 | ia64_compare_op0 = operands[0]; | |
4039 | ia64_compare_op1 = operands[1]; | |
4040 | DONE; | |
1d5d7a21 | 4041 | }) |
c65ebc55 JW |
4042 | |
4043 | (define_expand "cmpdf" | |
4044 | [(set (cc0) | |
0551c32d RH |
4045 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4046 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4047 | "" |
c65ebc55 JW |
4048 | { |
4049 | ia64_compare_op0 = operands[0]; | |
4050 | ia64_compare_op1 = operands[1]; | |
4051 | DONE; | |
1d5d7a21 | 4052 | }) |
c65ebc55 | 4053 | |
3f622353 | 4054 | (define_expand "cmptf" |
c65ebc55 | 4055 | [(set (cc0) |
3f622353 RH |
4056 | (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") |
4057 | (match_operand:TF 1 "tfreg_or_fp01_operand" "")))] | |
23c108af | 4058 | "INTEL_EXTENDED_IEEE_FORMAT" |
c65ebc55 JW |
4059 | { |
4060 | ia64_compare_op0 = operands[0]; | |
4061 | ia64_compare_op1 = operands[1]; | |
4062 | DONE; | |
1d5d7a21 | 4063 | }) |
c65ebc55 JW |
4064 | |
4065 | (define_insn "*cmpsi_normal" | |
f2f90c63 RH |
4066 | [(set (match_operand:BI 0 "register_operand" "=c") |
4067 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4068 | [(match_operand:SI 2 "gr_register_operand" "r") |
4069 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4070 | "" |
4071 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4072 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4073 | |
18a3c539 JW |
4074 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4075 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4076 | ||
c65ebc55 | 4077 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4078 | [(set (match_operand:BI 0 "register_operand" "=c") |
4079 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4080 | [(match_operand:SI 2 "gr_register_operand" "r") |
4081 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4082 | "" |
18a3c539 | 4083 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4084 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4085 | |
4086 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4087 | [(set (match_operand:BI 0 "register_operand" "=c") |
4088 | (match_operator:BI 1 "normal_comparison_operator" | |
4089 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4090 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4091 | "" |
f2f90c63 | 4092 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4093 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4094 | |
18a3c539 JW |
4095 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4096 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4097 | ||
c65ebc55 | 4098 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4099 | [(set (match_operand:BI 0 "register_operand" "=c") |
4100 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4101 | [(match_operand:DI 2 "gr_register_operand" "r") |
4102 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4103 | "" |
18a3c539 | 4104 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4105 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4106 | |
4107 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4108 | [(set (match_operand:BI 0 "register_operand" "=c") |
4109 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4110 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4111 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4112 | "" |
4113 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4114 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4115 | |
4116 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4117 | [(set (match_operand:BI 0 "register_operand" "=c") |
4118 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4119 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4120 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4121 | "" |
4122 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4123 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4124 | |
3f622353 | 4125 | (define_insn "*cmptf_internal" |
f2f90c63 RH |
4126 | [(set (match_operand:BI 0 "register_operand" "=c") |
4127 | (match_operator:BI 1 "comparison_operator" | |
3f622353 RH |
4128 | [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG") |
4129 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))] | |
23c108af | 4130 | "INTEL_EXTENDED_IEEE_FORMAT" |
3f622353 | 4131 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4132 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4133 | |
c65ebc55 JW |
4134 | ;; ??? Can this pattern be generated? |
4135 | ||
4136 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4137 | [(set (match_operand:BI 0 "register_operand" "=c") |
4138 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4139 | (const_int 1) |
4140 | (match_operand:DI 2 "immediate_operand" "n")) | |
4141 | (const_int 0)))] | |
4142 | "" | |
4143 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4144 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4145 | |
4146 | (define_insn "*bit_one" | |
f2f90c63 RH |
4147 | [(set (match_operand:BI 0 "register_operand" "=c") |
4148 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4149 | (const_int 1) |
4150 | (match_operand:DI 2 "immediate_operand" "n")) | |
4151 | (const_int 0)))] | |
4152 | "" | |
4153 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4154 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4155 | \f |
4156 | ;; :::::::::::::::::::: | |
4157 | ;; :: | |
4158 | ;; :: Branches | |
4159 | ;; :: | |
4160 | ;; :::::::::::::::::::: | |
4161 | ||
4162 | (define_expand "beq" | |
f2f90c63 RH |
4163 | [(set (pc) |
4164 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4165 | (label_ref (match_operand 0 "" "")) |
4166 | (pc)))] | |
4167 | "" | |
f2f90c63 | 4168 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4169 | |
4170 | (define_expand "bne" | |
f2f90c63 RH |
4171 | [(set (pc) |
4172 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4173 | (label_ref (match_operand 0 "" "")) |
4174 | (pc)))] | |
4175 | "" | |
f2f90c63 | 4176 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4177 | |
4178 | (define_expand "blt" | |
f2f90c63 RH |
4179 | [(set (pc) |
4180 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4181 | (label_ref (match_operand 0 "" "")) |
4182 | (pc)))] | |
4183 | "" | |
f2f90c63 | 4184 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4185 | |
4186 | (define_expand "ble" | |
f2f90c63 RH |
4187 | [(set (pc) |
4188 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4189 | (label_ref (match_operand 0 "" "")) |
4190 | (pc)))] | |
4191 | "" | |
f2f90c63 | 4192 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4193 | |
4194 | (define_expand "bgt" | |
f2f90c63 RH |
4195 | [(set (pc) |
4196 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4197 | (label_ref (match_operand 0 "" "")) |
4198 | (pc)))] | |
4199 | "" | |
f2f90c63 | 4200 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4201 | |
4202 | (define_expand "bge" | |
f2f90c63 RH |
4203 | [(set (pc) |
4204 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4205 | (label_ref (match_operand 0 "" "")) |
4206 | (pc)))] | |
4207 | "" | |
f2f90c63 | 4208 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4209 | |
4210 | (define_expand "bltu" | |
f2f90c63 RH |
4211 | [(set (pc) |
4212 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4213 | (label_ref (match_operand 0 "" "")) |
4214 | (pc)))] | |
4215 | "" | |
f2f90c63 | 4216 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4217 | |
4218 | (define_expand "bleu" | |
f2f90c63 RH |
4219 | [(set (pc) |
4220 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4221 | (label_ref (match_operand 0 "" "")) |
4222 | (pc)))] | |
4223 | "" | |
f2f90c63 | 4224 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4225 | |
4226 | (define_expand "bgtu" | |
f2f90c63 RH |
4227 | [(set (pc) |
4228 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4229 | (label_ref (match_operand 0 "" "")) |
4230 | (pc)))] | |
4231 | "" | |
f2f90c63 | 4232 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4233 | |
4234 | (define_expand "bgeu" | |
f2f90c63 RH |
4235 | [(set (pc) |
4236 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4237 | (label_ref (match_operand 0 "" "")) |
4238 | (pc)))] | |
4239 | "" | |
f2f90c63 | 4240 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4241 | |
e57b9d65 | 4242 | (define_expand "bunordered" |
f2f90c63 RH |
4243 | [(set (pc) |
4244 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4245 | (label_ref (match_operand 0 "" "")) |
4246 | (pc)))] | |
4247 | "" | |
f2f90c63 | 4248 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4249 | |
4250 | (define_expand "bordered" | |
f2f90c63 RH |
4251 | [(set (pc) |
4252 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4253 | (label_ref (match_operand 0 "" "")) |
4254 | (pc)))] | |
4255 | "" | |
f2f90c63 | 4256 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4257 | |
6b6c1201 | 4258 | (define_insn "*br_true" |
c65ebc55 | 4259 | [(set (pc) |
6b6c1201 | 4260 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4261 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4262 | (const_int 0)]) |
4263 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4264 | (pc)))] |
4265 | "" | |
85548039 | 4266 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4267 | [(set_attr "itanium_class" "br") |
e5bde68a | 4268 | (set_attr "predicable" "no")]) |
c65ebc55 | 4269 | |
6b6c1201 | 4270 | (define_insn "*br_false" |
c65ebc55 | 4271 | [(set (pc) |
6b6c1201 | 4272 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4273 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4274 | (const_int 0)]) |
c65ebc55 | 4275 | (pc) |
6b6c1201 | 4276 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4277 | "" |
85548039 | 4278 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4279 | [(set_attr "itanium_class" "br") |
e5bde68a | 4280 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4281 | \f |
4282 | ;; :::::::::::::::::::: | |
4283 | ;; :: | |
5527bf14 RH |
4284 | ;; :: Counted loop operations |
4285 | ;; :: | |
4286 | ;; :::::::::::::::::::: | |
4287 | ||
4288 | (define_expand "doloop_end" | |
4289 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4290 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4291 | (use (match_operand 2 "" "")) ; max iterations | |
4292 | (use (match_operand 3 "" "")) ; loop level | |
4293 | (use (match_operand 4 "" ""))] ; label | |
4294 | "" | |
5527bf14 RH |
4295 | { |
4296 | /* Only use cloop on innermost loops. */ | |
4297 | if (INTVAL (operands[3]) > 1) | |
4298 | FAIL; | |
4299 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4300 | operands[4])); | |
4301 | DONE; | |
1d5d7a21 | 4302 | }) |
5527bf14 RH |
4303 | |
4304 | (define_insn "doloop_end_internal" | |
4305 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4306 | (const_int 0)) | |
4307 | (label_ref (match_operand 1 "" "")) | |
4308 | (pc))) | |
4309 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
4310 | (plus:DI (match_dup 0) (const_int -1)) |
4311 | (match_dup 0)))] | |
5527bf14 RH |
4312 | "" |
4313 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4314 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4315 | (set_attr "predicable" "no")]) |
4316 | \f | |
4317 | ;; :::::::::::::::::::: | |
4318 | ;; :: | |
c65ebc55 JW |
4319 | ;; :: Set flag operations |
4320 | ;; :: | |
4321 | ;; :::::::::::::::::::: | |
4322 | ||
4323 | (define_expand "seq" | |
f2f90c63 | 4324 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4325 | "" |
f2f90c63 | 4326 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4327 | |
4328 | (define_expand "sne" | |
f2f90c63 | 4329 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4330 | "" |
f2f90c63 | 4331 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4332 | |
4333 | (define_expand "slt" | |
f2f90c63 | 4334 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4335 | "" |
f2f90c63 | 4336 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4337 | |
4338 | (define_expand "sle" | |
f2f90c63 | 4339 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4340 | "" |
f2f90c63 | 4341 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4342 | |
4343 | (define_expand "sgt" | |
f2f90c63 | 4344 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4345 | "" |
f2f90c63 | 4346 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4347 | |
4348 | (define_expand "sge" | |
f2f90c63 | 4349 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4350 | "" |
f2f90c63 | 4351 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4352 | |
4353 | (define_expand "sltu" | |
f2f90c63 | 4354 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4355 | "" |
f2f90c63 | 4356 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4357 | |
4358 | (define_expand "sleu" | |
f2f90c63 | 4359 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4360 | "" |
f2f90c63 | 4361 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4362 | |
4363 | (define_expand "sgtu" | |
f2f90c63 | 4364 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4365 | "" |
f2f90c63 | 4366 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4367 | |
4368 | (define_expand "sgeu" | |
f2f90c63 | 4369 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4370 | "" |
f2f90c63 | 4371 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4372 | |
e57b9d65 | 4373 | (define_expand "sunordered" |
f2f90c63 | 4374 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4375 | "" |
f2f90c63 | 4376 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4377 | |
4378 | (define_expand "sordered" | |
f2f90c63 | 4379 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4380 | "" |
f2f90c63 | 4381 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4382 | |
c65ebc55 JW |
4383 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4384 | ;; efficient than mov/mov/cst/cst. | |
4385 | ||
0551c32d RH |
4386 | (define_insn_and_split "*sne_internal" |
4387 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4388 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4389 | (const_int 0)))] |
4390 | "" | |
4391 | "#" | |
c65ebc55 | 4392 | "reload_completed" |
f2f90c63 RH |
4393 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4394 | (set (match_dup 0) (const_int 1))) | |
4395 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4396 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4397 | "" |
52e12ad0 | 4398 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4399 | |
0551c32d RH |
4400 | (define_insn_and_split "*seq_internal" |
4401 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4402 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4403 | (const_int 0)))] |
4404 | "" | |
4405 | "#" | |
c65ebc55 | 4406 | "reload_completed" |
f2f90c63 RH |
4407 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4408 | (set (match_dup 0) (const_int 0))) | |
4409 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4410 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4411 | "" |
52e12ad0 | 4412 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4413 | \f |
4414 | ;; :::::::::::::::::::: | |
4415 | ;; :: | |
4416 | ;; :: Conditional move instructions. | |
4417 | ;; :: | |
4418 | ;; :::::::::::::::::::: | |
4419 | ||
4420 | ;; ??? Add movXXcc patterns? | |
4421 | ||
c65ebc55 JW |
4422 | ;; |
4423 | ;; DImode if_then_else patterns. | |
4424 | ;; | |
4425 | ||
75cdbeb8 | 4426 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4427 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4428 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4429 | (if_then_else:DI |
f2f90c63 RH |
4430 | (match_operator 4 "predicate_operator" |
4431 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4432 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4433 | (const_int 0)]) |
f2f90c63 | 4434 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4435 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4436 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4437 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4438 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4439 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 4440 | { abort (); } |
75cdbeb8 RH |
4441 | [(set_attr "predicable" "no")]) |
4442 | ||
4443 | (define_split | |
f2f90c63 | 4444 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4445 | (if_then_else |
f2f90c63 RH |
4446 | (match_operator 4 "predicate_operator" |
4447 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4448 | (const_int 0)]) |
f2f90c63 RH |
4449 | (match_operand 2 "move_operand" "") |
4450 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4451 | "reload_completed" |
4452 | [(const_int 0)] | |
e5bde68a | 4453 | { |
3b572406 | 4454 | rtx tmp; |
2f937369 DM |
4455 | int emitted_something; |
4456 | ||
4457 | emitted_something = 0; | |
3b572406 | 4458 | if (! rtx_equal_p (operands[0], operands[2])) |
e5bde68a | 4459 | { |
3b572406 RH |
4460 | tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]); |
4461 | tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp); | |
4462 | emit_insn (tmp); | |
2f937369 | 4463 | emitted_something = 1; |
e5bde68a | 4464 | } |
3b572406 RH |
4465 | if (! rtx_equal_p (operands[0], operands[3])) |
4466 | { | |
4467 | tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4468 | VOIDmode, operands[1], const0_rtx); |
3b572406 RH |
4469 | tmp = gen_rtx_COND_EXEC (VOIDmode, tmp, |
4470 | gen_rtx_SET (VOIDmode, operands[0], | |
4471 | operands[3])); | |
4472 | emit_insn (tmp); | |
2f937369 | 4473 | emitted_something = 1; |
3b572406 | 4474 | } |
2f937369 DM |
4475 | if (! emitted_something) |
4476 | emit_note (NULL, NOTE_INSN_DELETED); | |
3b572406 | 4477 | DONE; |
1d5d7a21 | 4478 | }) |
c65ebc55 JW |
4479 | |
4480 | ;; Absolute value pattern. | |
4481 | ||
4482 | (define_insn "*absdi2_internal" | |
0551c32d | 4483 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4484 | (if_then_else:DI |
f2f90c63 RH |
4485 | (match_operator 4 "predicate_operator" |
4486 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4487 | (const_int 0)]) |
0551c32d RH |
4488 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4489 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4490 | "" |
e5bde68a | 4491 | "#" |
52e12ad0 | 4492 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4493 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4494 | |
4495 | (define_split | |
4496 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4497 | (if_then_else:DI |
f2f90c63 RH |
4498 | (match_operator 4 "predicate_operator" |
4499 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4500 | (const_int 0)]) |
0551c32d RH |
4501 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4502 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4503 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4504 | [(cond_exec | |
4505 | (match_dup 4) | |
4506 | (set (match_dup 0) | |
4507 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4508 | "") |
4509 | ||
e5bde68a RH |
4510 | (define_split |
4511 | [(set (match_operand:DI 0 "register_operand" "") | |
4512 | (if_then_else:DI | |
f2f90c63 RH |
4513 | (match_operator 4 "predicate_operator" |
4514 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4515 | (const_int 0)]) |
0551c32d RH |
4516 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4517 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4518 | "reload_completed" |
4519 | [(cond_exec | |
4520 | (match_dup 4) | |
4521 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4522 | (cond_exec | |
4523 | (match_dup 5) | |
4524 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4525 | { |
4526 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4527 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4528 | }) |
c65ebc55 JW |
4529 | |
4530 | ;; | |
4531 | ;; SImode if_then_else patterns. | |
4532 | ;; | |
4533 | ||
75cdbeb8 | 4534 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4535 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4536 | (if_then_else:SI |
f2f90c63 RH |
4537 | (match_operator 4 "predicate_operator" |
4538 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4539 | (const_int 0)]) |
f2f90c63 | 4540 | (match_operand:SI 2 "move_operand" |
3b572406 | 4541 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4542 | (match_operand:SI 3 "move_operand" |
3b572406 | 4543 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4544 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4545 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 4546 | { abort (); } |
3b572406 | 4547 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4548 | |
4549 | (define_insn "*abssi2_internal" | |
0551c32d | 4550 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4551 | (if_then_else:SI |
f2f90c63 RH |
4552 | (match_operator 4 "predicate_operator" |
4553 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4554 | (const_int 0)]) |
0551c32d RH |
4555 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4556 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4557 | "" |
e5bde68a | 4558 | "#" |
52e12ad0 | 4559 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4560 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4561 | |
4562 | (define_split | |
4563 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4564 | (if_then_else:SI |
f2f90c63 RH |
4565 | (match_operator 4 "predicate_operator" |
4566 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4567 | (const_int 0)]) |
0551c32d RH |
4568 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4569 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4570 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4571 | [(cond_exec | |
4572 | (match_dup 4) | |
4573 | (set (match_dup 0) | |
4574 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4575 | "") |
4576 | ||
e5bde68a RH |
4577 | (define_split |
4578 | [(set (match_operand:SI 0 "register_operand" "") | |
4579 | (if_then_else:SI | |
f2f90c63 RH |
4580 | (match_operator 4 "predicate_operator" |
4581 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4582 | (const_int 0)]) |
0551c32d RH |
4583 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4584 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4585 | "reload_completed" |
4586 | [(cond_exec | |
4587 | (match_dup 4) | |
4588 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4589 | (cond_exec | |
4590 | (match_dup 5) | |
4591 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4592 | { |
4593 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4594 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4595 | }) |
e5bde68a | 4596 | |
7dcc803e | 4597 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4598 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4599 | (match_operator:SI 5 "condop_operator" | |
4600 | [(if_then_else:SI | |
4601 | (match_operator 6 "predicate_operator" | |
4602 | [(match_operand:BI 1 "register_operand" "c") | |
4603 | (const_int 0)]) | |
4604 | (match_operand:SI 2 "gr_register_operand" "r") | |
4605 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4606 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4607 | "" | |
4608 | "#" | |
acb0638d BS |
4609 | "reload_completed" |
4610 | [(cond_exec | |
4611 | (match_dup 6) | |
4612 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4613 | (cond_exec | |
4614 | (match_dup 7) | |
4615 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
4616 | { |
4617 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4618 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4619 | } |
7dcc803e BS |
4620 | [(set_attr "itanium_class" "ialu") |
4621 | (set_attr "predicable" "no")]) | |
4622 | ||
acb0638d | 4623 | |
7dcc803e | 4624 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4625 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4626 | (match_operator:SI 5 "condop_operator" | |
4627 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4628 | (if_then_else:SI | |
4629 | (match_operator 6 "predicate_operator" | |
4630 | [(match_operand:BI 1 "register_operand" "c") | |
4631 | (const_int 0)]) | |
4632 | (match_operand:SI 2 "gr_register_operand" "r") | |
4633 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4634 | "" | |
4635 | "#" | |
acb0638d BS |
4636 | "reload_completed" |
4637 | [(cond_exec | |
4638 | (match_dup 6) | |
4639 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4640 | (cond_exec | |
4641 | (match_dup 7) | |
4642 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
4643 | { |
4644 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4645 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4646 | } |
7dcc803e BS |
4647 | [(set_attr "itanium_class" "ialu") |
4648 | (set_attr "predicable" "no")]) | |
acb0638d | 4649 | |
c65ebc55 JW |
4650 | \f |
4651 | ;; :::::::::::::::::::: | |
4652 | ;; :: | |
4653 | ;; :: Call and branch instructions | |
4654 | ;; :: | |
4655 | ;; :::::::::::::::::::: | |
4656 | ||
4657 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4658 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4659 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4660 | ;; registers used as operands. | |
4661 | ||
4662 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4663 | ;; is supplied for the sake of some RISC machines which need to put this | |
4664 | ;; information into the assembler code; they can put it in the RTL instead of | |
4665 | ;; operand 1. | |
4666 | ||
4667 | (define_expand "call" | |
4668 | [(use (match_operand:DI 0 "" "")) | |
4669 | (use (match_operand 1 "" "")) | |
4670 | (use (match_operand 2 "" "")) | |
4671 | (use (match_operand 3 "" ""))] | |
4672 | "" | |
c65ebc55 | 4673 | { |
2ed4af6f | 4674 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); |
c65ebc55 | 4675 | DONE; |
1d5d7a21 | 4676 | }) |
c65ebc55 | 4677 | |
2ed4af6f RH |
4678 | (define_expand "sibcall" |
4679 | [(use (match_operand:DI 0 "" "")) | |
4680 | (use (match_operand 1 "" "")) | |
4681 | (use (match_operand 2 "" "")) | |
4682 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 4683 | "" |
c65ebc55 | 4684 | { |
2ed4af6f RH |
4685 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); |
4686 | DONE; | |
1d5d7a21 | 4687 | }) |
c65ebc55 | 4688 | |
c65ebc55 | 4689 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4690 | ;; register in which the value is returned. There are three more operands, |
4691 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4692 | ;; increased by one). |
2ed4af6f | 4693 | ;; |
c65ebc55 JW |
4694 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4695 | ||
4696 | (define_expand "call_value" | |
4697 | [(use (match_operand 0 "" "")) | |
4698 | (use (match_operand:DI 1 "" "")) | |
4699 | (use (match_operand 2 "" "")) | |
4700 | (use (match_operand 3 "" "")) | |
4701 | (use (match_operand 4 "" ""))] | |
4702 | "" | |
c65ebc55 | 4703 | { |
2ed4af6f | 4704 | ia64_expand_call (operands[0], operands[1], operands[3], 0); |
c65ebc55 | 4705 | DONE; |
1d5d7a21 | 4706 | }) |
c65ebc55 | 4707 | |
2ed4af6f RH |
4708 | (define_expand "sibcall_value" |
4709 | [(use (match_operand 0 "" "")) | |
4710 | (use (match_operand:DI 1 "" "")) | |
4711 | (use (match_operand 2 "" "")) | |
4712 | (use (match_operand 3 "" "")) | |
4713 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 4714 | "" |
c65ebc55 | 4715 | { |
2ed4af6f RH |
4716 | ia64_expand_call (operands[0], operands[1], operands[3], 1); |
4717 | DONE; | |
1d5d7a21 | 4718 | }) |
c65ebc55 | 4719 | |
c65ebc55 JW |
4720 | ;; Call subroutine returning any type. |
4721 | ||
4722 | (define_expand "untyped_call" | |
4723 | [(parallel [(call (match_operand 0 "" "") | |
4724 | (const_int 0)) | |
4725 | (match_operand 1 "" "") | |
4726 | (match_operand 2 "" "")])] | |
4727 | "" | |
c65ebc55 JW |
4728 | { |
4729 | int i; | |
4730 | ||
4731 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4732 | ||
4733 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4734 | { | |
4735 | rtx set = XVECEXP (operands[2], 0, i); | |
4736 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4737 | } | |
4738 | ||
4739 | /* The optimizer does not know that the call sets the function value | |
4740 | registers we stored in the result block. We avoid problems by | |
4741 | claiming that all hard registers are used and clobbered at this | |
4742 | point. */ | |
4743 | emit_insn (gen_blockage ()); | |
4744 | ||
4745 | DONE; | |
1d5d7a21 | 4746 | }) |
c65ebc55 | 4747 | |
2ed4af6f | 4748 | (define_insn "call_nopic" |
52e12ad0 | 4749 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4750 | (match_operand 1 "" "")) |
52e12ad0 | 4751 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4752 | "" |
4753 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4754 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4755 | |
4756 | (define_insn "call_value_nopic" | |
4757 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4758 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4759 | (match_operand 2 "" ""))) |
52e12ad0 | 4760 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4761 | "" |
4762 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4763 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4764 | |
4765 | (define_insn "sibcall_nopic" | |
52e12ad0 | 4766 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4767 | (match_operand 1 "" "")) |
6ca3c22f RH |
4768 | (use (match_operand:DI 2 "register_operand" "=b,b")) |
4769 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4770 | "" |
4771 | "br%+.many %0" | |
52e12ad0 | 4772 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4773 | |
4774 | (define_insn "call_pic" | |
5da4f548 | 4775 | [(call (mem (match_operand 0 "call_operand" "b,i")) |
2ed4af6f | 4776 | (match_operand 1 "" "")) |
086c0f96 | 4777 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
52e12ad0 | 4778 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4779 | "" |
4780 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4781 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4782 | |
4783 | (define_insn "call_value_pic" | |
4784 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4785 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4786 | (match_operand 2 "" ""))) |
086c0f96 | 4787 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
52e12ad0 | 4788 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4789 | "" |
4790 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4791 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4792 | |
4793 | (define_insn "sibcall_pic" | |
4794 | [(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) | |
4795 | (match_operand 1 "" "")) | |
086c0f96 | 4796 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
6ca3c22f RH |
4797 | (use (match_operand:DI 2 "register_operand" "=b")) |
4798 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4799 | "" |
4800 | "br%+.many %0" | |
52e12ad0 | 4801 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4802 | |
c65ebc55 JW |
4803 | (define_insn "return_internal" |
4804 | [(return) | |
4805 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4806 | "" | |
4807 | "br.ret.sptk.many %0" | |
52e12ad0 | 4808 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4809 | |
4810 | (define_insn "return" | |
4811 | [(return)] | |
4812 | "ia64_direct_return ()" | |
4813 | "br.ret.sptk.many rp" | |
52e12ad0 | 4814 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4815 | |
6b6c1201 | 4816 | (define_insn "*return_true" |
c65ebc55 | 4817 | [(set (pc) |
6b6c1201 | 4818 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4819 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4820 | (const_int 0)]) |
c65ebc55 JW |
4821 | (return) |
4822 | (pc)))] | |
4823 | "ia64_direct_return ()" | |
13da91fd | 4824 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4825 | [(set_attr "itanium_class" "br") |
e5bde68a | 4826 | (set_attr "predicable" "no")]) |
c65ebc55 | 4827 | |
6b6c1201 | 4828 | (define_insn "*return_false" |
c65ebc55 | 4829 | [(set (pc) |
6b6c1201 | 4830 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4831 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4832 | (const_int 0)]) |
c65ebc55 JW |
4833 | (pc) |
4834 | (return)))] | |
4835 | "ia64_direct_return ()" | |
13da91fd | 4836 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4837 | [(set_attr "itanium_class" "br") |
e5bde68a | 4838 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4839 | |
4840 | (define_insn "jump" | |
4841 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4842 | "" | |
4843 | "br %l0" | |
52e12ad0 | 4844 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4845 | |
4846 | (define_insn "indirect_jump" | |
4847 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4848 | "" | |
4849 | "br %0" | |
52e12ad0 | 4850 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4851 | |
4852 | (define_expand "tablejump" | |
340f7e7c RH |
4853 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
4854 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 4855 | "" |
c65ebc55 | 4856 | { |
340f7e7c RH |
4857 | rtx op0 = operands[0]; |
4858 | rtx addr; | |
4859 | ||
4860 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
4861 | element into a register without bothering to see whether that | |
4862 | is necessary given the operand predicate. Check for MEM just | |
4863 | in case someone fixes this. */ | |
4864 | if (GET_CODE (op0) == MEM) | |
4865 | addr = XEXP (op0, 0); | |
4866 | else | |
4867 | { | |
4868 | /* Otherwise, cheat and guess that the previous insn in the | |
4869 | stream was the memory load. Grab the address from that. | |
4870 | Note we have to momentarily pop out of the sequence started | |
4871 | by the insn-emit wrapper in order to grab the last insn. */ | |
4872 | rtx last, set; | |
4873 | ||
4874 | end_sequence (); | |
4875 | last = get_last_insn (); | |
4876 | start_sequence (); | |
4877 | set = single_set (last); | |
4878 | ||
4879 | if (! rtx_equal_p (SET_DEST (set), op0) | |
4880 | || GET_CODE (SET_SRC (set)) != MEM) | |
4881 | abort (); | |
4882 | addr = XEXP (SET_SRC (set), 0); | |
4883 | if (rtx_equal_p (addr, op0)) | |
4884 | abort (); | |
4885 | } | |
c65ebc55 | 4886 | |
340f7e7c RH |
4887 | /* Jump table elements are stored pc-relative. That is, a displacement |
4888 | from the entry to the label. Thus to convert to an absolute address | |
4889 | we add the address of the memory from which the value is loaded. */ | |
4890 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
4891 | NULL_RTX, 1, OPTAB_DIRECT); | |
4892 | }) | |
c65ebc55 | 4893 | |
340f7e7c | 4894 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
4895 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
4896 | (use (label_ref (match_operand 1 "" "")))] | |
4897 | "" | |
4898 | "br %0" | |
52e12ad0 | 4899 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4900 | |
4901 | \f | |
4902 | ;; :::::::::::::::::::: | |
4903 | ;; :: | |
4904 | ;; :: Prologue and Epilogue instructions | |
4905 | ;; :: | |
4906 | ;; :::::::::::::::::::: | |
4907 | ||
4908 | (define_expand "prologue" | |
4909 | [(const_int 1)] | |
4910 | "" | |
c65ebc55 JW |
4911 | { |
4912 | ia64_expand_prologue (); | |
4913 | DONE; | |
1d5d7a21 | 4914 | }) |
c65ebc55 JW |
4915 | |
4916 | (define_expand "epilogue" | |
2ed4af6f RH |
4917 | [(return)] |
4918 | "" | |
2ed4af6f RH |
4919 | { |
4920 | ia64_expand_epilogue (0); | |
4921 | DONE; | |
1d5d7a21 | 4922 | }) |
2ed4af6f RH |
4923 | |
4924 | (define_expand "sibcall_epilogue" | |
4925 | [(return)] | |
c65ebc55 | 4926 | "" |
c65ebc55 | 4927 | { |
2ed4af6f | 4928 | ia64_expand_epilogue (1); |
c65ebc55 | 4929 | DONE; |
1d5d7a21 | 4930 | }) |
c65ebc55 JW |
4931 | |
4932 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4933 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4934 | ||
4935 | (define_insn "prologue_allocate_stack" | |
4936 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4937 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4938 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 4939 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
4940 | (match_dup 3))] |
4941 | "" | |
4942 | "@ | |
1d5d7a21 RH |
4943 | add %0 = %1, %2 |
4944 | adds %0 = %2, %1 | |
4945 | addl %0 = %2, %1" | |
52e12ad0 | 4946 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4947 | |
4948 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4949 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4950 | ||
4951 | (define_insn "epilogue_deallocate_stack" | |
4952 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4953 | (match_operand:DI 1 "register_operand" "+r")) | |
4954 | (set (match_dup 1) (match_dup 1))] | |
4955 | "" | |
4956 | "mov %0 = %1" | |
52e12ad0 | 4957 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 4958 | |
1d5d7a21 RH |
4959 | ;; As USE insns aren't meaningful after reload, this is used instead |
4960 | ;; to prevent deleting instructions setting registers for EH handling | |
4961 | (define_insn "prologue_use" | |
4962 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
4963 | UNSPEC_PROLOGUE_USE)] | |
4964 | "" | |
4965 | "" | |
4966 | [(set_attr "itanium_class" "ignore") | |
4967 | (set_attr "predicable" "no")]) | |
4968 | ||
c65ebc55 JW |
4969 | ;; Allocate a new register frame. |
4970 | ||
4971 | (define_insn "alloc" | |
4972 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4973 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
4974 | (use (match_operand:DI 1 "const_int_operand" "i")) |
4975 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4976 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4977 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4978 | "" | |
4979 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4980 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 4981 | (set_attr "predicable" "no")]) |
c65ebc55 | 4982 | |
97e242b0 RH |
4983 | ;; Modifies ar.unat |
4984 | (define_expand "gr_spill" | |
870f9ec0 RH |
4985 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4986 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
4987 | (match_operand:DI 2 "const_int_operand" "")] |
4988 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4989 | (clobber (match_dup 3))])] |
97e242b0 | 4990 | "" |
870f9ec0 | 4991 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4992 | |
870f9ec0 | 4993 | (define_insn "gr_spill_internal" |
c65ebc55 | 4994 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 | 4995 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
4996 | (match_operand:DI 2 "const_int_operand" "")] |
4997 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4998 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4999 | "" |
2130b7fb | 5000 | { |
1d5d7a21 RH |
5001 | /* Note that we use a C output pattern here to avoid the predicate |
5002 | being automatically added before the .mem.offset directive. */ | |
5003 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5004 | } | |
52e12ad0 | 5005 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5006 | |
97e242b0 RH |
5007 | ;; Reads ar.unat |
5008 | (define_expand "gr_restore" | |
870f9ec0 RH |
5009 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5010 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5011 | (match_operand:DI 2 "const_int_operand" "")] |
5012 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5013 | (use (match_dup 3))])] |
97e242b0 | 5014 | "" |
870f9ec0 | 5015 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5016 | |
870f9ec0 | 5017 | (define_insn "gr_restore_internal" |
c65ebc55 | 5018 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5019 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5020 | (match_operand:DI 2 "const_int_operand" "")] |
5021 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5022 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5023 | "" |
1d5d7a21 | 5024 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5025 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5026 | |
5027 | (define_insn "fr_spill" | |
3f622353 | 5028 | [(set (match_operand:TF 0 "memory_operand" "=m") |
086c0f96 RH |
5029 | (unspec:TF [(match_operand:TF 1 "register_operand" "f")] |
5030 | UNSPEC_FR_SPILL))] | |
c65ebc55 JW |
5031 | "" |
5032 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5033 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5034 | |
5035 | (define_insn "fr_restore" | |
3f622353 | 5036 | [(set (match_operand:TF 0 "register_operand" "=f") |
086c0f96 RH |
5037 | (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] |
5038 | UNSPEC_FR_RESTORE))] | |
c65ebc55 JW |
5039 | "" |
5040 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5041 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5042 | |
0024a804 JW |
5043 | ;; ??? The explicit stop is not ideal. It would be better if |
5044 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5045 | ;; fixed later. This avoids an RSE DV. | |
5046 | ||
0c96007e AM |
5047 | (define_insn "bsp_value" |
5048 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5049 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5050 | "" |
0024a804 | 5051 | ";;\;mov %0 = ar.bsp" |
52e12ad0 | 5052 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5053 | |
5054 | (define_insn "set_bsp" | |
086c0f96 RH |
5055 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5056 | UNSPECV_SET_BSP)] | |
0c96007e | 5057 | "" |
1d5d7a21 RH |
5058 | "flushrs |
5059 | mov r19=ar.rsc | |
5060 | ;; | |
5061 | and r19=0x1c,r19 | |
5062 | ;; | |
5063 | mov ar.rsc=r19 | |
5064 | ;; | |
5065 | mov ar.bspstore=%0 | |
5066 | ;; | |
5067 | or r19=0x3,r19 | |
5068 | ;; | |
5069 | loadrs | |
5070 | invala | |
5071 | ;; | |
5072 | mov ar.rsc=r19" | |
52e12ad0 | 5073 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5074 | (set_attr "predicable" "no")]) |
ce152ef8 | 5075 | |
0024a804 JW |
5076 | ;; ??? The explicit stops are not ideal. It would be better if |
5077 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5078 | ;; fixed later. This avoids an RSE DV. | |
5079 | ||
ce152ef8 | 5080 | (define_insn "flushrs" |
086c0f96 | 5081 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5082 | "" |
0024a804 | 5083 | ";;\;flushrs\;;;" |
52e12ad0 | 5084 | [(set_attr "itanium_class" "rse_m")]) |
c65ebc55 JW |
5085 | \f |
5086 | ;; :::::::::::::::::::: | |
5087 | ;; :: | |
5088 | ;; :: Miscellaneous instructions | |
5089 | ;; :: | |
5090 | ;; :::::::::::::::::::: | |
5091 | ||
5092 | ;; ??? Emiting a NOP instruction isn't very useful. This should probably | |
5093 | ;; be emitting ";;" to force a break in the instruction packing. | |
5094 | ||
5095 | ;; No operation, needed in case the user uses -g but not -O. | |
5096 | (define_insn "nop" | |
5097 | [(const_int 0)] | |
5098 | "" | |
5099 | "nop 0" | |
52e12ad0 | 5100 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5101 | |
2130b7fb BS |
5102 | (define_insn "nop_m" |
5103 | [(const_int 1)] | |
5104 | "" | |
5105 | "nop.m 0" | |
5106 | [(set_attr "itanium_class" "nop_m")]) | |
5107 | ||
5108 | (define_insn "nop_i" | |
5109 | [(const_int 2)] | |
5110 | "" | |
5111 | "nop.i 0" | |
5112 | [(set_attr "itanium_class" "nop_i")]) | |
5113 | ||
5114 | (define_insn "nop_f" | |
5115 | [(const_int 3)] | |
5116 | "" | |
5117 | "nop.f 0" | |
5118 | [(set_attr "itanium_class" "nop_f")]) | |
5119 | ||
5120 | (define_insn "nop_b" | |
5121 | [(const_int 4)] | |
5122 | "" | |
5123 | "nop.b 0" | |
5124 | [(set_attr "itanium_class" "nop_b")]) | |
5125 | ||
5126 | (define_insn "nop_x" | |
5127 | [(const_int 5)] | |
5128 | "" | |
5129 | "" | |
5130 | [(set_attr "itanium_class" "nop_x")]) | |
5131 | ||
2130b7fb | 5132 | (define_insn "bundle_selector" |
086c0f96 | 5133 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5134 | "" |
1d5d7a21 | 5135 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5136 | [(set_attr "itanium_class" "ignore") |
5137 | (set_attr "predicable" "no")]) | |
5138 | ||
c65ebc55 JW |
5139 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5140 | ;; point. | |
5141 | (define_insn "blockage" | |
086c0f96 | 5142 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5143 | "" |
5144 | "" | |
52e12ad0 | 5145 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5146 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5147 | |
5148 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5149 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5150 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5151 | "" |
5152 | ";;" | |
52e12ad0 | 5153 | [(set_attr "itanium_class" "stop_bit") |
e5bde68a | 5154 | (set_attr "predicable" "no")]) |
c65ebc55 | 5155 | |
26406018 RH |
5156 | (define_expand "trap" |
5157 | [(trap_if (const_int 1) (const_int 0))] | |
5158 | "" | |
5159 | "") | |
5160 | ||
5161 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
5162 | ;; produces worse code that setting the slot type to A. | |
5163 | ||
5164 | (define_insn "*trap" | |
5165 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
5166 | "" | |
5167 | "break %0" | |
5168 | [(set_attr "itanium_class" "chk_s")]) | |
5169 | ||
5170 | (define_expand "conditional_trap" | |
5171 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
5172 | "" | |
5173 | { | |
5174 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
5175 | }) | |
5176 | ||
5177 | (define_insn "*conditional_trap" | |
5178 | [(trap_if (match_operator 0 "predicate_operator" | |
5179 | [(match_operand:BI 1 "register_operand" "c") | |
5180 | (const_int 0)]) | |
5181 | (match_operand 2 "const_int_operand" ""))] | |
5182 | "" | |
5cf63e3f | 5183 | "(%J0) break %2" |
26406018 RH |
5184 | [(set_attr "itanium_class" "chk_s") |
5185 | (set_attr "predicable" "no")]) | |
5186 | ||
f12f25a7 | 5187 | (define_insn "break_f" |
086c0f96 | 5188 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
5189 | "" |
5190 | "break.f 0" | |
5191 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5192 | |
5193 | (define_insn "prefetch" | |
5194 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5195 | (match_operand:DI 1 "const_int_operand" "n") | |
5196 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5197 | "" | |
5198 | { | |
5199 | static const char * const alt[2][4] = { | |
b3656137 KG |
5200 | { |
5201 | "lfetch.nta [%0]", | |
5202 | "lfetch.nt1 [%0]", | |
5203 | "lfetch.nt2 [%0]", | |
5204 | "lfetch [%0]" | |
5205 | }, | |
5206 | { | |
5207 | "lfetch.excl.nta [%0]", | |
5208 | "lfetch.excl.nt1 [%0]", | |
5209 | "lfetch.excl.nt2 [%0]", | |
5210 | "lfetch.excl [%0]" | |
5211 | } | |
44eca121 JJ |
5212 | }; |
5213 | int i = (INTVAL (operands[1])); | |
5214 | int j = (INTVAL (operands[2])); | |
5215 | ||
5216 | if (i != 0 && i != 1) | |
5217 | abort (); | |
5218 | if (j < 0 || j > 3) | |
5219 | abort (); | |
5220 | return alt[i][j]; | |
5221 | } | |
5222 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5223 | \f |
5224 | ;; Non-local goto support. | |
5225 | ||
5226 | (define_expand "save_stack_nonlocal" | |
5227 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5228 | (use (match_operand:DI 1 "register_operand" ""))] | |
5229 | "" | |
c65ebc55 JW |
5230 | { |
5231 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5232 | \"__ia64_save_stack_nonlocal\"), | |
5233 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
5234 | operands[1], Pmode); | |
5235 | DONE; | |
1d5d7a21 | 5236 | }) |
c65ebc55 JW |
5237 | |
5238 | (define_expand "nonlocal_goto" | |
5239 | [(use (match_operand 0 "general_operand" "")) | |
5240 | (use (match_operand 1 "general_operand" "")) | |
5241 | (use (match_operand 2 "general_operand" "")) | |
5242 | (use (match_operand 3 "general_operand" ""))] | |
5243 | "" | |
c65ebc55 | 5244 | { |
c65ebc55 | 5245 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5246 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5247 | operands[1], Pmode, |
c65ebc55 | 5248 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5249 | operands[3], Pmode); |
c65ebc55 JW |
5250 | emit_barrier (); |
5251 | DONE; | |
1d5d7a21 | 5252 | }) |
c65ebc55 | 5253 | |
97e242b0 RH |
5254 | ;; The rest of the setjmp processing happens with the nonlocal_goto expander. |
5255 | ;; ??? This is not tested. | |
5256 | (define_expand "builtin_setjmp_setup" | |
5257 | [(use (match_operand:DI 0 "" ""))] | |
c65ebc55 | 5258 | "" |
c65ebc55 | 5259 | { |
97e242b0 RH |
5260 | emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); |
5261 | DONE; | |
1d5d7a21 | 5262 | }) |
97e242b0 RH |
5263 | |
5264 | (define_expand "builtin_setjmp_receiver" | |
5265 | [(use (match_operand:DI 0 "" ""))] | |
5266 | "" | |
97e242b0 RH |
5267 | { |
5268 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); | |
c65ebc55 | 5269 | DONE; |
1d5d7a21 | 5270 | }) |
c65ebc55 | 5271 | |
0c96007e AM |
5272 | (define_expand "eh_epilogue" |
5273 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5274 | (use (match_operand:DI 1 "register_operand" "r")) | |
5275 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5276 | "" | |
0c96007e AM |
5277 | { |
5278 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5279 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5280 | ||
5281 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5282 | { | |
5283 | emit_move_insn (bsp, operands[0]); | |
5284 | operands[0] = bsp; | |
5285 | } | |
5286 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5287 | { | |
5288 | emit_move_insn (sp, operands[2]); | |
5289 | operands[2] = sp; | |
5290 | } | |
5291 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5292 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5293 | ||
5294 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5295 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5296 | }) |
9525c690 JW |
5297 | \f |
5298 | ;; Builtin apply support. | |
5299 | ||
5300 | (define_expand "restore_stack_nonlocal" | |
5301 | [(use (match_operand:DI 0 "register_operand" "")) | |
5302 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5303 | "" | |
9525c690 JW |
5304 | { |
5305 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5306 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
5307 | 0, VOIDmode, 1, |
5308 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5309 | DONE; | |
1d5d7a21 | 5310 | }) |
9525c690 JW |
5311 | |
5312 | \f | |
5313 | ;;; Intrinsics support. | |
c65ebc55 | 5314 | |
0551c32d RH |
5315 | (define_expand "mf" |
5316 | [(set (mem:BLK (match_dup 0)) | |
086c0f96 | 5317 | (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))] |
0551c32d | 5318 | "" |
0551c32d RH |
5319 | { |
5320 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
5321 | MEM_VOLATILE_P (operands[0]) = 1; | |
1d5d7a21 | 5322 | }) |
0551c32d RH |
5323 | |
5324 | (define_insn "*mf_internal" | |
5325 | [(set (match_operand:BLK 0 "" "") | |
086c0f96 | 5326 | (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))] |
c65ebc55 JW |
5327 | "" |
5328 | "mf" | |
52e12ad0 | 5329 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
5330 | |
5331 | (define_insn "fetchadd_acq_si" | |
0551c32d RH |
5332 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5333 | (match_dup 1)) | |
5334 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5335 | (unspec:SI [(match_dup 1) | |
086c0f96 RH |
5336 | (match_operand:SI 2 "fetchadd_operand" "n")] |
5337 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
5338 | "" |
5339 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 5340 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5341 | |
5342 | (define_insn "fetchadd_acq_di" | |
0551c32d RH |
5343 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5344 | (match_dup 1)) | |
5345 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5346 | (unspec:DI [(match_dup 1) | |
086c0f96 RH |
5347 | (match_operand:DI 2 "fetchadd_operand" "n")] |
5348 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
5349 | "" |
5350 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 5351 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5352 | |
5353 | (define_insn "cmpxchg_acq_si" | |
0551c32d RH |
5354 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5355 | (match_dup 1)) | |
5356 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5357 | (unspec:SI [(match_dup 1) | |
5358 | (match_operand:SI 2 "gr_register_operand" "r") | |
086c0f96 RH |
5359 | (match_operand:SI 3 "ar_ccv_reg_operand" "")] |
5360 | UNSPEC_CMPXCHG_ACQ))] | |
c65ebc55 | 5361 | "" |
97e242b0 | 5362 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 5363 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5364 | |
5365 | (define_insn "cmpxchg_acq_di" | |
0551c32d RH |
5366 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5367 | (match_dup 1)) | |
5368 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5369 | (unspec:DI [(match_dup 1) | |
5370 | (match_operand:DI 2 "gr_register_operand" "r") | |
086c0f96 RH |
5371 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] |
5372 | UNSPEC_CMPXCHG_ACQ))] | |
c65ebc55 | 5373 | "" |
97e242b0 | 5374 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 5375 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 5376 | |
c65ebc55 | 5377 | (define_insn "xchgsi" |
0551c32d RH |
5378 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5379 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5380 | (set (match_dup 1) |
0551c32d | 5381 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5382 | "" |
5383 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 5384 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5385 | |
5386 | (define_insn "xchgdi" | |
0551c32d RH |
5387 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5388 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5389 | (set (match_dup 1) |
0551c32d | 5390 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5391 | "" |
5392 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 5393 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
5394 | \f |
5395 | ;; Predication. | |
5396 | ||
5397 | (define_cond_exec | |
5398 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5399 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5400 | (const_int 0)])] |
5401 | "" | |
5402 | "(%J0)") | |
3b572406 RH |
5403 | |
5404 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 5405 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 5406 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 5407 | "" |
054451ea | 5408 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5409 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5410 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5411 | |
5412 | (define_insn "safe_across_calls_all" | |
086c0f96 | 5413 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
5414 | "" |
5415 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5416 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5417 | (set_attr "predicable" "no")]) |
5418 | ||
5419 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 5420 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 5421 | "" |
ca3920ad JW |
5422 | { |
5423 | emit_safe_across_calls (asm_out_file); | |
1d5d7a21 RH |
5424 | return ""; |
5425 | } | |
52e12ad0 | 5426 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5427 | (set_attr "predicable" "no")]) |
5428 | ||
6dd12198 SE |
5429 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit |
5430 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
5431 | ||
5432 | (define_insn "ptr_extend" | |
5433 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
5434 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
5435 | UNSPEC_ADDP4))] | |
6dd12198 SE |
5436 | "" |
5437 | "addp4 %0 = 0,%1" | |
5438 | [(set_attr "itanium_class" "ialu")]) | |
5439 | ||
e206a74f SE |
5440 | ;; |
5441 | ;; Optimizations for ptr_extend | |
5442 | ||
5443 | (define_insn "*ptr_extend_plus_1" | |
5444 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5445 | (unspec:DI | |
5446 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5447 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 5448 | UNSPEC_ADDP4))] |
e206a74f SE |
5449 | "" |
5450 | "addp4 %0 = %2, %1" | |
5451 | [(set_attr "itanium_class" "ialu")]) | |
5452 | ||
5453 | (define_insn "*ptr_extend_plus_2" | |
5454 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5455 | (unspec:DI | |
5456 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5457 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 5458 | UNSPEC_ADDP4))] |
e206a74f SE |
5459 | "" |
5460 | "addp4 %0 = %1, %2" | |
5461 | [(set_attr "itanium_class" "ialu")]) |