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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
5b86a469 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 JW |
10 | ;; it under the terms of the GNU General Public License as published by |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
3bed2930 | 20 | ;; along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
21 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
22 | ;; Boston, MA 02110-1301, USA. | |
c65ebc55 JW |
23 | |
24 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
25 | ||
c65ebc55 JW |
26 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
27 | ;; reload. This will be fixed once scheduling support is turned on. | |
28 | ||
29 | ;; ??? Optimize for post-increment addressing modes. | |
30 | ||
31 | ;; ??? fselect is not supported, because there is no integer register | |
32 | ;; equivalent. | |
33 | ||
34 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
35 | ||
36 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
37 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
38 | ||
39 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
40 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
41 | ||
42 | ;; ??? Go through list of documented named patterns and look for more to | |
43 | ;; implement. | |
44 | ||
45 | ;; ??? Go through instruction manual and look for more instructions that | |
46 | ;; can be emitted. | |
47 | ||
48 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
49 | ||
26102535 RH |
50 | ;; ??? Need a better way to describe alternate fp status registers. |
51 | ||
086c0f96 | 52 | (define_constants |
7b6e506e RH |
53 | [; Relocations |
54 | (UNSPEC_LTOFF_DTPMOD 0) | |
55 | (UNSPEC_LTOFF_DTPREL 1) | |
56 | (UNSPEC_DTPREL 2) | |
57 | (UNSPEC_LTOFF_TPREL 3) | |
58 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 59 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
60 | |
61 | (UNSPEC_LD_BASE 9) | |
62 | (UNSPEC_GR_SPILL 10) | |
63 | (UNSPEC_GR_RESTORE 11) | |
64 | (UNSPEC_FR_SPILL 12) | |
65 | (UNSPEC_FR_RESTORE 13) | |
66 | (UNSPEC_FR_RECIP_APPROX 14) | |
67 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 68 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
69 | (UNSPEC_PIC_CALL 17) |
70 | (UNSPEC_MF 18) | |
71 | (UNSPEC_CMPXCHG_ACQ 19) | |
72 | (UNSPEC_FETCHADD_ACQ 20) | |
73 | (UNSPEC_BSP_VALUE 21) | |
74 | (UNSPEC_FLUSHRS 22) | |
75 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
76 | (UNSPEC_ADDP4 24) |
77 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 78 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
79 | (UNSPEC_SETF_EXP 27) |
80 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 81 | (UNSPEC_SHRP 29) |
046625fa | 82 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 83 | (UNSPEC_VECT_EXTR 31) |
086c0f96 RH |
84 | ]) |
85 | ||
86 | (define_constants | |
87 | [(UNSPECV_ALLOC 0) | |
88 | (UNSPECV_BLOCKAGE 1) | |
89 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
90 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
91 | (UNSPECV_SET_BSP 4) |
92 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
93 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 94 | (UNSPECV_SETJMP_RECEIVER 7) |
086c0f96 | 95 | ]) |
e543e219 | 96 | |
7905f799 | 97 | (include "predicates.md") |
c65ebc55 JW |
98 | \f |
99 | ;; :::::::::::::::::::: | |
100 | ;; :: | |
101 | ;; :: Attributes | |
102 | ;; :: | |
103 | ;; :::::::::::::::::::: | |
104 | ||
30028c85 VM |
105 | ;; Processor type. This attribute must exactly match the processor_type |
106 | ;; enumeration in ia64.h. | |
107 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
108 | ||
c65ebc55 JW |
109 | ;; Instruction type. This primarily determines how instructions can be |
110 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
111 | ||
112 | ;; A alu, can go in I or M syllable of a bundle | |
113 | ;; I integer | |
114 | ;; M memory | |
115 | ;; F floating-point | |
116 | ;; B branch | |
117 | ;; L long immediate, takes two syllables | |
118 | ;; S stop bit | |
119 | ||
120 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
121 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
122 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
123 | ;; which emit instruction that can go in any slot (e.g. nop). | |
124 | ||
1d5d7a21 | 125 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b JB |
126 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
127 | ld,chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, | |
f61134e8 RH |
128 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
129 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 130 | (const_string "unknown")) |
52e12ad0 | 131 | |
2130b7fb BS |
132 | ;; chk_s has an I and an M form; use type A for convenience. |
133 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
a71aef0b | 134 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
135 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
136 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 137 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
f61134e8 RH |
138 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua") |
139 | (const_string "A") | |
2130b7fb BS |
140 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
141 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
142 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
143 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
144 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
145 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 146 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 147 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
148 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
149 | (const_string "unknown"))) | |
c65ebc55 | 150 | |
2130b7fb BS |
151 | (define_attr "itanium_requires_unit0" "no,yes" |
152 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
153 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
154 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
155 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
156 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
157 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
158 | (const_string "no"))) | |
159 | ||
e5bde68a RH |
160 | ;; Predication. True iff this instruction can be predicated. |
161 | ||
162 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
163 | ||
fa978426 AS |
164 | ;; Empty. True iff this insn does not generate any code. |
165 | ||
166 | (define_attr "empty" "no,yes" (const_string "no")) | |
167 | ||
68e11b42 JW |
168 | ;; True iff this insn must be the first insn of an instruction group. |
169 | ;; This is true for the alloc instruction, and will also be true of others | |
170 | ;; when we have full intrinsics support. | |
171 | ||
172 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
c65ebc55 | 173 | \f |
30028c85 VM |
174 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
175 | ;; bundling. | |
176 | ||
177 | (automata_option "ndfa") | |
178 | ||
179 | ;; Uncomment the following line to output automata for debugging. | |
180 | ;; (automata_option "v") | |
181 | ||
182 | (automata_option "w") | |
183 | ||
30028c85 VM |
184 | (include "itanium1.md") |
185 | (include "itanium2.md") | |
186 | ||
c65ebc55 JW |
187 | \f |
188 | ;; :::::::::::::::::::: | |
189 | ;; :: | |
190 | ;; :: Moves | |
191 | ;; :: | |
192 | ;; :::::::::::::::::::: | |
193 | ||
f2f90c63 RH |
194 | ;; Set of a single predicate register. This is only used to implement |
195 | ;; pr-to-pr move and complement. | |
196 | ||
197 | (define_insn "*movcci" | |
198 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
199 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
200 | "" | |
201 | "@ | |
202 | cmp.ne %0, p0 = r0, r0 | |
203 | cmp.eq %0, p0 = r0, r0 | |
204 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 205 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
206 | (set_attr "predicable" "no")]) |
207 | ||
208 | (define_insn "movbi" | |
cd5c4048 RH |
209 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
210 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
211 | "" |
212 | "@ | |
213 | cmp.ne %0, %I0 = r0, r0 | |
214 | cmp.eq %0, %I0 = r0, r0 | |
215 | # | |
216 | # | |
217 | tbit.nz %0, %I0 = %1, 0 | |
218 | adds %0 = %1, r0 | |
219 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
220 | st1%Q0 %0 = %1%P0 |
221 | mov %0 = %1" | |
52e12ad0 | 222 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
223 | |
224 | (define_split | |
225 | [(set (match_operand:BI 0 "register_operand" "") | |
226 | (match_operand:BI 1 "register_operand" ""))] | |
227 | "reload_completed | |
228 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
229 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
230 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
231 | (set (match_dup 0) (const_int 1))) | |
232 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
233 | (set (match_dup 0) (const_int 0)))] | |
234 | "") | |
235 | ||
236 | (define_split | |
237 | [(set (match_operand:BI 0 "register_operand" "") | |
238 | (match_operand:BI 1 "register_operand" ""))] | |
239 | "reload_completed | |
240 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
241 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
242 | [(set (match_dup 2) (match_dup 4)) | |
243 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 244 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
245 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
246 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
247 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
248 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
249 | ||
c65ebc55 JW |
250 | (define_expand "movqi" |
251 | [(set (match_operand:QI 0 "general_operand" "") | |
252 | (match_operand:QI 1 "general_operand" ""))] | |
253 | "" | |
c65ebc55 | 254 | { |
7b6e506e RH |
255 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
256 | if (!op1) | |
257 | DONE; | |
258 | operands[1] = op1; | |
1d5d7a21 | 259 | }) |
c65ebc55 JW |
260 | |
261 | (define_insn "*movqi_internal" | |
4b983fdc RH |
262 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
263 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 264 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 265 | "@ |
13da91fd | 266 | mov %0 = %r1 |
c65ebc55 JW |
267 | addl %0 = %1, r0 |
268 | ld1%O1 %0 = %1%P1 | |
13da91fd | 269 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 270 | getf.sig %0 = %1 |
13da91fd RH |
271 | setf.sig %0 = %r1 |
272 | mov %0 = %1" | |
52e12ad0 | 273 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
274 | |
275 | (define_expand "movhi" | |
276 | [(set (match_operand:HI 0 "general_operand" "") | |
277 | (match_operand:HI 1 "general_operand" ""))] | |
278 | "" | |
c65ebc55 | 279 | { |
7b6e506e RH |
280 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
281 | if (!op1) | |
282 | DONE; | |
283 | operands[1] = op1; | |
1d5d7a21 | 284 | }) |
c65ebc55 JW |
285 | |
286 | (define_insn "*movhi_internal" | |
4b983fdc RH |
287 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
288 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 289 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 290 | "@ |
13da91fd | 291 | mov %0 = %r1 |
c65ebc55 JW |
292 | addl %0 = %1, r0 |
293 | ld2%O1 %0 = %1%P1 | |
13da91fd | 294 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 295 | getf.sig %0 = %1 |
13da91fd RH |
296 | setf.sig %0 = %r1 |
297 | mov %0 = %1" | |
52e12ad0 | 298 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
299 | |
300 | (define_expand "movsi" | |
301 | [(set (match_operand:SI 0 "general_operand" "") | |
302 | (match_operand:SI 1 "general_operand" ""))] | |
303 | "" | |
c65ebc55 | 304 | { |
7b6e506e RH |
305 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
306 | if (!op1) | |
307 | DONE; | |
308 | operands[1] = op1; | |
1d5d7a21 | 309 | }) |
c65ebc55 JW |
310 | |
311 | (define_insn "*movsi_internal" | |
97e242b0 | 312 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 313 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 314 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 315 | "@ |
13da91fd | 316 | mov %0 = %r1 |
c65ebc55 JW |
317 | addl %0 = %1, r0 |
318 | movl %0 = %1 | |
319 | ld4%O1 %0 = %1%P1 | |
13da91fd | 320 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 321 | getf.sig %0 = %1 |
13da91fd | 322 | setf.sig %0 = %r1 |
97e242b0 RH |
323 | mov %0 = %1 |
324 | mov %0 = %1 | |
325 | mov %0 = %r1" | |
1d5d7a21 | 326 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 327 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
328 | |
329 | (define_expand "movdi" | |
330 | [(set (match_operand:DI 0 "general_operand" "") | |
331 | (match_operand:DI 1 "general_operand" ""))] | |
332 | "" | |
c65ebc55 | 333 | { |
7b6e506e RH |
334 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
335 | if (!op1) | |
336 | DONE; | |
337 | operands[1] = op1; | |
1d5d7a21 | 338 | }) |
c65ebc55 | 339 | |
c65ebc55 | 340 | (define_insn "*movdi_internal" |
4b983fdc | 341 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 342 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 343 | (match_operand:DI 1 "move_operand" |
a32767e4 | 344 | "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 345 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
346 | { |
347 | static const char * const alt[] = { | |
1d5d7a21 RH |
348 | "%,mov %0 = %r1", |
349 | "%,addl %0 = %1, r0", | |
350 | "%,movl %0 = %1", | |
351 | "%,ld8%O1 %0 = %1%P1", | |
352 | "%,st8%Q0 %0 = %r1%P0", | |
353 | "%,getf.sig %0 = %1", | |
354 | "%,setf.sig %0 = %r1", | |
355 | "%,mov %0 = %1", | |
356 | "%,ldf8 %0 = %1%P1", | |
357 | "%,stf8 %0 = %1%P0", | |
358 | "%,mov %0 = %1", | |
359 | "%,mov %0 = %r1", | |
360 | "%,mov %0 = %1", | |
361 | "%,mov %0 = %1", | |
362 | "%,mov %0 = %1", | |
363 | "%,mov %0 = %1", | |
364 | "mov %0 = pr", | |
365 | "mov pr = %1, -1" | |
9b7bf67d RH |
366 | }; |
367 | ||
e820471b NS |
368 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
369 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
370 | |
371 | return alt[which_alternative]; | |
1d5d7a21 | 372 | } |
52e12ad0 | 373 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 374 | |
9b7bf67d | 375 | (define_split |
21515593 RH |
376 | [(set (match_operand 0 "register_operand" "") |
377 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 378 | "reload_completed" |
9b7bf67d | 379 | [(const_int 0)] |
9b7bf67d | 380 | { |
5e6c8b64 RH |
381 | if (ia64_expand_load_address (operands[0], operands[1])) |
382 | DONE; | |
383 | else | |
384 | FAIL; | |
1d5d7a21 | 385 | }) |
9b7bf67d | 386 | |
c65ebc55 | 387 | (define_expand "load_fptr" |
5e6c8b64 RH |
388 | [(set (match_operand:DI 0 "register_operand" "") |
389 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
390 | (set (match_dup 0) (match_dup 3))] | |
391 | "reload_completed" | |
c65ebc55 | 392 | { |
5e6c8b64 RH |
393 | operands[2] = pic_offset_table_rtx; |
394 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 395 | }) |
c65ebc55 JW |
396 | |
397 | (define_insn "*load_fptr_internal1" | |
398 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 399 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 400 | "reload_completed" |
c65ebc55 | 401 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 402 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
403 | |
404 | (define_insn "load_gprel" | |
405 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 406 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 407 | "reload_completed" |
c65ebc55 | 408 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 409 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 410 | |
5e6c8b64 | 411 | (define_insn "*gprel64_offset" |
59da9a7d JW |
412 | [(set (match_operand:DI 0 "register_operand" "=r") |
413 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 414 | "reload_completed" |
59da9a7d | 415 | "movl %0 = @gprel(%1)" |
52e12ad0 | 416 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
417 | |
418 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
419 | [(set (match_operand:DI 0 "register_operand" "") |
420 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
421 | (set (match_dup 0) | |
422 | (plus:DI (match_dup 2) (match_dup 0)))] | |
423 | "reload_completed" | |
ec039e3c | 424 | { |
5e6c8b64 | 425 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 426 | }) |
59da9a7d | 427 | |
af1e5518 RH |
428 | ;; This is used as a placeholder for the return address during early |
429 | ;; compilation. We won't know where we've placed this until during | |
430 | ;; reload, at which point it can wind up in b0, a general register, | |
431 | ;; or memory. The only safe destination under these conditions is a | |
432 | ;; general register. | |
433 | ||
434 | (define_insn_and_split "*movdi_ret_addr" | |
435 | [(set (match_operand:DI 0 "register_operand" "=r") | |
436 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
437 | "" | |
438 | "#" | |
439 | "reload_completed" | |
440 | [(const_int 0)] | |
441 | { | |
442 | ia64_split_return_addr_rtx (operands[0]); | |
443 | DONE; | |
444 | } | |
445 | [(set_attr "itanium_class" "ialu")]) | |
446 | ||
ef1ecf87 | 447 | (define_insn "*load_symptr_high" |
c65ebc55 | 448 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
449 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
450 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 451 | "reload_completed" |
ef1ecf87 RH |
452 | { |
453 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
454 | return "%,addl %0 = @ltoffx(%1), %2"; | |
455 | else | |
456 | return "%,addl %0 = @ltoff(%1), %2"; | |
457 | } | |
52e12ad0 | 458 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 459 | |
ef1ecf87 RH |
460 | (define_insn "*load_symptr_low" |
461 | [(set (match_operand:DI 0 "register_operand" "=r") | |
462 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
463 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 464 | "reload_completed" |
ef1ecf87 RH |
465 | { |
466 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
467 | return "%,ld8.mov %0 = [%1], %2"; | |
468 | else | |
469 | return "%,ld8 %0 = [%1]"; | |
470 | } | |
471 | [(set_attr "itanium_class" "ld")]) | |
472 | ||
5e6c8b64 | 473 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 474 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 475 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 476 | UNSPEC_DTPMOD))] |
7b6e506e | 477 | "" |
5e6c8b64 RH |
478 | "#" |
479 | "reload_completed" | |
480 | [(set (match_dup 0) | |
481 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
482 | (match_dup 2))) | |
483 | (set (match_dup 0) (match_dup 3))] | |
484 | { | |
485 | operands[2] = pic_offset_table_rtx; | |
486 | operands[3] = gen_const_mem (DImode, operands[0]); | |
487 | }) | |
7b6e506e | 488 | |
5e6c8b64 | 489 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 490 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 491 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
492 | UNSPEC_LTOFF_DTPMOD) |
493 | (match_operand:DI 2 "register_operand" "a")))] | |
494 | "reload_completed" | |
495 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
496 | [(set_attr "itanium_class" "ialu")]) |
497 | ||
498 | (define_expand "load_dtprel" | |
499 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 500 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
501 | UNSPEC_DTPREL))] |
502 | "" | |
503 | "") | |
504 | ||
505 | (define_insn "*load_dtprel64" | |
506 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 507 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
508 | UNSPEC_DTPREL))] |
509 | "TARGET_TLS64" | |
510 | "movl %0 = @dtprel(%1)" | |
511 | [(set_attr "itanium_class" "long_i")]) | |
512 | ||
513 | (define_insn "*load_dtprel22" | |
514 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 515 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
516 | UNSPEC_DTPREL))] |
517 | "" | |
518 | "addl %0 = @dtprel(%1), r0" | |
519 | [(set_attr "itanium_class" "ialu")]) | |
520 | ||
5e6c8b64 RH |
521 | (define_insn_and_split "*load_dtprel_gd" |
522 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 523 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
524 | UNSPEC_DTPREL))] |
525 | "" | |
526 | "#" | |
527 | "reload_completed" | |
528 | [(set (match_dup 0) | |
529 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
530 | (match_dup 2))) | |
531 | (set (match_dup 0) (match_dup 3))] | |
532 | { | |
533 | operands[2] = pic_offset_table_rtx; | |
534 | operands[3] = gen_const_mem (DImode, operands[0]); | |
535 | }) | |
536 | ||
537 | (define_insn "*load_ltoff_dtprel" | |
538 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 539 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
540 | UNSPEC_LTOFF_DTPREL) |
541 | (match_operand:DI 2 "register_operand" "a")))] | |
542 | "" | |
543 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
544 | [(set_attr "itanium_class" "ialu")]) | |
545 | ||
7b6e506e RH |
546 | (define_expand "add_dtprel" |
547 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 548 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
549 | UNSPEC_DTPREL) |
550 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
551 | "!TARGET_TLS64" |
552 | "") | |
553 | ||
554 | (define_insn "*add_dtprel14" | |
555 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 556 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
557 | UNSPEC_DTPREL) |
558 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 559 | "TARGET_TLS14" |
5e6c8b64 | 560 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
561 | [(set_attr "itanium_class" "ialu")]) |
562 | ||
563 | (define_insn "*add_dtprel22" | |
564 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 565 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
566 | UNSPEC_DTPREL) |
567 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 568 | "TARGET_TLS22" |
5e6c8b64 | 569 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
570 | [(set_attr "itanium_class" "ialu")]) |
571 | ||
572 | (define_expand "load_tprel" | |
573 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 574 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
575 | UNSPEC_TPREL))] |
576 | "" | |
577 | "") | |
578 | ||
579 | (define_insn "*load_tprel64" | |
580 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 581 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
582 | UNSPEC_TPREL))] |
583 | "TARGET_TLS64" | |
584 | "movl %0 = @tprel(%1)" | |
585 | [(set_attr "itanium_class" "long_i")]) | |
586 | ||
587 | (define_insn "*load_tprel22" | |
588 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 589 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
590 | UNSPEC_TPREL))] |
591 | "" | |
592 | "addl %0 = @tprel(%1), r0" | |
593 | [(set_attr "itanium_class" "ialu")]) | |
594 | ||
5e6c8b64 RH |
595 | (define_insn_and_split "*load_tprel_ie" |
596 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 597 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
598 | UNSPEC_TPREL))] |
599 | "" | |
600 | "#" | |
601 | "reload_completed" | |
602 | [(set (match_dup 0) | |
603 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
604 | (match_dup 2))) | |
605 | (set (match_dup 0) (match_dup 3))] | |
606 | { | |
607 | operands[2] = pic_offset_table_rtx; | |
608 | operands[3] = gen_const_mem (DImode, operands[0]); | |
609 | }) | |
610 | ||
611 | (define_insn "*load_ltoff_tprel" | |
612 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 613 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
614 | UNSPEC_LTOFF_TPREL) |
615 | (match_operand:DI 2 "register_operand" "a")))] | |
616 | "" | |
617 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
618 | [(set_attr "itanium_class" "ialu")]) | |
619 | ||
7b6e506e RH |
620 | (define_expand "add_tprel" |
621 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 622 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
623 | UNSPEC_TPREL) |
624 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
625 | "!TARGET_TLS64" |
626 | "") | |
627 | ||
628 | (define_insn "*add_tprel14" | |
629 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 630 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
631 | UNSPEC_TPREL) |
632 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 633 | "TARGET_TLS14" |
5e6c8b64 | 634 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
635 | [(set_attr "itanium_class" "ialu")]) |
636 | ||
637 | (define_insn "*add_tprel22" | |
638 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 639 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
640 | UNSPEC_TPREL) |
641 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 642 | "TARGET_TLS22" |
5e6c8b64 | 643 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
644 | [(set_attr "itanium_class" "ialu")]) |
645 | ||
3f622353 | 646 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
647 | ;; around to play with the second word. However, in order to avoid a |
648 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
649 | ;; in ia64_split_tmode_move. | |
3f622353 | 650 | (define_expand "movti" |
2ffe0e02 ZW |
651 | [(set (match_operand:TI 0 "general_operand" "") |
652 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 653 | "" |
3f622353 | 654 | { |
7b6e506e RH |
655 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
656 | if (!op1) | |
657 | DONE; | |
658 | operands[1] = op1; | |
1d5d7a21 | 659 | }) |
3f622353 RH |
660 | |
661 | (define_insn_and_split "*movti_internal" | |
a71aef0b JB |
662 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r, *fm,*x,*f, Q") |
663 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 664 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
665 | "@ |
666 | # | |
667 | # | |
668 | ldfp8 %X0 = %1%P1 | |
669 | # | |
670 | #" | |
671 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 672 | [(const_int 0)] |
3f622353 | 673 | { |
f57fc998 | 674 | ia64_split_tmode_move (operands); |
3f622353 | 675 | DONE; |
1d5d7a21 | 676 | } |
a71aef0b | 677 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")]) |
e314e331 | 678 | |
c65ebc55 JW |
679 | ;; Floating Point Moves |
680 | ;; | |
681 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 682 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
683 | |
684 | (define_expand "movsf" | |
685 | [(set (match_operand:SF 0 "general_operand" "") | |
686 | (match_operand:SF 1 "general_operand" ""))] | |
687 | "" | |
c65ebc55 | 688 | { |
7b6e506e RH |
689 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
690 | if (!op1) | |
691 | DONE; | |
692 | operands[1] = op1; | |
1d5d7a21 | 693 | }) |
c65ebc55 | 694 | |
c65ebc55 | 695 | (define_insn "*movsf_internal" |
4b983fdc RH |
696 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
697 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 698 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 699 | "@ |
1d5d7a21 RH |
700 | mov %0 = %F1 |
701 | ldfs %0 = %1%P1 | |
702 | stfs %0 = %F1%P0 | |
703 | getf.s %0 = %F1 | |
704 | setf.s %0 = %1 | |
705 | mov %0 = %1 | |
706 | ld4%O1 %0 = %1%P1 | |
707 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 708 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
709 | |
710 | (define_expand "movdf" | |
711 | [(set (match_operand:DF 0 "general_operand" "") | |
712 | (match_operand:DF 1 "general_operand" ""))] | |
713 | "" | |
c65ebc55 | 714 | { |
7b6e506e RH |
715 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
716 | if (!op1) | |
717 | DONE; | |
718 | operands[1] = op1; | |
1d5d7a21 | 719 | }) |
c65ebc55 | 720 | |
c65ebc55 | 721 | (define_insn "*movdf_internal" |
4b983fdc RH |
722 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
723 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 724 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 725 | "@ |
1d5d7a21 RH |
726 | mov %0 = %F1 |
727 | ldfd %0 = %1%P1 | |
728 | stfd %0 = %F1%P0 | |
729 | getf.d %0 = %F1 | |
730 | setf.d %0 = %1 | |
731 | mov %0 = %1 | |
732 | ld8%O1 %0 = %1%P1 | |
733 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 734 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 735 | |
3f622353 RH |
736 | ;; With no offsettable memory references, we've got to have a scratch |
737 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
738 | (define_expand "movxf" |
739 | [(set (match_operand:XF 0 "general_operand" "") | |
740 | (match_operand:XF 1 "general_operand" ""))] | |
741 | "" | |
e5bde68a | 742 | { |
4de67c26 JM |
743 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
744 | DONE; | |
1d5d7a21 | 745 | }) |
e5bde68a | 746 | |
3b572406 | 747 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 748 | |
02befdf4 | 749 | (define_insn "*movxf_internal" |
78d8e0f9 ZW |
750 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
751 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 752 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 753 | "@ |
1d5d7a21 RH |
754 | mov %0 = %F1 |
755 | ldfe %0 = %1%P1 | |
756 | stfe %0 = %F1%P0" | |
52e12ad0 | 757 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
f57fc998 | 758 | |
4de67c26 JM |
759 | ;; Same as for movxf, but for RFmode. |
760 | (define_expand "movrf" | |
761 | [(set (match_operand:RF 0 "general_operand" "") | |
762 | (match_operand:RF 1 "general_operand" ""))] | |
763 | "" | |
764 | { | |
765 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
766 | DONE; | |
767 | }) | |
768 | ||
769 | (define_insn "*movrf_internal" | |
770 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
771 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
772 | "ia64_move_ok (operands[0], operands[1])" | |
773 | "@ | |
774 | mov %0 = %F1 | |
775 | ldf.fill %0 = %1%P1 | |
776 | stf.spill %0 = %F1%P0" | |
777 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
778 | ||
f57fc998 | 779 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 780 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 781 | (define_expand "movtf" |
2ffe0e02 ZW |
782 | [(set (match_operand:TF 0 "general_operand" "") |
783 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
784 | "" |
785 | { | |
786 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
787 | if (!op1) | |
788 | DONE; | |
789 | operands[1] = op1; | |
790 | }) | |
791 | ||
792 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 793 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 794 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
795 | "ia64_move_ok (operands[0], operands[1])" |
796 | "#" | |
797 | "reload_completed" | |
798 | [(const_int 0)] | |
799 | { | |
800 | ia64_split_tmode_move (operands); | |
801 | DONE; | |
802 | } | |
803 | [(set_attr "itanium_class" "unknown") | |
804 | (set_attr "predicable" "no")]) | |
805 | ||
c65ebc55 JW |
806 | \f |
807 | ;; :::::::::::::::::::: | |
808 | ;; :: | |
809 | ;; :: Conversions | |
810 | ;; :: | |
811 | ;; :::::::::::::::::::: | |
812 | ||
813 | ;; Signed conversions from a smaller integer to a larger integer | |
814 | ||
815 | (define_insn "extendqidi2" | |
0551c32d RH |
816 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
817 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
818 | "" |
819 | "sxt1 %0 = %1" | |
52e12ad0 | 820 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
821 | |
822 | (define_insn "extendhidi2" | |
0551c32d RH |
823 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
824 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
825 | "" |
826 | "sxt2 %0 = %1" | |
52e12ad0 | 827 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
828 | |
829 | (define_insn "extendsidi2" | |
655f2eb9 RH |
830 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
831 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
832 | "" |
833 | "@ | |
834 | sxt4 %0 = %1 | |
aebf2462 | 835 | fsxt.r %0 = %1, %1" |
52e12ad0 | 836 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
837 | |
838 | ;; Unsigned conversions from a smaller integer to a larger integer | |
839 | ||
840 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
841 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
842 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
843 | "" |
844 | "@ | |
845 | zxt1 %0 = %1 | |
846 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 847 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
848 | |
849 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
850 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
851 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
852 | "" |
853 | "@ | |
854 | zxt2 %0 = %1 | |
855 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 856 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
857 | |
858 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 859 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 860 | (zero_extend:DI |
655f2eb9 | 861 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
862 | "" |
863 | "@ | |
d3f6e07b | 864 | addp4 %0 = %1, r0 |
c65ebc55 | 865 | ld4%O1 %0 = %1%P1 |
aebf2462 | 866 | fmix.r %0 = f0, %1" |
d3f6e07b | 867 | [(set_attr "itanium_class" "ialu,ld,fmisc")]) |
c65ebc55 JW |
868 | |
869 | ;; Convert between floating point types of different sizes. | |
870 | ||
640cea5f JW |
871 | ;; At first glance, it would appear that emitting fnorm for an extending |
872 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
873 | ;; correctly only if the input is properly rounded for its type. In | |
874 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
875 | ;; denorm single. Since we don't know what the next instruction will be, we | |
876 | ;; have to emit an fnorm. | |
877 | ||
e8e20f18 RH |
878 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
879 | ;; when we can. Should probably use a scheme like has been proposed | |
880 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
881 | ;; would let combine merge the thing into adjacent insns. See also how the |
882 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
883 | ;; se_register_operand. | |
c65ebc55 | 884 | |
640cea5f JW |
885 | (define_insn "extendsfdf2" |
886 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
887 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 888 | "" |
640cea5f JW |
889 | "fnorm.d %0 = %1" |
890 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 891 | |
02befdf4 ZW |
892 | (define_insn "extendsfxf2" |
893 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
894 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
895 | "" | |
640cea5f JW |
896 | "fnorm %0 = %1" |
897 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 898 | |
02befdf4 ZW |
899 | (define_insn "extenddfxf2" |
900 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
901 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
902 | "" | |
640cea5f JW |
903 | "fnorm %0 = %1" |
904 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 905 | |
c65ebc55 | 906 | (define_insn "truncdfsf2" |
0551c32d RH |
907 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
908 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 909 | "" |
aebf2462 | 910 | "fnorm.s %0 = %1" |
52e12ad0 | 911 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 912 | |
02befdf4 | 913 | (define_insn "truncxfsf2" |
0551c32d | 914 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
915 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
916 | "" | |
aebf2462 | 917 | "fnorm.s %0 = %1" |
52e12ad0 | 918 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 919 | |
02befdf4 | 920 | (define_insn "truncxfdf2" |
0551c32d | 921 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
922 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
923 | "" | |
aebf2462 | 924 | "fnorm.d %0 = %1" |
52e12ad0 | 925 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
926 | |
927 | ;; Convert between signed integer types and floating point. | |
928 | ||
02befdf4 ZW |
929 | (define_insn "floatdixf2" |
930 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
931 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
932 | "" | |
e5bde68a | 933 | "fcvt.xf %0 = %1" |
52e12ad0 | 934 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
935 | |
936 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
937 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
938 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 939 | "" |
aebf2462 | 940 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 941 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
942 | |
943 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
944 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
945 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 946 | "" |
aebf2462 | 947 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 948 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 949 | |
02befdf4 | 950 | (define_insn "fix_truncxfdi2" |
0551c32d | 951 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
952 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
953 | "" | |
aebf2462 | 954 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 955 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 956 | |
02befdf4 | 957 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 958 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 959 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 960 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 961 | "" |
aebf2462 | 962 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 963 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 964 | |
c65ebc55 JW |
965 | ;; Convert between unsigned integer types and floating point. |
966 | ||
967 | (define_insn "floatunsdisf2" | |
0551c32d RH |
968 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
969 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 970 | "" |
aebf2462 | 971 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 972 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
973 | |
974 | (define_insn "floatunsdidf2" | |
0551c32d RH |
975 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
976 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 977 | "" |
aebf2462 | 978 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 979 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 980 | |
02befdf4 ZW |
981 | (define_insn "floatunsdixf2" |
982 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
983 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
984 | "" | |
aebf2462 | 985 | "fcvt.xuf %0 = %1" |
52e12ad0 | 986 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 987 | |
c65ebc55 | 988 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
989 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
990 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 991 | "" |
aebf2462 | 992 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 993 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
994 | |
995 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
996 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
997 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 998 | "" |
aebf2462 | 999 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1000 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1001 | |
02befdf4 | 1002 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1003 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1004 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1005 | "" | |
aebf2462 | 1006 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1007 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1008 | |
02befdf4 | 1009 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1010 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1011 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1012 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1013 | "" |
aebf2462 | 1014 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1015 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1016 | \f |
1017 | ;; :::::::::::::::::::: | |
1018 | ;; :: | |
1019 | ;; :: Bit field extraction | |
1020 | ;; :: | |
1021 | ;; :::::::::::::::::::: | |
1022 | ||
c65ebc55 | 1023 | (define_insn "extv" |
0551c32d RH |
1024 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1025 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1026 | (match_operand:DI 2 "const_int_operand" "n") |
1027 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1028 | "" | |
1029 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1030 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1031 | |
1032 | (define_insn "extzv" | |
0551c32d RH |
1033 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1034 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1035 | (match_operand:DI 2 "const_int_operand" "n") |
1036 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1037 | "" | |
1038 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1039 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1040 | |
1041 | ;; Insert a bit field. | |
1042 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1043 | ;; Source1 can be 0 or -1. | |
1044 | ;; Source2 can be 0. | |
1045 | ||
1046 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1047 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1048 | ;; where source2 != dest. | |
1049 | ||
1050 | (define_expand "insv" | |
0551c32d | 1051 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1052 | (match_operand:DI 1 "const_int_operand" "") |
1053 | (match_operand:DI 2 "const_int_operand" "")) | |
1054 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1055 | "" | |
c65ebc55 JW |
1056 | { |
1057 | int width = INTVAL (operands[1]); | |
1058 | int shift = INTVAL (operands[2]); | |
1059 | ||
1060 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1061 | pseudo. */ | |
1062 | if (! register_operand (operands[3], DImode) | |
1063 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1064 | operands[3] = force_reg (DImode, operands[3]); | |
1065 | ||
1066 | /* If this is a single dep instruction, we have nothing to do. */ | |
1067 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1068 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1069 | { | |
1070 | /* Check for cases that can be implemented with a mix instruction. */ | |
1071 | if (width == 32 && shift == 0) | |
1072 | { | |
1073 | /* Directly generating the mix4left instruction confuses | |
1074 | optimize_bit_field in function.c. Since this is performing | |
1075 | a useful optimization, we defer generation of the complicated | |
1076 | mix4left RTL to the first splitting phase. */ | |
1077 | rtx tmp = gen_reg_rtx (DImode); | |
1078 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1079 | DONE; | |
1080 | } | |
1081 | else if (width == 32 && shift == 32) | |
1082 | { | |
1083 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1084 | DONE; | |
1085 | } | |
1086 | ||
d2ba6dcf JW |
1087 | /* We could handle remaining cases by emitting multiple dep |
1088 | instructions. | |
1089 | ||
1090 | If we need more than two dep instructions then we lose. A 6 | |
1091 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1092 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1093 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1094 | only one function unit that can execute dep and shr immed. | |
1095 | ||
1096 | If we only need two dep instruction, then we still lose. | |
1097 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1098 | the unnecessary mov, this is still undesirable because it will be | |
1099 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1100 | function unit. */ | |
1101 | ||
c65ebc55 JW |
1102 | FAIL; |
1103 | ||
1104 | #if 0 | |
1105 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1106 | for now. */ | |
1107 | while (width > 16) | |
1108 | { | |
1109 | rtx tmp; | |
1110 | ||
1111 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1112 | operands[3])); | |
1113 | shift += 16; | |
1114 | width -= 16; | |
1115 | tmp = gen_reg_rtx (DImode); | |
1116 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1117 | operands[3] = tmp; | |
1118 | } | |
1119 | operands[1] = GEN_INT (width); | |
1120 | operands[2] = GEN_INT (shift); | |
1121 | #endif | |
1122 | } | |
1d5d7a21 | 1123 | }) |
c65ebc55 JW |
1124 | |
1125 | (define_insn "*insv_internal" | |
0551c32d | 1126 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1127 | (match_operand:DI 1 "const_int_operand" "n") |
1128 | (match_operand:DI 2 "const_int_operand" "n")) | |
1129 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1130 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1131 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1132 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1133 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1134 | |
43a88a8c | 1135 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1136 | (define_insn "*shladdp4_internal" |
1137 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1138 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1139 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1140 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1141 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1142 | "shladdp4 %0 = %1, %2, r0" | |
1143 | [(set_attr "itanium_class" "ialu")]) | |
1144 | ||
041f25e6 | 1145 | (define_insn "*depz_internal" |
0551c32d RH |
1146 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1147 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1148 | (match_operand:DI 2 "const_int_operand" "n")) |
1149 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1150 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1151 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
041f25e6 RH |
1152 | { |
1153 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1154 | return "%,dep.z %0 = %1, %2, %3"; |
1155 | } | |
52e12ad0 | 1156 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1157 | |
c65ebc55 | 1158 | (define_insn "shift_mix4left" |
0551c32d | 1159 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1160 | (const_int 32) (const_int 0)) |
0551c32d RH |
1161 | (match_operand:DI 1 "gr_register_operand" "r")) |
1162 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1163 | "" |
1164 | "#" | |
52e12ad0 | 1165 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1166 | |
c65ebc55 JW |
1167 | (define_split |
1168 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1169 | (const_int 32) (const_int 0)) | |
1170 | (match_operand:DI 1 "register_operand" "")) | |
1171 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1172 | "" |
c65ebc55 JW |
1173 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1174 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1175 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1176 | "operands[3] = operands[2];") | |
1177 | ||
1178 | (define_insn "*mix4left" | |
0551c32d | 1179 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1180 | (const_int 32) (const_int 0)) |
0551c32d | 1181 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1182 | (const_int 32)))] |
1183 | "" | |
1184 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1185 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1186 | |
1187 | (define_insn "mix4right" | |
0551c32d | 1188 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1189 | (const_int 32) (const_int 32)) |
0551c32d | 1190 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1191 | "" |
1192 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1193 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1194 | |
1195 | ;; This is used by the rotrsi3 pattern. | |
1196 | ||
1197 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1198 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1199 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1200 | (ashift:DI (zero_extend:DI | |
1201 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1202 | (const_int 32))))] |
1203 | "" | |
fa9a44e8 | 1204 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1205 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1206 | |
1207 | \f | |
1208 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1209 | ;; :: |
f2f90c63 RH |
1210 | ;; :: 1 bit Integer arithmetic |
1211 | ;; :: | |
1212 | ;; :::::::::::::::::::: | |
1213 | ||
1214 | (define_insn_and_split "andbi3" | |
1215 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1216 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1217 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1218 | "" | |
1219 | "@ | |
1220 | # | |
1221 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1222 | and %0 = %2, %1" | |
1223 | "reload_completed | |
1224 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1225 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1226 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1227 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1228 | (match_dup 0))))] | |
1229 | "" | |
52e12ad0 | 1230 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1231 | |
1232 | (define_insn_and_split "*andcmbi3" | |
1233 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1234 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1235 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1236 | "" | |
1237 | "@ | |
1238 | # | |
967603ef | 1239 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1240 | andcm %0 = %2, %1" |
1241 | "reload_completed | |
1242 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1243 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1244 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1245 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1246 | (match_dup 0))))] | |
1247 | "" | |
52e12ad0 | 1248 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1249 | |
1250 | (define_insn_and_split "iorbi3" | |
1251 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1252 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1253 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1254 | "" | |
1255 | "@ | |
1256 | # | |
1257 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1258 | or %0 = %2, %1" | |
1259 | "reload_completed | |
1260 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1261 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1262 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1263 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1264 | (match_dup 0))))] | |
1265 | "" | |
52e12ad0 | 1266 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1267 | |
1268 | (define_insn_and_split "*iorcmbi3" | |
1269 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1270 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1271 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1272 | "" | |
1273 | "@ | |
1274 | # | |
967603ef | 1275 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1276 | "reload_completed |
1277 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1278 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1279 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1280 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1281 | (match_dup 0))))] | |
1282 | "" | |
52e12ad0 | 1283 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1284 | |
1285 | (define_insn "one_cmplbi2" | |
1286 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1287 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1288 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1289 | "" | |
1290 | "@ | |
1291 | tbit.z %0, %I0 = %1, 0 | |
1292 | xor %0 = 1, %1 | |
1293 | # | |
1294 | #" | |
52e12ad0 | 1295 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1296 | |
1297 | (define_split | |
1298 | [(set (match_operand:BI 0 "register_operand" "") | |
1299 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1300 | (clobber (match_scratch:BI 2 ""))] | |
1301 | "reload_completed | |
1302 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1303 | && rtx_equal_p (operands[0], operands[1])" |
1304 | [(set (match_dup 4) (match_dup 3)) | |
1305 | (set (match_dup 0) (const_int 1)) | |
1306 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1307 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1308 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1309 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1310 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1311 | ||
1312 | (define_split | |
1313 | [(set (match_operand:BI 0 "register_operand" "") | |
1314 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1315 | (clobber (match_scratch:BI 2 ""))] | |
1316 | "reload_completed | |
1317 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1318 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1319 | && ! rtx_equal_p (operands[0], operands[1])" | |
1320 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1321 | (set (match_dup 0) (const_int 0))) | |
1322 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1323 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1324 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1325 | "") |
1326 | ||
1327 | (define_insn "*cmpsi_and_0" | |
1328 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1329 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1330 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1331 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1332 | (match_operand:BI 1 "register_operand" "0")))] | |
1333 | "" | |
1334 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1335 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1336 | |
1337 | (define_insn "*cmpsi_and_1" | |
1338 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1339 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1340 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1341 | (const_int 0)]) | |
1342 | (match_operand:BI 1 "register_operand" "0")))] | |
1343 | "" | |
1344 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1345 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1346 | |
1347 | (define_insn "*cmpsi_andnot_0" | |
1348 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1349 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1350 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1351 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1352 | (match_operand:BI 1 "register_operand" "0")))] | |
1353 | "" | |
1354 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1355 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1356 | |
1357 | (define_insn "*cmpsi_andnot_1" | |
1358 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1359 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1360 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1361 | (const_int 0)])) | |
1362 | (match_operand:BI 1 "register_operand" "0")))] | |
1363 | "" | |
1364 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1365 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1366 | |
1367 | (define_insn "*cmpdi_and_0" | |
1368 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1369 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1370 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1371 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1372 | (match_operand:BI 1 "register_operand" "0")))] | |
1373 | "" | |
1374 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1375 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1376 | |
1377 | (define_insn "*cmpdi_and_1" | |
1378 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1379 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1380 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1381 | (const_int 0)]) | |
1382 | (match_operand:BI 1 "register_operand" "0")))] | |
1383 | "" | |
1384 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1385 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1386 | |
1387 | (define_insn "*cmpdi_andnot_0" | |
1388 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1389 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1390 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1391 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1392 | (match_operand:BI 1 "register_operand" "0")))] | |
1393 | "" | |
1394 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1395 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1396 | |
1397 | (define_insn "*cmpdi_andnot_1" | |
1398 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1399 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1400 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1401 | (const_int 0)])) | |
1402 | (match_operand:BI 1 "register_operand" "0")))] | |
1403 | "" | |
1404 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1405 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1406 | |
1407 | (define_insn "*tbit_and_0" | |
1408 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1409 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1410 | (const_int 1)) | |
1411 | (const_int 0)) | |
c77e04ae | 1412 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1413 | "" |
1414 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1415 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1416 | |
1417 | (define_insn "*tbit_and_1" | |
1418 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1419 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1420 | (const_int 1)) | |
1421 | (const_int 0)) | |
c77e04ae | 1422 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1423 | "" |
1424 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1425 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1426 | |
1427 | (define_insn "*tbit_and_2" | |
1428 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1429 | (and:BI (ne:BI (zero_extract:DI | |
1430 | (match_operand:DI 1 "gr_register_operand" "r") | |
1431 | (const_int 1) | |
1432 | (match_operand:DI 2 "const_int_operand" "n")) | |
1433 | (const_int 0)) | |
1434 | (match_operand:BI 3 "register_operand" "0")))] | |
1435 | "" | |
1436 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1437 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1438 | |
1439 | (define_insn "*tbit_and_3" | |
1440 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1441 | (and:BI (eq:BI (zero_extract:DI | |
1442 | (match_operand:DI 1 "gr_register_operand" "r") | |
1443 | (const_int 1) | |
1444 | (match_operand:DI 2 "const_int_operand" "n")) | |
1445 | (const_int 0)) | |
1446 | (match_operand:BI 3 "register_operand" "0")))] | |
1447 | "" | |
1448 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1449 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1450 | |
1451 | (define_insn "*cmpsi_or_0" | |
1452 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1453 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1454 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1455 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1456 | (match_operand:BI 1 "register_operand" "0")))] | |
1457 | "" | |
1458 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1459 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1460 | |
1461 | (define_insn "*cmpsi_or_1" | |
1462 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1463 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1464 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1465 | (const_int 0)]) | |
1466 | (match_operand:BI 1 "register_operand" "0")))] | |
1467 | "" | |
1468 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1469 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1470 | |
1471 | (define_insn "*cmpsi_orcm_0" | |
1472 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1473 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1474 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1475 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1476 | (match_operand:BI 1 "register_operand" "0")))] | |
1477 | "" | |
1478 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1479 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1480 | |
1481 | (define_insn "*cmpsi_orcm_1" | |
1482 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1483 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1484 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1485 | (const_int 0)])) | |
1486 | (match_operand:BI 1 "register_operand" "0")))] | |
1487 | "" | |
1488 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1489 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1490 | |
1491 | (define_insn "*cmpdi_or_0" | |
1492 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1493 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1494 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1495 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1496 | (match_operand:BI 1 "register_operand" "0")))] | |
1497 | "" | |
1498 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1499 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1500 | |
1501 | (define_insn "*cmpdi_or_1" | |
1502 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1503 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1504 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1505 | (const_int 0)]) | |
1506 | (match_operand:BI 1 "register_operand" "0")))] | |
1507 | "" | |
1508 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1509 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1510 | |
1511 | (define_insn "*cmpdi_orcm_0" | |
1512 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1513 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1514 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1515 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1516 | (match_operand:BI 1 "register_operand" "0")))] | |
1517 | "" | |
1518 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1519 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1520 | |
1521 | (define_insn "*cmpdi_orcm_1" | |
1522 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1523 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1524 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1525 | (const_int 0)])) | |
1526 | (match_operand:BI 1 "register_operand" "0")))] | |
1527 | "" | |
1528 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1529 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1530 | |
1531 | (define_insn "*tbit_or_0" | |
1532 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1533 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1534 | (const_int 1)) | |
1535 | (const_int 0)) | |
c77e04ae | 1536 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1537 | "" |
1538 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1539 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1540 | |
1541 | (define_insn "*tbit_or_1" | |
1542 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1543 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1544 | (const_int 1)) | |
1545 | (const_int 0)) | |
c77e04ae | 1546 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1547 | "" |
1548 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1549 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1550 | |
1551 | (define_insn "*tbit_or_2" | |
1552 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1553 | (ior:BI (ne:BI (zero_extract:DI | |
1554 | (match_operand:DI 1 "gr_register_operand" "r") | |
1555 | (const_int 1) | |
1556 | (match_operand:DI 2 "const_int_operand" "n")) | |
1557 | (const_int 0)) | |
1558 | (match_operand:BI 3 "register_operand" "0")))] | |
1559 | "" | |
1560 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1561 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1562 | |
1563 | (define_insn "*tbit_or_3" | |
1564 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1565 | (ior:BI (eq:BI (zero_extract:DI | |
1566 | (match_operand:DI 1 "gr_register_operand" "r") | |
1567 | (const_int 1) | |
1568 | (match_operand:DI 2 "const_int_operand" "n")) | |
1569 | (const_int 0)) | |
1570 | (match_operand:BI 3 "register_operand" "0")))] | |
1571 | "" | |
1572 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1573 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1574 | |
1575 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1576 | ||
1577 | (define_split | |
1578 | [(set (match_operand:BI 0 "register_operand" "") | |
1579 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1580 | (const_int 0)) | |
1581 | (match_operand:DI 3 "register_operand" "")) | |
1582 | (const_int 0)))] | |
1583 | "" | |
1584 | [(set (match_dup 0) | |
1585 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1586 | (match_dup 2)))] | |
1587 | "") | |
1588 | ||
1589 | (define_split | |
1590 | [(set (match_operand:BI 0 "register_operand" "") | |
1591 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1592 | (const_int 0)) | |
1593 | (match_operand:DI 3 "register_operand" "")) | |
1594 | (const_int 0)))] | |
1595 | "" | |
1596 | [(set (match_dup 0) | |
1597 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1598 | (match_dup 2))) | |
1599 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1600 | (clobber (scratch))])] | |
1601 | "") | |
1602 | ||
1603 | (define_split | |
1604 | [(set (match_operand:BI 0 "register_operand" "") | |
1605 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1606 | (const_int 0)) | |
1607 | (match_operand:DI 3 "register_operand" "")) | |
1608 | (const_int 0)))] | |
1609 | "" | |
1610 | [(set (match_dup 0) | |
1611 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1612 | (match_dup 2)))] | |
1613 | "") | |
1614 | ||
1615 | (define_split | |
1616 | [(set (match_operand:BI 0 "register_operand" "") | |
1617 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1618 | (const_int 0)) | |
1619 | (match_operand:DI 3 "register_operand" "")) | |
1620 | (const_int 0)))] | |
1621 | "" | |
1622 | [(set (match_dup 0) | |
1623 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1624 | (match_dup 2))) | |
1625 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1626 | (clobber (scratch))])] | |
1627 | "") | |
1628 | ||
1629 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1630 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1631 | ;; nothing bad happens to the comparisons in the meantime. | |
1632 | ;; | |
1633 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1634 | ;; that we're doing height reduction. | |
1635 | ; | |
1636 | ;(define_insn_and_split "" | |
1637 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1638 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1639 | ; [(match_operand 2 "" "") | |
1640 | ; (match_operand 3 "" "")]) | |
1641 | ; (match_operator:BI 4 "comparison_operator" | |
1642 | ; [(match_operand 5 "" "") | |
1643 | ; (match_operand 6 "" "")])) | |
1644 | ; (match_dup 0)))] | |
1645 | ; "flag_schedule_insns" | |
1646 | ; "#" | |
1647 | ; "" | |
1648 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1649 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1650 | ; "") | |
1651 | ; | |
1652 | ;(define_insn_and_split "" | |
1653 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1654 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1655 | ; [(match_operand 2 "" "") | |
1656 | ; (match_operand 3 "" "")]) | |
1657 | ; (match_operator:BI 4 "comparison_operator" | |
1658 | ; [(match_operand 5 "" "") | |
1659 | ; (match_operand 6 "" "")])) | |
1660 | ; (match_dup 0)))] | |
1661 | ; "flag_schedule_insns" | |
1662 | ; "#" | |
1663 | ; "" | |
1664 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1665 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1666 | ; "") | |
1667 | ; | |
1668 | ;(define_split | |
1669 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1670 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1671 | ; [(match_operand 2 "" "") | |
1672 | ; (match_operand 3 "" "")]) | |
1673 | ; (match_operand:BI 7 "register_operand" "")) | |
1674 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1675 | ; [(match_operand 5 "" "") | |
1676 | ; (match_operand 6 "" "")]) | |
1677 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1678 | ; "" | |
1679 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1680 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1681 | ; (match_dup 0)))] | |
1682 | ; "") | |
1683 | ; | |
1684 | ;(define_split | |
1685 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1686 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1687 | ; [(match_operand 2 "" "") | |
1688 | ; (match_operand 3 "" "")]) | |
1689 | ; (match_operand:BI 7 "register_operand" "")) | |
1690 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1691 | ; [(match_operand 5 "" "") | |
1692 | ; (match_operand 6 "" "")]) | |
1693 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1694 | ; "" | |
1695 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1696 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1697 | ; (match_dup 0)))] | |
1698 | ; "") | |
1699 | ||
1700 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1701 | ;; Note that we'll have already split the predicate copy, which | |
1702 | ;; is kind of a pain, but oh well. | |
1703 | ||
1704 | (define_peephole2 | |
1705 | [(set (match_operand:BI 0 "register_operand" "") | |
1706 | (match_operand:BI 1 "comparison_operator" "")) | |
1707 | (set (match_operand:CCI 2 "register_operand" "") | |
1708 | (match_operand:CCI 3 "register_operand" "")) | |
1709 | (set (match_operand:CCI 4 "register_operand" "") | |
1710 | (match_operand:CCI 5 "register_operand" "")) | |
1711 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1712 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1713 | "REGNO (operands[3]) == REGNO (operands[0]) |
1714 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1715 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1716 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1717 | [(set (match_dup 0) (match_dup 1)) | |
1718 | (set (match_dup 6) (match_dup 7))] | |
1719 | "operands[7] = copy_rtx (operands[1]);") | |
1720 | \f | |
1721 | ;; :::::::::::::::::::: | |
1722 | ;; :: | |
cf1f6ae3 RH |
1723 | ;; :: 16 bit Integer arithmetic |
1724 | ;; :: | |
1725 | ;; :::::::::::::::::::: | |
1726 | ||
1727 | (define_insn "mulhi3" | |
1728 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1729 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1730 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1731 | "" | |
2a7ffc85 | 1732 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1733 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1734 | |
1735 | \f | |
1736 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1737 | ;; :: |
1738 | ;; :: 32 bit Integer arithmetic | |
1739 | ;; :: | |
1740 | ;; :::::::::::::::::::: | |
1741 | ||
058557c4 | 1742 | (define_insn "addsi3" |
0551c32d RH |
1743 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1744 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1745 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1746 | "" |
1747 | "@ | |
1d5d7a21 RH |
1748 | add %0 = %1, %2 |
1749 | adds %0 = %2, %1 | |
1750 | addl %0 = %2, %1" | |
52e12ad0 | 1751 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1752 | |
1753 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1754 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1755 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1756 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1757 | (const_int 1)))] |
1758 | "" | |
1759 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1760 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1761 | |
5527bf14 | 1762 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1763 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1764 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1765 | (const_int 2)) |
1766 | (const_int 1)))] | |
1767 | "" | |
1768 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1769 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1770 | |
058557c4 | 1771 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1772 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1773 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1774 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1775 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1776 | "" |
058557c4 | 1777 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1778 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1779 | |
058557c4 | 1780 | (define_insn "subsi3" |
0551c32d RH |
1781 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1782 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1783 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1784 | "" |
1785 | "sub %0 = %1, %2" | |
52e12ad0 | 1786 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1787 | |
1788 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1789 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1790 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1791 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1792 | "" |
1793 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1794 | [(set_attr "itanium_class" "ialu")]) |
1795 | ||
1796 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1797 | |
058557c4 | 1798 | (define_insn "mulsi3" |
0551c32d | 1799 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1800 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1801 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1802 | "" |
aebf2462 | 1803 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1804 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1805 | |
655f2eb9 | 1806 | (define_insn "maddsi4" |
11a13704 RH |
1807 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1808 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1809 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1810 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1811 | "" | |
aebf2462 | 1812 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1813 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1814 | |
058557c4 | 1815 | (define_insn "negsi2" |
0551c32d RH |
1816 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1817 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1818 | "" |
1819 | "sub %0 = r0, %1" | |
52e12ad0 | 1820 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1821 | |
1822 | (define_expand "abssi2" | |
1823 | [(set (match_dup 2) | |
f2f90c63 | 1824 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1825 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1826 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1827 | (neg:SI (match_dup 1)) |
1828 | (match_dup 1)))] | |
c65ebc55 | 1829 | "" |
1d5d7a21 | 1830 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1831 | |
1832 | (define_expand "sminsi3" | |
1833 | [(set (match_dup 3) | |
f2f90c63 | 1834 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1835 | (match_operand:SI 2 "gr_register_operand" ""))) |
1836 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1837 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1838 | (match_dup 2) (match_dup 1)))] |
1839 | "" | |
1d5d7a21 | 1840 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1841 | |
1842 | (define_expand "smaxsi3" | |
1843 | [(set (match_dup 3) | |
f2f90c63 | 1844 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1845 | (match_operand:SI 2 "gr_register_operand" ""))) |
1846 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1847 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1848 | (match_dup 1) (match_dup 2)))] |
1849 | "" | |
1d5d7a21 | 1850 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1851 | |
1852 | (define_expand "uminsi3" | |
1853 | [(set (match_dup 3) | |
f2f90c63 | 1854 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1855 | (match_operand:SI 2 "gr_register_operand" ""))) |
1856 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1857 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1858 | (match_dup 2) (match_dup 1)))] |
1859 | "" | |
1d5d7a21 | 1860 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1861 | |
1862 | (define_expand "umaxsi3" | |
1863 | [(set (match_dup 3) | |
f2f90c63 | 1864 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1865 | (match_operand:SI 2 "gr_register_operand" ""))) |
1866 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1867 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1868 | (match_dup 1) (match_dup 2)))] |
1869 | "" | |
1d5d7a21 | 1870 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 1871 | |
655f2eb9 RH |
1872 | (define_expand "divsi3" |
1873 | [(set (match_operand:SI 0 "register_operand" "") | |
1874 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1875 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1876 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 1877 | { |
9aec7fb4 | 1878 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 1879 | |
02befdf4 | 1880 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
1881 | op0_di = gen_reg_rtx (DImode); |
1882 | ||
1883 | if (CONSTANT_P (operands[1])) | |
1884 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
1885 | op1_xf = gen_reg_rtx (XFmode); |
1886 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
1887 | |
1888 | if (CONSTANT_P (operands[2])) | |
1889 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
1890 | op2_xf = gen_reg_rtx (XFmode); |
1891 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
1892 | |
1893 | /* 2^-34 */ | |
9aec7fb4 SE |
1894 | twon34_exp = gen_reg_rtx (DImode); |
1895 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
1896 | twon34 = gen_reg_rtx (XFmode); | |
1897 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 1898 | |
85199961 L |
1899 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
1900 | CONST1_RTX (SImode))); | |
1901 | ||
02befdf4 | 1902 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 1903 | |
02befdf4 | 1904 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
1905 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
1906 | DONE; | |
1d5d7a21 | 1907 | }) |
655f2eb9 RH |
1908 | |
1909 | (define_expand "modsi3" | |
1910 | [(set (match_operand:SI 0 "register_operand" "") | |
1911 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
1912 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1913 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
1914 | { |
1915 | rtx op2_neg, op1_di, div; | |
1916 | ||
1917 | div = gen_reg_rtx (SImode); | |
1918 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
1919 | ||
1920 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1921 | ||
1922 | /* This is a trick to get us to reuse the value that we're sure to | |
1923 | have already copied to the FP regs. */ | |
1924 | op1_di = gen_reg_rtx (DImode); | |
1925 | convert_move (op1_di, operands[1], 0); | |
1926 | ||
1927 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1928 | gen_lowpart (SImode, op1_di))); | |
1929 | DONE; | |
1d5d7a21 | 1930 | }) |
655f2eb9 RH |
1931 | |
1932 | (define_expand "udivsi3" | |
1933 | [(set (match_operand:SI 0 "register_operand" "") | |
1934 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
1935 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1936 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 1937 | { |
9aec7fb4 | 1938 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 1939 | |
02befdf4 | 1940 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
1941 | op0_di = gen_reg_rtx (DImode); |
1942 | ||
1943 | if (CONSTANT_P (operands[1])) | |
1944 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
1945 | op1_xf = gen_reg_rtx (XFmode); |
1946 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
1947 | |
1948 | if (CONSTANT_P (operands[2])) | |
1949 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
1950 | op2_xf = gen_reg_rtx (XFmode); |
1951 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
1952 | |
1953 | /* 2^-34 */ | |
9aec7fb4 SE |
1954 | twon34_exp = gen_reg_rtx (DImode); |
1955 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
1956 | twon34 = gen_reg_rtx (XFmode); | |
1957 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 1958 | |
85199961 L |
1959 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
1960 | CONST1_RTX (SImode))); | |
1961 | ||
02befdf4 | 1962 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 1963 | |
02befdf4 | 1964 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
1965 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
1966 | DONE; | |
1d5d7a21 | 1967 | }) |
655f2eb9 RH |
1968 | |
1969 | (define_expand "umodsi3" | |
1970 | [(set (match_operand:SI 0 "register_operand" "") | |
1971 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
1972 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1973 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
1974 | { |
1975 | rtx op2_neg, op1_di, div; | |
1976 | ||
1977 | div = gen_reg_rtx (SImode); | |
1978 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
1979 | ||
1980 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1981 | ||
1982 | /* This is a trick to get us to reuse the value that we're sure to | |
1983 | have already copied to the FP regs. */ | |
1984 | op1_di = gen_reg_rtx (DImode); | |
1985 | convert_move (op1_di, operands[1], 1); | |
1986 | ||
1987 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1988 | gen_lowpart (SImode, op1_di))); | |
1989 | DONE; | |
1d5d7a21 | 1990 | }) |
655f2eb9 RH |
1991 | |
1992 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
1993 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
1994 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
1995 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
1996 | (clobber (match_scratch:XF 4 "=&f")) | |
1997 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 1998 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
1999 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2000 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2001 | "#" |
2002 | "&& reload_completed" | |
02befdf4 | 2003 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2004 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2005 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2006 | (use (const_int 1))]) |
2007 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2008 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2009 | (use (const_int 1))])) |
2010 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2011 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2012 | (minus:XF (match_dup 7) |
2013 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2014 | (use (const_int 1))])) |
2015 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2016 | (parallel [(set (match_dup 4) | |
02befdf4 | 2017 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2018 | (match_dup 4))) |
2019 | (use (const_int 1))])) | |
2020 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2021 | (parallel [(set (match_dup 5) | |
02befdf4 | 2022 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2023 | (match_dup 3))) |
2024 | (use (const_int 1))])) | |
2025 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2026 | (parallel [(set (match_dup 0) | |
02befdf4 | 2027 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2028 | (match_dup 4))) |
2029 | (use (const_int 1))])) | |
2030 | ] | |
02befdf4 | 2031 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2032 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2033 | \f |
2034 | ;; :::::::::::::::::::: | |
2035 | ;; :: | |
2036 | ;; :: 64 bit Integer arithmetic | |
2037 | ;; :: | |
2038 | ;; :::::::::::::::::::: | |
2039 | ||
2040 | (define_insn "adddi3" | |
0551c32d RH |
2041 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2042 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2043 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2044 | "" |
2045 | "@ | |
1d5d7a21 RH |
2046 | add %0 = %1, %2 |
2047 | adds %0 = %2, %1 | |
2048 | addl %0 = %2, %1" | |
52e12ad0 | 2049 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2050 | |
2051 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2052 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2053 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2054 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2055 | (const_int 1)))] |
2056 | "" | |
2057 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2058 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2059 | |
5527bf14 RH |
2060 | ;; This has some of the same problems as shladd. We let the shladd |
2061 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2062 | ;; a register, but not more ugliness here. | |
2063 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2064 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2065 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2066 | (const_int 2)) |
2067 | (const_int 1)))] | |
2068 | "" | |
2069 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2070 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2071 | |
c65ebc55 | 2072 | (define_insn "subdi3" |
0551c32d RH |
2073 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2074 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2075 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2076 | "" |
2077 | "sub %0 = %1, %2" | |
52e12ad0 | 2078 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2079 | |
2080 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2081 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2082 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2083 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2084 | "" |
2085 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2086 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2087 | |
cee58bc0 RH |
2088 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2089 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2090 | (define_insn "muldi3" |
0551c32d | 2091 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2092 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2093 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2094 | "" |
aebf2462 | 2095 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2096 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2097 | |
2098 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2099 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2100 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2101 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2102 | ;; here so that it will be present just in case register elimination gives us | |
2103 | ;; the funny result. | |
2104 | ||
2105 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2106 | ||
2107 | ;; ??? Maybe we should change how adds are canonicalized. | |
2108 | ||
655f2eb9 | 2109 | (define_insn "madddi4" |
0551c32d | 2110 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2111 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2112 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2113 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2114 | (clobber (match_scratch:DI 4 "=X"))] |
2115 | "" | |
aebf2462 | 2116 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2117 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2118 | |
2119 | ;; This can be created by register elimination if operand3 of shladd is an | |
2120 | ;; eliminable register or has reg_equiv_constant set. | |
2121 | ||
2122 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2123 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2124 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2125 | ;; incorrectly. |
2126 | ||
655f2eb9 | 2127 | (define_insn "*madddi4_elim" |
c65ebc55 | 2128 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2129 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2130 | (match_operand:DI 2 "register_operand" "f")) | |
2131 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2132 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2133 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2134 | "reload_in_progress" |
2135 | "#" | |
52e12ad0 | 2136 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2137 | |
c65ebc55 JW |
2138 | (define_split |
2139 | [(set (match_operand:DI 0 "register_operand" "") | |
2140 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2141 | (match_operand:DI 2 "register_operand" "")) | |
2142 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2143 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2144 | (clobber (match_scratch:DI 5 ""))] |
2145 | "reload_completed" | |
2146 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2147 | (match_dup 3))) | |
2148 | (clobber (match_dup 0))]) | |
c65ebc55 | 2149 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2150 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2151 | "") | |
2152 | ||
c65ebc55 | 2153 | (define_insn "smuldi3_highpart" |
0551c32d | 2154 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2155 | (truncate:DI |
2156 | (lshiftrt:TI | |
0551c32d RH |
2157 | (mult:TI (sign_extend:TI |
2158 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2159 | (sign_extend:TI | |
2160 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2161 | (const_int 64))))] |
2162 | "" | |
aebf2462 | 2163 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2164 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2165 | |
2166 | (define_insn "umuldi3_highpart" | |
0551c32d | 2167 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2168 | (truncate:DI |
2169 | (lshiftrt:TI | |
0551c32d RH |
2170 | (mult:TI (zero_extend:TI |
2171 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2172 | (zero_extend:TI | |
2173 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2174 | (const_int 64))))] |
2175 | "" | |
aebf2462 | 2176 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2177 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2178 | |
2179 | (define_insn "negdi2" | |
0551c32d RH |
2180 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2181 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2182 | "" |
2183 | "sub %0 = r0, %1" | |
52e12ad0 | 2184 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2185 | |
2186 | (define_expand "absdi2" | |
2187 | [(set (match_dup 2) | |
f2f90c63 | 2188 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2189 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2190 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2191 | (neg:DI (match_dup 1)) |
2192 | (match_dup 1)))] | |
c65ebc55 | 2193 | "" |
1d5d7a21 | 2194 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2195 | |
2196 | (define_expand "smindi3" | |
2197 | [(set (match_dup 3) | |
f2f90c63 | 2198 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2199 | (match_operand:DI 2 "gr_register_operand" ""))) |
2200 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2201 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2202 | (match_dup 2) (match_dup 1)))] |
2203 | "" | |
1d5d7a21 | 2204 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2205 | |
2206 | (define_expand "smaxdi3" | |
2207 | [(set (match_dup 3) | |
f2f90c63 | 2208 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2209 | (match_operand:DI 2 "gr_register_operand" ""))) |
2210 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2211 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2212 | (match_dup 1) (match_dup 2)))] |
2213 | "" | |
1d5d7a21 | 2214 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2215 | |
2216 | (define_expand "umindi3" | |
2217 | [(set (match_dup 3) | |
f2f90c63 | 2218 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2219 | (match_operand:DI 2 "gr_register_operand" ""))) |
2220 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2221 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2222 | (match_dup 2) (match_dup 1)))] |
2223 | "" | |
1d5d7a21 | 2224 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2225 | |
2226 | (define_expand "umaxdi3" | |
2227 | [(set (match_dup 3) | |
f2f90c63 | 2228 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2229 | (match_operand:DI 2 "gr_register_operand" ""))) |
2230 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2231 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2232 | (match_dup 1) (match_dup 2)))] |
2233 | "" | |
1d5d7a21 | 2234 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2235 | |
2236 | (define_expand "ffsdi2" | |
2237 | [(set (match_dup 6) | |
f2f90c63 | 2238 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2239 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2240 | (set (match_dup 5) (const_int 0)) | |
2241 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2242 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2243 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2244 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2245 | (match_dup 5) (match_dup 4)))] |
2246 | "" | |
c65ebc55 JW |
2247 | { |
2248 | operands[2] = gen_reg_rtx (DImode); | |
2249 | operands[3] = gen_reg_rtx (DImode); | |
2250 | operands[4] = gen_reg_rtx (DImode); | |
2251 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2252 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2253 | }) |
c65ebc55 | 2254 | |
c407570a RH |
2255 | (define_expand "ctzdi2" |
2256 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2257 | (const_int -1))) | |
2258 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2259 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2260 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2261 | (popcount:DI (match_dup 4)))] | |
2262 | "" | |
2263 | { | |
2264 | operands[2] = gen_reg_rtx (DImode); | |
2265 | operands[3] = gen_reg_rtx (DImode); | |
2266 | operands[4] = gen_reg_rtx (DImode); | |
2267 | }) | |
2268 | ||
c407570a RH |
2269 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2270 | (define_expand "clzdi2" | |
2271 | [(set (match_dup 2) | |
02befdf4 | 2272 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2273 | (set (match_dup 3) |
2274 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2275 | (set (match_dup 4) (const_int 65598)) | |
2276 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2277 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2278 | "" |
c407570a | 2279 | { |
02befdf4 | 2280 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2281 | operands[3] = gen_reg_rtx (DImode); |
2282 | operands[4] = gen_reg_rtx (DImode); | |
2283 | }) | |
2284 | ||
2285 | (define_insn "popcountdi2" | |
0551c32d | 2286 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2287 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2288 | "" |
2289 | "popcnt %0 = %1" | |
52e12ad0 | 2290 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2291 | |
02befdf4 | 2292 | (define_insn "*getf_exp_xf" |
c407570a | 2293 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2294 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2295 | UNSPEC_GETF_EXP))] |
02befdf4 | 2296 | "" |
c407570a RH |
2297 | "getf.exp %0 = %1" |
2298 | [(set_attr "itanium_class" "frfr")]) | |
2299 | ||
655f2eb9 RH |
2300 | (define_expand "divdi3" |
2301 | [(set (match_operand:DI 0 "register_operand" "") | |
2302 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2303 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2304 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2305 | { |
02befdf4 | 2306 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2307 | |
02befdf4 | 2308 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2309 | |
2310 | if (CONSTANT_P (operands[1])) | |
2311 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2312 | op1_xf = gen_reg_rtx (XFmode); |
2313 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2314 | |
2315 | if (CONSTANT_P (operands[2])) | |
2316 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2317 | op2_xf = gen_reg_rtx (XFmode); |
2318 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2319 | |
85199961 L |
2320 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2321 | CONST1_RTX (DImode))); | |
2322 | ||
dbdd120f | 2323 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2324 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2325 | else |
02befdf4 | 2326 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2327 | |
02befdf4 | 2328 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2329 | DONE; |
1d5d7a21 | 2330 | }) |
655f2eb9 RH |
2331 | |
2332 | (define_expand "moddi3" | |
2333 | [(set (match_operand:DI 0 "register_operand" "") | |
2334 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2335 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2336 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2337 | { |
2338 | rtx op2_neg, div; | |
2339 | ||
2340 | div = gen_reg_rtx (DImode); | |
2341 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2342 | ||
2343 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2344 | ||
2345 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2346 | DONE; | |
1d5d7a21 | 2347 | }) |
655f2eb9 RH |
2348 | |
2349 | (define_expand "udivdi3" | |
2350 | [(set (match_operand:DI 0 "register_operand" "") | |
2351 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2352 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2353 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2354 | { |
02befdf4 | 2355 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2356 | |
02befdf4 | 2357 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2358 | |
2359 | if (CONSTANT_P (operands[1])) | |
2360 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2361 | op1_xf = gen_reg_rtx (XFmode); |
2362 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2363 | |
2364 | if (CONSTANT_P (operands[2])) | |
2365 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2366 | op2_xf = gen_reg_rtx (XFmode); |
2367 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2368 | |
85199961 L |
2369 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2370 | CONST1_RTX (DImode))); | |
2371 | ||
dbdd120f | 2372 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2373 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2374 | else |
02befdf4 | 2375 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2376 | |
02befdf4 | 2377 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2378 | DONE; |
1d5d7a21 | 2379 | }) |
655f2eb9 RH |
2380 | |
2381 | (define_expand "umoddi3" | |
2382 | [(set (match_operand:DI 0 "register_operand" "") | |
2383 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2384 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2385 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2386 | { |
2387 | rtx op2_neg, div; | |
2388 | ||
2389 | div = gen_reg_rtx (DImode); | |
2390 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2391 | ||
2392 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2393 | ||
2394 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2395 | DONE; | |
1d5d7a21 | 2396 | }) |
655f2eb9 RH |
2397 | |
2398 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2399 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2400 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2401 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2402 | (clobber (match_scratch:XF 3 "=&f")) | |
2403 | (clobber (match_scratch:XF 4 "=&f")) | |
2404 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2405 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2406 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2407 | "#" |
2408 | "&& reload_completed" | |
02befdf4 | 2409 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2410 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2411 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2412 | (use (const_int 1))]) |
2413 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2414 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2415 | (minus:XF (match_dup 7) |
2416 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2417 | (use (const_int 1))])) |
2418 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2419 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2420 | (use (const_int 1))])) |
2421 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2422 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2423 | (use (const_int 1))])) |
2424 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2425 | (parallel [(set (match_dup 4) | |
02befdf4 | 2426 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2427 | (match_dup 4))) |
2428 | (use (const_int 1))])) | |
2429 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2430 | (parallel [(set (match_dup 0) | |
02befdf4 | 2431 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2432 | (match_dup 0))) |
2433 | (use (const_int 1))])) | |
2434 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2435 | (parallel [(set (match_dup 3) | |
02befdf4 | 2436 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2437 | (match_dup 4))) |
2438 | (use (const_int 1))])) | |
2439 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2440 | (parallel [(set (match_dup 0) | |
02befdf4 | 2441 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2442 | (match_dup 0))) |
2443 | (use (const_int 1))])) | |
2444 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2445 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2446 | (minus:XF (match_dup 1) |
2447 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2448 | (use (const_int 1))])) |
2449 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2450 | (parallel [(set (match_dup 0) | |
02befdf4 | 2451 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2452 | (match_dup 3))) |
2453 | (use (const_int 1))])) | |
2454 | ] | |
02befdf4 | 2455 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2456 | [(set_attr "predicable" "no")]) |
2457 | ||
2458 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2459 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2460 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2461 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2462 | (clobber (match_scratch:XF 3 "=&f")) | |
2463 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2464 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2465 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2466 | "#" |
2467 | "&& reload_completed" | |
02befdf4 | 2468 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2469 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2470 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2471 | (use (const_int 1))]) |
2472 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2473 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2474 | (minus:XF (match_dup 6) |
2475 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2476 | (use (const_int 1))])) |
2477 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2478 | (parallel [(set (match_dup 0) | |
02befdf4 | 2479 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2480 | (match_dup 0))) |
2481 | (use (const_int 1))])) | |
2482 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2483 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2484 | (use (const_int 1))])) |
2485 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2486 | (parallel [(set (match_dup 0) | |
02befdf4 | 2487 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2488 | (match_dup 0))) |
2489 | (use (const_int 1))])) | |
2490 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2491 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2492 | (use (const_int 1))])) |
2493 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2494 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2495 | (minus:XF (match_dup 1) |
2496 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2497 | (use (const_int 1))])) |
2498 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2499 | (parallel [(set (match_dup 0) | |
02befdf4 | 2500 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2501 | (match_dup 3))) |
2502 | (use (const_int 1))])) | |
2503 | ] | |
02befdf4 | 2504 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2505 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2506 | \f |
2507 | ;; :::::::::::::::::::: | |
2508 | ;; :: | |
a71aef0b JB |
2509 | ;; :: 128 bit Integer arithmetic |
2510 | ;; :: | |
2511 | ;; :::::::::::::::::::: | |
2512 | ||
2513 | (define_insn "addti3" | |
2514 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2515 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2516 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2517 | (clobber (match_scratch:BI 3 "=&c"))] | |
2518 | "" | |
2519 | "#" | |
2520 | [(set_attr "itanium_class" "unknown")]) | |
2521 | ||
2522 | (define_split | |
2523 | [(set (match_operand:TI 0 "register_operand" "") | |
2524 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2525 | (match_operand:TI 2 "register_operand" ""))) | |
2526 | (clobber (match_scratch:BI 3 ""))] | |
2527 | "reload_completed" | |
2528 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2529 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2530 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2531 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2532 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2533 | (set (match_dup 4) | |
2534 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2535 | (const_int 1))))] | |
2536 | { | |
2537 | operands[4] = gen_highpart (DImode, operands[0]); | |
2538 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2539 | operands[5] = gen_highpart (DImode, operands[1]); | |
2540 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2541 | operands[6] = gen_highpart (DImode, operands[2]); | |
2542 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2543 | }) | |
2544 | ||
2545 | (define_split | |
2546 | [(set (match_operand:TI 0 "register_operand" "") | |
2547 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2548 | (match_operand:TI 2 "immediate_operand" ""))) | |
2549 | (clobber (match_scratch:BI 3 ""))] | |
2550 | "reload_completed" | |
2551 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2552 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2553 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2554 | (set (match_dup 4) | |
2555 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2556 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2557 | (set (match_dup 4) | |
2558 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2559 | { | |
2560 | operands[4] = gen_highpart (DImode, operands[0]); | |
2561 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2562 | operands[5] = gen_highpart (DImode, operands[1]); | |
2563 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2564 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2565 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2566 | }) | |
2567 | ||
2568 | (define_insn "subti3" | |
2569 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2570 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2571 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2572 | (clobber (match_scratch:BI 3 "=&c"))] | |
2573 | "" | |
2574 | "#" | |
2575 | [(set_attr "itanium_class" "unknown")]) | |
2576 | ||
2577 | (define_split | |
2578 | [(set (match_operand:TI 0 "register_operand" "") | |
2579 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2580 | (match_operand:TI 2 "register_operand" ""))) | |
2581 | (clobber (match_scratch:BI 3 "=&c"))] | |
2582 | "reload_completed" | |
2583 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2584 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2585 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2586 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2587 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2588 | (set (match_dup 4) | |
2589 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2590 | { | |
2591 | operands[4] = gen_highpart (DImode, operands[0]); | |
2592 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2593 | operands[5] = gen_highpart (DImode, operands[1]); | |
2594 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2595 | operands[6] = gen_highpart (DImode, operands[2]); | |
2596 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2597 | }) | |
2598 | ||
2599 | (define_split | |
2600 | [(set (match_operand:TI 0 "register_operand" "") | |
2601 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2602 | (match_operand:TI 2 "register_operand" ""))) | |
2603 | (clobber (match_scratch:BI 3 "=&c"))] | |
2604 | "reload_completed && CONST_OK_FOR_K (INTVAL (operands[1]))" | |
2605 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2606 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2607 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2608 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2609 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2610 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2611 | { | |
2612 | operands[4] = gen_highpart (DImode, operands[0]); | |
2613 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2614 | operands[5] = gen_highpart (DImode, operands[2]); | |
2615 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2616 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2617 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2618 | }) | |
2619 | ||
2620 | (define_expand "mulditi3" | |
2621 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2622 | (mult:TI (sign_extend:TI | |
2623 | (match_operand:DI 1 "fr_register_operand" "")) | |
2624 | (sign_extend:TI | |
2625 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2626 | "" | |
2627 | "") | |
2628 | ||
2629 | (define_insn_and_split "*mulditi3_internal" | |
2630 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2631 | (mult:TI (sign_extend:TI | |
2632 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2633 | (sign_extend:TI | |
2634 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2635 | "" | |
2636 | "#" | |
2637 | "reload_completed" | |
2638 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2639 | (set (match_dup 3) (truncate:DI | |
2640 | (lshiftrt:TI | |
2641 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2642 | (sign_extend:TI (match_dup 2))) | |
2643 | (const_int 64))))] | |
2644 | { | |
2645 | operands[3] = gen_highpart (DImode, operands[0]); | |
2646 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2647 | } | |
2648 | [(set_attr "itanium_class" "unknown")]) | |
2649 | ||
2650 | (define_expand "umulditi3" | |
2651 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2652 | (mult:TI (zero_extend:TI | |
2653 | (match_operand:DI 1 "fr_register_operand" "")) | |
2654 | (zero_extend:TI | |
2655 | (match_operand:DI 2 "fr_register_operand" ""))))] | |
2656 | "" | |
2657 | "") | |
2658 | ||
2659 | (define_insn_and_split "*umulditi3_internal" | |
2660 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2661 | (mult:TI (zero_extend:TI | |
2662 | (match_operand:DI 1 "fr_register_operand" "%f")) | |
2663 | (zero_extend:TI | |
2664 | (match_operand:DI 2 "fr_register_operand" "f"))))] | |
2665 | "" | |
2666 | "#" | |
2667 | "reload_completed" | |
2668 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2669 | (set (match_dup 3) (truncate:DI | |
2670 | (lshiftrt:TI | |
2671 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2672 | (zero_extend:TI (match_dup 2))) | |
2673 | (const_int 64))))] | |
2674 | { | |
2675 | operands[3] = gen_highpart (DImode, operands[0]); | |
2676 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2677 | } | |
2678 | [(set_attr "itanium_class" "unknown")]) | |
2679 | ||
2680 | (define_insn_and_split "negti2" | |
2681 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2682 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2683 | (clobber (match_scratch:BI 2 "=&c"))] | |
2684 | "" | |
2685 | "#" | |
2686 | "reload_completed" | |
2687 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
2688 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
2689 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
2690 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
2691 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
2692 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
2693 | { | |
2694 | operands[3] = gen_highpart (DImode, operands[0]); | |
2695 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2696 | operands[4] = gen_highpart (DImode, operands[1]); | |
2697 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2698 | } | |
2699 | [(set_attr "itanium_class" "unknown")]) | |
2700 | \f | |
2701 | ;; :::::::::::::::::::: | |
2702 | ;; :: | |
c65ebc55 JW |
2703 | ;; :: 32 bit floating point arithmetic |
2704 | ;; :: | |
2705 | ;; :::::::::::::::::::: | |
2706 | ||
2707 | (define_insn "addsf3" | |
0551c32d RH |
2708 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2709 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2710 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2711 | "" |
aebf2462 | 2712 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2713 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2714 | |
2715 | (define_insn "subsf3" | |
0551c32d RH |
2716 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2717 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2718 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2719 | "" |
aebf2462 | 2720 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2721 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2722 | |
2723 | (define_insn "mulsf3" | |
0551c32d RH |
2724 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2725 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2726 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2727 | "" |
aebf2462 | 2728 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2729 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2730 | |
2731 | (define_insn "abssf2" | |
0551c32d RH |
2732 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2733 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2734 | "" |
aebf2462 | 2735 | "fabs %0 = %1" |
52e12ad0 | 2736 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2737 | |
2738 | (define_insn "negsf2" | |
0551c32d RH |
2739 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2740 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2741 | "" |
aebf2462 | 2742 | "fneg %0 = %1" |
52e12ad0 | 2743 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2744 | |
2745 | (define_insn "*nabssf2" | |
0551c32d RH |
2746 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2747 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2748 | "" |
aebf2462 | 2749 | "fnegabs %0 = %1" |
52e12ad0 | 2750 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2751 | |
046625fa RH |
2752 | (define_insn "copysignsf3" |
2753 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2754 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2755 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2756 | UNSPEC_COPYSIGN))] | |
2757 | "" | |
2758 | "fmerge.s %0 = %F2, %F1" | |
2759 | [(set_attr "itanium_class" "fmisc")]) | |
2760 | ||
2761 | (define_insn "*ncopysignsf3" | |
2762 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2763 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2764 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2765 | UNSPEC_COPYSIGN)))] | |
2766 | "" | |
2767 | "fmerge.ns %0 = %F2, %F1" | |
2768 | [(set_attr "itanium_class" "fmisc")]) | |
2769 | ||
7ae4d8d4 | 2770 | (define_insn "sminsf3" |
0551c32d RH |
2771 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2772 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2773 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2774 | "" |
aebf2462 | 2775 | "fmin %0 = %1, %F2" |
52e12ad0 | 2776 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2777 | |
7ae4d8d4 | 2778 | (define_insn "smaxsf3" |
0551c32d RH |
2779 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2780 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2781 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2782 | "" |
aebf2462 | 2783 | "fmax %0 = %1, %F2" |
52e12ad0 | 2784 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2785 | |
655f2eb9 | 2786 | (define_insn "*maddsf4" |
0551c32d RH |
2787 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2788 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2789 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2790 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2791 | "" |
aebf2462 | 2792 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2793 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2794 | |
655f2eb9 | 2795 | (define_insn "*msubsf4" |
0551c32d RH |
2796 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2797 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2798 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2799 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2800 | "" |
aebf2462 | 2801 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2802 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2803 | |
2804 | (define_insn "*nmulsf3" | |
0551c32d RH |
2805 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2806 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2807 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2808 | "" |
aebf2462 | 2809 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2810 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2811 | |
655f2eb9 | 2812 | (define_insn "*nmaddsf4" |
0551c32d | 2813 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
2814 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
2815 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2816 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2817 | "" |
aebf2462 | 2818 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2819 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2820 | |
52ad4d7b ZW |
2821 | (define_insn "*nmaddsf4_alts" |
2822 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2823 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
2824 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2825 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
2826 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2827 | "" | |
2828 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
2829 | [(set_attr "itanium_class" "fmac")]) | |
2830 | ||
26102535 RH |
2831 | (define_expand "divsf3" |
2832 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2833 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2834 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 2835 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
2836 | { |
2837 | rtx insn; | |
dbdd120f | 2838 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
2839 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
2840 | else | |
2841 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2842 | emit_insn (insn); | |
2843 | DONE; | |
1d5d7a21 | 2844 | }) |
26102535 RH |
2845 | |
2846 | (define_insn_and_split "divsf3_internal_lat" | |
2847 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2848 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2849 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
2850 | (clobber (match_scratch:XF 3 "=&f")) |
2851 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2852 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2853 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
2854 | "#" |
2855 | "&& reload_completed" | |
02befdf4 | 2856 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
2857 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2858 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 2859 | (use (const_int 0))]) |
26102535 | 2860 | (cond_exec (ne (match_dup 5) (const_int 0)) |
02befdf4 | 2861 | (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) |
26102535 RH |
2862 | (use (const_int 1))])) |
2863 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2864 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2865 | (minus:XF (match_dup 10) |
2866 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
2867 | (use (const_int 1))])) |
2868 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2869 | (parallel [(set (match_dup 3) | |
02befdf4 | 2870 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2871 | (match_dup 3))) |
2872 | (use (const_int 1))])) | |
2873 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2874 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
2875 | (use (const_int 1))])) |
2876 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2877 | (parallel [(set (match_dup 3) | |
02befdf4 | 2878 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2879 | (match_dup 3))) |
2880 | (use (const_int 1))])) | |
2881 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2882 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
2883 | (use (const_int 1))])) |
2884 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2885 | (parallel [(set (match_dup 9) | |
2886 | (float_truncate:DF | |
02befdf4 | 2887 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2888 | (match_dup 3)))) |
2889 | (use (const_int 1))])) | |
2890 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2891 | (set (match_dup 0) | |
2892 | (float_truncate:SF (match_dup 6)))) | |
2893 | ] | |
1d5d7a21 | 2894 | { |
02befdf4 ZW |
2895 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
2896 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
2897 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 2898 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); |
02befdf4 | 2899 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 2900 | } |
26102535 RH |
2901 | [(set_attr "predicable" "no")]) |
2902 | ||
2903 | (define_insn_and_split "divsf3_internal_thr" | |
2904 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2905 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2906 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
2907 | (clobber (match_scratch:XF 3 "=&f")) |
2908 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2909 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2910 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
2911 | "#" |
2912 | "&& reload_completed" | |
02befdf4 | 2913 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
2914 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2915 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 2916 | (use (const_int 0))]) |
26102535 RH |
2917 | (cond_exec (ne (match_dup 5) (const_int 0)) |
2918 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2919 | (minus:XF (match_dup 10) |
2920 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
2921 | (use (const_int 1))])) |
2922 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2923 | (parallel [(set (match_dup 3) | |
02befdf4 | 2924 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
2925 | (match_dup 3))) |
2926 | (use (const_int 1))])) | |
2927 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2928 | (parallel [(set (match_dup 6) | |
02befdf4 | 2929 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
2930 | (match_dup 6))) |
2931 | (use (const_int 1))])) | |
2932 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2933 | (parallel [(set (match_dup 9) | |
2934 | (float_truncate:SF | |
02befdf4 | 2935 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
2936 | (use (const_int 1))])) |
2937 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2938 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2939 | (minus:XF (match_dup 7) |
2940 | (mult:XF (match_dup 8) (match_dup 3)))) | |
26102535 RH |
2941 | (use (const_int 1))])) |
2942 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2943 | (set (match_dup 0) | |
2944 | (float_truncate:SF | |
02befdf4 | 2945 | (plus:XF (mult:XF (match_dup 4) (match_dup 6)) |
26102535 RH |
2946 | (match_dup 3))))) |
2947 | ] | |
1d5d7a21 | 2948 | { |
02befdf4 ZW |
2949 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
2950 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
2951 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 2952 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); |
02befdf4 | 2953 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 2954 | } |
26102535 | 2955 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
2956 | |
2957 | ;; Inline square root. | |
2958 | ||
2959 | (define_insn "*sqrt_approx" | |
2960 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
2961 | (div:XF (const_int 1) | |
2962 | (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f")))) | |
2963 | (set (match_operand:BI 1 "register_operand" "=c") | |
2964 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
2965 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
2966 | "" | |
2967 | "frsqrta.s%3 %0, %1 = %2" | |
2968 | [(set_attr "itanium_class" "fmisc") | |
2969 | (set_attr "predicable" "no")]) | |
2970 | ||
9aec7fb4 | 2971 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
2972 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
2973 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
2974 | UNSPEC_SETF_EXP))] | |
2975 | "" | |
2976 | "setf.exp %0 = %1" | |
2977 | [(set_attr "itanium_class" "frfr")]) | |
2978 | ||
2979 | (define_expand "sqrtsf2" | |
2980 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2981 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
2982 | "TARGET_INLINE_SQRT" | |
2983 | { | |
2984 | rtx insn; | |
b38ba463 | 2985 | #if 0 |
e820471b | 2986 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 2987 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 2988 | else |
b38ba463 | 2989 | #else |
e820471b | 2990 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 2991 | #endif |
e820471b | 2992 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
2993 | emit_insn (insn); |
2994 | DONE; | |
2995 | }) | |
2996 | ||
2997 | ;; Latency-optimized square root. | |
2998 | ;; FIXME: Implement. | |
2999 | ||
3000 | ;; Throughput-optimized square root. | |
3001 | ||
3002 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3003 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3004 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
3005 | ;; Register r2 in optimization guide. | |
3006 | (clobber (match_scratch:DI 2 "=r")) | |
3007 | ;; Register f8 in optimization guide | |
3008 | (clobber (match_scratch:XF 3 "=&f")) | |
3009 | ;; Register f9 in optimization guide | |
3010 | (clobber (match_scratch:XF 4 "=&f")) | |
3011 | ;; Register f10 in optimization guide | |
3012 | (clobber (match_scratch:XF 5 "=&f")) | |
3013 | ;; Register p6 in optimization guide. | |
3014 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3015 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3016 | "#" |
3017 | "&& reload_completed" | |
3018 | [ ;; exponent of +1/2 in r2 | |
3019 | (set (match_dup 2) (const_int 65534)) | |
3020 | ;; +1/2 in f8 | |
3021 | (set (match_dup 3) | |
3022 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3023 | ;; Step 1 | |
3024 | ;; y0 = 1/sqrt(a) in f7 | |
3025 | (parallel [(set (match_dup 7) | |
3026 | (div:XF (const_int 1) | |
3027 | (sqrt:XF (match_dup 8)))) | |
3028 | (set (match_dup 6) | |
3029 | (unspec:BI [(match_dup 8)] | |
3030 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3031 | (use (const_int 0))]) | |
3032 | ;; Step 2 | |
3033 | ;; H0 = 1/2 * y0 in f9 | |
3034 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3035 | (parallel [(set (match_dup 4) | |
3036 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3037 | (match_dup 9))) | |
3038 | (use (const_int 1))])) | |
3039 | ;; Step 3 | |
3040 | ;; S0 = a * y0 in f7 | |
3041 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3042 | (parallel [(set (match_dup 7) | |
3043 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3044 | (match_dup 9))) | |
3045 | (use (const_int 1))])) | |
3046 | ;; Step 4 | |
3047 | ;; d = 1/2 - S0 * H0 in f10 | |
3048 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3049 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3050 | (minus:XF (match_dup 3) |
3051 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3052 | (use (const_int 1))])) |
3053 | ;; Step 5 | |
3054 | ;; d' = d + 1/2 * d in f8 | |
3055 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3056 | (parallel [(set (match_dup 3) | |
3057 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3058 | (match_dup 5))) | |
3059 | (use (const_int 1))])) | |
3060 | ;; Step 6 | |
3061 | ;; e = d + d * d' in f8 | |
3062 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3063 | (parallel [(set (match_dup 3) | |
3064 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3065 | (match_dup 5))) | |
3066 | (use (const_int 1))])) | |
3067 | ;; Step 7 | |
3068 | ;; S1 = S0 + e * S0 in f7 | |
3069 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3070 | (parallel [(set (match_dup 0) | |
3071 | (float_truncate:SF | |
3072 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3073 | (match_dup 7)))) | |
3074 | (use (const_int 1))])) | |
3075 | ;; Step 8 | |
3076 | ;; H1 = H0 + e * H0 in f8 | |
3077 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3078 | (parallel [(set (match_dup 3) | |
3079 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3080 | (match_dup 4))) | |
3081 | (use (const_int 1))])) | |
3082 | ;; Step 9 | |
3083 | ;; d1 = a - S1 * S1 in f9 | |
3084 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3085 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3086 | (minus:XF (match_dup 8) |
3087 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3088 | (use (const_int 1))])) |
3089 | ;; Step 10 | |
3090 | ;; S = S1 + d1 * H1 in f7 | |
3091 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3092 | (parallel [(set (match_dup 0) | |
3093 | (float_truncate:SF | |
3094 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3095 | (match_dup 7)))) | |
3096 | (use (const_int 0))]))] | |
3097 | { | |
3098 | /* Generate 82-bit versions of the input and output operands. */ | |
3099 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3100 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3101 | /* Generate required floating-point constants. */ | |
3102 | operands[9] = CONST0_RTX (XFmode); | |
3103 | } | |
3104 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3105 | \f |
3106 | ;; :::::::::::::::::::: | |
3107 | ;; :: | |
3108 | ;; :: 64 bit floating point arithmetic | |
3109 | ;; :: | |
3110 | ;; :::::::::::::::::::: | |
3111 | ||
3112 | (define_insn "adddf3" | |
0551c32d RH |
3113 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3114 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3115 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3116 | "" |
aebf2462 | 3117 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 3118 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3119 | |
26102535 RH |
3120 | (define_insn "*adddf3_trunc" |
3121 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3122 | (float_truncate:SF | |
3123 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3124 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3125 | "" | |
aebf2462 | 3126 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3127 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3128 | |
c65ebc55 | 3129 | (define_insn "subdf3" |
0551c32d RH |
3130 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3131 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3132 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3133 | "" |
aebf2462 | 3134 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3135 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3136 | |
26102535 RH |
3137 | (define_insn "*subdf3_trunc" |
3138 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3139 | (float_truncate:SF | |
3140 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3141 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3142 | "" | |
aebf2462 | 3143 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3144 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3145 | |
c65ebc55 | 3146 | (define_insn "muldf3" |
0551c32d RH |
3147 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3148 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3149 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3150 | "" |
aebf2462 | 3151 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 3152 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3153 | |
26102535 RH |
3154 | (define_insn "*muldf3_trunc" |
3155 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3156 | (float_truncate:SF | |
3157 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3158 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
3159 | "" | |
aebf2462 | 3160 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3161 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3162 | |
c65ebc55 | 3163 | (define_insn "absdf2" |
0551c32d RH |
3164 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3165 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3166 | "" |
aebf2462 | 3167 | "fabs %0 = %1" |
52e12ad0 | 3168 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3169 | |
3170 | (define_insn "negdf2" | |
0551c32d RH |
3171 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3172 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3173 | "" |
aebf2462 | 3174 | "fneg %0 = %1" |
52e12ad0 | 3175 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3176 | |
3177 | (define_insn "*nabsdf2" | |
0551c32d RH |
3178 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3179 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3180 | "" |
aebf2462 | 3181 | "fnegabs %0 = %1" |
52e12ad0 | 3182 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3183 | |
046625fa RH |
3184 | (define_insn "copysigndf3" |
3185 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3186 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3187 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3188 | UNSPEC_COPYSIGN))] | |
3189 | "" | |
3190 | "fmerge.s %0 = %F2, %F1" | |
3191 | [(set_attr "itanium_class" "fmisc")]) | |
3192 | ||
3193 | (define_insn "*ncopysigndf3" | |
3194 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3195 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3196 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3197 | UNSPEC_COPYSIGN)))] | |
3198 | "" | |
3199 | "fmerge.ns %0 = %F2, %F1" | |
3200 | [(set_attr "itanium_class" "fmisc")]) | |
3201 | ||
7ae4d8d4 | 3202 | (define_insn "smindf3" |
0551c32d RH |
3203 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3204 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3205 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3206 | "" |
aebf2462 | 3207 | "fmin %0 = %1, %F2" |
52e12ad0 | 3208 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3209 | |
7ae4d8d4 | 3210 | (define_insn "smaxdf3" |
0551c32d RH |
3211 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3212 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3213 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3214 | "" |
aebf2462 | 3215 | "fmax %0 = %1, %F2" |
52e12ad0 | 3216 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3217 | |
655f2eb9 | 3218 | (define_insn "*madddf4" |
0551c32d RH |
3219 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3220 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3221 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3222 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3223 | "" |
aebf2462 | 3224 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3225 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3226 | |
26102535 RH |
3227 | (define_insn "*madddf4_trunc" |
3228 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3229 | (float_truncate:SF | |
3230 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3231 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3232 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3233 | "" | |
aebf2462 | 3234 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3235 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3236 | |
655f2eb9 | 3237 | (define_insn "*msubdf4" |
0551c32d RH |
3238 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3239 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3240 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3241 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3242 | "" |
aebf2462 | 3243 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3244 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3245 | |
26102535 RH |
3246 | (define_insn "*msubdf4_trunc" |
3247 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3248 | (float_truncate:SF | |
3249 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3250 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3251 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3252 | "" | |
aebf2462 | 3253 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3254 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3255 | |
c65ebc55 | 3256 | (define_insn "*nmuldf3" |
0551c32d RH |
3257 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3258 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3259 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3260 | "" |
aebf2462 | 3261 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3262 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3263 | |
26102535 RH |
3264 | (define_insn "*nmuldf3_trunc" |
3265 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3266 | (float_truncate:SF | |
3267 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3268 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3269 | "" | |
aebf2462 | 3270 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3271 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3272 | |
655f2eb9 | 3273 | (define_insn "*nmadddf4" |
0551c32d | 3274 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3275 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3276 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3277 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3278 | "" |
aebf2462 | 3279 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3280 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3281 | |
3282 | (define_insn "*nmadddf4_alts" | |
3283 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3284 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3285 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3286 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3287 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3288 | "" | |
aebf2462 | 3289 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3290 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3291 | |
52ad4d7b | 3292 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3293 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3294 | (float_truncate:SF | |
52ad4d7b ZW |
3295 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3296 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3297 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3298 | "" |
aebf2462 | 3299 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3300 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3301 | |
52ad4d7b ZW |
3302 | (define_insn "*nmadddf4_truncsf_alts" |
3303 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3304 | (float_truncate:SF | |
3305 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3306 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3307 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3308 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3309 | "" | |
3310 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3311 | [(set_attr "itanium_class" "fmac")]) | |
3312 | ||
26102535 RH |
3313 | (define_expand "divdf3" |
3314 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3315 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3316 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3317 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3318 | { |
3319 | rtx insn; | |
dbdd120f | 3320 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3321 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3322 | else | |
3323 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3324 | emit_insn (insn); | |
3325 | DONE; | |
1d5d7a21 | 3326 | }) |
26102535 RH |
3327 | |
3328 | (define_insn_and_split "divdf3_internal_lat" | |
3329 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3330 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3331 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3332 | (clobber (match_scratch:XF 3 "=&f")) |
3333 | (clobber (match_scratch:XF 4 "=&f")) | |
3334 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 3335 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 3336 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3337 | "#" |
3338 | "&& reload_completed" | |
02befdf4 | 3339 | [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) |
086c0f96 RH |
3340 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3341 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3342 | (use (const_int 0))]) |
26102535 | 3343 | (cond_exec (ne (match_dup 6) (const_int 0)) |
02befdf4 | 3344 | (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) |
26102535 RH |
3345 | (use (const_int 1))])) |
3346 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3347 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3348 | (minus:XF (match_dup 12) |
3349 | (mult:XF (match_dup 9) (match_dup 7)))) | |
26102535 RH |
3350 | (use (const_int 1))])) |
3351 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3352 | (parallel [(set (match_dup 3) | |
02befdf4 | 3353 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3354 | (match_dup 3))) |
3355 | (use (const_int 1))])) | |
3356 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3357 | (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3358 | (use (const_int 1))])) |
3359 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3360 | (parallel [(set (match_dup 7) | |
02befdf4 | 3361 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3362 | (match_dup 7))) |
3363 | (use (const_int 1))])) | |
3364 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3365 | (parallel [(set (match_dup 3) | |
02befdf4 | 3366 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3367 | (match_dup 3))) |
3368 | (use (const_int 1))])) | |
3369 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3370 | (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5))) |
26102535 RH |
3371 | (use (const_int 1))])) |
3372 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3373 | (parallel [(set (match_dup 7) | |
02befdf4 | 3374 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3375 | (match_dup 7))) |
3376 | (use (const_int 1))])) | |
3377 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3378 | (parallel [(set (match_dup 10) | |
3379 | (float_truncate:DF | |
02befdf4 | 3380 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3381 | (match_dup 3)))) |
3382 | (use (const_int 1))])) | |
3383 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3384 | (parallel [(set (match_dup 7) | |
02befdf4 | 3385 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3386 | (match_dup 7))) |
3387 | (use (const_int 1))])) | |
3388 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3389 | (parallel [(set (match_dup 11) | |
3390 | (float_truncate:DF | |
52ad4d7b ZW |
3391 | (minus:XF (match_dup 8) |
3392 | (mult:XF (match_dup 9) (match_dup 3))))) | |
26102535 RH |
3393 | (use (const_int 1))])) |
3394 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3395 | (set (match_dup 0) | |
02befdf4 | 3396 | (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3397 | (match_dup 3))))) |
3398 | ] | |
1d5d7a21 | 3399 | { |
02befdf4 ZW |
3400 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3401 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3402 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 RH |
3403 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
3404 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
02befdf4 | 3405 | operands[12] = CONST1_RTX (XFmode); |
1d5d7a21 | 3406 | } |
26102535 RH |
3407 | [(set_attr "predicable" "no")]) |
3408 | ||
3409 | (define_insn_and_split "divdf3_internal_thr" | |
3410 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3411 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3412 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 | 3413 | (clobber (match_scratch:XF 3 "=&f")) |
26102535 | 3414 | (clobber (match_scratch:DF 4 "=f")) |
f2f90c63 | 3415 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3416 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
3417 | "#" |
3418 | "&& reload_completed" | |
02befdf4 | 3419 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3420 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3421 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3422 | (use (const_int 0))]) |
26102535 RH |
3423 | (cond_exec (ne (match_dup 5) (const_int 0)) |
3424 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3425 | (minus:XF (match_dup 10) |
3426 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3427 | (use (const_int 1))])) |
3428 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3429 | (parallel [(set (match_dup 6) | |
02befdf4 | 3430 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3431 | (match_dup 6))) |
3432 | (use (const_int 1))])) | |
3433 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3434 | (parallel [(set (match_dup 3) | |
02befdf4 | 3435 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3436 | (use (const_int 1))])) |
3437 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3438 | (parallel [(set (match_dup 6) | |
02befdf4 | 3439 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3440 | (match_dup 6))) |
3441 | (use (const_int 1))])) | |
3442 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3443 | (parallel [(set (match_dup 3) | |
02befdf4 | 3444 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3445 | (use (const_int 1))])) |
3446 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3447 | (parallel [(set (match_dup 6) | |
02befdf4 | 3448 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3449 | (match_dup 6))) |
3450 | (use (const_int 1))])) | |
3451 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3452 | (parallel [(set (match_dup 9) | |
3453 | (float_truncate:DF | |
aa42f99d | 3454 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3455 | (use (const_int 1))])) |
3456 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3457 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3458 | (minus:DF (match_dup 1) |
3459 | (mult:DF (match_dup 2) (match_dup 9)))) | |
26102535 RH |
3460 | (use (const_int 1))])) |
3461 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3462 | (set (match_dup 0) | |
3463 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3464 | (match_dup 9)))) | |
3465 | ] | |
1d5d7a21 | 3466 | { |
02befdf4 ZW |
3467 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3468 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3469 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3470 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
02befdf4 | 3471 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3472 | } |
26102535 | 3473 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3474 | |
3475 | ;; Inline square root. | |
3476 | ||
3477 | (define_expand "sqrtdf2" | |
3478 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3479 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3480 | "TARGET_INLINE_SQRT" | |
3481 | { | |
3482 | rtx insn; | |
b38ba463 | 3483 | #if 0 |
e820471b | 3484 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3485 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3486 | else |
b38ba463 | 3487 | #else |
e820471b | 3488 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3489 | #endif |
e820471b | 3490 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3491 | emit_insn (insn); |
3492 | DONE; | |
3493 | }) | |
3494 | ||
3495 | ;; Latency-optimized square root. | |
3496 | ;; FIXME: Implement. | |
3497 | ||
3498 | ;; Throughput-optimized square root. | |
3499 | ||
3500 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3501 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3502 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3503 | ;; Register r2 in optimization guide. | |
3504 | (clobber (match_scratch:DI 2 "=r")) | |
3505 | ;; Register f8 in optimization guide | |
3506 | (clobber (match_scratch:XF 3 "=&f")) | |
3507 | ;; Register f9 in optimization guide | |
3508 | (clobber (match_scratch:XF 4 "=&f")) | |
3509 | ;; Register f10 in optimization guide | |
3510 | (clobber (match_scratch:XF 5 "=&f")) | |
3511 | ;; Register p6 in optimization guide. | |
3512 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3513 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3514 | "#" |
3515 | "&& reload_completed" | |
3516 | [ ;; exponent of +1/2 in r2 | |
3517 | (set (match_dup 2) (const_int 65534)) | |
3518 | ;; +1/2 in f10 | |
3519 | (set (match_dup 5) | |
3520 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3521 | ;; Step 1 | |
3522 | ;; y0 = 1/sqrt(a) in f7 | |
3523 | (parallel [(set (match_dup 7) | |
3524 | (div:XF (const_int 1) | |
3525 | (sqrt:XF (match_dup 8)))) | |
3526 | (set (match_dup 6) | |
3527 | (unspec:BI [(match_dup 8)] | |
3528 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3529 | (use (const_int 0))]) | |
3530 | ;; Step 2 | |
3531 | ;; H0 = 1/2 * y0 in f8 | |
3532 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3533 | (parallel [(set (match_dup 3) | |
3534 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3535 | (match_dup 9))) | |
3536 | (use (const_int 1))])) | |
3537 | ;; Step 3 | |
3538 | ;; G0 = a * y0 in f7 | |
3539 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3540 | (parallel [(set (match_dup 7) | |
3541 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3542 | (match_dup 9))) | |
3543 | (use (const_int 1))])) | |
3544 | ;; Step 4 | |
3545 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3546 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3547 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3548 | (minus:XF (match_dup 5) |
3549 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3550 | (use (const_int 1))])) |
3551 | ;; Step 5 | |
3552 | ;; H1 = H0 + r0 * H0 in f8 | |
3553 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3554 | (parallel [(set (match_dup 3) | |
3555 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3556 | (match_dup 3))) | |
3557 | (use (const_int 1))])) | |
3558 | ;; Step 6 | |
3559 | ;; G1 = G0 + r0 * G0 in f7 | |
3560 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3561 | (parallel [(set (match_dup 7) | |
3562 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3563 | (match_dup 7))) | |
3564 | (use (const_int 1))])) | |
3565 | ;; Step 7 | |
3566 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3567 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3568 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3569 | (minus:XF (match_dup 5) |
3570 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3571 | (use (const_int 1))])) |
3572 | ;; Step 8 | |
3573 | ;; H2 = H1 + r1 * H1 in f8 | |
3574 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3575 | (parallel [(set (match_dup 3) | |
3576 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3577 | (match_dup 3))) | |
3578 | (use (const_int 1))])) | |
3579 | ;; Step 9 | |
3580 | ;; G2 = G1 + r1 * G1 in f7 | |
3581 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3582 | (parallel [(set (match_dup 7) | |
3583 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3584 | (match_dup 7))) | |
3585 | (use (const_int 1))])) | |
3586 | ;; Step 10 | |
3587 | ;; d2 = a - G2 * G2 in f9 | |
3588 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3589 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3590 | (minus:XF (match_dup 8) |
3591 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3592 | (use (const_int 1))])) |
3593 | ;; Step 11 | |
3594 | ;; G3 = G2 + d2 * H2 in f7 | |
3595 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3596 | (parallel [(set (match_dup 7) | |
3597 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3598 | (match_dup 7))) | |
3599 | (use (const_int 1))])) | |
3600 | ;; Step 12 | |
3601 | ;; d3 = a - G3 * G3 in f9 | |
3602 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3603 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3604 | (minus:XF (match_dup 8) |
3605 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3606 | (use (const_int 1))])) |
3607 | ;; Step 13 | |
3608 | ;; S = G3 + d3 * H2 in f7 | |
3609 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3610 | (parallel [(set (match_dup 0) | |
3611 | (float_truncate:DF | |
3612 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3613 | (match_dup 7)))) | |
3614 | (use (const_int 0))]))] | |
3615 | { | |
3616 | /* Generate 82-bit versions of the input and output operands. */ | |
3617 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3618 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3619 | /* Generate required floating-point constants. */ | |
3620 | operands[9] = CONST0_RTX (XFmode); | |
3621 | } | |
3622 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3623 | \f |
3624 | ;; :::::::::::::::::::: | |
3625 | ;; :: | |
3626 | ;; :: 80 bit floating point arithmetic | |
3627 | ;; :: | |
3628 | ;; :::::::::::::::::::: | |
3629 | ||
02befdf4 ZW |
3630 | (define_insn "addxf3" |
3631 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3632 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3633 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3634 | "" | |
aebf2462 | 3635 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3636 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3637 | |
02befdf4 | 3638 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3639 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3640 | (float_truncate:SF | |
02befdf4 ZW |
3641 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3642 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3643 | "" | |
aebf2462 | 3644 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3645 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3646 | |
02befdf4 | 3647 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3648 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3649 | (float_truncate:DF | |
02befdf4 ZW |
3650 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3651 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3652 | "" | |
aebf2462 | 3653 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3654 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3655 | |
02befdf4 ZW |
3656 | (define_insn "subxf3" |
3657 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3658 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3659 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3660 | "" | |
aebf2462 | 3661 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3662 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3663 | |
02befdf4 | 3664 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3665 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3666 | (float_truncate:SF | |
02befdf4 ZW |
3667 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3668 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3669 | "" | |
aebf2462 | 3670 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3671 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3672 | |
02befdf4 | 3673 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3674 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3675 | (float_truncate:DF | |
02befdf4 ZW |
3676 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3677 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3678 | "" | |
aebf2462 | 3679 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3680 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3681 | |
02befdf4 ZW |
3682 | (define_insn "mulxf3" |
3683 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3684 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3685 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3686 | "" | |
aebf2462 | 3687 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3688 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3689 | |
02befdf4 | 3690 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3691 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3692 | (float_truncate:SF | |
02befdf4 ZW |
3693 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3694 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3695 | "" | |
aebf2462 | 3696 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3697 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3698 | |
02befdf4 | 3699 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3700 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3701 | (float_truncate:DF | |
02befdf4 ZW |
3702 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3703 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3704 | "" | |
aebf2462 | 3705 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3706 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3707 | |
02befdf4 ZW |
3708 | (define_insn "*mulxf3_alts" |
3709 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3710 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3711 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3712 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3713 | "" |
aebf2462 | 3714 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3715 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3716 | |
02befdf4 | 3717 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3718 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3719 | (float_truncate:SF | |
02befdf4 ZW |
3720 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3721 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3722 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3723 | "" |
aebf2462 | 3724 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3725 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3726 | |
02befdf4 | 3727 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3728 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3729 | (float_truncate:DF | |
02befdf4 ZW |
3730 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3731 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3732 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3733 | "" |
aebf2462 | 3734 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3735 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3736 | |
02befdf4 ZW |
3737 | (define_insn "absxf2" |
3738 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3739 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3740 | "" | |
aebf2462 | 3741 | "fabs %0 = %F1" |
52e12ad0 | 3742 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3743 | |
02befdf4 ZW |
3744 | (define_insn "negxf2" |
3745 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3746 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3747 | "" | |
aebf2462 | 3748 | "fneg %0 = %F1" |
52e12ad0 | 3749 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3750 | |
02befdf4 ZW |
3751 | (define_insn "*nabsxf2" |
3752 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3753 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3754 | "" | |
aebf2462 | 3755 | "fnegabs %0 = %F1" |
52e12ad0 | 3756 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3757 | |
046625fa RH |
3758 | (define_insn "copysignxf3" |
3759 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3760 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3761 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3762 | UNSPEC_COPYSIGN))] | |
3763 | "" | |
3764 | "fmerge.s %0 = %F2, %F1" | |
3765 | [(set_attr "itanium_class" "fmisc")]) | |
3766 | ||
3767 | (define_insn "*ncopysignxf3" | |
3768 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3769 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3770 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3771 | UNSPEC_COPYSIGN)))] | |
3772 | "" | |
3773 | "fmerge.ns %0 = %F2, %F1" | |
3774 | [(set_attr "itanium_class" "fmisc")]) | |
3775 | ||
7ae4d8d4 | 3776 | (define_insn "sminxf3" |
02befdf4 ZW |
3777 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3778 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3779 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3780 | "" | |
aebf2462 | 3781 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3782 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3783 | |
7ae4d8d4 | 3784 | (define_insn "smaxxf3" |
02befdf4 ZW |
3785 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3786 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3787 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3788 | "" | |
aebf2462 | 3789 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3790 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3791 | |
02befdf4 ZW |
3792 | (define_insn "*maddxf4" |
3793 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3794 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3795 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3796 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3797 | "" | |
aebf2462 | 3798 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3799 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3800 | |
02befdf4 | 3801 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3802 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3803 | (float_truncate:SF | |
02befdf4 ZW |
3804 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3805 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3806 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3807 | "" | |
aebf2462 | 3808 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3809 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3810 | |
02befdf4 | 3811 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3812 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3813 | (float_truncate:DF | |
02befdf4 ZW |
3814 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3815 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3816 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3817 | "" | |
aebf2462 | 3818 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3819 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3820 | |
02befdf4 ZW |
3821 | (define_insn "*maddxf4_alts" |
3822 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3823 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3824 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3825 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3826 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3827 | "" |
aebf2462 | 3828 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3829 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3830 | |
b38ba463 ZW |
3831 | (define_insn "*maddxf4_alts_truncsf" |
3832 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3833 | (float_truncate:SF | |
3834 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3835 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3836 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3837 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3838 | "" | |
3839 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3840 | [(set_attr "itanium_class" "fmac")]) | |
3841 | ||
02befdf4 | 3842 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3843 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3844 | (float_truncate:DF | |
02befdf4 ZW |
3845 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3846 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3847 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3848 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3849 | "" |
aebf2462 | 3850 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3851 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3852 | |
02befdf4 ZW |
3853 | (define_insn "*msubxf4" |
3854 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3855 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3856 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3857 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3858 | "" | |
aebf2462 | 3859 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3860 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3861 | |
02befdf4 | 3862 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3863 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3864 | (float_truncate:SF | |
02befdf4 ZW |
3865 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3866 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3867 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3868 | "" | |
aebf2462 | 3869 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3870 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3871 | |
02befdf4 | 3872 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3873 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3874 | (float_truncate:DF | |
02befdf4 ZW |
3875 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3876 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3877 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3878 | "" | |
aebf2462 | 3879 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3880 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3881 | |
02befdf4 ZW |
3882 | (define_insn "*nmulxf3" |
3883 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3884 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3885 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3886 | "" | |
aebf2462 | 3887 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3888 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3889 | |
02befdf4 | 3890 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3891 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3892 | (float_truncate:SF | |
02befdf4 ZW |
3893 | (neg:XF (mult:XF |
3894 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3895 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3896 | "" | |
aebf2462 | 3897 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3898 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3899 | |
02befdf4 | 3900 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3901 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3902 | (float_truncate:DF | |
02befdf4 ZW |
3903 | (neg:XF (mult:XF |
3904 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3905 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3906 | "" | |
aebf2462 | 3907 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3908 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3909 | |
02befdf4 ZW |
3910 | (define_insn "*nmaddxf4" |
3911 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3912 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3913 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3914 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3915 | )))] | |
02befdf4 | 3916 | "" |
aebf2462 | 3917 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3918 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3919 | |
02befdf4 | 3920 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3921 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3922 | (float_truncate:SF | |
52ad4d7b ZW |
3923 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3924 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3925 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3926 | ))))] | |
02befdf4 | 3927 | "" |
aebf2462 | 3928 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3929 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3930 | |
02befdf4 | 3931 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3932 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3933 | (float_truncate:DF | |
52ad4d7b ZW |
3934 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3935 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3936 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3937 | ))))] | |
02befdf4 | 3938 | "" |
aebf2462 | 3939 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3940 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3941 | |
02befdf4 ZW |
3942 | (define_insn "*nmaddxf4_alts" |
3943 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3944 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3945 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3946 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3947 | ))) | |
655f2eb9 | 3948 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3949 | "" |
aebf2462 | 3950 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3951 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3952 | |
52ad4d7b ZW |
3953 | (define_insn "*nmaddxf4_truncsf_alts" |
3954 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3955 | (float_truncate:SF | |
3956 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
3957 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3958 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3959 | )))) | |
3960 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3961 | "" | |
3962 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
3963 | [(set_attr "itanium_class" "fmac")]) | |
3964 | ||
02befdf4 | 3965 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
3966 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3967 | (float_truncate:DF | |
52ad4d7b ZW |
3968 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3969 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3970 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3971 | )))) | |
26102535 | 3972 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3973 | "" |
aebf2462 | 3974 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3975 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3976 | |
02befdf4 ZW |
3977 | (define_expand "divxf3" |
3978 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
3979 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
3980 | (match_operand:XF 2 "fr_register_operand" "")))] | |
3981 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 RH |
3982 | { |
3983 | rtx insn; | |
dbdd120f | 3984 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
02befdf4 | 3985 | insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]); |
26102535 | 3986 | else |
02befdf4 | 3987 | insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]); |
26102535 RH |
3988 | emit_insn (insn); |
3989 | DONE; | |
1d5d7a21 | 3990 | }) |
26102535 | 3991 | |
02befdf4 ZW |
3992 | (define_insn_and_split "divxf3_internal_lat" |
3993 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
3994 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
3995 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
3996 | (clobber (match_scratch:XF 3 "=&f")) | |
3997 | (clobber (match_scratch:XF 4 "=&f")) | |
3998 | (clobber (match_scratch:XF 5 "=&f")) | |
3999 | (clobber (match_scratch:XF 6 "=&f")) | |
f2f90c63 | 4000 | (clobber (match_scratch:BI 7 "=c"))] |
dbdd120f | 4001 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
4002 | "#" |
4003 | "&& reload_completed" | |
02befdf4 | 4004 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4005 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
4006 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4007 | (use (const_int 0))]) |
26102535 RH |
4008 | (cond_exec (ne (match_dup 7) (const_int 0)) |
4009 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4010 | (minus:XF (match_dup 8) |
4011 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4012 | (use (const_int 1))])) |
4013 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4014 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4015 | (use (const_int 1))])) |
4016 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4017 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4018 | (use (const_int 1))])) |
4019 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4020 | (parallel [(set (match_dup 6) | |
02befdf4 | 4021 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
4022 | (match_dup 3))) |
4023 | (use (const_int 1))])) | |
4024 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4025 | (parallel [(set (match_dup 3) | |
02befdf4 | 4026 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
26102535 RH |
4027 | (match_dup 3))) |
4028 | (use (const_int 1))])) | |
4029 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4030 | (parallel [(set (match_dup 5) | |
02befdf4 | 4031 | (plus:XF (mult:XF (match_dup 6) (match_dup 0)) |
26102535 RH |
4032 | (match_dup 0))) |
4033 | (use (const_int 1))])) | |
4034 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4035 | (parallel [(set (match_dup 0) | |
02befdf4 | 4036 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
4037 | (match_dup 0))) |
4038 | (use (const_int 1))])) | |
4039 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4040 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4041 | (minus:XF (match_dup 1) |
4042 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4043 | (use (const_int 1))])) |
4044 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4045 | (parallel [(set (match_dup 3) | |
02befdf4 | 4046 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4047 | (match_dup 4))) |
4048 | (use (const_int 1))])) | |
4049 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4050 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4051 | (minus:XF (match_dup 8) |
4052 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4053 | (use (const_int 1))])) |
4054 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4055 | (parallel [(set (match_dup 0) | |
02befdf4 | 4056 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4057 | (match_dup 0))) |
4058 | (use (const_int 1))])) | |
4059 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4060 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4061 | (minus:XF (match_dup 1) |
4062 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4063 | (use (const_int 1))])) |
4064 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4065 | (set (match_dup 0) | |
02befdf4 | 4066 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4067 | (match_dup 3)))) |
4068 | ] | |
02befdf4 | 4069 | "operands[8] = CONST1_RTX (XFmode);" |
26102535 RH |
4070 | [(set_attr "predicable" "no")]) |
4071 | ||
02befdf4 ZW |
4072 | (define_insn_and_split "divxf3_internal_thr" |
4073 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4074 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4075 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4076 | (clobber (match_scratch:XF 3 "=&f")) | |
4077 | (clobber (match_scratch:XF 4 "=&f")) | |
f2f90c63 | 4078 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 4079 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
4080 | "#" |
4081 | "&& reload_completed" | |
02befdf4 | 4082 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4083 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
4084 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 4085 | (use (const_int 0))]) |
26102535 RH |
4086 | (cond_exec (ne (match_dup 5) (const_int 0)) |
4087 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4088 | (minus:XF (match_dup 6) |
4089 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4090 | (use (const_int 1))])) |
4091 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4092 | (parallel [(set (match_dup 4) | |
02befdf4 | 4093 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4094 | (match_dup 0))) |
4095 | (use (const_int 1))])) | |
4096 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4097 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4098 | (use (const_int 1))])) |
4099 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4100 | (parallel [(set (match_dup 3) | |
02befdf4 | 4101 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
26102535 RH |
4102 | (match_dup 4))) |
4103 | (use (const_int 1))])) | |
4104 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4105 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4106 | (use (const_int 1))])) |
4107 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4108 | (parallel [(set (match_dup 0) | |
52ad4d7b ZW |
4109 | (minus:XF (match_dup 6) |
4110 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4111 | (use (const_int 1))])) |
4112 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4113 | (parallel [(set (match_dup 0) | |
02befdf4 | 4114 | (plus:XF (mult:XF (match_dup 0) (match_dup 3)) |
26102535 RH |
4115 | (match_dup 3))) |
4116 | (use (const_int 1))])) | |
4117 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4118 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4119 | (minus:XF (match_dup 1) |
4120 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4121 | (use (const_int 1))])) |
4122 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4123 | (parallel [(set (match_dup 3) | |
02befdf4 | 4124 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4125 | (match_dup 4))) |
4126 | (use (const_int 1))])) | |
4127 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4128 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4129 | (minus:XF (match_dup 6) |
4130 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4131 | (use (const_int 1))])) |
4132 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4133 | (parallel [(set (match_dup 0) | |
02befdf4 | 4134 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4135 | (match_dup 0))) |
4136 | (use (const_int 1))])) | |
4137 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4138 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4139 | (minus:XF (match_dup 1) |
4140 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4141 | (use (const_int 1))])) |
4142 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4143 | (set (match_dup 0) | |
02befdf4 | 4144 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4145 | (match_dup 3)))) |
4146 | ] | |
02befdf4 | 4147 | "operands[6] = CONST1_RTX (XFmode);" |
26102535 RH |
4148 | [(set_attr "predicable" "no")]) |
4149 | ||
b38ba463 ZW |
4150 | ;; Inline square root. |
4151 | ||
4152 | (define_expand "sqrtxf2" | |
4153 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4154 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
4155 | "TARGET_INLINE_SQRT" | |
4156 | { | |
4157 | rtx insn; | |
b38ba463 | 4158 | #if 0 |
e820471b | 4159 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 4160 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 4161 | else |
b38ba463 | 4162 | #else |
e820471b | 4163 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 4164 | #endif |
e820471b | 4165 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
4166 | emit_insn (insn); |
4167 | DONE; | |
4168 | }) | |
4169 | ||
4170 | ;; Latency-optimized square root. | |
4171 | ;; FIXME: Implement. | |
4172 | ||
4173 | ;; Throughput-optimized square root. | |
4174 | ||
4175 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4176 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4177 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
4178 | ;; Register r2 in optimization guide. | |
4179 | (clobber (match_scratch:DI 2 "=r")) | |
4180 | ;; Register f8 in optimization guide | |
4181 | (clobber (match_scratch:XF 3 "=&f")) | |
4182 | ;; Register f9 in optimization guide | |
4183 | (clobber (match_scratch:XF 4 "=&f")) | |
4184 | ;; Register f10 in optimization guide | |
4185 | (clobber (match_scratch:XF 5 "=&f")) | |
4186 | ;; Register f11 in optimization guide | |
4187 | (clobber (match_scratch:XF 6 "=&f")) | |
4188 | ;; Register p6 in optimization guide. | |
4189 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 4190 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
4191 | "#" |
4192 | "&& reload_completed" | |
4193 | [ ;; exponent of +1/2 in r2 | |
4194 | (set (match_dup 2) (const_int 65534)) | |
4195 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4196 | (set (match_dup 3) | |
4197 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4198 | ;; Step 1 | |
4199 | ;; y0 = 1/sqrt(a) in f7 | |
4200 | (parallel [(set (match_dup 8) | |
4201 | (div:XF (const_int 1) | |
4202 | (sqrt:XF (match_dup 9)))) | |
4203 | (set (match_dup 7) | |
4204 | (unspec:BI [(match_dup 9)] | |
4205 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
4206 | (use (const_int 0))]) | |
4207 | ;; Step 2 | |
4208 | ;; H0 = 1/2 * y0 in f9 | |
4209 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4210 | (parallel [(set (match_dup 4) | |
4211 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4212 | (match_dup 10))) | |
4213 | (use (const_int 1))])) | |
4214 | ;; Step 3 | |
4215 | ;; S0 = a * y0 in f7 | |
4216 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4217 | (parallel [(set (match_dup 8) | |
4218 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4219 | (match_dup 10))) | |
4220 | (use (const_int 1))])) | |
4221 | ;; Step 4 | |
4222 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4223 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4224 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4225 | (minus:XF (match_dup 3) |
4226 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4227 | (use (const_int 1))])) |
4228 | ;; Step 5 | |
4229 | ;; H1 = H0 + d0 * H0 in f9 | |
4230 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4231 | (parallel [(set (match_dup 4) | |
4232 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4233 | (match_dup 4))) | |
4234 | (use (const_int 1))])) | |
4235 | ;; Step 6 | |
4236 | ;; S1 = S0 + d0 * S0 in f7 | |
4237 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4238 | (parallel [(set (match_dup 8) | |
4239 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4240 | (match_dup 8))) | |
4241 | (use (const_int 1))])) | |
4242 | ;; Step 7 | |
4243 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4244 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4245 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4246 | (minus:XF (match_dup 3) |
4247 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4248 | (use (const_int 1))])) |
4249 | ;; Step 8 | |
4250 | ;; H2 = H1 + d1 * H1 in f9 | |
4251 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4252 | (parallel [(set (match_dup 4) | |
4253 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4254 | (match_dup 4))) | |
4255 | (use (const_int 1))])) | |
4256 | ;; Step 9 | |
4257 | ;; S2 = S1 + d1 * S1 in f7 | |
4258 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4259 | (parallel [(set (match_dup 8) | |
4260 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4261 | (match_dup 8))) | |
4262 | (use (const_int 1))])) | |
4263 | ;; Step 10 | |
4264 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4265 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4266 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4267 | (minus:XF (match_dup 3) |
4268 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4269 | (use (const_int 1))])) |
4270 | ;; Step 11 | |
4271 | ;; e2 = a - S2 * S2 in f8 | |
4272 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4273 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4274 | (minus:XF (match_dup 9) |
4275 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4276 | (use (const_int 1))])) |
4277 | ;; Step 12 | |
4278 | ;; S3 = S2 + e2 * H2 in f7 | |
4279 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4280 | (parallel [(set (match_dup 8) | |
4281 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4282 | (match_dup 8))) | |
4283 | (use (const_int 1))])) | |
4284 | ;; Step 13 | |
4285 | ;; H3 = H2 + d2 * H2 in f9 | |
4286 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4287 | (parallel [(set (match_dup 4) | |
4288 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4289 | (match_dup 4))) | |
4290 | (use (const_int 1))])) | |
4291 | ;; Step 14 | |
4292 | ;; e3 = a - S3 * S3 in f8 | |
4293 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4294 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4295 | (minus:XF (match_dup 9) |
4296 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4297 | (use (const_int 1))])) |
4298 | ;; Step 15 | |
4299 | ;; S = S3 + e3 * H3 in f7 | |
4300 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4301 | (parallel [(set (match_dup 0) | |
4302 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4303 | (match_dup 8))) | |
4304 | (use (const_int 0))]))] | |
4305 | { | |
4306 | /* Generate 82-bit versions of the input and output operands. */ | |
4307 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4308 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4309 | /* Generate required floating-point constants. */ | |
4310 | operands[10] = CONST0_RTX (XFmode); | |
4311 | } | |
4312 | [(set_attr "predicable" "no")]) | |
4313 | ||
26102535 RH |
4314 | ;; ??? frcpa works like cmp.foo.unc. |
4315 | ||
655f2eb9 | 4316 | (define_insn "*recip_approx" |
02befdf4 ZW |
4317 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
4318 | (div:XF (const_int 1) | |
4319 | (match_operand:XF 3 "fr_register_operand" "f"))) | |
f2f90c63 | 4320 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4321 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4322 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4323 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4324 | "" |
655f2eb9 | 4325 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4326 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4327 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4328 | \f |
4329 | ;; :::::::::::::::::::: | |
4330 | ;; :: | |
4331 | ;; :: 32 bit Integer Shifts and Rotates | |
4332 | ;; :: | |
4333 | ;; :::::::::::::::::::: | |
4334 | ||
9c668921 | 4335 | (define_expand "ashlsi3" |
0551c32d RH |
4336 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4337 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4338 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4339 | "" |
9c668921 RH |
4340 | { |
4341 | if (GET_CODE (operands[2]) != CONST_INT) | |
4342 | { | |
4343 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4344 | we've got to get rid of stray bits outside the SImode register. */ | |
4345 | rtx subshift = gen_reg_rtx (DImode); | |
4346 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4347 | operands[2] = subshift; | |
4348 | } | |
1d5d7a21 | 4349 | }) |
9c668921 RH |
4350 | |
4351 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4352 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4353 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4354 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4355 | "" |
041f25e6 RH |
4356 | "@ |
4357 | shladd %0 = %1, %2, r0 | |
4358 | dep.z %0 = %1, %2, %E2 | |
4359 | shl %0 = %1, %2" | |
52e12ad0 | 4360 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4361 | |
4362 | (define_expand "ashrsi3" | |
0551c32d RH |
4363 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4364 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4365 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4366 | "" |
c65ebc55 | 4367 | { |
041f25e6 RH |
4368 | rtx subtarget = gen_reg_rtx (DImode); |
4369 | if (GET_CODE (operands[2]) == CONST_INT) | |
4370 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4371 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4372 | else | |
4373 | { | |
9c668921 | 4374 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4375 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4376 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4377 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4378 | } |
4379 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4380 | DONE; | |
1d5d7a21 | 4381 | }) |
c65ebc55 | 4382 | |
c65ebc55 | 4383 | (define_expand "lshrsi3" |
0551c32d RH |
4384 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4385 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4386 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4387 | "" |
c65ebc55 | 4388 | { |
041f25e6 RH |
4389 | rtx subtarget = gen_reg_rtx (DImode); |
4390 | if (GET_CODE (operands[2]) == CONST_INT) | |
4391 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4392 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4393 | else | |
4394 | { | |
9c668921 | 4395 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4396 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4397 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4398 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4399 | } |
4400 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4401 | DONE; | |
1d5d7a21 | 4402 | }) |
c65ebc55 | 4403 | |
c65ebc55 | 4404 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4405 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4406 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4407 | |
4408 | (define_expand "rotrsi3" | |
66db6b45 RH |
4409 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4410 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4411 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4412 | "" | |
66db6b45 RH |
4413 | { |
4414 | if (GET_MODE (operands[2]) != VOIDmode) | |
4415 | { | |
4416 | rtx tmp = gen_reg_rtx (DImode); | |
4417 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4418 | operands[2] = tmp; | |
4419 | } | |
1d5d7a21 | 4420 | }) |
66db6b45 RH |
4421 | |
4422 | (define_insn_and_split "*rotrsi3_internal" | |
4423 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4424 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4425 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4426 | "" | |
4427 | "#" | |
4428 | "reload_completed" | |
c65ebc55 | 4429 | [(set (match_dup 3) |
66db6b45 | 4430 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4431 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4432 | (set (match_dup 3) | |
66db6b45 RH |
4433 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4434 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4435 | ||
4436 | (define_expand "rotlsi3" | |
4437 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4438 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4439 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4440 | "" |
c65ebc55 JW |
4441 | { |
4442 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4443 | { |
4444 | rtx tmp = gen_reg_rtx (SImode); | |
4445 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4446 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4447 | DONE; | |
4448 | } | |
1d5d7a21 | 4449 | }) |
66db6b45 RH |
4450 | |
4451 | (define_insn_and_split "*rotlsi3_internal" | |
4452 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4453 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4454 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4455 | "" | |
4456 | "#" | |
4457 | "reload_completed" | |
4458 | [(set (match_dup 3) | |
4459 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4460 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4461 | (set (match_dup 3) | |
4462 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4463 | { |
4464 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4465 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
4466 | }) | |
c65ebc55 JW |
4467 | \f |
4468 | ;; :::::::::::::::::::: | |
4469 | ;; :: | |
4470 | ;; :: 64 bit Integer Shifts and Rotates | |
4471 | ;; :: | |
4472 | ;; :::::::::::::::::::: | |
4473 | ||
4474 | (define_insn "ashldi3" | |
52e12ad0 BS |
4475 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4476 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4477 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4478 | "" |
041f25e6 RH |
4479 | "@ |
4480 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4481 | shl %0 = %1, %2 |
041f25e6 | 4482 | shl %0 = %1, %2" |
52e12ad0 | 4483 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4484 | |
4485 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4486 | ||
4487 | (define_insn "*shladd" | |
0551c32d RH |
4488 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4489 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4490 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4491 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4492 | "" |
4493 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4494 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4495 | |
4496 | ;; This can be created by register elimination if operand3 of shladd is an | |
4497 | ;; eliminable register or has reg_equiv_constant set. | |
4498 | ||
4499 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4500 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4501 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4502 | ;; incorrectly. | |
4503 | ||
5527bf14 | 4504 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4505 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4506 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4507 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4508 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4509 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4510 | "reload_in_progress" | |
e820471b | 4511 | "* gcc_unreachable ();" |
c65ebc55 JW |
4512 | "reload_completed" |
4513 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4514 | (match_dup 3))) | |
c65ebc55 | 4515 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4516 | "" |
52e12ad0 | 4517 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4518 | |
4519 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4520 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4521 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4522 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4523 | "" |
52e12ad0 BS |
4524 | "@ |
4525 | shr %0 = %1, %2 | |
4526 | shr %0 = %1, %2" | |
4527 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4528 | |
4529 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4530 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4531 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4532 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4533 | "" |
52e12ad0 BS |
4534 | "@ |
4535 | shr.u %0 = %1, %2 | |
4536 | shr.u %0 = %1, %2" | |
4537 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4538 | |
4539 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4540 | ;; will load the operand into a register and call the pattern if the predicate | |
4541 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4542 | ;; verify that we have an appropriate constant in the expander. | |
4543 | ||
4544 | (define_expand "rotrdi3" | |
0551c32d RH |
4545 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4546 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4547 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4548 | "" | |
c65ebc55 JW |
4549 | { |
4550 | if (! shift_count_operand (operands[2], DImode)) | |
4551 | FAIL; | |
1d5d7a21 | 4552 | }) |
c65ebc55 JW |
4553 | |
4554 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4555 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4556 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4557 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4558 | "" | |
4559 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4560 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4561 | |
66db6b45 RH |
4562 | (define_expand "rotldi3" |
4563 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4564 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4565 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4566 | "" | |
66db6b45 RH |
4567 | { |
4568 | if (! shift_count_operand (operands[2], DImode)) | |
4569 | FAIL; | |
1d5d7a21 | 4570 | }) |
66db6b45 RH |
4571 | |
4572 | (define_insn "*rotldi3_internal" | |
4573 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4574 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4575 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4576 | "" | |
4577 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4578 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4579 | \f |
4580 | ;; :::::::::::::::::::: | |
4581 | ;; :: | |
4582 | ;; :: 128 bit Integer Shifts and Rotates | |
4583 | ;; :: | |
4584 | ;; :::::::::::::::::::: | |
4585 | ||
16d8386b JB |
4586 | (define_expand "ashlti3" |
4587 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4588 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4589 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4590 | "" | |
4591 | { | |
4592 | if (!dshift_count_operand (operands[2], DImode)) | |
4593 | FAIL; | |
4594 | }) | |
4595 | ||
4596 | (define_insn_and_split "*ashlti3_internal" | |
4597 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4598 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4599 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4600 | "" | |
4601 | "#" | |
4602 | "reload_completed" | |
4603 | [(const_int 0)] | |
4604 | { | |
4605 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4606 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4607 | rtx rh = gen_highpart (DImode, operands[0]); | |
4608 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4609 | rtx shiftlo = GEN_INT (shift & 63); | |
4610 | ||
4611 | if (shift & 64) | |
4612 | { | |
4613 | emit_move_insn (rl, const0_rtx); | |
4614 | if (shift & 63) | |
4615 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4616 | else | |
4617 | emit_move_insn (rh, lo); | |
4618 | } | |
4619 | else | |
4620 | { | |
4621 | rtx hi = gen_highpart (DImode, operands[1]); | |
4622 | ||
4623 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4624 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4625 | } | |
4626 | DONE; | |
4627 | }) | |
4628 | ||
f526a3c8 RH |
4629 | (define_expand "ashrti3" |
4630 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4631 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4632 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4633 | "" | |
4634 | { | |
4635 | if (!dshift_count_operand (operands[2], DImode)) | |
4636 | FAIL; | |
4637 | }) | |
4638 | ||
4639 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4640 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4641 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4642 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4643 | "" | |
4644 | "#" | |
4645 | "reload_completed" | |
4646 | [(const_int 0)] | |
4647 | { | |
4648 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4649 | rtx rl = gen_lowpart (DImode, operands[0]); |
4650 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4651 | rtx hi = gen_highpart (DImode, operands[1]); |
4652 | rtx shiftlo = GEN_INT (shift & 63); | |
4653 | ||
4654 | if (shift & 64) | |
4655 | { | |
16d8386b JB |
4656 | if (shift & 63) |
4657 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4658 | else | |
4659 | emit_move_insn (rl, hi); | |
4660 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4661 | } |
4662 | else | |
4663 | { | |
16d8386b JB |
4664 | rtx lo = gen_lowpart (DImode, operands[1]); |
4665 | ||
4666 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4667 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4668 | } |
4669 | DONE; | |
4670 | }) | |
4671 | ||
4672 | (define_expand "lshrti3" | |
4673 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4674 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4675 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4676 | "" | |
4677 | { | |
4678 | if (!dshift_count_operand (operands[2], DImode)) | |
4679 | FAIL; | |
4680 | }) | |
4681 | ||
4682 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4683 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4684 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4685 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4686 | "" | |
4687 | "#" | |
4688 | "reload_completed" | |
4689 | [(const_int 0)] | |
4690 | { | |
4691 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4692 | rtx rl = gen_lowpart (DImode, operands[0]); |
4693 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4694 | rtx hi = gen_highpart (DImode, operands[1]); |
4695 | rtx shiftlo = GEN_INT (shift & 63); | |
4696 | ||
4697 | if (shift & 64) | |
4698 | { | |
16d8386b JB |
4699 | if (shift & 63) |
4700 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4701 | else | |
4702 | emit_move_insn (rl, hi); | |
4703 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4704 | } |
4705 | else | |
4706 | { | |
16d8386b JB |
4707 | rtx lo = gen_lowpart (DImode, operands[1]); |
4708 | ||
4709 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4710 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4711 | } |
4712 | DONE; | |
4713 | }) | |
4714 | ||
a71aef0b JB |
4715 | (define_expand "rotlti3" |
4716 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4717 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4718 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4719 | "" | |
4720 | { | |
4721 | if (! dshift_count_operand (operands[2], DImode)) | |
4722 | FAIL; | |
4723 | }) | |
4724 | ||
4725 | (define_insn_and_split "*rotlti3_internal" | |
4726 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4727 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4728 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4729 | "" | |
4730 | "#" | |
4731 | "reload_completed" | |
4732 | [(const_int 0)] | |
4733 | { | |
4734 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4735 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4736 | rtx rh = gen_highpart (DImode, operands[0]); | |
4737 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4738 | rtx hi = gen_highpart (DImode, operands[1]); | |
4739 | rtx countlo = GEN_INT (-count & 63); | |
4740 | ||
4741 | if (count & 64) | |
4742 | { | |
4743 | if (count & 63) | |
4744 | { | |
4745 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4746 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4747 | } | |
4748 | else | |
4749 | { | |
4750 | emit_move_insn (rl, hi); | |
4751 | emit_move_insn (rh, lo); | |
4752 | } | |
4753 | } | |
4754 | else | |
4755 | { | |
4756 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4757 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4758 | } | |
4759 | DONE; | |
4760 | } | |
4761 | [(set_attr "itanium_class" "unknown")]) | |
4762 | ||
f526a3c8 RH |
4763 | (define_insn "shrp" |
4764 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4765 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4766 | (match_operand:DI 2 "gr_register_operand" "r") | |
4767 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4768 | UNSPEC_SHRP))] | |
4769 | "" | |
4770 | "shrp %0 = %1, %2, %3" | |
4771 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4772 | \f |
4773 | ;; :::::::::::::::::::: | |
4774 | ;; :: | |
058557c4 | 4775 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
4776 | ;; :: |
4777 | ;; :::::::::::::::::::: | |
4778 | ||
4779 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4780 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4781 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4782 | ;; This doesn't work for unary logical operations, because we don't call | |
4783 | ;; apply_distributive_law for them. | |
4784 | ||
4785 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4786 | ;; apply_distributive_law. We get inefficient code for | |
4787 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4788 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4789 | ;; (zero_extend (and (not A) B)) in combine. | |
4790 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4791 | ;; one_cmplsi2 pattern. | |
4792 | ||
058557c4 | 4793 | (define_insn "one_cmplsi2" |
0551c32d RH |
4794 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4795 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4796 | "" |
4797 | "andcm %0 = -1, %1" | |
52e12ad0 | 4798 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4799 | \f |
4800 | ;; :::::::::::::::::::: | |
4801 | ;; :: | |
058557c4 | 4802 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
4803 | ;; :: |
4804 | ;; :::::::::::::::::::: | |
4805 | ||
4806 | (define_insn "anddi3" | |
0551c32d RH |
4807 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4808 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4809 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4810 | "" |
4811 | "@ | |
4812 | and %0 = %2, %1 | |
aebf2462 | 4813 | fand %0 = %2, %1" |
52e12ad0 | 4814 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4815 | |
4816 | (define_insn "*andnot" | |
0551c32d RH |
4817 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4818 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4819 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4820 | "" |
4821 | "@ | |
4822 | andcm %0 = %2, %1 | |
aebf2462 | 4823 | fandcm %0 = %2, %1" |
52e12ad0 | 4824 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4825 | |
4826 | (define_insn "iordi3" | |
0551c32d RH |
4827 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4828 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4829 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4830 | "" |
4831 | "@ | |
4832 | or %0 = %2, %1 | |
aebf2462 | 4833 | for %0 = %2, %1" |
52e12ad0 | 4834 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4835 | |
4836 | (define_insn "xordi3" | |
0551c32d RH |
4837 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4838 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4839 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4840 | "" |
4841 | "@ | |
4842 | xor %0 = %2, %1 | |
aebf2462 | 4843 | fxor %0 = %2, %1" |
52e12ad0 | 4844 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4845 | |
4846 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4847 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4848 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4849 | "" |
4850 | "andcm %0 = -1, %1" | |
52e12ad0 | 4851 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4852 | \f |
4853 | ;; :::::::::::::::::::: | |
4854 | ;; :: | |
4855 | ;; :: Comparisons | |
4856 | ;; :: | |
4857 | ;; :::::::::::::::::::: | |
4858 | ||
f2f90c63 RH |
4859 | (define_expand "cmpbi" |
4860 | [(set (cc0) | |
4861 | (compare (match_operand:BI 0 "register_operand" "") | |
4862 | (match_operand:BI 1 "const_int_operand" "")))] | |
4863 | "" | |
f2f90c63 RH |
4864 | { |
4865 | ia64_compare_op0 = operands[0]; | |
4866 | ia64_compare_op1 = operands[1]; | |
4867 | DONE; | |
1d5d7a21 | 4868 | }) |
f2f90c63 | 4869 | |
c65ebc55 JW |
4870 | (define_expand "cmpsi" |
4871 | [(set (cc0) | |
0551c32d RH |
4872 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4873 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4874 | "" |
c65ebc55 JW |
4875 | { |
4876 | ia64_compare_op0 = operands[0]; | |
4877 | ia64_compare_op1 = operands[1]; | |
4878 | DONE; | |
1d5d7a21 | 4879 | }) |
c65ebc55 JW |
4880 | |
4881 | (define_expand "cmpdi" | |
4882 | [(set (cc0) | |
0551c32d RH |
4883 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4884 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4885 | "" |
c65ebc55 JW |
4886 | { |
4887 | ia64_compare_op0 = operands[0]; | |
4888 | ia64_compare_op1 = operands[1]; | |
4889 | DONE; | |
1d5d7a21 | 4890 | }) |
c65ebc55 JW |
4891 | |
4892 | (define_expand "cmpsf" | |
4893 | [(set (cc0) | |
0551c32d RH |
4894 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4895 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4896 | "" |
c65ebc55 JW |
4897 | { |
4898 | ia64_compare_op0 = operands[0]; | |
4899 | ia64_compare_op1 = operands[1]; | |
4900 | DONE; | |
1d5d7a21 | 4901 | }) |
c65ebc55 JW |
4902 | |
4903 | (define_expand "cmpdf" | |
4904 | [(set (cc0) | |
0551c32d RH |
4905 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4906 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4907 | "" |
c65ebc55 JW |
4908 | { |
4909 | ia64_compare_op0 = operands[0]; | |
4910 | ia64_compare_op1 = operands[1]; | |
4911 | DONE; | |
1d5d7a21 | 4912 | }) |
c65ebc55 | 4913 | |
02befdf4 | 4914 | (define_expand "cmpxf" |
c65ebc55 | 4915 | [(set (cc0) |
02befdf4 ZW |
4916 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
4917 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
4918 | "" | |
c65ebc55 JW |
4919 | { |
4920 | ia64_compare_op0 = operands[0]; | |
4921 | ia64_compare_op1 = operands[1]; | |
4922 | DONE; | |
1d5d7a21 | 4923 | }) |
c65ebc55 | 4924 | |
24ea7948 ZW |
4925 | (define_expand "cmptf" |
4926 | [(set (cc0) | |
4927 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
4928 | (match_operand:TF 1 "gr_register_operand" "")))] | |
4929 | "TARGET_HPUX" | |
4930 | { | |
4931 | ia64_compare_op0 = operands[0]; | |
4932 | ia64_compare_op1 = operands[1]; | |
4933 | DONE; | |
4934 | }) | |
4935 | ||
c65ebc55 | 4936 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4937 | [(set (match_operand:BI 0 "register_operand" "=c") |
4938 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4939 | [(match_operand:SI 2 "gr_register_operand" "r") |
4940 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4941 | "" |
4942 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4943 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4944 | |
18a3c539 JW |
4945 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4946 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4947 | ||
c65ebc55 | 4948 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4949 | [(set (match_operand:BI 0 "register_operand" "=c") |
4950 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4951 | [(match_operand:SI 2 "gr_register_operand" "r") |
4952 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4953 | "" |
18a3c539 | 4954 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4955 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4956 | |
4957 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4958 | [(set (match_operand:BI 0 "register_operand" "=c") |
4959 | (match_operator:BI 1 "normal_comparison_operator" | |
4960 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4961 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4962 | "" |
f2f90c63 | 4963 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4964 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4965 | |
18a3c539 JW |
4966 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4967 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4968 | ||
c65ebc55 | 4969 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4970 | [(set (match_operand:BI 0 "register_operand" "=c") |
4971 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4972 | [(match_operand:DI 2 "gr_register_operand" "r") |
4973 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4974 | "" |
18a3c539 | 4975 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4976 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4977 | |
4978 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4979 | [(set (match_operand:BI 0 "register_operand" "=c") |
4980 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4981 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4982 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4983 | "" |
4984 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4985 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4986 | |
4987 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4988 | [(set (match_operand:BI 0 "register_operand" "=c") |
4989 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4990 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4991 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4992 | "" |
4993 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4994 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4995 | |
02befdf4 | 4996 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4997 | [(set (match_operand:BI 0 "register_operand" "=c") |
4998 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4999 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
5000 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
5001 | "" | |
3f622353 | 5002 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 5003 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 5004 | |
c65ebc55 JW |
5005 | ;; ??? Can this pattern be generated? |
5006 | ||
5007 | (define_insn "*bit_zero" | |
f2f90c63 RH |
5008 | [(set (match_operand:BI 0 "register_operand" "=c") |
5009 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
5010 | (const_int 1) |
5011 | (match_operand:DI 2 "immediate_operand" "n")) | |
5012 | (const_int 0)))] | |
5013 | "" | |
5014 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 5015 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5016 | |
5017 | (define_insn "*bit_one" | |
f2f90c63 RH |
5018 | [(set (match_operand:BI 0 "register_operand" "=c") |
5019 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
5020 | (const_int 1) |
5021 | (match_operand:DI 2 "immediate_operand" "n")) | |
5022 | (const_int 0)))] | |
5023 | "" | |
5024 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 5025 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5026 | \f |
5027 | ;; :::::::::::::::::::: | |
5028 | ;; :: | |
5029 | ;; :: Branches | |
5030 | ;; :: | |
5031 | ;; :::::::::::::::::::: | |
5032 | ||
5033 | (define_expand "beq" | |
f2f90c63 RH |
5034 | [(set (pc) |
5035 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5036 | (label_ref (match_operand 0 "" "")) |
5037 | (pc)))] | |
5038 | "" | |
f2f90c63 | 5039 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
5040 | |
5041 | (define_expand "bne" | |
f2f90c63 RH |
5042 | [(set (pc) |
5043 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5044 | (label_ref (match_operand 0 "" "")) |
5045 | (pc)))] | |
5046 | "" | |
f2f90c63 | 5047 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
5048 | |
5049 | (define_expand "blt" | |
f2f90c63 RH |
5050 | [(set (pc) |
5051 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5052 | (label_ref (match_operand 0 "" "")) |
5053 | (pc)))] | |
5054 | "" | |
f2f90c63 | 5055 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
5056 | |
5057 | (define_expand "ble" | |
f2f90c63 RH |
5058 | [(set (pc) |
5059 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5060 | (label_ref (match_operand 0 "" "")) |
5061 | (pc)))] | |
5062 | "" | |
f2f90c63 | 5063 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
5064 | |
5065 | (define_expand "bgt" | |
f2f90c63 RH |
5066 | [(set (pc) |
5067 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5068 | (label_ref (match_operand 0 "" "")) |
5069 | (pc)))] | |
5070 | "" | |
f2f90c63 | 5071 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
5072 | |
5073 | (define_expand "bge" | |
f2f90c63 RH |
5074 | [(set (pc) |
5075 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5076 | (label_ref (match_operand 0 "" "")) |
5077 | (pc)))] | |
5078 | "" | |
f2f90c63 | 5079 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
5080 | |
5081 | (define_expand "bltu" | |
f2f90c63 RH |
5082 | [(set (pc) |
5083 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5084 | (label_ref (match_operand 0 "" "")) |
5085 | (pc)))] | |
5086 | "" | |
f2f90c63 | 5087 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
5088 | |
5089 | (define_expand "bleu" | |
f2f90c63 RH |
5090 | [(set (pc) |
5091 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5092 | (label_ref (match_operand 0 "" "")) |
5093 | (pc)))] | |
5094 | "" | |
f2f90c63 | 5095 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
5096 | |
5097 | (define_expand "bgtu" | |
f2f90c63 RH |
5098 | [(set (pc) |
5099 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5100 | (label_ref (match_operand 0 "" "")) |
5101 | (pc)))] | |
5102 | "" | |
f2f90c63 | 5103 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5104 | |
5105 | (define_expand "bgeu" | |
f2f90c63 RH |
5106 | [(set (pc) |
5107 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5108 | (label_ref (match_operand 0 "" "")) |
5109 | (pc)))] | |
5110 | "" | |
f2f90c63 | 5111 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5112 | |
e57b9d65 | 5113 | (define_expand "bunordered" |
f2f90c63 RH |
5114 | [(set (pc) |
5115 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5116 | (label_ref (match_operand 0 "" "")) |
5117 | (pc)))] | |
5118 | "" | |
f2f90c63 | 5119 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5120 | |
5121 | (define_expand "bordered" | |
f2f90c63 RH |
5122 | [(set (pc) |
5123 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5124 | (label_ref (match_operand 0 "" "")) |
5125 | (pc)))] | |
5126 | "" | |
f2f90c63 | 5127 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5128 | |
6b6c1201 | 5129 | (define_insn "*br_true" |
c65ebc55 | 5130 | [(set (pc) |
6b6c1201 | 5131 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5132 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5133 | (const_int 0)]) |
5134 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5135 | (pc)))] |
5136 | "" | |
85548039 | 5137 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5138 | [(set_attr "itanium_class" "br") |
e5bde68a | 5139 | (set_attr "predicable" "no")]) |
c65ebc55 | 5140 | |
6b6c1201 | 5141 | (define_insn "*br_false" |
c65ebc55 | 5142 | [(set (pc) |
6b6c1201 | 5143 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5144 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5145 | (const_int 0)]) |
c65ebc55 | 5146 | (pc) |
6b6c1201 | 5147 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5148 | "" |
85548039 | 5149 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5150 | [(set_attr "itanium_class" "br") |
e5bde68a | 5151 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5152 | \f |
5153 | ;; :::::::::::::::::::: | |
5154 | ;; :: | |
5527bf14 RH |
5155 | ;; :: Counted loop operations |
5156 | ;; :: | |
5157 | ;; :::::::::::::::::::: | |
5158 | ||
5159 | (define_expand "doloop_end" | |
5160 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5161 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5162 | (use (match_operand 2 "" "")) ; max iterations | |
5163 | (use (match_operand 3 "" "")) ; loop level | |
5164 | (use (match_operand 4 "" ""))] ; label | |
5165 | "" | |
5527bf14 RH |
5166 | { |
5167 | /* Only use cloop on innermost loops. */ | |
5168 | if (INTVAL (operands[3]) > 1) | |
5169 | FAIL; | |
5170 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5171 | operands[4])); | |
5172 | DONE; | |
1d5d7a21 | 5173 | }) |
5527bf14 RH |
5174 | |
5175 | (define_insn "doloop_end_internal" | |
5176 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5177 | (const_int 0)) | |
5178 | (label_ref (match_operand 1 "" "")) | |
5179 | (pc))) | |
5180 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5181 | (plus:DI (match_dup 0) (const_int -1)) |
5182 | (match_dup 0)))] | |
5527bf14 RH |
5183 | "" |
5184 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5185 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5186 | (set_attr "predicable" "no")]) |
5187 | \f | |
5188 | ;; :::::::::::::::::::: | |
5189 | ;; :: | |
c65ebc55 JW |
5190 | ;; :: Set flag operations |
5191 | ;; :: | |
5192 | ;; :::::::::::::::::::: | |
5193 | ||
5194 | (define_expand "seq" | |
f2f90c63 | 5195 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5196 | "" |
f2f90c63 | 5197 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5198 | |
5199 | (define_expand "sne" | |
f2f90c63 | 5200 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5201 | "" |
f2f90c63 | 5202 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5203 | |
5204 | (define_expand "slt" | |
f2f90c63 | 5205 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5206 | "" |
f2f90c63 | 5207 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5208 | |
5209 | (define_expand "sle" | |
f2f90c63 | 5210 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5211 | "" |
f2f90c63 | 5212 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5213 | |
5214 | (define_expand "sgt" | |
f2f90c63 | 5215 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5216 | "" |
f2f90c63 | 5217 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5218 | |
5219 | (define_expand "sge" | |
f2f90c63 | 5220 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5221 | "" |
f2f90c63 | 5222 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5223 | |
5224 | (define_expand "sltu" | |
f2f90c63 | 5225 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5226 | "" |
f2f90c63 | 5227 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5228 | |
5229 | (define_expand "sleu" | |
f2f90c63 | 5230 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5231 | "" |
f2f90c63 | 5232 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5233 | |
5234 | (define_expand "sgtu" | |
f2f90c63 | 5235 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5236 | "" |
f2f90c63 | 5237 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5238 | |
5239 | (define_expand "sgeu" | |
f2f90c63 | 5240 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5241 | "" |
f2f90c63 | 5242 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5243 | |
e57b9d65 | 5244 | (define_expand "sunordered" |
f2f90c63 | 5245 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5246 | "" |
f2f90c63 | 5247 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5248 | |
5249 | (define_expand "sordered" | |
f2f90c63 | 5250 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5251 | "" |
f2f90c63 | 5252 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5253 | |
c65ebc55 JW |
5254 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5255 | ;; efficient than mov/mov/cst/cst. | |
5256 | ||
0551c32d RH |
5257 | (define_insn_and_split "*sne_internal" |
5258 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5259 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5260 | (const_int 0)))] |
5261 | "" | |
5262 | "#" | |
c65ebc55 | 5263 | "reload_completed" |
f2f90c63 RH |
5264 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5265 | (set (match_dup 0) (const_int 1))) | |
5266 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5267 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5268 | "" |
52e12ad0 | 5269 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5270 | |
0551c32d RH |
5271 | (define_insn_and_split "*seq_internal" |
5272 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5273 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5274 | (const_int 0)))] |
5275 | "" | |
5276 | "#" | |
c65ebc55 | 5277 | "reload_completed" |
f2f90c63 RH |
5278 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5279 | (set (match_dup 0) (const_int 0))) | |
5280 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5281 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5282 | "" |
52e12ad0 | 5283 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5284 | \f |
5285 | ;; :::::::::::::::::::: | |
5286 | ;; :: | |
5287 | ;; :: Conditional move instructions. | |
5288 | ;; :: | |
5289 | ;; :::::::::::::::::::: | |
5290 | ||
5291 | ;; ??? Add movXXcc patterns? | |
5292 | ||
c65ebc55 JW |
5293 | ;; |
5294 | ;; DImode if_then_else patterns. | |
5295 | ;; | |
5296 | ||
75cdbeb8 | 5297 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5298 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5299 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5300 | (if_then_else:DI |
f2f90c63 RH |
5301 | (match_operator 4 "predicate_operator" |
5302 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5303 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5304 | (const_int 0)]) |
f2f90c63 | 5305 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5306 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5307 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5308 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5309 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5310 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5311 | { gcc_unreachable (); } |
75cdbeb8 RH |
5312 | [(set_attr "predicable" "no")]) |
5313 | ||
5314 | (define_split | |
f2f90c63 | 5315 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5316 | (if_then_else |
f2f90c63 RH |
5317 | (match_operator 4 "predicate_operator" |
5318 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5319 | (const_int 0)]) |
f2f90c63 RH |
5320 | (match_operand 2 "move_operand" "") |
5321 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5322 | "reload_completed" |
5323 | [(const_int 0)] | |
e5bde68a | 5324 | { |
21515593 RH |
5325 | bool emitted_something = false; |
5326 | rtx dest = operands[0]; | |
5327 | rtx srct = operands[2]; | |
5328 | rtx srcf = operands[3]; | |
5329 | rtx cond = operands[4]; | |
2f937369 | 5330 | |
21515593 | 5331 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5332 | { |
21515593 RH |
5333 | ia64_emit_cond_move (dest, srct, cond); |
5334 | emitted_something = true; | |
e5bde68a | 5335 | } |
21515593 | 5336 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5337 | { |
21515593 RH |
5338 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5339 | VOIDmode, operands[1], const0_rtx); | |
5340 | ia64_emit_cond_move (dest, srcf, cond); | |
5341 | emitted_something = true; | |
3b572406 | 5342 | } |
2f937369 | 5343 | if (! emitted_something) |
f9974026 | 5344 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5345 | DONE; |
1d5d7a21 | 5346 | }) |
c65ebc55 JW |
5347 | |
5348 | ;; Absolute value pattern. | |
5349 | ||
5350 | (define_insn "*absdi2_internal" | |
0551c32d | 5351 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5352 | (if_then_else:DI |
f2f90c63 RH |
5353 | (match_operator 4 "predicate_operator" |
5354 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5355 | (const_int 0)]) |
0551c32d RH |
5356 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5357 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5358 | "" |
e5bde68a | 5359 | "#" |
52e12ad0 | 5360 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5361 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5362 | |
5363 | (define_split | |
5364 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5365 | (if_then_else:DI |
f2f90c63 RH |
5366 | (match_operator 4 "predicate_operator" |
5367 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5368 | (const_int 0)]) |
0551c32d RH |
5369 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5370 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5371 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5372 | [(cond_exec | |
5373 | (match_dup 4) | |
5374 | (set (match_dup 0) | |
5375 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5376 | "") |
5377 | ||
e5bde68a RH |
5378 | (define_split |
5379 | [(set (match_operand:DI 0 "register_operand" "") | |
5380 | (if_then_else:DI | |
f2f90c63 RH |
5381 | (match_operator 4 "predicate_operator" |
5382 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5383 | (const_int 0)]) |
0551c32d RH |
5384 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5385 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5386 | "reload_completed" |
5387 | [(cond_exec | |
5388 | (match_dup 4) | |
5389 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5390 | (cond_exec | |
5391 | (match_dup 5) | |
5392 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5393 | { |
5394 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5395 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5396 | }) |
c65ebc55 JW |
5397 | |
5398 | ;; | |
5399 | ;; SImode if_then_else patterns. | |
5400 | ;; | |
5401 | ||
75cdbeb8 | 5402 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5403 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5404 | (if_then_else:SI |
f2f90c63 RH |
5405 | (match_operator 4 "predicate_operator" |
5406 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5407 | (const_int 0)]) |
f2f90c63 | 5408 | (match_operand:SI 2 "move_operand" |
3b572406 | 5409 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5410 | (match_operand:SI 3 "move_operand" |
3b572406 | 5411 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5412 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5413 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5414 | { gcc_unreachable (); } |
3b572406 | 5415 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5416 | |
5417 | (define_insn "*abssi2_internal" | |
0551c32d | 5418 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5419 | (if_then_else:SI |
f2f90c63 RH |
5420 | (match_operator 4 "predicate_operator" |
5421 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5422 | (const_int 0)]) |
0551c32d RH |
5423 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5424 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5425 | "" |
e5bde68a | 5426 | "#" |
52e12ad0 | 5427 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5428 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5429 | |
5430 | (define_split | |
5431 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5432 | (if_then_else:SI |
f2f90c63 RH |
5433 | (match_operator 4 "predicate_operator" |
5434 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5435 | (const_int 0)]) |
0551c32d RH |
5436 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5437 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5438 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5439 | [(cond_exec | |
5440 | (match_dup 4) | |
5441 | (set (match_dup 0) | |
5442 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5443 | "") |
5444 | ||
e5bde68a RH |
5445 | (define_split |
5446 | [(set (match_operand:SI 0 "register_operand" "") | |
5447 | (if_then_else:SI | |
f2f90c63 RH |
5448 | (match_operator 4 "predicate_operator" |
5449 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5450 | (const_int 0)]) |
0551c32d RH |
5451 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5452 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5453 | "reload_completed" |
5454 | [(cond_exec | |
5455 | (match_dup 4) | |
5456 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5457 | (cond_exec | |
5458 | (match_dup 5) | |
5459 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5460 | { |
5461 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5462 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5463 | }) |
e5bde68a | 5464 | |
7dcc803e | 5465 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5466 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5467 | (match_operator:SI 5 "condop_operator" | |
5468 | [(if_then_else:SI | |
5469 | (match_operator 6 "predicate_operator" | |
5470 | [(match_operand:BI 1 "register_operand" "c") | |
5471 | (const_int 0)]) | |
5472 | (match_operand:SI 2 "gr_register_operand" "r") | |
5473 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5474 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5475 | "" | |
5476 | "#" | |
acb0638d BS |
5477 | "reload_completed" |
5478 | [(cond_exec | |
5479 | (match_dup 6) | |
5480 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5481 | (cond_exec | |
5482 | (match_dup 7) | |
5483 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5484 | { |
5485 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5486 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5487 | } |
7dcc803e BS |
5488 | [(set_attr "itanium_class" "ialu") |
5489 | (set_attr "predicable" "no")]) | |
5490 | ||
acb0638d | 5491 | |
7dcc803e | 5492 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5493 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5494 | (match_operator:SI 5 "condop_operator" | |
5495 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5496 | (if_then_else:SI | |
5497 | (match_operator 6 "predicate_operator" | |
5498 | [(match_operand:BI 1 "register_operand" "c") | |
5499 | (const_int 0)]) | |
5500 | (match_operand:SI 2 "gr_register_operand" "r") | |
5501 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5502 | "" | |
5503 | "#" | |
acb0638d BS |
5504 | "reload_completed" |
5505 | [(cond_exec | |
5506 | (match_dup 6) | |
5507 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5508 | (cond_exec | |
5509 | (match_dup 7) | |
5510 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5511 | { |
5512 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5513 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5514 | } |
7dcc803e BS |
5515 | [(set_attr "itanium_class" "ialu") |
5516 | (set_attr "predicable" "no")]) | |
acb0638d | 5517 | |
c65ebc55 JW |
5518 | \f |
5519 | ;; :::::::::::::::::::: | |
5520 | ;; :: | |
5521 | ;; :: Call and branch instructions | |
5522 | ;; :: | |
5523 | ;; :::::::::::::::::::: | |
5524 | ||
5525 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5526 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5527 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5528 | ;; registers used as operands. | |
5529 | ||
5530 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5531 | ;; is supplied for the sake of some RISC machines which need to put this | |
5532 | ;; information into the assembler code; they can put it in the RTL instead of | |
5533 | ;; operand 1. | |
5534 | ||
5535 | (define_expand "call" | |
5536 | [(use (match_operand:DI 0 "" "")) | |
5537 | (use (match_operand 1 "" "")) | |
5538 | (use (match_operand 2 "" "")) | |
5539 | (use (match_operand 3 "" ""))] | |
5540 | "" | |
c65ebc55 | 5541 | { |
599aedd9 | 5542 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5543 | DONE; |
1d5d7a21 | 5544 | }) |
c65ebc55 | 5545 | |
2ed4af6f RH |
5546 | (define_expand "sibcall" |
5547 | [(use (match_operand:DI 0 "" "")) | |
5548 | (use (match_operand 1 "" "")) | |
5549 | (use (match_operand 2 "" "")) | |
5550 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5551 | "" |
c65ebc55 | 5552 | { |
599aedd9 | 5553 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5554 | DONE; |
1d5d7a21 | 5555 | }) |
c65ebc55 | 5556 | |
c65ebc55 | 5557 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5558 | ;; register in which the value is returned. There are three more operands, |
5559 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5560 | ;; increased by one). |
2ed4af6f | 5561 | ;; |
c65ebc55 JW |
5562 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5563 | ||
5564 | (define_expand "call_value" | |
5565 | [(use (match_operand 0 "" "")) | |
5566 | (use (match_operand:DI 1 "" "")) | |
5567 | (use (match_operand 2 "" "")) | |
5568 | (use (match_operand 3 "" "")) | |
5569 | (use (match_operand 4 "" ""))] | |
5570 | "" | |
c65ebc55 | 5571 | { |
599aedd9 | 5572 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5573 | DONE; |
1d5d7a21 | 5574 | }) |
c65ebc55 | 5575 | |
2ed4af6f RH |
5576 | (define_expand "sibcall_value" |
5577 | [(use (match_operand 0 "" "")) | |
5578 | (use (match_operand:DI 1 "" "")) | |
5579 | (use (match_operand 2 "" "")) | |
5580 | (use (match_operand 3 "" "")) | |
5581 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5582 | "" |
c65ebc55 | 5583 | { |
599aedd9 | 5584 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5585 | DONE; |
1d5d7a21 | 5586 | }) |
c65ebc55 | 5587 | |
c65ebc55 JW |
5588 | ;; Call subroutine returning any type. |
5589 | ||
5590 | (define_expand "untyped_call" | |
5591 | [(parallel [(call (match_operand 0 "" "") | |
5592 | (const_int 0)) | |
5593 | (match_operand 1 "" "") | |
5594 | (match_operand 2 "" "")])] | |
5595 | "" | |
c65ebc55 JW |
5596 | { |
5597 | int i; | |
5598 | ||
5599 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5600 | ||
5601 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5602 | { | |
5603 | rtx set = XVECEXP (operands[2], 0, i); | |
5604 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5605 | } | |
5606 | ||
5607 | /* The optimizer does not know that the call sets the function value | |
5608 | registers we stored in the result block. We avoid problems by | |
5609 | claiming that all hard registers are used and clobbered at this | |
5610 | point. */ | |
5611 | emit_insn (gen_blockage ()); | |
5612 | ||
5613 | DONE; | |
1d5d7a21 | 5614 | }) |
c65ebc55 | 5615 | |
599aedd9 RH |
5616 | (define_insn "call_nogp" |
5617 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5618 | (const_int 0)) | |
5619 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5620 | "" |
599aedd9 | 5621 | "br.call%+.many %1 = %0" |
52e12ad0 | 5622 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5623 | |
599aedd9 | 5624 | (define_insn "call_value_nogp" |
75293ad6 | 5625 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5626 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5627 | (const_int 0))) | |
5628 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5629 | "" |
599aedd9 | 5630 | "br.call%+.many %2 = %1" |
52e12ad0 | 5631 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5632 | |
599aedd9 RH |
5633 | (define_insn "sibcall_nogp" |
5634 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5635 | (const_int 0))] | |
2ed4af6f RH |
5636 | "" |
5637 | "br%+.many %0" | |
52e12ad0 | 5638 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5639 | |
599aedd9 | 5640 | (define_insn "call_gp" |
c8083186 | 5641 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5642 | (const_int 1)) |
5643 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5644 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5645 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5646 | "" |
599aedd9 | 5647 | "#" |
52e12ad0 | 5648 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5649 | |
599aedd9 RH |
5650 | ;; Irritatingly, we don't have access to INSN within the split body. |
5651 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5652 | (define_split | |
5653 | [(call (mem (match_operand 0 "call_operand" "")) | |
5654 | (const_int 1)) | |
5655 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5656 | (clobber (match_scratch:DI 2 "")) | |
5657 | (clobber (match_scratch:DI 3 ""))] | |
5658 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5659 | [(const_int 0)] | |
5660 | { | |
5661 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5662 | operands[3], true, false); | |
5663 | DONE; | |
5664 | }) | |
5665 | ||
5666 | (define_split | |
5667 | [(call (mem (match_operand 0 "call_operand" "")) | |
5668 | (const_int 1)) | |
5669 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5670 | (clobber (match_scratch:DI 2 "")) | |
5671 | (clobber (match_scratch:DI 3 ""))] | |
5672 | "reload_completed" | |
5673 | [(const_int 0)] | |
5674 | { | |
5675 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5676 | operands[3], false, false); | |
5677 | DONE; | |
5678 | }) | |
5679 | ||
5680 | (define_insn "call_value_gp" | |
75293ad6 | 5681 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5682 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5683 | (const_int 1))) | |
5684 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5685 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5686 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5687 | "" |
599aedd9 | 5688 | "#" |
52e12ad0 | 5689 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5690 | |
599aedd9 RH |
5691 | (define_split |
5692 | [(set (match_operand 0 "" "") | |
5693 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5694 | (const_int 1))) | |
5695 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5696 | (clobber (match_scratch:DI 3 "")) | |
5697 | (clobber (match_scratch:DI 4 ""))] | |
5698 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5699 | [(const_int 0)] | |
5700 | { | |
5701 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5702 | operands[4], true, false); | |
5703 | DONE; | |
5704 | }) | |
5705 | ||
5706 | (define_split | |
5707 | [(set (match_operand 0 "" "") | |
5708 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5709 | (const_int 1))) | |
5710 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5711 | (clobber (match_scratch:DI 3 "")) | |
5712 | (clobber (match_scratch:DI 4 ""))] | |
5713 | "reload_completed" | |
5714 | [(const_int 0)] | |
5715 | { | |
5716 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5717 | operands[4], false, false); | |
5718 | DONE; | |
5719 | }) | |
5720 | ||
5721 | (define_insn_and_split "sibcall_gp" | |
5722 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5723 | (const_int 1)) | |
5724 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5725 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5726 | "" |
599aedd9 RH |
5727 | "#" |
5728 | "reload_completed" | |
5729 | [(const_int 0)] | |
5730 | { | |
5731 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5732 | operands[2], true, true); | |
5733 | DONE; | |
5734 | } | |
52e12ad0 | 5735 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5736 | |
c65ebc55 JW |
5737 | (define_insn "return_internal" |
5738 | [(return) | |
5739 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5740 | "" | |
5741 | "br.ret.sptk.many %0" | |
52e12ad0 | 5742 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5743 | |
5744 | (define_insn "return" | |
5745 | [(return)] | |
5746 | "ia64_direct_return ()" | |
5747 | "br.ret.sptk.many rp" | |
52e12ad0 | 5748 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5749 | |
6b6c1201 | 5750 | (define_insn "*return_true" |
c65ebc55 | 5751 | [(set (pc) |
6b6c1201 | 5752 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5753 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5754 | (const_int 0)]) |
c65ebc55 JW |
5755 | (return) |
5756 | (pc)))] | |
5757 | "ia64_direct_return ()" | |
13da91fd | 5758 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5759 | [(set_attr "itanium_class" "br") |
e5bde68a | 5760 | (set_attr "predicable" "no")]) |
c65ebc55 | 5761 | |
6b6c1201 | 5762 | (define_insn "*return_false" |
c65ebc55 | 5763 | [(set (pc) |
6b6c1201 | 5764 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5765 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5766 | (const_int 0)]) |
c65ebc55 JW |
5767 | (pc) |
5768 | (return)))] | |
5769 | "ia64_direct_return ()" | |
13da91fd | 5770 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5771 | [(set_attr "itanium_class" "br") |
e5bde68a | 5772 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5773 | |
5774 | (define_insn "jump" | |
5775 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5776 | "" | |
5777 | "br %l0" | |
52e12ad0 | 5778 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5779 | |
5780 | (define_insn "indirect_jump" | |
5781 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5782 | "" | |
5783 | "br %0" | |
52e12ad0 | 5784 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5785 | |
5786 | (define_expand "tablejump" | |
340f7e7c RH |
5787 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5788 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5789 | "" |
c65ebc55 | 5790 | { |
340f7e7c RH |
5791 | rtx op0 = operands[0]; |
5792 | rtx addr; | |
5793 | ||
5794 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5795 | element into a register without bothering to see whether that | |
5796 | is necessary given the operand predicate. Check for MEM just | |
5797 | in case someone fixes this. */ | |
5798 | if (GET_CODE (op0) == MEM) | |
5799 | addr = XEXP (op0, 0); | |
5800 | else | |
5801 | { | |
5802 | /* Otherwise, cheat and guess that the previous insn in the | |
5803 | stream was the memory load. Grab the address from that. | |
5804 | Note we have to momentarily pop out of the sequence started | |
5805 | by the insn-emit wrapper in order to grab the last insn. */ | |
5806 | rtx last, set; | |
5807 | ||
5808 | end_sequence (); | |
5809 | last = get_last_insn (); | |
5810 | start_sequence (); | |
5811 | set = single_set (last); | |
5812 | ||
e820471b NS |
5813 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5814 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5815 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5816 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5817 | } |
c65ebc55 | 5818 | |
340f7e7c RH |
5819 | /* Jump table elements are stored pc-relative. That is, a displacement |
5820 | from the entry to the label. Thus to convert to an absolute address | |
5821 | we add the address of the memory from which the value is loaded. */ | |
5822 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5823 | NULL_RTX, 1, OPTAB_DIRECT); | |
5824 | }) | |
c65ebc55 | 5825 | |
340f7e7c | 5826 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5827 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5828 | (use (label_ref (match_operand 1 "" "")))] | |
5829 | "" | |
5830 | "br %0" | |
52e12ad0 | 5831 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5832 | |
5833 | \f | |
5834 | ;; :::::::::::::::::::: | |
5835 | ;; :: | |
5836 | ;; :: Prologue and Epilogue instructions | |
5837 | ;; :: | |
5838 | ;; :::::::::::::::::::: | |
5839 | ||
5840 | (define_expand "prologue" | |
5841 | [(const_int 1)] | |
5842 | "" | |
c65ebc55 JW |
5843 | { |
5844 | ia64_expand_prologue (); | |
5845 | DONE; | |
1d5d7a21 | 5846 | }) |
c65ebc55 JW |
5847 | |
5848 | (define_expand "epilogue" | |
2ed4af6f RH |
5849 | [(return)] |
5850 | "" | |
2ed4af6f RH |
5851 | { |
5852 | ia64_expand_epilogue (0); | |
5853 | DONE; | |
1d5d7a21 | 5854 | }) |
2ed4af6f RH |
5855 | |
5856 | (define_expand "sibcall_epilogue" | |
5857 | [(return)] | |
c65ebc55 | 5858 | "" |
c65ebc55 | 5859 | { |
2ed4af6f | 5860 | ia64_expand_epilogue (1); |
c65ebc55 | 5861 | DONE; |
1d5d7a21 | 5862 | }) |
c65ebc55 JW |
5863 | |
5864 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5865 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5866 | ||
5867 | (define_insn "prologue_allocate_stack" | |
5868 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5869 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5870 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5871 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5872 | (match_dup 3))] |
5873 | "" | |
5874 | "@ | |
1d5d7a21 RH |
5875 | add %0 = %1, %2 |
5876 | adds %0 = %2, %1 | |
5877 | addl %0 = %2, %1" | |
52e12ad0 | 5878 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5879 | |
5880 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5881 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5882 | ||
5883 | (define_insn "epilogue_deallocate_stack" | |
5884 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5885 | (match_operand:DI 1 "register_operand" "+r")) | |
5886 | (set (match_dup 1) (match_dup 1))] | |
5887 | "" | |
5888 | "mov %0 = %1" | |
52e12ad0 | 5889 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5890 | |
1d5d7a21 RH |
5891 | ;; As USE insns aren't meaningful after reload, this is used instead |
5892 | ;; to prevent deleting instructions setting registers for EH handling | |
5893 | (define_insn "prologue_use" | |
5894 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5895 | UNSPEC_PROLOGUE_USE)] | |
5896 | "" | |
5897 | "" | |
5898 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5899 | (set_attr "predicable" "no") |
5900 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5901 | |
c65ebc55 JW |
5902 | ;; Allocate a new register frame. |
5903 | ||
5904 | (define_insn "alloc" | |
5905 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5906 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5907 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5908 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5909 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5910 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5911 | "" | |
5912 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5913 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
5914 | (set_attr "predicable" "no") |
5915 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 5916 | |
97e242b0 RH |
5917 | ;; Modifies ar.unat |
5918 | (define_expand "gr_spill" | |
870f9ec0 RH |
5919 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5920 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5921 | (match_operand:DI 2 "const_int_operand" "")] |
5922 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5923 | (clobber (match_dup 3))])] |
97e242b0 | 5924 | "" |
870f9ec0 | 5925 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5926 | |
870f9ec0 | 5927 | (define_insn "gr_spill_internal" |
c65ebc55 | 5928 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 | 5929 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5930 | (match_operand:DI 2 "const_int_operand" "")] |
5931 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5932 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5933 | "" |
2130b7fb | 5934 | { |
1d5d7a21 RH |
5935 | /* Note that we use a C output pattern here to avoid the predicate |
5936 | being automatically added before the .mem.offset directive. */ | |
5937 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5938 | } | |
52e12ad0 | 5939 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5940 | |
97e242b0 RH |
5941 | ;; Reads ar.unat |
5942 | (define_expand "gr_restore" | |
870f9ec0 RH |
5943 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5944 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5945 | (match_operand:DI 2 "const_int_operand" "")] |
5946 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5947 | (use (match_dup 3))])] |
97e242b0 | 5948 | "" |
870f9ec0 | 5949 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5950 | |
870f9ec0 | 5951 | (define_insn "gr_restore_internal" |
c65ebc55 | 5952 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5953 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5954 | (match_operand:DI 2 "const_int_operand" "")] |
5955 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5956 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5957 | "" |
1d5d7a21 | 5958 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5959 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5960 | |
5961 | (define_insn "fr_spill" | |
02befdf4 ZW |
5962 | [(set (match_operand:XF 0 "memory_operand" "=m") |
5963 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] | |
086c0f96 | 5964 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5965 | "" |
5966 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5967 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5968 | |
5969 | (define_insn "fr_restore" | |
02befdf4 ZW |
5970 | [(set (match_operand:XF 0 "register_operand" "=f") |
5971 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5972 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5973 | "" |
5974 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5975 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5976 | |
0024a804 JW |
5977 | ;; ??? The explicit stop is not ideal. It would be better if |
5978 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5979 | ;; fixed later. This avoids an RSE DV. | |
5980 | ||
0c96007e AM |
5981 | (define_insn "bsp_value" |
5982 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5983 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5984 | "" |
582d11e6 JW |
5985 | "* |
5986 | { | |
5987 | return \";;\;%,mov %0 = ar.bsp\"; | |
5988 | }" | |
52e12ad0 | 5989 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5990 | |
5991 | (define_insn "set_bsp" | |
086c0f96 RH |
5992 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5993 | UNSPECV_SET_BSP)] | |
0c96007e | 5994 | "" |
1d5d7a21 RH |
5995 | "flushrs |
5996 | mov r19=ar.rsc | |
5997 | ;; | |
5998 | and r19=0x1c,r19 | |
5999 | ;; | |
6000 | mov ar.rsc=r19 | |
6001 | ;; | |
6002 | mov ar.bspstore=%0 | |
6003 | ;; | |
6004 | or r19=0x3,r19 | |
6005 | ;; | |
6006 | loadrs | |
6007 | invala | |
6008 | ;; | |
6009 | mov ar.rsc=r19" | |
52e12ad0 | 6010 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 6011 | (set_attr "predicable" "no")]) |
ce152ef8 | 6012 | |
0024a804 JW |
6013 | ;; ??? The explicit stops are not ideal. It would be better if |
6014 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
6015 | ;; fixed later. This avoids an RSE DV. | |
6016 | ||
ce152ef8 | 6017 | (define_insn "flushrs" |
086c0f96 | 6018 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 6019 | "" |
0024a804 | 6020 | ";;\;flushrs\;;;" |
582d11e6 JW |
6021 | [(set_attr "itanium_class" "rse_m") |
6022 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
6023 | \f |
6024 | ;; :::::::::::::::::::: | |
6025 | ;; :: | |
6026 | ;; :: Miscellaneous instructions | |
6027 | ;; :: | |
6028 | ;; :::::::::::::::::::: | |
6029 | ||
839a4992 | 6030 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
6031 | ;; be emitting ";;" to force a break in the instruction packing. |
6032 | ||
6033 | ;; No operation, needed in case the user uses -g but not -O. | |
6034 | (define_insn "nop" | |
6035 | [(const_int 0)] | |
6036 | "" | |
6037 | "nop 0" | |
30028c85 | 6038 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 6039 | |
2130b7fb BS |
6040 | (define_insn "nop_m" |
6041 | [(const_int 1)] | |
6042 | "" | |
6043 | "nop.m 0" | |
6044 | [(set_attr "itanium_class" "nop_m")]) | |
6045 | ||
6046 | (define_insn "nop_i" | |
6047 | [(const_int 2)] | |
6048 | "" | |
6049 | "nop.i 0" | |
6050 | [(set_attr "itanium_class" "nop_i")]) | |
6051 | ||
6052 | (define_insn "nop_f" | |
6053 | [(const_int 3)] | |
6054 | "" | |
6055 | "nop.f 0" | |
6056 | [(set_attr "itanium_class" "nop_f")]) | |
6057 | ||
6058 | (define_insn "nop_b" | |
6059 | [(const_int 4)] | |
6060 | "" | |
6061 | "nop.b 0" | |
6062 | [(set_attr "itanium_class" "nop_b")]) | |
6063 | ||
6064 | (define_insn "nop_x" | |
6065 | [(const_int 5)] | |
6066 | "" | |
6067 | "" | |
fa978426 AS |
6068 | [(set_attr "itanium_class" "nop_x") |
6069 | (set_attr "empty" "yes")]) | |
2130b7fb | 6070 | |
30028c85 VM |
6071 | ;; The following insn will be never generated. It is used only by |
6072 | ;; insn scheduler to change state before advancing cycle. | |
6073 | (define_insn "pre_cycle" | |
6074 | [(const_int 6)] | |
6075 | "" | |
6076 | "" | |
6077 | [(set_attr "itanium_class" "pre_cycle")]) | |
6078 | ||
2130b7fb | 6079 | (define_insn "bundle_selector" |
086c0f96 | 6080 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 6081 | "" |
1d5d7a21 | 6082 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
6083 | [(set_attr "itanium_class" "ignore") |
6084 | (set_attr "predicable" "no")]) | |
6085 | ||
c65ebc55 JW |
6086 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
6087 | ;; point. | |
6088 | (define_insn "blockage" | |
086c0f96 | 6089 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
6090 | "" |
6091 | "" | |
52e12ad0 | 6092 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 6093 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
6094 | |
6095 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
6096 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
6097 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
6098 | "" |
6099 | ";;" | |
52e12ad0 | 6100 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6101 | (set_attr "predicable" "no") |
6102 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6103 | |
26406018 RH |
6104 | (define_expand "trap" |
6105 | [(trap_if (const_int 1) (const_int 0))] | |
6106 | "" | |
6107 | "") | |
6108 | ||
6109 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6110 | ;; produces worse code that setting the slot type to A. | |
6111 | ||
6112 | (define_insn "*trap" | |
6113 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6114 | "" | |
6115 | "break %0" | |
6116 | [(set_attr "itanium_class" "chk_s")]) | |
6117 | ||
6118 | (define_expand "conditional_trap" | |
6119 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6120 | "" | |
6121 | { | |
6122 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6123 | }) | |
6124 | ||
6125 | (define_insn "*conditional_trap" | |
6126 | [(trap_if (match_operator 0 "predicate_operator" | |
6127 | [(match_operand:BI 1 "register_operand" "c") | |
6128 | (const_int 0)]) | |
6129 | (match_operand 2 "const_int_operand" ""))] | |
6130 | "" | |
5cf63e3f | 6131 | "(%J0) break %2" |
26406018 RH |
6132 | [(set_attr "itanium_class" "chk_s") |
6133 | (set_attr "predicable" "no")]) | |
6134 | ||
f12f25a7 | 6135 | (define_insn "break_f" |
086c0f96 | 6136 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6137 | "" |
6138 | "break.f 0" | |
6139 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6140 | |
6141 | (define_insn "prefetch" | |
6142 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6143 | (match_operand:DI 1 "const_int_operand" "n") | |
6144 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6145 | "" | |
6146 | { | |
6147 | static const char * const alt[2][4] = { | |
b3656137 | 6148 | { |
92cbea22 L |
6149 | "%,lfetch.nta [%0]", |
6150 | "%,lfetch.nt1 [%0]", | |
6151 | "%,lfetch.nt2 [%0]", | |
6152 | "%,lfetch [%0]" | |
b3656137 KG |
6153 | }, |
6154 | { | |
92cbea22 L |
6155 | "%,lfetch.excl.nta [%0]", |
6156 | "%,lfetch.excl.nt1 [%0]", | |
6157 | "%,lfetch.excl.nt2 [%0]", | |
6158 | "%,lfetch.excl [%0]" | |
b3656137 | 6159 | } |
44eca121 JJ |
6160 | }; |
6161 | int i = (INTVAL (operands[1])); | |
6162 | int j = (INTVAL (operands[2])); | |
6163 | ||
e820471b NS |
6164 | gcc_assert (i == 0 || i == 1); |
6165 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
6166 | return alt[i][j]; |
6167 | } | |
6168 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6169 | \f |
6170 | ;; Non-local goto support. | |
6171 | ||
6172 | (define_expand "save_stack_nonlocal" | |
6173 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6174 | (use (match_operand:DI 1 "register_operand" ""))] | |
6175 | "" | |
c65ebc55 JW |
6176 | { |
6177 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6178 | \"__ia64_save_stack_nonlocal\"), | |
6179 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
6180 | operands[1], Pmode); | |
6181 | DONE; | |
1d5d7a21 | 6182 | }) |
c65ebc55 JW |
6183 | |
6184 | (define_expand "nonlocal_goto" | |
6185 | [(use (match_operand 0 "general_operand" "")) | |
6186 | (use (match_operand 1 "general_operand" "")) | |
6187 | (use (match_operand 2 "general_operand" "")) | |
6188 | (use (match_operand 3 "general_operand" ""))] | |
6189 | "" | |
c65ebc55 | 6190 | { |
c65ebc55 | 6191 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6192 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6193 | operands[1], Pmode, |
c65ebc55 | 6194 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6195 | operands[3], Pmode); |
c65ebc55 JW |
6196 | emit_barrier (); |
6197 | DONE; | |
1d5d7a21 | 6198 | }) |
c65ebc55 | 6199 | |
b39eb2f9 RH |
6200 | (define_insn_and_split "builtin_setjmp_receiver" |
6201 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6202 | "" |
b39eb2f9 RH |
6203 | "#" |
6204 | "reload_completed" | |
6205 | [(const_int 0)] | |
97e242b0 | 6206 | { |
599aedd9 | 6207 | ia64_reload_gp (); |
c65ebc55 | 6208 | DONE; |
1d5d7a21 | 6209 | }) |
c65ebc55 | 6210 | |
0c96007e AM |
6211 | (define_expand "eh_epilogue" |
6212 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6213 | (use (match_operand:DI 1 "register_operand" "r")) | |
6214 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6215 | "" | |
0c96007e AM |
6216 | { |
6217 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6218 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6219 | ||
6220 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6221 | { | |
6222 | emit_move_insn (bsp, operands[0]); | |
6223 | operands[0] = bsp; | |
6224 | } | |
6225 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6226 | { | |
6227 | emit_move_insn (sp, operands[2]); | |
6228 | operands[2] = sp; | |
6229 | } | |
6230 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
6231 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
6232 | ||
6233 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6234 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6235 | }) |
9525c690 JW |
6236 | \f |
6237 | ;; Builtin apply support. | |
6238 | ||
6239 | (define_expand "restore_stack_nonlocal" | |
6240 | [(use (match_operand:DI 0 "register_operand" "")) | |
6241 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6242 | "" | |
9525c690 JW |
6243 | { |
6244 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6245 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
6246 | 0, VOIDmode, 1, |
6247 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
6248 | DONE; | |
1d5d7a21 | 6249 | }) |
9525c690 | 6250 | |
e5bde68a RH |
6251 | \f |
6252 | ;; Predication. | |
6253 | ||
6254 | (define_cond_exec | |
6255 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6256 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6257 | (const_int 0)])] |
6258 | "" | |
6259 | "(%J0)") | |
3b572406 RH |
6260 | |
6261 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6262 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6263 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6264 | "" |
054451ea | 6265 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6266 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6267 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6268 | |
6269 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6270 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6271 | "" |
6272 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6273 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6274 | (set_attr "predicable" "no")]) |
6275 | ||
6276 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6277 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6278 | "" |
ca3920ad | 6279 | { |
1bc7c5b6 | 6280 | emit_safe_across_calls (); |
1d5d7a21 RH |
6281 | return ""; |
6282 | } | |
52e12ad0 | 6283 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6284 | (set_attr "predicable" "no")]) |
6285 | ||
6dd12198 SE |
6286 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit |
6287 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
6288 | ||
6289 | (define_insn "ptr_extend" | |
6290 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6291 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6292 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6293 | "" |
6294 | "addp4 %0 = 0,%1" | |
6295 | [(set_attr "itanium_class" "ialu")]) | |
6296 | ||
e206a74f SE |
6297 | ;; |
6298 | ;; Optimizations for ptr_extend | |
6299 | ||
36c216e5 | 6300 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6301 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6302 | (unspec:DI | |
6303 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6304 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6305 | UNSPEC_ADDP4))] |
08744705 | 6306 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6307 | "addp4 %0 = %2, %1" |
6308 | [(set_attr "itanium_class" "ialu")]) | |
6309 | ||
6310 | (define_insn "*ptr_extend_plus_2" | |
6311 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6312 | (unspec:DI | |
6313 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6314 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6315 | UNSPEC_ADDP4))] |
08744705 | 6316 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6317 | "addp4 %0 = %1, %2" |
6318 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6319 | |
d26afa4f SE |
6320 | ;; |
6321 | ;; Get instruction pointer | |
6322 | ||
6323 | (define_insn "ip_value" | |
6324 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6325 | (pc))] | |
6326 | "" | |
6327 | "mov %0 = ip" | |
6328 | [(set_attr "itanium_class" "ialu")]) | |
6329 | ||
f61134e8 RH |
6330 | ;; Vector operations |
6331 | (include "vect.md") | |
af795c3c RH |
6332 | ;; Atomic operations |
6333 | (include "sync.md") |