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c65ebc55 | 1 | ;; IA-64 Machine description template |
f4ef873c | 2 | ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
58 | ||
59 | (UNSPEC_LD_BASE 9) | |
60 | (UNSPEC_GR_SPILL 10) | |
61 | (UNSPEC_GR_RESTORE 11) | |
62 | (UNSPEC_FR_SPILL 12) | |
63 | (UNSPEC_FR_RESTORE 13) | |
64 | (UNSPEC_FR_RECIP_APPROX 14) | |
65 | (UNSPEC_PRED_REL_MUTEX 15) | |
66 | (UNSPEC_POPCNT 16) | |
67 | (UNSPEC_PIC_CALL 17) | |
68 | (UNSPEC_MF 18) | |
69 | (UNSPEC_CMPXCHG_ACQ 19) | |
70 | (UNSPEC_FETCHADD_ACQ 20) | |
71 | (UNSPEC_BSP_VALUE 21) | |
72 | (UNSPEC_FLUSHRS 22) | |
73 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
74 | (UNSPEC_ADDP4 24) |
75 | (UNSPEC_PROLOGUE_USE 25) | |
76 | ]) | |
77 | ||
78 | (define_constants | |
79 | [(UNSPECV_ALLOC 0) | |
80 | (UNSPECV_BLOCKAGE 1) | |
81 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
82 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
83 | (UNSPECV_SET_BSP 4) |
84 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
85 | (UNSPECV_PSAC_NORMAL 6) | |
086c0f96 | 86 | ]) |
c65ebc55 JW |
87 | \f |
88 | ;; :::::::::::::::::::: | |
89 | ;; :: | |
90 | ;; :: Attributes | |
91 | ;; :: | |
92 | ;; :::::::::::::::::::: | |
93 | ||
94 | ;; Instruction type. This primarily determines how instructions can be | |
95 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
96 | ||
97 | ;; A alu, can go in I or M syllable of a bundle | |
98 | ;; I integer | |
99 | ;; M memory | |
100 | ;; F floating-point | |
101 | ;; B branch | |
102 | ;; L long immediate, takes two syllables | |
103 | ;; S stop bit | |
104 | ||
105 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
106 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
107 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
108 | ;; which emit instruction that can go in any slot (e.g. nop). | |
109 | ||
1d5d7a21 RH |
110 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
111 | fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld, | |
112 | chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0, | |
113 | syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f, | |
114 | nop_i,nop_m,nop_x,lfetch" | |
115 | (const_string "unknown")) | |
52e12ad0 | 116 | |
2130b7fb BS |
117 | ;; chk_s has an I and an M form; use type A for convenience. |
118 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
119 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
120 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
121 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 122 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
2130b7fb BS |
123 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
124 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
125 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
126 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
127 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
128 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
129 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 130 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 131 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
132 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
133 | (const_string "unknown"))) | |
c65ebc55 | 134 | |
2130b7fb BS |
135 | (define_attr "itanium_requires_unit0" "no,yes" |
136 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
137 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
138 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
139 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
140 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
141 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
142 | (const_string "no"))) | |
143 | ||
e5bde68a RH |
144 | ;; Predication. True iff this instruction can be predicated. |
145 | ||
146 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
147 | ||
c65ebc55 JW |
148 | \f |
149 | ;; :::::::::::::::::::: | |
150 | ;; :: | |
151 | ;; :: Function Units | |
152 | ;; :: | |
153 | ;; :::::::::::::::::::: | |
154 | ||
2130b7fb BS |
155 | ;; We define 6 "dummy" functional units. All the real work to decide which |
156 | ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only | |
157 | ;; have to ensure here that there are enough copies of the dummy unit so | |
158 | ;; that the scheduler doesn't get confused by MD_SCHED_REORDER. | |
159 | ;; Other than the 6 dummies for normal insns, we also add a single dummy unit | |
160 | ;; for stop bits. | |
161 | ||
162 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0) | |
163 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0) | |
164 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0) | |
165 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0) | |
166 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0) | |
167 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0) | |
168 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0) | |
169 | ||
170 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
171 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0) | |
172 | ;; There is only ony insn `mov = ar.unat' for frar_m: | |
173 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0) | |
174 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0) | |
175 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0) | |
176 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0) | |
177 | ||
178 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0) | |
179 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0) | |
180 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0) | |
181 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0) | |
182 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0) | |
183 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0) | |
184 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0) | |
185 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0) | |
186 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0) | |
187 | ||
188 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
189 | ;; is the 1st syllable of the bundle after stop bit. | |
190 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0) | |
191 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0) | |
192 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0) | |
193 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0) | |
194 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0) | |
195 | ;; Now we use only one insn `mf'. Therfore latency time is set up to 0. | |
196 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0) | |
197 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0) | |
198 | ||
199 | ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use | |
200 | ;; latency time equal to 0: | |
201 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0) | |
202 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
203 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0) | |
204 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0) | |
205 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0) | |
206 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0) | |
207 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0) | |
208 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0) | |
209 | ||
210 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0) | |
211 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0) | |
212 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0) | |
213 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0) | |
214 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0) | |
215 | ||
216 | (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0) | |
217 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0) | |
218 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0) | |
c65ebc55 JW |
219 | \f |
220 | ;; :::::::::::::::::::: | |
221 | ;; :: | |
222 | ;; :: Moves | |
223 | ;; :: | |
224 | ;; :::::::::::::::::::: | |
225 | ||
f2f90c63 RH |
226 | ;; Set of a single predicate register. This is only used to implement |
227 | ;; pr-to-pr move and complement. | |
228 | ||
229 | (define_insn "*movcci" | |
230 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
231 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
232 | "" | |
233 | "@ | |
234 | cmp.ne %0, p0 = r0, r0 | |
235 | cmp.eq %0, p0 = r0, r0 | |
236 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 237 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
238 | (set_attr "predicable" "no")]) |
239 | ||
240 | (define_insn "movbi" | |
cd5c4048 RH |
241 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
242 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
243 | "" |
244 | "@ | |
245 | cmp.ne %0, %I0 = r0, r0 | |
246 | cmp.eq %0, %I0 = r0, r0 | |
247 | # | |
248 | # | |
249 | tbit.nz %0, %I0 = %1, 0 | |
250 | adds %0 = %1, r0 | |
251 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
252 | st1%Q0 %0 = %1%P0 |
253 | mov %0 = %1" | |
52e12ad0 | 254 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
255 | |
256 | (define_split | |
257 | [(set (match_operand:BI 0 "register_operand" "") | |
258 | (match_operand:BI 1 "register_operand" ""))] | |
259 | "reload_completed | |
260 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
261 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
262 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
263 | (set (match_dup 0) (const_int 1))) | |
264 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
265 | (set (match_dup 0) (const_int 0)))] | |
266 | "") | |
267 | ||
268 | (define_split | |
269 | [(set (match_operand:BI 0 "register_operand" "") | |
270 | (match_operand:BI 1 "register_operand" ""))] | |
271 | "reload_completed | |
272 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
273 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
274 | [(set (match_dup 2) (match_dup 4)) | |
275 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 276 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
277 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
278 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
279 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
280 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
281 | ||
c65ebc55 JW |
282 | (define_expand "movqi" |
283 | [(set (match_operand:QI 0 "general_operand" "") | |
284 | (match_operand:QI 1 "general_operand" ""))] | |
285 | "" | |
c65ebc55 | 286 | { |
7b6e506e RH |
287 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
288 | if (!op1) | |
289 | DONE; | |
290 | operands[1] = op1; | |
1d5d7a21 | 291 | }) |
c65ebc55 JW |
292 | |
293 | (define_insn "*movqi_internal" | |
4b983fdc RH |
294 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
295 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 296 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 297 | "@ |
13da91fd | 298 | mov %0 = %r1 |
c65ebc55 JW |
299 | addl %0 = %1, r0 |
300 | ld1%O1 %0 = %1%P1 | |
13da91fd | 301 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 302 | getf.sig %0 = %1 |
13da91fd RH |
303 | setf.sig %0 = %r1 |
304 | mov %0 = %1" | |
52e12ad0 | 305 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
306 | |
307 | (define_expand "movhi" | |
308 | [(set (match_operand:HI 0 "general_operand" "") | |
309 | (match_operand:HI 1 "general_operand" ""))] | |
310 | "" | |
c65ebc55 | 311 | { |
7b6e506e RH |
312 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
313 | if (!op1) | |
314 | DONE; | |
315 | operands[1] = op1; | |
1d5d7a21 | 316 | }) |
c65ebc55 JW |
317 | |
318 | (define_insn "*movhi_internal" | |
4b983fdc RH |
319 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
320 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 321 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 322 | "@ |
13da91fd | 323 | mov %0 = %r1 |
c65ebc55 JW |
324 | addl %0 = %1, r0 |
325 | ld2%O1 %0 = %1%P1 | |
13da91fd | 326 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 327 | getf.sig %0 = %1 |
13da91fd RH |
328 | setf.sig %0 = %r1 |
329 | mov %0 = %1" | |
52e12ad0 | 330 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
331 | |
332 | (define_expand "movsi" | |
333 | [(set (match_operand:SI 0 "general_operand" "") | |
334 | (match_operand:SI 1 "general_operand" ""))] | |
335 | "" | |
c65ebc55 | 336 | { |
7b6e506e RH |
337 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
338 | if (!op1) | |
339 | DONE; | |
340 | operands[1] = op1; | |
1d5d7a21 | 341 | }) |
c65ebc55 JW |
342 | |
343 | (define_insn "*movsi_internal" | |
97e242b0 | 344 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 345 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 346 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 347 | "@ |
13da91fd | 348 | mov %0 = %r1 |
c65ebc55 JW |
349 | addl %0 = %1, r0 |
350 | movl %0 = %1 | |
351 | ld4%O1 %0 = %1%P1 | |
13da91fd | 352 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 353 | getf.sig %0 = %1 |
13da91fd | 354 | setf.sig %0 = %r1 |
97e242b0 RH |
355 | mov %0 = %1 |
356 | mov %0 = %1 | |
357 | mov %0 = %r1" | |
1d5d7a21 | 358 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 359 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
360 | |
361 | (define_expand "movdi" | |
362 | [(set (match_operand:DI 0 "general_operand" "") | |
363 | (match_operand:DI 1 "general_operand" ""))] | |
364 | "" | |
c65ebc55 | 365 | { |
7b6e506e RH |
366 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
367 | if (!op1) | |
368 | DONE; | |
369 | operands[1] = op1; | |
1d5d7a21 | 370 | }) |
c65ebc55 | 371 | |
9a89adb8 RH |
372 | ;; This is used during early compilation to delay the decision on |
373 | ;; how to refer to a variable as long as possible. This is especially | |
374 | ;; important between initial rtl generation and optimization for | |
375 | ;; deferred functions, since we may acquire additional information | |
376 | ;; on the variables used in the meantime. | |
377 | ||
378 | (define_insn_and_split "movdi_symbolic" | |
379 | [(set (match_operand:DI 0 "register_operand" "=r") | |
380 | (match_operand:DI 1 "symbolic_operand" "s")) | |
7b6e506e | 381 | (clobber (match_scratch:DI 2 "=r")) |
9a89adb8 RH |
382 | (use (reg:DI 1))] |
383 | "" | |
384 | "* abort ();" | |
7b6e506e | 385 | "!no_new_pseudos || reload_completed" |
9a89adb8 | 386 | [(const_int 0)] |
7b6e506e RH |
387 | { |
388 | rtx scratch = operands[2]; | |
389 | if (!reload_completed) | |
390 | gen_reg_rtx (Pmode); | |
391 | ia64_expand_load_address (operands[0], operands[1], scratch); | |
392 | DONE; | |
393 | }) | |
9a89adb8 | 394 | |
c65ebc55 | 395 | (define_insn "*movdi_internal" |
4b983fdc | 396 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 397 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 398 | (match_operand:DI 1 "move_operand" |
52e12ad0 | 399 | "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 400 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
401 | { |
402 | static const char * const alt[] = { | |
1d5d7a21 RH |
403 | "%,mov %0 = %r1", |
404 | "%,addl %0 = %1, r0", | |
405 | "%,movl %0 = %1", | |
406 | "%,ld8%O1 %0 = %1%P1", | |
407 | "%,st8%Q0 %0 = %r1%P0", | |
408 | "%,getf.sig %0 = %1", | |
409 | "%,setf.sig %0 = %r1", | |
410 | "%,mov %0 = %1", | |
411 | "%,ldf8 %0 = %1%P1", | |
412 | "%,stf8 %0 = %1%P0", | |
413 | "%,mov %0 = %1", | |
414 | "%,mov %0 = %r1", | |
415 | "%,mov %0 = %1", | |
416 | "%,mov %0 = %1", | |
417 | "%,mov %0 = %1", | |
418 | "%,mov %0 = %1", | |
419 | "mov %0 = pr", | |
420 | "mov pr = %1, -1" | |
9b7bf67d RH |
421 | }; |
422 | ||
9b7bf67d RH |
423 | if (which_alternative == 2 && ! TARGET_NO_PIC |
424 | && symbolic_operand (operands[1], VOIDmode)) | |
425 | abort (); | |
426 | ||
427 | return alt[which_alternative]; | |
1d5d7a21 | 428 | } |
52e12ad0 | 429 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 430 | |
9b7bf67d RH |
431 | (define_split |
432 | [(set (match_operand:DI 0 "register_operand" "") | |
433 | (match_operand:DI 1 "symbolic_operand" ""))] | |
434 | "reload_completed && ! TARGET_NO_PIC" | |
435 | [(const_int 0)] | |
9b7bf67d | 436 | { |
b5d37c6f | 437 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d | 438 | DONE; |
1d5d7a21 | 439 | }) |
9b7bf67d | 440 | |
c65ebc55 JW |
441 | (define_expand "load_fptr" |
442 | [(set (match_dup 2) | |
443 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" ""))) | |
ec039e3c | 444 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 | 445 | "" |
c65ebc55 | 446 | { |
ec039e3c RH |
447 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
448 | operands[3] = gen_rtx_MEM (DImode, operands[2]); | |
449 | RTX_UNCHANGING_P (operands[3]) = 1; | |
1d5d7a21 | 450 | }) |
c65ebc55 JW |
451 | |
452 | (define_insn "*load_fptr_internal1" | |
453 | [(set (match_operand:DI 0 "register_operand" "=r") | |
454 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))] | |
455 | "" | |
456 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 457 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
458 | |
459 | (define_insn "load_gprel" | |
460 | [(set (match_operand:DI 0 "register_operand" "=r") | |
461 | (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))] | |
462 | "" | |
463 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 464 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 465 | |
59da9a7d JW |
466 | (define_insn "gprel64_offset" |
467 | [(set (match_operand:DI 0 "register_operand" "=r") | |
468 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
469 | "" | |
470 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 471 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
472 | |
473 | (define_expand "load_gprel64" | |
474 | [(set (match_dup 2) | |
b5d37c6f | 475 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 476 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 477 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 478 | "" |
ec039e3c RH |
479 | { |
480 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 481 | operands[3] = pic_offset_table_rtx; |
1d5d7a21 | 482 | }) |
59da9a7d | 483 | |
c65ebc55 | 484 | (define_expand "load_symptr" |
b5d37c6f BS |
485 | [(set (match_operand:DI 2 "register_operand" "") |
486 | (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) | |
dee4095a | 487 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 | 488 | "" |
c65ebc55 | 489 | { |
dee4095a | 490 | operands[3] = gen_rtx_MEM (DImode, operands[2]); |
b5d37c6f | 491 | operands[4] = pic_offset_table_rtx; |
dee4095a | 492 | RTX_UNCHANGING_P (operands[3]) = 1; |
1d5d7a21 | 493 | }) |
c65ebc55 JW |
494 | |
495 | (define_insn "*load_symptr_internal1" | |
496 | [(set (match_operand:DI 0 "register_operand" "=r") | |
ec039e3c | 497 | (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))] |
c65ebc55 JW |
498 | "" |
499 | "addl %0 = @ltoff(%1), gp" | |
52e12ad0 | 500 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 501 | |
7b6e506e RH |
502 | (define_insn "load_ltoff_dtpmod" |
503 | [(set (match_operand:DI 0 "register_operand" "=r") | |
504 | (plus:DI (reg:DI 1) | |
505 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
506 | UNSPEC_LTOFF_DTPMOD)))] | |
507 | "" | |
508 | "addl %0 = @ltoff(@dtpmod(%1)), gp" | |
509 | [(set_attr "itanium_class" "ialu")]) | |
510 | ||
511 | (define_insn "load_ltoff_dtprel" | |
512 | [(set (match_operand:DI 0 "register_operand" "=r") | |
513 | (plus:DI (reg:DI 1) | |
514 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
515 | UNSPEC_LTOFF_DTPREL)))] | |
516 | "" | |
517 | "addl %0 = @ltoff(@dtprel(%1)), gp" | |
518 | [(set_attr "itanium_class" "ialu")]) | |
519 | ||
520 | (define_expand "load_dtprel" | |
521 | [(set (match_operand:DI 0 "register_operand" "") | |
522 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
523 | UNSPEC_DTPREL))] | |
524 | "" | |
525 | "") | |
526 | ||
527 | (define_insn "*load_dtprel64" | |
528 | [(set (match_operand:DI 0 "register_operand" "=r") | |
529 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
530 | UNSPEC_DTPREL))] | |
531 | "TARGET_TLS64" | |
532 | "movl %0 = @dtprel(%1)" | |
533 | [(set_attr "itanium_class" "long_i")]) | |
534 | ||
535 | (define_insn "*load_dtprel22" | |
536 | [(set (match_operand:DI 0 "register_operand" "=r") | |
537 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
538 | UNSPEC_DTPREL))] | |
539 | "" | |
540 | "addl %0 = @dtprel(%1), r0" | |
541 | [(set_attr "itanium_class" "ialu")]) | |
542 | ||
543 | (define_expand "add_dtprel" | |
544 | [(set (match_operand:DI 0 "register_operand" "") | |
545 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
546 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
547 | UNSPEC_DTPREL)))] | |
548 | "!TARGET_TLS64" | |
549 | "") | |
550 | ||
551 | (define_insn "*add_dtprel14" | |
552 | [(set (match_operand:DI 0 "register_operand" "=r") | |
553 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
554 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
555 | UNSPEC_DTPREL)))] | |
556 | "TARGET_TLS14" | |
557 | "adds %0 = @dtprel(%2), %1" | |
558 | [(set_attr "itanium_class" "ialu")]) | |
559 | ||
560 | (define_insn "*add_dtprel22" | |
561 | [(set (match_operand:DI 0 "register_operand" "=r") | |
562 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
563 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
564 | UNSPEC_DTPREL)))] | |
565 | "TARGET_TLS22" | |
566 | "addl %0 = @dtprel(%2), %1" | |
567 | [(set_attr "itanium_class" "ialu")]) | |
568 | ||
569 | (define_insn "load_ltoff_tprel" | |
570 | [(set (match_operand:DI 0 "register_operand" "=r") | |
571 | (plus:DI (reg:DI 1) | |
572 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
573 | UNSPEC_LTOFF_TPREL)))] | |
574 | "" | |
575 | "addl %0 = @ltoff(@tprel(%1)), gp" | |
576 | [(set_attr "itanium_class" "ialu")]) | |
577 | ||
578 | (define_expand "load_tprel" | |
579 | [(set (match_operand:DI 0 "register_operand" "") | |
580 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
581 | UNSPEC_TPREL))] | |
582 | "" | |
583 | "") | |
584 | ||
585 | (define_insn "*load_tprel64" | |
586 | [(set (match_operand:DI 0 "register_operand" "=r") | |
587 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
588 | UNSPEC_TPREL))] | |
589 | "TARGET_TLS64" | |
590 | "movl %0 = @tprel(%1)" | |
591 | [(set_attr "itanium_class" "long_i")]) | |
592 | ||
593 | (define_insn "*load_tprel22" | |
594 | [(set (match_operand:DI 0 "register_operand" "=r") | |
595 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
596 | UNSPEC_TPREL))] | |
597 | "" | |
598 | "addl %0 = @tprel(%1), r0" | |
599 | [(set_attr "itanium_class" "ialu")]) | |
600 | ||
601 | (define_expand "add_tprel" | |
602 | [(set (match_operand:DI 0 "register_operand" "") | |
603 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
604 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
605 | UNSPEC_TPREL)))] | |
606 | "!TARGET_TLS64" | |
607 | "") | |
608 | ||
609 | (define_insn "*add_tprel14" | |
610 | [(set (match_operand:DI 0 "register_operand" "=r") | |
611 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
612 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
613 | UNSPEC_TPREL)))] | |
614 | "TARGET_TLS14" | |
615 | "adds %0 = @tprel(%2), %1" | |
616 | [(set_attr "itanium_class" "ialu")]) | |
617 | ||
618 | (define_insn "*add_tprel22" | |
619 | [(set (match_operand:DI 0 "register_operand" "=r") | |
620 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
621 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
622 | UNSPEC_TPREL)))] | |
623 | "TARGET_TLS22" | |
624 | "addl %0 = @tprel(%2), %1" | |
625 | [(set_attr "itanium_class" "ialu")]) | |
626 | ||
3f622353 RH |
627 | ;; With no offsettable memory references, we've got to have a scratch |
628 | ;; around to play with the second word. | |
629 | (define_expand "movti" | |
630 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
631 | (match_operand:TI 1 "general_operand" "")) | |
632 | (clobber (match_scratch:DI 2 ""))])] | |
633 | "" | |
3f622353 | 634 | { |
7b6e506e RH |
635 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
636 | if (!op1) | |
637 | DONE; | |
638 | operands[1] = op1; | |
1d5d7a21 | 639 | }) |
3f622353 RH |
640 | |
641 | (define_insn_and_split "*movti_internal" | |
642 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
643 | (match_operand:TI 1 "general_operand" "ri,m,r")) | |
644 | (clobber (match_scratch:DI 2 "=X,&r,&r"))] | |
645 | "ia64_move_ok (operands[0], operands[1])" | |
646 | "#" | |
647 | "reload_completed" | |
648 | [(const_int 0)] | |
3f622353 | 649 | { |
703cf211 | 650 | rtx adj1, adj2, in[2], out[2], insn; |
3f622353 RH |
651 | int first; |
652 | ||
653 | adj1 = ia64_split_timode (in, operands[1], operands[2]); | |
654 | adj2 = ia64_split_timode (out, operands[0], operands[2]); | |
655 | ||
656 | first = 0; | |
657 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
658 | { | |
659 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
660 | abort (); | |
661 | first = 1; | |
662 | } | |
663 | ||
664 | if (adj1 && adj2) | |
665 | abort (); | |
666 | if (adj1) | |
667 | emit_insn (adj1); | |
668 | if (adj2) | |
669 | emit_insn (adj2); | |
703cf211 BS |
670 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); |
671 | if (GET_CODE (out[first]) == MEM | |
672 | && GET_CODE (XEXP (out[first], 0)) == POST_MODIFY) | |
673 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
674 | XEXP (XEXP (out[first], 0), 0), | |
675 | REG_NOTES (insn)); | |
676 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
677 | if (GET_CODE (out[!first]) == MEM | |
678 | && GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY) | |
679 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
680 | XEXP (XEXP (out[!first], 0), 0), | |
681 | REG_NOTES (insn)); | |
3f622353 | 682 | DONE; |
1d5d7a21 | 683 | } |
52e12ad0 | 684 | [(set_attr "itanium_class" "unknown") |
3f622353 | 685 | (set_attr "predicable" "no")]) |
e314e331 | 686 | |
3f622353 RH |
687 | ;; ??? SSA creates these. Can't allow memories since we don't have |
688 | ;; the scratch register. Fortunately combine will know how to add | |
689 | ;; the clobber and scratch. | |
690 | (define_insn_and_split "*movti_internal_reg" | |
691 | [(set (match_operand:TI 0 "register_operand" "=r") | |
692 | (match_operand:TI 1 "nonmemory_operand" "ri"))] | |
693 | "" | |
e314e331 | 694 | "#" |
3f622353 RH |
695 | "reload_completed" |
696 | [(const_int 0)] | |
3f622353 RH |
697 | { |
698 | rtx in[2], out[2]; | |
699 | int first; | |
700 | ||
701 | ia64_split_timode (in, operands[1], NULL_RTX); | |
702 | ia64_split_timode (out, operands[0], NULL_RTX); | |
703 | ||
704 | first = 0; | |
705 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
706 | { | |
707 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
708 | abort (); | |
709 | first = 1; | |
710 | } | |
711 | ||
712 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
713 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
714 | DONE; | |
1d5d7a21 | 715 | } |
52e12ad0 | 716 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
717 | (set_attr "predicable" "no")]) |
718 | ||
3f622353 RH |
719 | (define_expand "reload_inti" |
720 | [(parallel [(set (match_operand:TI 0 "register_operand" "=r") | |
721 | (match_operand:TI 1 "" "m")) | |
60a3c181 | 722 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 | 723 | "" |
3f622353 | 724 | { |
60a3c181 RH |
725 | unsigned int s_regno = REGNO (operands[2]); |
726 | if (s_regno == REGNO (operands[0])) | |
727 | s_regno += 1; | |
728 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
1d5d7a21 | 729 | }) |
3f622353 RH |
730 | |
731 | (define_expand "reload_outti" | |
732 | [(parallel [(set (match_operand:TI 0 "" "=m") | |
733 | (match_operand:TI 1 "register_operand" "r")) | |
60a3c181 | 734 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 | 735 | "" |
3f622353 | 736 | { |
60a3c181 RH |
737 | unsigned int s_regno = REGNO (operands[2]); |
738 | if (s_regno == REGNO (operands[1])) | |
739 | s_regno += 1; | |
740 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
1d5d7a21 | 741 | }) |
e314e331 | 742 | |
c65ebc55 JW |
743 | ;; Floating Point Moves |
744 | ;; | |
745 | ;; Note - Patterns for SF mode moves are compulsory, but | |
746 | ;; patterns for DF are optional, as GCC can synthesise them. | |
747 | ||
748 | (define_expand "movsf" | |
749 | [(set (match_operand:SF 0 "general_operand" "") | |
750 | (match_operand:SF 1 "general_operand" ""))] | |
751 | "" | |
c65ebc55 | 752 | { |
7b6e506e RH |
753 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
754 | if (!op1) | |
755 | DONE; | |
756 | operands[1] = op1; | |
1d5d7a21 | 757 | }) |
c65ebc55 | 758 | |
c65ebc55 | 759 | (define_insn "*movsf_internal" |
4b983fdc RH |
760 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
761 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 762 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 763 | "@ |
1d5d7a21 RH |
764 | mov %0 = %F1 |
765 | ldfs %0 = %1%P1 | |
766 | stfs %0 = %F1%P0 | |
767 | getf.s %0 = %F1 | |
768 | setf.s %0 = %1 | |
769 | mov %0 = %1 | |
770 | ld4%O1 %0 = %1%P1 | |
771 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 772 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
773 | |
774 | (define_expand "movdf" | |
775 | [(set (match_operand:DF 0 "general_operand" "") | |
776 | (match_operand:DF 1 "general_operand" ""))] | |
777 | "" | |
c65ebc55 | 778 | { |
7b6e506e RH |
779 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
780 | if (!op1) | |
781 | DONE; | |
782 | operands[1] = op1; | |
1d5d7a21 | 783 | }) |
c65ebc55 | 784 | |
c65ebc55 | 785 | (define_insn "*movdf_internal" |
4b983fdc RH |
786 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
787 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 788 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 789 | "@ |
1d5d7a21 RH |
790 | mov %0 = %F1 |
791 | ldfd %0 = %1%P1 | |
792 | stfd %0 = %F1%P0 | |
793 | getf.d %0 = %F1 | |
794 | setf.d %0 = %1 | |
795 | mov %0 = %1 | |
796 | ld8%O1 %0 = %1%P1 | |
797 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 798 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 799 | |
3f622353 RH |
800 | ;; With no offsettable memory references, we've got to have a scratch |
801 | ;; around to play with the second word if the variable winds up in GRs. | |
802 | (define_expand "movtf" | |
803 | [(set (match_operand:TF 0 "general_operand" "") | |
804 | (match_operand:TF 1 "general_operand" ""))] | |
23c108af | 805 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 806 | { |
3f622353 RH |
807 | /* We must support TFmode loads into general registers for stdarg/vararg |
808 | and unprototyped calls. We split them into DImode loads for convenience. | |
809 | We don't need TFmode stores from general regs, because a stdarg/vararg | |
810 | routine does a block store to memory of unnamed arguments. */ | |
811 | if (GET_CODE (operands[0]) == REG | |
812 | && GR_REGNO_P (REGNO (operands[0]))) | |
813 | { | |
814 | /* We're hoping to transform everything that deals with TFmode | |
815 | quantities and GR registers early in the compiler. */ | |
816 | if (no_new_pseudos) | |
817 | abort (); | |
818 | ||
819 | /* Struct to register can just use TImode instead. */ | |
820 | if ((GET_CODE (operands[1]) == SUBREG | |
821 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
822 | || (GET_CODE (operands[1]) == REG | |
823 | && GR_REGNO_P (REGNO (operands[1])))) | |
824 | { | |
825 | emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), | |
826 | SUBREG_REG (operands[1])); | |
827 | DONE; | |
828 | } | |
829 | ||
830 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
831 | { | |
832 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), | |
2bf47a10 | 833 | operand_subword (operands[1], 0, 0, TFmode)); |
3f622353 | 834 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), |
2bf47a10 | 835 | operand_subword (operands[1], 1, 0, TFmode)); |
3f622353 RH |
836 | DONE; |
837 | } | |
838 | ||
839 | /* If the quantity is in a register not known to be GR, spill it. */ | |
840 | if (register_operand (operands[1], TFmode)) | |
841 | operands[1] = spill_tfmode_operand (operands[1], 1); | |
842 | ||
843 | if (GET_CODE (operands[1]) == MEM) | |
844 | { | |
845 | rtx out[2]; | |
846 | ||
847 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
848 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); | |
849 | ||
f4ef873c RK |
850 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
851 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
852 | DONE; |
853 | } | |
854 | ||
855 | abort (); | |
856 | } | |
857 | ||
858 | if (! reload_in_progress && ! reload_completed) | |
859 | { | |
860 | operands[0] = spill_tfmode_operand (operands[0], 0); | |
861 | operands[1] = spill_tfmode_operand (operands[1], 0); | |
862 | ||
863 | if (! ia64_move_ok (operands[0], operands[1])) | |
864 | operands[1] = force_reg (TFmode, operands[1]); | |
865 | } | |
1d5d7a21 | 866 | }) |
e5bde68a | 867 | |
3b572406 | 868 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 869 | |
3f622353 RH |
870 | (define_insn "*movtf_internal" |
871 | [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m") | |
872 | (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] | |
23c108af | 873 | "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 874 | "@ |
1d5d7a21 RH |
875 | mov %0 = %F1 |
876 | ldfe %0 = %1%P1 | |
877 | stfe %0 = %F1%P0" | |
52e12ad0 | 878 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
c65ebc55 JW |
879 | \f |
880 | ;; :::::::::::::::::::: | |
881 | ;; :: | |
882 | ;; :: Conversions | |
883 | ;; :: | |
884 | ;; :::::::::::::::::::: | |
885 | ||
886 | ;; Signed conversions from a smaller integer to a larger integer | |
887 | ||
888 | (define_insn "extendqidi2" | |
0551c32d RH |
889 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
890 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
891 | "" |
892 | "sxt1 %0 = %1" | |
52e12ad0 | 893 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
894 | |
895 | (define_insn "extendhidi2" | |
0551c32d RH |
896 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
897 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
898 | "" |
899 | "sxt2 %0 = %1" | |
52e12ad0 | 900 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
901 | |
902 | (define_insn "extendsidi2" | |
655f2eb9 RH |
903 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
904 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
905 | "" |
906 | "@ | |
907 | sxt4 %0 = %1 | |
aebf2462 | 908 | fsxt.r %0 = %1, %1" |
52e12ad0 | 909 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
910 | |
911 | ;; Unsigned conversions from a smaller integer to a larger integer | |
912 | ||
913 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
914 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
915 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
916 | "" |
917 | "@ | |
918 | zxt1 %0 = %1 | |
919 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 920 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
921 | |
922 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
923 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
924 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
925 | "" |
926 | "@ | |
927 | zxt2 %0 = %1 | |
928 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 929 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
930 | |
931 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 932 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 933 | (zero_extend:DI |
655f2eb9 | 934 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
935 | "" |
936 | "@ | |
937 | zxt4 %0 = %1 | |
938 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 939 | fmix.r %0 = f0, %1" |
52e12ad0 | 940 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
941 | |
942 | ;; Convert between floating point types of different sizes. | |
943 | ||
640cea5f JW |
944 | ;; At first glance, it would appear that emitting fnorm for an extending |
945 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
946 | ;; correctly only if the input is properly rounded for its type. In | |
947 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
948 | ;; denorm single. Since we don't know what the next instruction will be, we | |
949 | ;; have to emit an fnorm. | |
950 | ||
e8e20f18 RH |
951 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
952 | ;; when we can. Should probably use a scheme like has been proposed | |
953 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
954 | ;; would let combine merge the thing into adjacent insns. See also how the |
955 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
956 | ;; se_register_operand. | |
c65ebc55 | 957 | |
640cea5f JW |
958 | (define_insn "extendsfdf2" |
959 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
960 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 961 | "" |
640cea5f JW |
962 | "fnorm.d %0 = %1" |
963 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 964 | |
640cea5f JW |
965 | (define_insn "extendsftf2" |
966 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
967 | (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))] | |
23c108af | 968 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
969 | "fnorm %0 = %1" |
970 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 971 | |
640cea5f JW |
972 | (define_insn "extenddftf2" |
973 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
974 | (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))] | |
23c108af | 975 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
976 | "fnorm %0 = %1" |
977 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 978 | |
c65ebc55 | 979 | (define_insn "truncdfsf2" |
0551c32d RH |
980 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
981 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 982 | "" |
aebf2462 | 983 | "fnorm.s %0 = %1" |
52e12ad0 | 984 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 985 | |
3f622353 | 986 | (define_insn "trunctfsf2" |
0551c32d RH |
987 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
988 | (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 989 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 990 | "fnorm.s %0 = %1" |
52e12ad0 | 991 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 992 | |
3f622353 | 993 | (define_insn "trunctfdf2" |
0551c32d RH |
994 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
995 | (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 996 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 997 | "fnorm.d %0 = %1" |
52e12ad0 | 998 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
999 | |
1000 | ;; Convert between signed integer types and floating point. | |
1001 | ||
3f622353 | 1002 | (define_insn "floatditf2" |
0551c32d RH |
1003 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
1004 | (float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 1005 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 1006 | "fcvt.xf %0 = %1" |
52e12ad0 | 1007 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1008 | |
23c108af SE |
1009 | ;; ??? Suboptimal. This should be split somehow. |
1010 | (define_insn "floatdidf2" | |
1011 | [(set (match_operand:DF 0 "register_operand" "=f") | |
1012 | (float:DF (match_operand:DI 1 "register_operand" "f")))] | |
1013 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
1014 | "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0" | |
1015 | [(set_attr "itanium_class" "fcvtfx")]) | |
1016 | ||
1017 | ;; ??? Suboptimal. This should be split somehow. | |
1018 | (define_insn "floatdisf2" | |
1019 | [(set (match_operand:SF 0 "register_operand" "=f") | |
1020 | (float:SF (match_operand:DI 1 "register_operand" "f")))] | |
1021 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
1022 | "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0" | |
1023 | [(set_attr "itanium_class" "fcvtfx")]) | |
1024 | ||
c65ebc55 | 1025 | (define_insn "fix_truncsfdi2" |
0551c32d RH |
1026 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1027 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1028 | "" |
aebf2462 | 1029 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1030 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1031 | |
1032 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1033 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1034 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1035 | "" |
aebf2462 | 1036 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1037 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1038 | |
3f622353 | 1039 | (define_insn "fix_trunctfdi2" |
0551c32d RH |
1040 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1041 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1042 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1043 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1044 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1045 | |
655f2eb9 RH |
1046 | (define_insn "fix_trunctfdi2_alts" |
1047 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
1048 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
1049 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 1050 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1051 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1052 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1053 | |
c65ebc55 JW |
1054 | ;; Convert between unsigned integer types and floating point. |
1055 | ||
1056 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1057 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1058 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1059 | "" |
aebf2462 | 1060 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1061 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1062 | |
1063 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1064 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1065 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1066 | "" |
aebf2462 | 1067 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1068 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1069 | |
3f622353 | 1070 | (define_insn "floatunsditf2" |
0551c32d RH |
1071 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
1072 | (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 1073 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1074 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1075 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1076 | |
c65ebc55 | 1077 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1078 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1079 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1080 | "" |
aebf2462 | 1081 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1082 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1083 | |
1084 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1085 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1086 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1087 | "" |
aebf2462 | 1088 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1089 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1090 | |
3f622353 | 1091 | (define_insn "fixuns_trunctfdi2" |
0551c32d RH |
1092 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1093 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 1094 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1095 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1096 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 RH |
1097 | |
1098 | (define_insn "fixuns_trunctfdi2_alts" | |
1099 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
1100 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
1101 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 1102 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 1103 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1104 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1105 | \f |
1106 | ;; :::::::::::::::::::: | |
1107 | ;; :: | |
1108 | ;; :: Bit field extraction | |
1109 | ;; :: | |
1110 | ;; :::::::::::::::::::: | |
1111 | ||
c65ebc55 | 1112 | (define_insn "extv" |
0551c32d RH |
1113 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1114 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1115 | (match_operand:DI 2 "const_int_operand" "n") |
1116 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1117 | "" | |
1118 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1119 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1120 | |
1121 | (define_insn "extzv" | |
0551c32d RH |
1122 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1123 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1124 | (match_operand:DI 2 "const_int_operand" "n") |
1125 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1126 | "" | |
1127 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1128 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1129 | |
1130 | ;; Insert a bit field. | |
1131 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1132 | ;; Source1 can be 0 or -1. | |
1133 | ;; Source2 can be 0. | |
1134 | ||
1135 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1136 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1137 | ;; where source2 != dest. | |
1138 | ||
1139 | (define_expand "insv" | |
0551c32d | 1140 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1141 | (match_operand:DI 1 "const_int_operand" "") |
1142 | (match_operand:DI 2 "const_int_operand" "")) | |
1143 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1144 | "" | |
c65ebc55 JW |
1145 | { |
1146 | int width = INTVAL (operands[1]); | |
1147 | int shift = INTVAL (operands[2]); | |
1148 | ||
1149 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1150 | pseudo. */ | |
1151 | if (! register_operand (operands[3], DImode) | |
1152 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1153 | operands[3] = force_reg (DImode, operands[3]); | |
1154 | ||
1155 | /* If this is a single dep instruction, we have nothing to do. */ | |
1156 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1157 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1158 | { | |
1159 | /* Check for cases that can be implemented with a mix instruction. */ | |
1160 | if (width == 32 && shift == 0) | |
1161 | { | |
1162 | /* Directly generating the mix4left instruction confuses | |
1163 | optimize_bit_field in function.c. Since this is performing | |
1164 | a useful optimization, we defer generation of the complicated | |
1165 | mix4left RTL to the first splitting phase. */ | |
1166 | rtx tmp = gen_reg_rtx (DImode); | |
1167 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1168 | DONE; | |
1169 | } | |
1170 | else if (width == 32 && shift == 32) | |
1171 | { | |
1172 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1173 | DONE; | |
1174 | } | |
1175 | ||
d2ba6dcf JW |
1176 | /* We could handle remaining cases by emitting multiple dep |
1177 | instructions. | |
1178 | ||
1179 | If we need more than two dep instructions then we lose. A 6 | |
1180 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1181 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1182 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1183 | only one function unit that can execute dep and shr immed. | |
1184 | ||
1185 | If we only need two dep instruction, then we still lose. | |
1186 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1187 | the unnecessary mov, this is still undesirable because it will be | |
1188 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1189 | function unit. */ | |
1190 | ||
c65ebc55 JW |
1191 | FAIL; |
1192 | ||
1193 | #if 0 | |
1194 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1195 | for now. */ | |
1196 | while (width > 16) | |
1197 | { | |
1198 | rtx tmp; | |
1199 | ||
1200 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1201 | operands[3])); | |
1202 | shift += 16; | |
1203 | width -= 16; | |
1204 | tmp = gen_reg_rtx (DImode); | |
1205 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1206 | operands[3] = tmp; | |
1207 | } | |
1208 | operands[1] = GEN_INT (width); | |
1209 | operands[2] = GEN_INT (shift); | |
1210 | #endif | |
1211 | } | |
1d5d7a21 | 1212 | }) |
c65ebc55 JW |
1213 | |
1214 | (define_insn "*insv_internal" | |
0551c32d | 1215 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1216 | (match_operand:DI 1 "const_int_operand" "n") |
1217 | (match_operand:DI 2 "const_int_operand" "n")) | |
1218 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1219 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1220 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1221 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1222 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1223 | |
041f25e6 RH |
1224 | ;; Combine doesn't like to create bitfield insertions into zero. |
1225 | (define_insn "*depz_internal" | |
0551c32d RH |
1226 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1227 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1228 | (match_operand:DI 2 "const_int_operand" "n")) |
1229 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1230 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1231 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
041f25e6 RH |
1232 | { |
1233 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1234 | return "%,dep.z %0 = %1, %2, %3"; |
1235 | } | |
52e12ad0 | 1236 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1237 | |
c65ebc55 | 1238 | (define_insn "shift_mix4left" |
0551c32d | 1239 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1240 | (const_int 32) (const_int 0)) |
0551c32d RH |
1241 | (match_operand:DI 1 "gr_register_operand" "r")) |
1242 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1243 | "" |
1244 | "#" | |
52e12ad0 | 1245 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1246 | |
c65ebc55 JW |
1247 | (define_split |
1248 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1249 | (const_int 32) (const_int 0)) | |
1250 | (match_operand:DI 1 "register_operand" "")) | |
1251 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1252 | "reload_completed" | |
1253 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
c65ebc55 JW |
1254 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) |
1255 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1256 | "operands[3] = operands[2];") | |
1257 | ||
1258 | (define_split | |
1259 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1260 | (const_int 32) (const_int 0)) | |
1261 | (match_operand:DI 1 "register_operand" "")) | |
1262 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1263 | "! reload_completed" | |
1264 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
1265 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1266 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1267 | "operands[3] = operands[2];") | |
1268 | ||
1269 | (define_insn "*mix4left" | |
0551c32d | 1270 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1271 | (const_int 32) (const_int 0)) |
0551c32d | 1272 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1273 | (const_int 32)))] |
1274 | "" | |
1275 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1276 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1277 | |
1278 | (define_insn "mix4right" | |
0551c32d | 1279 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1280 | (const_int 32) (const_int 32)) |
0551c32d | 1281 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1282 | "" |
1283 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1284 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1285 | |
1286 | ;; This is used by the rotrsi3 pattern. | |
1287 | ||
1288 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1289 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1290 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1291 | (ashift:DI (zero_extend:DI | |
1292 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1293 | (const_int 32))))] |
1294 | "" | |
fa9a44e8 | 1295 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1296 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1297 | |
1298 | \f | |
1299 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1300 | ;; :: |
f2f90c63 RH |
1301 | ;; :: 1 bit Integer arithmetic |
1302 | ;; :: | |
1303 | ;; :::::::::::::::::::: | |
1304 | ||
1305 | (define_insn_and_split "andbi3" | |
1306 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1307 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1308 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1309 | "" | |
1310 | "@ | |
1311 | # | |
1312 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1313 | and %0 = %2, %1" | |
1314 | "reload_completed | |
1315 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1316 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1317 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1318 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1319 | (match_dup 0))))] | |
1320 | "" | |
52e12ad0 | 1321 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1322 | |
1323 | (define_insn_and_split "*andcmbi3" | |
1324 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1325 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1326 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1327 | "" | |
1328 | "@ | |
1329 | # | |
967603ef | 1330 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1331 | andcm %0 = %2, %1" |
1332 | "reload_completed | |
1333 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1334 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1335 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1336 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1337 | (match_dup 0))))] | |
1338 | "" | |
52e12ad0 | 1339 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1340 | |
1341 | (define_insn_and_split "iorbi3" | |
1342 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1343 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1344 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1345 | "" | |
1346 | "@ | |
1347 | # | |
1348 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1349 | or %0 = %2, %1" | |
1350 | "reload_completed | |
1351 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1352 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1353 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1354 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1355 | (match_dup 0))))] | |
1356 | "" | |
52e12ad0 | 1357 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1358 | |
1359 | (define_insn_and_split "*iorcmbi3" | |
1360 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1361 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1362 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1363 | "" | |
1364 | "@ | |
1365 | # | |
967603ef | 1366 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1367 | "reload_completed |
1368 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1369 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1370 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1371 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1372 | (match_dup 0))))] | |
1373 | "" | |
52e12ad0 | 1374 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1375 | |
1376 | (define_insn "one_cmplbi2" | |
1377 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1378 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1379 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1380 | "" | |
1381 | "@ | |
1382 | tbit.z %0, %I0 = %1, 0 | |
1383 | xor %0 = 1, %1 | |
1384 | # | |
1385 | #" | |
52e12ad0 | 1386 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1387 | |
1388 | (define_split | |
1389 | [(set (match_operand:BI 0 "register_operand" "") | |
1390 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1391 | (clobber (match_scratch:BI 2 ""))] | |
1392 | "reload_completed | |
1393 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1394 | && rtx_equal_p (operands[0], operands[1])" |
1395 | [(set (match_dup 4) (match_dup 3)) | |
1396 | (set (match_dup 0) (const_int 1)) | |
1397 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1398 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1399 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1400 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1401 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1402 | ||
1403 | (define_split | |
1404 | [(set (match_operand:BI 0 "register_operand" "") | |
1405 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1406 | (clobber (match_scratch:BI 2 ""))] | |
1407 | "reload_completed | |
1408 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1409 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1410 | && ! rtx_equal_p (operands[0], operands[1])" | |
1411 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1412 | (set (match_dup 0) (const_int 0))) | |
1413 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1414 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1415 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1416 | "") |
1417 | ||
1418 | (define_insn "*cmpsi_and_0" | |
1419 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1420 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1421 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1422 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1423 | (match_operand:BI 1 "register_operand" "0")))] | |
1424 | "" | |
1425 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1426 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1427 | |
1428 | (define_insn "*cmpsi_and_1" | |
1429 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1430 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1431 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1432 | (const_int 0)]) | |
1433 | (match_operand:BI 1 "register_operand" "0")))] | |
1434 | "" | |
1435 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1436 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1437 | |
1438 | (define_insn "*cmpsi_andnot_0" | |
1439 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1440 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1441 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1442 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1443 | (match_operand:BI 1 "register_operand" "0")))] | |
1444 | "" | |
1445 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1446 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1447 | |
1448 | (define_insn "*cmpsi_andnot_1" | |
1449 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1450 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1451 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1452 | (const_int 0)])) | |
1453 | (match_operand:BI 1 "register_operand" "0")))] | |
1454 | "" | |
1455 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1456 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1457 | |
1458 | (define_insn "*cmpdi_and_0" | |
1459 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1460 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1461 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1462 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1463 | (match_operand:BI 1 "register_operand" "0")))] | |
1464 | "" | |
1465 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1466 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1467 | |
1468 | (define_insn "*cmpdi_and_1" | |
1469 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1470 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1471 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1472 | (const_int 0)]) | |
1473 | (match_operand:BI 1 "register_operand" "0")))] | |
1474 | "" | |
1475 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1476 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1477 | |
1478 | (define_insn "*cmpdi_andnot_0" | |
1479 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1480 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1481 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1482 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1483 | (match_operand:BI 1 "register_operand" "0")))] | |
1484 | "" | |
1485 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1486 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1487 | |
1488 | (define_insn "*cmpdi_andnot_1" | |
1489 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1490 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1491 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1492 | (const_int 0)])) | |
1493 | (match_operand:BI 1 "register_operand" "0")))] | |
1494 | "" | |
1495 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1496 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1497 | |
1498 | (define_insn "*tbit_and_0" | |
1499 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1500 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1501 | (const_int 1)) | |
1502 | (const_int 0)) | |
c77e04ae | 1503 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1504 | "" |
1505 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1506 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1507 | |
1508 | (define_insn "*tbit_and_1" | |
1509 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1510 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1511 | (const_int 1)) | |
1512 | (const_int 0)) | |
c77e04ae | 1513 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1514 | "" |
1515 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1516 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1517 | |
1518 | (define_insn "*tbit_and_2" | |
1519 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1520 | (and:BI (ne:BI (zero_extract:DI | |
1521 | (match_operand:DI 1 "gr_register_operand" "r") | |
1522 | (const_int 1) | |
1523 | (match_operand:DI 2 "const_int_operand" "n")) | |
1524 | (const_int 0)) | |
1525 | (match_operand:BI 3 "register_operand" "0")))] | |
1526 | "" | |
1527 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1528 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1529 | |
1530 | (define_insn "*tbit_and_3" | |
1531 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1532 | (and:BI (eq:BI (zero_extract:DI | |
1533 | (match_operand:DI 1 "gr_register_operand" "r") | |
1534 | (const_int 1) | |
1535 | (match_operand:DI 2 "const_int_operand" "n")) | |
1536 | (const_int 0)) | |
1537 | (match_operand:BI 3 "register_operand" "0")))] | |
1538 | "" | |
1539 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1540 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1541 | |
1542 | (define_insn "*cmpsi_or_0" | |
1543 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1544 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1545 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1546 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1547 | (match_operand:BI 1 "register_operand" "0")))] | |
1548 | "" | |
1549 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1550 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1551 | |
1552 | (define_insn "*cmpsi_or_1" | |
1553 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1554 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1555 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1556 | (const_int 0)]) | |
1557 | (match_operand:BI 1 "register_operand" "0")))] | |
1558 | "" | |
1559 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1560 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1561 | |
1562 | (define_insn "*cmpsi_orcm_0" | |
1563 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1564 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1565 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1566 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1567 | (match_operand:BI 1 "register_operand" "0")))] | |
1568 | "" | |
1569 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1570 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1571 | |
1572 | (define_insn "*cmpsi_orcm_1" | |
1573 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1574 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1575 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1576 | (const_int 0)])) | |
1577 | (match_operand:BI 1 "register_operand" "0")))] | |
1578 | "" | |
1579 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1580 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1581 | |
1582 | (define_insn "*cmpdi_or_0" | |
1583 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1584 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1585 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1586 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1587 | (match_operand:BI 1 "register_operand" "0")))] | |
1588 | "" | |
1589 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1590 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1591 | |
1592 | (define_insn "*cmpdi_or_1" | |
1593 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1594 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1595 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1596 | (const_int 0)]) | |
1597 | (match_operand:BI 1 "register_operand" "0")))] | |
1598 | "" | |
1599 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1600 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1601 | |
1602 | (define_insn "*cmpdi_orcm_0" | |
1603 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1604 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1605 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1606 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1607 | (match_operand:BI 1 "register_operand" "0")))] | |
1608 | "" | |
1609 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1610 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1611 | |
1612 | (define_insn "*cmpdi_orcm_1" | |
1613 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1614 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1615 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1616 | (const_int 0)])) | |
1617 | (match_operand:BI 1 "register_operand" "0")))] | |
1618 | "" | |
1619 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1620 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1621 | |
1622 | (define_insn "*tbit_or_0" | |
1623 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1624 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1625 | (const_int 1)) | |
1626 | (const_int 0)) | |
c77e04ae | 1627 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1628 | "" |
1629 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1630 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1631 | |
1632 | (define_insn "*tbit_or_1" | |
1633 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1634 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1635 | (const_int 1)) | |
1636 | (const_int 0)) | |
c77e04ae | 1637 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1638 | "" |
1639 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1640 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1641 | |
1642 | (define_insn "*tbit_or_2" | |
1643 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1644 | (ior:BI (ne:BI (zero_extract:DI | |
1645 | (match_operand:DI 1 "gr_register_operand" "r") | |
1646 | (const_int 1) | |
1647 | (match_operand:DI 2 "const_int_operand" "n")) | |
1648 | (const_int 0)) | |
1649 | (match_operand:BI 3 "register_operand" "0")))] | |
1650 | "" | |
1651 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1652 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1653 | |
1654 | (define_insn "*tbit_or_3" | |
1655 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1656 | (ior:BI (eq:BI (zero_extract:DI | |
1657 | (match_operand:DI 1 "gr_register_operand" "r") | |
1658 | (const_int 1) | |
1659 | (match_operand:DI 2 "const_int_operand" "n")) | |
1660 | (const_int 0)) | |
1661 | (match_operand:BI 3 "register_operand" "0")))] | |
1662 | "" | |
1663 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1664 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1665 | |
1666 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1667 | ||
1668 | (define_split | |
1669 | [(set (match_operand:BI 0 "register_operand" "") | |
1670 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1671 | (const_int 0)) | |
1672 | (match_operand:DI 3 "register_operand" "")) | |
1673 | (const_int 0)))] | |
1674 | "" | |
1675 | [(set (match_dup 0) | |
1676 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1677 | (match_dup 2)))] | |
1678 | "") | |
1679 | ||
1680 | (define_split | |
1681 | [(set (match_operand:BI 0 "register_operand" "") | |
1682 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1683 | (const_int 0)) | |
1684 | (match_operand:DI 3 "register_operand" "")) | |
1685 | (const_int 0)))] | |
1686 | "" | |
1687 | [(set (match_dup 0) | |
1688 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1689 | (match_dup 2))) | |
1690 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1691 | (clobber (scratch))])] | |
1692 | "") | |
1693 | ||
1694 | (define_split | |
1695 | [(set (match_operand:BI 0 "register_operand" "") | |
1696 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1697 | (const_int 0)) | |
1698 | (match_operand:DI 3 "register_operand" "")) | |
1699 | (const_int 0)))] | |
1700 | "" | |
1701 | [(set (match_dup 0) | |
1702 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1703 | (match_dup 2)))] | |
1704 | "") | |
1705 | ||
1706 | (define_split | |
1707 | [(set (match_operand:BI 0 "register_operand" "") | |
1708 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1709 | (const_int 0)) | |
1710 | (match_operand:DI 3 "register_operand" "")) | |
1711 | (const_int 0)))] | |
1712 | "" | |
1713 | [(set (match_dup 0) | |
1714 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1715 | (match_dup 2))) | |
1716 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1717 | (clobber (scratch))])] | |
1718 | "") | |
1719 | ||
1720 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1721 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1722 | ;; nothing bad happens to the comparisons in the meantime. | |
1723 | ;; | |
1724 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1725 | ;; that we're doing height reduction. | |
1726 | ; | |
1727 | ;(define_insn_and_split "" | |
1728 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1729 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1730 | ; [(match_operand 2 "" "") | |
1731 | ; (match_operand 3 "" "")]) | |
1732 | ; (match_operator:BI 4 "comparison_operator" | |
1733 | ; [(match_operand 5 "" "") | |
1734 | ; (match_operand 6 "" "")])) | |
1735 | ; (match_dup 0)))] | |
1736 | ; "flag_schedule_insns" | |
1737 | ; "#" | |
1738 | ; "" | |
1739 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1740 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1741 | ; "") | |
1742 | ; | |
1743 | ;(define_insn_and_split "" | |
1744 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1745 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1746 | ; [(match_operand 2 "" "") | |
1747 | ; (match_operand 3 "" "")]) | |
1748 | ; (match_operator:BI 4 "comparison_operator" | |
1749 | ; [(match_operand 5 "" "") | |
1750 | ; (match_operand 6 "" "")])) | |
1751 | ; (match_dup 0)))] | |
1752 | ; "flag_schedule_insns" | |
1753 | ; "#" | |
1754 | ; "" | |
1755 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1756 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1757 | ; "") | |
1758 | ; | |
1759 | ;(define_split | |
1760 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1761 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1762 | ; [(match_operand 2 "" "") | |
1763 | ; (match_operand 3 "" "")]) | |
1764 | ; (match_operand:BI 7 "register_operand" "")) | |
1765 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1766 | ; [(match_operand 5 "" "") | |
1767 | ; (match_operand 6 "" "")]) | |
1768 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1769 | ; "" | |
1770 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1771 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1772 | ; (match_dup 0)))] | |
1773 | ; "") | |
1774 | ; | |
1775 | ;(define_split | |
1776 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1777 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1778 | ; [(match_operand 2 "" "") | |
1779 | ; (match_operand 3 "" "")]) | |
1780 | ; (match_operand:BI 7 "register_operand" "")) | |
1781 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1782 | ; [(match_operand 5 "" "") | |
1783 | ; (match_operand 6 "" "")]) | |
1784 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1785 | ; "" | |
1786 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1787 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1788 | ; (match_dup 0)))] | |
1789 | ; "") | |
1790 | ||
1791 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1792 | ;; Note that we'll have already split the predicate copy, which | |
1793 | ;; is kind of a pain, but oh well. | |
1794 | ||
1795 | (define_peephole2 | |
1796 | [(set (match_operand:BI 0 "register_operand" "") | |
1797 | (match_operand:BI 1 "comparison_operator" "")) | |
1798 | (set (match_operand:CCI 2 "register_operand" "") | |
1799 | (match_operand:CCI 3 "register_operand" "")) | |
1800 | (set (match_operand:CCI 4 "register_operand" "") | |
1801 | (match_operand:CCI 5 "register_operand" "")) | |
1802 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1803 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1804 | "REGNO (operands[3]) == REGNO (operands[0]) |
1805 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1806 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1807 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1808 | [(set (match_dup 0) (match_dup 1)) | |
1809 | (set (match_dup 6) (match_dup 7))] | |
1810 | "operands[7] = copy_rtx (operands[1]);") | |
1811 | \f | |
1812 | ;; :::::::::::::::::::: | |
1813 | ;; :: | |
cf1f6ae3 RH |
1814 | ;; :: 16 bit Integer arithmetic |
1815 | ;; :: | |
1816 | ;; :::::::::::::::::::: | |
1817 | ||
1818 | (define_insn "mulhi3" | |
1819 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1820 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1821 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1822 | "" | |
2a7ffc85 | 1823 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1824 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1825 | |
1826 | \f | |
1827 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1828 | ;; :: |
1829 | ;; :: 32 bit Integer arithmetic | |
1830 | ;; :: | |
1831 | ;; :::::::::::::::::::: | |
1832 | ||
058557c4 | 1833 | (define_insn "addsi3" |
0551c32d RH |
1834 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1835 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1836 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1837 | "" |
1838 | "@ | |
1d5d7a21 RH |
1839 | add %0 = %1, %2 |
1840 | adds %0 = %2, %1 | |
1841 | addl %0 = %2, %1" | |
52e12ad0 | 1842 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1843 | |
1844 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1845 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1846 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1847 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1848 | (const_int 1)))] |
1849 | "" | |
1850 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1851 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1852 | |
5527bf14 | 1853 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1854 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1855 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1856 | (const_int 2)) |
1857 | (const_int 1)))] | |
1858 | "" | |
1859 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1860 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1861 | |
058557c4 | 1862 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1863 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1864 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1865 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1866 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1867 | "" |
058557c4 | 1868 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1869 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1870 | |
058557c4 | 1871 | (define_insn "subsi3" |
0551c32d RH |
1872 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1873 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1874 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1875 | "" |
1876 | "sub %0 = %1, %2" | |
52e12ad0 | 1877 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1878 | |
1879 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1880 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1881 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1882 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1883 | "" |
1884 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1885 | [(set_attr "itanium_class" "ialu")]) |
1886 | ||
1887 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1888 | |
058557c4 | 1889 | (define_insn "mulsi3" |
0551c32d | 1890 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1891 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1892 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1893 | "" |
aebf2462 | 1894 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1895 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1896 | |
655f2eb9 | 1897 | (define_insn "maddsi4" |
11a13704 RH |
1898 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1899 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1900 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1901 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1902 | "" | |
aebf2462 | 1903 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1904 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1905 | |
058557c4 | 1906 | (define_insn "negsi2" |
0551c32d RH |
1907 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1908 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1909 | "" |
1910 | "sub %0 = r0, %1" | |
52e12ad0 | 1911 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1912 | |
1913 | (define_expand "abssi2" | |
1914 | [(set (match_dup 2) | |
f2f90c63 | 1915 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1916 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1917 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1918 | (neg:SI (match_dup 1)) |
1919 | (match_dup 1)))] | |
c65ebc55 | 1920 | "" |
1d5d7a21 | 1921 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1922 | |
1923 | (define_expand "sminsi3" | |
1924 | [(set (match_dup 3) | |
f2f90c63 | 1925 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1926 | (match_operand:SI 2 "gr_register_operand" ""))) |
1927 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1928 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1929 | (match_dup 2) (match_dup 1)))] |
1930 | "" | |
1d5d7a21 | 1931 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1932 | |
1933 | (define_expand "smaxsi3" | |
1934 | [(set (match_dup 3) | |
f2f90c63 | 1935 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1936 | (match_operand:SI 2 "gr_register_operand" ""))) |
1937 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1938 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1939 | (match_dup 1) (match_dup 2)))] |
1940 | "" | |
1d5d7a21 | 1941 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1942 | |
1943 | (define_expand "uminsi3" | |
1944 | [(set (match_dup 3) | |
f2f90c63 | 1945 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1946 | (match_operand:SI 2 "gr_register_operand" ""))) |
1947 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1948 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1949 | (match_dup 2) (match_dup 1)))] |
1950 | "" | |
1d5d7a21 | 1951 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1952 | |
1953 | (define_expand "umaxsi3" | |
1954 | [(set (match_dup 3) | |
f2f90c63 | 1955 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1956 | (match_operand:SI 2 "gr_register_operand" ""))) |
1957 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1958 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1959 | (match_dup 1) (match_dup 2)))] |
1960 | "" | |
1d5d7a21 | 1961 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 1962 | |
655f2eb9 RH |
1963 | (define_expand "divsi3" |
1964 | [(set (match_operand:SI 0 "register_operand" "") | |
1965 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1966 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1967 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1968 | { |
1969 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1970 | ||
1971 | op0_tf = gen_reg_rtx (TFmode); | |
1972 | op0_di = gen_reg_rtx (DImode); | |
1973 | ||
1974 | if (CONSTANT_P (operands[1])) | |
1975 | operands[1] = force_reg (SImode, operands[1]); | |
1976 | op1_tf = gen_reg_rtx (TFmode); | |
1977 | expand_float (op1_tf, operands[1], 0); | |
1978 | ||
1979 | if (CONSTANT_P (operands[2])) | |
1980 | operands[2] = force_reg (SImode, operands[2]); | |
1981 | op2_tf = gen_reg_rtx (TFmode); | |
1982 | expand_float (op2_tf, operands[2], 0); | |
1983 | ||
1984 | /* 2^-34 */ | |
1985 | #if 0 | |
1986 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1987 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1988 | twon34 = force_reg (TFmode, twon34); | |
1989 | #else | |
1990 | twon34 = gen_reg_rtx (TFmode); | |
1991 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1992 | #endif | |
1993 | ||
1994 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1995 | ||
1996 | emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1997 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1998 | DONE; | |
1d5d7a21 | 1999 | }) |
655f2eb9 RH |
2000 | |
2001 | (define_expand "modsi3" | |
2002 | [(set (match_operand:SI 0 "register_operand" "") | |
2003 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2004 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2005 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2006 | { |
2007 | rtx op2_neg, op1_di, div; | |
2008 | ||
2009 | div = gen_reg_rtx (SImode); | |
2010 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2011 | ||
2012 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2013 | ||
2014 | /* This is a trick to get us to reuse the value that we're sure to | |
2015 | have already copied to the FP regs. */ | |
2016 | op1_di = gen_reg_rtx (DImode); | |
2017 | convert_move (op1_di, operands[1], 0); | |
2018 | ||
2019 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2020 | gen_lowpart (SImode, op1_di))); | |
2021 | DONE; | |
1d5d7a21 | 2022 | }) |
655f2eb9 RH |
2023 | |
2024 | (define_expand "udivsi3" | |
2025 | [(set (match_operand:SI 0 "register_operand" "") | |
2026 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2027 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2028 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2029 | { |
2030 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
2031 | ||
2032 | op0_tf = gen_reg_rtx (TFmode); | |
2033 | op0_di = gen_reg_rtx (DImode); | |
2034 | ||
2035 | if (CONSTANT_P (operands[1])) | |
2036 | operands[1] = force_reg (SImode, operands[1]); | |
2037 | op1_tf = gen_reg_rtx (TFmode); | |
2038 | expand_float (op1_tf, operands[1], 1); | |
2039 | ||
2040 | if (CONSTANT_P (operands[2])) | |
2041 | operands[2] = force_reg (SImode, operands[2]); | |
2042 | op2_tf = gen_reg_rtx (TFmode); | |
2043 | expand_float (op2_tf, operands[2], 1); | |
2044 | ||
2045 | /* 2^-34 */ | |
2046 | #if 0 | |
2047 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
2048 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
2049 | twon34 = force_reg (TFmode, twon34); | |
2050 | #else | |
2051 | twon34 = gen_reg_rtx (TFmode); | |
2052 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
2053 | #endif | |
2054 | ||
2055 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
2056 | ||
2057 | emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
2058 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
2059 | DONE; | |
1d5d7a21 | 2060 | }) |
655f2eb9 RH |
2061 | |
2062 | (define_expand "umodsi3" | |
2063 | [(set (match_operand:SI 0 "register_operand" "") | |
2064 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2065 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 2066 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2067 | { |
2068 | rtx op2_neg, op1_di, div; | |
2069 | ||
2070 | div = gen_reg_rtx (SImode); | |
2071 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2072 | ||
2073 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2074 | ||
2075 | /* This is a trick to get us to reuse the value that we're sure to | |
2076 | have already copied to the FP regs. */ | |
2077 | op1_di = gen_reg_rtx (DImode); | |
2078 | convert_move (op1_di, operands[1], 1); | |
2079 | ||
2080 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2081 | gen_lowpart (SImode, op1_di))); | |
2082 | DONE; | |
1d5d7a21 | 2083 | }) |
655f2eb9 RH |
2084 | |
2085 | (define_insn_and_split "divsi3_internal" | |
2086 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2087 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2088 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2089 | (clobber (match_scratch:TF 4 "=&f")) | |
2090 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2091 | (clobber (match_scratch:BI 6 "=c")) |
655f2eb9 | 2092 | (use (match_operand:TF 3 "fr_register_operand" "f"))] |
23c108af | 2093 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2094 | "#" |
2095 | "&& reload_completed" | |
2096 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2097 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2098 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2099 | (use (const_int 1))]) |
2100 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2101 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2102 | (use (const_int 1))])) | |
2103 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2104 | (parallel [(set (match_dup 5) | |
2105 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2106 | (match_dup 7))) | |
2107 | (use (const_int 1))])) | |
2108 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2109 | (parallel [(set (match_dup 4) | |
2110 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2111 | (match_dup 4))) | |
2112 | (use (const_int 1))])) | |
2113 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2114 | (parallel [(set (match_dup 5) | |
2115 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
2116 | (match_dup 3))) | |
2117 | (use (const_int 1))])) | |
2118 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2119 | (parallel [(set (match_dup 0) | |
2120 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2121 | (match_dup 4))) | |
2122 | (use (const_int 1))])) | |
2123 | ] | |
2124 | "operands[7] = CONST1_RTX (TFmode);" | |
2125 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2126 | \f |
2127 | ;; :::::::::::::::::::: | |
2128 | ;; :: | |
2129 | ;; :: 64 bit Integer arithmetic | |
2130 | ;; :: | |
2131 | ;; :::::::::::::::::::: | |
2132 | ||
2133 | (define_insn "adddi3" | |
0551c32d RH |
2134 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2135 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2136 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2137 | "" |
2138 | "@ | |
1d5d7a21 RH |
2139 | add %0 = %1, %2 |
2140 | adds %0 = %2, %1 | |
2141 | addl %0 = %2, %1" | |
52e12ad0 | 2142 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2143 | |
2144 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2145 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2146 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2147 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2148 | (const_int 1)))] |
2149 | "" | |
2150 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2151 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2152 | |
5527bf14 RH |
2153 | ;; This has some of the same problems as shladd. We let the shladd |
2154 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2155 | ;; a register, but not more ugliness here. | |
2156 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2157 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2158 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2159 | (const_int 2)) |
2160 | (const_int 1)))] | |
2161 | "" | |
2162 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2163 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2164 | |
c65ebc55 | 2165 | (define_insn "subdi3" |
0551c32d RH |
2166 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2167 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2168 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2169 | "" |
2170 | "sub %0 = %1, %2" | |
52e12ad0 | 2171 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2172 | |
2173 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2174 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2175 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2176 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2177 | "" |
2178 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2179 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2180 | |
cee58bc0 RH |
2181 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2182 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2183 | (define_insn "muldi3" |
0551c32d | 2184 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2185 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2186 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2187 | "" |
aebf2462 | 2188 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2189 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2190 | |
2191 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2192 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2193 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2194 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2195 | ;; here so that it will be present just in case register elimination gives us | |
2196 | ;; the funny result. | |
2197 | ||
2198 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2199 | ||
2200 | ;; ??? Maybe we should change how adds are canonicalized. | |
2201 | ||
655f2eb9 | 2202 | (define_insn "madddi4" |
0551c32d | 2203 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2204 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2205 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2206 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2207 | (clobber (match_scratch:DI 4 "=X"))] |
2208 | "" | |
aebf2462 | 2209 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2210 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2211 | |
2212 | ;; This can be created by register elimination if operand3 of shladd is an | |
2213 | ;; eliminable register or has reg_equiv_constant set. | |
2214 | ||
2215 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2216 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2217 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2218 | ;; incorrectly. |
2219 | ||
655f2eb9 | 2220 | (define_insn "*madddi4_elim" |
c65ebc55 | 2221 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2222 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2223 | (match_operand:DI 2 "register_operand" "f")) | |
2224 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2225 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2226 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2227 | "reload_in_progress" |
2228 | "#" | |
52e12ad0 | 2229 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2230 | |
c65ebc55 JW |
2231 | (define_split |
2232 | [(set (match_operand:DI 0 "register_operand" "") | |
2233 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2234 | (match_operand:DI 2 "register_operand" "")) | |
2235 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2236 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2237 | (clobber (match_scratch:DI 5 ""))] |
2238 | "reload_completed" | |
2239 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2240 | (match_dup 3))) | |
2241 | (clobber (match_dup 0))]) | |
c65ebc55 | 2242 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2243 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2244 | "") | |
2245 | ||
2246 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2247 | ;; to generate them. | |
2248 | ||
2249 | (define_insn "smuldi3_highpart" | |
0551c32d | 2250 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2251 | (truncate:DI |
2252 | (lshiftrt:TI | |
0551c32d RH |
2253 | (mult:TI (sign_extend:TI |
2254 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2255 | (sign_extend:TI | |
2256 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2257 | (const_int 64))))] |
2258 | "" | |
aebf2462 | 2259 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2260 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2261 | |
2262 | (define_insn "umuldi3_highpart" | |
0551c32d | 2263 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2264 | (truncate:DI |
2265 | (lshiftrt:TI | |
0551c32d RH |
2266 | (mult:TI (zero_extend:TI |
2267 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2268 | (zero_extend:TI | |
2269 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2270 | (const_int 64))))] |
2271 | "" | |
aebf2462 | 2272 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2273 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2274 | |
2275 | (define_insn "negdi2" | |
0551c32d RH |
2276 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2277 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2278 | "" |
2279 | "sub %0 = r0, %1" | |
52e12ad0 | 2280 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2281 | |
2282 | (define_expand "absdi2" | |
2283 | [(set (match_dup 2) | |
f2f90c63 | 2284 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2285 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2286 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2287 | (neg:DI (match_dup 1)) |
2288 | (match_dup 1)))] | |
c65ebc55 | 2289 | "" |
1d5d7a21 | 2290 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2291 | |
2292 | (define_expand "smindi3" | |
2293 | [(set (match_dup 3) | |
f2f90c63 | 2294 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2295 | (match_operand:DI 2 "gr_register_operand" ""))) |
2296 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2297 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2298 | (match_dup 2) (match_dup 1)))] |
2299 | "" | |
1d5d7a21 | 2300 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2301 | |
2302 | (define_expand "smaxdi3" | |
2303 | [(set (match_dup 3) | |
f2f90c63 | 2304 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2305 | (match_operand:DI 2 "gr_register_operand" ""))) |
2306 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2307 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2308 | (match_dup 1) (match_dup 2)))] |
2309 | "" | |
1d5d7a21 | 2310 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2311 | |
2312 | (define_expand "umindi3" | |
2313 | [(set (match_dup 3) | |
f2f90c63 | 2314 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2315 | (match_operand:DI 2 "gr_register_operand" ""))) |
2316 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2317 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2318 | (match_dup 2) (match_dup 1)))] |
2319 | "" | |
1d5d7a21 | 2320 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2321 | |
2322 | (define_expand "umaxdi3" | |
2323 | [(set (match_dup 3) | |
f2f90c63 | 2324 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2325 | (match_operand:DI 2 "gr_register_operand" ""))) |
2326 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2327 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2328 | (match_dup 1) (match_dup 2)))] |
2329 | "" | |
1d5d7a21 | 2330 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2331 | |
2332 | (define_expand "ffsdi2" | |
2333 | [(set (match_dup 6) | |
f2f90c63 | 2334 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2335 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2336 | (set (match_dup 5) (const_int 0)) | |
2337 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
086c0f96 | 2338 | (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_POPCNT)) |
0551c32d | 2339 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2340 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2341 | (match_dup 5) (match_dup 4)))] |
2342 | "" | |
c65ebc55 JW |
2343 | { |
2344 | operands[2] = gen_reg_rtx (DImode); | |
2345 | operands[3] = gen_reg_rtx (DImode); | |
2346 | operands[4] = gen_reg_rtx (DImode); | |
2347 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2348 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2349 | }) |
c65ebc55 JW |
2350 | |
2351 | (define_insn "*popcnt" | |
0551c32d | 2352 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
086c0f96 RH |
2353 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] |
2354 | UNSPEC_POPCNT))] | |
c65ebc55 JW |
2355 | "" |
2356 | "popcnt %0 = %1" | |
52e12ad0 | 2357 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2358 | |
655f2eb9 RH |
2359 | (define_expand "divdi3" |
2360 | [(set (match_operand:DI 0 "register_operand" "") | |
2361 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2362 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2363 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2364 | { |
2365 | rtx op1_tf, op2_tf, op0_tf; | |
2366 | ||
2367 | op0_tf = gen_reg_rtx (TFmode); | |
2368 | ||
2369 | if (CONSTANT_P (operands[1])) | |
2370 | operands[1] = force_reg (DImode, operands[1]); | |
2371 | op1_tf = gen_reg_rtx (TFmode); | |
2372 | expand_float (op1_tf, operands[1], 0); | |
2373 | ||
2374 | if (CONSTANT_P (operands[2])) | |
2375 | operands[2] = force_reg (DImode, operands[2]); | |
2376 | op2_tf = gen_reg_rtx (TFmode); | |
2377 | expand_float (op2_tf, operands[2], 0); | |
2378 | ||
2379 | if (TARGET_INLINE_DIV_LAT) | |
2380 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2381 | else | |
2382 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2383 | ||
2384 | emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2385 | DONE; | |
1d5d7a21 | 2386 | }) |
655f2eb9 RH |
2387 | |
2388 | (define_expand "moddi3" | |
2389 | [(set (match_operand:DI 0 "register_operand" "") | |
2390 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2391 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2392 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2393 | { |
2394 | rtx op2_neg, div; | |
2395 | ||
2396 | div = gen_reg_rtx (DImode); | |
2397 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2398 | ||
2399 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2400 | ||
2401 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2402 | DONE; | |
1d5d7a21 | 2403 | }) |
655f2eb9 RH |
2404 | |
2405 | (define_expand "udivdi3" | |
2406 | [(set (match_operand:DI 0 "register_operand" "") | |
2407 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2408 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2409 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2410 | { |
2411 | rtx op1_tf, op2_tf, op0_tf; | |
2412 | ||
2413 | op0_tf = gen_reg_rtx (TFmode); | |
2414 | ||
2415 | if (CONSTANT_P (operands[1])) | |
2416 | operands[1] = force_reg (DImode, operands[1]); | |
2417 | op1_tf = gen_reg_rtx (TFmode); | |
2418 | expand_float (op1_tf, operands[1], 1); | |
2419 | ||
2420 | if (CONSTANT_P (operands[2])) | |
2421 | operands[2] = force_reg (DImode, operands[2]); | |
2422 | op2_tf = gen_reg_rtx (TFmode); | |
2423 | expand_float (op2_tf, operands[2], 1); | |
2424 | ||
2425 | if (TARGET_INLINE_DIV_LAT) | |
2426 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2427 | else | |
2428 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2429 | ||
2430 | emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2431 | DONE; | |
1d5d7a21 | 2432 | }) |
655f2eb9 RH |
2433 | |
2434 | (define_expand "umoddi3" | |
2435 | [(set (match_operand:DI 0 "register_operand" "") | |
2436 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2437 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2438 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2439 | { |
2440 | rtx op2_neg, div; | |
2441 | ||
2442 | div = gen_reg_rtx (DImode); | |
2443 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2444 | ||
2445 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2446 | ||
2447 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2448 | DONE; | |
1d5d7a21 | 2449 | }) |
655f2eb9 RH |
2450 | |
2451 | (define_insn_and_split "divdi3_internal_lat" | |
2452 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2453 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2454 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2455 | (clobber (match_scratch:TF 3 "=&f")) | |
2456 | (clobber (match_scratch:TF 4 "=&f")) | |
2457 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2458 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2459 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
655f2eb9 RH |
2460 | "#" |
2461 | "&& reload_completed" | |
2462 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2463 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2464 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2465 | (use (const_int 1))]) |
2466 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2467 | (parallel [(set (match_dup 3) | |
2468 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2469 | (match_dup 7))) | |
2470 | (use (const_int 1))])) | |
2471 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2472 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2473 | (use (const_int 1))])) | |
2474 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2475 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
2476 | (use (const_int 1))])) | |
2477 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2478 | (parallel [(set (match_dup 4) | |
2479 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
2480 | (match_dup 4))) | |
2481 | (use (const_int 1))])) | |
2482 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2483 | (parallel [(set (match_dup 0) | |
2484 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2485 | (match_dup 0))) | |
2486 | (use (const_int 1))])) | |
2487 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2488 | (parallel [(set (match_dup 3) | |
2489 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2490 | (match_dup 4))) | |
2491 | (use (const_int 1))])) | |
2492 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2493 | (parallel [(set (match_dup 0) | |
2494 | (plus:TF (mult:TF (match_dup 5) (match_dup 0)) | |
2495 | (match_dup 0))) | |
2496 | (use (const_int 1))])) | |
2497 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2498 | (parallel [(set (match_dup 4) | |
2499 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2500 | (match_dup 1))) | |
2501 | (use (const_int 1))])) | |
2502 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2503 | (parallel [(set (match_dup 0) | |
2504 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2505 | (match_dup 3))) | |
2506 | (use (const_int 1))])) | |
2507 | ] | |
2508 | "operands[7] = CONST1_RTX (TFmode);" | |
2509 | [(set_attr "predicable" "no")]) | |
2510 | ||
2511 | (define_insn_and_split "divdi3_internal_thr" | |
2512 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2513 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2514 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2515 | (clobber (match_scratch:TF 3 "=&f")) | |
2516 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2517 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2518 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
655f2eb9 RH |
2519 | "#" |
2520 | "&& reload_completed" | |
2521 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
2522 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2523 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2524 | (use (const_int 1))]) |
2525 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2526 | (parallel [(set (match_dup 3) | |
2527 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2528 | (match_dup 6))) | |
2529 | (use (const_int 1))])) | |
2530 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2531 | (parallel [(set (match_dup 0) | |
2532 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2533 | (match_dup 0))) | |
2534 | (use (const_int 1))])) | |
2535 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2536 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
2537 | (use (const_int 1))])) | |
2538 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2539 | (parallel [(set (match_dup 0) | |
2540 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2541 | (match_dup 0))) | |
2542 | (use (const_int 1))])) | |
2543 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2544 | (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1))) | |
2545 | (use (const_int 1))])) | |
2546 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2547 | (parallel [(set (match_dup 4) | |
2548 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2549 | (match_dup 1))) | |
2550 | (use (const_int 1))])) | |
2551 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2552 | (parallel [(set (match_dup 0) | |
2553 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2554 | (match_dup 3))) | |
2555 | (use (const_int 1))])) | |
2556 | ] | |
2557 | "operands[6] = CONST1_RTX (TFmode);" | |
2558 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2559 | \f |
2560 | ;; :::::::::::::::::::: | |
2561 | ;; :: | |
2562 | ;; :: 32 bit floating point arithmetic | |
2563 | ;; :: | |
2564 | ;; :::::::::::::::::::: | |
2565 | ||
2566 | (define_insn "addsf3" | |
0551c32d RH |
2567 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2568 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2569 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2570 | "" |
aebf2462 | 2571 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2572 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2573 | |
2574 | (define_insn "subsf3" | |
0551c32d RH |
2575 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2576 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2577 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2578 | "" |
aebf2462 | 2579 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2580 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2581 | |
2582 | (define_insn "mulsf3" | |
0551c32d RH |
2583 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2584 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2585 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2586 | "" |
aebf2462 | 2587 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2588 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2589 | |
2590 | (define_insn "abssf2" | |
0551c32d RH |
2591 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2592 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2593 | "" |
aebf2462 | 2594 | "fabs %0 = %1" |
52e12ad0 | 2595 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2596 | |
2597 | (define_insn "negsf2" | |
0551c32d RH |
2598 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2599 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2600 | "" |
aebf2462 | 2601 | "fneg %0 = %1" |
52e12ad0 | 2602 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2603 | |
2604 | (define_insn "*nabssf2" | |
0551c32d RH |
2605 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2606 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2607 | "" |
aebf2462 | 2608 | "fnegabs %0 = %1" |
52e12ad0 | 2609 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2610 | |
2611 | (define_insn "minsf3" | |
0551c32d RH |
2612 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2613 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2614 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2615 | "" |
aebf2462 | 2616 | "fmin %0 = %1, %F2" |
52e12ad0 | 2617 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2618 | |
2619 | (define_insn "maxsf3" | |
0551c32d RH |
2620 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2621 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2622 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2623 | "" |
aebf2462 | 2624 | "fmax %0 = %1, %F2" |
52e12ad0 | 2625 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2626 | |
655f2eb9 | 2627 | (define_insn "*maddsf4" |
0551c32d RH |
2628 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2629 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2630 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2631 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2632 | "" |
aebf2462 | 2633 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2634 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2635 | |
655f2eb9 | 2636 | (define_insn "*msubsf4" |
0551c32d RH |
2637 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2638 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2639 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2640 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2641 | "" |
aebf2462 | 2642 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2643 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2644 | |
2645 | (define_insn "*nmulsf3" | |
0551c32d RH |
2646 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2647 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2648 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2649 | "" |
aebf2462 | 2650 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2651 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2652 | |
2653 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? | |
2654 | ||
655f2eb9 | 2655 | (define_insn "*nmaddsf4" |
0551c32d | 2656 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
26102535 RH |
2657 | (plus:SF (neg:SF (mult:SF |
2658 | (match_operand:SF 1 "fr_register_operand" "f") | |
2659 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
0551c32d | 2660 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2661 | "" |
aebf2462 | 2662 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2663 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2664 | |
26102535 RH |
2665 | (define_expand "divsf3" |
2666 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2667 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2668 | (match_operand:SF 2 "fr_register_operand" "")))] | |
23c108af | 2669 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2670 | { |
2671 | rtx insn; | |
2672 | if (TARGET_INLINE_DIV_LAT) | |
2673 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); | |
2674 | else | |
2675 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2676 | emit_insn (insn); | |
2677 | DONE; | |
1d5d7a21 | 2678 | }) |
26102535 RH |
2679 | |
2680 | (define_insn_and_split "divsf3_internal_lat" | |
2681 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2682 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2683 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2684 | (clobber (match_scratch:TF 3 "=&f")) | |
2685 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2686 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2687 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2688 | "#" |
2689 | "&& reload_completed" | |
2690 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
2691 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2692 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
2693 | (use (const_int 1))]) |
2694 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2695 | (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) | |
2696 | (use (const_int 1))])) | |
2697 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2698 | (parallel [(set (match_dup 4) | |
2699 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2700 | (match_dup 10))) | |
2701 | (use (const_int 1))])) | |
2702 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2703 | (parallel [(set (match_dup 3) | |
2704 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2705 | (match_dup 3))) | |
2706 | (use (const_int 1))])) | |
2707 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2708 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2709 | (use (const_int 1))])) | |
2710 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2711 | (parallel [(set (match_dup 3) | |
2712 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2713 | (match_dup 3))) | |
2714 | (use (const_int 1))])) | |
2715 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2716 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2717 | (use (const_int 1))])) | |
2718 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2719 | (parallel [(set (match_dup 9) | |
2720 | (float_truncate:DF | |
2721 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2722 | (match_dup 3)))) | |
2723 | (use (const_int 1))])) | |
2724 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2725 | (set (match_dup 0) | |
2726 | (float_truncate:SF (match_dup 6)))) | |
2727 | ] | |
1d5d7a21 RH |
2728 | { |
2729 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2730 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2731 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2732 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); | |
2733 | operands[10] = CONST1_RTX (TFmode); | |
2734 | } | |
26102535 RH |
2735 | [(set_attr "predicable" "no")]) |
2736 | ||
2737 | (define_insn_and_split "divsf3_internal_thr" | |
2738 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2739 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2740 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2741 | (clobber (match_scratch:TF 3 "=&f")) | |
2742 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2743 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2744 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2745 | "#" |
2746 | "&& reload_completed" | |
2747 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
2748 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2749 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
2750 | (use (const_int 1))]) |
2751 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2752 | (parallel [(set (match_dup 3) | |
2753 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2754 | (match_dup 10))) | |
2755 | (use (const_int 1))])) | |
2756 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2757 | (parallel [(set (match_dup 3) | |
2758 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
2759 | (match_dup 3))) | |
2760 | (use (const_int 1))])) | |
2761 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2762 | (parallel [(set (match_dup 6) | |
2763 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
2764 | (match_dup 6))) | |
2765 | (use (const_int 1))])) | |
2766 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2767 | (parallel [(set (match_dup 9) | |
2768 | (float_truncate:SF | |
2769 | (mult:TF (match_dup 7) (match_dup 6)))) | |
2770 | (use (const_int 1))])) | |
2771 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2772 | (parallel [(set (match_dup 4) | |
2773 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3))) | |
2774 | (match_dup 7))) | |
2775 | (use (const_int 1))])) | |
2776 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2777 | (set (match_dup 0) | |
2778 | (float_truncate:SF | |
2779 | (plus:TF (mult:TF (match_dup 4) (match_dup 6)) | |
2780 | (match_dup 3))))) | |
2781 | ] | |
1d5d7a21 RH |
2782 | { |
2783 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2784 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2785 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2786 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); | |
2787 | operands[10] = CONST1_RTX (TFmode); | |
2788 | } | |
26102535 | 2789 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2790 | \f |
2791 | ;; :::::::::::::::::::: | |
2792 | ;; :: | |
2793 | ;; :: 64 bit floating point arithmetic | |
2794 | ;; :: | |
2795 | ;; :::::::::::::::::::: | |
2796 | ||
2797 | (define_insn "adddf3" | |
0551c32d RH |
2798 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2799 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2800 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2801 | "" |
aebf2462 | 2802 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2803 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2804 | |
26102535 RH |
2805 | (define_insn "*adddf3_trunc" |
2806 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2807 | (float_truncate:SF | |
2808 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2809 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2810 | "" | |
aebf2462 | 2811 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2812 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2813 | |
c65ebc55 | 2814 | (define_insn "subdf3" |
0551c32d RH |
2815 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2816 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2817 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2818 | "" |
aebf2462 | 2819 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2820 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2821 | |
26102535 RH |
2822 | (define_insn "*subdf3_trunc" |
2823 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2824 | (float_truncate:SF | |
2825 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2826 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2827 | "" | |
aebf2462 | 2828 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2829 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2830 | |
c65ebc55 | 2831 | (define_insn "muldf3" |
0551c32d RH |
2832 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2833 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2834 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2835 | "" |
aebf2462 | 2836 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2837 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2838 | |
26102535 RH |
2839 | (define_insn "*muldf3_trunc" |
2840 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2841 | (float_truncate:SF | |
2842 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2843 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2844 | "" | |
aebf2462 | 2845 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2846 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2847 | |
c65ebc55 | 2848 | (define_insn "absdf2" |
0551c32d RH |
2849 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2850 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2851 | "" |
aebf2462 | 2852 | "fabs %0 = %1" |
52e12ad0 | 2853 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2854 | |
2855 | (define_insn "negdf2" | |
0551c32d RH |
2856 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2857 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2858 | "" |
aebf2462 | 2859 | "fneg %0 = %1" |
52e12ad0 | 2860 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2861 | |
2862 | (define_insn "*nabsdf2" | |
0551c32d RH |
2863 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2864 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2865 | "" |
aebf2462 | 2866 | "fnegabs %0 = %1" |
52e12ad0 | 2867 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2868 | |
2869 | (define_insn "mindf3" | |
0551c32d RH |
2870 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2871 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2872 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2873 | "" |
aebf2462 | 2874 | "fmin %0 = %1, %F2" |
52e12ad0 | 2875 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2876 | |
2877 | (define_insn "maxdf3" | |
0551c32d RH |
2878 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2879 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2880 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2881 | "" |
aebf2462 | 2882 | "fmax %0 = %1, %F2" |
52e12ad0 | 2883 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2884 | |
655f2eb9 | 2885 | (define_insn "*madddf4" |
0551c32d RH |
2886 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2887 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2888 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2889 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2890 | "" |
aebf2462 | 2891 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 2892 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2893 | |
26102535 RH |
2894 | (define_insn "*madddf4_trunc" |
2895 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2896 | (float_truncate:SF | |
2897 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2898 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2899 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2900 | "" | |
aebf2462 | 2901 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2902 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2903 | |
655f2eb9 | 2904 | (define_insn "*msubdf4" |
0551c32d RH |
2905 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2906 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2907 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2908 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2909 | "" |
aebf2462 | 2910 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 2911 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2912 | |
26102535 RH |
2913 | (define_insn "*msubdf4_trunc" |
2914 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2915 | (float_truncate:SF | |
2916 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2917 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2918 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2919 | "" | |
aebf2462 | 2920 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2921 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2922 | |
c65ebc55 | 2923 | (define_insn "*nmuldf3" |
0551c32d RH |
2924 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2925 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2926 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2927 | "" |
aebf2462 | 2928 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 2929 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2930 | |
26102535 RH |
2931 | (define_insn "*nmuldf3_trunc" |
2932 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2933 | (float_truncate:SF | |
2934 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2935 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
2936 | "" | |
aebf2462 | 2937 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2938 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2939 | |
c65ebc55 JW |
2940 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
2941 | ||
655f2eb9 | 2942 | (define_insn "*nmadddf4" |
0551c32d | 2943 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
26102535 RH |
2944 | (plus:DF (neg:DF (mult:DF |
2945 | (match_operand:DF 1 "fr_register_operand" "f") | |
2946 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
0551c32d | 2947 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2948 | "" |
aebf2462 | 2949 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 2950 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2951 | |
2952 | (define_insn "*nmadddf4_alts" | |
2953 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2954 | (plus:DF (neg:DF (mult:DF | |
2955 | (match_operand:DF 1 "fr_register_operand" "f") | |
2956 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2957 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))) | |
2958 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2959 | "" | |
aebf2462 | 2960 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 2961 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2962 | |
2963 | (define_insn "*nmadddf4_trunc" | |
2964 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2965 | (float_truncate:SF | |
2966 | (plus:DF (neg:DF (mult:DF | |
2967 | (match_operand:DF 1 "fr_register_operand" "f") | |
2968 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2969 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2970 | "" | |
aebf2462 | 2971 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2972 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2973 | |
2974 | (define_expand "divdf3" | |
2975 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
2976 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
2977 | (match_operand:DF 2 "fr_register_operand" "")))] | |
23c108af | 2978 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2979 | { |
2980 | rtx insn; | |
2981 | if (TARGET_INLINE_DIV_LAT) | |
2982 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); | |
2983 | else | |
2984 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
2985 | emit_insn (insn); | |
2986 | DONE; | |
1d5d7a21 | 2987 | }) |
26102535 RH |
2988 | |
2989 | (define_insn_and_split "divdf3_internal_lat" | |
2990 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2991 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2992 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2993 | (clobber (match_scratch:TF 3 "=&f")) | |
2994 | (clobber (match_scratch:TF 4 "=&f")) | |
2995 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2996 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2997 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2998 | "#" |
2999 | "&& reload_completed" | |
3000 | [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) | |
086c0f96 RH |
3001 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3002 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3003 | (use (const_int 1))]) |
3004 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3005 | (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) | |
3006 | (use (const_int 1))])) | |
3007 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3008 | (parallel [(set (match_dup 4) | |
3009 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7))) | |
3010 | (match_dup 12))) | |
3011 | (use (const_int 1))])) | |
3012 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3013 | (parallel [(set (match_dup 3) | |
3014 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
3015 | (match_dup 3))) | |
3016 | (use (const_int 1))])) | |
3017 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3018 | (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4))) | |
3019 | (use (const_int 1))])) | |
3020 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3021 | (parallel [(set (match_dup 7) | |
3022 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
3023 | (match_dup 7))) | |
3024 | (use (const_int 1))])) | |
3025 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3026 | (parallel [(set (match_dup 3) | |
3027 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3028 | (match_dup 3))) | |
3029 | (use (const_int 1))])) | |
3030 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3031 | (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5))) | |
3032 | (use (const_int 1))])) | |
3033 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3034 | (parallel [(set (match_dup 7) | |
3035 | (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
3036 | (match_dup 7))) | |
3037 | (use (const_int 1))])) | |
3038 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3039 | (parallel [(set (match_dup 10) | |
3040 | (float_truncate:DF | |
3041 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
3042 | (match_dup 3)))) | |
3043 | (use (const_int 1))])) | |
3044 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3045 | (parallel [(set (match_dup 7) | |
3046 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
3047 | (match_dup 7))) | |
3048 | (use (const_int 1))])) | |
3049 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3050 | (parallel [(set (match_dup 11) | |
3051 | (float_truncate:DF | |
3052 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3))) | |
3053 | (match_dup 8)))) | |
3054 | (use (const_int 1))])) | |
3055 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3056 | (set (match_dup 0) | |
3057 | (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
3058 | (match_dup 3))))) | |
3059 | ] | |
1d5d7a21 RH |
3060 | { |
3061 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3062 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3063 | operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3064 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3065 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
3066 | operands[12] = CONST1_RTX (TFmode); | |
3067 | } | |
26102535 RH |
3068 | [(set_attr "predicable" "no")]) |
3069 | ||
3070 | (define_insn_and_split "divdf3_internal_thr" | |
3071 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3072 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3073 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
3074 | (clobber (match_scratch:TF 3 "=&f")) | |
3075 | (clobber (match_scratch:DF 4 "=f")) | |
f2f90c63 | 3076 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3077 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3078 | "#" |
3079 | "&& reload_completed" | |
3080 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
086c0f96 RH |
3081 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3082 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3083 | (use (const_int 1))]) |
3084 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3085 | (parallel [(set (match_dup 3) | |
3086 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
3087 | (match_dup 10))) | |
3088 | (use (const_int 1))])) | |
3089 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3090 | (parallel [(set (match_dup 6) | |
3091 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3092 | (match_dup 6))) | |
3093 | (use (const_int 1))])) | |
3094 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3095 | (parallel [(set (match_dup 3) | |
3096 | (mult:TF (match_dup 3) (match_dup 3))) | |
3097 | (use (const_int 1))])) | |
3098 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3099 | (parallel [(set (match_dup 6) | |
3100 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3101 | (match_dup 6))) | |
3102 | (use (const_int 1))])) | |
3103 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3104 | (parallel [(set (match_dup 3) | |
3105 | (mult:TF (match_dup 3) (match_dup 3))) | |
3106 | (use (const_int 1))])) | |
3107 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3108 | (parallel [(set (match_dup 6) | |
3109 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3110 | (match_dup 6))) | |
3111 | (use (const_int 1))])) | |
3112 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3113 | (parallel [(set (match_dup 9) | |
3114 | (float_truncate:DF | |
3115 | (mult:TF (match_dup 7) (match_dup 3)))) | |
3116 | (use (const_int 1))])) | |
3117 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3118 | (parallel [(set (match_dup 4) | |
3119 | (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9))) | |
3120 | (match_dup 1))) | |
3121 | (use (const_int 1))])) | |
3122 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3123 | (set (match_dup 0) | |
3124 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3125 | (match_dup 9)))) | |
3126 | ] | |
1d5d7a21 RH |
3127 | { |
3128 | operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3129 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3130 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3131 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3132 | operands[10] = CONST1_RTX (TFmode); | |
3133 | } | |
26102535 | 3134 | [(set_attr "predicable" "no")]) |
3f622353 RH |
3135 | \f |
3136 | ;; :::::::::::::::::::: | |
3137 | ;; :: | |
3138 | ;; :: 80 bit floating point arithmetic | |
3139 | ;; :: | |
3140 | ;; :::::::::::::::::::: | |
3141 | ||
3142 | (define_insn "addtf3" | |
0551c32d | 3143 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3144 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3145 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3146 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3147 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3148 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3149 | |
26102535 RH |
3150 | (define_insn "*addtf3_truncsf" |
3151 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3152 | (float_truncate:SF | |
3153 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3154 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3155 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3156 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3157 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3158 | |
3159 | (define_insn "*addtf3_truncdf" | |
3160 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3161 | (float_truncate:DF | |
3162 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3163 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3164 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3165 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3166 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3167 | |
3f622353 | 3168 | (define_insn "subtf3" |
0551c32d | 3169 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3170 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3171 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3172 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3173 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3174 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3175 | |
26102535 RH |
3176 | (define_insn "*subtf3_truncsf" |
3177 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3178 | (float_truncate:SF | |
3179 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3180 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3181 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3182 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3183 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3184 | |
3185 | (define_insn "*subtf3_truncdf" | |
3186 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3187 | (float_truncate:DF | |
3188 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3189 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3190 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3191 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3192 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3193 | |
3f622353 | 3194 | (define_insn "multf3" |
0551c32d | 3195 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3196 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3197 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3198 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3199 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3200 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3201 | |
26102535 RH |
3202 | (define_insn "*multf3_truncsf" |
3203 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3204 | (float_truncate:SF | |
3205 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3206 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3207 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3208 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3209 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3210 | |
3211 | (define_insn "*multf3_truncdf" | |
3212 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3213 | (float_truncate:DF | |
3214 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3215 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3216 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3217 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3218 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3219 | |
655f2eb9 RH |
3220 | (define_insn "*multf3_alts" |
3221 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3222 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3223 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3224 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3225 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3226 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3227 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3228 | |
26102535 RH |
3229 | (define_insn "*multf3_truncsf_alts" |
3230 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3231 | (float_truncate:SF | |
3232 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3233 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3234 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3235 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3236 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3237 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3238 | |
3239 | (define_insn "*multf3_truncdf_alts" | |
3240 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3241 | (float_truncate:DF | |
3242 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3243 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3244 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3245 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3246 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3247 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3248 | |
3f622353 | 3249 | (define_insn "abstf2" |
0551c32d | 3250 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3251 | (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3252 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3253 | "fabs %0 = %F1" |
52e12ad0 | 3254 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3255 | |
3256 | (define_insn "negtf2" | |
0551c32d | 3257 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3258 | (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3259 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3260 | "fneg %0 = %F1" |
52e12ad0 | 3261 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3262 | |
3263 | (define_insn "*nabstf2" | |
0551c32d | 3264 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3265 | (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))] |
23c108af | 3266 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3267 | "fnegabs %0 = %F1" |
52e12ad0 | 3268 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3269 | |
3270 | (define_insn "mintf3" | |
0551c32d | 3271 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3272 | (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3273 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3274 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3275 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3276 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3277 | |
3278 | (define_insn "maxtf3" | |
0551c32d | 3279 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3280 | (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3281 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3282 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3283 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3284 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3285 | |
655f2eb9 | 3286 | (define_insn "*maddtf4" |
0551c32d | 3287 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3288 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3289 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3290 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3291 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3292 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3293 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3294 | |
26102535 RH |
3295 | (define_insn "*maddtf4_truncsf" |
3296 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3297 | (float_truncate:SF | |
3298 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3299 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3300 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3301 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3302 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3303 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3304 | |
3305 | (define_insn "*maddtf4_truncdf" | |
3306 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3307 | (float_truncate:DF | |
3308 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3309 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3310 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3311 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3312 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3313 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3314 | |
655f2eb9 RH |
3315 | (define_insn "*maddtf4_alts" |
3316 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3317 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3318 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3319 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3320 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3321 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3322 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3323 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3324 | |
26102535 RH |
3325 | (define_insn "*maddtf4_alts_truncdf" |
3326 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3327 | (float_truncate:DF | |
3328 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3329 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3330 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3331 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3332 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3333 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3334 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3335 | |
655f2eb9 | 3336 | (define_insn "*msubtf4" |
0551c32d | 3337 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3338 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3339 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3340 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3341 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3342 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3343 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3344 | |
26102535 RH |
3345 | (define_insn "*msubtf4_truncsf" |
3346 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3347 | (float_truncate:SF | |
3348 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3349 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3350 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3351 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3352 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3353 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3354 | |
3355 | (define_insn "*msubtf4_truncdf" | |
3356 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3357 | (float_truncate:DF | |
3358 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3359 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3360 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3361 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3362 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3363 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3364 | |
3f622353 | 3365 | (define_insn "*nmultf3" |
0551c32d | 3366 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3367 | (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3368 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3369 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3370 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3371 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3372 | |
26102535 RH |
3373 | (define_insn "*nmultf3_truncsf" |
3374 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3375 | (float_truncate:SF | |
3376 | (neg:TF (mult:TF | |
3377 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3378 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3379 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3380 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3381 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3382 | |
3383 | (define_insn "*nmultf3_truncdf" | |
3384 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3385 | (float_truncate:DF | |
3386 | (neg:TF (mult:TF | |
3387 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3388 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3389 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3390 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3391 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3392 | |
3f622353 RH |
3393 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
3394 | ||
655f2eb9 | 3395 | (define_insn "*nmaddtf4" |
0551c32d | 3396 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3397 | (plus:TF (neg:TF (mult:TF |
3398 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3399 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3400 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3401 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3402 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3403 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3404 | |
26102535 RH |
3405 | (define_insn "*nmaddtf4_truncsf" |
3406 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3407 | (float_truncate:SF | |
3408 | (plus:TF (neg:TF (mult:TF | |
3409 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3410 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3411 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3412 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3413 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3414 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3415 | |
3416 | (define_insn "*nmaddtf4_truncdf" | |
3417 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3418 | (float_truncate:DF | |
3419 | (plus:TF (neg:TF (mult:TF | |
3420 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3421 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3422 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3423 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3424 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3425 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3426 | |
655f2eb9 RH |
3427 | (define_insn "*nmaddtf4_alts" |
3428 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3429 | (plus:TF (neg:TF (mult:TF | |
3430 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3431 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3432 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3433 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3434 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3435 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3436 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3437 | |
26102535 RH |
3438 | (define_insn "*nmaddtf4_truncdf_alts" |
3439 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3440 | (float_truncate:DF | |
3441 | (plus:TF (neg:TF | |
3442 | (mult:TF | |
3443 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3444 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3445 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3446 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3447 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3448 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3449 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3450 | |
3451 | (define_expand "divtf3" | |
3452 | [(set (match_operand:TF 0 "fr_register_operand" "") | |
3453 | (div:TF (match_operand:TF 1 "fr_register_operand" "") | |
3454 | (match_operand:TF 2 "fr_register_operand" "")))] | |
23c108af | 3455 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3456 | { |
3457 | rtx insn; | |
3458 | if (TARGET_INLINE_DIV_LAT) | |
3459 | insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]); | |
3460 | else | |
3461 | insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); | |
3462 | emit_insn (insn); | |
3463 | DONE; | |
1d5d7a21 | 3464 | }) |
26102535 RH |
3465 | |
3466 | (define_insn_and_split "divtf3_internal_lat" | |
3467 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3468 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3469 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3470 | (clobber (match_scratch:TF 3 "=&f")) | |
3471 | (clobber (match_scratch:TF 4 "=&f")) | |
3472 | (clobber (match_scratch:TF 5 "=&f")) | |
3473 | (clobber (match_scratch:TF 6 "=&f")) | |
f2f90c63 | 3474 | (clobber (match_scratch:BI 7 "=c"))] |
23c108af | 3475 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3476 | "#" |
3477 | "&& reload_completed" | |
3478 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
3479 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
3480 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3481 | (use (const_int 1))]) |
3482 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3483 | (parallel [(set (match_dup 3) | |
3484 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3485 | (match_dup 8))) | |
3486 | (use (const_int 1))])) | |
3487 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3488 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3489 | (use (const_int 1))])) | |
3490 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3491 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
3492 | (use (const_int 1))])) | |
3493 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3494 | (parallel [(set (match_dup 6) | |
3495 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
3496 | (match_dup 3))) | |
3497 | (use (const_int 1))])) | |
3498 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3499 | (parallel [(set (match_dup 3) | |
3500 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
3501 | (match_dup 3))) | |
3502 | (use (const_int 1))])) | |
3503 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3504 | (parallel [(set (match_dup 5) | |
3505 | (plus:TF (mult:TF (match_dup 6) (match_dup 0)) | |
3506 | (match_dup 0))) | |
3507 | (use (const_int 1))])) | |
3508 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3509 | (parallel [(set (match_dup 0) | |
3510 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3511 | (match_dup 0))) | |
3512 | (use (const_int 1))])) | |
3513 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3514 | (parallel [(set (match_dup 4) | |
3515 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3516 | (match_dup 1))) | |
3517 | (use (const_int 1))])) | |
3518 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3519 | (parallel [(set (match_dup 3) | |
3520 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3521 | (match_dup 4))) | |
3522 | (use (const_int 1))])) | |
3523 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3524 | (parallel [(set (match_dup 5) | |
3525 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3526 | (match_dup 8))) | |
3527 | (use (const_int 1))])) | |
3528 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3529 | (parallel [(set (match_dup 0) | |
3530 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3531 | (match_dup 0))) | |
3532 | (use (const_int 1))])) | |
3533 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3534 | (parallel [(set (match_dup 4) | |
3535 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3536 | (match_dup 1))) | |
3537 | (use (const_int 1))])) | |
3538 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3539 | (set (match_dup 0) | |
3540 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3541 | (match_dup 3)))) | |
3542 | ] | |
3543 | "operands[8] = CONST1_RTX (TFmode);" | |
3544 | [(set_attr "predicable" "no")]) | |
3545 | ||
3546 | (define_insn_and_split "divtf3_internal_thr" | |
3547 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3548 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3549 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3550 | (clobber (match_scratch:TF 3 "=&f")) | |
3551 | (clobber (match_scratch:TF 4 "=&f")) | |
f2f90c63 | 3552 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3553 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3554 | "#" |
3555 | "&& reload_completed" | |
3556 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
086c0f96 RH |
3557 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
3558 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3559 | (use (const_int 1))]) |
3560 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3561 | (parallel [(set (match_dup 3) | |
3562 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3563 | (match_dup 6))) | |
3564 | (use (const_int 1))])) | |
3565 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3566 | (parallel [(set (match_dup 4) | |
3567 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3568 | (match_dup 0))) | |
3569 | (use (const_int 1))])) | |
3570 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3571 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
3572 | (use (const_int 1))])) | |
3573 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3574 | (parallel [(set (match_dup 3) | |
3575 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
3576 | (match_dup 4))) | |
3577 | (use (const_int 1))])) | |
3578 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3579 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3580 | (use (const_int 1))])) | |
3581 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3582 | (parallel [(set (match_dup 0) | |
3583 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3584 | (match_dup 6))) | |
3585 | (use (const_int 1))])) | |
3586 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3587 | (parallel [(set (match_dup 0) | |
3588 | (plus:TF (mult:TF (match_dup 0) (match_dup 3)) | |
3589 | (match_dup 3))) | |
3590 | (use (const_int 1))])) | |
3591 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3592 | (parallel [(set (match_dup 3) | |
3593 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3594 | (match_dup 1))) | |
3595 | (use (const_int 1))])) | |
3596 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3597 | (parallel [(set (match_dup 3) | |
3598 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3599 | (match_dup 4))) | |
3600 | (use (const_int 1))])) | |
3601 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3602 | (parallel [(set (match_dup 4) | |
3603 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3604 | (match_dup 6))) | |
3605 | (use (const_int 1))])) | |
3606 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3607 | (parallel [(set (match_dup 0) | |
3608 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3609 | (match_dup 0))) | |
3610 | (use (const_int 1))])) | |
3611 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3612 | (parallel [(set (match_dup 4) | |
3613 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3614 | (match_dup 1))) | |
3615 | (use (const_int 1))])) | |
3616 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3617 | (set (match_dup 0) | |
3618 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3619 | (match_dup 3)))) | |
3620 | ] | |
3621 | "operands[6] = CONST1_RTX (TFmode);" | |
3622 | [(set_attr "predicable" "no")]) | |
3623 | ||
3624 | ;; ??? frcpa works like cmp.foo.unc. | |
3625 | ||
655f2eb9 RH |
3626 | (define_insn "*recip_approx" |
3627 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3628 | (div:TF (const_int 1) | |
3629 | (match_operand:TF 3 "fr_register_operand" "f"))) | |
f2f90c63 RH |
3630 | (set (match_operand:BI 1 "register_operand" "=c") |
3631 | (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") | |
086c0f96 | 3632 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 3633 | (use (match_operand:SI 4 "const_int_operand" ""))] |
23c108af | 3634 | "INTEL_EXTENDED_IEEE_FORMAT" |
655f2eb9 | 3635 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 3636 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3637 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3638 | \f |
3639 | ;; :::::::::::::::::::: | |
3640 | ;; :: | |
3641 | ;; :: 32 bit Integer Shifts and Rotates | |
3642 | ;; :: | |
3643 | ;; :::::::::::::::::::: | |
3644 | ||
9c668921 | 3645 | (define_expand "ashlsi3" |
0551c32d RH |
3646 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3647 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3648 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 3649 | "" |
9c668921 RH |
3650 | { |
3651 | if (GET_CODE (operands[2]) != CONST_INT) | |
3652 | { | |
3653 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3654 | we've got to get rid of stray bits outside the SImode register. */ | |
3655 | rtx subshift = gen_reg_rtx (DImode); | |
3656 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3657 | operands[2] = subshift; | |
3658 | } | |
1d5d7a21 | 3659 | }) |
9c668921 RH |
3660 | |
3661 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3662 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3663 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3664 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3665 | "" |
041f25e6 RH |
3666 | "@ |
3667 | shladd %0 = %1, %2, r0 | |
3668 | dep.z %0 = %1, %2, %E2 | |
3669 | shl %0 = %1, %2" | |
52e12ad0 | 3670 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3671 | |
3672 | (define_expand "ashrsi3" | |
0551c32d RH |
3673 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3674 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3675 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3676 | "" |
c65ebc55 | 3677 | { |
041f25e6 RH |
3678 | rtx subtarget = gen_reg_rtx (DImode); |
3679 | if (GET_CODE (operands[2]) == CONST_INT) | |
3680 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3681 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3682 | else | |
3683 | { | |
9c668921 | 3684 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3685 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3686 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3687 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3688 | } |
3689 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3690 | DONE; | |
1d5d7a21 | 3691 | }) |
c65ebc55 | 3692 | |
c65ebc55 | 3693 | (define_expand "lshrsi3" |
0551c32d RH |
3694 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3695 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3696 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3697 | "" |
c65ebc55 | 3698 | { |
041f25e6 RH |
3699 | rtx subtarget = gen_reg_rtx (DImode); |
3700 | if (GET_CODE (operands[2]) == CONST_INT) | |
3701 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3702 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3703 | else | |
3704 | { | |
9c668921 | 3705 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3706 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3707 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3708 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3709 | } |
3710 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3711 | DONE; | |
1d5d7a21 | 3712 | }) |
c65ebc55 | 3713 | |
c65ebc55 | 3714 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3715 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3716 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3717 | |
3718 | (define_expand "rotrsi3" | |
66db6b45 RH |
3719 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3720 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3721 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3722 | "" | |
66db6b45 RH |
3723 | { |
3724 | if (GET_MODE (operands[2]) != VOIDmode) | |
3725 | { | |
3726 | rtx tmp = gen_reg_rtx (DImode); | |
3727 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3728 | operands[2] = tmp; | |
3729 | } | |
1d5d7a21 | 3730 | }) |
66db6b45 RH |
3731 | |
3732 | (define_insn_and_split "*rotrsi3_internal" | |
3733 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3734 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3735 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3736 | "" | |
3737 | "#" | |
3738 | "reload_completed" | |
c65ebc55 | 3739 | [(set (match_dup 3) |
66db6b45 | 3740 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3741 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3742 | (set (match_dup 3) | |
66db6b45 RH |
3743 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3744 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3745 | ||
3746 | (define_expand "rotlsi3" | |
3747 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3748 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3749 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3750 | "" |
c65ebc55 JW |
3751 | { |
3752 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3753 | { |
3754 | rtx tmp = gen_reg_rtx (SImode); | |
3755 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3756 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3757 | DONE; | |
3758 | } | |
1d5d7a21 | 3759 | }) |
66db6b45 RH |
3760 | |
3761 | (define_insn_and_split "*rotlsi3_internal" | |
3762 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3763 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3764 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3765 | "" | |
3766 | "#" | |
3767 | "reload_completed" | |
3768 | [(set (match_dup 3) | |
3769 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3770 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3771 | (set (match_dup 3) | |
3772 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
3773 | { |
3774 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3775 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
3776 | }) | |
c65ebc55 JW |
3777 | \f |
3778 | ;; :::::::::::::::::::: | |
3779 | ;; :: | |
3780 | ;; :: 64 bit Integer Shifts and Rotates | |
3781 | ;; :: | |
3782 | ;; :::::::::::::::::::: | |
3783 | ||
3784 | (define_insn "ashldi3" | |
52e12ad0 BS |
3785 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3786 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3787 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3788 | "" |
041f25e6 RH |
3789 | "@ |
3790 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3791 | shl %0 = %1, %2 |
041f25e6 | 3792 | shl %0 = %1, %2" |
52e12ad0 | 3793 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3794 | |
3795 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3796 | ||
3797 | (define_insn "*shladd" | |
0551c32d RH |
3798 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3799 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3800 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3801 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3802 | "" |
3803 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3804 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3805 | |
3806 | ;; This can be created by register elimination if operand3 of shladd is an | |
3807 | ;; eliminable register or has reg_equiv_constant set. | |
3808 | ||
3809 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3810 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3811 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3812 | ;; incorrectly. | |
3813 | ||
5527bf14 | 3814 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3815 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3816 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3817 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3818 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3819 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3820 | "reload_in_progress" | |
5527bf14 | 3821 | "* abort ();" |
c65ebc55 JW |
3822 | "reload_completed" |
3823 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3824 | (match_dup 3))) | |
c65ebc55 | 3825 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3826 | "" |
52e12ad0 | 3827 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3828 | |
3829 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3830 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3831 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3832 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3833 | "" |
52e12ad0 BS |
3834 | "@ |
3835 | shr %0 = %1, %2 | |
3836 | shr %0 = %1, %2" | |
3837 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3838 | |
3839 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3840 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3841 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3842 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3843 | "" |
52e12ad0 BS |
3844 | "@ |
3845 | shr.u %0 = %1, %2 | |
3846 | shr.u %0 = %1, %2" | |
3847 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3848 | |
3849 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3850 | ;; will load the operand into a register and call the pattern if the predicate | |
3851 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3852 | ;; verify that we have an appropriate constant in the expander. | |
3853 | ||
3854 | (define_expand "rotrdi3" | |
0551c32d RH |
3855 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3856 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3857 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3858 | "" | |
c65ebc55 JW |
3859 | { |
3860 | if (! shift_count_operand (operands[2], DImode)) | |
3861 | FAIL; | |
1d5d7a21 | 3862 | }) |
c65ebc55 JW |
3863 | |
3864 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3865 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3866 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3867 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3868 | "" | |
3869 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3870 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3871 | |
66db6b45 RH |
3872 | (define_expand "rotldi3" |
3873 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3874 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3875 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3876 | "" | |
66db6b45 RH |
3877 | { |
3878 | if (! shift_count_operand (operands[2], DImode)) | |
3879 | FAIL; | |
1d5d7a21 | 3880 | }) |
66db6b45 RH |
3881 | |
3882 | (define_insn "*rotldi3_internal" | |
3883 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3884 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3885 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3886 | "" | |
3887 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3888 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
3889 | \f |
3890 | ;; :::::::::::::::::::: | |
3891 | ;; :: | |
058557c4 | 3892 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
3893 | ;; :: |
3894 | ;; :::::::::::::::::::: | |
3895 | ||
3896 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3897 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3898 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3899 | ;; This doesn't work for unary logical operations, because we don't call | |
3900 | ;; apply_distributive_law for them. | |
3901 | ||
3902 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3903 | ;; apply_distributive_law. We get inefficient code for | |
3904 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3905 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3906 | ;; (zero_extend (and (not A) B)) in combine. | |
3907 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3908 | ;; one_cmplsi2 pattern. | |
3909 | ||
058557c4 | 3910 | (define_insn "one_cmplsi2" |
0551c32d RH |
3911 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3912 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3913 | "" |
3914 | "andcm %0 = -1, %1" | |
52e12ad0 | 3915 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3916 | \f |
3917 | ;; :::::::::::::::::::: | |
3918 | ;; :: | |
058557c4 | 3919 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
3920 | ;; :: |
3921 | ;; :::::::::::::::::::: | |
3922 | ||
3923 | (define_insn "anddi3" | |
0551c32d RH |
3924 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3925 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3926 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3927 | "" |
3928 | "@ | |
3929 | and %0 = %2, %1 | |
aebf2462 | 3930 | fand %0 = %2, %1" |
52e12ad0 | 3931 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3932 | |
3933 | (define_insn "*andnot" | |
0551c32d RH |
3934 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3935 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3936 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3937 | "" |
3938 | "@ | |
3939 | andcm %0 = %2, %1 | |
aebf2462 | 3940 | fandcm %0 = %2, %1" |
52e12ad0 | 3941 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3942 | |
3943 | (define_insn "iordi3" | |
0551c32d RH |
3944 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3945 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3946 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3947 | "" |
3948 | "@ | |
3949 | or %0 = %2, %1 | |
aebf2462 | 3950 | for %0 = %2, %1" |
52e12ad0 | 3951 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3952 | |
3953 | (define_insn "xordi3" | |
0551c32d RH |
3954 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3955 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3956 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3957 | "" |
3958 | "@ | |
3959 | xor %0 = %2, %1 | |
aebf2462 | 3960 | fxor %0 = %2, %1" |
52e12ad0 | 3961 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3962 | |
3963 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3964 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3965 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3966 | "" |
3967 | "andcm %0 = -1, %1" | |
52e12ad0 | 3968 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3969 | \f |
3970 | ;; :::::::::::::::::::: | |
3971 | ;; :: | |
3972 | ;; :: Comparisons | |
3973 | ;; :: | |
3974 | ;; :::::::::::::::::::: | |
3975 | ||
f2f90c63 RH |
3976 | (define_expand "cmpbi" |
3977 | [(set (cc0) | |
3978 | (compare (match_operand:BI 0 "register_operand" "") | |
3979 | (match_operand:BI 1 "const_int_operand" "")))] | |
3980 | "" | |
f2f90c63 RH |
3981 | { |
3982 | ia64_compare_op0 = operands[0]; | |
3983 | ia64_compare_op1 = operands[1]; | |
3984 | DONE; | |
1d5d7a21 | 3985 | }) |
f2f90c63 | 3986 | |
c65ebc55 JW |
3987 | (define_expand "cmpsi" |
3988 | [(set (cc0) | |
0551c32d RH |
3989 | (compare (match_operand:SI 0 "gr_register_operand" "") |
3990 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 3991 | "" |
c65ebc55 JW |
3992 | { |
3993 | ia64_compare_op0 = operands[0]; | |
3994 | ia64_compare_op1 = operands[1]; | |
3995 | DONE; | |
1d5d7a21 | 3996 | }) |
c65ebc55 JW |
3997 | |
3998 | (define_expand "cmpdi" | |
3999 | [(set (cc0) | |
0551c32d RH |
4000 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4001 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4002 | "" |
c65ebc55 JW |
4003 | { |
4004 | ia64_compare_op0 = operands[0]; | |
4005 | ia64_compare_op1 = operands[1]; | |
4006 | DONE; | |
1d5d7a21 | 4007 | }) |
c65ebc55 JW |
4008 | |
4009 | (define_expand "cmpsf" | |
4010 | [(set (cc0) | |
0551c32d RH |
4011 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4012 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4013 | "" |
c65ebc55 JW |
4014 | { |
4015 | ia64_compare_op0 = operands[0]; | |
4016 | ia64_compare_op1 = operands[1]; | |
4017 | DONE; | |
1d5d7a21 | 4018 | }) |
c65ebc55 JW |
4019 | |
4020 | (define_expand "cmpdf" | |
4021 | [(set (cc0) | |
0551c32d RH |
4022 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4023 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4024 | "" |
c65ebc55 JW |
4025 | { |
4026 | ia64_compare_op0 = operands[0]; | |
4027 | ia64_compare_op1 = operands[1]; | |
4028 | DONE; | |
1d5d7a21 | 4029 | }) |
c65ebc55 | 4030 | |
3f622353 | 4031 | (define_expand "cmptf" |
c65ebc55 | 4032 | [(set (cc0) |
3f622353 RH |
4033 | (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") |
4034 | (match_operand:TF 1 "tfreg_or_fp01_operand" "")))] | |
23c108af | 4035 | "INTEL_EXTENDED_IEEE_FORMAT" |
c65ebc55 JW |
4036 | { |
4037 | ia64_compare_op0 = operands[0]; | |
4038 | ia64_compare_op1 = operands[1]; | |
4039 | DONE; | |
1d5d7a21 | 4040 | }) |
c65ebc55 JW |
4041 | |
4042 | (define_insn "*cmpsi_normal" | |
f2f90c63 RH |
4043 | [(set (match_operand:BI 0 "register_operand" "=c") |
4044 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4045 | [(match_operand:SI 2 "gr_register_operand" "r") |
4046 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4047 | "" |
4048 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4049 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4050 | |
18a3c539 JW |
4051 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4052 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4053 | ||
c65ebc55 | 4054 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4055 | [(set (match_operand:BI 0 "register_operand" "=c") |
4056 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4057 | [(match_operand:SI 2 "gr_register_operand" "r") |
4058 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4059 | "" |
18a3c539 | 4060 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4061 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4062 | |
4063 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4064 | [(set (match_operand:BI 0 "register_operand" "=c") |
4065 | (match_operator:BI 1 "normal_comparison_operator" | |
4066 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4067 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4068 | "" |
f2f90c63 | 4069 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4070 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4071 | |
18a3c539 JW |
4072 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4073 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4074 | ||
c65ebc55 | 4075 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4076 | [(set (match_operand:BI 0 "register_operand" "=c") |
4077 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4078 | [(match_operand:DI 2 "gr_register_operand" "r") |
4079 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4080 | "" |
18a3c539 | 4081 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4082 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4083 | |
4084 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4085 | [(set (match_operand:BI 0 "register_operand" "=c") |
4086 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4087 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4088 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4089 | "" |
4090 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4091 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4092 | |
4093 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4094 | [(set (match_operand:BI 0 "register_operand" "=c") |
4095 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4096 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4097 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4098 | "" |
4099 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4100 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4101 | |
3f622353 | 4102 | (define_insn "*cmptf_internal" |
f2f90c63 RH |
4103 | [(set (match_operand:BI 0 "register_operand" "=c") |
4104 | (match_operator:BI 1 "comparison_operator" | |
3f622353 RH |
4105 | [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG") |
4106 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))] | |
23c108af | 4107 | "INTEL_EXTENDED_IEEE_FORMAT" |
3f622353 | 4108 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4109 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4110 | |
c65ebc55 JW |
4111 | ;; ??? Can this pattern be generated? |
4112 | ||
4113 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4114 | [(set (match_operand:BI 0 "register_operand" "=c") |
4115 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4116 | (const_int 1) |
4117 | (match_operand:DI 2 "immediate_operand" "n")) | |
4118 | (const_int 0)))] | |
4119 | "" | |
4120 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4121 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4122 | |
4123 | (define_insn "*bit_one" | |
f2f90c63 RH |
4124 | [(set (match_operand:BI 0 "register_operand" "=c") |
4125 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4126 | (const_int 1) |
4127 | (match_operand:DI 2 "immediate_operand" "n")) | |
4128 | (const_int 0)))] | |
4129 | "" | |
4130 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4131 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4132 | \f |
4133 | ;; :::::::::::::::::::: | |
4134 | ;; :: | |
4135 | ;; :: Branches | |
4136 | ;; :: | |
4137 | ;; :::::::::::::::::::: | |
4138 | ||
4139 | (define_expand "beq" | |
f2f90c63 RH |
4140 | [(set (pc) |
4141 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4142 | (label_ref (match_operand 0 "" "")) |
4143 | (pc)))] | |
4144 | "" | |
f2f90c63 | 4145 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4146 | |
4147 | (define_expand "bne" | |
f2f90c63 RH |
4148 | [(set (pc) |
4149 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4150 | (label_ref (match_operand 0 "" "")) |
4151 | (pc)))] | |
4152 | "" | |
f2f90c63 | 4153 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4154 | |
4155 | (define_expand "blt" | |
f2f90c63 RH |
4156 | [(set (pc) |
4157 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4158 | (label_ref (match_operand 0 "" "")) |
4159 | (pc)))] | |
4160 | "" | |
f2f90c63 | 4161 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4162 | |
4163 | (define_expand "ble" | |
f2f90c63 RH |
4164 | [(set (pc) |
4165 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4166 | (label_ref (match_operand 0 "" "")) |
4167 | (pc)))] | |
4168 | "" | |
f2f90c63 | 4169 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4170 | |
4171 | (define_expand "bgt" | |
f2f90c63 RH |
4172 | [(set (pc) |
4173 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4174 | (label_ref (match_operand 0 "" "")) |
4175 | (pc)))] | |
4176 | "" | |
f2f90c63 | 4177 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4178 | |
4179 | (define_expand "bge" | |
f2f90c63 RH |
4180 | [(set (pc) |
4181 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4182 | (label_ref (match_operand 0 "" "")) |
4183 | (pc)))] | |
4184 | "" | |
f2f90c63 | 4185 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4186 | |
4187 | (define_expand "bltu" | |
f2f90c63 RH |
4188 | [(set (pc) |
4189 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4190 | (label_ref (match_operand 0 "" "")) |
4191 | (pc)))] | |
4192 | "" | |
f2f90c63 | 4193 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4194 | |
4195 | (define_expand "bleu" | |
f2f90c63 RH |
4196 | [(set (pc) |
4197 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4198 | (label_ref (match_operand 0 "" "")) |
4199 | (pc)))] | |
4200 | "" | |
f2f90c63 | 4201 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4202 | |
4203 | (define_expand "bgtu" | |
f2f90c63 RH |
4204 | [(set (pc) |
4205 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4206 | (label_ref (match_operand 0 "" "")) |
4207 | (pc)))] | |
4208 | "" | |
f2f90c63 | 4209 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4210 | |
4211 | (define_expand "bgeu" | |
f2f90c63 RH |
4212 | [(set (pc) |
4213 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4214 | (label_ref (match_operand 0 "" "")) |
4215 | (pc)))] | |
4216 | "" | |
f2f90c63 | 4217 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4218 | |
e57b9d65 | 4219 | (define_expand "bunordered" |
f2f90c63 RH |
4220 | [(set (pc) |
4221 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4222 | (label_ref (match_operand 0 "" "")) |
4223 | (pc)))] | |
4224 | "" | |
f2f90c63 | 4225 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4226 | |
4227 | (define_expand "bordered" | |
f2f90c63 RH |
4228 | [(set (pc) |
4229 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4230 | (label_ref (match_operand 0 "" "")) |
4231 | (pc)))] | |
4232 | "" | |
f2f90c63 | 4233 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4234 | |
6b6c1201 | 4235 | (define_insn "*br_true" |
c65ebc55 | 4236 | [(set (pc) |
6b6c1201 | 4237 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4238 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4239 | (const_int 0)]) |
4240 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4241 | (pc)))] |
4242 | "" | |
85548039 | 4243 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4244 | [(set_attr "itanium_class" "br") |
e5bde68a | 4245 | (set_attr "predicable" "no")]) |
c65ebc55 | 4246 | |
6b6c1201 | 4247 | (define_insn "*br_false" |
c65ebc55 | 4248 | [(set (pc) |
6b6c1201 | 4249 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4250 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4251 | (const_int 0)]) |
c65ebc55 | 4252 | (pc) |
6b6c1201 | 4253 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4254 | "" |
85548039 | 4255 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4256 | [(set_attr "itanium_class" "br") |
e5bde68a | 4257 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4258 | \f |
4259 | ;; :::::::::::::::::::: | |
4260 | ;; :: | |
5527bf14 RH |
4261 | ;; :: Counted loop operations |
4262 | ;; :: | |
4263 | ;; :::::::::::::::::::: | |
4264 | ||
4265 | (define_expand "doloop_end" | |
4266 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4267 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4268 | (use (match_operand 2 "" "")) ; max iterations | |
4269 | (use (match_operand 3 "" "")) ; loop level | |
4270 | (use (match_operand 4 "" ""))] ; label | |
4271 | "" | |
5527bf14 RH |
4272 | { |
4273 | /* Only use cloop on innermost loops. */ | |
4274 | if (INTVAL (operands[3]) > 1) | |
4275 | FAIL; | |
4276 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4277 | operands[4])); | |
4278 | DONE; | |
1d5d7a21 | 4279 | }) |
5527bf14 RH |
4280 | |
4281 | (define_insn "doloop_end_internal" | |
4282 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4283 | (const_int 0)) | |
4284 | (label_ref (match_operand 1 "" "")) | |
4285 | (pc))) | |
4286 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
4287 | (match_dup 0) | |
4288 | (plus:DI (match_dup 0) (const_int -1))))] | |
4289 | "" | |
4290 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4291 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4292 | (set_attr "predicable" "no")]) |
4293 | \f | |
4294 | ;; :::::::::::::::::::: | |
4295 | ;; :: | |
c65ebc55 JW |
4296 | ;; :: Set flag operations |
4297 | ;; :: | |
4298 | ;; :::::::::::::::::::: | |
4299 | ||
4300 | (define_expand "seq" | |
f2f90c63 | 4301 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4302 | "" |
f2f90c63 | 4303 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4304 | |
4305 | (define_expand "sne" | |
f2f90c63 | 4306 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4307 | "" |
f2f90c63 | 4308 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4309 | |
4310 | (define_expand "slt" | |
f2f90c63 | 4311 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4312 | "" |
f2f90c63 | 4313 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4314 | |
4315 | (define_expand "sle" | |
f2f90c63 | 4316 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4317 | "" |
f2f90c63 | 4318 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4319 | |
4320 | (define_expand "sgt" | |
f2f90c63 | 4321 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4322 | "" |
f2f90c63 | 4323 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4324 | |
4325 | (define_expand "sge" | |
f2f90c63 | 4326 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4327 | "" |
f2f90c63 | 4328 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4329 | |
4330 | (define_expand "sltu" | |
f2f90c63 | 4331 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4332 | "" |
f2f90c63 | 4333 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4334 | |
4335 | (define_expand "sleu" | |
f2f90c63 | 4336 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4337 | "" |
f2f90c63 | 4338 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4339 | |
4340 | (define_expand "sgtu" | |
f2f90c63 | 4341 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4342 | "" |
f2f90c63 | 4343 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4344 | |
4345 | (define_expand "sgeu" | |
f2f90c63 | 4346 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4347 | "" |
f2f90c63 | 4348 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4349 | |
e57b9d65 | 4350 | (define_expand "sunordered" |
f2f90c63 | 4351 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4352 | "" |
f2f90c63 | 4353 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4354 | |
4355 | (define_expand "sordered" | |
f2f90c63 | 4356 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4357 | "" |
f2f90c63 | 4358 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4359 | |
c65ebc55 JW |
4360 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4361 | ;; efficient than mov/mov/cst/cst. | |
4362 | ||
0551c32d RH |
4363 | (define_insn_and_split "*sne_internal" |
4364 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4365 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4366 | (const_int 0)))] |
4367 | "" | |
4368 | "#" | |
c65ebc55 | 4369 | "reload_completed" |
f2f90c63 RH |
4370 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4371 | (set (match_dup 0) (const_int 1))) | |
4372 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4373 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4374 | "" |
52e12ad0 | 4375 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4376 | |
0551c32d RH |
4377 | (define_insn_and_split "*seq_internal" |
4378 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4379 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4380 | (const_int 0)))] |
4381 | "" | |
4382 | "#" | |
c65ebc55 | 4383 | "reload_completed" |
f2f90c63 RH |
4384 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4385 | (set (match_dup 0) (const_int 0))) | |
4386 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4387 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4388 | "" |
52e12ad0 | 4389 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4390 | \f |
4391 | ;; :::::::::::::::::::: | |
4392 | ;; :: | |
4393 | ;; :: Conditional move instructions. | |
4394 | ;; :: | |
4395 | ;; :::::::::::::::::::: | |
4396 | ||
4397 | ;; ??? Add movXXcc patterns? | |
4398 | ||
c65ebc55 JW |
4399 | ;; |
4400 | ;; DImode if_then_else patterns. | |
4401 | ;; | |
4402 | ||
75cdbeb8 | 4403 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4404 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4405 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4406 | (if_then_else:DI |
f2f90c63 RH |
4407 | (match_operator 4 "predicate_operator" |
4408 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4409 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4410 | (const_int 0)]) |
f2f90c63 | 4411 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4412 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4413 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4414 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4415 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4416 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 4417 | { abort (); } |
75cdbeb8 RH |
4418 | [(set_attr "predicable" "no")]) |
4419 | ||
4420 | (define_split | |
f2f90c63 | 4421 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4422 | (if_then_else |
f2f90c63 RH |
4423 | (match_operator 4 "predicate_operator" |
4424 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4425 | (const_int 0)]) |
f2f90c63 RH |
4426 | (match_operand 2 "move_operand" "") |
4427 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4428 | "reload_completed" |
4429 | [(const_int 0)] | |
e5bde68a | 4430 | { |
3b572406 RH |
4431 | rtx tmp; |
4432 | if (! rtx_equal_p (operands[0], operands[2])) | |
e5bde68a | 4433 | { |
3b572406 RH |
4434 | tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]); |
4435 | tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp); | |
4436 | emit_insn (tmp); | |
e5bde68a | 4437 | } |
3b572406 RH |
4438 | if (! rtx_equal_p (operands[0], operands[3])) |
4439 | { | |
4440 | tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4441 | VOIDmode, operands[1], const0_rtx); |
3b572406 RH |
4442 | tmp = gen_rtx_COND_EXEC (VOIDmode, tmp, |
4443 | gen_rtx_SET (VOIDmode, operands[0], | |
4444 | operands[3])); | |
4445 | emit_insn (tmp); | |
4446 | } | |
4447 | DONE; | |
1d5d7a21 | 4448 | }) |
c65ebc55 JW |
4449 | |
4450 | ;; Absolute value pattern. | |
4451 | ||
4452 | (define_insn "*absdi2_internal" | |
0551c32d | 4453 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4454 | (if_then_else:DI |
f2f90c63 RH |
4455 | (match_operator 4 "predicate_operator" |
4456 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4457 | (const_int 0)]) |
0551c32d RH |
4458 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4459 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4460 | "" |
e5bde68a | 4461 | "#" |
52e12ad0 | 4462 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4463 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4464 | |
4465 | (define_split | |
4466 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4467 | (if_then_else:DI |
f2f90c63 RH |
4468 | (match_operator 4 "predicate_operator" |
4469 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4470 | (const_int 0)]) |
0551c32d RH |
4471 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4472 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4473 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4474 | [(cond_exec | |
4475 | (match_dup 4) | |
4476 | (set (match_dup 0) | |
4477 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4478 | "") |
4479 | ||
e5bde68a RH |
4480 | (define_split |
4481 | [(set (match_operand:DI 0 "register_operand" "") | |
4482 | (if_then_else:DI | |
f2f90c63 RH |
4483 | (match_operator 4 "predicate_operator" |
4484 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4485 | (const_int 0)]) |
0551c32d RH |
4486 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4487 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4488 | "reload_completed" |
4489 | [(cond_exec | |
4490 | (match_dup 4) | |
4491 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4492 | (cond_exec | |
4493 | (match_dup 5) | |
4494 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4495 | { |
4496 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4497 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4498 | }) |
c65ebc55 JW |
4499 | |
4500 | ;; | |
4501 | ;; SImode if_then_else patterns. | |
4502 | ;; | |
4503 | ||
75cdbeb8 | 4504 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4505 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4506 | (if_then_else:SI |
f2f90c63 RH |
4507 | (match_operator 4 "predicate_operator" |
4508 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4509 | (const_int 0)]) |
f2f90c63 | 4510 | (match_operand:SI 2 "move_operand" |
3b572406 | 4511 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4512 | (match_operand:SI 3 "move_operand" |
3b572406 | 4513 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4514 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4515 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 4516 | { abort (); } |
3b572406 | 4517 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4518 | |
4519 | (define_insn "*abssi2_internal" | |
0551c32d | 4520 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4521 | (if_then_else:SI |
f2f90c63 RH |
4522 | (match_operator 4 "predicate_operator" |
4523 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4524 | (const_int 0)]) |
0551c32d RH |
4525 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4526 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4527 | "" |
e5bde68a | 4528 | "#" |
52e12ad0 | 4529 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4530 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4531 | |
4532 | (define_split | |
4533 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4534 | (if_then_else:SI |
f2f90c63 RH |
4535 | (match_operator 4 "predicate_operator" |
4536 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4537 | (const_int 0)]) |
0551c32d RH |
4538 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4539 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4540 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4541 | [(cond_exec | |
4542 | (match_dup 4) | |
4543 | (set (match_dup 0) | |
4544 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4545 | "") |
4546 | ||
e5bde68a RH |
4547 | (define_split |
4548 | [(set (match_operand:SI 0 "register_operand" "") | |
4549 | (if_then_else:SI | |
f2f90c63 RH |
4550 | (match_operator 4 "predicate_operator" |
4551 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4552 | (const_int 0)]) |
0551c32d RH |
4553 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4554 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4555 | "reload_completed" |
4556 | [(cond_exec | |
4557 | (match_dup 4) | |
4558 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4559 | (cond_exec | |
4560 | (match_dup 5) | |
4561 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4562 | { |
4563 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4564 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4565 | }) |
e5bde68a | 4566 | |
7dcc803e | 4567 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4568 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4569 | (match_operator:SI 5 "condop_operator" | |
4570 | [(if_then_else:SI | |
4571 | (match_operator 6 "predicate_operator" | |
4572 | [(match_operand:BI 1 "register_operand" "c") | |
4573 | (const_int 0)]) | |
4574 | (match_operand:SI 2 "gr_register_operand" "r") | |
4575 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4576 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4577 | "" | |
4578 | "#" | |
acb0638d BS |
4579 | "reload_completed" |
4580 | [(cond_exec | |
4581 | (match_dup 6) | |
4582 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4583 | (cond_exec | |
4584 | (match_dup 7) | |
4585 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
4586 | { |
4587 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4588 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4589 | } |
7dcc803e BS |
4590 | [(set_attr "itanium_class" "ialu") |
4591 | (set_attr "predicable" "no")]) | |
4592 | ||
acb0638d | 4593 | |
7dcc803e | 4594 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4595 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4596 | (match_operator:SI 5 "condop_operator" | |
4597 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4598 | (if_then_else:SI | |
4599 | (match_operator 6 "predicate_operator" | |
4600 | [(match_operand:BI 1 "register_operand" "c") | |
4601 | (const_int 0)]) | |
4602 | (match_operand:SI 2 "gr_register_operand" "r") | |
4603 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4604 | "" | |
4605 | "#" | |
acb0638d BS |
4606 | "reload_completed" |
4607 | [(cond_exec | |
4608 | (match_dup 6) | |
4609 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4610 | (cond_exec | |
4611 | (match_dup 7) | |
4612 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
4613 | { |
4614 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4615 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4616 | } |
7dcc803e BS |
4617 | [(set_attr "itanium_class" "ialu") |
4618 | (set_attr "predicable" "no")]) | |
acb0638d | 4619 | |
c65ebc55 JW |
4620 | \f |
4621 | ;; :::::::::::::::::::: | |
4622 | ;; :: | |
4623 | ;; :: Call and branch instructions | |
4624 | ;; :: | |
4625 | ;; :::::::::::::::::::: | |
4626 | ||
4627 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4628 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4629 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4630 | ;; registers used as operands. | |
4631 | ||
4632 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4633 | ;; is supplied for the sake of some RISC machines which need to put this | |
4634 | ;; information into the assembler code; they can put it in the RTL instead of | |
4635 | ;; operand 1. | |
4636 | ||
4637 | (define_expand "call" | |
4638 | [(use (match_operand:DI 0 "" "")) | |
4639 | (use (match_operand 1 "" "")) | |
4640 | (use (match_operand 2 "" "")) | |
4641 | (use (match_operand 3 "" ""))] | |
4642 | "" | |
c65ebc55 | 4643 | { |
2ed4af6f | 4644 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); |
c65ebc55 | 4645 | DONE; |
1d5d7a21 | 4646 | }) |
c65ebc55 | 4647 | |
2ed4af6f RH |
4648 | (define_expand "sibcall" |
4649 | [(use (match_operand:DI 0 "" "")) | |
4650 | (use (match_operand 1 "" "")) | |
4651 | (use (match_operand 2 "" "")) | |
4652 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 4653 | "" |
c65ebc55 | 4654 | { |
2ed4af6f RH |
4655 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); |
4656 | DONE; | |
1d5d7a21 | 4657 | }) |
c65ebc55 | 4658 | |
c65ebc55 | 4659 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4660 | ;; register in which the value is returned. There are three more operands, |
4661 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4662 | ;; increased by one). |
2ed4af6f | 4663 | ;; |
c65ebc55 JW |
4664 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4665 | ||
4666 | (define_expand "call_value" | |
4667 | [(use (match_operand 0 "" "")) | |
4668 | (use (match_operand:DI 1 "" "")) | |
4669 | (use (match_operand 2 "" "")) | |
4670 | (use (match_operand 3 "" "")) | |
4671 | (use (match_operand 4 "" ""))] | |
4672 | "" | |
c65ebc55 | 4673 | { |
2ed4af6f | 4674 | ia64_expand_call (operands[0], operands[1], operands[3], 0); |
c65ebc55 | 4675 | DONE; |
1d5d7a21 | 4676 | }) |
c65ebc55 | 4677 | |
2ed4af6f RH |
4678 | (define_expand "sibcall_value" |
4679 | [(use (match_operand 0 "" "")) | |
4680 | (use (match_operand:DI 1 "" "")) | |
4681 | (use (match_operand 2 "" "")) | |
4682 | (use (match_operand 3 "" "")) | |
4683 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 4684 | "" |
c65ebc55 | 4685 | { |
2ed4af6f RH |
4686 | ia64_expand_call (operands[0], operands[1], operands[3], 1); |
4687 | DONE; | |
1d5d7a21 | 4688 | }) |
c65ebc55 | 4689 | |
c65ebc55 JW |
4690 | ;; Call subroutine returning any type. |
4691 | ||
4692 | (define_expand "untyped_call" | |
4693 | [(parallel [(call (match_operand 0 "" "") | |
4694 | (const_int 0)) | |
4695 | (match_operand 1 "" "") | |
4696 | (match_operand 2 "" "")])] | |
4697 | "" | |
c65ebc55 JW |
4698 | { |
4699 | int i; | |
4700 | ||
4701 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4702 | ||
4703 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4704 | { | |
4705 | rtx set = XVECEXP (operands[2], 0, i); | |
4706 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4707 | } | |
4708 | ||
4709 | /* The optimizer does not know that the call sets the function value | |
4710 | registers we stored in the result block. We avoid problems by | |
4711 | claiming that all hard registers are used and clobbered at this | |
4712 | point. */ | |
4713 | emit_insn (gen_blockage ()); | |
4714 | ||
4715 | DONE; | |
1d5d7a21 | 4716 | }) |
c65ebc55 | 4717 | |
2ed4af6f | 4718 | (define_insn "call_nopic" |
52e12ad0 | 4719 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4720 | (match_operand 1 "" "")) |
52e12ad0 | 4721 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4722 | "" |
4723 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4724 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4725 | |
4726 | (define_insn "call_value_nopic" | |
4727 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4728 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4729 | (match_operand 2 "" ""))) |
52e12ad0 | 4730 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4731 | "" |
4732 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4733 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4734 | |
4735 | (define_insn "sibcall_nopic" | |
52e12ad0 | 4736 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4737 | (match_operand 1 "" "")) |
6ca3c22f RH |
4738 | (use (match_operand:DI 2 "register_operand" "=b,b")) |
4739 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4740 | "" |
4741 | "br%+.many %0" | |
52e12ad0 | 4742 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4743 | |
4744 | (define_insn "call_pic" | |
52e12ad0 | 4745 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4746 | (match_operand 1 "" "")) |
086c0f96 | 4747 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
52e12ad0 | 4748 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4749 | "" |
4750 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4751 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4752 | |
4753 | (define_insn "call_value_pic" | |
4754 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4755 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4756 | (match_operand 2 "" ""))) |
086c0f96 | 4757 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
52e12ad0 | 4758 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4759 | "" |
4760 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4761 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4762 | |
4763 | (define_insn "sibcall_pic" | |
4764 | [(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) | |
4765 | (match_operand 1 "" "")) | |
086c0f96 | 4766 | (use (unspec [(reg:DI 1)] UNSPEC_PIC_CALL)) |
6ca3c22f RH |
4767 | (use (match_operand:DI 2 "register_operand" "=b")) |
4768 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4769 | "" |
4770 | "br%+.many %0" | |
52e12ad0 | 4771 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4772 | |
c65ebc55 JW |
4773 | (define_insn "return_internal" |
4774 | [(return) | |
4775 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4776 | "" | |
4777 | "br.ret.sptk.many %0" | |
52e12ad0 | 4778 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4779 | |
4780 | (define_insn "return" | |
4781 | [(return)] | |
4782 | "ia64_direct_return ()" | |
4783 | "br.ret.sptk.many rp" | |
52e12ad0 | 4784 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4785 | |
6b6c1201 | 4786 | (define_insn "*return_true" |
c65ebc55 | 4787 | [(set (pc) |
6b6c1201 | 4788 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4789 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4790 | (const_int 0)]) |
c65ebc55 JW |
4791 | (return) |
4792 | (pc)))] | |
4793 | "ia64_direct_return ()" | |
13da91fd | 4794 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4795 | [(set_attr "itanium_class" "br") |
e5bde68a | 4796 | (set_attr "predicable" "no")]) |
c65ebc55 | 4797 | |
6b6c1201 | 4798 | (define_insn "*return_false" |
c65ebc55 | 4799 | [(set (pc) |
6b6c1201 | 4800 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4801 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4802 | (const_int 0)]) |
c65ebc55 JW |
4803 | (pc) |
4804 | (return)))] | |
4805 | "ia64_direct_return ()" | |
13da91fd | 4806 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4807 | [(set_attr "itanium_class" "br") |
e5bde68a | 4808 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4809 | |
4810 | (define_insn "jump" | |
4811 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4812 | "" | |
4813 | "br %l0" | |
52e12ad0 | 4814 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4815 | |
4816 | (define_insn "indirect_jump" | |
4817 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4818 | "" | |
4819 | "br %0" | |
52e12ad0 | 4820 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4821 | |
4822 | (define_expand "tablejump" | |
340f7e7c RH |
4823 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
4824 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 4825 | "" |
c65ebc55 | 4826 | { |
340f7e7c RH |
4827 | rtx op0 = operands[0]; |
4828 | rtx addr; | |
4829 | ||
4830 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
4831 | element into a register without bothering to see whether that | |
4832 | is necessary given the operand predicate. Check for MEM just | |
4833 | in case someone fixes this. */ | |
4834 | if (GET_CODE (op0) == MEM) | |
4835 | addr = XEXP (op0, 0); | |
4836 | else | |
4837 | { | |
4838 | /* Otherwise, cheat and guess that the previous insn in the | |
4839 | stream was the memory load. Grab the address from that. | |
4840 | Note we have to momentarily pop out of the sequence started | |
4841 | by the insn-emit wrapper in order to grab the last insn. */ | |
4842 | rtx last, set; | |
4843 | ||
4844 | end_sequence (); | |
4845 | last = get_last_insn (); | |
4846 | start_sequence (); | |
4847 | set = single_set (last); | |
4848 | ||
4849 | if (! rtx_equal_p (SET_DEST (set), op0) | |
4850 | || GET_CODE (SET_SRC (set)) != MEM) | |
4851 | abort (); | |
4852 | addr = XEXP (SET_SRC (set), 0); | |
4853 | if (rtx_equal_p (addr, op0)) | |
4854 | abort (); | |
4855 | } | |
c65ebc55 | 4856 | |
340f7e7c RH |
4857 | /* Jump table elements are stored pc-relative. That is, a displacement |
4858 | from the entry to the label. Thus to convert to an absolute address | |
4859 | we add the address of the memory from which the value is loaded. */ | |
4860 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
4861 | NULL_RTX, 1, OPTAB_DIRECT); | |
4862 | }) | |
c65ebc55 | 4863 | |
340f7e7c | 4864 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
4865 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
4866 | (use (label_ref (match_operand 1 "" "")))] | |
4867 | "" | |
4868 | "br %0" | |
52e12ad0 | 4869 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4870 | |
4871 | \f | |
4872 | ;; :::::::::::::::::::: | |
4873 | ;; :: | |
4874 | ;; :: Prologue and Epilogue instructions | |
4875 | ;; :: | |
4876 | ;; :::::::::::::::::::: | |
4877 | ||
4878 | (define_expand "prologue" | |
4879 | [(const_int 1)] | |
4880 | "" | |
c65ebc55 JW |
4881 | { |
4882 | ia64_expand_prologue (); | |
4883 | DONE; | |
1d5d7a21 | 4884 | }) |
c65ebc55 JW |
4885 | |
4886 | (define_expand "epilogue" | |
2ed4af6f RH |
4887 | [(return)] |
4888 | "" | |
2ed4af6f RH |
4889 | { |
4890 | ia64_expand_epilogue (0); | |
4891 | DONE; | |
1d5d7a21 | 4892 | }) |
2ed4af6f RH |
4893 | |
4894 | (define_expand "sibcall_epilogue" | |
4895 | [(return)] | |
c65ebc55 | 4896 | "" |
c65ebc55 | 4897 | { |
2ed4af6f | 4898 | ia64_expand_epilogue (1); |
c65ebc55 | 4899 | DONE; |
1d5d7a21 | 4900 | }) |
c65ebc55 JW |
4901 | |
4902 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4903 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4904 | ||
4905 | (define_insn "prologue_allocate_stack" | |
4906 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4907 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4908 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 4909 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
4910 | (match_dup 3))] |
4911 | "" | |
4912 | "@ | |
1d5d7a21 RH |
4913 | add %0 = %1, %2 |
4914 | adds %0 = %2, %1 | |
4915 | addl %0 = %2, %1" | |
52e12ad0 | 4916 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4917 | |
4918 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4919 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4920 | ||
4921 | (define_insn "epilogue_deallocate_stack" | |
4922 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4923 | (match_operand:DI 1 "register_operand" "+r")) | |
4924 | (set (match_dup 1) (match_dup 1))] | |
4925 | "" | |
4926 | "mov %0 = %1" | |
52e12ad0 | 4927 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 4928 | |
1d5d7a21 RH |
4929 | ;; As USE insns aren't meaningful after reload, this is used instead |
4930 | ;; to prevent deleting instructions setting registers for EH handling | |
4931 | (define_insn "prologue_use" | |
4932 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
4933 | UNSPEC_PROLOGUE_USE)] | |
4934 | "" | |
4935 | "" | |
4936 | [(set_attr "itanium_class" "ignore") | |
4937 | (set_attr "predicable" "no")]) | |
4938 | ||
c65ebc55 JW |
4939 | ;; Allocate a new register frame. |
4940 | ||
4941 | (define_insn "alloc" | |
4942 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4943 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
4944 | (use (match_operand:DI 1 "const_int_operand" "i")) |
4945 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4946 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4947 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4948 | "" | |
4949 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4950 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 4951 | (set_attr "predicable" "no")]) |
c65ebc55 | 4952 | |
97e242b0 RH |
4953 | ;; Modifies ar.unat |
4954 | (define_expand "gr_spill" | |
870f9ec0 RH |
4955 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4956 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
4957 | (match_operand:DI 2 "const_int_operand" "")] |
4958 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4959 | (clobber (match_dup 3))])] |
97e242b0 | 4960 | "" |
870f9ec0 | 4961 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4962 | |
870f9ec0 | 4963 | (define_insn "gr_spill_internal" |
c65ebc55 | 4964 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 | 4965 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
4966 | (match_operand:DI 2 "const_int_operand" "")] |
4967 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4968 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4969 | "" |
2130b7fb | 4970 | { |
1d5d7a21 RH |
4971 | /* Note that we use a C output pattern here to avoid the predicate |
4972 | being automatically added before the .mem.offset directive. */ | |
4973 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
4974 | } | |
52e12ad0 | 4975 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4976 | |
97e242b0 RH |
4977 | ;; Reads ar.unat |
4978 | (define_expand "gr_restore" | |
870f9ec0 RH |
4979 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4980 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
4981 | (match_operand:DI 2 "const_int_operand" "")] |
4982 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4983 | (use (match_dup 3))])] |
97e242b0 | 4984 | "" |
870f9ec0 | 4985 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4986 | |
870f9ec0 | 4987 | (define_insn "gr_restore_internal" |
c65ebc55 | 4988 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 4989 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
4990 | (match_operand:DI 2 "const_int_operand" "")] |
4991 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4992 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4993 | "" |
1d5d7a21 | 4994 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 4995 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4996 | |
4997 | (define_insn "fr_spill" | |
3f622353 | 4998 | [(set (match_operand:TF 0 "memory_operand" "=m") |
086c0f96 RH |
4999 | (unspec:TF [(match_operand:TF 1 "register_operand" "f")] |
5000 | UNSPEC_FR_SPILL))] | |
c65ebc55 JW |
5001 | "" |
5002 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5003 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5004 | |
5005 | (define_insn "fr_restore" | |
3f622353 | 5006 | [(set (match_operand:TF 0 "register_operand" "=f") |
086c0f96 RH |
5007 | (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] |
5008 | UNSPEC_FR_RESTORE))] | |
c65ebc55 JW |
5009 | "" |
5010 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5011 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5012 | |
0024a804 JW |
5013 | ;; ??? The explicit stop is not ideal. It would be better if |
5014 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5015 | ;; fixed later. This avoids an RSE DV. | |
5016 | ||
0c96007e AM |
5017 | (define_insn "bsp_value" |
5018 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5019 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5020 | "" |
0024a804 | 5021 | ";;\;mov %0 = ar.bsp" |
52e12ad0 | 5022 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5023 | |
5024 | (define_insn "set_bsp" | |
086c0f96 RH |
5025 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5026 | UNSPECV_SET_BSP)] | |
0c96007e | 5027 | "" |
1d5d7a21 RH |
5028 | "flushrs |
5029 | mov r19=ar.rsc | |
5030 | ;; | |
5031 | and r19=0x1c,r19 | |
5032 | ;; | |
5033 | mov ar.rsc=r19 | |
5034 | ;; | |
5035 | mov ar.bspstore=%0 | |
5036 | ;; | |
5037 | or r19=0x3,r19 | |
5038 | ;; | |
5039 | loadrs | |
5040 | invala | |
5041 | ;; | |
5042 | mov ar.rsc=r19" | |
52e12ad0 | 5043 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5044 | (set_attr "predicable" "no")]) |
ce152ef8 | 5045 | |
0024a804 JW |
5046 | ;; ??? The explicit stops are not ideal. It would be better if |
5047 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5048 | ;; fixed later. This avoids an RSE DV. | |
5049 | ||
ce152ef8 | 5050 | (define_insn "flushrs" |
086c0f96 | 5051 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5052 | "" |
0024a804 | 5053 | ";;\;flushrs\;;;" |
52e12ad0 | 5054 | [(set_attr "itanium_class" "rse_m")]) |
c65ebc55 JW |
5055 | \f |
5056 | ;; :::::::::::::::::::: | |
5057 | ;; :: | |
5058 | ;; :: Miscellaneous instructions | |
5059 | ;; :: | |
5060 | ;; :::::::::::::::::::: | |
5061 | ||
5062 | ;; ??? Emiting a NOP instruction isn't very useful. This should probably | |
5063 | ;; be emitting ";;" to force a break in the instruction packing. | |
5064 | ||
5065 | ;; No operation, needed in case the user uses -g but not -O. | |
5066 | (define_insn "nop" | |
5067 | [(const_int 0)] | |
5068 | "" | |
5069 | "nop 0" | |
52e12ad0 | 5070 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5071 | |
2130b7fb BS |
5072 | (define_insn "nop_m" |
5073 | [(const_int 1)] | |
5074 | "" | |
5075 | "nop.m 0" | |
5076 | [(set_attr "itanium_class" "nop_m")]) | |
5077 | ||
5078 | (define_insn "nop_i" | |
5079 | [(const_int 2)] | |
5080 | "" | |
5081 | "nop.i 0" | |
5082 | [(set_attr "itanium_class" "nop_i")]) | |
5083 | ||
5084 | (define_insn "nop_f" | |
5085 | [(const_int 3)] | |
5086 | "" | |
5087 | "nop.f 0" | |
5088 | [(set_attr "itanium_class" "nop_f")]) | |
5089 | ||
5090 | (define_insn "nop_b" | |
5091 | [(const_int 4)] | |
5092 | "" | |
5093 | "nop.b 0" | |
5094 | [(set_attr "itanium_class" "nop_b")]) | |
5095 | ||
5096 | (define_insn "nop_x" | |
5097 | [(const_int 5)] | |
5098 | "" | |
5099 | "" | |
5100 | [(set_attr "itanium_class" "nop_x")]) | |
5101 | ||
2130b7fb | 5102 | (define_insn "bundle_selector" |
086c0f96 | 5103 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5104 | "" |
1d5d7a21 | 5105 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5106 | [(set_attr "itanium_class" "ignore") |
5107 | (set_attr "predicable" "no")]) | |
5108 | ||
c65ebc55 JW |
5109 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5110 | ;; point. | |
5111 | (define_insn "blockage" | |
086c0f96 | 5112 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5113 | "" |
5114 | "" | |
52e12ad0 | 5115 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5116 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5117 | |
5118 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5119 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5120 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5121 | "" |
5122 | ";;" | |
52e12ad0 | 5123 | [(set_attr "itanium_class" "stop_bit") |
e5bde68a | 5124 | (set_attr "predicable" "no")]) |
c65ebc55 | 5125 | |
26406018 RH |
5126 | (define_expand "trap" |
5127 | [(trap_if (const_int 1) (const_int 0))] | |
5128 | "" | |
5129 | "") | |
5130 | ||
5131 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
5132 | ;; produces worse code that setting the slot type to A. | |
5133 | ||
5134 | (define_insn "*trap" | |
5135 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
5136 | "" | |
5137 | "break %0" | |
5138 | [(set_attr "itanium_class" "chk_s")]) | |
5139 | ||
5140 | (define_expand "conditional_trap" | |
5141 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
5142 | "" | |
5143 | { | |
5144 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
5145 | }) | |
5146 | ||
5147 | (define_insn "*conditional_trap" | |
5148 | [(trap_if (match_operator 0 "predicate_operator" | |
5149 | [(match_operand:BI 1 "register_operand" "c") | |
5150 | (const_int 0)]) | |
5151 | (match_operand 2 "const_int_operand" ""))] | |
5152 | "" | |
5cf63e3f | 5153 | "(%J0) break %2" |
26406018 RH |
5154 | [(set_attr "itanium_class" "chk_s") |
5155 | (set_attr "predicable" "no")]) | |
5156 | ||
f12f25a7 | 5157 | (define_insn "break_f" |
086c0f96 | 5158 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
5159 | "" |
5160 | "break.f 0" | |
5161 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5162 | |
5163 | (define_insn "prefetch" | |
5164 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5165 | (match_operand:DI 1 "const_int_operand" "n") | |
5166 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5167 | "" | |
5168 | { | |
5169 | static const char * const alt[2][4] = { | |
b3656137 KG |
5170 | { |
5171 | "lfetch.nta [%0]", | |
5172 | "lfetch.nt1 [%0]", | |
5173 | "lfetch.nt2 [%0]", | |
5174 | "lfetch [%0]" | |
5175 | }, | |
5176 | { | |
5177 | "lfetch.excl.nta [%0]", | |
5178 | "lfetch.excl.nt1 [%0]", | |
5179 | "lfetch.excl.nt2 [%0]", | |
5180 | "lfetch.excl [%0]" | |
5181 | } | |
44eca121 JJ |
5182 | }; |
5183 | int i = (INTVAL (operands[1])); | |
5184 | int j = (INTVAL (operands[2])); | |
5185 | ||
5186 | if (i != 0 && i != 1) | |
5187 | abort (); | |
5188 | if (j < 0 || j > 3) | |
5189 | abort (); | |
5190 | return alt[i][j]; | |
5191 | } | |
5192 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5193 | \f |
5194 | ;; Non-local goto support. | |
5195 | ||
5196 | (define_expand "save_stack_nonlocal" | |
5197 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5198 | (use (match_operand:DI 1 "register_operand" ""))] | |
5199 | "" | |
c65ebc55 JW |
5200 | { |
5201 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5202 | \"__ia64_save_stack_nonlocal\"), | |
5203 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
5204 | operands[1], Pmode); | |
5205 | DONE; | |
1d5d7a21 | 5206 | }) |
c65ebc55 JW |
5207 | |
5208 | (define_expand "nonlocal_goto" | |
5209 | [(use (match_operand 0 "general_operand" "")) | |
5210 | (use (match_operand 1 "general_operand" "")) | |
5211 | (use (match_operand 2 "general_operand" "")) | |
5212 | (use (match_operand 3 "general_operand" ""))] | |
5213 | "" | |
c65ebc55 | 5214 | { |
c65ebc55 | 5215 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5216 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5217 | operands[1], Pmode, |
c65ebc55 | 5218 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5219 | operands[3], Pmode); |
c65ebc55 JW |
5220 | emit_barrier (); |
5221 | DONE; | |
1d5d7a21 | 5222 | }) |
c65ebc55 | 5223 | |
97e242b0 RH |
5224 | ;; The rest of the setjmp processing happens with the nonlocal_goto expander. |
5225 | ;; ??? This is not tested. | |
5226 | (define_expand "builtin_setjmp_setup" | |
5227 | [(use (match_operand:DI 0 "" ""))] | |
c65ebc55 | 5228 | "" |
c65ebc55 | 5229 | { |
97e242b0 RH |
5230 | emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); |
5231 | DONE; | |
1d5d7a21 | 5232 | }) |
97e242b0 RH |
5233 | |
5234 | (define_expand "builtin_setjmp_receiver" | |
5235 | [(use (match_operand:DI 0 "" ""))] | |
5236 | "" | |
97e242b0 RH |
5237 | { |
5238 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); | |
c65ebc55 | 5239 | DONE; |
1d5d7a21 | 5240 | }) |
c65ebc55 | 5241 | |
0c96007e AM |
5242 | (define_expand "eh_epilogue" |
5243 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5244 | (use (match_operand:DI 1 "register_operand" "r")) | |
5245 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5246 | "" | |
0c96007e AM |
5247 | { |
5248 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5249 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5250 | ||
5251 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5252 | { | |
5253 | emit_move_insn (bsp, operands[0]); | |
5254 | operands[0] = bsp; | |
5255 | } | |
5256 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5257 | { | |
5258 | emit_move_insn (sp, operands[2]); | |
5259 | operands[2] = sp; | |
5260 | } | |
5261 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5262 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5263 | ||
5264 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5265 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5266 | }) |
9525c690 JW |
5267 | \f |
5268 | ;; Builtin apply support. | |
5269 | ||
5270 | (define_expand "restore_stack_nonlocal" | |
5271 | [(use (match_operand:DI 0 "register_operand" "")) | |
5272 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5273 | "" | |
9525c690 JW |
5274 | { |
5275 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5276 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
5277 | 0, VOIDmode, 1, |
5278 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5279 | DONE; | |
1d5d7a21 | 5280 | }) |
9525c690 JW |
5281 | |
5282 | \f | |
5283 | ;;; Intrinsics support. | |
c65ebc55 | 5284 | |
0551c32d RH |
5285 | (define_expand "mf" |
5286 | [(set (mem:BLK (match_dup 0)) | |
086c0f96 | 5287 | (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))] |
0551c32d | 5288 | "" |
0551c32d RH |
5289 | { |
5290 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
5291 | MEM_VOLATILE_P (operands[0]) = 1; | |
1d5d7a21 | 5292 | }) |
0551c32d RH |
5293 | |
5294 | (define_insn "*mf_internal" | |
5295 | [(set (match_operand:BLK 0 "" "") | |
086c0f96 | 5296 | (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))] |
c65ebc55 JW |
5297 | "" |
5298 | "mf" | |
52e12ad0 | 5299 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
5300 | |
5301 | (define_insn "fetchadd_acq_si" | |
0551c32d RH |
5302 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5303 | (match_dup 1)) | |
5304 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5305 | (unspec:SI [(match_dup 1) | |
086c0f96 RH |
5306 | (match_operand:SI 2 "fetchadd_operand" "n")] |
5307 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
5308 | "" |
5309 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 5310 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5311 | |
5312 | (define_insn "fetchadd_acq_di" | |
0551c32d RH |
5313 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5314 | (match_dup 1)) | |
5315 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5316 | (unspec:DI [(match_dup 1) | |
086c0f96 RH |
5317 | (match_operand:DI 2 "fetchadd_operand" "n")] |
5318 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
5319 | "" |
5320 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 5321 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5322 | |
5323 | (define_insn "cmpxchg_acq_si" | |
0551c32d RH |
5324 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5325 | (match_dup 1)) | |
5326 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5327 | (unspec:SI [(match_dup 1) | |
5328 | (match_operand:SI 2 "gr_register_operand" "r") | |
086c0f96 RH |
5329 | (match_operand:SI 3 "ar_ccv_reg_operand" "")] |
5330 | UNSPEC_CMPXCHG_ACQ))] | |
c65ebc55 | 5331 | "" |
97e242b0 | 5332 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 5333 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5334 | |
5335 | (define_insn "cmpxchg_acq_di" | |
0551c32d RH |
5336 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5337 | (match_dup 1)) | |
5338 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5339 | (unspec:DI [(match_dup 1) | |
5340 | (match_operand:DI 2 "gr_register_operand" "r") | |
086c0f96 RH |
5341 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] |
5342 | UNSPEC_CMPXCHG_ACQ))] | |
c65ebc55 | 5343 | "" |
97e242b0 | 5344 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 5345 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 5346 | |
c65ebc55 | 5347 | (define_insn "xchgsi" |
0551c32d RH |
5348 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5349 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5350 | (set (match_dup 1) |
0551c32d | 5351 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5352 | "" |
5353 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 5354 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5355 | |
5356 | (define_insn "xchgdi" | |
0551c32d RH |
5357 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5358 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5359 | (set (match_dup 1) |
0551c32d | 5360 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5361 | "" |
5362 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 5363 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
5364 | \f |
5365 | ;; Predication. | |
5366 | ||
5367 | (define_cond_exec | |
5368 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5369 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5370 | (const_int 0)])] |
5371 | "" | |
5372 | "(%J0)") | |
3b572406 RH |
5373 | |
5374 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 5375 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 5376 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 5377 | "" |
054451ea | 5378 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5379 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5380 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5381 | |
5382 | (define_insn "safe_across_calls_all" | |
086c0f96 | 5383 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
5384 | "" |
5385 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5386 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5387 | (set_attr "predicable" "no")]) |
5388 | ||
5389 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 5390 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 5391 | "" |
ca3920ad JW |
5392 | { |
5393 | emit_safe_across_calls (asm_out_file); | |
1d5d7a21 RH |
5394 | return ""; |
5395 | } | |
52e12ad0 | 5396 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5397 | (set_attr "predicable" "no")]) |
5398 | ||
6dd12198 SE |
5399 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit |
5400 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
5401 | ||
5402 | (define_insn "ptr_extend" | |
5403 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
5404 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
5405 | UNSPEC_ADDP4))] | |
6dd12198 SE |
5406 | "" |
5407 | "addp4 %0 = 0,%1" | |
5408 | [(set_attr "itanium_class" "ialu")]) | |
5409 | ||
e206a74f SE |
5410 | ;; |
5411 | ;; Optimizations for ptr_extend | |
5412 | ||
5413 | (define_insn "*ptr_extend_plus_1" | |
5414 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5415 | (unspec:DI | |
5416 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5417 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 5418 | UNSPEC_ADDP4))] |
e206a74f SE |
5419 | "" |
5420 | "addp4 %0 = %2, %1" | |
5421 | [(set_attr "itanium_class" "ialu")]) | |
5422 | ||
5423 | (define_insn "*ptr_extend_plus_2" | |
5424 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5425 | (unspec:DI | |
5426 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5427 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 5428 | UNSPEC_ADDP4))] |
e206a74f SE |
5429 | "" |
5430 | "addp4 %0 = %1, %2" | |
5431 | [(set_attr "itanium_class" "ialu")]) |