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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
bbbbb16a ILT |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
3 | ;; 2009 Free Software Foundation, Inc. | |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 10 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
12 | ;; any later version. |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 58 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
59 | |
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
046625fa | 81 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 82 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
83 | (UNSPEC_LDA 40) |
84 | (UNSPEC_LDS 41) | |
388092d5 AB |
85 | (UNSPEC_LDS_A 42) |
86 | (UNSPEC_LDSA 43) | |
87 | (UNSPEC_LDCCLR 44) | |
88 | (UNSPEC_LDCNC 45) | |
89 | (UNSPEC_CHKACLR 46) | |
90 | (UNSPEC_CHKANC 47) | |
91 | (UNSPEC_CHKS 48) | |
92 | (UNSPEC_FR_RECIP_APPROX_RES 49) | |
93 | (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50) | |
086c0f96 RH |
94 | ]) |
95 | ||
96 | (define_constants | |
97 | [(UNSPECV_ALLOC 0) | |
98 | (UNSPECV_BLOCKAGE 1) | |
99 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
100 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
101 | (UNSPECV_SET_BSP 4) |
102 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
103 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 104 | (UNSPECV_SETJMP_RECEIVER 7) |
39a5cfa4 | 105 | (UNSPECV_GOTO_RECEIVER 8) |
086c0f96 | 106 | ]) |
e543e219 | 107 | |
7905f799 | 108 | (include "predicates.md") |
13f70342 | 109 | (include "constraints.md") |
c65ebc55 JW |
110 | \f |
111 | ;; :::::::::::::::::::: | |
112 | ;; :: | |
113 | ;; :: Attributes | |
114 | ;; :: | |
115 | ;; :::::::::::::::::::: | |
116 | ||
30028c85 VM |
117 | ;; Processor type. This attribute must exactly match the processor_type |
118 | ;; enumeration in ia64.h. | |
bbbbb16a ILT |
119 | (define_attr "cpu" "itanium,itanium2" |
120 | (const (symbol_ref "((enum attr_cpu) ia64_tune)"))) | |
30028c85 | 121 | |
c65ebc55 JW |
122 | ;; Instruction type. This primarily determines how instructions can be |
123 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
124 | ||
125 | ;; A alu, can go in I or M syllable of a bundle | |
126 | ;; I integer | |
127 | ;; M memory | |
128 | ;; F floating-point | |
129 | ;; B branch | |
130 | ;; L long immediate, takes two syllables | |
131 | ;; S stop bit | |
132 | ||
133 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
134 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
135 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
136 | ;; which emit instruction that can go in any slot (e.g. nop). | |
137 | ||
1d5d7a21 | 138 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 139 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 140 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
141 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
142 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 143 | (const_string "unknown")) |
52e12ad0 | 144 | |
048d0d36 | 145 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 146 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 147 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
148 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
149 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 150 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
151 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
152 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 153 | (const_string "A") |
2130b7fb BS |
154 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
155 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
156 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
157 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
158 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
159 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 160 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 161 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
162 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
163 | (const_string "unknown"))) | |
c65ebc55 | 164 | |
2130b7fb BS |
165 | (define_attr "itanium_requires_unit0" "no,yes" |
166 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
167 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
168 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
169 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
170 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
171 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
172 | (const_string "no"))) | |
173 | ||
e5bde68a RH |
174 | ;; Predication. True iff this instruction can be predicated. |
175 | ||
176 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
177 | ||
fa978426 AS |
178 | ;; Empty. True iff this insn does not generate any code. |
179 | ||
180 | (define_attr "empty" "no,yes" (const_string "no")) | |
181 | ||
68e11b42 JW |
182 | ;; True iff this insn must be the first insn of an instruction group. |
183 | ;; This is true for the alloc instruction, and will also be true of others | |
184 | ;; when we have full intrinsics support. | |
185 | ||
186 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
187 | |
188 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
189 | ||
190 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
191 | ||
192 | (define_attr "check_load" "no,yes" (const_string "no")) | |
388092d5 AB |
193 | |
194 | (define_attr "speculable1" "no,yes" (const_string "no")) | |
195 | ||
196 | (define_attr "speculable2" "no,yes" (const_string "no")) | |
c65ebc55 | 197 | \f |
30028c85 VM |
198 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
199 | ;; bundling. | |
200 | ||
201 | (automata_option "ndfa") | |
202 | ||
203 | ;; Uncomment the following line to output automata for debugging. | |
204 | ;; (automata_option "v") | |
205 | ||
206 | (automata_option "w") | |
207 | ||
30028c85 VM |
208 | (include "itanium1.md") |
209 | (include "itanium2.md") | |
210 | ||
c65ebc55 JW |
211 | \f |
212 | ;; :::::::::::::::::::: | |
213 | ;; :: | |
214 | ;; :: Moves | |
215 | ;; :: | |
216 | ;; :::::::::::::::::::: | |
217 | ||
f2f90c63 RH |
218 | ;; Set of a single predicate register. This is only used to implement |
219 | ;; pr-to-pr move and complement. | |
220 | ||
221 | (define_insn "*movcci" | |
222 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
223 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
224 | "" | |
225 | "@ | |
226 | cmp.ne %0, p0 = r0, r0 | |
227 | cmp.eq %0, p0 = r0, r0 | |
228 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 229 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
230 | (set_attr "predicable" "no")]) |
231 | ||
232 | (define_insn "movbi" | |
b6fb7d46 JW |
233 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
234 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
235 | "" |
236 | "@ | |
237 | cmp.ne %0, %I0 = r0, r0 | |
238 | cmp.eq %0, %I0 = r0, r0 | |
239 | # | |
240 | # | |
241 | tbit.nz %0, %I0 = %1, 0 | |
242 | adds %0 = %1, r0 | |
243 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
244 | st1%Q0 %0 = %1%P0 |
245 | mov %0 = %1" | |
388092d5 AB |
246 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu") |
247 | (set_attr "speculable1" "yes") | |
248 | (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")]) | |
f2f90c63 RH |
249 | |
250 | (define_split | |
251 | [(set (match_operand:BI 0 "register_operand" "") | |
252 | (match_operand:BI 1 "register_operand" ""))] | |
253 | "reload_completed | |
254 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
255 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
256 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
257 | (set (match_dup 0) (const_int 1))) | |
258 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
259 | (set (match_dup 0) (const_int 0)))] | |
260 | "") | |
261 | ||
262 | (define_split | |
263 | [(set (match_operand:BI 0 "register_operand" "") | |
264 | (match_operand:BI 1 "register_operand" ""))] | |
265 | "reload_completed | |
266 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
267 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
268 | [(set (match_dup 2) (match_dup 4)) | |
269 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 270 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
271 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
272 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
273 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
274 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
275 | ||
c65ebc55 JW |
276 | (define_expand "movqi" |
277 | [(set (match_operand:QI 0 "general_operand" "") | |
278 | (match_operand:QI 1 "general_operand" ""))] | |
279 | "" | |
c65ebc55 | 280 | { |
7b6e506e RH |
281 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
282 | if (!op1) | |
283 | DONE; | |
284 | operands[1] = op1; | |
1d5d7a21 | 285 | }) |
c65ebc55 | 286 | |
388092d5 | 287 | (define_insn "movqi_internal" |
4b983fdc RH |
288 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
289 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 290 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 291 | "@ |
13da91fd | 292 | mov %0 = %r1 |
c65ebc55 JW |
293 | addl %0 = %1, r0 |
294 | ld1%O1 %0 = %1%P1 | |
13da91fd | 295 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 296 | getf.sig %0 = %1 |
13da91fd RH |
297 | setf.sig %0 = %r1 |
298 | mov %0 = %1" | |
388092d5 AB |
299 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
300 | (set_attr "speculable1" "yes") | |
301 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
302 | |
303 | (define_expand "movhi" | |
304 | [(set (match_operand:HI 0 "general_operand" "") | |
305 | (match_operand:HI 1 "general_operand" ""))] | |
306 | "" | |
c65ebc55 | 307 | { |
7b6e506e RH |
308 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
309 | if (!op1) | |
310 | DONE; | |
311 | operands[1] = op1; | |
1d5d7a21 | 312 | }) |
c65ebc55 | 313 | |
388092d5 | 314 | (define_insn "movhi_internal" |
4b983fdc RH |
315 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
316 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 317 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 318 | "@ |
13da91fd | 319 | mov %0 = %r1 |
c65ebc55 JW |
320 | addl %0 = %1, r0 |
321 | ld2%O1 %0 = %1%P1 | |
13da91fd | 322 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 323 | getf.sig %0 = %1 |
13da91fd RH |
324 | setf.sig %0 = %r1 |
325 | mov %0 = %1" | |
388092d5 AB |
326 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
327 | (set_attr "speculable1" "yes") | |
328 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
329 | |
330 | (define_expand "movsi" | |
331 | [(set (match_operand:SI 0 "general_operand" "") | |
332 | (match_operand:SI 1 "general_operand" ""))] | |
333 | "" | |
c65ebc55 | 334 | { |
7b6e506e RH |
335 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
336 | if (!op1) | |
337 | DONE; | |
338 | operands[1] = op1; | |
1d5d7a21 | 339 | }) |
c65ebc55 | 340 | |
388092d5 | 341 | (define_insn "movsi_internal" |
4e483a22 JB |
342 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d") |
343 | (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))] | |
aebf2462 | 344 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 345 | "@ |
13da91fd | 346 | mov %0 = %r1 |
c65ebc55 | 347 | addl %0 = %1, r0 |
4e483a22 | 348 | addp4 %0 = %1 - 0x100000000, r0 |
c65ebc55 JW |
349 | movl %0 = %1 |
350 | ld4%O1 %0 = %1%P1 | |
13da91fd | 351 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 352 | getf.sig %0 = %1 |
13da91fd | 353 | setf.sig %0 = %r1 |
97e242b0 RH |
354 | mov %0 = %1 |
355 | mov %0 = %1 | |
356 | mov %0 = %r1" | |
1d5d7a21 | 357 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
388092d5 AB |
358 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m") |
359 | (set_attr "speculable1" "yes") | |
360 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")]) | |
c65ebc55 JW |
361 | |
362 | (define_expand "movdi" | |
363 | [(set (match_operand:DI 0 "general_operand" "") | |
364 | (match_operand:DI 1 "general_operand" ""))] | |
365 | "" | |
c65ebc55 | 366 | { |
7b6e506e RH |
367 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
368 | if (!op1) | |
369 | DONE; | |
370 | operands[1] = op1; | |
1d5d7a21 | 371 | }) |
c65ebc55 | 372 | |
388092d5 | 373 | (define_insn "movdi_internal" |
4b983fdc | 374 | [(set (match_operand:DI 0 "destination_operand" |
4e483a22 | 375 | "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 376 | (match_operand:DI 1 "move_operand" |
4e483a22 | 377 | "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 378 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
379 | { |
380 | static const char * const alt[] = { | |
1d5d7a21 RH |
381 | "%,mov %0 = %r1", |
382 | "%,addl %0 = %1, r0", | |
4e483a22 | 383 | "%,addp4 %0 = %1 - 0x100000000, r0", |
1d5d7a21 RH |
384 | "%,movl %0 = %1", |
385 | "%,ld8%O1 %0 = %1%P1", | |
386 | "%,st8%Q0 %0 = %r1%P0", | |
387 | "%,getf.sig %0 = %1", | |
388 | "%,setf.sig %0 = %r1", | |
389 | "%,mov %0 = %1", | |
390 | "%,ldf8 %0 = %1%P1", | |
391 | "%,stf8 %0 = %1%P0", | |
392 | "%,mov %0 = %1", | |
393 | "%,mov %0 = %r1", | |
394 | "%,mov %0 = %1", | |
395 | "%,mov %0 = %1", | |
396 | "%,mov %0 = %1", | |
397 | "%,mov %0 = %1", | |
398 | "mov %0 = pr", | |
399 | "mov pr = %1, -1" | |
9b7bf67d RH |
400 | }; |
401 | ||
e820471b NS |
402 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
403 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
404 | |
405 | return alt[which_alternative]; | |
1d5d7a21 | 406 | } |
388092d5 AB |
407 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr") |
408 | (set_attr "speculable1" "yes") | |
409 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")]) | |
c65ebc55 | 410 | |
3abcb3a7 | 411 | (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI]) |
f90b7a5a | 412 | (define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")]) |
3abcb3a7 | 413 | (define_mode_iterator MODE_FOR_EXTEND [QI HI SI]) |
048d0d36 MK |
414 | |
415 | (define_mode_attr output_a [ | |
416 | (BI "ld1.a %0 = %1%P1") | |
417 | (QI "ld1.a %0 = %1%P1") | |
418 | (HI "ld2.a %0 = %1%P1") | |
419 | (SI "ld4.a %0 = %1%P1") | |
420 | (DI | |
421 | "@ | |
422 | ld8.a %0 = %1%P1 | |
423 | ldf8.a %0 = %1%P1") | |
424 | (SF | |
425 | "@ | |
426 | ldfs.a %0 = %1%P1 | |
427 | ld4.a %0 = %1%P1") | |
428 | (DF | |
429 | "@ | |
430 | ldfd.a %0 = %1%P1 | |
431 | ld8.a %0 = %1%P1") | |
432 | (XF "ldfe.a %0 = %1%P1") | |
433 | (TI "ldfp8.a %X0 = %1%P1")]) | |
434 | ||
435 | (define_mode_attr output_s [ | |
436 | (BI "ld1.s %0 = %1%P1") | |
437 | (QI "ld1.s %0 = %1%P1") | |
438 | (HI "ld2.s %0 = %1%P1") | |
439 | (SI "ld4.s %0 = %1%P1") | |
440 | (DI | |
441 | "@ | |
442 | ld8.s %0 = %1%P1 | |
443 | ldf8.s %0 = %1%P1") | |
444 | (SF | |
445 | "@ | |
446 | ldfs.s %0 = %1%P1 | |
447 | ld4.s %0 = %1%P1") | |
448 | (DF | |
449 | "@ | |
450 | ldfd.s %0 = %1%P1 | |
451 | ld8.s %0 = %1%P1") | |
452 | (XF "ldfe.s %0 = %1%P1") | |
453 | (TI "ldfp8.s %X0 = %1%P1")]) | |
454 | ||
455 | (define_mode_attr output_sa [ | |
456 | (BI "ld1.sa %0 = %1%P1") | |
457 | (QI "ld1.sa %0 = %1%P1") | |
458 | (HI "ld2.sa %0 = %1%P1") | |
459 | (SI "ld4.sa %0 = %1%P1") | |
460 | (DI | |
461 | "@ | |
462 | ld8.sa %0 = %1%P1 | |
463 | ldf8.sa %0 = %1%P1") | |
464 | (SF | |
465 | "@ | |
466 | ldfs.sa %0 = %1%P1 | |
467 | ld4.sa %0 = %1%P1") | |
468 | (DF | |
469 | "@ | |
470 | ldfd.sa %0 = %1%P1 | |
471 | ld8.sa %0 = %1%P1") | |
472 | (XF "ldfe.sa %0 = %1%P1") | |
473 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
474 | ||
475 | (define_mode_attr output_c_clr [ | |
476 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
477 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
478 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
479 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
480 | (DI | |
481 | "@ | |
482 | ld8.c.clr%O1 %0 = %1%P1 | |
483 | ldf8.c.clr %0 = %1%P1") | |
484 | (SF | |
485 | "@ | |
486 | ldfs.c.clr %0 = %1%P1 | |
487 | ld4.c.clr%O1 %0 = %1%P1") | |
488 | (DF | |
489 | "@ | |
490 | ldfd.c.clr %0 = %1%P1 | |
491 | ld8.c.clr%O1 %0 = %1%P1") | |
492 | (XF "ldfe.c.clr %0 = %1%P1") | |
493 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
494 | ||
388092d5 AB |
495 | (define_mode_attr output_c_nc [ |
496 | (BI "ld1.c.nc%O1 %0 = %1%P1") | |
497 | (QI "ld1.c.nc%O1 %0 = %1%P1") | |
498 | (HI "ld2.c.nc%O1 %0 = %1%P1") | |
499 | (SI "ld4.c.nc%O1 %0 = %1%P1") | |
500 | (DI | |
501 | "@ | |
502 | ld8.c.nc%O1 %0 = %1%P1 | |
503 | ldf8.c.nc %0 = %1%P1") | |
504 | (SF | |
505 | "@ | |
506 | ldfs.c.nc %0 = %1%P1 | |
507 | ld4.c.nc%O1 %0 = %1%P1") | |
508 | (DF | |
509 | "@ | |
510 | ldfd.c.nc %0 = %1%P1 | |
511 | ld8.c.nc%O1 %0 = %1%P1") | |
512 | (XF "ldfe.c.nc %0 = %1%P1") | |
513 | (TI "ldfp8.c.nc %X0 = %1%P1")]) | |
514 | ||
048d0d36 MK |
515 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) |
516 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
517 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
518 | ||
519 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
520 | ||
f6ec1d11 MK |
521 | ;; Define register predicate prefix. |
522 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 523 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
524 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
525 | ||
526 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
527 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
528 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
529 | ||
530 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
531 | ||
532 | (define_insn "mov<mode>_advanced" | |
533 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
534 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
535 | "ia64_move_ok (operands[0], operands[1])" | |
536 | "<output_a>" | |
537 | [(set_attr "itanium_class" "<ld_class>") | |
538 | (set_attr "data_speculative" "<attr_yes>")]) | |
539 | ||
540 | (define_insn "zero_extend<mode>di2_advanced" | |
541 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
542 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
543 | "" | |
544 | "<output_a>" | |
545 | [(set_attr "itanium_class" "<ld_class>") | |
546 | (set_attr "data_speculative" "<attr_yes>")]) | |
547 | ||
548 | (define_insn "mov<mode>_speculative" | |
549 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
550 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
551 | "ia64_move_ok (operands[0], operands[1])" | |
552 | "<output_s>" | |
553 | [(set_attr "itanium_class" "<ld_class>") | |
554 | (set_attr "control_speculative" "<attr_yes>")]) | |
555 | ||
556 | (define_insn "zero_extend<mode>di2_speculative" | |
557 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
558 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
559 | "" | |
560 | "<output_s>" | |
561 | [(set_attr "itanium_class" "<ld_class>") | |
562 | (set_attr "control_speculative" "<attr_yes>")]) | |
563 | ||
564 | (define_insn "mov<mode>_speculative_advanced" | |
565 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
566 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
567 | "ia64_move_ok (operands[0], operands[1])" | |
568 | "<output_sa>" | |
569 | [(set_attr "itanium_class" "<ld_class>") | |
570 | (set_attr "data_speculative" "<attr_yes>") | |
571 | (set_attr "control_speculative" "<attr_yes>")]) | |
572 | ||
388092d5 AB |
573 | (define_insn "mov<mode>_speculative_a" |
574 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
575 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))] | |
576 | "ia64_move_ok (operands[0], operands[1])" | |
577 | "<output_sa>" | |
578 | [(set_attr "itanium_class" "<ld_class>") | |
579 | (set_attr "data_speculative" "<attr_yes>") | |
580 | (set_attr "control_speculative" "<attr_yes>")]) | |
581 | ||
048d0d36 MK |
582 | (define_insn "zero_extend<mode>di2_speculative_advanced" |
583 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
584 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
585 | "" | |
586 | "<output_sa>" | |
587 | [(set_attr "itanium_class" "<ld_class>") | |
588 | (set_attr "data_speculative" "<attr_yes>") | |
589 | (set_attr "control_speculative" "<attr_yes>")]) | |
590 | ||
388092d5 AB |
591 | (define_insn "zero_extend<mode>di2_speculative_a" |
592 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
593 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))] | |
594 | "" | |
595 | "<output_sa>" | |
596 | [(set_attr "itanium_class" "<ld_class>") | |
597 | (set_attr "data_speculative" "<attr_yes>") | |
598 | (set_attr "control_speculative" "<attr_yes>")]) | |
599 | ||
048d0d36 MK |
600 | (define_insn "mov<mode>_clr" |
601 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
602 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
603 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
604 | (match_dup 0)))] | |
605 | "ia64_move_ok (operands[0], operands[1])" | |
606 | "<output_c_clr>" | |
607 | [(set_attr "itanium_class" "<ld_class>") | |
608 | (set_attr "check_load" "<attr_yes>")]) | |
609 | ||
388092d5 AB |
610 | (define_insn "mov<mode>_nc" |
611 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
612 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
613 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
614 | (match_dup 0)))] | |
615 | "ia64_move_ok (operands[0], operands[1])" | |
616 | "<output_c_nc>" | |
617 | [(set_attr "itanium_class" "<ld_class>") | |
618 | (set_attr "check_load" "<attr_yes>")]) | |
619 | ||
048d0d36 MK |
620 | (define_insn "zero_extend<mode>di2_clr" |
621 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
622 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
623 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
624 | (match_dup 0)))] | |
625 | "" | |
626 | "<output_c_clr>" | |
627 | [(set_attr "itanium_class" "<ld_class>") | |
628 | (set_attr "check_load" "<attr_yes>")]) | |
629 | ||
388092d5 AB |
630 | (define_insn "zero_extend<mode>di2_nc" |
631 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
632 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
633 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
634 | (match_dup 0)))] | |
635 | "" | |
636 | "<output_c_nc>" | |
637 | [(set_attr "itanium_class" "<ld_class>") | |
638 | (set_attr "check_load" "<attr_yes>")]) | |
639 | ||
048d0d36 MK |
640 | (define_insn "advanced_load_check_clr_<mode>" |
641 | [(set (pc) | |
642 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
643 | (pc) | |
644 | (label_ref (match_operand 1 "" ""))))] | |
645 | "" | |
646 | "chk.a.clr %0, %l1" | |
647 | [(set_attr "itanium_class" "<chka_class>")]) | |
648 | ||
388092d5 AB |
649 | (define_insn "advanced_load_check_nc_<mode>" |
650 | [(set (pc) | |
651 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0)) | |
652 | (pc) | |
653 | (label_ref (match_operand 1 "" ""))))] | |
654 | "" | |
655 | "chk.a.clr %0, %l1" | |
656 | [(set_attr "itanium_class" "<chka_class>")]) | |
657 | ||
048d0d36 MK |
658 | (define_insn "speculation_check_<mode>" |
659 | [(set (pc) | |
660 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
661 | (pc) | |
662 | (label_ref (match_operand 1 "" ""))))] | |
663 | "" | |
664 | "chk.s %0, %l1" | |
665 | [(set_attr "itanium_class" "<chks_class>")]) | |
666 | ||
9b7bf67d | 667 | (define_split |
21515593 RH |
668 | [(set (match_operand 0 "register_operand" "") |
669 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 670 | "reload_completed" |
9b7bf67d | 671 | [(const_int 0)] |
9b7bf67d | 672 | { |
5e6c8b64 RH |
673 | if (ia64_expand_load_address (operands[0], operands[1])) |
674 | DONE; | |
675 | else | |
676 | FAIL; | |
1d5d7a21 | 677 | }) |
9b7bf67d | 678 | |
c65ebc55 | 679 | (define_expand "load_fptr" |
5e6c8b64 RH |
680 | [(set (match_operand:DI 0 "register_operand" "") |
681 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
682 | (set (match_dup 0) (match_dup 3))] | |
683 | "reload_completed" | |
c65ebc55 | 684 | { |
5e6c8b64 RH |
685 | operands[2] = pic_offset_table_rtx; |
686 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 687 | }) |
c65ebc55 JW |
688 | |
689 | (define_insn "*load_fptr_internal1" | |
690 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 691 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 692 | "reload_completed" |
c65ebc55 | 693 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 694 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
695 | |
696 | (define_insn "load_gprel" | |
697 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 698 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 699 | "reload_completed" |
c65ebc55 | 700 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 701 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 702 | |
5e6c8b64 | 703 | (define_insn "*gprel64_offset" |
59da9a7d JW |
704 | [(set (match_operand:DI 0 "register_operand" "=r") |
705 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 706 | "reload_completed" |
59da9a7d | 707 | "movl %0 = @gprel(%1)" |
52e12ad0 | 708 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
709 | |
710 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
711 | [(set (match_operand:DI 0 "register_operand" "") |
712 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
713 | (set (match_dup 0) | |
714 | (plus:DI (match_dup 2) (match_dup 0)))] | |
715 | "reload_completed" | |
ec039e3c | 716 | { |
5e6c8b64 | 717 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 718 | }) |
59da9a7d | 719 | |
af1e5518 RH |
720 | ;; This is used as a placeholder for the return address during early |
721 | ;; compilation. We won't know where we've placed this until during | |
722 | ;; reload, at which point it can wind up in b0, a general register, | |
723 | ;; or memory. The only safe destination under these conditions is a | |
724 | ;; general register. | |
725 | ||
726 | (define_insn_and_split "*movdi_ret_addr" | |
727 | [(set (match_operand:DI 0 "register_operand" "=r") | |
728 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
729 | "" | |
730 | "#" | |
731 | "reload_completed" | |
732 | [(const_int 0)] | |
733 | { | |
734 | ia64_split_return_addr_rtx (operands[0]); | |
735 | DONE; | |
736 | } | |
737 | [(set_attr "itanium_class" "ialu")]) | |
738 | ||
ef1ecf87 | 739 | (define_insn "*load_symptr_high" |
c65ebc55 | 740 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
741 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
742 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 743 | "reload_completed" |
ef1ecf87 RH |
744 | { |
745 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
746 | return "%,addl %0 = @ltoffx(%1), %2"; | |
747 | else | |
748 | return "%,addl %0 = @ltoff(%1), %2"; | |
749 | } | |
52e12ad0 | 750 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 751 | |
ef1ecf87 RH |
752 | (define_insn "*load_symptr_low" |
753 | [(set (match_operand:DI 0 "register_operand" "=r") | |
754 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
755 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 756 | "reload_completed" |
ef1ecf87 RH |
757 | { |
758 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
759 | return "%,ld8.mov %0 = [%1], %2"; | |
760 | else | |
761 | return "%,ld8 %0 = [%1]"; | |
762 | } | |
763 | [(set_attr "itanium_class" "ld")]) | |
764 | ||
5e6c8b64 | 765 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 766 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 767 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 768 | UNSPEC_DTPMOD))] |
7b6e506e | 769 | "" |
5e6c8b64 RH |
770 | "#" |
771 | "reload_completed" | |
772 | [(set (match_dup 0) | |
773 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
774 | (match_dup 2))) | |
775 | (set (match_dup 0) (match_dup 3))] | |
776 | { | |
777 | operands[2] = pic_offset_table_rtx; | |
778 | operands[3] = gen_const_mem (DImode, operands[0]); | |
779 | }) | |
7b6e506e | 780 | |
5e6c8b64 | 781 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 782 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 783 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
784 | UNSPEC_LTOFF_DTPMOD) |
785 | (match_operand:DI 2 "register_operand" "a")))] | |
786 | "reload_completed" | |
787 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
788 | [(set_attr "itanium_class" "ialu")]) |
789 | ||
790 | (define_expand "load_dtprel" | |
791 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 792 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
793 | UNSPEC_DTPREL))] |
794 | "" | |
795 | "") | |
796 | ||
797 | (define_insn "*load_dtprel64" | |
798 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 799 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
800 | UNSPEC_DTPREL))] |
801 | "TARGET_TLS64" | |
802 | "movl %0 = @dtprel(%1)" | |
803 | [(set_attr "itanium_class" "long_i")]) | |
804 | ||
805 | (define_insn "*load_dtprel22" | |
806 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 807 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
808 | UNSPEC_DTPREL))] |
809 | "" | |
810 | "addl %0 = @dtprel(%1), r0" | |
811 | [(set_attr "itanium_class" "ialu")]) | |
812 | ||
5e6c8b64 RH |
813 | (define_insn_and_split "*load_dtprel_gd" |
814 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 815 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
816 | UNSPEC_DTPREL))] |
817 | "" | |
818 | "#" | |
819 | "reload_completed" | |
820 | [(set (match_dup 0) | |
821 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
822 | (match_dup 2))) | |
823 | (set (match_dup 0) (match_dup 3))] | |
824 | { | |
825 | operands[2] = pic_offset_table_rtx; | |
826 | operands[3] = gen_const_mem (DImode, operands[0]); | |
827 | }) | |
828 | ||
829 | (define_insn "*load_ltoff_dtprel" | |
830 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 831 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
832 | UNSPEC_LTOFF_DTPREL) |
833 | (match_operand:DI 2 "register_operand" "a")))] | |
834 | "" | |
835 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
836 | [(set_attr "itanium_class" "ialu")]) | |
837 | ||
7b6e506e RH |
838 | (define_expand "add_dtprel" |
839 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 840 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
841 | UNSPEC_DTPREL) |
842 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
843 | "!TARGET_TLS64" |
844 | "") | |
845 | ||
846 | (define_insn "*add_dtprel14" | |
847 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 848 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
849 | UNSPEC_DTPREL) |
850 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 851 | "TARGET_TLS14" |
5e6c8b64 | 852 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
853 | [(set_attr "itanium_class" "ialu")]) |
854 | ||
855 | (define_insn "*add_dtprel22" | |
856 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 857 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
858 | UNSPEC_DTPREL) |
859 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 860 | "TARGET_TLS22" |
5e6c8b64 | 861 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
862 | [(set_attr "itanium_class" "ialu")]) |
863 | ||
864 | (define_expand "load_tprel" | |
865 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 866 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
867 | UNSPEC_TPREL))] |
868 | "" | |
869 | "") | |
870 | ||
871 | (define_insn "*load_tprel64" | |
872 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 873 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
874 | UNSPEC_TPREL))] |
875 | "TARGET_TLS64" | |
876 | "movl %0 = @tprel(%1)" | |
877 | [(set_attr "itanium_class" "long_i")]) | |
878 | ||
879 | (define_insn "*load_tprel22" | |
880 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 881 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
882 | UNSPEC_TPREL))] |
883 | "" | |
884 | "addl %0 = @tprel(%1), r0" | |
885 | [(set_attr "itanium_class" "ialu")]) | |
886 | ||
5e6c8b64 RH |
887 | (define_insn_and_split "*load_tprel_ie" |
888 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 889 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
890 | UNSPEC_TPREL))] |
891 | "" | |
892 | "#" | |
893 | "reload_completed" | |
894 | [(set (match_dup 0) | |
895 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
896 | (match_dup 2))) | |
897 | (set (match_dup 0) (match_dup 3))] | |
898 | { | |
899 | operands[2] = pic_offset_table_rtx; | |
900 | operands[3] = gen_const_mem (DImode, operands[0]); | |
901 | }) | |
902 | ||
903 | (define_insn "*load_ltoff_tprel" | |
904 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 905 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
906 | UNSPEC_LTOFF_TPREL) |
907 | (match_operand:DI 2 "register_operand" "a")))] | |
908 | "" | |
909 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
910 | [(set_attr "itanium_class" "ialu")]) | |
911 | ||
7b6e506e RH |
912 | (define_expand "add_tprel" |
913 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 914 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
915 | UNSPEC_TPREL) |
916 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
917 | "!TARGET_TLS64" |
918 | "") | |
919 | ||
920 | (define_insn "*add_tprel14" | |
921 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 922 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
923 | UNSPEC_TPREL) |
924 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 925 | "TARGET_TLS14" |
5e6c8b64 | 926 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
927 | [(set_attr "itanium_class" "ialu")]) |
928 | ||
929 | (define_insn "*add_tprel22" | |
930 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 931 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
932 | UNSPEC_TPREL) |
933 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 934 | "TARGET_TLS22" |
5e6c8b64 | 935 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
936 | [(set_attr "itanium_class" "ialu")]) |
937 | ||
3f622353 | 938 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
939 | ;; around to play with the second word. However, in order to avoid a |
940 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
941 | ;; in ia64_split_tmode_move. | |
3f622353 | 942 | (define_expand "movti" |
2ffe0e02 ZW |
943 | [(set (match_operand:TI 0 "general_operand" "") |
944 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 945 | "" |
3f622353 | 946 | { |
7b6e506e RH |
947 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
948 | if (!op1) | |
949 | DONE; | |
950 | operands[1] = op1; | |
1d5d7a21 | 951 | }) |
3f622353 | 952 | |
388092d5 | 953 | (define_insn_and_split "movti_internal" |
b6fb7d46 JW |
954 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
955 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 956 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
957 | "@ |
958 | # | |
959 | # | |
960 | ldfp8 %X0 = %1%P1 | |
961 | # | |
962 | #" | |
963 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 964 | [(const_int 0)] |
3f622353 | 965 | { |
f57fc998 | 966 | ia64_split_tmode_move (operands); |
3f622353 | 967 | DONE; |
1d5d7a21 | 968 | } |
388092d5 AB |
969 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown") |
970 | (set_attr "speculable1" "yes") | |
971 | (set_attr "speculable2" "no, no, yes, no, no")]) | |
e314e331 | 972 | |
c65ebc55 JW |
973 | ;; Floating Point Moves |
974 | ;; | |
975 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 976 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
977 | |
978 | (define_expand "movsf" | |
979 | [(set (match_operand:SF 0 "general_operand" "") | |
980 | (match_operand:SF 1 "general_operand" ""))] | |
981 | "" | |
c65ebc55 | 982 | { |
7b6e506e RH |
983 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
984 | if (!op1) | |
985 | DONE; | |
986 | operands[1] = op1; | |
1d5d7a21 | 987 | }) |
c65ebc55 | 988 | |
388092d5 | 989 | (define_insn "movsf_internal" |
735b94a7 SE |
990 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
991 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 992 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 993 | "@ |
1d5d7a21 RH |
994 | mov %0 = %F1 |
995 | ldfs %0 = %1%P1 | |
996 | stfs %0 = %F1%P0 | |
997 | getf.s %0 = %F1 | |
998 | setf.s %0 = %1 | |
999 | mov %0 = %1 | |
1000 | ld4%O1 %0 = %1%P1 | |
735b94a7 SE |
1001 | st4%Q0 %0 = %1%P0 |
1002 | movl %0 = %G1" | |
1003 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1004 | (set_attr "speculable1" "yes") |
735b94a7 | 1005 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 JW |
1006 | |
1007 | (define_expand "movdf" | |
1008 | [(set (match_operand:DF 0 "general_operand" "") | |
1009 | (match_operand:DF 1 "general_operand" ""))] | |
1010 | "" | |
c65ebc55 | 1011 | { |
7b6e506e RH |
1012 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1013 | if (!op1) | |
1014 | DONE; | |
1015 | operands[1] = op1; | |
1d5d7a21 | 1016 | }) |
c65ebc55 | 1017 | |
388092d5 | 1018 | (define_insn "movdf_internal" |
735b94a7 SE |
1019 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
1020 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 1021 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1022 | "@ |
1d5d7a21 RH |
1023 | mov %0 = %F1 |
1024 | ldfd %0 = %1%P1 | |
1025 | stfd %0 = %F1%P0 | |
1026 | getf.d %0 = %F1 | |
1027 | setf.d %0 = %1 | |
1028 | mov %0 = %1 | |
1029 | ld8%O1 %0 = %1%P1 | |
735b94a7 SE |
1030 | st8%Q0 %0 = %1%P0 |
1031 | movl %0 = %G1" | |
1032 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1033 | (set_attr "speculable1" "yes") |
735b94a7 | 1034 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 | 1035 | |
3f622353 RH |
1036 | ;; With no offsettable memory references, we've got to have a scratch |
1037 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1038 | (define_expand "movxf" |
1039 | [(set (match_operand:XF 0 "general_operand" "") | |
1040 | (match_operand:XF 1 "general_operand" ""))] | |
1041 | "" | |
e5bde68a | 1042 | { |
4de67c26 JM |
1043 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
1044 | DONE; | |
1d5d7a21 | 1045 | }) |
e5bde68a | 1046 | |
3b572406 | 1047 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1048 | |
388092d5 | 1049 | (define_insn "movxf_internal" |
78d8e0f9 ZW |
1050 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1051 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1052 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1053 | "@ |
1d5d7a21 RH |
1054 | mov %0 = %F1 |
1055 | ldfe %0 = %1%P1 | |
1056 | stfe %0 = %F1%P0" | |
388092d5 AB |
1057 | [(set_attr "itanium_class" "fmisc,fld,stf") |
1058 | (set_attr "speculable1" "yes") | |
1059 | (set_attr "speculable2" "no, yes,no")]) | |
f57fc998 | 1060 | |
4de67c26 JM |
1061 | ;; Same as for movxf, but for RFmode. |
1062 | (define_expand "movrf" | |
1063 | [(set (match_operand:RF 0 "general_operand" "") | |
1064 | (match_operand:RF 1 "general_operand" ""))] | |
1065 | "" | |
1066 | { | |
1067 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
1068 | DONE; | |
1069 | }) | |
1070 | ||
1071 | (define_insn "*movrf_internal" | |
1072 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
1073 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
1074 | "ia64_move_ok (operands[0], operands[1])" | |
1075 | "@ | |
1076 | mov %0 = %F1 | |
1077 | ldf.fill %0 = %1%P1 | |
1078 | stf.spill %0 = %F1%P0" | |
1079 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
1080 | ||
f57fc998 | 1081 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 1082 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1083 | (define_expand "movtf" |
2ffe0e02 ZW |
1084 | [(set (match_operand:TF 0 "general_operand" "") |
1085 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1086 | "" |
1087 | { | |
1088 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1089 | if (!op1) | |
1090 | DONE; | |
1091 | operands[1] = op1; | |
1092 | }) | |
1093 | ||
1094 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 1095 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 1096 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1097 | "ia64_move_ok (operands[0], operands[1])" |
1098 | "#" | |
1099 | "reload_completed" | |
1100 | [(const_int 0)] | |
1101 | { | |
1102 | ia64_split_tmode_move (operands); | |
1103 | DONE; | |
1104 | } | |
1105 | [(set_attr "itanium_class" "unknown") | |
1106 | (set_attr "predicable" "no")]) | |
1107 | ||
c65ebc55 JW |
1108 | \f |
1109 | ;; :::::::::::::::::::: | |
1110 | ;; :: | |
1111 | ;; :: Conversions | |
1112 | ;; :: | |
1113 | ;; :::::::::::::::::::: | |
1114 | ||
1115 | ;; Signed conversions from a smaller integer to a larger integer | |
1116 | ||
1117 | (define_insn "extendqidi2" | |
0551c32d RH |
1118 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1119 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1120 | "" |
1121 | "sxt1 %0 = %1" | |
52e12ad0 | 1122 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1123 | |
1124 | (define_insn "extendhidi2" | |
0551c32d RH |
1125 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1126 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1127 | "" |
1128 | "sxt2 %0 = %1" | |
52e12ad0 | 1129 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1130 | |
1131 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1132 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1133 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1134 | "" |
1135 | "@ | |
1136 | sxt4 %0 = %1 | |
aebf2462 | 1137 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1138 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1139 | |
1140 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1141 | ||
1142 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1143 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1144 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1145 | "" |
1146 | "@ | |
1147 | zxt1 %0 = %1 | |
1148 | ld1%O1 %0 = %1%P1" | |
388092d5 AB |
1149 | [(set_attr "itanium_class" "xtd,ld") |
1150 | (set_attr "speculable1" "yes") | |
1151 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1152 | |
1153 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1154 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1155 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1156 | "" |
1157 | "@ | |
1158 | zxt2 %0 = %1 | |
1159 | ld2%O1 %0 = %1%P1" | |
388092d5 AB |
1160 | [(set_attr "itanium_class" "xtd,ld") |
1161 | (set_attr "speculable1" "yes") | |
1162 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1163 | |
1164 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1165 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1166 | (zero_extend:DI |
655f2eb9 | 1167 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1168 | "" |
1169 | "@ | |
d3f6e07b | 1170 | addp4 %0 = %1, r0 |
c65ebc55 | 1171 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1172 | fmix.r %0 = f0, %1" |
388092d5 AB |
1173 | [(set_attr "itanium_class" "ialu,ld,fmisc") |
1174 | (set_attr "speculable1" "yes") | |
1175 | (set_attr "speculable2" "no, yes,no")]) | |
c65ebc55 JW |
1176 | |
1177 | ;; Convert between floating point types of different sizes. | |
1178 | ||
640cea5f JW |
1179 | ;; At first glance, it would appear that emitting fnorm for an extending |
1180 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1181 | ;; correctly only if the input is properly rounded for its type. In | |
1182 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1183 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1184 | ;; have to emit an fnorm. | |
1185 | ||
e8e20f18 RH |
1186 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1187 | ;; when we can. Should probably use a scheme like has been proposed | |
1188 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1189 | ;; would let combine merge the thing into adjacent insns. See also how the |
1190 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1191 | ;; se_register_operand. | |
c65ebc55 | 1192 | |
640cea5f JW |
1193 | (define_insn "extendsfdf2" |
1194 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
6adb807e | 1195 | (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1196 | "" |
6adb807e | 1197 | "fnorm.d %0 = %F1" |
640cea5f | 1198 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1199 | |
02befdf4 ZW |
1200 | (define_insn "extendsfxf2" |
1201 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1202 | (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1203 | "" |
6adb807e | 1204 | "fnorm %0 = %F1" |
640cea5f | 1205 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1206 | |
02befdf4 ZW |
1207 | (define_insn "extenddfxf2" |
1208 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1209 | (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1210 | "" |
6adb807e | 1211 | "fnorm %0 = %F1" |
640cea5f | 1212 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1213 | |
c65ebc55 | 1214 | (define_insn "truncdfsf2" |
0551c32d | 1215 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1216 | (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1217 | "" |
6adb807e | 1218 | "fnorm.s %0 = %F1" |
52e12ad0 | 1219 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1220 | |
02befdf4 | 1221 | (define_insn "truncxfsf2" |
0551c32d | 1222 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1223 | (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1224 | "" |
6adb807e | 1225 | "fnorm.s %0 = %F1" |
52e12ad0 | 1226 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1227 | |
02befdf4 | 1228 | (define_insn "truncxfdf2" |
0551c32d | 1229 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1230 | (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1231 | "" |
6adb807e | 1232 | "fnorm.d %0 = %F1" |
52e12ad0 | 1233 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1234 | |
1235 | ;; Convert between signed integer types and floating point. | |
1236 | ||
02befdf4 ZW |
1237 | (define_insn "floatdixf2" |
1238 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1239 | (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1240 | "" |
6adb807e | 1241 | "fcvt.xf %0 = %F1" |
52e12ad0 | 1242 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1243 | |
1244 | (define_insn "fix_truncsfdi2" | |
0551c32d | 1245 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1246 | (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1247 | "" |
6adb807e | 1248 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1249 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1250 | |
1251 | (define_insn "fix_truncdfdi2" | |
0551c32d | 1252 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1253 | (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1254 | "" |
6adb807e | 1255 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1256 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1257 | |
02befdf4 | 1258 | (define_insn "fix_truncxfdi2" |
0551c32d | 1259 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1260 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1261 | "" |
6adb807e | 1262 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1263 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1264 | |
02befdf4 | 1265 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1266 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1267 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) |
655f2eb9 | 1268 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1269 | "" |
6adb807e | 1270 | "fcvt.fx.trunc.s%2 %0 = %F1" |
52e12ad0 | 1271 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1272 | |
c65ebc55 JW |
1273 | ;; Convert between unsigned integer types and floating point. |
1274 | ||
1275 | (define_insn "floatunsdisf2" | |
0551c32d | 1276 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1277 | (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1278 | "" |
6adb807e | 1279 | "fcvt.xuf.s %0 = %F1" |
52e12ad0 | 1280 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1281 | |
1282 | (define_insn "floatunsdidf2" | |
0551c32d | 1283 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1284 | (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1285 | "" |
6adb807e | 1286 | "fcvt.xuf.d %0 = %F1" |
52e12ad0 | 1287 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1288 | |
02befdf4 ZW |
1289 | (define_insn "floatunsdixf2" |
1290 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1291 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1292 | "" |
6adb807e | 1293 | "fcvt.xuf %0 = %F1" |
52e12ad0 | 1294 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1295 | |
c65ebc55 | 1296 | (define_insn "fixuns_truncsfdi2" |
0551c32d | 1297 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1298 | (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1299 | "" |
6adb807e | 1300 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1301 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1302 | |
1303 | (define_insn "fixuns_truncdfdi2" | |
0551c32d | 1304 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1305 | (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1306 | "" |
6adb807e | 1307 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1308 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1309 | |
02befdf4 | 1310 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1311 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1312 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1313 | "" |
6adb807e | 1314 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1315 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1316 | |
02befdf4 | 1317 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1318 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1319 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) |
655f2eb9 | 1320 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1321 | "" |
6adb807e | 1322 | "fcvt.fxu.trunc.s%2 %0 = %F1" |
52e12ad0 | 1323 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1324 | \f |
1325 | ;; :::::::::::::::::::: | |
1326 | ;; :: | |
1327 | ;; :: Bit field extraction | |
1328 | ;; :: | |
1329 | ;; :::::::::::::::::::: | |
1330 | ||
c65ebc55 | 1331 | (define_insn "extv" |
0551c32d RH |
1332 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1333 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1334 | (match_operand:DI 2 "extr_len_operand" "n") |
1335 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1336 | "" |
1337 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1338 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1339 | |
1340 | (define_insn "extzv" | |
0551c32d RH |
1341 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1342 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1343 | (match_operand:DI 2 "extr_len_operand" "n") |
1344 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1345 | "" |
1346 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1347 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1348 | |
1349 | ;; Insert a bit field. | |
1350 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1351 | ;; Source1 can be 0 or -1. | |
1352 | ;; Source2 can be 0. | |
1353 | ||
1354 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1355 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1356 | ;; where source2 != dest. | |
1357 | ||
1358 | (define_expand "insv" | |
0551c32d | 1359 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1360 | (match_operand:DI 1 "const_int_operand" "") |
1361 | (match_operand:DI 2 "const_int_operand" "")) | |
1362 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1363 | "" | |
c65ebc55 JW |
1364 | { |
1365 | int width = INTVAL (operands[1]); | |
1366 | int shift = INTVAL (operands[2]); | |
1367 | ||
1368 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1369 | pseudo. */ | |
1370 | if (! register_operand (operands[3], DImode) | |
1371 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1372 | operands[3] = force_reg (DImode, operands[3]); | |
1373 | ||
1374 | /* If this is a single dep instruction, we have nothing to do. */ | |
1375 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1376 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1377 | { | |
1378 | /* Check for cases that can be implemented with a mix instruction. */ | |
1379 | if (width == 32 && shift == 0) | |
1380 | { | |
1381 | /* Directly generating the mix4left instruction confuses | |
1382 | optimize_bit_field in function.c. Since this is performing | |
1383 | a useful optimization, we defer generation of the complicated | |
1384 | mix4left RTL to the first splitting phase. */ | |
1385 | rtx tmp = gen_reg_rtx (DImode); | |
1386 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1387 | DONE; | |
1388 | } | |
1389 | else if (width == 32 && shift == 32) | |
1390 | { | |
1391 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1392 | DONE; | |
1393 | } | |
1394 | ||
d2ba6dcf JW |
1395 | /* We could handle remaining cases by emitting multiple dep |
1396 | instructions. | |
1397 | ||
1398 | If we need more than two dep instructions then we lose. A 6 | |
1399 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1400 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1401 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1402 | only one function unit that can execute dep and shr immed. | |
1403 | ||
1404 | If we only need two dep instruction, then we still lose. | |
1405 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1406 | the unnecessary mov, this is still undesirable because it will be | |
1407 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1408 | function unit. */ | |
1409 | ||
c65ebc55 JW |
1410 | FAIL; |
1411 | ||
1412 | #if 0 | |
1413 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1414 | for now. */ | |
1415 | while (width > 16) | |
1416 | { | |
1417 | rtx tmp; | |
1418 | ||
1419 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1420 | operands[3])); | |
1421 | shift += 16; | |
1422 | width -= 16; | |
1423 | tmp = gen_reg_rtx (DImode); | |
1424 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1425 | operands[3] = tmp; | |
1426 | } | |
1427 | operands[1] = GEN_INT (width); | |
1428 | operands[2] = GEN_INT (shift); | |
1429 | #endif | |
1430 | } | |
1d5d7a21 | 1431 | }) |
c65ebc55 JW |
1432 | |
1433 | (define_insn "*insv_internal" | |
0551c32d | 1434 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1435 | (match_operand:DI 1 "const_int_operand" "n") |
1436 | (match_operand:DI 2 "const_int_operand" "n")) | |
1437 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1438 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1439 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1440 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1441 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1442 | |
43a88a8c | 1443 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1444 | (define_insn "*shladdp4_internal" |
1445 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1446 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1447 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1448 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1449 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1450 | "shladdp4 %0 = %1, %2, r0" | |
1451 | [(set_attr "itanium_class" "ialu")]) | |
1452 | ||
041f25e6 | 1453 | (define_insn "*depz_internal" |
0551c32d RH |
1454 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1455 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1456 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1457 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1458 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1459 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1460 | { |
1461 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1462 | return "%,dep.z %0 = %1, %2, %3"; |
1463 | } | |
52e12ad0 | 1464 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1465 | |
c65ebc55 | 1466 | (define_insn "shift_mix4left" |
0551c32d | 1467 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1468 | (const_int 32) (const_int 0)) |
0551c32d RH |
1469 | (match_operand:DI 1 "gr_register_operand" "r")) |
1470 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1471 | "" |
1472 | "#" | |
52e12ad0 | 1473 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1474 | |
c65ebc55 JW |
1475 | (define_split |
1476 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1477 | (const_int 32) (const_int 0)) | |
1478 | (match_operand:DI 1 "register_operand" "")) | |
1479 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1480 | "" |
c65ebc55 JW |
1481 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1482 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1483 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1484 | "operands[3] = operands[2];") | |
1485 | ||
1486 | (define_insn "*mix4left" | |
0551c32d | 1487 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1488 | (const_int 32) (const_int 0)) |
0551c32d | 1489 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1490 | (const_int 32)))] |
1491 | "" | |
1492 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1493 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1494 | |
1495 | (define_insn "mix4right" | |
0551c32d | 1496 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1497 | (const_int 32) (const_int 32)) |
0551c32d | 1498 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1499 | "" |
1500 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1501 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1502 | |
1503 | ;; This is used by the rotrsi3 pattern. | |
1504 | ||
1505 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1506 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1507 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1508 | (ashift:DI (zero_extend:DI | |
1509 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1510 | (const_int 32))))] |
1511 | "" | |
fa9a44e8 | 1512 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1513 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1514 | |
1515 | \f | |
1516 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1517 | ;; :: |
27a9b99d | 1518 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1519 | ;; :: |
1520 | ;; :::::::::::::::::::: | |
1521 | ||
1522 | (define_insn_and_split "andbi3" | |
1523 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1524 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1525 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1526 | "" | |
1527 | "@ | |
1528 | # | |
1529 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1530 | and %0 = %2, %1" | |
1531 | "reload_completed | |
1532 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1533 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1534 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1535 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1536 | (match_dup 0))))] | |
1537 | "" | |
52e12ad0 | 1538 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1539 | |
1540 | (define_insn_and_split "*andcmbi3" | |
1541 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1542 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1543 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1544 | "" | |
1545 | "@ | |
1546 | # | |
967603ef | 1547 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1548 | andcm %0 = %2, %1" |
1549 | "reload_completed | |
1550 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1551 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1552 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1553 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1554 | (match_dup 0))))] | |
1555 | "" | |
52e12ad0 | 1556 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1557 | |
1558 | (define_insn_and_split "iorbi3" | |
1559 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1560 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1561 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1562 | "" | |
1563 | "@ | |
1564 | # | |
1565 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1566 | or %0 = %2, %1" | |
1567 | "reload_completed | |
1568 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1569 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1570 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1571 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1572 | (match_dup 0))))] | |
1573 | "" | |
52e12ad0 | 1574 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1575 | |
1576 | (define_insn_and_split "*iorcmbi3" | |
1577 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1578 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1579 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1580 | "" | |
1581 | "@ | |
1582 | # | |
967603ef | 1583 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1584 | "reload_completed |
1585 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1586 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1587 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1588 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1589 | (match_dup 0))))] | |
1590 | "" | |
52e12ad0 | 1591 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1592 | |
1593 | (define_insn "one_cmplbi2" | |
1594 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1595 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1596 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1597 | "" | |
1598 | "@ | |
1599 | tbit.z %0, %I0 = %1, 0 | |
1600 | xor %0 = 1, %1 | |
1601 | # | |
1602 | #" | |
52e12ad0 | 1603 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1604 | |
1605 | (define_split | |
1606 | [(set (match_operand:BI 0 "register_operand" "") | |
1607 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1608 | (clobber (match_scratch:BI 2 ""))] | |
1609 | "reload_completed | |
1610 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1611 | && rtx_equal_p (operands[0], operands[1])" |
1612 | [(set (match_dup 4) (match_dup 3)) | |
1613 | (set (match_dup 0) (const_int 1)) | |
1614 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1615 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1616 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1617 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1618 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1619 | ||
1620 | (define_split | |
1621 | [(set (match_operand:BI 0 "register_operand" "") | |
1622 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1623 | (clobber (match_scratch:BI 2 ""))] | |
1624 | "reload_completed | |
1625 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1626 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1627 | && ! rtx_equal_p (operands[0], operands[1])" | |
1628 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1629 | (set (match_dup 0) (const_int 0))) | |
1630 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1631 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1632 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1633 | "") |
1634 | ||
1635 | (define_insn "*cmpsi_and_0" | |
1636 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1637 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1638 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1639 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1640 | (match_operand:BI 1 "register_operand" "0")))] | |
1641 | "" | |
1642 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1643 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1644 | |
1645 | (define_insn "*cmpsi_and_1" | |
1646 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1647 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1648 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1649 | (const_int 0)]) | |
1650 | (match_operand:BI 1 "register_operand" "0")))] | |
1651 | "" | |
1652 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1653 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1654 | |
1655 | (define_insn "*cmpsi_andnot_0" | |
1656 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1657 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1658 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1659 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1660 | (match_operand:BI 1 "register_operand" "0")))] | |
1661 | "" | |
1662 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1663 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1664 | |
1665 | (define_insn "*cmpsi_andnot_1" | |
1666 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1667 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1668 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1669 | (const_int 0)])) | |
1670 | (match_operand:BI 1 "register_operand" "0")))] | |
1671 | "" | |
1672 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1673 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1674 | |
1675 | (define_insn "*cmpdi_and_0" | |
1676 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1677 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1678 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1679 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1680 | (match_operand:BI 1 "register_operand" "0")))] | |
1681 | "" | |
1682 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1683 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1684 | |
1685 | (define_insn "*cmpdi_and_1" | |
1686 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1687 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1688 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1689 | (const_int 0)]) | |
1690 | (match_operand:BI 1 "register_operand" "0")))] | |
1691 | "" | |
1692 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1693 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1694 | |
1695 | (define_insn "*cmpdi_andnot_0" | |
1696 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1697 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1698 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1699 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1700 | (match_operand:BI 1 "register_operand" "0")))] | |
1701 | "" | |
1702 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1703 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1704 | |
1705 | (define_insn "*cmpdi_andnot_1" | |
1706 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1707 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1708 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1709 | (const_int 0)])) | |
1710 | (match_operand:BI 1 "register_operand" "0")))] | |
1711 | "" | |
1712 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1713 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1714 | |
1715 | (define_insn "*tbit_and_0" | |
1716 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1717 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1718 | (const_int 1)) | |
1719 | (const_int 0)) | |
c77e04ae | 1720 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1721 | "" |
1722 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1723 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1724 | |
1725 | (define_insn "*tbit_and_1" | |
1726 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1727 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1728 | (const_int 1)) | |
1729 | (const_int 0)) | |
c77e04ae | 1730 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1731 | "" |
1732 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1733 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1734 | |
1735 | (define_insn "*tbit_and_2" | |
1736 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1737 | (and:BI (ne:BI (zero_extract:DI | |
1738 | (match_operand:DI 1 "gr_register_operand" "r") | |
1739 | (const_int 1) | |
5d48891e | 1740 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1741 | (const_int 0)) |
1742 | (match_operand:BI 3 "register_operand" "0")))] | |
1743 | "" | |
1744 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1745 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1746 | |
1747 | (define_insn "*tbit_and_3" | |
1748 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1749 | (and:BI (eq:BI (zero_extract:DI | |
1750 | (match_operand:DI 1 "gr_register_operand" "r") | |
1751 | (const_int 1) | |
5d48891e | 1752 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1753 | (const_int 0)) |
1754 | (match_operand:BI 3 "register_operand" "0")))] | |
1755 | "" | |
1756 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1757 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1758 | |
1759 | (define_insn "*cmpsi_or_0" | |
1760 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1761 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1762 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1763 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1764 | (match_operand:BI 1 "register_operand" "0")))] | |
1765 | "" | |
1766 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1767 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1768 | |
1769 | (define_insn "*cmpsi_or_1" | |
1770 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1771 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1772 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1773 | (const_int 0)]) | |
1774 | (match_operand:BI 1 "register_operand" "0")))] | |
1775 | "" | |
1776 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1777 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1778 | |
1779 | (define_insn "*cmpsi_orcm_0" | |
1780 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1781 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1782 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1783 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1784 | (match_operand:BI 1 "register_operand" "0")))] | |
1785 | "" | |
1786 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1787 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1788 | |
1789 | (define_insn "*cmpsi_orcm_1" | |
1790 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1791 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1792 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1793 | (const_int 0)])) | |
1794 | (match_operand:BI 1 "register_operand" "0")))] | |
1795 | "" | |
1796 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1797 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1798 | |
1799 | (define_insn "*cmpdi_or_0" | |
1800 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1801 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1802 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1803 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1804 | (match_operand:BI 1 "register_operand" "0")))] | |
1805 | "" | |
1806 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1807 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1808 | |
1809 | (define_insn "*cmpdi_or_1" | |
1810 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1811 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1812 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1813 | (const_int 0)]) | |
1814 | (match_operand:BI 1 "register_operand" "0")))] | |
1815 | "" | |
1816 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1817 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1818 | |
1819 | (define_insn "*cmpdi_orcm_0" | |
1820 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1821 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1822 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1823 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1824 | (match_operand:BI 1 "register_operand" "0")))] | |
1825 | "" | |
1826 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1827 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1828 | |
1829 | (define_insn "*cmpdi_orcm_1" | |
1830 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1831 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1832 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1833 | (const_int 0)])) | |
1834 | (match_operand:BI 1 "register_operand" "0")))] | |
1835 | "" | |
1836 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1837 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1838 | |
1839 | (define_insn "*tbit_or_0" | |
1840 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1841 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1842 | (const_int 1)) | |
1843 | (const_int 0)) | |
c77e04ae | 1844 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1845 | "" |
1846 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1847 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1848 | |
1849 | (define_insn "*tbit_or_1" | |
1850 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1851 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1852 | (const_int 1)) | |
1853 | (const_int 0)) | |
c77e04ae | 1854 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1855 | "" |
1856 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1857 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1858 | |
1859 | (define_insn "*tbit_or_2" | |
1860 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1861 | (ior:BI (ne:BI (zero_extract:DI | |
1862 | (match_operand:DI 1 "gr_register_operand" "r") | |
1863 | (const_int 1) | |
5d48891e | 1864 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1865 | (const_int 0)) |
1866 | (match_operand:BI 3 "register_operand" "0")))] | |
1867 | "" | |
1868 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1869 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1870 | |
1871 | (define_insn "*tbit_or_3" | |
1872 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1873 | (ior:BI (eq:BI (zero_extract:DI | |
1874 | (match_operand:DI 1 "gr_register_operand" "r") | |
1875 | (const_int 1) | |
5d48891e | 1876 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1877 | (const_int 0)) |
1878 | (match_operand:BI 3 "register_operand" "0")))] | |
1879 | "" | |
1880 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1881 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1882 | |
1883 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1884 | ||
1885 | (define_split | |
1886 | [(set (match_operand:BI 0 "register_operand" "") | |
1887 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1888 | (const_int 0)) | |
1889 | (match_operand:DI 3 "register_operand" "")) | |
1890 | (const_int 0)))] | |
1891 | "" | |
1892 | [(set (match_dup 0) | |
1893 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1894 | (match_dup 2)))] | |
1895 | "") | |
1896 | ||
1897 | (define_split | |
1898 | [(set (match_operand:BI 0 "register_operand" "") | |
1899 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1900 | (const_int 0)) | |
1901 | (match_operand:DI 3 "register_operand" "")) | |
1902 | (const_int 0)))] | |
1903 | "" | |
1904 | [(set (match_dup 0) | |
1905 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1906 | (match_dup 2))) | |
1907 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1908 | (clobber (scratch))])] | |
1909 | "") | |
1910 | ||
1911 | (define_split | |
1912 | [(set (match_operand:BI 0 "register_operand" "") | |
1913 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1914 | (const_int 0)) | |
1915 | (match_operand:DI 3 "register_operand" "")) | |
1916 | (const_int 0)))] | |
1917 | "" | |
1918 | [(set (match_dup 0) | |
1919 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1920 | (match_dup 2)))] | |
1921 | "") | |
1922 | ||
1923 | (define_split | |
1924 | [(set (match_operand:BI 0 "register_operand" "") | |
1925 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1926 | (const_int 0)) | |
1927 | (match_operand:DI 3 "register_operand" "")) | |
1928 | (const_int 0)))] | |
1929 | "" | |
1930 | [(set (match_dup 0) | |
1931 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1932 | (match_dup 2))) | |
1933 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1934 | (clobber (scratch))])] | |
1935 | "") | |
1936 | ||
1937 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1938 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1939 | ;; nothing bad happens to the comparisons in the meantime. | |
1940 | ;; | |
1941 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1942 | ;; that we're doing height reduction. | |
1943 | ; | |
1944 | ;(define_insn_and_split "" | |
1945 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1946 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1947 | ; [(match_operand 2 "" "") | |
1948 | ; (match_operand 3 "" "")]) | |
1949 | ; (match_operator:BI 4 "comparison_operator" | |
1950 | ; [(match_operand 5 "" "") | |
1951 | ; (match_operand 6 "" "")])) | |
1952 | ; (match_dup 0)))] | |
1953 | ; "flag_schedule_insns" | |
1954 | ; "#" | |
1955 | ; "" | |
1956 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1957 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1958 | ; "") | |
1959 | ; | |
1960 | ;(define_insn_and_split "" | |
1961 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1962 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1963 | ; [(match_operand 2 "" "") | |
1964 | ; (match_operand 3 "" "")]) | |
1965 | ; (match_operator:BI 4 "comparison_operator" | |
1966 | ; [(match_operand 5 "" "") | |
1967 | ; (match_operand 6 "" "")])) | |
1968 | ; (match_dup 0)))] | |
1969 | ; "flag_schedule_insns" | |
1970 | ; "#" | |
1971 | ; "" | |
1972 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1973 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1974 | ; "") | |
1975 | ; | |
1976 | ;(define_split | |
1977 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1978 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1979 | ; [(match_operand 2 "" "") | |
1980 | ; (match_operand 3 "" "")]) | |
1981 | ; (match_operand:BI 7 "register_operand" "")) | |
1982 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1983 | ; [(match_operand 5 "" "") | |
1984 | ; (match_operand 6 "" "")]) | |
1985 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1986 | ; "" | |
1987 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1988 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1989 | ; (match_dup 0)))] | |
1990 | ; "") | |
1991 | ; | |
1992 | ;(define_split | |
1993 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1994 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1995 | ; [(match_operand 2 "" "") | |
1996 | ; (match_operand 3 "" "")]) | |
1997 | ; (match_operand:BI 7 "register_operand" "")) | |
1998 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1999 | ; [(match_operand 5 "" "") | |
2000 | ; (match_operand 6 "" "")]) | |
2001 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2002 | ; "" | |
2003 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2004 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2005 | ; (match_dup 0)))] | |
2006 | ; "") | |
2007 | ||
2008 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2009 | ;; Note that we'll have already split the predicate copy, which | |
2010 | ;; is kind of a pain, but oh well. | |
2011 | ||
2012 | (define_peephole2 | |
2013 | [(set (match_operand:BI 0 "register_operand" "") | |
2014 | (match_operand:BI 1 "comparison_operator" "")) | |
2015 | (set (match_operand:CCI 2 "register_operand" "") | |
2016 | (match_operand:CCI 3 "register_operand" "")) | |
2017 | (set (match_operand:CCI 4 "register_operand" "") | |
2018 | (match_operand:CCI 5 "register_operand" "")) | |
2019 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2020 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2021 | "REGNO (operands[3]) == REGNO (operands[0]) |
2022 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2023 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2024 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2025 | [(set (match_dup 0) (match_dup 1)) | |
2026 | (set (match_dup 6) (match_dup 7))] | |
2027 | "operands[7] = copy_rtx (operands[1]);") | |
2028 | \f | |
2029 | ;; :::::::::::::::::::: | |
2030 | ;; :: | |
27a9b99d | 2031 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
2032 | ;; :: |
2033 | ;; :::::::::::::::::::: | |
2034 | ||
2035 | (define_insn "mulhi3" | |
2036 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2037 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2038 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2039 | "" | |
2a7ffc85 | 2040 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2041 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2042 | |
2043 | \f | |
2044 | ;; :::::::::::::::::::: | |
c65ebc55 | 2045 | ;; :: |
27a9b99d | 2046 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
2047 | ;; :: |
2048 | ;; :::::::::::::::::::: | |
2049 | ||
058557c4 | 2050 | (define_insn "addsi3" |
0551c32d RH |
2051 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2052 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2053 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2054 | "" |
2055 | "@ | |
1d5d7a21 RH |
2056 | add %0 = %1, %2 |
2057 | adds %0 = %2, %1 | |
2058 | addl %0 = %2, %1" | |
52e12ad0 | 2059 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2060 | |
2061 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2062 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2063 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2064 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2065 | (const_int 1)))] |
2066 | "" | |
2067 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2068 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2069 | |
5527bf14 | 2070 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2071 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2072 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2073 | (const_int 2)) |
2074 | (const_int 1)))] | |
2075 | "" | |
2076 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2077 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2078 | |
058557c4 | 2079 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2080 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2081 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2082 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2083 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2084 | "" |
058557c4 | 2085 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2086 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2087 | |
058557c4 | 2088 | (define_insn "subsi3" |
0551c32d RH |
2089 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2090 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2091 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2092 | "" |
2093 | "sub %0 = %1, %2" | |
52e12ad0 | 2094 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2095 | |
2096 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2097 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2098 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2099 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2100 | "" |
2101 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2102 | [(set_attr "itanium_class" "ialu")]) |
2103 | ||
2104 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2105 | |
058557c4 | 2106 | (define_insn "mulsi3" |
0551c32d | 2107 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2108 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2109 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2110 | "" |
aebf2462 | 2111 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2112 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2113 | |
655f2eb9 | 2114 | (define_insn "maddsi4" |
11a13704 RH |
2115 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2116 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2117 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2118 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2119 | "" | |
aebf2462 | 2120 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2121 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2122 | |
058557c4 | 2123 | (define_insn "negsi2" |
0551c32d RH |
2124 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2125 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2126 | "" |
2127 | "sub %0 = r0, %1" | |
52e12ad0 | 2128 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2129 | |
2130 | (define_expand "abssi2" | |
2131 | [(set (match_dup 2) | |
f2f90c63 | 2132 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2133 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2134 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2135 | (neg:SI (match_dup 1)) |
2136 | (match_dup 1)))] | |
c65ebc55 | 2137 | "" |
1d5d7a21 | 2138 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2139 | |
2140 | (define_expand "sminsi3" | |
2141 | [(set (match_dup 3) | |
f2f90c63 | 2142 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2143 | (match_operand:SI 2 "gr_register_operand" ""))) |
2144 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2145 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2146 | (match_dup 2) (match_dup 1)))] |
2147 | "" | |
1d5d7a21 | 2148 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2149 | |
2150 | (define_expand "smaxsi3" | |
2151 | [(set (match_dup 3) | |
f2f90c63 | 2152 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2153 | (match_operand:SI 2 "gr_register_operand" ""))) |
2154 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2155 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2156 | (match_dup 1) (match_dup 2)))] |
2157 | "" | |
1d5d7a21 | 2158 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2159 | |
2160 | (define_expand "uminsi3" | |
2161 | [(set (match_dup 3) | |
f2f90c63 | 2162 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2163 | (match_operand:SI 2 "gr_register_operand" ""))) |
2164 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2165 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2166 | (match_dup 2) (match_dup 1)))] |
2167 | "" | |
1d5d7a21 | 2168 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2169 | |
2170 | (define_expand "umaxsi3" | |
2171 | [(set (match_dup 3) | |
f2f90c63 | 2172 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2173 | (match_operand:SI 2 "gr_register_operand" ""))) |
2174 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2175 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2176 | (match_dup 1) (match_dup 2)))] |
2177 | "" | |
1d5d7a21 | 2178 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2179 | |
655f2eb9 RH |
2180 | (define_expand "divsi3" |
2181 | [(set (match_operand:SI 0 "register_operand" "") | |
2182 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2183 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2184 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2185 | { |
9aec7fb4 | 2186 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2187 | |
02befdf4 | 2188 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2189 | op0_di = gen_reg_rtx (DImode); |
2190 | ||
2191 | if (CONSTANT_P (operands[1])) | |
2192 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2193 | op1_xf = gen_reg_rtx (XFmode); |
2194 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2195 | |
2196 | if (CONSTANT_P (operands[2])) | |
2197 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2198 | op2_xf = gen_reg_rtx (XFmode); |
2199 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2200 | |
2201 | /* 2^-34 */ | |
9aec7fb4 SE |
2202 | twon34_exp = gen_reg_rtx (DImode); |
2203 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2204 | twon34 = gen_reg_rtx (XFmode); | |
2205 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2206 | |
85199961 L |
2207 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2208 | CONST1_RTX (SImode))); | |
2209 | ||
02befdf4 | 2210 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2211 | |
02befdf4 | 2212 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2213 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2214 | DONE; | |
1d5d7a21 | 2215 | }) |
655f2eb9 RH |
2216 | |
2217 | (define_expand "modsi3" | |
2218 | [(set (match_operand:SI 0 "register_operand" "") | |
2219 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2220 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2221 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2222 | { |
2223 | rtx op2_neg, op1_di, div; | |
2224 | ||
2225 | div = gen_reg_rtx (SImode); | |
2226 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2227 | ||
2228 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2229 | ||
2230 | /* This is a trick to get us to reuse the value that we're sure to | |
2231 | have already copied to the FP regs. */ | |
2232 | op1_di = gen_reg_rtx (DImode); | |
2233 | convert_move (op1_di, operands[1], 0); | |
2234 | ||
2235 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2236 | gen_lowpart (SImode, op1_di))); | |
2237 | DONE; | |
1d5d7a21 | 2238 | }) |
655f2eb9 RH |
2239 | |
2240 | (define_expand "udivsi3" | |
2241 | [(set (match_operand:SI 0 "register_operand" "") | |
2242 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2243 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2244 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2245 | { |
9aec7fb4 | 2246 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2247 | |
02befdf4 | 2248 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2249 | op0_di = gen_reg_rtx (DImode); |
2250 | ||
2251 | if (CONSTANT_P (operands[1])) | |
2252 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2253 | op1_xf = gen_reg_rtx (XFmode); |
2254 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2255 | |
2256 | if (CONSTANT_P (operands[2])) | |
2257 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2258 | op2_xf = gen_reg_rtx (XFmode); |
2259 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2260 | |
2261 | /* 2^-34 */ | |
9aec7fb4 SE |
2262 | twon34_exp = gen_reg_rtx (DImode); |
2263 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2264 | twon34 = gen_reg_rtx (XFmode); | |
2265 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2266 | |
85199961 L |
2267 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2268 | CONST1_RTX (SImode))); | |
2269 | ||
02befdf4 | 2270 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2271 | |
02befdf4 | 2272 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2273 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2274 | DONE; | |
1d5d7a21 | 2275 | }) |
655f2eb9 RH |
2276 | |
2277 | (define_expand "umodsi3" | |
2278 | [(set (match_operand:SI 0 "register_operand" "") | |
2279 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2280 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2281 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2282 | { |
2283 | rtx op2_neg, op1_di, div; | |
2284 | ||
2285 | div = gen_reg_rtx (SImode); | |
2286 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2287 | ||
2288 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2289 | ||
2290 | /* This is a trick to get us to reuse the value that we're sure to | |
2291 | have already copied to the FP regs. */ | |
2292 | op1_di = gen_reg_rtx (DImode); | |
2293 | convert_move (op1_di, operands[1], 1); | |
2294 | ||
2295 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2296 | gen_lowpart (SImode, op1_di))); | |
2297 | DONE; | |
1d5d7a21 | 2298 | }) |
655f2eb9 RH |
2299 | |
2300 | (define_insn_and_split "divsi3_internal" | |
02befdf4 | 2301 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2302 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2303 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2304 | (clobber (match_scratch:XF 4 "=&f")) |
2305 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2306 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2307 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2308 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2309 | "#" |
2310 | "&& reload_completed" | |
07acc7b3 JW |
2311 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2312 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2313 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2314 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2315 | (use (const_int 1))]) |
2316 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2317 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2318 | (use (const_int 1))])) |
2319 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2320 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2321 | (minus:XF (match_dup 7) |
2322 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2323 | (use (const_int 1))])) |
2324 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2325 | (parallel [(set (match_dup 4) | |
02befdf4 | 2326 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2327 | (match_dup 4))) |
2328 | (use (const_int 1))])) | |
2329 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2330 | (parallel [(set (match_dup 5) | |
02befdf4 | 2331 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2332 | (match_dup 3))) |
2333 | (use (const_int 1))])) | |
2334 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2335 | (parallel [(set (match_dup 0) | |
02befdf4 | 2336 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2337 | (match_dup 4))) |
2338 | (use (const_int 1))])) | |
2339 | ] | |
02befdf4 | 2340 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2341 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2342 | \f |
2343 | ;; :::::::::::::::::::: | |
2344 | ;; :: | |
27a9b99d | 2345 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2346 | ;; :: |
2347 | ;; :::::::::::::::::::: | |
2348 | ||
2349 | (define_insn "adddi3" | |
0551c32d RH |
2350 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2351 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2352 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2353 | "" |
2354 | "@ | |
1d5d7a21 RH |
2355 | add %0 = %1, %2 |
2356 | adds %0 = %2, %1 | |
2357 | addl %0 = %2, %1" | |
52e12ad0 | 2358 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2359 | |
2360 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2361 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2362 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2363 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2364 | (const_int 1)))] |
2365 | "" | |
2366 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2367 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2368 | |
5527bf14 RH |
2369 | ;; This has some of the same problems as shladd. We let the shladd |
2370 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2371 | ;; a register, but not more ugliness here. | |
2372 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2373 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2374 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2375 | (const_int 2)) |
2376 | (const_int 1)))] | |
2377 | "" | |
2378 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2379 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2380 | |
c65ebc55 | 2381 | (define_insn "subdi3" |
0551c32d RH |
2382 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2383 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2384 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2385 | "" |
2386 | "sub %0 = %1, %2" | |
52e12ad0 | 2387 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2388 | |
2389 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2390 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2391 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2392 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2393 | "" |
2394 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2395 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2396 | |
cee58bc0 RH |
2397 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2398 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2399 | (define_insn "muldi3" |
0551c32d | 2400 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2401 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2402 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2403 | "" |
aebf2462 | 2404 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2405 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2406 | |
2407 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2408 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2409 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2410 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2411 | ;; here so that it will be present just in case register elimination gives us | |
2412 | ;; the funny result. | |
2413 | ||
2414 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2415 | ||
2416 | ;; ??? Maybe we should change how adds are canonicalized. | |
2417 | ||
655f2eb9 | 2418 | (define_insn "madddi4" |
0551c32d | 2419 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2420 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2421 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2422 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2423 | (clobber (match_scratch:DI 4 "=X"))] |
2424 | "" | |
aebf2462 | 2425 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2426 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2427 | |
2428 | ;; This can be created by register elimination if operand3 of shladd is an | |
2429 | ;; eliminable register or has reg_equiv_constant set. | |
2430 | ||
2431 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2432 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2433 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2434 | ;; incorrectly. |
2435 | ||
655f2eb9 | 2436 | (define_insn "*madddi4_elim" |
c65ebc55 | 2437 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2438 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2439 | (match_operand:DI 2 "register_operand" "f")) | |
2440 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2441 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2442 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2443 | "reload_in_progress" |
2444 | "#" | |
52e12ad0 | 2445 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2446 | |
c65ebc55 JW |
2447 | (define_split |
2448 | [(set (match_operand:DI 0 "register_operand" "") | |
2449 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2450 | (match_operand:DI 2 "register_operand" "")) | |
2451 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2452 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2453 | (clobber (match_scratch:DI 5 ""))] |
2454 | "reload_completed" | |
2455 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2456 | (match_dup 3))) | |
2457 | (clobber (match_dup 0))]) | |
c65ebc55 | 2458 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2459 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2460 | "") | |
2461 | ||
c65ebc55 | 2462 | (define_insn "smuldi3_highpart" |
0551c32d | 2463 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2464 | (truncate:DI |
2465 | (lshiftrt:TI | |
0551c32d | 2466 | (mult:TI (sign_extend:TI |
6adb807e | 2467 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2468 | (sign_extend:TI |
6adb807e | 2469 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2470 | (const_int 64))))] |
2471 | "" | |
6adb807e | 2472 | "xmpy.h %0 = %F1, %F2" |
52e12ad0 | 2473 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2474 | |
2475 | (define_insn "umuldi3_highpart" | |
0551c32d | 2476 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2477 | (truncate:DI |
2478 | (lshiftrt:TI | |
0551c32d | 2479 | (mult:TI (zero_extend:TI |
6adb807e | 2480 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2481 | (zero_extend:TI |
6adb807e | 2482 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2483 | (const_int 64))))] |
2484 | "" | |
6adb807e | 2485 | "xmpy.hu %0 = %F1, %F2" |
52e12ad0 | 2486 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2487 | |
2488 | (define_insn "negdi2" | |
0551c32d RH |
2489 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2490 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2491 | "" |
2492 | "sub %0 = r0, %1" | |
52e12ad0 | 2493 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2494 | |
2495 | (define_expand "absdi2" | |
2496 | [(set (match_dup 2) | |
f2f90c63 | 2497 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2498 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2499 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2500 | (neg:DI (match_dup 1)) |
2501 | (match_dup 1)))] | |
c65ebc55 | 2502 | "" |
1d5d7a21 | 2503 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2504 | |
2505 | (define_expand "smindi3" | |
2506 | [(set (match_dup 3) | |
f2f90c63 | 2507 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2508 | (match_operand:DI 2 "gr_register_operand" ""))) |
2509 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2510 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2511 | (match_dup 2) (match_dup 1)))] |
2512 | "" | |
1d5d7a21 | 2513 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2514 | |
2515 | (define_expand "smaxdi3" | |
2516 | [(set (match_dup 3) | |
f2f90c63 | 2517 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2518 | (match_operand:DI 2 "gr_register_operand" ""))) |
2519 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2520 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2521 | (match_dup 1) (match_dup 2)))] |
2522 | "" | |
1d5d7a21 | 2523 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2524 | |
2525 | (define_expand "umindi3" | |
2526 | [(set (match_dup 3) | |
f2f90c63 | 2527 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2528 | (match_operand:DI 2 "gr_register_operand" ""))) |
2529 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2530 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2531 | (match_dup 2) (match_dup 1)))] |
2532 | "" | |
1d5d7a21 | 2533 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2534 | |
2535 | (define_expand "umaxdi3" | |
2536 | [(set (match_dup 3) | |
f2f90c63 | 2537 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2538 | (match_operand:DI 2 "gr_register_operand" ""))) |
2539 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2540 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2541 | (match_dup 1) (match_dup 2)))] |
2542 | "" | |
1d5d7a21 | 2543 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2544 | |
2545 | (define_expand "ffsdi2" | |
2546 | [(set (match_dup 6) | |
f2f90c63 | 2547 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2548 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2549 | (set (match_dup 5) (const_int 0)) | |
2550 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2551 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2552 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2553 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2554 | (match_dup 5) (match_dup 4)))] |
2555 | "" | |
c65ebc55 JW |
2556 | { |
2557 | operands[2] = gen_reg_rtx (DImode); | |
2558 | operands[3] = gen_reg_rtx (DImode); | |
2559 | operands[4] = gen_reg_rtx (DImode); | |
2560 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2561 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2562 | }) |
c65ebc55 | 2563 | |
c407570a RH |
2564 | (define_expand "ctzdi2" |
2565 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2566 | (const_int -1))) | |
2567 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2568 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2569 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2570 | (popcount:DI (match_dup 4)))] | |
2571 | "" | |
2572 | { | |
2573 | operands[2] = gen_reg_rtx (DImode); | |
2574 | operands[3] = gen_reg_rtx (DImode); | |
2575 | operands[4] = gen_reg_rtx (DImode); | |
2576 | }) | |
2577 | ||
c407570a RH |
2578 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2579 | (define_expand "clzdi2" | |
2580 | [(set (match_dup 2) | |
6adb807e | 2581 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))) |
c407570a RH |
2582 | (set (match_dup 3) |
2583 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2584 | (set (match_dup 4) (const_int 65598)) | |
2585 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2586 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2587 | "" |
c407570a | 2588 | { |
02befdf4 | 2589 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2590 | operands[3] = gen_reg_rtx (DImode); |
2591 | operands[4] = gen_reg_rtx (DImode); | |
2592 | }) | |
2593 | ||
2594 | (define_insn "popcountdi2" | |
0551c32d | 2595 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2596 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2597 | "" |
2598 | "popcnt %0 = %1" | |
52e12ad0 | 2599 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2600 | |
ff848f0e RS |
2601 | (define_insn "bswapdi2" |
2602 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2603 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2604 | "" | |
2605 | "mux1 %0 = %1, @rev" | |
2606 | [(set_attr "itanium_class" "mmshf")]) | |
2607 | ||
02befdf4 | 2608 | (define_insn "*getf_exp_xf" |
c407570a | 2609 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6adb807e | 2610 | (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")] |
c407570a | 2611 | UNSPEC_GETF_EXP))] |
02befdf4 | 2612 | "" |
6adb807e | 2613 | "getf.exp %0 = %F1" |
c407570a RH |
2614 | [(set_attr "itanium_class" "frfr")]) |
2615 | ||
655f2eb9 RH |
2616 | (define_expand "divdi3" |
2617 | [(set (match_operand:DI 0 "register_operand" "") | |
2618 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2619 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2620 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2621 | { |
02befdf4 | 2622 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2623 | |
02befdf4 | 2624 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2625 | |
2626 | if (CONSTANT_P (operands[1])) | |
2627 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2628 | op1_xf = gen_reg_rtx (XFmode); |
2629 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2630 | |
2631 | if (CONSTANT_P (operands[2])) | |
2632 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2633 | op2_xf = gen_reg_rtx (XFmode); |
2634 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2635 | |
85199961 L |
2636 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2637 | CONST1_RTX (DImode))); | |
2638 | ||
dbdd120f | 2639 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2640 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2641 | else |
02befdf4 | 2642 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2643 | |
02befdf4 | 2644 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2645 | DONE; |
1d5d7a21 | 2646 | }) |
655f2eb9 RH |
2647 | |
2648 | (define_expand "moddi3" | |
2649 | [(set (match_operand:DI 0 "register_operand" "") | |
2650 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2651 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2652 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2653 | { |
2654 | rtx op2_neg, div; | |
2655 | ||
2656 | div = gen_reg_rtx (DImode); | |
2657 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2658 | ||
2659 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2660 | ||
2661 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2662 | DONE; | |
1d5d7a21 | 2663 | }) |
655f2eb9 RH |
2664 | |
2665 | (define_expand "udivdi3" | |
2666 | [(set (match_operand:DI 0 "register_operand" "") | |
2667 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2668 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2669 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2670 | { |
02befdf4 | 2671 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2672 | |
02befdf4 | 2673 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2674 | |
2675 | if (CONSTANT_P (operands[1])) | |
2676 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2677 | op1_xf = gen_reg_rtx (XFmode); |
2678 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2679 | |
2680 | if (CONSTANT_P (operands[2])) | |
2681 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2682 | op2_xf = gen_reg_rtx (XFmode); |
2683 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2684 | |
85199961 L |
2685 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2686 | CONST1_RTX (DImode))); | |
2687 | ||
dbdd120f | 2688 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2689 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2690 | else |
02befdf4 | 2691 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2692 | |
02befdf4 | 2693 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2694 | DONE; |
1d5d7a21 | 2695 | }) |
655f2eb9 RH |
2696 | |
2697 | (define_expand "umoddi3" | |
2698 | [(set (match_operand:DI 0 "register_operand" "") | |
2699 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2700 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2701 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2702 | { |
2703 | rtx op2_neg, div; | |
2704 | ||
2705 | div = gen_reg_rtx (DImode); | |
2706 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2707 | ||
2708 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2709 | ||
2710 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2711 | DONE; | |
1d5d7a21 | 2712 | }) |
655f2eb9 RH |
2713 | |
2714 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 | 2715 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2716 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2717 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2718 | (clobber (match_scratch:XF 3 "=&f")) |
2719 | (clobber (match_scratch:XF 4 "=&f")) | |
2720 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2721 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2722 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2723 | "#" |
2724 | "&& reload_completed" | |
07acc7b3 JW |
2725 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2726 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2727 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2728 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2729 | (use (const_int 1))]) |
2730 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2731 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2732 | (minus:XF (match_dup 7) |
2733 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2734 | (use (const_int 1))])) |
2735 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2736 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2737 | (use (const_int 1))])) |
2738 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2739 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2740 | (use (const_int 1))])) |
2741 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2742 | (parallel [(set (match_dup 4) | |
02befdf4 | 2743 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2744 | (match_dup 4))) |
2745 | (use (const_int 1))])) | |
2746 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2747 | (parallel [(set (match_dup 0) | |
02befdf4 | 2748 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2749 | (match_dup 0))) |
2750 | (use (const_int 1))])) | |
2751 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2752 | (parallel [(set (match_dup 3) | |
02befdf4 | 2753 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2754 | (match_dup 4))) |
2755 | (use (const_int 1))])) | |
2756 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2757 | (parallel [(set (match_dup 0) | |
02befdf4 | 2758 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2759 | (match_dup 0))) |
2760 | (use (const_int 1))])) | |
2761 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2762 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2763 | (minus:XF (match_dup 1) |
2764 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2765 | (use (const_int 1))])) |
2766 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2767 | (parallel [(set (match_dup 0) | |
02befdf4 | 2768 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2769 | (match_dup 3))) |
2770 | (use (const_int 1))])) | |
2771 | ] | |
02befdf4 | 2772 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2773 | [(set_attr "predicable" "no")]) |
2774 | ||
2775 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 | 2776 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2777 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2778 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2779 | (clobber (match_scratch:XF 3 "=&f")) |
2780 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2781 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2782 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2783 | "#" |
2784 | "&& reload_completed" | |
07acc7b3 JW |
2785 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2786 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2787 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2788 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2789 | (use (const_int 1))]) |
2790 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2791 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2792 | (minus:XF (match_dup 6) |
2793 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2794 | (use (const_int 1))])) |
2795 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2796 | (parallel [(set (match_dup 0) | |
02befdf4 | 2797 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2798 | (match_dup 0))) |
2799 | (use (const_int 1))])) | |
2800 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2801 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2802 | (use (const_int 1))])) |
2803 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2804 | (parallel [(set (match_dup 0) | |
02befdf4 | 2805 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2806 | (match_dup 0))) |
2807 | (use (const_int 1))])) | |
2808 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2809 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2810 | (use (const_int 1))])) |
2811 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2812 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2813 | (minus:XF (match_dup 1) |
2814 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2815 | (use (const_int 1))])) |
2816 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2817 | (parallel [(set (match_dup 0) | |
02befdf4 | 2818 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2819 | (match_dup 3))) |
2820 | (use (const_int 1))])) | |
2821 | ] | |
02befdf4 | 2822 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2823 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2824 | \f |
2825 | ;; :::::::::::::::::::: | |
2826 | ;; :: | |
27a9b99d | 2827 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2828 | ;; :: |
2829 | ;; :::::::::::::::::::: | |
2830 | ||
2831 | (define_insn "addti3" | |
2832 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2833 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2834 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2835 | (clobber (match_scratch:BI 3 "=&c"))] | |
2836 | "" | |
2837 | "#" | |
2838 | [(set_attr "itanium_class" "unknown")]) | |
2839 | ||
2840 | (define_split | |
2841 | [(set (match_operand:TI 0 "register_operand" "") | |
2842 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2843 | (match_operand:TI 2 "register_operand" ""))) | |
2844 | (clobber (match_scratch:BI 3 ""))] | |
2845 | "reload_completed" | |
2846 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2847 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2848 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2849 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2850 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2851 | (set (match_dup 4) | |
2852 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2853 | (const_int 1))))] | |
2854 | { | |
2855 | operands[4] = gen_highpart (DImode, operands[0]); | |
2856 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2857 | operands[5] = gen_highpart (DImode, operands[1]); | |
2858 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2859 | operands[6] = gen_highpart (DImode, operands[2]); | |
2860 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2861 | }) | |
2862 | ||
2863 | (define_split | |
2864 | [(set (match_operand:TI 0 "register_operand" "") | |
2865 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2866 | (match_operand:TI 2 "immediate_operand" ""))) | |
2867 | (clobber (match_scratch:BI 3 ""))] | |
2868 | "reload_completed" | |
2869 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2870 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2871 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2872 | (set (match_dup 4) | |
2873 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2874 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2875 | (set (match_dup 4) | |
2876 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2877 | { | |
2878 | operands[4] = gen_highpart (DImode, operands[0]); | |
2879 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2880 | operands[5] = gen_highpart (DImode, operands[1]); | |
2881 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2882 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2883 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2884 | }) | |
2885 | ||
2886 | (define_insn "subti3" | |
2887 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2888 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2889 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2890 | (clobber (match_scratch:BI 3 "=&c"))] | |
2891 | "" | |
2892 | "#" | |
2893 | [(set_attr "itanium_class" "unknown")]) | |
2894 | ||
2895 | (define_split | |
2896 | [(set (match_operand:TI 0 "register_operand" "") | |
2897 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2898 | (match_operand:TI 2 "register_operand" ""))) | |
2899 | (clobber (match_scratch:BI 3 "=&c"))] | |
2900 | "reload_completed" | |
2901 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2902 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2903 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2904 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2905 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2906 | (set (match_dup 4) | |
2907 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2908 | { | |
2909 | operands[4] = gen_highpart (DImode, operands[0]); | |
2910 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2911 | operands[5] = gen_highpart (DImode, operands[1]); | |
2912 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2913 | operands[6] = gen_highpart (DImode, operands[2]); | |
2914 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2915 | }) | |
2916 | ||
2917 | (define_split | |
2918 | [(set (match_operand:TI 0 "register_operand" "") | |
2919 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2920 | (match_operand:TI 2 "register_operand" ""))) | |
2921 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2922 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2923 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2924 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2925 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2926 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2927 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2928 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2929 | { | |
2930 | operands[4] = gen_highpart (DImode, operands[0]); | |
2931 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2932 | operands[5] = gen_highpart (DImode, operands[2]); | |
2933 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2934 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2935 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2936 | }) | |
2937 | ||
2938 | (define_expand "mulditi3" | |
2939 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2940 | (mult:TI (sign_extend:TI | |
6adb807e | 2941 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2942 | (sign_extend:TI |
6adb807e | 2943 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2944 | "" |
2945 | "") | |
2946 | ||
2947 | (define_insn_and_split "*mulditi3_internal" | |
2948 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2949 | (mult:TI (sign_extend:TI | |
6adb807e | 2950 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2951 | (sign_extend:TI |
6adb807e | 2952 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2953 | "" |
2954 | "#" | |
2955 | "reload_completed" | |
2956 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2957 | (set (match_dup 3) (truncate:DI | |
2958 | (lshiftrt:TI | |
2959 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2960 | (sign_extend:TI (match_dup 2))) | |
2961 | (const_int 64))))] | |
2962 | { | |
2963 | operands[3] = gen_highpart (DImode, operands[0]); | |
2964 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2965 | } | |
2966 | [(set_attr "itanium_class" "unknown")]) | |
2967 | ||
2968 | (define_expand "umulditi3" | |
2969 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2970 | (mult:TI (zero_extend:TI | |
6adb807e | 2971 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2972 | (zero_extend:TI |
6adb807e | 2973 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2974 | "" |
2975 | "") | |
2976 | ||
2977 | (define_insn_and_split "*umulditi3_internal" | |
2978 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2979 | (mult:TI (zero_extend:TI | |
6adb807e | 2980 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2981 | (zero_extend:TI |
6adb807e | 2982 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2983 | "" |
2984 | "#" | |
2985 | "reload_completed" | |
2986 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2987 | (set (match_dup 3) (truncate:DI | |
2988 | (lshiftrt:TI | |
2989 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2990 | (zero_extend:TI (match_dup 2))) | |
2991 | (const_int 64))))] | |
2992 | { | |
2993 | operands[3] = gen_highpart (DImode, operands[0]); | |
2994 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2995 | } | |
2996 | [(set_attr "itanium_class" "unknown")]) | |
2997 | ||
2998 | (define_insn_and_split "negti2" | |
2999 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
3000 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
3001 | (clobber (match_scratch:BI 2 "=&c"))] | |
3002 | "" | |
3003 | "#" | |
3004 | "reload_completed" | |
3005 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
3006 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
3007 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
3008 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
3009 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
3010 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
3011 | { | |
3012 | operands[3] = gen_highpart (DImode, operands[0]); | |
3013 | operands[0] = gen_lowpart (DImode, operands[0]); | |
3014 | operands[4] = gen_highpart (DImode, operands[1]); | |
3015 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3016 | } | |
3017 | [(set_attr "itanium_class" "unknown")]) | |
3018 | \f | |
3019 | ;; :::::::::::::::::::: | |
3020 | ;; :: | |
27a9b99d | 3021 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
3022 | ;; :: |
3023 | ;; :::::::::::::::::::: | |
3024 | ||
3025 | (define_insn "addsf3" | |
0551c32d | 3026 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3027 | (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3028 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3029 | "" |
6adb807e | 3030 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3031 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3032 | |
3033 | (define_insn "subsf3" | |
0551c32d RH |
3034 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3035 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3036 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3037 | "" |
aebf2462 | 3038 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3039 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3040 | |
3041 | (define_insn "mulsf3" | |
0551c32d | 3042 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3043 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3044 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3045 | "" |
6adb807e | 3046 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3047 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3048 | |
3049 | (define_insn "abssf2" | |
0551c32d | 3050 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3051 | (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3052 | "" |
6adb807e | 3053 | "fabs %0 = %F1" |
52e12ad0 | 3054 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3055 | |
3056 | (define_insn "negsf2" | |
0551c32d | 3057 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3058 | (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3059 | "" |
6adb807e | 3060 | "fneg %0 = %F1" |
52e12ad0 | 3061 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3062 | |
3063 | (define_insn "*nabssf2" | |
0551c32d | 3064 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3065 | (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 3066 | "" |
6adb807e | 3067 | "fnegabs %0 = %F1" |
52e12ad0 | 3068 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3069 | |
046625fa RH |
3070 | (define_insn "copysignsf3" |
3071 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3072 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3073 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3074 | UNSPEC_COPYSIGN))] | |
3075 | "" | |
3076 | "fmerge.s %0 = %F2, %F1" | |
3077 | [(set_attr "itanium_class" "fmisc")]) | |
3078 | ||
3079 | (define_insn "*ncopysignsf3" | |
3080 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3081 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3082 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3083 | UNSPEC_COPYSIGN)))] | |
3084 | "" | |
3085 | "fmerge.ns %0 = %F2, %F1" | |
3086 | [(set_attr "itanium_class" "fmisc")]) | |
3087 | ||
7ae4d8d4 | 3088 | (define_insn "sminsf3" |
0551c32d | 3089 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3090 | (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3091 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3092 | "" |
6adb807e | 3093 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3094 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3095 | |
7ae4d8d4 | 3096 | (define_insn "smaxsf3" |
0551c32d | 3097 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3098 | (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3099 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3100 | "" |
6adb807e | 3101 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3102 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3103 | |
655f2eb9 | 3104 | (define_insn "*maddsf4" |
0551c32d | 3105 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3106 | (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3107 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3108 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 3109 | "TARGET_FUSED_MADD" |
6adb807e | 3110 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3111 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3112 | |
655f2eb9 | 3113 | (define_insn "*msubsf4" |
0551c32d | 3114 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3115 | (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3116 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3117 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 3118 | "TARGET_FUSED_MADD" |
6adb807e | 3119 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3120 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3121 | |
3122 | (define_insn "*nmulsf3" | |
0551c32d | 3123 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3124 | (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3125 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3126 | "" |
6adb807e | 3127 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3128 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3129 | |
655f2eb9 | 3130 | (define_insn "*nmaddsf4" |
0551c32d | 3131 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b | 3132 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3133 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3134 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
583ca921 | 3135 | "TARGET_FUSED_MADD" |
6adb807e | 3136 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3137 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3138 | |
52ad4d7b ZW |
3139 | (define_insn "*nmaddsf4_alts" |
3140 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3141 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
6adb807e SE |
3142 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3143 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))) | |
52ad4d7b ZW |
3144 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3145 | "" | |
6adb807e | 3146 | "fnma.s.s%4 %0 = %F1, %F2, %F3" |
52ad4d7b ZW |
3147 | [(set_attr "itanium_class" "fmac")]) |
3148 | ||
26102535 RH |
3149 | (define_expand "divsf3" |
3150 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
6adb807e SE |
3151 | (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "") |
3152 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 3153 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3154 | { |
3155 | rtx insn; | |
dbdd120f | 3156 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3157 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
3158 | else | |
3159 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
3160 | emit_insn (insn); | |
3161 | DONE; | |
1d5d7a21 | 3162 | }) |
26102535 | 3163 | |
9aec7fb4 | 3164 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3165 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3166 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3167 | UNSPEC_SETF_EXP))] | |
3168 | "" | |
3169 | "setf.exp %0 = %1" | |
3170 | [(set_attr "itanium_class" "frfr")]) | |
3171 | ||
f3a83111 SE |
3172 | |
3173 | ;; Inline square root. | |
3174 | ||
b38ba463 ZW |
3175 | (define_expand "sqrtsf2" |
3176 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
6adb807e | 3177 | (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
3178 | "TARGET_INLINE_SQRT" |
3179 | { | |
3180 | rtx insn; | |
e820471b | 3181 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3182 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 3183 | else |
f3a83111 | 3184 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3185 | emit_insn (insn); |
3186 | DONE; | |
3187 | }) | |
c65ebc55 JW |
3188 | \f |
3189 | ;; :::::::::::::::::::: | |
3190 | ;; :: | |
27a9b99d | 3191 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
3192 | ;; :: |
3193 | ;; :::::::::::::::::::: | |
3194 | ||
3195 | (define_insn "adddf3" | |
0551c32d | 3196 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3197 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3198 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3199 | "" |
6adb807e | 3200 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3201 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3202 | |
26102535 RH |
3203 | (define_insn "*adddf3_trunc" |
3204 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3205 | (float_truncate:SF | |
6adb807e | 3206 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
26102535 RH |
3207 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] |
3208 | "" | |
6adb807e | 3209 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3210 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3211 | |
c65ebc55 | 3212 | (define_insn "subdf3" |
0551c32d RH |
3213 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3214 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3215 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3216 | "" |
aebf2462 | 3217 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3218 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3219 | |
26102535 RH |
3220 | (define_insn "*subdf3_trunc" |
3221 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3222 | (float_truncate:SF | |
3223 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3224 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3225 | "" | |
aebf2462 | 3226 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3227 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3228 | |
c65ebc55 | 3229 | (define_insn "muldf3" |
0551c32d | 3230 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3231 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3232 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3233 | "" |
6adb807e | 3234 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3235 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3236 | |
26102535 RH |
3237 | (define_insn "*muldf3_trunc" |
3238 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3239 | (float_truncate:SF | |
6adb807e SE |
3240 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3241 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
26102535 | 3242 | "" |
6adb807e | 3243 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3244 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3245 | |
c65ebc55 | 3246 | (define_insn "absdf2" |
0551c32d | 3247 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3248 | (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3249 | "" |
6adb807e | 3250 | "fabs %0 = %F1" |
52e12ad0 | 3251 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3252 | |
3253 | (define_insn "negdf2" | |
0551c32d | 3254 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3255 | (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3256 | "" |
6adb807e | 3257 | "fneg %0 = %F1" |
52e12ad0 | 3258 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3259 | |
3260 | (define_insn "*nabsdf2" | |
0551c32d | 3261 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3262 | (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 3263 | "" |
6adb807e | 3264 | "fnegabs %0 = %F1" |
52e12ad0 | 3265 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3266 | |
046625fa RH |
3267 | (define_insn "copysigndf3" |
3268 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3269 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3270 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3271 | UNSPEC_COPYSIGN))] | |
3272 | "" | |
3273 | "fmerge.s %0 = %F2, %F1" | |
3274 | [(set_attr "itanium_class" "fmisc")]) | |
3275 | ||
3276 | (define_insn "*ncopysigndf3" | |
3277 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3278 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3279 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3280 | UNSPEC_COPYSIGN)))] | |
3281 | "" | |
3282 | "fmerge.ns %0 = %F2, %F1" | |
3283 | [(set_attr "itanium_class" "fmisc")]) | |
3284 | ||
7ae4d8d4 | 3285 | (define_insn "smindf3" |
0551c32d | 3286 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3287 | (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3288 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3289 | "" |
6adb807e | 3290 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3291 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3292 | |
7ae4d8d4 | 3293 | (define_insn "smaxdf3" |
0551c32d | 3294 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3295 | (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3296 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3297 | "" |
6adb807e | 3298 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3299 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3300 | |
655f2eb9 | 3301 | (define_insn "*madddf4" |
0551c32d | 3302 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3303 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3304 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3305 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 3306 | "TARGET_FUSED_MADD" |
6adb807e | 3307 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3308 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3309 | |
26102535 RH |
3310 | (define_insn "*madddf4_trunc" |
3311 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3312 | (float_truncate:SF | |
6adb807e SE |
3313 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3314 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 | 3315 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
583ca921 | 3316 | "TARGET_FUSED_MADD" |
6adb807e | 3317 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3318 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3319 | |
655f2eb9 | 3320 | (define_insn "*msubdf4" |
0551c32d | 3321 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3322 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3323 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3324 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
583ca921 | 3325 | "TARGET_FUSED_MADD" |
6adb807e | 3326 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3327 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3328 | |
26102535 RH |
3329 | (define_insn "*msubdf4_trunc" |
3330 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3331 | (float_truncate:SF | |
6adb807e SE |
3332 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3333 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 | 3334 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
583ca921 | 3335 | "TARGET_FUSED_MADD" |
6adb807e | 3336 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3337 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3338 | |
c65ebc55 | 3339 | (define_insn "*nmuldf3" |
0551c32d | 3340 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3341 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3342 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3343 | "" |
6adb807e | 3344 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3345 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3346 | |
26102535 RH |
3347 | (define_insn "*nmuldf3_trunc" |
3348 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3349 | (float_truncate:SF | |
6adb807e SE |
3350 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3351 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
26102535 | 3352 | "" |
6adb807e | 3353 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3354 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3355 | |
655f2eb9 | 3356 | (define_insn "*nmadddf4" |
0551c32d | 3357 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b | 3358 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3359 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3360 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
583ca921 | 3361 | "TARGET_FUSED_MADD" |
6adb807e | 3362 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3363 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3364 | |
3365 | (define_insn "*nmadddf4_alts" | |
3366 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b | 3367 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3368 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3369 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))) | |
26102535 RH |
3370 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3371 | "" | |
6adb807e | 3372 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3373 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3374 | |
52ad4d7b | 3375 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3376 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3377 | (float_truncate:SF | |
52ad4d7b | 3378 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3379 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3380 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
583ca921 | 3381 | "TARGET_FUSED_MADD" |
6adb807e | 3382 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3383 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3384 | |
52ad4d7b ZW |
3385 | (define_insn "*nmadddf4_truncsf_alts" |
3386 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3387 | (float_truncate:SF | |
3388 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
6adb807e SE |
3389 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3390 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))) | |
52ad4d7b ZW |
3391 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3392 | "" | |
6adb807e | 3393 | "fnma.s.s%4 %0 = %F1, %F2, %F3" |
52ad4d7b ZW |
3394 | [(set_attr "itanium_class" "fmac")]) |
3395 | ||
26102535 RH |
3396 | (define_expand "divdf3" |
3397 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
6adb807e SE |
3398 | (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "") |
3399 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 3400 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3401 | { |
3402 | rtx insn; | |
dbdd120f | 3403 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3404 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3405 | else | |
3406 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3407 | emit_insn (insn); | |
3408 | DONE; | |
1d5d7a21 | 3409 | }) |
26102535 | 3410 | |
b38ba463 ZW |
3411 | ;; Inline square root. |
3412 | ||
3413 | (define_expand "sqrtdf2" | |
3414 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
6adb807e | 3415 | (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
3416 | "TARGET_INLINE_SQRT" |
3417 | { | |
3418 | rtx insn; | |
b38ba463 | 3419 | #if 0 |
e820471b | 3420 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3421 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3422 | else |
b38ba463 | 3423 | #endif |
e820471b | 3424 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3425 | emit_insn (insn); |
3426 | DONE; | |
3427 | }) | |
3f622353 RH |
3428 | \f |
3429 | ;; :::::::::::::::::::: | |
3430 | ;; :: | |
27a9b99d | 3431 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3432 | ;; :: |
3433 | ;; :::::::::::::::::::: | |
3434 | ||
02befdf4 ZW |
3435 | (define_insn "addxf3" |
3436 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3437 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3438 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3439 | "" | |
aebf2462 | 3440 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3441 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3442 | |
02befdf4 | 3443 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3444 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3445 | (float_truncate:SF | |
02befdf4 ZW |
3446 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3447 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3448 | "" | |
aebf2462 | 3449 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3450 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3451 | |
02befdf4 | 3452 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3453 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3454 | (float_truncate:DF | |
02befdf4 ZW |
3455 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3456 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3457 | "" | |
aebf2462 | 3458 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3459 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3460 | |
02befdf4 ZW |
3461 | (define_insn "subxf3" |
3462 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3463 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3464 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3465 | "" | |
aebf2462 | 3466 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3467 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3468 | |
02befdf4 | 3469 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3470 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3471 | (float_truncate:SF | |
02befdf4 ZW |
3472 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3473 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3474 | "" | |
aebf2462 | 3475 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3476 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3477 | |
02befdf4 | 3478 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3479 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3480 | (float_truncate:DF | |
02befdf4 ZW |
3481 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3482 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3483 | "" | |
aebf2462 | 3484 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3485 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3486 | |
02befdf4 ZW |
3487 | (define_insn "mulxf3" |
3488 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3489 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3490 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3491 | "" | |
aebf2462 | 3492 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3493 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3494 | |
02befdf4 | 3495 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3496 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3497 | (float_truncate:SF | |
02befdf4 ZW |
3498 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3499 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3500 | "" | |
aebf2462 | 3501 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3502 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3503 | |
02befdf4 | 3504 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3505 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3506 | (float_truncate:DF | |
02befdf4 ZW |
3507 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3508 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3509 | "" | |
aebf2462 | 3510 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3511 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3512 | |
02befdf4 ZW |
3513 | (define_insn "*mulxf3_alts" |
3514 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3515 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3516 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3517 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3518 | "" |
aebf2462 | 3519 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3520 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3521 | |
02befdf4 | 3522 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3523 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3524 | (float_truncate:SF | |
02befdf4 ZW |
3525 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3526 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3527 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3528 | "" |
aebf2462 | 3529 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3530 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3531 | |
02befdf4 | 3532 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3533 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3534 | (float_truncate:DF | |
02befdf4 ZW |
3535 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3536 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3537 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3538 | "" |
aebf2462 | 3539 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3540 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3541 | |
02befdf4 ZW |
3542 | (define_insn "absxf2" |
3543 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3544 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3545 | "" | |
aebf2462 | 3546 | "fabs %0 = %F1" |
52e12ad0 | 3547 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3548 | |
02befdf4 ZW |
3549 | (define_insn "negxf2" |
3550 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3551 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3552 | "" | |
aebf2462 | 3553 | "fneg %0 = %F1" |
52e12ad0 | 3554 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3555 | |
02befdf4 ZW |
3556 | (define_insn "*nabsxf2" |
3557 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3558 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3559 | "" | |
aebf2462 | 3560 | "fnegabs %0 = %F1" |
52e12ad0 | 3561 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3562 | |
046625fa RH |
3563 | (define_insn "copysignxf3" |
3564 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3565 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3566 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3567 | UNSPEC_COPYSIGN))] | |
3568 | "" | |
3569 | "fmerge.s %0 = %F2, %F1" | |
3570 | [(set_attr "itanium_class" "fmisc")]) | |
3571 | ||
3572 | (define_insn "*ncopysignxf3" | |
3573 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3574 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3575 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3576 | UNSPEC_COPYSIGN)))] | |
3577 | "" | |
3578 | "fmerge.ns %0 = %F2, %F1" | |
3579 | [(set_attr "itanium_class" "fmisc")]) | |
3580 | ||
7ae4d8d4 | 3581 | (define_insn "sminxf3" |
02befdf4 ZW |
3582 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3583 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3584 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3585 | "" | |
aebf2462 | 3586 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3587 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3588 | |
7ae4d8d4 | 3589 | (define_insn "smaxxf3" |
02befdf4 ZW |
3590 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3591 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3592 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3593 | "" | |
aebf2462 | 3594 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3595 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3596 | |
02befdf4 ZW |
3597 | (define_insn "*maddxf4" |
3598 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3599 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3600 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3601 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
583ca921 | 3602 | "TARGET_FUSED_MADD" |
aebf2462 | 3603 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3604 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3605 | |
02befdf4 | 3606 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3607 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3608 | (float_truncate:SF | |
02befdf4 ZW |
3609 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3610 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3611 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3612 | "TARGET_FUSED_MADD" |
aebf2462 | 3613 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3614 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3615 | |
02befdf4 | 3616 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3617 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3618 | (float_truncate:DF | |
02befdf4 ZW |
3619 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3620 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3621 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3622 | "TARGET_FUSED_MADD" |
aebf2462 | 3623 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3624 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3625 | |
02befdf4 ZW |
3626 | (define_insn "*maddxf4_alts" |
3627 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3628 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3629 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3630 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3631 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3632 | "" |
aebf2462 | 3633 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3634 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3635 | |
b38ba463 ZW |
3636 | (define_insn "*maddxf4_alts_truncsf" |
3637 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3638 | (float_truncate:SF | |
3639 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3640 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3641 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3642 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3643 | "" | |
3644 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3645 | [(set_attr "itanium_class" "fmac")]) | |
3646 | ||
02befdf4 | 3647 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3648 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3649 | (float_truncate:DF | |
02befdf4 ZW |
3650 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3651 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3652 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3653 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3654 | "" |
aebf2462 | 3655 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3656 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3657 | |
02befdf4 ZW |
3658 | (define_insn "*msubxf4" |
3659 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3660 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3661 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3662 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
583ca921 | 3663 | "TARGET_FUSED_MADD" |
aebf2462 | 3664 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3665 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3666 | |
02befdf4 | 3667 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3668 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3669 | (float_truncate:SF | |
02befdf4 ZW |
3670 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3671 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3672 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3673 | "TARGET_FUSED_MADD" |
aebf2462 | 3674 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3675 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3676 | |
02befdf4 | 3677 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3678 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3679 | (float_truncate:DF | |
02befdf4 ZW |
3680 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3681 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3682 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
583ca921 | 3683 | "TARGET_FUSED_MADD" |
aebf2462 | 3684 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3685 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3686 | |
02befdf4 ZW |
3687 | (define_insn "*nmulxf3" |
3688 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3689 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3690 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3691 | "" | |
aebf2462 | 3692 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3693 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3694 | |
02befdf4 | 3695 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3696 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3697 | (float_truncate:SF | |
02befdf4 ZW |
3698 | (neg:XF (mult:XF |
3699 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3700 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3701 | "" | |
aebf2462 | 3702 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3703 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3704 | |
02befdf4 | 3705 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3706 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3707 | (float_truncate:DF | |
02befdf4 ZW |
3708 | (neg:XF (mult:XF |
3709 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3710 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3711 | "" | |
aebf2462 | 3712 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3713 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3714 | |
02befdf4 ZW |
3715 | (define_insn "*nmaddxf4" |
3716 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3717 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3718 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3719 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3720 | )))] | |
583ca921 | 3721 | "TARGET_FUSED_MADD" |
aebf2462 | 3722 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3723 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3724 | |
02befdf4 | 3725 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3726 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3727 | (float_truncate:SF | |
52ad4d7b ZW |
3728 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3729 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3730 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3731 | ))))] | |
583ca921 | 3732 | "TARGET_FUSED_MADD" |
aebf2462 | 3733 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3734 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3735 | |
02befdf4 | 3736 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3737 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3738 | (float_truncate:DF | |
52ad4d7b ZW |
3739 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3740 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3741 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3742 | ))))] | |
583ca921 | 3743 | "TARGET_FUSED_MADD" |
aebf2462 | 3744 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3745 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3746 | |
02befdf4 ZW |
3747 | (define_insn "*nmaddxf4_alts" |
3748 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3749 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3750 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3751 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3752 | ))) | |
655f2eb9 | 3753 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3754 | "" |
aebf2462 | 3755 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3756 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3757 | |
52ad4d7b ZW |
3758 | (define_insn "*nmaddxf4_truncsf_alts" |
3759 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3760 | (float_truncate:SF | |
3761 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
3762 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3763 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3764 | )))) | |
3765 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3766 | "" | |
3767 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
3768 | [(set_attr "itanium_class" "fmac")]) | |
3769 | ||
02befdf4 | 3770 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
3771 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3772 | (float_truncate:DF | |
52ad4d7b ZW |
3773 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3774 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3775 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3776 | )))) | |
26102535 | 3777 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3778 | "" |
aebf2462 | 3779 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3780 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3781 | |
02befdf4 ZW |
3782 | (define_expand "divxf3" |
3783 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
6adb807e SE |
3784 | (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "") |
3785 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 3786 | "TARGET_INLINE_FLOAT_DIV" |
26102535 | 3787 | { |
13d1a6e7 SE |
3788 | /* There is only one divxf3 sequence, not two like for divsf and divdf. */ |
3789 | emit_insn (gen_divxf3_internal (operands[0], operands[1], operands[2])); | |
26102535 | 3790 | DONE; |
1d5d7a21 | 3791 | }) |
26102535 | 3792 | |
b38ba463 ZW |
3793 | ;; Inline square root. |
3794 | ||
3795 | (define_expand "sqrtxf2" | |
3796 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
6adb807e | 3797 | (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
3798 | "TARGET_INLINE_SQRT" |
3799 | { | |
3800 | rtx insn; | |
f3a83111 | 3801 | insn = gen_sqrtxf2_internal (operands[0], operands[1]); |
b38ba463 ZW |
3802 | emit_insn (insn); |
3803 | DONE; | |
3804 | }) | |
3805 | ||
26102535 RH |
3806 | ;; ??? frcpa works like cmp.foo.unc. |
3807 | ||
655f2eb9 | 3808 | (define_insn "*recip_approx" |
02befdf4 | 3809 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
07acc7b3 | 3810 | (unspec:XF [(const_int 1) |
6adb807e | 3811 | (match_operand:XF 3 "fr_reg_or_fp01_operand" "fG")] |
07acc7b3 | 3812 | UNSPEC_FR_RECIP_APPROX_RES)) |
f2f90c63 | 3813 | (set (match_operand:BI 1 "register_operand" "=c") |
6adb807e | 3814 | (unspec:BI [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") |
086c0f96 | 3815 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 3816 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3817 | "" |
6adb807e | 3818 | "frcpa.s%4 %0, %1 = %F2, %F3" |
52e12ad0 | 3819 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3820 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3821 | \f |
3822 | ;; :::::::::::::::::::: | |
3823 | ;; :: | |
27a9b99d | 3824 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
3825 | ;; :: |
3826 | ;; :::::::::::::::::::: | |
3827 | ||
9c668921 | 3828 | (define_expand "ashlsi3" |
0551c32d RH |
3829 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3830 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3831 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 3832 | "" |
9c668921 RH |
3833 | { |
3834 | if (GET_CODE (operands[2]) != CONST_INT) | |
3835 | { | |
3836 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3837 | we've got to get rid of stray bits outside the SImode register. */ | |
3838 | rtx subshift = gen_reg_rtx (DImode); | |
3839 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3840 | operands[2] = subshift; | |
3841 | } | |
1d5d7a21 | 3842 | }) |
9c668921 RH |
3843 | |
3844 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3845 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3846 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3847 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3848 | "" |
041f25e6 RH |
3849 | "@ |
3850 | shladd %0 = %1, %2, r0 | |
3851 | dep.z %0 = %1, %2, %E2 | |
3852 | shl %0 = %1, %2" | |
52e12ad0 | 3853 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3854 | |
3855 | (define_expand "ashrsi3" | |
0551c32d RH |
3856 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3857 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3858 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3859 | "" |
c65ebc55 | 3860 | { |
041f25e6 RH |
3861 | rtx subtarget = gen_reg_rtx (DImode); |
3862 | if (GET_CODE (operands[2]) == CONST_INT) | |
3863 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3864 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3865 | else | |
3866 | { | |
9c668921 | 3867 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3868 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3869 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3870 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3871 | } |
3872 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3873 | DONE; | |
1d5d7a21 | 3874 | }) |
c65ebc55 | 3875 | |
c65ebc55 | 3876 | (define_expand "lshrsi3" |
0551c32d RH |
3877 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3878 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3879 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3880 | "" |
c65ebc55 | 3881 | { |
041f25e6 RH |
3882 | rtx subtarget = gen_reg_rtx (DImode); |
3883 | if (GET_CODE (operands[2]) == CONST_INT) | |
3884 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3885 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3886 | else | |
3887 | { | |
9c668921 | 3888 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3889 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3890 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3891 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3892 | } |
3893 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3894 | DONE; | |
1d5d7a21 | 3895 | }) |
c65ebc55 | 3896 | |
c65ebc55 | 3897 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3898 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3899 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3900 | |
3901 | (define_expand "rotrsi3" | |
66db6b45 RH |
3902 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3903 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3904 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3905 | "" | |
66db6b45 RH |
3906 | { |
3907 | if (GET_MODE (operands[2]) != VOIDmode) | |
3908 | { | |
3909 | rtx tmp = gen_reg_rtx (DImode); | |
3910 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3911 | operands[2] = tmp; | |
3912 | } | |
1d5d7a21 | 3913 | }) |
66db6b45 RH |
3914 | |
3915 | (define_insn_and_split "*rotrsi3_internal" | |
3916 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3917 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3918 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3919 | "" | |
3920 | "#" | |
3921 | "reload_completed" | |
c65ebc55 | 3922 | [(set (match_dup 3) |
66db6b45 | 3923 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3924 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3925 | (set (match_dup 3) | |
66db6b45 RH |
3926 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3927 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3928 | ||
3929 | (define_expand "rotlsi3" | |
3930 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3931 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3932 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3933 | "" |
c65ebc55 JW |
3934 | { |
3935 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3936 | { |
3937 | rtx tmp = gen_reg_rtx (SImode); | |
3938 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3939 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3940 | DONE; | |
3941 | } | |
1d5d7a21 | 3942 | }) |
66db6b45 RH |
3943 | |
3944 | (define_insn_and_split "*rotlsi3_internal" | |
3945 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3946 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3947 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3948 | "" | |
51094457 JB |
3949 | "mux2 %0 = %1, 0xe1" |
3950 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
3951 | [(set (match_dup 3) |
3952 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3953 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3954 | (set (match_dup 3) | |
3955 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
3956 | { |
3957 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3958 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
3959 | } |
3960 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
3961 | \f |
3962 | ;; :::::::::::::::::::: | |
3963 | ;; :: | |
27a9b99d | 3964 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
3965 | ;; :: |
3966 | ;; :::::::::::::::::::: | |
3967 | ||
3968 | (define_insn "ashldi3" | |
52e12ad0 BS |
3969 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3970 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3971 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3972 | "" |
041f25e6 RH |
3973 | "@ |
3974 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3975 | shl %0 = %1, %2 |
041f25e6 | 3976 | shl %0 = %1, %2" |
52e12ad0 | 3977 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3978 | |
3979 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3980 | ||
3981 | (define_insn "*shladd" | |
0551c32d RH |
3982 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3983 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3984 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3985 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3986 | "" |
3987 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3988 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3989 | |
3990 | ;; This can be created by register elimination if operand3 of shladd is an | |
3991 | ;; eliminable register or has reg_equiv_constant set. | |
3992 | ||
3993 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3994 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3995 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3996 | ;; incorrectly. | |
3997 | ||
5527bf14 | 3998 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3999 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4000 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4001 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4002 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4003 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4004 | "reload_in_progress" | |
e820471b | 4005 | "* gcc_unreachable ();" |
c65ebc55 JW |
4006 | "reload_completed" |
4007 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4008 | (match_dup 3))) | |
c65ebc55 | 4009 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4010 | "" |
52e12ad0 | 4011 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4012 | |
4013 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4014 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4015 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4016 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4017 | "" |
52e12ad0 BS |
4018 | "@ |
4019 | shr %0 = %1, %2 | |
4020 | shr %0 = %1, %2" | |
4021 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4022 | |
4023 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4024 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4025 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4026 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4027 | "" |
52e12ad0 BS |
4028 | "@ |
4029 | shr.u %0 = %1, %2 | |
4030 | shr.u %0 = %1, %2" | |
4031 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4032 | |
4033 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4034 | ;; will load the operand into a register and call the pattern if the predicate | |
4035 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4036 | ;; verify that we have an appropriate constant in the expander. | |
4037 | ||
4038 | (define_expand "rotrdi3" | |
0551c32d RH |
4039 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4040 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4041 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4042 | "" | |
c65ebc55 JW |
4043 | { |
4044 | if (! shift_count_operand (operands[2], DImode)) | |
4045 | FAIL; | |
1d5d7a21 | 4046 | }) |
c65ebc55 JW |
4047 | |
4048 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4049 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4050 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4051 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4052 | "" | |
4053 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4054 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4055 | |
66db6b45 RH |
4056 | (define_expand "rotldi3" |
4057 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4058 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4059 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4060 | "" | |
66db6b45 RH |
4061 | { |
4062 | if (! shift_count_operand (operands[2], DImode)) | |
4063 | FAIL; | |
1d5d7a21 | 4064 | }) |
66db6b45 RH |
4065 | |
4066 | (define_insn "*rotldi3_internal" | |
4067 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4068 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4069 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4070 | "" | |
4071 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4072 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4073 | \f |
4074 | ;; :::::::::::::::::::: | |
4075 | ;; :: | |
27a9b99d | 4076 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
4077 | ;; :: |
4078 | ;; :::::::::::::::::::: | |
4079 | ||
16d8386b JB |
4080 | (define_expand "ashlti3" |
4081 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4082 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4083 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4084 | "" | |
4085 | { | |
4086 | if (!dshift_count_operand (operands[2], DImode)) | |
4087 | FAIL; | |
4088 | }) | |
4089 | ||
4090 | (define_insn_and_split "*ashlti3_internal" | |
4091 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4092 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4093 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4094 | "" | |
4095 | "#" | |
4096 | "reload_completed" | |
4097 | [(const_int 0)] | |
4098 | { | |
4099 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4100 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4101 | rtx rh = gen_highpart (DImode, operands[0]); | |
4102 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4103 | rtx shiftlo = GEN_INT (shift & 63); | |
4104 | ||
4105 | if (shift & 64) | |
4106 | { | |
4107 | emit_move_insn (rl, const0_rtx); | |
4108 | if (shift & 63) | |
4109 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4110 | else | |
4111 | emit_move_insn (rh, lo); | |
4112 | } | |
4113 | else | |
4114 | { | |
4115 | rtx hi = gen_highpart (DImode, operands[1]); | |
4116 | ||
4117 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4118 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4119 | } | |
4120 | DONE; | |
4121 | }) | |
4122 | ||
f526a3c8 RH |
4123 | (define_expand "ashrti3" |
4124 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4125 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4126 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4127 | "" | |
4128 | { | |
4129 | if (!dshift_count_operand (operands[2], DImode)) | |
4130 | FAIL; | |
4131 | }) | |
4132 | ||
4133 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4134 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4135 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4136 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4137 | "" | |
4138 | "#" | |
4139 | "reload_completed" | |
4140 | [(const_int 0)] | |
4141 | { | |
4142 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4143 | rtx rl = gen_lowpart (DImode, operands[0]); |
4144 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4145 | rtx hi = gen_highpart (DImode, operands[1]); |
4146 | rtx shiftlo = GEN_INT (shift & 63); | |
4147 | ||
4148 | if (shift & 64) | |
4149 | { | |
16d8386b JB |
4150 | if (shift & 63) |
4151 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4152 | else | |
4153 | emit_move_insn (rl, hi); | |
4154 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4155 | } |
4156 | else | |
4157 | { | |
16d8386b JB |
4158 | rtx lo = gen_lowpart (DImode, operands[1]); |
4159 | ||
4160 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4161 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4162 | } |
4163 | DONE; | |
4164 | }) | |
4165 | ||
4166 | (define_expand "lshrti3" | |
4167 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4168 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4169 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4170 | "" | |
4171 | { | |
4172 | if (!dshift_count_operand (operands[2], DImode)) | |
4173 | FAIL; | |
4174 | }) | |
4175 | ||
4176 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4177 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4178 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4179 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4180 | "" | |
4181 | "#" | |
4182 | "reload_completed" | |
4183 | [(const_int 0)] | |
4184 | { | |
4185 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4186 | rtx rl = gen_lowpart (DImode, operands[0]); |
4187 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4188 | rtx hi = gen_highpart (DImode, operands[1]); |
4189 | rtx shiftlo = GEN_INT (shift & 63); | |
4190 | ||
4191 | if (shift & 64) | |
4192 | { | |
16d8386b JB |
4193 | if (shift & 63) |
4194 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4195 | else | |
4196 | emit_move_insn (rl, hi); | |
4197 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4198 | } |
4199 | else | |
4200 | { | |
16d8386b JB |
4201 | rtx lo = gen_lowpart (DImode, operands[1]); |
4202 | ||
4203 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4204 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4205 | } |
4206 | DONE; | |
4207 | }) | |
4208 | ||
a71aef0b JB |
4209 | (define_expand "rotlti3" |
4210 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4211 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4212 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4213 | "" | |
4214 | { | |
4215 | if (! dshift_count_operand (operands[2], DImode)) | |
4216 | FAIL; | |
4217 | }) | |
4218 | ||
4219 | (define_insn_and_split "*rotlti3_internal" | |
4220 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4221 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4222 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4223 | "" | |
4224 | "#" | |
4225 | "reload_completed" | |
4226 | [(const_int 0)] | |
4227 | { | |
4228 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4229 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4230 | rtx rh = gen_highpart (DImode, operands[0]); | |
4231 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4232 | rtx hi = gen_highpart (DImode, operands[1]); | |
4233 | rtx countlo = GEN_INT (-count & 63); | |
4234 | ||
4235 | if (count & 64) | |
4236 | { | |
4237 | if (count & 63) | |
4238 | { | |
4239 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4240 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4241 | } | |
4242 | else | |
4243 | { | |
4244 | emit_move_insn (rl, hi); | |
4245 | emit_move_insn (rh, lo); | |
4246 | } | |
4247 | } | |
4248 | else | |
4249 | { | |
4250 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4251 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4252 | } | |
4253 | DONE; | |
4254 | } | |
4255 | [(set_attr "itanium_class" "unknown")]) | |
4256 | ||
f526a3c8 RH |
4257 | (define_insn "shrp" |
4258 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4259 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4260 | (match_operand:DI 2 "gr_register_operand" "r") | |
4261 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4262 | UNSPEC_SHRP))] | |
4263 | "" | |
4264 | "shrp %0 = %1, %2, %3" | |
4265 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4266 | \f |
4267 | ;; :::::::::::::::::::: | |
4268 | ;; :: | |
27a9b99d | 4269 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
4270 | ;; :: |
4271 | ;; :::::::::::::::::::: | |
4272 | ||
4273 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4274 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4275 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4276 | ;; This doesn't work for unary logical operations, because we don't call | |
4277 | ;; apply_distributive_law for them. | |
4278 | ||
4279 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4280 | ;; apply_distributive_law. We get inefficient code for | |
4281 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4282 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4283 | ;; (zero_extend (and (not A) B)) in combine. | |
4284 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4285 | ;; one_cmplsi2 pattern. | |
4286 | ||
058557c4 | 4287 | (define_insn "one_cmplsi2" |
0551c32d RH |
4288 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4289 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4290 | "" |
4291 | "andcm %0 = -1, %1" | |
52e12ad0 | 4292 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4293 | \f |
4294 | ;; :::::::::::::::::::: | |
4295 | ;; :: | |
27a9b99d | 4296 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
4297 | ;; :: |
4298 | ;; :::::::::::::::::::: | |
4299 | ||
4300 | (define_insn "anddi3" | |
0551c32d RH |
4301 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4302 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4303 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4304 | "" |
4305 | "@ | |
4306 | and %0 = %2, %1 | |
aebf2462 | 4307 | fand %0 = %2, %1" |
52e12ad0 | 4308 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4309 | |
4310 | (define_insn "*andnot" | |
0551c32d RH |
4311 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4312 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4313 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4314 | "" |
4315 | "@ | |
4316 | andcm %0 = %2, %1 | |
aebf2462 | 4317 | fandcm %0 = %2, %1" |
52e12ad0 | 4318 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4319 | |
4320 | (define_insn "iordi3" | |
0551c32d RH |
4321 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4322 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4323 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4324 | "" |
4325 | "@ | |
4326 | or %0 = %2, %1 | |
aebf2462 | 4327 | for %0 = %2, %1" |
52e12ad0 | 4328 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4329 | |
4330 | (define_insn "xordi3" | |
0551c32d RH |
4331 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4332 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4333 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4334 | "" |
4335 | "@ | |
4336 | xor %0 = %2, %1 | |
aebf2462 | 4337 | fxor %0 = %2, %1" |
52e12ad0 | 4338 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4339 | |
4340 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4341 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4342 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4343 | "" |
4344 | "andcm %0 = -1, %1" | |
52e12ad0 | 4345 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4346 | \f |
4347 | ;; :::::::::::::::::::: | |
4348 | ;; :: | |
4349 | ;; :: Comparisons | |
4350 | ;; :: | |
4351 | ;; :::::::::::::::::::: | |
4352 | ||
f90b7a5a PB |
4353 | (define_expand "cbranchbi4" |
4354 | [(set (pc) | |
4355 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4356 | [(match_operand:BI 1 "register_operand" "") | |
4357 | (match_operand:BI 2 "const_int_operand" "")]) | |
4358 | (label_ref (match_operand 3 "" "")) | |
4359 | (pc)))] | |
f2f90c63 | 4360 | "" |
f90b7a5a | 4361 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
f2f90c63 | 4362 | |
f90b7a5a PB |
4363 | (define_expand "cbranchsi4" |
4364 | [(set (pc) | |
4365 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4366 | [(match_operand:SI 1 "gr_register_operand" "") | |
4367 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4368 | (label_ref (match_operand 3 "" "")) | |
4369 | (pc)))] | |
c65ebc55 | 4370 | "" |
f90b7a5a | 4371 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4372 | |
f90b7a5a PB |
4373 | (define_expand "cbranchdi4" |
4374 | [(set (pc) | |
4375 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4376 | [(match_operand:DI 1 "gr_register_operand" "") | |
4377 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4378 | (label_ref (match_operand 3 "" "")) | |
4379 | (pc)))] | |
c65ebc55 | 4380 | "" |
f90b7a5a | 4381 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4382 | |
f90b7a5a PB |
4383 | (define_expand "cbranchsf4" |
4384 | [(set (pc) | |
4385 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4386 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
4387 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
4388 | (label_ref (match_operand 3 "" "")) | |
4389 | (pc)))] | |
c65ebc55 | 4390 | "" |
f90b7a5a | 4391 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4392 | |
f90b7a5a PB |
4393 | (define_expand "cbranchdf4" |
4394 | [(set (pc) | |
4395 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4396 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
4397 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
4398 | (label_ref (match_operand 3 "" "")) | |
4399 | (pc)))] | |
c65ebc55 | 4400 | "" |
f90b7a5a | 4401 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4402 | |
f90b7a5a PB |
4403 | (define_expand "cbranchxf4" |
4404 | [(set (pc) | |
4405 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4406 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
4407 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
4408 | (label_ref (match_operand 3 "" "")) | |
4409 | (pc)))] | |
02befdf4 | 4410 | "" |
f90b7a5a | 4411 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4412 | |
f90b7a5a PB |
4413 | (define_expand "cbranchtf4" |
4414 | [(set (pc) | |
4415 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
4416 | [(match_operand:TF 1 "gr_register_operand" "") | |
4417 | (match_operand:TF 2 "gr_register_operand" "")]) | |
4418 | (label_ref (match_operand 3 "" "")) | |
4419 | (pc)))] | |
24ea7948 | 4420 | "TARGET_HPUX" |
f90b7a5a PB |
4421 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
4422 | ||
24ea7948 | 4423 | |
c65ebc55 | 4424 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4425 | [(set (match_operand:BI 0 "register_operand" "=c") |
4426 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4427 | [(match_operand:SI 2 "gr_register_operand" "r") |
4428 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4429 | "" |
4430 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4431 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4432 | |
18a3c539 JW |
4433 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4434 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4435 | ||
c65ebc55 | 4436 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4437 | [(set (match_operand:BI 0 "register_operand" "=c") |
4438 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4439 | [(match_operand:SI 2 "gr_register_operand" "r") |
4440 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4441 | "" |
18a3c539 | 4442 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4443 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4444 | |
4445 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4446 | [(set (match_operand:BI 0 "register_operand" "=c") |
4447 | (match_operator:BI 1 "normal_comparison_operator" | |
4448 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4449 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4450 | "" |
f2f90c63 | 4451 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4452 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4453 | |
18a3c539 JW |
4454 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4455 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4456 | ||
c65ebc55 | 4457 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4458 | [(set (match_operand:BI 0 "register_operand" "=c") |
4459 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4460 | [(match_operand:DI 2 "gr_register_operand" "r") |
4461 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4462 | "" |
18a3c539 | 4463 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4464 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4465 | |
4466 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4467 | [(set (match_operand:BI 0 "register_operand" "=c") |
4468 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4469 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4470 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4471 | "" |
4472 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4473 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4474 | |
4475 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4476 | [(set (match_operand:BI 0 "register_operand" "=c") |
4477 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4478 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4479 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4480 | "" |
4481 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4482 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4483 | |
02befdf4 | 4484 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4485 | [(set (match_operand:BI 0 "register_operand" "=c") |
4486 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4487 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
4488 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
4489 | "" | |
3f622353 | 4490 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4491 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4492 | |
c65ebc55 JW |
4493 | ;; ??? Can this pattern be generated? |
4494 | ||
4495 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4496 | [(set (match_operand:BI 0 "register_operand" "=c") |
4497 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4498 | (const_int 1) |
5d48891e | 4499 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4500 | (const_int 0)))] |
4501 | "" | |
4502 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4503 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4504 | |
4505 | (define_insn "*bit_one" | |
f2f90c63 RH |
4506 | [(set (match_operand:BI 0 "register_operand" "=c") |
4507 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4508 | (const_int 1) |
5d48891e | 4509 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4510 | (const_int 0)))] |
4511 | "" | |
4512 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4513 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4514 | \f |
4515 | ;; :::::::::::::::::::: | |
4516 | ;; :: | |
4517 | ;; :: Branches | |
4518 | ;; :: | |
4519 | ;; :::::::::::::::::::: | |
4520 | ||
6b6c1201 | 4521 | (define_insn "*br_true" |
c65ebc55 | 4522 | [(set (pc) |
6b6c1201 | 4523 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4524 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4525 | (const_int 0)]) |
4526 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4527 | (pc)))] |
4528 | "" | |
85548039 | 4529 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4530 | [(set_attr "itanium_class" "br") |
e5bde68a | 4531 | (set_attr "predicable" "no")]) |
c65ebc55 | 4532 | |
6b6c1201 | 4533 | (define_insn "*br_false" |
c65ebc55 | 4534 | [(set (pc) |
6b6c1201 | 4535 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4536 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4537 | (const_int 0)]) |
c65ebc55 | 4538 | (pc) |
6b6c1201 | 4539 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4540 | "" |
85548039 | 4541 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4542 | [(set_attr "itanium_class" "br") |
e5bde68a | 4543 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4544 | \f |
4545 | ;; :::::::::::::::::::: | |
4546 | ;; :: | |
5527bf14 RH |
4547 | ;; :: Counted loop operations |
4548 | ;; :: | |
4549 | ;; :::::::::::::::::::: | |
4550 | ||
4551 | (define_expand "doloop_end" | |
4552 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4553 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4554 | (use (match_operand 2 "" "")) ; max iterations | |
4555 | (use (match_operand 3 "" "")) ; loop level | |
4556 | (use (match_operand 4 "" ""))] ; label | |
4557 | "" | |
5527bf14 RH |
4558 | { |
4559 | /* Only use cloop on innermost loops. */ | |
4560 | if (INTVAL (operands[3]) > 1) | |
4561 | FAIL; | |
4562 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4563 | operands[4])); | |
4564 | DONE; | |
1d5d7a21 | 4565 | }) |
5527bf14 RH |
4566 | |
4567 | (define_insn "doloop_end_internal" | |
4568 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4569 | (const_int 0)) | |
4570 | (label_ref (match_operand 1 "" "")) | |
4571 | (pc))) | |
4572 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
4573 | (plus:DI (match_dup 0) (const_int -1)) |
4574 | (match_dup 0)))] | |
5527bf14 RH |
4575 | "" |
4576 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4577 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4578 | (set_attr "predicable" "no")]) |
4579 | \f | |
4580 | ;; :::::::::::::::::::: | |
4581 | ;; :: | |
c65ebc55 JW |
4582 | ;; :: Set flag operations |
4583 | ;; :: | |
4584 | ;; :::::::::::::::::::: | |
4585 | ||
f90b7a5a PB |
4586 | (define_expand "cstorebi4" |
4587 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4588 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4589 | [(match_operand:BI 2 "register_operand" "") | |
4590 | (match_operand:BI 3 "const_int_operand" "")]))] | |
c65ebc55 | 4591 | "" |
f90b7a5a | 4592 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 4593 | |
f90b7a5a PB |
4594 | (define_expand "cstoresi4" |
4595 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4596 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4597 | [(match_operand:SI 2 "gr_register_operand" "") | |
4598 | (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 4599 | "" |
f90b7a5a | 4600 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4601 | |
f90b7a5a PB |
4602 | (define_expand "cstoredi4" |
4603 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4604 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4605 | [(match_operand:DI 2 "gr_register_operand" "") | |
4606 | (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 4607 | "" |
f90b7a5a | 4608 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4609 | |
f90b7a5a PB |
4610 | (define_expand "cstoresf4" |
4611 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4612 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4613 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "") | |
4614 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4615 | "" |
f90b7a5a | 4616 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4617 | |
f90b7a5a PB |
4618 | (define_expand "cstoredf4" |
4619 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4620 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4621 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "") | |
4622 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4623 | "" |
f90b7a5a | 4624 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4625 | |
f90b7a5a PB |
4626 | (define_expand "cstorexf4" |
4627 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4628 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4629 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "") | |
4630 | (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))] | |
c65ebc55 | 4631 | "" |
f90b7a5a | 4632 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4633 | |
f90b7a5a PB |
4634 | (define_expand "cstoretf4" |
4635 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4636 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4637 | [(match_operand:TF 2 "gr_register_operand" "") | |
4638 | (match_operand:TF 3 "gr_register_operand" "")]))] | |
4639 | "TARGET_HPUX" | |
4640 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") | |
e57b9d65 | 4641 | |
c65ebc55 JW |
4642 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4643 | ;; efficient than mov/mov/cst/cst. | |
4644 | ||
0551c32d RH |
4645 | (define_insn_and_split "*sne_internal" |
4646 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4647 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4648 | (const_int 0)))] |
4649 | "" | |
4650 | "#" | |
c65ebc55 | 4651 | "reload_completed" |
f2f90c63 RH |
4652 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4653 | (set (match_dup 0) (const_int 1))) | |
4654 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4655 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4656 | "" |
52e12ad0 | 4657 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4658 | |
0551c32d RH |
4659 | (define_insn_and_split "*seq_internal" |
4660 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4661 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4662 | (const_int 0)))] |
4663 | "" | |
4664 | "#" | |
c65ebc55 | 4665 | "reload_completed" |
f2f90c63 RH |
4666 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4667 | (set (match_dup 0) (const_int 0))) | |
4668 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4669 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4670 | "" |
52e12ad0 | 4671 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4672 | \f |
4673 | ;; :::::::::::::::::::: | |
4674 | ;; :: | |
4675 | ;; :: Conditional move instructions. | |
4676 | ;; :: | |
4677 | ;; :::::::::::::::::::: | |
4678 | ||
4679 | ;; ??? Add movXXcc patterns? | |
4680 | ||
c65ebc55 JW |
4681 | ;; |
4682 | ;; DImode if_then_else patterns. | |
4683 | ;; | |
4684 | ||
75cdbeb8 | 4685 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4686 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4687 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4688 | (if_then_else:DI |
f2f90c63 RH |
4689 | (match_operator 4 "predicate_operator" |
4690 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4691 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4692 | (const_int 0)]) |
f2f90c63 | 4693 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4694 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4695 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4696 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4697 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4698 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4699 | { gcc_unreachable (); } |
75cdbeb8 RH |
4700 | [(set_attr "predicable" "no")]) |
4701 | ||
4702 | (define_split | |
f2f90c63 | 4703 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4704 | (if_then_else |
f2f90c63 RH |
4705 | (match_operator 4 "predicate_operator" |
4706 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4707 | (const_int 0)]) |
f2f90c63 RH |
4708 | (match_operand 2 "move_operand" "") |
4709 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4710 | "reload_completed" |
4711 | [(const_int 0)] | |
e5bde68a | 4712 | { |
21515593 RH |
4713 | bool emitted_something = false; |
4714 | rtx dest = operands[0]; | |
4715 | rtx srct = operands[2]; | |
4716 | rtx srcf = operands[3]; | |
4717 | rtx cond = operands[4]; | |
2f937369 | 4718 | |
21515593 | 4719 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 4720 | { |
21515593 RH |
4721 | ia64_emit_cond_move (dest, srct, cond); |
4722 | emitted_something = true; | |
e5bde68a | 4723 | } |
21515593 | 4724 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 4725 | { |
21515593 RH |
4726 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
4727 | VOIDmode, operands[1], const0_rtx); | |
4728 | ia64_emit_cond_move (dest, srcf, cond); | |
4729 | emitted_something = true; | |
3b572406 | 4730 | } |
2f937369 | 4731 | if (! emitted_something) |
f9974026 | 4732 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 4733 | DONE; |
1d5d7a21 | 4734 | }) |
c65ebc55 JW |
4735 | |
4736 | ;; Absolute value pattern. | |
4737 | ||
4738 | (define_insn "*absdi2_internal" | |
0551c32d | 4739 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4740 | (if_then_else:DI |
f2f90c63 RH |
4741 | (match_operator 4 "predicate_operator" |
4742 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4743 | (const_int 0)]) |
0551c32d RH |
4744 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4745 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4746 | "" |
e5bde68a | 4747 | "#" |
52e12ad0 | 4748 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4749 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4750 | |
4751 | (define_split | |
4752 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4753 | (if_then_else:DI |
f2f90c63 RH |
4754 | (match_operator 4 "predicate_operator" |
4755 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4756 | (const_int 0)]) |
0551c32d RH |
4757 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4758 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4759 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4760 | [(cond_exec | |
4761 | (match_dup 4) | |
4762 | (set (match_dup 0) | |
4763 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4764 | "") |
4765 | ||
e5bde68a RH |
4766 | (define_split |
4767 | [(set (match_operand:DI 0 "register_operand" "") | |
4768 | (if_then_else:DI | |
f2f90c63 RH |
4769 | (match_operator 4 "predicate_operator" |
4770 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4771 | (const_int 0)]) |
0551c32d RH |
4772 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4773 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4774 | "reload_completed" |
4775 | [(cond_exec | |
4776 | (match_dup 4) | |
4777 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4778 | (cond_exec | |
4779 | (match_dup 5) | |
4780 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4781 | { |
4782 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4783 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4784 | }) |
c65ebc55 JW |
4785 | |
4786 | ;; | |
4787 | ;; SImode if_then_else patterns. | |
4788 | ;; | |
4789 | ||
75cdbeb8 | 4790 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4791 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4792 | (if_then_else:SI |
f2f90c63 RH |
4793 | (match_operator 4 "predicate_operator" |
4794 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4795 | (const_int 0)]) |
f2f90c63 | 4796 | (match_operand:SI 2 "move_operand" |
3b572406 | 4797 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4798 | (match_operand:SI 3 "move_operand" |
3b572406 | 4799 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4800 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4801 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4802 | { gcc_unreachable (); } |
3b572406 | 4803 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4804 | |
4805 | (define_insn "*abssi2_internal" | |
0551c32d | 4806 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4807 | (if_then_else:SI |
f2f90c63 RH |
4808 | (match_operator 4 "predicate_operator" |
4809 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4810 | (const_int 0)]) |
0551c32d RH |
4811 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4812 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4813 | "" |
e5bde68a | 4814 | "#" |
52e12ad0 | 4815 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4816 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4817 | |
4818 | (define_split | |
4819 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4820 | (if_then_else:SI |
f2f90c63 RH |
4821 | (match_operator 4 "predicate_operator" |
4822 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4823 | (const_int 0)]) |
0551c32d RH |
4824 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4825 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4826 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4827 | [(cond_exec | |
4828 | (match_dup 4) | |
4829 | (set (match_dup 0) | |
4830 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4831 | "") |
4832 | ||
e5bde68a RH |
4833 | (define_split |
4834 | [(set (match_operand:SI 0 "register_operand" "") | |
4835 | (if_then_else:SI | |
f2f90c63 RH |
4836 | (match_operator 4 "predicate_operator" |
4837 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4838 | (const_int 0)]) |
0551c32d RH |
4839 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4840 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4841 | "reload_completed" |
4842 | [(cond_exec | |
4843 | (match_dup 4) | |
4844 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4845 | (cond_exec | |
4846 | (match_dup 5) | |
4847 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4848 | { |
4849 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4850 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4851 | }) |
e5bde68a | 4852 | |
7dcc803e | 4853 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4854 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4855 | (match_operator:SI 5 "condop_operator" | |
4856 | [(if_then_else:SI | |
4857 | (match_operator 6 "predicate_operator" | |
4858 | [(match_operand:BI 1 "register_operand" "c") | |
4859 | (const_int 0)]) | |
4860 | (match_operand:SI 2 "gr_register_operand" "r") | |
4861 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4862 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4863 | "" | |
4864 | "#" | |
acb0638d BS |
4865 | "reload_completed" |
4866 | [(cond_exec | |
4867 | (match_dup 6) | |
4868 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4869 | (cond_exec | |
4870 | (match_dup 7) | |
4871 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
4872 | { |
4873 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4874 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4875 | } |
7dcc803e BS |
4876 | [(set_attr "itanium_class" "ialu") |
4877 | (set_attr "predicable" "no")]) | |
4878 | ||
acb0638d | 4879 | |
7dcc803e | 4880 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4881 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4882 | (match_operator:SI 5 "condop_operator" | |
4883 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4884 | (if_then_else:SI | |
4885 | (match_operator 6 "predicate_operator" | |
4886 | [(match_operand:BI 1 "register_operand" "c") | |
4887 | (const_int 0)]) | |
4888 | (match_operand:SI 2 "gr_register_operand" "r") | |
4889 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4890 | "" | |
4891 | "#" | |
acb0638d BS |
4892 | "reload_completed" |
4893 | [(cond_exec | |
4894 | (match_dup 6) | |
4895 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4896 | (cond_exec | |
4897 | (match_dup 7) | |
4898 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
4899 | { |
4900 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4901 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4902 | } |
7dcc803e BS |
4903 | [(set_attr "itanium_class" "ialu") |
4904 | (set_attr "predicable" "no")]) | |
acb0638d | 4905 | |
c65ebc55 JW |
4906 | \f |
4907 | ;; :::::::::::::::::::: | |
4908 | ;; :: | |
4909 | ;; :: Call and branch instructions | |
4910 | ;; :: | |
4911 | ;; :::::::::::::::::::: | |
4912 | ||
4913 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4914 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4915 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4916 | ;; registers used as operands. | |
4917 | ||
4918 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4919 | ;; is supplied for the sake of some RISC machines which need to put this | |
4920 | ;; information into the assembler code; they can put it in the RTL instead of | |
4921 | ;; operand 1. | |
4922 | ||
4923 | (define_expand "call" | |
4924 | [(use (match_operand:DI 0 "" "")) | |
4925 | (use (match_operand 1 "" "")) | |
4926 | (use (match_operand 2 "" "")) | |
4927 | (use (match_operand 3 "" ""))] | |
4928 | "" | |
c65ebc55 | 4929 | { |
599aedd9 | 4930 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 4931 | DONE; |
1d5d7a21 | 4932 | }) |
c65ebc55 | 4933 | |
2ed4af6f RH |
4934 | (define_expand "sibcall" |
4935 | [(use (match_operand:DI 0 "" "")) | |
4936 | (use (match_operand 1 "" "")) | |
4937 | (use (match_operand 2 "" "")) | |
4938 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 4939 | "" |
c65ebc55 | 4940 | { |
599aedd9 | 4941 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 4942 | DONE; |
1d5d7a21 | 4943 | }) |
c65ebc55 | 4944 | |
c65ebc55 | 4945 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4946 | ;; register in which the value is returned. There are three more operands, |
4947 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4948 | ;; increased by one). |
2ed4af6f | 4949 | ;; |
c65ebc55 JW |
4950 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4951 | ||
4952 | (define_expand "call_value" | |
4953 | [(use (match_operand 0 "" "")) | |
4954 | (use (match_operand:DI 1 "" "")) | |
4955 | (use (match_operand 2 "" "")) | |
4956 | (use (match_operand 3 "" "")) | |
4957 | (use (match_operand 4 "" ""))] | |
4958 | "" | |
c65ebc55 | 4959 | { |
599aedd9 | 4960 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 4961 | DONE; |
1d5d7a21 | 4962 | }) |
c65ebc55 | 4963 | |
2ed4af6f RH |
4964 | (define_expand "sibcall_value" |
4965 | [(use (match_operand 0 "" "")) | |
4966 | (use (match_operand:DI 1 "" "")) | |
4967 | (use (match_operand 2 "" "")) | |
4968 | (use (match_operand 3 "" "")) | |
4969 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 4970 | "" |
c65ebc55 | 4971 | { |
599aedd9 | 4972 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 4973 | DONE; |
1d5d7a21 | 4974 | }) |
c65ebc55 | 4975 | |
c65ebc55 JW |
4976 | ;; Call subroutine returning any type. |
4977 | ||
4978 | (define_expand "untyped_call" | |
4979 | [(parallel [(call (match_operand 0 "" "") | |
4980 | (const_int 0)) | |
4981 | (match_operand 1 "" "") | |
4982 | (match_operand 2 "" "")])] | |
4983 | "" | |
c65ebc55 JW |
4984 | { |
4985 | int i; | |
4986 | ||
4987 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4988 | ||
4989 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4990 | { | |
4991 | rtx set = XVECEXP (operands[2], 0, i); | |
4992 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4993 | } | |
4994 | ||
4995 | /* The optimizer does not know that the call sets the function value | |
4996 | registers we stored in the result block. We avoid problems by | |
4997 | claiming that all hard registers are used and clobbered at this | |
4998 | point. */ | |
4999 | emit_insn (gen_blockage ()); | |
5000 | ||
5001 | DONE; | |
1d5d7a21 | 5002 | }) |
c65ebc55 | 5003 | |
599aedd9 RH |
5004 | (define_insn "call_nogp" |
5005 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5006 | (const_int 0)) | |
5007 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5008 | "" |
599aedd9 | 5009 | "br.call%+.many %1 = %0" |
52e12ad0 | 5010 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5011 | |
599aedd9 | 5012 | (define_insn "call_value_nogp" |
75293ad6 | 5013 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5014 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5015 | (const_int 0))) | |
5016 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5017 | "" |
599aedd9 | 5018 | "br.call%+.many %2 = %1" |
52e12ad0 | 5019 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5020 | |
599aedd9 RH |
5021 | (define_insn "sibcall_nogp" |
5022 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5023 | (const_int 0))] | |
2ed4af6f RH |
5024 | "" |
5025 | "br%+.many %0" | |
52e12ad0 | 5026 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5027 | |
599aedd9 | 5028 | (define_insn "call_gp" |
c8083186 | 5029 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5030 | (const_int 1)) |
5031 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5032 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5033 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5034 | "" |
599aedd9 | 5035 | "#" |
52e12ad0 | 5036 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5037 | |
599aedd9 RH |
5038 | ;; Irritatingly, we don't have access to INSN within the split body. |
5039 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5040 | (define_split | |
5041 | [(call (mem (match_operand 0 "call_operand" "")) | |
5042 | (const_int 1)) | |
5043 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5044 | (clobber (match_scratch:DI 2 "")) | |
5045 | (clobber (match_scratch:DI 3 ""))] | |
5046 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5047 | [(const_int 0)] | |
5048 | { | |
5049 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5050 | operands[3], true, false); | |
5051 | DONE; | |
5052 | }) | |
5053 | ||
5054 | (define_split | |
5055 | [(call (mem (match_operand 0 "call_operand" "")) | |
5056 | (const_int 1)) | |
5057 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5058 | (clobber (match_scratch:DI 2 "")) | |
5059 | (clobber (match_scratch:DI 3 ""))] | |
5060 | "reload_completed" | |
5061 | [(const_int 0)] | |
5062 | { | |
5063 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5064 | operands[3], false, false); | |
5065 | DONE; | |
5066 | }) | |
5067 | ||
5068 | (define_insn "call_value_gp" | |
75293ad6 | 5069 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5070 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5071 | (const_int 1))) | |
5072 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5073 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5074 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5075 | "" |
599aedd9 | 5076 | "#" |
52e12ad0 | 5077 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5078 | |
599aedd9 RH |
5079 | (define_split |
5080 | [(set (match_operand 0 "" "") | |
5081 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5082 | (const_int 1))) | |
5083 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5084 | (clobber (match_scratch:DI 3 "")) | |
5085 | (clobber (match_scratch:DI 4 ""))] | |
5086 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5087 | [(const_int 0)] | |
5088 | { | |
5089 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5090 | operands[4], true, false); | |
5091 | DONE; | |
5092 | }) | |
5093 | ||
5094 | (define_split | |
5095 | [(set (match_operand 0 "" "") | |
5096 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5097 | (const_int 1))) | |
5098 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5099 | (clobber (match_scratch:DI 3 "")) | |
5100 | (clobber (match_scratch:DI 4 ""))] | |
5101 | "reload_completed" | |
5102 | [(const_int 0)] | |
5103 | { | |
5104 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5105 | operands[4], false, false); | |
5106 | DONE; | |
5107 | }) | |
5108 | ||
5109 | (define_insn_and_split "sibcall_gp" | |
5110 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5111 | (const_int 1)) | |
5112 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5113 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5114 | "" |
599aedd9 RH |
5115 | "#" |
5116 | "reload_completed" | |
5117 | [(const_int 0)] | |
5118 | { | |
5119 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5120 | operands[2], true, true); | |
5121 | DONE; | |
5122 | } | |
52e12ad0 | 5123 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5124 | |
c65ebc55 JW |
5125 | (define_insn "return_internal" |
5126 | [(return) | |
5127 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5128 | "" | |
5129 | "br.ret.sptk.many %0" | |
52e12ad0 | 5130 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5131 | |
5132 | (define_insn "return" | |
5133 | [(return)] | |
5134 | "ia64_direct_return ()" | |
5135 | "br.ret.sptk.many rp" | |
52e12ad0 | 5136 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5137 | |
6b6c1201 | 5138 | (define_insn "*return_true" |
c65ebc55 | 5139 | [(set (pc) |
6b6c1201 | 5140 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5141 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5142 | (const_int 0)]) |
c65ebc55 JW |
5143 | (return) |
5144 | (pc)))] | |
5145 | "ia64_direct_return ()" | |
13da91fd | 5146 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5147 | [(set_attr "itanium_class" "br") |
e5bde68a | 5148 | (set_attr "predicable" "no")]) |
c65ebc55 | 5149 | |
6b6c1201 | 5150 | (define_insn "*return_false" |
c65ebc55 | 5151 | [(set (pc) |
6b6c1201 | 5152 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5153 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5154 | (const_int 0)]) |
c65ebc55 JW |
5155 | (pc) |
5156 | (return)))] | |
5157 | "ia64_direct_return ()" | |
13da91fd | 5158 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5159 | [(set_attr "itanium_class" "br") |
e5bde68a | 5160 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5161 | |
5162 | (define_insn "jump" | |
5163 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5164 | "" | |
5165 | "br %l0" | |
52e12ad0 | 5166 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5167 | |
5168 | (define_insn "indirect_jump" | |
5169 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5170 | "" | |
5171 | "br %0" | |
52e12ad0 | 5172 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5173 | |
5174 | (define_expand "tablejump" | |
340f7e7c RH |
5175 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5176 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5177 | "" |
c65ebc55 | 5178 | { |
340f7e7c RH |
5179 | rtx op0 = operands[0]; |
5180 | rtx addr; | |
5181 | ||
5182 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5183 | element into a register without bothering to see whether that | |
5184 | is necessary given the operand predicate. Check for MEM just | |
5185 | in case someone fixes this. */ | |
5186 | if (GET_CODE (op0) == MEM) | |
5187 | addr = XEXP (op0, 0); | |
5188 | else | |
5189 | { | |
5190 | /* Otherwise, cheat and guess that the previous insn in the | |
5191 | stream was the memory load. Grab the address from that. | |
5192 | Note we have to momentarily pop out of the sequence started | |
5193 | by the insn-emit wrapper in order to grab the last insn. */ | |
5194 | rtx last, set; | |
5195 | ||
5196 | end_sequence (); | |
5197 | last = get_last_insn (); | |
5198 | start_sequence (); | |
5199 | set = single_set (last); | |
5200 | ||
e820471b NS |
5201 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5202 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5203 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5204 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5205 | } |
c65ebc55 | 5206 | |
340f7e7c RH |
5207 | /* Jump table elements are stored pc-relative. That is, a displacement |
5208 | from the entry to the label. Thus to convert to an absolute address | |
5209 | we add the address of the memory from which the value is loaded. */ | |
5210 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5211 | NULL_RTX, 1, OPTAB_DIRECT); | |
5212 | }) | |
c65ebc55 | 5213 | |
340f7e7c | 5214 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5215 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5216 | (use (label_ref (match_operand 1 "" "")))] | |
5217 | "" | |
5218 | "br %0" | |
52e12ad0 | 5219 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5220 | |
5221 | \f | |
5222 | ;; :::::::::::::::::::: | |
5223 | ;; :: | |
5224 | ;; :: Prologue and Epilogue instructions | |
5225 | ;; :: | |
5226 | ;; :::::::::::::::::::: | |
5227 | ||
5228 | (define_expand "prologue" | |
5229 | [(const_int 1)] | |
5230 | "" | |
c65ebc55 JW |
5231 | { |
5232 | ia64_expand_prologue (); | |
5233 | DONE; | |
1d5d7a21 | 5234 | }) |
c65ebc55 JW |
5235 | |
5236 | (define_expand "epilogue" | |
2ed4af6f RH |
5237 | [(return)] |
5238 | "" | |
2ed4af6f RH |
5239 | { |
5240 | ia64_expand_epilogue (0); | |
5241 | DONE; | |
1d5d7a21 | 5242 | }) |
2ed4af6f RH |
5243 | |
5244 | (define_expand "sibcall_epilogue" | |
5245 | [(return)] | |
c65ebc55 | 5246 | "" |
c65ebc55 | 5247 | { |
2ed4af6f | 5248 | ia64_expand_epilogue (1); |
c65ebc55 | 5249 | DONE; |
1d5d7a21 | 5250 | }) |
c65ebc55 JW |
5251 | |
5252 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5253 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5254 | ||
5255 | (define_insn "prologue_allocate_stack" | |
5256 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5257 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5258 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5259 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5260 | (match_dup 3))] |
5261 | "" | |
5262 | "@ | |
1d5d7a21 RH |
5263 | add %0 = %1, %2 |
5264 | adds %0 = %2, %1 | |
5265 | addl %0 = %2, %1" | |
52e12ad0 | 5266 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5267 | |
5268 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5269 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5270 | ||
5271 | (define_insn "epilogue_deallocate_stack" | |
5272 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5273 | (match_operand:DI 1 "register_operand" "+r")) | |
5274 | (set (match_dup 1) (match_dup 1))] | |
5275 | "" | |
5276 | "mov %0 = %1" | |
52e12ad0 | 5277 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5278 | |
1d5d7a21 RH |
5279 | ;; As USE insns aren't meaningful after reload, this is used instead |
5280 | ;; to prevent deleting instructions setting registers for EH handling | |
5281 | (define_insn "prologue_use" | |
5282 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5283 | UNSPEC_PROLOGUE_USE)] | |
5284 | "" | |
5285 | "" | |
5286 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5287 | (set_attr "predicable" "no") |
5288 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5289 | |
c65ebc55 JW |
5290 | ;; Allocate a new register frame. |
5291 | ||
5292 | (define_insn "alloc" | |
5293 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5294 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5295 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5296 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5297 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5298 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5299 | "" | |
5300 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5301 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
5302 | (set_attr "predicable" "no") |
5303 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 5304 | |
97e242b0 RH |
5305 | ;; Modifies ar.unat |
5306 | (define_expand "gr_spill" | |
870f9ec0 RH |
5307 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5308 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5309 | (match_operand:DI 2 "const_int_operand" "")] |
5310 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5311 | (clobber (match_dup 3))])] |
97e242b0 | 5312 | "" |
870f9ec0 | 5313 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5314 | |
870f9ec0 | 5315 | (define_insn "gr_spill_internal" |
b6fb7d46 | 5316 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 5317 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5318 | (match_operand:DI 2 "const_int_operand" "")] |
5319 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5320 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5321 | "" |
2130b7fb | 5322 | { |
1d5d7a21 RH |
5323 | /* Note that we use a C output pattern here to avoid the predicate |
5324 | being automatically added before the .mem.offset directive. */ | |
5325 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5326 | } | |
52e12ad0 | 5327 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5328 | |
97e242b0 RH |
5329 | ;; Reads ar.unat |
5330 | (define_expand "gr_restore" | |
870f9ec0 RH |
5331 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5332 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5333 | (match_operand:DI 2 "const_int_operand" "")] |
5334 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5335 | (use (match_dup 3))])] |
97e242b0 | 5336 | "" |
870f9ec0 | 5337 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5338 | |
870f9ec0 | 5339 | (define_insn "gr_restore_internal" |
c65ebc55 | 5340 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5341 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5342 | (match_operand:DI 2 "const_int_operand" "")] |
5343 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5344 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5345 | "" |
1d5d7a21 | 5346 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5347 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5348 | |
5349 | (define_insn "fr_spill" | |
b6fb7d46 | 5350 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 5351 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 5352 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5353 | "" |
5354 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5355 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5356 | |
5357 | (define_insn "fr_restore" | |
02befdf4 ZW |
5358 | [(set (match_operand:XF 0 "register_operand" "=f") |
5359 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5360 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5361 | "" |
5362 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5363 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5364 | |
0024a804 JW |
5365 | ;; ??? The explicit stop is not ideal. It would be better if |
5366 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5367 | ;; fixed later. This avoids an RSE DV. | |
5368 | ||
0c96007e AM |
5369 | (define_insn "bsp_value" |
5370 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5371 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5372 | "" |
582d11e6 JW |
5373 | "* |
5374 | { | |
5375 | return \";;\;%,mov %0 = ar.bsp\"; | |
5376 | }" | |
52e12ad0 | 5377 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5378 | |
5379 | (define_insn "set_bsp" | |
086c0f96 RH |
5380 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5381 | UNSPECV_SET_BSP)] | |
0c96007e | 5382 | "" |
1d5d7a21 RH |
5383 | "flushrs |
5384 | mov r19=ar.rsc | |
5385 | ;; | |
5386 | and r19=0x1c,r19 | |
5387 | ;; | |
5388 | mov ar.rsc=r19 | |
5389 | ;; | |
5390 | mov ar.bspstore=%0 | |
5391 | ;; | |
5392 | or r19=0x3,r19 | |
5393 | ;; | |
5394 | loadrs | |
5395 | invala | |
5396 | ;; | |
5397 | mov ar.rsc=r19" | |
52e12ad0 | 5398 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5399 | (set_attr "predicable" "no")]) |
ce152ef8 | 5400 | |
0024a804 JW |
5401 | ;; ??? The explicit stops are not ideal. It would be better if |
5402 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5403 | ;; fixed later. This avoids an RSE DV. | |
5404 | ||
ce152ef8 | 5405 | (define_insn "flushrs" |
086c0f96 | 5406 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5407 | "" |
0024a804 | 5408 | ";;\;flushrs\;;;" |
582d11e6 JW |
5409 | [(set_attr "itanium_class" "rse_m") |
5410 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
5411 | \f |
5412 | ;; :::::::::::::::::::: | |
5413 | ;; :: | |
5414 | ;; :: Miscellaneous instructions | |
5415 | ;; :: | |
5416 | ;; :::::::::::::::::::: | |
5417 | ||
839a4992 | 5418 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
5419 | ;; be emitting ";;" to force a break in the instruction packing. |
5420 | ||
5421 | ;; No operation, needed in case the user uses -g but not -O. | |
5422 | (define_insn "nop" | |
5423 | [(const_int 0)] | |
5424 | "" | |
5425 | "nop 0" | |
30028c85 | 5426 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 5427 | |
2130b7fb BS |
5428 | (define_insn "nop_m" |
5429 | [(const_int 1)] | |
5430 | "" | |
5431 | "nop.m 0" | |
5432 | [(set_attr "itanium_class" "nop_m")]) | |
5433 | ||
5434 | (define_insn "nop_i" | |
5435 | [(const_int 2)] | |
5436 | "" | |
5437 | "nop.i 0" | |
5438 | [(set_attr "itanium_class" "nop_i")]) | |
5439 | ||
5440 | (define_insn "nop_f" | |
5441 | [(const_int 3)] | |
5442 | "" | |
5443 | "nop.f 0" | |
5444 | [(set_attr "itanium_class" "nop_f")]) | |
5445 | ||
5446 | (define_insn "nop_b" | |
5447 | [(const_int 4)] | |
5448 | "" | |
5449 | "nop.b 0" | |
5450 | [(set_attr "itanium_class" "nop_b")]) | |
5451 | ||
5452 | (define_insn "nop_x" | |
5453 | [(const_int 5)] | |
5454 | "" | |
5455 | "" | |
fa978426 AS |
5456 | [(set_attr "itanium_class" "nop_x") |
5457 | (set_attr "empty" "yes")]) | |
2130b7fb | 5458 | |
30028c85 VM |
5459 | ;; The following insn will be never generated. It is used only by |
5460 | ;; insn scheduler to change state before advancing cycle. | |
5461 | (define_insn "pre_cycle" | |
5462 | [(const_int 6)] | |
5463 | "" | |
5464 | "" | |
5465 | [(set_attr "itanium_class" "pre_cycle")]) | |
5466 | ||
2130b7fb | 5467 | (define_insn "bundle_selector" |
086c0f96 | 5468 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5469 | "" |
1d5d7a21 | 5470 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5471 | [(set_attr "itanium_class" "ignore") |
5472 | (set_attr "predicable" "no")]) | |
5473 | ||
c65ebc55 JW |
5474 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5475 | ;; point. | |
5476 | (define_insn "blockage" | |
086c0f96 | 5477 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5478 | "" |
5479 | "" | |
52e12ad0 | 5480 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5481 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5482 | |
5483 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5484 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5485 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5486 | "" |
5487 | ";;" | |
52e12ad0 | 5488 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
5489 | (set_attr "predicable" "no") |
5490 | (set_attr "empty" "yes")]) | |
c65ebc55 | 5491 | |
26406018 RH |
5492 | (define_expand "trap" |
5493 | [(trap_if (const_int 1) (const_int 0))] | |
5494 | "" | |
5495 | "") | |
5496 | ||
5497 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
5498 | ;; produces worse code that setting the slot type to A. | |
5499 | ||
5500 | (define_insn "*trap" | |
5501 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
5502 | "" | |
5503 | "break %0" | |
048d0d36 | 5504 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 | 5505 | |
f90b7a5a PB |
5506 | (define_expand "ctrapbi4" |
5507 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5508 | [(match_operand:BI 1 "register_operand" "") | |
5509 | (match_operand:BI 2 "const_int_operand" "")]) | |
5510 | (match_operand 3 "" ""))] | |
26406018 | 5511 | "" |
f90b7a5a PB |
5512 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
5513 | ||
5514 | (define_expand "ctrapsi4" | |
5515 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5516 | [(match_operand:SI 1 "gr_register_operand" "") | |
5517 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
5518 | (match_operand 3 "" ""))] | |
5519 | "" | |
5520 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5521 | ||
5522 | (define_expand "ctrapdi4" | |
5523 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5524 | [(match_operand:DI 1 "gr_register_operand" "") | |
5525 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
5526 | (match_operand 3 "" ""))] | |
5527 | "" | |
5528 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5529 | ||
5530 | (define_expand "ctrapsf4" | |
5531 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5532 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
5533 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
5534 | (match_operand 3 "" ""))] | |
5535 | "" | |
5536 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5537 | ||
5538 | (define_expand "ctrapdf4" | |
5539 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5540 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
5541 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
5542 | (match_operand 3 "" ""))] | |
5543 | "" | |
5544 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5545 | ||
5546 | (define_expand "ctrapxf4" | |
5547 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5548 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
5549 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
5550 | (match_operand 3 "" ""))] | |
5551 | "" | |
5552 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5553 | ||
5554 | (define_expand "ctraptf4" | |
5555 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
5556 | [(match_operand:TF 1 "gr_register_operand" "") | |
5557 | (match_operand:TF 2 "gr_register_operand" "")]) | |
5558 | (match_operand 3 "" ""))] | |
5559 | "TARGET_HPUX" | |
5560 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5561 | ||
26406018 RH |
5562 | |
5563 | (define_insn "*conditional_trap" | |
5564 | [(trap_if (match_operator 0 "predicate_operator" | |
5565 | [(match_operand:BI 1 "register_operand" "c") | |
5566 | (const_int 0)]) | |
5567 | (match_operand 2 "const_int_operand" ""))] | |
5568 | "" | |
5cf63e3f | 5569 | "(%J0) break %2" |
048d0d36 | 5570 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
5571 | (set_attr "predicable" "no")]) |
5572 | ||
f12f25a7 | 5573 | (define_insn "break_f" |
086c0f96 | 5574 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
5575 | "" |
5576 | "break.f 0" | |
5577 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5578 | |
5579 | (define_insn "prefetch" | |
5580 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5581 | (match_operand:DI 1 "const_int_operand" "n") | |
5582 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5583 | "" | |
5584 | { | |
5585 | static const char * const alt[2][4] = { | |
b3656137 | 5586 | { |
92cbea22 L |
5587 | "%,lfetch.nta [%0]", |
5588 | "%,lfetch.nt1 [%0]", | |
5589 | "%,lfetch.nt2 [%0]", | |
5590 | "%,lfetch [%0]" | |
b3656137 KG |
5591 | }, |
5592 | { | |
92cbea22 L |
5593 | "%,lfetch.excl.nta [%0]", |
5594 | "%,lfetch.excl.nt1 [%0]", | |
5595 | "%,lfetch.excl.nt2 [%0]", | |
5596 | "%,lfetch.excl [%0]" | |
b3656137 | 5597 | } |
44eca121 JJ |
5598 | }; |
5599 | int i = (INTVAL (operands[1])); | |
5600 | int j = (INTVAL (operands[2])); | |
5601 | ||
e820471b NS |
5602 | gcc_assert (i == 0 || i == 1); |
5603 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
5604 | return alt[i][j]; |
5605 | } | |
5606 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5607 | \f |
5608 | ;; Non-local goto support. | |
5609 | ||
5610 | (define_expand "save_stack_nonlocal" | |
5611 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5612 | (use (match_operand:DI 1 "register_operand" ""))] | |
5613 | "" | |
c65ebc55 JW |
5614 | { |
5615 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5616 | \"__ia64_save_stack_nonlocal\"), | |
bbbbb16a | 5617 | LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode, |
c65ebc55 JW |
5618 | operands[1], Pmode); |
5619 | DONE; | |
1d5d7a21 | 5620 | }) |
c65ebc55 JW |
5621 | |
5622 | (define_expand "nonlocal_goto" | |
5623 | [(use (match_operand 0 "general_operand" "")) | |
5624 | (use (match_operand 1 "general_operand" "")) | |
5625 | (use (match_operand 2 "general_operand" "")) | |
5626 | (use (match_operand 3 "general_operand" ""))] | |
5627 | "" | |
c65ebc55 | 5628 | { |
c65ebc55 | 5629 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5630 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5631 | operands[1], Pmode, |
c65ebc55 | 5632 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5633 | operands[3], Pmode); |
c65ebc55 JW |
5634 | emit_barrier (); |
5635 | DONE; | |
1d5d7a21 | 5636 | }) |
c65ebc55 | 5637 | |
39a5cfa4 SE |
5638 | (define_insn_and_split "nonlocal_goto_receiver" |
5639 | [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)] | |
5640 | "" | |
5641 | "#" | |
5642 | "reload_completed" | |
5643 | [(const_int 0)] | |
5644 | { | |
5645 | ia64_reload_gp (); | |
5646 | DONE; | |
5647 | }) | |
5648 | ||
b39eb2f9 RH |
5649 | (define_insn_and_split "builtin_setjmp_receiver" |
5650 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 5651 | "" |
b39eb2f9 RH |
5652 | "#" |
5653 | "reload_completed" | |
5654 | [(const_int 0)] | |
97e242b0 | 5655 | { |
599aedd9 | 5656 | ia64_reload_gp (); |
c65ebc55 | 5657 | DONE; |
1d5d7a21 | 5658 | }) |
c65ebc55 | 5659 | |
0c96007e AM |
5660 | (define_expand "eh_epilogue" |
5661 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5662 | (use (match_operand:DI 1 "register_operand" "r")) | |
5663 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5664 | "" | |
0c96007e AM |
5665 | { |
5666 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5667 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5668 | ||
5669 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5670 | { | |
5671 | emit_move_insn (bsp, operands[0]); | |
5672 | operands[0] = bsp; | |
5673 | } | |
5674 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5675 | { | |
5676 | emit_move_insn (sp, operands[2]); | |
5677 | operands[2] = sp; | |
5678 | } | |
c41c1387 RS |
5679 | emit_use (sp); |
5680 | emit_use (bsp); | |
0c96007e AM |
5681 | |
5682 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5683 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5684 | }) |
9525c690 JW |
5685 | \f |
5686 | ;; Builtin apply support. | |
5687 | ||
5688 | (define_expand "restore_stack_nonlocal" | |
5689 | [(use (match_operand:DI 0 "register_operand" "")) | |
5690 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5691 | "" | |
9525c690 JW |
5692 | { |
5693 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5694 | "__ia64_restore_stack_nonlocal"), |
bbbbb16a | 5695 | LCT_NORMAL, VOIDmode, 1, |
9525c690 JW |
5696 | copy_to_reg (XEXP (operands[1], 0)), Pmode); |
5697 | DONE; | |
1d5d7a21 | 5698 | }) |
9525c690 | 5699 | |
e5bde68a RH |
5700 | \f |
5701 | ;; Predication. | |
5702 | ||
5703 | (define_cond_exec | |
5704 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5705 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5706 | (const_int 0)])] |
5707 | "" | |
5708 | "(%J0)") | |
3b572406 RH |
5709 | |
5710 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 5711 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 5712 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 5713 | "" |
054451ea | 5714 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5715 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5716 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5717 | |
5718 | (define_insn "safe_across_calls_all" | |
086c0f96 | 5719 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
5720 | "" |
5721 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5722 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5723 | (set_attr "predicable" "no")]) |
5724 | ||
5725 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 5726 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 5727 | "" |
ca3920ad | 5728 | { |
1bc7c5b6 | 5729 | emit_safe_across_calls (); |
1d5d7a21 RH |
5730 | return ""; |
5731 | } | |
52e12ad0 | 5732 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5733 | (set_attr "predicable" "no")]) |
5734 | ||
27a9b99d | 5735 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
5736 | ;; pointer. This is used by the HP-UX 32 bit mode. |
5737 | ||
5738 | (define_insn "ptr_extend" | |
5739 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
5740 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
5741 | UNSPEC_ADDP4))] | |
6dd12198 SE |
5742 | "" |
5743 | "addp4 %0 = 0,%1" | |
5744 | [(set_attr "itanium_class" "ialu")]) | |
5745 | ||
e206a74f SE |
5746 | ;; |
5747 | ;; Optimizations for ptr_extend | |
5748 | ||
36c216e5 | 5749 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
5750 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5751 | (unspec:DI | |
5752 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5753 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 5754 | UNSPEC_ADDP4))] |
08744705 | 5755 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5756 | "addp4 %0 = %2, %1" |
5757 | [(set_attr "itanium_class" "ialu")]) | |
5758 | ||
5759 | (define_insn "*ptr_extend_plus_2" | |
5760 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5761 | (unspec:DI | |
5762 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5763 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 5764 | UNSPEC_ADDP4))] |
08744705 | 5765 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5766 | "addp4 %0 = %1, %2" |
5767 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 5768 | |
d26afa4f SE |
5769 | ;; |
5770 | ;; Get instruction pointer | |
5771 | ||
5772 | (define_insn "ip_value" | |
5773 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5774 | (pc))] | |
5775 | "" | |
5776 | "mov %0 = ip" | |
6107a6ae | 5777 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 5778 | |
f61134e8 RH |
5779 | ;; Vector operations |
5780 | (include "vect.md") | |
af795c3c RH |
5781 | ;; Atomic operations |
5782 | (include "sync.md") | |
4883241c SE |
5783 | ;; New division operations |
5784 | (include "div.md") |