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ac445222 1;; IA-64 Machine description template
b9c74b4d 2;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
71e45bc2 3;; 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
ac445222 4;; Contributed by James E. Wilson <wilson@cygnus.com> and
5;; David Mosberger <davidm@hpl.hp.com>.
6
73f45a5c 7;; This file is part of GCC.
ac445222 8
73f45a5c 9;; GCC is free software; you can redistribute it and/or modify
ac445222 10;; it under the terms of the GNU General Public License as published by
038d1e19 11;; the Free Software Foundation; either version 3, or (at your option)
ac445222 12;; any later version.
13
73f45a5c 14;; GCC is distributed in the hope that it will be useful,
ac445222 15;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17;; GNU General Public License for more details.
18
19;; You should have received a copy of the GNU General Public License
038d1e19 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
ac445222 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24
ac445222 25;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26;; reload. This will be fixed once scheduling support is turned on.
27
28;; ??? Optimize for post-increment addressing modes.
29
30;; ??? fselect is not supported, because there is no integer register
31;; equivalent.
32
33;; ??? fp abs/min/max instructions may also work for integer values.
34
35;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36;; it assumes the operand is a register and takes REGNO of it without checking.
37
38;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39;; it assumes the operand is a register and takes REGNO of it without checking.
40
41;; ??? Go through list of documented named patterns and look for more to
42;; implement.
43
44;; ??? Go through instruction manual and look for more instructions that
45;; can be emitted.
46
47;; ??? Add function unit scheduling info for Itanium (TM) processor.
48
276f19f8 49;; ??? Need a better way to describe alternate fp status registers.
50
defa4417 51(define_c_enum "unspec"
c87e09ad 52 [; Relocations
defa4417 53 UNSPEC_LTOFF_DTPMOD
54 UNSPEC_LTOFF_DTPREL
55 UNSPEC_DTPREL
56 UNSPEC_LTOFF_TPREL
57 UNSPEC_TPREL
58 UNSPEC_DTPMOD
59
60 UNSPEC_LD_BASE
61 UNSPEC_GR_SPILL
62 UNSPEC_GR_RESTORE
63 UNSPEC_FR_SPILL
64 UNSPEC_FR_RESTORE
65 UNSPEC_FR_RECIP_APPROX
66 UNSPEC_PRED_REL_MUTEX
67 UNSPEC_GETF_EXP
68 UNSPEC_PIC_CALL
69 UNSPEC_MF
70 UNSPEC_CMPXCHG_ACQ
e35728c4 71 UNSPEC_CMPXCHG_REL
defa4417 72 UNSPEC_FETCHADD_ACQ
e35728c4 73 UNSPEC_FETCHADD_REL
defa4417 74 UNSPEC_BSP_VALUE
75 UNSPEC_FLUSHRS
76 UNSPEC_BUNDLE_SELECTOR
77 UNSPEC_ADDP4
78 UNSPEC_PROLOGUE_USE
79 UNSPEC_RET_ADDR
80 UNSPEC_SETF_EXP
81 UNSPEC_FR_SQRT_RECIP_APPROX
82 UNSPEC_SHRP
83 UNSPEC_COPYSIGN
84 UNSPEC_VECT_EXTR
85 UNSPEC_LDA
86 UNSPEC_LDS
87 UNSPEC_LDS_A
88 UNSPEC_LDSA
89 UNSPEC_LDCCLR
90 UNSPEC_LDCNC
91 UNSPEC_CHKACLR
92 UNSPEC_CHKANC
93 UNSPEC_CHKS
94 UNSPEC_FR_RECIP_APPROX_RES
95 UNSPEC_FR_SQRT_RECIP_APPROX_RES
e2b723ca 96 ])
97
defa4417 98(define_c_enum "unspecv" [
99 UNSPECV_ALLOC
100 UNSPECV_BLOCKAGE
101 UNSPECV_INSN_GROUP_BARRIER
102 UNSPECV_BREAK
103 UNSPECV_SET_BSP
104 UNSPECV_PSAC_ALL ; pred.safe_across_calls
105 UNSPECV_PSAC_NORMAL
106 UNSPECV_SETJMP_RECEIVER
107 UNSPECV_GOTO_RECEIVER
28d5c3d9 108 UNSPECV_PROBE_STACK_ADDRESS
109 UNSPECV_PROBE_STACK_RANGE
e2b723ca 110 ])
cbf464bd 111
b3371e51 112(include "predicates.md")
269f7060 113(include "constraints.md")
ac445222 114\f
115;; ::::::::::::::::::::
116;; ::
117;; :: Attributes
118;; ::
119;; ::::::::::::::::::::
120
58ada791 121;; Processor type. This attribute must exactly match the processor_type
122;; enumeration in ia64.h.
b9c74b4d 123(define_attr "cpu" "itanium,itanium2"
124 (const (symbol_ref "((enum attr_cpu) ia64_tune)")))
58ada791 125
ac445222 126;; Instruction type. This primarily determines how instructions can be
127;; packed in bundles, and secondarily affects scheduling to function units.
128
129;; A alu, can go in I or M syllable of a bundle
130;; I integer
131;; M memory
132;; F floating-point
133;; B branch
134;; L long immediate, takes two syllables
135;; S stop bit
136
137;; ??? Should not have any pattern with type unknown. Perhaps add code to
138;; check this in md_reorg? Currently use unknown for patterns which emit
139;; multiple instructions, patterns which emit 0 instructions, and patterns
140;; which emit instruction that can go in any slot (e.g. nop).
141
d2ba5713 142(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
4d053aca 143 fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
ea13ae4c 144 ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
a5c5f9d3 145 st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
146 nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
d2ba5713 147 (const_string "unknown"))
bf6ff2f6 148
ea13ae4c 149;; chk_s_i has an I and an M form; use type A for convenience.
a0bb0d20 150(define_attr "type" "unknown,A,I,M,F,B,L,X,S"
4d053aca 151 (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
bf6ff2f6 152 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
153 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
0df58423 154 (eq_attr "itanium_class" "lfetch") (const_string "M")
ea13ae4c 155 (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M")
156 (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua")
a5c5f9d3 157 (const_string "A")
a0bb0d20 158 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
159 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
bf6ff2f6 160 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
161 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
a0bb0d20 162 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
163 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
bf6ff2f6 164 (eq_attr "itanium_class" "stop_bit") (const_string "S")
a0bb0d20 165 (eq_attr "itanium_class" "nop_x") (const_string "X")
bf6ff2f6 166 (eq_attr "itanium_class" "long_i") (const_string "L")]
167 (const_string "unknown")))
ac445222 168
a0bb0d20 169(define_attr "itanium_requires_unit0" "no,yes"
170 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
171 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
172 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
173 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
174 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
175 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
176 (const_string "no")))
177
945c34bb 178;; Predication. True iff this instruction can be predicated.
179
180(define_attr "predicable" "no,yes" (const_string "yes"))
181
2b71c761 182;; Empty. True iff this insn does not generate any code.
183
184(define_attr "empty" "no,yes" (const_string "no"))
185
5f121199 186;; True iff this insn must be the first insn of an instruction group.
187;; This is true for the alloc instruction, and will also be true of others
188;; when we have full intrinsics support.
189
190(define_attr "first_insn" "no,yes" (const_string "no"))
ea13ae4c 191
192(define_attr "data_speculative" "no,yes" (const_string "no"))
193
194(define_attr "control_speculative" "no,yes" (const_string "no"))
195
196(define_attr "check_load" "no,yes" (const_string "no"))
cf7898a6 197
198(define_attr "speculable1" "no,yes" (const_string "no"))
199
200(define_attr "speculable2" "no,yes" (const_string "no"))
ac445222 201\f
58ada791 202;; DFA descriptions of ia64 processors used for insn scheduling and
203;; bundling.
204
205(automata_option "ndfa")
206
207;; Uncomment the following line to output automata for debugging.
208;; (automata_option "v")
209
210(automata_option "w")
211
58ada791 212(include "itanium2.md")
dd7870fa 213\f
214;; Mode iterators
215
216; Used for truncations from XFmode.
217(define_mode_iterator MODE_SDF [SF DF])
58ada791 218
dd7870fa 219(define_mode_attr suffix [
220 (SF ".s")
221 (DF ".d")
222 (XF "")
223 ])
ac445222 224\f
225;; ::::::::::::::::::::
226;; ::
227;; :: Moves
228;; ::
229;; ::::::::::::::::::::
230
33c8f6d1 231;; Set of a single predicate register. This is only used to implement
232;; pr-to-pr move and complement.
233
690f2a81 234(define_insn "movcci"
235 [(set (match_operand:CCI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*m,*r")
236 (match_operand:CCI 1 "move_operand" " O,n, c, c,*r,*m,*r,*r"))]
33c8f6d1 237 ""
238 "@
239 cmp.ne %0, p0 = r0, r0
240 cmp.eq %0, p0 = r0, r0
690f2a81 241 (%1) cmp.eq.unc %0, p0 = r0, r0
242 #
243 tbit.nz %0, p0 = %1, 0
244 ld1%O1 %0 = %1%P1
245 st1%Q0 %0 = %1%P0
246 mov %0 = %1"
247 [(set_attr "itanium_class" "icmp,icmp,icmp,unknown,tbit,ld,st,ialu")
33c8f6d1 248 (set_attr "predicable" "no")])
249
690f2a81 250(define_split
251 [(set (match_operand:CCI 0 "register_operand" "")
252 (match_operand:CCI 1 "register_operand" ""))]
253 "reload_completed
254 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
255 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
256 [(set (match_dup 2) (const_int 0))
257 (cond_exec (ne (match_dup 3) (const_int 0))
258 (set (match_dup 2) (const_int 1)))]
259 "operands[2] = gen_rtx_REG (BImode, REGNO (operands[0]));
260 operands[3] = gen_rtx_REG (BImode, REGNO (operands[1]));")
261
33c8f6d1 262(define_insn "movbi"
0d442ac4 263 [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
264 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
33c8f6d1 265 ""
266 "@
267 cmp.ne %0, %I0 = r0, r0
268 cmp.eq %0, %I0 = r0, r0
269 #
270 #
271 tbit.nz %0, %I0 = %1, 0
272 adds %0 = %1, r0
273 ld1%O1 %0 = %1%P1
aef29c61 274 st1%Q0 %0 = %1%P0
275 mov %0 = %1"
cf7898a6 276 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
277 (set_attr "speculable1" "yes")
278 (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")])
33c8f6d1 279
280(define_split
281 [(set (match_operand:BI 0 "register_operand" "")
282 (match_operand:BI 1 "register_operand" ""))]
283 "reload_completed
284 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
285 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
286 [(cond_exec (ne (match_dup 1) (const_int 0))
287 (set (match_dup 0) (const_int 1)))
288 (cond_exec (eq (match_dup 1) (const_int 0))
289 (set (match_dup 0) (const_int 0)))]
290 "")
291
292(define_split
293 [(set (match_operand:BI 0 "register_operand" "")
294 (match_operand:BI 1 "register_operand" ""))]
295 "reload_completed
296 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
297 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
298 [(set (match_dup 2) (match_dup 4))
299 (set (match_dup 3) (match_dup 5))
e2b723ca 300 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
33c8f6d1 301 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
302 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
303 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
304 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
305
ac445222 306(define_expand "movqi"
307 [(set (match_operand:QI 0 "general_operand" "")
308 (match_operand:QI 1 "general_operand" ""))]
309 ""
ac445222 310{
c87e09ad 311 rtx op1 = ia64_expand_move (operands[0], operands[1]);
312 if (!op1)
313 DONE;
314 operands[1] = op1;
d2ba5713 315})
ac445222 316
cf7898a6 317(define_insn "movqi_internal"
40988080 318 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
319 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
8b0dd03f 320 "ia64_move_ok (operands[0], operands[1])"
ac445222 321 "@
08f8478f 322 mov %0 = %r1
ac445222 323 addl %0 = %1, r0
324 ld1%O1 %0 = %1%P1
08f8478f 325 st1%Q0 %0 = %r1%P0
ac445222 326 getf.sig %0 = %1
08f8478f 327 setf.sig %0 = %r1
328 mov %0 = %1"
cf7898a6 329 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
330 (set_attr "speculable1" "yes")
331 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
ac445222 332
333(define_expand "movhi"
334 [(set (match_operand:HI 0 "general_operand" "")
335 (match_operand:HI 1 "general_operand" ""))]
336 ""
ac445222 337{
c87e09ad 338 rtx op1 = ia64_expand_move (operands[0], operands[1]);
339 if (!op1)
340 DONE;
341 operands[1] = op1;
d2ba5713 342})
ac445222 343
cf7898a6 344(define_insn "movhi_internal"
40988080 345 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
346 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
8b0dd03f 347 "ia64_move_ok (operands[0], operands[1])"
ac445222 348 "@
08f8478f 349 mov %0 = %r1
ac445222 350 addl %0 = %1, r0
351 ld2%O1 %0 = %1%P1
08f8478f 352 st2%Q0 %0 = %r1%P0
ac445222 353 getf.sig %0 = %1
08f8478f 354 setf.sig %0 = %r1
355 mov %0 = %1"
cf7898a6 356 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
357 (set_attr "speculable1" "yes")
358 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
ac445222 359
360(define_expand "movsi"
361 [(set (match_operand:SI 0 "general_operand" "")
362 (match_operand:SI 1 "general_operand" ""))]
363 ""
ac445222 364{
c87e09ad 365 rtx op1 = ia64_expand_move (operands[0], operands[1]);
366 if (!op1)
367 DONE;
368 operands[1] = op1;
d2ba5713 369})
ac445222 370
cf7898a6 371(define_insn "movsi_internal"
80538812 372 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
373 (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
8b0dd03f 374 "ia64_move_ok (operands[0], operands[1])"
ac445222 375 "@
08f8478f 376 mov %0 = %r1
ac445222 377 addl %0 = %1, r0
80538812 378 addp4 %0 = %1 - 0x100000000, r0
ac445222 379 movl %0 = %1
380 ld4%O1 %0 = %1%P1
08f8478f 381 st4%Q0 %0 = %r1%P0
ac445222 382 getf.sig %0 = %1
08f8478f 383 setf.sig %0 = %r1
cac50a9f 384 mov %0 = %1
385 mov %0 = %1
386 mov %0 = %r1"
d2ba5713 387 ;; frar_m, toar_m ??? why not frar_i and toar_i
cf7898a6 388 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
389 (set_attr "speculable1" "yes")
390 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")])
ac445222 391
392(define_expand "movdi"
393 [(set (match_operand:DI 0 "general_operand" "")
394 (match_operand:DI 1 "general_operand" ""))]
395 ""
ac445222 396{
c87e09ad 397 rtx op1 = ia64_expand_move (operands[0], operands[1]);
398 if (!op1)
399 DONE;
400 operands[1] = op1;
d2ba5713 401})
ac445222 402
cf7898a6 403(define_insn "movdi_internal"
40988080 404 [(set (match_operand:DI 0 "destination_operand"
80538812 405 "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
40988080 406 (match_operand:DI 1 "move_operand"
80538812 407 "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
8b0dd03f 408 "ia64_move_ok (operands[0], operands[1])"
7a525da6 409{
410 static const char * const alt[] = {
d2ba5713 411 "%,mov %0 = %r1",
412 "%,addl %0 = %1, r0",
80538812 413 "%,addp4 %0 = %1 - 0x100000000, r0",
d2ba5713 414 "%,movl %0 = %1",
415 "%,ld8%O1 %0 = %1%P1",
416 "%,st8%Q0 %0 = %r1%P0",
417 "%,getf.sig %0 = %1",
418 "%,setf.sig %0 = %r1",
419 "%,mov %0 = %1",
420 "%,ldf8 %0 = %1%P1",
421 "%,stf8 %0 = %1%P0",
422 "%,mov %0 = %1",
423 "%,mov %0 = %r1",
424 "%,mov %0 = %1",
425 "%,mov %0 = %1",
426 "%,mov %0 = %1",
427 "%,mov %0 = %1",
428 "mov %0 = pr",
429 "mov pr = %1, -1"
7a525da6 430 };
431
c5c17bca 432 gcc_assert (which_alternative != 2 || TARGET_NO_PIC
433 || !symbolic_operand (operands[1], VOIDmode));
7a525da6 434
435 return alt[which_alternative];
d2ba5713 436}
cf7898a6 437 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
438 (set_attr "speculable1" "yes")
439 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
ac445222 440
fd781bb2 441(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
74f4459c 442(define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")])
fd781bb2 443(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
ea13ae4c 444
445(define_mode_attr output_a [
446 (BI "ld1.a %0 = %1%P1")
447 (QI "ld1.a %0 = %1%P1")
448 (HI "ld2.a %0 = %1%P1")
449 (SI "ld4.a %0 = %1%P1")
450 (DI
451 "@
452 ld8.a %0 = %1%P1
453 ldf8.a %0 = %1%P1")
454 (SF
455 "@
456 ldfs.a %0 = %1%P1
457 ld4.a %0 = %1%P1")
458 (DF
459 "@
460 ldfd.a %0 = %1%P1
461 ld8.a %0 = %1%P1")
462 (XF "ldfe.a %0 = %1%P1")
463 (TI "ldfp8.a %X0 = %1%P1")])
464
465(define_mode_attr output_s [
466 (BI "ld1.s %0 = %1%P1")
467 (QI "ld1.s %0 = %1%P1")
468 (HI "ld2.s %0 = %1%P1")
469 (SI "ld4.s %0 = %1%P1")
470 (DI
471 "@
472 ld8.s %0 = %1%P1
473 ldf8.s %0 = %1%P1")
474 (SF
475 "@
476 ldfs.s %0 = %1%P1
477 ld4.s %0 = %1%P1")
478 (DF
479 "@
480 ldfd.s %0 = %1%P1
481 ld8.s %0 = %1%P1")
482 (XF "ldfe.s %0 = %1%P1")
483 (TI "ldfp8.s %X0 = %1%P1")])
484
485(define_mode_attr output_sa [
486 (BI "ld1.sa %0 = %1%P1")
487 (QI "ld1.sa %0 = %1%P1")
488 (HI "ld2.sa %0 = %1%P1")
489 (SI "ld4.sa %0 = %1%P1")
490 (DI
491 "@
492 ld8.sa %0 = %1%P1
493 ldf8.sa %0 = %1%P1")
494 (SF
495 "@
496 ldfs.sa %0 = %1%P1
497 ld4.sa %0 = %1%P1")
498 (DF
499 "@
500 ldfd.sa %0 = %1%P1
501 ld8.sa %0 = %1%P1")
502 (XF "ldfe.sa %0 = %1%P1")
503 (TI "ldfp8.sa %X0 = %1%P1")])
504
505(define_mode_attr output_c_clr [
506 (BI "ld1.c.clr%O1 %0 = %1%P1")
507 (QI "ld1.c.clr%O1 %0 = %1%P1")
508 (HI "ld2.c.clr%O1 %0 = %1%P1")
509 (SI "ld4.c.clr%O1 %0 = %1%P1")
510 (DI
511 "@
512 ld8.c.clr%O1 %0 = %1%P1
513 ldf8.c.clr %0 = %1%P1")
514 (SF
515 "@
516 ldfs.c.clr %0 = %1%P1
517 ld4.c.clr%O1 %0 = %1%P1")
518 (DF
519 "@
520 ldfd.c.clr %0 = %1%P1
521 ld8.c.clr%O1 %0 = %1%P1")
522 (XF "ldfe.c.clr %0 = %1%P1")
523 (TI "ldfp8.c.clr %X0 = %1%P1")])
524
cf7898a6 525(define_mode_attr output_c_nc [
526 (BI "ld1.c.nc%O1 %0 = %1%P1")
527 (QI "ld1.c.nc%O1 %0 = %1%P1")
528 (HI "ld2.c.nc%O1 %0 = %1%P1")
529 (SI "ld4.c.nc%O1 %0 = %1%P1")
530 (DI
531 "@
532 ld8.c.nc%O1 %0 = %1%P1
533 ldf8.c.nc %0 = %1%P1")
534 (SF
535 "@
536 ldfs.c.nc %0 = %1%P1
537 ld4.c.nc%O1 %0 = %1%P1")
538 (DF
539 "@
540 ldfd.c.nc %0 = %1%P1
541 ld8.c.nc%O1 %0 = %1%P1")
542 (XF "ldfe.c.nc %0 = %1%P1")
543 (TI "ldfp8.c.nc %X0 = %1%P1")])
544
ea13ae4c 545(define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
546(define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
547(define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
548
549(define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")])
550
1c42a59d 551;; Define register predicate prefix.
552;; We can generate speculative loads only for general and fp registers - this
85694bac 553;; is constrained in ia64.c: ia64_speculate_insn ().
ea13ae4c 554(define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
555
556(define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
557(define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")])
558(define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")])
559
560(define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")])
561
562(define_insn "mov<mode>_advanced"
563 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
564 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))]
565 "ia64_move_ok (operands[0], operands[1])"
566 "<output_a>"
567 [(set_attr "itanium_class" "<ld_class>")
568 (set_attr "data_speculative" "<attr_yes>")])
569
570(define_insn "zero_extend<mode>di2_advanced"
571 [(set (match_operand:DI 0 "gr_register_operand" "=r")
572 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))]
573 ""
574 "<output_a>"
575 [(set_attr "itanium_class" "<ld_class>")
576 (set_attr "data_speculative" "<attr_yes>")])
577
578(define_insn "mov<mode>_speculative"
579 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
580 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))]
581 "ia64_move_ok (operands[0], operands[1])"
582 "<output_s>"
583 [(set_attr "itanium_class" "<ld_class>")
584 (set_attr "control_speculative" "<attr_yes>")])
585
586(define_insn "zero_extend<mode>di2_speculative"
587 [(set (match_operand:DI 0 "gr_register_operand" "=r")
588 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))]
589 ""
590 "<output_s>"
591 [(set_attr "itanium_class" "<ld_class>")
592 (set_attr "control_speculative" "<attr_yes>")])
593
594(define_insn "mov<mode>_speculative_advanced"
595 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
596 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))]
597 "ia64_move_ok (operands[0], operands[1])"
598 "<output_sa>"
599 [(set_attr "itanium_class" "<ld_class>")
600 (set_attr "data_speculative" "<attr_yes>")
601 (set_attr "control_speculative" "<attr_yes>")])
602
cf7898a6 603(define_insn "mov<mode>_speculative_a"
604 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
605 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
606 "ia64_move_ok (operands[0], operands[1])"
607 "<output_sa>"
608 [(set_attr "itanium_class" "<ld_class>")
609 (set_attr "data_speculative" "<attr_yes>")
610 (set_attr "control_speculative" "<attr_yes>")])
611
ea13ae4c 612(define_insn "zero_extend<mode>di2_speculative_advanced"
613 [(set (match_operand:DI 0 "gr_register_operand" "=r")
614 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
615 ""
616 "<output_sa>"
617 [(set_attr "itanium_class" "<ld_class>")
618 (set_attr "data_speculative" "<attr_yes>")
619 (set_attr "control_speculative" "<attr_yes>")])
620
cf7898a6 621(define_insn "zero_extend<mode>di2_speculative_a"
622 [(set (match_operand:DI 0 "gr_register_operand" "=r")
623 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
624 ""
625 "<output_sa>"
626 [(set_attr "itanium_class" "<ld_class>")
627 (set_attr "data_speculative" "<attr_yes>")
628 (set_attr "control_speculative" "<attr_yes>")])
629
ea13ae4c 630(define_insn "mov<mode>_clr"
631 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
632 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
633 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
634 (match_dup 0)))]
635 "ia64_move_ok (operands[0], operands[1])"
636 "<output_c_clr>"
637 [(set_attr "itanium_class" "<ld_class>")
638 (set_attr "check_load" "<attr_yes>")])
639
cf7898a6 640(define_insn "mov<mode>_nc"
641 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
642 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
643 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
644 (match_dup 0)))]
645 "ia64_move_ok (operands[0], operands[1])"
646 "<output_c_nc>"
647 [(set_attr "itanium_class" "<ld_class>")
648 (set_attr "check_load" "<attr_yes>")])
649
ea13ae4c 650(define_insn "zero_extend<mode>di2_clr"
651 [(set (match_operand:DI 0 "gr_register_operand" "+r")
652 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
653 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
654 (match_dup 0)))]
655 ""
656 "<output_c_clr>"
657 [(set_attr "itanium_class" "<ld_class>")
658 (set_attr "check_load" "<attr_yes>")])
659
cf7898a6 660(define_insn "zero_extend<mode>di2_nc"
661 [(set (match_operand:DI 0 "gr_register_operand" "+r")
662 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
663 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
664 (match_dup 0)))]
665 ""
666 "<output_c_nc>"
667 [(set_attr "itanium_class" "<ld_class>")
668 (set_attr "check_load" "<attr_yes>")])
669
ea13ae4c 670(define_insn "advanced_load_check_clr_<mode>"
671 [(set (pc)
672 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
673 (pc)
674 (label_ref (match_operand 1 "" ""))))]
675 ""
676 "chk.a.clr %0, %l1"
677 [(set_attr "itanium_class" "<chka_class>")])
678
cf7898a6 679(define_insn "advanced_load_check_nc_<mode>"
680 [(set (pc)
681 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
682 (pc)
683 (label_ref (match_operand 1 "" ""))))]
684 ""
685 "chk.a.clr %0, %l1"
686 [(set_attr "itanium_class" "<chka_class>")])
687
ea13ae4c 688(define_insn "speculation_check_<mode>"
689 [(set (pc)
690 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
691 (pc)
692 (label_ref (match_operand 1 "" ""))))]
693 ""
694 "chk.s %0, %l1"
695 [(set_attr "itanium_class" "<chks_class>")])
696
7a525da6 697(define_split
58b90768 698 [(set (match_operand 0 "register_operand" "")
699 (match_operand 1 "symbolic_operand" ""))]
3ec3c84f 700 "reload_completed"
7a525da6 701 [(const_int 0)]
7a525da6 702{
3ec3c84f 703 if (ia64_expand_load_address (operands[0], operands[1]))
704 DONE;
705 else
706 FAIL;
d2ba5713 707})
7a525da6 708
ac445222 709(define_expand "load_fptr"
3ec3c84f 710 [(set (match_operand:DI 0 "register_operand" "")
711 (plus:DI (match_dup 2) (match_operand 1 "function_operand" "")))
712 (set (match_dup 0) (match_dup 3))]
713 "reload_completed"
ac445222 714{
3ec3c84f 715 operands[2] = pic_offset_table_rtx;
716 operands[3] = gen_const_mem (DImode, operands[0]);
d2ba5713 717})
ac445222 718
719(define_insn "*load_fptr_internal1"
720 [(set (match_operand:DI 0 "register_operand" "=r")
9fd73f31 721 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
3ec3c84f 722 "reload_completed"
ac445222 723 "addl %0 = @ltoff(@fptr(%1)), gp"
bf6ff2f6 724 [(set_attr "itanium_class" "ialu")])
ac445222 725
726(define_insn "load_gprel"
727 [(set (match_operand:DI 0 "register_operand" "=r")
9fd73f31 728 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
3ec3c84f 729 "reload_completed"
ac445222 730 "addl %0 = @gprel(%1), gp"
bf6ff2f6 731 [(set_attr "itanium_class" "ialu")])
ac445222 732
3ec3c84f 733(define_insn "*gprel64_offset"
cc40da95 734 [(set (match_operand:DI 0 "register_operand" "=r")
735 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
3ec3c84f 736 "reload_completed"
cc40da95 737 "movl %0 = @gprel(%1)"
bf6ff2f6 738 [(set_attr "itanium_class" "long_i")])
cc40da95 739
740(define_expand "load_gprel64"
3ec3c84f 741 [(set (match_operand:DI 0 "register_operand" "")
742 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
743 (set (match_dup 0)
744 (plus:DI (match_dup 2) (match_dup 0)))]
745 "reload_completed"
4174c5dc 746{
3ec3c84f 747 operands[2] = pic_offset_table_rtx;
d2ba5713 748})
cc40da95 749
f6b73c1b 750;; This is used as a placeholder for the return address during early
751;; compilation. We won't know where we've placed this until during
752;; reload, at which point it can wind up in b0, a general register,
753;; or memory. The only safe destination under these conditions is a
754;; general register.
755
756(define_insn_and_split "*movdi_ret_addr"
757 [(set (match_operand:DI 0 "register_operand" "=r")
758 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
759 ""
760 "#"
761 "reload_completed"
762 [(const_int 0)]
763{
764 ia64_split_return_addr_rtx (operands[0]);
765 DONE;
766}
767 [(set_attr "itanium_class" "ialu")])
768
0cc4b4a2 769(define_insn "*load_symptr_high"
ac445222 770 [(set (match_operand:DI 0 "register_operand" "=r")
0cc4b4a2 771 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
772 (match_operand:DI 2 "register_operand" "a")))]
3ec3c84f 773 "reload_completed"
0cc4b4a2 774{
775 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
776 return "%,addl %0 = @ltoffx(%1), %2";
777 else
778 return "%,addl %0 = @ltoff(%1), %2";
779}
bf6ff2f6 780 [(set_attr "itanium_class" "ialu")])
ac445222 781
0cc4b4a2 782(define_insn "*load_symptr_low"
783 [(set (match_operand:DI 0 "register_operand" "=r")
7ea22d30 784 (lo_sum:DI (mem:DI (match_operand:DI 1 "register_operand" "r"))
0cc4b4a2 785 (match_operand 2 "got_symbolic_operand" "s")))]
3ec3c84f 786 "reload_completed"
0cc4b4a2 787{
788 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
789 return "%,ld8.mov %0 = [%1], %2";
790 else
791 return "%,ld8 %0 = [%1]";
792}
793 [(set_attr "itanium_class" "ld")])
794
3ec3c84f 795(define_insn_and_split "load_dtpmod"
c87e09ad 796 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 797 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
3ec3c84f 798 UNSPEC_DTPMOD))]
c87e09ad 799 ""
3ec3c84f 800 "#"
801 "reload_completed"
802 [(set (match_dup 0)
803 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
804 (match_dup 2)))
805 (set (match_dup 0) (match_dup 3))]
806{
807 operands[2] = pic_offset_table_rtx;
808 operands[3] = gen_const_mem (DImode, operands[0]);
809})
c87e09ad 810
3ec3c84f 811(define_insn "*load_ltoff_dtpmod"
c87e09ad 812 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 813 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
3ec3c84f 814 UNSPEC_LTOFF_DTPMOD)
815 (match_operand:DI 2 "register_operand" "a")))]
816 "reload_completed"
817 "addl %0 = @ltoff(@dtpmod(%1)), %2"
c87e09ad 818 [(set_attr "itanium_class" "ialu")])
819
820(define_expand "load_dtprel"
821 [(set (match_operand:DI 0 "register_operand" "")
5bc9de32 822 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
c87e09ad 823 UNSPEC_DTPREL))]
824 ""
825 "")
826
827(define_insn "*load_dtprel64"
828 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 829 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
c87e09ad 830 UNSPEC_DTPREL))]
831 "TARGET_TLS64"
832 "movl %0 = @dtprel(%1)"
833 [(set_attr "itanium_class" "long_i")])
834
835(define_insn "*load_dtprel22"
836 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 837 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
c87e09ad 838 UNSPEC_DTPREL))]
839 ""
840 "addl %0 = @dtprel(%1), r0"
841 [(set_attr "itanium_class" "ialu")])
842
3ec3c84f 843(define_insn_and_split "*load_dtprel_gd"
844 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 845 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
3ec3c84f 846 UNSPEC_DTPREL))]
847 ""
848 "#"
849 "reload_completed"
850 [(set (match_dup 0)
851 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
852 (match_dup 2)))
853 (set (match_dup 0) (match_dup 3))]
854{
855 operands[2] = pic_offset_table_rtx;
856 operands[3] = gen_const_mem (DImode, operands[0]);
857})
858
859(define_insn "*load_ltoff_dtprel"
860 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 861 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
3ec3c84f 862 UNSPEC_LTOFF_DTPREL)
863 (match_operand:DI 2 "register_operand" "a")))]
864 ""
865 "addl %0 = @ltoff(@dtprel(%1)), %2"
866 [(set_attr "itanium_class" "ialu")])
867
c87e09ad 868(define_expand "add_dtprel"
869 [(set (match_operand:DI 0 "register_operand" "")
5bc9de32 870 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
3ec3c84f 871 UNSPEC_DTPREL)
872 (match_operand:DI 2 "register_operand" "")))]
c87e09ad 873 "!TARGET_TLS64"
874 "")
875
876(define_insn "*add_dtprel14"
877 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 878 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
3ec3c84f 879 UNSPEC_DTPREL)
880 (match_operand:DI 2 "register_operand" "r")))]
c87e09ad 881 "TARGET_TLS14"
3ec3c84f 882 "adds %0 = @dtprel(%1), %2"
c87e09ad 883 [(set_attr "itanium_class" "ialu")])
884
885(define_insn "*add_dtprel22"
886 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 887 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
3ec3c84f 888 UNSPEC_DTPREL)
889 (match_operand:DI 2 "register_operand" "a")))]
c87e09ad 890 "TARGET_TLS22"
3ec3c84f 891 "addl %0 = @dtprel(%1), %2"
c87e09ad 892 [(set_attr "itanium_class" "ialu")])
893
894(define_expand "load_tprel"
895 [(set (match_operand:DI 0 "register_operand" "")
5bc9de32 896 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
c87e09ad 897 UNSPEC_TPREL))]
898 ""
899 "")
900
901(define_insn "*load_tprel64"
902 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 903 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
c87e09ad 904 UNSPEC_TPREL))]
905 "TARGET_TLS64"
906 "movl %0 = @tprel(%1)"
907 [(set_attr "itanium_class" "long_i")])
908
909(define_insn "*load_tprel22"
910 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 911 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
c87e09ad 912 UNSPEC_TPREL))]
913 ""
914 "addl %0 = @tprel(%1), r0"
915 [(set_attr "itanium_class" "ialu")])
916
3ec3c84f 917(define_insn_and_split "*load_tprel_ie"
918 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 919 (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
3ec3c84f 920 UNSPEC_TPREL))]
921 ""
922 "#"
923 "reload_completed"
924 [(set (match_dup 0)
925 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
926 (match_dup 2)))
927 (set (match_dup 0) (match_dup 3))]
928{
929 operands[2] = pic_offset_table_rtx;
930 operands[3] = gen_const_mem (DImode, operands[0]);
931})
932
933(define_insn "*load_ltoff_tprel"
934 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 935 (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
3ec3c84f 936 UNSPEC_LTOFF_TPREL)
937 (match_operand:DI 2 "register_operand" "a")))]
938 ""
939 "addl %0 = @ltoff(@tprel(%1)), %2"
940 [(set_attr "itanium_class" "ialu")])
941
c87e09ad 942(define_expand "add_tprel"
943 [(set (match_operand:DI 0 "register_operand" "")
5bc9de32 944 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
3ec3c84f 945 UNSPEC_TPREL)
946 (match_operand:DI 2 "register_operand" "")))]
c87e09ad 947 "!TARGET_TLS64"
948 "")
949
950(define_insn "*add_tprel14"
951 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 952 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
3ec3c84f 953 UNSPEC_TPREL)
954 (match_operand:DI 2 "register_operand" "r")))]
c87e09ad 955 "TARGET_TLS14"
3ec3c84f 956 "adds %0 = @tprel(%1), %2"
c87e09ad 957 [(set_attr "itanium_class" "ialu")])
958
959(define_insn "*add_tprel22"
960 [(set (match_operand:DI 0 "register_operand" "=r")
5bc9de32 961 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
3ec3c84f 962 UNSPEC_TPREL)
963 (match_operand:DI 2 "register_operand" "a")))]
c87e09ad 964 "TARGET_TLS22"
3ec3c84f 965 "addl %0 = @tprel(%1), %2"
c87e09ad 966 [(set_attr "itanium_class" "ialu")])
967
d5f10acf 968;; With no offsettable memory references, we've got to have a scratch
2cb948c5 969;; around to play with the second word. However, in order to avoid a
970;; reload nightmare we lie, claim we don't need one, and fix it up
971;; in ia64_split_tmode_move.
d5f10acf 972(define_expand "movti"
2cb948c5 973 [(set (match_operand:TI 0 "general_operand" "")
974 (match_operand:TI 1 "general_operand" ""))]
d5f10acf 975 ""
d5f10acf 976{
c87e09ad 977 rtx op1 = ia64_expand_move (operands[0], operands[1]);
978 if (!op1)
979 DONE;
980 operands[1] = op1;
d2ba5713 981})
d5f10acf 982
cf7898a6 983(define_insn_and_split "movti_internal"
0d442ac4 984 [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
985 (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
d5f10acf 986 "ia64_move_ok (operands[0], operands[1])"
4d053aca 987 "@
988 #
989 #
990 ldfp8 %X0 = %1%P1
991 #
992 #"
993 "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
d5f10acf 994 [(const_int 0)]
d5f10acf 995{
223b25f9 996 ia64_split_tmode_move (operands);
d5f10acf 997 DONE;
d2ba5713 998}
cf7898a6 999 [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
1000 (set_attr "speculable1" "yes")
1001 (set_attr "speculable2" "no, no, yes, no, no")])
e84fc051 1002
ac445222 1003;; Floating Point Moves
1004;;
1005;; Note - Patterns for SF mode moves are compulsory, but
a2f10574 1006;; patterns for DF are optional, as GCC can synthesize them.
ac445222 1007
1008(define_expand "movsf"
1009 [(set (match_operand:SF 0 "general_operand" "")
1010 (match_operand:SF 1 "general_operand" ""))]
1011 ""
ac445222 1012{
c87e09ad 1013 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1014 if (!op1)
1015 DONE;
1016 operands[1] = op1;
d2ba5713 1017})
ac445222 1018
cf7898a6 1019(define_insn "movsf_internal"
e41d35a8 1020 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
1021 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
8b0dd03f 1022 "ia64_move_ok (operands[0], operands[1])"
ac445222 1023 "@
d2ba5713 1024 mov %0 = %F1
1025 ldfs %0 = %1%P1
1026 stfs %0 = %F1%P0
1027 getf.s %0 = %F1
1028 setf.s %0 = %1
1029 mov %0 = %1
1030 ld4%O1 %0 = %1%P1
e41d35a8 1031 st4%Q0 %0 = %1%P0
1032 movl %0 = %G1"
1033 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
cf7898a6 1034 (set_attr "speculable1" "yes")
e41d35a8 1035 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
ac445222 1036
1037(define_expand "movdf"
1038 [(set (match_operand:DF 0 "general_operand" "")
1039 (match_operand:DF 1 "general_operand" ""))]
1040 ""
ac445222 1041{
c87e09ad 1042 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1043 if (!op1)
1044 DONE;
1045 operands[1] = op1;
d2ba5713 1046})
ac445222 1047
cf7898a6 1048(define_insn "movdf_internal"
e41d35a8 1049 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
1050 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
8b0dd03f 1051 "ia64_move_ok (operands[0], operands[1])"
ac445222 1052 "@
d2ba5713 1053 mov %0 = %F1
1054 ldfd %0 = %1%P1
1055 stfd %0 = %F1%P0
1056 getf.d %0 = %F1
1057 setf.d %0 = %1
1058 mov %0 = %1
1059 ld8%O1 %0 = %1%P1
e41d35a8 1060 st8%Q0 %0 = %1%P0
1061 movl %0 = %G1"
1062 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
cf7898a6 1063 (set_attr "speculable1" "yes")
e41d35a8 1064 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
ac445222 1065
d5f10acf 1066;; With no offsettable memory references, we've got to have a scratch
1067;; around to play with the second word if the variable winds up in GRs.
b8bc42e9 1068(define_expand "movxf"
1069 [(set (match_operand:XF 0 "general_operand" "")
1070 (match_operand:XF 1 "general_operand" ""))]
1071 ""
945c34bb 1072{
7a979707 1073 if (ia64_expand_movxf_movrf (XFmode, operands))
1074 DONE;
d2ba5713 1075})
945c34bb 1076
9b06caff 1077;; ??? There's no easy way to mind volatile acquire/release semantics.
479da38b 1078
cf7898a6 1079(define_insn "movxf_internal"
cc14bb75 1080 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
1081 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
b8bc42e9 1082 "ia64_move_ok (operands[0], operands[1])"
945c34bb 1083 "@
d2ba5713 1084 mov %0 = %F1
1085 ldfe %0 = %1%P1
1086 stfe %0 = %F1%P0"
cf7898a6 1087 [(set_attr "itanium_class" "fmisc,fld,stf")
1088 (set_attr "speculable1" "yes")
1089 (set_attr "speculable2" "no, yes,no")])
223b25f9 1090
7a979707 1091;; Same as for movxf, but for RFmode.
1092(define_expand "movrf"
1093 [(set (match_operand:RF 0 "general_operand" "")
1094 (match_operand:RF 1 "general_operand" ""))]
1095 ""
1096{
1097 if (ia64_expand_movxf_movrf (RFmode, operands))
1098 DONE;
1099})
1100
1101(define_insn "*movrf_internal"
1102 [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
1103 (match_operand:RF 1 "general_operand" "fG,m,fG"))]
1104 "ia64_move_ok (operands[0], operands[1])"
1105 "@
1106 mov %0 = %F1
1107 ldf.fill %0 = %1%P1
1108 stf.spill %0 = %F1%P0"
1109 [(set_attr "itanium_class" "fmisc,fld,stf")])
1110
223b25f9 1111;; Better code generation via insns that deal with TFmode register pairs
2cb948c5 1112;; directly. Same concerns apply as for TImode.
223b25f9 1113(define_expand "movtf"
2cb948c5 1114 [(set (match_operand:TF 0 "general_operand" "")
1115 (match_operand:TF 1 "general_operand" ""))]
223b25f9 1116 ""
1117{
1118 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1119 if (!op1)
1120 DONE;
1121 operands[1] = op1;
1122})
1123
1124(define_insn_and_split "*movtf_internal"
2bb8b67b 1125 [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
2cb948c5 1126 (match_operand:TF 1 "general_operand" "ri,m,r"))]
223b25f9 1127 "ia64_move_ok (operands[0], operands[1])"
1128 "#"
1129 "reload_completed"
1130 [(const_int 0)]
1131{
1132 ia64_split_tmode_move (operands);
1133 DONE;
1134}
1135 [(set_attr "itanium_class" "unknown")
1136 (set_attr "predicable" "no")])
1137
ac445222 1138\f
1139;; ::::::::::::::::::::
1140;; ::
1141;; :: Conversions
1142;; ::
1143;; ::::::::::::::::::::
1144
1145;; Signed conversions from a smaller integer to a larger integer
1146
1147(define_insn "extendqidi2"
f087d65d 1148 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1149 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
ac445222 1150 ""
1151 "sxt1 %0 = %1"
bf6ff2f6 1152 [(set_attr "itanium_class" "xtd")])
ac445222 1153
1154(define_insn "extendhidi2"
f087d65d 1155 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1156 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
ac445222 1157 ""
1158 "sxt2 %0 = %1"
bf6ff2f6 1159 [(set_attr "itanium_class" "xtd")])
ac445222 1160
1161(define_insn "extendsidi2"
1beeaf61 1162 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1163 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
ac445222 1164 ""
1165 "@
1166 sxt4 %0 = %1
8b0dd03f 1167 fsxt.r %0 = %1, %1"
bf6ff2f6 1168 [(set_attr "itanium_class" "xtd,fmisc")])
ac445222 1169
1170;; Unsigned conversions from a smaller integer to a larger integer
1171
1172(define_insn "zero_extendqidi2"
f087d65d 1173 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1174 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
ac445222 1175 ""
1176 "@
1177 zxt1 %0 = %1
1178 ld1%O1 %0 = %1%P1"
cf7898a6 1179 [(set_attr "itanium_class" "xtd,ld")
1180 (set_attr "speculable1" "yes")
1181 (set_attr "speculable2" "no, yes")])
ac445222 1182
1183(define_insn "zero_extendhidi2"
f087d65d 1184 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1185 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
ac445222 1186 ""
1187 "@
1188 zxt2 %0 = %1
1189 ld2%O1 %0 = %1%P1"
cf7898a6 1190 [(set_attr "itanium_class" "xtd,ld")
1191 (set_attr "speculable1" "yes")
1192 (set_attr "speculable2" "no, yes")])
ac445222 1193
1194(define_insn "zero_extendsidi2"
1beeaf61 1195 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
f087d65d 1196 (zero_extend:DI
1beeaf61 1197 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
ac445222 1198 ""
1199 "@
fd2a554e 1200 addp4 %0 = %1, r0
ac445222 1201 ld4%O1 %0 = %1%P1
8b0dd03f 1202 fmix.r %0 = f0, %1"
cf7898a6 1203 [(set_attr "itanium_class" "ialu,ld,fmisc")
1204 (set_attr "speculable1" "yes")
1205 (set_attr "speculable2" "no, yes,no")])
ac445222 1206
1207;; Convert between floating point types of different sizes.
1208
16d3db92 1209;; At first glance, it would appear that emitting fnorm for an extending
1210;; conversion is unnecessary. However, the stf and getf instructions work
1211;; correctly only if the input is properly rounded for its type. In
1212;; particular, we get the wrong result for getf.d/stfd if the input is a
1213;; denorm single. Since we don't know what the next instruction will be, we
1214;; have to emit an fnorm.
1215
7653bea8 1216;; ??? Optimization opportunity here. Get rid of the insn altogether
1217;; when we can. Should probably use a scheme like has been proposed
1218;; for ia32 in dealing with operands that match unary operators. This
16d3db92 1219;; would let combine merge the thing into adjacent insns. See also how the
1220;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
1221;; se_register_operand.
ac445222 1222
16d3db92 1223(define_insn "extendsfdf2"
1224 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 1225 (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1226 ""
d363dedc 1227 "fnorm.d %0 = %F1"
16d3db92 1228 [(set_attr "itanium_class" "fmac")])
ac445222 1229
b8bc42e9 1230(define_insn "extendsfxf2"
1231 [(set (match_operand:XF 0 "fr_register_operand" "=f")
d363dedc 1232 (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1233 ""
d363dedc 1234 "fnorm %0 = %F1"
16d3db92 1235 [(set_attr "itanium_class" "fmac")])
d5f10acf 1236
b8bc42e9 1237(define_insn "extenddfxf2"
1238 [(set (match_operand:XF 0 "fr_register_operand" "=f")
d363dedc 1239 (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1240 ""
d363dedc 1241 "fnorm %0 = %F1"
16d3db92 1242 [(set_attr "itanium_class" "fmac")])
d5f10acf 1243
ac445222 1244(define_insn "truncdfsf2"
f087d65d 1245 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 1246 (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1247 ""
d363dedc 1248 "fnorm.s %0 = %F1"
bf6ff2f6 1249 [(set_attr "itanium_class" "fmac")])
ac445222 1250
b8bc42e9 1251(define_insn "truncxfsf2"
f087d65d 1252 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 1253 (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1254 ""
d363dedc 1255 "fnorm.s %0 = %F1"
bf6ff2f6 1256 [(set_attr "itanium_class" "fmac")])
ac445222 1257
b8bc42e9 1258(define_insn "truncxfdf2"
f087d65d 1259 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 1260 (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1261 ""
d363dedc 1262 "fnorm.d %0 = %F1"
bf6ff2f6 1263 [(set_attr "itanium_class" "fmac")])
945c34bb 1264
1265;; Convert between signed integer types and floating point.
1266
a58127d5 1267(define_insn "floatdirf2"
1268 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1269 (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1270 ""
1271 "fcvt.xf %0 = %F1"
1272 [(set_attr "itanium_class" "fcvtfx")])
1273
b8bc42e9 1274(define_insn "floatdixf2"
1275 [(set (match_operand:XF 0 "fr_register_operand" "=f")
d363dedc 1276 (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1277 ""
d363dedc 1278 "fcvt.xf %0 = %F1"
bf6ff2f6 1279 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1280
1281(define_insn "fix_truncsfdi2"
f087d65d 1282 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1283 (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1284 ""
d363dedc 1285 "fcvt.fx.trunc %0 = %F1"
bf6ff2f6 1286 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1287
1288(define_insn "fix_truncdfdi2"
f087d65d 1289 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1290 (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1291 ""
d363dedc 1292 "fcvt.fx.trunc %0 = %F1"
bf6ff2f6 1293 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1294
b8bc42e9 1295(define_insn "fix_truncxfdi2"
f087d65d 1296 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1297 (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1298 ""
d363dedc 1299 "fcvt.fx.trunc %0 = %F1"
bf6ff2f6 1300 [(set_attr "itanium_class" "fcvtfx")])
d5f10acf 1301
a58127d5 1302(define_insn "fix_truncrfdi2"
1beeaf61 1303 [(set (match_operand:DI 0 "fr_register_operand" "=f")
a58127d5 1304 (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1305 ""
a58127d5 1306 "fcvt.fx.trunc %0 = %F1"
bf6ff2f6 1307 [(set_attr "itanium_class" "fcvtfx")])
1beeaf61 1308
ac445222 1309;; Convert between unsigned integer types and floating point.
1310
1311(define_insn "floatunsdisf2"
f087d65d 1312 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 1313 (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1314 ""
d363dedc 1315 "fcvt.xuf.s %0 = %F1"
bf6ff2f6 1316 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1317
1318(define_insn "floatunsdidf2"
f087d65d 1319 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 1320 (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1321 ""
d363dedc 1322 "fcvt.xuf.d %0 = %F1"
bf6ff2f6 1323 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1324
b8bc42e9 1325(define_insn "floatunsdixf2"
1326 [(set (match_operand:XF 0 "fr_register_operand" "=f")
d363dedc 1327 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1328 ""
d363dedc 1329 "fcvt.xuf %0 = %F1"
bf6ff2f6 1330 [(set_attr "itanium_class" "fcvtfx")])
d5f10acf 1331
a58127d5 1332(define_insn "floatunsdirf2"
1333 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1334 (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1335 ""
1336 "fcvt.xuf %0 = %F1"
1337 [(set_attr "itanium_class" "fcvtfx")])
1338
ac445222 1339(define_insn "fixuns_truncsfdi2"
f087d65d 1340 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1341 (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1342 ""
d363dedc 1343 "fcvt.fxu.trunc %0 = %F1"
bf6ff2f6 1344 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1345
1346(define_insn "fixuns_truncdfdi2"
f087d65d 1347 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1348 (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 1349 ""
d363dedc 1350 "fcvt.fxu.trunc %0 = %F1"
bf6ff2f6 1351 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1352
b8bc42e9 1353(define_insn "fixuns_truncxfdi2"
f087d65d 1354 [(set (match_operand:DI 0 "fr_register_operand" "=f")
d363dedc 1355 (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1356 ""
d363dedc 1357 "fcvt.fxu.trunc %0 = %F1"
bf6ff2f6 1358 [(set_attr "itanium_class" "fcvtfx")])
1beeaf61 1359
a58127d5 1360(define_insn "fixuns_truncrfdi2"
1beeaf61 1361 [(set (match_operand:DI 0 "fr_register_operand" "=f")
a58127d5 1362 (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
b8bc42e9 1363 ""
a58127d5 1364 "fcvt.fxu.trunc %0 = %F1"
bf6ff2f6 1365 [(set_attr "itanium_class" "fcvtfx")])
ac445222 1366\f
1367;; ::::::::::::::::::::
1368;; ::
1369;; :: Bit field extraction
1370;; ::
1371;; ::::::::::::::::::::
1372
ac445222 1373(define_insn "extv"
f087d65d 1374 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1375 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
986fafd5 1376 (match_operand:DI 2 "extr_len_operand" "n")
1377 (match_operand:DI 3 "shift_count_operand" "M")))]
ac445222 1378 ""
1379 "extr %0 = %1, %3, %2"
bf6ff2f6 1380 [(set_attr "itanium_class" "ishf")])
ac445222 1381
1382(define_insn "extzv"
f087d65d 1383 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1384 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
986fafd5 1385 (match_operand:DI 2 "extr_len_operand" "n")
1386 (match_operand:DI 3 "shift_count_operand" "M")))]
ac445222 1387 ""
1388 "extr.u %0 = %1, %3, %2"
bf6ff2f6 1389 [(set_attr "itanium_class" "ishf")])
ac445222 1390
1391;; Insert a bit field.
1392;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1393;; Source1 can be 0 or -1.
1394;; Source2 can be 0.
1395
1396;; ??? Actual dep instruction is more powerful than what these insv
1397;; patterns support. Unfortunately, combine is unable to create patterns
1398;; where source2 != dest.
1399
1400(define_expand "insv"
f087d65d 1401 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
ac445222 1402 (match_operand:DI 1 "const_int_operand" "")
1403 (match_operand:DI 2 "const_int_operand" ""))
1404 (match_operand:DI 3 "nonmemory_operand" ""))]
1405 ""
ac445222 1406{
1407 int width = INTVAL (operands[1]);
1408 int shift = INTVAL (operands[2]);
1409
1410 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1411 pseudo. */
1412 if (! register_operand (operands[3], DImode)
1413 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1414 operands[3] = force_reg (DImode, operands[3]);
1415
1416 /* If this is a single dep instruction, we have nothing to do. */
1417 if (! ((register_operand (operands[3], DImode) && width <= 16)
1418 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1419 {
1420 /* Check for cases that can be implemented with a mix instruction. */
1421 if (width == 32 && shift == 0)
1422 {
1423 /* Directly generating the mix4left instruction confuses
1424 optimize_bit_field in function.c. Since this is performing
1425 a useful optimization, we defer generation of the complicated
1426 mix4left RTL to the first splitting phase. */
1427 rtx tmp = gen_reg_rtx (DImode);
1428 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1429 DONE;
1430 }
1431 else if (width == 32 && shift == 32)
1432 {
1433 emit_insn (gen_mix4right (operands[0], operands[3]));
1434 DONE;
1435 }
1436
74e01dd8 1437 /* We could handle remaining cases by emitting multiple dep
1438 instructions.
1439
1440 If we need more than two dep instructions then we lose. A 6
1441 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1442 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1443 the latter is 6 cycles on an Itanium (TM) processor, because there is
1444 only one function unit that can execute dep and shr immed.
1445
1446 If we only need two dep instruction, then we still lose.
1447 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1448 the unnecessary mov, this is still undesirable because it will be
1449 hard to optimize, and it creates unnecessary pressure on the I0
1450 function unit. */
1451
ac445222 1452 FAIL;
1453
1454#if 0
1455 /* This code may be useful for other IA-64 processors, so we leave it in
1456 for now. */
1457 while (width > 16)
1458 {
1459 rtx tmp;
1460
1461 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1462 operands[3]));
1463 shift += 16;
1464 width -= 16;
1465 tmp = gen_reg_rtx (DImode);
1466 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1467 operands[3] = tmp;
1468 }
1469 operands[1] = GEN_INT (width);
1470 operands[2] = GEN_INT (shift);
1471#endif
1472 }
d2ba5713 1473})
ac445222 1474
1475(define_insn "*insv_internal"
f087d65d 1476 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
ac445222 1477 (match_operand:DI 1 "const_int_operand" "n")
1478 (match_operand:DI 2 "const_int_operand" "n"))
1479 (match_operand:DI 3 "nonmemory_operand" "rP"))]
f087d65d 1480 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
ac445222 1481 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1482 "dep %0 = %3, %0, %2, %1"
bf6ff2f6 1483 [(set_attr "itanium_class" "ishf")])
ac445222 1484
ceb2fe0f 1485;; Combine doesn't like to create bit-field insertions into zero.
fd2a554e 1486(define_insn "*shladdp4_internal"
1487 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1488 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1489 (match_operand:DI 2 "shladd_log2_operand" "n"))
1490 (match_operand:DI 3 "const_int_operand" "n")))]
1491 "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
1492 "shladdp4 %0 = %1, %2, r0"
1493 [(set_attr "itanium_class" "ialu")])
1494
6709362a 1495(define_insn "*depz_internal"
f087d65d 1496 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1497 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
269f7060 1498 (match_operand:DI 2 "const_int_operand" "M"))
6709362a 1499 (match_operand:DI 3 "const_int_operand" "n")))]
269f7060 1500 "satisfies_constraint_M (operands[2])
6709362a 1501 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
6709362a 1502{
1503 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
d2ba5713 1504 return "%,dep.z %0 = %1, %2, %3";
1505}
bf6ff2f6 1506 [(set_attr "itanium_class" "ishf")])
6709362a 1507
ac445222 1508(define_insn "shift_mix4left"
f087d65d 1509 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
ac445222 1510 (const_int 32) (const_int 0))
f087d65d 1511 (match_operand:DI 1 "gr_register_operand" "r"))
1512 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
ac445222 1513 ""
1514 "#"
bf6ff2f6 1515 [(set_attr "itanium_class" "unknown")])
ac445222 1516
ac445222 1517(define_split
1518 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1519 (const_int 32) (const_int 0))
1520 (match_operand:DI 1 "register_operand" ""))
1521 (clobber (match_operand:DI 2 "register_operand" ""))]
8cad207a 1522 ""
ac445222 1523 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1524 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1525 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1526 "operands[3] = operands[2];")
1527
1528(define_insn "*mix4left"
f087d65d 1529 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
ac445222 1530 (const_int 32) (const_int 0))
f087d65d 1531 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 1532 (const_int 32)))]
1533 ""
1534 "mix4.l %0 = %0, %r1"
bf6ff2f6 1535 [(set_attr "itanium_class" "mmshf")])
ac445222 1536
1537(define_insn "mix4right"
f087d65d 1538 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
ac445222 1539 (const_int 32) (const_int 32))
f087d65d 1540 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
ac445222 1541 ""
1542 "mix4.r %0 = %r1, %0"
bf6ff2f6 1543 [(set_attr "itanium_class" "mmshf")])
ac445222 1544
1545;; This is used by the rotrsi3 pattern.
1546
1547(define_insn "*mix4right_3op"
f087d65d 1548 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1549 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1550 (ashift:DI (zero_extend:DI
1551 (match_operand:SI 2 "gr_register_operand" "r"))
ac445222 1552 (const_int 32))))]
1553 ""
e89d0443 1554 "mix4.r %0 = %2, %1"
bf6ff2f6 1555 [(set_attr "itanium_class" "mmshf")])
ac445222 1556
1557\f
1558;; ::::::::::::::::::::
a89cc05e 1559;; ::
3cc94518 1560;; :: 1-bit Integer arithmetic
33c8f6d1 1561;; ::
1562;; ::::::::::::::::::::
1563
1564(define_insn_and_split "andbi3"
1565 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1566 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1567 (match_operand:BI 2 "register_operand" "c,r,r")))]
1568 ""
1569 "@
1570 #
1571 tbit.nz.and.orcm %0, %I0 = %2, 0
1572 and %0 = %2, %1"
1573 "reload_completed
1574 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1575 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1576 [(cond_exec (eq (match_dup 2) (const_int 0))
1577 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1578 (match_dup 0))))]
1579 ""
bf6ff2f6 1580 [(set_attr "itanium_class" "unknown,tbit,ilog")])
33c8f6d1 1581
1582(define_insn_and_split "*andcmbi3"
1583 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1584 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1585 (match_operand:BI 2 "register_operand" "0,0,r")))]
1586 ""
1587 "@
1588 #
abb07d71 1589 tbit.z.and.orcm %0, %I0 = %1, 0
33c8f6d1 1590 andcm %0 = %2, %1"
1591 "reload_completed
1592 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
abb07d71 1593 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
33c8f6d1 1594 [(cond_exec (ne (match_dup 1) (const_int 0))
1595 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1596 (match_dup 0))))]
1597 ""
bf6ff2f6 1598 [(set_attr "itanium_class" "unknown,tbit,ilog")])
33c8f6d1 1599
1600(define_insn_and_split "iorbi3"
1601 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1602 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1603 (match_operand:BI 2 "register_operand" "c,r,r")))]
1604 ""
1605 "@
1606 #
1607 tbit.nz.or.andcm %0, %I0 = %2, 0
1608 or %0 = %2, %1"
1609 "reload_completed
1610 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1611 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1612 [(cond_exec (ne (match_dup 2) (const_int 0))
1613 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1614 (match_dup 0))))]
1615 ""
bf6ff2f6 1616 [(set_attr "itanium_class" "unknown,tbit,ilog")])
33c8f6d1 1617
1618(define_insn_and_split "*iorcmbi3"
1619 [(set (match_operand:BI 0 "register_operand" "=c,c")
1620 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1621 (match_operand:BI 2 "register_operand" "0,0")))]
1622 ""
1623 "@
1624 #
abb07d71 1625 tbit.z.or.andcm %0, %I0 = %1, 0"
33c8f6d1 1626 "reload_completed
1627 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
abb07d71 1628 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
33c8f6d1 1629 [(cond_exec (eq (match_dup 1) (const_int 0))
1630 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1631 (match_dup 0))))]
1632 ""
bf6ff2f6 1633 [(set_attr "itanium_class" "unknown,tbit")])
33c8f6d1 1634
1635(define_insn "one_cmplbi2"
1636 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1637 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1638 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1639 ""
1640 "@
1641 tbit.z %0, %I0 = %1, 0
1642 xor %0 = 1, %1
1643 #
1644 #"
bf6ff2f6 1645 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
33c8f6d1 1646
1647(define_split
1648 [(set (match_operand:BI 0 "register_operand" "")
1649 (not:BI (match_operand:BI 1 "register_operand" "")))
1650 (clobber (match_scratch:BI 2 ""))]
1651 "reload_completed
1652 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
33c8f6d1 1653 && rtx_equal_p (operands[0], operands[1])"
1654 [(set (match_dup 4) (match_dup 3))
1655 (set (match_dup 0) (const_int 1))
1656 (cond_exec (ne (match_dup 2) (const_int 0))
1657 (set (match_dup 0) (const_int 0)))
e2b723ca 1658 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
33c8f6d1 1659 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1660 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1661
1662(define_split
1663 [(set (match_operand:BI 0 "register_operand" "")
1664 (not:BI (match_operand:BI 1 "register_operand" "")))
1665 (clobber (match_scratch:BI 2 ""))]
1666 "reload_completed
1667 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1668 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1669 && ! rtx_equal_p (operands[0], operands[1])"
1670 [(cond_exec (ne (match_dup 1) (const_int 0))
1671 (set (match_dup 0) (const_int 0)))
1672 (cond_exec (eq (match_dup 1) (const_int 0))
1673 (set (match_dup 0) (const_int 1)))
e2b723ca 1674 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
33c8f6d1 1675 "")
1676
1677(define_insn "*cmpsi_and_0"
1678 [(set (match_operand:BI 0 "register_operand" "=c")
1679 (and:BI (match_operator:BI 4 "predicate_operator"
1680 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1681 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1682 (match_operand:BI 1 "register_operand" "0")))]
1683 ""
1684 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
bf6ff2f6 1685 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1686
1687(define_insn "*cmpsi_and_1"
1688 [(set (match_operand:BI 0 "register_operand" "=c")
1689 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1690 [(match_operand:SI 2 "gr_register_operand" "r")
1691 (const_int 0)])
1692 (match_operand:BI 1 "register_operand" "0")))]
1693 ""
1694 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
bf6ff2f6 1695 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1696
1697(define_insn "*cmpsi_andnot_0"
1698 [(set (match_operand:BI 0 "register_operand" "=c")
1699 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1700 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1701 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1702 (match_operand:BI 1 "register_operand" "0")))]
1703 ""
1704 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
bf6ff2f6 1705 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1706
1707(define_insn "*cmpsi_andnot_1"
1708 [(set (match_operand:BI 0 "register_operand" "=c")
1709 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1710 [(match_operand:SI 2 "gr_register_operand" "r")
1711 (const_int 0)]))
1712 (match_operand:BI 1 "register_operand" "0")))]
1713 ""
1714 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
bf6ff2f6 1715 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1716
1717(define_insn "*cmpdi_and_0"
1718 [(set (match_operand:BI 0 "register_operand" "=c")
1719 (and:BI (match_operator:BI 4 "predicate_operator"
1720 [(match_operand:DI 2 "gr_register_operand" "r")
1721 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1722 (match_operand:BI 1 "register_operand" "0")))]
1723 ""
1724 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
bf6ff2f6 1725 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1726
1727(define_insn "*cmpdi_and_1"
1728 [(set (match_operand:BI 0 "register_operand" "=c")
1729 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1730 [(match_operand:DI 2 "gr_register_operand" "r")
1731 (const_int 0)])
1732 (match_operand:BI 1 "register_operand" "0")))]
1733 ""
1734 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
bf6ff2f6 1735 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1736
1737(define_insn "*cmpdi_andnot_0"
1738 [(set (match_operand:BI 0 "register_operand" "=c")
1739 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1740 [(match_operand:DI 2 "gr_register_operand" "r")
1741 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1742 (match_operand:BI 1 "register_operand" "0")))]
1743 ""
1744 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
bf6ff2f6 1745 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1746
1747(define_insn "*cmpdi_andnot_1"
1748 [(set (match_operand:BI 0 "register_operand" "=c")
1749 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1750 [(match_operand:DI 2 "gr_register_operand" "r")
1751 (const_int 0)]))
1752 (match_operand:BI 1 "register_operand" "0")))]
1753 ""
1754 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
bf6ff2f6 1755 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1756
1757(define_insn "*tbit_and_0"
1758 [(set (match_operand:BI 0 "register_operand" "=c")
1759 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1760 (const_int 1))
1761 (const_int 0))
dd193d7c 1762 (match_operand:BI 2 "register_operand" "0")))]
33c8f6d1 1763 ""
1764 "tbit.nz.and.orcm %0, %I0 = %1, 0"
bf6ff2f6 1765 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1766
1767(define_insn "*tbit_and_1"
1768 [(set (match_operand:BI 0 "register_operand" "=c")
1769 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1770 (const_int 1))
1771 (const_int 0))
dd193d7c 1772 (match_operand:BI 2 "register_operand" "0")))]
33c8f6d1 1773 ""
1774 "tbit.z.and.orcm %0, %I0 = %1, 0"
bf6ff2f6 1775 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1776
1777(define_insn "*tbit_and_2"
1778 [(set (match_operand:BI 0 "register_operand" "=c")
1779 (and:BI (ne:BI (zero_extract:DI
1780 (match_operand:DI 1 "gr_register_operand" "r")
1781 (const_int 1)
986fafd5 1782 (match_operand:DI 2 "shift_count_operand" "M"))
33c8f6d1 1783 (const_int 0))
1784 (match_operand:BI 3 "register_operand" "0")))]
1785 ""
1786 "tbit.nz.and.orcm %0, %I0 = %1, %2"
bf6ff2f6 1787 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1788
1789(define_insn "*tbit_and_3"
1790 [(set (match_operand:BI 0 "register_operand" "=c")
1791 (and:BI (eq:BI (zero_extract:DI
1792 (match_operand:DI 1 "gr_register_operand" "r")
1793 (const_int 1)
986fafd5 1794 (match_operand:DI 2 "shift_count_operand" "M"))
33c8f6d1 1795 (const_int 0))
1796 (match_operand:BI 3 "register_operand" "0")))]
1797 ""
1798 "tbit.z.and.orcm %0, %I0 = %1, %2"
bf6ff2f6 1799 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1800
1801(define_insn "*cmpsi_or_0"
1802 [(set (match_operand:BI 0 "register_operand" "=c")
1803 (ior:BI (match_operator:BI 4 "predicate_operator"
1804 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1805 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1806 (match_operand:BI 1 "register_operand" "0")))]
1807 ""
1808 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
bf6ff2f6 1809 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1810
1811(define_insn "*cmpsi_or_1"
1812 [(set (match_operand:BI 0 "register_operand" "=c")
1813 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1814 [(match_operand:SI 2 "gr_register_operand" "r")
1815 (const_int 0)])
1816 (match_operand:BI 1 "register_operand" "0")))]
1817 ""
1818 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
bf6ff2f6 1819 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1820
1821(define_insn "*cmpsi_orcm_0"
1822 [(set (match_operand:BI 0 "register_operand" "=c")
1823 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1824 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1825 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1826 (match_operand:BI 1 "register_operand" "0")))]
1827 ""
1828 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
bf6ff2f6 1829 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1830
1831(define_insn "*cmpsi_orcm_1"
1832 [(set (match_operand:BI 0 "register_operand" "=c")
1833 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1834 [(match_operand:SI 2 "gr_register_operand" "r")
1835 (const_int 0)]))
1836 (match_operand:BI 1 "register_operand" "0")))]
1837 ""
1838 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
bf6ff2f6 1839 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1840
1841(define_insn "*cmpdi_or_0"
1842 [(set (match_operand:BI 0 "register_operand" "=c")
1843 (ior:BI (match_operator:BI 4 "predicate_operator"
1844 [(match_operand:DI 2 "gr_register_operand" "r")
1845 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1846 (match_operand:BI 1 "register_operand" "0")))]
1847 ""
1848 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
bf6ff2f6 1849 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1850
1851(define_insn "*cmpdi_or_1"
1852 [(set (match_operand:BI 0 "register_operand" "=c")
1853 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1854 [(match_operand:DI 2 "gr_register_operand" "r")
1855 (const_int 0)])
1856 (match_operand:BI 1 "register_operand" "0")))]
1857 ""
1858 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
bf6ff2f6 1859 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1860
1861(define_insn "*cmpdi_orcm_0"
1862 [(set (match_operand:BI 0 "register_operand" "=c")
1863 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1864 [(match_operand:DI 2 "gr_register_operand" "r")
1865 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1866 (match_operand:BI 1 "register_operand" "0")))]
1867 ""
1868 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
bf6ff2f6 1869 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1870
1871(define_insn "*cmpdi_orcm_1"
1872 [(set (match_operand:BI 0 "register_operand" "=c")
1873 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1874 [(match_operand:DI 2 "gr_register_operand" "r")
1875 (const_int 0)]))
1876 (match_operand:BI 1 "register_operand" "0")))]
1877 ""
1878 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
bf6ff2f6 1879 [(set_attr "itanium_class" "icmp")])
33c8f6d1 1880
1881(define_insn "*tbit_or_0"
1882 [(set (match_operand:BI 0 "register_operand" "=c")
1883 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1884 (const_int 1))
1885 (const_int 0))
dd193d7c 1886 (match_operand:BI 2 "register_operand" "0")))]
33c8f6d1 1887 ""
1888 "tbit.nz.or.andcm %0, %I0 = %1, 0"
bf6ff2f6 1889 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1890
1891(define_insn "*tbit_or_1"
1892 [(set (match_operand:BI 0 "register_operand" "=c")
1893 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1894 (const_int 1))
1895 (const_int 0))
dd193d7c 1896 (match_operand:BI 2 "register_operand" "0")))]
33c8f6d1 1897 ""
1898 "tbit.z.or.andcm %0, %I0 = %1, 0"
bf6ff2f6 1899 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1900
1901(define_insn "*tbit_or_2"
1902 [(set (match_operand:BI 0 "register_operand" "=c")
1903 (ior:BI (ne:BI (zero_extract:DI
1904 (match_operand:DI 1 "gr_register_operand" "r")
1905 (const_int 1)
986fafd5 1906 (match_operand:DI 2 "shift_count_operand" "M"))
33c8f6d1 1907 (const_int 0))
1908 (match_operand:BI 3 "register_operand" "0")))]
1909 ""
1910 "tbit.nz.or.andcm %0, %I0 = %1, %2"
bf6ff2f6 1911 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1912
1913(define_insn "*tbit_or_3"
1914 [(set (match_operand:BI 0 "register_operand" "=c")
1915 (ior:BI (eq:BI (zero_extract:DI
1916 (match_operand:DI 1 "gr_register_operand" "r")
1917 (const_int 1)
986fafd5 1918 (match_operand:DI 2 "shift_count_operand" "M"))
33c8f6d1 1919 (const_int 0))
1920 (match_operand:BI 3 "register_operand" "0")))]
1921 ""
1922 "tbit.z.or.andcm %0, %I0 = %1, %2"
bf6ff2f6 1923 [(set_attr "itanium_class" "tbit")])
33c8f6d1 1924
1925;; Transform test of and/or of setcc into parallel comparisons.
1926
1927(define_split
1928 [(set (match_operand:BI 0 "register_operand" "")
1929 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1930 (const_int 0))
1931 (match_operand:DI 3 "register_operand" ""))
1932 (const_int 0)))]
1933 ""
1934 [(set (match_dup 0)
1935 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1936 (match_dup 2)))]
1937 "")
1938
1939(define_split
1940 [(set (match_operand:BI 0 "register_operand" "")
1941 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1942 (const_int 0))
1943 (match_operand:DI 3 "register_operand" ""))
1944 (const_int 0)))]
1945 ""
1946 [(set (match_dup 0)
1947 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1948 (match_dup 2)))
1949 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1950 (clobber (scratch))])]
1951 "")
1952
1953(define_split
1954 [(set (match_operand:BI 0 "register_operand" "")
1955 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1956 (const_int 0))
1957 (match_operand:DI 3 "register_operand" ""))
1958 (const_int 0)))]
1959 ""
1960 [(set (match_dup 0)
1961 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1962 (match_dup 2)))]
1963 "")
1964
1965(define_split
1966 [(set (match_operand:BI 0 "register_operand" "")
1967 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1968 (const_int 0))
1969 (match_operand:DI 3 "register_operand" ""))
1970 (const_int 0)))]
1971 ""
1972 [(set (match_dup 0)
1973 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1974 (match_dup 2)))
1975 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1976 (clobber (scratch))])]
1977 "")
1978
1979;; ??? Incredibly hackish. Either need four proper patterns with all
1980;; the alternatives, or rely on sched1 to split the insn and hope that
1981;; nothing bad happens to the comparisons in the meantime.
1982;;
1983;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1984;; that we're doing height reduction.
1985;
1986;(define_insn_and_split ""
1987; [(set (match_operand:BI 0 "register_operand" "=c")
1988; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1989; [(match_operand 2 "" "")
1990; (match_operand 3 "" "")])
1991; (match_operator:BI 4 "comparison_operator"
1992; [(match_operand 5 "" "")
1993; (match_operand 6 "" "")]))
1994; (match_dup 0)))]
1995; "flag_schedule_insns"
1996; "#"
1997; ""
1998; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1999; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
2000; "")
2001;
2002;(define_insn_and_split ""
2003; [(set (match_operand:BI 0 "register_operand" "=c")
2004; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2005; [(match_operand 2 "" "")
2006; (match_operand 3 "" "")])
2007; (match_operator:BI 4 "comparison_operator"
2008; [(match_operand 5 "" "")
2009; (match_operand 6 "" "")]))
2010; (match_dup 0)))]
2011; "flag_schedule_insns"
2012; "#"
2013; ""
2014; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
2015; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
2016; "")
2017;
2018;(define_split
2019; [(set (match_operand:BI 0 "register_operand" "")
2020; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
2021; [(match_operand 2 "" "")
2022; (match_operand 3 "" "")])
2023; (match_operand:BI 7 "register_operand" ""))
2024; (and:BI (match_operator:BI 4 "comparison_operator"
2025; [(match_operand 5 "" "")
2026; (match_operand 6 "" "")])
2027; (match_operand:BI 8 "register_operand" ""))))]
2028; ""
2029; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
2030; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
2031; (match_dup 0)))]
2032; "")
2033;
2034;(define_split
2035; [(set (match_operand:BI 0 "register_operand" "")
2036; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2037; [(match_operand 2 "" "")
2038; (match_operand 3 "" "")])
2039; (match_operand:BI 7 "register_operand" ""))
2040; (ior:BI (match_operator:BI 4 "comparison_operator"
2041; [(match_operand 5 "" "")
2042; (match_operand 6 "" "")])
2043; (match_operand:BI 8 "register_operand" ""))))]
2044; ""
2045; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
2046; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
2047; (match_dup 0)))]
2048; "")
2049
2050;; Try harder to avoid predicate copies by duplicating compares.
2051;; Note that we'll have already split the predicate copy, which
2052;; is kind of a pain, but oh well.
2053
2054(define_peephole2
2055 [(set (match_operand:BI 0 "register_operand" "")
2056 (match_operand:BI 1 "comparison_operator" ""))
2057 (set (match_operand:CCI 2 "register_operand" "")
2058 (match_operand:CCI 3 "register_operand" ""))
2059 (set (match_operand:CCI 4 "register_operand" "")
2060 (match_operand:CCI 5 "register_operand" ""))
2061 (set (match_operand:BI 6 "register_operand" "")
e2b723ca 2062 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
33c8f6d1 2063 "REGNO (operands[3]) == REGNO (operands[0])
2064 && REGNO (operands[4]) == REGNO (operands[0]) + 1
2065 && REGNO (operands[4]) == REGNO (operands[2]) + 1
2066 && REGNO (operands[6]) == REGNO (operands[2])"
2067 [(set (match_dup 0) (match_dup 1))
2068 (set (match_dup 6) (match_dup 7))]
2069 "operands[7] = copy_rtx (operands[1]);")
2070\f
2071;; ::::::::::::::::::::
2072;; ::
3cc94518 2073;; :: 16-bit Integer arithmetic
a89cc05e 2074;; ::
2075;; ::::::::::::::::::::
2076
2077(define_insn "mulhi3"
2078 [(set (match_operand:HI 0 "gr_register_operand" "=r")
2079 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
2080 (match_operand:HI 2 "gr_register_operand" "r")))]
2081 ""
113d69fe 2082 "pmpy2.r %0 = %1, %2"
bf6ff2f6 2083 [(set_attr "itanium_class" "mmmul")])
a89cc05e 2084
2085\f
2086;; ::::::::::::::::::::
ac445222 2087;; ::
3cc94518 2088;; :: 32-bit Integer arithmetic
ac445222 2089;; ::
2090;; ::::::::::::::::::::
2091
eab36ec2 2092(define_insn "addsi3"
f087d65d 2093 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
2094 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
2095 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
ac445222 2096 ""
2097 "@
d2ba5713 2098 add %0 = %1, %2
2099 adds %0 = %2, %1
2100 addl %0 = %2, %1"
bf6ff2f6 2101 [(set_attr "itanium_class" "ialu")])
ac445222 2102
2103(define_insn "*addsi3_plus1"
f087d65d 2104 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2105 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
2106 (match_operand:SI 2 "gr_register_operand" "r"))
ac445222 2107 (const_int 1)))]
2108 ""
2109 "add %0 = %1, %2, 1"
bf6ff2f6 2110 [(set_attr "itanium_class" "ialu")])
ac445222 2111
9641f63c 2112(define_insn "*addsi3_plus1_alt"
f087d65d 2113 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2114 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
9641f63c 2115 (const_int 2))
2116 (const_int 1)))]
2117 ""
2118 "add %0 = %1, %1, 1"
bf6ff2f6 2119 [(set_attr "itanium_class" "ialu")])
9641f63c 2120
eab36ec2 2121(define_insn "*addsi3_shladd"
f087d65d 2122 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2123 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
eab36ec2 2124 (match_operand:SI 2 "shladd_operand" "n"))
f087d65d 2125 (match_operand:SI 3 "gr_register_operand" "r")))]
ac445222 2126 ""
eab36ec2 2127 "shladd %0 = %1, %S2, %3"
bf6ff2f6 2128 [(set_attr "itanium_class" "ialu")])
ac445222 2129
eab36ec2 2130(define_insn "subsi3"
f087d65d 2131 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2132 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
2133 (match_operand:SI 2 "gr_register_operand" "r")))]
ac445222 2134 ""
2135 "sub %0 = %1, %2"
bf6ff2f6 2136 [(set_attr "itanium_class" "ialu")])
ac445222 2137
2138(define_insn "*subsi3_minus1"
f087d65d 2139 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2140 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
2141 (match_operand:SI 2 "gr_register_operand" "r")))]
ac445222 2142 ""
2143 "sub %0 = %2, %1, 1"
bf6ff2f6 2144 [(set_attr "itanium_class" "ialu")])
2145
2146;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
ac445222 2147
eab36ec2 2148(define_insn "mulsi3"
f087d65d 2149 [(set (match_operand:SI 0 "fr_register_operand" "=f")
1a832885 2150 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2151 (match_operand:SI 2 "grfr_register_operand" "f")))]
ac445222 2152 ""
8b0dd03f 2153 "xmpy.l %0 = %1, %2"
bf6ff2f6 2154 [(set_attr "itanium_class" "xmpy")])
ac445222 2155
1beeaf61 2156(define_insn "maddsi4"
1a832885 2157 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2158 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2159 (match_operand:SI 2 "grfr_register_operand" "f"))
2160 (match_operand:SI 3 "grfr_register_operand" "f")))]
2161 ""
8b0dd03f 2162 "xma.l %0 = %1, %2, %3"
bf6ff2f6 2163 [(set_attr "itanium_class" "xmpy")])
1a832885 2164
eab36ec2 2165(define_insn "negsi2"
f087d65d 2166 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2167 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
ac445222 2168 ""
2169 "sub %0 = r0, %1"
bf6ff2f6 2170 [(set_attr "itanium_class" "ialu")])
ac445222 2171
2172(define_expand "abssi2"
2173 [(set (match_dup 2)
33c8f6d1 2174 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
f087d65d 2175 (set (match_operand:SI 0 "gr_register_operand" "")
33c8f6d1 2176 (if_then_else:SI (eq (match_dup 2) (const_int 0))
945c34bb 2177 (neg:SI (match_dup 1))
2178 (match_dup 1)))]
ac445222 2179 ""
d2ba5713 2180 { operands[2] = gen_reg_rtx (BImode); })
ac445222 2181
2182(define_expand "sminsi3"
2183 [(set (match_dup 3)
33c8f6d1 2184 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
f087d65d 2185 (match_operand:SI 2 "gr_register_operand" "")))
2186 (set (match_operand:SI 0 "gr_register_operand" "")
33c8f6d1 2187 (if_then_else:SI (ne (match_dup 3) (const_int 0))
ac445222 2188 (match_dup 2) (match_dup 1)))]
2189 ""
d2ba5713 2190 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2191
2192(define_expand "smaxsi3"
2193 [(set (match_dup 3)
33c8f6d1 2194 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
f087d65d 2195 (match_operand:SI 2 "gr_register_operand" "")))
2196 (set (match_operand:SI 0 "gr_register_operand" "")
33c8f6d1 2197 (if_then_else:SI (ne (match_dup 3) (const_int 0))
ac445222 2198 (match_dup 1) (match_dup 2)))]
2199 ""
d2ba5713 2200 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2201
2202(define_expand "uminsi3"
2203 [(set (match_dup 3)
33c8f6d1 2204 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
f087d65d 2205 (match_operand:SI 2 "gr_register_operand" "")))
2206 (set (match_operand:SI 0 "gr_register_operand" "")
33c8f6d1 2207 (if_then_else:SI (ne (match_dup 3) (const_int 0))
ac445222 2208 (match_dup 2) (match_dup 1)))]
2209 ""
d2ba5713 2210 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2211
2212(define_expand "umaxsi3"
2213 [(set (match_dup 3)
33c8f6d1 2214 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
f087d65d 2215 (match_operand:SI 2 "gr_register_operand" "")))
2216 (set (match_operand:SI 0 "gr_register_operand" "")
33c8f6d1 2217 (if_then_else:SI (ne (match_dup 3) (const_int 0))
ac445222 2218 (match_dup 1) (match_dup 2)))]
2219 ""
d2ba5713 2220 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2221\f
2222;; ::::::::::::::::::::
2223;; ::
3cc94518 2224;; :: 64-bit Integer arithmetic
ac445222 2225;; ::
2226;; ::::::::::::::::::::
2227
2228(define_insn "adddi3"
f087d65d 2229 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2230 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2231 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
ac445222 2232 ""
2233 "@
d2ba5713 2234 add %0 = %1, %2
2235 adds %0 = %2, %1
2236 addl %0 = %2, %1"
bf6ff2f6 2237 [(set_attr "itanium_class" "ialu")])
ac445222 2238
2239(define_insn "*adddi3_plus1"
f087d65d 2240 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2241 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2242 (match_operand:DI 2 "gr_register_operand" "r"))
ac445222 2243 (const_int 1)))]
2244 ""
2245 "add %0 = %1, %2, 1"
bf6ff2f6 2246 [(set_attr "itanium_class" "ialu")])
ac445222 2247
9641f63c 2248;; This has some of the same problems as shladd. We let the shladd
2249;; eliminator hack handle it, which results in the 1 being forced into
2250;; a register, but not more ugliness here.
2251(define_insn "*adddi3_plus1_alt"
f087d65d 2252 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2253 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
9641f63c 2254 (const_int 2))
2255 (const_int 1)))]
2256 ""
2257 "add %0 = %1, %1, 1"
bf6ff2f6 2258 [(set_attr "itanium_class" "ialu")])
9641f63c 2259
ac445222 2260(define_insn "subdi3"
f087d65d 2261 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2262 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2263 (match_operand:DI 2 "gr_register_operand" "r")))]
ac445222 2264 ""
2265 "sub %0 = %1, %2"
bf6ff2f6 2266 [(set_attr "itanium_class" "ialu")])
ac445222 2267
2268(define_insn "*subdi3_minus1"
f087d65d 2269 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2270 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2271 (match_operand:DI 2 "gr_register_operand" "r")))]
ac445222 2272 ""
2273 "sub %0 = %2, %1, 1"
bf6ff2f6 2274 [(set_attr "itanium_class" "ialu")])
ac445222 2275
cd23ff93 2276;; ??? Use grfr instead of fr because of virtual register elimination
2277;; and silly test cases multiplying by the frame pointer.
ac445222 2278(define_insn "muldi3"
f087d65d 2279 [(set (match_operand:DI 0 "fr_register_operand" "=f")
cd23ff93 2280 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2281 (match_operand:DI 2 "grfr_register_operand" "f")))]
ac445222 2282 ""
8b0dd03f 2283 "xmpy.l %0 = %1, %2"
bf6ff2f6 2284 [(set_attr "itanium_class" "xmpy")])
ac445222 2285
2286;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2287;; same problem that we have with shladd below. Unfortunately, this case is
2288;; much harder to fix because the multiply puts the result in an FP register,
2289;; but the add needs inputs from a general register. We add a spurious clobber
2290;; here so that it will be present just in case register elimination gives us
2291;; the funny result.
2292
2293;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2294
2295;; ??? Maybe we should change how adds are canonicalized.
2296
1beeaf61 2297(define_insn "madddi4"
f087d65d 2298 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1a832885 2299 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2300 (match_operand:DI 2 "grfr_register_operand" "f"))
2301 (match_operand:DI 3 "grfr_register_operand" "f")))
ac445222 2302 (clobber (match_scratch:DI 4 "=X"))]
2303 ""
8b0dd03f 2304 "xma.l %0 = %1, %2, %3"
bf6ff2f6 2305 [(set_attr "itanium_class" "xmpy")])
ac445222 2306
2307;; This can be created by register elimination if operand3 of shladd is an
2308;; eliminable register or has reg_equiv_constant set.
2309
2310;; We have to use nonmemory_operand for operand 4, to ensure that the
2311;; validate_changes call inside eliminate_regs will always succeed. If it
1beeaf61 2312;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
ac445222 2313;; incorrectly.
2314
1beeaf61 2315(define_insn "*madddi4_elim"
ac445222 2316 [(set (match_operand:DI 0 "register_operand" "=&r")
08f8478f 2317 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2318 (match_operand:DI 2 "register_operand" "f"))
2319 (match_operand:DI 3 "register_operand" "f"))
ac445222 2320 (match_operand:DI 4 "nonmemory_operand" "rI")))
08f8478f 2321 (clobber (match_scratch:DI 5 "=f"))]
ac445222 2322 "reload_in_progress"
2323 "#"
bf6ff2f6 2324 [(set_attr "itanium_class" "unknown")])
ac445222 2325
ac445222 2326(define_split
2327 [(set (match_operand:DI 0 "register_operand" "")
2328 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2329 (match_operand:DI 2 "register_operand" ""))
2330 (match_operand:DI 3 "register_operand" ""))
f087d65d 2331 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
ac445222 2332 (clobber (match_scratch:DI 5 ""))]
2333 "reload_completed"
2334 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2335 (match_dup 3)))
2336 (clobber (match_dup 0))])
ac445222 2337 (set (match_dup 0) (match_dup 5))
ac445222 2338 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2339 "")
2340
ac445222 2341(define_insn "smuldi3_highpart"
f087d65d 2342 [(set (match_operand:DI 0 "fr_register_operand" "=f")
ac445222 2343 (truncate:DI
2344 (lshiftrt:TI
f087d65d 2345 (mult:TI (sign_extend:TI
d363dedc 2346 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
f087d65d 2347 (sign_extend:TI
d363dedc 2348 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
ac445222 2349 (const_int 64))))]
2350 ""
d363dedc 2351 "xmpy.h %0 = %F1, %F2"
bf6ff2f6 2352 [(set_attr "itanium_class" "xmpy")])
ac445222 2353
2354(define_insn "umuldi3_highpart"
f087d65d 2355 [(set (match_operand:DI 0 "fr_register_operand" "=f")
ac445222 2356 (truncate:DI
2357 (lshiftrt:TI
f087d65d 2358 (mult:TI (zero_extend:TI
d363dedc 2359 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
f087d65d 2360 (zero_extend:TI
d363dedc 2361 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
ac445222 2362 (const_int 64))))]
2363 ""
d363dedc 2364 "xmpy.hu %0 = %F1, %F2"
bf6ff2f6 2365 [(set_attr "itanium_class" "xmpy")])
ac445222 2366
2367(define_insn "negdi2"
f087d65d 2368 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2369 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
ac445222 2370 ""
2371 "sub %0 = r0, %1"
bf6ff2f6 2372 [(set_attr "itanium_class" "ialu")])
ac445222 2373
2374(define_expand "absdi2"
2375 [(set (match_dup 2)
33c8f6d1 2376 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
f087d65d 2377 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2378 (if_then_else:DI (eq (match_dup 2) (const_int 0))
945c34bb 2379 (neg:DI (match_dup 1))
2380 (match_dup 1)))]
ac445222 2381 ""
d2ba5713 2382 { operands[2] = gen_reg_rtx (BImode); })
ac445222 2383
2384(define_expand "smindi3"
2385 [(set (match_dup 3)
33c8f6d1 2386 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
f087d65d 2387 (match_operand:DI 2 "gr_register_operand" "")))
2388 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2389 (if_then_else:DI (ne (match_dup 3) (const_int 0))
ac445222 2390 (match_dup 2) (match_dup 1)))]
2391 ""
d2ba5713 2392 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2393
2394(define_expand "smaxdi3"
2395 [(set (match_dup 3)
33c8f6d1 2396 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
f087d65d 2397 (match_operand:DI 2 "gr_register_operand" "")))
2398 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2399 (if_then_else:DI (ne (match_dup 3) (const_int 0))
ac445222 2400 (match_dup 1) (match_dup 2)))]
2401 ""
d2ba5713 2402 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2403
2404(define_expand "umindi3"
2405 [(set (match_dup 3)
33c8f6d1 2406 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
f087d65d 2407 (match_operand:DI 2 "gr_register_operand" "")))
2408 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2409 (if_then_else:DI (ne (match_dup 3) (const_int 0))
ac445222 2410 (match_dup 2) (match_dup 1)))]
2411 ""
d2ba5713 2412 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2413
2414(define_expand "umaxdi3"
2415 [(set (match_dup 3)
33c8f6d1 2416 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
f087d65d 2417 (match_operand:DI 2 "gr_register_operand" "")))
2418 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2419 (if_then_else:DI (ne (match_dup 3) (const_int 0))
ac445222 2420 (match_dup 1) (match_dup 2)))]
2421 ""
d2ba5713 2422 { operands[3] = gen_reg_rtx (BImode); })
ac445222 2423
2424(define_expand "ffsdi2"
2425 [(set (match_dup 6)
33c8f6d1 2426 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
ac445222 2427 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2428 (set (match_dup 5) (const_int 0))
2429 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2d0a3e2b 2430 (set (match_dup 4) (popcount:DI (match_dup 3)))
f087d65d 2431 (set (match_operand:DI 0 "gr_register_operand" "")
33c8f6d1 2432 (if_then_else:DI (ne (match_dup 6) (const_int 0))
ac445222 2433 (match_dup 5) (match_dup 4)))]
2434 ""
ac445222 2435{
2436 operands[2] = gen_reg_rtx (DImode);
2437 operands[3] = gen_reg_rtx (DImode);
2438 operands[4] = gen_reg_rtx (DImode);
2439 operands[5] = gen_reg_rtx (DImode);
33c8f6d1 2440 operands[6] = gen_reg_rtx (BImode);
d2ba5713 2441})
ac445222 2442
2d0a3e2b 2443(define_expand "ctzdi2"
2444 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2445 (const_int -1)))
2446 (set (match_dup 3) (not:DI (match_dup 1)))
2447 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2448 (set (match_operand:DI 0 "gr_register_operand" "")
2449 (popcount:DI (match_dup 4)))]
2450 ""
2451{
2452 operands[2] = gen_reg_rtx (DImode);
2453 operands[3] = gen_reg_rtx (DImode);
2454 operands[4] = gen_reg_rtx (DImode);
2455})
2456
2d0a3e2b 2457;; Note the computation here is op0 = 63 - (exp - 0xffff).
2458(define_expand "clzdi2"
2459 [(set (match_dup 2)
d363dedc 2460 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "")))
2d0a3e2b 2461 (set (match_dup 3)
2462 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2463 (set (match_dup 4) (const_int 65598))
2464 (set (match_operand:DI 0 "gr_register_operand" "")
2465 (minus:DI (match_dup 4) (match_dup 3)))]
b8bc42e9 2466 ""
2d0a3e2b 2467{
b8bc42e9 2468 operands[2] = gen_reg_rtx (XFmode);
2d0a3e2b 2469 operands[3] = gen_reg_rtx (DImode);
2470 operands[4] = gen_reg_rtx (DImode);
2471})
2472
2473(define_insn "popcountdi2"
f087d65d 2474 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2d0a3e2b 2475 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
ac445222 2476 ""
2477 "popcnt %0 = %1"
bf6ff2f6 2478 [(set_attr "itanium_class" "mmmul")])
ac445222 2479
b4267756 2480(define_insn "bswapdi2"
2481 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2482 (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2483 ""
2484 "mux1 %0 = %1, @rev"
2485 [(set_attr "itanium_class" "mmshf")])
2486
b8bc42e9 2487(define_insn "*getf_exp_xf"
2d0a3e2b 2488 [(set (match_operand:DI 0 "gr_register_operand" "=r")
d363dedc 2489 (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")]
2d0a3e2b 2490 UNSPEC_GETF_EXP))]
b8bc42e9 2491 ""
d363dedc 2492 "getf.exp %0 = %F1"
2d0a3e2b 2493 [(set_attr "itanium_class" "frfr")])
ac445222 2494\f
2495;; ::::::::::::::::::::
2496;; ::
3cc94518 2497;; :: 128-bit Integer arithmetic
4d053aca 2498;; ::
2499;; ::::::::::::::::::::
2500
2501(define_insn "addti3"
2502 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2503 (plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
2504 (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
2505 (clobber (match_scratch:BI 3 "=&c"))]
2506 ""
2507 "#"
2508 [(set_attr "itanium_class" "unknown")])
2509
2510(define_split
2511 [(set (match_operand:TI 0 "register_operand" "")
2512 (plus:TI (match_operand:TI 1 "register_operand" "")
2513 (match_operand:TI 2 "register_operand" "")))
2514 (clobber (match_scratch:BI 3 ""))]
2515 "reload_completed"
2516 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2517 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2518 (cond_exec (eq (match_dup 3) (const_int 0))
2519 (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
2520 (cond_exec (ne (match_dup 3) (const_int 0))
2521 (set (match_dup 4)
2522 (plus:DI (plus:DI (match_dup 5) (match_dup 6))
2523 (const_int 1))))]
2524{
2525 operands[4] = gen_highpart (DImode, operands[0]);
2526 operands[0] = gen_lowpart (DImode, operands[0]);
2527 operands[5] = gen_highpart (DImode, operands[1]);
2528 operands[1] = gen_lowpart (DImode, operands[1]);
2529 operands[6] = gen_highpart (DImode, operands[2]);
2530 operands[2] = gen_lowpart (DImode, operands[2]);
2531})
2532
2533(define_split
2534 [(set (match_operand:TI 0 "register_operand" "")
2535 (plus:TI (match_operand:TI 1 "register_operand" "")
2536 (match_operand:TI 2 "immediate_operand" "")))
2537 (clobber (match_scratch:BI 3 ""))]
2538 "reload_completed"
2539 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2540 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2541 (cond_exec (eq (match_dup 3) (const_int 0))
2542 (set (match_dup 4)
2543 (plus:DI (match_dup 5) (match_dup 6))))
2544 (cond_exec (ne (match_dup 3) (const_int 0))
2545 (set (match_dup 4)
2546 (plus:DI (match_dup 5) (match_dup 7))))]
2547{
2548 operands[4] = gen_highpart (DImode, operands[0]);
2549 operands[0] = gen_lowpart (DImode, operands[0]);
2550 operands[5] = gen_highpart (DImode, operands[1]);
2551 operands[1] = gen_lowpart (DImode, operands[1]);
2552 operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2553 operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
2554})
2555
2556(define_insn "subti3"
2557 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2558 (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
2559 (match_operand:TI 2 "gr_register_operand" "r")))
2560 (clobber (match_scratch:BI 3 "=&c"))]
2561 ""
2562 "#"
2563 [(set_attr "itanium_class" "unknown")])
2564
2565(define_split
2566 [(set (match_operand:TI 0 "register_operand" "")
2567 (minus:TI (match_operand:TI 1 "register_operand" "")
2568 (match_operand:TI 2 "register_operand" "")))
2569 (clobber (match_scratch:BI 3 "=&c"))]
2570 "reload_completed"
2571 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2572 (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
2573 (cond_exec (eq (match_dup 3) (const_int 0))
2574 (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
2575 (cond_exec (ne (match_dup 3) (const_int 0))
2576 (set (match_dup 4)
2577 (plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
2578{
2579 operands[4] = gen_highpart (DImode, operands[0]);
2580 operands[0] = gen_lowpart (DImode, operands[0]);
2581 operands[5] = gen_highpart (DImode, operands[1]);
2582 operands[1] = gen_lowpart (DImode, operands[1]);
2583 operands[6] = gen_highpart (DImode, operands[2]);
2584 operands[2] = gen_lowpart (DImode, operands[2]);
2585})
2586
2587(define_split
2588 [(set (match_operand:TI 0 "register_operand" "")
2589 (minus:TI (match_operand:TI 1 "immediate_operand" "")
2590 (match_operand:TI 2 "register_operand" "")))
2591 (clobber (match_scratch:BI 3 "=&c"))]
269f7060 2592 "reload_completed && satisfies_constraint_K (operands[1])"
4d053aca 2593 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2594 (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
2595 (cond_exec (ne (match_dup 3) (const_int 0))
2596 (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
2597 (cond_exec (eq (match_dup 3) (const_int 0))
2598 (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
2599{
2600 operands[4] = gen_highpart (DImode, operands[0]);
2601 operands[0] = gen_lowpart (DImode, operands[0]);
2602 operands[5] = gen_highpart (DImode, operands[2]);
2603 operands[2] = gen_lowpart (DImode, operands[2]);
2604 operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
2605 operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
2606})
2607
2608(define_expand "mulditi3"
2609 [(set (match_operand:TI 0 "fr_register_operand" "")
2610 (mult:TI (sign_extend:TI
d363dedc 2611 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
4d053aca 2612 (sign_extend:TI
d363dedc 2613 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
4d053aca 2614 ""
2615 "")
2616
2617(define_insn_and_split "*mulditi3_internal"
2618 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2619 (mult:TI (sign_extend:TI
d363dedc 2620 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
4d053aca 2621 (sign_extend:TI
d363dedc 2622 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
4d053aca 2623 ""
2624 "#"
2625 "reload_completed"
2626 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2627 (set (match_dup 3) (truncate:DI
2628 (lshiftrt:TI
2629 (mult:TI (sign_extend:TI (match_dup 1))
2630 (sign_extend:TI (match_dup 2)))
2631 (const_int 64))))]
2632{
2633 operands[3] = gen_highpart (DImode, operands[0]);
2634 operands[0] = gen_lowpart (DImode, operands[0]);
2635}
2636 [(set_attr "itanium_class" "unknown")])
2637
2638(define_expand "umulditi3"
2639 [(set (match_operand:TI 0 "fr_register_operand" "")
2640 (mult:TI (zero_extend:TI
d363dedc 2641 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
4d053aca 2642 (zero_extend:TI
d363dedc 2643 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
4d053aca 2644 ""
2645 "")
2646
2647(define_insn_and_split "*umulditi3_internal"
2648 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2649 (mult:TI (zero_extend:TI
d363dedc 2650 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
4d053aca 2651 (zero_extend:TI
d363dedc 2652 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
4d053aca 2653 ""
2654 "#"
2655 "reload_completed"
2656 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2657 (set (match_dup 3) (truncate:DI
2658 (lshiftrt:TI
2659 (mult:TI (zero_extend:TI (match_dup 1))
2660 (zero_extend:TI (match_dup 2)))
2661 (const_int 64))))]
2662{
2663 operands[3] = gen_highpart (DImode, operands[0]);
2664 operands[0] = gen_lowpart (DImode, operands[0]);
2665}
2666 [(set_attr "itanium_class" "unknown")])
2667
2668(define_insn_and_split "negti2"
2669 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2670 (neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
2671 (clobber (match_scratch:BI 2 "=&c"))]
2672 ""
2673 "#"
2674 "reload_completed"
2675 [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
2676 (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
2677 (cond_exec (eq (match_dup 2) (const_int 0))
2678 (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
2679 (cond_exec (ne (match_dup 2) (const_int 0))
2680 (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
2681{
2682 operands[3] = gen_highpart (DImode, operands[0]);
2683 operands[0] = gen_lowpart (DImode, operands[0]);
2684 operands[4] = gen_highpart (DImode, operands[1]);
2685 operands[1] = gen_lowpart (DImode, operands[1]);
2686}
2687 [(set_attr "itanium_class" "unknown")])
2688\f
2689;; ::::::::::::::::::::
2690;; ::
3cc94518 2691;; :: 32-bit floating point arithmetic
ac445222 2692;; ::
2693;; ::::::::::::::::::::
2694
2695(define_insn "addsf3"
f087d65d 2696 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3cc9aaf1 2697 (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "%fG")
2698 (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
ac445222 2699 ""
d363dedc 2700 "fadd.s %0 = %F1, %F2"
bf6ff2f6 2701 [(set_attr "itanium_class" "fmac")])
ac445222 2702
2703(define_insn "subsf3"
f087d65d 2704 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2705 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
3cc9aaf1 2706 (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
ac445222 2707 ""
8b0dd03f 2708 "fsub.s %0 = %F1, %F2"
bf6ff2f6 2709 [(set_attr "itanium_class" "fmac")])
ac445222 2710
2711(define_insn "mulsf3"
f087d65d 2712 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2713 (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2714 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2715 ""
d363dedc 2716 "fmpy.s %0 = %F1, %F2"
bf6ff2f6 2717 [(set_attr "itanium_class" "fmac")])
ac445222 2718
2719(define_insn "abssf2"
f087d65d 2720 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2721 (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2722 ""
d363dedc 2723 "fabs %0 = %F1"
bf6ff2f6 2724 [(set_attr "itanium_class" "fmisc")])
ac445222 2725
2726(define_insn "negsf2"
f087d65d 2727 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2728 (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2729 ""
d363dedc 2730 "fneg %0 = %F1"
bf6ff2f6 2731 [(set_attr "itanium_class" "fmisc")])
ac445222 2732
2733(define_insn "*nabssf2"
f087d65d 2734 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2735 (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))]
ac445222 2736 ""
d363dedc 2737 "fnegabs %0 = %F1"
bf6ff2f6 2738 [(set_attr "itanium_class" "fmisc")])
ac445222 2739
270436f3 2740(define_insn "copysignsf3"
2741 [(set (match_operand:SF 0 "register_operand" "=f")
2742 (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2743 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2744 UNSPEC_COPYSIGN))]
2745 ""
2746 "fmerge.s %0 = %F2, %F1"
2747 [(set_attr "itanium_class" "fmisc")])
2748
2749(define_insn "*ncopysignsf3"
2750 [(set (match_operand:SF 0 "register_operand" "=f")
2751 (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2752 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2753 UNSPEC_COPYSIGN)))]
2754 ""
2755 "fmerge.ns %0 = %F2, %F1"
2756 [(set_attr "itanium_class" "fmisc")])
2757
10c2e6f6 2758(define_insn "sminsf3"
f087d65d 2759 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2760 (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
f087d65d 2761 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2762 ""
d363dedc 2763 "fmin %0 = %F1, %F2"
bf6ff2f6 2764 [(set_attr "itanium_class" "fmisc")])
ac445222 2765
10c2e6f6 2766(define_insn "smaxsf3"
f087d65d 2767 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2768 (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
f087d65d 2769 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2770 ""
d363dedc 2771 "fmax %0 = %F1, %F2"
bf6ff2f6 2772 [(set_attr "itanium_class" "fmisc")])
ac445222 2773
ac445222 2774(define_insn "*nmulsf3"
f087d65d 2775 [(set (match_operand:SF 0 "fr_register_operand" "=f")
d363dedc 2776 (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2777 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
ac445222 2778 ""
d363dedc 2779 "fnmpy.s %0 = %F1, %F2"
bf6ff2f6 2780 [(set_attr "itanium_class" "fmac")])
ac445222 2781
2fd6708c 2782(define_insn "fmasf4"
2783 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2784 (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2785 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2786 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2787 ""
2788 "fma.s %0 = %F1, %F2, %F3"
2789 [(set_attr "itanium_class" "fmac")])
2790
dd7870fa 2791(define_insn "fmssf4"
2fd6708c 2792 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2793 (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2794 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2795 (neg:SF
2796 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2797 ""
2798 "fms.s %0 = %F1, %F2, %F3"
2799 [(set_attr "itanium_class" "fmac")])
2800
dd7870fa 2801(define_insn "fnmasf4"
2fd6708c 2802 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2803 (fma:SF (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))
2804 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
2805 (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2806 ""
2807 "fnma.s %0 = %F1, %F2, %F3"
2808 [(set_attr "itanium_class" "fmac")])
ac445222 2809\f
2810;; ::::::::::::::::::::
2811;; ::
3cc94518 2812;; :: 64-bit floating point arithmetic
ac445222 2813;; ::
2814;; ::::::::::::::::::::
2815
2816(define_insn "adddf3"
f087d65d 2817 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3cc9aaf1 2818 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
2819 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
ac445222 2820 ""
d363dedc 2821 "fadd.d %0 = %F1, %F2"
bf6ff2f6 2822 [(set_attr "itanium_class" "fmac")])
ac445222 2823
276f19f8 2824(define_insn "*adddf3_trunc"
2825 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2826 (float_truncate:SF
3cc9aaf1 2827 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG")
2828 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
276f19f8 2829 ""
d363dedc 2830 "fadd.s %0 = %F1, %F2"
bf6ff2f6 2831 [(set_attr "itanium_class" "fmac")])
276f19f8 2832
ac445222 2833(define_insn "subdf3"
f087d65d 2834 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2835 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3cc9aaf1 2836 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))]
ac445222 2837 ""
8b0dd03f 2838 "fsub.d %0 = %F1, %F2"
bf6ff2f6 2839 [(set_attr "itanium_class" "fmac")])
ac445222 2840
276f19f8 2841(define_insn "*subdf3_trunc"
2842 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2843 (float_truncate:SF
2844 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
3cc9aaf1 2845 (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))]
276f19f8 2846 ""
8b0dd03f 2847 "fsub.s %0 = %F1, %F2"
bf6ff2f6 2848 [(set_attr "itanium_class" "fmac")])
276f19f8 2849
ac445222 2850(define_insn "muldf3"
f087d65d 2851 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2852 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2853 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2854 ""
d363dedc 2855 "fmpy.d %0 = %F1, %F2"
bf6ff2f6 2856 [(set_attr "itanium_class" "fmac")])
ac445222 2857
276f19f8 2858(define_insn "*muldf3_trunc"
2859 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2860 (float_truncate:SF
d363dedc 2861 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2862 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
276f19f8 2863 ""
d363dedc 2864 "fmpy.s %0 = %F1, %F2"
bf6ff2f6 2865 [(set_attr "itanium_class" "fmac")])
276f19f8 2866
ac445222 2867(define_insn "absdf2"
f087d65d 2868 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2869 (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2870 ""
d363dedc 2871 "fabs %0 = %F1"
bf6ff2f6 2872 [(set_attr "itanium_class" "fmisc")])
ac445222 2873
2874(define_insn "negdf2"
f087d65d 2875 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2876 (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2877 ""
d363dedc 2878 "fneg %0 = %F1"
bf6ff2f6 2879 [(set_attr "itanium_class" "fmisc")])
ac445222 2880
2881(define_insn "*nabsdf2"
f087d65d 2882 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2883 (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))]
ac445222 2884 ""
d363dedc 2885 "fnegabs %0 = %F1"
bf6ff2f6 2886 [(set_attr "itanium_class" "fmisc")])
ac445222 2887
270436f3 2888(define_insn "copysigndf3"
2889 [(set (match_operand:DF 0 "register_operand" "=f")
2890 (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2891 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2892 UNSPEC_COPYSIGN))]
2893 ""
2894 "fmerge.s %0 = %F2, %F1"
2895 [(set_attr "itanium_class" "fmisc")])
2896
2897(define_insn "*ncopysigndf3"
2898 [(set (match_operand:DF 0 "register_operand" "=f")
2899 (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2900 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2901 UNSPEC_COPYSIGN)))]
2902 ""
2903 "fmerge.ns %0 = %F2, %F1"
2904 [(set_attr "itanium_class" "fmisc")])
2905
10c2e6f6 2906(define_insn "smindf3"
f087d65d 2907 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2908 (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
f087d65d 2909 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2910 ""
d363dedc 2911 "fmin %0 = %F1, %F2"
bf6ff2f6 2912 [(set_attr "itanium_class" "fmisc")])
ac445222 2913
10c2e6f6 2914(define_insn "smaxdf3"
f087d65d 2915 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2916 (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
f087d65d 2917 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
ac445222 2918 ""
d363dedc 2919 "fmax %0 = %F1, %F2"
bf6ff2f6 2920 [(set_attr "itanium_class" "fmisc")])
ac445222 2921
ac445222 2922(define_insn "*nmuldf3"
f087d65d 2923 [(set (match_operand:DF 0 "fr_register_operand" "=f")
d363dedc 2924 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2925 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
ac445222 2926 ""
d363dedc 2927 "fnmpy.d %0 = %F1, %F2"
bf6ff2f6 2928 [(set_attr "itanium_class" "fmac")])
ac445222 2929
276f19f8 2930(define_insn "*nmuldf3_trunc"
2931 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2932 (float_truncate:SF
d363dedc 2933 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2934 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
276f19f8 2935 ""
d363dedc 2936 "fnmpy.s %0 = %F1, %F2"
bf6ff2f6 2937 [(set_attr "itanium_class" "fmac")])
276f19f8 2938
2fd6708c 2939(define_insn "fmadf4"
2940 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2941 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2942 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2943 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2944 ""
2945 "fma.d %0 = %F1, %F2, %F3"
2946 [(set_attr "itanium_class" "fmac")])
2947
dd7870fa 2948(define_insn "*fmadf_trunc_sf"
2949 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2950 (float_truncate:SF
2951 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2952 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2953 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2954 ""
2955 "fma.s %0 = %F1, %F2, %F3"
2956 [(set_attr "itanium_class" "fmac")])
2957
2958(define_insn "fmsdf4"
2fd6708c 2959 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2960 (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2961 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2962 (neg:DF
2963 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2964 ""
2965 "fms.d %0 = %F1, %F2, %F3"
2966 [(set_attr "itanium_class" "fmac")])
2967
dd7870fa 2968(define_insn "*fmsdf_trunc_sf"
2969 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2970 (float_truncate:SF
2971 (fma:DF
2972 (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2973 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2974 (neg:DF
2975 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))]
2976 ""
2977 "fms.s %0 = %F1, %F2, %F3"
2978 [(set_attr "itanium_class" "fmac")])
2979
2980(define_insn "fnmadf4"
2fd6708c 2981 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2982 (fma:DF (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))
2983 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2984 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
2985 ""
2986 "fnma.d %0 = %F1, %F2, %F3"
2987 [(set_attr "itanium_class" "fmac")])
dd7870fa 2988
2989(define_insn "*fnmadf_trunc_sf"
2990 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2991 (float_truncate:SF
2992 (fma:DF
2993 (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))
2994 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
2995 (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
2996 ""
2997 "fnma.s %0 = %F1, %F2, %F3"
2998 [(set_attr "itanium_class" "fmac")])
d5f10acf 2999\f
3000;; ::::::::::::::::::::
3001;; ::
3cc94518 3002;; :: 80-bit floating point arithmetic
d5f10acf 3003;; ::
3004;; ::::::::::::::::::::
3005
b8bc42e9 3006(define_insn "addxf3"
3007 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3cc9aaf1 3008 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3009 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
b8bc42e9 3010 ""
8b0dd03f 3011 "fadd %0 = %F1, %F2"
bf6ff2f6 3012 [(set_attr "itanium_class" "fmac")])
d5f10acf 3013
b8bc42e9 3014(define_insn "*addxf3_truncsf"
276f19f8 3015 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3016 (float_truncate:SF
3cc9aaf1 3017 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3018 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
b8bc42e9 3019 ""
8b0dd03f 3020 "fadd.s %0 = %F1, %F2"
bf6ff2f6 3021 [(set_attr "itanium_class" "fmac")])
276f19f8 3022
b8bc42e9 3023(define_insn "*addxf3_truncdf"
276f19f8 3024 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3025 (float_truncate:DF
3cc9aaf1 3026 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG")
3027 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
b8bc42e9 3028 ""
8b0dd03f 3029 "fadd.d %0 = %F1, %F2"
bf6ff2f6 3030 [(set_attr "itanium_class" "fmac")])
276f19f8 3031
b8bc42e9 3032(define_insn "subxf3"
3033 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3034 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3cc9aaf1 3035 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))]
b8bc42e9 3036 ""
8b0dd03f 3037 "fsub %0 = %F1, %F2"
bf6ff2f6 3038 [(set_attr "itanium_class" "fmac")])
d5f10acf 3039
b8bc42e9 3040(define_insn "*subxf3_truncsf"
276f19f8 3041 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3042 (float_truncate:SF
b8bc42e9 3043 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3cc9aaf1 3044 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
b8bc42e9 3045 ""
8b0dd03f 3046 "fsub.s %0 = %F1, %F2"
bf6ff2f6 3047 [(set_attr "itanium_class" "fmac")])
276f19f8 3048
b8bc42e9 3049(define_insn "*subxf3_truncdf"
276f19f8 3050 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3051 (float_truncate:DF
b8bc42e9 3052 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3cc9aaf1 3053 (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))]
b8bc42e9 3054 ""
8b0dd03f 3055 "fsub.d %0 = %F1, %F2"
bf6ff2f6 3056 [(set_attr "itanium_class" "fmac")])
276f19f8 3057
b8bc42e9 3058(define_insn "mulxf3"
3059 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3060 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3061 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3062 ""
8b0dd03f 3063 "fmpy %0 = %F1, %F2"
bf6ff2f6 3064 [(set_attr "itanium_class" "fmac")])
d5f10acf 3065
b8bc42e9 3066(define_insn "*mulxf3_truncsf"
276f19f8 3067 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3068 (float_truncate:SF
b8bc42e9 3069 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3070 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3071 ""
8b0dd03f 3072 "fmpy.s %0 = %F1, %F2"
bf6ff2f6 3073 [(set_attr "itanium_class" "fmac")])
276f19f8 3074
b8bc42e9 3075(define_insn "*mulxf3_truncdf"
276f19f8 3076 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3077 (float_truncate:DF
b8bc42e9 3078 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3079 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3080 ""
8b0dd03f 3081 "fmpy.d %0 = %F1, %F2"
bf6ff2f6 3082 [(set_attr "itanium_class" "fmac")])
276f19f8 3083
b8bc42e9 3084(define_insn "absxf2"
3085 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3086 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3087 ""
8b0dd03f 3088 "fabs %0 = %F1"
bf6ff2f6 3089 [(set_attr "itanium_class" "fmisc")])
d5f10acf 3090
b8bc42e9 3091(define_insn "negxf2"
3092 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3093 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3094 ""
8b0dd03f 3095 "fneg %0 = %F1"
bf6ff2f6 3096 [(set_attr "itanium_class" "fmisc")])
d5f10acf 3097
b8bc42e9 3098(define_insn "*nabsxf2"
3099 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3100 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3101 ""
8b0dd03f 3102 "fnegabs %0 = %F1"
bf6ff2f6 3103 [(set_attr "itanium_class" "fmisc")])
d5f10acf 3104
270436f3 3105(define_insn "copysignxf3"
3106 [(set (match_operand:XF 0 "register_operand" "=f")
3107 (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3108 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3109 UNSPEC_COPYSIGN))]
3110 ""
3111 "fmerge.s %0 = %F2, %F1"
3112 [(set_attr "itanium_class" "fmisc")])
3113
3114(define_insn "*ncopysignxf3"
3115 [(set (match_operand:XF 0 "register_operand" "=f")
3116 (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3117 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3118 UNSPEC_COPYSIGN)))]
3119 ""
3120 "fmerge.ns %0 = %F2, %F1"
3121 [(set_attr "itanium_class" "fmisc")])
3122
10c2e6f6 3123(define_insn "sminxf3"
b8bc42e9 3124 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3125 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3126 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3127 ""
8b0dd03f 3128 "fmin %0 = %F1, %F2"
bf6ff2f6 3129 [(set_attr "itanium_class" "fmisc")])
d5f10acf 3130
10c2e6f6 3131(define_insn "smaxxf3"
b8bc42e9 3132 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3133 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3134 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3135 ""
8b0dd03f 3136 "fmax %0 = %F1, %F2"
bf6ff2f6 3137 [(set_attr "itanium_class" "fmisc")])
d5f10acf 3138
b8bc42e9 3139(define_insn "*nmulxf3"
3140 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3141 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3142 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3143 ""
8b0dd03f 3144 "fnmpy %0 = %F1, %F2"
bf6ff2f6 3145 [(set_attr "itanium_class" "fmac")])
ac445222 3146
b8bc42e9 3147(define_insn "*nmulxf3_truncsf"
276f19f8 3148 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3149 (float_truncate:SF
b8bc42e9 3150 (neg:XF (mult:XF
3151 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3152 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3153 ""
8b0dd03f 3154 "fnmpy.s %0 = %F1, %F2"
bf6ff2f6 3155 [(set_attr "itanium_class" "fmac")])
276f19f8 3156
b8bc42e9 3157(define_insn "*nmulxf3_truncdf"
276f19f8 3158 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3159 (float_truncate:DF
b8bc42e9 3160 (neg:XF (mult:XF
3161 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3162 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3163 ""
8b0dd03f 3164 "fnmpy.d %0 = %F1, %F2"
bf6ff2f6 3165 [(set_attr "itanium_class" "fmac")])
276f19f8 3166
2fd6708c 3167(define_insn "fmaxf4"
3168 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3169 (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3170 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3171 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
3172 ""
3173 "fma %0 = %F1, %F2, %F3"
3174 [(set_attr "itanium_class" "fmac")])
3175
dd7870fa 3176(define_insn "*fmaxf_trunc_<mode>"
3177 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3178 (float_truncate:MODE_SDF
3179 (fma:XF
3180 (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3181 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3182 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3183 ""
3184 "fma<suffix> %0 = %F1, %F2, %F3"
3185 [(set_attr "itanium_class" "fmac")])
3186
3187(define_insn "fmsxf4"
2fd6708c 3188 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3189 (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3190 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3191 (neg:XF
3192 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3193 ""
3194 "fms %0 = %F1, %F2, %F3"
3195 [(set_attr "itanium_class" "fmac")])
3196
dd7870fa 3197(define_insn "*fmsxf_trunc_<mode>"
3198 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3199 (float_truncate:MODE_SDF
3200 (fma:XF
3201 (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3202 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3203 (neg:XF
3204 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))]
3205 ""
3206 "fms<suffix> %0 = %F1, %F2, %F3"
3207 [(set_attr "itanium_class" "fmac")])
3208
3209(define_insn "fnmaxf4"
2fd6708c 3210 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3211 (fma:XF (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))
3212 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3213 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))]
3214 ""
3215 "fnma %0 = %F1, %F2, %F3"
3216 [(set_attr "itanium_class" "fmac")])
dd7870fa 3217
3218(define_insn "*fnmaxf_trunc_<mode>"
3219 [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f")
3220 (float_truncate:MODE_SDF
3221 (fma:XF
3222 (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))
3223 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
3224 (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))]
3225 ""
3226 "fnma<suffix> %0 = %F1, %F2, %F3"
3227 [(set_attr "itanium_class" "fmac")])
ac445222 3228\f
3229;; ::::::::::::::::::::
3230;; ::
3cc94518 3231;; :: 32-bit Integer Shifts and Rotates
ac445222 3232;; ::
3233;; ::::::::::::::::::::
3234
2f3e8f0e 3235(define_expand "ashlsi3"
f087d65d 3236 [(set (match_operand:SI 0 "gr_register_operand" "")
3237 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3238 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
2f3e8f0e 3239 ""
2f3e8f0e 3240{
3241 if (GET_CODE (operands[2]) != CONST_INT)
3242 {
3243 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3244 we've got to get rid of stray bits outside the SImode register. */
3245 rtx subshift = gen_reg_rtx (DImode);
3246 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3247 operands[2] = subshift;
3248 }
d2ba5713 3249})
2f3e8f0e 3250
3251(define_insn "*ashlsi3_internal"
f087d65d 3252 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3253 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3254 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
ac445222 3255 ""
6709362a 3256 "@
3257 shladd %0 = %1, %2, r0
3258 dep.z %0 = %1, %2, %E2
3259 shl %0 = %1, %2"
bf6ff2f6 3260 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
ac445222 3261
3262(define_expand "ashrsi3"
f087d65d 3263 [(set (match_operand:SI 0 "gr_register_operand" "")
3264 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3265 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
ac445222 3266 ""
ac445222 3267{
6709362a 3268 rtx subtarget = gen_reg_rtx (DImode);
3269 if (GET_CODE (operands[2]) == CONST_INT)
3270 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3271 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3272 else
3273 {
2f3e8f0e 3274 rtx subshift = gen_reg_rtx (DImode);
6709362a 3275 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
2f3e8f0e 3276 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3277 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
6709362a 3278 }
3279 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3280 DONE;
d2ba5713 3281})
ac445222 3282
ac445222 3283(define_expand "lshrsi3"
f087d65d 3284 [(set (match_operand:SI 0 "gr_register_operand" "")
3285 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3286 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
ac445222 3287 ""
ac445222 3288{
6709362a 3289 rtx subtarget = gen_reg_rtx (DImode);
3290 if (GET_CODE (operands[2]) == CONST_INT)
3291 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3292 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3293 else
3294 {
2f3e8f0e 3295 rtx subshift = gen_reg_rtx (DImode);
6709362a 3296 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
2f3e8f0e 3297 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3298 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
6709362a 3299 }
3300 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3301 DONE;
d2ba5713 3302})
ac445222 3303
ac445222 3304;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
1ef83f39 3305;; here, instead of 64 like the patterns above. Keep the pattern together
3306;; until after combine; otherwise it won't get matched often.
ac445222 3307
3308(define_expand "rotrsi3"
1ef83f39 3309 [(set (match_operand:SI 0 "gr_register_operand" "")
3310 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3311 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3312 ""
1ef83f39 3313{
3314 if (GET_MODE (operands[2]) != VOIDmode)
3315 {
3316 rtx tmp = gen_reg_rtx (DImode);
3317 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3318 operands[2] = tmp;
3319 }
d2ba5713 3320})
1ef83f39 3321
3322(define_insn_and_split "*rotrsi3_internal"
3323 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3324 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3325 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3326 ""
3327 "#"
3328 "reload_completed"
ac445222 3329 [(set (match_dup 3)
1ef83f39 3330 (ior:DI (zero_extend:DI (match_dup 1))
ac445222 3331 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3332 (set (match_dup 3)
1ef83f39 3333 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3334 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3335
3336(define_expand "rotlsi3"
3337 [(set (match_operand:SI 0 "gr_register_operand" "")
3338 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3339 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
ac445222 3340 ""
ac445222 3341{
3342 if (! shift_32bit_count_operand (operands[2], SImode))
1ef83f39 3343 {
3344 rtx tmp = gen_reg_rtx (SImode);
3345 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3346 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3347 DONE;
3348 }
d2ba5713 3349})
1ef83f39 3350
3351(define_insn_and_split "*rotlsi3_internal"
3352 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3353 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3354 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3355 ""
c1dff23b 3356 "mux2 %0 = %1, 0xe1"
3357 "reload_completed && INTVAL (operands[2]) != 16"
1ef83f39 3358 [(set (match_dup 3)
3359 (ior:DI (zero_extend:DI (match_dup 1))
3360 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3361 (set (match_dup 3)
3362 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
d2ba5713 3363{
3364 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3365 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
c1dff23b 3366}
3367 [(set_attr "itanium_class" "mmshf")])
ac445222 3368\f
3369;; ::::::::::::::::::::
3370;; ::
3cc94518 3371;; :: 64-bit Integer Shifts and Rotates
ac445222 3372;; ::
3373;; ::::::::::::::::::::
3374
3375(define_insn "ashldi3"
bf6ff2f6 3376 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3377 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3378 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
ac445222 3379 ""
6709362a 3380 "@
3381 shladd %0 = %1, %2, r0
bf6ff2f6 3382 shl %0 = %1, %2
6709362a 3383 shl %0 = %1, %2"
bf6ff2f6 3384 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
ac445222 3385
3386;; ??? Maybe combine this with the multiply and add instruction?
3387
3388(define_insn "*shladd"
f087d65d 3389 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3390 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 3391 (match_operand:DI 2 "shladd_operand" "n"))
f087d65d 3392 (match_operand:DI 3 "gr_register_operand" "r")))]
ac445222 3393 ""
3394 "shladd %0 = %1, %S2, %3"
bf6ff2f6 3395 [(set_attr "itanium_class" "ialu")])
ac445222 3396
3397;; This can be created by register elimination if operand3 of shladd is an
3398;; eliminable register or has reg_equiv_constant set.
3399
3400;; We have to use nonmemory_operand for operand 4, to ensure that the
3401;; validate_changes call inside eliminate_regs will always succeed. If it
3402;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3403;; incorrectly.
3404
9641f63c 3405(define_insn_and_split "*shladd_elim"
f087d65d 3406 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3407 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 3408 (match_operand:DI 2 "shladd_operand" "n"))
9641f63c 3409 (match_operand:DI 3 "nonmemory_operand" "r"))
ac445222 3410 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3411 "reload_in_progress"
c5c17bca 3412 "* gcc_unreachable ();"
ac445222 3413 "reload_completed"
3414 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3415 (match_dup 3)))
ac445222 3416 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
9641f63c 3417 ""
bf6ff2f6 3418 [(set_attr "itanium_class" "unknown")])
ac445222 3419
3420(define_insn "ashrdi3"
bf6ff2f6 3421 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3422 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3423 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
ac445222 3424 ""
bf6ff2f6 3425 "@
3426 shr %0 = %1, %2
3427 shr %0 = %1, %2"
3428 [(set_attr "itanium_class" "mmshf,mmshfi")])
ac445222 3429
3430(define_insn "lshrdi3"
bf6ff2f6 3431 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3432 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3433 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
ac445222 3434 ""
bf6ff2f6 3435 "@
3436 shr.u %0 = %1, %2
3437 shr.u %0 = %1, %2"
3438 [(set_attr "itanium_class" "mmshf,mmshfi")])
ac445222 3439
3440;; Using a predicate that accepts only constants doesn't work, because optabs
3441;; will load the operand into a register and call the pattern if the predicate
3442;; did not accept it on the first try. So we use nonmemory_operand and then
3443;; verify that we have an appropriate constant in the expander.
3444
3445(define_expand "rotrdi3"
f087d65d 3446 [(set (match_operand:DI 0 "gr_register_operand" "")
3447 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
ac445222 3448 (match_operand:DI 2 "nonmemory_operand" "")))]
3449 ""
ac445222 3450{
3451 if (! shift_count_operand (operands[2], DImode))
3452 FAIL;
d2ba5713 3453})
ac445222 3454
3455(define_insn "*rotrdi3_internal"
f087d65d 3456 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3457 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 3458 (match_operand:DI 2 "shift_count_operand" "M")))]
3459 ""
3460 "shrp %0 = %1, %1, %2"
bf6ff2f6 3461 [(set_attr "itanium_class" "ishf")])
ac445222 3462
1ef83f39 3463(define_expand "rotldi3"
3464 [(set (match_operand:DI 0 "gr_register_operand" "")
3465 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3466 (match_operand:DI 2 "nonmemory_operand" "")))]
3467 ""
1ef83f39 3468{
3469 if (! shift_count_operand (operands[2], DImode))
3470 FAIL;
d2ba5713 3471})
1ef83f39 3472
3473(define_insn "*rotldi3_internal"
3474 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3475 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3476 (match_operand:DI 2 "shift_count_operand" "M")))]
3477 ""
3478 "shrp %0 = %1, %1, %e2"
bf6ff2f6 3479 [(set_attr "itanium_class" "ishf")])
6d6f3860 3480\f
3481;; ::::::::::::::::::::
3482;; ::
3cc94518 3483;; :: 128-bit Integer Shifts and Rotates
6d6f3860 3484;; ::
3485;; ::::::::::::::::::::
3486
814d3ff5 3487(define_expand "ashlti3"
3488 [(set (match_operand:TI 0 "gr_register_operand" "")
3489 (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
3490 (match_operand:DI 2 "nonmemory_operand" "")))]
3491 ""
3492{
3493 if (!dshift_count_operand (operands[2], DImode))
3494 FAIL;
3495})
3496
3497(define_insn_and_split "*ashlti3_internal"
3498 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3499 (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
3500 (match_operand:DI 2 "dshift_count_operand" "n")))]
3501 ""
3502 "#"
3503 "reload_completed"
3504 [(const_int 0)]
3505{
3506 HOST_WIDE_INT shift = INTVAL (operands[2]);
3507 rtx rl = gen_lowpart (DImode, operands[0]);
3508 rtx rh = gen_highpart (DImode, operands[0]);
3509 rtx lo = gen_lowpart (DImode, operands[1]);
3510 rtx shiftlo = GEN_INT (shift & 63);
3511
3512 if (shift & 64)
3513 {
3514 emit_move_insn (rl, const0_rtx);
3515 if (shift & 63)
3516 emit_insn (gen_ashldi3 (rh, lo, shiftlo));
3517 else
3518 emit_move_insn (rh, lo);
3519 }
3520 else
3521 {
3522 rtx hi = gen_highpart (DImode, operands[1]);
3523
3524 emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
3525 emit_insn (gen_ashldi3 (rl, lo, shiftlo));
3526 }
3527 DONE;
3528})
3529
6d6f3860 3530(define_expand "ashrti3"
3531 [(set (match_operand:TI 0 "gr_register_operand" "")
3532 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3533 (match_operand:DI 2 "nonmemory_operand" "")))]
3534 ""
3535{
3536 if (!dshift_count_operand (operands[2], DImode))
3537 FAIL;
3538})
3539
3540(define_insn_and_split "*ashrti3_internal"
814d3ff5 3541 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
6d6f3860 3542 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3543 (match_operand:DI 2 "dshift_count_operand" "n")))]
3544 ""
3545 "#"
3546 "reload_completed"
3547 [(const_int 0)]
3548{
3549 HOST_WIDE_INT shift = INTVAL (operands[2]);
814d3ff5 3550 rtx rl = gen_lowpart (DImode, operands[0]);
3551 rtx rh = gen_highpart (DImode, operands[0]);
6d6f3860 3552 rtx hi = gen_highpart (DImode, operands[1]);
3553 rtx shiftlo = GEN_INT (shift & 63);
3554
3555 if (shift & 64)
3556 {
814d3ff5 3557 if (shift & 63)
3558 emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
3559 else
3560 emit_move_insn (rl, hi);
3561 emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
6d6f3860 3562 }
3563 else
3564 {
814d3ff5 3565 rtx lo = gen_lowpart (DImode, operands[1]);
3566
3567 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3568 emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
6d6f3860 3569 }
3570 DONE;
3571})
3572
3573(define_expand "lshrti3"
3574 [(set (match_operand:TI 0 "gr_register_operand" "")
3575 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3576 (match_operand:DI 2 "nonmemory_operand" "")))]
3577 ""
3578{
3579 if (!dshift_count_operand (operands[2], DImode))
3580 FAIL;
3581})
3582
3583(define_insn_and_split "*lshrti3_internal"
814d3ff5 3584 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
6d6f3860 3585 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3586 (match_operand:DI 2 "dshift_count_operand" "n")))]
3587 ""
3588 "#"
3589 "reload_completed"
3590 [(const_int 0)]
3591{
3592 HOST_WIDE_INT shift = INTVAL (operands[2]);
814d3ff5 3593 rtx rl = gen_lowpart (DImode, operands[0]);
3594 rtx rh = gen_highpart (DImode, operands[0]);
6d6f3860 3595 rtx hi = gen_highpart (DImode, operands[1]);
3596 rtx shiftlo = GEN_INT (shift & 63);
3597
3598 if (shift & 64)
3599 {
814d3ff5 3600 if (shift & 63)
3601 emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
3602 else
3603 emit_move_insn (rl, hi);
3604 emit_move_insn (rh, const0_rtx);
6d6f3860 3605 }
3606 else
3607 {
814d3ff5 3608 rtx lo = gen_lowpart (DImode, operands[1]);
3609
3610 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3611 emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
6d6f3860 3612 }
3613 DONE;
3614})
3615
4d053aca 3616(define_expand "rotlti3"
3617 [(set (match_operand:TI 0 "gr_register_operand" "")
3618 (rotate:TI (match_operand:TI 1 "gr_register_operand" "")
3619 (match_operand:DI 2 "nonmemory_operand" "")))]
3620 ""
3621{
3622 if (! dshift_count_operand (operands[2], DImode))
3623 FAIL;
3624})
3625
3626(define_insn_and_split "*rotlti3_internal"
3627 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3628 (rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
3629 (match_operand:DI 2 "dshift_count_operand" "n")))]
3630 ""
3631 "#"
3632 "reload_completed"
3633 [(const_int 0)]
3634{
3635 HOST_WIDE_INT count = INTVAL (operands[2]);
3636 rtx rl = gen_lowpart (DImode, operands[0]);
3637 rtx rh = gen_highpart (DImode, operands[0]);
3638 rtx lo = gen_lowpart (DImode, operands[1]);
3639 rtx hi = gen_highpart (DImode, operands[1]);
3640 rtx countlo = GEN_INT (-count & 63);
3641
3642 if (count & 64)
3643 {
3644 if (count & 63)
3645 {
3646 emit_insn (gen_shrp (rl, hi, lo, countlo));
3647 emit_insn (gen_shrp (rh, lo, hi, countlo));
3648 }
3649 else
3650 {
3651 emit_move_insn (rl, hi);
3652 emit_move_insn (rh, lo);
3653 }
3654 }
3655 else
3656 {
3657 emit_insn (gen_shrp (rl, lo, hi, countlo));
3658 emit_insn (gen_shrp (rh, hi, lo, countlo));
3659 }
3660 DONE;
3661}
3662 [(set_attr "itanium_class" "unknown")])
3663
6d6f3860 3664(define_insn "shrp"
3665 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3666 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
3667 (match_operand:DI 2 "gr_register_operand" "r")
3668 (match_operand:DI 3 "shift_count_operand" "M")]
3669 UNSPEC_SHRP))]
3670 ""
3671 "shrp %0 = %1, %2, %3"
3672 [(set_attr "itanium_class" "ishf")])
ac445222 3673\f
3674;; ::::::::::::::::::::
3675;; ::
3cc94518 3676;; :: 32-bit Integer Logical operations
ac445222 3677;; ::
3678;; ::::::::::::::::::::
3679
3680;; We don't seem to need any other 32-bit logical operations, because gcc
3681;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3682;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3683;; This doesn't work for unary logical operations, because we don't call
3684;; apply_distributive_law for them.
3685
3686;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3687;; apply_distributive_law. We get inefficient code for
3688;; int sub4 (int i, int j) { return i & ~j; }
3689;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3690;; (zero_extend (and (not A) B)) in combine.
3691;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3692;; one_cmplsi2 pattern.
3693
eab36ec2 3694(define_insn "one_cmplsi2"
f087d65d 3695 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3696 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
ac445222 3697 ""
3698 "andcm %0 = -1, %1"
bf6ff2f6 3699 [(set_attr "itanium_class" "ilog")])
ac445222 3700\f
3701;; ::::::::::::::::::::
3702;; ::
3cc94518 3703;; :: 64-bit Integer Logical operations
ac445222 3704;; ::
3705;; ::::::::::::::::::::
3706
3707(define_insn "anddi3"
f087d65d 3708 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3709 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3710 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
ac445222 3711 ""
3712 "@
3713 and %0 = %2, %1
8b0dd03f 3714 fand %0 = %2, %1"
bf6ff2f6 3715 [(set_attr "itanium_class" "ilog,fmisc")])
ac445222 3716
3717(define_insn "*andnot"
f087d65d 3718 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3719 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3720 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
ac445222 3721 ""
3722 "@
3723 andcm %0 = %2, %1
8b0dd03f 3724 fandcm %0 = %2, %1"
bf6ff2f6 3725 [(set_attr "itanium_class" "ilog,fmisc")])
ac445222 3726
3727(define_insn "iordi3"
f087d65d 3728 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3729 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3730 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
ac445222 3731 ""
3732 "@
3733 or %0 = %2, %1
8b0dd03f 3734 for %0 = %2, %1"
bf6ff2f6 3735 [(set_attr "itanium_class" "ilog,fmisc")])
ac445222 3736
3737(define_insn "xordi3"
f087d65d 3738 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3739 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3740 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
ac445222 3741 ""
3742 "@
3743 xor %0 = %2, %1
8b0dd03f 3744 fxor %0 = %2, %1"
bf6ff2f6 3745 [(set_attr "itanium_class" "ilog,fmisc")])
ac445222 3746
3747(define_insn "one_cmpldi2"
f087d65d 3748 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3749 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
ac445222 3750 ""
3751 "andcm %0 = -1, %1"
bf6ff2f6 3752 [(set_attr "itanium_class" "ilog")])
ac445222 3753\f
3754;; ::::::::::::::::::::
3755;; ::
3756;; :: Comparisons
3757;; ::
3758;; ::::::::::::::::::::
3759
74f4459c 3760(define_expand "cbranchbi4"
3761 [(set (pc)
3762 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3763 [(match_operand:BI 1 "register_operand" "")
3764 (match_operand:BI 2 "const_int_operand" "")])
3765 (label_ref (match_operand 3 "" ""))
3766 (pc)))]
33c8f6d1 3767 ""
74f4459c 3768 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
33c8f6d1 3769
74f4459c 3770(define_expand "cbranchsi4"
3771 [(set (pc)
3772 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3773 [(match_operand:SI 1 "gr_register_operand" "")
3774 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3775 (label_ref (match_operand 3 "" ""))
3776 (pc)))]
ac445222 3777 ""
74f4459c 3778 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
ac445222 3779
74f4459c 3780(define_expand "cbranchdi4"
3781 [(set (pc)
3782 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3783 [(match_operand:DI 1 "gr_register_operand" "")
3784 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3785 (label_ref (match_operand 3 "" ""))
3786 (pc)))]
ac445222 3787 ""
74f4459c 3788 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
ac445222 3789
74f4459c 3790(define_expand "cbranchsf4"
3791 [(set (pc)
3792 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3793 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
3794 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
3795 (label_ref (match_operand 3 "" ""))
3796 (pc)))]
ac445222 3797 ""
74f4459c 3798 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
ac445222 3799
74f4459c 3800(define_expand "cbranchdf4"
3801 [(set (pc)
3802 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3803 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
3804 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
3805 (label_ref (match_operand 3 "" ""))
3806 (pc)))]
ac445222 3807 ""
74f4459c 3808 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
ac445222 3809
74f4459c 3810(define_expand "cbranchxf4"
3811 [(set (pc)
3812 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3813 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
3814 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
3815 (label_ref (match_operand 3 "" ""))
3816 (pc)))]
b8bc42e9 3817 ""
74f4459c 3818 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
ac445222 3819
74f4459c 3820(define_expand "cbranchtf4"
3821 [(set (pc)
3822 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3823 [(match_operand:TF 1 "gr_register_operand" "")
3824 (match_operand:TF 2 "gr_register_operand" "")])
3825 (label_ref (match_operand 3 "" ""))
3826 (pc)))]
9abe3ad4 3827 "TARGET_HPUX"
74f4459c 3828 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3829
9abe3ad4 3830
ac445222 3831(define_insn "*cmpsi_normal"
33c8f6d1 3832 [(set (match_operand:BI 0 "register_operand" "=c")
3833 (match_operator:BI 1 "normal_comparison_operator"
f087d65d 3834 [(match_operand:SI 2 "gr_register_operand" "r")
3835 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
ac445222 3836 ""
3837 "cmp4.%C1 %0, %I0 = %3, %2"
bf6ff2f6 3838 [(set_attr "itanium_class" "icmp")])
ac445222 3839
836ac237 3840;; We use %r3 because it is possible for us to match a 0, and two of the
3841;; unsigned comparisons don't accept immediate operands of zero.
3842
ac445222 3843(define_insn "*cmpsi_adjusted"
33c8f6d1 3844 [(set (match_operand:BI 0 "register_operand" "=c")
3845 (match_operator:BI 1 "adjusted_comparison_operator"
f087d65d 3846 [(match_operand:SI 2 "gr_register_operand" "r")
3847 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
ac445222 3848 ""
836ac237 3849 "cmp4.%C1 %0, %I0 = %r3, %2"
bf6ff2f6 3850 [(set_attr "itanium_class" "icmp")])
ac445222 3851
3852(define_insn "*cmpdi_normal"
33c8f6d1 3853 [(set (match_operand:BI 0 "register_operand" "=c")
3854 (match_operator:BI 1 "normal_comparison_operator"
3855 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
f087d65d 3856 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
ac445222 3857 ""
33c8f6d1 3858 "cmp.%C1 %0, %I0 = %3, %r2"
bf6ff2f6 3859 [(set_attr "itanium_class" "icmp")])
ac445222 3860
836ac237 3861;; We use %r3 because it is possible for us to match a 0, and two of the
3862;; unsigned comparisons don't accept immediate operands of zero.
3863
ac445222 3864(define_insn "*cmpdi_adjusted"
33c8f6d1 3865 [(set (match_operand:BI 0 "register_operand" "=c")
3866 (match_operator:BI 1 "adjusted_comparison_operator"
f087d65d 3867 [(match_operand:DI 2 "gr_register_operand" "r")
3868 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
ac445222 3869 ""
836ac237 3870 "cmp.%C1 %0, %I0 = %r3, %2"
bf6ff2f6 3871 [(set_attr "itanium_class" "icmp")])
ac445222 3872
3873(define_insn "*cmpsf_internal"
33c8f6d1 3874 [(set (match_operand:BI 0 "register_operand" "=c")
3875 (match_operator:BI 1 "comparison_operator"
f087d65d 3876 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
3877 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
ac445222 3878 ""
3879 "fcmp.%D1 %0, %I0 = %F2, %F3"
bf6ff2f6 3880 [(set_attr "itanium_class" "fcmp")])
ac445222 3881
3882(define_insn "*cmpdf_internal"
33c8f6d1 3883 [(set (match_operand:BI 0 "register_operand" "=c")
3884 (match_operator:BI 1 "comparison_operator"
f087d65d 3885 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
3886 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
ac445222 3887 ""
3888 "fcmp.%D1 %0, %I0 = %F2, %F3"
bf6ff2f6 3889 [(set_attr "itanium_class" "fcmp")])
ac445222 3890
b8bc42e9 3891(define_insn "*cmpxf_internal"
33c8f6d1 3892 [(set (match_operand:BI 0 "register_operand" "=c")
3893 (match_operator:BI 1 "comparison_operator"
b8bc42e9 3894 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3895 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
3896 ""
d5f10acf 3897 "fcmp.%D1 %0, %I0 = %F2, %F3"
bf6ff2f6 3898 [(set_attr "itanium_class" "fcmp")])
d5f10acf 3899
ac445222 3900;; ??? Can this pattern be generated?
3901
3902(define_insn "*bit_zero"
33c8f6d1 3903 [(set (match_operand:BI 0 "register_operand" "=c")
3904 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 3905 (const_int 1)
986fafd5 3906 (match_operand:DI 2 "shift_count_operand" "M"))
ac445222 3907 (const_int 0)))]
3908 ""
3909 "tbit.z %0, %I0 = %1, %2"
bf6ff2f6 3910 [(set_attr "itanium_class" "tbit")])
ac445222 3911
3912(define_insn "*bit_one"
33c8f6d1 3913 [(set (match_operand:BI 0 "register_operand" "=c")
3914 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
ac445222 3915 (const_int 1)
986fafd5 3916 (match_operand:DI 2 "shift_count_operand" "M"))
ac445222 3917 (const_int 0)))]
3918 ""
3919 "tbit.nz %0, %I0 = %1, %2"
bf6ff2f6 3920 [(set_attr "itanium_class" "tbit")])
ac445222 3921\f
3922;; ::::::::::::::::::::
3923;; ::
3924;; :: Branches
3925;; ::
3926;; ::::::::::::::::::::
3927
341cffb9 3928(define_insn "*br_true"
ac445222 3929 [(set (pc)
341cffb9 3930 (if_then_else (match_operator 0 "predicate_operator"
33c8f6d1 3931 [(match_operand:BI 1 "register_operand" "c")
341cffb9 3932 (const_int 0)])
3933 (label_ref (match_operand 2 "" ""))
ac445222 3934 (pc)))]
3935 ""
464c9e08 3936 "(%J0) br.cond%+ %l2"
bf6ff2f6 3937 [(set_attr "itanium_class" "br")
945c34bb 3938 (set_attr "predicable" "no")])
ac445222 3939
341cffb9 3940(define_insn "*br_false"
ac445222 3941 [(set (pc)
341cffb9 3942 (if_then_else (match_operator 0 "predicate_operator"
33c8f6d1 3943 [(match_operand:BI 1 "register_operand" "c")
341cffb9 3944 (const_int 0)])
ac445222 3945 (pc)
341cffb9 3946 (label_ref (match_operand 2 "" ""))))]
ac445222 3947 ""
464c9e08 3948 "(%j0) br.cond%+ %l2"
bf6ff2f6 3949 [(set_attr "itanium_class" "br")
945c34bb 3950 (set_attr "predicable" "no")])
ac445222 3951\f
3952;; ::::::::::::::::::::
3953;; ::
9641f63c 3954;; :: Counted loop operations
3955;; ::
3956;; ::::::::::::::::::::
3957
3958(define_expand "doloop_end"
3959 [(use (match_operand 0 "" "")) ; loop pseudo
3960 (use (match_operand 1 "" "")) ; iterations; zero if unknown
3961 (use (match_operand 2 "" "")) ; max iterations
3962 (use (match_operand 3 "" "")) ; loop level
bbdfcf34 3963 (use (match_operand 4 "" "")) ; label
3964 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
9641f63c 3965 ""
9641f63c 3966{
3967 /* Only use cloop on innermost loops. */
3968 if (INTVAL (operands[3]) > 1)
3969 FAIL;
3970 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
3971 operands[4]));
3972 DONE;
d2ba5713 3973})
9641f63c 3974
3975(define_insn "doloop_end_internal"
3976 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
3977 (const_int 0))
3978 (label_ref (match_operand 1 "" ""))
3979 (pc)))
3980 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
56fb49bf 3981 (plus:DI (match_dup 0) (const_int -1))
3982 (match_dup 0)))]
9641f63c 3983 ""
3984 "br.cloop.sptk.few %l1"
bf6ff2f6 3985 [(set_attr "itanium_class" "br")
9641f63c 3986 (set_attr "predicable" "no")])
3987\f
3988;; ::::::::::::::::::::
3989;; ::
ac445222 3990;; :: Set flag operations
3991;; ::
3992;; ::::::::::::::::::::
3993
74f4459c 3994(define_expand "cstorebi4"
3995 [(set (match_operand:DI 0 "gr_register_operand" "")
3996 (match_operator:DI 1 "ia64_cbranch_operator"
3997 [(match_operand:BI 2 "register_operand" "")
3998 (match_operand:BI 3 "const_int_operand" "")]))]
ac445222 3999 ""
7eae7954 4000 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4001
74f4459c 4002(define_expand "cstoresi4"
4003 [(set (match_operand:DI 0 "gr_register_operand" "")
4004 (match_operator:DI 1 "ia64_cbranch_operator"
4005 [(match_operand:SI 2 "gr_register_operand" "")
4006 (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
ac445222 4007 ""
74f4459c 4008 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4009
74f4459c 4010(define_expand "cstoredi4"
4011 [(set (match_operand:DI 0 "gr_register_operand" "")
4012 (match_operator:DI 1 "ia64_cbranch_operator"
4013 [(match_operand:DI 2 "gr_register_operand" "")
4014 (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
ac445222 4015 ""
74f4459c 4016 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4017
74f4459c 4018(define_expand "cstoresf4"
4019 [(set (match_operand:DI 0 "gr_register_operand" "")
4020 (match_operator:DI 1 "ia64_cbranch_operator"
4021 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "")
4022 (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))]
ac445222 4023 ""
74f4459c 4024 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4025
74f4459c 4026(define_expand "cstoredf4"
4027 [(set (match_operand:DI 0 "gr_register_operand" "")
4028 (match_operator:DI 1 "ia64_cbranch_operator"
4029 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "")
4030 (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))]
ac445222 4031 ""
74f4459c 4032 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4033
74f4459c 4034(define_expand "cstorexf4"
4035 [(set (match_operand:DI 0 "gr_register_operand" "")
4036 (match_operator:DI 1 "ia64_cbranch_operator"
4037 [(match_operand:XF 2 "xfreg_or_fp01_operand" "")
4038 (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))]
ac445222 4039 ""
74f4459c 4040 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
ac445222 4041
74f4459c 4042(define_expand "cstoretf4"
4043 [(set (match_operand:DI 0 "gr_register_operand" "")
4044 (match_operator:DI 1 "ia64_cbranch_operator"
4045 [(match_operand:TF 2 "gr_register_operand" "")
4046 (match_operand:TF 3 "gr_register_operand" "")]))]
4047 "TARGET_HPUX"
4048 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
0aa63c5e 4049
ac445222 4050;; Don't allow memory as destination here, because cmov/cmov/st is more
4051;; efficient than mov/mov/cst/cst.
4052
f087d65d 4053(define_insn_and_split "*sne_internal"
4054 [(set (match_operand:DI 0 "gr_register_operand" "=r")
33c8f6d1 4055 (ne:DI (match_operand:BI 1 "register_operand" "c")
ac445222 4056 (const_int 0)))]
4057 ""
4058 "#"
ac445222 4059 "reload_completed"
33c8f6d1 4060 [(cond_exec (ne (match_dup 1) (const_int 0))
4061 (set (match_dup 0) (const_int 1)))
4062 (cond_exec (eq (match_dup 1) (const_int 0))
4063 (set (match_dup 0) (const_int 0)))]
f087d65d 4064 ""
bf6ff2f6 4065 [(set_attr "itanium_class" "unknown")])
ac445222 4066
f087d65d 4067(define_insn_and_split "*seq_internal"
4068 [(set (match_operand:DI 0 "gr_register_operand" "=r")
33c8f6d1 4069 (eq:DI (match_operand:BI 1 "register_operand" "c")
ac445222 4070 (const_int 0)))]
4071 ""
4072 "#"
ac445222 4073 "reload_completed"
33c8f6d1 4074 [(cond_exec (ne (match_dup 1) (const_int 0))
4075 (set (match_dup 0) (const_int 0)))
4076 (cond_exec (eq (match_dup 1) (const_int 0))
4077 (set (match_dup 0) (const_int 1)))]
f087d65d 4078 ""
bf6ff2f6 4079 [(set_attr "itanium_class" "unknown")])
ac445222 4080\f
4081;; ::::::::::::::::::::
4082;; ::
4083;; :: Conditional move instructions.
4084;; ::
4085;; ::::::::::::::::::::
4086
4087;; ??? Add movXXcc patterns?
4088
ac445222 4089;;
4090;; DImode if_then_else patterns.
4091;;
4092
479da38b 4093(define_insn "*cmovdi_internal"
81ef4261 4094 [(set (match_operand:DI 0 "not_postinc_destination_operand"
aef29c61 4095 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
945c34bb 4096 (if_then_else:DI
33c8f6d1 4097 (match_operator 4 "predicate_operator"
4098 [(match_operand:BI 1 "register_operand"
aef29c61 4099 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
945c34bb 4100 (const_int 0)])
81ef4261 4101 (match_operand:DI 2 "not_postinc_move_operand"
aef29c61 4102 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
81ef4261 4103 (match_operand:DI 3 "not_postinc_move_operand"
aef29c61 4104 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
8b0dd03f 4105 "ia64_move_ok (operands[0], operands[2])
33c8f6d1 4106 && ia64_move_ok (operands[0], operands[3])"
c5c17bca 4107 { gcc_unreachable (); }
479da38b 4108 [(set_attr "predicable" "no")])
4109
4110(define_split
81ef4261 4111 [(set (match_operand 0 "not_postinc_destination_operand" "")
479da38b 4112 (if_then_else
33c8f6d1 4113 (match_operator 4 "predicate_operator"
4114 [(match_operand:BI 1 "register_operand" "")
479da38b 4115 (const_int 0)])
81ef4261 4116 (match_operand 2 "not_postinc_move_operand" "")
4117 (match_operand 3 "not_postinc_move_operand" "")))]
9b06caff 4118 "reload_completed"
4119 [(const_int 0)]
945c34bb 4120{
58b90768 4121 bool emitted_something = false;
4122 rtx dest = operands[0];
4123 rtx srct = operands[2];
4124 rtx srcf = operands[3];
4125 rtx cond = operands[4];
31d3e01c 4126
58b90768 4127 if (! rtx_equal_p (dest, srct))
945c34bb 4128 {
58b90768 4129 ia64_emit_cond_move (dest, srct, cond);
4130 emitted_something = true;
945c34bb 4131 }
58b90768 4132 if (! rtx_equal_p (dest, srcf))
9b06caff 4133 {
58b90768 4134 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
4135 VOIDmode, operands[1], const0_rtx);
4136 ia64_emit_cond_move (dest, srcf, cond);
4137 emitted_something = true;
9b06caff 4138 }
31d3e01c 4139 if (! emitted_something)
e6d15273 4140 emit_note (NOTE_INSN_DELETED);
9b06caff 4141 DONE;
d2ba5713 4142})
ac445222 4143
4144;; Absolute value pattern.
4145
4146(define_insn "*absdi2_internal"
f087d65d 4147 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
945c34bb 4148 (if_then_else:DI
33c8f6d1 4149 (match_operator 4 "predicate_operator"
4150 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4151 (const_int 0)])
f087d65d 4152 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4153 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
ac445222 4154 ""
945c34bb 4155 "#"
bf6ff2f6 4156 [(set_attr "itanium_class" "ialu,unknown")
9b06caff 4157 (set_attr "predicable" "no")])
ac445222 4158
4159(define_split
4160 [(set (match_operand:DI 0 "register_operand" "")
945c34bb 4161 (if_then_else:DI
33c8f6d1 4162 (match_operator 4 "predicate_operator"
4163 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4164 (const_int 0)])
f087d65d 4165 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4166 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
945c34bb 4167 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4168 [(cond_exec
4169 (match_dup 4)
4170 (set (match_dup 0)
4171 (neg:DI (match_dup 2))))]
ac445222 4172 "")
4173
945c34bb 4174(define_split
4175 [(set (match_operand:DI 0 "register_operand" "")
4176 (if_then_else:DI
33c8f6d1 4177 (match_operator 4 "predicate_operator"
4178 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4179 (const_int 0)])
f087d65d 4180 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4181 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
945c34bb 4182 "reload_completed"
4183 [(cond_exec
4184 (match_dup 4)
4185 (set (match_dup 0) (neg:DI (match_dup 2))))
4186 (cond_exec
4187 (match_dup 5)
4188 (set (match_dup 0) (match_dup 3)))]
945c34bb 4189{
4190 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
33c8f6d1 4191 VOIDmode, operands[1], const0_rtx);
d2ba5713 4192})
ac445222 4193
4194;;
4195;; SImode if_then_else patterns.
4196;;
4197
479da38b 4198(define_insn "*cmovsi_internal"
81ef4261 4199 [(set (match_operand:SI 0 "not_postinc_destination_operand"
4200 "=r,m,*f,r,m,*f,r,m,*f")
945c34bb 4201 (if_then_else:SI
33c8f6d1 4202 (match_operator 4 "predicate_operator"
4203 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
945c34bb 4204 (const_int 0)])
81ef4261 4205 (match_operand:SI 2 "not_postinc_move_operand"
9b06caff 4206 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
81ef4261 4207 (match_operand:SI 3 "not_postinc_move_operand"
9b06caff 4208 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
8b0dd03f 4209 "ia64_move_ok (operands[0], operands[2])
33c8f6d1 4210 && ia64_move_ok (operands[0], operands[3])"
c5c17bca 4211 { gcc_unreachable (); }
9b06caff 4212 [(set_attr "predicable" "no")])
ac445222 4213
4214(define_insn "*abssi2_internal"
f087d65d 4215 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
945c34bb 4216 (if_then_else:SI
33c8f6d1 4217 (match_operator 4 "predicate_operator"
4218 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4219 (const_int 0)])
f087d65d 4220 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4221 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
ac445222 4222 ""
945c34bb 4223 "#"
bf6ff2f6 4224 [(set_attr "itanium_class" "ialu,unknown")
9b06caff 4225 (set_attr "predicable" "no")])
ac445222 4226
4227(define_split
4228 [(set (match_operand:SI 0 "register_operand" "")
945c34bb 4229 (if_then_else:SI
33c8f6d1 4230 (match_operator 4 "predicate_operator"
4231 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4232 (const_int 0)])
f087d65d 4233 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4234 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
945c34bb 4235 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4236 [(cond_exec
4237 (match_dup 4)
4238 (set (match_dup 0)
4239 (neg:SI (match_dup 2))))]
ac445222 4240 "")
4241
945c34bb 4242(define_split
4243 [(set (match_operand:SI 0 "register_operand" "")
4244 (if_then_else:SI
33c8f6d1 4245 (match_operator 4 "predicate_operator"
4246 [(match_operand:BI 1 "register_operand" "c,c")
945c34bb 4247 (const_int 0)])
f087d65d 4248 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4249 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
945c34bb 4250 "reload_completed"
4251 [(cond_exec
4252 (match_dup 4)
4253 (set (match_dup 0) (neg:SI (match_dup 2))))
4254 (cond_exec
4255 (match_dup 5)
4256 (set (match_dup 0) (match_dup 3)))]
945c34bb 4257{
4258 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
33c8f6d1 4259 VOIDmode, operands[1], const0_rtx);
d2ba5713 4260})
945c34bb 4261
20956cd7 4262(define_insn_and_split "*cond_opsi2_internal"
a4b30b9e 4263 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4264 (match_operator:SI 5 "condop_operator"
4265 [(if_then_else:SI
4266 (match_operator 6 "predicate_operator"
4267 [(match_operand:BI 1 "register_operand" "c")
4268 (const_int 0)])
4269 (match_operand:SI 2 "gr_register_operand" "r")
4270 (match_operand:SI 3 "gr_register_operand" "r"))
4271 (match_operand:SI 4 "gr_register_operand" "r")]))]
4272 ""
4273 "#"
a4b30b9e 4274 "reload_completed"
4275 [(cond_exec
4276 (match_dup 6)
4277 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
4278 (cond_exec
4279 (match_dup 7)
4280 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
a4b30b9e 4281{
4282 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4283 VOIDmode, operands[1], const0_rtx);
d2ba5713 4284}
20956cd7 4285 [(set_attr "itanium_class" "ialu")
4286 (set_attr "predicable" "no")])
4287
a4b30b9e 4288
20956cd7 4289(define_insn_and_split "*cond_opsi2_internal_b"
a4b30b9e 4290 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4291 (match_operator:SI 5 "condop_operator"
4292 [(match_operand:SI 4 "gr_register_operand" "r")
4293 (if_then_else:SI
4294 (match_operator 6 "predicate_operator"
4295 [(match_operand:BI 1 "register_operand" "c")
4296 (const_int 0)])
4297 (match_operand:SI 2 "gr_register_operand" "r")
4298 (match_operand:SI 3 "gr_register_operand" "r"))]))]
4299 ""
4300 "#"
a4b30b9e 4301 "reload_completed"
4302 [(cond_exec
4303 (match_dup 6)
4304 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
4305 (cond_exec
4306 (match_dup 7)
4307 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
a4b30b9e 4308{
4309 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4310 VOIDmode, operands[1], const0_rtx);
d2ba5713 4311}
20956cd7 4312 [(set_attr "itanium_class" "ialu")
4313 (set_attr "predicable" "no")])
a4b30b9e 4314
ac445222 4315\f
4316;; ::::::::::::::::::::
4317;; ::
4318;; :: Call and branch instructions
4319;; ::
4320;; ::::::::::::::::::::
4321
4322;; Subroutine call instruction returning no value. Operand 0 is the function
4323;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4324;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4325;; registers used as operands.
4326
4327;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4328;; is supplied for the sake of some RISC machines which need to put this
4329;; information into the assembler code; they can put it in the RTL instead of
4330;; operand 1.
4331
4332(define_expand "call"
4333 [(use (match_operand:DI 0 "" ""))
4334 (use (match_operand 1 "" ""))
4335 (use (match_operand 2 "" ""))
4336 (use (match_operand 3 "" ""))]
4337 ""
ac445222 4338{
e13693ec 4339 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
ac445222 4340 DONE;
d2ba5713 4341})
ac445222 4342
46ebdd6b 4343(define_expand "sibcall"
4344 [(use (match_operand:DI 0 "" ""))
4345 (use (match_operand 1 "" ""))
4346 (use (match_operand 2 "" ""))
4347 (use (match_operand 3 "" ""))]
ac445222 4348 ""
ac445222 4349{
e13693ec 4350 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
46ebdd6b 4351 DONE;
d2ba5713 4352})
ac445222 4353
ac445222 4354;; Subroutine call instruction returning a value. Operand 0 is the hard
46ebdd6b 4355;; register in which the value is returned. There are three more operands,
4356;; the same as the three operands of the `call' instruction (but with numbers
ac445222 4357;; increased by one).
46ebdd6b 4358;;
ac445222 4359;; Subroutines that return `BLKmode' objects use the `call' insn.
4360
4361(define_expand "call_value"
4362 [(use (match_operand 0 "" ""))
4363 (use (match_operand:DI 1 "" ""))
4364 (use (match_operand 2 "" ""))
4365 (use (match_operand 3 "" ""))
4366 (use (match_operand 4 "" ""))]
4367 ""
ac445222 4368{
e13693ec 4369 ia64_expand_call (operands[0], operands[1], operands[3], false);
ac445222 4370 DONE;
d2ba5713 4371})
ac445222 4372
46ebdd6b 4373(define_expand "sibcall_value"
4374 [(use (match_operand 0 "" ""))
4375 (use (match_operand:DI 1 "" ""))
4376 (use (match_operand 2 "" ""))
4377 (use (match_operand 3 "" ""))
4378 (use (match_operand 4 "" ""))]
ac445222 4379 ""
ac445222 4380{
e13693ec 4381 ia64_expand_call (operands[0], operands[1], operands[3], true);
46ebdd6b 4382 DONE;
d2ba5713 4383})
ac445222 4384
ac445222 4385;; Call subroutine returning any type.
4386
4387(define_expand "untyped_call"
4388 [(parallel [(call (match_operand 0 "" "")
4389 (const_int 0))
4390 (match_operand 1 "" "")
4391 (match_operand 2 "" "")])]
4392 ""
ac445222 4393{
4394 int i;
4395
4396 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4397
4398 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4399 {
4400 rtx set = XVECEXP (operands[2], 0, i);
4401 emit_move_insn (SET_DEST (set), SET_SRC (set));
4402 }
4403
4404 /* The optimizer does not know that the call sets the function value
4405 registers we stored in the result block. We avoid problems by
4406 claiming that all hard registers are used and clobbered at this
4407 point. */
4408 emit_insn (gen_blockage ());
4409
4410 DONE;
d2ba5713 4411})
ac445222 4412
e13693ec 4413(define_insn "call_nogp"
e4f53c6a 4414 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s"))
e13693ec 4415 (const_int 0))
4416 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
46ebdd6b 4417 ""
e13693ec 4418 "br.call%+.many %1 = %0"
bf6ff2f6 4419 [(set_attr "itanium_class" "br,scall")])
46ebdd6b 4420
e13693ec 4421(define_insn "call_value_nogp"
f73be2c0 4422 [(set (match_operand 0 "" "=X,X")
e4f53c6a 4423 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,s"))
e13693ec 4424 (const_int 0)))
4425 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
46ebdd6b 4426 ""
e13693ec 4427 "br.call%+.many %2 = %1"
bf6ff2f6 4428 [(set_attr "itanium_class" "br,scall")])
46ebdd6b 4429
e13693ec 4430(define_insn "sibcall_nogp"
e4f53c6a 4431 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s"))
e13693ec 4432 (const_int 0))]
46ebdd6b 4433 ""
4434 "br%+.many %0"
bf6ff2f6 4435 [(set_attr "itanium_class" "br,scall")])
46ebdd6b 4436
e13693ec 4437(define_insn "call_gp"
e4f53c6a 4438 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s"))
e13693ec 4439 (const_int 1))
4440 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
4441 (clobber (match_scratch:DI 2 "=&r,X"))
4442 (clobber (match_scratch:DI 3 "=b,X"))]
46ebdd6b 4443 ""
e13693ec 4444 "#"
bf6ff2f6 4445 [(set_attr "itanium_class" "br,scall")])
46ebdd6b 4446
e13693ec 4447;; Irritatingly, we don't have access to INSN within the split body.
4448;; See commentary in ia64_split_call as to why these aren't peep2.
4449(define_split
4450 [(call (mem (match_operand 0 "call_operand" ""))
4451 (const_int 1))
4452 (clobber (match_operand:DI 1 "register_operand" ""))
4453 (clobber (match_scratch:DI 2 ""))
4454 (clobber (match_scratch:DI 3 ""))]
4455 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4456 [(const_int 0)]
4457{
4458 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4459 operands[3], true, false);
4460 DONE;
4461})
4462
4463(define_split
4464 [(call (mem (match_operand 0 "call_operand" ""))
4465 (const_int 1))
4466 (clobber (match_operand:DI 1 "register_operand" ""))
4467 (clobber (match_scratch:DI 2 ""))
4468 (clobber (match_scratch:DI 3 ""))]
4469 "reload_completed"
4470 [(const_int 0)]
4471{
4472 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4473 operands[3], false, false);
4474 DONE;
4475})
4476
4477(define_insn "call_value_gp"
f73be2c0 4478 [(set (match_operand 0 "" "=X,X")
e4f53c6a 4479 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,s"))
e13693ec 4480 (const_int 1)))
4481 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
4482 (clobber (match_scratch:DI 3 "=&r,X"))
4483 (clobber (match_scratch:DI 4 "=b,X"))]
46ebdd6b 4484 ""
e13693ec 4485 "#"
bf6ff2f6 4486 [(set_attr "itanium_class" "br,scall")])
46ebdd6b 4487
e13693ec 4488(define_split
4489 [(set (match_operand 0 "" "")
4490 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4491 (const_int 1)))
4492 (clobber (match_operand:DI 2 "register_operand" ""))
4493 (clobber (match_scratch:DI 3 ""))
4494 (clobber (match_scratch:DI 4 ""))]
4495 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4496 [(const_int 0)]
4497{
4498 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4499 operands[4], true, false);
4500 DONE;
4501})
4502
4503(define_split
4504 [(set (match_operand 0 "" "")
4505 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4506 (const_int 1)))
4507 (clobber (match_operand:DI 2 "register_operand" ""))
4508 (clobber (match_scratch:DI 3 ""))
4509 (clobber (match_scratch:DI 4 ""))]
4510 "reload_completed"
4511 [(const_int 0)]
4512{
4513 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4514 operands[4], false, false);
4515 DONE;
4516})
4517
4518(define_insn_and_split "sibcall_gp"
e4f53c6a 4519 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s"))
e13693ec 4520 (const_int 1))
4521 (clobber (match_scratch:DI 1 "=&r,X"))
4522 (clobber (match_scratch:DI 2 "=b,X"))]
46ebdd6b 4523 ""
e13693ec 4524 "#"
4525 "reload_completed"
4526 [(const_int 0)]
4527{
4528 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
4529 operands[2], true, true);
4530 DONE;
4531}
bf6ff2f6 4532 [(set_attr "itanium_class" "br")])
46ebdd6b 4533
ac445222 4534(define_insn "return_internal"
4535 [(return)
4536 (use (match_operand:DI 0 "register_operand" "b"))]
4537 ""
4538 "br.ret.sptk.many %0"
bf6ff2f6 4539 [(set_attr "itanium_class" "br")])
ac445222 4540
4541(define_insn "return"
4542 [(return)]
4543 "ia64_direct_return ()"
4544 "br.ret.sptk.many rp"
bf6ff2f6 4545 [(set_attr "itanium_class" "br")])
ac445222 4546
341cffb9 4547(define_insn "*return_true"
ac445222 4548 [(set (pc)
341cffb9 4549 (if_then_else (match_operator 0 "predicate_operator"
33c8f6d1 4550 [(match_operand:BI 1 "register_operand" "c")
341cffb9 4551 (const_int 0)])
ac445222 4552 (return)
4553 (pc)))]
4554 "ia64_direct_return ()"
08f8478f 4555 "(%J0) br.ret%+.many rp"
bf6ff2f6 4556 [(set_attr "itanium_class" "br")
945c34bb 4557 (set_attr "predicable" "no")])
ac445222 4558
341cffb9 4559(define_insn "*return_false"
ac445222 4560 [(set (pc)
341cffb9 4561 (if_then_else (match_operator 0 "predicate_operator"
33c8f6d1 4562 [(match_operand:BI 1 "register_operand" "c")
341cffb9 4563 (const_int 0)])
ac445222 4564 (pc)
4565 (return)))]
4566 "ia64_direct_return ()"
08f8478f 4567 "(%j0) br.ret%+.many rp"
bf6ff2f6 4568 [(set_attr "itanium_class" "br")
945c34bb 4569 (set_attr "predicable" "no")])
ac445222 4570
4571(define_insn "jump"
4572 [(set (pc) (label_ref (match_operand 0 "" "")))]
4573 ""
4574 "br %l0"
bf6ff2f6 4575 [(set_attr "itanium_class" "br")])
ac445222 4576
4577(define_insn "indirect_jump"
4578 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4579 ""
4580 "br %0"
bf6ff2f6 4581 [(set_attr "itanium_class" "br")])
ac445222 4582
4583(define_expand "tablejump"
a2295d74 4584 [(parallel [(set (pc) (match_operand 0 "memory_operand" ""))
feb8ef57 4585 (use (label_ref (match_operand 1 "" "")))])]
ac445222 4586 ""
ac445222 4587{
feb8ef57 4588 rtx op0 = operands[0];
4589 rtx addr;
4590
4591 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
4592 element into a register without bothering to see whether that
4593 is necessary given the operand predicate. Check for MEM just
4594 in case someone fixes this. */
4595 if (GET_CODE (op0) == MEM)
4596 addr = XEXP (op0, 0);
4597 else
4598 {
4599 /* Otherwise, cheat and guess that the previous insn in the
4600 stream was the memory load. Grab the address from that.
4601 Note we have to momentarily pop out of the sequence started
4602 by the insn-emit wrapper in order to grab the last insn. */
4603 rtx last, set;
4604
4605 end_sequence ();
4606 last = get_last_insn ();
4607 start_sequence ();
4608 set = single_set (last);
4609
c5c17bca 4610 gcc_assert (rtx_equal_p (SET_DEST (set), op0)
4611 && GET_CODE (SET_SRC (set)) == MEM);
feb8ef57 4612 addr = XEXP (SET_SRC (set), 0);
c5c17bca 4613 gcc_assert (!rtx_equal_p (addr, op0));
feb8ef57 4614 }
ac445222 4615
feb8ef57 4616 /* Jump table elements are stored pc-relative. That is, a displacement
4617 from the entry to the label. Thus to convert to an absolute address
4618 we add the address of the memory from which the value is loaded. */
4619 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
a2295d74 4620 NULL_RTX, 0, OPTAB_DIRECT);
feb8ef57 4621})
ac445222 4622
feb8ef57 4623(define_insn "*tablejump_internal"
ac445222 4624 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4625 (use (label_ref (match_operand 1 "" "")))]
4626 ""
4627 "br %0"
bf6ff2f6 4628 [(set_attr "itanium_class" "br")])
ac445222 4629
4630\f
4631;; ::::::::::::::::::::
4632;; ::
4633;; :: Prologue and Epilogue instructions
4634;; ::
4635;; ::::::::::::::::::::
4636
4637(define_expand "prologue"
4638 [(const_int 1)]
4639 ""
ac445222 4640{
4641 ia64_expand_prologue ();
4642 DONE;
d2ba5713 4643})
ac445222 4644
4645(define_expand "epilogue"
46ebdd6b 4646 [(return)]
4647 ""
46ebdd6b 4648{
4649 ia64_expand_epilogue (0);
4650 DONE;
d2ba5713 4651})
46ebdd6b 4652
4653(define_expand "sibcall_epilogue"
4654 [(return)]
ac445222 4655 ""
ac445222 4656{
46ebdd6b 4657 ia64_expand_epilogue (1);
ac445222 4658 DONE;
d2ba5713 4659})
ac445222 4660
4661;; This prevents the scheduler from moving the SP decrement past FP-relative
4662;; stack accesses. This is the same as adddi3 plus the extra set.
4663
4664(define_insn "prologue_allocate_stack"
4665 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4666 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
f087d65d 4667 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
b8536bfb 4668 (set (match_operand:DI 3 "register_operand" "+r,r,r")
ac445222 4669 (match_dup 3))]
4670 ""
4671 "@
d2ba5713 4672 add %0 = %1, %2
4673 adds %0 = %2, %1
4674 addl %0 = %2, %1"
bf6ff2f6 4675 [(set_attr "itanium_class" "ialu")])
ac445222 4676
4677;; This prevents the scheduler from moving the SP restore past FP-relative
4678;; stack accesses. This is similar to movdi plus the extra set.
4679
4680(define_insn "epilogue_deallocate_stack"
4681 [(set (match_operand:DI 0 "register_operand" "=r")
4682 (match_operand:DI 1 "register_operand" "+r"))
4683 (set (match_dup 1) (match_dup 1))]
4684 ""
4685 "mov %0 = %1"
bf6ff2f6 4686 [(set_attr "itanium_class" "ialu")])
ac445222 4687
d2ba5713 4688;; As USE insns aren't meaningful after reload, this is used instead
4689;; to prevent deleting instructions setting registers for EH handling
4690(define_insn "prologue_use"
4691 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
4692 UNSPEC_PROLOGUE_USE)]
4693 ""
4694 ""
4695 [(set_attr "itanium_class" "ignore")
2b71c761 4696 (set_attr "predicable" "no")
4697 (set_attr "empty" "yes")])
d2ba5713 4698
ac445222 4699;; Allocate a new register frame.
4700
4701(define_insn "alloc"
4702 [(set (match_operand:DI 0 "register_operand" "=r")
e2b723ca 4703 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
ac445222 4704 (use (match_operand:DI 1 "const_int_operand" "i"))
4705 (use (match_operand:DI 2 "const_int_operand" "i"))
4706 (use (match_operand:DI 3 "const_int_operand" "i"))
4707 (use (match_operand:DI 4 "const_int_operand" "i"))]
4708 ""
4709 "alloc %0 = ar.pfs, %1, %2, %3, %4"
bf6ff2f6 4710 [(set_attr "itanium_class" "syst_m0")
5f121199 4711 (set_attr "predicable" "no")
4712 (set_attr "first_insn" "yes")])
ac445222 4713
cac50a9f 4714;; Modifies ar.unat
4715(define_expand "gr_spill"
de4f4740 4716 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
4717 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
e2b723ca 4718 (match_operand:DI 2 "const_int_operand" "")]
4719 UNSPEC_GR_SPILL))
de4f4740 4720 (clobber (match_dup 3))])]
cac50a9f 4721 ""
de4f4740 4722 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
cac50a9f 4723
de4f4740 4724(define_insn "gr_spill_internal"
0d442ac4 4725 [(set (match_operand:DI 0 "destination_operand" "=m")
de4f4740 4726 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
e2b723ca 4727 (match_operand:DI 2 "const_int_operand" "")]
4728 UNSPEC_GR_SPILL))
de4f4740 4729 (clobber (match_operand:DI 3 "register_operand" ""))]
ac445222 4730 ""
a0bb0d20 4731{
d2ba5713 4732 /* Note that we use a C output pattern here to avoid the predicate
4733 being automatically added before the .mem.offset directive. */
4734 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
4735}
bf6ff2f6 4736 [(set_attr "itanium_class" "st")])
ac445222 4737
cac50a9f 4738;; Reads ar.unat
4739(define_expand "gr_restore"
de4f4740 4740 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
4741 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
e2b723ca 4742 (match_operand:DI 2 "const_int_operand" "")]
4743 UNSPEC_GR_RESTORE))
de4f4740 4744 (use (match_dup 3))])]
cac50a9f 4745 ""
de4f4740 4746 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
cac50a9f 4747
de4f4740 4748(define_insn "gr_restore_internal"
ac445222 4749 [(set (match_operand:DI 0 "register_operand" "=r")
de4f4740 4750 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
e2b723ca 4751 (match_operand:DI 2 "const_int_operand" "")]
4752 UNSPEC_GR_RESTORE))
de4f4740 4753 (use (match_operand:DI 3 "register_operand" ""))]
ac445222 4754 ""
d2ba5713 4755 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
bf6ff2f6 4756 [(set_attr "itanium_class" "ld")])
ac445222 4757
4758(define_insn "fr_spill"
0d442ac4 4759 [(set (match_operand:XF 0 "destination_operand" "=m")
b8bc42e9 4760 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
e2b723ca 4761 UNSPEC_FR_SPILL))]
ac445222 4762 ""
4763 "stf.spill %0 = %1%P0"
bf6ff2f6 4764 [(set_attr "itanium_class" "stf")])
ac445222 4765
4766(define_insn "fr_restore"
b8bc42e9 4767 [(set (match_operand:XF 0 "register_operand" "=f")
4768 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
e2b723ca 4769 UNSPEC_FR_RESTORE))]
ac445222 4770 ""
4771 "ldf.fill %0 = %1%P1"
bf6ff2f6 4772 [(set_attr "itanium_class" "fld")])
ac445222 4773
f8b4f867 4774;; ??? The explicit stop is not ideal. It would be better if
4775;; rtx_needs_barrier took care of this, but this is something that can be
4776;; fixed later. This avoids an RSE DV.
4777
7c2f467a 4778(define_insn "bsp_value"
4779 [(set (match_operand:DI 0 "register_operand" "=r")
e2b723ca 4780 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
7c2f467a 4781 ""
3823bd9c 4782 "*
4783{
4784 return \";;\;%,mov %0 = ar.bsp\";
4785}"
bf6ff2f6 4786 [(set_attr "itanium_class" "frar_i")])
7c2f467a 4787
4788(define_insn "set_bsp"
e2b723ca 4789 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
4790 UNSPECV_SET_BSP)]
7c2f467a 4791 ""
d2ba5713 4792 "flushrs
4793 mov r19=ar.rsc
4794 ;;
4795 and r19=0x1c,r19
4796 ;;
4797 mov ar.rsc=r19
4798 ;;
4799 mov ar.bspstore=%0
4800 ;;
4801 or r19=0x3,r19
4802 ;;
4803 loadrs
4804 invala
4805 ;;
4806 mov ar.rsc=r19"
bf6ff2f6 4807 [(set_attr "itanium_class" "unknown")
945c34bb 4808 (set_attr "predicable" "no")])
fbba5463 4809
f8b4f867 4810;; ??? The explicit stops are not ideal. It would be better if
4811;; rtx_needs_barrier took care of this, but this is something that can be
4812;; fixed later. This avoids an RSE DV.
4813
fbba5463 4814(define_insn "flushrs"
e2b723ca 4815 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
fbba5463 4816 ""
f8b4f867 4817 ";;\;flushrs\;;;"
3823bd9c 4818 [(set_attr "itanium_class" "rse_m")
4819 (set_attr "predicable" "no")])
ac445222 4820\f
4821;; ::::::::::::::::::::
4822;; ::
4823;; :: Miscellaneous instructions
4824;; ::
4825;; ::::::::::::::::::::
4826
efee20da 4827;; ??? Emitting a NOP instruction isn't very useful. This should probably
ac445222 4828;; be emitting ";;" to force a break in the instruction packing.
4829
4830;; No operation, needed in case the user uses -g but not -O.
4831(define_insn "nop"
4832 [(const_int 0)]
4833 ""
4834 "nop 0"
58ada791 4835 [(set_attr "itanium_class" "nop")])
ac445222 4836
a0bb0d20 4837(define_insn "nop_m"
4838 [(const_int 1)]
4839 ""
4840 "nop.m 0"
4841 [(set_attr "itanium_class" "nop_m")])
4842
4843(define_insn "nop_i"
4844 [(const_int 2)]
4845 ""
4846 "nop.i 0"
4847 [(set_attr "itanium_class" "nop_i")])
4848
4849(define_insn "nop_f"
4850 [(const_int 3)]
4851 ""
4852 "nop.f 0"
4853 [(set_attr "itanium_class" "nop_f")])
4854
4855(define_insn "nop_b"
4856 [(const_int 4)]
4857 ""
4858 "nop.b 0"
4859 [(set_attr "itanium_class" "nop_b")])
4860
4861(define_insn "nop_x"
4862 [(const_int 5)]
4863 ""
4864 ""
2b71c761 4865 [(set_attr "itanium_class" "nop_x")
4866 (set_attr "empty" "yes")])
a0bb0d20 4867
58ada791 4868;; The following insn will be never generated. It is used only by
4869;; insn scheduler to change state before advancing cycle.
4870(define_insn "pre_cycle"
4871 [(const_int 6)]
4872 ""
4873 ""
4874 [(set_attr "itanium_class" "pre_cycle")])
4875
a0bb0d20 4876(define_insn "bundle_selector"
e2b723ca 4877 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
a0bb0d20 4878 ""
d2ba5713 4879 { return get_bundle_name (INTVAL (operands[0])); }
a0bb0d20 4880 [(set_attr "itanium_class" "ignore")
4881 (set_attr "predicable" "no")])
4882
ac445222 4883;; Pseudo instruction that prevents the scheduler from moving code above this
4884;; point.
4885(define_insn "blockage"
e2b723ca 4886 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
ac445222 4887 ""
4888 ""
bf6ff2f6 4889 [(set_attr "itanium_class" "ignore")
945c34bb 4890 (set_attr "predicable" "no")])
ac445222 4891
4892(define_insn "insn_group_barrier"
e2b723ca 4893 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
4894 UNSPECV_INSN_GROUP_BARRIER)]
ac445222 4895 ""
4896 ";;"
bf6ff2f6 4897 [(set_attr "itanium_class" "stop_bit")
2b71c761 4898 (set_attr "predicable" "no")
4899 (set_attr "empty" "yes")])
ac445222 4900
0b126525 4901(define_expand "trap"
4902 [(trap_if (const_int 1) (const_int 0))]
4903 ""
4904 "")
4905
4906;; ??? We don't have a match-any slot type. Setting the type to unknown
4907;; produces worse code that setting the slot type to A.
4908
4909(define_insn "*trap"
4910 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
4911 ""
4912 "break %0"
ea13ae4c 4913 [(set_attr "itanium_class" "chk_s_i")])
0b126525 4914
74f4459c 4915(define_expand "ctrapbi4"
4916 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4917 [(match_operand:BI 1 "register_operand" "")
4918 (match_operand:BI 2 "const_int_operand" "")])
4919 (match_operand 3 "" ""))]
0b126525 4920 ""
74f4459c 4921 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4922
4923(define_expand "ctrapsi4"
4924 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4925 [(match_operand:SI 1 "gr_register_operand" "")
4926 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4927 (match_operand 3 "" ""))]
4928 ""
4929 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4930
4931(define_expand "ctrapdi4"
4932 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4933 [(match_operand:DI 1 "gr_register_operand" "")
4934 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4935 (match_operand 3 "" ""))]
4936 ""
4937 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4938
4939(define_expand "ctrapsf4"
4940 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4941 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
4942 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
4943 (match_operand 3 "" ""))]
4944 ""
4945 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4946
4947(define_expand "ctrapdf4"
4948 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4949 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
4950 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
4951 (match_operand 3 "" ""))]
4952 ""
4953 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4954
4955(define_expand "ctrapxf4"
4956 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4957 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
4958 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
4959 (match_operand 3 "" ""))]
4960 ""
4961 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4962
4963(define_expand "ctraptf4"
4964 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4965 [(match_operand:TF 1 "gr_register_operand" "")
4966 (match_operand:TF 2 "gr_register_operand" "")])
4967 (match_operand 3 "" ""))]
4968 "TARGET_HPUX"
4969 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4970
0b126525 4971
4972(define_insn "*conditional_trap"
4973 [(trap_if (match_operator 0 "predicate_operator"
4974 [(match_operand:BI 1 "register_operand" "c")
4975 (const_int 0)])
4976 (match_operand 2 "const_int_operand" ""))]
4977 ""
813b4920 4978 "(%J0) break %2"
ea13ae4c 4979 [(set_attr "itanium_class" "chk_s_i")
0b126525 4980 (set_attr "predicable" "no")])
4981
b69208e6 4982(define_insn "break_f"
e2b723ca 4983 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
b69208e6 4984 ""
4985 "break.f 0"
4986 [(set_attr "itanium_class" "nop_f")])
0df58423 4987
4988(define_insn "prefetch"
4989 [(prefetch (match_operand:DI 0 "address_operand" "p")
4990 (match_operand:DI 1 "const_int_operand" "n")
4991 (match_operand:DI 2 "const_int_operand" "n"))]
4992 ""
4993{
4994 static const char * const alt[2][4] = {
917938fe 4995 {
bd9cb32c 4996 "%,lfetch.nta [%0]",
4997 "%,lfetch.nt1 [%0]",
4998 "%,lfetch.nt2 [%0]",
4999 "%,lfetch [%0]"
917938fe 5000 },
5001 {
bd9cb32c 5002 "%,lfetch.excl.nta [%0]",
5003 "%,lfetch.excl.nt1 [%0]",
5004 "%,lfetch.excl.nt2 [%0]",
5005 "%,lfetch.excl [%0]"
917938fe 5006 }
0df58423 5007 };
5008 int i = (INTVAL (operands[1]));
5009 int j = (INTVAL (operands[2]));
5010
c5c17bca 5011 gcc_assert (i == 0 || i == 1);
5012 gcc_assert (j >= 0 && j <= 3);
0df58423 5013 return alt[i][j];
5014}
5015 [(set_attr "itanium_class" "lfetch")])
ac445222 5016\f
5017;; Non-local goto support.
5018
5019(define_expand "save_stack_nonlocal"
5020 [(use (match_operand:OI 0 "memory_operand" ""))
5021 (use (match_operand:DI 1 "register_operand" ""))]
5022 ""
ac445222 5023{
5024 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5025 \"__ia64_save_stack_nonlocal\"),
b9c74b4d 5026 LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
ac445222 5027 operands[1], Pmode);
5028 DONE;
d2ba5713 5029})
ac445222 5030
5031(define_expand "nonlocal_goto"
5032 [(use (match_operand 0 "general_operand" ""))
5033 (use (match_operand 1 "general_operand" ""))
5034 (use (match_operand 2 "general_operand" ""))
5035 (use (match_operand 3 "general_operand" ""))]
5036 ""
ac445222 5037{
ac445222 5038 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
449c0509 5039 LCT_NORETURN, VOIDmode, 3,
28d202a8 5040 operands[1], Pmode,
ac445222 5041 copy_to_reg (XEXP (operands[2], 0)), Pmode,
28d202a8 5042 operands[3], Pmode);
ac445222 5043 emit_barrier ();
5044 DONE;
d2ba5713 5045})
ac445222 5046
7aaa74b8 5047(define_insn_and_split "nonlocal_goto_receiver"
5048 [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)]
5049 ""
5050 "#"
5051 "reload_completed"
5052 [(const_int 0)]
5053{
5054 ia64_reload_gp ();
5055 DONE;
5056})
5057
8bc66e4d 5058(define_insn_and_split "builtin_setjmp_receiver"
5059 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
cac50a9f 5060 ""
8bc66e4d 5061 "#"
5062 "reload_completed"
5063 [(const_int 0)]
cac50a9f 5064{
e13693ec 5065 ia64_reload_gp ();
ac445222 5066 DONE;
d2ba5713 5067})
ac445222 5068
7c2f467a 5069(define_expand "eh_epilogue"
5070 [(use (match_operand:DI 0 "register_operand" "r"))
5071 (use (match_operand:DI 1 "register_operand" "r"))
5072 (use (match_operand:DI 2 "register_operand" "r"))]
5073 ""
7c2f467a 5074{
5075 rtx bsp = gen_rtx_REG (Pmode, 10);
5076 rtx sp = gen_rtx_REG (Pmode, 9);
5077
5078 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5079 {
5080 emit_move_insn (bsp, operands[0]);
5081 operands[0] = bsp;
5082 }
5083 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5084 {
5085 emit_move_insn (sp, operands[2]);
5086 operands[2] = sp;
5087 }
18b42941 5088 emit_use (sp);
5089 emit_use (bsp);
7c2f467a 5090
5091 cfun->machine->ia64_eh_epilogue_sp = sp;
5092 cfun->machine->ia64_eh_epilogue_bsp = bsp;
d2ba5713 5093})
c06fbba2 5094\f
5095;; Builtin apply support.
5096
5097(define_expand "restore_stack_nonlocal"
5098 [(use (match_operand:DI 0 "register_operand" ""))
5099 (use (match_operand:OI 1 "memory_operand" ""))]
5100 ""
c06fbba2 5101{
5102 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
d2ba5713 5103 "__ia64_restore_stack_nonlocal"),
b9c74b4d 5104 LCT_NORMAL, VOIDmode, 1,
c06fbba2 5105 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5106 DONE;
d2ba5713 5107})
c06fbba2 5108
945c34bb 5109\f
5110;; Predication.
5111
5112(define_cond_exec
5113 [(match_operator 0 "predicate_operator"
33c8f6d1 5114 [(match_operand:BI 1 "register_operand" "c")
945c34bb 5115 (const_int 0)])]
5116 ""
5117 "(%J0)")
9b06caff 5118
5119(define_insn "pred_rel_mutex"
33c8f6d1 5120 [(set (match_operand:BI 0 "register_operand" "+c")
e2b723ca 5121 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
9b06caff 5122 ""
aad3d095 5123 ".pred.rel.mutex %0, %I0"
bf6ff2f6 5124 [(set_attr "itanium_class" "ignore")
9b06caff 5125 (set_attr "predicable" "no")])
356b51a0 5126
5127(define_insn "safe_across_calls_all"
e2b723ca 5128 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
356b51a0 5129 ""
5130 ".pred.safe_across_calls p1-p63"
bf6ff2f6 5131 [(set_attr "itanium_class" "ignore")
356b51a0 5132 (set_attr "predicable" "no")])
5133
5134(define_insn "safe_across_calls_normal"
e2b723ca 5135 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
356b51a0 5136 ""
356b51a0 5137{
92c473b8 5138 emit_safe_across_calls ();
d2ba5713 5139 return "";
5140}
bf6ff2f6 5141 [(set_attr "itanium_class" "ignore")
356b51a0 5142 (set_attr "predicable" "no")])
5143
3cc94518 5144;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit
3cc092f7 5145;; pointer. This is used by the HP-UX 32 bit mode.
5146
5147(define_insn "ptr_extend"
5148 [(set (match_operand:DI 0 "gr_register_operand" "=r")
e2b723ca 5149 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5150 UNSPEC_ADDP4))]
3cc092f7 5151 ""
5152 "addp4 %0 = 0,%1"
5153 [(set_attr "itanium_class" "ialu")])
5154
736414ab 5155;;
5156;; Optimizations for ptr_extend
5157
f10f921c 5158(define_insn "ptr_extend_plus_imm"
736414ab 5159 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5160 (unspec:DI
5161 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5162 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
e2b723ca 5163 UNSPEC_ADDP4))]
19316b5e 5164 "addp4_optimize_ok (operands[1], operands[2])"
736414ab 5165 "addp4 %0 = %2, %1"
5166 [(set_attr "itanium_class" "ialu")])
5167
5168(define_insn "*ptr_extend_plus_2"
5169 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5170 (unspec:DI
5171 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5172 (match_operand:SI 2 "basereg_operand" "r"))]
e2b723ca 5173 UNSPEC_ADDP4))]
19316b5e 5174 "addp4_optimize_ok (operands[1], operands[2])"
736414ab 5175 "addp4 %0 = %1, %2"
5176 [(set_attr "itanium_class" "ialu")])
a5c5f9d3 5177
f0ae8b21 5178;;
5179;; Get instruction pointer
5180
5181(define_insn "ip_value"
5182 [(set (match_operand:DI 0 "register_operand" "=r")
5183 (pc))]
5184 ""
5185 "mov %0 = ip"
64b86428 5186 [(set_attr "itanium_class" "frbr")])
f0ae8b21 5187
28d5c3d9 5188;;
5189;; Stack checking
5190
5191(define_insn "probe_stack_address"
5192 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
5193 UNSPECV_PROBE_STACK_ADDRESS)]
5194 ""
5195 "probe.w.fault %0, 0"
5196[(set_attr "itanium_class" "chk_s_i")])
5197
5198(define_insn "probe_stack_range"
5199 [(set (match_operand:DI 0 "register_operand" "=r")
5200 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0")
5201 (match_operand:DI 2 "register_operand" "r")]
5202 UNSPECV_PROBE_STACK_RANGE))]
5203 ""
5204 "* return output_probe_stack_range (operands[0], operands[2]);"
5205 [(set_attr "itanium_class" "unknown")
5206 (set_attr "predicable" "no")])
5207
a5c5f9d3 5208;; Vector operations
5209(include "vect.md")
7c1e874f 5210;; Atomic operations
5211(include "sync.md")
78d690bb 5212;; New division operations
5213(include "div.md")
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