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c65ebc55 | 1 | ;; IA-64 Machine description template |
cbe34bb5 | 2 | ;; Copyright (C) 1999-2017 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
3bed2930 | 6 | ;; This file is part of GCC. |
c65ebc55 | 7 | |
3bed2930 | 8 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 9 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
11 | ;; any later version. |
12 | ||
3bed2930 | 13 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | ;; along with GCC; see the file COPYING3. If not see |
20 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
21 | |
22 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
23 | ||
c65ebc55 JW |
24 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
25 | ;; reload. This will be fixed once scheduling support is turned on. | |
26 | ||
27 | ;; ??? Optimize for post-increment addressing modes. | |
28 | ||
29 | ;; ??? fselect is not supported, because there is no integer register | |
30 | ;; equivalent. | |
31 | ||
32 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
33 | ||
34 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
35 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
36 | ||
37 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
38 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
39 | ||
40 | ;; ??? Go through list of documented named patterns and look for more to | |
41 | ;; implement. | |
42 | ||
43 | ;; ??? Go through instruction manual and look for more instructions that | |
44 | ;; can be emitted. | |
45 | ||
46 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
47 | ||
26102535 RH |
48 | ;; ??? Need a better way to describe alternate fp status registers. |
49 | ||
127e44c8 | 50 | (define_c_enum "unspec" |
7b6e506e | 51 | [; Relocations |
127e44c8 RH |
52 | UNSPEC_LTOFF_DTPMOD |
53 | UNSPEC_LTOFF_DTPREL | |
54 | UNSPEC_DTPREL | |
55 | UNSPEC_LTOFF_TPREL | |
56 | UNSPEC_TPREL | |
57 | UNSPEC_DTPMOD | |
58 | ||
59 | UNSPEC_LD_BASE | |
60 | UNSPEC_GR_SPILL | |
61 | UNSPEC_GR_RESTORE | |
62 | UNSPEC_FR_SPILL | |
63 | UNSPEC_FR_RESTORE | |
64 | UNSPEC_FR_RECIP_APPROX | |
65 | UNSPEC_PRED_REL_MUTEX | |
66 | UNSPEC_GETF_EXP | |
67 | UNSPEC_PIC_CALL | |
68 | UNSPEC_MF | |
69 | UNSPEC_CMPXCHG_ACQ | |
28875d67 | 70 | UNSPEC_CMPXCHG_REL |
127e44c8 | 71 | UNSPEC_FETCHADD_ACQ |
28875d67 | 72 | UNSPEC_FETCHADD_REL |
127e44c8 RH |
73 | UNSPEC_BSP_VALUE |
74 | UNSPEC_FLUSHRS | |
75 | UNSPEC_BUNDLE_SELECTOR | |
76 | UNSPEC_ADDP4 | |
77 | UNSPEC_PROLOGUE_USE | |
78 | UNSPEC_RET_ADDR | |
79 | UNSPEC_SETF_EXP | |
80 | UNSPEC_FR_SQRT_RECIP_APPROX | |
81 | UNSPEC_SHRP | |
82 | UNSPEC_COPYSIGN | |
83 | UNSPEC_VECT_EXTR | |
84 | UNSPEC_LDA | |
85 | UNSPEC_LDS | |
86 | UNSPEC_LDS_A | |
87 | UNSPEC_LDSA | |
88 | UNSPEC_LDCCLR | |
89 | UNSPEC_LDCNC | |
90 | UNSPEC_CHKACLR | |
91 | UNSPEC_CHKANC | |
92 | UNSPEC_CHKS | |
93 | UNSPEC_FR_RECIP_APPROX_RES | |
94 | UNSPEC_FR_SQRT_RECIP_APPROX_RES | |
086c0f96 RH |
95 | ]) |
96 | ||
127e44c8 RH |
97 | (define_c_enum "unspecv" [ |
98 | UNSPECV_ALLOC | |
99 | UNSPECV_BLOCKAGE | |
100 | UNSPECV_INSN_GROUP_BARRIER | |
101 | UNSPECV_BREAK | |
102 | UNSPECV_SET_BSP | |
103 | UNSPECV_PSAC_ALL ; pred.safe_across_calls | |
104 | UNSPECV_PSAC_NORMAL | |
105 | UNSPECV_SETJMP_RECEIVER | |
106 | UNSPECV_GOTO_RECEIVER | |
7b84aac0 EB |
107 | UNSPECV_PROBE_STACK_ADDRESS |
108 | UNSPECV_PROBE_STACK_RANGE | |
086c0f96 | 109 | ]) |
e543e219 | 110 | |
7905f799 | 111 | (include "predicates.md") |
13f70342 | 112 | (include "constraints.md") |
c65ebc55 JW |
113 | \f |
114 | ;; :::::::::::::::::::: | |
115 | ;; :: | |
116 | ;; :: Attributes | |
117 | ;; :: | |
118 | ;; :::::::::::::::::::: | |
119 | ||
30028c85 VM |
120 | ;; Processor type. This attribute must exactly match the processor_type |
121 | ;; enumeration in ia64.h. | |
bbbbb16a ILT |
122 | (define_attr "cpu" "itanium,itanium2" |
123 | (const (symbol_ref "((enum attr_cpu) ia64_tune)"))) | |
30028c85 | 124 | |
c65ebc55 JW |
125 | ;; Instruction type. This primarily determines how instructions can be |
126 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
127 | ||
128 | ;; A alu, can go in I or M syllable of a bundle | |
129 | ;; I integer | |
130 | ;; M memory | |
131 | ;; F floating-point | |
132 | ;; B branch | |
133 | ;; L long immediate, takes two syllables | |
134 | ;; S stop bit | |
135 | ||
136 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
137 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
138 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
139 | ;; which emit instruction that can go in any slot (e.g. nop). | |
140 | ||
1d5d7a21 | 141 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 142 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 143 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
144 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
145 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 146 | (const_string "unknown")) |
52e12ad0 | 147 | |
048d0d36 | 148 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 149 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 150 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
151 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
152 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 153 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
154 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
155 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 156 | (const_string "A") |
2130b7fb BS |
157 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
158 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
159 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
160 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
161 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
162 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 163 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 164 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
165 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
166 | (const_string "unknown"))) | |
c65ebc55 | 167 | |
2130b7fb BS |
168 | (define_attr "itanium_requires_unit0" "no,yes" |
169 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
170 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
171 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
172 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
173 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
174 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
175 | (const_string "no"))) | |
176 | ||
e5bde68a RH |
177 | ;; Predication. True iff this instruction can be predicated. |
178 | ||
179 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
180 | ||
fa978426 AS |
181 | ;; Empty. True iff this insn does not generate any code. |
182 | ||
183 | (define_attr "empty" "no,yes" (const_string "no")) | |
184 | ||
68e11b42 JW |
185 | ;; True iff this insn must be the first insn of an instruction group. |
186 | ;; This is true for the alloc instruction, and will also be true of others | |
187 | ;; when we have full intrinsics support. | |
188 | ||
189 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
190 | |
191 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
192 | ||
193 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
194 | ||
195 | (define_attr "check_load" "no,yes" (const_string "no")) | |
388092d5 AB |
196 | |
197 | (define_attr "speculable1" "no,yes" (const_string "no")) | |
198 | ||
199 | (define_attr "speculable2" "no,yes" (const_string "no")) | |
c65ebc55 | 200 | \f |
30028c85 VM |
201 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
202 | ;; bundling. | |
203 | ||
204 | (automata_option "ndfa") | |
205 | ||
206 | ;; Uncomment the following line to output automata for debugging. | |
207 | ;; (automata_option "v") | |
208 | ||
209 | (automata_option "w") | |
210 | ||
30028c85 | 211 | (include "itanium2.md") |
f19f1e5e RH |
212 | \f |
213 | ;; Mode iterators | |
214 | ||
215 | ; Used for truncations from XFmode. | |
216 | (define_mode_iterator MODE_SDF [SF DF]) | |
30028c85 | 217 | |
f19f1e5e RH |
218 | (define_mode_attr suffix [ |
219 | (SF ".s") | |
220 | (DF ".d") | |
221 | (XF "") | |
222 | ]) | |
c65ebc55 JW |
223 | \f |
224 | ;; :::::::::::::::::::: | |
225 | ;; :: | |
226 | ;; :: Moves | |
227 | ;; :: | |
228 | ;; :::::::::::::::::::: | |
229 | ||
f2f90c63 RH |
230 | ;; Set of a single predicate register. This is only used to implement |
231 | ;; pr-to-pr move and complement. | |
232 | ||
33620355 EB |
233 | (define_insn "movcci" |
234 | [(set (match_operand:CCI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*m,*r") | |
235 | (match_operand:CCI 1 "move_operand" " O,n, c, c,*r,*m,*r,*r"))] | |
f2f90c63 RH |
236 | "" |
237 | "@ | |
238 | cmp.ne %0, p0 = r0, r0 | |
239 | cmp.eq %0, p0 = r0, r0 | |
33620355 EB |
240 | (%1) cmp.eq.unc %0, p0 = r0, r0 |
241 | # | |
242 | tbit.nz %0, p0 = %1, 0 | |
243 | ld1%O1 %0 = %1%P1 | |
244 | st1%Q0 %0 = %1%P0 | |
245 | mov %0 = %1" | |
246 | [(set_attr "itanium_class" "icmp,icmp,icmp,unknown,tbit,ld,st,ialu") | |
f2f90c63 RH |
247 | (set_attr "predicable" "no")]) |
248 | ||
33620355 EB |
249 | (define_split |
250 | [(set (match_operand:CCI 0 "register_operand" "") | |
251 | (match_operand:CCI 1 "register_operand" ""))] | |
252 | "reload_completed | |
253 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
254 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
255 | [(set (match_dup 2) (const_int 0)) | |
256 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
257 | (set (match_dup 2) (const_int 1)))] | |
258 | "operands[2] = gen_rtx_REG (BImode, REGNO (operands[0])); | |
259 | operands[3] = gen_rtx_REG (BImode, REGNO (operands[1]));") | |
260 | ||
f2f90c63 | 261 | (define_insn "movbi" |
b6fb7d46 JW |
262 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
263 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
264 | "" |
265 | "@ | |
266 | cmp.ne %0, %I0 = r0, r0 | |
267 | cmp.eq %0, %I0 = r0, r0 | |
268 | # | |
269 | # | |
270 | tbit.nz %0, %I0 = %1, 0 | |
271 | adds %0 = %1, r0 | |
272 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
273 | st1%Q0 %0 = %1%P0 |
274 | mov %0 = %1" | |
388092d5 AB |
275 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu") |
276 | (set_attr "speculable1" "yes") | |
277 | (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")]) | |
f2f90c63 RH |
278 | |
279 | (define_split | |
280 | [(set (match_operand:BI 0 "register_operand" "") | |
281 | (match_operand:BI 1 "register_operand" ""))] | |
282 | "reload_completed | |
283 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
284 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
285 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
286 | (set (match_dup 0) (const_int 1))) | |
287 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
288 | (set (match_dup 0) (const_int 0)))] | |
289 | "") | |
290 | ||
291 | (define_split | |
292 | [(set (match_operand:BI 0 "register_operand" "") | |
293 | (match_operand:BI 1 "register_operand" ""))] | |
294 | "reload_completed | |
295 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
296 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
297 | [(set (match_dup 2) (match_dup 4)) | |
298 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 299 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
300 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
301 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
302 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
303 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
304 | ||
c65ebc55 JW |
305 | (define_expand "movqi" |
306 | [(set (match_operand:QI 0 "general_operand" "") | |
307 | (match_operand:QI 1 "general_operand" ""))] | |
308 | "" | |
c65ebc55 | 309 | { |
7b6e506e RH |
310 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
311 | if (!op1) | |
312 | DONE; | |
313 | operands[1] = op1; | |
1d5d7a21 | 314 | }) |
c65ebc55 | 315 | |
388092d5 | 316 | (define_insn "movqi_internal" |
4b983fdc RH |
317 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
318 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 319 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 320 | "@ |
13da91fd | 321 | mov %0 = %r1 |
c65ebc55 JW |
322 | addl %0 = %1, r0 |
323 | ld1%O1 %0 = %1%P1 | |
13da91fd | 324 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 325 | getf.sig %0 = %1 |
13da91fd RH |
326 | setf.sig %0 = %r1 |
327 | mov %0 = %1" | |
388092d5 AB |
328 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
329 | (set_attr "speculable1" "yes") | |
330 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
331 | |
332 | (define_expand "movhi" | |
333 | [(set (match_operand:HI 0 "general_operand" "") | |
334 | (match_operand:HI 1 "general_operand" ""))] | |
335 | "" | |
c65ebc55 | 336 | { |
7b6e506e RH |
337 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
338 | if (!op1) | |
339 | DONE; | |
340 | operands[1] = op1; | |
1d5d7a21 | 341 | }) |
c65ebc55 | 342 | |
388092d5 | 343 | (define_insn "movhi_internal" |
4b983fdc RH |
344 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
345 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 346 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 347 | "@ |
13da91fd | 348 | mov %0 = %r1 |
c65ebc55 JW |
349 | addl %0 = %1, r0 |
350 | ld2%O1 %0 = %1%P1 | |
13da91fd | 351 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 352 | getf.sig %0 = %1 |
13da91fd RH |
353 | setf.sig %0 = %r1 |
354 | mov %0 = %1" | |
388092d5 AB |
355 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
356 | (set_attr "speculable1" "yes") | |
357 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
358 | |
359 | (define_expand "movsi" | |
360 | [(set (match_operand:SI 0 "general_operand" "") | |
361 | (match_operand:SI 1 "general_operand" ""))] | |
362 | "" | |
c65ebc55 | 363 | { |
7b6e506e RH |
364 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
365 | if (!op1) | |
366 | DONE; | |
367 | operands[1] = op1; | |
1d5d7a21 | 368 | }) |
c65ebc55 | 369 | |
388092d5 | 370 | (define_insn "movsi_internal" |
4e483a22 JB |
371 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d") |
372 | (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))] | |
aebf2462 | 373 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 374 | "@ |
13da91fd | 375 | mov %0 = %r1 |
c65ebc55 | 376 | addl %0 = %1, r0 |
4e483a22 | 377 | addp4 %0 = %1 - 0x100000000, r0 |
c65ebc55 JW |
378 | movl %0 = %1 |
379 | ld4%O1 %0 = %1%P1 | |
13da91fd | 380 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 381 | getf.sig %0 = %1 |
13da91fd | 382 | setf.sig %0 = %r1 |
97e242b0 RH |
383 | mov %0 = %1 |
384 | mov %0 = %1 | |
385 | mov %0 = %r1" | |
1d5d7a21 | 386 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
388092d5 AB |
387 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m") |
388 | (set_attr "speculable1" "yes") | |
389 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")]) | |
c65ebc55 JW |
390 | |
391 | (define_expand "movdi" | |
392 | [(set (match_operand:DI 0 "general_operand" "") | |
393 | (match_operand:DI 1 "general_operand" ""))] | |
394 | "" | |
c65ebc55 | 395 | { |
7b6e506e RH |
396 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
397 | if (!op1) | |
398 | DONE; | |
399 | operands[1] = op1; | |
1d5d7a21 | 400 | }) |
c65ebc55 | 401 | |
388092d5 | 402 | (define_insn "movdi_internal" |
4b983fdc | 403 | [(set (match_operand:DI 0 "destination_operand" |
4e483a22 | 404 | "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 405 | (match_operand:DI 1 "move_operand" |
4e483a22 | 406 | "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 407 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
408 | { |
409 | static const char * const alt[] = { | |
1d5d7a21 RH |
410 | "%,mov %0 = %r1", |
411 | "%,addl %0 = %1, r0", | |
4e483a22 | 412 | "%,addp4 %0 = %1 - 0x100000000, r0", |
1d5d7a21 RH |
413 | "%,movl %0 = %1", |
414 | "%,ld8%O1 %0 = %1%P1", | |
415 | "%,st8%Q0 %0 = %r1%P0", | |
416 | "%,getf.sig %0 = %1", | |
417 | "%,setf.sig %0 = %r1", | |
418 | "%,mov %0 = %1", | |
419 | "%,ldf8 %0 = %1%P1", | |
420 | "%,stf8 %0 = %1%P0", | |
421 | "%,mov %0 = %1", | |
422 | "%,mov %0 = %r1", | |
423 | "%,mov %0 = %1", | |
424 | "%,mov %0 = %1", | |
425 | "%,mov %0 = %1", | |
426 | "%,mov %0 = %1", | |
427 | "mov %0 = pr", | |
428 | "mov pr = %1, -1" | |
9b7bf67d RH |
429 | }; |
430 | ||
e820471b NS |
431 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
432 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
433 | |
434 | return alt[which_alternative]; | |
1d5d7a21 | 435 | } |
388092d5 AB |
436 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr") |
437 | (set_attr "speculable1" "yes") | |
438 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")]) | |
c65ebc55 | 439 | |
3abcb3a7 | 440 | (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI]) |
f90b7a5a | 441 | (define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")]) |
3abcb3a7 | 442 | (define_mode_iterator MODE_FOR_EXTEND [QI HI SI]) |
048d0d36 MK |
443 | |
444 | (define_mode_attr output_a [ | |
445 | (BI "ld1.a %0 = %1%P1") | |
446 | (QI "ld1.a %0 = %1%P1") | |
447 | (HI "ld2.a %0 = %1%P1") | |
448 | (SI "ld4.a %0 = %1%P1") | |
449 | (DI | |
450 | "@ | |
451 | ld8.a %0 = %1%P1 | |
452 | ldf8.a %0 = %1%P1") | |
453 | (SF | |
454 | "@ | |
455 | ldfs.a %0 = %1%P1 | |
456 | ld4.a %0 = %1%P1") | |
457 | (DF | |
458 | "@ | |
459 | ldfd.a %0 = %1%P1 | |
460 | ld8.a %0 = %1%P1") | |
461 | (XF "ldfe.a %0 = %1%P1") | |
462 | (TI "ldfp8.a %X0 = %1%P1")]) | |
463 | ||
464 | (define_mode_attr output_s [ | |
465 | (BI "ld1.s %0 = %1%P1") | |
466 | (QI "ld1.s %0 = %1%P1") | |
467 | (HI "ld2.s %0 = %1%P1") | |
468 | (SI "ld4.s %0 = %1%P1") | |
469 | (DI | |
470 | "@ | |
471 | ld8.s %0 = %1%P1 | |
472 | ldf8.s %0 = %1%P1") | |
473 | (SF | |
474 | "@ | |
475 | ldfs.s %0 = %1%P1 | |
476 | ld4.s %0 = %1%P1") | |
477 | (DF | |
478 | "@ | |
479 | ldfd.s %0 = %1%P1 | |
480 | ld8.s %0 = %1%P1") | |
481 | (XF "ldfe.s %0 = %1%P1") | |
482 | (TI "ldfp8.s %X0 = %1%P1")]) | |
483 | ||
484 | (define_mode_attr output_sa [ | |
485 | (BI "ld1.sa %0 = %1%P1") | |
486 | (QI "ld1.sa %0 = %1%P1") | |
487 | (HI "ld2.sa %0 = %1%P1") | |
488 | (SI "ld4.sa %0 = %1%P1") | |
489 | (DI | |
490 | "@ | |
491 | ld8.sa %0 = %1%P1 | |
492 | ldf8.sa %0 = %1%P1") | |
493 | (SF | |
494 | "@ | |
495 | ldfs.sa %0 = %1%P1 | |
496 | ld4.sa %0 = %1%P1") | |
497 | (DF | |
498 | "@ | |
499 | ldfd.sa %0 = %1%P1 | |
500 | ld8.sa %0 = %1%P1") | |
501 | (XF "ldfe.sa %0 = %1%P1") | |
502 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
503 | ||
504 | (define_mode_attr output_c_clr [ | |
505 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
506 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
507 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
508 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
509 | (DI | |
510 | "@ | |
511 | ld8.c.clr%O1 %0 = %1%P1 | |
512 | ldf8.c.clr %0 = %1%P1") | |
513 | (SF | |
514 | "@ | |
515 | ldfs.c.clr %0 = %1%P1 | |
516 | ld4.c.clr%O1 %0 = %1%P1") | |
517 | (DF | |
518 | "@ | |
519 | ldfd.c.clr %0 = %1%P1 | |
520 | ld8.c.clr%O1 %0 = %1%P1") | |
521 | (XF "ldfe.c.clr %0 = %1%P1") | |
522 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
523 | ||
388092d5 AB |
524 | (define_mode_attr output_c_nc [ |
525 | (BI "ld1.c.nc%O1 %0 = %1%P1") | |
526 | (QI "ld1.c.nc%O1 %0 = %1%P1") | |
527 | (HI "ld2.c.nc%O1 %0 = %1%P1") | |
528 | (SI "ld4.c.nc%O1 %0 = %1%P1") | |
529 | (DI | |
530 | "@ | |
531 | ld8.c.nc%O1 %0 = %1%P1 | |
532 | ldf8.c.nc %0 = %1%P1") | |
533 | (SF | |
534 | "@ | |
535 | ldfs.c.nc %0 = %1%P1 | |
536 | ld4.c.nc%O1 %0 = %1%P1") | |
537 | (DF | |
538 | "@ | |
539 | ldfd.c.nc %0 = %1%P1 | |
540 | ld8.c.nc%O1 %0 = %1%P1") | |
541 | (XF "ldfe.c.nc %0 = %1%P1") | |
542 | (TI "ldfp8.c.nc %X0 = %1%P1")]) | |
543 | ||
048d0d36 MK |
544 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) |
545 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
546 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
547 | ||
548 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
549 | ||
f6ec1d11 MK |
550 | ;; Define register predicate prefix. |
551 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 552 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
553 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
554 | ||
555 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
556 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
557 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
558 | ||
559 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
560 | ||
561 | (define_insn "mov<mode>_advanced" | |
562 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
563 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
564 | "ia64_move_ok (operands[0], operands[1])" | |
565 | "<output_a>" | |
566 | [(set_attr "itanium_class" "<ld_class>") | |
567 | (set_attr "data_speculative" "<attr_yes>")]) | |
568 | ||
569 | (define_insn "zero_extend<mode>di2_advanced" | |
570 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
571 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
572 | "" | |
573 | "<output_a>" | |
574 | [(set_attr "itanium_class" "<ld_class>") | |
575 | (set_attr "data_speculative" "<attr_yes>")]) | |
576 | ||
577 | (define_insn "mov<mode>_speculative" | |
578 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
579 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
580 | "ia64_move_ok (operands[0], operands[1])" | |
581 | "<output_s>" | |
582 | [(set_attr "itanium_class" "<ld_class>") | |
583 | (set_attr "control_speculative" "<attr_yes>")]) | |
584 | ||
585 | (define_insn "zero_extend<mode>di2_speculative" | |
586 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
587 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
588 | "" | |
589 | "<output_s>" | |
590 | [(set_attr "itanium_class" "<ld_class>") | |
591 | (set_attr "control_speculative" "<attr_yes>")]) | |
592 | ||
593 | (define_insn "mov<mode>_speculative_advanced" | |
594 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
595 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
596 | "ia64_move_ok (operands[0], operands[1])" | |
597 | "<output_sa>" | |
598 | [(set_attr "itanium_class" "<ld_class>") | |
599 | (set_attr "data_speculative" "<attr_yes>") | |
600 | (set_attr "control_speculative" "<attr_yes>")]) | |
601 | ||
388092d5 AB |
602 | (define_insn "mov<mode>_speculative_a" |
603 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
604 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))] | |
605 | "ia64_move_ok (operands[0], operands[1])" | |
606 | "<output_sa>" | |
607 | [(set_attr "itanium_class" "<ld_class>") | |
608 | (set_attr "data_speculative" "<attr_yes>") | |
609 | (set_attr "control_speculative" "<attr_yes>")]) | |
610 | ||
048d0d36 MK |
611 | (define_insn "zero_extend<mode>di2_speculative_advanced" |
612 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
613 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
614 | "" | |
615 | "<output_sa>" | |
616 | [(set_attr "itanium_class" "<ld_class>") | |
617 | (set_attr "data_speculative" "<attr_yes>") | |
618 | (set_attr "control_speculative" "<attr_yes>")]) | |
619 | ||
388092d5 AB |
620 | (define_insn "zero_extend<mode>di2_speculative_a" |
621 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
622 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))] | |
623 | "" | |
624 | "<output_sa>" | |
625 | [(set_attr "itanium_class" "<ld_class>") | |
626 | (set_attr "data_speculative" "<attr_yes>") | |
627 | (set_attr "control_speculative" "<attr_yes>")]) | |
628 | ||
048d0d36 MK |
629 | (define_insn "mov<mode>_clr" |
630 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
631 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
632 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
633 | (match_dup 0)))] | |
634 | "ia64_move_ok (operands[0], operands[1])" | |
635 | "<output_c_clr>" | |
636 | [(set_attr "itanium_class" "<ld_class>") | |
637 | (set_attr "check_load" "<attr_yes>")]) | |
638 | ||
388092d5 AB |
639 | (define_insn "mov<mode>_nc" |
640 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
641 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
642 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
643 | (match_dup 0)))] | |
644 | "ia64_move_ok (operands[0], operands[1])" | |
645 | "<output_c_nc>" | |
646 | [(set_attr "itanium_class" "<ld_class>") | |
647 | (set_attr "check_load" "<attr_yes>")]) | |
648 | ||
048d0d36 MK |
649 | (define_insn "zero_extend<mode>di2_clr" |
650 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
651 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
652 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
653 | (match_dup 0)))] | |
654 | "" | |
655 | "<output_c_clr>" | |
656 | [(set_attr "itanium_class" "<ld_class>") | |
657 | (set_attr "check_load" "<attr_yes>")]) | |
658 | ||
388092d5 AB |
659 | (define_insn "zero_extend<mode>di2_nc" |
660 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
661 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
662 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
663 | (match_dup 0)))] | |
664 | "" | |
665 | "<output_c_nc>" | |
666 | [(set_attr "itanium_class" "<ld_class>") | |
667 | (set_attr "check_load" "<attr_yes>")]) | |
668 | ||
048d0d36 MK |
669 | (define_insn "advanced_load_check_clr_<mode>" |
670 | [(set (pc) | |
671 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
672 | (pc) | |
673 | (label_ref (match_operand 1 "" ""))))] | |
674 | "" | |
675 | "chk.a.clr %0, %l1" | |
676 | [(set_attr "itanium_class" "<chka_class>")]) | |
677 | ||
388092d5 AB |
678 | (define_insn "advanced_load_check_nc_<mode>" |
679 | [(set (pc) | |
680 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0)) | |
681 | (pc) | |
682 | (label_ref (match_operand 1 "" ""))))] | |
683 | "" | |
684 | "chk.a.clr %0, %l1" | |
685 | [(set_attr "itanium_class" "<chka_class>")]) | |
686 | ||
048d0d36 MK |
687 | (define_insn "speculation_check_<mode>" |
688 | [(set (pc) | |
689 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
690 | (pc) | |
691 | (label_ref (match_operand 1 "" ""))))] | |
692 | "" | |
693 | "chk.s %0, %l1" | |
694 | [(set_attr "itanium_class" "<chks_class>")]) | |
695 | ||
9b7bf67d | 696 | (define_split |
21515593 RH |
697 | [(set (match_operand 0 "register_operand" "") |
698 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 699 | "reload_completed" |
9b7bf67d | 700 | [(const_int 0)] |
9b7bf67d | 701 | { |
5e6c8b64 RH |
702 | if (ia64_expand_load_address (operands[0], operands[1])) |
703 | DONE; | |
704 | else | |
705 | FAIL; | |
1d5d7a21 | 706 | }) |
9b7bf67d | 707 | |
c65ebc55 | 708 | (define_expand "load_fptr" |
5e6c8b64 RH |
709 | [(set (match_operand:DI 0 "register_operand" "") |
710 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
711 | (set (match_dup 0) (match_dup 3))] | |
712 | "reload_completed" | |
c65ebc55 | 713 | { |
5e6c8b64 RH |
714 | operands[2] = pic_offset_table_rtx; |
715 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 716 | }) |
c65ebc55 JW |
717 | |
718 | (define_insn "*load_fptr_internal1" | |
719 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 720 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 721 | "reload_completed" |
c65ebc55 | 722 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 723 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
724 | |
725 | (define_insn "load_gprel" | |
726 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 727 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 728 | "reload_completed" |
c65ebc55 | 729 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 730 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 731 | |
5e6c8b64 | 732 | (define_insn "*gprel64_offset" |
59da9a7d JW |
733 | [(set (match_operand:DI 0 "register_operand" "=r") |
734 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 735 | "reload_completed" |
59da9a7d | 736 | "movl %0 = @gprel(%1)" |
52e12ad0 | 737 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
738 | |
739 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
740 | [(set (match_operand:DI 0 "register_operand" "") |
741 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
742 | (set (match_dup 0) | |
743 | (plus:DI (match_dup 2) (match_dup 0)))] | |
744 | "reload_completed" | |
ec039e3c | 745 | { |
5e6c8b64 | 746 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 747 | }) |
59da9a7d | 748 | |
af1e5518 RH |
749 | ;; This is used as a placeholder for the return address during early |
750 | ;; compilation. We won't know where we've placed this until during | |
751 | ;; reload, at which point it can wind up in b0, a general register, | |
752 | ;; or memory. The only safe destination under these conditions is a | |
753 | ;; general register. | |
754 | ||
755 | (define_insn_and_split "*movdi_ret_addr" | |
756 | [(set (match_operand:DI 0 "register_operand" "=r") | |
757 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
758 | "" | |
759 | "#" | |
760 | "reload_completed" | |
761 | [(const_int 0)] | |
762 | { | |
763 | ia64_split_return_addr_rtx (operands[0]); | |
764 | DONE; | |
765 | } | |
766 | [(set_attr "itanium_class" "ialu")]) | |
767 | ||
ef1ecf87 | 768 | (define_insn "*load_symptr_high" |
c65ebc55 | 769 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
770 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
771 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 772 | "reload_completed" |
ef1ecf87 RH |
773 | { |
774 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
775 | return "%,addl %0 = @ltoffx(%1), %2"; | |
776 | else | |
777 | return "%,addl %0 = @ltoff(%1), %2"; | |
778 | } | |
52e12ad0 | 779 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 780 | |
ef1ecf87 RH |
781 | (define_insn "*load_symptr_low" |
782 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1f88caaa | 783 | (lo_sum:DI (mem:DI (match_operand:DI 1 "register_operand" "r")) |
ef1ecf87 | 784 | (match_operand 2 "got_symbolic_operand" "s")))] |
5e6c8b64 | 785 | "reload_completed" |
ef1ecf87 RH |
786 | { |
787 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
788 | return "%,ld8.mov %0 = [%1], %2"; | |
789 | else | |
790 | return "%,ld8 %0 = [%1]"; | |
791 | } | |
792 | [(set_attr "itanium_class" "ld")]) | |
793 | ||
5e6c8b64 | 794 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 795 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 796 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 797 | UNSPEC_DTPMOD))] |
7b6e506e | 798 | "" |
5e6c8b64 RH |
799 | "#" |
800 | "reload_completed" | |
801 | [(set (match_dup 0) | |
802 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
803 | (match_dup 2))) | |
804 | (set (match_dup 0) (match_dup 3))] | |
805 | { | |
806 | operands[2] = pic_offset_table_rtx; | |
807 | operands[3] = gen_const_mem (DImode, operands[0]); | |
808 | }) | |
7b6e506e | 809 | |
5e6c8b64 | 810 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 811 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 812 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
813 | UNSPEC_LTOFF_DTPMOD) |
814 | (match_operand:DI 2 "register_operand" "a")))] | |
815 | "reload_completed" | |
816 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
817 | [(set_attr "itanium_class" "ialu")]) |
818 | ||
819 | (define_expand "load_dtprel" | |
820 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 821 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
822 | UNSPEC_DTPREL))] |
823 | "" | |
824 | "") | |
825 | ||
826 | (define_insn "*load_dtprel64" | |
827 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 828 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
829 | UNSPEC_DTPREL))] |
830 | "TARGET_TLS64" | |
831 | "movl %0 = @dtprel(%1)" | |
832 | [(set_attr "itanium_class" "long_i")]) | |
833 | ||
834 | (define_insn "*load_dtprel22" | |
835 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 836 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
837 | UNSPEC_DTPREL))] |
838 | "" | |
839 | "addl %0 = @dtprel(%1), r0" | |
840 | [(set_attr "itanium_class" "ialu")]) | |
841 | ||
5e6c8b64 RH |
842 | (define_insn_and_split "*load_dtprel_gd" |
843 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 844 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
845 | UNSPEC_DTPREL))] |
846 | "" | |
847 | "#" | |
848 | "reload_completed" | |
849 | [(set (match_dup 0) | |
850 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
851 | (match_dup 2))) | |
852 | (set (match_dup 0) (match_dup 3))] | |
853 | { | |
854 | operands[2] = pic_offset_table_rtx; | |
855 | operands[3] = gen_const_mem (DImode, operands[0]); | |
856 | }) | |
857 | ||
858 | (define_insn "*load_ltoff_dtprel" | |
859 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 860 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
861 | UNSPEC_LTOFF_DTPREL) |
862 | (match_operand:DI 2 "register_operand" "a")))] | |
863 | "" | |
864 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
865 | [(set_attr "itanium_class" "ialu")]) | |
866 | ||
7b6e506e RH |
867 | (define_expand "add_dtprel" |
868 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 869 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
870 | UNSPEC_DTPREL) |
871 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
872 | "!TARGET_TLS64" |
873 | "") | |
874 | ||
875 | (define_insn "*add_dtprel14" | |
876 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 877 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
878 | UNSPEC_DTPREL) |
879 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 880 | "TARGET_TLS14" |
5e6c8b64 | 881 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
882 | [(set_attr "itanium_class" "ialu")]) |
883 | ||
884 | (define_insn "*add_dtprel22" | |
885 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 886 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
887 | UNSPEC_DTPREL) |
888 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 889 | "TARGET_TLS22" |
5e6c8b64 | 890 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
891 | [(set_attr "itanium_class" "ialu")]) |
892 | ||
893 | (define_expand "load_tprel" | |
894 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 895 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
896 | UNSPEC_TPREL))] |
897 | "" | |
898 | "") | |
899 | ||
900 | (define_insn "*load_tprel64" | |
901 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 902 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
903 | UNSPEC_TPREL))] |
904 | "TARGET_TLS64" | |
905 | "movl %0 = @tprel(%1)" | |
906 | [(set_attr "itanium_class" "long_i")]) | |
907 | ||
908 | (define_insn "*load_tprel22" | |
909 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 910 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
911 | UNSPEC_TPREL))] |
912 | "" | |
913 | "addl %0 = @tprel(%1), r0" | |
914 | [(set_attr "itanium_class" "ialu")]) | |
915 | ||
5e6c8b64 RH |
916 | (define_insn_and_split "*load_tprel_ie" |
917 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 918 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
919 | UNSPEC_TPREL))] |
920 | "" | |
921 | "#" | |
922 | "reload_completed" | |
923 | [(set (match_dup 0) | |
924 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
925 | (match_dup 2))) | |
926 | (set (match_dup 0) (match_dup 3))] | |
927 | { | |
928 | operands[2] = pic_offset_table_rtx; | |
929 | operands[3] = gen_const_mem (DImode, operands[0]); | |
930 | }) | |
931 | ||
932 | (define_insn "*load_ltoff_tprel" | |
933 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 934 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
935 | UNSPEC_LTOFF_TPREL) |
936 | (match_operand:DI 2 "register_operand" "a")))] | |
937 | "" | |
938 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
939 | [(set_attr "itanium_class" "ialu")]) | |
940 | ||
7b6e506e RH |
941 | (define_expand "add_tprel" |
942 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 943 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
944 | UNSPEC_TPREL) |
945 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
946 | "!TARGET_TLS64" |
947 | "") | |
948 | ||
949 | (define_insn "*add_tprel14" | |
950 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 951 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
952 | UNSPEC_TPREL) |
953 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 954 | "TARGET_TLS14" |
5e6c8b64 | 955 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
956 | [(set_attr "itanium_class" "ialu")]) |
957 | ||
958 | (define_insn "*add_tprel22" | |
959 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 960 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
961 | UNSPEC_TPREL) |
962 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 963 | "TARGET_TLS22" |
5e6c8b64 | 964 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
965 | [(set_attr "itanium_class" "ialu")]) |
966 | ||
3f622353 | 967 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
968 | ;; around to play with the second word. However, in order to avoid a |
969 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
970 | ;; in ia64_split_tmode_move. | |
3f622353 | 971 | (define_expand "movti" |
2ffe0e02 ZW |
972 | [(set (match_operand:TI 0 "general_operand" "") |
973 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 974 | "" |
3f622353 | 975 | { |
7b6e506e RH |
976 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
977 | if (!op1) | |
978 | DONE; | |
979 | operands[1] = op1; | |
1d5d7a21 | 980 | }) |
3f622353 | 981 | |
388092d5 | 982 | (define_insn_and_split "movti_internal" |
b6fb7d46 JW |
983 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
984 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 985 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
986 | "@ |
987 | # | |
988 | # | |
989 | ldfp8 %X0 = %1%P1 | |
990 | # | |
991 | #" | |
992 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 993 | [(const_int 0)] |
3f622353 | 994 | { |
f57fc998 | 995 | ia64_split_tmode_move (operands); |
3f622353 | 996 | DONE; |
1d5d7a21 | 997 | } |
388092d5 AB |
998 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown") |
999 | (set_attr "speculable1" "yes") | |
1000 | (set_attr "speculable2" "no, no, yes, no, no")]) | |
e314e331 | 1001 | |
c65ebc55 JW |
1002 | ;; Floating Point Moves |
1003 | ;; | |
1004 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 1005 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
1006 | |
1007 | (define_expand "movsf" | |
1008 | [(set (match_operand:SF 0 "general_operand" "") | |
1009 | (match_operand:SF 1 "general_operand" ""))] | |
1010 | "" | |
c65ebc55 | 1011 | { |
7b6e506e RH |
1012 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1013 | if (!op1) | |
1014 | DONE; | |
1015 | operands[1] = op1; | |
1d5d7a21 | 1016 | }) |
c65ebc55 | 1017 | |
388092d5 | 1018 | (define_insn "movsf_internal" |
735b94a7 SE |
1019 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
1020 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 1021 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1022 | "@ |
1d5d7a21 RH |
1023 | mov %0 = %F1 |
1024 | ldfs %0 = %1%P1 | |
1025 | stfs %0 = %F1%P0 | |
1026 | getf.s %0 = %F1 | |
1027 | setf.s %0 = %1 | |
1028 | mov %0 = %1 | |
1029 | ld4%O1 %0 = %1%P1 | |
735b94a7 SE |
1030 | st4%Q0 %0 = %1%P0 |
1031 | movl %0 = %G1" | |
1032 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1033 | (set_attr "speculable1" "yes") |
735b94a7 | 1034 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 JW |
1035 | |
1036 | (define_expand "movdf" | |
1037 | [(set (match_operand:DF 0 "general_operand" "") | |
1038 | (match_operand:DF 1 "general_operand" ""))] | |
1039 | "" | |
c65ebc55 | 1040 | { |
7b6e506e RH |
1041 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1042 | if (!op1) | |
1043 | DONE; | |
1044 | operands[1] = op1; | |
1d5d7a21 | 1045 | }) |
c65ebc55 | 1046 | |
388092d5 | 1047 | (define_insn "movdf_internal" |
735b94a7 SE |
1048 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r") |
1049 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))] | |
aebf2462 | 1050 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1051 | "@ |
1d5d7a21 RH |
1052 | mov %0 = %F1 |
1053 | ldfd %0 = %1%P1 | |
1054 | stfd %0 = %F1%P0 | |
1055 | getf.d %0 = %F1 | |
1056 | setf.d %0 = %1 | |
1057 | mov %0 = %1 | |
1058 | ld8%O1 %0 = %1%P1 | |
735b94a7 SE |
1059 | st8%Q0 %0 = %1%P0 |
1060 | movl %0 = %G1" | |
1061 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i") | |
388092d5 | 1062 | (set_attr "speculable1" "yes") |
735b94a7 | 1063 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")]) |
c65ebc55 | 1064 | |
3f622353 RH |
1065 | ;; With no offsettable memory references, we've got to have a scratch |
1066 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1067 | (define_expand "movxf" |
1068 | [(set (match_operand:XF 0 "general_operand" "") | |
1069 | (match_operand:XF 1 "general_operand" ""))] | |
1070 | "" | |
e5bde68a | 1071 | { |
4de67c26 JM |
1072 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
1073 | DONE; | |
1d5d7a21 | 1074 | }) |
e5bde68a | 1075 | |
3b572406 | 1076 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1077 | |
388092d5 | 1078 | (define_insn "movxf_internal" |
78d8e0f9 ZW |
1079 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1080 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1081 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1082 | "@ |
1d5d7a21 RH |
1083 | mov %0 = %F1 |
1084 | ldfe %0 = %1%P1 | |
1085 | stfe %0 = %F1%P0" | |
388092d5 AB |
1086 | [(set_attr "itanium_class" "fmisc,fld,stf") |
1087 | (set_attr "speculable1" "yes") | |
1088 | (set_attr "speculable2" "no, yes,no")]) | |
f57fc998 | 1089 | |
4de67c26 JM |
1090 | ;; Same as for movxf, but for RFmode. |
1091 | (define_expand "movrf" | |
1092 | [(set (match_operand:RF 0 "general_operand" "") | |
1093 | (match_operand:RF 1 "general_operand" ""))] | |
1094 | "" | |
1095 | { | |
1096 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
1097 | DONE; | |
1098 | }) | |
1099 | ||
1100 | (define_insn "*movrf_internal" | |
1101 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
1102 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
1103 | "ia64_move_ok (operands[0], operands[1])" | |
1104 | "@ | |
1105 | mov %0 = %F1 | |
1106 | ldf.fill %0 = %1%P1 | |
1107 | stf.spill %0 = %F1%P0" | |
1108 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
1109 | ||
f57fc998 | 1110 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 1111 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1112 | (define_expand "movtf" |
2ffe0e02 ZW |
1113 | [(set (match_operand:TF 0 "general_operand" "") |
1114 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1115 | "" |
1116 | { | |
1117 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1118 | if (!op1) | |
1119 | DONE; | |
1120 | operands[1] = op1; | |
1121 | }) | |
1122 | ||
1123 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 1124 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 1125 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1126 | "ia64_move_ok (operands[0], operands[1])" |
1127 | "#" | |
1128 | "reload_completed" | |
1129 | [(const_int 0)] | |
1130 | { | |
1131 | ia64_split_tmode_move (operands); | |
1132 | DONE; | |
1133 | } | |
1134 | [(set_attr "itanium_class" "unknown") | |
1135 | (set_attr "predicable" "no")]) | |
1136 | ||
c65ebc55 JW |
1137 | \f |
1138 | ;; :::::::::::::::::::: | |
1139 | ;; :: | |
1140 | ;; :: Conversions | |
1141 | ;; :: | |
1142 | ;; :::::::::::::::::::: | |
1143 | ||
1144 | ;; Signed conversions from a smaller integer to a larger integer | |
1145 | ||
1146 | (define_insn "extendqidi2" | |
0551c32d RH |
1147 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1148 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1149 | "" |
1150 | "sxt1 %0 = %1" | |
52e12ad0 | 1151 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1152 | |
1153 | (define_insn "extendhidi2" | |
0551c32d RH |
1154 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1155 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1156 | "" |
1157 | "sxt2 %0 = %1" | |
52e12ad0 | 1158 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1159 | |
1160 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1161 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1162 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1163 | "" |
1164 | "@ | |
1165 | sxt4 %0 = %1 | |
aebf2462 | 1166 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1167 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1168 | |
1169 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1170 | ||
1171 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1172 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1173 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1174 | "" |
1175 | "@ | |
1176 | zxt1 %0 = %1 | |
1177 | ld1%O1 %0 = %1%P1" | |
388092d5 AB |
1178 | [(set_attr "itanium_class" "xtd,ld") |
1179 | (set_attr "speculable1" "yes") | |
1180 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1181 | |
1182 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1183 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1184 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1185 | "" |
1186 | "@ | |
1187 | zxt2 %0 = %1 | |
1188 | ld2%O1 %0 = %1%P1" | |
388092d5 AB |
1189 | [(set_attr "itanium_class" "xtd,ld") |
1190 | (set_attr "speculable1" "yes") | |
1191 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1192 | |
1193 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1194 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1195 | (zero_extend:DI |
655f2eb9 | 1196 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1197 | "" |
1198 | "@ | |
d3f6e07b | 1199 | addp4 %0 = %1, r0 |
c65ebc55 | 1200 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1201 | fmix.r %0 = f0, %1" |
388092d5 AB |
1202 | [(set_attr "itanium_class" "ialu,ld,fmisc") |
1203 | (set_attr "speculable1" "yes") | |
1204 | (set_attr "speculable2" "no, yes,no")]) | |
c65ebc55 JW |
1205 | |
1206 | ;; Convert between floating point types of different sizes. | |
1207 | ||
640cea5f JW |
1208 | ;; At first glance, it would appear that emitting fnorm for an extending |
1209 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1210 | ;; correctly only if the input is properly rounded for its type. In | |
1211 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1212 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1213 | ;; have to emit an fnorm. | |
1214 | ||
e8e20f18 RH |
1215 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1216 | ;; when we can. Should probably use a scheme like has been proposed | |
1217 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1218 | ;; would let combine merge the thing into adjacent insns. See also how the |
1219 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1220 | ;; se_register_operand. | |
c65ebc55 | 1221 | |
640cea5f JW |
1222 | (define_insn "extendsfdf2" |
1223 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
6adb807e | 1224 | (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1225 | "" |
6adb807e | 1226 | "fnorm.d %0 = %F1" |
640cea5f | 1227 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1228 | |
02befdf4 ZW |
1229 | (define_insn "extendsfxf2" |
1230 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1231 | (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1232 | "" |
6adb807e | 1233 | "fnorm %0 = %F1" |
640cea5f | 1234 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1235 | |
02befdf4 ZW |
1236 | (define_insn "extenddfxf2" |
1237 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1238 | (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1239 | "" |
6adb807e | 1240 | "fnorm %0 = %F1" |
640cea5f | 1241 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1242 | |
c65ebc55 | 1243 | (define_insn "truncdfsf2" |
0551c32d | 1244 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1245 | (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1246 | "" |
6adb807e | 1247 | "fnorm.s %0 = %F1" |
52e12ad0 | 1248 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1249 | |
02befdf4 | 1250 | (define_insn "truncxfsf2" |
0551c32d | 1251 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1252 | (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1253 | "" |
6adb807e | 1254 | "fnorm.s %0 = %F1" |
52e12ad0 | 1255 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1256 | |
02befdf4 | 1257 | (define_insn "truncxfdf2" |
0551c32d | 1258 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1259 | (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1260 | "" |
6adb807e | 1261 | "fnorm.d %0 = %F1" |
52e12ad0 | 1262 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1263 | |
1264 | ;; Convert between signed integer types and floating point. | |
1265 | ||
49df2fb8 SE |
1266 | (define_insn "floatdirf2" |
1267 | [(set (match_operand:RF 0 "fr_register_operand" "=f") | |
1268 | (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] | |
1269 | "" | |
1270 | "fcvt.xf %0 = %F1" | |
1271 | [(set_attr "itanium_class" "fcvtfx")]) | |
1272 | ||
02befdf4 ZW |
1273 | (define_insn "floatdixf2" |
1274 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1275 | (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1276 | "" |
6adb807e | 1277 | "fcvt.xf %0 = %F1" |
52e12ad0 | 1278 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1279 | |
1280 | (define_insn "fix_truncsfdi2" | |
0551c32d | 1281 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1282 | (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1283 | "" |
6adb807e | 1284 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1285 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1286 | |
1287 | (define_insn "fix_truncdfdi2" | |
0551c32d | 1288 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1289 | (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1290 | "" |
6adb807e | 1291 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1292 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1293 | |
02befdf4 | 1294 | (define_insn "fix_truncxfdi2" |
0551c32d | 1295 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1296 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1297 | "" |
6adb807e | 1298 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1299 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1300 | |
49df2fb8 | 1301 | (define_insn "fix_truncrfdi2" |
655f2eb9 | 1302 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
49df2fb8 | 1303 | (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1304 | "" |
49df2fb8 | 1305 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1306 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1307 | |
c65ebc55 JW |
1308 | ;; Convert between unsigned integer types and floating point. |
1309 | ||
1310 | (define_insn "floatunsdisf2" | |
0551c32d | 1311 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1312 | (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1313 | "" |
6adb807e | 1314 | "fcvt.xuf.s %0 = %F1" |
52e12ad0 | 1315 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1316 | |
1317 | (define_insn "floatunsdidf2" | |
0551c32d | 1318 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1319 | (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1320 | "" |
6adb807e | 1321 | "fcvt.xuf.d %0 = %F1" |
52e12ad0 | 1322 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1323 | |
02befdf4 ZW |
1324 | (define_insn "floatunsdixf2" |
1325 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1326 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1327 | "" |
6adb807e | 1328 | "fcvt.xuf %0 = %F1" |
52e12ad0 | 1329 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1330 | |
49df2fb8 SE |
1331 | (define_insn "floatunsdirf2" |
1332 | [(set (match_operand:RF 0 "fr_register_operand" "=f") | |
1333 | (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] | |
1334 | "" | |
1335 | "fcvt.xuf %0 = %F1" | |
1336 | [(set_attr "itanium_class" "fcvtfx")]) | |
1337 | ||
c65ebc55 | 1338 | (define_insn "fixuns_truncsfdi2" |
0551c32d | 1339 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1340 | (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1341 | "" |
6adb807e | 1342 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1343 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1344 | |
1345 | (define_insn "fixuns_truncdfdi2" | |
0551c32d | 1346 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1347 | (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1348 | "" |
6adb807e | 1349 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1350 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1351 | |
02befdf4 | 1352 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1353 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1354 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1355 | "" |
6adb807e | 1356 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1357 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1358 | |
49df2fb8 | 1359 | (define_insn "fixuns_truncrfdi2" |
655f2eb9 | 1360 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
49df2fb8 | 1361 | (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1362 | "" |
49df2fb8 | 1363 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1364 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1365 | \f |
1366 | ;; :::::::::::::::::::: | |
1367 | ;; :: | |
1368 | ;; :: Bit field extraction | |
1369 | ;; :: | |
1370 | ;; :::::::::::::::::::: | |
1371 | ||
c65ebc55 | 1372 | (define_insn "extv" |
0551c32d RH |
1373 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1374 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1375 | (match_operand:DI 2 "extr_len_operand" "n") |
1376 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1377 | "" |
1378 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1379 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1380 | |
1381 | (define_insn "extzv" | |
0551c32d RH |
1382 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1383 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1384 | (match_operand:DI 2 "extr_len_operand" "n") |
1385 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1386 | "" |
1387 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1388 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1389 | |
1390 | ;; Insert a bit field. | |
1391 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1392 | ;; Source1 can be 0 or -1. | |
1393 | ;; Source2 can be 0. | |
1394 | ||
1395 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1396 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1397 | ;; where source2 != dest. | |
1398 | ||
1399 | (define_expand "insv" | |
0551c32d | 1400 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1401 | (match_operand:DI 1 "const_int_operand" "") |
1402 | (match_operand:DI 2 "const_int_operand" "")) | |
1403 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1404 | "" | |
c65ebc55 JW |
1405 | { |
1406 | int width = INTVAL (operands[1]); | |
1407 | int shift = INTVAL (operands[2]); | |
1408 | ||
1409 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1410 | pseudo. */ | |
1411 | if (! register_operand (operands[3], DImode) | |
1412 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1413 | operands[3] = force_reg (DImode, operands[3]); | |
1414 | ||
1415 | /* If this is a single dep instruction, we have nothing to do. */ | |
1416 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1417 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1418 | { | |
1419 | /* Check for cases that can be implemented with a mix instruction. */ | |
1420 | if (width == 32 && shift == 0) | |
1421 | { | |
1422 | /* Directly generating the mix4left instruction confuses | |
1423 | optimize_bit_field in function.c. Since this is performing | |
1424 | a useful optimization, we defer generation of the complicated | |
1425 | mix4left RTL to the first splitting phase. */ | |
1426 | rtx tmp = gen_reg_rtx (DImode); | |
1427 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1428 | DONE; | |
1429 | } | |
1430 | else if (width == 32 && shift == 32) | |
1431 | { | |
1432 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1433 | DONE; | |
1434 | } | |
1435 | ||
d2ba6dcf JW |
1436 | /* We could handle remaining cases by emitting multiple dep |
1437 | instructions. | |
1438 | ||
1439 | If we need more than two dep instructions then we lose. A 6 | |
1440 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1441 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1442 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1443 | only one function unit that can execute dep and shr immed. | |
1444 | ||
1445 | If we only need two dep instruction, then we still lose. | |
1446 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1447 | the unnecessary mov, this is still undesirable because it will be | |
1448 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1449 | function unit. */ | |
1450 | ||
c65ebc55 JW |
1451 | FAIL; |
1452 | ||
1453 | #if 0 | |
1454 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1455 | for now. */ | |
1456 | while (width > 16) | |
1457 | { | |
1458 | rtx tmp; | |
1459 | ||
1460 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1461 | operands[3])); | |
1462 | shift += 16; | |
1463 | width -= 16; | |
1464 | tmp = gen_reg_rtx (DImode); | |
1465 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1466 | operands[3] = tmp; | |
1467 | } | |
1468 | operands[1] = GEN_INT (width); | |
1469 | operands[2] = GEN_INT (shift); | |
1470 | #endif | |
1471 | } | |
1d5d7a21 | 1472 | }) |
c65ebc55 JW |
1473 | |
1474 | (define_insn "*insv_internal" | |
0551c32d | 1475 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1476 | (match_operand:DI 1 "const_int_operand" "n") |
1477 | (match_operand:DI 2 "const_int_operand" "n")) | |
1478 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1479 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1480 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1481 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1482 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1483 | |
43a88a8c | 1484 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1485 | (define_insn "*shladdp4_internal" |
1486 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1487 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1488 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1489 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1490 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1491 | "shladdp4 %0 = %1, %2, r0" | |
1492 | [(set_attr "itanium_class" "ialu")]) | |
1493 | ||
041f25e6 | 1494 | (define_insn "*depz_internal" |
0551c32d RH |
1495 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1496 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1497 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1498 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1499 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1500 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1501 | { |
1502 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1503 | return "%,dep.z %0 = %1, %2, %3"; |
1504 | } | |
52e12ad0 | 1505 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1506 | |
c65ebc55 | 1507 | (define_insn "shift_mix4left" |
0551c32d | 1508 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1509 | (const_int 32) (const_int 0)) |
0551c32d RH |
1510 | (match_operand:DI 1 "gr_register_operand" "r")) |
1511 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1512 | "" |
1513 | "#" | |
52e12ad0 | 1514 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1515 | |
c65ebc55 JW |
1516 | (define_split |
1517 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1518 | (const_int 32) (const_int 0)) | |
1519 | (match_operand:DI 1 "register_operand" "")) | |
1520 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1521 | "" |
c65ebc55 JW |
1522 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1523 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1524 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1525 | "operands[3] = operands[2];") | |
1526 | ||
1527 | (define_insn "*mix4left" | |
0551c32d | 1528 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1529 | (const_int 32) (const_int 0)) |
0551c32d | 1530 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1531 | (const_int 32)))] |
1532 | "" | |
1533 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1534 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1535 | |
1536 | (define_insn "mix4right" | |
0551c32d | 1537 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1538 | (const_int 32) (const_int 32)) |
0551c32d | 1539 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1540 | "" |
1541 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1542 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1543 | |
1544 | ;; This is used by the rotrsi3 pattern. | |
1545 | ||
1546 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1547 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1548 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1549 | (ashift:DI (zero_extend:DI | |
1550 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1551 | (const_int 32))))] |
1552 | "" | |
fa9a44e8 | 1553 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1554 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1555 | |
1556 | \f | |
1557 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1558 | ;; :: |
27a9b99d | 1559 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1560 | ;; :: |
1561 | ;; :::::::::::::::::::: | |
1562 | ||
1563 | (define_insn_and_split "andbi3" | |
1564 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1565 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1566 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1567 | "" | |
1568 | "@ | |
1569 | # | |
1570 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1571 | and %0 = %2, %1" | |
1572 | "reload_completed | |
1573 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1574 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1575 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1576 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1577 | (match_dup 0))))] | |
1578 | "" | |
52e12ad0 | 1579 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1580 | |
1581 | (define_insn_and_split "*andcmbi3" | |
1582 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1583 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1584 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1585 | "" | |
1586 | "@ | |
1587 | # | |
967603ef | 1588 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1589 | andcm %0 = %2, %1" |
1590 | "reload_completed | |
1591 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1592 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1593 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1594 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1595 | (match_dup 0))))] | |
1596 | "" | |
52e12ad0 | 1597 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1598 | |
1599 | (define_insn_and_split "iorbi3" | |
1600 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1601 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1602 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1603 | "" | |
1604 | "@ | |
1605 | # | |
1606 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1607 | or %0 = %2, %1" | |
1608 | "reload_completed | |
1609 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1610 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1611 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1612 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1613 | (match_dup 0))))] | |
1614 | "" | |
52e12ad0 | 1615 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1616 | |
1617 | (define_insn_and_split "*iorcmbi3" | |
1618 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1619 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1620 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1621 | "" | |
1622 | "@ | |
1623 | # | |
967603ef | 1624 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1625 | "reload_completed |
1626 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1627 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1628 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1629 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1630 | (match_dup 0))))] | |
1631 | "" | |
52e12ad0 | 1632 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1633 | |
1634 | (define_insn "one_cmplbi2" | |
1635 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1636 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1637 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1638 | "" | |
1639 | "@ | |
1640 | tbit.z %0, %I0 = %1, 0 | |
1641 | xor %0 = 1, %1 | |
1642 | # | |
1643 | #" | |
52e12ad0 | 1644 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1645 | |
1646 | (define_split | |
1647 | [(set (match_operand:BI 0 "register_operand" "") | |
1648 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1649 | (clobber (match_scratch:BI 2 ""))] | |
1650 | "reload_completed | |
1651 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1652 | && rtx_equal_p (operands[0], operands[1])" |
1653 | [(set (match_dup 4) (match_dup 3)) | |
1654 | (set (match_dup 0) (const_int 1)) | |
1655 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1656 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1657 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1658 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1659 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1660 | ||
1661 | (define_split | |
1662 | [(set (match_operand:BI 0 "register_operand" "") | |
1663 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1664 | (clobber (match_scratch:BI 2 ""))] | |
1665 | "reload_completed | |
1666 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1667 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1668 | && ! rtx_equal_p (operands[0], operands[1])" | |
1669 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1670 | (set (match_dup 0) (const_int 0))) | |
1671 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1672 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1673 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1674 | "") |
1675 | ||
1676 | (define_insn "*cmpsi_and_0" | |
1677 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1678 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1679 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1680 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1681 | (match_operand:BI 1 "register_operand" "0")))] | |
1682 | "" | |
1683 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1684 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1685 | |
1686 | (define_insn "*cmpsi_and_1" | |
1687 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1688 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1689 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1690 | (const_int 0)]) | |
1691 | (match_operand:BI 1 "register_operand" "0")))] | |
1692 | "" | |
1693 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1694 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1695 | |
1696 | (define_insn "*cmpsi_andnot_0" | |
1697 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1698 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1699 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1700 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1701 | (match_operand:BI 1 "register_operand" "0")))] | |
1702 | "" | |
1703 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1704 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1705 | |
1706 | (define_insn "*cmpsi_andnot_1" | |
1707 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1708 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1709 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1710 | (const_int 0)])) | |
1711 | (match_operand:BI 1 "register_operand" "0")))] | |
1712 | "" | |
1713 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1714 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1715 | |
1716 | (define_insn "*cmpdi_and_0" | |
1717 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1718 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1719 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1720 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1721 | (match_operand:BI 1 "register_operand" "0")))] | |
1722 | "" | |
1723 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1724 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1725 | |
1726 | (define_insn "*cmpdi_and_1" | |
1727 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1728 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1729 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1730 | (const_int 0)]) | |
1731 | (match_operand:BI 1 "register_operand" "0")))] | |
1732 | "" | |
1733 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1734 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1735 | |
1736 | (define_insn "*cmpdi_andnot_0" | |
1737 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1738 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1739 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1740 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1741 | (match_operand:BI 1 "register_operand" "0")))] | |
1742 | "" | |
1743 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1744 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1745 | |
1746 | (define_insn "*cmpdi_andnot_1" | |
1747 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1748 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1749 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1750 | (const_int 0)])) | |
1751 | (match_operand:BI 1 "register_operand" "0")))] | |
1752 | "" | |
1753 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1754 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1755 | |
1756 | (define_insn "*tbit_and_0" | |
1757 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1758 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1759 | (const_int 1)) | |
1760 | (const_int 0)) | |
c77e04ae | 1761 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1762 | "" |
1763 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1764 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1765 | |
1766 | (define_insn "*tbit_and_1" | |
1767 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1768 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1769 | (const_int 1)) | |
1770 | (const_int 0)) | |
c77e04ae | 1771 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1772 | "" |
1773 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1774 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1775 | |
1776 | (define_insn "*tbit_and_2" | |
1777 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1778 | (and:BI (ne:BI (zero_extract:DI | |
1779 | (match_operand:DI 1 "gr_register_operand" "r") | |
1780 | (const_int 1) | |
5d48891e | 1781 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1782 | (const_int 0)) |
1783 | (match_operand:BI 3 "register_operand" "0")))] | |
1784 | "" | |
1785 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1786 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1787 | |
1788 | (define_insn "*tbit_and_3" | |
1789 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1790 | (and:BI (eq:BI (zero_extract:DI | |
1791 | (match_operand:DI 1 "gr_register_operand" "r") | |
1792 | (const_int 1) | |
5d48891e | 1793 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1794 | (const_int 0)) |
1795 | (match_operand:BI 3 "register_operand" "0")))] | |
1796 | "" | |
1797 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1798 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1799 | |
1800 | (define_insn "*cmpsi_or_0" | |
1801 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1802 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1803 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1804 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1805 | (match_operand:BI 1 "register_operand" "0")))] | |
1806 | "" | |
1807 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1808 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1809 | |
1810 | (define_insn "*cmpsi_or_1" | |
1811 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1812 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1813 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1814 | (const_int 0)]) | |
1815 | (match_operand:BI 1 "register_operand" "0")))] | |
1816 | "" | |
1817 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1818 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1819 | |
1820 | (define_insn "*cmpsi_orcm_0" | |
1821 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1822 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1823 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1824 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1825 | (match_operand:BI 1 "register_operand" "0")))] | |
1826 | "" | |
1827 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1828 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1829 | |
1830 | (define_insn "*cmpsi_orcm_1" | |
1831 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1832 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1833 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1834 | (const_int 0)])) | |
1835 | (match_operand:BI 1 "register_operand" "0")))] | |
1836 | "" | |
1837 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1838 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1839 | |
1840 | (define_insn "*cmpdi_or_0" | |
1841 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1842 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1843 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1844 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1845 | (match_operand:BI 1 "register_operand" "0")))] | |
1846 | "" | |
1847 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1848 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1849 | |
1850 | (define_insn "*cmpdi_or_1" | |
1851 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1852 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1853 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1854 | (const_int 0)]) | |
1855 | (match_operand:BI 1 "register_operand" "0")))] | |
1856 | "" | |
1857 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1858 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1859 | |
1860 | (define_insn "*cmpdi_orcm_0" | |
1861 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1862 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1863 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1864 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1865 | (match_operand:BI 1 "register_operand" "0")))] | |
1866 | "" | |
1867 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1868 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1869 | |
1870 | (define_insn "*cmpdi_orcm_1" | |
1871 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1872 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1873 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1874 | (const_int 0)])) | |
1875 | (match_operand:BI 1 "register_operand" "0")))] | |
1876 | "" | |
1877 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1878 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1879 | |
1880 | (define_insn "*tbit_or_0" | |
1881 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1882 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1883 | (const_int 1)) | |
1884 | (const_int 0)) | |
c77e04ae | 1885 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1886 | "" |
1887 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1888 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1889 | |
1890 | (define_insn "*tbit_or_1" | |
1891 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1892 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1893 | (const_int 1)) | |
1894 | (const_int 0)) | |
c77e04ae | 1895 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1896 | "" |
1897 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1898 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1899 | |
1900 | (define_insn "*tbit_or_2" | |
1901 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1902 | (ior:BI (ne:BI (zero_extract:DI | |
1903 | (match_operand:DI 1 "gr_register_operand" "r") | |
1904 | (const_int 1) | |
5d48891e | 1905 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1906 | (const_int 0)) |
1907 | (match_operand:BI 3 "register_operand" "0")))] | |
1908 | "" | |
1909 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1910 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1911 | |
1912 | (define_insn "*tbit_or_3" | |
1913 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1914 | (ior:BI (eq:BI (zero_extract:DI | |
1915 | (match_operand:DI 1 "gr_register_operand" "r") | |
1916 | (const_int 1) | |
5d48891e | 1917 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1918 | (const_int 0)) |
1919 | (match_operand:BI 3 "register_operand" "0")))] | |
1920 | "" | |
1921 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1922 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1923 | |
1924 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1925 | ||
1926 | (define_split | |
1927 | [(set (match_operand:BI 0 "register_operand" "") | |
1928 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1929 | (const_int 0)) | |
1930 | (match_operand:DI 3 "register_operand" "")) | |
1931 | (const_int 0)))] | |
1932 | "" | |
1933 | [(set (match_dup 0) | |
1934 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1935 | (match_dup 2)))] | |
1936 | "") | |
1937 | ||
1938 | (define_split | |
1939 | [(set (match_operand:BI 0 "register_operand" "") | |
1940 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1941 | (const_int 0)) | |
1942 | (match_operand:DI 3 "register_operand" "")) | |
1943 | (const_int 0)))] | |
1944 | "" | |
1945 | [(set (match_dup 0) | |
1946 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1947 | (match_dup 2))) | |
1948 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1949 | (clobber (scratch))])] | |
1950 | "") | |
1951 | ||
1952 | (define_split | |
1953 | [(set (match_operand:BI 0 "register_operand" "") | |
1954 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1955 | (const_int 0)) | |
1956 | (match_operand:DI 3 "register_operand" "")) | |
1957 | (const_int 0)))] | |
1958 | "" | |
1959 | [(set (match_dup 0) | |
1960 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1961 | (match_dup 2)))] | |
1962 | "") | |
1963 | ||
1964 | (define_split | |
1965 | [(set (match_operand:BI 0 "register_operand" "") | |
1966 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1967 | (const_int 0)) | |
1968 | (match_operand:DI 3 "register_operand" "")) | |
1969 | (const_int 0)))] | |
1970 | "" | |
1971 | [(set (match_dup 0) | |
1972 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1973 | (match_dup 2))) | |
1974 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1975 | (clobber (scratch))])] | |
1976 | "") | |
1977 | ||
1978 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1979 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1980 | ;; nothing bad happens to the comparisons in the meantime. | |
1981 | ;; | |
1982 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1983 | ;; that we're doing height reduction. | |
1984 | ; | |
1985 | ;(define_insn_and_split "" | |
1986 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1987 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1988 | ; [(match_operand 2 "" "") | |
1989 | ; (match_operand 3 "" "")]) | |
1990 | ; (match_operator:BI 4 "comparison_operator" | |
1991 | ; [(match_operand 5 "" "") | |
1992 | ; (match_operand 6 "" "")])) | |
1993 | ; (match_dup 0)))] | |
1994 | ; "flag_schedule_insns" | |
1995 | ; "#" | |
1996 | ; "" | |
1997 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1998 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1999 | ; "") | |
2000 | ; | |
2001 | ;(define_insn_and_split "" | |
2002 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
2003 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
2004 | ; [(match_operand 2 "" "") | |
2005 | ; (match_operand 3 "" "")]) | |
2006 | ; (match_operator:BI 4 "comparison_operator" | |
2007 | ; [(match_operand 5 "" "") | |
2008 | ; (match_operand 6 "" "")])) | |
2009 | ; (match_dup 0)))] | |
2010 | ; "flag_schedule_insns" | |
2011 | ; "#" | |
2012 | ; "" | |
2013 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
2014 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
2015 | ; "") | |
2016 | ; | |
2017 | ;(define_split | |
2018 | ; [(set (match_operand:BI 0 "register_operand" "") | |
2019 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
2020 | ; [(match_operand 2 "" "") | |
2021 | ; (match_operand 3 "" "")]) | |
2022 | ; (match_operand:BI 7 "register_operand" "")) | |
2023 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
2024 | ; [(match_operand 5 "" "") | |
2025 | ; (match_operand 6 "" "")]) | |
2026 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2027 | ; "" | |
2028 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
2029 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
2030 | ; (match_dup 0)))] | |
2031 | ; "") | |
2032 | ; | |
2033 | ;(define_split | |
2034 | ; [(set (match_operand:BI 0 "register_operand" "") | |
2035 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
2036 | ; [(match_operand 2 "" "") | |
2037 | ; (match_operand 3 "" "")]) | |
2038 | ; (match_operand:BI 7 "register_operand" "")) | |
2039 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
2040 | ; [(match_operand 5 "" "") | |
2041 | ; (match_operand 6 "" "")]) | |
2042 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2043 | ; "" | |
2044 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2045 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2046 | ; (match_dup 0)))] | |
2047 | ; "") | |
2048 | ||
2049 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2050 | ;; Note that we'll have already split the predicate copy, which | |
2051 | ;; is kind of a pain, but oh well. | |
2052 | ||
2053 | (define_peephole2 | |
2054 | [(set (match_operand:BI 0 "register_operand" "") | |
2055 | (match_operand:BI 1 "comparison_operator" "")) | |
2056 | (set (match_operand:CCI 2 "register_operand" "") | |
2057 | (match_operand:CCI 3 "register_operand" "")) | |
2058 | (set (match_operand:CCI 4 "register_operand" "") | |
2059 | (match_operand:CCI 5 "register_operand" "")) | |
2060 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2061 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2062 | "REGNO (operands[3]) == REGNO (operands[0]) |
2063 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2064 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2065 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2066 | [(set (match_dup 0) (match_dup 1)) | |
2067 | (set (match_dup 6) (match_dup 7))] | |
2068 | "operands[7] = copy_rtx (operands[1]);") | |
2069 | \f | |
2070 | ;; :::::::::::::::::::: | |
2071 | ;; :: | |
27a9b99d | 2072 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
2073 | ;; :: |
2074 | ;; :::::::::::::::::::: | |
2075 | ||
2076 | (define_insn "mulhi3" | |
2077 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2078 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2079 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2080 | "" | |
2a7ffc85 | 2081 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2082 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2083 | |
2084 | \f | |
2085 | ;; :::::::::::::::::::: | |
c65ebc55 | 2086 | ;; :: |
27a9b99d | 2087 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
2088 | ;; :: |
2089 | ;; :::::::::::::::::::: | |
2090 | ||
058557c4 | 2091 | (define_insn "addsi3" |
0551c32d RH |
2092 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2093 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2094 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2095 | "" |
2096 | "@ | |
1d5d7a21 RH |
2097 | add %0 = %1, %2 |
2098 | adds %0 = %2, %1 | |
2099 | addl %0 = %2, %1" | |
52e12ad0 | 2100 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2101 | |
2102 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2103 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2104 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2105 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2106 | (const_int 1)))] |
2107 | "" | |
2108 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2109 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2110 | |
5527bf14 | 2111 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2112 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2113 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2114 | (const_int 2)) |
2115 | (const_int 1)))] | |
2116 | "" | |
2117 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2118 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2119 | |
058557c4 | 2120 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2121 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2122 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2123 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2124 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2125 | "" |
058557c4 | 2126 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2127 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2128 | |
058557c4 | 2129 | (define_insn "subsi3" |
0551c32d RH |
2130 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2131 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2132 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2133 | "" |
2134 | "sub %0 = %1, %2" | |
52e12ad0 | 2135 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2136 | |
2137 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2138 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2139 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2140 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2141 | "" |
2142 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2143 | [(set_attr "itanium_class" "ialu")]) |
2144 | ||
2145 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2146 | |
058557c4 | 2147 | (define_insn "mulsi3" |
0551c32d | 2148 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2149 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2150 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2151 | "" |
aebf2462 | 2152 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2153 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2154 | |
655f2eb9 | 2155 | (define_insn "maddsi4" |
11a13704 RH |
2156 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2157 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2158 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2159 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2160 | "" | |
aebf2462 | 2161 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2162 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2163 | |
058557c4 | 2164 | (define_insn "negsi2" |
0551c32d RH |
2165 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2166 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2167 | "" |
2168 | "sub %0 = r0, %1" | |
52e12ad0 | 2169 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2170 | |
2171 | (define_expand "abssi2" | |
2172 | [(set (match_dup 2) | |
f2f90c63 | 2173 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2174 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2175 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2176 | (neg:SI (match_dup 1)) |
2177 | (match_dup 1)))] | |
c65ebc55 | 2178 | "" |
1d5d7a21 | 2179 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2180 | |
2181 | (define_expand "sminsi3" | |
2182 | [(set (match_dup 3) | |
f2f90c63 | 2183 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2184 | (match_operand:SI 2 "gr_register_operand" ""))) |
2185 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2186 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2187 | (match_dup 2) (match_dup 1)))] |
2188 | "" | |
1d5d7a21 | 2189 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2190 | |
2191 | (define_expand "smaxsi3" | |
2192 | [(set (match_dup 3) | |
f2f90c63 | 2193 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2194 | (match_operand:SI 2 "gr_register_operand" ""))) |
2195 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2196 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2197 | (match_dup 1) (match_dup 2)))] |
2198 | "" | |
1d5d7a21 | 2199 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2200 | |
2201 | (define_expand "uminsi3" | |
2202 | [(set (match_dup 3) | |
f2f90c63 | 2203 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2204 | (match_operand:SI 2 "gr_register_operand" ""))) |
2205 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2206 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2207 | (match_dup 2) (match_dup 1)))] |
2208 | "" | |
1d5d7a21 | 2209 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2210 | |
2211 | (define_expand "umaxsi3" | |
2212 | [(set (match_dup 3) | |
f2f90c63 | 2213 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2214 | (match_operand:SI 2 "gr_register_operand" ""))) |
2215 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2216 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2217 | (match_dup 1) (match_dup 2)))] |
2218 | "" | |
1d5d7a21 | 2219 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2220 | \f |
2221 | ;; :::::::::::::::::::: | |
2222 | ;; :: | |
27a9b99d | 2223 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2224 | ;; :: |
2225 | ;; :::::::::::::::::::: | |
2226 | ||
2227 | (define_insn "adddi3" | |
0551c32d RH |
2228 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2229 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2230 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2231 | "" |
2232 | "@ | |
1d5d7a21 RH |
2233 | add %0 = %1, %2 |
2234 | adds %0 = %2, %1 | |
2235 | addl %0 = %2, %1" | |
52e12ad0 | 2236 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2237 | |
2238 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2239 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2240 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2241 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2242 | (const_int 1)))] |
2243 | "" | |
2244 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2245 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2246 | |
5527bf14 RH |
2247 | ;; This has some of the same problems as shladd. We let the shladd |
2248 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2249 | ;; a register, but not more ugliness here. | |
2250 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2251 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2252 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2253 | (const_int 2)) |
2254 | (const_int 1)))] | |
2255 | "" | |
2256 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2257 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2258 | |
c65ebc55 | 2259 | (define_insn "subdi3" |
0551c32d RH |
2260 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2261 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2262 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2263 | "" |
2264 | "sub %0 = %1, %2" | |
52e12ad0 | 2265 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2266 | |
2267 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2268 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2269 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2270 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2271 | "" |
2272 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2273 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2274 | |
cee58bc0 RH |
2275 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2276 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2277 | (define_insn "muldi3" |
0551c32d | 2278 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2279 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2280 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2281 | "" |
aebf2462 | 2282 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2283 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2284 | |
2285 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2286 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2287 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2288 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2289 | ;; here so that it will be present just in case register elimination gives us | |
2290 | ;; the funny result. | |
2291 | ||
2292 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2293 | ||
2294 | ;; ??? Maybe we should change how adds are canonicalized. | |
2295 | ||
655f2eb9 | 2296 | (define_insn "madddi4" |
0551c32d | 2297 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2298 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2299 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2300 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2301 | (clobber (match_scratch:DI 4 "=X"))] |
2302 | "" | |
aebf2462 | 2303 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2304 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2305 | |
2306 | ;; This can be created by register elimination if operand3 of shladd is an | |
2307 | ;; eliminable register or has reg_equiv_constant set. | |
2308 | ||
2309 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2310 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2311 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2312 | ;; incorrectly. |
2313 | ||
655f2eb9 | 2314 | (define_insn "*madddi4_elim" |
c65ebc55 | 2315 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2316 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2317 | (match_operand:DI 2 "register_operand" "f")) | |
2318 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2319 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2320 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2321 | "reload_in_progress" |
2322 | "#" | |
52e12ad0 | 2323 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2324 | |
c65ebc55 JW |
2325 | (define_split |
2326 | [(set (match_operand:DI 0 "register_operand" "") | |
2327 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2328 | (match_operand:DI 2 "register_operand" "")) | |
2329 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2330 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2331 | (clobber (match_scratch:DI 5 ""))] |
2332 | "reload_completed" | |
2333 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2334 | (match_dup 3))) | |
2335 | (clobber (match_dup 0))]) | |
c65ebc55 | 2336 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2337 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2338 | "") | |
2339 | ||
c65ebc55 | 2340 | (define_insn "smuldi3_highpart" |
0551c32d | 2341 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2342 | (truncate:DI |
2343 | (lshiftrt:TI | |
0551c32d | 2344 | (mult:TI (sign_extend:TI |
6adb807e | 2345 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2346 | (sign_extend:TI |
6adb807e | 2347 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2348 | (const_int 64))))] |
2349 | "" | |
6adb807e | 2350 | "xmpy.h %0 = %F1, %F2" |
52e12ad0 | 2351 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2352 | |
2353 | (define_insn "umuldi3_highpart" | |
0551c32d | 2354 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2355 | (truncate:DI |
2356 | (lshiftrt:TI | |
0551c32d | 2357 | (mult:TI (zero_extend:TI |
6adb807e | 2358 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2359 | (zero_extend:TI |
6adb807e | 2360 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2361 | (const_int 64))))] |
2362 | "" | |
6adb807e | 2363 | "xmpy.hu %0 = %F1, %F2" |
52e12ad0 | 2364 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2365 | |
2366 | (define_insn "negdi2" | |
0551c32d RH |
2367 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2368 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2369 | "" |
2370 | "sub %0 = r0, %1" | |
52e12ad0 | 2371 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2372 | |
2373 | (define_expand "absdi2" | |
2374 | [(set (match_dup 2) | |
f2f90c63 | 2375 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2376 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2377 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2378 | (neg:DI (match_dup 1)) |
2379 | (match_dup 1)))] | |
c65ebc55 | 2380 | "" |
1d5d7a21 | 2381 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2382 | |
2383 | (define_expand "smindi3" | |
2384 | [(set (match_dup 3) | |
f2f90c63 | 2385 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2386 | (match_operand:DI 2 "gr_register_operand" ""))) |
2387 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2388 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2389 | (match_dup 2) (match_dup 1)))] |
2390 | "" | |
1d5d7a21 | 2391 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2392 | |
2393 | (define_expand "smaxdi3" | |
2394 | [(set (match_dup 3) | |
f2f90c63 | 2395 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2396 | (match_operand:DI 2 "gr_register_operand" ""))) |
2397 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2398 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2399 | (match_dup 1) (match_dup 2)))] |
2400 | "" | |
1d5d7a21 | 2401 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2402 | |
2403 | (define_expand "umindi3" | |
2404 | [(set (match_dup 3) | |
f2f90c63 | 2405 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2406 | (match_operand:DI 2 "gr_register_operand" ""))) |
2407 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2408 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2409 | (match_dup 2) (match_dup 1)))] |
2410 | "" | |
1d5d7a21 | 2411 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2412 | |
2413 | (define_expand "umaxdi3" | |
2414 | [(set (match_dup 3) | |
f2f90c63 | 2415 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2416 | (match_operand:DI 2 "gr_register_operand" ""))) |
2417 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2418 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2419 | (match_dup 1) (match_dup 2)))] |
2420 | "" | |
1d5d7a21 | 2421 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2422 | |
2423 | (define_expand "ffsdi2" | |
2424 | [(set (match_dup 6) | |
f2f90c63 | 2425 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2426 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2427 | (set (match_dup 5) (const_int 0)) | |
2428 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2429 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2430 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2431 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2432 | (match_dup 5) (match_dup 4)))] |
2433 | "" | |
c65ebc55 JW |
2434 | { |
2435 | operands[2] = gen_reg_rtx (DImode); | |
2436 | operands[3] = gen_reg_rtx (DImode); | |
2437 | operands[4] = gen_reg_rtx (DImode); | |
2438 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2439 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2440 | }) |
c65ebc55 | 2441 | |
c407570a RH |
2442 | (define_expand "ctzdi2" |
2443 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2444 | (const_int -1))) | |
2445 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2446 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2447 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2448 | (popcount:DI (match_dup 4)))] | |
2449 | "" | |
2450 | { | |
2451 | operands[2] = gen_reg_rtx (DImode); | |
2452 | operands[3] = gen_reg_rtx (DImode); | |
2453 | operands[4] = gen_reg_rtx (DImode); | |
2454 | }) | |
2455 | ||
c407570a RH |
2456 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2457 | (define_expand "clzdi2" | |
2458 | [(set (match_dup 2) | |
6adb807e | 2459 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))) |
c407570a RH |
2460 | (set (match_dup 3) |
2461 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2462 | (set (match_dup 4) (const_int 65598)) | |
2463 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2464 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2465 | "" |
c407570a | 2466 | { |
02befdf4 | 2467 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2468 | operands[3] = gen_reg_rtx (DImode); |
2469 | operands[4] = gen_reg_rtx (DImode); | |
2470 | }) | |
2471 | ||
2472 | (define_insn "popcountdi2" | |
0551c32d | 2473 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2474 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2475 | "" |
2476 | "popcnt %0 = %1" | |
52e12ad0 | 2477 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2478 | |
ff848f0e RS |
2479 | (define_insn "bswapdi2" |
2480 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2481 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2482 | "" | |
2483 | "mux1 %0 = %1, @rev" | |
2484 | [(set_attr "itanium_class" "mmshf")]) | |
2485 | ||
02befdf4 | 2486 | (define_insn "*getf_exp_xf" |
c407570a | 2487 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6adb807e | 2488 | (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")] |
c407570a | 2489 | UNSPEC_GETF_EXP))] |
02befdf4 | 2490 | "" |
6adb807e | 2491 | "getf.exp %0 = %F1" |
c407570a | 2492 | [(set_attr "itanium_class" "frfr")]) |
c65ebc55 JW |
2493 | \f |
2494 | ;; :::::::::::::::::::: | |
2495 | ;; :: | |
27a9b99d | 2496 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2497 | ;; :: |
2498 | ;; :::::::::::::::::::: | |
2499 | ||
2500 | (define_insn "addti3" | |
2501 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2502 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2503 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2504 | (clobber (match_scratch:BI 3 "=&c"))] | |
2505 | "" | |
2506 | "#" | |
2507 | [(set_attr "itanium_class" "unknown")]) | |
2508 | ||
2509 | (define_split | |
2510 | [(set (match_operand:TI 0 "register_operand" "") | |
2511 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2512 | (match_operand:TI 2 "register_operand" ""))) | |
2513 | (clobber (match_scratch:BI 3 ""))] | |
2514 | "reload_completed" | |
2515 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2516 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2517 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2518 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2519 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2520 | (set (match_dup 4) | |
2521 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2522 | (const_int 1))))] | |
2523 | { | |
2524 | operands[4] = gen_highpart (DImode, operands[0]); | |
2525 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2526 | operands[5] = gen_highpart (DImode, operands[1]); | |
2527 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2528 | operands[6] = gen_highpart (DImode, operands[2]); | |
2529 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2530 | }) | |
2531 | ||
2532 | (define_split | |
2533 | [(set (match_operand:TI 0 "register_operand" "") | |
2534 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2535 | (match_operand:TI 2 "immediate_operand" ""))) | |
2536 | (clobber (match_scratch:BI 3 ""))] | |
2537 | "reload_completed" | |
2538 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2539 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2540 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2541 | (set (match_dup 4) | |
2542 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2543 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2544 | (set (match_dup 4) | |
2545 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2546 | { | |
2547 | operands[4] = gen_highpart (DImode, operands[0]); | |
2548 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2549 | operands[5] = gen_highpart (DImode, operands[1]); | |
2550 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2551 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2552 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2553 | }) | |
2554 | ||
2555 | (define_insn "subti3" | |
2556 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2557 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2558 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2559 | (clobber (match_scratch:BI 3 "=&c"))] | |
2560 | "" | |
2561 | "#" | |
2562 | [(set_attr "itanium_class" "unknown")]) | |
2563 | ||
2564 | (define_split | |
2565 | [(set (match_operand:TI 0 "register_operand" "") | |
2566 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2567 | (match_operand:TI 2 "register_operand" ""))) | |
516e2f1c | 2568 | (clobber (match_scratch:BI 3 ""))] |
a71aef0b JB |
2569 | "reload_completed" |
2570 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2571 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2572 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2573 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2574 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2575 | (set (match_dup 4) | |
2576 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2577 | { | |
2578 | operands[4] = gen_highpart (DImode, operands[0]); | |
2579 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2580 | operands[5] = gen_highpart (DImode, operands[1]); | |
2581 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2582 | operands[6] = gen_highpart (DImode, operands[2]); | |
2583 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2584 | }) | |
2585 | ||
2586 | (define_split | |
2587 | [(set (match_operand:TI 0 "register_operand" "") | |
2588 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2589 | (match_operand:TI 2 "register_operand" ""))) | |
516e2f1c | 2590 | (clobber (match_scratch:BI 3 ""))] |
13f70342 | 2591 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2592 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2593 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2594 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2595 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2596 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2597 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2598 | { | |
2599 | operands[4] = gen_highpart (DImode, operands[0]); | |
2600 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2601 | operands[5] = gen_highpart (DImode, operands[2]); | |
2602 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2603 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2604 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2605 | }) | |
2606 | ||
2607 | (define_expand "mulditi3" | |
2608 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2609 | (mult:TI (sign_extend:TI | |
6adb807e | 2610 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2611 | (sign_extend:TI |
6adb807e | 2612 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2613 | "" |
2614 | "") | |
2615 | ||
2616 | (define_insn_and_split "*mulditi3_internal" | |
2617 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2618 | (mult:TI (sign_extend:TI | |
6adb807e | 2619 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2620 | (sign_extend:TI |
6adb807e | 2621 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2622 | "" |
2623 | "#" | |
2624 | "reload_completed" | |
2625 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2626 | (set (match_dup 3) (truncate:DI | |
2627 | (lshiftrt:TI | |
2628 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2629 | (sign_extend:TI (match_dup 2))) | |
2630 | (const_int 64))))] | |
2631 | { | |
2632 | operands[3] = gen_highpart (DImode, operands[0]); | |
2633 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2634 | } | |
2635 | [(set_attr "itanium_class" "unknown")]) | |
2636 | ||
2637 | (define_expand "umulditi3" | |
2638 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2639 | (mult:TI (zero_extend:TI | |
6adb807e | 2640 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2641 | (zero_extend:TI |
6adb807e | 2642 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2643 | "" |
2644 | "") | |
2645 | ||
2646 | (define_insn_and_split "*umulditi3_internal" | |
2647 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2648 | (mult:TI (zero_extend:TI | |
6adb807e | 2649 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2650 | (zero_extend:TI |
6adb807e | 2651 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2652 | "" |
2653 | "#" | |
2654 | "reload_completed" | |
2655 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2656 | (set (match_dup 3) (truncate:DI | |
2657 | (lshiftrt:TI | |
2658 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2659 | (zero_extend:TI (match_dup 2))) | |
2660 | (const_int 64))))] | |
2661 | { | |
2662 | operands[3] = gen_highpart (DImode, operands[0]); | |
2663 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2664 | } | |
2665 | [(set_attr "itanium_class" "unknown")]) | |
2666 | ||
2667 | (define_insn_and_split "negti2" | |
2668 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2669 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2670 | (clobber (match_scratch:BI 2 "=&c"))] | |
2671 | "" | |
2672 | "#" | |
2673 | "reload_completed" | |
2674 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
2675 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
2676 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
2677 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
2678 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
2679 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
2680 | { | |
2681 | operands[3] = gen_highpart (DImode, operands[0]); | |
2682 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2683 | operands[4] = gen_highpart (DImode, operands[1]); | |
2684 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2685 | } | |
2686 | [(set_attr "itanium_class" "unknown")]) | |
2687 | \f | |
2688 | ;; :::::::::::::::::::: | |
2689 | ;; :: | |
27a9b99d | 2690 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
2691 | ;; :: |
2692 | ;; :::::::::::::::::::: | |
2693 | ||
2694 | (define_insn "addsf3" | |
0551c32d | 2695 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
33974673 SE |
2696 | (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "%fG") |
2697 | (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
c65ebc55 | 2698 | "" |
6adb807e | 2699 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 2700 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2701 | |
2702 | (define_insn "subsf3" | |
0551c32d RH |
2703 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2704 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
33974673 | 2705 | (match_operand:SF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] |
c65ebc55 | 2706 | "" |
aebf2462 | 2707 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2708 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2709 | |
2710 | (define_insn "mulsf3" | |
0551c32d | 2711 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2712 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2713 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2714 | "" |
6adb807e | 2715 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 2716 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2717 | |
2718 | (define_insn "abssf2" | |
0551c32d | 2719 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2720 | (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2721 | "" |
6adb807e | 2722 | "fabs %0 = %F1" |
52e12ad0 | 2723 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2724 | |
2725 | (define_insn "negsf2" | |
0551c32d | 2726 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2727 | (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2728 | "" |
6adb807e | 2729 | "fneg %0 = %F1" |
52e12ad0 | 2730 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2731 | |
2732 | (define_insn "*nabssf2" | |
0551c32d | 2733 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2734 | (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 2735 | "" |
6adb807e | 2736 | "fnegabs %0 = %F1" |
52e12ad0 | 2737 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2738 | |
046625fa RH |
2739 | (define_insn "copysignsf3" |
2740 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2741 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2742 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2743 | UNSPEC_COPYSIGN))] | |
2744 | "" | |
2745 | "fmerge.s %0 = %F2, %F1" | |
2746 | [(set_attr "itanium_class" "fmisc")]) | |
2747 | ||
2748 | (define_insn "*ncopysignsf3" | |
2749 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2750 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2751 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2752 | UNSPEC_COPYSIGN)))] | |
2753 | "" | |
2754 | "fmerge.ns %0 = %F2, %F1" | |
2755 | [(set_attr "itanium_class" "fmisc")]) | |
2756 | ||
7ae4d8d4 | 2757 | (define_insn "sminsf3" |
0551c32d | 2758 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2759 | (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2760 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2761 | "" |
6adb807e | 2762 | "fmin %0 = %F1, %F2" |
52e12ad0 | 2763 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2764 | |
7ae4d8d4 | 2765 | (define_insn "smaxsf3" |
0551c32d | 2766 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 2767 | (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2768 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2769 | "" |
6adb807e | 2770 | "fmax %0 = %F1, %F2" |
52e12ad0 | 2771 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2772 | |
c65ebc55 | 2773 | (define_insn "*nmulsf3" |
0551c32d | 2774 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
2775 | (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
2776 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 2777 | "" |
6adb807e | 2778 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 2779 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2780 | |
46935749 RH |
2781 | (define_insn "fmasf4" |
2782 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2783 | (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2784 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") | |
2785 | (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
2786 | "" | |
2787 | "fma.s %0 = %F1, %F2, %F3" | |
2788 | [(set_attr "itanium_class" "fmac")]) | |
2789 | ||
f19f1e5e | 2790 | (define_insn "fmssf4" |
46935749 RH |
2791 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2792 | (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2793 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") | |
2794 | (neg:SF | |
2795 | (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
2796 | "" | |
2797 | "fms.s %0 = %F1, %F2, %F3" | |
2798 | [(set_attr "itanium_class" "fmac")]) | |
2799 | ||
f19f1e5e | 2800 | (define_insn "fnmasf4" |
46935749 RH |
2801 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2802 | (fma:SF (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")) | |
2803 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") | |
2804 | (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
2805 | "" | |
2806 | "fnma.s %0 = %F1, %F2, %F3" | |
2807 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 JW |
2808 | \f |
2809 | ;; :::::::::::::::::::: | |
2810 | ;; :: | |
27a9b99d | 2811 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
2812 | ;; :: |
2813 | ;; :::::::::::::::::::: | |
2814 | ||
2815 | (define_insn "adddf3" | |
0551c32d | 2816 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
33974673 SE |
2817 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG") |
2818 | (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
c65ebc55 | 2819 | "" |
6adb807e | 2820 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 2821 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2822 | |
26102535 RH |
2823 | (define_insn "*adddf3_trunc" |
2824 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2825 | (float_truncate:SF | |
33974673 SE |
2826 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "%fG") |
2827 | (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
26102535 | 2828 | "" |
6adb807e | 2829 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 2830 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2831 | |
c65ebc55 | 2832 | (define_insn "subdf3" |
0551c32d RH |
2833 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2834 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
33974673 | 2835 | (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ")))] |
c65ebc55 | 2836 | "" |
aebf2462 | 2837 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2838 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2839 | |
26102535 RH |
2840 | (define_insn "*subdf3_trunc" |
2841 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2842 | (float_truncate:SF | |
2843 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
33974673 | 2844 | (match_operand:DF 2 "fr_reg_or_signed_fp01_operand" "fZ"))))] |
26102535 | 2845 | "" |
aebf2462 | 2846 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2847 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2848 | |
c65ebc55 | 2849 | (define_insn "muldf3" |
0551c32d | 2850 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2851 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2852 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2853 | "" |
6adb807e | 2854 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 2855 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2856 | |
26102535 RH |
2857 | (define_insn "*muldf3_trunc" |
2858 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2859 | (float_truncate:SF | |
6adb807e SE |
2860 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2861 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
26102535 | 2862 | "" |
6adb807e | 2863 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 2864 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2865 | |
c65ebc55 | 2866 | (define_insn "absdf2" |
0551c32d | 2867 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2868 | (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2869 | "" |
6adb807e | 2870 | "fabs %0 = %F1" |
52e12ad0 | 2871 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2872 | |
2873 | (define_insn "negdf2" | |
0551c32d | 2874 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2875 | (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2876 | "" |
6adb807e | 2877 | "fneg %0 = %F1" |
52e12ad0 | 2878 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2879 | |
2880 | (define_insn "*nabsdf2" | |
0551c32d | 2881 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2882 | (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 2883 | "" |
6adb807e | 2884 | "fnegabs %0 = %F1" |
52e12ad0 | 2885 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2886 | |
046625fa RH |
2887 | (define_insn "copysigndf3" |
2888 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2889 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2890 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2891 | UNSPEC_COPYSIGN))] | |
2892 | "" | |
2893 | "fmerge.s %0 = %F2, %F1" | |
2894 | [(set_attr "itanium_class" "fmisc")]) | |
2895 | ||
2896 | (define_insn "*ncopysigndf3" | |
2897 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2898 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2899 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2900 | UNSPEC_COPYSIGN)))] | |
2901 | "" | |
2902 | "fmerge.ns %0 = %F2, %F1" | |
2903 | [(set_attr "itanium_class" "fmisc")]) | |
2904 | ||
7ae4d8d4 | 2905 | (define_insn "smindf3" |
0551c32d | 2906 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2907 | (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2908 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2909 | "" |
6adb807e | 2910 | "fmin %0 = %F1, %F2" |
52e12ad0 | 2911 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2912 | |
7ae4d8d4 | 2913 | (define_insn "smaxdf3" |
0551c32d | 2914 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 2915 | (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 2916 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2917 | "" |
6adb807e | 2918 | "fmax %0 = %F1, %F2" |
52e12ad0 | 2919 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2920 | |
c65ebc55 | 2921 | (define_insn "*nmuldf3" |
0551c32d | 2922 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
2923 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2924 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 2925 | "" |
6adb807e | 2926 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 2927 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2928 | |
26102535 RH |
2929 | (define_insn "*nmuldf3_trunc" |
2930 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2931 | (float_truncate:SF | |
6adb807e SE |
2932 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
2933 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
26102535 | 2934 | "" |
6adb807e | 2935 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 2936 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2937 | |
46935749 RH |
2938 | (define_insn "fmadf4" |
2939 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2940 | (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2941 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2942 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
2943 | "" | |
2944 | "fma.d %0 = %F1, %F2, %F3" | |
2945 | [(set_attr "itanium_class" "fmac")]) | |
2946 | ||
f19f1e5e RH |
2947 | (define_insn "*fmadf_trunc_sf" |
2948 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2949 | (float_truncate:SF | |
2950 | (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2951 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2952 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
2953 | "" | |
2954 | "fma.s %0 = %F1, %F2, %F3" | |
2955 | [(set_attr "itanium_class" "fmac")]) | |
2956 | ||
2957 | (define_insn "fmsdf4" | |
46935749 RH |
2958 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2959 | (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2960 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2961 | (neg:DF | |
2962 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
2963 | "" | |
2964 | "fms.d %0 = %F1, %F2, %F3" | |
2965 | [(set_attr "itanium_class" "fmac")]) | |
2966 | ||
f19f1e5e RH |
2967 | (define_insn "*fmsdf_trunc_sf" |
2968 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2969 | (float_truncate:SF | |
2970 | (fma:DF | |
2971 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2972 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2973 | (neg:DF | |
2974 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))] | |
2975 | "" | |
2976 | "fms.s %0 = %F1, %F2, %F3" | |
2977 | [(set_attr "itanium_class" "fmac")]) | |
2978 | ||
2979 | (define_insn "fnmadf4" | |
46935749 RH |
2980 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2981 | (fma:DF (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")) | |
2982 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2983 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
2984 | "" | |
2985 | "fnma.d %0 = %F1, %F2, %F3" | |
2986 | [(set_attr "itanium_class" "fmac")]) | |
f19f1e5e RH |
2987 | |
2988 | (define_insn "*fnmadf_trunc_sf" | |
2989 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2990 | (float_truncate:SF | |
2991 | (fma:DF | |
2992 | (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")) | |
2993 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") | |
2994 | (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
2995 | "" | |
2996 | "fnma.s %0 = %F1, %F2, %F3" | |
2997 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 RH |
2998 | \f |
2999 | ;; :::::::::::::::::::: | |
3000 | ;; :: | |
27a9b99d | 3001 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3002 | ;; :: |
3003 | ;; :::::::::::::::::::: | |
3004 | ||
02befdf4 ZW |
3005 | (define_insn "addxf3" |
3006 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
33974673 SE |
3007 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") |
3008 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))] | |
02befdf4 | 3009 | "" |
aebf2462 | 3010 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3011 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3012 | |
02befdf4 | 3013 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3014 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3015 | (float_truncate:SF | |
33974673 SE |
3016 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") |
3017 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] | |
02befdf4 | 3018 | "" |
aebf2462 | 3019 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3020 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3021 | |
02befdf4 | 3022 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3023 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3024 | (float_truncate:DF | |
33974673 SE |
3025 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "%fG") |
3026 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] | |
02befdf4 | 3027 | "" |
aebf2462 | 3028 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3029 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3030 | |
02befdf4 ZW |
3031 | (define_insn "subxf3" |
3032 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3033 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
33974673 | 3034 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ")))] |
02befdf4 | 3035 | "" |
aebf2462 | 3036 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3037 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3038 | |
02befdf4 | 3039 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3040 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3041 | (float_truncate:SF | |
02befdf4 | 3042 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
33974673 | 3043 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] |
02befdf4 | 3044 | "" |
aebf2462 | 3045 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3046 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3047 | |
02befdf4 | 3048 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3049 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3050 | (float_truncate:DF | |
02befdf4 | 3051 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
33974673 | 3052 | (match_operand:XF 2 "xfreg_or_signed_fp01_operand" "fZ"))))] |
02befdf4 | 3053 | "" |
aebf2462 | 3054 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3055 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3056 | |
02befdf4 ZW |
3057 | (define_insn "mulxf3" |
3058 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3059 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3060 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3061 | "" | |
aebf2462 | 3062 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3063 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3064 | |
02befdf4 | 3065 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3066 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3067 | (float_truncate:SF | |
02befdf4 ZW |
3068 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3069 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3070 | "" | |
aebf2462 | 3071 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3072 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3073 | |
02befdf4 | 3074 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3075 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3076 | (float_truncate:DF | |
02befdf4 ZW |
3077 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3078 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3079 | "" | |
aebf2462 | 3080 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3081 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3082 | |
02befdf4 ZW |
3083 | (define_insn "absxf2" |
3084 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3085 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3086 | "" | |
aebf2462 | 3087 | "fabs %0 = %F1" |
52e12ad0 | 3088 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3089 | |
02befdf4 ZW |
3090 | (define_insn "negxf2" |
3091 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3092 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3093 | "" | |
aebf2462 | 3094 | "fneg %0 = %F1" |
52e12ad0 | 3095 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3096 | |
02befdf4 ZW |
3097 | (define_insn "*nabsxf2" |
3098 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3099 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3100 | "" | |
aebf2462 | 3101 | "fnegabs %0 = %F1" |
52e12ad0 | 3102 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3103 | |
046625fa RH |
3104 | (define_insn "copysignxf3" |
3105 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3106 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3107 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3108 | UNSPEC_COPYSIGN))] | |
3109 | "" | |
3110 | "fmerge.s %0 = %F2, %F1" | |
3111 | [(set_attr "itanium_class" "fmisc")]) | |
3112 | ||
3113 | (define_insn "*ncopysignxf3" | |
3114 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3115 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3116 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3117 | UNSPEC_COPYSIGN)))] | |
3118 | "" | |
3119 | "fmerge.ns %0 = %F2, %F1" | |
3120 | [(set_attr "itanium_class" "fmisc")]) | |
3121 | ||
7ae4d8d4 | 3122 | (define_insn "sminxf3" |
02befdf4 ZW |
3123 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3124 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3125 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3126 | "" | |
aebf2462 | 3127 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3128 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3129 | |
7ae4d8d4 | 3130 | (define_insn "smaxxf3" |
02befdf4 ZW |
3131 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3132 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3133 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3134 | "" | |
aebf2462 | 3135 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3136 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3137 | |
02befdf4 ZW |
3138 | (define_insn "*nmulxf3" |
3139 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3140 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3141 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3142 | "" | |
aebf2462 | 3143 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3144 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3145 | |
02befdf4 | 3146 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3147 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3148 | (float_truncate:SF | |
02befdf4 ZW |
3149 | (neg:XF (mult:XF |
3150 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3151 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3152 | "" | |
aebf2462 | 3153 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3154 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3155 | |
02befdf4 | 3156 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3157 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3158 | (float_truncate:DF | |
02befdf4 ZW |
3159 | (neg:XF (mult:XF |
3160 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3161 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3162 | "" | |
aebf2462 | 3163 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3164 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3165 | |
46935749 RH |
3166 | (define_insn "fmaxf4" |
3167 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3168 | (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3169 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3170 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
3171 | "" | |
3172 | "fma %0 = %F1, %F2, %F3" | |
3173 | [(set_attr "itanium_class" "fmac")]) | |
3174 | ||
f19f1e5e RH |
3175 | (define_insn "*fmaxf_trunc_<mode>" |
3176 | [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f") | |
3177 | (float_truncate:MODE_SDF | |
3178 | (fma:XF | |
3179 | (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3180 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3181 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
3182 | "" | |
3183 | "fma<suffix> %0 = %F1, %F2, %F3" | |
3184 | [(set_attr "itanium_class" "fmac")]) | |
3185 | ||
3186 | (define_insn "fmsxf4" | |
46935749 RH |
3187 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3188 | (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3189 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3190 | (neg:XF | |
3191 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
3192 | "" | |
3193 | "fms %0 = %F1, %F2, %F3" | |
3194 | [(set_attr "itanium_class" "fmac")]) | |
3195 | ||
f19f1e5e RH |
3196 | (define_insn "*fmsxf_trunc_<mode>" |
3197 | [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f") | |
3198 | (float_truncate:MODE_SDF | |
3199 | (fma:XF | |
3200 | (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3201 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3202 | (neg:XF | |
3203 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))))] | |
3204 | "" | |
3205 | "fms<suffix> %0 = %F1, %F2, %F3" | |
3206 | [(set_attr "itanium_class" "fmac")]) | |
3207 | ||
3208 | (define_insn "fnmaxf4" | |
46935749 RH |
3209 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3210 | (fma:XF (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")) | |
3211 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3212 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] | |
3213 | "" | |
3214 | "fnma %0 = %F1, %F2, %F3" | |
3215 | [(set_attr "itanium_class" "fmac")]) | |
f19f1e5e RH |
3216 | |
3217 | (define_insn "*fnmaxf_trunc_<mode>" | |
3218 | [(set (match_operand:MODE_SDF 0 "fr_register_operand" "=f") | |
3219 | (float_truncate:MODE_SDF | |
3220 | (fma:XF | |
3221 | (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")) | |
3222 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") | |
3223 | (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] | |
3224 | "" | |
3225 | "fnma<suffix> %0 = %F1, %F2, %F3" | |
3226 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 JW |
3227 | \f |
3228 | ;; :::::::::::::::::::: | |
3229 | ;; :: | |
27a9b99d | 3230 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
3231 | ;; :: |
3232 | ;; :::::::::::::::::::: | |
3233 | ||
9c668921 | 3234 | (define_expand "ashlsi3" |
0551c32d RH |
3235 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3236 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3237 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 3238 | "" |
9c668921 RH |
3239 | { |
3240 | if (GET_CODE (operands[2]) != CONST_INT) | |
3241 | { | |
3242 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3243 | we've got to get rid of stray bits outside the SImode register. */ | |
3244 | rtx subshift = gen_reg_rtx (DImode); | |
3245 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3246 | operands[2] = subshift; | |
3247 | } | |
1d5d7a21 | 3248 | }) |
9c668921 RH |
3249 | |
3250 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3251 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3252 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3253 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3254 | "" |
041f25e6 RH |
3255 | "@ |
3256 | shladd %0 = %1, %2, r0 | |
3257 | dep.z %0 = %1, %2, %E2 | |
3258 | shl %0 = %1, %2" | |
52e12ad0 | 3259 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3260 | |
3261 | (define_expand "ashrsi3" | |
0551c32d RH |
3262 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3263 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3264 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3265 | "" |
c65ebc55 | 3266 | { |
041f25e6 RH |
3267 | rtx subtarget = gen_reg_rtx (DImode); |
3268 | if (GET_CODE (operands[2]) == CONST_INT) | |
3269 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3270 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3271 | else | |
3272 | { | |
9c668921 | 3273 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3274 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3275 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3276 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3277 | } |
3278 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3279 | DONE; | |
1d5d7a21 | 3280 | }) |
c65ebc55 | 3281 | |
c65ebc55 | 3282 | (define_expand "lshrsi3" |
0551c32d RH |
3283 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3284 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3285 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3286 | "" |
c65ebc55 | 3287 | { |
041f25e6 RH |
3288 | rtx subtarget = gen_reg_rtx (DImode); |
3289 | if (GET_CODE (operands[2]) == CONST_INT) | |
3290 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3291 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3292 | else | |
3293 | { | |
9c668921 | 3294 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3295 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3296 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3297 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3298 | } |
3299 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3300 | DONE; | |
1d5d7a21 | 3301 | }) |
c65ebc55 | 3302 | |
c65ebc55 | 3303 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3304 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3305 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3306 | |
3307 | (define_expand "rotrsi3" | |
66db6b45 RH |
3308 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3309 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3310 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3311 | "" | |
66db6b45 RH |
3312 | { |
3313 | if (GET_MODE (operands[2]) != VOIDmode) | |
3314 | { | |
3315 | rtx tmp = gen_reg_rtx (DImode); | |
3316 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3317 | operands[2] = tmp; | |
3318 | } | |
1d5d7a21 | 3319 | }) |
66db6b45 RH |
3320 | |
3321 | (define_insn_and_split "*rotrsi3_internal" | |
3322 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3323 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3324 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3325 | "" | |
3326 | "#" | |
3327 | "reload_completed" | |
c65ebc55 | 3328 | [(set (match_dup 3) |
66db6b45 | 3329 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3330 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3331 | (set (match_dup 3) | |
66db6b45 RH |
3332 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3333 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3334 | ||
3335 | (define_expand "rotlsi3" | |
3336 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3337 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3338 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 3339 | "" |
c65ebc55 JW |
3340 | { |
3341 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3342 | { |
3343 | rtx tmp = gen_reg_rtx (SImode); | |
3344 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3345 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3346 | DONE; | |
3347 | } | |
1d5d7a21 | 3348 | }) |
66db6b45 RH |
3349 | |
3350 | (define_insn_and_split "*rotlsi3_internal" | |
3351 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3352 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3353 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3354 | "" | |
51094457 JB |
3355 | "mux2 %0 = %1, 0xe1" |
3356 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
3357 | [(set (match_dup 3) |
3358 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3359 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3360 | (set (match_dup 3) | |
3361 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
3362 | { |
3363 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3364 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
3365 | } |
3366 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
3367 | \f |
3368 | ;; :::::::::::::::::::: | |
3369 | ;; :: | |
27a9b99d | 3370 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
3371 | ;; :: |
3372 | ;; :::::::::::::::::::: | |
3373 | ||
3374 | (define_insn "ashldi3" | |
52e12ad0 BS |
3375 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3376 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3377 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3378 | "" |
041f25e6 RH |
3379 | "@ |
3380 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3381 | shl %0 = %1, %2 |
041f25e6 | 3382 | shl %0 = %1, %2" |
52e12ad0 | 3383 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3384 | |
3385 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3386 | ||
3387 | (define_insn "*shladd" | |
0551c32d RH |
3388 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3389 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3390 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3391 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3392 | "" |
3393 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3394 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3395 | |
3396 | ;; This can be created by register elimination if operand3 of shladd is an | |
3397 | ;; eliminable register or has reg_equiv_constant set. | |
3398 | ||
3399 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3400 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3401 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3402 | ;; incorrectly. | |
3403 | ||
5527bf14 | 3404 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3405 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3406 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3407 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3408 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3409 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3410 | "reload_in_progress" | |
e820471b | 3411 | "* gcc_unreachable ();" |
c65ebc55 JW |
3412 | "reload_completed" |
3413 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3414 | (match_dup 3))) | |
c65ebc55 | 3415 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3416 | "" |
52e12ad0 | 3417 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3418 | |
3419 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3420 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3421 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3422 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3423 | "" |
52e12ad0 BS |
3424 | "@ |
3425 | shr %0 = %1, %2 | |
3426 | shr %0 = %1, %2" | |
3427 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3428 | |
3429 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3430 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3431 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3432 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3433 | "" |
52e12ad0 BS |
3434 | "@ |
3435 | shr.u %0 = %1, %2 | |
3436 | shr.u %0 = %1, %2" | |
3437 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3438 | |
3439 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3440 | ;; will load the operand into a register and call the pattern if the predicate | |
3441 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3442 | ;; verify that we have an appropriate constant in the expander. | |
3443 | ||
3444 | (define_expand "rotrdi3" | |
0551c32d RH |
3445 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3446 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3447 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3448 | "" | |
c65ebc55 JW |
3449 | { |
3450 | if (! shift_count_operand (operands[2], DImode)) | |
3451 | FAIL; | |
1d5d7a21 | 3452 | }) |
c65ebc55 JW |
3453 | |
3454 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3455 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3456 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3457 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3458 | "" | |
3459 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3460 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3461 | |
66db6b45 RH |
3462 | (define_expand "rotldi3" |
3463 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3464 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3465 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3466 | "" | |
66db6b45 RH |
3467 | { |
3468 | if (! shift_count_operand (operands[2], DImode)) | |
3469 | FAIL; | |
1d5d7a21 | 3470 | }) |
66db6b45 RH |
3471 | |
3472 | (define_insn "*rotldi3_internal" | |
3473 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3474 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3475 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3476 | "" | |
3477 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3478 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
3479 | \f |
3480 | ;; :::::::::::::::::::: | |
3481 | ;; :: | |
27a9b99d | 3482 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
3483 | ;; :: |
3484 | ;; :::::::::::::::::::: | |
3485 | ||
16d8386b JB |
3486 | (define_expand "ashlti3" |
3487 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3488 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
3489 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3490 | "" | |
3491 | { | |
3492 | if (!dshift_count_operand (operands[2], DImode)) | |
3493 | FAIL; | |
3494 | }) | |
3495 | ||
3496 | (define_insn_and_split "*ashlti3_internal" | |
3497 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
3498 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
3499 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3500 | "" | |
3501 | "#" | |
3502 | "reload_completed" | |
3503 | [(const_int 0)] | |
3504 | { | |
3505 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
3506 | rtx rl = gen_lowpart (DImode, operands[0]); | |
3507 | rtx rh = gen_highpart (DImode, operands[0]); | |
3508 | rtx lo = gen_lowpart (DImode, operands[1]); | |
3509 | rtx shiftlo = GEN_INT (shift & 63); | |
3510 | ||
3511 | if (shift & 64) | |
3512 | { | |
3513 | emit_move_insn (rl, const0_rtx); | |
3514 | if (shift & 63) | |
3515 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
3516 | else | |
3517 | emit_move_insn (rh, lo); | |
3518 | } | |
3519 | else | |
3520 | { | |
3521 | rtx hi = gen_highpart (DImode, operands[1]); | |
3522 | ||
3523 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
3524 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
3525 | } | |
3526 | DONE; | |
3527 | }) | |
3528 | ||
f526a3c8 RH |
3529 | (define_expand "ashrti3" |
3530 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3531 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
3532 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3533 | "" | |
3534 | { | |
3535 | if (!dshift_count_operand (operands[2], DImode)) | |
3536 | FAIL; | |
3537 | }) | |
3538 | ||
3539 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 3540 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
3541 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
3542 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3543 | "" | |
3544 | "#" | |
3545 | "reload_completed" | |
3546 | [(const_int 0)] | |
3547 | { | |
3548 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
3549 | rtx rl = gen_lowpart (DImode, operands[0]); |
3550 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
3551 | rtx hi = gen_highpart (DImode, operands[1]); |
3552 | rtx shiftlo = GEN_INT (shift & 63); | |
3553 | ||
3554 | if (shift & 64) | |
3555 | { | |
16d8386b JB |
3556 | if (shift & 63) |
3557 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
3558 | else | |
3559 | emit_move_insn (rl, hi); | |
3560 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
3561 | } |
3562 | else | |
3563 | { | |
16d8386b JB |
3564 | rtx lo = gen_lowpart (DImode, operands[1]); |
3565 | ||
3566 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
3567 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
3568 | } |
3569 | DONE; | |
3570 | }) | |
3571 | ||
3572 | (define_expand "lshrti3" | |
3573 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3574 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
3575 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3576 | "" | |
3577 | { | |
3578 | if (!dshift_count_operand (operands[2], DImode)) | |
3579 | FAIL; | |
3580 | }) | |
3581 | ||
3582 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 3583 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
3584 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
3585 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3586 | "" | |
3587 | "#" | |
3588 | "reload_completed" | |
3589 | [(const_int 0)] | |
3590 | { | |
3591 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
3592 | rtx rl = gen_lowpart (DImode, operands[0]); |
3593 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
3594 | rtx hi = gen_highpart (DImode, operands[1]); |
3595 | rtx shiftlo = GEN_INT (shift & 63); | |
3596 | ||
3597 | if (shift & 64) | |
3598 | { | |
16d8386b JB |
3599 | if (shift & 63) |
3600 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
3601 | else | |
3602 | emit_move_insn (rl, hi); | |
3603 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
3604 | } |
3605 | else | |
3606 | { | |
16d8386b JB |
3607 | rtx lo = gen_lowpart (DImode, operands[1]); |
3608 | ||
3609 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
3610 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
3611 | } |
3612 | DONE; | |
3613 | }) | |
3614 | ||
a71aef0b JB |
3615 | (define_expand "rotlti3" |
3616 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
3617 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
3618 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3619 | "" | |
3620 | { | |
3621 | if (! dshift_count_operand (operands[2], DImode)) | |
3622 | FAIL; | |
3623 | }) | |
3624 | ||
3625 | (define_insn_and_split "*rotlti3_internal" | |
3626 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
3627 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
3628 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
3629 | "" | |
3630 | "#" | |
3631 | "reload_completed" | |
3632 | [(const_int 0)] | |
3633 | { | |
3634 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
3635 | rtx rl = gen_lowpart (DImode, operands[0]); | |
3636 | rtx rh = gen_highpart (DImode, operands[0]); | |
3637 | rtx lo = gen_lowpart (DImode, operands[1]); | |
3638 | rtx hi = gen_highpart (DImode, operands[1]); | |
3639 | rtx countlo = GEN_INT (-count & 63); | |
3640 | ||
3641 | if (count & 64) | |
3642 | { | |
3643 | if (count & 63) | |
3644 | { | |
3645 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
3646 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
3647 | } | |
3648 | else | |
3649 | { | |
3650 | emit_move_insn (rl, hi); | |
3651 | emit_move_insn (rh, lo); | |
3652 | } | |
3653 | } | |
3654 | else | |
3655 | { | |
3656 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
3657 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
3658 | } | |
3659 | DONE; | |
3660 | } | |
3661 | [(set_attr "itanium_class" "unknown")]) | |
3662 | ||
f526a3c8 RH |
3663 | (define_insn "shrp" |
3664 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3665 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
3666 | (match_operand:DI 2 "gr_register_operand" "r") | |
3667 | (match_operand:DI 3 "shift_count_operand" "M")] | |
3668 | UNSPEC_SHRP))] | |
3669 | "" | |
3670 | "shrp %0 = %1, %2, %3" | |
3671 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
3672 | \f |
3673 | ;; :::::::::::::::::::: | |
3674 | ;; :: | |
27a9b99d | 3675 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
3676 | ;; :: |
3677 | ;; :::::::::::::::::::: | |
3678 | ||
3679 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3680 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3681 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3682 | ;; This doesn't work for unary logical operations, because we don't call | |
3683 | ;; apply_distributive_law for them. | |
3684 | ||
3685 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3686 | ;; apply_distributive_law. We get inefficient code for | |
3687 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3688 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3689 | ;; (zero_extend (and (not A) B)) in combine. | |
3690 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3691 | ;; one_cmplsi2 pattern. | |
3692 | ||
058557c4 | 3693 | (define_insn "one_cmplsi2" |
0551c32d RH |
3694 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3695 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3696 | "" |
3697 | "andcm %0 = -1, %1" | |
52e12ad0 | 3698 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3699 | \f |
3700 | ;; :::::::::::::::::::: | |
3701 | ;; :: | |
27a9b99d | 3702 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
3703 | ;; :: |
3704 | ;; :::::::::::::::::::: | |
3705 | ||
3706 | (define_insn "anddi3" | |
0551c32d RH |
3707 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3708 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3709 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3710 | "" |
3711 | "@ | |
3712 | and %0 = %2, %1 | |
aebf2462 | 3713 | fand %0 = %2, %1" |
52e12ad0 | 3714 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3715 | |
3716 | (define_insn "*andnot" | |
0551c32d RH |
3717 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3718 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3719 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3720 | "" |
3721 | "@ | |
3722 | andcm %0 = %2, %1 | |
aebf2462 | 3723 | fandcm %0 = %2, %1" |
52e12ad0 | 3724 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3725 | |
3726 | (define_insn "iordi3" | |
0551c32d RH |
3727 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3728 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3729 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3730 | "" |
3731 | "@ | |
3732 | or %0 = %2, %1 | |
aebf2462 | 3733 | for %0 = %2, %1" |
52e12ad0 | 3734 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3735 | |
3736 | (define_insn "xordi3" | |
0551c32d RH |
3737 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3738 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3739 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3740 | "" |
3741 | "@ | |
3742 | xor %0 = %2, %1 | |
aebf2462 | 3743 | fxor %0 = %2, %1" |
52e12ad0 | 3744 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3745 | |
3746 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3747 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3748 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3749 | "" |
3750 | "andcm %0 = -1, %1" | |
52e12ad0 | 3751 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3752 | \f |
3753 | ;; :::::::::::::::::::: | |
3754 | ;; :: | |
3755 | ;; :: Comparisons | |
3756 | ;; :: | |
3757 | ;; :::::::::::::::::::: | |
3758 | ||
f90b7a5a PB |
3759 | (define_expand "cbranchbi4" |
3760 | [(set (pc) | |
3761 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3762 | [(match_operand:BI 1 "register_operand" "") | |
3763 | (match_operand:BI 2 "const_int_operand" "")]) | |
3764 | (label_ref (match_operand 3 "" "")) | |
3765 | (pc)))] | |
f2f90c63 | 3766 | "" |
f90b7a5a | 3767 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
f2f90c63 | 3768 | |
f90b7a5a PB |
3769 | (define_expand "cbranchsi4" |
3770 | [(set (pc) | |
3771 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3772 | [(match_operand:SI 1 "gr_register_operand" "") | |
3773 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
3774 | (label_ref (match_operand 3 "" "")) | |
3775 | (pc)))] | |
c65ebc55 | 3776 | "" |
f90b7a5a | 3777 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3778 | |
f90b7a5a PB |
3779 | (define_expand "cbranchdi4" |
3780 | [(set (pc) | |
3781 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3782 | [(match_operand:DI 1 "gr_register_operand" "") | |
3783 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
3784 | (label_ref (match_operand 3 "" "")) | |
3785 | (pc)))] | |
c65ebc55 | 3786 | "" |
f90b7a5a | 3787 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3788 | |
f90b7a5a PB |
3789 | (define_expand "cbranchsf4" |
3790 | [(set (pc) | |
3791 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3792 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
3793 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
3794 | (label_ref (match_operand 3 "" "")) | |
3795 | (pc)))] | |
c65ebc55 | 3796 | "" |
f90b7a5a | 3797 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3798 | |
f90b7a5a PB |
3799 | (define_expand "cbranchdf4" |
3800 | [(set (pc) | |
3801 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3802 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
3803 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
3804 | (label_ref (match_operand 3 "" "")) | |
3805 | (pc)))] | |
c65ebc55 | 3806 | "" |
f90b7a5a | 3807 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3808 | |
f90b7a5a PB |
3809 | (define_expand "cbranchxf4" |
3810 | [(set (pc) | |
3811 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3812 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
3813 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
3814 | (label_ref (match_operand 3 "" "")) | |
3815 | (pc)))] | |
02befdf4 | 3816 | "" |
f90b7a5a | 3817 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
c65ebc55 | 3818 | |
f90b7a5a PB |
3819 | (define_expand "cbranchtf4" |
3820 | [(set (pc) | |
3821 | (if_then_else (match_operator 0 "ia64_cbranch_operator" | |
3822 | [(match_operand:TF 1 "gr_register_operand" "") | |
3823 | (match_operand:TF 2 "gr_register_operand" "")]) | |
3824 | (label_ref (match_operand 3 "" "")) | |
3825 | (pc)))] | |
24ea7948 | 3826 | "TARGET_HPUX" |
f90b7a5a PB |
3827 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
3828 | ||
24ea7948 | 3829 | |
c65ebc55 | 3830 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
3831 | [(set (match_operand:BI 0 "register_operand" "=c") |
3832 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
3833 | [(match_operand:SI 2 "gr_register_operand" "r") |
3834 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
3835 | "" |
3836 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 3837 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3838 | |
18a3c539 JW |
3839 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3840 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3841 | ||
c65ebc55 | 3842 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
3843 | [(set (match_operand:BI 0 "register_operand" "=c") |
3844 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3845 | [(match_operand:SI 2 "gr_register_operand" "r") |
3846 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3847 | "" |
18a3c539 | 3848 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3849 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3850 | |
3851 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
3852 | [(set (match_operand:BI 0 "register_operand" "=c") |
3853 | (match_operator:BI 1 "normal_comparison_operator" | |
3854 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 3855 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 3856 | "" |
f2f90c63 | 3857 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 3858 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3859 | |
18a3c539 JW |
3860 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3861 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3862 | ||
c65ebc55 | 3863 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
3864 | [(set (match_operand:BI 0 "register_operand" "=c") |
3865 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3866 | [(match_operand:DI 2 "gr_register_operand" "r") |
3867 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3868 | "" |
18a3c539 | 3869 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3870 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3871 | |
3872 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
3873 | [(set (match_operand:BI 0 "register_operand" "=c") |
3874 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
3875 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
3876 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
3877 | "" |
3878 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 3879 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
3880 | |
3881 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
3882 | [(set (match_operand:BI 0 "register_operand" "=c") |
3883 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
3884 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
3885 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
3886 | "" |
3887 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 3888 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 3889 | |
02befdf4 | 3890 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
3891 | [(set (match_operand:BI 0 "register_operand" "=c") |
3892 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
3893 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
3894 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
3895 | "" | |
3f622353 | 3896 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 3897 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 3898 | |
c65ebc55 JW |
3899 | ;; ??? Can this pattern be generated? |
3900 | ||
3901 | (define_insn "*bit_zero" | |
f2f90c63 RH |
3902 | [(set (match_operand:BI 0 "register_operand" "=c") |
3903 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3904 | (const_int 1) |
5d48891e | 3905 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
3906 | (const_int 0)))] |
3907 | "" | |
3908 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 3909 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
3910 | |
3911 | (define_insn "*bit_one" | |
f2f90c63 RH |
3912 | [(set (match_operand:BI 0 "register_operand" "=c") |
3913 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3914 | (const_int 1) |
5d48891e | 3915 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
3916 | (const_int 0)))] |
3917 | "" | |
3918 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 3919 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
3920 | \f |
3921 | ;; :::::::::::::::::::: | |
3922 | ;; :: | |
3923 | ;; :: Branches | |
3924 | ;; :: | |
3925 | ;; :::::::::::::::::::: | |
3926 | ||
6b6c1201 | 3927 | (define_insn "*br_true" |
c65ebc55 | 3928 | [(set (pc) |
6b6c1201 | 3929 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 3930 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
3931 | (const_int 0)]) |
3932 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
3933 | (pc)))] |
3934 | "" | |
85548039 | 3935 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 3936 | [(set_attr "itanium_class" "br") |
e5bde68a | 3937 | (set_attr "predicable" "no")]) |
c65ebc55 | 3938 | |
6b6c1201 | 3939 | (define_insn "*br_false" |
c65ebc55 | 3940 | [(set (pc) |
6b6c1201 | 3941 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 3942 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 3943 | (const_int 0)]) |
c65ebc55 | 3944 | (pc) |
6b6c1201 | 3945 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 3946 | "" |
85548039 | 3947 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 3948 | [(set_attr "itanium_class" "br") |
e5bde68a | 3949 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3950 | \f |
3951 | ;; :::::::::::::::::::: | |
3952 | ;; :: | |
5527bf14 RH |
3953 | ;; :: Counted loop operations |
3954 | ;; :: | |
3955 | ;; :::::::::::::::::::: | |
3956 | ||
3957 | (define_expand "doloop_end" | |
3958 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 3959 | (use (match_operand 1 "" ""))] ; label |
5527bf14 | 3960 | "" |
5527bf14 | 3961 | { |
fee13acd AS |
3962 | if (GET_MODE (operands[0]) != DImode) |
3963 | FAIL; | |
3964 | ||
5527bf14 | 3965 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), |
1d0216c8 | 3966 | operands[1])); |
5527bf14 | 3967 | DONE; |
1d5d7a21 | 3968 | }) |
5527bf14 RH |
3969 | |
3970 | (define_insn "doloop_end_internal" | |
3971 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
3972 | (const_int 0)) | |
3973 | (label_ref (match_operand 1 "" "")) | |
3974 | (pc))) | |
3975 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
3976 | (plus:DI (match_dup 0) (const_int -1)) |
3977 | (match_dup 0)))] | |
5527bf14 RH |
3978 | "" |
3979 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 3980 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
3981 | (set_attr "predicable" "no")]) |
3982 | \f | |
3983 | ;; :::::::::::::::::::: | |
3984 | ;; :: | |
c65ebc55 JW |
3985 | ;; :: Set flag operations |
3986 | ;; :: | |
3987 | ;; :::::::::::::::::::: | |
3988 | ||
f90b7a5a PB |
3989 | (define_expand "cstorebi4" |
3990 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3991 | (match_operator:DI 1 "ia64_cbranch_operator" | |
3992 | [(match_operand:BI 2 "register_operand" "") | |
3993 | (match_operand:BI 3 "const_int_operand" "")]))] | |
c65ebc55 | 3994 | "" |
bf321310 | 3995 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 3996 | |
f90b7a5a PB |
3997 | (define_expand "cstoresi4" |
3998 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3999 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4000 | [(match_operand:SI 2 "gr_register_operand" "") | |
4001 | (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 4002 | "" |
f90b7a5a | 4003 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4004 | |
f90b7a5a PB |
4005 | (define_expand "cstoredi4" |
4006 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4007 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4008 | [(match_operand:DI 2 "gr_register_operand" "") | |
4009 | (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))] | |
c65ebc55 | 4010 | "" |
f90b7a5a | 4011 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4012 | |
f90b7a5a PB |
4013 | (define_expand "cstoresf4" |
4014 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4015 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4016 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "") | |
4017 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4018 | "" |
f90b7a5a | 4019 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4020 | |
f90b7a5a PB |
4021 | (define_expand "cstoredf4" |
4022 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4023 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4024 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "") | |
4025 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))] | |
c65ebc55 | 4026 | "" |
f90b7a5a | 4027 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4028 | |
f90b7a5a PB |
4029 | (define_expand "cstorexf4" |
4030 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4031 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4032 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "") | |
4033 | (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))] | |
c65ebc55 | 4034 | "" |
f90b7a5a | 4035 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") |
c65ebc55 | 4036 | |
f90b7a5a PB |
4037 | (define_expand "cstoretf4" |
4038 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4039 | (match_operator:DI 1 "ia64_cbranch_operator" | |
4040 | [(match_operand:TF 2 "gr_register_operand" "") | |
4041 | (match_operand:TF 3 "gr_register_operand" "")]))] | |
4042 | "TARGET_HPUX" | |
4043 | "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);") | |
e57b9d65 | 4044 | |
c65ebc55 JW |
4045 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4046 | ;; efficient than mov/mov/cst/cst. | |
4047 | ||
0551c32d RH |
4048 | (define_insn_and_split "*sne_internal" |
4049 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4050 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4051 | (const_int 0)))] |
4052 | "" | |
4053 | "#" | |
c65ebc55 | 4054 | "reload_completed" |
f2f90c63 RH |
4055 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4056 | (set (match_dup 0) (const_int 1))) | |
4057 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4058 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4059 | "" |
52e12ad0 | 4060 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4061 | |
0551c32d RH |
4062 | (define_insn_and_split "*seq_internal" |
4063 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4064 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4065 | (const_int 0)))] |
4066 | "" | |
4067 | "#" | |
c65ebc55 | 4068 | "reload_completed" |
f2f90c63 RH |
4069 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4070 | (set (match_dup 0) (const_int 0))) | |
4071 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4072 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4073 | "" |
52e12ad0 | 4074 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4075 | \f |
4076 | ;; :::::::::::::::::::: | |
4077 | ;; :: | |
4078 | ;; :: Conditional move instructions. | |
4079 | ;; :: | |
4080 | ;; :::::::::::::::::::: | |
4081 | ||
4082 | ;; ??? Add movXXcc patterns? | |
4083 | ||
c65ebc55 JW |
4084 | ;; |
4085 | ;; DImode if_then_else patterns. | |
4086 | ;; | |
4087 | ||
75cdbeb8 | 4088 | (define_insn "*cmovdi_internal" |
cd17b213 | 4089 | [(set (match_operand:DI 0 "not_postinc_destination_operand" |
cd5c4048 | 4090 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4091 | (if_then_else:DI |
f2f90c63 RH |
4092 | (match_operator 4 "predicate_operator" |
4093 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4094 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4095 | (const_int 0)]) |
cd17b213 | 4096 | (match_operand:DI 2 "not_postinc_move_operand" |
cd5c4048 | 4097 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
cd17b213 | 4098 | (match_operand:DI 3 "not_postinc_move_operand" |
cd5c4048 | 4099 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4100 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4101 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4102 | { gcc_unreachable (); } |
75cdbeb8 RH |
4103 | [(set_attr "predicable" "no")]) |
4104 | ||
4105 | (define_split | |
cd17b213 | 4106 | [(set (match_operand 0 "not_postinc_destination_operand" "") |
75cdbeb8 | 4107 | (if_then_else |
f2f90c63 RH |
4108 | (match_operator 4 "predicate_operator" |
4109 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4110 | (const_int 0)]) |
cd17b213 SE |
4111 | (match_operand 2 "not_postinc_move_operand" "") |
4112 | (match_operand 3 "not_postinc_move_operand" "")))] | |
3b572406 RH |
4113 | "reload_completed" |
4114 | [(const_int 0)] | |
e5bde68a | 4115 | { |
21515593 RH |
4116 | bool emitted_something = false; |
4117 | rtx dest = operands[0]; | |
4118 | rtx srct = operands[2]; | |
4119 | rtx srcf = operands[3]; | |
4120 | rtx cond = operands[4]; | |
2f937369 | 4121 | |
21515593 | 4122 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 4123 | { |
21515593 RH |
4124 | ia64_emit_cond_move (dest, srct, cond); |
4125 | emitted_something = true; | |
e5bde68a | 4126 | } |
21515593 | 4127 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 4128 | { |
21515593 RH |
4129 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
4130 | VOIDmode, operands[1], const0_rtx); | |
4131 | ia64_emit_cond_move (dest, srcf, cond); | |
4132 | emitted_something = true; | |
3b572406 | 4133 | } |
2f937369 | 4134 | if (! emitted_something) |
f9974026 | 4135 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 4136 | DONE; |
1d5d7a21 | 4137 | }) |
c65ebc55 JW |
4138 | |
4139 | ;; Absolute value pattern. | |
4140 | ||
4141 | (define_insn "*absdi2_internal" | |
0551c32d | 4142 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4143 | (if_then_else:DI |
f2f90c63 RH |
4144 | (match_operator 4 "predicate_operator" |
4145 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4146 | (const_int 0)]) |
0551c32d RH |
4147 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4148 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4149 | "" |
e5bde68a | 4150 | "#" |
52e12ad0 | 4151 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4152 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4153 | |
4154 | (define_split | |
4155 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4156 | (if_then_else:DI |
f2f90c63 | 4157 | (match_operator 4 "predicate_operator" |
516e2f1c | 4158 | [(match_operand:BI 1 "register_operand" "") |
e5bde68a | 4159 | (const_int 0)]) |
0551c32d RH |
4160 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4161 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4162 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4163 | [(cond_exec | |
4164 | (match_dup 4) | |
4165 | (set (match_dup 0) | |
4166 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4167 | "") |
4168 | ||
e5bde68a RH |
4169 | (define_split |
4170 | [(set (match_operand:DI 0 "register_operand" "") | |
4171 | (if_then_else:DI | |
f2f90c63 | 4172 | (match_operator 4 "predicate_operator" |
516e2f1c | 4173 | [(match_operand:BI 1 "register_operand" "") |
e5bde68a | 4174 | (const_int 0)]) |
0551c32d RH |
4175 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4176 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4177 | "reload_completed" |
4178 | [(cond_exec | |
4179 | (match_dup 4) | |
4180 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4181 | (cond_exec | |
4182 | (match_dup 5) | |
4183 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4184 | { |
4185 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4186 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4187 | }) |
c65ebc55 JW |
4188 | |
4189 | ;; | |
4190 | ;; SImode if_then_else patterns. | |
4191 | ;; | |
4192 | ||
75cdbeb8 | 4193 | (define_insn "*cmovsi_internal" |
cd17b213 SE |
4194 | [(set (match_operand:SI 0 "not_postinc_destination_operand" |
4195 | "=r,m,*f,r,m,*f,r,m,*f") | |
e5bde68a | 4196 | (if_then_else:SI |
f2f90c63 RH |
4197 | (match_operator 4 "predicate_operator" |
4198 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4199 | (const_int 0)]) |
cd17b213 | 4200 | (match_operand:SI 2 "not_postinc_move_operand" |
3b572406 | 4201 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
cd17b213 | 4202 | (match_operand:SI 3 "not_postinc_move_operand" |
3b572406 | 4203 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4204 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4205 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 4206 | { gcc_unreachable (); } |
3b572406 | 4207 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4208 | |
4209 | (define_insn "*abssi2_internal" | |
0551c32d | 4210 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4211 | (if_then_else:SI |
f2f90c63 RH |
4212 | (match_operator 4 "predicate_operator" |
4213 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4214 | (const_int 0)]) |
0551c32d RH |
4215 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4216 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4217 | "" |
e5bde68a | 4218 | "#" |
52e12ad0 | 4219 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4220 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4221 | |
4222 | (define_split | |
4223 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4224 | (if_then_else:SI |
f2f90c63 | 4225 | (match_operator 4 "predicate_operator" |
516e2f1c | 4226 | [(match_operand:BI 1 "register_operand" "") |
e5bde68a | 4227 | (const_int 0)]) |
0551c32d RH |
4228 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4229 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4230 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4231 | [(cond_exec | |
4232 | (match_dup 4) | |
4233 | (set (match_dup 0) | |
4234 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4235 | "") |
4236 | ||
e5bde68a RH |
4237 | (define_split |
4238 | [(set (match_operand:SI 0 "register_operand" "") | |
4239 | (if_then_else:SI | |
f2f90c63 | 4240 | (match_operator 4 "predicate_operator" |
516e2f1c | 4241 | [(match_operand:BI 1 "register_operand" "") |
e5bde68a | 4242 | (const_int 0)]) |
0551c32d RH |
4243 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4244 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4245 | "reload_completed" |
4246 | [(cond_exec | |
4247 | (match_dup 4) | |
4248 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4249 | (cond_exec | |
4250 | (match_dup 5) | |
4251 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
4252 | { |
4253 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4254 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 4255 | }) |
e5bde68a | 4256 | |
7dcc803e | 4257 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4258 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4259 | (match_operator:SI 5 "condop_operator" | |
4260 | [(if_then_else:SI | |
4261 | (match_operator 6 "predicate_operator" | |
4262 | [(match_operand:BI 1 "register_operand" "c") | |
4263 | (const_int 0)]) | |
4264 | (match_operand:SI 2 "gr_register_operand" "r") | |
4265 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4266 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4267 | "" | |
4268 | "#" | |
acb0638d BS |
4269 | "reload_completed" |
4270 | [(cond_exec | |
4271 | (match_dup 6) | |
4272 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4273 | (cond_exec | |
4274 | (match_dup 7) | |
4275 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
4276 | { |
4277 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4278 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4279 | } |
7dcc803e BS |
4280 | [(set_attr "itanium_class" "ialu") |
4281 | (set_attr "predicable" "no")]) | |
4282 | ||
acb0638d | 4283 | |
7dcc803e | 4284 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4285 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4286 | (match_operator:SI 5 "condop_operator" | |
4287 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4288 | (if_then_else:SI | |
4289 | (match_operator 6 "predicate_operator" | |
4290 | [(match_operand:BI 1 "register_operand" "c") | |
4291 | (const_int 0)]) | |
4292 | (match_operand:SI 2 "gr_register_operand" "r") | |
4293 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4294 | "" | |
4295 | "#" | |
acb0638d BS |
4296 | "reload_completed" |
4297 | [(cond_exec | |
4298 | (match_dup 6) | |
4299 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4300 | (cond_exec | |
4301 | (match_dup 7) | |
4302 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
4303 | { |
4304 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4305 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 4306 | } |
7dcc803e BS |
4307 | [(set_attr "itanium_class" "ialu") |
4308 | (set_attr "predicable" "no")]) | |
acb0638d | 4309 | |
c65ebc55 JW |
4310 | \f |
4311 | ;; :::::::::::::::::::: | |
4312 | ;; :: | |
4313 | ;; :: Call and branch instructions | |
4314 | ;; :: | |
4315 | ;; :::::::::::::::::::: | |
4316 | ||
4317 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4318 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4319 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4320 | ;; registers used as operands. | |
4321 | ||
4322 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4323 | ;; is supplied for the sake of some RISC machines which need to put this | |
4324 | ;; information into the assembler code; they can put it in the RTL instead of | |
4325 | ;; operand 1. | |
4326 | ||
4327 | (define_expand "call" | |
4328 | [(use (match_operand:DI 0 "" "")) | |
4329 | (use (match_operand 1 "" "")) | |
4330 | (use (match_operand 2 "" "")) | |
4331 | (use (match_operand 3 "" ""))] | |
4332 | "" | |
c65ebc55 | 4333 | { |
599aedd9 | 4334 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 4335 | DONE; |
1d5d7a21 | 4336 | }) |
c65ebc55 | 4337 | |
2ed4af6f RH |
4338 | (define_expand "sibcall" |
4339 | [(use (match_operand:DI 0 "" "")) | |
4340 | (use (match_operand 1 "" "")) | |
4341 | (use (match_operand 2 "" "")) | |
4342 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 4343 | "" |
c65ebc55 | 4344 | { |
599aedd9 | 4345 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 4346 | DONE; |
1d5d7a21 | 4347 | }) |
c65ebc55 | 4348 | |
c65ebc55 | 4349 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4350 | ;; register in which the value is returned. There are three more operands, |
4351 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4352 | ;; increased by one). |
2ed4af6f | 4353 | ;; |
c65ebc55 JW |
4354 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4355 | ||
4356 | (define_expand "call_value" | |
4357 | [(use (match_operand 0 "" "")) | |
4358 | (use (match_operand:DI 1 "" "")) | |
4359 | (use (match_operand 2 "" "")) | |
4360 | (use (match_operand 3 "" "")) | |
4361 | (use (match_operand 4 "" ""))] | |
4362 | "" | |
c65ebc55 | 4363 | { |
599aedd9 | 4364 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 4365 | DONE; |
1d5d7a21 | 4366 | }) |
c65ebc55 | 4367 | |
2ed4af6f RH |
4368 | (define_expand "sibcall_value" |
4369 | [(use (match_operand 0 "" "")) | |
4370 | (use (match_operand:DI 1 "" "")) | |
4371 | (use (match_operand 2 "" "")) | |
4372 | (use (match_operand 3 "" "")) | |
4373 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 4374 | "" |
c65ebc55 | 4375 | { |
599aedd9 | 4376 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 4377 | DONE; |
1d5d7a21 | 4378 | }) |
c65ebc55 | 4379 | |
c65ebc55 JW |
4380 | ;; Call subroutine returning any type. |
4381 | ||
4382 | (define_expand "untyped_call" | |
4383 | [(parallel [(call (match_operand 0 "" "") | |
4384 | (const_int 0)) | |
4385 | (match_operand 1 "" "") | |
4386 | (match_operand 2 "" "")])] | |
4387 | "" | |
c65ebc55 JW |
4388 | { |
4389 | int i; | |
4390 | ||
4391 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4392 | ||
4393 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4394 | { | |
4395 | rtx set = XVECEXP (operands[2], 0, i); | |
4396 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4397 | } | |
4398 | ||
4399 | /* The optimizer does not know that the call sets the function value | |
4400 | registers we stored in the result block. We avoid problems by | |
4401 | claiming that all hard registers are used and clobbered at this | |
4402 | point. */ | |
4403 | emit_insn (gen_blockage ()); | |
4404 | ||
4405 | DONE; | |
1d5d7a21 | 4406 | }) |
c65ebc55 | 4407 | |
599aedd9 | 4408 | (define_insn "call_nogp" |
67b476d1 | 4409 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s")) |
599aedd9 RH |
4410 | (const_int 0)) |
4411 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 4412 | "" |
599aedd9 | 4413 | "br.call%+.many %1 = %0" |
52e12ad0 | 4414 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4415 | |
599aedd9 | 4416 | (define_insn "call_value_nogp" |
75293ad6 | 4417 | [(set (match_operand 0 "" "=X,X") |
67b476d1 | 4418 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,s")) |
599aedd9 RH |
4419 | (const_int 0))) |
4420 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 4421 | "" |
599aedd9 | 4422 | "br.call%+.many %2 = %1" |
52e12ad0 | 4423 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4424 | |
599aedd9 | 4425 | (define_insn "sibcall_nogp" |
67b476d1 | 4426 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,s")) |
599aedd9 | 4427 | (const_int 0))] |
2ed4af6f RH |
4428 | "" |
4429 | "br%+.many %0" | |
52e12ad0 | 4430 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4431 | |
599aedd9 | 4432 | (define_insn "call_gp" |
67b476d1 | 4433 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s")) |
599aedd9 RH |
4434 | (const_int 1)) |
4435 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
4436 | (clobber (match_scratch:DI 2 "=&r,X")) | |
4437 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 4438 | "" |
599aedd9 | 4439 | "#" |
52e12ad0 | 4440 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4441 | |
599aedd9 RH |
4442 | ;; Irritatingly, we don't have access to INSN within the split body. |
4443 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
4444 | (define_split | |
4445 | [(call (mem (match_operand 0 "call_operand" "")) | |
4446 | (const_int 1)) | |
4447 | (clobber (match_operand:DI 1 "register_operand" "")) | |
4448 | (clobber (match_scratch:DI 2 "")) | |
4449 | (clobber (match_scratch:DI 3 ""))] | |
4450 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
4451 | [(const_int 0)] | |
4452 | { | |
4453 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
4454 | operands[3], true, false); | |
4455 | DONE; | |
4456 | }) | |
4457 | ||
4458 | (define_split | |
4459 | [(call (mem (match_operand 0 "call_operand" "")) | |
4460 | (const_int 1)) | |
4461 | (clobber (match_operand:DI 1 "register_operand" "")) | |
4462 | (clobber (match_scratch:DI 2 "")) | |
4463 | (clobber (match_scratch:DI 3 ""))] | |
4464 | "reload_completed" | |
4465 | [(const_int 0)] | |
4466 | { | |
4467 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
4468 | operands[3], false, false); | |
4469 | DONE; | |
4470 | }) | |
4471 | ||
4472 | (define_insn "call_value_gp" | |
75293ad6 | 4473 | [(set (match_operand 0 "" "=X,X") |
67b476d1 | 4474 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,s")) |
599aedd9 RH |
4475 | (const_int 1))) |
4476 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
4477 | (clobber (match_scratch:DI 3 "=&r,X")) | |
4478 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 4479 | "" |
599aedd9 | 4480 | "#" |
52e12ad0 | 4481 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 4482 | |
599aedd9 RH |
4483 | (define_split |
4484 | [(set (match_operand 0 "" "") | |
4485 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
4486 | (const_int 1))) | |
4487 | (clobber (match_operand:DI 2 "register_operand" "")) | |
4488 | (clobber (match_scratch:DI 3 "")) | |
4489 | (clobber (match_scratch:DI 4 ""))] | |
4490 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
4491 | [(const_int 0)] | |
4492 | { | |
4493 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
4494 | operands[4], true, false); | |
4495 | DONE; | |
4496 | }) | |
4497 | ||
4498 | (define_split | |
4499 | [(set (match_operand 0 "" "") | |
4500 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
4501 | (const_int 1))) | |
4502 | (clobber (match_operand:DI 2 "register_operand" "")) | |
4503 | (clobber (match_scratch:DI 3 "")) | |
4504 | (clobber (match_scratch:DI 4 ""))] | |
4505 | "reload_completed" | |
4506 | [(const_int 0)] | |
4507 | { | |
4508 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
4509 | operands[4], false, false); | |
4510 | DONE; | |
4511 | }) | |
4512 | ||
4513 | (define_insn_and_split "sibcall_gp" | |
67b476d1 | 4514 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,s")) |
599aedd9 RH |
4515 | (const_int 1)) |
4516 | (clobber (match_scratch:DI 1 "=&r,X")) | |
4517 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 4518 | "" |
599aedd9 RH |
4519 | "#" |
4520 | "reload_completed" | |
4521 | [(const_int 0)] | |
4522 | { | |
4523 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
4524 | operands[2], true, true); | |
4525 | DONE; | |
4526 | } | |
52e12ad0 | 4527 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4528 | |
c65ebc55 JW |
4529 | (define_insn "return_internal" |
4530 | [(return) | |
4531 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4532 | "" | |
4533 | "br.ret.sptk.many %0" | |
52e12ad0 | 4534 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4535 | |
4536 | (define_insn "return" | |
4537 | [(return)] | |
4538 | "ia64_direct_return ()" | |
4539 | "br.ret.sptk.many rp" | |
52e12ad0 | 4540 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4541 | |
6b6c1201 | 4542 | (define_insn "*return_true" |
c65ebc55 | 4543 | [(set (pc) |
6b6c1201 | 4544 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4545 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4546 | (const_int 0)]) |
c65ebc55 JW |
4547 | (return) |
4548 | (pc)))] | |
4549 | "ia64_direct_return ()" | |
13da91fd | 4550 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4551 | [(set_attr "itanium_class" "br") |
e5bde68a | 4552 | (set_attr "predicable" "no")]) |
c65ebc55 | 4553 | |
6b6c1201 | 4554 | (define_insn "*return_false" |
c65ebc55 | 4555 | [(set (pc) |
6b6c1201 | 4556 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4557 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4558 | (const_int 0)]) |
c65ebc55 JW |
4559 | (pc) |
4560 | (return)))] | |
4561 | "ia64_direct_return ()" | |
13da91fd | 4562 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4563 | [(set_attr "itanium_class" "br") |
e5bde68a | 4564 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4565 | |
4566 | (define_insn "jump" | |
4567 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4568 | "" | |
4569 | "br %l0" | |
52e12ad0 | 4570 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4571 | |
4572 | (define_insn "indirect_jump" | |
4573 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4574 | "" | |
4575 | "br %0" | |
52e12ad0 | 4576 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4577 | |
4578 | (define_expand "tablejump" | |
2283164d | 4579 | [(parallel [(set (pc) (match_operand 0 "memory_operand" "")) |
340f7e7c | 4580 | (use (label_ref (match_operand 1 "" "")))])] |
c65ebc55 | 4581 | "" |
c65ebc55 | 4582 | { |
340f7e7c RH |
4583 | rtx op0 = operands[0]; |
4584 | rtx addr; | |
4585 | ||
4586 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
4587 | element into a register without bothering to see whether that | |
4588 | is necessary given the operand predicate. Check for MEM just | |
4589 | in case someone fixes this. */ | |
4590 | if (GET_CODE (op0) == MEM) | |
4591 | addr = XEXP (op0, 0); | |
4592 | else | |
4593 | { | |
4594 | /* Otherwise, cheat and guess that the previous insn in the | |
4595 | stream was the memory load. Grab the address from that. | |
4596 | Note we have to momentarily pop out of the sequence started | |
4597 | by the insn-emit wrapper in order to grab the last insn. */ | |
e8a54173 DM |
4598 | rtx_insn *last; |
4599 | rtx set; | |
340f7e7c RH |
4600 | |
4601 | end_sequence (); | |
4602 | last = get_last_insn (); | |
4603 | start_sequence (); | |
4604 | set = single_set (last); | |
4605 | ||
e820471b NS |
4606 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
4607 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 4608 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 4609 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 4610 | } |
c65ebc55 | 4611 | |
340f7e7c RH |
4612 | /* Jump table elements are stored pc-relative. That is, a displacement |
4613 | from the entry to the label. Thus to convert to an absolute address | |
4614 | we add the address of the memory from which the value is loaded. */ | |
4615 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
2283164d | 4616 | NULL_RTX, 0, OPTAB_DIRECT); |
340f7e7c | 4617 | }) |
c65ebc55 | 4618 | |
340f7e7c | 4619 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
4620 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
4621 | (use (label_ref (match_operand 1 "" "")))] | |
4622 | "" | |
4623 | "br %0" | |
52e12ad0 | 4624 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4625 | |
4626 | \f | |
4627 | ;; :::::::::::::::::::: | |
4628 | ;; :: | |
4629 | ;; :: Prologue and Epilogue instructions | |
4630 | ;; :: | |
4631 | ;; :::::::::::::::::::: | |
4632 | ||
4633 | (define_expand "prologue" | |
4634 | [(const_int 1)] | |
4635 | "" | |
c65ebc55 JW |
4636 | { |
4637 | ia64_expand_prologue (); | |
4638 | DONE; | |
1d5d7a21 | 4639 | }) |
c65ebc55 JW |
4640 | |
4641 | (define_expand "epilogue" | |
2ed4af6f RH |
4642 | [(return)] |
4643 | "" | |
2ed4af6f RH |
4644 | { |
4645 | ia64_expand_epilogue (0); | |
4646 | DONE; | |
1d5d7a21 | 4647 | }) |
2ed4af6f RH |
4648 | |
4649 | (define_expand "sibcall_epilogue" | |
4650 | [(return)] | |
c65ebc55 | 4651 | "" |
c65ebc55 | 4652 | { |
2ed4af6f | 4653 | ia64_expand_epilogue (1); |
c65ebc55 | 4654 | DONE; |
1d5d7a21 | 4655 | }) |
c65ebc55 JW |
4656 | |
4657 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4658 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
9eb8c09f KY |
4659 | ;; Explicit predicated version of insn needed to check by CODE_FOR_ |
4660 | ;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. | |
c65ebc55 JW |
4661 | |
4662 | (define_insn "prologue_allocate_stack" | |
4663 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4664 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4665 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 4666 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
4667 | (match_dup 3))] |
4668 | "" | |
4669 | "@ | |
1d5d7a21 RH |
4670 | add %0 = %1, %2 |
4671 | adds %0 = %2, %1 | |
4672 | addl %0 = %2, %1" | |
9eb8c09f KY |
4673 | [(set_attr "itanium_class" "ialu") |
4674 | (set_attr "predicable" "no")]) | |
4675 | ||
4676 | (define_insn "prologue_allocate_stack_pr" | |
4677 | [(cond_exec (match_operator 0 ("predicate_operator") | |
4678 | [(match_operand:BI 1 ("register_operand") ("c,c,c")) | |
4679 | (const_int 0)]) | |
4680 | (parallel | |
4681 | [(set (match_operand:DI 2 "register_operand" "=r,r,r") | |
4682 | (plus:DI (match_operand:DI 3 "register_operand" "%r,r,a") | |
4683 | (match_operand:DI 4 "gr_reg_or_22bit_operand" "r,I,J"))) | |
4684 | (set (match_operand:DI 5 "register_operand" "+r,r,r") | |
4685 | (match_dup 5))]))] | |
4686 | "" | |
4687 | "@ | |
4688 | (%J0) add %2 = %3, %4 | |
4689 | (%J0) adds %2 = %3, %4 | |
4690 | (%J0) addl %2 = %3, %4" | |
4691 | [(set_attr "itanium_class" "ialu") | |
4692 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
4693 | |
4694 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4695 | ;; stack accesses. This is similar to movdi plus the extra set. | |
9eb8c09f KY |
4696 | ;; Explicit predicated version of insn needed to check by CODE_FOR_ |
4697 | ;; in ia64_single_set, where despite of 2 sets this define_insn should be OK. | |
c65ebc55 JW |
4698 | |
4699 | (define_insn "epilogue_deallocate_stack" | |
4700 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4701 | (match_operand:DI 1 "register_operand" "+r")) | |
4702 | (set (match_dup 1) (match_dup 1))] | |
4703 | "" | |
4704 | "mov %0 = %1" | |
9eb8c09f KY |
4705 | [(set_attr "itanium_class" "ialu") |
4706 | (set_attr "predicable" "no")]) | |
4707 | ||
4708 | (define_insn "epilogue_deallocate_stack_pr" | |
4709 | [(cond_exec (match_operator 0 ("predicate_operator") | |
4710 | [(match_operand:BI 1 ("register_operand") ("c")) | |
4711 | (const_int 0)]) | |
4712 | (parallel | |
4713 | [(set (match_operand:DI 2 "register_operand" "=r") | |
4714 | (match_operand:DI 3 "register_operand" "+r")) | |
4715 | (set (match_dup 3) (match_dup 3))]))] | |
4716 | "" | |
4717 | "(%J0) mov %2 = %3" | |
4718 | [(set_attr "itanium_class" "ialu") | |
4719 | (set_attr "predicable" "no")]) | |
c65ebc55 | 4720 | |
1d5d7a21 RH |
4721 | ;; As USE insns aren't meaningful after reload, this is used instead |
4722 | ;; to prevent deleting instructions setting registers for EH handling | |
4723 | (define_insn "prologue_use" | |
4724 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
4725 | UNSPEC_PROLOGUE_USE)] | |
4726 | "" | |
4727 | "" | |
4728 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
4729 | (set_attr "predicable" "no") |
4730 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 4731 | |
c65ebc55 JW |
4732 | ;; Allocate a new register frame. |
4733 | ||
4734 | (define_insn "alloc" | |
4735 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4736 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
4737 | (use (match_operand:DI 1 "const_int_operand" "i")) |
4738 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4739 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4740 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4741 | "" | |
4742 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4743 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
4744 | (set_attr "predicable" "no") |
4745 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 4746 | |
97e242b0 RH |
4747 | ;; Modifies ar.unat |
4748 | (define_expand "gr_spill" | |
870f9ec0 RH |
4749 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4750 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
4751 | (match_operand:DI 2 "const_int_operand" "")] |
4752 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4753 | (clobber (match_dup 3))])] |
97e242b0 | 4754 | "" |
870f9ec0 | 4755 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4756 | |
870f9ec0 | 4757 | (define_insn "gr_spill_internal" |
b6fb7d46 | 4758 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 4759 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
4760 | (match_operand:DI 2 "const_int_operand" "")] |
4761 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 4762 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4763 | "" |
2130b7fb | 4764 | { |
1d5d7a21 RH |
4765 | /* Note that we use a C output pattern here to avoid the predicate |
4766 | being automatically added before the .mem.offset directive. */ | |
4767 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
4768 | } | |
52e12ad0 | 4769 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4770 | |
97e242b0 RH |
4771 | ;; Reads ar.unat |
4772 | (define_expand "gr_restore" | |
870f9ec0 RH |
4773 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4774 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
4775 | (match_operand:DI 2 "const_int_operand" "")] |
4776 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4777 | (use (match_dup 3))])] |
97e242b0 | 4778 | "" |
870f9ec0 | 4779 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4780 | |
870f9ec0 | 4781 | (define_insn "gr_restore_internal" |
c65ebc55 | 4782 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 4783 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
4784 | (match_operand:DI 2 "const_int_operand" "")] |
4785 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 4786 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 4787 | "" |
1d5d7a21 | 4788 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 4789 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4790 | |
4791 | (define_insn "fr_spill" | |
b6fb7d46 | 4792 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 4793 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 4794 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
4795 | "" |
4796 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 4797 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
4798 | |
4799 | (define_insn "fr_restore" | |
02befdf4 ZW |
4800 | [(set (match_operand:XF 0 "register_operand" "=f") |
4801 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 4802 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
4803 | "" |
4804 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 4805 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 4806 | |
0024a804 JW |
4807 | ;; ??? The explicit stop is not ideal. It would be better if |
4808 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4809 | ;; fixed later. This avoids an RSE DV. | |
4810 | ||
0c96007e AM |
4811 | (define_insn "bsp_value" |
4812 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 4813 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 4814 | "" |
582d11e6 JW |
4815 | "* |
4816 | { | |
4817 | return \";;\;%,mov %0 = ar.bsp\"; | |
4818 | }" | |
52e12ad0 | 4819 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
4820 | |
4821 | (define_insn "set_bsp" | |
086c0f96 RH |
4822 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
4823 | UNSPECV_SET_BSP)] | |
0c96007e | 4824 | "" |
1d5d7a21 RH |
4825 | "flushrs |
4826 | mov r19=ar.rsc | |
4827 | ;; | |
4828 | and r19=0x1c,r19 | |
4829 | ;; | |
4830 | mov ar.rsc=r19 | |
4831 | ;; | |
4832 | mov ar.bspstore=%0 | |
4833 | ;; | |
4834 | or r19=0x3,r19 | |
4835 | ;; | |
4836 | loadrs | |
4837 | invala | |
4838 | ;; | |
4839 | mov ar.rsc=r19" | |
52e12ad0 | 4840 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 4841 | (set_attr "predicable" "no")]) |
ce152ef8 | 4842 | |
0024a804 JW |
4843 | ;; ??? The explicit stops are not ideal. It would be better if |
4844 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4845 | ;; fixed later. This avoids an RSE DV. | |
4846 | ||
ce152ef8 | 4847 | (define_insn "flushrs" |
086c0f96 | 4848 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 4849 | "" |
0024a804 | 4850 | ";;\;flushrs\;;;" |
582d11e6 JW |
4851 | [(set_attr "itanium_class" "rse_m") |
4852 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
4853 | \f |
4854 | ;; :::::::::::::::::::: | |
4855 | ;; :: | |
4856 | ;; :: Miscellaneous instructions | |
4857 | ;; :: | |
4858 | ;; :::::::::::::::::::: | |
4859 | ||
839a4992 | 4860 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
4861 | ;; be emitting ";;" to force a break in the instruction packing. |
4862 | ||
4863 | ;; No operation, needed in case the user uses -g but not -O. | |
4864 | (define_insn "nop" | |
4865 | [(const_int 0)] | |
4866 | "" | |
4867 | "nop 0" | |
30028c85 | 4868 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 4869 | |
2130b7fb BS |
4870 | (define_insn "nop_m" |
4871 | [(const_int 1)] | |
4872 | "" | |
4873 | "nop.m 0" | |
4874 | [(set_attr "itanium_class" "nop_m")]) | |
4875 | ||
4876 | (define_insn "nop_i" | |
4877 | [(const_int 2)] | |
4878 | "" | |
4879 | "nop.i 0" | |
4880 | [(set_attr "itanium_class" "nop_i")]) | |
4881 | ||
4882 | (define_insn "nop_f" | |
4883 | [(const_int 3)] | |
4884 | "" | |
4885 | "nop.f 0" | |
4886 | [(set_attr "itanium_class" "nop_f")]) | |
4887 | ||
4888 | (define_insn "nop_b" | |
4889 | [(const_int 4)] | |
4890 | "" | |
4891 | "nop.b 0" | |
4892 | [(set_attr "itanium_class" "nop_b")]) | |
4893 | ||
4894 | (define_insn "nop_x" | |
4895 | [(const_int 5)] | |
4896 | "" | |
4897 | "" | |
fa978426 AS |
4898 | [(set_attr "itanium_class" "nop_x") |
4899 | (set_attr "empty" "yes")]) | |
2130b7fb | 4900 | |
30028c85 VM |
4901 | ;; The following insn will be never generated. It is used only by |
4902 | ;; insn scheduler to change state before advancing cycle. | |
4903 | (define_insn "pre_cycle" | |
4904 | [(const_int 6)] | |
4905 | "" | |
4906 | "" | |
4907 | [(set_attr "itanium_class" "pre_cycle")]) | |
4908 | ||
2130b7fb | 4909 | (define_insn "bundle_selector" |
086c0f96 | 4910 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 4911 | "" |
1d5d7a21 | 4912 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
4913 | [(set_attr "itanium_class" "ignore") |
4914 | (set_attr "predicable" "no")]) | |
4915 | ||
c65ebc55 JW |
4916 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
4917 | ;; point. | |
4918 | (define_insn "blockage" | |
086c0f96 | 4919 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
4920 | "" |
4921 | "" | |
52e12ad0 | 4922 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 4923 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4924 | |
4925 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
4926 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
4927 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
4928 | "" |
4929 | ";;" | |
52e12ad0 | 4930 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
4931 | (set_attr "predicable" "no") |
4932 | (set_attr "empty" "yes")]) | |
c65ebc55 | 4933 | |
26406018 RH |
4934 | (define_expand "trap" |
4935 | [(trap_if (const_int 1) (const_int 0))] | |
4936 | "" | |
4937 | "") | |
4938 | ||
4939 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
4940 | ;; produces worse code that setting the slot type to A. | |
4941 | ||
4942 | (define_insn "*trap" | |
4943 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
4944 | "" | |
4945 | "break %0" | |
048d0d36 | 4946 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 | 4947 | |
f90b7a5a PB |
4948 | (define_expand "ctrapbi4" |
4949 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4950 | [(match_operand:BI 1 "register_operand" "") | |
4951 | (match_operand:BI 2 "const_int_operand" "")]) | |
4952 | (match_operand 3 "" ""))] | |
26406018 | 4953 | "" |
f90b7a5a PB |
4954 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") |
4955 | ||
4956 | (define_expand "ctrapsi4" | |
4957 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4958 | [(match_operand:SI 1 "gr_register_operand" "") | |
4959 | (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4960 | (match_operand 3 "" ""))] | |
4961 | "" | |
4962 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4963 | ||
4964 | (define_expand "ctrapdi4" | |
4965 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4966 | [(match_operand:DI 1 "gr_register_operand" "") | |
4967 | (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")]) | |
4968 | (match_operand 3 "" ""))] | |
4969 | "" | |
4970 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4971 | ||
4972 | (define_expand "ctrapsf4" | |
4973 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4974 | [(match_operand:SF 1 "fr_reg_or_fp01_operand" "") | |
4975 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")]) | |
4976 | (match_operand 3 "" ""))] | |
4977 | "" | |
4978 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4979 | ||
4980 | (define_expand "ctrapdf4" | |
4981 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4982 | [(match_operand:DF 1 "fr_reg_or_fp01_operand" "") | |
4983 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")]) | |
4984 | (match_operand 3 "" ""))] | |
4985 | "" | |
4986 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4987 | ||
4988 | (define_expand "ctrapxf4" | |
4989 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4990 | [(match_operand:XF 1 "xfreg_or_fp01_operand" "") | |
4991 | (match_operand:XF 2 "xfreg_or_fp01_operand" "")]) | |
4992 | (match_operand 3 "" ""))] | |
4993 | "" | |
4994 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
4995 | ||
4996 | (define_expand "ctraptf4" | |
4997 | [(trap_if (match_operator 0 "ia64_cbranch_operator" | |
4998 | [(match_operand:TF 1 "gr_register_operand" "") | |
4999 | (match_operand:TF 2 "gr_register_operand" "")]) | |
5000 | (match_operand 3 "" ""))] | |
5001 | "TARGET_HPUX" | |
5002 | "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);") | |
5003 | ||
26406018 RH |
5004 | |
5005 | (define_insn "*conditional_trap" | |
5006 | [(trap_if (match_operator 0 "predicate_operator" | |
5007 | [(match_operand:BI 1 "register_operand" "c") | |
5008 | (const_int 0)]) | |
5009 | (match_operand 2 "const_int_operand" ""))] | |
5010 | "" | |
5cf63e3f | 5011 | "(%J0) break %2" |
048d0d36 | 5012 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
5013 | (set_attr "predicable" "no")]) |
5014 | ||
f12f25a7 | 5015 | (define_insn "break_f" |
086c0f96 | 5016 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
5017 | "" |
5018 | "break.f 0" | |
5019 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5020 | |
5021 | (define_insn "prefetch" | |
5022 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5023 | (match_operand:DI 1 "const_int_operand" "n") | |
5024 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5025 | "" | |
5026 | { | |
5027 | static const char * const alt[2][4] = { | |
b3656137 | 5028 | { |
92cbea22 L |
5029 | "%,lfetch.nta [%0]", |
5030 | "%,lfetch.nt1 [%0]", | |
5031 | "%,lfetch.nt2 [%0]", | |
5032 | "%,lfetch [%0]" | |
b3656137 KG |
5033 | }, |
5034 | { | |
92cbea22 L |
5035 | "%,lfetch.excl.nta [%0]", |
5036 | "%,lfetch.excl.nt1 [%0]", | |
5037 | "%,lfetch.excl.nt2 [%0]", | |
5038 | "%,lfetch.excl [%0]" | |
b3656137 | 5039 | } |
44eca121 JJ |
5040 | }; |
5041 | int i = (INTVAL (operands[1])); | |
5042 | int j = (INTVAL (operands[2])); | |
5043 | ||
e820471b NS |
5044 | gcc_assert (i == 0 || i == 1); |
5045 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
5046 | return alt[i][j]; |
5047 | } | |
5048 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5049 | \f |
5050 | ;; Non-local goto support. | |
5051 | ||
5052 | (define_expand "save_stack_nonlocal" | |
5053 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5054 | (use (match_operand:DI 1 "register_operand" ""))] | |
5055 | "" | |
c65ebc55 JW |
5056 | { |
5057 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5058 | \"__ia64_save_stack_nonlocal\"), | |
bbbbb16a | 5059 | LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode, |
c65ebc55 JW |
5060 | operands[1], Pmode); |
5061 | DONE; | |
1d5d7a21 | 5062 | }) |
c65ebc55 JW |
5063 | |
5064 | (define_expand "nonlocal_goto" | |
5065 | [(use (match_operand 0 "general_operand" "")) | |
5066 | (use (match_operand 1 "general_operand" "")) | |
5067 | (use (match_operand 2 "general_operand" "")) | |
5068 | (use (match_operand 3 "general_operand" ""))] | |
5069 | "" | |
c65ebc55 | 5070 | { |
c65ebc55 | 5071 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5072 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5073 | operands[1], Pmode, |
c65ebc55 | 5074 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5075 | operands[3], Pmode); |
c65ebc55 JW |
5076 | emit_barrier (); |
5077 | DONE; | |
1d5d7a21 | 5078 | }) |
c65ebc55 | 5079 | |
39a5cfa4 SE |
5080 | (define_insn_and_split "nonlocal_goto_receiver" |
5081 | [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)] | |
5082 | "" | |
5083 | "#" | |
5084 | "reload_completed" | |
5085 | [(const_int 0)] | |
5086 | { | |
5087 | ia64_reload_gp (); | |
5088 | DONE; | |
5089 | }) | |
5090 | ||
b39eb2f9 RH |
5091 | (define_insn_and_split "builtin_setjmp_receiver" |
5092 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 5093 | "" |
b39eb2f9 RH |
5094 | "#" |
5095 | "reload_completed" | |
5096 | [(const_int 0)] | |
97e242b0 | 5097 | { |
599aedd9 | 5098 | ia64_reload_gp (); |
c65ebc55 | 5099 | DONE; |
1d5d7a21 | 5100 | }) |
c65ebc55 | 5101 | |
0c96007e AM |
5102 | (define_expand "eh_epilogue" |
5103 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5104 | (use (match_operand:DI 1 "register_operand" "r")) | |
5105 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5106 | "" | |
0c96007e AM |
5107 | { |
5108 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5109 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5110 | ||
5111 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5112 | { | |
5113 | emit_move_insn (bsp, operands[0]); | |
5114 | operands[0] = bsp; | |
5115 | } | |
5116 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5117 | { | |
5118 | emit_move_insn (sp, operands[2]); | |
5119 | operands[2] = sp; | |
5120 | } | |
c41c1387 RS |
5121 | emit_use (sp); |
5122 | emit_use (bsp); | |
0c96007e AM |
5123 | |
5124 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5125 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5126 | }) |
9525c690 JW |
5127 | \f |
5128 | ;; Builtin apply support. | |
5129 | ||
5130 | (define_expand "restore_stack_nonlocal" | |
5131 | [(use (match_operand:DI 0 "register_operand" "")) | |
5132 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5133 | "" | |
9525c690 JW |
5134 | { |
5135 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5136 | "__ia64_restore_stack_nonlocal"), |
bbbbb16a | 5137 | LCT_NORMAL, VOIDmode, 1, |
9525c690 JW |
5138 | copy_to_reg (XEXP (operands[1], 0)), Pmode); |
5139 | DONE; | |
1d5d7a21 | 5140 | }) |
9525c690 | 5141 | |
e5bde68a RH |
5142 | \f |
5143 | ;; Predication. | |
5144 | ||
5145 | (define_cond_exec | |
5146 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5147 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5148 | (const_int 0)])] |
5149 | "" | |
5150 | "(%J0)") | |
3b572406 RH |
5151 | |
5152 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 5153 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 5154 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 5155 | "" |
054451ea | 5156 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5157 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5158 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5159 | |
5160 | (define_insn "safe_across_calls_all" | |
086c0f96 | 5161 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
5162 | "" |
5163 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5164 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5165 | (set_attr "predicable" "no")]) |
5166 | ||
5167 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 5168 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 5169 | "" |
ca3920ad | 5170 | { |
1bc7c5b6 | 5171 | emit_safe_across_calls (); |
1d5d7a21 RH |
5172 | return ""; |
5173 | } | |
52e12ad0 | 5174 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5175 | (set_attr "predicable" "no")]) |
5176 | ||
27a9b99d | 5177 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
5178 | ;; pointer. This is used by the HP-UX 32 bit mode. |
5179 | ||
5180 | (define_insn "ptr_extend" | |
5181 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
5182 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
5183 | UNSPEC_ADDP4))] | |
6dd12198 SE |
5184 | "" |
5185 | "addp4 %0 = 0,%1" | |
5186 | [(set_attr "itanium_class" "ialu")]) | |
5187 | ||
e206a74f SE |
5188 | ;; |
5189 | ;; Optimizations for ptr_extend | |
5190 | ||
36c216e5 | 5191 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
5192 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5193 | (unspec:DI | |
5194 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5195 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 5196 | UNSPEC_ADDP4))] |
08744705 | 5197 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5198 | "addp4 %0 = %2, %1" |
5199 | [(set_attr "itanium_class" "ialu")]) | |
5200 | ||
5201 | (define_insn "*ptr_extend_plus_2" | |
5202 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5203 | (unspec:DI | |
5204 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5205 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 5206 | UNSPEC_ADDP4))] |
08744705 | 5207 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
5208 | "addp4 %0 = %1, %2" |
5209 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 5210 | |
d26afa4f SE |
5211 | ;; |
5212 | ;; Get instruction pointer | |
5213 | ||
5214 | (define_insn "ip_value" | |
5215 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5216 | (pc))] | |
5217 | "" | |
5218 | "mov %0 = ip" | |
6107a6ae | 5219 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 5220 | |
7b84aac0 EB |
5221 | ;; |
5222 | ;; Stack checking | |
5223 | ||
5224 | (define_insn "probe_stack_address" | |
5225 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] | |
5226 | UNSPECV_PROBE_STACK_ADDRESS)] | |
5227 | "" | |
5228 | "probe.w.fault %0, 0" | |
5229 | [(set_attr "itanium_class" "chk_s_i")]) | |
5230 | ||
5231 | (define_insn "probe_stack_range" | |
5232 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5233 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "0") | |
5234 | (match_operand:DI 2 "register_operand" "r")] | |
5235 | UNSPECV_PROBE_STACK_RANGE))] | |
5236 | "" | |
5237 | "* return output_probe_stack_range (operands[0], operands[2]);" | |
5238 | [(set_attr "itanium_class" "unknown") | |
5239 | (set_attr "predicable" "no")]) | |
5240 | ||
f61134e8 RH |
5241 | ;; Vector operations |
5242 | (include "vect.md") | |
af795c3c RH |
5243 | ;; Atomic operations |
5244 | (include "sync.md") | |
4883241c SE |
5245 | ;; New division operations |
5246 | (include "div.md") |