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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
bbbbb16a ILT |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
3 | ;; 2009 Free Software Foundation, Inc. | |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 | 10 | ;; it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | ;; the Free Software Foundation; either version 3, or (at your option) |
c65ebc55 JW |
12 | ;; any later version. |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
c65ebc55 JW |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
086c0f96 | 51 | (define_constants |
7b6e506e RH |
52 | [; Relocations |
53 | (UNSPEC_LTOFF_DTPMOD 0) | |
54 | (UNSPEC_LTOFF_DTPREL 1) | |
55 | (UNSPEC_DTPREL 2) | |
56 | (UNSPEC_LTOFF_TPREL 3) | |
57 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 58 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
59 | |
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
046625fa | 81 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 82 | (UNSPEC_VECT_EXTR 31) |
048d0d36 MK |
83 | (UNSPEC_LDA 40) |
84 | (UNSPEC_LDS 41) | |
388092d5 AB |
85 | (UNSPEC_LDS_A 42) |
86 | (UNSPEC_LDSA 43) | |
87 | (UNSPEC_LDCCLR 44) | |
88 | (UNSPEC_LDCNC 45) | |
89 | (UNSPEC_CHKACLR 46) | |
90 | (UNSPEC_CHKANC 47) | |
91 | (UNSPEC_CHKS 48) | |
92 | (UNSPEC_FR_RECIP_APPROX_RES 49) | |
93 | (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50) | |
086c0f96 RH |
94 | ]) |
95 | ||
96 | (define_constants | |
97 | [(UNSPECV_ALLOC 0) | |
98 | (UNSPECV_BLOCKAGE 1) | |
99 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
100 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
101 | (UNSPECV_SET_BSP 4) |
102 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
103 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 104 | (UNSPECV_SETJMP_RECEIVER 7) |
39a5cfa4 | 105 | (UNSPECV_GOTO_RECEIVER 8) |
086c0f96 | 106 | ]) |
e543e219 | 107 | |
7905f799 | 108 | (include "predicates.md") |
13f70342 | 109 | (include "constraints.md") |
c65ebc55 JW |
110 | \f |
111 | ;; :::::::::::::::::::: | |
112 | ;; :: | |
113 | ;; :: Attributes | |
114 | ;; :: | |
115 | ;; :::::::::::::::::::: | |
116 | ||
30028c85 VM |
117 | ;; Processor type. This attribute must exactly match the processor_type |
118 | ;; enumeration in ia64.h. | |
bbbbb16a ILT |
119 | (define_attr "cpu" "itanium,itanium2" |
120 | (const (symbol_ref "((enum attr_cpu) ia64_tune)"))) | |
30028c85 | 121 | |
c65ebc55 JW |
122 | ;; Instruction type. This primarily determines how instructions can be |
123 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
124 | ||
125 | ;; A alu, can go in I or M syllable of a bundle | |
126 | ;; I integer | |
127 | ;; M memory | |
128 | ;; F floating-point | |
129 | ;; B branch | |
130 | ;; L long immediate, takes two syllables | |
131 | ;; S stop bit | |
132 | ||
133 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
134 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
135 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
136 | ;; which emit instruction that can go in any slot (e.g. nop). | |
137 | ||
1d5d7a21 | 138 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
a71aef0b | 139 | fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf, |
048d0d36 | 140 | ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
f61134e8 RH |
141 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, |
142 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 143 | (const_string "unknown")) |
52e12ad0 | 144 | |
048d0d36 | 145 | ;; chk_s_i has an I and an M form; use type A for convenience. |
2130b7fb | 146 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" |
a71aef0b | 147 | (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M") |
52e12ad0 BS |
148 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
149 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 150 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
048d0d36 MK |
151 | (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M") |
152 | (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua") | |
f61134e8 | 153 | (const_string "A") |
2130b7fb BS |
154 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
155 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
156 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
157 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
158 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
159 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 160 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 161 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
162 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
163 | (const_string "unknown"))) | |
c65ebc55 | 164 | |
2130b7fb BS |
165 | (define_attr "itanium_requires_unit0" "no,yes" |
166 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
167 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
168 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
169 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
170 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
171 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
172 | (const_string "no"))) | |
173 | ||
e5bde68a RH |
174 | ;; Predication. True iff this instruction can be predicated. |
175 | ||
176 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
177 | ||
fa978426 AS |
178 | ;; Empty. True iff this insn does not generate any code. |
179 | ||
180 | (define_attr "empty" "no,yes" (const_string "no")) | |
181 | ||
68e11b42 JW |
182 | ;; True iff this insn must be the first insn of an instruction group. |
183 | ;; This is true for the alloc instruction, and will also be true of others | |
184 | ;; when we have full intrinsics support. | |
185 | ||
186 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
048d0d36 MK |
187 | |
188 | (define_attr "data_speculative" "no,yes" (const_string "no")) | |
189 | ||
190 | (define_attr "control_speculative" "no,yes" (const_string "no")) | |
191 | ||
192 | (define_attr "check_load" "no,yes" (const_string "no")) | |
388092d5 AB |
193 | |
194 | (define_attr "speculable1" "no,yes" (const_string "no")) | |
195 | ||
196 | (define_attr "speculable2" "no,yes" (const_string "no")) | |
c65ebc55 | 197 | \f |
30028c85 VM |
198 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
199 | ;; bundling. | |
200 | ||
201 | (automata_option "ndfa") | |
202 | ||
203 | ;; Uncomment the following line to output automata for debugging. | |
204 | ;; (automata_option "v") | |
205 | ||
206 | (automata_option "w") | |
207 | ||
30028c85 VM |
208 | (include "itanium1.md") |
209 | (include "itanium2.md") | |
210 | ||
c65ebc55 JW |
211 | \f |
212 | ;; :::::::::::::::::::: | |
213 | ;; :: | |
214 | ;; :: Moves | |
215 | ;; :: | |
216 | ;; :::::::::::::::::::: | |
217 | ||
f2f90c63 RH |
218 | ;; Set of a single predicate register. This is only used to implement |
219 | ;; pr-to-pr move and complement. | |
220 | ||
221 | (define_insn "*movcci" | |
222 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
223 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
224 | "" | |
225 | "@ | |
226 | cmp.ne %0, p0 = r0, r0 | |
227 | cmp.eq %0, p0 = r0, r0 | |
228 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 229 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
230 | (set_attr "predicable" "no")]) |
231 | ||
232 | (define_insn "movbi" | |
b6fb7d46 JW |
233 | [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
234 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
235 | "" |
236 | "@ | |
237 | cmp.ne %0, %I0 = r0, r0 | |
238 | cmp.eq %0, %I0 = r0, r0 | |
239 | # | |
240 | # | |
241 | tbit.nz %0, %I0 = %1, 0 | |
242 | adds %0 = %1, r0 | |
243 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
244 | st1%Q0 %0 = %1%P0 |
245 | mov %0 = %1" | |
388092d5 AB |
246 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu") |
247 | (set_attr "speculable1" "yes") | |
248 | (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")]) | |
f2f90c63 RH |
249 | |
250 | (define_split | |
251 | [(set (match_operand:BI 0 "register_operand" "") | |
252 | (match_operand:BI 1 "register_operand" ""))] | |
253 | "reload_completed | |
254 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
255 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
256 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
257 | (set (match_dup 0) (const_int 1))) | |
258 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
259 | (set (match_dup 0) (const_int 0)))] | |
260 | "") | |
261 | ||
262 | (define_split | |
263 | [(set (match_operand:BI 0 "register_operand" "") | |
264 | (match_operand:BI 1 "register_operand" ""))] | |
265 | "reload_completed | |
266 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
267 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
268 | [(set (match_dup 2) (match_dup 4)) | |
269 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 270 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
271 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
272 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
273 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
274 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
275 | ||
c65ebc55 JW |
276 | (define_expand "movqi" |
277 | [(set (match_operand:QI 0 "general_operand" "") | |
278 | (match_operand:QI 1 "general_operand" ""))] | |
279 | "" | |
c65ebc55 | 280 | { |
7b6e506e RH |
281 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
282 | if (!op1) | |
283 | DONE; | |
284 | operands[1] = op1; | |
1d5d7a21 | 285 | }) |
c65ebc55 | 286 | |
388092d5 | 287 | (define_insn "movqi_internal" |
4b983fdc RH |
288 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
289 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 290 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 291 | "@ |
13da91fd | 292 | mov %0 = %r1 |
c65ebc55 JW |
293 | addl %0 = %1, r0 |
294 | ld1%O1 %0 = %1%P1 | |
13da91fd | 295 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 296 | getf.sig %0 = %1 |
13da91fd RH |
297 | setf.sig %0 = %r1 |
298 | mov %0 = %1" | |
388092d5 AB |
299 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
300 | (set_attr "speculable1" "yes") | |
301 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
302 | |
303 | (define_expand "movhi" | |
304 | [(set (match_operand:HI 0 "general_operand" "") | |
305 | (match_operand:HI 1 "general_operand" ""))] | |
306 | "" | |
c65ebc55 | 307 | { |
7b6e506e RH |
308 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
309 | if (!op1) | |
310 | DONE; | |
311 | operands[1] = op1; | |
1d5d7a21 | 312 | }) |
c65ebc55 | 313 | |
388092d5 | 314 | (define_insn "movhi_internal" |
4b983fdc RH |
315 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
316 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 317 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 318 | "@ |
13da91fd | 319 | mov %0 = %r1 |
c65ebc55 JW |
320 | addl %0 = %1, r0 |
321 | ld2%O1 %0 = %1%P1 | |
13da91fd | 322 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 323 | getf.sig %0 = %1 |
13da91fd RH |
324 | setf.sig %0 = %r1 |
325 | mov %0 = %1" | |
388092d5 AB |
326 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc") |
327 | (set_attr "speculable1" "yes") | |
328 | (set_attr "speculable2" "no, no, yes,no,no, no, no")]) | |
c65ebc55 JW |
329 | |
330 | (define_expand "movsi" | |
331 | [(set (match_operand:SI 0 "general_operand" "") | |
332 | (match_operand:SI 1 "general_operand" ""))] | |
333 | "" | |
c65ebc55 | 334 | { |
7b6e506e RH |
335 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
336 | if (!op1) | |
337 | DONE; | |
338 | operands[1] = op1; | |
1d5d7a21 | 339 | }) |
c65ebc55 | 340 | |
388092d5 | 341 | (define_insn "movsi_internal" |
4e483a22 JB |
342 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d") |
343 | (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))] | |
aebf2462 | 344 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 345 | "@ |
13da91fd | 346 | mov %0 = %r1 |
c65ebc55 | 347 | addl %0 = %1, r0 |
4e483a22 | 348 | addp4 %0 = %1 - 0x100000000, r0 |
c65ebc55 JW |
349 | movl %0 = %1 |
350 | ld4%O1 %0 = %1%P1 | |
13da91fd | 351 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 352 | getf.sig %0 = %1 |
13da91fd | 353 | setf.sig %0 = %r1 |
97e242b0 RH |
354 | mov %0 = %1 |
355 | mov %0 = %1 | |
356 | mov %0 = %r1" | |
1d5d7a21 | 357 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
388092d5 AB |
358 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m") |
359 | (set_attr "speculable1" "yes") | |
360 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")]) | |
c65ebc55 JW |
361 | |
362 | (define_expand "movdi" | |
363 | [(set (match_operand:DI 0 "general_operand" "") | |
364 | (match_operand:DI 1 "general_operand" ""))] | |
365 | "" | |
c65ebc55 | 366 | { |
7b6e506e RH |
367 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
368 | if (!op1) | |
369 | DONE; | |
370 | operands[1] = op1; | |
1d5d7a21 | 371 | }) |
c65ebc55 | 372 | |
388092d5 | 373 | (define_insn "movdi_internal" |
4b983fdc | 374 | [(set (match_operand:DI 0 "destination_operand" |
4e483a22 | 375 | "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 376 | (match_operand:DI 1 "move_operand" |
4e483a22 | 377 | "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 378 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
379 | { |
380 | static const char * const alt[] = { | |
1d5d7a21 RH |
381 | "%,mov %0 = %r1", |
382 | "%,addl %0 = %1, r0", | |
4e483a22 | 383 | "%,addp4 %0 = %1 - 0x100000000, r0", |
1d5d7a21 RH |
384 | "%,movl %0 = %1", |
385 | "%,ld8%O1 %0 = %1%P1", | |
386 | "%,st8%Q0 %0 = %r1%P0", | |
387 | "%,getf.sig %0 = %1", | |
388 | "%,setf.sig %0 = %r1", | |
389 | "%,mov %0 = %1", | |
390 | "%,ldf8 %0 = %1%P1", | |
391 | "%,stf8 %0 = %1%P0", | |
392 | "%,mov %0 = %1", | |
393 | "%,mov %0 = %r1", | |
394 | "%,mov %0 = %1", | |
395 | "%,mov %0 = %1", | |
396 | "%,mov %0 = %1", | |
397 | "%,mov %0 = %1", | |
398 | "mov %0 = pr", | |
399 | "mov pr = %1, -1" | |
9b7bf67d RH |
400 | }; |
401 | ||
e820471b NS |
402 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
403 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
404 | |
405 | return alt[which_alternative]; | |
1d5d7a21 | 406 | } |
388092d5 AB |
407 | [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr") |
408 | (set_attr "speculable1" "yes") | |
409 | (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")]) | |
c65ebc55 | 410 | |
3abcb3a7 HPN |
411 | (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI]) |
412 | (define_mode_iterator MODE_FOR_EXTEND [QI HI SI]) | |
048d0d36 MK |
413 | |
414 | (define_mode_attr output_a [ | |
415 | (BI "ld1.a %0 = %1%P1") | |
416 | (QI "ld1.a %0 = %1%P1") | |
417 | (HI "ld2.a %0 = %1%P1") | |
418 | (SI "ld4.a %0 = %1%P1") | |
419 | (DI | |
420 | "@ | |
421 | ld8.a %0 = %1%P1 | |
422 | ldf8.a %0 = %1%P1") | |
423 | (SF | |
424 | "@ | |
425 | ldfs.a %0 = %1%P1 | |
426 | ld4.a %0 = %1%P1") | |
427 | (DF | |
428 | "@ | |
429 | ldfd.a %0 = %1%P1 | |
430 | ld8.a %0 = %1%P1") | |
431 | (XF "ldfe.a %0 = %1%P1") | |
432 | (TI "ldfp8.a %X0 = %1%P1")]) | |
433 | ||
434 | (define_mode_attr output_s [ | |
435 | (BI "ld1.s %0 = %1%P1") | |
436 | (QI "ld1.s %0 = %1%P1") | |
437 | (HI "ld2.s %0 = %1%P1") | |
438 | (SI "ld4.s %0 = %1%P1") | |
439 | (DI | |
440 | "@ | |
441 | ld8.s %0 = %1%P1 | |
442 | ldf8.s %0 = %1%P1") | |
443 | (SF | |
444 | "@ | |
445 | ldfs.s %0 = %1%P1 | |
446 | ld4.s %0 = %1%P1") | |
447 | (DF | |
448 | "@ | |
449 | ldfd.s %0 = %1%P1 | |
450 | ld8.s %0 = %1%P1") | |
451 | (XF "ldfe.s %0 = %1%P1") | |
452 | (TI "ldfp8.s %X0 = %1%P1")]) | |
453 | ||
454 | (define_mode_attr output_sa [ | |
455 | (BI "ld1.sa %0 = %1%P1") | |
456 | (QI "ld1.sa %0 = %1%P1") | |
457 | (HI "ld2.sa %0 = %1%P1") | |
458 | (SI "ld4.sa %0 = %1%P1") | |
459 | (DI | |
460 | "@ | |
461 | ld8.sa %0 = %1%P1 | |
462 | ldf8.sa %0 = %1%P1") | |
463 | (SF | |
464 | "@ | |
465 | ldfs.sa %0 = %1%P1 | |
466 | ld4.sa %0 = %1%P1") | |
467 | (DF | |
468 | "@ | |
469 | ldfd.sa %0 = %1%P1 | |
470 | ld8.sa %0 = %1%P1") | |
471 | (XF "ldfe.sa %0 = %1%P1") | |
472 | (TI "ldfp8.sa %X0 = %1%P1")]) | |
473 | ||
474 | (define_mode_attr output_c_clr [ | |
475 | (BI "ld1.c.clr%O1 %0 = %1%P1") | |
476 | (QI "ld1.c.clr%O1 %0 = %1%P1") | |
477 | (HI "ld2.c.clr%O1 %0 = %1%P1") | |
478 | (SI "ld4.c.clr%O1 %0 = %1%P1") | |
479 | (DI | |
480 | "@ | |
481 | ld8.c.clr%O1 %0 = %1%P1 | |
482 | ldf8.c.clr %0 = %1%P1") | |
483 | (SF | |
484 | "@ | |
485 | ldfs.c.clr %0 = %1%P1 | |
486 | ld4.c.clr%O1 %0 = %1%P1") | |
487 | (DF | |
488 | "@ | |
489 | ldfd.c.clr %0 = %1%P1 | |
490 | ld8.c.clr%O1 %0 = %1%P1") | |
491 | (XF "ldfe.c.clr %0 = %1%P1") | |
492 | (TI "ldfp8.c.clr %X0 = %1%P1")]) | |
493 | ||
388092d5 AB |
494 | (define_mode_attr output_c_nc [ |
495 | (BI "ld1.c.nc%O1 %0 = %1%P1") | |
496 | (QI "ld1.c.nc%O1 %0 = %1%P1") | |
497 | (HI "ld2.c.nc%O1 %0 = %1%P1") | |
498 | (SI "ld4.c.nc%O1 %0 = %1%P1") | |
499 | (DI | |
500 | "@ | |
501 | ld8.c.nc%O1 %0 = %1%P1 | |
502 | ldf8.c.nc %0 = %1%P1") | |
503 | (SF | |
504 | "@ | |
505 | ldfs.c.nc %0 = %1%P1 | |
506 | ld4.c.nc%O1 %0 = %1%P1") | |
507 | (DF | |
508 | "@ | |
509 | ldfd.c.nc %0 = %1%P1 | |
510 | ld8.c.nc%O1 %0 = %1%P1") | |
511 | (XF "ldfe.c.nc %0 = %1%P1") | |
512 | (TI "ldfp8.c.nc %X0 = %1%P1")]) | |
513 | ||
048d0d36 MK |
514 | (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")]) |
515 | (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")]) | |
516 | (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")]) | |
517 | ||
518 | (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) | |
519 | ||
f6ec1d11 MK |
520 | ;; Define register predicate prefix. |
521 | ;; We can generate speculative loads only for general and fp registers - this | |
ea2c620c | 522 | ;; is constrained in ia64.c: ia64_speculate_insn (). |
048d0d36 MK |
523 | (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) |
524 | ||
525 | (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) | |
526 | (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")]) | |
527 | (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")]) | |
528 | ||
529 | (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")]) | |
530 | ||
531 | (define_insn "mov<mode>_advanced" | |
532 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
533 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))] | |
534 | "ia64_move_ok (operands[0], operands[1])" | |
535 | "<output_a>" | |
536 | [(set_attr "itanium_class" "<ld_class>") | |
537 | (set_attr "data_speculative" "<attr_yes>")]) | |
538 | ||
539 | (define_insn "zero_extend<mode>di2_advanced" | |
540 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
541 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))] | |
542 | "" | |
543 | "<output_a>" | |
544 | [(set_attr "itanium_class" "<ld_class>") | |
545 | (set_attr "data_speculative" "<attr_yes>")]) | |
546 | ||
547 | (define_insn "mov<mode>_speculative" | |
548 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
549 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))] | |
550 | "ia64_move_ok (operands[0], operands[1])" | |
551 | "<output_s>" | |
552 | [(set_attr "itanium_class" "<ld_class>") | |
553 | (set_attr "control_speculative" "<attr_yes>")]) | |
554 | ||
555 | (define_insn "zero_extend<mode>di2_speculative" | |
556 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
557 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))] | |
558 | "" | |
559 | "<output_s>" | |
560 | [(set_attr "itanium_class" "<ld_class>") | |
561 | (set_attr "control_speculative" "<attr_yes>")]) | |
562 | ||
563 | (define_insn "mov<mode>_speculative_advanced" | |
564 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
565 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))] | |
566 | "ia64_move_ok (operands[0], operands[1])" | |
567 | "<output_sa>" | |
568 | [(set_attr "itanium_class" "<ld_class>") | |
569 | (set_attr "data_speculative" "<attr_yes>") | |
570 | (set_attr "control_speculative" "<attr_yes>")]) | |
571 | ||
388092d5 AB |
572 | (define_insn "mov<mode>_speculative_a" |
573 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>") | |
574 | (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))] | |
575 | "ia64_move_ok (operands[0], operands[1])" | |
576 | "<output_sa>" | |
577 | [(set_attr "itanium_class" "<ld_class>") | |
578 | (set_attr "data_speculative" "<attr_yes>") | |
579 | (set_attr "control_speculative" "<attr_yes>")]) | |
580 | ||
048d0d36 MK |
581 | (define_insn "zero_extend<mode>di2_speculative_advanced" |
582 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
583 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))] | |
584 | "" | |
585 | "<output_sa>" | |
586 | [(set_attr "itanium_class" "<ld_class>") | |
587 | (set_attr "data_speculative" "<attr_yes>") | |
588 | (set_attr "control_speculative" "<attr_yes>")]) | |
589 | ||
388092d5 AB |
590 | (define_insn "zero_extend<mode>di2_speculative_a" |
591 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
592 | (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))] | |
593 | "" | |
594 | "<output_sa>" | |
595 | [(set_attr "itanium_class" "<ld_class>") | |
596 | (set_attr "data_speculative" "<attr_yes>") | |
597 | (set_attr "control_speculative" "<attr_yes>")]) | |
598 | ||
048d0d36 MK |
599 | (define_insn "mov<mode>_clr" |
600 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
601 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
602 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
603 | (match_dup 0)))] | |
604 | "ia64_move_ok (operands[0], operands[1])" | |
605 | "<output_c_clr>" | |
606 | [(set_attr "itanium_class" "<ld_class>") | |
607 | (set_attr "check_load" "<attr_yes>")]) | |
608 | ||
388092d5 AB |
609 | (define_insn "mov<mode>_nc" |
610 | [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>") | |
611 | (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
612 | (match_operand:MODE 1 "memory_operand" "<mem_constr>") | |
613 | (match_dup 0)))] | |
614 | "ia64_move_ok (operands[0], operands[1])" | |
615 | "<output_c_nc>" | |
616 | [(set_attr "itanium_class" "<ld_class>") | |
617 | (set_attr "check_load" "<attr_yes>")]) | |
618 | ||
048d0d36 MK |
619 | (define_insn "zero_extend<mode>di2_clr" |
620 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
621 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0)) | |
622 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
623 | (match_dup 0)))] | |
624 | "" | |
625 | "<output_c_clr>" | |
626 | [(set_attr "itanium_class" "<ld_class>") | |
627 | (set_attr "check_load" "<attr_yes>")]) | |
628 | ||
388092d5 AB |
629 | (define_insn "zero_extend<mode>di2_nc" |
630 | [(set (match_operand:DI 0 "gr_register_operand" "+r") | |
631 | (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0)) | |
632 | (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")) | |
633 | (match_dup 0)))] | |
634 | "" | |
635 | "<output_c_nc>" | |
636 | [(set_attr "itanium_class" "<ld_class>") | |
637 | (set_attr "check_load" "<attr_yes>")]) | |
638 | ||
048d0d36 MK |
639 | (define_insn "advanced_load_check_clr_<mode>" |
640 | [(set (pc) | |
641 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0)) | |
642 | (pc) | |
643 | (label_ref (match_operand 1 "" ""))))] | |
644 | "" | |
645 | "chk.a.clr %0, %l1" | |
646 | [(set_attr "itanium_class" "<chka_class>")]) | |
647 | ||
388092d5 AB |
648 | (define_insn "advanced_load_check_nc_<mode>" |
649 | [(set (pc) | |
650 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0)) | |
651 | (pc) | |
652 | (label_ref (match_operand 1 "" ""))))] | |
653 | "" | |
654 | "chk.a.clr %0, %l1" | |
655 | [(set_attr "itanium_class" "<chka_class>")]) | |
656 | ||
048d0d36 MK |
657 | (define_insn "speculation_check_<mode>" |
658 | [(set (pc) | |
659 | (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0)) | |
660 | (pc) | |
661 | (label_ref (match_operand 1 "" ""))))] | |
662 | "" | |
663 | "chk.s %0, %l1" | |
664 | [(set_attr "itanium_class" "<chks_class>")]) | |
665 | ||
9b7bf67d | 666 | (define_split |
21515593 RH |
667 | [(set (match_operand 0 "register_operand" "") |
668 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 669 | "reload_completed" |
9b7bf67d | 670 | [(const_int 0)] |
9b7bf67d | 671 | { |
5e6c8b64 RH |
672 | if (ia64_expand_load_address (operands[0], operands[1])) |
673 | DONE; | |
674 | else | |
675 | FAIL; | |
1d5d7a21 | 676 | }) |
9b7bf67d | 677 | |
c65ebc55 | 678 | (define_expand "load_fptr" |
5e6c8b64 RH |
679 | [(set (match_operand:DI 0 "register_operand" "") |
680 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
681 | (set (match_dup 0) (match_dup 3))] | |
682 | "reload_completed" | |
c65ebc55 | 683 | { |
5e6c8b64 RH |
684 | operands[2] = pic_offset_table_rtx; |
685 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 686 | }) |
c65ebc55 JW |
687 | |
688 | (define_insn "*load_fptr_internal1" | |
689 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 690 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 691 | "reload_completed" |
c65ebc55 | 692 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 693 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
694 | |
695 | (define_insn "load_gprel" | |
696 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 697 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 698 | "reload_completed" |
c65ebc55 | 699 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 700 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 701 | |
5e6c8b64 | 702 | (define_insn "*gprel64_offset" |
59da9a7d JW |
703 | [(set (match_operand:DI 0 "register_operand" "=r") |
704 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 705 | "reload_completed" |
59da9a7d | 706 | "movl %0 = @gprel(%1)" |
52e12ad0 | 707 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
708 | |
709 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
710 | [(set (match_operand:DI 0 "register_operand" "") |
711 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
712 | (set (match_dup 0) | |
713 | (plus:DI (match_dup 2) (match_dup 0)))] | |
714 | "reload_completed" | |
ec039e3c | 715 | { |
5e6c8b64 | 716 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 717 | }) |
59da9a7d | 718 | |
af1e5518 RH |
719 | ;; This is used as a placeholder for the return address during early |
720 | ;; compilation. We won't know where we've placed this until during | |
721 | ;; reload, at which point it can wind up in b0, a general register, | |
722 | ;; or memory. The only safe destination under these conditions is a | |
723 | ;; general register. | |
724 | ||
725 | (define_insn_and_split "*movdi_ret_addr" | |
726 | [(set (match_operand:DI 0 "register_operand" "=r") | |
727 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
728 | "" | |
729 | "#" | |
730 | "reload_completed" | |
731 | [(const_int 0)] | |
732 | { | |
733 | ia64_split_return_addr_rtx (operands[0]); | |
734 | DONE; | |
735 | } | |
736 | [(set_attr "itanium_class" "ialu")]) | |
737 | ||
ef1ecf87 | 738 | (define_insn "*load_symptr_high" |
c65ebc55 | 739 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
740 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
741 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 742 | "reload_completed" |
ef1ecf87 RH |
743 | { |
744 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
745 | return "%,addl %0 = @ltoffx(%1), %2"; | |
746 | else | |
747 | return "%,addl %0 = @ltoff(%1), %2"; | |
748 | } | |
52e12ad0 | 749 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 750 | |
ef1ecf87 RH |
751 | (define_insn "*load_symptr_low" |
752 | [(set (match_operand:DI 0 "register_operand" "=r") | |
753 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
754 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 755 | "reload_completed" |
ef1ecf87 RH |
756 | { |
757 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
758 | return "%,ld8.mov %0 = [%1], %2"; | |
759 | else | |
760 | return "%,ld8 %0 = [%1]"; | |
761 | } | |
762 | [(set_attr "itanium_class" "ld")]) | |
763 | ||
5e6c8b64 | 764 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 765 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 766 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 767 | UNSPEC_DTPMOD))] |
7b6e506e | 768 | "" |
5e6c8b64 RH |
769 | "#" |
770 | "reload_completed" | |
771 | [(set (match_dup 0) | |
772 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
773 | (match_dup 2))) | |
774 | (set (match_dup 0) (match_dup 3))] | |
775 | { | |
776 | operands[2] = pic_offset_table_rtx; | |
777 | operands[3] = gen_const_mem (DImode, operands[0]); | |
778 | }) | |
7b6e506e | 779 | |
5e6c8b64 | 780 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 781 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 782 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
783 | UNSPEC_LTOFF_DTPMOD) |
784 | (match_operand:DI 2 "register_operand" "a")))] | |
785 | "reload_completed" | |
786 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
787 | [(set_attr "itanium_class" "ialu")]) |
788 | ||
789 | (define_expand "load_dtprel" | |
790 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 791 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
792 | UNSPEC_DTPREL))] |
793 | "" | |
794 | "") | |
795 | ||
796 | (define_insn "*load_dtprel64" | |
797 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 798 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
799 | UNSPEC_DTPREL))] |
800 | "TARGET_TLS64" | |
801 | "movl %0 = @dtprel(%1)" | |
802 | [(set_attr "itanium_class" "long_i")]) | |
803 | ||
804 | (define_insn "*load_dtprel22" | |
805 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 806 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
807 | UNSPEC_DTPREL))] |
808 | "" | |
809 | "addl %0 = @dtprel(%1), r0" | |
810 | [(set_attr "itanium_class" "ialu")]) | |
811 | ||
5e6c8b64 RH |
812 | (define_insn_and_split "*load_dtprel_gd" |
813 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 814 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
815 | UNSPEC_DTPREL))] |
816 | "" | |
817 | "#" | |
818 | "reload_completed" | |
819 | [(set (match_dup 0) | |
820 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
821 | (match_dup 2))) | |
822 | (set (match_dup 0) (match_dup 3))] | |
823 | { | |
824 | operands[2] = pic_offset_table_rtx; | |
825 | operands[3] = gen_const_mem (DImode, operands[0]); | |
826 | }) | |
827 | ||
828 | (define_insn "*load_ltoff_dtprel" | |
829 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 830 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
831 | UNSPEC_LTOFF_DTPREL) |
832 | (match_operand:DI 2 "register_operand" "a")))] | |
833 | "" | |
834 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
835 | [(set_attr "itanium_class" "ialu")]) | |
836 | ||
7b6e506e RH |
837 | (define_expand "add_dtprel" |
838 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 839 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
840 | UNSPEC_DTPREL) |
841 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
842 | "!TARGET_TLS64" |
843 | "") | |
844 | ||
845 | (define_insn "*add_dtprel14" | |
846 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 847 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
848 | UNSPEC_DTPREL) |
849 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 850 | "TARGET_TLS14" |
5e6c8b64 | 851 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
852 | [(set_attr "itanium_class" "ialu")]) |
853 | ||
854 | (define_insn "*add_dtprel22" | |
855 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 856 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
857 | UNSPEC_DTPREL) |
858 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 859 | "TARGET_TLS22" |
5e6c8b64 | 860 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
861 | [(set_attr "itanium_class" "ialu")]) |
862 | ||
863 | (define_expand "load_tprel" | |
864 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 865 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
866 | UNSPEC_TPREL))] |
867 | "" | |
868 | "") | |
869 | ||
870 | (define_insn "*load_tprel64" | |
871 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 872 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
873 | UNSPEC_TPREL))] |
874 | "TARGET_TLS64" | |
875 | "movl %0 = @tprel(%1)" | |
876 | [(set_attr "itanium_class" "long_i")]) | |
877 | ||
878 | (define_insn "*load_tprel22" | |
879 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 880 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
881 | UNSPEC_TPREL))] |
882 | "" | |
883 | "addl %0 = @tprel(%1), r0" | |
884 | [(set_attr "itanium_class" "ialu")]) | |
885 | ||
5e6c8b64 RH |
886 | (define_insn_and_split "*load_tprel_ie" |
887 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 888 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
889 | UNSPEC_TPREL))] |
890 | "" | |
891 | "#" | |
892 | "reload_completed" | |
893 | [(set (match_dup 0) | |
894 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
895 | (match_dup 2))) | |
896 | (set (match_dup 0) (match_dup 3))] | |
897 | { | |
898 | operands[2] = pic_offset_table_rtx; | |
899 | operands[3] = gen_const_mem (DImode, operands[0]); | |
900 | }) | |
901 | ||
902 | (define_insn "*load_ltoff_tprel" | |
903 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 904 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
905 | UNSPEC_LTOFF_TPREL) |
906 | (match_operand:DI 2 "register_operand" "a")))] | |
907 | "" | |
908 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
909 | [(set_attr "itanium_class" "ialu")]) | |
910 | ||
7b6e506e RH |
911 | (define_expand "add_tprel" |
912 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 913 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
914 | UNSPEC_TPREL) |
915 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
916 | "!TARGET_TLS64" |
917 | "") | |
918 | ||
919 | (define_insn "*add_tprel14" | |
920 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 921 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
922 | UNSPEC_TPREL) |
923 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 924 | "TARGET_TLS14" |
5e6c8b64 | 925 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
926 | [(set_attr "itanium_class" "ialu")]) |
927 | ||
928 | (define_insn "*add_tprel22" | |
929 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 930 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
931 | UNSPEC_TPREL) |
932 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 933 | "TARGET_TLS22" |
5e6c8b64 | 934 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
935 | [(set_attr "itanium_class" "ialu")]) |
936 | ||
3f622353 | 937 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
938 | ;; around to play with the second word. However, in order to avoid a |
939 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
940 | ;; in ia64_split_tmode_move. | |
3f622353 | 941 | (define_expand "movti" |
2ffe0e02 ZW |
942 | [(set (match_operand:TI 0 "general_operand" "") |
943 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 944 | "" |
3f622353 | 945 | { |
7b6e506e RH |
946 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
947 | if (!op1) | |
948 | DONE; | |
949 | operands[1] = op1; | |
1d5d7a21 | 950 | }) |
3f622353 | 951 | |
388092d5 | 952 | (define_insn_and_split "movti_internal" |
b6fb7d46 JW |
953 | [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q") |
954 | (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))] | |
3f622353 | 955 | "ia64_move_ok (operands[0], operands[1])" |
a71aef0b JB |
956 | "@ |
957 | # | |
958 | # | |
959 | ldfp8 %X0 = %1%P1 | |
960 | # | |
961 | #" | |
962 | "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])" | |
3f622353 | 963 | [(const_int 0)] |
3f622353 | 964 | { |
f57fc998 | 965 | ia64_split_tmode_move (operands); |
3f622353 | 966 | DONE; |
1d5d7a21 | 967 | } |
388092d5 AB |
968 | [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown") |
969 | (set_attr "speculable1" "yes") | |
970 | (set_attr "speculable2" "no, no, yes, no, no")]) | |
e314e331 | 971 | |
c65ebc55 JW |
972 | ;; Floating Point Moves |
973 | ;; | |
974 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 975 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
976 | |
977 | (define_expand "movsf" | |
978 | [(set (match_operand:SF 0 "general_operand" "") | |
979 | (match_operand:SF 1 "general_operand" ""))] | |
980 | "" | |
c65ebc55 | 981 | { |
7b6e506e RH |
982 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
983 | if (!op1) | |
984 | DONE; | |
985 | operands[1] = op1; | |
1d5d7a21 | 986 | }) |
c65ebc55 | 987 | |
388092d5 | 988 | (define_insn "movsf_internal" |
4b983fdc RH |
989 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
990 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 991 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 992 | "@ |
1d5d7a21 RH |
993 | mov %0 = %F1 |
994 | ldfs %0 = %1%P1 | |
995 | stfs %0 = %F1%P0 | |
996 | getf.s %0 = %F1 | |
997 | setf.s %0 = %1 | |
998 | mov %0 = %1 | |
999 | ld4%O1 %0 = %1%P1 | |
1000 | st4%Q0 %0 = %1%P0" | |
388092d5 AB |
1001 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st") |
1002 | (set_attr "speculable1" "yes") | |
1003 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")]) | |
c65ebc55 JW |
1004 | |
1005 | (define_expand "movdf" | |
1006 | [(set (match_operand:DF 0 "general_operand" "") | |
1007 | (match_operand:DF 1 "general_operand" ""))] | |
1008 | "" | |
c65ebc55 | 1009 | { |
7b6e506e RH |
1010 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
1011 | if (!op1) | |
1012 | DONE; | |
1013 | operands[1] = op1; | |
1d5d7a21 | 1014 | }) |
c65ebc55 | 1015 | |
388092d5 | 1016 | (define_insn "movdf_internal" |
4b983fdc RH |
1017 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
1018 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 1019 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1020 | "@ |
1d5d7a21 RH |
1021 | mov %0 = %F1 |
1022 | ldfd %0 = %1%P1 | |
1023 | stfd %0 = %F1%P0 | |
1024 | getf.d %0 = %F1 | |
1025 | setf.d %0 = %1 | |
1026 | mov %0 = %1 | |
1027 | ld8%O1 %0 = %1%P1 | |
1028 | st8%Q0 %0 = %1%P0" | |
388092d5 AB |
1029 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st") |
1030 | (set_attr "speculable1" "yes") | |
1031 | (set_attr "speculable2" "no, yes,no, no, no, no, yes,no")]) | |
c65ebc55 | 1032 | |
3f622353 RH |
1033 | ;; With no offsettable memory references, we've got to have a scratch |
1034 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1035 | (define_expand "movxf" |
1036 | [(set (match_operand:XF 0 "general_operand" "") | |
1037 | (match_operand:XF 1 "general_operand" ""))] | |
1038 | "" | |
e5bde68a | 1039 | { |
4de67c26 JM |
1040 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
1041 | DONE; | |
1d5d7a21 | 1042 | }) |
e5bde68a | 1043 | |
3b572406 | 1044 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1045 | |
388092d5 | 1046 | (define_insn "movxf_internal" |
78d8e0f9 ZW |
1047 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1048 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1049 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1050 | "@ |
1d5d7a21 RH |
1051 | mov %0 = %F1 |
1052 | ldfe %0 = %1%P1 | |
1053 | stfe %0 = %F1%P0" | |
388092d5 AB |
1054 | [(set_attr "itanium_class" "fmisc,fld,stf") |
1055 | (set_attr "speculable1" "yes") | |
1056 | (set_attr "speculable2" "no, yes,no")]) | |
f57fc998 | 1057 | |
4de67c26 JM |
1058 | ;; Same as for movxf, but for RFmode. |
1059 | (define_expand "movrf" | |
1060 | [(set (match_operand:RF 0 "general_operand" "") | |
1061 | (match_operand:RF 1 "general_operand" ""))] | |
1062 | "" | |
1063 | { | |
1064 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
1065 | DONE; | |
1066 | }) | |
1067 | ||
1068 | (define_insn "*movrf_internal" | |
1069 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
1070 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
1071 | "ia64_move_ok (operands[0], operands[1])" | |
1072 | "@ | |
1073 | mov %0 = %F1 | |
1074 | ldf.fill %0 = %1%P1 | |
1075 | stf.spill %0 = %F1%P0" | |
1076 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
1077 | ||
f57fc998 | 1078 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 1079 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1080 | (define_expand "movtf" |
2ffe0e02 ZW |
1081 | [(set (match_operand:TF 0 "general_operand" "") |
1082 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1083 | "" |
1084 | { | |
1085 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1086 | if (!op1) | |
1087 | DONE; | |
1088 | operands[1] = op1; | |
1089 | }) | |
1090 | ||
1091 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 1092 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 1093 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1094 | "ia64_move_ok (operands[0], operands[1])" |
1095 | "#" | |
1096 | "reload_completed" | |
1097 | [(const_int 0)] | |
1098 | { | |
1099 | ia64_split_tmode_move (operands); | |
1100 | DONE; | |
1101 | } | |
1102 | [(set_attr "itanium_class" "unknown") | |
1103 | (set_attr "predicable" "no")]) | |
1104 | ||
c65ebc55 JW |
1105 | \f |
1106 | ;; :::::::::::::::::::: | |
1107 | ;; :: | |
1108 | ;; :: Conversions | |
1109 | ;; :: | |
1110 | ;; :::::::::::::::::::: | |
1111 | ||
1112 | ;; Signed conversions from a smaller integer to a larger integer | |
1113 | ||
1114 | (define_insn "extendqidi2" | |
0551c32d RH |
1115 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1116 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1117 | "" |
1118 | "sxt1 %0 = %1" | |
52e12ad0 | 1119 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1120 | |
1121 | (define_insn "extendhidi2" | |
0551c32d RH |
1122 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1123 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1124 | "" |
1125 | "sxt2 %0 = %1" | |
52e12ad0 | 1126 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1127 | |
1128 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1129 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1130 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1131 | "" |
1132 | "@ | |
1133 | sxt4 %0 = %1 | |
aebf2462 | 1134 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1135 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1136 | |
1137 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1138 | ||
1139 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1140 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1141 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1142 | "" |
1143 | "@ | |
1144 | zxt1 %0 = %1 | |
1145 | ld1%O1 %0 = %1%P1" | |
388092d5 AB |
1146 | [(set_attr "itanium_class" "xtd,ld") |
1147 | (set_attr "speculable1" "yes") | |
1148 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1149 | |
1150 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1151 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1152 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1153 | "" |
1154 | "@ | |
1155 | zxt2 %0 = %1 | |
1156 | ld2%O1 %0 = %1%P1" | |
388092d5 AB |
1157 | [(set_attr "itanium_class" "xtd,ld") |
1158 | (set_attr "speculable1" "yes") | |
1159 | (set_attr "speculable2" "no, yes")]) | |
c65ebc55 JW |
1160 | |
1161 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1162 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1163 | (zero_extend:DI |
655f2eb9 | 1164 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1165 | "" |
1166 | "@ | |
d3f6e07b | 1167 | addp4 %0 = %1, r0 |
c65ebc55 | 1168 | ld4%O1 %0 = %1%P1 |
aebf2462 | 1169 | fmix.r %0 = f0, %1" |
388092d5 AB |
1170 | [(set_attr "itanium_class" "ialu,ld,fmisc") |
1171 | (set_attr "speculable1" "yes") | |
1172 | (set_attr "speculable2" "no, yes,no")]) | |
c65ebc55 JW |
1173 | |
1174 | ;; Convert between floating point types of different sizes. | |
1175 | ||
640cea5f JW |
1176 | ;; At first glance, it would appear that emitting fnorm for an extending |
1177 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1178 | ;; correctly only if the input is properly rounded for its type. In | |
1179 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1180 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1181 | ;; have to emit an fnorm. | |
1182 | ||
e8e20f18 RH |
1183 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1184 | ;; when we can. Should probably use a scheme like has been proposed | |
1185 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1186 | ;; would let combine merge the thing into adjacent insns. See also how the |
1187 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1188 | ;; se_register_operand. | |
c65ebc55 | 1189 | |
640cea5f JW |
1190 | (define_insn "extendsfdf2" |
1191 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
6adb807e | 1192 | (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1193 | "" |
6adb807e | 1194 | "fnorm.d %0 = %F1" |
640cea5f | 1195 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1196 | |
02befdf4 ZW |
1197 | (define_insn "extendsfxf2" |
1198 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1199 | (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1200 | "" |
6adb807e | 1201 | "fnorm %0 = %F1" |
640cea5f | 1202 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1203 | |
02befdf4 ZW |
1204 | (define_insn "extenddfxf2" |
1205 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1206 | (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1207 | "" |
6adb807e | 1208 | "fnorm %0 = %F1" |
640cea5f | 1209 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 1210 | |
c65ebc55 | 1211 | (define_insn "truncdfsf2" |
0551c32d | 1212 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1213 | (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1214 | "" |
6adb807e | 1215 | "fnorm.s %0 = %F1" |
52e12ad0 | 1216 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1217 | |
02befdf4 | 1218 | (define_insn "truncxfsf2" |
0551c32d | 1219 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1220 | (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1221 | "" |
6adb807e | 1222 | "fnorm.s %0 = %F1" |
52e12ad0 | 1223 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1224 | |
02befdf4 | 1225 | (define_insn "truncxfdf2" |
0551c32d | 1226 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1227 | (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1228 | "" |
6adb807e | 1229 | "fnorm.d %0 = %F1" |
52e12ad0 | 1230 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1231 | |
1232 | ;; Convert between signed integer types and floating point. | |
1233 | ||
02befdf4 ZW |
1234 | (define_insn "floatdixf2" |
1235 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1236 | (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1237 | "" |
6adb807e | 1238 | "fcvt.xf %0 = %F1" |
52e12ad0 | 1239 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1240 | |
1241 | (define_insn "fix_truncsfdi2" | |
0551c32d | 1242 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1243 | (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1244 | "" |
6adb807e | 1245 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1246 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1247 | |
1248 | (define_insn "fix_truncdfdi2" | |
0551c32d | 1249 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1250 | (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1251 | "" |
6adb807e | 1252 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1253 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1254 | |
02befdf4 | 1255 | (define_insn "fix_truncxfdi2" |
0551c32d | 1256 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1257 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1258 | "" |
6adb807e | 1259 | "fcvt.fx.trunc %0 = %F1" |
52e12ad0 | 1260 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1261 | |
02befdf4 | 1262 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1263 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1264 | (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) |
655f2eb9 | 1265 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1266 | "" |
6adb807e | 1267 | "fcvt.fx.trunc.s%2 %0 = %F1" |
52e12ad0 | 1268 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1269 | |
c65ebc55 JW |
1270 | ;; Convert between unsigned integer types and floating point. |
1271 | ||
1272 | (define_insn "floatunsdisf2" | |
0551c32d | 1273 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 1274 | (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1275 | "" |
6adb807e | 1276 | "fcvt.xuf.s %0 = %F1" |
52e12ad0 | 1277 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1278 | |
1279 | (define_insn "floatunsdidf2" | |
0551c32d | 1280 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 1281 | (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1282 | "" |
6adb807e | 1283 | "fcvt.xuf.d %0 = %F1" |
52e12ad0 | 1284 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1285 | |
02befdf4 ZW |
1286 | (define_insn "floatunsdixf2" |
1287 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
6adb807e | 1288 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1289 | "" |
6adb807e | 1290 | "fcvt.xuf %0 = %F1" |
52e12ad0 | 1291 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1292 | |
c65ebc55 | 1293 | (define_insn "fixuns_truncsfdi2" |
0551c32d | 1294 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1295 | (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1296 | "" |
6adb807e | 1297 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1298 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1299 | |
1300 | (define_insn "fixuns_truncdfdi2" | |
0551c32d | 1301 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1302 | (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 1303 | "" |
6adb807e | 1304 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1305 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1306 | |
02befdf4 | 1307 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1308 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1309 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
02befdf4 | 1310 | "" |
6adb807e | 1311 | "fcvt.fxu.trunc %0 = %F1" |
52e12ad0 | 1312 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1313 | |
02befdf4 | 1314 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1315 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
6adb807e | 1316 | (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) |
655f2eb9 | 1317 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1318 | "" |
6adb807e | 1319 | "fcvt.fxu.trunc.s%2 %0 = %F1" |
52e12ad0 | 1320 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1321 | \f |
1322 | ;; :::::::::::::::::::: | |
1323 | ;; :: | |
1324 | ;; :: Bit field extraction | |
1325 | ;; :: | |
1326 | ;; :::::::::::::::::::: | |
1327 | ||
c65ebc55 | 1328 | (define_insn "extv" |
0551c32d RH |
1329 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1330 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1331 | (match_operand:DI 2 "extr_len_operand" "n") |
1332 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1333 | "" |
1334 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1335 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1336 | |
1337 | (define_insn "extzv" | |
0551c32d RH |
1338 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1339 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5d48891e SE |
1340 | (match_operand:DI 2 "extr_len_operand" "n") |
1341 | (match_operand:DI 3 "shift_count_operand" "M")))] | |
c65ebc55 JW |
1342 | "" |
1343 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1344 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1345 | |
1346 | ;; Insert a bit field. | |
1347 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1348 | ;; Source1 can be 0 or -1. | |
1349 | ;; Source2 can be 0. | |
1350 | ||
1351 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1352 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1353 | ;; where source2 != dest. | |
1354 | ||
1355 | (define_expand "insv" | |
0551c32d | 1356 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1357 | (match_operand:DI 1 "const_int_operand" "") |
1358 | (match_operand:DI 2 "const_int_operand" "")) | |
1359 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1360 | "" | |
c65ebc55 JW |
1361 | { |
1362 | int width = INTVAL (operands[1]); | |
1363 | int shift = INTVAL (operands[2]); | |
1364 | ||
1365 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1366 | pseudo. */ | |
1367 | if (! register_operand (operands[3], DImode) | |
1368 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1369 | operands[3] = force_reg (DImode, operands[3]); | |
1370 | ||
1371 | /* If this is a single dep instruction, we have nothing to do. */ | |
1372 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1373 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1374 | { | |
1375 | /* Check for cases that can be implemented with a mix instruction. */ | |
1376 | if (width == 32 && shift == 0) | |
1377 | { | |
1378 | /* Directly generating the mix4left instruction confuses | |
1379 | optimize_bit_field in function.c. Since this is performing | |
1380 | a useful optimization, we defer generation of the complicated | |
1381 | mix4left RTL to the first splitting phase. */ | |
1382 | rtx tmp = gen_reg_rtx (DImode); | |
1383 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1384 | DONE; | |
1385 | } | |
1386 | else if (width == 32 && shift == 32) | |
1387 | { | |
1388 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1389 | DONE; | |
1390 | } | |
1391 | ||
d2ba6dcf JW |
1392 | /* We could handle remaining cases by emitting multiple dep |
1393 | instructions. | |
1394 | ||
1395 | If we need more than two dep instructions then we lose. A 6 | |
1396 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1397 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1398 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1399 | only one function unit that can execute dep and shr immed. | |
1400 | ||
1401 | If we only need two dep instruction, then we still lose. | |
1402 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1403 | the unnecessary mov, this is still undesirable because it will be | |
1404 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1405 | function unit. */ | |
1406 | ||
c65ebc55 JW |
1407 | FAIL; |
1408 | ||
1409 | #if 0 | |
1410 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1411 | for now. */ | |
1412 | while (width > 16) | |
1413 | { | |
1414 | rtx tmp; | |
1415 | ||
1416 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1417 | operands[3])); | |
1418 | shift += 16; | |
1419 | width -= 16; | |
1420 | tmp = gen_reg_rtx (DImode); | |
1421 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1422 | operands[3] = tmp; | |
1423 | } | |
1424 | operands[1] = GEN_INT (width); | |
1425 | operands[2] = GEN_INT (shift); | |
1426 | #endif | |
1427 | } | |
1d5d7a21 | 1428 | }) |
c65ebc55 JW |
1429 | |
1430 | (define_insn "*insv_internal" | |
0551c32d | 1431 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1432 | (match_operand:DI 1 "const_int_operand" "n") |
1433 | (match_operand:DI 2 "const_int_operand" "n")) | |
1434 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1435 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1436 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1437 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1438 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1439 | |
43a88a8c | 1440 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1441 | (define_insn "*shladdp4_internal" |
1442 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1443 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1444 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1445 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1446 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1447 | "shladdp4 %0 = %1, %2, r0" | |
1448 | [(set_attr "itanium_class" "ialu")]) | |
1449 | ||
041f25e6 | 1450 | (define_insn "*depz_internal" |
0551c32d RH |
1451 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1452 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
13f70342 | 1453 | (match_operand:DI 2 "const_int_operand" "M")) |
041f25e6 | 1454 | (match_operand:DI 3 "const_int_operand" "n")))] |
13f70342 | 1455 | "satisfies_constraint_M (operands[2]) |
041f25e6 | 1456 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" |
041f25e6 RH |
1457 | { |
1458 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1459 | return "%,dep.z %0 = %1, %2, %3"; |
1460 | } | |
52e12ad0 | 1461 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1462 | |
c65ebc55 | 1463 | (define_insn "shift_mix4left" |
0551c32d | 1464 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1465 | (const_int 32) (const_int 0)) |
0551c32d RH |
1466 | (match_operand:DI 1 "gr_register_operand" "r")) |
1467 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1468 | "" |
1469 | "#" | |
52e12ad0 | 1470 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1471 | |
c65ebc55 JW |
1472 | (define_split |
1473 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1474 | (const_int 32) (const_int 0)) | |
1475 | (match_operand:DI 1 "register_operand" "")) | |
1476 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1477 | "" |
c65ebc55 JW |
1478 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1479 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1480 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1481 | "operands[3] = operands[2];") | |
1482 | ||
1483 | (define_insn "*mix4left" | |
0551c32d | 1484 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1485 | (const_int 32) (const_int 0)) |
0551c32d | 1486 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1487 | (const_int 32)))] |
1488 | "" | |
1489 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1490 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1491 | |
1492 | (define_insn "mix4right" | |
0551c32d | 1493 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1494 | (const_int 32) (const_int 32)) |
0551c32d | 1495 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1496 | "" |
1497 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1498 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1499 | |
1500 | ;; This is used by the rotrsi3 pattern. | |
1501 | ||
1502 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1503 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1504 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1505 | (ashift:DI (zero_extend:DI | |
1506 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1507 | (const_int 32))))] |
1508 | "" | |
fa9a44e8 | 1509 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1510 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1511 | |
1512 | \f | |
1513 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1514 | ;; :: |
27a9b99d | 1515 | ;; :: 1-bit Integer arithmetic |
f2f90c63 RH |
1516 | ;; :: |
1517 | ;; :::::::::::::::::::: | |
1518 | ||
1519 | (define_insn_and_split "andbi3" | |
1520 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1521 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1522 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1523 | "" | |
1524 | "@ | |
1525 | # | |
1526 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1527 | and %0 = %2, %1" | |
1528 | "reload_completed | |
1529 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1530 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1531 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1532 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1533 | (match_dup 0))))] | |
1534 | "" | |
52e12ad0 | 1535 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1536 | |
1537 | (define_insn_and_split "*andcmbi3" | |
1538 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1539 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1540 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1541 | "" | |
1542 | "@ | |
1543 | # | |
967603ef | 1544 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1545 | andcm %0 = %2, %1" |
1546 | "reload_completed | |
1547 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1548 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1549 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1550 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1551 | (match_dup 0))))] | |
1552 | "" | |
52e12ad0 | 1553 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1554 | |
1555 | (define_insn_and_split "iorbi3" | |
1556 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1557 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1558 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1559 | "" | |
1560 | "@ | |
1561 | # | |
1562 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1563 | or %0 = %2, %1" | |
1564 | "reload_completed | |
1565 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1566 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1567 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1568 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1569 | (match_dup 0))))] | |
1570 | "" | |
52e12ad0 | 1571 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1572 | |
1573 | (define_insn_and_split "*iorcmbi3" | |
1574 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1575 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1576 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1577 | "" | |
1578 | "@ | |
1579 | # | |
967603ef | 1580 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1581 | "reload_completed |
1582 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1583 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1584 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1585 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1586 | (match_dup 0))))] | |
1587 | "" | |
52e12ad0 | 1588 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1589 | |
1590 | (define_insn "one_cmplbi2" | |
1591 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1592 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1593 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1594 | "" | |
1595 | "@ | |
1596 | tbit.z %0, %I0 = %1, 0 | |
1597 | xor %0 = 1, %1 | |
1598 | # | |
1599 | #" | |
52e12ad0 | 1600 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1601 | |
1602 | (define_split | |
1603 | [(set (match_operand:BI 0 "register_operand" "") | |
1604 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1605 | (clobber (match_scratch:BI 2 ""))] | |
1606 | "reload_completed | |
1607 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1608 | && rtx_equal_p (operands[0], operands[1])" |
1609 | [(set (match_dup 4) (match_dup 3)) | |
1610 | (set (match_dup 0) (const_int 1)) | |
1611 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1612 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1613 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1614 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1615 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1616 | ||
1617 | (define_split | |
1618 | [(set (match_operand:BI 0 "register_operand" "") | |
1619 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1620 | (clobber (match_scratch:BI 2 ""))] | |
1621 | "reload_completed | |
1622 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1623 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1624 | && ! rtx_equal_p (operands[0], operands[1])" | |
1625 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1626 | (set (match_dup 0) (const_int 0))) | |
1627 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1628 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1629 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1630 | "") |
1631 | ||
1632 | (define_insn "*cmpsi_and_0" | |
1633 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1634 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1635 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1636 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1637 | (match_operand:BI 1 "register_operand" "0")))] | |
1638 | "" | |
1639 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1640 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1641 | |
1642 | (define_insn "*cmpsi_and_1" | |
1643 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1644 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1645 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1646 | (const_int 0)]) | |
1647 | (match_operand:BI 1 "register_operand" "0")))] | |
1648 | "" | |
1649 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1650 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1651 | |
1652 | (define_insn "*cmpsi_andnot_0" | |
1653 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1654 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1655 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1656 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1657 | (match_operand:BI 1 "register_operand" "0")))] | |
1658 | "" | |
1659 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1660 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1661 | |
1662 | (define_insn "*cmpsi_andnot_1" | |
1663 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1664 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1665 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1666 | (const_int 0)])) | |
1667 | (match_operand:BI 1 "register_operand" "0")))] | |
1668 | "" | |
1669 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1670 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1671 | |
1672 | (define_insn "*cmpdi_and_0" | |
1673 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1674 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1675 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1676 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1677 | (match_operand:BI 1 "register_operand" "0")))] | |
1678 | "" | |
1679 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1680 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1681 | |
1682 | (define_insn "*cmpdi_and_1" | |
1683 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1684 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1685 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1686 | (const_int 0)]) | |
1687 | (match_operand:BI 1 "register_operand" "0")))] | |
1688 | "" | |
1689 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1690 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1691 | |
1692 | (define_insn "*cmpdi_andnot_0" | |
1693 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1694 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1695 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1696 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1697 | (match_operand:BI 1 "register_operand" "0")))] | |
1698 | "" | |
1699 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1700 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1701 | |
1702 | (define_insn "*cmpdi_andnot_1" | |
1703 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1704 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1705 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1706 | (const_int 0)])) | |
1707 | (match_operand:BI 1 "register_operand" "0")))] | |
1708 | "" | |
1709 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1710 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1711 | |
1712 | (define_insn "*tbit_and_0" | |
1713 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1714 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1715 | (const_int 1)) | |
1716 | (const_int 0)) | |
c77e04ae | 1717 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1718 | "" |
1719 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1720 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1721 | |
1722 | (define_insn "*tbit_and_1" | |
1723 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1724 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1725 | (const_int 1)) | |
1726 | (const_int 0)) | |
c77e04ae | 1727 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1728 | "" |
1729 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1730 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1731 | |
1732 | (define_insn "*tbit_and_2" | |
1733 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1734 | (and:BI (ne:BI (zero_extract:DI | |
1735 | (match_operand:DI 1 "gr_register_operand" "r") | |
1736 | (const_int 1) | |
5d48891e | 1737 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1738 | (const_int 0)) |
1739 | (match_operand:BI 3 "register_operand" "0")))] | |
1740 | "" | |
1741 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1742 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1743 | |
1744 | (define_insn "*tbit_and_3" | |
1745 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1746 | (and:BI (eq:BI (zero_extract:DI | |
1747 | (match_operand:DI 1 "gr_register_operand" "r") | |
1748 | (const_int 1) | |
5d48891e | 1749 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1750 | (const_int 0)) |
1751 | (match_operand:BI 3 "register_operand" "0")))] | |
1752 | "" | |
1753 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1754 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1755 | |
1756 | (define_insn "*cmpsi_or_0" | |
1757 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1758 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1759 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1760 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1761 | (match_operand:BI 1 "register_operand" "0")))] | |
1762 | "" | |
1763 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1764 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1765 | |
1766 | (define_insn "*cmpsi_or_1" | |
1767 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1768 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1769 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1770 | (const_int 0)]) | |
1771 | (match_operand:BI 1 "register_operand" "0")))] | |
1772 | "" | |
1773 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1774 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1775 | |
1776 | (define_insn "*cmpsi_orcm_0" | |
1777 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1778 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1779 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1780 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1781 | (match_operand:BI 1 "register_operand" "0")))] | |
1782 | "" | |
1783 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1784 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1785 | |
1786 | (define_insn "*cmpsi_orcm_1" | |
1787 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1788 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1789 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1790 | (const_int 0)])) | |
1791 | (match_operand:BI 1 "register_operand" "0")))] | |
1792 | "" | |
1793 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1794 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1795 | |
1796 | (define_insn "*cmpdi_or_0" | |
1797 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1798 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1799 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1800 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1801 | (match_operand:BI 1 "register_operand" "0")))] | |
1802 | "" | |
1803 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1804 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1805 | |
1806 | (define_insn "*cmpdi_or_1" | |
1807 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1808 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1809 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1810 | (const_int 0)]) | |
1811 | (match_operand:BI 1 "register_operand" "0")))] | |
1812 | "" | |
1813 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1814 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1815 | |
1816 | (define_insn "*cmpdi_orcm_0" | |
1817 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1818 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1819 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1820 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1821 | (match_operand:BI 1 "register_operand" "0")))] | |
1822 | "" | |
1823 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1824 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1825 | |
1826 | (define_insn "*cmpdi_orcm_1" | |
1827 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1828 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1829 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1830 | (const_int 0)])) | |
1831 | (match_operand:BI 1 "register_operand" "0")))] | |
1832 | "" | |
1833 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1834 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1835 | |
1836 | (define_insn "*tbit_or_0" | |
1837 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1838 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1839 | (const_int 1)) | |
1840 | (const_int 0)) | |
c77e04ae | 1841 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1842 | "" |
1843 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1844 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1845 | |
1846 | (define_insn "*tbit_or_1" | |
1847 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1848 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1849 | (const_int 1)) | |
1850 | (const_int 0)) | |
c77e04ae | 1851 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1852 | "" |
1853 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1854 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1855 | |
1856 | (define_insn "*tbit_or_2" | |
1857 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1858 | (ior:BI (ne:BI (zero_extract:DI | |
1859 | (match_operand:DI 1 "gr_register_operand" "r") | |
1860 | (const_int 1) | |
5d48891e | 1861 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1862 | (const_int 0)) |
1863 | (match_operand:BI 3 "register_operand" "0")))] | |
1864 | "" | |
1865 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1866 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1867 | |
1868 | (define_insn "*tbit_or_3" | |
1869 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1870 | (ior:BI (eq:BI (zero_extract:DI | |
1871 | (match_operand:DI 1 "gr_register_operand" "r") | |
1872 | (const_int 1) | |
5d48891e | 1873 | (match_operand:DI 2 "shift_count_operand" "M")) |
f2f90c63 RH |
1874 | (const_int 0)) |
1875 | (match_operand:BI 3 "register_operand" "0")))] | |
1876 | "" | |
1877 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1878 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1879 | |
1880 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1881 | ||
1882 | (define_split | |
1883 | [(set (match_operand:BI 0 "register_operand" "") | |
1884 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1885 | (const_int 0)) | |
1886 | (match_operand:DI 3 "register_operand" "")) | |
1887 | (const_int 0)))] | |
1888 | "" | |
1889 | [(set (match_dup 0) | |
1890 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1891 | (match_dup 2)))] | |
1892 | "") | |
1893 | ||
1894 | (define_split | |
1895 | [(set (match_operand:BI 0 "register_operand" "") | |
1896 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1897 | (const_int 0)) | |
1898 | (match_operand:DI 3 "register_operand" "")) | |
1899 | (const_int 0)))] | |
1900 | "" | |
1901 | [(set (match_dup 0) | |
1902 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1903 | (match_dup 2))) | |
1904 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1905 | (clobber (scratch))])] | |
1906 | "") | |
1907 | ||
1908 | (define_split | |
1909 | [(set (match_operand:BI 0 "register_operand" "") | |
1910 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1911 | (const_int 0)) | |
1912 | (match_operand:DI 3 "register_operand" "")) | |
1913 | (const_int 0)))] | |
1914 | "" | |
1915 | [(set (match_dup 0) | |
1916 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1917 | (match_dup 2)))] | |
1918 | "") | |
1919 | ||
1920 | (define_split | |
1921 | [(set (match_operand:BI 0 "register_operand" "") | |
1922 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1923 | (const_int 0)) | |
1924 | (match_operand:DI 3 "register_operand" "")) | |
1925 | (const_int 0)))] | |
1926 | "" | |
1927 | [(set (match_dup 0) | |
1928 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1929 | (match_dup 2))) | |
1930 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1931 | (clobber (scratch))])] | |
1932 | "") | |
1933 | ||
1934 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1935 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1936 | ;; nothing bad happens to the comparisons in the meantime. | |
1937 | ;; | |
1938 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1939 | ;; that we're doing height reduction. | |
1940 | ; | |
1941 | ;(define_insn_and_split "" | |
1942 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1943 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1944 | ; [(match_operand 2 "" "") | |
1945 | ; (match_operand 3 "" "")]) | |
1946 | ; (match_operator:BI 4 "comparison_operator" | |
1947 | ; [(match_operand 5 "" "") | |
1948 | ; (match_operand 6 "" "")])) | |
1949 | ; (match_dup 0)))] | |
1950 | ; "flag_schedule_insns" | |
1951 | ; "#" | |
1952 | ; "" | |
1953 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1954 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1955 | ; "") | |
1956 | ; | |
1957 | ;(define_insn_and_split "" | |
1958 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1959 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1960 | ; [(match_operand 2 "" "") | |
1961 | ; (match_operand 3 "" "")]) | |
1962 | ; (match_operator:BI 4 "comparison_operator" | |
1963 | ; [(match_operand 5 "" "") | |
1964 | ; (match_operand 6 "" "")])) | |
1965 | ; (match_dup 0)))] | |
1966 | ; "flag_schedule_insns" | |
1967 | ; "#" | |
1968 | ; "" | |
1969 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1970 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1971 | ; "") | |
1972 | ; | |
1973 | ;(define_split | |
1974 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1975 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1976 | ; [(match_operand 2 "" "") | |
1977 | ; (match_operand 3 "" "")]) | |
1978 | ; (match_operand:BI 7 "register_operand" "")) | |
1979 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1980 | ; [(match_operand 5 "" "") | |
1981 | ; (match_operand 6 "" "")]) | |
1982 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1983 | ; "" | |
1984 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1985 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1986 | ; (match_dup 0)))] | |
1987 | ; "") | |
1988 | ; | |
1989 | ;(define_split | |
1990 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1991 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1992 | ; [(match_operand 2 "" "") | |
1993 | ; (match_operand 3 "" "")]) | |
1994 | ; (match_operand:BI 7 "register_operand" "")) | |
1995 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1996 | ; [(match_operand 5 "" "") | |
1997 | ; (match_operand 6 "" "")]) | |
1998 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1999 | ; "" | |
2000 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2001 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2002 | ; (match_dup 0)))] | |
2003 | ; "") | |
2004 | ||
2005 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2006 | ;; Note that we'll have already split the predicate copy, which | |
2007 | ;; is kind of a pain, but oh well. | |
2008 | ||
2009 | (define_peephole2 | |
2010 | [(set (match_operand:BI 0 "register_operand" "") | |
2011 | (match_operand:BI 1 "comparison_operator" "")) | |
2012 | (set (match_operand:CCI 2 "register_operand" "") | |
2013 | (match_operand:CCI 3 "register_operand" "")) | |
2014 | (set (match_operand:CCI 4 "register_operand" "") | |
2015 | (match_operand:CCI 5 "register_operand" "")) | |
2016 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2017 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2018 | "REGNO (operands[3]) == REGNO (operands[0]) |
2019 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2020 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2021 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2022 | [(set (match_dup 0) (match_dup 1)) | |
2023 | (set (match_dup 6) (match_dup 7))] | |
2024 | "operands[7] = copy_rtx (operands[1]);") | |
2025 | \f | |
2026 | ;; :::::::::::::::::::: | |
2027 | ;; :: | |
27a9b99d | 2028 | ;; :: 16-bit Integer arithmetic |
cf1f6ae3 RH |
2029 | ;; :: |
2030 | ;; :::::::::::::::::::: | |
2031 | ||
2032 | (define_insn "mulhi3" | |
2033 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2034 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2035 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2036 | "" | |
2a7ffc85 | 2037 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2038 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2039 | |
2040 | \f | |
2041 | ;; :::::::::::::::::::: | |
c65ebc55 | 2042 | ;; :: |
27a9b99d | 2043 | ;; :: 32-bit Integer arithmetic |
c65ebc55 JW |
2044 | ;; :: |
2045 | ;; :::::::::::::::::::: | |
2046 | ||
058557c4 | 2047 | (define_insn "addsi3" |
0551c32d RH |
2048 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2049 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2050 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2051 | "" |
2052 | "@ | |
1d5d7a21 RH |
2053 | add %0 = %1, %2 |
2054 | adds %0 = %2, %1 | |
2055 | addl %0 = %2, %1" | |
52e12ad0 | 2056 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2057 | |
2058 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2059 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2060 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2061 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2062 | (const_int 1)))] |
2063 | "" | |
2064 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2065 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2066 | |
5527bf14 | 2067 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2068 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2069 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2070 | (const_int 2)) |
2071 | (const_int 1)))] | |
2072 | "" | |
2073 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2074 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2075 | |
058557c4 | 2076 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2077 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2078 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2079 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2080 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2081 | "" |
058557c4 | 2082 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2083 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2084 | |
058557c4 | 2085 | (define_insn "subsi3" |
0551c32d RH |
2086 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2087 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2088 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2089 | "" |
2090 | "sub %0 = %1, %2" | |
52e12ad0 | 2091 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2092 | |
2093 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2094 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2095 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2096 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2097 | "" |
2098 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2099 | [(set_attr "itanium_class" "ialu")]) |
2100 | ||
2101 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2102 | |
058557c4 | 2103 | (define_insn "mulsi3" |
0551c32d | 2104 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2105 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2106 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2107 | "" |
aebf2462 | 2108 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2109 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2110 | |
655f2eb9 | 2111 | (define_insn "maddsi4" |
11a13704 RH |
2112 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2113 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2114 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2115 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2116 | "" | |
aebf2462 | 2117 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2118 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2119 | |
058557c4 | 2120 | (define_insn "negsi2" |
0551c32d RH |
2121 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2122 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2123 | "" |
2124 | "sub %0 = r0, %1" | |
52e12ad0 | 2125 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2126 | |
2127 | (define_expand "abssi2" | |
2128 | [(set (match_dup 2) | |
f2f90c63 | 2129 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2130 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2131 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2132 | (neg:SI (match_dup 1)) |
2133 | (match_dup 1)))] | |
c65ebc55 | 2134 | "" |
1d5d7a21 | 2135 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2136 | |
2137 | (define_expand "sminsi3" | |
2138 | [(set (match_dup 3) | |
f2f90c63 | 2139 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2140 | (match_operand:SI 2 "gr_register_operand" ""))) |
2141 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2142 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2143 | (match_dup 2) (match_dup 1)))] |
2144 | "" | |
1d5d7a21 | 2145 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2146 | |
2147 | (define_expand "smaxsi3" | |
2148 | [(set (match_dup 3) | |
f2f90c63 | 2149 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2150 | (match_operand:SI 2 "gr_register_operand" ""))) |
2151 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2152 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2153 | (match_dup 1) (match_dup 2)))] |
2154 | "" | |
1d5d7a21 | 2155 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2156 | |
2157 | (define_expand "uminsi3" | |
2158 | [(set (match_dup 3) | |
f2f90c63 | 2159 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2160 | (match_operand:SI 2 "gr_register_operand" ""))) |
2161 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2162 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2163 | (match_dup 2) (match_dup 1)))] |
2164 | "" | |
1d5d7a21 | 2165 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2166 | |
2167 | (define_expand "umaxsi3" | |
2168 | [(set (match_dup 3) | |
f2f90c63 | 2169 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2170 | (match_operand:SI 2 "gr_register_operand" ""))) |
2171 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2172 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2173 | (match_dup 1) (match_dup 2)))] |
2174 | "" | |
1d5d7a21 | 2175 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2176 | |
655f2eb9 RH |
2177 | (define_expand "divsi3" |
2178 | [(set (match_operand:SI 0 "register_operand" "") | |
2179 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2180 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2181 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2182 | { |
9aec7fb4 | 2183 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2184 | |
02befdf4 | 2185 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2186 | op0_di = gen_reg_rtx (DImode); |
2187 | ||
2188 | if (CONSTANT_P (operands[1])) | |
2189 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2190 | op1_xf = gen_reg_rtx (XFmode); |
2191 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2192 | |
2193 | if (CONSTANT_P (operands[2])) | |
2194 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2195 | op2_xf = gen_reg_rtx (XFmode); |
2196 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2197 | |
2198 | /* 2^-34 */ | |
9aec7fb4 SE |
2199 | twon34_exp = gen_reg_rtx (DImode); |
2200 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2201 | twon34 = gen_reg_rtx (XFmode); | |
2202 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2203 | |
85199961 L |
2204 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2205 | CONST1_RTX (SImode))); | |
2206 | ||
02befdf4 | 2207 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2208 | |
02befdf4 | 2209 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2210 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2211 | DONE; | |
1d5d7a21 | 2212 | }) |
655f2eb9 RH |
2213 | |
2214 | (define_expand "modsi3" | |
2215 | [(set (match_operand:SI 0 "register_operand" "") | |
2216 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2217 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2218 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2219 | { |
2220 | rtx op2_neg, op1_di, div; | |
2221 | ||
2222 | div = gen_reg_rtx (SImode); | |
2223 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2224 | ||
2225 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2226 | ||
2227 | /* This is a trick to get us to reuse the value that we're sure to | |
2228 | have already copied to the FP regs. */ | |
2229 | op1_di = gen_reg_rtx (DImode); | |
2230 | convert_move (op1_di, operands[1], 0); | |
2231 | ||
2232 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2233 | gen_lowpart (SImode, op1_di))); | |
2234 | DONE; | |
1d5d7a21 | 2235 | }) |
655f2eb9 RH |
2236 | |
2237 | (define_expand "udivsi3" | |
2238 | [(set (match_operand:SI 0 "register_operand" "") | |
2239 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2240 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2241 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2242 | { |
9aec7fb4 | 2243 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2244 | |
02befdf4 | 2245 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2246 | op0_di = gen_reg_rtx (DImode); |
2247 | ||
2248 | if (CONSTANT_P (operands[1])) | |
2249 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2250 | op1_xf = gen_reg_rtx (XFmode); |
2251 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2252 | |
2253 | if (CONSTANT_P (operands[2])) | |
2254 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2255 | op2_xf = gen_reg_rtx (XFmode); |
2256 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2257 | |
2258 | /* 2^-34 */ | |
9aec7fb4 SE |
2259 | twon34_exp = gen_reg_rtx (DImode); |
2260 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2261 | twon34 = gen_reg_rtx (XFmode); | |
2262 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2263 | |
85199961 L |
2264 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (SImode), |
2265 | CONST1_RTX (SImode))); | |
2266 | ||
02befdf4 | 2267 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2268 | |
02befdf4 | 2269 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2270 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2271 | DONE; | |
1d5d7a21 | 2272 | }) |
655f2eb9 RH |
2273 | |
2274 | (define_expand "umodsi3" | |
2275 | [(set (match_operand:SI 0 "register_operand" "") | |
2276 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2277 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2278 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2279 | { |
2280 | rtx op2_neg, op1_di, div; | |
2281 | ||
2282 | div = gen_reg_rtx (SImode); | |
2283 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2284 | ||
2285 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2286 | ||
2287 | /* This is a trick to get us to reuse the value that we're sure to | |
2288 | have already copied to the FP regs. */ | |
2289 | op1_di = gen_reg_rtx (DImode); | |
2290 | convert_move (op1_di, operands[1], 1); | |
2291 | ||
2292 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2293 | gen_lowpart (SImode, op1_di))); | |
2294 | DONE; | |
1d5d7a21 | 2295 | }) |
655f2eb9 RH |
2296 | |
2297 | (define_insn_and_split "divsi3_internal" | |
02befdf4 | 2298 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2299 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2300 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2301 | (clobber (match_scratch:XF 4 "=&f")) |
2302 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2303 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2304 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2305 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2306 | "#" |
2307 | "&& reload_completed" | |
07acc7b3 JW |
2308 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2309 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2310 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2311 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2312 | (use (const_int 1))]) |
2313 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2314 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2315 | (use (const_int 1))])) |
2316 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2317 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2318 | (minus:XF (match_dup 7) |
2319 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2320 | (use (const_int 1))])) |
2321 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2322 | (parallel [(set (match_dup 4) | |
02befdf4 | 2323 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2324 | (match_dup 4))) |
2325 | (use (const_int 1))])) | |
2326 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2327 | (parallel [(set (match_dup 5) | |
02befdf4 | 2328 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2329 | (match_dup 3))) |
2330 | (use (const_int 1))])) | |
2331 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2332 | (parallel [(set (match_dup 0) | |
02befdf4 | 2333 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2334 | (match_dup 4))) |
2335 | (use (const_int 1))])) | |
2336 | ] | |
02befdf4 | 2337 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2338 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2339 | \f |
2340 | ;; :::::::::::::::::::: | |
2341 | ;; :: | |
27a9b99d | 2342 | ;; :: 64-bit Integer arithmetic |
c65ebc55 JW |
2343 | ;; :: |
2344 | ;; :::::::::::::::::::: | |
2345 | ||
2346 | (define_insn "adddi3" | |
0551c32d RH |
2347 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2348 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2349 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2350 | "" |
2351 | "@ | |
1d5d7a21 RH |
2352 | add %0 = %1, %2 |
2353 | adds %0 = %2, %1 | |
2354 | addl %0 = %2, %1" | |
52e12ad0 | 2355 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2356 | |
2357 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2358 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2359 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2360 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2361 | (const_int 1)))] |
2362 | "" | |
2363 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2364 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2365 | |
5527bf14 RH |
2366 | ;; This has some of the same problems as shladd. We let the shladd |
2367 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2368 | ;; a register, but not more ugliness here. | |
2369 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2370 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2371 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2372 | (const_int 2)) |
2373 | (const_int 1)))] | |
2374 | "" | |
2375 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2376 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2377 | |
c65ebc55 | 2378 | (define_insn "subdi3" |
0551c32d RH |
2379 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2380 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2381 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2382 | "" |
2383 | "sub %0 = %1, %2" | |
52e12ad0 | 2384 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2385 | |
2386 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2387 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2388 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2389 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2390 | "" |
2391 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2392 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2393 | |
cee58bc0 RH |
2394 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2395 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2396 | (define_insn "muldi3" |
0551c32d | 2397 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2398 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2399 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2400 | "" |
aebf2462 | 2401 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2402 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2403 | |
2404 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2405 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2406 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2407 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2408 | ;; here so that it will be present just in case register elimination gives us | |
2409 | ;; the funny result. | |
2410 | ||
2411 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2412 | ||
2413 | ;; ??? Maybe we should change how adds are canonicalized. | |
2414 | ||
655f2eb9 | 2415 | (define_insn "madddi4" |
0551c32d | 2416 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2417 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2418 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2419 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2420 | (clobber (match_scratch:DI 4 "=X"))] |
2421 | "" | |
aebf2462 | 2422 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2423 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2424 | |
2425 | ;; This can be created by register elimination if operand3 of shladd is an | |
2426 | ;; eliminable register or has reg_equiv_constant set. | |
2427 | ||
2428 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2429 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2430 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2431 | ;; incorrectly. |
2432 | ||
655f2eb9 | 2433 | (define_insn "*madddi4_elim" |
c65ebc55 | 2434 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2435 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2436 | (match_operand:DI 2 "register_operand" "f")) | |
2437 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2438 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2439 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2440 | "reload_in_progress" |
2441 | "#" | |
52e12ad0 | 2442 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2443 | |
c65ebc55 JW |
2444 | (define_split |
2445 | [(set (match_operand:DI 0 "register_operand" "") | |
2446 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2447 | (match_operand:DI 2 "register_operand" "")) | |
2448 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2449 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2450 | (clobber (match_scratch:DI 5 ""))] |
2451 | "reload_completed" | |
2452 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2453 | (match_dup 3))) | |
2454 | (clobber (match_dup 0))]) | |
c65ebc55 | 2455 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2456 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2457 | "") | |
2458 | ||
c65ebc55 | 2459 | (define_insn "smuldi3_highpart" |
0551c32d | 2460 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2461 | (truncate:DI |
2462 | (lshiftrt:TI | |
0551c32d | 2463 | (mult:TI (sign_extend:TI |
6adb807e | 2464 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2465 | (sign_extend:TI |
6adb807e | 2466 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2467 | (const_int 64))))] |
2468 | "" | |
6adb807e | 2469 | "xmpy.h %0 = %F1, %F2" |
52e12ad0 | 2470 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2471 | |
2472 | (define_insn "umuldi3_highpart" | |
0551c32d | 2473 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2474 | (truncate:DI |
2475 | (lshiftrt:TI | |
0551c32d | 2476 | (mult:TI (zero_extend:TI |
6adb807e | 2477 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
0551c32d | 2478 | (zero_extend:TI |
6adb807e | 2479 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))) |
c65ebc55 JW |
2480 | (const_int 64))))] |
2481 | "" | |
6adb807e | 2482 | "xmpy.hu %0 = %F1, %F2" |
52e12ad0 | 2483 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2484 | |
2485 | (define_insn "negdi2" | |
0551c32d RH |
2486 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2487 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2488 | "" |
2489 | "sub %0 = r0, %1" | |
52e12ad0 | 2490 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2491 | |
2492 | (define_expand "absdi2" | |
2493 | [(set (match_dup 2) | |
f2f90c63 | 2494 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2495 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2496 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2497 | (neg:DI (match_dup 1)) |
2498 | (match_dup 1)))] | |
c65ebc55 | 2499 | "" |
1d5d7a21 | 2500 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2501 | |
2502 | (define_expand "smindi3" | |
2503 | [(set (match_dup 3) | |
f2f90c63 | 2504 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2505 | (match_operand:DI 2 "gr_register_operand" ""))) |
2506 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2507 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2508 | (match_dup 2) (match_dup 1)))] |
2509 | "" | |
1d5d7a21 | 2510 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2511 | |
2512 | (define_expand "smaxdi3" | |
2513 | [(set (match_dup 3) | |
f2f90c63 | 2514 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2515 | (match_operand:DI 2 "gr_register_operand" ""))) |
2516 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2517 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2518 | (match_dup 1) (match_dup 2)))] |
2519 | "" | |
1d5d7a21 | 2520 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2521 | |
2522 | (define_expand "umindi3" | |
2523 | [(set (match_dup 3) | |
f2f90c63 | 2524 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2525 | (match_operand:DI 2 "gr_register_operand" ""))) |
2526 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2527 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2528 | (match_dup 2) (match_dup 1)))] |
2529 | "" | |
1d5d7a21 | 2530 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2531 | |
2532 | (define_expand "umaxdi3" | |
2533 | [(set (match_dup 3) | |
f2f90c63 | 2534 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2535 | (match_operand:DI 2 "gr_register_operand" ""))) |
2536 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2537 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2538 | (match_dup 1) (match_dup 2)))] |
2539 | "" | |
1d5d7a21 | 2540 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2541 | |
2542 | (define_expand "ffsdi2" | |
2543 | [(set (match_dup 6) | |
f2f90c63 | 2544 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2545 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2546 | (set (match_dup 5) (const_int 0)) | |
2547 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2548 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2549 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2550 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2551 | (match_dup 5) (match_dup 4)))] |
2552 | "" | |
c65ebc55 JW |
2553 | { |
2554 | operands[2] = gen_reg_rtx (DImode); | |
2555 | operands[3] = gen_reg_rtx (DImode); | |
2556 | operands[4] = gen_reg_rtx (DImode); | |
2557 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2558 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2559 | }) |
c65ebc55 | 2560 | |
c407570a RH |
2561 | (define_expand "ctzdi2" |
2562 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2563 | (const_int -1))) | |
2564 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2565 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2566 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2567 | (popcount:DI (match_dup 4)))] | |
2568 | "" | |
2569 | { | |
2570 | operands[2] = gen_reg_rtx (DImode); | |
2571 | operands[3] = gen_reg_rtx (DImode); | |
2572 | operands[4] = gen_reg_rtx (DImode); | |
2573 | }) | |
2574 | ||
c407570a RH |
2575 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2576 | (define_expand "clzdi2" | |
2577 | [(set (match_dup 2) | |
6adb807e | 2578 | (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))) |
c407570a RH |
2579 | (set (match_dup 3) |
2580 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2581 | (set (match_dup 4) (const_int 65598)) | |
2582 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2583 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2584 | "" |
c407570a | 2585 | { |
02befdf4 | 2586 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2587 | operands[3] = gen_reg_rtx (DImode); |
2588 | operands[4] = gen_reg_rtx (DImode); | |
2589 | }) | |
2590 | ||
2591 | (define_insn "popcountdi2" | |
0551c32d | 2592 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2593 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2594 | "" |
2595 | "popcnt %0 = %1" | |
52e12ad0 | 2596 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2597 | |
ff848f0e RS |
2598 | (define_insn "bswapdi2" |
2599 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
2600 | (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
2601 | "" | |
2602 | "mux1 %0 = %1, @rev" | |
2603 | [(set_attr "itanium_class" "mmshf")]) | |
2604 | ||
02befdf4 | 2605 | (define_insn "*getf_exp_xf" |
c407570a | 2606 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6adb807e | 2607 | (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")] |
c407570a | 2608 | UNSPEC_GETF_EXP))] |
02befdf4 | 2609 | "" |
6adb807e | 2610 | "getf.exp %0 = %F1" |
c407570a RH |
2611 | [(set_attr "itanium_class" "frfr")]) |
2612 | ||
655f2eb9 RH |
2613 | (define_expand "divdi3" |
2614 | [(set (match_operand:DI 0 "register_operand" "") | |
2615 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2616 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2617 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2618 | { |
02befdf4 | 2619 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2620 | |
02befdf4 | 2621 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2622 | |
2623 | if (CONSTANT_P (operands[1])) | |
2624 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2625 | op1_xf = gen_reg_rtx (XFmode); |
2626 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2627 | |
2628 | if (CONSTANT_P (operands[2])) | |
2629 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2630 | op2_xf = gen_reg_rtx (XFmode); |
2631 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2632 | |
85199961 L |
2633 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2634 | CONST1_RTX (DImode))); | |
2635 | ||
dbdd120f | 2636 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2637 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2638 | else |
02befdf4 | 2639 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2640 | |
02befdf4 | 2641 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2642 | DONE; |
1d5d7a21 | 2643 | }) |
655f2eb9 RH |
2644 | |
2645 | (define_expand "moddi3" | |
2646 | [(set (match_operand:DI 0 "register_operand" "") | |
2647 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2648 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2649 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2650 | { |
2651 | rtx op2_neg, div; | |
2652 | ||
2653 | div = gen_reg_rtx (DImode); | |
2654 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2655 | ||
2656 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2657 | ||
2658 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2659 | DONE; | |
1d5d7a21 | 2660 | }) |
655f2eb9 RH |
2661 | |
2662 | (define_expand "udivdi3" | |
2663 | [(set (match_operand:DI 0 "register_operand" "") | |
2664 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2665 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2666 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2667 | { |
02befdf4 | 2668 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2669 | |
02befdf4 | 2670 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2671 | |
2672 | if (CONSTANT_P (operands[1])) | |
2673 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2674 | op1_xf = gen_reg_rtx (XFmode); |
2675 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2676 | |
2677 | if (CONSTANT_P (operands[2])) | |
2678 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2679 | op2_xf = gen_reg_rtx (XFmode); |
2680 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2681 | |
85199961 L |
2682 | emit_insn (gen_cond_trap (EQ, operands[2], CONST0_RTX (DImode), |
2683 | CONST1_RTX (DImode))); | |
2684 | ||
dbdd120f | 2685 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2686 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2687 | else |
02befdf4 | 2688 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2689 | |
02befdf4 | 2690 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2691 | DONE; |
1d5d7a21 | 2692 | }) |
655f2eb9 RH |
2693 | |
2694 | (define_expand "umoddi3" | |
2695 | [(set (match_operand:DI 0 "register_operand" "") | |
2696 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2697 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2698 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2699 | { |
2700 | rtx op2_neg, div; | |
2701 | ||
2702 | div = gen_reg_rtx (DImode); | |
2703 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2704 | ||
2705 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2706 | ||
2707 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2708 | DONE; | |
1d5d7a21 | 2709 | }) |
655f2eb9 RH |
2710 | |
2711 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 | 2712 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2713 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2714 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2715 | (clobber (match_scratch:XF 3 "=&f")) |
2716 | (clobber (match_scratch:XF 4 "=&f")) | |
2717 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2718 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2719 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2720 | "#" |
2721 | "&& reload_completed" | |
07acc7b3 JW |
2722 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2723 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2724 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2725 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2726 | (use (const_int 1))]) |
2727 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2728 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2729 | (minus:XF (match_dup 7) |
2730 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2731 | (use (const_int 1))])) |
2732 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2733 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2734 | (use (const_int 1))])) |
2735 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2736 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2737 | (use (const_int 1))])) |
2738 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2739 | (parallel [(set (match_dup 4) | |
02befdf4 | 2740 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2741 | (match_dup 4))) |
2742 | (use (const_int 1))])) | |
2743 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2744 | (parallel [(set (match_dup 0) | |
02befdf4 | 2745 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2746 | (match_dup 0))) |
2747 | (use (const_int 1))])) | |
2748 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2749 | (parallel [(set (match_dup 3) | |
02befdf4 | 2750 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2751 | (match_dup 4))) |
2752 | (use (const_int 1))])) | |
2753 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2754 | (parallel [(set (match_dup 0) | |
02befdf4 | 2755 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2756 | (match_dup 0))) |
2757 | (use (const_int 1))])) | |
2758 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2759 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2760 | (minus:XF (match_dup 1) |
2761 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2762 | (use (const_int 1))])) |
2763 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2764 | (parallel [(set (match_dup 0) | |
02befdf4 | 2765 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2766 | (match_dup 3))) |
2767 | (use (const_int 1))])) | |
2768 | ] | |
02befdf4 | 2769 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2770 | [(set_attr "predicable" "no")]) |
2771 | ||
2772 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 | 2773 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
6adb807e SE |
2774 | (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") |
2775 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")))) | |
02befdf4 ZW |
2776 | (clobber (match_scratch:XF 3 "=&f")) |
2777 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2778 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2779 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2780 | "#" |
2781 | "&& reload_completed" | |
07acc7b3 JW |
2782 | [(parallel [(set (match_dup 0) (unspec:XF [(const_int 1) (match_dup 2)] |
2783 | UNSPEC_FR_RECIP_APPROX_RES)) | |
086c0f96 RH |
2784 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2785 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2786 | (use (const_int 1))]) |
2787 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2788 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2789 | (minus:XF (match_dup 6) |
2790 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2791 | (use (const_int 1))])) |
2792 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2793 | (parallel [(set (match_dup 0) | |
02befdf4 | 2794 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2795 | (match_dup 0))) |
2796 | (use (const_int 1))])) | |
2797 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2798 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2799 | (use (const_int 1))])) |
2800 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2801 | (parallel [(set (match_dup 0) | |
02befdf4 | 2802 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2803 | (match_dup 0))) |
2804 | (use (const_int 1))])) | |
2805 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2806 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2807 | (use (const_int 1))])) |
2808 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2809 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2810 | (minus:XF (match_dup 1) |
2811 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2812 | (use (const_int 1))])) |
2813 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2814 | (parallel [(set (match_dup 0) | |
02befdf4 | 2815 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2816 | (match_dup 3))) |
2817 | (use (const_int 1))])) | |
2818 | ] | |
02befdf4 | 2819 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2820 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2821 | \f |
2822 | ;; :::::::::::::::::::: | |
2823 | ;; :: | |
27a9b99d | 2824 | ;; :: 128-bit Integer arithmetic |
a71aef0b JB |
2825 | ;; :: |
2826 | ;; :::::::::::::::::::: | |
2827 | ||
2828 | (define_insn "addti3" | |
2829 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2830 | (plus:TI (match_operand:TI 1 "gr_register_operand" "%r") | |
2831 | (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI"))) | |
2832 | (clobber (match_scratch:BI 3 "=&c"))] | |
2833 | "" | |
2834 | "#" | |
2835 | [(set_attr "itanium_class" "unknown")]) | |
2836 | ||
2837 | (define_split | |
2838 | [(set (match_operand:TI 0 "register_operand" "") | |
2839 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2840 | (match_operand:TI 2 "register_operand" ""))) | |
2841 | (clobber (match_scratch:BI 3 ""))] | |
2842 | "reload_completed" | |
2843 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2844 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2845 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2846 | (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6)))) | |
2847 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2848 | (set (match_dup 4) | |
2849 | (plus:DI (plus:DI (match_dup 5) (match_dup 6)) | |
2850 | (const_int 1))))] | |
2851 | { | |
2852 | operands[4] = gen_highpart (DImode, operands[0]); | |
2853 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2854 | operands[5] = gen_highpart (DImode, operands[1]); | |
2855 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2856 | operands[6] = gen_highpart (DImode, operands[2]); | |
2857 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2858 | }) | |
2859 | ||
2860 | (define_split | |
2861 | [(set (match_operand:TI 0 "register_operand" "") | |
2862 | (plus:TI (match_operand:TI 1 "register_operand" "") | |
2863 | (match_operand:TI 2 "immediate_operand" ""))) | |
2864 | (clobber (match_scratch:BI 3 ""))] | |
2865 | "reload_completed" | |
2866 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2))) | |
2867 | (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1))) | |
2868 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2869 | (set (match_dup 4) | |
2870 | (plus:DI (match_dup 5) (match_dup 6)))) | |
2871 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2872 | (set (match_dup 4) | |
2873 | (plus:DI (match_dup 5) (match_dup 7))))] | |
2874 | { | |
2875 | operands[4] = gen_highpart (DImode, operands[0]); | |
2876 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2877 | operands[5] = gen_highpart (DImode, operands[1]); | |
2878 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2879 | operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx; | |
2880 | operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx; | |
2881 | }) | |
2882 | ||
2883 | (define_insn "subti3" | |
2884 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2885 | (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK") | |
2886 | (match_operand:TI 2 "gr_register_operand" "r"))) | |
2887 | (clobber (match_scratch:BI 3 "=&c"))] | |
2888 | "" | |
2889 | "#" | |
2890 | [(set_attr "itanium_class" "unknown")]) | |
2891 | ||
2892 | (define_split | |
2893 | [(set (match_operand:TI 0 "register_operand" "") | |
2894 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
2895 | (match_operand:TI 2 "register_operand" ""))) | |
2896 | (clobber (match_scratch:BI 3 "=&c"))] | |
2897 | "reload_completed" | |
2898 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) | |
2899 | (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0))) | |
2900 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2901 | (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6)))) | |
2902 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2903 | (set (match_dup 4) | |
2904 | (plus:DI (not:DI (match_dup 6)) (match_dup 5))))] | |
2905 | { | |
2906 | operands[4] = gen_highpart (DImode, operands[0]); | |
2907 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2908 | operands[5] = gen_highpart (DImode, operands[1]); | |
2909 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2910 | operands[6] = gen_highpart (DImode, operands[2]); | |
2911 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2912 | }) | |
2913 | ||
2914 | (define_split | |
2915 | [(set (match_operand:TI 0 "register_operand" "") | |
2916 | (minus:TI (match_operand:TI 1 "immediate_operand" "") | |
2917 | (match_operand:TI 2 "register_operand" ""))) | |
2918 | (clobber (match_scratch:BI 3 "=&c"))] | |
13f70342 | 2919 | "reload_completed && satisfies_constraint_K (operands[1])" |
a71aef0b JB |
2920 | [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2))) |
2921 | (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1))) | |
2922 | (cond_exec (ne (match_dup 3) (const_int 0)) | |
2923 | (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5)))) | |
2924 | (cond_exec (eq (match_dup 3) (const_int 0)) | |
2925 | (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))] | |
2926 | { | |
2927 | operands[4] = gen_highpart (DImode, operands[0]); | |
2928 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2929 | operands[5] = gen_highpart (DImode, operands[2]); | |
2930 | operands[2] = gen_lowpart (DImode, operands[2]); | |
2931 | operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx; | |
2932 | operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; | |
2933 | }) | |
2934 | ||
2935 | (define_expand "mulditi3" | |
2936 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2937 | (mult:TI (sign_extend:TI | |
6adb807e | 2938 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2939 | (sign_extend:TI |
6adb807e | 2940 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2941 | "" |
2942 | "") | |
2943 | ||
2944 | (define_insn_and_split "*mulditi3_internal" | |
2945 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2946 | (mult:TI (sign_extend:TI | |
6adb807e | 2947 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2948 | (sign_extend:TI |
6adb807e | 2949 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2950 | "" |
2951 | "#" | |
2952 | "reload_completed" | |
2953 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2954 | (set (match_dup 3) (truncate:DI | |
2955 | (lshiftrt:TI | |
2956 | (mult:TI (sign_extend:TI (match_dup 1)) | |
2957 | (sign_extend:TI (match_dup 2))) | |
2958 | (const_int 64))))] | |
2959 | { | |
2960 | operands[3] = gen_highpart (DImode, operands[0]); | |
2961 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2962 | } | |
2963 | [(set_attr "itanium_class" "unknown")]) | |
2964 | ||
2965 | (define_expand "umulditi3" | |
2966 | [(set (match_operand:TI 0 "fr_register_operand" "") | |
2967 | (mult:TI (zero_extend:TI | |
6adb807e | 2968 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "")) |
a71aef0b | 2969 | (zero_extend:TI |
6adb807e | 2970 | (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))] |
a71aef0b JB |
2971 | "" |
2972 | "") | |
2973 | ||
2974 | (define_insn_and_split "*umulditi3_internal" | |
2975 | [(set (match_operand:TI 0 "fr_register_operand" "=&f") | |
2976 | (mult:TI (zero_extend:TI | |
6adb807e | 2977 | (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")) |
a71aef0b | 2978 | (zero_extend:TI |
6adb807e | 2979 | (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))] |
a71aef0b JB |
2980 | "" |
2981 | "#" | |
2982 | "reload_completed" | |
2983 | [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2))) | |
2984 | (set (match_dup 3) (truncate:DI | |
2985 | (lshiftrt:TI | |
2986 | (mult:TI (zero_extend:TI (match_dup 1)) | |
2987 | (zero_extend:TI (match_dup 2))) | |
2988 | (const_int 64))))] | |
2989 | { | |
2990 | operands[3] = gen_highpart (DImode, operands[0]); | |
2991 | operands[0] = gen_lowpart (DImode, operands[0]); | |
2992 | } | |
2993 | [(set_attr "itanium_class" "unknown")]) | |
2994 | ||
2995 | (define_insn_and_split "negti2" | |
2996 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
2997 | (neg:TI (match_operand:TI 1 "gr_register_operand" "r"))) | |
2998 | (clobber (match_scratch:BI 2 "=&c"))] | |
2999 | "" | |
3000 | "#" | |
3001 | "reload_completed" | |
3002 | [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0))) | |
3003 | (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1))) | |
3004 | (cond_exec (eq (match_dup 2) (const_int 0)) | |
3005 | (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4)))) | |
3006 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
3007 | (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))] | |
3008 | { | |
3009 | operands[3] = gen_highpart (DImode, operands[0]); | |
3010 | operands[0] = gen_lowpart (DImode, operands[0]); | |
3011 | operands[4] = gen_highpart (DImode, operands[1]); | |
3012 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3013 | } | |
3014 | [(set_attr "itanium_class" "unknown")]) | |
3015 | \f | |
3016 | ;; :::::::::::::::::::: | |
3017 | ;; :: | |
27a9b99d | 3018 | ;; :: 32-bit floating point arithmetic |
c65ebc55 JW |
3019 | ;; :: |
3020 | ;; :::::::::::::::::::: | |
3021 | ||
3022 | (define_insn "addsf3" | |
0551c32d | 3023 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3024 | (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3025 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3026 | "" |
6adb807e | 3027 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3028 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3029 | |
3030 | (define_insn "subsf3" | |
0551c32d RH |
3031 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3032 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3033 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3034 | "" |
aebf2462 | 3035 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3036 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3037 | |
3038 | (define_insn "mulsf3" | |
0551c32d | 3039 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3040 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3041 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3042 | "" |
6adb807e | 3043 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3044 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3045 | |
3046 | (define_insn "abssf2" | |
0551c32d | 3047 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3048 | (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3049 | "" |
6adb807e | 3050 | "fabs %0 = %F1" |
52e12ad0 | 3051 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3052 | |
3053 | (define_insn "negsf2" | |
0551c32d | 3054 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3055 | (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3056 | "" |
6adb807e | 3057 | "fneg %0 = %F1" |
52e12ad0 | 3058 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3059 | |
3060 | (define_insn "*nabssf2" | |
0551c32d | 3061 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3062 | (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 3063 | "" |
6adb807e | 3064 | "fnegabs %0 = %F1" |
52e12ad0 | 3065 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3066 | |
046625fa RH |
3067 | (define_insn "copysignsf3" |
3068 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3069 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3070 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3071 | UNSPEC_COPYSIGN))] | |
3072 | "" | |
3073 | "fmerge.s %0 = %F2, %F1" | |
3074 | [(set_attr "itanium_class" "fmisc")]) | |
3075 | ||
3076 | (define_insn "*ncopysignsf3" | |
3077 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3078 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
3079 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
3080 | UNSPEC_COPYSIGN)))] | |
3081 | "" | |
3082 | "fmerge.ns %0 = %F2, %F1" | |
3083 | [(set_attr "itanium_class" "fmisc")]) | |
3084 | ||
7ae4d8d4 | 3085 | (define_insn "sminsf3" |
0551c32d | 3086 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3087 | (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3088 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3089 | "" |
6adb807e | 3090 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3091 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3092 | |
7ae4d8d4 | 3093 | (define_insn "smaxsf3" |
0551c32d | 3094 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e | 3095 | (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3096 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3097 | "" |
6adb807e | 3098 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3099 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3100 | |
655f2eb9 | 3101 | (define_insn "*maddsf4" |
0551c32d | 3102 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3103 | (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3104 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3105 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3106 | "" |
6adb807e | 3107 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3108 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3109 | |
655f2eb9 | 3110 | (define_insn "*msubsf4" |
0551c32d | 3111 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3112 | (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3113 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3114 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3115 | "" |
6adb807e | 3116 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3117 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
3118 | |
3119 | (define_insn "*nmulsf3" | |
0551c32d | 3120 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
6adb807e SE |
3121 | (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3122 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3123 | "" |
6adb807e | 3124 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3125 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3126 | |
655f2eb9 | 3127 | (define_insn "*nmaddsf4" |
0551c32d | 3128 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b | 3129 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3130 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3131 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3132 | "" |
6adb807e | 3133 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3134 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3135 | |
52ad4d7b ZW |
3136 | (define_insn "*nmaddsf4_alts" |
3137 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3138 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
6adb807e SE |
3139 | (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") |
3140 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))) | |
52ad4d7b ZW |
3141 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3142 | "" | |
6adb807e | 3143 | "fnma.s.s%4 %0 = %F1, %F2, %F3" |
52ad4d7b ZW |
3144 | [(set_attr "itanium_class" "fmac")]) |
3145 | ||
26102535 RH |
3146 | (define_expand "divsf3" |
3147 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
6adb807e SE |
3148 | (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "") |
3149 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 3150 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3151 | { |
3152 | rtx insn; | |
dbdd120f | 3153 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3154 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
3155 | else | |
3156 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
3157 | emit_insn (insn); | |
3158 | DONE; | |
1d5d7a21 | 3159 | }) |
26102535 | 3160 | |
b38ba463 ZW |
3161 | ;; Inline square root. |
3162 | ||
3163 | (define_insn "*sqrt_approx" | |
3164 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3165 | (div:XF (const_int 1) | |
6adb807e | 3166 | (unspec:XF [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] |
07acc7b3 | 3167 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) |
b38ba463 ZW |
3168 | (set (match_operand:BI 1 "register_operand" "=c") |
3169 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3170 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
3171 | "" | |
3172 | "frsqrta.s%3 %0, %1 = %2" | |
3173 | [(set_attr "itanium_class" "fmisc") | |
3174 | (set_attr "predicable" "no")]) | |
3175 | ||
9aec7fb4 | 3176 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3177 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3178 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3179 | UNSPEC_SETF_EXP))] | |
3180 | "" | |
3181 | "setf.exp %0 = %1" | |
3182 | [(set_attr "itanium_class" "frfr")]) | |
3183 | ||
3184 | (define_expand "sqrtsf2" | |
3185 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
6adb807e | 3186 | (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
3187 | "TARGET_INLINE_SQRT" |
3188 | { | |
3189 | rtx insn; | |
b38ba463 | 3190 | #if 0 |
e820471b | 3191 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3192 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 3193 | else |
b38ba463 | 3194 | #else |
e820471b | 3195 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3196 | #endif |
e820471b | 3197 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3198 | emit_insn (insn); |
3199 | DONE; | |
3200 | }) | |
3201 | ||
3202 | ;; Latency-optimized square root. | |
3203 | ;; FIXME: Implement. | |
3204 | ||
3205 | ;; Throughput-optimized square root. | |
3206 | ||
3207 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3208 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
6adb807e | 3209 | (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))) |
b38ba463 ZW |
3210 | ;; Register r2 in optimization guide. |
3211 | (clobber (match_scratch:DI 2 "=r")) | |
3212 | ;; Register f8 in optimization guide | |
3213 | (clobber (match_scratch:XF 3 "=&f")) | |
3214 | ;; Register f9 in optimization guide | |
3215 | (clobber (match_scratch:XF 4 "=&f")) | |
3216 | ;; Register f10 in optimization guide | |
3217 | (clobber (match_scratch:XF 5 "=&f")) | |
3218 | ;; Register p6 in optimization guide. | |
3219 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3220 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3221 | "#" |
3222 | "&& reload_completed" | |
3223 | [ ;; exponent of +1/2 in r2 | |
3224 | (set (match_dup 2) (const_int 65534)) | |
3225 | ;; +1/2 in f8 | |
3226 | (set (match_dup 3) | |
3227 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3228 | ;; Step 1 | |
3229 | ;; y0 = 1/sqrt(a) in f7 | |
3230 | (parallel [(set (match_dup 7) | |
3231 | (div:XF (const_int 1) | |
07acc7b3 JW |
3232 | (unspec:XF [(match_dup 8)] |
3233 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
3234 | (set (match_dup 6) |
3235 | (unspec:BI [(match_dup 8)] | |
07acc7b3 | 3236 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
3237 | (use (const_int 0))]) |
3238 | ;; Step 2 | |
3239 | ;; H0 = 1/2 * y0 in f9 | |
3240 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3241 | (parallel [(set (match_dup 4) | |
3242 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3243 | (match_dup 9))) | |
3244 | (use (const_int 1))])) | |
3245 | ;; Step 3 | |
3246 | ;; S0 = a * y0 in f7 | |
3247 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3248 | (parallel [(set (match_dup 7) | |
3249 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3250 | (match_dup 9))) | |
3251 | (use (const_int 1))])) | |
3252 | ;; Step 4 | |
3253 | ;; d = 1/2 - S0 * H0 in f10 | |
3254 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3255 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3256 | (minus:XF (match_dup 3) |
3257 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3258 | (use (const_int 1))])) |
3259 | ;; Step 5 | |
3260 | ;; d' = d + 1/2 * d in f8 | |
3261 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3262 | (parallel [(set (match_dup 3) | |
3263 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3264 | (match_dup 5))) | |
3265 | (use (const_int 1))])) | |
3266 | ;; Step 6 | |
3267 | ;; e = d + d * d' in f8 | |
3268 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3269 | (parallel [(set (match_dup 3) | |
3270 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3271 | (match_dup 5))) | |
3272 | (use (const_int 1))])) | |
3273 | ;; Step 7 | |
3274 | ;; S1 = S0 + e * S0 in f7 | |
3275 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3276 | (parallel [(set (match_dup 0) | |
3277 | (float_truncate:SF | |
3278 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3279 | (match_dup 7)))) | |
3280 | (use (const_int 1))])) | |
3281 | ;; Step 8 | |
3282 | ;; H1 = H0 + e * H0 in f8 | |
3283 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3284 | (parallel [(set (match_dup 3) | |
3285 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3286 | (match_dup 4))) | |
3287 | (use (const_int 1))])) | |
3288 | ;; Step 9 | |
3289 | ;; d1 = a - S1 * S1 in f9 | |
3290 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3291 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3292 | (minus:XF (match_dup 8) |
3293 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3294 | (use (const_int 1))])) |
3295 | ;; Step 10 | |
3296 | ;; S = S1 + d1 * H1 in f7 | |
3297 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3298 | (parallel [(set (match_dup 0) | |
3299 | (float_truncate:SF | |
3300 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3301 | (match_dup 7)))) | |
3302 | (use (const_int 0))]))] | |
3303 | { | |
3304 | /* Generate 82-bit versions of the input and output operands. */ | |
3305 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3306 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3307 | /* Generate required floating-point constants. */ | |
3308 | operands[9] = CONST0_RTX (XFmode); | |
3309 | } | |
3310 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3311 | \f |
3312 | ;; :::::::::::::::::::: | |
3313 | ;; :: | |
27a9b99d | 3314 | ;; :: 64-bit floating point arithmetic |
c65ebc55 JW |
3315 | ;; :: |
3316 | ;; :::::::::::::::::::: | |
3317 | ||
3318 | (define_insn "adddf3" | |
0551c32d | 3319 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3320 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3321 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3322 | "" |
6adb807e | 3323 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3324 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3325 | |
26102535 RH |
3326 | (define_insn "*adddf3_trunc" |
3327 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3328 | (float_truncate:SF | |
6adb807e | 3329 | (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
26102535 RH |
3330 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] |
3331 | "" | |
6adb807e | 3332 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3333 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3334 | |
c65ebc55 | 3335 | (define_insn "subdf3" |
0551c32d RH |
3336 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3337 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3338 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3339 | "" |
aebf2462 | 3340 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3341 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3342 | |
26102535 RH |
3343 | (define_insn "*subdf3_trunc" |
3344 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3345 | (float_truncate:SF | |
3346 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3347 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3348 | "" | |
aebf2462 | 3349 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3350 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3351 | |
c65ebc55 | 3352 | (define_insn "muldf3" |
0551c32d | 3353 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3354 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3355 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3356 | "" |
6adb807e | 3357 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3358 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3359 | |
26102535 RH |
3360 | (define_insn "*muldf3_trunc" |
3361 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3362 | (float_truncate:SF | |
6adb807e SE |
3363 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3364 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
26102535 | 3365 | "" |
6adb807e | 3366 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3367 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3368 | |
c65ebc55 | 3369 | (define_insn "absdf2" |
0551c32d | 3370 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3371 | (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3372 | "" |
6adb807e | 3373 | "fabs %0 = %F1" |
52e12ad0 | 3374 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3375 | |
3376 | (define_insn "negdf2" | |
0551c32d | 3377 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3378 | (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3379 | "" |
6adb807e | 3380 | "fneg %0 = %F1" |
52e12ad0 | 3381 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3382 | |
3383 | (define_insn "*nabsdf2" | |
0551c32d | 3384 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3385 | (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))] |
c65ebc55 | 3386 | "" |
6adb807e | 3387 | "fnegabs %0 = %F1" |
52e12ad0 | 3388 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3389 | |
046625fa RH |
3390 | (define_insn "copysigndf3" |
3391 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3392 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3393 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3394 | UNSPEC_COPYSIGN))] | |
3395 | "" | |
3396 | "fmerge.s %0 = %F2, %F1" | |
3397 | [(set_attr "itanium_class" "fmisc")]) | |
3398 | ||
3399 | (define_insn "*ncopysigndf3" | |
3400 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3401 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3402 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
3403 | UNSPEC_COPYSIGN)))] | |
3404 | "" | |
3405 | "fmerge.ns %0 = %F2, %F1" | |
3406 | [(set_attr "itanium_class" "fmisc")]) | |
3407 | ||
7ae4d8d4 | 3408 | (define_insn "smindf3" |
0551c32d | 3409 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3410 | (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3411 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3412 | "" |
6adb807e | 3413 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3414 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3415 | |
7ae4d8d4 | 3416 | (define_insn "smaxdf3" |
0551c32d | 3417 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e | 3418 | (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
0551c32d | 3419 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3420 | "" |
6adb807e | 3421 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3422 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3423 | |
655f2eb9 | 3424 | (define_insn "*madddf4" |
0551c32d | 3425 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3426 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3427 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3428 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3429 | "" |
6adb807e | 3430 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3431 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3432 | |
26102535 RH |
3433 | (define_insn "*madddf4_trunc" |
3434 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3435 | (float_truncate:SF | |
6adb807e SE |
3436 | (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3437 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 RH |
3438 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
3439 | "" | |
6adb807e | 3440 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3441 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3442 | |
655f2eb9 | 3443 | (define_insn "*msubdf4" |
0551c32d | 3444 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3445 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3446 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
0551c32d | 3447 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 3448 | "" |
6adb807e | 3449 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3450 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3451 | |
26102535 RH |
3452 | (define_insn "*msubdf4_trunc" |
3453 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3454 | (float_truncate:SF | |
6adb807e SE |
3455 | (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3456 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")) | |
26102535 RH |
3457 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] |
3458 | "" | |
6adb807e | 3459 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3460 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3461 | |
c65ebc55 | 3462 | (define_insn "*nmuldf3" |
0551c32d | 3463 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
6adb807e SE |
3464 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3465 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3466 | "" |
6adb807e | 3467 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3468 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3469 | |
26102535 RH |
3470 | (define_insn "*nmuldf3_trunc" |
3471 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3472 | (float_truncate:SF | |
6adb807e SE |
3473 | (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3474 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
26102535 | 3475 | "" |
6adb807e | 3476 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3477 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3478 | |
655f2eb9 | 3479 | (define_insn "*nmadddf4" |
0551c32d | 3480 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b | 3481 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3482 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3483 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
c65ebc55 | 3484 | "" |
6adb807e | 3485 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3486 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3487 | |
3488 | (define_insn "*nmadddf4_alts" | |
3489 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b | 3490 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3491 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3492 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))) | |
26102535 RH |
3493 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3494 | "" | |
6adb807e | 3495 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3496 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3497 | |
52ad4d7b | 3498 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3499 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3500 | (float_truncate:SF | |
52ad4d7b | 3501 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
6adb807e SE |
3502 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3503 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))] | |
26102535 | 3504 | "" |
6adb807e | 3505 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3506 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3507 | |
52ad4d7b ZW |
3508 | (define_insn "*nmadddf4_truncsf_alts" |
3509 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3510 | (float_truncate:SF | |
3511 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
6adb807e SE |
3512 | (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") |
3513 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))) | |
52ad4d7b ZW |
3514 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3515 | "" | |
6adb807e | 3516 | "fnma.s.s%4 %0 = %F1, %F2, %F3" |
52ad4d7b ZW |
3517 | [(set_attr "itanium_class" "fmac")]) |
3518 | ||
26102535 RH |
3519 | (define_expand "divdf3" |
3520 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
6adb807e SE |
3521 | (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "") |
3522 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 3523 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3524 | { |
3525 | rtx insn; | |
dbdd120f | 3526 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3527 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3528 | else | |
3529 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3530 | emit_insn (insn); | |
3531 | DONE; | |
1d5d7a21 | 3532 | }) |
26102535 | 3533 | |
b38ba463 ZW |
3534 | ;; Inline square root. |
3535 | ||
3536 | (define_expand "sqrtdf2" | |
3537 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
6adb807e | 3538 | (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
3539 | "TARGET_INLINE_SQRT" |
3540 | { | |
3541 | rtx insn; | |
b38ba463 | 3542 | #if 0 |
e820471b | 3543 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3544 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3545 | else |
b38ba463 | 3546 | #else |
e820471b | 3547 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3548 | #endif |
e820471b | 3549 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3550 | emit_insn (insn); |
3551 | DONE; | |
3552 | }) | |
3553 | ||
3554 | ;; Latency-optimized square root. | |
3555 | ;; FIXME: Implement. | |
3556 | ||
3557 | ;; Throughput-optimized square root. | |
3558 | ||
3559 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3560 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
6adb807e | 3561 | (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))) |
b38ba463 ZW |
3562 | ;; Register r2 in optimization guide. |
3563 | (clobber (match_scratch:DI 2 "=r")) | |
3564 | ;; Register f8 in optimization guide | |
3565 | (clobber (match_scratch:XF 3 "=&f")) | |
3566 | ;; Register f9 in optimization guide | |
3567 | (clobber (match_scratch:XF 4 "=&f")) | |
3568 | ;; Register f10 in optimization guide | |
3569 | (clobber (match_scratch:XF 5 "=&f")) | |
3570 | ;; Register p6 in optimization guide. | |
3571 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3572 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3573 | "#" |
3574 | "&& reload_completed" | |
3575 | [ ;; exponent of +1/2 in r2 | |
3576 | (set (match_dup 2) (const_int 65534)) | |
3577 | ;; +1/2 in f10 | |
3578 | (set (match_dup 5) | |
3579 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3580 | ;; Step 1 | |
3581 | ;; y0 = 1/sqrt(a) in f7 | |
3582 | (parallel [(set (match_dup 7) | |
3583 | (div:XF (const_int 1) | |
07acc7b3 JW |
3584 | (unspec:XF [(match_dup 8)] |
3585 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
3586 | (set (match_dup 6) |
3587 | (unspec:BI [(match_dup 8)] | |
07acc7b3 | 3588 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
3589 | (use (const_int 0))]) |
3590 | ;; Step 2 | |
3591 | ;; H0 = 1/2 * y0 in f8 | |
3592 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3593 | (parallel [(set (match_dup 3) | |
3594 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3595 | (match_dup 9))) | |
3596 | (use (const_int 1))])) | |
3597 | ;; Step 3 | |
3598 | ;; G0 = a * y0 in f7 | |
3599 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3600 | (parallel [(set (match_dup 7) | |
3601 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3602 | (match_dup 9))) | |
3603 | (use (const_int 1))])) | |
3604 | ;; Step 4 | |
3605 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3606 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3607 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3608 | (minus:XF (match_dup 5) |
3609 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3610 | (use (const_int 1))])) |
3611 | ;; Step 5 | |
3612 | ;; H1 = H0 + r0 * H0 in f8 | |
3613 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3614 | (parallel [(set (match_dup 3) | |
3615 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3616 | (match_dup 3))) | |
3617 | (use (const_int 1))])) | |
3618 | ;; Step 6 | |
3619 | ;; G1 = G0 + r0 * G0 in f7 | |
3620 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3621 | (parallel [(set (match_dup 7) | |
3622 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3623 | (match_dup 7))) | |
3624 | (use (const_int 1))])) | |
3625 | ;; Step 7 | |
3626 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3627 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3628 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3629 | (minus:XF (match_dup 5) |
3630 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3631 | (use (const_int 1))])) |
3632 | ;; Step 8 | |
3633 | ;; H2 = H1 + r1 * H1 in f8 | |
3634 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3635 | (parallel [(set (match_dup 3) | |
3636 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3637 | (match_dup 3))) | |
3638 | (use (const_int 1))])) | |
3639 | ;; Step 9 | |
3640 | ;; G2 = G1 + r1 * G1 in f7 | |
3641 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3642 | (parallel [(set (match_dup 7) | |
3643 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3644 | (match_dup 7))) | |
3645 | (use (const_int 1))])) | |
3646 | ;; Step 10 | |
3647 | ;; d2 = a - G2 * G2 in f9 | |
3648 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3649 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3650 | (minus:XF (match_dup 8) |
3651 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3652 | (use (const_int 1))])) |
3653 | ;; Step 11 | |
3654 | ;; G3 = G2 + d2 * H2 in f7 | |
3655 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3656 | (parallel [(set (match_dup 7) | |
3657 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3658 | (match_dup 7))) | |
3659 | (use (const_int 1))])) | |
3660 | ;; Step 12 | |
3661 | ;; d3 = a - G3 * G3 in f9 | |
3662 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3663 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3664 | (minus:XF (match_dup 8) |
3665 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3666 | (use (const_int 1))])) |
3667 | ;; Step 13 | |
3668 | ;; S = G3 + d3 * H2 in f7 | |
3669 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3670 | (parallel [(set (match_dup 0) | |
3671 | (float_truncate:DF | |
3672 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3673 | (match_dup 7)))) | |
3674 | (use (const_int 0))]))] | |
3675 | { | |
3676 | /* Generate 82-bit versions of the input and output operands. */ | |
3677 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3678 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3679 | /* Generate required floating-point constants. */ | |
3680 | operands[9] = CONST0_RTX (XFmode); | |
3681 | } | |
3682 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3683 | \f |
3684 | ;; :::::::::::::::::::: | |
3685 | ;; :: | |
27a9b99d | 3686 | ;; :: 80-bit floating point arithmetic |
3f622353 RH |
3687 | ;; :: |
3688 | ;; :::::::::::::::::::: | |
3689 | ||
02befdf4 ZW |
3690 | (define_insn "addxf3" |
3691 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3692 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3693 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3694 | "" | |
aebf2462 | 3695 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3696 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3697 | |
02befdf4 | 3698 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3699 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3700 | (float_truncate:SF | |
02befdf4 ZW |
3701 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3702 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3703 | "" | |
aebf2462 | 3704 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3705 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3706 | |
02befdf4 | 3707 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3708 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3709 | (float_truncate:DF | |
02befdf4 ZW |
3710 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3711 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3712 | "" | |
aebf2462 | 3713 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3714 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3715 | |
02befdf4 ZW |
3716 | (define_insn "subxf3" |
3717 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3718 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3719 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3720 | "" | |
aebf2462 | 3721 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3722 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3723 | |
02befdf4 | 3724 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3725 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3726 | (float_truncate:SF | |
02befdf4 ZW |
3727 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3728 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3729 | "" | |
aebf2462 | 3730 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3731 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3732 | |
02befdf4 | 3733 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3734 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3735 | (float_truncate:DF | |
02befdf4 ZW |
3736 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3737 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3738 | "" | |
aebf2462 | 3739 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3740 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3741 | |
02befdf4 ZW |
3742 | (define_insn "mulxf3" |
3743 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3744 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3745 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3746 | "" | |
aebf2462 | 3747 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3748 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3749 | |
02befdf4 | 3750 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3751 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3752 | (float_truncate:SF | |
02befdf4 ZW |
3753 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3754 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3755 | "" | |
aebf2462 | 3756 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3757 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3758 | |
02befdf4 | 3759 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3760 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3761 | (float_truncate:DF | |
02befdf4 ZW |
3762 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3763 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3764 | "" | |
aebf2462 | 3765 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3766 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3767 | |
02befdf4 ZW |
3768 | (define_insn "*mulxf3_alts" |
3769 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3770 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3771 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3772 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3773 | "" |
aebf2462 | 3774 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3775 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3776 | |
02befdf4 | 3777 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3778 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3779 | (float_truncate:SF | |
02befdf4 ZW |
3780 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3781 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3782 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3783 | "" |
aebf2462 | 3784 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3785 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3786 | |
02befdf4 | 3787 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3788 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3789 | (float_truncate:DF | |
02befdf4 ZW |
3790 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3791 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3792 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3793 | "" |
aebf2462 | 3794 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3795 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3796 | |
02befdf4 ZW |
3797 | (define_insn "absxf2" |
3798 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3799 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3800 | "" | |
aebf2462 | 3801 | "fabs %0 = %F1" |
52e12ad0 | 3802 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3803 | |
02befdf4 ZW |
3804 | (define_insn "negxf2" |
3805 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3806 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3807 | "" | |
aebf2462 | 3808 | "fneg %0 = %F1" |
52e12ad0 | 3809 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3810 | |
02befdf4 ZW |
3811 | (define_insn "*nabsxf2" |
3812 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3813 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3814 | "" | |
aebf2462 | 3815 | "fnegabs %0 = %F1" |
52e12ad0 | 3816 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3817 | |
046625fa RH |
3818 | (define_insn "copysignxf3" |
3819 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3820 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3821 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3822 | UNSPEC_COPYSIGN))] | |
3823 | "" | |
3824 | "fmerge.s %0 = %F2, %F1" | |
3825 | [(set_attr "itanium_class" "fmisc")]) | |
3826 | ||
3827 | (define_insn "*ncopysignxf3" | |
3828 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3829 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3830 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3831 | UNSPEC_COPYSIGN)))] | |
3832 | "" | |
3833 | "fmerge.ns %0 = %F2, %F1" | |
3834 | [(set_attr "itanium_class" "fmisc")]) | |
3835 | ||
7ae4d8d4 | 3836 | (define_insn "sminxf3" |
02befdf4 ZW |
3837 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3838 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3839 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3840 | "" | |
aebf2462 | 3841 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3842 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3843 | |
7ae4d8d4 | 3844 | (define_insn "smaxxf3" |
02befdf4 ZW |
3845 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3846 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3847 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3848 | "" | |
aebf2462 | 3849 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3850 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3851 | |
02befdf4 ZW |
3852 | (define_insn "*maddxf4" |
3853 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3854 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3855 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3856 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3857 | "" | |
aebf2462 | 3858 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3859 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3860 | |
02befdf4 | 3861 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3862 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3863 | (float_truncate:SF | |
02befdf4 ZW |
3864 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3865 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3866 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3867 | "" | |
aebf2462 | 3868 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3869 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3870 | |
02befdf4 | 3871 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3872 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3873 | (float_truncate:DF | |
02befdf4 ZW |
3874 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3875 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3876 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3877 | "" | |
aebf2462 | 3878 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3879 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3880 | |
02befdf4 ZW |
3881 | (define_insn "*maddxf4_alts" |
3882 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3883 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3884 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3885 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3886 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3887 | "" |
aebf2462 | 3888 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3889 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3890 | |
b38ba463 ZW |
3891 | (define_insn "*maddxf4_alts_truncsf" |
3892 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3893 | (float_truncate:SF | |
3894 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3895 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3896 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3897 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3898 | "" | |
3899 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3900 | [(set_attr "itanium_class" "fmac")]) | |
3901 | ||
02befdf4 | 3902 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3903 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3904 | (float_truncate:DF | |
02befdf4 ZW |
3905 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3906 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3907 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3908 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3909 | "" |
aebf2462 | 3910 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3911 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3912 | |
02befdf4 ZW |
3913 | (define_insn "*msubxf4" |
3914 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3915 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3916 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3917 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3918 | "" | |
aebf2462 | 3919 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3920 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3921 | |
02befdf4 | 3922 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3923 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3924 | (float_truncate:SF | |
02befdf4 ZW |
3925 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3926 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3927 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3928 | "" | |
aebf2462 | 3929 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3930 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3931 | |
02befdf4 | 3932 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3933 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3934 | (float_truncate:DF | |
02befdf4 ZW |
3935 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3936 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3937 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3938 | "" | |
aebf2462 | 3939 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3940 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3941 | |
02befdf4 ZW |
3942 | (define_insn "*nmulxf3" |
3943 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3944 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3945 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3946 | "" | |
aebf2462 | 3947 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3948 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3949 | |
02befdf4 | 3950 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3951 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3952 | (float_truncate:SF | |
02befdf4 ZW |
3953 | (neg:XF (mult:XF |
3954 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3955 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3956 | "" | |
aebf2462 | 3957 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3958 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3959 | |
02befdf4 | 3960 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3961 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3962 | (float_truncate:DF | |
02befdf4 ZW |
3963 | (neg:XF (mult:XF |
3964 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3965 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3966 | "" | |
aebf2462 | 3967 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3968 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3969 | |
02befdf4 ZW |
3970 | (define_insn "*nmaddxf4" |
3971 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3972 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3973 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3974 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3975 | )))] | |
02befdf4 | 3976 | "" |
aebf2462 | 3977 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3978 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3979 | |
02befdf4 | 3980 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3981 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3982 | (float_truncate:SF | |
52ad4d7b ZW |
3983 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3984 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3985 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3986 | ))))] | |
02befdf4 | 3987 | "" |
aebf2462 | 3988 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3989 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3990 | |
02befdf4 | 3991 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3992 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3993 | (float_truncate:DF | |
52ad4d7b ZW |
3994 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3995 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3996 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3997 | ))))] | |
02befdf4 | 3998 | "" |
aebf2462 | 3999 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4000 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4001 | |
02befdf4 ZW |
4002 | (define_insn "*nmaddxf4_alts" |
4003 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4004 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4005 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4006 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4007 | ))) | |
655f2eb9 | 4008 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4009 | "" |
aebf2462 | 4010 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4011 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4012 | |
52ad4d7b ZW |
4013 | (define_insn "*nmaddxf4_truncsf_alts" |
4014 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4015 | (float_truncate:SF | |
4016 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
4017 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4018 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4019 | )))) | |
4020 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4021 | "" | |
4022 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
4023 | [(set_attr "itanium_class" "fmac")]) | |
4024 | ||
02befdf4 | 4025 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
4026 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4027 | (float_truncate:DF | |
52ad4d7b ZW |
4028 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4029 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4030 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4031 | )))) | |
26102535 | 4032 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4033 | "" |
aebf2462 | 4034 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4035 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4036 | |
02befdf4 ZW |
4037 | (define_expand "divxf3" |
4038 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
6adb807e SE |
4039 | (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "") |
4040 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))] | |
02befdf4 | 4041 | "TARGET_INLINE_FLOAT_DIV" |
26102535 | 4042 | { |
13d1a6e7 SE |
4043 | /* There is only one divxf3 sequence, not two like for divsf and divdf. */ |
4044 | emit_insn (gen_divxf3_internal (operands[0], operands[1], operands[2])); | |
26102535 | 4045 | DONE; |
1d5d7a21 | 4046 | }) |
26102535 | 4047 | |
b38ba463 ZW |
4048 | ;; Inline square root. |
4049 | ||
4050 | (define_expand "sqrtxf2" | |
4051 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
6adb807e | 4052 | (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))] |
b38ba463 ZW |
4053 | "TARGET_INLINE_SQRT" |
4054 | { | |
4055 | rtx insn; | |
b38ba463 | 4056 | #if 0 |
e820471b | 4057 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 4058 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 4059 | else |
b38ba463 | 4060 | #else |
e820471b | 4061 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 4062 | #endif |
e820471b | 4063 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
4064 | emit_insn (insn); |
4065 | DONE; | |
4066 | }) | |
4067 | ||
4068 | ;; Latency-optimized square root. | |
4069 | ;; FIXME: Implement. | |
4070 | ||
4071 | ;; Throughput-optimized square root. | |
4072 | ||
4073 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4074 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
6adb807e | 4075 | (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG"))) |
b38ba463 ZW |
4076 | ;; Register r2 in optimization guide. |
4077 | (clobber (match_scratch:DI 2 "=r")) | |
4078 | ;; Register f8 in optimization guide | |
4079 | (clobber (match_scratch:XF 3 "=&f")) | |
4080 | ;; Register f9 in optimization guide | |
4081 | (clobber (match_scratch:XF 4 "=&f")) | |
4082 | ;; Register f10 in optimization guide | |
4083 | (clobber (match_scratch:XF 5 "=&f")) | |
4084 | ;; Register f11 in optimization guide | |
4085 | (clobber (match_scratch:XF 6 "=&f")) | |
4086 | ;; Register p6 in optimization guide. | |
4087 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 4088 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
4089 | "#" |
4090 | "&& reload_completed" | |
4091 | [ ;; exponent of +1/2 in r2 | |
4092 | (set (match_dup 2) (const_int 65534)) | |
4093 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4094 | (set (match_dup 3) | |
4095 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4096 | ;; Step 1 | |
4097 | ;; y0 = 1/sqrt(a) in f7 | |
4098 | (parallel [(set (match_dup 8) | |
4099 | (div:XF (const_int 1) | |
07acc7b3 JW |
4100 | (unspec:XF [(match_dup 9)] |
4101 | UNSPEC_FR_SQRT_RECIP_APPROX_RES))) | |
b38ba463 ZW |
4102 | (set (match_dup 7) |
4103 | (unspec:BI [(match_dup 9)] | |
07acc7b3 | 4104 | UNSPEC_FR_SQRT_RECIP_APPROX)) |
b38ba463 ZW |
4105 | (use (const_int 0))]) |
4106 | ;; Step 2 | |
4107 | ;; H0 = 1/2 * y0 in f9 | |
4108 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4109 | (parallel [(set (match_dup 4) | |
4110 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4111 | (match_dup 10))) | |
4112 | (use (const_int 1))])) | |
4113 | ;; Step 3 | |
4114 | ;; S0 = a * y0 in f7 | |
4115 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4116 | (parallel [(set (match_dup 8) | |
4117 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4118 | (match_dup 10))) | |
4119 | (use (const_int 1))])) | |
4120 | ;; Step 4 | |
4121 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4122 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4123 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4124 | (minus:XF (match_dup 3) |
4125 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4126 | (use (const_int 1))])) |
4127 | ;; Step 5 | |
4128 | ;; H1 = H0 + d0 * H0 in f9 | |
4129 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4130 | (parallel [(set (match_dup 4) | |
4131 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4132 | (match_dup 4))) | |
4133 | (use (const_int 1))])) | |
4134 | ;; Step 6 | |
4135 | ;; S1 = S0 + d0 * S0 in f7 | |
4136 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4137 | (parallel [(set (match_dup 8) | |
4138 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4139 | (match_dup 8))) | |
4140 | (use (const_int 1))])) | |
4141 | ;; Step 7 | |
4142 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4143 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4144 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4145 | (minus:XF (match_dup 3) |
4146 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4147 | (use (const_int 1))])) |
4148 | ;; Step 8 | |
4149 | ;; H2 = H1 + d1 * H1 in f9 | |
4150 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4151 | (parallel [(set (match_dup 4) | |
4152 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4153 | (match_dup 4))) | |
4154 | (use (const_int 1))])) | |
4155 | ;; Step 9 | |
4156 | ;; S2 = S1 + d1 * S1 in f7 | |
4157 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4158 | (parallel [(set (match_dup 8) | |
4159 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4160 | (match_dup 8))) | |
4161 | (use (const_int 1))])) | |
4162 | ;; Step 10 | |
4163 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4164 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4165 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4166 | (minus:XF (match_dup 3) |
4167 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4168 | (use (const_int 1))])) |
4169 | ;; Step 11 | |
4170 | ;; e2 = a - S2 * S2 in f8 | |
4171 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4172 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4173 | (minus:XF (match_dup 9) |
4174 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4175 | (use (const_int 1))])) |
4176 | ;; Step 12 | |
4177 | ;; S3 = S2 + e2 * H2 in f7 | |
4178 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4179 | (parallel [(set (match_dup 8) | |
4180 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4181 | (match_dup 8))) | |
4182 | (use (const_int 1))])) | |
4183 | ;; Step 13 | |
4184 | ;; H3 = H2 + d2 * H2 in f9 | |
4185 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4186 | (parallel [(set (match_dup 4) | |
4187 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4188 | (match_dup 4))) | |
4189 | (use (const_int 1))])) | |
4190 | ;; Step 14 | |
4191 | ;; e3 = a - S3 * S3 in f8 | |
4192 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4193 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4194 | (minus:XF (match_dup 9) |
4195 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4196 | (use (const_int 1))])) |
4197 | ;; Step 15 | |
4198 | ;; S = S3 + e3 * H3 in f7 | |
4199 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4200 | (parallel [(set (match_dup 0) | |
4201 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4202 | (match_dup 8))) | |
4203 | (use (const_int 0))]))] | |
4204 | { | |
4205 | /* Generate 82-bit versions of the input and output operands. */ | |
4206 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4207 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4208 | /* Generate required floating-point constants. */ | |
4209 | operands[10] = CONST0_RTX (XFmode); | |
4210 | } | |
4211 | [(set_attr "predicable" "no")]) | |
4212 | ||
26102535 RH |
4213 | ;; ??? frcpa works like cmp.foo.unc. |
4214 | ||
655f2eb9 | 4215 | (define_insn "*recip_approx" |
02befdf4 | 4216 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
07acc7b3 | 4217 | (unspec:XF [(const_int 1) |
6adb807e | 4218 | (match_operand:XF 3 "fr_reg_or_fp01_operand" "fG")] |
07acc7b3 | 4219 | UNSPEC_FR_RECIP_APPROX_RES)) |
f2f90c63 | 4220 | (set (match_operand:BI 1 "register_operand" "=c") |
6adb807e | 4221 | (unspec:BI [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") |
086c0f96 | 4222 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4223 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4224 | "" |
6adb807e | 4225 | "frcpa.s%4 %0, %1 = %F2, %F3" |
52e12ad0 | 4226 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4227 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4228 | \f |
4229 | ;; :::::::::::::::::::: | |
4230 | ;; :: | |
27a9b99d | 4231 | ;; :: 32-bit Integer Shifts and Rotates |
c65ebc55 JW |
4232 | ;; :: |
4233 | ;; :::::::::::::::::::: | |
4234 | ||
9c668921 | 4235 | (define_expand "ashlsi3" |
0551c32d RH |
4236 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4237 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4238 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4239 | "" |
9c668921 RH |
4240 | { |
4241 | if (GET_CODE (operands[2]) != CONST_INT) | |
4242 | { | |
4243 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4244 | we've got to get rid of stray bits outside the SImode register. */ | |
4245 | rtx subshift = gen_reg_rtx (DImode); | |
4246 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4247 | operands[2] = subshift; | |
4248 | } | |
1d5d7a21 | 4249 | }) |
9c668921 RH |
4250 | |
4251 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4252 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4253 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4254 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4255 | "" |
041f25e6 RH |
4256 | "@ |
4257 | shladd %0 = %1, %2, r0 | |
4258 | dep.z %0 = %1, %2, %E2 | |
4259 | shl %0 = %1, %2" | |
52e12ad0 | 4260 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4261 | |
4262 | (define_expand "ashrsi3" | |
0551c32d RH |
4263 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4264 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4265 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4266 | "" |
c65ebc55 | 4267 | { |
041f25e6 RH |
4268 | rtx subtarget = gen_reg_rtx (DImode); |
4269 | if (GET_CODE (operands[2]) == CONST_INT) | |
4270 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4271 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4272 | else | |
4273 | { | |
9c668921 | 4274 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4275 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4276 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4277 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4278 | } |
4279 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4280 | DONE; | |
1d5d7a21 | 4281 | }) |
c65ebc55 | 4282 | |
c65ebc55 | 4283 | (define_expand "lshrsi3" |
0551c32d RH |
4284 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4285 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4286 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4287 | "" |
c65ebc55 | 4288 | { |
041f25e6 RH |
4289 | rtx subtarget = gen_reg_rtx (DImode); |
4290 | if (GET_CODE (operands[2]) == CONST_INT) | |
4291 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4292 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4293 | else | |
4294 | { | |
9c668921 | 4295 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4296 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4297 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4298 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4299 | } |
4300 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4301 | DONE; | |
1d5d7a21 | 4302 | }) |
c65ebc55 | 4303 | |
c65ebc55 | 4304 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4305 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4306 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4307 | |
4308 | (define_expand "rotrsi3" | |
66db6b45 RH |
4309 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4310 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4311 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4312 | "" | |
66db6b45 RH |
4313 | { |
4314 | if (GET_MODE (operands[2]) != VOIDmode) | |
4315 | { | |
4316 | rtx tmp = gen_reg_rtx (DImode); | |
4317 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4318 | operands[2] = tmp; | |
4319 | } | |
1d5d7a21 | 4320 | }) |
66db6b45 RH |
4321 | |
4322 | (define_insn_and_split "*rotrsi3_internal" | |
4323 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4324 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4325 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4326 | "" | |
4327 | "#" | |
4328 | "reload_completed" | |
c65ebc55 | 4329 | [(set (match_dup 3) |
66db6b45 | 4330 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4331 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4332 | (set (match_dup 3) | |
66db6b45 RH |
4333 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4334 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4335 | ||
4336 | (define_expand "rotlsi3" | |
4337 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4338 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4339 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4340 | "" |
c65ebc55 JW |
4341 | { |
4342 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4343 | { |
4344 | rtx tmp = gen_reg_rtx (SImode); | |
4345 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4346 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4347 | DONE; | |
4348 | } | |
1d5d7a21 | 4349 | }) |
66db6b45 RH |
4350 | |
4351 | (define_insn_and_split "*rotlsi3_internal" | |
4352 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4353 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4354 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4355 | "" | |
51094457 JB |
4356 | "mux2 %0 = %1, 0xe1" |
4357 | "reload_completed && INTVAL (operands[2]) != 16" | |
66db6b45 RH |
4358 | [(set (match_dup 3) |
4359 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4360 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4361 | (set (match_dup 3) | |
4362 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4363 | { |
4364 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4365 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
51094457 JB |
4366 | } |
4367 | [(set_attr "itanium_class" "mmshf")]) | |
c65ebc55 JW |
4368 | \f |
4369 | ;; :::::::::::::::::::: | |
4370 | ;; :: | |
27a9b99d | 4371 | ;; :: 64-bit Integer Shifts and Rotates |
c65ebc55 JW |
4372 | ;; :: |
4373 | ;; :::::::::::::::::::: | |
4374 | ||
4375 | (define_insn "ashldi3" | |
52e12ad0 BS |
4376 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4377 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4378 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4379 | "" |
041f25e6 RH |
4380 | "@ |
4381 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4382 | shl %0 = %1, %2 |
041f25e6 | 4383 | shl %0 = %1, %2" |
52e12ad0 | 4384 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4385 | |
4386 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4387 | ||
4388 | (define_insn "*shladd" | |
0551c32d RH |
4389 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4390 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4391 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4392 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4393 | "" |
4394 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4395 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4396 | |
4397 | ;; This can be created by register elimination if operand3 of shladd is an | |
4398 | ;; eliminable register or has reg_equiv_constant set. | |
4399 | ||
4400 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4401 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4402 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4403 | ;; incorrectly. | |
4404 | ||
5527bf14 | 4405 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4406 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4407 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4408 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4409 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4410 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4411 | "reload_in_progress" | |
e820471b | 4412 | "* gcc_unreachable ();" |
c65ebc55 JW |
4413 | "reload_completed" |
4414 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4415 | (match_dup 3))) | |
c65ebc55 | 4416 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4417 | "" |
52e12ad0 | 4418 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4419 | |
4420 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4421 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4422 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4423 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4424 | "" |
52e12ad0 BS |
4425 | "@ |
4426 | shr %0 = %1, %2 | |
4427 | shr %0 = %1, %2" | |
4428 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4429 | |
4430 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4431 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4432 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4433 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4434 | "" |
52e12ad0 BS |
4435 | "@ |
4436 | shr.u %0 = %1, %2 | |
4437 | shr.u %0 = %1, %2" | |
4438 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4439 | |
4440 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4441 | ;; will load the operand into a register and call the pattern if the predicate | |
4442 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4443 | ;; verify that we have an appropriate constant in the expander. | |
4444 | ||
4445 | (define_expand "rotrdi3" | |
0551c32d RH |
4446 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4447 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4448 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4449 | "" | |
c65ebc55 JW |
4450 | { |
4451 | if (! shift_count_operand (operands[2], DImode)) | |
4452 | FAIL; | |
1d5d7a21 | 4453 | }) |
c65ebc55 JW |
4454 | |
4455 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4456 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4457 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4458 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4459 | "" | |
4460 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4461 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4462 | |
66db6b45 RH |
4463 | (define_expand "rotldi3" |
4464 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4465 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4466 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4467 | "" | |
66db6b45 RH |
4468 | { |
4469 | if (! shift_count_operand (operands[2], DImode)) | |
4470 | FAIL; | |
1d5d7a21 | 4471 | }) |
66db6b45 RH |
4472 | |
4473 | (define_insn "*rotldi3_internal" | |
4474 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4475 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4476 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4477 | "" | |
4478 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4479 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4480 | \f |
4481 | ;; :::::::::::::::::::: | |
4482 | ;; :: | |
27a9b99d | 4483 | ;; :: 128-bit Integer Shifts and Rotates |
f526a3c8 RH |
4484 | ;; :: |
4485 | ;; :::::::::::::::::::: | |
4486 | ||
16d8386b JB |
4487 | (define_expand "ashlti3" |
4488 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4489 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4490 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4491 | "" | |
4492 | { | |
4493 | if (!dshift_count_operand (operands[2], DImode)) | |
4494 | FAIL; | |
4495 | }) | |
4496 | ||
4497 | (define_insn_and_split "*ashlti3_internal" | |
4498 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4499 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4500 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4501 | "" | |
4502 | "#" | |
4503 | "reload_completed" | |
4504 | [(const_int 0)] | |
4505 | { | |
4506 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4507 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4508 | rtx rh = gen_highpart (DImode, operands[0]); | |
4509 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4510 | rtx shiftlo = GEN_INT (shift & 63); | |
4511 | ||
4512 | if (shift & 64) | |
4513 | { | |
4514 | emit_move_insn (rl, const0_rtx); | |
4515 | if (shift & 63) | |
4516 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4517 | else | |
4518 | emit_move_insn (rh, lo); | |
4519 | } | |
4520 | else | |
4521 | { | |
4522 | rtx hi = gen_highpart (DImode, operands[1]); | |
4523 | ||
4524 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4525 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4526 | } | |
4527 | DONE; | |
4528 | }) | |
4529 | ||
f526a3c8 RH |
4530 | (define_expand "ashrti3" |
4531 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4532 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4533 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4534 | "" | |
4535 | { | |
4536 | if (!dshift_count_operand (operands[2], DImode)) | |
4537 | FAIL; | |
4538 | }) | |
4539 | ||
4540 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4541 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4542 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4543 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4544 | "" | |
4545 | "#" | |
4546 | "reload_completed" | |
4547 | [(const_int 0)] | |
4548 | { | |
4549 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4550 | rtx rl = gen_lowpart (DImode, operands[0]); |
4551 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4552 | rtx hi = gen_highpart (DImode, operands[1]); |
4553 | rtx shiftlo = GEN_INT (shift & 63); | |
4554 | ||
4555 | if (shift & 64) | |
4556 | { | |
16d8386b JB |
4557 | if (shift & 63) |
4558 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4559 | else | |
4560 | emit_move_insn (rl, hi); | |
4561 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4562 | } |
4563 | else | |
4564 | { | |
16d8386b JB |
4565 | rtx lo = gen_lowpart (DImode, operands[1]); |
4566 | ||
4567 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4568 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4569 | } |
4570 | DONE; | |
4571 | }) | |
4572 | ||
4573 | (define_expand "lshrti3" | |
4574 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4575 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4576 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4577 | "" | |
4578 | { | |
4579 | if (!dshift_count_operand (operands[2], DImode)) | |
4580 | FAIL; | |
4581 | }) | |
4582 | ||
4583 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4584 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4585 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4586 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4587 | "" | |
4588 | "#" | |
4589 | "reload_completed" | |
4590 | [(const_int 0)] | |
4591 | { | |
4592 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4593 | rtx rl = gen_lowpart (DImode, operands[0]); |
4594 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4595 | rtx hi = gen_highpart (DImode, operands[1]); |
4596 | rtx shiftlo = GEN_INT (shift & 63); | |
4597 | ||
4598 | if (shift & 64) | |
4599 | { | |
16d8386b JB |
4600 | if (shift & 63) |
4601 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4602 | else | |
4603 | emit_move_insn (rl, hi); | |
4604 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4605 | } |
4606 | else | |
4607 | { | |
16d8386b JB |
4608 | rtx lo = gen_lowpart (DImode, operands[1]); |
4609 | ||
4610 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4611 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4612 | } |
4613 | DONE; | |
4614 | }) | |
4615 | ||
a71aef0b JB |
4616 | (define_expand "rotlti3" |
4617 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4618 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "") | |
4619 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4620 | "" | |
4621 | { | |
4622 | if (! dshift_count_operand (operands[2], DImode)) | |
4623 | FAIL; | |
4624 | }) | |
4625 | ||
4626 | (define_insn_and_split "*rotlti3_internal" | |
4627 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4628 | (rotate:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4629 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4630 | "" | |
4631 | "#" | |
4632 | "reload_completed" | |
4633 | [(const_int 0)] | |
4634 | { | |
4635 | HOST_WIDE_INT count = INTVAL (operands[2]); | |
4636 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4637 | rtx rh = gen_highpart (DImode, operands[0]); | |
4638 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4639 | rtx hi = gen_highpart (DImode, operands[1]); | |
4640 | rtx countlo = GEN_INT (-count & 63); | |
4641 | ||
4642 | if (count & 64) | |
4643 | { | |
4644 | if (count & 63) | |
4645 | { | |
4646 | emit_insn (gen_shrp (rl, hi, lo, countlo)); | |
4647 | emit_insn (gen_shrp (rh, lo, hi, countlo)); | |
4648 | } | |
4649 | else | |
4650 | { | |
4651 | emit_move_insn (rl, hi); | |
4652 | emit_move_insn (rh, lo); | |
4653 | } | |
4654 | } | |
4655 | else | |
4656 | { | |
4657 | emit_insn (gen_shrp (rl, lo, hi, countlo)); | |
4658 | emit_insn (gen_shrp (rh, hi, lo, countlo)); | |
4659 | } | |
4660 | DONE; | |
4661 | } | |
4662 | [(set_attr "itanium_class" "unknown")]) | |
4663 | ||
f526a3c8 RH |
4664 | (define_insn "shrp" |
4665 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4666 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4667 | (match_operand:DI 2 "gr_register_operand" "r") | |
4668 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4669 | UNSPEC_SHRP))] | |
4670 | "" | |
4671 | "shrp %0 = %1, %2, %3" | |
4672 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4673 | \f |
4674 | ;; :::::::::::::::::::: | |
4675 | ;; :: | |
27a9b99d | 4676 | ;; :: 32-bit Integer Logical operations |
c65ebc55 JW |
4677 | ;; :: |
4678 | ;; :::::::::::::::::::: | |
4679 | ||
4680 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4681 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4682 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4683 | ;; This doesn't work for unary logical operations, because we don't call | |
4684 | ;; apply_distributive_law for them. | |
4685 | ||
4686 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4687 | ;; apply_distributive_law. We get inefficient code for | |
4688 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4689 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4690 | ;; (zero_extend (and (not A) B)) in combine. | |
4691 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4692 | ;; one_cmplsi2 pattern. | |
4693 | ||
058557c4 | 4694 | (define_insn "one_cmplsi2" |
0551c32d RH |
4695 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4696 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4697 | "" |
4698 | "andcm %0 = -1, %1" | |
52e12ad0 | 4699 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4700 | \f |
4701 | ;; :::::::::::::::::::: | |
4702 | ;; :: | |
27a9b99d | 4703 | ;; :: 64-bit Integer Logical operations |
c65ebc55 JW |
4704 | ;; :: |
4705 | ;; :::::::::::::::::::: | |
4706 | ||
4707 | (define_insn "anddi3" | |
0551c32d RH |
4708 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4709 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4710 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4711 | "" |
4712 | "@ | |
4713 | and %0 = %2, %1 | |
aebf2462 | 4714 | fand %0 = %2, %1" |
52e12ad0 | 4715 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4716 | |
4717 | (define_insn "*andnot" | |
0551c32d RH |
4718 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4719 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4720 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4721 | "" |
4722 | "@ | |
4723 | andcm %0 = %2, %1 | |
aebf2462 | 4724 | fandcm %0 = %2, %1" |
52e12ad0 | 4725 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4726 | |
4727 | (define_insn "iordi3" | |
0551c32d RH |
4728 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4729 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4730 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4731 | "" |
4732 | "@ | |
4733 | or %0 = %2, %1 | |
aebf2462 | 4734 | for %0 = %2, %1" |
52e12ad0 | 4735 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4736 | |
4737 | (define_insn "xordi3" | |
0551c32d RH |
4738 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4739 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4740 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4741 | "" |
4742 | "@ | |
4743 | xor %0 = %2, %1 | |
aebf2462 | 4744 | fxor %0 = %2, %1" |
52e12ad0 | 4745 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4746 | |
4747 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4748 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4749 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4750 | "" |
4751 | "andcm %0 = -1, %1" | |
52e12ad0 | 4752 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4753 | \f |
4754 | ;; :::::::::::::::::::: | |
4755 | ;; :: | |
4756 | ;; :: Comparisons | |
4757 | ;; :: | |
4758 | ;; :::::::::::::::::::: | |
4759 | ||
f2f90c63 RH |
4760 | (define_expand "cmpbi" |
4761 | [(set (cc0) | |
4762 | (compare (match_operand:BI 0 "register_operand" "") | |
4763 | (match_operand:BI 1 "const_int_operand" "")))] | |
4764 | "" | |
f2f90c63 RH |
4765 | { |
4766 | ia64_compare_op0 = operands[0]; | |
4767 | ia64_compare_op1 = operands[1]; | |
4768 | DONE; | |
1d5d7a21 | 4769 | }) |
f2f90c63 | 4770 | |
c65ebc55 JW |
4771 | (define_expand "cmpsi" |
4772 | [(set (cc0) | |
0551c32d RH |
4773 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4774 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4775 | "" |
c65ebc55 JW |
4776 | { |
4777 | ia64_compare_op0 = operands[0]; | |
4778 | ia64_compare_op1 = operands[1]; | |
4779 | DONE; | |
1d5d7a21 | 4780 | }) |
c65ebc55 JW |
4781 | |
4782 | (define_expand "cmpdi" | |
4783 | [(set (cc0) | |
0551c32d RH |
4784 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4785 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4786 | "" |
c65ebc55 JW |
4787 | { |
4788 | ia64_compare_op0 = operands[0]; | |
4789 | ia64_compare_op1 = operands[1]; | |
4790 | DONE; | |
1d5d7a21 | 4791 | }) |
c65ebc55 JW |
4792 | |
4793 | (define_expand "cmpsf" | |
4794 | [(set (cc0) | |
0551c32d RH |
4795 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4796 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4797 | "" |
c65ebc55 JW |
4798 | { |
4799 | ia64_compare_op0 = operands[0]; | |
4800 | ia64_compare_op1 = operands[1]; | |
4801 | DONE; | |
1d5d7a21 | 4802 | }) |
c65ebc55 JW |
4803 | |
4804 | (define_expand "cmpdf" | |
4805 | [(set (cc0) | |
0551c32d RH |
4806 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4807 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4808 | "" |
c65ebc55 JW |
4809 | { |
4810 | ia64_compare_op0 = operands[0]; | |
4811 | ia64_compare_op1 = operands[1]; | |
4812 | DONE; | |
1d5d7a21 | 4813 | }) |
c65ebc55 | 4814 | |
02befdf4 | 4815 | (define_expand "cmpxf" |
c65ebc55 | 4816 | [(set (cc0) |
02befdf4 ZW |
4817 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
4818 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
4819 | "" | |
c65ebc55 JW |
4820 | { |
4821 | ia64_compare_op0 = operands[0]; | |
4822 | ia64_compare_op1 = operands[1]; | |
4823 | DONE; | |
1d5d7a21 | 4824 | }) |
c65ebc55 | 4825 | |
24ea7948 ZW |
4826 | (define_expand "cmptf" |
4827 | [(set (cc0) | |
4828 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
4829 | (match_operand:TF 1 "gr_register_operand" "")))] | |
4830 | "TARGET_HPUX" | |
4831 | { | |
4832 | ia64_compare_op0 = operands[0]; | |
4833 | ia64_compare_op1 = operands[1]; | |
4834 | DONE; | |
4835 | }) | |
4836 | ||
c65ebc55 | 4837 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4838 | [(set (match_operand:BI 0 "register_operand" "=c") |
4839 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4840 | [(match_operand:SI 2 "gr_register_operand" "r") |
4841 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4842 | "" |
4843 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4844 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4845 | |
18a3c539 JW |
4846 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4847 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4848 | ||
c65ebc55 | 4849 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4850 | [(set (match_operand:BI 0 "register_operand" "=c") |
4851 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4852 | [(match_operand:SI 2 "gr_register_operand" "r") |
4853 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4854 | "" |
18a3c539 | 4855 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4856 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4857 | |
4858 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4859 | [(set (match_operand:BI 0 "register_operand" "=c") |
4860 | (match_operator:BI 1 "normal_comparison_operator" | |
4861 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4862 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4863 | "" |
f2f90c63 | 4864 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4865 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4866 | |
18a3c539 JW |
4867 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4868 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4869 | ||
c65ebc55 | 4870 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4871 | [(set (match_operand:BI 0 "register_operand" "=c") |
4872 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4873 | [(match_operand:DI 2 "gr_register_operand" "r") |
4874 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4875 | "" |
18a3c539 | 4876 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4877 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4878 | |
4879 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4880 | [(set (match_operand:BI 0 "register_operand" "=c") |
4881 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4882 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4883 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4884 | "" |
4885 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4886 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4887 | |
4888 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4889 | [(set (match_operand:BI 0 "register_operand" "=c") |
4890 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4891 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4892 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4893 | "" |
4894 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4895 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4896 | |
02befdf4 | 4897 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4898 | [(set (match_operand:BI 0 "register_operand" "=c") |
4899 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4900 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
4901 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
4902 | "" | |
3f622353 | 4903 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4904 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4905 | |
c65ebc55 JW |
4906 | ;; ??? Can this pattern be generated? |
4907 | ||
4908 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4909 | [(set (match_operand:BI 0 "register_operand" "=c") |
4910 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4911 | (const_int 1) |
5d48891e | 4912 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4913 | (const_int 0)))] |
4914 | "" | |
4915 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4916 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4917 | |
4918 | (define_insn "*bit_one" | |
f2f90c63 RH |
4919 | [(set (match_operand:BI 0 "register_operand" "=c") |
4920 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4921 | (const_int 1) |
5d48891e | 4922 | (match_operand:DI 2 "shift_count_operand" "M")) |
c65ebc55 JW |
4923 | (const_int 0)))] |
4924 | "" | |
4925 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4926 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4927 | \f |
4928 | ;; :::::::::::::::::::: | |
4929 | ;; :: | |
4930 | ;; :: Branches | |
4931 | ;; :: | |
4932 | ;; :::::::::::::::::::: | |
4933 | ||
4934 | (define_expand "beq" | |
f2f90c63 RH |
4935 | [(set (pc) |
4936 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4937 | (label_ref (match_operand 0 "" "")) |
4938 | (pc)))] | |
4939 | "" | |
f2f90c63 | 4940 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4941 | |
4942 | (define_expand "bne" | |
f2f90c63 RH |
4943 | [(set (pc) |
4944 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4945 | (label_ref (match_operand 0 "" "")) |
4946 | (pc)))] | |
4947 | "" | |
f2f90c63 | 4948 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4949 | |
4950 | (define_expand "blt" | |
f2f90c63 RH |
4951 | [(set (pc) |
4952 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4953 | (label_ref (match_operand 0 "" "")) |
4954 | (pc)))] | |
4955 | "" | |
f2f90c63 | 4956 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4957 | |
4958 | (define_expand "ble" | |
f2f90c63 RH |
4959 | [(set (pc) |
4960 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4961 | (label_ref (match_operand 0 "" "")) |
4962 | (pc)))] | |
4963 | "" | |
f2f90c63 | 4964 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4965 | |
4966 | (define_expand "bgt" | |
f2f90c63 RH |
4967 | [(set (pc) |
4968 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4969 | (label_ref (match_operand 0 "" "")) |
4970 | (pc)))] | |
4971 | "" | |
f2f90c63 | 4972 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4973 | |
4974 | (define_expand "bge" | |
f2f90c63 RH |
4975 | [(set (pc) |
4976 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4977 | (label_ref (match_operand 0 "" "")) |
4978 | (pc)))] | |
4979 | "" | |
f2f90c63 | 4980 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4981 | |
4982 | (define_expand "bltu" | |
f2f90c63 RH |
4983 | [(set (pc) |
4984 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4985 | (label_ref (match_operand 0 "" "")) |
4986 | (pc)))] | |
4987 | "" | |
f2f90c63 | 4988 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4989 | |
4990 | (define_expand "bleu" | |
f2f90c63 RH |
4991 | [(set (pc) |
4992 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4993 | (label_ref (match_operand 0 "" "")) |
4994 | (pc)))] | |
4995 | "" | |
f2f90c63 | 4996 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4997 | |
4998 | (define_expand "bgtu" | |
f2f90c63 RH |
4999 | [(set (pc) |
5000 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5001 | (label_ref (match_operand 0 "" "")) |
5002 | (pc)))] | |
5003 | "" | |
f2f90c63 | 5004 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5005 | |
5006 | (define_expand "bgeu" | |
f2f90c63 RH |
5007 | [(set (pc) |
5008 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5009 | (label_ref (match_operand 0 "" "")) |
5010 | (pc)))] | |
5011 | "" | |
f2f90c63 | 5012 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5013 | |
e57b9d65 | 5014 | (define_expand "bunordered" |
f2f90c63 RH |
5015 | [(set (pc) |
5016 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5017 | (label_ref (match_operand 0 "" "")) |
5018 | (pc)))] | |
5019 | "" | |
f2f90c63 | 5020 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5021 | |
5022 | (define_expand "bordered" | |
f2f90c63 RH |
5023 | [(set (pc) |
5024 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5025 | (label_ref (match_operand 0 "" "")) |
5026 | (pc)))] | |
5027 | "" | |
f2f90c63 | 5028 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5029 | |
6b6c1201 | 5030 | (define_insn "*br_true" |
c65ebc55 | 5031 | [(set (pc) |
6b6c1201 | 5032 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5033 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5034 | (const_int 0)]) |
5035 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5036 | (pc)))] |
5037 | "" | |
85548039 | 5038 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5039 | [(set_attr "itanium_class" "br") |
e5bde68a | 5040 | (set_attr "predicable" "no")]) |
c65ebc55 | 5041 | |
6b6c1201 | 5042 | (define_insn "*br_false" |
c65ebc55 | 5043 | [(set (pc) |
6b6c1201 | 5044 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5045 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5046 | (const_int 0)]) |
c65ebc55 | 5047 | (pc) |
6b6c1201 | 5048 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5049 | "" |
85548039 | 5050 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5051 | [(set_attr "itanium_class" "br") |
e5bde68a | 5052 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5053 | \f |
5054 | ;; :::::::::::::::::::: | |
5055 | ;; :: | |
5527bf14 RH |
5056 | ;; :: Counted loop operations |
5057 | ;; :: | |
5058 | ;; :::::::::::::::::::: | |
5059 | ||
5060 | (define_expand "doloop_end" | |
5061 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5062 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5063 | (use (match_operand 2 "" "")) ; max iterations | |
5064 | (use (match_operand 3 "" "")) ; loop level | |
5065 | (use (match_operand 4 "" ""))] ; label | |
5066 | "" | |
5527bf14 RH |
5067 | { |
5068 | /* Only use cloop on innermost loops. */ | |
5069 | if (INTVAL (operands[3]) > 1) | |
5070 | FAIL; | |
5071 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5072 | operands[4])); | |
5073 | DONE; | |
1d5d7a21 | 5074 | }) |
5527bf14 RH |
5075 | |
5076 | (define_insn "doloop_end_internal" | |
5077 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5078 | (const_int 0)) | |
5079 | (label_ref (match_operand 1 "" "")) | |
5080 | (pc))) | |
5081 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5082 | (plus:DI (match_dup 0) (const_int -1)) |
5083 | (match_dup 0)))] | |
5527bf14 RH |
5084 | "" |
5085 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5086 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5087 | (set_attr "predicable" "no")]) |
5088 | \f | |
5089 | ;; :::::::::::::::::::: | |
5090 | ;; :: | |
c65ebc55 JW |
5091 | ;; :: Set flag operations |
5092 | ;; :: | |
5093 | ;; :::::::::::::::::::: | |
5094 | ||
5095 | (define_expand "seq" | |
f2f90c63 | 5096 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5097 | "" |
f2f90c63 | 5098 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5099 | |
5100 | (define_expand "sne" | |
f2f90c63 | 5101 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5102 | "" |
f2f90c63 | 5103 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5104 | |
5105 | (define_expand "slt" | |
f2f90c63 | 5106 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5107 | "" |
f2f90c63 | 5108 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5109 | |
5110 | (define_expand "sle" | |
f2f90c63 | 5111 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5112 | "" |
f2f90c63 | 5113 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5114 | |
5115 | (define_expand "sgt" | |
f2f90c63 | 5116 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5117 | "" |
f2f90c63 | 5118 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5119 | |
5120 | (define_expand "sge" | |
f2f90c63 | 5121 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5122 | "" |
f2f90c63 | 5123 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5124 | |
5125 | (define_expand "sltu" | |
f2f90c63 | 5126 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5127 | "" |
f2f90c63 | 5128 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5129 | |
5130 | (define_expand "sleu" | |
f2f90c63 | 5131 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5132 | "" |
f2f90c63 | 5133 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5134 | |
5135 | (define_expand "sgtu" | |
f2f90c63 | 5136 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5137 | "" |
f2f90c63 | 5138 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5139 | |
5140 | (define_expand "sgeu" | |
f2f90c63 | 5141 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5142 | "" |
f2f90c63 | 5143 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5144 | |
e57b9d65 | 5145 | (define_expand "sunordered" |
f2f90c63 | 5146 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5147 | "" |
f2f90c63 | 5148 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5149 | |
5150 | (define_expand "sordered" | |
f2f90c63 | 5151 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5152 | "" |
f2f90c63 | 5153 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5154 | |
c65ebc55 JW |
5155 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5156 | ;; efficient than mov/mov/cst/cst. | |
5157 | ||
0551c32d RH |
5158 | (define_insn_and_split "*sne_internal" |
5159 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5160 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5161 | (const_int 0)))] |
5162 | "" | |
5163 | "#" | |
c65ebc55 | 5164 | "reload_completed" |
f2f90c63 RH |
5165 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5166 | (set (match_dup 0) (const_int 1))) | |
5167 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5168 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5169 | "" |
52e12ad0 | 5170 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5171 | |
0551c32d RH |
5172 | (define_insn_and_split "*seq_internal" |
5173 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5174 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5175 | (const_int 0)))] |
5176 | "" | |
5177 | "#" | |
c65ebc55 | 5178 | "reload_completed" |
f2f90c63 RH |
5179 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5180 | (set (match_dup 0) (const_int 0))) | |
5181 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5182 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5183 | "" |
52e12ad0 | 5184 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5185 | \f |
5186 | ;; :::::::::::::::::::: | |
5187 | ;; :: | |
5188 | ;; :: Conditional move instructions. | |
5189 | ;; :: | |
5190 | ;; :::::::::::::::::::: | |
5191 | ||
5192 | ;; ??? Add movXXcc patterns? | |
5193 | ||
c65ebc55 JW |
5194 | ;; |
5195 | ;; DImode if_then_else patterns. | |
5196 | ;; | |
5197 | ||
75cdbeb8 | 5198 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5199 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5200 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5201 | (if_then_else:DI |
f2f90c63 RH |
5202 | (match_operator 4 "predicate_operator" |
5203 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5204 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5205 | (const_int 0)]) |
f2f90c63 | 5206 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5207 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5208 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5209 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5210 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5211 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5212 | { gcc_unreachable (); } |
75cdbeb8 RH |
5213 | [(set_attr "predicable" "no")]) |
5214 | ||
5215 | (define_split | |
f2f90c63 | 5216 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5217 | (if_then_else |
f2f90c63 RH |
5218 | (match_operator 4 "predicate_operator" |
5219 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5220 | (const_int 0)]) |
f2f90c63 RH |
5221 | (match_operand 2 "move_operand" "") |
5222 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5223 | "reload_completed" |
5224 | [(const_int 0)] | |
e5bde68a | 5225 | { |
21515593 RH |
5226 | bool emitted_something = false; |
5227 | rtx dest = operands[0]; | |
5228 | rtx srct = operands[2]; | |
5229 | rtx srcf = operands[3]; | |
5230 | rtx cond = operands[4]; | |
2f937369 | 5231 | |
21515593 | 5232 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5233 | { |
21515593 RH |
5234 | ia64_emit_cond_move (dest, srct, cond); |
5235 | emitted_something = true; | |
e5bde68a | 5236 | } |
21515593 | 5237 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5238 | { |
21515593 RH |
5239 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5240 | VOIDmode, operands[1], const0_rtx); | |
5241 | ia64_emit_cond_move (dest, srcf, cond); | |
5242 | emitted_something = true; | |
3b572406 | 5243 | } |
2f937369 | 5244 | if (! emitted_something) |
f9974026 | 5245 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5246 | DONE; |
1d5d7a21 | 5247 | }) |
c65ebc55 JW |
5248 | |
5249 | ;; Absolute value pattern. | |
5250 | ||
5251 | (define_insn "*absdi2_internal" | |
0551c32d | 5252 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5253 | (if_then_else:DI |
f2f90c63 RH |
5254 | (match_operator 4 "predicate_operator" |
5255 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5256 | (const_int 0)]) |
0551c32d RH |
5257 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5258 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5259 | "" |
e5bde68a | 5260 | "#" |
52e12ad0 | 5261 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5262 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5263 | |
5264 | (define_split | |
5265 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5266 | (if_then_else:DI |
f2f90c63 RH |
5267 | (match_operator 4 "predicate_operator" |
5268 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5269 | (const_int 0)]) |
0551c32d RH |
5270 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5271 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5272 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5273 | [(cond_exec | |
5274 | (match_dup 4) | |
5275 | (set (match_dup 0) | |
5276 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5277 | "") |
5278 | ||
e5bde68a RH |
5279 | (define_split |
5280 | [(set (match_operand:DI 0 "register_operand" "") | |
5281 | (if_then_else:DI | |
f2f90c63 RH |
5282 | (match_operator 4 "predicate_operator" |
5283 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5284 | (const_int 0)]) |
0551c32d RH |
5285 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5286 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5287 | "reload_completed" |
5288 | [(cond_exec | |
5289 | (match_dup 4) | |
5290 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5291 | (cond_exec | |
5292 | (match_dup 5) | |
5293 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5294 | { |
5295 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5296 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5297 | }) |
c65ebc55 JW |
5298 | |
5299 | ;; | |
5300 | ;; SImode if_then_else patterns. | |
5301 | ;; | |
5302 | ||
75cdbeb8 | 5303 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5304 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5305 | (if_then_else:SI |
f2f90c63 RH |
5306 | (match_operator 4 "predicate_operator" |
5307 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5308 | (const_int 0)]) |
f2f90c63 | 5309 | (match_operand:SI 2 "move_operand" |
3b572406 | 5310 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5311 | (match_operand:SI 3 "move_operand" |
3b572406 | 5312 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5313 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5314 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5315 | { gcc_unreachable (); } |
3b572406 | 5316 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5317 | |
5318 | (define_insn "*abssi2_internal" | |
0551c32d | 5319 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5320 | (if_then_else:SI |
f2f90c63 RH |
5321 | (match_operator 4 "predicate_operator" |
5322 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5323 | (const_int 0)]) |
0551c32d RH |
5324 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5325 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5326 | "" |
e5bde68a | 5327 | "#" |
52e12ad0 | 5328 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5329 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5330 | |
5331 | (define_split | |
5332 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5333 | (if_then_else:SI |
f2f90c63 RH |
5334 | (match_operator 4 "predicate_operator" |
5335 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5336 | (const_int 0)]) |
0551c32d RH |
5337 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5338 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5339 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5340 | [(cond_exec | |
5341 | (match_dup 4) | |
5342 | (set (match_dup 0) | |
5343 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5344 | "") |
5345 | ||
e5bde68a RH |
5346 | (define_split |
5347 | [(set (match_operand:SI 0 "register_operand" "") | |
5348 | (if_then_else:SI | |
f2f90c63 RH |
5349 | (match_operator 4 "predicate_operator" |
5350 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5351 | (const_int 0)]) |
0551c32d RH |
5352 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5353 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5354 | "reload_completed" |
5355 | [(cond_exec | |
5356 | (match_dup 4) | |
5357 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5358 | (cond_exec | |
5359 | (match_dup 5) | |
5360 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5361 | { |
5362 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5363 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5364 | }) |
e5bde68a | 5365 | |
7dcc803e | 5366 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5367 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5368 | (match_operator:SI 5 "condop_operator" | |
5369 | [(if_then_else:SI | |
5370 | (match_operator 6 "predicate_operator" | |
5371 | [(match_operand:BI 1 "register_operand" "c") | |
5372 | (const_int 0)]) | |
5373 | (match_operand:SI 2 "gr_register_operand" "r") | |
5374 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5375 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5376 | "" | |
5377 | "#" | |
acb0638d BS |
5378 | "reload_completed" |
5379 | [(cond_exec | |
5380 | (match_dup 6) | |
5381 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5382 | (cond_exec | |
5383 | (match_dup 7) | |
5384 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5385 | { |
5386 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5387 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5388 | } |
7dcc803e BS |
5389 | [(set_attr "itanium_class" "ialu") |
5390 | (set_attr "predicable" "no")]) | |
5391 | ||
acb0638d | 5392 | |
7dcc803e | 5393 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5394 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5395 | (match_operator:SI 5 "condop_operator" | |
5396 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5397 | (if_then_else:SI | |
5398 | (match_operator 6 "predicate_operator" | |
5399 | [(match_operand:BI 1 "register_operand" "c") | |
5400 | (const_int 0)]) | |
5401 | (match_operand:SI 2 "gr_register_operand" "r") | |
5402 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5403 | "" | |
5404 | "#" | |
acb0638d BS |
5405 | "reload_completed" |
5406 | [(cond_exec | |
5407 | (match_dup 6) | |
5408 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5409 | (cond_exec | |
5410 | (match_dup 7) | |
5411 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5412 | { |
5413 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5414 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5415 | } |
7dcc803e BS |
5416 | [(set_attr "itanium_class" "ialu") |
5417 | (set_attr "predicable" "no")]) | |
acb0638d | 5418 | |
c65ebc55 JW |
5419 | \f |
5420 | ;; :::::::::::::::::::: | |
5421 | ;; :: | |
5422 | ;; :: Call and branch instructions | |
5423 | ;; :: | |
5424 | ;; :::::::::::::::::::: | |
5425 | ||
5426 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5427 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5428 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5429 | ;; registers used as operands. | |
5430 | ||
5431 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5432 | ;; is supplied for the sake of some RISC machines which need to put this | |
5433 | ;; information into the assembler code; they can put it in the RTL instead of | |
5434 | ;; operand 1. | |
5435 | ||
5436 | (define_expand "call" | |
5437 | [(use (match_operand:DI 0 "" "")) | |
5438 | (use (match_operand 1 "" "")) | |
5439 | (use (match_operand 2 "" "")) | |
5440 | (use (match_operand 3 "" ""))] | |
5441 | "" | |
c65ebc55 | 5442 | { |
599aedd9 | 5443 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5444 | DONE; |
1d5d7a21 | 5445 | }) |
c65ebc55 | 5446 | |
2ed4af6f RH |
5447 | (define_expand "sibcall" |
5448 | [(use (match_operand:DI 0 "" "")) | |
5449 | (use (match_operand 1 "" "")) | |
5450 | (use (match_operand 2 "" "")) | |
5451 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5452 | "" |
c65ebc55 | 5453 | { |
599aedd9 | 5454 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5455 | DONE; |
1d5d7a21 | 5456 | }) |
c65ebc55 | 5457 | |
c65ebc55 | 5458 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5459 | ;; register in which the value is returned. There are three more operands, |
5460 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5461 | ;; increased by one). |
2ed4af6f | 5462 | ;; |
c65ebc55 JW |
5463 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5464 | ||
5465 | (define_expand "call_value" | |
5466 | [(use (match_operand 0 "" "")) | |
5467 | (use (match_operand:DI 1 "" "")) | |
5468 | (use (match_operand 2 "" "")) | |
5469 | (use (match_operand 3 "" "")) | |
5470 | (use (match_operand 4 "" ""))] | |
5471 | "" | |
c65ebc55 | 5472 | { |
599aedd9 | 5473 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5474 | DONE; |
1d5d7a21 | 5475 | }) |
c65ebc55 | 5476 | |
2ed4af6f RH |
5477 | (define_expand "sibcall_value" |
5478 | [(use (match_operand 0 "" "")) | |
5479 | (use (match_operand:DI 1 "" "")) | |
5480 | (use (match_operand 2 "" "")) | |
5481 | (use (match_operand 3 "" "")) | |
5482 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5483 | "" |
c65ebc55 | 5484 | { |
599aedd9 | 5485 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5486 | DONE; |
1d5d7a21 | 5487 | }) |
c65ebc55 | 5488 | |
c65ebc55 JW |
5489 | ;; Call subroutine returning any type. |
5490 | ||
5491 | (define_expand "untyped_call" | |
5492 | [(parallel [(call (match_operand 0 "" "") | |
5493 | (const_int 0)) | |
5494 | (match_operand 1 "" "") | |
5495 | (match_operand 2 "" "")])] | |
5496 | "" | |
c65ebc55 JW |
5497 | { |
5498 | int i; | |
5499 | ||
5500 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5501 | ||
5502 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5503 | { | |
5504 | rtx set = XVECEXP (operands[2], 0, i); | |
5505 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5506 | } | |
5507 | ||
5508 | /* The optimizer does not know that the call sets the function value | |
5509 | registers we stored in the result block. We avoid problems by | |
5510 | claiming that all hard registers are used and clobbered at this | |
5511 | point. */ | |
5512 | emit_insn (gen_blockage ()); | |
5513 | ||
5514 | DONE; | |
1d5d7a21 | 5515 | }) |
c65ebc55 | 5516 | |
599aedd9 RH |
5517 | (define_insn "call_nogp" |
5518 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5519 | (const_int 0)) | |
5520 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5521 | "" |
599aedd9 | 5522 | "br.call%+.many %1 = %0" |
52e12ad0 | 5523 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5524 | |
599aedd9 | 5525 | (define_insn "call_value_nogp" |
75293ad6 | 5526 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5527 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5528 | (const_int 0))) | |
5529 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5530 | "" |
599aedd9 | 5531 | "br.call%+.many %2 = %1" |
52e12ad0 | 5532 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5533 | |
599aedd9 RH |
5534 | (define_insn "sibcall_nogp" |
5535 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5536 | (const_int 0))] | |
2ed4af6f RH |
5537 | "" |
5538 | "br%+.many %0" | |
52e12ad0 | 5539 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5540 | |
599aedd9 | 5541 | (define_insn "call_gp" |
c8083186 | 5542 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5543 | (const_int 1)) |
5544 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5545 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5546 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5547 | "" |
599aedd9 | 5548 | "#" |
52e12ad0 | 5549 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5550 | |
599aedd9 RH |
5551 | ;; Irritatingly, we don't have access to INSN within the split body. |
5552 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5553 | (define_split | |
5554 | [(call (mem (match_operand 0 "call_operand" "")) | |
5555 | (const_int 1)) | |
5556 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5557 | (clobber (match_scratch:DI 2 "")) | |
5558 | (clobber (match_scratch:DI 3 ""))] | |
5559 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5560 | [(const_int 0)] | |
5561 | { | |
5562 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5563 | operands[3], true, false); | |
5564 | DONE; | |
5565 | }) | |
5566 | ||
5567 | (define_split | |
5568 | [(call (mem (match_operand 0 "call_operand" "")) | |
5569 | (const_int 1)) | |
5570 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5571 | (clobber (match_scratch:DI 2 "")) | |
5572 | (clobber (match_scratch:DI 3 ""))] | |
5573 | "reload_completed" | |
5574 | [(const_int 0)] | |
5575 | { | |
5576 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5577 | operands[3], false, false); | |
5578 | DONE; | |
5579 | }) | |
5580 | ||
5581 | (define_insn "call_value_gp" | |
75293ad6 | 5582 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5583 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5584 | (const_int 1))) | |
5585 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5586 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5587 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5588 | "" |
599aedd9 | 5589 | "#" |
52e12ad0 | 5590 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5591 | |
599aedd9 RH |
5592 | (define_split |
5593 | [(set (match_operand 0 "" "") | |
5594 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5595 | (const_int 1))) | |
5596 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5597 | (clobber (match_scratch:DI 3 "")) | |
5598 | (clobber (match_scratch:DI 4 ""))] | |
5599 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5600 | [(const_int 0)] | |
5601 | { | |
5602 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5603 | operands[4], true, false); | |
5604 | DONE; | |
5605 | }) | |
5606 | ||
5607 | (define_split | |
5608 | [(set (match_operand 0 "" "") | |
5609 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5610 | (const_int 1))) | |
5611 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5612 | (clobber (match_scratch:DI 3 "")) | |
5613 | (clobber (match_scratch:DI 4 ""))] | |
5614 | "reload_completed" | |
5615 | [(const_int 0)] | |
5616 | { | |
5617 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5618 | operands[4], false, false); | |
5619 | DONE; | |
5620 | }) | |
5621 | ||
5622 | (define_insn_and_split "sibcall_gp" | |
5623 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5624 | (const_int 1)) | |
5625 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5626 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5627 | "" |
599aedd9 RH |
5628 | "#" |
5629 | "reload_completed" | |
5630 | [(const_int 0)] | |
5631 | { | |
5632 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5633 | operands[2], true, true); | |
5634 | DONE; | |
5635 | } | |
52e12ad0 | 5636 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5637 | |
c65ebc55 JW |
5638 | (define_insn "return_internal" |
5639 | [(return) | |
5640 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5641 | "" | |
5642 | "br.ret.sptk.many %0" | |
52e12ad0 | 5643 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5644 | |
5645 | (define_insn "return" | |
5646 | [(return)] | |
5647 | "ia64_direct_return ()" | |
5648 | "br.ret.sptk.many rp" | |
52e12ad0 | 5649 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5650 | |
6b6c1201 | 5651 | (define_insn "*return_true" |
c65ebc55 | 5652 | [(set (pc) |
6b6c1201 | 5653 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5654 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5655 | (const_int 0)]) |
c65ebc55 JW |
5656 | (return) |
5657 | (pc)))] | |
5658 | "ia64_direct_return ()" | |
13da91fd | 5659 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5660 | [(set_attr "itanium_class" "br") |
e5bde68a | 5661 | (set_attr "predicable" "no")]) |
c65ebc55 | 5662 | |
6b6c1201 | 5663 | (define_insn "*return_false" |
c65ebc55 | 5664 | [(set (pc) |
6b6c1201 | 5665 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5666 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5667 | (const_int 0)]) |
c65ebc55 JW |
5668 | (pc) |
5669 | (return)))] | |
5670 | "ia64_direct_return ()" | |
13da91fd | 5671 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5672 | [(set_attr "itanium_class" "br") |
e5bde68a | 5673 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5674 | |
5675 | (define_insn "jump" | |
5676 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5677 | "" | |
5678 | "br %l0" | |
52e12ad0 | 5679 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5680 | |
5681 | (define_insn "indirect_jump" | |
5682 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5683 | "" | |
5684 | "br %0" | |
52e12ad0 | 5685 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5686 | |
5687 | (define_expand "tablejump" | |
340f7e7c RH |
5688 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5689 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5690 | "" |
c65ebc55 | 5691 | { |
340f7e7c RH |
5692 | rtx op0 = operands[0]; |
5693 | rtx addr; | |
5694 | ||
5695 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5696 | element into a register without bothering to see whether that | |
5697 | is necessary given the operand predicate. Check for MEM just | |
5698 | in case someone fixes this. */ | |
5699 | if (GET_CODE (op0) == MEM) | |
5700 | addr = XEXP (op0, 0); | |
5701 | else | |
5702 | { | |
5703 | /* Otherwise, cheat and guess that the previous insn in the | |
5704 | stream was the memory load. Grab the address from that. | |
5705 | Note we have to momentarily pop out of the sequence started | |
5706 | by the insn-emit wrapper in order to grab the last insn. */ | |
5707 | rtx last, set; | |
5708 | ||
5709 | end_sequence (); | |
5710 | last = get_last_insn (); | |
5711 | start_sequence (); | |
5712 | set = single_set (last); | |
5713 | ||
e820471b NS |
5714 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5715 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5716 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5717 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5718 | } |
c65ebc55 | 5719 | |
340f7e7c RH |
5720 | /* Jump table elements are stored pc-relative. That is, a displacement |
5721 | from the entry to the label. Thus to convert to an absolute address | |
5722 | we add the address of the memory from which the value is loaded. */ | |
5723 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5724 | NULL_RTX, 1, OPTAB_DIRECT); | |
5725 | }) | |
c65ebc55 | 5726 | |
340f7e7c | 5727 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5728 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5729 | (use (label_ref (match_operand 1 "" "")))] | |
5730 | "" | |
5731 | "br %0" | |
52e12ad0 | 5732 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5733 | |
5734 | \f | |
5735 | ;; :::::::::::::::::::: | |
5736 | ;; :: | |
5737 | ;; :: Prologue and Epilogue instructions | |
5738 | ;; :: | |
5739 | ;; :::::::::::::::::::: | |
5740 | ||
5741 | (define_expand "prologue" | |
5742 | [(const_int 1)] | |
5743 | "" | |
c65ebc55 JW |
5744 | { |
5745 | ia64_expand_prologue (); | |
5746 | DONE; | |
1d5d7a21 | 5747 | }) |
c65ebc55 JW |
5748 | |
5749 | (define_expand "epilogue" | |
2ed4af6f RH |
5750 | [(return)] |
5751 | "" | |
2ed4af6f RH |
5752 | { |
5753 | ia64_expand_epilogue (0); | |
5754 | DONE; | |
1d5d7a21 | 5755 | }) |
2ed4af6f RH |
5756 | |
5757 | (define_expand "sibcall_epilogue" | |
5758 | [(return)] | |
c65ebc55 | 5759 | "" |
c65ebc55 | 5760 | { |
2ed4af6f | 5761 | ia64_expand_epilogue (1); |
c65ebc55 | 5762 | DONE; |
1d5d7a21 | 5763 | }) |
c65ebc55 JW |
5764 | |
5765 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5766 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5767 | ||
5768 | (define_insn "prologue_allocate_stack" | |
5769 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5770 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5771 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5772 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5773 | (match_dup 3))] |
5774 | "" | |
5775 | "@ | |
1d5d7a21 RH |
5776 | add %0 = %1, %2 |
5777 | adds %0 = %2, %1 | |
5778 | addl %0 = %2, %1" | |
52e12ad0 | 5779 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5780 | |
5781 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5782 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5783 | ||
5784 | (define_insn "epilogue_deallocate_stack" | |
5785 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5786 | (match_operand:DI 1 "register_operand" "+r")) | |
5787 | (set (match_dup 1) (match_dup 1))] | |
5788 | "" | |
5789 | "mov %0 = %1" | |
52e12ad0 | 5790 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5791 | |
1d5d7a21 RH |
5792 | ;; As USE insns aren't meaningful after reload, this is used instead |
5793 | ;; to prevent deleting instructions setting registers for EH handling | |
5794 | (define_insn "prologue_use" | |
5795 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5796 | UNSPEC_PROLOGUE_USE)] | |
5797 | "" | |
5798 | "" | |
5799 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5800 | (set_attr "predicable" "no") |
5801 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5802 | |
c65ebc55 JW |
5803 | ;; Allocate a new register frame. |
5804 | ||
5805 | (define_insn "alloc" | |
5806 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5807 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5808 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5809 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5810 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5811 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5812 | "" | |
5813 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5814 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
5815 | (set_attr "predicable" "no") |
5816 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 5817 | |
97e242b0 RH |
5818 | ;; Modifies ar.unat |
5819 | (define_expand "gr_spill" | |
870f9ec0 RH |
5820 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5821 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5822 | (match_operand:DI 2 "const_int_operand" "")] |
5823 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5824 | (clobber (match_dup 3))])] |
97e242b0 | 5825 | "" |
870f9ec0 | 5826 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5827 | |
870f9ec0 | 5828 | (define_insn "gr_spill_internal" |
b6fb7d46 | 5829 | [(set (match_operand:DI 0 "destination_operand" "=m") |
870f9ec0 | 5830 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5831 | (match_operand:DI 2 "const_int_operand" "")] |
5832 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5833 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5834 | "" |
2130b7fb | 5835 | { |
1d5d7a21 RH |
5836 | /* Note that we use a C output pattern here to avoid the predicate |
5837 | being automatically added before the .mem.offset directive. */ | |
5838 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5839 | } | |
52e12ad0 | 5840 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5841 | |
97e242b0 RH |
5842 | ;; Reads ar.unat |
5843 | (define_expand "gr_restore" | |
870f9ec0 RH |
5844 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5845 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5846 | (match_operand:DI 2 "const_int_operand" "")] |
5847 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5848 | (use (match_dup 3))])] |
97e242b0 | 5849 | "" |
870f9ec0 | 5850 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5851 | |
870f9ec0 | 5852 | (define_insn "gr_restore_internal" |
c65ebc55 | 5853 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5854 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5855 | (match_operand:DI 2 "const_int_operand" "")] |
5856 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5857 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5858 | "" |
1d5d7a21 | 5859 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5860 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5861 | |
5862 | (define_insn "fr_spill" | |
b6fb7d46 | 5863 | [(set (match_operand:XF 0 "destination_operand" "=m") |
02befdf4 | 5864 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] |
086c0f96 | 5865 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5866 | "" |
5867 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5868 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5869 | |
5870 | (define_insn "fr_restore" | |
02befdf4 ZW |
5871 | [(set (match_operand:XF 0 "register_operand" "=f") |
5872 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5873 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5874 | "" |
5875 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5876 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5877 | |
0024a804 JW |
5878 | ;; ??? The explicit stop is not ideal. It would be better if |
5879 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5880 | ;; fixed later. This avoids an RSE DV. | |
5881 | ||
0c96007e AM |
5882 | (define_insn "bsp_value" |
5883 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5884 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5885 | "" |
582d11e6 JW |
5886 | "* |
5887 | { | |
5888 | return \";;\;%,mov %0 = ar.bsp\"; | |
5889 | }" | |
52e12ad0 | 5890 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5891 | |
5892 | (define_insn "set_bsp" | |
086c0f96 RH |
5893 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5894 | UNSPECV_SET_BSP)] | |
0c96007e | 5895 | "" |
1d5d7a21 RH |
5896 | "flushrs |
5897 | mov r19=ar.rsc | |
5898 | ;; | |
5899 | and r19=0x1c,r19 | |
5900 | ;; | |
5901 | mov ar.rsc=r19 | |
5902 | ;; | |
5903 | mov ar.bspstore=%0 | |
5904 | ;; | |
5905 | or r19=0x3,r19 | |
5906 | ;; | |
5907 | loadrs | |
5908 | invala | |
5909 | ;; | |
5910 | mov ar.rsc=r19" | |
52e12ad0 | 5911 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5912 | (set_attr "predicable" "no")]) |
ce152ef8 | 5913 | |
0024a804 JW |
5914 | ;; ??? The explicit stops are not ideal. It would be better if |
5915 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5916 | ;; fixed later. This avoids an RSE DV. | |
5917 | ||
ce152ef8 | 5918 | (define_insn "flushrs" |
086c0f96 | 5919 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5920 | "" |
0024a804 | 5921 | ";;\;flushrs\;;;" |
582d11e6 JW |
5922 | [(set_attr "itanium_class" "rse_m") |
5923 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
5924 | \f |
5925 | ;; :::::::::::::::::::: | |
5926 | ;; :: | |
5927 | ;; :: Miscellaneous instructions | |
5928 | ;; :: | |
5929 | ;; :::::::::::::::::::: | |
5930 | ||
839a4992 | 5931 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
5932 | ;; be emitting ";;" to force a break in the instruction packing. |
5933 | ||
5934 | ;; No operation, needed in case the user uses -g but not -O. | |
5935 | (define_insn "nop" | |
5936 | [(const_int 0)] | |
5937 | "" | |
5938 | "nop 0" | |
30028c85 | 5939 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 5940 | |
2130b7fb BS |
5941 | (define_insn "nop_m" |
5942 | [(const_int 1)] | |
5943 | "" | |
5944 | "nop.m 0" | |
5945 | [(set_attr "itanium_class" "nop_m")]) | |
5946 | ||
5947 | (define_insn "nop_i" | |
5948 | [(const_int 2)] | |
5949 | "" | |
5950 | "nop.i 0" | |
5951 | [(set_attr "itanium_class" "nop_i")]) | |
5952 | ||
5953 | (define_insn "nop_f" | |
5954 | [(const_int 3)] | |
5955 | "" | |
5956 | "nop.f 0" | |
5957 | [(set_attr "itanium_class" "nop_f")]) | |
5958 | ||
5959 | (define_insn "nop_b" | |
5960 | [(const_int 4)] | |
5961 | "" | |
5962 | "nop.b 0" | |
5963 | [(set_attr "itanium_class" "nop_b")]) | |
5964 | ||
5965 | (define_insn "nop_x" | |
5966 | [(const_int 5)] | |
5967 | "" | |
5968 | "" | |
fa978426 AS |
5969 | [(set_attr "itanium_class" "nop_x") |
5970 | (set_attr "empty" "yes")]) | |
2130b7fb | 5971 | |
30028c85 VM |
5972 | ;; The following insn will be never generated. It is used only by |
5973 | ;; insn scheduler to change state before advancing cycle. | |
5974 | (define_insn "pre_cycle" | |
5975 | [(const_int 6)] | |
5976 | "" | |
5977 | "" | |
5978 | [(set_attr "itanium_class" "pre_cycle")]) | |
5979 | ||
2130b7fb | 5980 | (define_insn "bundle_selector" |
086c0f96 | 5981 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5982 | "" |
1d5d7a21 | 5983 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5984 | [(set_attr "itanium_class" "ignore") |
5985 | (set_attr "predicable" "no")]) | |
5986 | ||
c65ebc55 JW |
5987 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5988 | ;; point. | |
5989 | (define_insn "blockage" | |
086c0f96 | 5990 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5991 | "" |
5992 | "" | |
52e12ad0 | 5993 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5994 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5995 | |
5996 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5997 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5998 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5999 | "" |
6000 | ";;" | |
52e12ad0 | 6001 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6002 | (set_attr "predicable" "no") |
6003 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6004 | |
26406018 RH |
6005 | (define_expand "trap" |
6006 | [(trap_if (const_int 1) (const_int 0))] | |
6007 | "" | |
6008 | "") | |
6009 | ||
6010 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6011 | ;; produces worse code that setting the slot type to A. | |
6012 | ||
6013 | (define_insn "*trap" | |
6014 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6015 | "" | |
6016 | "break %0" | |
048d0d36 | 6017 | [(set_attr "itanium_class" "chk_s_i")]) |
26406018 RH |
6018 | |
6019 | (define_expand "conditional_trap" | |
6020 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6021 | "" | |
6022 | { | |
6023 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6024 | }) | |
6025 | ||
6026 | (define_insn "*conditional_trap" | |
6027 | [(trap_if (match_operator 0 "predicate_operator" | |
6028 | [(match_operand:BI 1 "register_operand" "c") | |
6029 | (const_int 0)]) | |
6030 | (match_operand 2 "const_int_operand" ""))] | |
6031 | "" | |
5cf63e3f | 6032 | "(%J0) break %2" |
048d0d36 | 6033 | [(set_attr "itanium_class" "chk_s_i") |
26406018 RH |
6034 | (set_attr "predicable" "no")]) |
6035 | ||
f12f25a7 | 6036 | (define_insn "break_f" |
086c0f96 | 6037 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6038 | "" |
6039 | "break.f 0" | |
6040 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6041 | |
6042 | (define_insn "prefetch" | |
6043 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6044 | (match_operand:DI 1 "const_int_operand" "n") | |
6045 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6046 | "" | |
6047 | { | |
6048 | static const char * const alt[2][4] = { | |
b3656137 | 6049 | { |
92cbea22 L |
6050 | "%,lfetch.nta [%0]", |
6051 | "%,lfetch.nt1 [%0]", | |
6052 | "%,lfetch.nt2 [%0]", | |
6053 | "%,lfetch [%0]" | |
b3656137 KG |
6054 | }, |
6055 | { | |
92cbea22 L |
6056 | "%,lfetch.excl.nta [%0]", |
6057 | "%,lfetch.excl.nt1 [%0]", | |
6058 | "%,lfetch.excl.nt2 [%0]", | |
6059 | "%,lfetch.excl [%0]" | |
b3656137 | 6060 | } |
44eca121 JJ |
6061 | }; |
6062 | int i = (INTVAL (operands[1])); | |
6063 | int j = (INTVAL (operands[2])); | |
6064 | ||
e820471b NS |
6065 | gcc_assert (i == 0 || i == 1); |
6066 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
6067 | return alt[i][j]; |
6068 | } | |
6069 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6070 | \f |
6071 | ;; Non-local goto support. | |
6072 | ||
6073 | (define_expand "save_stack_nonlocal" | |
6074 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6075 | (use (match_operand:DI 1 "register_operand" ""))] | |
6076 | "" | |
c65ebc55 JW |
6077 | { |
6078 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6079 | \"__ia64_save_stack_nonlocal\"), | |
bbbbb16a | 6080 | LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode, |
c65ebc55 JW |
6081 | operands[1], Pmode); |
6082 | DONE; | |
1d5d7a21 | 6083 | }) |
c65ebc55 JW |
6084 | |
6085 | (define_expand "nonlocal_goto" | |
6086 | [(use (match_operand 0 "general_operand" "")) | |
6087 | (use (match_operand 1 "general_operand" "")) | |
6088 | (use (match_operand 2 "general_operand" "")) | |
6089 | (use (match_operand 3 "general_operand" ""))] | |
6090 | "" | |
c65ebc55 | 6091 | { |
c65ebc55 | 6092 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6093 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6094 | operands[1], Pmode, |
c65ebc55 | 6095 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6096 | operands[3], Pmode); |
c65ebc55 JW |
6097 | emit_barrier (); |
6098 | DONE; | |
1d5d7a21 | 6099 | }) |
c65ebc55 | 6100 | |
39a5cfa4 SE |
6101 | (define_insn_and_split "nonlocal_goto_receiver" |
6102 | [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)] | |
6103 | "" | |
6104 | "#" | |
6105 | "reload_completed" | |
6106 | [(const_int 0)] | |
6107 | { | |
6108 | ia64_reload_gp (); | |
6109 | DONE; | |
6110 | }) | |
6111 | ||
b39eb2f9 RH |
6112 | (define_insn_and_split "builtin_setjmp_receiver" |
6113 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6114 | "" |
b39eb2f9 RH |
6115 | "#" |
6116 | "reload_completed" | |
6117 | [(const_int 0)] | |
97e242b0 | 6118 | { |
599aedd9 | 6119 | ia64_reload_gp (); |
c65ebc55 | 6120 | DONE; |
1d5d7a21 | 6121 | }) |
c65ebc55 | 6122 | |
0c96007e AM |
6123 | (define_expand "eh_epilogue" |
6124 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6125 | (use (match_operand:DI 1 "register_operand" "r")) | |
6126 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6127 | "" | |
0c96007e AM |
6128 | { |
6129 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6130 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6131 | ||
6132 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6133 | { | |
6134 | emit_move_insn (bsp, operands[0]); | |
6135 | operands[0] = bsp; | |
6136 | } | |
6137 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6138 | { | |
6139 | emit_move_insn (sp, operands[2]); | |
6140 | operands[2] = sp; | |
6141 | } | |
c41c1387 RS |
6142 | emit_use (sp); |
6143 | emit_use (bsp); | |
0c96007e AM |
6144 | |
6145 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6146 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6147 | }) |
9525c690 JW |
6148 | \f |
6149 | ;; Builtin apply support. | |
6150 | ||
6151 | (define_expand "restore_stack_nonlocal" | |
6152 | [(use (match_operand:DI 0 "register_operand" "")) | |
6153 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6154 | "" | |
9525c690 JW |
6155 | { |
6156 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6157 | "__ia64_restore_stack_nonlocal"), |
bbbbb16a | 6158 | LCT_NORMAL, VOIDmode, 1, |
9525c690 JW |
6159 | copy_to_reg (XEXP (operands[1], 0)), Pmode); |
6160 | DONE; | |
1d5d7a21 | 6161 | }) |
9525c690 | 6162 | |
e5bde68a RH |
6163 | \f |
6164 | ;; Predication. | |
6165 | ||
6166 | (define_cond_exec | |
6167 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6168 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6169 | (const_int 0)])] |
6170 | "" | |
6171 | "(%J0)") | |
3b572406 RH |
6172 | |
6173 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6174 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6175 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6176 | "" |
054451ea | 6177 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6178 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6179 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6180 | |
6181 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6182 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6183 | "" |
6184 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6185 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6186 | (set_attr "predicable" "no")]) |
6187 | ||
6188 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6189 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6190 | "" |
ca3920ad | 6191 | { |
1bc7c5b6 | 6192 | emit_safe_across_calls (); |
1d5d7a21 RH |
6193 | return ""; |
6194 | } | |
52e12ad0 | 6195 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6196 | (set_attr "predicable" "no")]) |
6197 | ||
27a9b99d | 6198 | ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit |
6dd12198 SE |
6199 | ;; pointer. This is used by the HP-UX 32 bit mode. |
6200 | ||
6201 | (define_insn "ptr_extend" | |
6202 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6203 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6204 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6205 | "" |
6206 | "addp4 %0 = 0,%1" | |
6207 | [(set_attr "itanium_class" "ialu")]) | |
6208 | ||
e206a74f SE |
6209 | ;; |
6210 | ;; Optimizations for ptr_extend | |
6211 | ||
36c216e5 | 6212 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6213 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6214 | (unspec:DI | |
6215 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6216 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6217 | UNSPEC_ADDP4))] |
08744705 | 6218 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6219 | "addp4 %0 = %2, %1" |
6220 | [(set_attr "itanium_class" "ialu")]) | |
6221 | ||
6222 | (define_insn "*ptr_extend_plus_2" | |
6223 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6224 | (unspec:DI | |
6225 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6226 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6227 | UNSPEC_ADDP4))] |
08744705 | 6228 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6229 | "addp4 %0 = %1, %2" |
6230 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6231 | |
d26afa4f SE |
6232 | ;; |
6233 | ;; Get instruction pointer | |
6234 | ||
6235 | (define_insn "ip_value" | |
6236 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6237 | (pc))] | |
6238 | "" | |
6239 | "mov %0 = ip" | |
6107a6ae | 6240 | [(set_attr "itanium_class" "frbr")]) |
d26afa4f | 6241 | |
f61134e8 RH |
6242 | ;; Vector operations |
6243 | (include "vect.md") | |
af795c3c RH |
6244 | ;; Atomic operations |
6245 | (include "sync.md") | |
4883241c SE |
6246 | ;; New division operations |
6247 | (include "div.md") |