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Commit | Line | Data |
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c65ebc55 | 1 | ;; IA-64 Machine description template |
5b86a469 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 JW |
10 | ;; it under the terms of the GNU General Public License as published by |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
3bed2930 | 20 | ;; along with GCC; see the file COPYING. If not, write to |
39d14dda KC |
21 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
22 | ;; Boston, MA 02110-1301, USA. | |
c65ebc55 JW |
23 | |
24 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
25 | ||
c65ebc55 JW |
26 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
27 | ;; reload. This will be fixed once scheduling support is turned on. | |
28 | ||
29 | ;; ??? Optimize for post-increment addressing modes. | |
30 | ||
31 | ;; ??? fselect is not supported, because there is no integer register | |
32 | ;; equivalent. | |
33 | ||
34 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
35 | ||
36 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
37 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
38 | ||
39 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
40 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
41 | ||
42 | ;; ??? Go through list of documented named patterns and look for more to | |
43 | ;; implement. | |
44 | ||
45 | ;; ??? Go through instruction manual and look for more instructions that | |
46 | ;; can be emitted. | |
47 | ||
48 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
49 | ||
26102535 RH |
50 | ;; ??? Need a better way to describe alternate fp status registers. |
51 | ||
086c0f96 | 52 | (define_constants |
7b6e506e RH |
53 | [; Relocations |
54 | (UNSPEC_LTOFF_DTPMOD 0) | |
55 | (UNSPEC_LTOFF_DTPREL 1) | |
56 | (UNSPEC_DTPREL 2) | |
57 | (UNSPEC_LTOFF_TPREL 3) | |
58 | (UNSPEC_TPREL 4) | |
5e6c8b64 | 59 | (UNSPEC_DTPMOD 5) |
7b6e506e RH |
60 | |
61 | (UNSPEC_LD_BASE 9) | |
62 | (UNSPEC_GR_SPILL 10) | |
63 | (UNSPEC_GR_RESTORE 11) | |
64 | (UNSPEC_FR_SPILL 12) | |
65 | (UNSPEC_FR_RESTORE 13) | |
66 | (UNSPEC_FR_RECIP_APPROX 14) | |
67 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 68 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
69 | (UNSPEC_PIC_CALL 17) |
70 | (UNSPEC_MF 18) | |
71 | (UNSPEC_CMPXCHG_ACQ 19) | |
72 | (UNSPEC_FETCHADD_ACQ 20) | |
73 | (UNSPEC_BSP_VALUE 21) | |
74 | (UNSPEC_FLUSHRS 22) | |
75 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
76 | (UNSPEC_ADDP4 24) |
77 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 78 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
79 | (UNSPEC_SETF_EXP 27) |
80 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 81 | (UNSPEC_SHRP 29) |
046625fa | 82 | (UNSPEC_COPYSIGN 30) |
b4e3537b | 83 | (UNSPEC_VECT_EXTR 31) |
086c0f96 RH |
84 | ]) |
85 | ||
86 | (define_constants | |
87 | [(UNSPECV_ALLOC 0) | |
88 | (UNSPECV_BLOCKAGE 1) | |
89 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
90 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
91 | (UNSPECV_SET_BSP 4) |
92 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
93 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 94 | (UNSPECV_SETJMP_RECEIVER 7) |
086c0f96 | 95 | ]) |
e543e219 | 96 | |
7905f799 | 97 | (include "predicates.md") |
c65ebc55 JW |
98 | \f |
99 | ;; :::::::::::::::::::: | |
100 | ;; :: | |
101 | ;; :: Attributes | |
102 | ;; :: | |
103 | ;; :::::::::::::::::::: | |
104 | ||
30028c85 VM |
105 | ;; Processor type. This attribute must exactly match the processor_type |
106 | ;; enumeration in ia64.h. | |
107 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
108 | ||
c65ebc55 JW |
109 | ;; Instruction type. This primarily determines how instructions can be |
110 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
111 | ||
112 | ;; A alu, can go in I or M syllable of a bundle | |
113 | ;; I integer | |
114 | ;; M memory | |
115 | ;; F floating-point | |
116 | ;; B branch | |
117 | ;; L long immediate, takes two syllables | |
118 | ;; S stop bit | |
119 | ||
120 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
121 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
122 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
123 | ;; which emit instruction that can go in any slot (e.g. nop). | |
124 | ||
1d5d7a21 RH |
125 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
126 | fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld, | |
f61134e8 RH |
127 | chk_s,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf, |
128 | st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop, | |
129 | nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 130 | (const_string "unknown")) |
52e12ad0 | 131 | |
2130b7fb BS |
132 | ;; chk_s has an I and an M form; use type A for convenience. |
133 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
134 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
135 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
136 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 137 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
f61134e8 RH |
138 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog,mmalua") |
139 | (const_string "A") | |
2130b7fb BS |
140 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") |
141 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
142 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
143 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
144 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
145 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 146 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 147 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
148 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
149 | (const_string "unknown"))) | |
c65ebc55 | 150 | |
2130b7fb BS |
151 | (define_attr "itanium_requires_unit0" "no,yes" |
152 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
153 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
154 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
155 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
156 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
157 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
158 | (const_string "no"))) | |
159 | ||
e5bde68a RH |
160 | ;; Predication. True iff this instruction can be predicated. |
161 | ||
162 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
163 | ||
fa978426 AS |
164 | ;; Empty. True iff this insn does not generate any code. |
165 | ||
166 | (define_attr "empty" "no,yes" (const_string "no")) | |
167 | ||
68e11b42 JW |
168 | ;; True iff this insn must be the first insn of an instruction group. |
169 | ;; This is true for the alloc instruction, and will also be true of others | |
170 | ;; when we have full intrinsics support. | |
171 | ||
172 | (define_attr "first_insn" "no,yes" (const_string "no")) | |
c65ebc55 | 173 | \f |
30028c85 VM |
174 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
175 | ;; bundling. | |
176 | ||
177 | (automata_option "ndfa") | |
178 | ||
179 | ;; Uncomment the following line to output automata for debugging. | |
180 | ;; (automata_option "v") | |
181 | ||
182 | (automata_option "w") | |
183 | ||
30028c85 VM |
184 | (include "itanium1.md") |
185 | (include "itanium2.md") | |
186 | ||
c65ebc55 JW |
187 | \f |
188 | ;; :::::::::::::::::::: | |
189 | ;; :: | |
190 | ;; :: Moves | |
191 | ;; :: | |
192 | ;; :::::::::::::::::::: | |
193 | ||
f2f90c63 RH |
194 | ;; Set of a single predicate register. This is only used to implement |
195 | ;; pr-to-pr move and complement. | |
196 | ||
197 | (define_insn "*movcci" | |
198 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
199 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
200 | "" | |
201 | "@ | |
202 | cmp.ne %0, p0 = r0, r0 | |
203 | cmp.eq %0, p0 = r0, r0 | |
204 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 205 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
206 | (set_attr "predicable" "no")]) |
207 | ||
208 | (define_insn "movbi" | |
cd5c4048 RH |
209 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
210 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
211 | "" |
212 | "@ | |
213 | cmp.ne %0, %I0 = r0, r0 | |
214 | cmp.eq %0, %I0 = r0, r0 | |
215 | # | |
216 | # | |
217 | tbit.nz %0, %I0 = %1, 0 | |
218 | adds %0 = %1, r0 | |
219 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
220 | st1%Q0 %0 = %1%P0 |
221 | mov %0 = %1" | |
52e12ad0 | 222 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
223 | |
224 | (define_split | |
225 | [(set (match_operand:BI 0 "register_operand" "") | |
226 | (match_operand:BI 1 "register_operand" ""))] | |
227 | "reload_completed | |
228 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
229 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
230 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
231 | (set (match_dup 0) (const_int 1))) | |
232 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
233 | (set (match_dup 0) (const_int 0)))] | |
234 | "") | |
235 | ||
236 | (define_split | |
237 | [(set (match_operand:BI 0 "register_operand" "") | |
238 | (match_operand:BI 1 "register_operand" ""))] | |
239 | "reload_completed | |
240 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
241 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
242 | [(set (match_dup 2) (match_dup 4)) | |
243 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 244 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
245 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
246 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
247 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
248 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
249 | ||
c65ebc55 JW |
250 | (define_expand "movqi" |
251 | [(set (match_operand:QI 0 "general_operand" "") | |
252 | (match_operand:QI 1 "general_operand" ""))] | |
253 | "" | |
c65ebc55 | 254 | { |
7b6e506e RH |
255 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
256 | if (!op1) | |
257 | DONE; | |
258 | operands[1] = op1; | |
1d5d7a21 | 259 | }) |
c65ebc55 JW |
260 | |
261 | (define_insn "*movqi_internal" | |
4b983fdc RH |
262 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
263 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 264 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 265 | "@ |
13da91fd | 266 | mov %0 = %r1 |
c65ebc55 JW |
267 | addl %0 = %1, r0 |
268 | ld1%O1 %0 = %1%P1 | |
13da91fd | 269 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 270 | getf.sig %0 = %1 |
13da91fd RH |
271 | setf.sig %0 = %r1 |
272 | mov %0 = %1" | |
52e12ad0 | 273 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
274 | |
275 | (define_expand "movhi" | |
276 | [(set (match_operand:HI 0 "general_operand" "") | |
277 | (match_operand:HI 1 "general_operand" ""))] | |
278 | "" | |
c65ebc55 | 279 | { |
7b6e506e RH |
280 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
281 | if (!op1) | |
282 | DONE; | |
283 | operands[1] = op1; | |
1d5d7a21 | 284 | }) |
c65ebc55 JW |
285 | |
286 | (define_insn "*movhi_internal" | |
4b983fdc RH |
287 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
288 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 289 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 290 | "@ |
13da91fd | 291 | mov %0 = %r1 |
c65ebc55 JW |
292 | addl %0 = %1, r0 |
293 | ld2%O1 %0 = %1%P1 | |
13da91fd | 294 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 295 | getf.sig %0 = %1 |
13da91fd RH |
296 | setf.sig %0 = %r1 |
297 | mov %0 = %1" | |
52e12ad0 | 298 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
299 | |
300 | (define_expand "movsi" | |
301 | [(set (match_operand:SI 0 "general_operand" "") | |
302 | (match_operand:SI 1 "general_operand" ""))] | |
303 | "" | |
c65ebc55 | 304 | { |
7b6e506e RH |
305 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
306 | if (!op1) | |
307 | DONE; | |
308 | operands[1] = op1; | |
1d5d7a21 | 309 | }) |
c65ebc55 JW |
310 | |
311 | (define_insn "*movsi_internal" | |
97e242b0 | 312 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 313 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 314 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 315 | "@ |
13da91fd | 316 | mov %0 = %r1 |
c65ebc55 JW |
317 | addl %0 = %1, r0 |
318 | movl %0 = %1 | |
319 | ld4%O1 %0 = %1%P1 | |
13da91fd | 320 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 321 | getf.sig %0 = %1 |
13da91fd | 322 | setf.sig %0 = %r1 |
97e242b0 RH |
323 | mov %0 = %1 |
324 | mov %0 = %1 | |
325 | mov %0 = %r1" | |
1d5d7a21 | 326 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 327 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
328 | |
329 | (define_expand "movdi" | |
330 | [(set (match_operand:DI 0 "general_operand" "") | |
331 | (match_operand:DI 1 "general_operand" ""))] | |
332 | "" | |
c65ebc55 | 333 | { |
7b6e506e RH |
334 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
335 | if (!op1) | |
336 | DONE; | |
337 | operands[1] = op1; | |
1d5d7a21 | 338 | }) |
c65ebc55 | 339 | |
c65ebc55 | 340 | (define_insn "*movdi_internal" |
4b983fdc | 341 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 342 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 343 | (match_operand:DI 1 "move_operand" |
a32767e4 | 344 | "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 345 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
346 | { |
347 | static const char * const alt[] = { | |
1d5d7a21 RH |
348 | "%,mov %0 = %r1", |
349 | "%,addl %0 = %1, r0", | |
350 | "%,movl %0 = %1", | |
351 | "%,ld8%O1 %0 = %1%P1", | |
352 | "%,st8%Q0 %0 = %r1%P0", | |
353 | "%,getf.sig %0 = %1", | |
354 | "%,setf.sig %0 = %r1", | |
355 | "%,mov %0 = %1", | |
356 | "%,ldf8 %0 = %1%P1", | |
357 | "%,stf8 %0 = %1%P0", | |
358 | "%,mov %0 = %1", | |
359 | "%,mov %0 = %r1", | |
360 | "%,mov %0 = %1", | |
361 | "%,mov %0 = %1", | |
362 | "%,mov %0 = %1", | |
363 | "%,mov %0 = %1", | |
364 | "mov %0 = pr", | |
365 | "mov pr = %1, -1" | |
9b7bf67d RH |
366 | }; |
367 | ||
e820471b NS |
368 | gcc_assert (which_alternative != 2 || TARGET_NO_PIC |
369 | || !symbolic_operand (operands[1], VOIDmode)); | |
9b7bf67d RH |
370 | |
371 | return alt[which_alternative]; | |
1d5d7a21 | 372 | } |
52e12ad0 | 373 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 374 | |
9b7bf67d | 375 | (define_split |
21515593 RH |
376 | [(set (match_operand 0 "register_operand" "") |
377 | (match_operand 1 "symbolic_operand" ""))] | |
5e6c8b64 | 378 | "reload_completed" |
9b7bf67d | 379 | [(const_int 0)] |
9b7bf67d | 380 | { |
5e6c8b64 RH |
381 | if (ia64_expand_load_address (operands[0], operands[1])) |
382 | DONE; | |
383 | else | |
384 | FAIL; | |
1d5d7a21 | 385 | }) |
9b7bf67d | 386 | |
c65ebc55 | 387 | (define_expand "load_fptr" |
5e6c8b64 RH |
388 | [(set (match_operand:DI 0 "register_operand" "") |
389 | (plus:DI (match_dup 2) (match_operand 1 "function_operand" ""))) | |
390 | (set (match_dup 0) (match_dup 3))] | |
391 | "reload_completed" | |
c65ebc55 | 392 | { |
5e6c8b64 RH |
393 | operands[2] = pic_offset_table_rtx; |
394 | operands[3] = gen_const_mem (DImode, operands[0]); | |
1d5d7a21 | 395 | }) |
c65ebc55 JW |
396 | |
397 | (define_insn "*load_fptr_internal1" | |
398 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 399 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
5e6c8b64 | 400 | "reload_completed" |
c65ebc55 | 401 | "addl %0 = @ltoff(@fptr(%1)), gp" |
52e12ad0 | 402 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
403 | |
404 | (define_insn "load_gprel" | |
405 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 406 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
5e6c8b64 | 407 | "reload_completed" |
c65ebc55 | 408 | "addl %0 = @gprel(%1), gp" |
52e12ad0 | 409 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 410 | |
5e6c8b64 | 411 | (define_insn "*gprel64_offset" |
59da9a7d JW |
412 | [(set (match_operand:DI 0 "register_operand" "=r") |
413 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
5e6c8b64 | 414 | "reload_completed" |
59da9a7d | 415 | "movl %0 = @gprel(%1)" |
52e12ad0 | 416 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
417 | |
418 | (define_expand "load_gprel64" | |
5e6c8b64 RH |
419 | [(set (match_operand:DI 0 "register_operand" "") |
420 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2))) | |
421 | (set (match_dup 0) | |
422 | (plus:DI (match_dup 2) (match_dup 0)))] | |
423 | "reload_completed" | |
ec039e3c | 424 | { |
5e6c8b64 | 425 | operands[2] = pic_offset_table_rtx; |
1d5d7a21 | 426 | }) |
59da9a7d | 427 | |
af1e5518 RH |
428 | ;; This is used as a placeholder for the return address during early |
429 | ;; compilation. We won't know where we've placed this until during | |
430 | ;; reload, at which point it can wind up in b0, a general register, | |
431 | ;; or memory. The only safe destination under these conditions is a | |
432 | ;; general register. | |
433 | ||
434 | (define_insn_and_split "*movdi_ret_addr" | |
435 | [(set (match_operand:DI 0 "register_operand" "=r") | |
436 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
437 | "" | |
438 | "#" | |
439 | "reload_completed" | |
440 | [(const_int 0)] | |
441 | { | |
442 | ia64_split_return_addr_rtx (operands[0]); | |
443 | DONE; | |
444 | } | |
445 | [(set_attr "itanium_class" "ialu")]) | |
446 | ||
ef1ecf87 | 447 | (define_insn "*load_symptr_high" |
c65ebc55 | 448 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
449 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
450 | (match_operand:DI 2 "register_operand" "a")))] | |
5e6c8b64 | 451 | "reload_completed" |
ef1ecf87 RH |
452 | { |
453 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
454 | return "%,addl %0 = @ltoffx(%1), %2"; | |
455 | else | |
456 | return "%,addl %0 = @ltoff(%1), %2"; | |
457 | } | |
52e12ad0 | 458 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 459 | |
ef1ecf87 RH |
460 | (define_insn "*load_symptr_low" |
461 | [(set (match_operand:DI 0 "register_operand" "=r") | |
462 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
463 | (match_operand 2 "got_symbolic_operand" "s")))] | |
5e6c8b64 | 464 | "reload_completed" |
ef1ecf87 RH |
465 | { |
466 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
467 | return "%,ld8.mov %0 = [%1], %2"; | |
468 | else | |
469 | return "%,ld8 %0 = [%1]"; | |
470 | } | |
471 | [(set_attr "itanium_class" "ld")]) | |
472 | ||
5e6c8b64 | 473 | (define_insn_and_split "load_dtpmod" |
7b6e506e | 474 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 475 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 | 476 | UNSPEC_DTPMOD))] |
7b6e506e | 477 | "" |
5e6c8b64 RH |
478 | "#" |
479 | "reload_completed" | |
480 | [(set (match_dup 0) | |
481 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD) | |
482 | (match_dup 2))) | |
483 | (set (match_dup 0) (match_dup 3))] | |
484 | { | |
485 | operands[2] = pic_offset_table_rtx; | |
486 | operands[3] = gen_const_mem (DImode, operands[0]); | |
487 | }) | |
7b6e506e | 488 | |
5e6c8b64 | 489 | (define_insn "*load_ltoff_dtpmod" |
7b6e506e | 490 | [(set (match_operand:DI 0 "register_operand" "=r") |
5e2b4439 | 491 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
492 | UNSPEC_LTOFF_DTPMOD) |
493 | (match_operand:DI 2 "register_operand" "a")))] | |
494 | "reload_completed" | |
495 | "addl %0 = @ltoff(@dtpmod(%1)), %2" | |
7b6e506e RH |
496 | [(set_attr "itanium_class" "ialu")]) |
497 | ||
498 | (define_expand "load_dtprel" | |
499 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 500 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
501 | UNSPEC_DTPREL))] |
502 | "" | |
503 | "") | |
504 | ||
505 | (define_insn "*load_dtprel64" | |
506 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 507 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
508 | UNSPEC_DTPREL))] |
509 | "TARGET_TLS64" | |
510 | "movl %0 = @dtprel(%1)" | |
511 | [(set_attr "itanium_class" "long_i")]) | |
512 | ||
513 | (define_insn "*load_dtprel22" | |
514 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 515 | (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
7b6e506e RH |
516 | UNSPEC_DTPREL))] |
517 | "" | |
518 | "addl %0 = @dtprel(%1), r0" | |
519 | [(set_attr "itanium_class" "ialu")]) | |
520 | ||
5e6c8b64 RH |
521 | (define_insn_and_split "*load_dtprel_gd" |
522 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 523 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
524 | UNSPEC_DTPREL))] |
525 | "" | |
526 | "#" | |
527 | "reload_completed" | |
528 | [(set (match_dup 0) | |
529 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL) | |
530 | (match_dup 2))) | |
531 | (set (match_dup 0) (match_dup 3))] | |
532 | { | |
533 | operands[2] = pic_offset_table_rtx; | |
534 | operands[3] = gen_const_mem (DImode, operands[0]); | |
535 | }) | |
536 | ||
537 | (define_insn "*load_ltoff_dtprel" | |
538 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 539 | (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
5e6c8b64 RH |
540 | UNSPEC_LTOFF_DTPREL) |
541 | (match_operand:DI 2 "register_operand" "a")))] | |
542 | "" | |
543 | "addl %0 = @ltoff(@dtprel(%1)), %2" | |
544 | [(set_attr "itanium_class" "ialu")]) | |
545 | ||
7b6e506e RH |
546 | (define_expand "add_dtprel" |
547 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 548 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
549 | UNSPEC_DTPREL) |
550 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
551 | "!TARGET_TLS64" |
552 | "") | |
553 | ||
554 | (define_insn "*add_dtprel14" | |
555 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 556 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
557 | UNSPEC_DTPREL) |
558 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 559 | "TARGET_TLS14" |
5e6c8b64 | 560 | "adds %0 = @dtprel(%1), %2" |
7b6e506e RH |
561 | [(set_attr "itanium_class" "ialu")]) |
562 | ||
563 | (define_insn "*add_dtprel22" | |
564 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 565 | (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")] |
5e6c8b64 RH |
566 | UNSPEC_DTPREL) |
567 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 568 | "TARGET_TLS22" |
5e6c8b64 | 569 | "addl %0 = @dtprel(%1), %2" |
7b6e506e RH |
570 | [(set_attr "itanium_class" "ialu")]) |
571 | ||
572 | (define_expand "load_tprel" | |
573 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 574 | (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] |
7b6e506e RH |
575 | UNSPEC_TPREL))] |
576 | "" | |
577 | "") | |
578 | ||
579 | (define_insn "*load_tprel64" | |
580 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 581 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
582 | UNSPEC_TPREL))] |
583 | "TARGET_TLS64" | |
584 | "movl %0 = @tprel(%1)" | |
585 | [(set_attr "itanium_class" "long_i")]) | |
586 | ||
587 | (define_insn "*load_tprel22" | |
588 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 589 | (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
7b6e506e RH |
590 | UNSPEC_TPREL))] |
591 | "" | |
592 | "addl %0 = @tprel(%1), r0" | |
593 | [(set_attr "itanium_class" "ialu")]) | |
594 | ||
5e6c8b64 RH |
595 | (define_insn_and_split "*load_tprel_ie" |
596 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 597 | (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
598 | UNSPEC_TPREL))] |
599 | "" | |
600 | "#" | |
601 | "reload_completed" | |
602 | [(set (match_dup 0) | |
603 | (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL) | |
604 | (match_dup 2))) | |
605 | (set (match_dup 0) (match_dup 3))] | |
606 | { | |
607 | operands[2] = pic_offset_table_rtx; | |
608 | operands[3] = gen_const_mem (DImode, operands[0]); | |
609 | }) | |
610 | ||
611 | (define_insn "*load_ltoff_tprel" | |
612 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 613 | (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")] |
5e6c8b64 RH |
614 | UNSPEC_LTOFF_TPREL) |
615 | (match_operand:DI 2 "register_operand" "a")))] | |
616 | "" | |
617 | "addl %0 = @ltoff(@tprel(%1)), %2" | |
618 | [(set_attr "itanium_class" "ialu")]) | |
619 | ||
7b6e506e RH |
620 | (define_expand "add_tprel" |
621 | [(set (match_operand:DI 0 "register_operand" "") | |
5e2b4439 | 622 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
623 | UNSPEC_TPREL) |
624 | (match_operand:DI 2 "register_operand" "")))] | |
7b6e506e RH |
625 | "!TARGET_TLS64" |
626 | "") | |
627 | ||
628 | (define_insn "*add_tprel14" | |
629 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 630 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
631 | UNSPEC_TPREL) |
632 | (match_operand:DI 2 "register_operand" "r")))] | |
7b6e506e | 633 | "TARGET_TLS14" |
5e6c8b64 | 634 | "adds %0 = @tprel(%1), %2" |
7b6e506e RH |
635 | [(set_attr "itanium_class" "ialu")]) |
636 | ||
637 | (define_insn "*add_tprel22" | |
638 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5e2b4439 | 639 | (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")] |
5e6c8b64 RH |
640 | UNSPEC_TPREL) |
641 | (match_operand:DI 2 "register_operand" "a")))] | |
7b6e506e | 642 | "TARGET_TLS22" |
5e6c8b64 | 643 | "addl %0 = @tprel(%1), %2" |
7b6e506e RH |
644 | [(set_attr "itanium_class" "ialu")]) |
645 | ||
3f622353 | 646 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
647 | ;; around to play with the second word. However, in order to avoid a |
648 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
649 | ;; in ia64_split_tmode_move. | |
3f622353 | 650 | (define_expand "movti" |
2ffe0e02 ZW |
651 | [(set (match_operand:TI 0 "general_operand" "") |
652 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 653 | "" |
3f622353 | 654 | { |
7b6e506e RH |
655 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
656 | if (!op1) | |
657 | DONE; | |
658 | operands[1] = op1; | |
1d5d7a21 | 659 | }) |
3f622353 RH |
660 | |
661 | (define_insn_and_split "*movti_internal" | |
662 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
2ffe0e02 | 663 | (match_operand:TI 1 "general_operand" "ri,m,r"))] |
3f622353 RH |
664 | "ia64_move_ok (operands[0], operands[1])" |
665 | "#" | |
666 | "reload_completed" | |
667 | [(const_int 0)] | |
3f622353 | 668 | { |
f57fc998 | 669 | ia64_split_tmode_move (operands); |
3f622353 | 670 | DONE; |
1d5d7a21 | 671 | } |
52e12ad0 | 672 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
673 | (set_attr "predicable" "no")]) |
674 | ||
c65ebc55 JW |
675 | ;; Floating Point Moves |
676 | ;; | |
677 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 678 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
679 | |
680 | (define_expand "movsf" | |
681 | [(set (match_operand:SF 0 "general_operand" "") | |
682 | (match_operand:SF 1 "general_operand" ""))] | |
683 | "" | |
c65ebc55 | 684 | { |
7b6e506e RH |
685 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
686 | if (!op1) | |
687 | DONE; | |
688 | operands[1] = op1; | |
1d5d7a21 | 689 | }) |
c65ebc55 | 690 | |
c65ebc55 | 691 | (define_insn "*movsf_internal" |
4b983fdc RH |
692 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
693 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 694 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 695 | "@ |
1d5d7a21 RH |
696 | mov %0 = %F1 |
697 | ldfs %0 = %1%P1 | |
698 | stfs %0 = %F1%P0 | |
699 | getf.s %0 = %F1 | |
700 | setf.s %0 = %1 | |
701 | mov %0 = %1 | |
702 | ld4%O1 %0 = %1%P1 | |
703 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 704 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
705 | |
706 | (define_expand "movdf" | |
707 | [(set (match_operand:DF 0 "general_operand" "") | |
708 | (match_operand:DF 1 "general_operand" ""))] | |
709 | "" | |
c65ebc55 | 710 | { |
7b6e506e RH |
711 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
712 | if (!op1) | |
713 | DONE; | |
714 | operands[1] = op1; | |
1d5d7a21 | 715 | }) |
c65ebc55 | 716 | |
c65ebc55 | 717 | (define_insn "*movdf_internal" |
4b983fdc RH |
718 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
719 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 720 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 721 | "@ |
1d5d7a21 RH |
722 | mov %0 = %F1 |
723 | ldfd %0 = %1%P1 | |
724 | stfd %0 = %F1%P0 | |
725 | getf.d %0 = %F1 | |
726 | setf.d %0 = %1 | |
727 | mov %0 = %1 | |
728 | ld8%O1 %0 = %1%P1 | |
729 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 730 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 731 | |
3f622353 RH |
732 | ;; With no offsettable memory references, we've got to have a scratch |
733 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
734 | (define_expand "movxf" |
735 | [(set (match_operand:XF 0 "general_operand" "") | |
736 | (match_operand:XF 1 "general_operand" ""))] | |
737 | "" | |
e5bde68a | 738 | { |
4de67c26 JM |
739 | if (ia64_expand_movxf_movrf (XFmode, operands)) |
740 | DONE; | |
1d5d7a21 | 741 | }) |
e5bde68a | 742 | |
3b572406 | 743 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 744 | |
02befdf4 | 745 | (define_insn "*movxf_internal" |
78d8e0f9 ZW |
746 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
747 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 748 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 749 | "@ |
1d5d7a21 RH |
750 | mov %0 = %F1 |
751 | ldfe %0 = %1%P1 | |
752 | stfe %0 = %F1%P0" | |
52e12ad0 | 753 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
f57fc998 | 754 | |
4de67c26 JM |
755 | ;; Same as for movxf, but for RFmode. |
756 | (define_expand "movrf" | |
757 | [(set (match_operand:RF 0 "general_operand" "") | |
758 | (match_operand:RF 1 "general_operand" ""))] | |
759 | "" | |
760 | { | |
761 | if (ia64_expand_movxf_movrf (RFmode, operands)) | |
762 | DONE; | |
763 | }) | |
764 | ||
765 | (define_insn "*movrf_internal" | |
766 | [(set (match_operand:RF 0 "destination_operand" "=f,f, m") | |
767 | (match_operand:RF 1 "general_operand" "fG,m,fG"))] | |
768 | "ia64_move_ok (operands[0], operands[1])" | |
769 | "@ | |
770 | mov %0 = %F1 | |
771 | ldf.fill %0 = %1%P1 | |
772 | stf.spill %0 = %F1%P0" | |
773 | [(set_attr "itanium_class" "fmisc,fld,stf")]) | |
774 | ||
f57fc998 | 775 | ;; Better code generation via insns that deal with TFmode register pairs |
2ffe0e02 | 776 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 777 | (define_expand "movtf" |
2ffe0e02 ZW |
778 | [(set (match_operand:TF 0 "general_operand" "") |
779 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
780 | "" |
781 | { | |
782 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
783 | if (!op1) | |
784 | DONE; | |
785 | operands[1] = op1; | |
786 | }) | |
787 | ||
788 | (define_insn_and_split "*movtf_internal" | |
e77ee95d | 789 | [(set (match_operand:TF 0 "destination_operand" "=r,r,m") |
2ffe0e02 | 790 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
791 | "ia64_move_ok (operands[0], operands[1])" |
792 | "#" | |
793 | "reload_completed" | |
794 | [(const_int 0)] | |
795 | { | |
796 | ia64_split_tmode_move (operands); | |
797 | DONE; | |
798 | } | |
799 | [(set_attr "itanium_class" "unknown") | |
800 | (set_attr "predicable" "no")]) | |
801 | ||
c65ebc55 JW |
802 | \f |
803 | ;; :::::::::::::::::::: | |
804 | ;; :: | |
805 | ;; :: Conversions | |
806 | ;; :: | |
807 | ;; :::::::::::::::::::: | |
808 | ||
809 | ;; Signed conversions from a smaller integer to a larger integer | |
810 | ||
811 | (define_insn "extendqidi2" | |
0551c32d RH |
812 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
813 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
814 | "" |
815 | "sxt1 %0 = %1" | |
52e12ad0 | 816 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
817 | |
818 | (define_insn "extendhidi2" | |
0551c32d RH |
819 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
820 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
821 | "" |
822 | "sxt2 %0 = %1" | |
52e12ad0 | 823 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
824 | |
825 | (define_insn "extendsidi2" | |
655f2eb9 RH |
826 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
827 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
828 | "" |
829 | "@ | |
830 | sxt4 %0 = %1 | |
aebf2462 | 831 | fsxt.r %0 = %1, %1" |
52e12ad0 | 832 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
833 | |
834 | ;; Unsigned conversions from a smaller integer to a larger integer | |
835 | ||
836 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
837 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
838 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
839 | "" |
840 | "@ | |
841 | zxt1 %0 = %1 | |
842 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 843 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
844 | |
845 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
846 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
847 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
848 | "" |
849 | "@ | |
850 | zxt2 %0 = %1 | |
851 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 852 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
853 | |
854 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 855 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 856 | (zero_extend:DI |
655f2eb9 | 857 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
858 | "" |
859 | "@ | |
d3f6e07b | 860 | addp4 %0 = %1, r0 |
c65ebc55 | 861 | ld4%O1 %0 = %1%P1 |
aebf2462 | 862 | fmix.r %0 = f0, %1" |
d3f6e07b | 863 | [(set_attr "itanium_class" "ialu,ld,fmisc")]) |
c65ebc55 JW |
864 | |
865 | ;; Convert between floating point types of different sizes. | |
866 | ||
640cea5f JW |
867 | ;; At first glance, it would appear that emitting fnorm for an extending |
868 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
869 | ;; correctly only if the input is properly rounded for its type. In | |
870 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
871 | ;; denorm single. Since we don't know what the next instruction will be, we | |
872 | ;; have to emit an fnorm. | |
873 | ||
e8e20f18 RH |
874 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
875 | ;; when we can. Should probably use a scheme like has been proposed | |
876 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
877 | ;; would let combine merge the thing into adjacent insns. See also how the |
878 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
879 | ;; se_register_operand. | |
c65ebc55 | 880 | |
640cea5f JW |
881 | (define_insn "extendsfdf2" |
882 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
883 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 884 | "" |
640cea5f JW |
885 | "fnorm.d %0 = %1" |
886 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 887 | |
02befdf4 ZW |
888 | (define_insn "extendsfxf2" |
889 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
890 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
891 | "" | |
640cea5f JW |
892 | "fnorm %0 = %1" |
893 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 894 | |
02befdf4 ZW |
895 | (define_insn "extenddfxf2" |
896 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
897 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
898 | "" | |
640cea5f JW |
899 | "fnorm %0 = %1" |
900 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 901 | |
c65ebc55 | 902 | (define_insn "truncdfsf2" |
0551c32d RH |
903 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
904 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 905 | "" |
aebf2462 | 906 | "fnorm.s %0 = %1" |
52e12ad0 | 907 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 908 | |
02befdf4 | 909 | (define_insn "truncxfsf2" |
0551c32d | 910 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
911 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
912 | "" | |
aebf2462 | 913 | "fnorm.s %0 = %1" |
52e12ad0 | 914 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 915 | |
02befdf4 | 916 | (define_insn "truncxfdf2" |
0551c32d | 917 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
918 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
919 | "" | |
aebf2462 | 920 | "fnorm.d %0 = %1" |
52e12ad0 | 921 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
922 | |
923 | ;; Convert between signed integer types and floating point. | |
924 | ||
02befdf4 ZW |
925 | (define_insn "floatdixf2" |
926 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
927 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
928 | "" | |
e5bde68a | 929 | "fcvt.xf %0 = %1" |
52e12ad0 | 930 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
931 | |
932 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
933 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
934 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 935 | "" |
aebf2462 | 936 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 937 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
938 | |
939 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
940 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
941 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 942 | "" |
aebf2462 | 943 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 944 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 945 | |
02befdf4 | 946 | (define_insn "fix_truncxfdi2" |
0551c32d | 947 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
948 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
949 | "" | |
aebf2462 | 950 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 951 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 952 | |
02befdf4 | 953 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 954 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 955 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 956 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 957 | "" |
aebf2462 | 958 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 959 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 960 | |
c65ebc55 JW |
961 | ;; Convert between unsigned integer types and floating point. |
962 | ||
963 | (define_insn "floatunsdisf2" | |
0551c32d RH |
964 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
965 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 966 | "" |
aebf2462 | 967 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 968 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
969 | |
970 | (define_insn "floatunsdidf2" | |
0551c32d RH |
971 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
972 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 973 | "" |
aebf2462 | 974 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 975 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 976 | |
02befdf4 ZW |
977 | (define_insn "floatunsdixf2" |
978 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
979 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
980 | "" | |
aebf2462 | 981 | "fcvt.xuf %0 = %1" |
52e12ad0 | 982 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 983 | |
c65ebc55 | 984 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
985 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
986 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 987 | "" |
aebf2462 | 988 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 989 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
990 | |
991 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
992 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
993 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 994 | "" |
aebf2462 | 995 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 996 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 997 | |
02befdf4 | 998 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 999 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1000 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1001 | "" | |
aebf2462 | 1002 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1003 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1004 | |
02befdf4 | 1005 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1006 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1007 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1008 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1009 | "" |
aebf2462 | 1010 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1011 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1012 | \f |
1013 | ;; :::::::::::::::::::: | |
1014 | ;; :: | |
1015 | ;; :: Bit field extraction | |
1016 | ;; :: | |
1017 | ;; :::::::::::::::::::: | |
1018 | ||
c65ebc55 | 1019 | (define_insn "extv" |
0551c32d RH |
1020 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1021 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1022 | (match_operand:DI 2 "const_int_operand" "n") |
1023 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1024 | "" | |
1025 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1026 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1027 | |
1028 | (define_insn "extzv" | |
0551c32d RH |
1029 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1030 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1031 | (match_operand:DI 2 "const_int_operand" "n") |
1032 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1033 | "" | |
1034 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1035 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1036 | |
1037 | ;; Insert a bit field. | |
1038 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1039 | ;; Source1 can be 0 or -1. | |
1040 | ;; Source2 can be 0. | |
1041 | ||
1042 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1043 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1044 | ;; where source2 != dest. | |
1045 | ||
1046 | (define_expand "insv" | |
0551c32d | 1047 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1048 | (match_operand:DI 1 "const_int_operand" "") |
1049 | (match_operand:DI 2 "const_int_operand" "")) | |
1050 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1051 | "" | |
c65ebc55 JW |
1052 | { |
1053 | int width = INTVAL (operands[1]); | |
1054 | int shift = INTVAL (operands[2]); | |
1055 | ||
1056 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1057 | pseudo. */ | |
1058 | if (! register_operand (operands[3], DImode) | |
1059 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1060 | operands[3] = force_reg (DImode, operands[3]); | |
1061 | ||
1062 | /* If this is a single dep instruction, we have nothing to do. */ | |
1063 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1064 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1065 | { | |
1066 | /* Check for cases that can be implemented with a mix instruction. */ | |
1067 | if (width == 32 && shift == 0) | |
1068 | { | |
1069 | /* Directly generating the mix4left instruction confuses | |
1070 | optimize_bit_field in function.c. Since this is performing | |
1071 | a useful optimization, we defer generation of the complicated | |
1072 | mix4left RTL to the first splitting phase. */ | |
1073 | rtx tmp = gen_reg_rtx (DImode); | |
1074 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1075 | DONE; | |
1076 | } | |
1077 | else if (width == 32 && shift == 32) | |
1078 | { | |
1079 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1080 | DONE; | |
1081 | } | |
1082 | ||
d2ba6dcf JW |
1083 | /* We could handle remaining cases by emitting multiple dep |
1084 | instructions. | |
1085 | ||
1086 | If we need more than two dep instructions then we lose. A 6 | |
1087 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1088 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1089 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1090 | only one function unit that can execute dep and shr immed. | |
1091 | ||
1092 | If we only need two dep instruction, then we still lose. | |
1093 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1094 | the unnecessary mov, this is still undesirable because it will be | |
1095 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1096 | function unit. */ | |
1097 | ||
c65ebc55 JW |
1098 | FAIL; |
1099 | ||
1100 | #if 0 | |
1101 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1102 | for now. */ | |
1103 | while (width > 16) | |
1104 | { | |
1105 | rtx tmp; | |
1106 | ||
1107 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1108 | operands[3])); | |
1109 | shift += 16; | |
1110 | width -= 16; | |
1111 | tmp = gen_reg_rtx (DImode); | |
1112 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1113 | operands[3] = tmp; | |
1114 | } | |
1115 | operands[1] = GEN_INT (width); | |
1116 | operands[2] = GEN_INT (shift); | |
1117 | #endif | |
1118 | } | |
1d5d7a21 | 1119 | }) |
c65ebc55 JW |
1120 | |
1121 | (define_insn "*insv_internal" | |
0551c32d | 1122 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1123 | (match_operand:DI 1 "const_int_operand" "n") |
1124 | (match_operand:DI 2 "const_int_operand" "n")) | |
1125 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1126 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1127 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1128 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1129 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1130 | |
43a88a8c | 1131 | ;; Combine doesn't like to create bit-field insertions into zero. |
d3f6e07b JB |
1132 | (define_insn "*shladdp4_internal" |
1133 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
1134 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1135 | (match_operand:DI 2 "shladd_log2_operand" "n")) | |
1136 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1137 | "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32" | |
1138 | "shladdp4 %0 = %1, %2, r0" | |
1139 | [(set_attr "itanium_class" "ialu")]) | |
1140 | ||
041f25e6 | 1141 | (define_insn "*depz_internal" |
0551c32d RH |
1142 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1143 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1144 | (match_operand:DI 2 "const_int_operand" "n")) |
1145 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1146 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1147 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
041f25e6 RH |
1148 | { |
1149 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1150 | return "%,dep.z %0 = %1, %2, %3"; |
1151 | } | |
52e12ad0 | 1152 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1153 | |
c65ebc55 | 1154 | (define_insn "shift_mix4left" |
0551c32d | 1155 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1156 | (const_int 32) (const_int 0)) |
0551c32d RH |
1157 | (match_operand:DI 1 "gr_register_operand" "r")) |
1158 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1159 | "" |
1160 | "#" | |
52e12ad0 | 1161 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1162 | |
c65ebc55 JW |
1163 | (define_split |
1164 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1165 | (const_int 32) (const_int 0)) | |
1166 | (match_operand:DI 1 "register_operand" "")) | |
1167 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1168 | "" |
c65ebc55 JW |
1169 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1170 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1171 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1172 | "operands[3] = operands[2];") | |
1173 | ||
1174 | (define_insn "*mix4left" | |
0551c32d | 1175 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1176 | (const_int 32) (const_int 0)) |
0551c32d | 1177 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1178 | (const_int 32)))] |
1179 | "" | |
1180 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1181 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1182 | |
1183 | (define_insn "mix4right" | |
0551c32d | 1184 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1185 | (const_int 32) (const_int 32)) |
0551c32d | 1186 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1187 | "" |
1188 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1189 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1190 | |
1191 | ;; This is used by the rotrsi3 pattern. | |
1192 | ||
1193 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1194 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1195 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1196 | (ashift:DI (zero_extend:DI | |
1197 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1198 | (const_int 32))))] |
1199 | "" | |
fa9a44e8 | 1200 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1201 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1202 | |
1203 | \f | |
1204 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1205 | ;; :: |
f2f90c63 RH |
1206 | ;; :: 1 bit Integer arithmetic |
1207 | ;; :: | |
1208 | ;; :::::::::::::::::::: | |
1209 | ||
1210 | (define_insn_and_split "andbi3" | |
1211 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1212 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1213 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1214 | "" | |
1215 | "@ | |
1216 | # | |
1217 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1218 | and %0 = %2, %1" | |
1219 | "reload_completed | |
1220 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1221 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1222 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1223 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1224 | (match_dup 0))))] | |
1225 | "" | |
52e12ad0 | 1226 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1227 | |
1228 | (define_insn_and_split "*andcmbi3" | |
1229 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1230 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1231 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1232 | "" | |
1233 | "@ | |
1234 | # | |
967603ef | 1235 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1236 | andcm %0 = %2, %1" |
1237 | "reload_completed | |
1238 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1239 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1240 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1241 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1242 | (match_dup 0))))] | |
1243 | "" | |
52e12ad0 | 1244 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1245 | |
1246 | (define_insn_and_split "iorbi3" | |
1247 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1248 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1249 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1250 | "" | |
1251 | "@ | |
1252 | # | |
1253 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1254 | or %0 = %2, %1" | |
1255 | "reload_completed | |
1256 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1257 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1258 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1259 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1260 | (match_dup 0))))] | |
1261 | "" | |
52e12ad0 | 1262 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1263 | |
1264 | (define_insn_and_split "*iorcmbi3" | |
1265 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1266 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1267 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1268 | "" | |
1269 | "@ | |
1270 | # | |
967603ef | 1271 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1272 | "reload_completed |
1273 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1274 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1275 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1276 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1277 | (match_dup 0))))] | |
1278 | "" | |
52e12ad0 | 1279 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1280 | |
1281 | (define_insn "one_cmplbi2" | |
1282 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1283 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1284 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1285 | "" | |
1286 | "@ | |
1287 | tbit.z %0, %I0 = %1, 0 | |
1288 | xor %0 = 1, %1 | |
1289 | # | |
1290 | #" | |
52e12ad0 | 1291 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1292 | |
1293 | (define_split | |
1294 | [(set (match_operand:BI 0 "register_operand" "") | |
1295 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1296 | (clobber (match_scratch:BI 2 ""))] | |
1297 | "reload_completed | |
1298 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1299 | && rtx_equal_p (operands[0], operands[1])" |
1300 | [(set (match_dup 4) (match_dup 3)) | |
1301 | (set (match_dup 0) (const_int 1)) | |
1302 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1303 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1304 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1305 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1306 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1307 | ||
1308 | (define_split | |
1309 | [(set (match_operand:BI 0 "register_operand" "") | |
1310 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1311 | (clobber (match_scratch:BI 2 ""))] | |
1312 | "reload_completed | |
1313 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1314 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1315 | && ! rtx_equal_p (operands[0], operands[1])" | |
1316 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1317 | (set (match_dup 0) (const_int 0))) | |
1318 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1319 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1320 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1321 | "") |
1322 | ||
1323 | (define_insn "*cmpsi_and_0" | |
1324 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1325 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1326 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1327 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1328 | (match_operand:BI 1 "register_operand" "0")))] | |
1329 | "" | |
1330 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1331 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1332 | |
1333 | (define_insn "*cmpsi_and_1" | |
1334 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1335 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1336 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1337 | (const_int 0)]) | |
1338 | (match_operand:BI 1 "register_operand" "0")))] | |
1339 | "" | |
1340 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1341 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1342 | |
1343 | (define_insn "*cmpsi_andnot_0" | |
1344 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1345 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1346 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1347 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1348 | (match_operand:BI 1 "register_operand" "0")))] | |
1349 | "" | |
1350 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1351 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1352 | |
1353 | (define_insn "*cmpsi_andnot_1" | |
1354 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1355 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1356 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1357 | (const_int 0)])) | |
1358 | (match_operand:BI 1 "register_operand" "0")))] | |
1359 | "" | |
1360 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1361 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1362 | |
1363 | (define_insn "*cmpdi_and_0" | |
1364 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1365 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1366 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1367 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1368 | (match_operand:BI 1 "register_operand" "0")))] | |
1369 | "" | |
1370 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1371 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1372 | |
1373 | (define_insn "*cmpdi_and_1" | |
1374 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1375 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1376 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1377 | (const_int 0)]) | |
1378 | (match_operand:BI 1 "register_operand" "0")))] | |
1379 | "" | |
1380 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1381 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1382 | |
1383 | (define_insn "*cmpdi_andnot_0" | |
1384 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1385 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1386 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1387 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1388 | (match_operand:BI 1 "register_operand" "0")))] | |
1389 | "" | |
1390 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1391 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1392 | |
1393 | (define_insn "*cmpdi_andnot_1" | |
1394 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1395 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1396 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1397 | (const_int 0)])) | |
1398 | (match_operand:BI 1 "register_operand" "0")))] | |
1399 | "" | |
1400 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1401 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1402 | |
1403 | (define_insn "*tbit_and_0" | |
1404 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1405 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1406 | (const_int 1)) | |
1407 | (const_int 0)) | |
c77e04ae | 1408 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1409 | "" |
1410 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1411 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1412 | |
1413 | (define_insn "*tbit_and_1" | |
1414 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1415 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1416 | (const_int 1)) | |
1417 | (const_int 0)) | |
c77e04ae | 1418 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1419 | "" |
1420 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1421 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1422 | |
1423 | (define_insn "*tbit_and_2" | |
1424 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1425 | (and:BI (ne:BI (zero_extract:DI | |
1426 | (match_operand:DI 1 "gr_register_operand" "r") | |
1427 | (const_int 1) | |
1428 | (match_operand:DI 2 "const_int_operand" "n")) | |
1429 | (const_int 0)) | |
1430 | (match_operand:BI 3 "register_operand" "0")))] | |
1431 | "" | |
1432 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1433 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1434 | |
1435 | (define_insn "*tbit_and_3" | |
1436 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1437 | (and:BI (eq:BI (zero_extract:DI | |
1438 | (match_operand:DI 1 "gr_register_operand" "r") | |
1439 | (const_int 1) | |
1440 | (match_operand:DI 2 "const_int_operand" "n")) | |
1441 | (const_int 0)) | |
1442 | (match_operand:BI 3 "register_operand" "0")))] | |
1443 | "" | |
1444 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1445 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1446 | |
1447 | (define_insn "*cmpsi_or_0" | |
1448 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1449 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1450 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1451 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1452 | (match_operand:BI 1 "register_operand" "0")))] | |
1453 | "" | |
1454 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1455 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1456 | |
1457 | (define_insn "*cmpsi_or_1" | |
1458 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1459 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1460 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1461 | (const_int 0)]) | |
1462 | (match_operand:BI 1 "register_operand" "0")))] | |
1463 | "" | |
1464 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1465 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1466 | |
1467 | (define_insn "*cmpsi_orcm_0" | |
1468 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1469 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1470 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1471 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1472 | (match_operand:BI 1 "register_operand" "0")))] | |
1473 | "" | |
1474 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1475 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1476 | |
1477 | (define_insn "*cmpsi_orcm_1" | |
1478 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1479 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1480 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1481 | (const_int 0)])) | |
1482 | (match_operand:BI 1 "register_operand" "0")))] | |
1483 | "" | |
1484 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1485 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1486 | |
1487 | (define_insn "*cmpdi_or_0" | |
1488 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1489 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1490 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1491 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1492 | (match_operand:BI 1 "register_operand" "0")))] | |
1493 | "" | |
1494 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1495 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1496 | |
1497 | (define_insn "*cmpdi_or_1" | |
1498 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1499 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1500 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1501 | (const_int 0)]) | |
1502 | (match_operand:BI 1 "register_operand" "0")))] | |
1503 | "" | |
1504 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1505 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1506 | |
1507 | (define_insn "*cmpdi_orcm_0" | |
1508 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1509 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1510 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1511 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1512 | (match_operand:BI 1 "register_operand" "0")))] | |
1513 | "" | |
1514 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1515 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1516 | |
1517 | (define_insn "*cmpdi_orcm_1" | |
1518 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1519 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1520 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1521 | (const_int 0)])) | |
1522 | (match_operand:BI 1 "register_operand" "0")))] | |
1523 | "" | |
1524 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1525 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1526 | |
1527 | (define_insn "*tbit_or_0" | |
1528 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1529 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1530 | (const_int 1)) | |
1531 | (const_int 0)) | |
c77e04ae | 1532 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1533 | "" |
1534 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1535 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1536 | |
1537 | (define_insn "*tbit_or_1" | |
1538 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1539 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1540 | (const_int 1)) | |
1541 | (const_int 0)) | |
c77e04ae | 1542 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1543 | "" |
1544 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1545 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1546 | |
1547 | (define_insn "*tbit_or_2" | |
1548 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1549 | (ior:BI (ne:BI (zero_extract:DI | |
1550 | (match_operand:DI 1 "gr_register_operand" "r") | |
1551 | (const_int 1) | |
1552 | (match_operand:DI 2 "const_int_operand" "n")) | |
1553 | (const_int 0)) | |
1554 | (match_operand:BI 3 "register_operand" "0")))] | |
1555 | "" | |
1556 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1557 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1558 | |
1559 | (define_insn "*tbit_or_3" | |
1560 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1561 | (ior:BI (eq:BI (zero_extract:DI | |
1562 | (match_operand:DI 1 "gr_register_operand" "r") | |
1563 | (const_int 1) | |
1564 | (match_operand:DI 2 "const_int_operand" "n")) | |
1565 | (const_int 0)) | |
1566 | (match_operand:BI 3 "register_operand" "0")))] | |
1567 | "" | |
1568 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1569 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1570 | |
1571 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1572 | ||
1573 | (define_split | |
1574 | [(set (match_operand:BI 0 "register_operand" "") | |
1575 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1576 | (const_int 0)) | |
1577 | (match_operand:DI 3 "register_operand" "")) | |
1578 | (const_int 0)))] | |
1579 | "" | |
1580 | [(set (match_dup 0) | |
1581 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1582 | (match_dup 2)))] | |
1583 | "") | |
1584 | ||
1585 | (define_split | |
1586 | [(set (match_operand:BI 0 "register_operand" "") | |
1587 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1588 | (const_int 0)) | |
1589 | (match_operand:DI 3 "register_operand" "")) | |
1590 | (const_int 0)))] | |
1591 | "" | |
1592 | [(set (match_dup 0) | |
1593 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1594 | (match_dup 2))) | |
1595 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1596 | (clobber (scratch))])] | |
1597 | "") | |
1598 | ||
1599 | (define_split | |
1600 | [(set (match_operand:BI 0 "register_operand" "") | |
1601 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1602 | (const_int 0)) | |
1603 | (match_operand:DI 3 "register_operand" "")) | |
1604 | (const_int 0)))] | |
1605 | "" | |
1606 | [(set (match_dup 0) | |
1607 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1608 | (match_dup 2)))] | |
1609 | "") | |
1610 | ||
1611 | (define_split | |
1612 | [(set (match_operand:BI 0 "register_operand" "") | |
1613 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1614 | (const_int 0)) | |
1615 | (match_operand:DI 3 "register_operand" "")) | |
1616 | (const_int 0)))] | |
1617 | "" | |
1618 | [(set (match_dup 0) | |
1619 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1620 | (match_dup 2))) | |
1621 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1622 | (clobber (scratch))])] | |
1623 | "") | |
1624 | ||
1625 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1626 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1627 | ;; nothing bad happens to the comparisons in the meantime. | |
1628 | ;; | |
1629 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1630 | ;; that we're doing height reduction. | |
1631 | ; | |
1632 | ;(define_insn_and_split "" | |
1633 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1634 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1635 | ; [(match_operand 2 "" "") | |
1636 | ; (match_operand 3 "" "")]) | |
1637 | ; (match_operator:BI 4 "comparison_operator" | |
1638 | ; [(match_operand 5 "" "") | |
1639 | ; (match_operand 6 "" "")])) | |
1640 | ; (match_dup 0)))] | |
1641 | ; "flag_schedule_insns" | |
1642 | ; "#" | |
1643 | ; "" | |
1644 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1645 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1646 | ; "") | |
1647 | ; | |
1648 | ;(define_insn_and_split "" | |
1649 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1650 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1651 | ; [(match_operand 2 "" "") | |
1652 | ; (match_operand 3 "" "")]) | |
1653 | ; (match_operator:BI 4 "comparison_operator" | |
1654 | ; [(match_operand 5 "" "") | |
1655 | ; (match_operand 6 "" "")])) | |
1656 | ; (match_dup 0)))] | |
1657 | ; "flag_schedule_insns" | |
1658 | ; "#" | |
1659 | ; "" | |
1660 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1661 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1662 | ; "") | |
1663 | ; | |
1664 | ;(define_split | |
1665 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1666 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1667 | ; [(match_operand 2 "" "") | |
1668 | ; (match_operand 3 "" "")]) | |
1669 | ; (match_operand:BI 7 "register_operand" "")) | |
1670 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1671 | ; [(match_operand 5 "" "") | |
1672 | ; (match_operand 6 "" "")]) | |
1673 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1674 | ; "" | |
1675 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1676 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1677 | ; (match_dup 0)))] | |
1678 | ; "") | |
1679 | ; | |
1680 | ;(define_split | |
1681 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1682 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1683 | ; [(match_operand 2 "" "") | |
1684 | ; (match_operand 3 "" "")]) | |
1685 | ; (match_operand:BI 7 "register_operand" "")) | |
1686 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1687 | ; [(match_operand 5 "" "") | |
1688 | ; (match_operand 6 "" "")]) | |
1689 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1690 | ; "" | |
1691 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1692 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1693 | ; (match_dup 0)))] | |
1694 | ; "") | |
1695 | ||
1696 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1697 | ;; Note that we'll have already split the predicate copy, which | |
1698 | ;; is kind of a pain, but oh well. | |
1699 | ||
1700 | (define_peephole2 | |
1701 | [(set (match_operand:BI 0 "register_operand" "") | |
1702 | (match_operand:BI 1 "comparison_operator" "")) | |
1703 | (set (match_operand:CCI 2 "register_operand" "") | |
1704 | (match_operand:CCI 3 "register_operand" "")) | |
1705 | (set (match_operand:CCI 4 "register_operand" "") | |
1706 | (match_operand:CCI 5 "register_operand" "")) | |
1707 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 1708 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1709 | "REGNO (operands[3]) == REGNO (operands[0]) |
1710 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1711 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1712 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1713 | [(set (match_dup 0) (match_dup 1)) | |
1714 | (set (match_dup 6) (match_dup 7))] | |
1715 | "operands[7] = copy_rtx (operands[1]);") | |
1716 | \f | |
1717 | ;; :::::::::::::::::::: | |
1718 | ;; :: | |
cf1f6ae3 RH |
1719 | ;; :: 16 bit Integer arithmetic |
1720 | ;; :: | |
1721 | ;; :::::::::::::::::::: | |
1722 | ||
1723 | (define_insn "mulhi3" | |
1724 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1725 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1726 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1727 | "" | |
2a7ffc85 | 1728 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1729 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1730 | |
1731 | \f | |
1732 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1733 | ;; :: |
1734 | ;; :: 32 bit Integer arithmetic | |
1735 | ;; :: | |
1736 | ;; :::::::::::::::::::: | |
1737 | ||
058557c4 | 1738 | (define_insn "addsi3" |
0551c32d RH |
1739 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1740 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1741 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1742 | "" |
1743 | "@ | |
1d5d7a21 RH |
1744 | add %0 = %1, %2 |
1745 | adds %0 = %2, %1 | |
1746 | addl %0 = %2, %1" | |
52e12ad0 | 1747 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1748 | |
1749 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1750 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1751 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1752 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1753 | (const_int 1)))] |
1754 | "" | |
1755 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1756 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1757 | |
5527bf14 | 1758 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1759 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1760 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1761 | (const_int 2)) |
1762 | (const_int 1)))] | |
1763 | "" | |
1764 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1765 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1766 | |
058557c4 | 1767 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1768 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1769 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1770 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1771 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1772 | "" |
058557c4 | 1773 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1774 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1775 | |
058557c4 | 1776 | (define_insn "subsi3" |
0551c32d RH |
1777 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1778 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1779 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1780 | "" |
1781 | "sub %0 = %1, %2" | |
52e12ad0 | 1782 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1783 | |
1784 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1785 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1786 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1787 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1788 | "" |
1789 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1790 | [(set_attr "itanium_class" "ialu")]) |
1791 | ||
1792 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1793 | |
058557c4 | 1794 | (define_insn "mulsi3" |
0551c32d | 1795 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1796 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1797 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1798 | "" |
aebf2462 | 1799 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1800 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1801 | |
655f2eb9 | 1802 | (define_insn "maddsi4" |
11a13704 RH |
1803 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1804 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1805 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1806 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1807 | "" | |
aebf2462 | 1808 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1809 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1810 | |
058557c4 | 1811 | (define_insn "negsi2" |
0551c32d RH |
1812 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1813 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1814 | "" |
1815 | "sub %0 = r0, %1" | |
52e12ad0 | 1816 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1817 | |
1818 | (define_expand "abssi2" | |
1819 | [(set (match_dup 2) | |
f2f90c63 | 1820 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1821 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1822 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1823 | (neg:SI (match_dup 1)) |
1824 | (match_dup 1)))] | |
c65ebc55 | 1825 | "" |
1d5d7a21 | 1826 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1827 | |
1828 | (define_expand "sminsi3" | |
1829 | [(set (match_dup 3) | |
f2f90c63 | 1830 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1831 | (match_operand:SI 2 "gr_register_operand" ""))) |
1832 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1833 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1834 | (match_dup 2) (match_dup 1)))] |
1835 | "" | |
1d5d7a21 | 1836 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1837 | |
1838 | (define_expand "smaxsi3" | |
1839 | [(set (match_dup 3) | |
f2f90c63 | 1840 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1841 | (match_operand:SI 2 "gr_register_operand" ""))) |
1842 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1843 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1844 | (match_dup 1) (match_dup 2)))] |
1845 | "" | |
1d5d7a21 | 1846 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1847 | |
1848 | (define_expand "uminsi3" | |
1849 | [(set (match_dup 3) | |
f2f90c63 | 1850 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1851 | (match_operand:SI 2 "gr_register_operand" ""))) |
1852 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1853 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1854 | (match_dup 2) (match_dup 1)))] |
1855 | "" | |
1d5d7a21 | 1856 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
1857 | |
1858 | (define_expand "umaxsi3" | |
1859 | [(set (match_dup 3) | |
f2f90c63 | 1860 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1861 | (match_operand:SI 2 "gr_register_operand" ""))) |
1862 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1863 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1864 | (match_dup 1) (match_dup 2)))] |
1865 | "" | |
1d5d7a21 | 1866 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 1867 | |
655f2eb9 RH |
1868 | (define_expand "divsi3" |
1869 | [(set (match_operand:SI 0 "register_operand" "") | |
1870 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1871 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1872 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 1873 | { |
9aec7fb4 | 1874 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 1875 | |
02befdf4 | 1876 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
1877 | op0_di = gen_reg_rtx (DImode); |
1878 | ||
1879 | if (CONSTANT_P (operands[1])) | |
1880 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
1881 | op1_xf = gen_reg_rtx (XFmode); |
1882 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
1883 | |
1884 | if (CONSTANT_P (operands[2])) | |
1885 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
1886 | op2_xf = gen_reg_rtx (XFmode); |
1887 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
1888 | |
1889 | /* 2^-34 */ | |
9aec7fb4 SE |
1890 | twon34_exp = gen_reg_rtx (DImode); |
1891 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
1892 | twon34 = gen_reg_rtx (XFmode); | |
1893 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 1894 | |
02befdf4 | 1895 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 1896 | |
02befdf4 | 1897 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
1898 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
1899 | DONE; | |
1d5d7a21 | 1900 | }) |
655f2eb9 RH |
1901 | |
1902 | (define_expand "modsi3" | |
1903 | [(set (match_operand:SI 0 "register_operand" "") | |
1904 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
1905 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1906 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
1907 | { |
1908 | rtx op2_neg, op1_di, div; | |
1909 | ||
1910 | div = gen_reg_rtx (SImode); | |
1911 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
1912 | ||
1913 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1914 | ||
1915 | /* This is a trick to get us to reuse the value that we're sure to | |
1916 | have already copied to the FP regs. */ | |
1917 | op1_di = gen_reg_rtx (DImode); | |
1918 | convert_move (op1_di, operands[1], 0); | |
1919 | ||
1920 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1921 | gen_lowpart (SImode, op1_di))); | |
1922 | DONE; | |
1d5d7a21 | 1923 | }) |
655f2eb9 RH |
1924 | |
1925 | (define_expand "udivsi3" | |
1926 | [(set (match_operand:SI 0 "register_operand" "") | |
1927 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
1928 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1929 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 1930 | { |
9aec7fb4 | 1931 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 1932 | |
02befdf4 | 1933 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
1934 | op0_di = gen_reg_rtx (DImode); |
1935 | ||
1936 | if (CONSTANT_P (operands[1])) | |
1937 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
1938 | op1_xf = gen_reg_rtx (XFmode); |
1939 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
1940 | |
1941 | if (CONSTANT_P (operands[2])) | |
1942 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
1943 | op2_xf = gen_reg_rtx (XFmode); |
1944 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
1945 | |
1946 | /* 2^-34 */ | |
9aec7fb4 SE |
1947 | twon34_exp = gen_reg_rtx (DImode); |
1948 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
1949 | twon34 = gen_reg_rtx (XFmode); | |
1950 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 1951 | |
02befdf4 | 1952 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 1953 | |
02befdf4 | 1954 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
1955 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
1956 | DONE; | |
1d5d7a21 | 1957 | }) |
655f2eb9 RH |
1958 | |
1959 | (define_expand "umodsi3" | |
1960 | [(set (match_operand:SI 0 "register_operand" "") | |
1961 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
1962 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 1963 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
1964 | { |
1965 | rtx op2_neg, op1_di, div; | |
1966 | ||
1967 | div = gen_reg_rtx (SImode); | |
1968 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
1969 | ||
1970 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1971 | ||
1972 | /* This is a trick to get us to reuse the value that we're sure to | |
1973 | have already copied to the FP regs. */ | |
1974 | op1_di = gen_reg_rtx (DImode); | |
1975 | convert_move (op1_di, operands[1], 1); | |
1976 | ||
1977 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1978 | gen_lowpart (SImode, op1_di))); | |
1979 | DONE; | |
1d5d7a21 | 1980 | }) |
655f2eb9 RH |
1981 | |
1982 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
1983 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
1984 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
1985 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
1986 | (clobber (match_scratch:XF 4 "=&f")) | |
1987 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 1988 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
1989 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
1990 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
1991 | "#" |
1992 | "&& reload_completed" | |
02befdf4 | 1993 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
1994 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
1995 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
1996 | (use (const_int 1))]) |
1997 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 1998 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
1999 | (use (const_int 1))])) |
2000 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2001 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2002 | (minus:XF (match_dup 7) |
2003 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2004 | (use (const_int 1))])) |
2005 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2006 | (parallel [(set (match_dup 4) | |
02befdf4 | 2007 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2008 | (match_dup 4))) |
2009 | (use (const_int 1))])) | |
2010 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2011 | (parallel [(set (match_dup 5) | |
02befdf4 | 2012 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2013 | (match_dup 3))) |
2014 | (use (const_int 1))])) | |
2015 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2016 | (parallel [(set (match_dup 0) | |
02befdf4 | 2017 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2018 | (match_dup 4))) |
2019 | (use (const_int 1))])) | |
2020 | ] | |
02befdf4 | 2021 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2022 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2023 | \f |
2024 | ;; :::::::::::::::::::: | |
2025 | ;; :: | |
2026 | ;; :: 64 bit Integer arithmetic | |
2027 | ;; :: | |
2028 | ;; :::::::::::::::::::: | |
2029 | ||
2030 | (define_insn "adddi3" | |
0551c32d RH |
2031 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2032 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2033 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2034 | "" |
2035 | "@ | |
1d5d7a21 RH |
2036 | add %0 = %1, %2 |
2037 | adds %0 = %2, %1 | |
2038 | addl %0 = %2, %1" | |
52e12ad0 | 2039 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2040 | |
2041 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2042 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2043 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2044 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2045 | (const_int 1)))] |
2046 | "" | |
2047 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2048 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2049 | |
5527bf14 RH |
2050 | ;; This has some of the same problems as shladd. We let the shladd |
2051 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2052 | ;; a register, but not more ugliness here. | |
2053 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2054 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2055 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2056 | (const_int 2)) |
2057 | (const_int 1)))] | |
2058 | "" | |
2059 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2060 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2061 | |
c65ebc55 | 2062 | (define_insn "subdi3" |
0551c32d RH |
2063 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2064 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2065 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2066 | "" |
2067 | "sub %0 = %1, %2" | |
52e12ad0 | 2068 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2069 | |
2070 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2071 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2072 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2073 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2074 | "" |
2075 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2076 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2077 | |
cee58bc0 RH |
2078 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2079 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2080 | (define_insn "muldi3" |
0551c32d | 2081 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2082 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2083 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2084 | "" |
aebf2462 | 2085 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2086 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2087 | |
2088 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2089 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2090 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2091 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2092 | ;; here so that it will be present just in case register elimination gives us | |
2093 | ;; the funny result. | |
2094 | ||
2095 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2096 | ||
2097 | ;; ??? Maybe we should change how adds are canonicalized. | |
2098 | ||
655f2eb9 | 2099 | (define_insn "madddi4" |
0551c32d | 2100 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2101 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2102 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2103 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2104 | (clobber (match_scratch:DI 4 "=X"))] |
2105 | "" | |
aebf2462 | 2106 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2107 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2108 | |
2109 | ;; This can be created by register elimination if operand3 of shladd is an | |
2110 | ;; eliminable register or has reg_equiv_constant set. | |
2111 | ||
2112 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2113 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2114 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2115 | ;; incorrectly. |
2116 | ||
655f2eb9 | 2117 | (define_insn "*madddi4_elim" |
c65ebc55 | 2118 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2119 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2120 | (match_operand:DI 2 "register_operand" "f")) | |
2121 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2122 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2123 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2124 | "reload_in_progress" |
2125 | "#" | |
52e12ad0 | 2126 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2127 | |
c65ebc55 JW |
2128 | (define_split |
2129 | [(set (match_operand:DI 0 "register_operand" "") | |
2130 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2131 | (match_operand:DI 2 "register_operand" "")) | |
2132 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2133 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2134 | (clobber (match_scratch:DI 5 ""))] |
2135 | "reload_completed" | |
2136 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2137 | (match_dup 3))) | |
2138 | (clobber (match_dup 0))]) | |
c65ebc55 | 2139 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2140 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2141 | "") | |
2142 | ||
2143 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2144 | ;; to generate them. | |
2145 | ||
2146 | (define_insn "smuldi3_highpart" | |
0551c32d | 2147 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2148 | (truncate:DI |
2149 | (lshiftrt:TI | |
0551c32d RH |
2150 | (mult:TI (sign_extend:TI |
2151 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2152 | (sign_extend:TI | |
2153 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2154 | (const_int 64))))] |
2155 | "" | |
aebf2462 | 2156 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2157 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2158 | |
2159 | (define_insn "umuldi3_highpart" | |
0551c32d | 2160 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2161 | (truncate:DI |
2162 | (lshiftrt:TI | |
0551c32d RH |
2163 | (mult:TI (zero_extend:TI |
2164 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2165 | (zero_extend:TI | |
2166 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2167 | (const_int 64))))] |
2168 | "" | |
aebf2462 | 2169 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2170 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2171 | |
2172 | (define_insn "negdi2" | |
0551c32d RH |
2173 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2174 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2175 | "" |
2176 | "sub %0 = r0, %1" | |
52e12ad0 | 2177 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2178 | |
2179 | (define_expand "absdi2" | |
2180 | [(set (match_dup 2) | |
f2f90c63 | 2181 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2182 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2183 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2184 | (neg:DI (match_dup 1)) |
2185 | (match_dup 1)))] | |
c65ebc55 | 2186 | "" |
1d5d7a21 | 2187 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2188 | |
2189 | (define_expand "smindi3" | |
2190 | [(set (match_dup 3) | |
f2f90c63 | 2191 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2192 | (match_operand:DI 2 "gr_register_operand" ""))) |
2193 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2194 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2195 | (match_dup 2) (match_dup 1)))] |
2196 | "" | |
1d5d7a21 | 2197 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2198 | |
2199 | (define_expand "smaxdi3" | |
2200 | [(set (match_dup 3) | |
f2f90c63 | 2201 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2202 | (match_operand:DI 2 "gr_register_operand" ""))) |
2203 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2204 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2205 | (match_dup 1) (match_dup 2)))] |
2206 | "" | |
1d5d7a21 | 2207 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2208 | |
2209 | (define_expand "umindi3" | |
2210 | [(set (match_dup 3) | |
f2f90c63 | 2211 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2212 | (match_operand:DI 2 "gr_register_operand" ""))) |
2213 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2214 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2215 | (match_dup 2) (match_dup 1)))] |
2216 | "" | |
1d5d7a21 | 2217 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2218 | |
2219 | (define_expand "umaxdi3" | |
2220 | [(set (match_dup 3) | |
f2f90c63 | 2221 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2222 | (match_operand:DI 2 "gr_register_operand" ""))) |
2223 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2224 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2225 | (match_dup 1) (match_dup 2)))] |
2226 | "" | |
1d5d7a21 | 2227 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2228 | |
2229 | (define_expand "ffsdi2" | |
2230 | [(set (match_dup 6) | |
f2f90c63 | 2231 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2232 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2233 | (set (match_dup 5) (const_int 0)) | |
2234 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2235 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2236 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2237 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2238 | (match_dup 5) (match_dup 4)))] |
2239 | "" | |
c65ebc55 JW |
2240 | { |
2241 | operands[2] = gen_reg_rtx (DImode); | |
2242 | operands[3] = gen_reg_rtx (DImode); | |
2243 | operands[4] = gen_reg_rtx (DImode); | |
2244 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2245 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2246 | }) |
c65ebc55 | 2247 | |
c407570a RH |
2248 | (define_expand "ctzdi2" |
2249 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2250 | (const_int -1))) | |
2251 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2252 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2253 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2254 | (popcount:DI (match_dup 4)))] | |
2255 | "" | |
2256 | { | |
2257 | operands[2] = gen_reg_rtx (DImode); | |
2258 | operands[3] = gen_reg_rtx (DImode); | |
2259 | operands[4] = gen_reg_rtx (DImode); | |
2260 | }) | |
2261 | ||
c407570a RH |
2262 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2263 | (define_expand "clzdi2" | |
2264 | [(set (match_dup 2) | |
02befdf4 | 2265 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2266 | (set (match_dup 3) |
2267 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2268 | (set (match_dup 4) (const_int 65598)) | |
2269 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2270 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2271 | "" |
c407570a | 2272 | { |
02befdf4 | 2273 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2274 | operands[3] = gen_reg_rtx (DImode); |
2275 | operands[4] = gen_reg_rtx (DImode); | |
2276 | }) | |
2277 | ||
2278 | (define_insn "popcountdi2" | |
0551c32d | 2279 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2280 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2281 | "" |
2282 | "popcnt %0 = %1" | |
52e12ad0 | 2283 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2284 | |
02befdf4 | 2285 | (define_insn "*getf_exp_xf" |
c407570a | 2286 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2287 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2288 | UNSPEC_GETF_EXP))] |
02befdf4 | 2289 | "" |
c407570a RH |
2290 | "getf.exp %0 = %1" |
2291 | [(set_attr "itanium_class" "frfr")]) | |
2292 | ||
655f2eb9 RH |
2293 | (define_expand "divdi3" |
2294 | [(set (match_operand:DI 0 "register_operand" "") | |
2295 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2296 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2297 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2298 | { |
02befdf4 | 2299 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2300 | |
02befdf4 | 2301 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2302 | |
2303 | if (CONSTANT_P (operands[1])) | |
2304 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2305 | op1_xf = gen_reg_rtx (XFmode); |
2306 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2307 | |
2308 | if (CONSTANT_P (operands[2])) | |
2309 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2310 | op2_xf = gen_reg_rtx (XFmode); |
2311 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2312 | |
dbdd120f | 2313 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2314 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2315 | else |
02befdf4 | 2316 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2317 | |
02befdf4 | 2318 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2319 | DONE; |
1d5d7a21 | 2320 | }) |
655f2eb9 RH |
2321 | |
2322 | (define_expand "moddi3" | |
2323 | [(set (match_operand:DI 0 "register_operand" "") | |
2324 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2325 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2326 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2327 | { |
2328 | rtx op2_neg, div; | |
2329 | ||
2330 | div = gen_reg_rtx (DImode); | |
2331 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2332 | ||
2333 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2334 | ||
2335 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2336 | DONE; | |
1d5d7a21 | 2337 | }) |
655f2eb9 RH |
2338 | |
2339 | (define_expand "udivdi3" | |
2340 | [(set (match_operand:DI 0 "register_operand" "") | |
2341 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2342 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2343 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2344 | { |
02befdf4 | 2345 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2346 | |
02befdf4 | 2347 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2348 | |
2349 | if (CONSTANT_P (operands[1])) | |
2350 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2351 | op1_xf = gen_reg_rtx (XFmode); |
2352 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2353 | |
2354 | if (CONSTANT_P (operands[2])) | |
2355 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2356 | op2_xf = gen_reg_rtx (XFmode); |
2357 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2358 | |
dbdd120f | 2359 | if (TARGET_INLINE_INT_DIV == INL_MIN_LAT) |
02befdf4 | 2360 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2361 | else |
02befdf4 | 2362 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2363 | |
02befdf4 | 2364 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2365 | DONE; |
1d5d7a21 | 2366 | }) |
655f2eb9 RH |
2367 | |
2368 | (define_expand "umoddi3" | |
2369 | [(set (match_operand:DI 0 "register_operand" "") | |
2370 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2371 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2372 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2373 | { |
2374 | rtx op2_neg, div; | |
2375 | ||
2376 | div = gen_reg_rtx (DImode); | |
2377 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2378 | ||
2379 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2380 | ||
2381 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2382 | DONE; | |
1d5d7a21 | 2383 | }) |
655f2eb9 RH |
2384 | |
2385 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2386 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2387 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2388 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2389 | (clobber (match_scratch:XF 3 "=&f")) | |
2390 | (clobber (match_scratch:XF 4 "=&f")) | |
2391 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2392 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 2393 | "TARGET_INLINE_INT_DIV == INL_MIN_LAT" |
655f2eb9 RH |
2394 | "#" |
2395 | "&& reload_completed" | |
02befdf4 | 2396 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2397 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2398 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2399 | (use (const_int 1))]) |
2400 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2401 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2402 | (minus:XF (match_dup 7) |
2403 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2404 | (use (const_int 1))])) |
2405 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2406 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2407 | (use (const_int 1))])) |
2408 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2409 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2410 | (use (const_int 1))])) |
2411 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2412 | (parallel [(set (match_dup 4) | |
02befdf4 | 2413 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2414 | (match_dup 4))) |
2415 | (use (const_int 1))])) | |
2416 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2417 | (parallel [(set (match_dup 0) | |
02befdf4 | 2418 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2419 | (match_dup 0))) |
2420 | (use (const_int 1))])) | |
2421 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2422 | (parallel [(set (match_dup 3) | |
02befdf4 | 2423 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2424 | (match_dup 4))) |
2425 | (use (const_int 1))])) | |
2426 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2427 | (parallel [(set (match_dup 0) | |
02befdf4 | 2428 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2429 | (match_dup 0))) |
2430 | (use (const_int 1))])) | |
2431 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2432 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2433 | (minus:XF (match_dup 1) |
2434 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2435 | (use (const_int 1))])) |
2436 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2437 | (parallel [(set (match_dup 0) | |
02befdf4 | 2438 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2439 | (match_dup 3))) |
2440 | (use (const_int 1))])) | |
2441 | ] | |
02befdf4 | 2442 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2443 | [(set_attr "predicable" "no")]) |
2444 | ||
2445 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2446 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2447 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2448 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2449 | (clobber (match_scratch:XF 3 "=&f")) | |
2450 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2451 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2452 | "TARGET_INLINE_INT_DIV == INL_MAX_THR" |
655f2eb9 RH |
2453 | "#" |
2454 | "&& reload_completed" | |
02befdf4 | 2455 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2456 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2457 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2458 | (use (const_int 1))]) |
2459 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2460 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2461 | (minus:XF (match_dup 6) |
2462 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2463 | (use (const_int 1))])) |
2464 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2465 | (parallel [(set (match_dup 0) | |
02befdf4 | 2466 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2467 | (match_dup 0))) |
2468 | (use (const_int 1))])) | |
2469 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2470 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2471 | (use (const_int 1))])) |
2472 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2473 | (parallel [(set (match_dup 0) | |
02befdf4 | 2474 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2475 | (match_dup 0))) |
2476 | (use (const_int 1))])) | |
2477 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2478 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2479 | (use (const_int 1))])) |
2480 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2481 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2482 | (minus:XF (match_dup 1) |
2483 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2484 | (use (const_int 1))])) |
2485 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2486 | (parallel [(set (match_dup 0) | |
02befdf4 | 2487 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2488 | (match_dup 3))) |
2489 | (use (const_int 1))])) | |
2490 | ] | |
02befdf4 | 2491 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2492 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2493 | \f |
2494 | ;; :::::::::::::::::::: | |
2495 | ;; :: | |
2496 | ;; :: 32 bit floating point arithmetic | |
2497 | ;; :: | |
2498 | ;; :::::::::::::::::::: | |
2499 | ||
2500 | (define_insn "addsf3" | |
0551c32d RH |
2501 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2502 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2503 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2504 | "" |
aebf2462 | 2505 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2506 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2507 | |
2508 | (define_insn "subsf3" | |
0551c32d RH |
2509 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2510 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2511 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2512 | "" |
aebf2462 | 2513 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2514 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2515 | |
2516 | (define_insn "mulsf3" | |
0551c32d RH |
2517 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2518 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2519 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2520 | "" |
aebf2462 | 2521 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2522 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2523 | |
2524 | (define_insn "abssf2" | |
0551c32d RH |
2525 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2526 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2527 | "" |
aebf2462 | 2528 | "fabs %0 = %1" |
52e12ad0 | 2529 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2530 | |
2531 | (define_insn "negsf2" | |
0551c32d RH |
2532 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2533 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2534 | "" |
aebf2462 | 2535 | "fneg %0 = %1" |
52e12ad0 | 2536 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2537 | |
2538 | (define_insn "*nabssf2" | |
0551c32d RH |
2539 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2540 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2541 | "" |
aebf2462 | 2542 | "fnegabs %0 = %1" |
52e12ad0 | 2543 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2544 | |
046625fa RH |
2545 | (define_insn "copysignsf3" |
2546 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2547 | (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2548 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2549 | UNSPEC_COPYSIGN))] | |
2550 | "" | |
2551 | "fmerge.s %0 = %F2, %F1" | |
2552 | [(set_attr "itanium_class" "fmisc")]) | |
2553 | ||
2554 | (define_insn "*ncopysignsf3" | |
2555 | [(set (match_operand:SF 0 "register_operand" "=f") | |
2556 | (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2557 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] | |
2558 | UNSPEC_COPYSIGN)))] | |
2559 | "" | |
2560 | "fmerge.ns %0 = %F2, %F1" | |
2561 | [(set_attr "itanium_class" "fmisc")]) | |
2562 | ||
7ae4d8d4 | 2563 | (define_insn "sminsf3" |
0551c32d RH |
2564 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2565 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2566 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2567 | "" |
aebf2462 | 2568 | "fmin %0 = %1, %F2" |
52e12ad0 | 2569 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2570 | |
7ae4d8d4 | 2571 | (define_insn "smaxsf3" |
0551c32d RH |
2572 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2573 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2574 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2575 | "" |
aebf2462 | 2576 | "fmax %0 = %1, %F2" |
52e12ad0 | 2577 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2578 | |
655f2eb9 | 2579 | (define_insn "*maddsf4" |
0551c32d RH |
2580 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2581 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2582 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2583 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2584 | "" |
aebf2462 | 2585 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2586 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2587 | |
655f2eb9 | 2588 | (define_insn "*msubsf4" |
0551c32d RH |
2589 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2590 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2591 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2592 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2593 | "" |
aebf2462 | 2594 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2595 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2596 | |
2597 | (define_insn "*nmulsf3" | |
0551c32d RH |
2598 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2599 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2600 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2601 | "" |
aebf2462 | 2602 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2603 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2604 | |
655f2eb9 | 2605 | (define_insn "*nmaddsf4" |
0551c32d | 2606 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
2607 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
2608 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2609 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2610 | "" |
aebf2462 | 2611 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2612 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2613 | |
52ad4d7b ZW |
2614 | (define_insn "*nmaddsf4_alts" |
2615 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2616 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
2617 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2618 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
2619 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2620 | "" | |
2621 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
2622 | [(set_attr "itanium_class" "fmac")]) | |
2623 | ||
26102535 RH |
2624 | (define_expand "divsf3" |
2625 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2626 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2627 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 2628 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
2629 | { |
2630 | rtx insn; | |
dbdd120f | 2631 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
2632 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
2633 | else | |
2634 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2635 | emit_insn (insn); | |
2636 | DONE; | |
1d5d7a21 | 2637 | }) |
26102535 RH |
2638 | |
2639 | (define_insn_and_split "divsf3_internal_lat" | |
2640 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2641 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2642 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
2643 | (clobber (match_scratch:XF 3 "=&f")) |
2644 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2645 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2646 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
2647 | "#" |
2648 | "&& reload_completed" | |
02befdf4 | 2649 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
2650 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2651 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 2652 | (use (const_int 0))]) |
26102535 | 2653 | (cond_exec (ne (match_dup 5) (const_int 0)) |
02befdf4 | 2654 | (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) |
26102535 RH |
2655 | (use (const_int 1))])) |
2656 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2657 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2658 | (minus:XF (match_dup 10) |
2659 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
2660 | (use (const_int 1))])) |
2661 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2662 | (parallel [(set (match_dup 3) | |
02befdf4 | 2663 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2664 | (match_dup 3))) |
2665 | (use (const_int 1))])) | |
2666 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2667 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
2668 | (use (const_int 1))])) |
2669 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2670 | (parallel [(set (match_dup 3) | |
02befdf4 | 2671 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2672 | (match_dup 3))) |
2673 | (use (const_int 1))])) | |
2674 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2675 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
2676 | (use (const_int 1))])) |
2677 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2678 | (parallel [(set (match_dup 9) | |
2679 | (float_truncate:DF | |
02befdf4 | 2680 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2681 | (match_dup 3)))) |
2682 | (use (const_int 1))])) | |
2683 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2684 | (set (match_dup 0) | |
2685 | (float_truncate:SF (match_dup 6)))) | |
2686 | ] | |
1d5d7a21 | 2687 | { |
02befdf4 ZW |
2688 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
2689 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
2690 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 2691 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); |
02befdf4 | 2692 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 2693 | } |
26102535 RH |
2694 | [(set_attr "predicable" "no")]) |
2695 | ||
2696 | (define_insn_and_split "divsf3_internal_thr" | |
2697 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2698 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2699 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
2700 | (clobber (match_scratch:XF 3 "=&f")) |
2701 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2702 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 2703 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
2704 | "#" |
2705 | "&& reload_completed" | |
02befdf4 | 2706 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
2707 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2708 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 2709 | (use (const_int 0))]) |
26102535 RH |
2710 | (cond_exec (ne (match_dup 5) (const_int 0)) |
2711 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2712 | (minus:XF (match_dup 10) |
2713 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
2714 | (use (const_int 1))])) |
2715 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2716 | (parallel [(set (match_dup 3) | |
02befdf4 | 2717 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
2718 | (match_dup 3))) |
2719 | (use (const_int 1))])) | |
2720 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2721 | (parallel [(set (match_dup 6) | |
02befdf4 | 2722 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
2723 | (match_dup 6))) |
2724 | (use (const_int 1))])) | |
2725 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2726 | (parallel [(set (match_dup 9) | |
2727 | (float_truncate:SF | |
02befdf4 | 2728 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
2729 | (use (const_int 1))])) |
2730 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2731 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2732 | (minus:XF (match_dup 7) |
2733 | (mult:XF (match_dup 8) (match_dup 3)))) | |
26102535 RH |
2734 | (use (const_int 1))])) |
2735 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2736 | (set (match_dup 0) | |
2737 | (float_truncate:SF | |
02befdf4 | 2738 | (plus:XF (mult:XF (match_dup 4) (match_dup 6)) |
26102535 RH |
2739 | (match_dup 3))))) |
2740 | ] | |
1d5d7a21 | 2741 | { |
02befdf4 ZW |
2742 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
2743 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
2744 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 2745 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); |
02befdf4 | 2746 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 2747 | } |
26102535 | 2748 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
2749 | |
2750 | ;; Inline square root. | |
2751 | ||
2752 | (define_insn "*sqrt_approx" | |
2753 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
2754 | (div:XF (const_int 1) | |
2755 | (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f")))) | |
2756 | (set (match_operand:BI 1 "register_operand" "=c") | |
2757 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
2758 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
2759 | "" | |
2760 | "frsqrta.s%3 %0, %1 = %2" | |
2761 | [(set_attr "itanium_class" "fmisc") | |
2762 | (set_attr "predicable" "no")]) | |
2763 | ||
9aec7fb4 | 2764 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
2765 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
2766 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
2767 | UNSPEC_SETF_EXP))] | |
2768 | "" | |
2769 | "setf.exp %0 = %1" | |
2770 | [(set_attr "itanium_class" "frfr")]) | |
2771 | ||
2772 | (define_expand "sqrtsf2" | |
2773 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2774 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
2775 | "TARGET_INLINE_SQRT" | |
2776 | { | |
2777 | rtx insn; | |
b38ba463 | 2778 | #if 0 |
e820471b | 2779 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 2780 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); |
e820471b | 2781 | else |
b38ba463 | 2782 | #else |
e820471b | 2783 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 2784 | #endif |
e820471b | 2785 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
2786 | emit_insn (insn); |
2787 | DONE; | |
2788 | }) | |
2789 | ||
2790 | ;; Latency-optimized square root. | |
2791 | ;; FIXME: Implement. | |
2792 | ||
2793 | ;; Throughput-optimized square root. | |
2794 | ||
2795 | (define_insn_and_split "sqrtsf2_internal_thr" | |
2796 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2797 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
2798 | ;; Register r2 in optimization guide. | |
2799 | (clobber (match_scratch:DI 2 "=r")) | |
2800 | ;; Register f8 in optimization guide | |
2801 | (clobber (match_scratch:XF 3 "=&f")) | |
2802 | ;; Register f9 in optimization guide | |
2803 | (clobber (match_scratch:XF 4 "=&f")) | |
2804 | ;; Register f10 in optimization guide | |
2805 | (clobber (match_scratch:XF 5 "=&f")) | |
2806 | ;; Register p6 in optimization guide. | |
2807 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 2808 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
2809 | "#" |
2810 | "&& reload_completed" | |
2811 | [ ;; exponent of +1/2 in r2 | |
2812 | (set (match_dup 2) (const_int 65534)) | |
2813 | ;; +1/2 in f8 | |
2814 | (set (match_dup 3) | |
2815 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
2816 | ;; Step 1 | |
2817 | ;; y0 = 1/sqrt(a) in f7 | |
2818 | (parallel [(set (match_dup 7) | |
2819 | (div:XF (const_int 1) | |
2820 | (sqrt:XF (match_dup 8)))) | |
2821 | (set (match_dup 6) | |
2822 | (unspec:BI [(match_dup 8)] | |
2823 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
2824 | (use (const_int 0))]) | |
2825 | ;; Step 2 | |
2826 | ;; H0 = 1/2 * y0 in f9 | |
2827 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2828 | (parallel [(set (match_dup 4) | |
2829 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
2830 | (match_dup 9))) | |
2831 | (use (const_int 1))])) | |
2832 | ;; Step 3 | |
2833 | ;; S0 = a * y0 in f7 | |
2834 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2835 | (parallel [(set (match_dup 7) | |
2836 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
2837 | (match_dup 9))) | |
2838 | (use (const_int 1))])) | |
2839 | ;; Step 4 | |
2840 | ;; d = 1/2 - S0 * H0 in f10 | |
2841 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2842 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2843 | (minus:XF (match_dup 3) |
2844 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
2845 | (use (const_int 1))])) |
2846 | ;; Step 5 | |
2847 | ;; d' = d + 1/2 * d in f8 | |
2848 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2849 | (parallel [(set (match_dup 3) | |
2850 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
2851 | (match_dup 5))) | |
2852 | (use (const_int 1))])) | |
2853 | ;; Step 6 | |
2854 | ;; e = d + d * d' in f8 | |
2855 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2856 | (parallel [(set (match_dup 3) | |
2857 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
2858 | (match_dup 5))) | |
2859 | (use (const_int 1))])) | |
2860 | ;; Step 7 | |
2861 | ;; S1 = S0 + e * S0 in f7 | |
2862 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2863 | (parallel [(set (match_dup 0) | |
2864 | (float_truncate:SF | |
2865 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
2866 | (match_dup 7)))) | |
2867 | (use (const_int 1))])) | |
2868 | ;; Step 8 | |
2869 | ;; H1 = H0 + e * H0 in f8 | |
2870 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2871 | (parallel [(set (match_dup 3) | |
2872 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
2873 | (match_dup 4))) | |
2874 | (use (const_int 1))])) | |
2875 | ;; Step 9 | |
2876 | ;; d1 = a - S1 * S1 in f9 | |
2877 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2878 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2879 | (minus:XF (match_dup 8) |
2880 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
2881 | (use (const_int 1))])) |
2882 | ;; Step 10 | |
2883 | ;; S = S1 + d1 * H1 in f7 | |
2884 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2885 | (parallel [(set (match_dup 0) | |
2886 | (float_truncate:SF | |
2887 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
2888 | (match_dup 7)))) | |
2889 | (use (const_int 0))]))] | |
2890 | { | |
2891 | /* Generate 82-bit versions of the input and output operands. */ | |
2892 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
2893 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
2894 | /* Generate required floating-point constants. */ | |
2895 | operands[9] = CONST0_RTX (XFmode); | |
2896 | } | |
2897 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2898 | \f |
2899 | ;; :::::::::::::::::::: | |
2900 | ;; :: | |
2901 | ;; :: 64 bit floating point arithmetic | |
2902 | ;; :: | |
2903 | ;; :::::::::::::::::::: | |
2904 | ||
2905 | (define_insn "adddf3" | |
0551c32d RH |
2906 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2907 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2908 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2909 | "" |
aebf2462 | 2910 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2911 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2912 | |
26102535 RH |
2913 | (define_insn "*adddf3_trunc" |
2914 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2915 | (float_truncate:SF | |
2916 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2917 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2918 | "" | |
aebf2462 | 2919 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2920 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2921 | |
c65ebc55 | 2922 | (define_insn "subdf3" |
0551c32d RH |
2923 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2924 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2925 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2926 | "" |
aebf2462 | 2927 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2928 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2929 | |
26102535 RH |
2930 | (define_insn "*subdf3_trunc" |
2931 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2932 | (float_truncate:SF | |
2933 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2934 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2935 | "" | |
aebf2462 | 2936 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2937 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2938 | |
c65ebc55 | 2939 | (define_insn "muldf3" |
0551c32d RH |
2940 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2941 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2942 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2943 | "" |
aebf2462 | 2944 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2945 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2946 | |
26102535 RH |
2947 | (define_insn "*muldf3_trunc" |
2948 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2949 | (float_truncate:SF | |
2950 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2951 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2952 | "" | |
aebf2462 | 2953 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2954 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2955 | |
c65ebc55 | 2956 | (define_insn "absdf2" |
0551c32d RH |
2957 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2958 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2959 | "" |
aebf2462 | 2960 | "fabs %0 = %1" |
52e12ad0 | 2961 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2962 | |
2963 | (define_insn "negdf2" | |
0551c32d RH |
2964 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2965 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2966 | "" |
aebf2462 | 2967 | "fneg %0 = %1" |
52e12ad0 | 2968 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2969 | |
2970 | (define_insn "*nabsdf2" | |
0551c32d RH |
2971 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2972 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2973 | "" |
aebf2462 | 2974 | "fnegabs %0 = %1" |
52e12ad0 | 2975 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2976 | |
046625fa RH |
2977 | (define_insn "copysigndf3" |
2978 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2979 | (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2980 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2981 | UNSPEC_COPYSIGN))] | |
2982 | "" | |
2983 | "fmerge.s %0 = %F2, %F1" | |
2984 | [(set_attr "itanium_class" "fmisc")]) | |
2985 | ||
2986 | (define_insn "*ncopysigndf3" | |
2987 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2988 | (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2989 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] | |
2990 | UNSPEC_COPYSIGN)))] | |
2991 | "" | |
2992 | "fmerge.ns %0 = %F2, %F1" | |
2993 | [(set_attr "itanium_class" "fmisc")]) | |
2994 | ||
7ae4d8d4 | 2995 | (define_insn "smindf3" |
0551c32d RH |
2996 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2997 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2998 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2999 | "" |
aebf2462 | 3000 | "fmin %0 = %1, %F2" |
52e12ad0 | 3001 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3002 | |
7ae4d8d4 | 3003 | (define_insn "smaxdf3" |
0551c32d RH |
3004 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3005 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3006 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3007 | "" |
aebf2462 | 3008 | "fmax %0 = %1, %F2" |
52e12ad0 | 3009 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3010 | |
655f2eb9 | 3011 | (define_insn "*madddf4" |
0551c32d RH |
3012 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3013 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3014 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3015 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3016 | "" |
aebf2462 | 3017 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3018 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3019 | |
26102535 RH |
3020 | (define_insn "*madddf4_trunc" |
3021 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3022 | (float_truncate:SF | |
3023 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3024 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3025 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3026 | "" | |
aebf2462 | 3027 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3028 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3029 | |
655f2eb9 | 3030 | (define_insn "*msubdf4" |
0551c32d RH |
3031 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3032 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3033 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3034 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3035 | "" |
aebf2462 | 3036 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3037 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3038 | |
26102535 RH |
3039 | (define_insn "*msubdf4_trunc" |
3040 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3041 | (float_truncate:SF | |
3042 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3043 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3044 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3045 | "" | |
aebf2462 | 3046 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3047 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3048 | |
c65ebc55 | 3049 | (define_insn "*nmuldf3" |
0551c32d RH |
3050 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3051 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3052 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3053 | "" |
aebf2462 | 3054 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3055 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3056 | |
26102535 RH |
3057 | (define_insn "*nmuldf3_trunc" |
3058 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3059 | (float_truncate:SF | |
3060 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3061 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3062 | "" | |
aebf2462 | 3063 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3064 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3065 | |
655f2eb9 | 3066 | (define_insn "*nmadddf4" |
0551c32d | 3067 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3068 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3069 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3070 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3071 | "" |
aebf2462 | 3072 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3073 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3074 | |
3075 | (define_insn "*nmadddf4_alts" | |
3076 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3077 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3078 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3079 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3080 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3081 | "" | |
aebf2462 | 3082 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3083 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3084 | |
52ad4d7b | 3085 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3086 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3087 | (float_truncate:SF | |
52ad4d7b ZW |
3088 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3089 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3090 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3091 | "" |
aebf2462 | 3092 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3093 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3094 | |
52ad4d7b ZW |
3095 | (define_insn "*nmadddf4_truncsf_alts" |
3096 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3097 | (float_truncate:SF | |
3098 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3099 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3100 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3101 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3102 | "" | |
3103 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3104 | [(set_attr "itanium_class" "fmac")]) | |
3105 | ||
26102535 RH |
3106 | (define_expand "divdf3" |
3107 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3108 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3109 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3110 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3111 | { |
3112 | rtx insn; | |
dbdd120f | 3113 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
26102535 RH |
3114 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3115 | else | |
3116 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3117 | emit_insn (insn); | |
3118 | DONE; | |
1d5d7a21 | 3119 | }) |
26102535 RH |
3120 | |
3121 | (define_insn_and_split "divdf3_internal_lat" | |
3122 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3123 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3124 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3125 | (clobber (match_scratch:XF 3 "=&f")) |
3126 | (clobber (match_scratch:XF 4 "=&f")) | |
3127 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 3128 | (clobber (match_scratch:BI 6 "=c"))] |
dbdd120f | 3129 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3130 | "#" |
3131 | "&& reload_completed" | |
02befdf4 | 3132 | [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) |
086c0f96 RH |
3133 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3134 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3135 | (use (const_int 0))]) |
26102535 | 3136 | (cond_exec (ne (match_dup 6) (const_int 0)) |
02befdf4 | 3137 | (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) |
26102535 RH |
3138 | (use (const_int 1))])) |
3139 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3140 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3141 | (minus:XF (match_dup 12) |
3142 | (mult:XF (match_dup 9) (match_dup 7)))) | |
26102535 RH |
3143 | (use (const_int 1))])) |
3144 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3145 | (parallel [(set (match_dup 3) | |
02befdf4 | 3146 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3147 | (match_dup 3))) |
3148 | (use (const_int 1))])) | |
3149 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3150 | (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3151 | (use (const_int 1))])) |
3152 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3153 | (parallel [(set (match_dup 7) | |
02befdf4 | 3154 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3155 | (match_dup 7))) |
3156 | (use (const_int 1))])) | |
3157 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3158 | (parallel [(set (match_dup 3) | |
02befdf4 | 3159 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3160 | (match_dup 3))) |
3161 | (use (const_int 1))])) | |
3162 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3163 | (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5))) |
26102535 RH |
3164 | (use (const_int 1))])) |
3165 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3166 | (parallel [(set (match_dup 7) | |
02befdf4 | 3167 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3168 | (match_dup 7))) |
3169 | (use (const_int 1))])) | |
3170 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3171 | (parallel [(set (match_dup 10) | |
3172 | (float_truncate:DF | |
02befdf4 | 3173 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3174 | (match_dup 3)))) |
3175 | (use (const_int 1))])) | |
3176 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3177 | (parallel [(set (match_dup 7) | |
02befdf4 | 3178 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3179 | (match_dup 7))) |
3180 | (use (const_int 1))])) | |
3181 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3182 | (parallel [(set (match_dup 11) | |
3183 | (float_truncate:DF | |
52ad4d7b ZW |
3184 | (minus:XF (match_dup 8) |
3185 | (mult:XF (match_dup 9) (match_dup 3))))) | |
26102535 RH |
3186 | (use (const_int 1))])) |
3187 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3188 | (set (match_dup 0) | |
02befdf4 | 3189 | (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3190 | (match_dup 3))))) |
3191 | ] | |
1d5d7a21 | 3192 | { |
02befdf4 ZW |
3193 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3194 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3195 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 RH |
3196 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
3197 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
02befdf4 | 3198 | operands[12] = CONST1_RTX (XFmode); |
1d5d7a21 | 3199 | } |
26102535 RH |
3200 | [(set_attr "predicable" "no")]) |
3201 | ||
3202 | (define_insn_and_split "divdf3_internal_thr" | |
3203 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3204 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3205 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 | 3206 | (clobber (match_scratch:XF 3 "=&f")) |
26102535 | 3207 | (clobber (match_scratch:DF 4 "=f")) |
f2f90c63 | 3208 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3209 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
3210 | "#" |
3211 | "&& reload_completed" | |
02befdf4 | 3212 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3213 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3214 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3215 | (use (const_int 0))]) |
26102535 RH |
3216 | (cond_exec (ne (match_dup 5) (const_int 0)) |
3217 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3218 | (minus:XF (match_dup 10) |
3219 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3220 | (use (const_int 1))])) |
3221 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3222 | (parallel [(set (match_dup 6) | |
02befdf4 | 3223 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3224 | (match_dup 6))) |
3225 | (use (const_int 1))])) | |
3226 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3227 | (parallel [(set (match_dup 3) | |
02befdf4 | 3228 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3229 | (use (const_int 1))])) |
3230 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3231 | (parallel [(set (match_dup 6) | |
02befdf4 | 3232 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3233 | (match_dup 6))) |
3234 | (use (const_int 1))])) | |
3235 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3236 | (parallel [(set (match_dup 3) | |
02befdf4 | 3237 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3238 | (use (const_int 1))])) |
3239 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3240 | (parallel [(set (match_dup 6) | |
02befdf4 | 3241 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3242 | (match_dup 6))) |
3243 | (use (const_int 1))])) | |
3244 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3245 | (parallel [(set (match_dup 9) | |
3246 | (float_truncate:DF | |
aa42f99d | 3247 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3248 | (use (const_int 1))])) |
3249 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3250 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3251 | (minus:DF (match_dup 1) |
3252 | (mult:DF (match_dup 2) (match_dup 9)))) | |
26102535 RH |
3253 | (use (const_int 1))])) |
3254 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3255 | (set (match_dup 0) | |
3256 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3257 | (match_dup 9)))) | |
3258 | ] | |
1d5d7a21 | 3259 | { |
02befdf4 ZW |
3260 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3261 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3262 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3263 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
02befdf4 | 3264 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3265 | } |
26102535 | 3266 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3267 | |
3268 | ;; Inline square root. | |
3269 | ||
3270 | (define_expand "sqrtdf2" | |
3271 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3272 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3273 | "TARGET_INLINE_SQRT" | |
3274 | { | |
3275 | rtx insn; | |
b38ba463 | 3276 | #if 0 |
e820471b | 3277 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3278 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); |
e820471b | 3279 | else |
b38ba463 | 3280 | #else |
e820471b | 3281 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3282 | #endif |
e820471b | 3283 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3284 | emit_insn (insn); |
3285 | DONE; | |
3286 | }) | |
3287 | ||
3288 | ;; Latency-optimized square root. | |
3289 | ;; FIXME: Implement. | |
3290 | ||
3291 | ;; Throughput-optimized square root. | |
3292 | ||
3293 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3294 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3295 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3296 | ;; Register r2 in optimization guide. | |
3297 | (clobber (match_scratch:DI 2 "=r")) | |
3298 | ;; Register f8 in optimization guide | |
3299 | (clobber (match_scratch:XF 3 "=&f")) | |
3300 | ;; Register f9 in optimization guide | |
3301 | (clobber (match_scratch:XF 4 "=&f")) | |
3302 | ;; Register f10 in optimization guide | |
3303 | (clobber (match_scratch:XF 5 "=&f")) | |
3304 | ;; Register p6 in optimization guide. | |
3305 | (clobber (match_scratch:BI 6 "=c"))] | |
dbdd120f | 3306 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3307 | "#" |
3308 | "&& reload_completed" | |
3309 | [ ;; exponent of +1/2 in r2 | |
3310 | (set (match_dup 2) (const_int 65534)) | |
3311 | ;; +1/2 in f10 | |
3312 | (set (match_dup 5) | |
3313 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3314 | ;; Step 1 | |
3315 | ;; y0 = 1/sqrt(a) in f7 | |
3316 | (parallel [(set (match_dup 7) | |
3317 | (div:XF (const_int 1) | |
3318 | (sqrt:XF (match_dup 8)))) | |
3319 | (set (match_dup 6) | |
3320 | (unspec:BI [(match_dup 8)] | |
3321 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3322 | (use (const_int 0))]) | |
3323 | ;; Step 2 | |
3324 | ;; H0 = 1/2 * y0 in f8 | |
3325 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3326 | (parallel [(set (match_dup 3) | |
3327 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3328 | (match_dup 9))) | |
3329 | (use (const_int 1))])) | |
3330 | ;; Step 3 | |
3331 | ;; G0 = a * y0 in f7 | |
3332 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3333 | (parallel [(set (match_dup 7) | |
3334 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3335 | (match_dup 9))) | |
3336 | (use (const_int 1))])) | |
3337 | ;; Step 4 | |
3338 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3339 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3340 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3341 | (minus:XF (match_dup 5) |
3342 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3343 | (use (const_int 1))])) |
3344 | ;; Step 5 | |
3345 | ;; H1 = H0 + r0 * H0 in f8 | |
3346 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3347 | (parallel [(set (match_dup 3) | |
3348 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3349 | (match_dup 3))) | |
3350 | (use (const_int 1))])) | |
3351 | ;; Step 6 | |
3352 | ;; G1 = G0 + r0 * G0 in f7 | |
3353 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3354 | (parallel [(set (match_dup 7) | |
3355 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3356 | (match_dup 7))) | |
3357 | (use (const_int 1))])) | |
3358 | ;; Step 7 | |
3359 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3360 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3361 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3362 | (minus:XF (match_dup 5) |
3363 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3364 | (use (const_int 1))])) |
3365 | ;; Step 8 | |
3366 | ;; H2 = H1 + r1 * H1 in f8 | |
3367 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3368 | (parallel [(set (match_dup 3) | |
3369 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3370 | (match_dup 3))) | |
3371 | (use (const_int 1))])) | |
3372 | ;; Step 9 | |
3373 | ;; G2 = G1 + r1 * G1 in f7 | |
3374 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3375 | (parallel [(set (match_dup 7) | |
3376 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3377 | (match_dup 7))) | |
3378 | (use (const_int 1))])) | |
3379 | ;; Step 10 | |
3380 | ;; d2 = a - G2 * G2 in f9 | |
3381 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3382 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3383 | (minus:XF (match_dup 8) |
3384 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3385 | (use (const_int 1))])) |
3386 | ;; Step 11 | |
3387 | ;; G3 = G2 + d2 * H2 in f7 | |
3388 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3389 | (parallel [(set (match_dup 7) | |
3390 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3391 | (match_dup 7))) | |
3392 | (use (const_int 1))])) | |
3393 | ;; Step 12 | |
3394 | ;; d3 = a - G3 * G3 in f9 | |
3395 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3396 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3397 | (minus:XF (match_dup 8) |
3398 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3399 | (use (const_int 1))])) |
3400 | ;; Step 13 | |
3401 | ;; S = G3 + d3 * H2 in f7 | |
3402 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3403 | (parallel [(set (match_dup 0) | |
3404 | (float_truncate:DF | |
3405 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3406 | (match_dup 7)))) | |
3407 | (use (const_int 0))]))] | |
3408 | { | |
3409 | /* Generate 82-bit versions of the input and output operands. */ | |
3410 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3411 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3412 | /* Generate required floating-point constants. */ | |
3413 | operands[9] = CONST0_RTX (XFmode); | |
3414 | } | |
3415 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3416 | \f |
3417 | ;; :::::::::::::::::::: | |
3418 | ;; :: | |
3419 | ;; :: 80 bit floating point arithmetic | |
3420 | ;; :: | |
3421 | ;; :::::::::::::::::::: | |
3422 | ||
02befdf4 ZW |
3423 | (define_insn "addxf3" |
3424 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3425 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3426 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3427 | "" | |
aebf2462 | 3428 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3429 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3430 | |
02befdf4 | 3431 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3432 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3433 | (float_truncate:SF | |
02befdf4 ZW |
3434 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3435 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3436 | "" | |
aebf2462 | 3437 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3438 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3439 | |
02befdf4 | 3440 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3441 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3442 | (float_truncate:DF | |
02befdf4 ZW |
3443 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3444 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3445 | "" | |
aebf2462 | 3446 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3447 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3448 | |
02befdf4 ZW |
3449 | (define_insn "subxf3" |
3450 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3451 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3452 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3453 | "" | |
aebf2462 | 3454 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3455 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3456 | |
02befdf4 | 3457 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3458 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3459 | (float_truncate:SF | |
02befdf4 ZW |
3460 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3461 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3462 | "" | |
aebf2462 | 3463 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3464 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3465 | |
02befdf4 | 3466 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3467 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3468 | (float_truncate:DF | |
02befdf4 ZW |
3469 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3470 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3471 | "" | |
aebf2462 | 3472 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3473 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3474 | |
02befdf4 ZW |
3475 | (define_insn "mulxf3" |
3476 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3477 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3478 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3479 | "" | |
aebf2462 | 3480 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3481 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3482 | |
02befdf4 | 3483 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3484 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3485 | (float_truncate:SF | |
02befdf4 ZW |
3486 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3487 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3488 | "" | |
aebf2462 | 3489 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3490 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3491 | |
02befdf4 | 3492 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3493 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3494 | (float_truncate:DF | |
02befdf4 ZW |
3495 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3496 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3497 | "" | |
aebf2462 | 3498 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3499 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3500 | |
02befdf4 ZW |
3501 | (define_insn "*mulxf3_alts" |
3502 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3503 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3504 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3505 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3506 | "" |
aebf2462 | 3507 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3508 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3509 | |
02befdf4 | 3510 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3511 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3512 | (float_truncate:SF | |
02befdf4 ZW |
3513 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3514 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3515 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3516 | "" |
aebf2462 | 3517 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3518 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3519 | |
02befdf4 | 3520 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3521 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3522 | (float_truncate:DF | |
02befdf4 ZW |
3523 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3524 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3525 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3526 | "" |
aebf2462 | 3527 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3528 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3529 | |
02befdf4 ZW |
3530 | (define_insn "absxf2" |
3531 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3532 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3533 | "" | |
aebf2462 | 3534 | "fabs %0 = %F1" |
52e12ad0 | 3535 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3536 | |
02befdf4 ZW |
3537 | (define_insn "negxf2" |
3538 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3539 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3540 | "" | |
aebf2462 | 3541 | "fneg %0 = %F1" |
52e12ad0 | 3542 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3543 | |
02befdf4 ZW |
3544 | (define_insn "*nabsxf2" |
3545 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3546 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3547 | "" | |
aebf2462 | 3548 | "fnegabs %0 = %F1" |
52e12ad0 | 3549 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3550 | |
046625fa RH |
3551 | (define_insn "copysignxf3" |
3552 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3553 | (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3554 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3555 | UNSPEC_COPYSIGN))] | |
3556 | "" | |
3557 | "fmerge.s %0 = %F2, %F1" | |
3558 | [(set_attr "itanium_class" "fmisc")]) | |
3559 | ||
3560 | (define_insn "*ncopysignxf3" | |
3561 | [(set (match_operand:XF 0 "register_operand" "=f") | |
3562 | (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") | |
3563 | (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] | |
3564 | UNSPEC_COPYSIGN)))] | |
3565 | "" | |
3566 | "fmerge.ns %0 = %F2, %F1" | |
3567 | [(set_attr "itanium_class" "fmisc")]) | |
3568 | ||
7ae4d8d4 | 3569 | (define_insn "sminxf3" |
02befdf4 ZW |
3570 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3571 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3572 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3573 | "" | |
aebf2462 | 3574 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3575 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3576 | |
7ae4d8d4 | 3577 | (define_insn "smaxxf3" |
02befdf4 ZW |
3578 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3579 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3580 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3581 | "" | |
aebf2462 | 3582 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3583 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3584 | |
02befdf4 ZW |
3585 | (define_insn "*maddxf4" |
3586 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3587 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3588 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3589 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3590 | "" | |
aebf2462 | 3591 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3592 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3593 | |
02befdf4 | 3594 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3595 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3596 | (float_truncate:SF | |
02befdf4 ZW |
3597 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3598 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3599 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3600 | "" | |
aebf2462 | 3601 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3602 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3603 | |
02befdf4 | 3604 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3605 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3606 | (float_truncate:DF | |
02befdf4 ZW |
3607 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3608 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3609 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3610 | "" | |
aebf2462 | 3611 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3612 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3613 | |
02befdf4 ZW |
3614 | (define_insn "*maddxf4_alts" |
3615 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3616 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3617 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3618 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3619 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3620 | "" |
aebf2462 | 3621 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3622 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3623 | |
b38ba463 ZW |
3624 | (define_insn "*maddxf4_alts_truncsf" |
3625 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3626 | (float_truncate:SF | |
3627 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3628 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3629 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3630 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3631 | "" | |
3632 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3633 | [(set_attr "itanium_class" "fmac")]) | |
3634 | ||
02befdf4 | 3635 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3636 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3637 | (float_truncate:DF | |
02befdf4 ZW |
3638 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3639 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3640 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3641 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3642 | "" |
aebf2462 | 3643 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3644 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3645 | |
02befdf4 ZW |
3646 | (define_insn "*msubxf4" |
3647 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3648 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3649 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3650 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3651 | "" | |
aebf2462 | 3652 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3653 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3654 | |
02befdf4 | 3655 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3656 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3657 | (float_truncate:SF | |
02befdf4 ZW |
3658 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3659 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3660 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3661 | "" | |
aebf2462 | 3662 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3663 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3664 | |
02befdf4 | 3665 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3666 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3667 | (float_truncate:DF | |
02befdf4 ZW |
3668 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3669 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3670 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3671 | "" | |
aebf2462 | 3672 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3673 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3674 | |
02befdf4 ZW |
3675 | (define_insn "*nmulxf3" |
3676 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3677 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3678 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3679 | "" | |
aebf2462 | 3680 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3681 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3682 | |
02befdf4 | 3683 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3684 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3685 | (float_truncate:SF | |
02befdf4 ZW |
3686 | (neg:XF (mult:XF |
3687 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3688 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3689 | "" | |
aebf2462 | 3690 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3691 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3692 | |
02befdf4 | 3693 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3694 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3695 | (float_truncate:DF | |
02befdf4 ZW |
3696 | (neg:XF (mult:XF |
3697 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3698 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3699 | "" | |
aebf2462 | 3700 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3701 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3702 | |
02befdf4 ZW |
3703 | (define_insn "*nmaddxf4" |
3704 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3705 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3706 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3707 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3708 | )))] | |
02befdf4 | 3709 | "" |
aebf2462 | 3710 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3711 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3712 | |
02befdf4 | 3713 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
3714 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3715 | (float_truncate:SF | |
52ad4d7b ZW |
3716 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3717 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3718 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3719 | ))))] | |
02befdf4 | 3720 | "" |
aebf2462 | 3721 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3722 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3723 | |
02befdf4 | 3724 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
3725 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3726 | (float_truncate:DF | |
52ad4d7b ZW |
3727 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3728 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3729 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3730 | ))))] | |
02befdf4 | 3731 | "" |
aebf2462 | 3732 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3733 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3734 | |
02befdf4 ZW |
3735 | (define_insn "*nmaddxf4_alts" |
3736 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3737 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3738 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3739 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3740 | ))) | |
655f2eb9 | 3741 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3742 | "" |
aebf2462 | 3743 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3744 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3745 | |
52ad4d7b ZW |
3746 | (define_insn "*nmaddxf4_truncsf_alts" |
3747 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3748 | (float_truncate:SF | |
3749 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
3750 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3751 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3752 | )))) | |
3753 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3754 | "" | |
3755 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
3756 | [(set_attr "itanium_class" "fmac")]) | |
3757 | ||
02befdf4 | 3758 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
3759 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3760 | (float_truncate:DF | |
52ad4d7b ZW |
3761 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3762 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3763 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3764 | )))) | |
26102535 | 3765 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3766 | "" |
aebf2462 | 3767 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3768 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3769 | |
02befdf4 ZW |
3770 | (define_expand "divxf3" |
3771 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
3772 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
3773 | (match_operand:XF 2 "fr_register_operand" "")))] | |
3774 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 RH |
3775 | { |
3776 | rtx insn; | |
dbdd120f | 3777 | if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT) |
02befdf4 | 3778 | insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]); |
26102535 | 3779 | else |
02befdf4 | 3780 | insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]); |
26102535 RH |
3781 | emit_insn (insn); |
3782 | DONE; | |
1d5d7a21 | 3783 | }) |
26102535 | 3784 | |
02befdf4 ZW |
3785 | (define_insn_and_split "divxf3_internal_lat" |
3786 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
3787 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
3788 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
3789 | (clobber (match_scratch:XF 3 "=&f")) | |
3790 | (clobber (match_scratch:XF 4 "=&f")) | |
3791 | (clobber (match_scratch:XF 5 "=&f")) | |
3792 | (clobber (match_scratch:XF 6 "=&f")) | |
f2f90c63 | 3793 | (clobber (match_scratch:BI 7 "=c"))] |
dbdd120f | 3794 | "TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT" |
26102535 RH |
3795 | "#" |
3796 | "&& reload_completed" | |
02befdf4 | 3797 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
3798 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
3799 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3800 | (use (const_int 0))]) |
26102535 RH |
3801 | (cond_exec (ne (match_dup 7) (const_int 0)) |
3802 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3803 | (minus:XF (match_dup 8) |
3804 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
3805 | (use (const_int 1))])) |
3806 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 3807 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
3808 | (use (const_int 1))])) |
3809 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 3810 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3811 | (use (const_int 1))])) |
3812 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3813 | (parallel [(set (match_dup 6) | |
02befdf4 | 3814 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
3815 | (match_dup 3))) |
3816 | (use (const_int 1))])) | |
3817 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3818 | (parallel [(set (match_dup 3) | |
02befdf4 | 3819 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
26102535 RH |
3820 | (match_dup 3))) |
3821 | (use (const_int 1))])) | |
3822 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3823 | (parallel [(set (match_dup 5) | |
02befdf4 | 3824 | (plus:XF (mult:XF (match_dup 6) (match_dup 0)) |
26102535 RH |
3825 | (match_dup 0))) |
3826 | (use (const_int 1))])) | |
3827 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3828 | (parallel [(set (match_dup 0) | |
02befdf4 | 3829 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3830 | (match_dup 0))) |
3831 | (use (const_int 1))])) | |
3832 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3833 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3834 | (minus:XF (match_dup 1) |
3835 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
3836 | (use (const_int 1))])) |
3837 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3838 | (parallel [(set (match_dup 3) | |
02befdf4 | 3839 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
3840 | (match_dup 4))) |
3841 | (use (const_int 1))])) | |
3842 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3843 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3844 | (minus:XF (match_dup 8) |
3845 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
3846 | (use (const_int 1))])) |
3847 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3848 | (parallel [(set (match_dup 0) | |
02befdf4 | 3849 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
3850 | (match_dup 0))) |
3851 | (use (const_int 1))])) | |
3852 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3853 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3854 | (minus:XF (match_dup 1) |
3855 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
3856 | (use (const_int 1))])) |
3857 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3858 | (set (match_dup 0) | |
02befdf4 | 3859 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
3860 | (match_dup 3)))) |
3861 | ] | |
02befdf4 | 3862 | "operands[8] = CONST1_RTX (XFmode);" |
26102535 RH |
3863 | [(set_attr "predicable" "no")]) |
3864 | ||
02befdf4 ZW |
3865 | (define_insn_and_split "divxf3_internal_thr" |
3866 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
3867 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
3868 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
3869 | (clobber (match_scratch:XF 3 "=&f")) | |
3870 | (clobber (match_scratch:XF 4 "=&f")) | |
f2f90c63 | 3871 | (clobber (match_scratch:BI 5 "=c"))] |
dbdd120f | 3872 | "TARGET_INLINE_FLOAT_DIV == INL_MAX_THR" |
26102535 RH |
3873 | "#" |
3874 | "&& reload_completed" | |
02befdf4 | 3875 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
3876 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
3877 | UNSPEC_FR_RECIP_APPROX)) | |
4a36a3f1 | 3878 | (use (const_int 0))]) |
26102535 RH |
3879 | (cond_exec (ne (match_dup 5) (const_int 0)) |
3880 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3881 | (minus:XF (match_dup 6) |
3882 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
3883 | (use (const_int 1))])) |
3884 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3885 | (parallel [(set (match_dup 4) | |
02befdf4 | 3886 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
3887 | (match_dup 0))) |
3888 | (use (const_int 1))])) | |
3889 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3890 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3891 | (use (const_int 1))])) |
3892 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3893 | (parallel [(set (match_dup 3) | |
02befdf4 | 3894 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
26102535 RH |
3895 | (match_dup 4))) |
3896 | (use (const_int 1))])) | |
3897 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 3898 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
3899 | (use (const_int 1))])) |
3900 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3901 | (parallel [(set (match_dup 0) | |
52ad4d7b ZW |
3902 | (minus:XF (match_dup 6) |
3903 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
3904 | (use (const_int 1))])) |
3905 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3906 | (parallel [(set (match_dup 0) | |
02befdf4 | 3907 | (plus:XF (mult:XF (match_dup 0) (match_dup 3)) |
26102535 RH |
3908 | (match_dup 3))) |
3909 | (use (const_int 1))])) | |
3910 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3911 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3912 | (minus:XF (match_dup 1) |
3913 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
3914 | (use (const_int 1))])) |
3915 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3916 | (parallel [(set (match_dup 3) | |
02befdf4 | 3917 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
3918 | (match_dup 4))) |
3919 | (use (const_int 1))])) | |
3920 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3921 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3922 | (minus:XF (match_dup 6) |
3923 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
3924 | (use (const_int 1))])) |
3925 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3926 | (parallel [(set (match_dup 0) | |
02befdf4 | 3927 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
3928 | (match_dup 0))) |
3929 | (use (const_int 1))])) | |
3930 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3931 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3932 | (minus:XF (match_dup 1) |
3933 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
3934 | (use (const_int 1))])) |
3935 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3936 | (set (match_dup 0) | |
02befdf4 | 3937 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
3938 | (match_dup 3)))) |
3939 | ] | |
02befdf4 | 3940 | "operands[6] = CONST1_RTX (XFmode);" |
26102535 RH |
3941 | [(set_attr "predicable" "no")]) |
3942 | ||
b38ba463 ZW |
3943 | ;; Inline square root. |
3944 | ||
3945 | (define_expand "sqrtxf2" | |
3946 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
3947 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
3948 | "TARGET_INLINE_SQRT" | |
3949 | { | |
3950 | rtx insn; | |
b38ba463 | 3951 | #if 0 |
e820471b | 3952 | if (TARGET_INLINE_SQRT == INL_MIN_LAT) |
b38ba463 | 3953 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); |
e820471b | 3954 | else |
b38ba463 | 3955 | #else |
e820471b | 3956 | gcc_assert (TARGET_INLINE_SQRT != INL_MIN_LAT); |
b38ba463 | 3957 | #endif |
e820471b | 3958 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); |
b38ba463 ZW |
3959 | emit_insn (insn); |
3960 | DONE; | |
3961 | }) | |
3962 | ||
3963 | ;; Latency-optimized square root. | |
3964 | ;; FIXME: Implement. | |
3965 | ||
3966 | ;; Throughput-optimized square root. | |
3967 | ||
3968 | (define_insn_and_split "sqrtxf2_internal_thr" | |
3969 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
3970 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
3971 | ;; Register r2 in optimization guide. | |
3972 | (clobber (match_scratch:DI 2 "=r")) | |
3973 | ;; Register f8 in optimization guide | |
3974 | (clobber (match_scratch:XF 3 "=&f")) | |
3975 | ;; Register f9 in optimization guide | |
3976 | (clobber (match_scratch:XF 4 "=&f")) | |
3977 | ;; Register f10 in optimization guide | |
3978 | (clobber (match_scratch:XF 5 "=&f")) | |
3979 | ;; Register f11 in optimization guide | |
3980 | (clobber (match_scratch:XF 6 "=&f")) | |
3981 | ;; Register p6 in optimization guide. | |
3982 | (clobber (match_scratch:BI 7 "=c"))] | |
dbdd120f | 3983 | "TARGET_INLINE_SQRT == INL_MAX_THR" |
b38ba463 ZW |
3984 | "#" |
3985 | "&& reload_completed" | |
3986 | [ ;; exponent of +1/2 in r2 | |
3987 | (set (match_dup 2) (const_int 65534)) | |
3988 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
3989 | (set (match_dup 3) | |
3990 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3991 | ;; Step 1 | |
3992 | ;; y0 = 1/sqrt(a) in f7 | |
3993 | (parallel [(set (match_dup 8) | |
3994 | (div:XF (const_int 1) | |
3995 | (sqrt:XF (match_dup 9)))) | |
3996 | (set (match_dup 7) | |
3997 | (unspec:BI [(match_dup 9)] | |
3998 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3999 | (use (const_int 0))]) | |
4000 | ;; Step 2 | |
4001 | ;; H0 = 1/2 * y0 in f9 | |
4002 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4003 | (parallel [(set (match_dup 4) | |
4004 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4005 | (match_dup 10))) | |
4006 | (use (const_int 1))])) | |
4007 | ;; Step 3 | |
4008 | ;; S0 = a * y0 in f7 | |
4009 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4010 | (parallel [(set (match_dup 8) | |
4011 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4012 | (match_dup 10))) | |
4013 | (use (const_int 1))])) | |
4014 | ;; Step 4 | |
4015 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4016 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4017 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4018 | (minus:XF (match_dup 3) |
4019 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4020 | (use (const_int 1))])) |
4021 | ;; Step 5 | |
4022 | ;; H1 = H0 + d0 * H0 in f9 | |
4023 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4024 | (parallel [(set (match_dup 4) | |
4025 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4026 | (match_dup 4))) | |
4027 | (use (const_int 1))])) | |
4028 | ;; Step 6 | |
4029 | ;; S1 = S0 + d0 * S0 in f7 | |
4030 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4031 | (parallel [(set (match_dup 8) | |
4032 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4033 | (match_dup 8))) | |
4034 | (use (const_int 1))])) | |
4035 | ;; Step 7 | |
4036 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4037 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4038 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4039 | (minus:XF (match_dup 3) |
4040 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4041 | (use (const_int 1))])) |
4042 | ;; Step 8 | |
4043 | ;; H2 = H1 + d1 * H1 in f9 | |
4044 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4045 | (parallel [(set (match_dup 4) | |
4046 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4047 | (match_dup 4))) | |
4048 | (use (const_int 1))])) | |
4049 | ;; Step 9 | |
4050 | ;; S2 = S1 + d1 * S1 in f7 | |
4051 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4052 | (parallel [(set (match_dup 8) | |
4053 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4054 | (match_dup 8))) | |
4055 | (use (const_int 1))])) | |
4056 | ;; Step 10 | |
4057 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4058 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4059 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4060 | (minus:XF (match_dup 3) |
4061 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4062 | (use (const_int 1))])) |
4063 | ;; Step 11 | |
4064 | ;; e2 = a - S2 * S2 in f8 | |
4065 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4066 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4067 | (minus:XF (match_dup 9) |
4068 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4069 | (use (const_int 1))])) |
4070 | ;; Step 12 | |
4071 | ;; S3 = S2 + e2 * H2 in f7 | |
4072 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4073 | (parallel [(set (match_dup 8) | |
4074 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4075 | (match_dup 8))) | |
4076 | (use (const_int 1))])) | |
4077 | ;; Step 13 | |
4078 | ;; H3 = H2 + d2 * H2 in f9 | |
4079 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4080 | (parallel [(set (match_dup 4) | |
4081 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4082 | (match_dup 4))) | |
4083 | (use (const_int 1))])) | |
4084 | ;; Step 14 | |
4085 | ;; e3 = a - S3 * S3 in f8 | |
4086 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4087 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4088 | (minus:XF (match_dup 9) |
4089 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4090 | (use (const_int 1))])) |
4091 | ;; Step 15 | |
4092 | ;; S = S3 + e3 * H3 in f7 | |
4093 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4094 | (parallel [(set (match_dup 0) | |
4095 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4096 | (match_dup 8))) | |
4097 | (use (const_int 0))]))] | |
4098 | { | |
4099 | /* Generate 82-bit versions of the input and output operands. */ | |
4100 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4101 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4102 | /* Generate required floating-point constants. */ | |
4103 | operands[10] = CONST0_RTX (XFmode); | |
4104 | } | |
4105 | [(set_attr "predicable" "no")]) | |
4106 | ||
26102535 RH |
4107 | ;; ??? frcpa works like cmp.foo.unc. |
4108 | ||
655f2eb9 | 4109 | (define_insn "*recip_approx" |
02befdf4 ZW |
4110 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
4111 | (div:XF (const_int 1) | |
4112 | (match_operand:XF 3 "fr_register_operand" "f"))) | |
f2f90c63 | 4113 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4114 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4115 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4116 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4117 | "" |
655f2eb9 | 4118 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4119 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4120 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4121 | \f |
4122 | ;; :::::::::::::::::::: | |
4123 | ;; :: | |
4124 | ;; :: 32 bit Integer Shifts and Rotates | |
4125 | ;; :: | |
4126 | ;; :::::::::::::::::::: | |
4127 | ||
9c668921 | 4128 | (define_expand "ashlsi3" |
0551c32d RH |
4129 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4130 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4131 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4132 | "" |
9c668921 RH |
4133 | { |
4134 | if (GET_CODE (operands[2]) != CONST_INT) | |
4135 | { | |
4136 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4137 | we've got to get rid of stray bits outside the SImode register. */ | |
4138 | rtx subshift = gen_reg_rtx (DImode); | |
4139 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4140 | operands[2] = subshift; | |
4141 | } | |
1d5d7a21 | 4142 | }) |
9c668921 RH |
4143 | |
4144 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4145 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4146 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4147 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4148 | "" |
041f25e6 RH |
4149 | "@ |
4150 | shladd %0 = %1, %2, r0 | |
4151 | dep.z %0 = %1, %2, %E2 | |
4152 | shl %0 = %1, %2" | |
52e12ad0 | 4153 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4154 | |
4155 | (define_expand "ashrsi3" | |
0551c32d RH |
4156 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4157 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4158 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4159 | "" |
c65ebc55 | 4160 | { |
041f25e6 RH |
4161 | rtx subtarget = gen_reg_rtx (DImode); |
4162 | if (GET_CODE (operands[2]) == CONST_INT) | |
4163 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4164 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4165 | else | |
4166 | { | |
9c668921 | 4167 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4168 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4169 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4170 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4171 | } |
4172 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4173 | DONE; | |
1d5d7a21 | 4174 | }) |
c65ebc55 | 4175 | |
c65ebc55 | 4176 | (define_expand "lshrsi3" |
0551c32d RH |
4177 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4178 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4179 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4180 | "" |
c65ebc55 | 4181 | { |
041f25e6 RH |
4182 | rtx subtarget = gen_reg_rtx (DImode); |
4183 | if (GET_CODE (operands[2]) == CONST_INT) | |
4184 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4185 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4186 | else | |
4187 | { | |
9c668921 | 4188 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4189 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4190 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4191 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4192 | } |
4193 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4194 | DONE; | |
1d5d7a21 | 4195 | }) |
c65ebc55 | 4196 | |
c65ebc55 | 4197 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4198 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4199 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4200 | |
4201 | (define_expand "rotrsi3" | |
66db6b45 RH |
4202 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4203 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4204 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4205 | "" | |
66db6b45 RH |
4206 | { |
4207 | if (GET_MODE (operands[2]) != VOIDmode) | |
4208 | { | |
4209 | rtx tmp = gen_reg_rtx (DImode); | |
4210 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4211 | operands[2] = tmp; | |
4212 | } | |
1d5d7a21 | 4213 | }) |
66db6b45 RH |
4214 | |
4215 | (define_insn_and_split "*rotrsi3_internal" | |
4216 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4217 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4218 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4219 | "" | |
4220 | "#" | |
4221 | "reload_completed" | |
c65ebc55 | 4222 | [(set (match_dup 3) |
66db6b45 | 4223 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4224 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4225 | (set (match_dup 3) | |
66db6b45 RH |
4226 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4227 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4228 | ||
4229 | (define_expand "rotlsi3" | |
4230 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4231 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4232 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4233 | "" |
c65ebc55 JW |
4234 | { |
4235 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4236 | { |
4237 | rtx tmp = gen_reg_rtx (SImode); | |
4238 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4239 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4240 | DONE; | |
4241 | } | |
1d5d7a21 | 4242 | }) |
66db6b45 RH |
4243 | |
4244 | (define_insn_and_split "*rotlsi3_internal" | |
4245 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4246 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4247 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4248 | "" | |
4249 | "#" | |
4250 | "reload_completed" | |
4251 | [(set (match_dup 3) | |
4252 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4253 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4254 | (set (match_dup 3) | |
4255 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4256 | { |
4257 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4258 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
4259 | }) | |
c65ebc55 JW |
4260 | \f |
4261 | ;; :::::::::::::::::::: | |
4262 | ;; :: | |
4263 | ;; :: 64 bit Integer Shifts and Rotates | |
4264 | ;; :: | |
4265 | ;; :::::::::::::::::::: | |
4266 | ||
4267 | (define_insn "ashldi3" | |
52e12ad0 BS |
4268 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4269 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4270 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4271 | "" |
041f25e6 RH |
4272 | "@ |
4273 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4274 | shl %0 = %1, %2 |
041f25e6 | 4275 | shl %0 = %1, %2" |
52e12ad0 | 4276 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4277 | |
4278 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4279 | ||
4280 | (define_insn "*shladd" | |
0551c32d RH |
4281 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4282 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4283 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4284 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4285 | "" |
4286 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4287 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4288 | |
4289 | ;; This can be created by register elimination if operand3 of shladd is an | |
4290 | ;; eliminable register or has reg_equiv_constant set. | |
4291 | ||
4292 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4293 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4294 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4295 | ;; incorrectly. | |
4296 | ||
5527bf14 | 4297 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4298 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4299 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4300 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4301 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4302 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4303 | "reload_in_progress" | |
e820471b | 4304 | "* gcc_unreachable ();" |
c65ebc55 JW |
4305 | "reload_completed" |
4306 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4307 | (match_dup 3))) | |
c65ebc55 | 4308 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4309 | "" |
52e12ad0 | 4310 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4311 | |
4312 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4313 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4314 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4315 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4316 | "" |
52e12ad0 BS |
4317 | "@ |
4318 | shr %0 = %1, %2 | |
4319 | shr %0 = %1, %2" | |
4320 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4321 | |
4322 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4323 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4324 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4325 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4326 | "" |
52e12ad0 BS |
4327 | "@ |
4328 | shr.u %0 = %1, %2 | |
4329 | shr.u %0 = %1, %2" | |
4330 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4331 | |
4332 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4333 | ;; will load the operand into a register and call the pattern if the predicate | |
4334 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4335 | ;; verify that we have an appropriate constant in the expander. | |
4336 | ||
4337 | (define_expand "rotrdi3" | |
0551c32d RH |
4338 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4339 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4340 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4341 | "" | |
c65ebc55 JW |
4342 | { |
4343 | if (! shift_count_operand (operands[2], DImode)) | |
4344 | FAIL; | |
1d5d7a21 | 4345 | }) |
c65ebc55 JW |
4346 | |
4347 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4348 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4349 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4350 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4351 | "" | |
4352 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4353 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4354 | |
66db6b45 RH |
4355 | (define_expand "rotldi3" |
4356 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4357 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4358 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4359 | "" | |
66db6b45 RH |
4360 | { |
4361 | if (! shift_count_operand (operands[2], DImode)) | |
4362 | FAIL; | |
1d5d7a21 | 4363 | }) |
66db6b45 RH |
4364 | |
4365 | (define_insn "*rotldi3_internal" | |
4366 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4367 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4368 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4369 | "" | |
4370 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4371 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4372 | \f |
4373 | ;; :::::::::::::::::::: | |
4374 | ;; :: | |
4375 | ;; :: 128 bit Integer Shifts and Rotates | |
4376 | ;; :: | |
4377 | ;; :::::::::::::::::::: | |
4378 | ||
16d8386b JB |
4379 | (define_expand "ashlti3" |
4380 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4381 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "") | |
4382 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4383 | "" | |
4384 | { | |
4385 | if (!dshift_count_operand (operands[2], DImode)) | |
4386 | FAIL; | |
4387 | }) | |
4388 | ||
4389 | (define_insn_and_split "*ashlti3_internal" | |
4390 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") | |
4391 | (ashift:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4392 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4393 | "" | |
4394 | "#" | |
4395 | "reload_completed" | |
4396 | [(const_int 0)] | |
4397 | { | |
4398 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4399 | rtx rl = gen_lowpart (DImode, operands[0]); | |
4400 | rtx rh = gen_highpart (DImode, operands[0]); | |
4401 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4402 | rtx shiftlo = GEN_INT (shift & 63); | |
4403 | ||
4404 | if (shift & 64) | |
4405 | { | |
4406 | emit_move_insn (rl, const0_rtx); | |
4407 | if (shift & 63) | |
4408 | emit_insn (gen_ashldi3 (rh, lo, shiftlo)); | |
4409 | else | |
4410 | emit_move_insn (rh, lo); | |
4411 | } | |
4412 | else | |
4413 | { | |
4414 | rtx hi = gen_highpart (DImode, operands[1]); | |
4415 | ||
4416 | emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63))); | |
4417 | emit_insn (gen_ashldi3 (rl, lo, shiftlo)); | |
4418 | } | |
4419 | DONE; | |
4420 | }) | |
4421 | ||
f526a3c8 RH |
4422 | (define_expand "ashrti3" |
4423 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4424 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4425 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4426 | "" | |
4427 | { | |
4428 | if (!dshift_count_operand (operands[2], DImode)) | |
4429 | FAIL; | |
4430 | }) | |
4431 | ||
4432 | (define_insn_and_split "*ashrti3_internal" | |
16d8386b | 4433 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4434 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4435 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4436 | "" | |
4437 | "#" | |
4438 | "reload_completed" | |
4439 | [(const_int 0)] | |
4440 | { | |
4441 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4442 | rtx rl = gen_lowpart (DImode, operands[0]); |
4443 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4444 | rtx hi = gen_highpart (DImode, operands[1]); |
4445 | rtx shiftlo = GEN_INT (shift & 63); | |
4446 | ||
4447 | if (shift & 64) | |
4448 | { | |
16d8386b JB |
4449 | if (shift & 63) |
4450 | emit_insn (gen_ashrdi3 (rl, hi, shiftlo)); | |
4451 | else | |
4452 | emit_move_insn (rl, hi); | |
4453 | emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63))); | |
f526a3c8 RH |
4454 | } |
4455 | else | |
4456 | { | |
16d8386b JB |
4457 | rtx lo = gen_lowpart (DImode, operands[1]); |
4458 | ||
4459 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4460 | emit_insn (gen_ashrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4461 | } |
4462 | DONE; | |
4463 | }) | |
4464 | ||
4465 | (define_expand "lshrti3" | |
4466 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4467 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4468 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4469 | "" | |
4470 | { | |
4471 | if (!dshift_count_operand (operands[2], DImode)) | |
4472 | FAIL; | |
4473 | }) | |
4474 | ||
4475 | (define_insn_and_split "*lshrti3_internal" | |
16d8386b | 4476 | [(set (match_operand:TI 0 "gr_register_operand" "=&r") |
f526a3c8 RH |
4477 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") |
4478 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4479 | "" | |
4480 | "#" | |
4481 | "reload_completed" | |
4482 | [(const_int 0)] | |
4483 | { | |
4484 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
16d8386b JB |
4485 | rtx rl = gen_lowpart (DImode, operands[0]); |
4486 | rtx rh = gen_highpart (DImode, operands[0]); | |
f526a3c8 RH |
4487 | rtx hi = gen_highpart (DImode, operands[1]); |
4488 | rtx shiftlo = GEN_INT (shift & 63); | |
4489 | ||
4490 | if (shift & 64) | |
4491 | { | |
16d8386b JB |
4492 | if (shift & 63) |
4493 | emit_insn (gen_lshrdi3 (rl, hi, shiftlo)); | |
4494 | else | |
4495 | emit_move_insn (rl, hi); | |
4496 | emit_move_insn (rh, const0_rtx); | |
f526a3c8 RH |
4497 | } |
4498 | else | |
4499 | { | |
16d8386b JB |
4500 | rtx lo = gen_lowpart (DImode, operands[1]); |
4501 | ||
4502 | emit_insn (gen_shrp (rl, hi, lo, shiftlo)); | |
4503 | emit_insn (gen_lshrdi3 (rh, hi, shiftlo)); | |
f526a3c8 RH |
4504 | } |
4505 | DONE; | |
4506 | }) | |
4507 | ||
4508 | (define_insn "shrp" | |
4509 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4510 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4511 | (match_operand:DI 2 "gr_register_operand" "r") | |
4512 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4513 | UNSPEC_SHRP))] | |
4514 | "" | |
4515 | "shrp %0 = %1, %2, %3" | |
4516 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4517 | \f |
4518 | ;; :::::::::::::::::::: | |
4519 | ;; :: | |
058557c4 | 4520 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
4521 | ;; :: |
4522 | ;; :::::::::::::::::::: | |
4523 | ||
4524 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4525 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4526 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4527 | ;; This doesn't work for unary logical operations, because we don't call | |
4528 | ;; apply_distributive_law for them. | |
4529 | ||
4530 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4531 | ;; apply_distributive_law. We get inefficient code for | |
4532 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4533 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4534 | ;; (zero_extend (and (not A) B)) in combine. | |
4535 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4536 | ;; one_cmplsi2 pattern. | |
4537 | ||
058557c4 | 4538 | (define_insn "one_cmplsi2" |
0551c32d RH |
4539 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4540 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4541 | "" |
4542 | "andcm %0 = -1, %1" | |
52e12ad0 | 4543 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4544 | \f |
4545 | ;; :::::::::::::::::::: | |
4546 | ;; :: | |
058557c4 | 4547 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
4548 | ;; :: |
4549 | ;; :::::::::::::::::::: | |
4550 | ||
4551 | (define_insn "anddi3" | |
0551c32d RH |
4552 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4553 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4554 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4555 | "" |
4556 | "@ | |
4557 | and %0 = %2, %1 | |
aebf2462 | 4558 | fand %0 = %2, %1" |
52e12ad0 | 4559 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4560 | |
4561 | (define_insn "*andnot" | |
0551c32d RH |
4562 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4563 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4564 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4565 | "" |
4566 | "@ | |
4567 | andcm %0 = %2, %1 | |
aebf2462 | 4568 | fandcm %0 = %2, %1" |
52e12ad0 | 4569 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4570 | |
4571 | (define_insn "iordi3" | |
0551c32d RH |
4572 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4573 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4574 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4575 | "" |
4576 | "@ | |
4577 | or %0 = %2, %1 | |
aebf2462 | 4578 | for %0 = %2, %1" |
52e12ad0 | 4579 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4580 | |
4581 | (define_insn "xordi3" | |
0551c32d RH |
4582 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4583 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4584 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4585 | "" |
4586 | "@ | |
4587 | xor %0 = %2, %1 | |
aebf2462 | 4588 | fxor %0 = %2, %1" |
52e12ad0 | 4589 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4590 | |
4591 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4592 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4593 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4594 | "" |
4595 | "andcm %0 = -1, %1" | |
52e12ad0 | 4596 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4597 | \f |
4598 | ;; :::::::::::::::::::: | |
4599 | ;; :: | |
4600 | ;; :: Comparisons | |
4601 | ;; :: | |
4602 | ;; :::::::::::::::::::: | |
4603 | ||
f2f90c63 RH |
4604 | (define_expand "cmpbi" |
4605 | [(set (cc0) | |
4606 | (compare (match_operand:BI 0 "register_operand" "") | |
4607 | (match_operand:BI 1 "const_int_operand" "")))] | |
4608 | "" | |
f2f90c63 RH |
4609 | { |
4610 | ia64_compare_op0 = operands[0]; | |
4611 | ia64_compare_op1 = operands[1]; | |
4612 | DONE; | |
1d5d7a21 | 4613 | }) |
f2f90c63 | 4614 | |
c65ebc55 JW |
4615 | (define_expand "cmpsi" |
4616 | [(set (cc0) | |
0551c32d RH |
4617 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4618 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4619 | "" |
c65ebc55 JW |
4620 | { |
4621 | ia64_compare_op0 = operands[0]; | |
4622 | ia64_compare_op1 = operands[1]; | |
4623 | DONE; | |
1d5d7a21 | 4624 | }) |
c65ebc55 JW |
4625 | |
4626 | (define_expand "cmpdi" | |
4627 | [(set (cc0) | |
0551c32d RH |
4628 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4629 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4630 | "" |
c65ebc55 JW |
4631 | { |
4632 | ia64_compare_op0 = operands[0]; | |
4633 | ia64_compare_op1 = operands[1]; | |
4634 | DONE; | |
1d5d7a21 | 4635 | }) |
c65ebc55 JW |
4636 | |
4637 | (define_expand "cmpsf" | |
4638 | [(set (cc0) | |
0551c32d RH |
4639 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4640 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4641 | "" |
c65ebc55 JW |
4642 | { |
4643 | ia64_compare_op0 = operands[0]; | |
4644 | ia64_compare_op1 = operands[1]; | |
4645 | DONE; | |
1d5d7a21 | 4646 | }) |
c65ebc55 JW |
4647 | |
4648 | (define_expand "cmpdf" | |
4649 | [(set (cc0) | |
0551c32d RH |
4650 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4651 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4652 | "" |
c65ebc55 JW |
4653 | { |
4654 | ia64_compare_op0 = operands[0]; | |
4655 | ia64_compare_op1 = operands[1]; | |
4656 | DONE; | |
1d5d7a21 | 4657 | }) |
c65ebc55 | 4658 | |
02befdf4 | 4659 | (define_expand "cmpxf" |
c65ebc55 | 4660 | [(set (cc0) |
02befdf4 ZW |
4661 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
4662 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
4663 | "" | |
c65ebc55 JW |
4664 | { |
4665 | ia64_compare_op0 = operands[0]; | |
4666 | ia64_compare_op1 = operands[1]; | |
4667 | DONE; | |
1d5d7a21 | 4668 | }) |
c65ebc55 | 4669 | |
24ea7948 ZW |
4670 | (define_expand "cmptf" |
4671 | [(set (cc0) | |
4672 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
4673 | (match_operand:TF 1 "gr_register_operand" "")))] | |
4674 | "TARGET_HPUX" | |
4675 | { | |
4676 | ia64_compare_op0 = operands[0]; | |
4677 | ia64_compare_op1 = operands[1]; | |
4678 | DONE; | |
4679 | }) | |
4680 | ||
c65ebc55 | 4681 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4682 | [(set (match_operand:BI 0 "register_operand" "=c") |
4683 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4684 | [(match_operand:SI 2 "gr_register_operand" "r") |
4685 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4686 | "" |
4687 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4688 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4689 | |
18a3c539 JW |
4690 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4691 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4692 | ||
c65ebc55 | 4693 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4694 | [(set (match_operand:BI 0 "register_operand" "=c") |
4695 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4696 | [(match_operand:SI 2 "gr_register_operand" "r") |
4697 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4698 | "" |
18a3c539 | 4699 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4700 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4701 | |
4702 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4703 | [(set (match_operand:BI 0 "register_operand" "=c") |
4704 | (match_operator:BI 1 "normal_comparison_operator" | |
4705 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4706 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4707 | "" |
f2f90c63 | 4708 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4709 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4710 | |
18a3c539 JW |
4711 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4712 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4713 | ||
c65ebc55 | 4714 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4715 | [(set (match_operand:BI 0 "register_operand" "=c") |
4716 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4717 | [(match_operand:DI 2 "gr_register_operand" "r") |
4718 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4719 | "" |
18a3c539 | 4720 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4721 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4722 | |
4723 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4724 | [(set (match_operand:BI 0 "register_operand" "=c") |
4725 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4726 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4727 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4728 | "" |
4729 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4730 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4731 | |
4732 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4733 | [(set (match_operand:BI 0 "register_operand" "=c") |
4734 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4735 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4736 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4737 | "" |
4738 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4739 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4740 | |
02befdf4 | 4741 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4742 | [(set (match_operand:BI 0 "register_operand" "=c") |
4743 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4744 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
4745 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
4746 | "" | |
3f622353 | 4747 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4748 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4749 | |
c65ebc55 JW |
4750 | ;; ??? Can this pattern be generated? |
4751 | ||
4752 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4753 | [(set (match_operand:BI 0 "register_operand" "=c") |
4754 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4755 | (const_int 1) |
4756 | (match_operand:DI 2 "immediate_operand" "n")) | |
4757 | (const_int 0)))] | |
4758 | "" | |
4759 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4760 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4761 | |
4762 | (define_insn "*bit_one" | |
f2f90c63 RH |
4763 | [(set (match_operand:BI 0 "register_operand" "=c") |
4764 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4765 | (const_int 1) |
4766 | (match_operand:DI 2 "immediate_operand" "n")) | |
4767 | (const_int 0)))] | |
4768 | "" | |
4769 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4770 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4771 | \f |
4772 | ;; :::::::::::::::::::: | |
4773 | ;; :: | |
4774 | ;; :: Branches | |
4775 | ;; :: | |
4776 | ;; :::::::::::::::::::: | |
4777 | ||
4778 | (define_expand "beq" | |
f2f90c63 RH |
4779 | [(set (pc) |
4780 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4781 | (label_ref (match_operand 0 "" "")) |
4782 | (pc)))] | |
4783 | "" | |
f2f90c63 | 4784 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4785 | |
4786 | (define_expand "bne" | |
f2f90c63 RH |
4787 | [(set (pc) |
4788 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4789 | (label_ref (match_operand 0 "" "")) |
4790 | (pc)))] | |
4791 | "" | |
f2f90c63 | 4792 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4793 | |
4794 | (define_expand "blt" | |
f2f90c63 RH |
4795 | [(set (pc) |
4796 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4797 | (label_ref (match_operand 0 "" "")) |
4798 | (pc)))] | |
4799 | "" | |
f2f90c63 | 4800 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4801 | |
4802 | (define_expand "ble" | |
f2f90c63 RH |
4803 | [(set (pc) |
4804 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4805 | (label_ref (match_operand 0 "" "")) |
4806 | (pc)))] | |
4807 | "" | |
f2f90c63 | 4808 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4809 | |
4810 | (define_expand "bgt" | |
f2f90c63 RH |
4811 | [(set (pc) |
4812 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4813 | (label_ref (match_operand 0 "" "")) |
4814 | (pc)))] | |
4815 | "" | |
f2f90c63 | 4816 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4817 | |
4818 | (define_expand "bge" | |
f2f90c63 RH |
4819 | [(set (pc) |
4820 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4821 | (label_ref (match_operand 0 "" "")) |
4822 | (pc)))] | |
4823 | "" | |
f2f90c63 | 4824 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4825 | |
4826 | (define_expand "bltu" | |
f2f90c63 RH |
4827 | [(set (pc) |
4828 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4829 | (label_ref (match_operand 0 "" "")) |
4830 | (pc)))] | |
4831 | "" | |
f2f90c63 | 4832 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4833 | |
4834 | (define_expand "bleu" | |
f2f90c63 RH |
4835 | [(set (pc) |
4836 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4837 | (label_ref (match_operand 0 "" "")) |
4838 | (pc)))] | |
4839 | "" | |
f2f90c63 | 4840 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4841 | |
4842 | (define_expand "bgtu" | |
f2f90c63 RH |
4843 | [(set (pc) |
4844 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4845 | (label_ref (match_operand 0 "" "")) |
4846 | (pc)))] | |
4847 | "" | |
f2f90c63 | 4848 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4849 | |
4850 | (define_expand "bgeu" | |
f2f90c63 RH |
4851 | [(set (pc) |
4852 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4853 | (label_ref (match_operand 0 "" "")) |
4854 | (pc)))] | |
4855 | "" | |
f2f90c63 | 4856 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4857 | |
e57b9d65 | 4858 | (define_expand "bunordered" |
f2f90c63 RH |
4859 | [(set (pc) |
4860 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4861 | (label_ref (match_operand 0 "" "")) |
4862 | (pc)))] | |
4863 | "" | |
f2f90c63 | 4864 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4865 | |
4866 | (define_expand "bordered" | |
f2f90c63 RH |
4867 | [(set (pc) |
4868 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4869 | (label_ref (match_operand 0 "" "")) |
4870 | (pc)))] | |
4871 | "" | |
f2f90c63 | 4872 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4873 | |
6b6c1201 | 4874 | (define_insn "*br_true" |
c65ebc55 | 4875 | [(set (pc) |
6b6c1201 | 4876 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4877 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4878 | (const_int 0)]) |
4879 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4880 | (pc)))] |
4881 | "" | |
85548039 | 4882 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4883 | [(set_attr "itanium_class" "br") |
e5bde68a | 4884 | (set_attr "predicable" "no")]) |
c65ebc55 | 4885 | |
6b6c1201 | 4886 | (define_insn "*br_false" |
c65ebc55 | 4887 | [(set (pc) |
6b6c1201 | 4888 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4889 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4890 | (const_int 0)]) |
c65ebc55 | 4891 | (pc) |
6b6c1201 | 4892 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4893 | "" |
85548039 | 4894 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4895 | [(set_attr "itanium_class" "br") |
e5bde68a | 4896 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4897 | \f |
4898 | ;; :::::::::::::::::::: | |
4899 | ;; :: | |
5527bf14 RH |
4900 | ;; :: Counted loop operations |
4901 | ;; :: | |
4902 | ;; :::::::::::::::::::: | |
4903 | ||
4904 | (define_expand "doloop_end" | |
4905 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4906 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4907 | (use (match_operand 2 "" "")) ; max iterations | |
4908 | (use (match_operand 3 "" "")) ; loop level | |
4909 | (use (match_operand 4 "" ""))] ; label | |
4910 | "" | |
5527bf14 RH |
4911 | { |
4912 | /* Only use cloop on innermost loops. */ | |
4913 | if (INTVAL (operands[3]) > 1) | |
4914 | FAIL; | |
4915 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4916 | operands[4])); | |
4917 | DONE; | |
1d5d7a21 | 4918 | }) |
5527bf14 RH |
4919 | |
4920 | (define_insn "doloop_end_internal" | |
4921 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4922 | (const_int 0)) | |
4923 | (label_ref (match_operand 1 "" "")) | |
4924 | (pc))) | |
4925 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
4926 | (plus:DI (match_dup 0) (const_int -1)) |
4927 | (match_dup 0)))] | |
5527bf14 RH |
4928 | "" |
4929 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4930 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4931 | (set_attr "predicable" "no")]) |
4932 | \f | |
4933 | ;; :::::::::::::::::::: | |
4934 | ;; :: | |
c65ebc55 JW |
4935 | ;; :: Set flag operations |
4936 | ;; :: | |
4937 | ;; :::::::::::::::::::: | |
4938 | ||
4939 | (define_expand "seq" | |
f2f90c63 | 4940 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4941 | "" |
f2f90c63 | 4942 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4943 | |
4944 | (define_expand "sne" | |
f2f90c63 | 4945 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4946 | "" |
f2f90c63 | 4947 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4948 | |
4949 | (define_expand "slt" | |
f2f90c63 | 4950 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4951 | "" |
f2f90c63 | 4952 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4953 | |
4954 | (define_expand "sle" | |
f2f90c63 | 4955 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4956 | "" |
f2f90c63 | 4957 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4958 | |
4959 | (define_expand "sgt" | |
f2f90c63 | 4960 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4961 | "" |
f2f90c63 | 4962 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4963 | |
4964 | (define_expand "sge" | |
f2f90c63 | 4965 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4966 | "" |
f2f90c63 | 4967 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4968 | |
4969 | (define_expand "sltu" | |
f2f90c63 | 4970 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4971 | "" |
f2f90c63 | 4972 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4973 | |
4974 | (define_expand "sleu" | |
f2f90c63 | 4975 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4976 | "" |
f2f90c63 | 4977 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4978 | |
4979 | (define_expand "sgtu" | |
f2f90c63 | 4980 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4981 | "" |
f2f90c63 | 4982 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4983 | |
4984 | (define_expand "sgeu" | |
f2f90c63 | 4985 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4986 | "" |
f2f90c63 | 4987 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4988 | |
e57b9d65 | 4989 | (define_expand "sunordered" |
f2f90c63 | 4990 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4991 | "" |
f2f90c63 | 4992 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4993 | |
4994 | (define_expand "sordered" | |
f2f90c63 | 4995 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4996 | "" |
f2f90c63 | 4997 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4998 | |
c65ebc55 JW |
4999 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5000 | ;; efficient than mov/mov/cst/cst. | |
5001 | ||
0551c32d RH |
5002 | (define_insn_and_split "*sne_internal" |
5003 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5004 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5005 | (const_int 0)))] |
5006 | "" | |
5007 | "#" | |
c65ebc55 | 5008 | "reload_completed" |
f2f90c63 RH |
5009 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5010 | (set (match_dup 0) (const_int 1))) | |
5011 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5012 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5013 | "" |
52e12ad0 | 5014 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5015 | |
0551c32d RH |
5016 | (define_insn_and_split "*seq_internal" |
5017 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5018 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5019 | (const_int 0)))] |
5020 | "" | |
5021 | "#" | |
c65ebc55 | 5022 | "reload_completed" |
f2f90c63 RH |
5023 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5024 | (set (match_dup 0) (const_int 0))) | |
5025 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5026 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5027 | "" |
52e12ad0 | 5028 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5029 | \f |
5030 | ;; :::::::::::::::::::: | |
5031 | ;; :: | |
5032 | ;; :: Conditional move instructions. | |
5033 | ;; :: | |
5034 | ;; :::::::::::::::::::: | |
5035 | ||
5036 | ;; ??? Add movXXcc patterns? | |
5037 | ||
c65ebc55 JW |
5038 | ;; |
5039 | ;; DImode if_then_else patterns. | |
5040 | ;; | |
5041 | ||
75cdbeb8 | 5042 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5043 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5044 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5045 | (if_then_else:DI |
f2f90c63 RH |
5046 | (match_operator 4 "predicate_operator" |
5047 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5048 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5049 | (const_int 0)]) |
f2f90c63 | 5050 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5051 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5052 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5053 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5054 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5055 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5056 | { gcc_unreachable (); } |
75cdbeb8 RH |
5057 | [(set_attr "predicable" "no")]) |
5058 | ||
5059 | (define_split | |
f2f90c63 | 5060 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5061 | (if_then_else |
f2f90c63 RH |
5062 | (match_operator 4 "predicate_operator" |
5063 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5064 | (const_int 0)]) |
f2f90c63 RH |
5065 | (match_operand 2 "move_operand" "") |
5066 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5067 | "reload_completed" |
5068 | [(const_int 0)] | |
e5bde68a | 5069 | { |
21515593 RH |
5070 | bool emitted_something = false; |
5071 | rtx dest = operands[0]; | |
5072 | rtx srct = operands[2]; | |
5073 | rtx srcf = operands[3]; | |
5074 | rtx cond = operands[4]; | |
2f937369 | 5075 | |
21515593 | 5076 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5077 | { |
21515593 RH |
5078 | ia64_emit_cond_move (dest, srct, cond); |
5079 | emitted_something = true; | |
e5bde68a | 5080 | } |
21515593 | 5081 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5082 | { |
21515593 RH |
5083 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5084 | VOIDmode, operands[1], const0_rtx); | |
5085 | ia64_emit_cond_move (dest, srcf, cond); | |
5086 | emitted_something = true; | |
3b572406 | 5087 | } |
2f937369 | 5088 | if (! emitted_something) |
f9974026 | 5089 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5090 | DONE; |
1d5d7a21 | 5091 | }) |
c65ebc55 JW |
5092 | |
5093 | ;; Absolute value pattern. | |
5094 | ||
5095 | (define_insn "*absdi2_internal" | |
0551c32d | 5096 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5097 | (if_then_else:DI |
f2f90c63 RH |
5098 | (match_operator 4 "predicate_operator" |
5099 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5100 | (const_int 0)]) |
0551c32d RH |
5101 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5102 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5103 | "" |
e5bde68a | 5104 | "#" |
52e12ad0 | 5105 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5106 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5107 | |
5108 | (define_split | |
5109 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5110 | (if_then_else:DI |
f2f90c63 RH |
5111 | (match_operator 4 "predicate_operator" |
5112 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5113 | (const_int 0)]) |
0551c32d RH |
5114 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5115 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5116 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5117 | [(cond_exec | |
5118 | (match_dup 4) | |
5119 | (set (match_dup 0) | |
5120 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5121 | "") |
5122 | ||
e5bde68a RH |
5123 | (define_split |
5124 | [(set (match_operand:DI 0 "register_operand" "") | |
5125 | (if_then_else:DI | |
f2f90c63 RH |
5126 | (match_operator 4 "predicate_operator" |
5127 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5128 | (const_int 0)]) |
0551c32d RH |
5129 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5130 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5131 | "reload_completed" |
5132 | [(cond_exec | |
5133 | (match_dup 4) | |
5134 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5135 | (cond_exec | |
5136 | (match_dup 5) | |
5137 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5138 | { |
5139 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5140 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5141 | }) |
c65ebc55 JW |
5142 | |
5143 | ;; | |
5144 | ;; SImode if_then_else patterns. | |
5145 | ;; | |
5146 | ||
75cdbeb8 | 5147 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5148 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5149 | (if_then_else:SI |
f2f90c63 RH |
5150 | (match_operator 4 "predicate_operator" |
5151 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5152 | (const_int 0)]) |
f2f90c63 | 5153 | (match_operand:SI 2 "move_operand" |
3b572406 | 5154 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5155 | (match_operand:SI 3 "move_operand" |
3b572406 | 5156 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5157 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5158 | && ia64_move_ok (operands[0], operands[3])" |
e820471b | 5159 | { gcc_unreachable (); } |
3b572406 | 5160 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5161 | |
5162 | (define_insn "*abssi2_internal" | |
0551c32d | 5163 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5164 | (if_then_else:SI |
f2f90c63 RH |
5165 | (match_operator 4 "predicate_operator" |
5166 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5167 | (const_int 0)]) |
0551c32d RH |
5168 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5169 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5170 | "" |
e5bde68a | 5171 | "#" |
52e12ad0 | 5172 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5173 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5174 | |
5175 | (define_split | |
5176 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5177 | (if_then_else:SI |
f2f90c63 RH |
5178 | (match_operator 4 "predicate_operator" |
5179 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5180 | (const_int 0)]) |
0551c32d RH |
5181 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5182 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5183 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5184 | [(cond_exec | |
5185 | (match_dup 4) | |
5186 | (set (match_dup 0) | |
5187 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5188 | "") |
5189 | ||
e5bde68a RH |
5190 | (define_split |
5191 | [(set (match_operand:SI 0 "register_operand" "") | |
5192 | (if_then_else:SI | |
f2f90c63 RH |
5193 | (match_operator 4 "predicate_operator" |
5194 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5195 | (const_int 0)]) |
0551c32d RH |
5196 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5197 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5198 | "reload_completed" |
5199 | [(cond_exec | |
5200 | (match_dup 4) | |
5201 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5202 | (cond_exec | |
5203 | (match_dup 5) | |
5204 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5205 | { |
5206 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5207 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5208 | }) |
e5bde68a | 5209 | |
7dcc803e | 5210 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5211 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5212 | (match_operator:SI 5 "condop_operator" | |
5213 | [(if_then_else:SI | |
5214 | (match_operator 6 "predicate_operator" | |
5215 | [(match_operand:BI 1 "register_operand" "c") | |
5216 | (const_int 0)]) | |
5217 | (match_operand:SI 2 "gr_register_operand" "r") | |
5218 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5219 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5220 | "" | |
5221 | "#" | |
acb0638d BS |
5222 | "reload_completed" |
5223 | [(cond_exec | |
5224 | (match_dup 6) | |
5225 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5226 | (cond_exec | |
5227 | (match_dup 7) | |
5228 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5229 | { |
5230 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5231 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5232 | } |
7dcc803e BS |
5233 | [(set_attr "itanium_class" "ialu") |
5234 | (set_attr "predicable" "no")]) | |
5235 | ||
acb0638d | 5236 | |
7dcc803e | 5237 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5238 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5239 | (match_operator:SI 5 "condop_operator" | |
5240 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5241 | (if_then_else:SI | |
5242 | (match_operator 6 "predicate_operator" | |
5243 | [(match_operand:BI 1 "register_operand" "c") | |
5244 | (const_int 0)]) | |
5245 | (match_operand:SI 2 "gr_register_operand" "r") | |
5246 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5247 | "" | |
5248 | "#" | |
acb0638d BS |
5249 | "reload_completed" |
5250 | [(cond_exec | |
5251 | (match_dup 6) | |
5252 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5253 | (cond_exec | |
5254 | (match_dup 7) | |
5255 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5256 | { |
5257 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5258 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5259 | } |
7dcc803e BS |
5260 | [(set_attr "itanium_class" "ialu") |
5261 | (set_attr "predicable" "no")]) | |
acb0638d | 5262 | |
c65ebc55 JW |
5263 | \f |
5264 | ;; :::::::::::::::::::: | |
5265 | ;; :: | |
5266 | ;; :: Call and branch instructions | |
5267 | ;; :: | |
5268 | ;; :::::::::::::::::::: | |
5269 | ||
5270 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5271 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5272 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5273 | ;; registers used as operands. | |
5274 | ||
5275 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5276 | ;; is supplied for the sake of some RISC machines which need to put this | |
5277 | ;; information into the assembler code; they can put it in the RTL instead of | |
5278 | ;; operand 1. | |
5279 | ||
5280 | (define_expand "call" | |
5281 | [(use (match_operand:DI 0 "" "")) | |
5282 | (use (match_operand 1 "" "")) | |
5283 | (use (match_operand 2 "" "")) | |
5284 | (use (match_operand 3 "" ""))] | |
5285 | "" | |
c65ebc55 | 5286 | { |
599aedd9 | 5287 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5288 | DONE; |
1d5d7a21 | 5289 | }) |
c65ebc55 | 5290 | |
2ed4af6f RH |
5291 | (define_expand "sibcall" |
5292 | [(use (match_operand:DI 0 "" "")) | |
5293 | (use (match_operand 1 "" "")) | |
5294 | (use (match_operand 2 "" "")) | |
5295 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5296 | "" |
c65ebc55 | 5297 | { |
599aedd9 | 5298 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5299 | DONE; |
1d5d7a21 | 5300 | }) |
c65ebc55 | 5301 | |
c65ebc55 | 5302 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5303 | ;; register in which the value is returned. There are three more operands, |
5304 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5305 | ;; increased by one). |
2ed4af6f | 5306 | ;; |
c65ebc55 JW |
5307 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5308 | ||
5309 | (define_expand "call_value" | |
5310 | [(use (match_operand 0 "" "")) | |
5311 | (use (match_operand:DI 1 "" "")) | |
5312 | (use (match_operand 2 "" "")) | |
5313 | (use (match_operand 3 "" "")) | |
5314 | (use (match_operand 4 "" ""))] | |
5315 | "" | |
c65ebc55 | 5316 | { |
599aedd9 | 5317 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5318 | DONE; |
1d5d7a21 | 5319 | }) |
c65ebc55 | 5320 | |
2ed4af6f RH |
5321 | (define_expand "sibcall_value" |
5322 | [(use (match_operand 0 "" "")) | |
5323 | (use (match_operand:DI 1 "" "")) | |
5324 | (use (match_operand 2 "" "")) | |
5325 | (use (match_operand 3 "" "")) | |
5326 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5327 | "" |
c65ebc55 | 5328 | { |
599aedd9 | 5329 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5330 | DONE; |
1d5d7a21 | 5331 | }) |
c65ebc55 | 5332 | |
c65ebc55 JW |
5333 | ;; Call subroutine returning any type. |
5334 | ||
5335 | (define_expand "untyped_call" | |
5336 | [(parallel [(call (match_operand 0 "" "") | |
5337 | (const_int 0)) | |
5338 | (match_operand 1 "" "") | |
5339 | (match_operand 2 "" "")])] | |
5340 | "" | |
c65ebc55 JW |
5341 | { |
5342 | int i; | |
5343 | ||
5344 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5345 | ||
5346 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5347 | { | |
5348 | rtx set = XVECEXP (operands[2], 0, i); | |
5349 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5350 | } | |
5351 | ||
5352 | /* The optimizer does not know that the call sets the function value | |
5353 | registers we stored in the result block. We avoid problems by | |
5354 | claiming that all hard registers are used and clobbered at this | |
5355 | point. */ | |
5356 | emit_insn (gen_blockage ()); | |
5357 | ||
5358 | DONE; | |
1d5d7a21 | 5359 | }) |
c65ebc55 | 5360 | |
599aedd9 RH |
5361 | (define_insn "call_nogp" |
5362 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5363 | (const_int 0)) | |
5364 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5365 | "" |
599aedd9 | 5366 | "br.call%+.many %1 = %0" |
52e12ad0 | 5367 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5368 | |
599aedd9 | 5369 | (define_insn "call_value_nogp" |
75293ad6 | 5370 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5371 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5372 | (const_int 0))) | |
5373 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5374 | "" |
599aedd9 | 5375 | "br.call%+.many %2 = %1" |
52e12ad0 | 5376 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5377 | |
599aedd9 RH |
5378 | (define_insn "sibcall_nogp" |
5379 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5380 | (const_int 0))] | |
2ed4af6f RH |
5381 | "" |
5382 | "br%+.many %0" | |
52e12ad0 | 5383 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5384 | |
599aedd9 | 5385 | (define_insn "call_gp" |
c8083186 | 5386 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5387 | (const_int 1)) |
5388 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5389 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5390 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5391 | "" |
599aedd9 | 5392 | "#" |
52e12ad0 | 5393 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5394 | |
599aedd9 RH |
5395 | ;; Irritatingly, we don't have access to INSN within the split body. |
5396 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5397 | (define_split | |
5398 | [(call (mem (match_operand 0 "call_operand" "")) | |
5399 | (const_int 1)) | |
5400 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5401 | (clobber (match_scratch:DI 2 "")) | |
5402 | (clobber (match_scratch:DI 3 ""))] | |
5403 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5404 | [(const_int 0)] | |
5405 | { | |
5406 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5407 | operands[3], true, false); | |
5408 | DONE; | |
5409 | }) | |
5410 | ||
5411 | (define_split | |
5412 | [(call (mem (match_operand 0 "call_operand" "")) | |
5413 | (const_int 1)) | |
5414 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5415 | (clobber (match_scratch:DI 2 "")) | |
5416 | (clobber (match_scratch:DI 3 ""))] | |
5417 | "reload_completed" | |
5418 | [(const_int 0)] | |
5419 | { | |
5420 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5421 | operands[3], false, false); | |
5422 | DONE; | |
5423 | }) | |
5424 | ||
5425 | (define_insn "call_value_gp" | |
75293ad6 | 5426 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5427 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5428 | (const_int 1))) | |
5429 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5430 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5431 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5432 | "" |
599aedd9 | 5433 | "#" |
52e12ad0 | 5434 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5435 | |
599aedd9 RH |
5436 | (define_split |
5437 | [(set (match_operand 0 "" "") | |
5438 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5439 | (const_int 1))) | |
5440 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5441 | (clobber (match_scratch:DI 3 "")) | |
5442 | (clobber (match_scratch:DI 4 ""))] | |
5443 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5444 | [(const_int 0)] | |
5445 | { | |
5446 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5447 | operands[4], true, false); | |
5448 | DONE; | |
5449 | }) | |
5450 | ||
5451 | (define_split | |
5452 | [(set (match_operand 0 "" "") | |
5453 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5454 | (const_int 1))) | |
5455 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5456 | (clobber (match_scratch:DI 3 "")) | |
5457 | (clobber (match_scratch:DI 4 ""))] | |
5458 | "reload_completed" | |
5459 | [(const_int 0)] | |
5460 | { | |
5461 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5462 | operands[4], false, false); | |
5463 | DONE; | |
5464 | }) | |
5465 | ||
5466 | (define_insn_and_split "sibcall_gp" | |
5467 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5468 | (const_int 1)) | |
5469 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5470 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5471 | "" |
599aedd9 RH |
5472 | "#" |
5473 | "reload_completed" | |
5474 | [(const_int 0)] | |
5475 | { | |
5476 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5477 | operands[2], true, true); | |
5478 | DONE; | |
5479 | } | |
52e12ad0 | 5480 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5481 | |
c65ebc55 JW |
5482 | (define_insn "return_internal" |
5483 | [(return) | |
5484 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5485 | "" | |
5486 | "br.ret.sptk.many %0" | |
52e12ad0 | 5487 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5488 | |
5489 | (define_insn "return" | |
5490 | [(return)] | |
5491 | "ia64_direct_return ()" | |
5492 | "br.ret.sptk.many rp" | |
52e12ad0 | 5493 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5494 | |
6b6c1201 | 5495 | (define_insn "*return_true" |
c65ebc55 | 5496 | [(set (pc) |
6b6c1201 | 5497 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5498 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5499 | (const_int 0)]) |
c65ebc55 JW |
5500 | (return) |
5501 | (pc)))] | |
5502 | "ia64_direct_return ()" | |
13da91fd | 5503 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5504 | [(set_attr "itanium_class" "br") |
e5bde68a | 5505 | (set_attr "predicable" "no")]) |
c65ebc55 | 5506 | |
6b6c1201 | 5507 | (define_insn "*return_false" |
c65ebc55 | 5508 | [(set (pc) |
6b6c1201 | 5509 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5510 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5511 | (const_int 0)]) |
c65ebc55 JW |
5512 | (pc) |
5513 | (return)))] | |
5514 | "ia64_direct_return ()" | |
13da91fd | 5515 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5516 | [(set_attr "itanium_class" "br") |
e5bde68a | 5517 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5518 | |
5519 | (define_insn "jump" | |
5520 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5521 | "" | |
5522 | "br %l0" | |
52e12ad0 | 5523 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5524 | |
5525 | (define_insn "indirect_jump" | |
5526 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5527 | "" | |
5528 | "br %0" | |
52e12ad0 | 5529 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5530 | |
5531 | (define_expand "tablejump" | |
340f7e7c RH |
5532 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5533 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5534 | "" |
c65ebc55 | 5535 | { |
340f7e7c RH |
5536 | rtx op0 = operands[0]; |
5537 | rtx addr; | |
5538 | ||
5539 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5540 | element into a register without bothering to see whether that | |
5541 | is necessary given the operand predicate. Check for MEM just | |
5542 | in case someone fixes this. */ | |
5543 | if (GET_CODE (op0) == MEM) | |
5544 | addr = XEXP (op0, 0); | |
5545 | else | |
5546 | { | |
5547 | /* Otherwise, cheat and guess that the previous insn in the | |
5548 | stream was the memory load. Grab the address from that. | |
5549 | Note we have to momentarily pop out of the sequence started | |
5550 | by the insn-emit wrapper in order to grab the last insn. */ | |
5551 | rtx last, set; | |
5552 | ||
5553 | end_sequence (); | |
5554 | last = get_last_insn (); | |
5555 | start_sequence (); | |
5556 | set = single_set (last); | |
5557 | ||
e820471b NS |
5558 | gcc_assert (rtx_equal_p (SET_DEST (set), op0) |
5559 | && GET_CODE (SET_SRC (set)) == MEM); | |
340f7e7c | 5560 | addr = XEXP (SET_SRC (set), 0); |
e820471b | 5561 | gcc_assert (!rtx_equal_p (addr, op0)); |
340f7e7c | 5562 | } |
c65ebc55 | 5563 | |
340f7e7c RH |
5564 | /* Jump table elements are stored pc-relative. That is, a displacement |
5565 | from the entry to the label. Thus to convert to an absolute address | |
5566 | we add the address of the memory from which the value is loaded. */ | |
5567 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5568 | NULL_RTX, 1, OPTAB_DIRECT); | |
5569 | }) | |
c65ebc55 | 5570 | |
340f7e7c | 5571 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5572 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5573 | (use (label_ref (match_operand 1 "" "")))] | |
5574 | "" | |
5575 | "br %0" | |
52e12ad0 | 5576 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5577 | |
5578 | \f | |
5579 | ;; :::::::::::::::::::: | |
5580 | ;; :: | |
5581 | ;; :: Prologue and Epilogue instructions | |
5582 | ;; :: | |
5583 | ;; :::::::::::::::::::: | |
5584 | ||
5585 | (define_expand "prologue" | |
5586 | [(const_int 1)] | |
5587 | "" | |
c65ebc55 JW |
5588 | { |
5589 | ia64_expand_prologue (); | |
5590 | DONE; | |
1d5d7a21 | 5591 | }) |
c65ebc55 JW |
5592 | |
5593 | (define_expand "epilogue" | |
2ed4af6f RH |
5594 | [(return)] |
5595 | "" | |
2ed4af6f RH |
5596 | { |
5597 | ia64_expand_epilogue (0); | |
5598 | DONE; | |
1d5d7a21 | 5599 | }) |
2ed4af6f RH |
5600 | |
5601 | (define_expand "sibcall_epilogue" | |
5602 | [(return)] | |
c65ebc55 | 5603 | "" |
c65ebc55 | 5604 | { |
2ed4af6f | 5605 | ia64_expand_epilogue (1); |
c65ebc55 | 5606 | DONE; |
1d5d7a21 | 5607 | }) |
c65ebc55 JW |
5608 | |
5609 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5610 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5611 | ||
5612 | (define_insn "prologue_allocate_stack" | |
5613 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5614 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5615 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5616 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5617 | (match_dup 3))] |
5618 | "" | |
5619 | "@ | |
1d5d7a21 RH |
5620 | add %0 = %1, %2 |
5621 | adds %0 = %2, %1 | |
5622 | addl %0 = %2, %1" | |
52e12ad0 | 5623 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5624 | |
5625 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5626 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5627 | ||
5628 | (define_insn "epilogue_deallocate_stack" | |
5629 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5630 | (match_operand:DI 1 "register_operand" "+r")) | |
5631 | (set (match_dup 1) (match_dup 1))] | |
5632 | "" | |
5633 | "mov %0 = %1" | |
52e12ad0 | 5634 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5635 | |
1d5d7a21 RH |
5636 | ;; As USE insns aren't meaningful after reload, this is used instead |
5637 | ;; to prevent deleting instructions setting registers for EH handling | |
5638 | (define_insn "prologue_use" | |
5639 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5640 | UNSPEC_PROLOGUE_USE)] | |
5641 | "" | |
5642 | "" | |
5643 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5644 | (set_attr "predicable" "no") |
5645 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5646 | |
c65ebc55 JW |
5647 | ;; Allocate a new register frame. |
5648 | ||
5649 | (define_insn "alloc" | |
5650 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5651 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5652 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5653 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5654 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5655 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5656 | "" | |
5657 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5658 | [(set_attr "itanium_class" "syst_m0") |
68e11b42 JW |
5659 | (set_attr "predicable" "no") |
5660 | (set_attr "first_insn" "yes")]) | |
c65ebc55 | 5661 | |
97e242b0 RH |
5662 | ;; Modifies ar.unat |
5663 | (define_expand "gr_spill" | |
870f9ec0 RH |
5664 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5665 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5666 | (match_operand:DI 2 "const_int_operand" "")] |
5667 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5668 | (clobber (match_dup 3))])] |
97e242b0 | 5669 | "" |
870f9ec0 | 5670 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5671 | |
870f9ec0 | 5672 | (define_insn "gr_spill_internal" |
c65ebc55 | 5673 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 | 5674 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5675 | (match_operand:DI 2 "const_int_operand" "")] |
5676 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5677 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5678 | "" |
2130b7fb | 5679 | { |
1d5d7a21 RH |
5680 | /* Note that we use a C output pattern here to avoid the predicate |
5681 | being automatically added before the .mem.offset directive. */ | |
5682 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5683 | } | |
52e12ad0 | 5684 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5685 | |
97e242b0 RH |
5686 | ;; Reads ar.unat |
5687 | (define_expand "gr_restore" | |
870f9ec0 RH |
5688 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5689 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5690 | (match_operand:DI 2 "const_int_operand" "")] |
5691 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5692 | (use (match_dup 3))])] |
97e242b0 | 5693 | "" |
870f9ec0 | 5694 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5695 | |
870f9ec0 | 5696 | (define_insn "gr_restore_internal" |
c65ebc55 | 5697 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5698 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5699 | (match_operand:DI 2 "const_int_operand" "")] |
5700 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5701 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5702 | "" |
1d5d7a21 | 5703 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5704 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5705 | |
5706 | (define_insn "fr_spill" | |
02befdf4 ZW |
5707 | [(set (match_operand:XF 0 "memory_operand" "=m") |
5708 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] | |
086c0f96 | 5709 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5710 | "" |
5711 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5712 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5713 | |
5714 | (define_insn "fr_restore" | |
02befdf4 ZW |
5715 | [(set (match_operand:XF 0 "register_operand" "=f") |
5716 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5717 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5718 | "" |
5719 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5720 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5721 | |
0024a804 JW |
5722 | ;; ??? The explicit stop is not ideal. It would be better if |
5723 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5724 | ;; fixed later. This avoids an RSE DV. | |
5725 | ||
0c96007e AM |
5726 | (define_insn "bsp_value" |
5727 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5728 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5729 | "" |
582d11e6 JW |
5730 | "* |
5731 | { | |
5732 | return \";;\;%,mov %0 = ar.bsp\"; | |
5733 | }" | |
52e12ad0 | 5734 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5735 | |
5736 | (define_insn "set_bsp" | |
086c0f96 RH |
5737 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5738 | UNSPECV_SET_BSP)] | |
0c96007e | 5739 | "" |
1d5d7a21 RH |
5740 | "flushrs |
5741 | mov r19=ar.rsc | |
5742 | ;; | |
5743 | and r19=0x1c,r19 | |
5744 | ;; | |
5745 | mov ar.rsc=r19 | |
5746 | ;; | |
5747 | mov ar.bspstore=%0 | |
5748 | ;; | |
5749 | or r19=0x3,r19 | |
5750 | ;; | |
5751 | loadrs | |
5752 | invala | |
5753 | ;; | |
5754 | mov ar.rsc=r19" | |
52e12ad0 | 5755 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5756 | (set_attr "predicable" "no")]) |
ce152ef8 | 5757 | |
0024a804 JW |
5758 | ;; ??? The explicit stops are not ideal. It would be better if |
5759 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5760 | ;; fixed later. This avoids an RSE DV. | |
5761 | ||
ce152ef8 | 5762 | (define_insn "flushrs" |
086c0f96 | 5763 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5764 | "" |
0024a804 | 5765 | ";;\;flushrs\;;;" |
582d11e6 JW |
5766 | [(set_attr "itanium_class" "rse_m") |
5767 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
5768 | \f |
5769 | ;; :::::::::::::::::::: | |
5770 | ;; :: | |
5771 | ;; :: Miscellaneous instructions | |
5772 | ;; :: | |
5773 | ;; :::::::::::::::::::: | |
5774 | ||
839a4992 | 5775 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
5776 | ;; be emitting ";;" to force a break in the instruction packing. |
5777 | ||
5778 | ;; No operation, needed in case the user uses -g but not -O. | |
5779 | (define_insn "nop" | |
5780 | [(const_int 0)] | |
5781 | "" | |
5782 | "nop 0" | |
30028c85 | 5783 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 5784 | |
2130b7fb BS |
5785 | (define_insn "nop_m" |
5786 | [(const_int 1)] | |
5787 | "" | |
5788 | "nop.m 0" | |
5789 | [(set_attr "itanium_class" "nop_m")]) | |
5790 | ||
5791 | (define_insn "nop_i" | |
5792 | [(const_int 2)] | |
5793 | "" | |
5794 | "nop.i 0" | |
5795 | [(set_attr "itanium_class" "nop_i")]) | |
5796 | ||
5797 | (define_insn "nop_f" | |
5798 | [(const_int 3)] | |
5799 | "" | |
5800 | "nop.f 0" | |
5801 | [(set_attr "itanium_class" "nop_f")]) | |
5802 | ||
5803 | (define_insn "nop_b" | |
5804 | [(const_int 4)] | |
5805 | "" | |
5806 | "nop.b 0" | |
5807 | [(set_attr "itanium_class" "nop_b")]) | |
5808 | ||
5809 | (define_insn "nop_x" | |
5810 | [(const_int 5)] | |
5811 | "" | |
5812 | "" | |
fa978426 AS |
5813 | [(set_attr "itanium_class" "nop_x") |
5814 | (set_attr "empty" "yes")]) | |
2130b7fb | 5815 | |
30028c85 VM |
5816 | ;; The following insn will be never generated. It is used only by |
5817 | ;; insn scheduler to change state before advancing cycle. | |
5818 | (define_insn "pre_cycle" | |
5819 | [(const_int 6)] | |
5820 | "" | |
5821 | "" | |
5822 | [(set_attr "itanium_class" "pre_cycle")]) | |
5823 | ||
2130b7fb | 5824 | (define_insn "bundle_selector" |
086c0f96 | 5825 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 5826 | "" |
1d5d7a21 | 5827 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
5828 | [(set_attr "itanium_class" "ignore") |
5829 | (set_attr "predicable" "no")]) | |
5830 | ||
c65ebc55 JW |
5831 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5832 | ;; point. | |
5833 | (define_insn "blockage" | |
086c0f96 | 5834 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
5835 | "" |
5836 | "" | |
52e12ad0 | 5837 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5838 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5839 | |
5840 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
5841 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
5842 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
5843 | "" |
5844 | ";;" | |
52e12ad0 | 5845 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
5846 | (set_attr "predicable" "no") |
5847 | (set_attr "empty" "yes")]) | |
c65ebc55 | 5848 | |
26406018 RH |
5849 | (define_expand "trap" |
5850 | [(trap_if (const_int 1) (const_int 0))] | |
5851 | "" | |
5852 | "") | |
5853 | ||
5854 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
5855 | ;; produces worse code that setting the slot type to A. | |
5856 | ||
5857 | (define_insn "*trap" | |
5858 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
5859 | "" | |
5860 | "break %0" | |
5861 | [(set_attr "itanium_class" "chk_s")]) | |
5862 | ||
5863 | (define_expand "conditional_trap" | |
5864 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
5865 | "" | |
5866 | { | |
5867 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
5868 | }) | |
5869 | ||
5870 | (define_insn "*conditional_trap" | |
5871 | [(trap_if (match_operator 0 "predicate_operator" | |
5872 | [(match_operand:BI 1 "register_operand" "c") | |
5873 | (const_int 0)]) | |
5874 | (match_operand 2 "const_int_operand" ""))] | |
5875 | "" | |
5cf63e3f | 5876 | "(%J0) break %2" |
26406018 RH |
5877 | [(set_attr "itanium_class" "chk_s") |
5878 | (set_attr "predicable" "no")]) | |
5879 | ||
f12f25a7 | 5880 | (define_insn "break_f" |
086c0f96 | 5881 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
5882 | "" |
5883 | "break.f 0" | |
5884 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5885 | |
5886 | (define_insn "prefetch" | |
5887 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5888 | (match_operand:DI 1 "const_int_operand" "n") | |
5889 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5890 | "" | |
5891 | { | |
5892 | static const char * const alt[2][4] = { | |
b3656137 | 5893 | { |
92cbea22 L |
5894 | "%,lfetch.nta [%0]", |
5895 | "%,lfetch.nt1 [%0]", | |
5896 | "%,lfetch.nt2 [%0]", | |
5897 | "%,lfetch [%0]" | |
b3656137 KG |
5898 | }, |
5899 | { | |
92cbea22 L |
5900 | "%,lfetch.excl.nta [%0]", |
5901 | "%,lfetch.excl.nt1 [%0]", | |
5902 | "%,lfetch.excl.nt2 [%0]", | |
5903 | "%,lfetch.excl [%0]" | |
b3656137 | 5904 | } |
44eca121 JJ |
5905 | }; |
5906 | int i = (INTVAL (operands[1])); | |
5907 | int j = (INTVAL (operands[2])); | |
5908 | ||
e820471b NS |
5909 | gcc_assert (i == 0 || i == 1); |
5910 | gcc_assert (j >= 0 && j <= 3); | |
44eca121 JJ |
5911 | return alt[i][j]; |
5912 | } | |
5913 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5914 | \f |
5915 | ;; Non-local goto support. | |
5916 | ||
5917 | (define_expand "save_stack_nonlocal" | |
5918 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5919 | (use (match_operand:DI 1 "register_operand" ""))] | |
5920 | "" | |
c65ebc55 JW |
5921 | { |
5922 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5923 | \"__ia64_save_stack_nonlocal\"), | |
5924 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
5925 | operands[1], Pmode); | |
5926 | DONE; | |
1d5d7a21 | 5927 | }) |
c65ebc55 JW |
5928 | |
5929 | (define_expand "nonlocal_goto" | |
5930 | [(use (match_operand 0 "general_operand" "")) | |
5931 | (use (match_operand 1 "general_operand" "")) | |
5932 | (use (match_operand 2 "general_operand" "")) | |
5933 | (use (match_operand 3 "general_operand" ""))] | |
5934 | "" | |
c65ebc55 | 5935 | { |
c65ebc55 | 5936 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5937 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5938 | operands[1], Pmode, |
c65ebc55 | 5939 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5940 | operands[3], Pmode); |
c65ebc55 JW |
5941 | emit_barrier (); |
5942 | DONE; | |
1d5d7a21 | 5943 | }) |
c65ebc55 | 5944 | |
b39eb2f9 RH |
5945 | (define_insn_and_split "builtin_setjmp_receiver" |
5946 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 5947 | "" |
b39eb2f9 RH |
5948 | "#" |
5949 | "reload_completed" | |
5950 | [(const_int 0)] | |
97e242b0 | 5951 | { |
599aedd9 | 5952 | ia64_reload_gp (); |
c65ebc55 | 5953 | DONE; |
1d5d7a21 | 5954 | }) |
c65ebc55 | 5955 | |
0c96007e AM |
5956 | (define_expand "eh_epilogue" |
5957 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5958 | (use (match_operand:DI 1 "register_operand" "r")) | |
5959 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5960 | "" | |
0c96007e AM |
5961 | { |
5962 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5963 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5964 | ||
5965 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5966 | { | |
5967 | emit_move_insn (bsp, operands[0]); | |
5968 | operands[0] = bsp; | |
5969 | } | |
5970 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5971 | { | |
5972 | emit_move_insn (sp, operands[2]); | |
5973 | operands[2] = sp; | |
5974 | } | |
5975 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5976 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5977 | ||
5978 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5979 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 5980 | }) |
9525c690 JW |
5981 | \f |
5982 | ;; Builtin apply support. | |
5983 | ||
5984 | (define_expand "restore_stack_nonlocal" | |
5985 | [(use (match_operand:DI 0 "register_operand" "")) | |
5986 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5987 | "" | |
9525c690 JW |
5988 | { |
5989 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 5990 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
5991 | 0, VOIDmode, 1, |
5992 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5993 | DONE; | |
1d5d7a21 | 5994 | }) |
9525c690 | 5995 | |
e5bde68a RH |
5996 | \f |
5997 | ;; Predication. | |
5998 | ||
5999 | (define_cond_exec | |
6000 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6001 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6002 | (const_int 0)])] |
6003 | "" | |
6004 | "(%J0)") | |
3b572406 RH |
6005 | |
6006 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6007 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6008 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6009 | "" |
054451ea | 6010 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6011 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6012 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6013 | |
6014 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6015 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6016 | "" |
6017 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6018 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6019 | (set_attr "predicable" "no")]) |
6020 | ||
6021 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6022 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6023 | "" |
ca3920ad | 6024 | { |
1bc7c5b6 | 6025 | emit_safe_across_calls (); |
1d5d7a21 RH |
6026 | return ""; |
6027 | } | |
52e12ad0 | 6028 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6029 | (set_attr "predicable" "no")]) |
6030 | ||
6dd12198 SE |
6031 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit |
6032 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
6033 | ||
6034 | (define_insn "ptr_extend" | |
6035 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6036 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6037 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6038 | "" |
6039 | "addp4 %0 = 0,%1" | |
6040 | [(set_attr "itanium_class" "ialu")]) | |
6041 | ||
e206a74f SE |
6042 | ;; |
6043 | ;; Optimizations for ptr_extend | |
6044 | ||
36c216e5 | 6045 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6046 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6047 | (unspec:DI | |
6048 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6049 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6050 | UNSPEC_ADDP4))] |
08744705 | 6051 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6052 | "addp4 %0 = %2, %1" |
6053 | [(set_attr "itanium_class" "ialu")]) | |
6054 | ||
6055 | (define_insn "*ptr_extend_plus_2" | |
6056 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6057 | (unspec:DI | |
6058 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6059 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6060 | UNSPEC_ADDP4))] |
08744705 | 6061 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6062 | "addp4 %0 = %1, %2" |
6063 | [(set_attr "itanium_class" "ialu")]) | |
f61134e8 | 6064 | |
d26afa4f SE |
6065 | ;; |
6066 | ;; Get instruction pointer | |
6067 | ||
6068 | (define_insn "ip_value" | |
6069 | [(set (match_operand:DI 0 "register_operand" "=r") | |
6070 | (pc))] | |
6071 | "" | |
6072 | "mov %0 = ip" | |
6073 | [(set_attr "itanium_class" "ialu")]) | |
6074 | ||
f61134e8 RH |
6075 | ;; Vector operations |
6076 | (include "vect.md") | |
af795c3c RH |
6077 | ;; Atomic operations |
6078 | (include "sync.md") |