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c65ebc55 | 1 | ;; IA-64 Machine description template |
f4ef873c | 2 | ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
e5bde68a RH |
51 | ;; Unspec usage: |
52 | ;; | |
53 | ;; unspec: | |
54 | ;; 1 gr_spill | |
55 | ;; 2 gr_restore | |
56 | ;; 3 fr_spill | |
57 | ;; 4 fr_restore | |
655f2eb9 | 58 | ;; 5 recip_approx |
f2f90c63 | 59 | ;; 7 pred_rel_mutex |
e5bde68a | 60 | ;; 8 popcnt |
2ed4af6f | 61 | ;; 9 pic call |
97e242b0 | 62 | ;; 12 mf |
e5bde68a | 63 | ;; 13 cmpxchg_acq |
e5bde68a RH |
64 | ;; 19 fetchadd_acq |
65 | ;; 20 bsp_value | |
ce152ef8 | 66 | ;; 21 flushrs |
2130b7fb BS |
67 | ;; 22 bundle selector |
68 | ;; 23 cycle display | |
6dd12198 | 69 | ;; 24 addp4 |
d0e82870 | 70 | ;; 25 prologue_use |
e5bde68a RH |
71 | ;; |
72 | ;; unspec_volatile: | |
73 | ;; 0 alloc | |
74 | ;; 1 blockage | |
75 | ;; 2 insn_group_barrier | |
f12f25a7 | 76 | ;; 3 break |
e5bde68a | 77 | ;; 5 set_bsp |
ca3920ad JW |
78 | ;; 8 pred.safe_across_calls all |
79 | ;; 9 pred.safe_across_calls normal | |
c65ebc55 JW |
80 | \f |
81 | ;; :::::::::::::::::::: | |
82 | ;; :: | |
83 | ;; :: Attributes | |
84 | ;; :: | |
85 | ;; :::::::::::::::::::: | |
86 | ||
87 | ;; Instruction type. This primarily determines how instructions can be | |
88 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
89 | ||
90 | ;; A alu, can go in I or M syllable of a bundle | |
91 | ;; I integer | |
92 | ;; M memory | |
93 | ;; F floating-point | |
94 | ;; B branch | |
95 | ;; L long immediate, takes two syllables | |
96 | ;; S stop bit | |
97 | ||
98 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
99 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
100 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
101 | ;; which emit instruction that can go in any slot (e.g. nop). | |
102 | ||
44eca121 | 103 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x,lfetch" |
52e12ad0 BS |
104 | (const_string "unknown")) |
105 | ||
2130b7fb BS |
106 | ;; chk_s has an I and an M form; use type A for convenience. |
107 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
108 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
109 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
110 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 111 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
2130b7fb BS |
112 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
113 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
114 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
115 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
116 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
117 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
118 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 119 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 120 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
121 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
122 | (const_string "unknown"))) | |
c65ebc55 | 123 | |
2130b7fb BS |
124 | (define_attr "itanium_requires_unit0" "no,yes" |
125 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
126 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
127 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
128 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
129 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
130 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
131 | (const_string "no"))) | |
132 | ||
e5bde68a RH |
133 | ;; Predication. True iff this instruction can be predicated. |
134 | ||
135 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
136 | ||
c65ebc55 JW |
137 | \f |
138 | ;; :::::::::::::::::::: | |
139 | ;; :: | |
140 | ;; :: Function Units | |
141 | ;; :: | |
142 | ;; :::::::::::::::::::: | |
143 | ||
2130b7fb BS |
144 | ;; We define 6 "dummy" functional units. All the real work to decide which |
145 | ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only | |
146 | ;; have to ensure here that there are enough copies of the dummy unit so | |
147 | ;; that the scheduler doesn't get confused by MD_SCHED_REORDER. | |
148 | ;; Other than the 6 dummies for normal insns, we also add a single dummy unit | |
149 | ;; for stop bits. | |
150 | ||
151 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0) | |
152 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0) | |
153 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0) | |
154 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0) | |
155 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0) | |
156 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0) | |
157 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0) | |
158 | ||
159 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
160 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0) | |
161 | ;; There is only ony insn `mov = ar.unat' for frar_m: | |
162 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0) | |
163 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0) | |
164 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0) | |
165 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0) | |
166 | ||
167 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0) | |
168 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0) | |
169 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0) | |
170 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0) | |
171 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0) | |
172 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0) | |
173 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0) | |
174 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0) | |
175 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0) | |
176 | ||
177 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
178 | ;; is the 1st syllable of the bundle after stop bit. | |
179 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0) | |
180 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0) | |
181 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0) | |
182 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0) | |
183 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0) | |
184 | ;; Now we use only one insn `mf'. Therfore latency time is set up to 0. | |
185 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0) | |
186 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0) | |
187 | ||
188 | ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use | |
189 | ;; latency time equal to 0: | |
190 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0) | |
191 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
192 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0) | |
193 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0) | |
194 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0) | |
195 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0) | |
196 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0) | |
197 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0) | |
198 | ||
199 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0) | |
200 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0) | |
201 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0) | |
202 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0) | |
203 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0) | |
204 | ||
205 | (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0) | |
206 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0) | |
207 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0) | |
c65ebc55 JW |
208 | \f |
209 | ;; :::::::::::::::::::: | |
210 | ;; :: | |
211 | ;; :: Moves | |
212 | ;; :: | |
213 | ;; :::::::::::::::::::: | |
214 | ||
f2f90c63 RH |
215 | ;; Set of a single predicate register. This is only used to implement |
216 | ;; pr-to-pr move and complement. | |
217 | ||
218 | (define_insn "*movcci" | |
219 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
220 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
221 | "" | |
222 | "@ | |
223 | cmp.ne %0, p0 = r0, r0 | |
224 | cmp.eq %0, p0 = r0, r0 | |
225 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 226 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
227 | (set_attr "predicable" "no")]) |
228 | ||
229 | (define_insn "movbi" | |
cd5c4048 RH |
230 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
231 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
232 | "" |
233 | "@ | |
234 | cmp.ne %0, %I0 = r0, r0 | |
235 | cmp.eq %0, %I0 = r0, r0 | |
236 | # | |
237 | # | |
238 | tbit.nz %0, %I0 = %1, 0 | |
239 | adds %0 = %1, r0 | |
240 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
241 | st1%Q0 %0 = %1%P0 |
242 | mov %0 = %1" | |
52e12ad0 | 243 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
244 | |
245 | (define_split | |
246 | [(set (match_operand:BI 0 "register_operand" "") | |
247 | (match_operand:BI 1 "register_operand" ""))] | |
248 | "reload_completed | |
249 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
250 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
251 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
252 | (set (match_dup 0) (const_int 1))) | |
253 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
254 | (set (match_dup 0) (const_int 0)))] | |
255 | "") | |
256 | ||
257 | (define_split | |
258 | [(set (match_operand:BI 0 "register_operand" "") | |
259 | (match_operand:BI 1 "register_operand" ""))] | |
260 | "reload_completed | |
261 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
262 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
263 | [(set (match_dup 2) (match_dup 4)) | |
264 | (set (match_dup 3) (match_dup 5)) | |
265 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
266 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); | |
267 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
268 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
269 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
270 | ||
c65ebc55 JW |
271 | (define_expand "movqi" |
272 | [(set (match_operand:QI 0 "general_operand" "") | |
273 | (match_operand:QI 1 "general_operand" ""))] | |
274 | "" | |
275 | " | |
276 | { | |
277 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
278 | && ! ia64_move_ok (operands[0], operands[1])) |
279 | operands[1] = force_reg (QImode, operands[1]); | |
c65ebc55 JW |
280 | }") |
281 | ||
282 | (define_insn "*movqi_internal" | |
4b983fdc RH |
283 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
284 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 285 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 286 | "@ |
13da91fd | 287 | mov %0 = %r1 |
c65ebc55 JW |
288 | addl %0 = %1, r0 |
289 | ld1%O1 %0 = %1%P1 | |
13da91fd | 290 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 291 | getf.sig %0 = %1 |
13da91fd RH |
292 | setf.sig %0 = %r1 |
293 | mov %0 = %1" | |
52e12ad0 | 294 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
295 | |
296 | (define_expand "movhi" | |
297 | [(set (match_operand:HI 0 "general_operand" "") | |
298 | (match_operand:HI 1 "general_operand" ""))] | |
299 | "" | |
300 | " | |
301 | { | |
302 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
303 | && ! ia64_move_ok (operands[0], operands[1])) |
304 | operands[1] = force_reg (HImode, operands[1]); | |
c65ebc55 JW |
305 | }") |
306 | ||
307 | (define_insn "*movhi_internal" | |
4b983fdc RH |
308 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
309 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 310 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 311 | "@ |
13da91fd | 312 | mov %0 = %r1 |
c65ebc55 JW |
313 | addl %0 = %1, r0 |
314 | ld2%O1 %0 = %1%P1 | |
13da91fd | 315 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 316 | getf.sig %0 = %1 |
13da91fd RH |
317 | setf.sig %0 = %r1 |
318 | mov %0 = %1" | |
52e12ad0 | 319 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
320 | |
321 | (define_expand "movsi" | |
322 | [(set (match_operand:SI 0 "general_operand" "") | |
323 | (match_operand:SI 1 "general_operand" ""))] | |
324 | "" | |
325 | " | |
326 | { | |
327 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
328 | && ! ia64_move_ok (operands[0], operands[1])) |
329 | operands[1] = force_reg (SImode, operands[1]); | |
c65ebc55 JW |
330 | }") |
331 | ||
332 | (define_insn "*movsi_internal" | |
97e242b0 | 333 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 334 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 335 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 336 | "@ |
13da91fd | 337 | mov %0 = %r1 |
c65ebc55 JW |
338 | addl %0 = %1, r0 |
339 | movl %0 = %1 | |
340 | ld4%O1 %0 = %1%P1 | |
13da91fd | 341 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 342 | getf.sig %0 = %1 |
13da91fd | 343 | setf.sig %0 = %r1 |
97e242b0 RH |
344 | mov %0 = %1 |
345 | mov %0 = %1 | |
346 | mov %0 = %r1" | |
52e12ad0 BS |
347 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
348 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) | |
c65ebc55 JW |
349 | |
350 | (define_expand "movdi" | |
351 | [(set (match_operand:DI 0 "general_operand" "") | |
352 | (match_operand:DI 1 "general_operand" ""))] | |
353 | "" | |
354 | " | |
355 | { | |
9a89adb8 RH |
356 | if (! reload_in_progress && ! reload_completed |
357 | && ! ia64_move_ok (operands[0], operands[1])) | |
358 | operands[1] = force_reg (DImode, operands[1]); | |
ec039e3c | 359 | if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode)) |
c65ebc55 | 360 | { |
9a89adb8 RH |
361 | /* Before optimization starts, delay committing to any particular |
362 | type of PIC address load. If this function gets deferred, we | |
363 | may acquire information that changes the value of the | |
364 | sdata_symbolic_operand predicate. */ | |
7c866fb5 JW |
365 | /* But don't delay for function pointers. Loading a function address |
366 | actually loads the address of the descriptor not the function. | |
367 | If we represent these as SYMBOL_REFs, then they get cse'd with | |
368 | calls, and we end up with calls to the descriptor address instead of | |
369 | calls to the function address. Functions are not candidates for | |
370 | sdata anyways. */ | |
371 | if (rtx_equal_function_value_matters | |
372 | && ! (GET_CODE (operands[1]) == SYMBOL_REF | |
373 | && SYMBOL_REF_FLAG (operands[1]))) | |
b5d37c6f | 374 | emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode))); |
9a89adb8 | 375 | else |
b5d37c6f | 376 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d | 377 | DONE; |
c65ebc55 | 378 | } |
c65ebc55 JW |
379 | }") |
380 | ||
9a89adb8 RH |
381 | ;; This is used during early compilation to delay the decision on |
382 | ;; how to refer to a variable as long as possible. This is especially | |
383 | ;; important between initial rtl generation and optimization for | |
384 | ;; deferred functions, since we may acquire additional information | |
385 | ;; on the variables used in the meantime. | |
386 | ||
ef375129 JW |
387 | ;; ??? This causes us to lose REG_LABEL notes, because the insn splitter |
388 | ;; does not attempt to preserve any REG_NOTES on the input instruction. | |
389 | ||
9a89adb8 RH |
390 | (define_insn_and_split "movdi_symbolic" |
391 | [(set (match_operand:DI 0 "register_operand" "=r") | |
392 | (match_operand:DI 1 "symbolic_operand" "s")) | |
b5d37c6f | 393 | (clobber (match_operand:DI 2 "register_operand" "+r")) |
9a89adb8 RH |
394 | (use (reg:DI 1))] |
395 | "" | |
396 | "* abort ();" | |
397 | "" | |
398 | [(const_int 0)] | |
b5d37c6f | 399 | "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;") |
9a89adb8 | 400 | |
c65ebc55 | 401 | (define_insn "*movdi_internal" |
4b983fdc | 402 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 403 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 404 | (match_operand:DI 1 "move_operand" |
52e12ad0 | 405 | "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 406 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
407 | "* |
408 | { | |
409 | static const char * const alt[] = { | |
6f8aa100 RH |
410 | \"%,mov %0 = %r1\", |
411 | \"%,addl %0 = %1, r0\", | |
412 | \"%,movl %0 = %1\", | |
413 | \"%,ld8%O1 %0 = %1%P1\", | |
414 | \"%,st8%Q0 %0 = %r1%P0\", | |
415 | \"%,getf.sig %0 = %1\", | |
416 | \"%,setf.sig %0 = %r1\", | |
417 | \"%,mov %0 = %1\", | |
418 | \"%,ldf8 %0 = %1%P1\", | |
419 | \"%,stf8 %0 = %1%P0\", | |
420 | \"%,mov %0 = %1\", | |
5527bf14 RH |
421 | \"%,mov %0 = %r1\", |
422 | \"%,mov %0 = %1\", | |
514f96e6 RH |
423 | \"%,mov %0 = %1\", |
424 | \"%,mov %0 = %1\", | |
52e12ad0 | 425 | \"%,mov %0 = %1\", |
97e242b0 RH |
426 | \"mov %0 = pr\", |
427 | \"mov pr = %1, -1\" | |
9b7bf67d RH |
428 | }; |
429 | ||
9b7bf67d RH |
430 | if (which_alternative == 2 && ! TARGET_NO_PIC |
431 | && symbolic_operand (operands[1], VOIDmode)) | |
432 | abort (); | |
433 | ||
434 | return alt[which_alternative]; | |
435 | }" | |
52e12ad0 | 436 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 437 | |
9b7bf67d RH |
438 | (define_split |
439 | [(set (match_operand:DI 0 "register_operand" "") | |
440 | (match_operand:DI 1 "symbolic_operand" ""))] | |
441 | "reload_completed && ! TARGET_NO_PIC" | |
442 | [(const_int 0)] | |
443 | " | |
444 | { | |
b5d37c6f | 445 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d RH |
446 | DONE; |
447 | }") | |
448 | ||
c65ebc55 JW |
449 | (define_expand "load_fptr" |
450 | [(set (match_dup 2) | |
451 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" ""))) | |
ec039e3c | 452 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
453 | "" |
454 | " | |
455 | { | |
ec039e3c RH |
456 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
457 | operands[3] = gen_rtx_MEM (DImode, operands[2]); | |
458 | RTX_UNCHANGING_P (operands[3]) = 1; | |
c65ebc55 JW |
459 | }") |
460 | ||
461 | (define_insn "*load_fptr_internal1" | |
462 | [(set (match_operand:DI 0 "register_operand" "=r") | |
463 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))] | |
464 | "" | |
465 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 466 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
467 | |
468 | (define_insn "load_gprel" | |
469 | [(set (match_operand:DI 0 "register_operand" "=r") | |
470 | (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))] | |
471 | "" | |
472 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 473 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 474 | |
59da9a7d JW |
475 | (define_insn "gprel64_offset" |
476 | [(set (match_operand:DI 0 "register_operand" "=r") | |
477 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
478 | "" | |
479 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 480 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
481 | |
482 | (define_expand "load_gprel64" | |
483 | [(set (match_dup 2) | |
b5d37c6f | 484 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 485 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 486 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 487 | "" |
ec039e3c RH |
488 | " |
489 | { | |
490 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 491 | operands[3] = pic_offset_table_rtx; |
59da9a7d JW |
492 | }") |
493 | ||
c65ebc55 | 494 | (define_expand "load_symptr" |
b5d37c6f BS |
495 | [(set (match_operand:DI 2 "register_operand" "") |
496 | (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) | |
dee4095a | 497 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
498 | "" |
499 | " | |
500 | { | |
dee4095a | 501 | operands[3] = gen_rtx_MEM (DImode, operands[2]); |
b5d37c6f | 502 | operands[4] = pic_offset_table_rtx; |
dee4095a | 503 | RTX_UNCHANGING_P (operands[3]) = 1; |
c65ebc55 JW |
504 | }") |
505 | ||
506 | (define_insn "*load_symptr_internal1" | |
507 | [(set (match_operand:DI 0 "register_operand" "=r") | |
ec039e3c | 508 | (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))] |
c65ebc55 JW |
509 | "" |
510 | "addl %0 = @ltoff(%1), gp" | |
52e12ad0 | 511 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 512 | |
3f622353 RH |
513 | ;; With no offsettable memory references, we've got to have a scratch |
514 | ;; around to play with the second word. | |
515 | (define_expand "movti" | |
516 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
517 | (match_operand:TI 1 "general_operand" "")) | |
518 | (clobber (match_scratch:DI 2 ""))])] | |
519 | "" | |
520 | " | |
521 | { | |
522 | if (! reload_in_progress && ! reload_completed | |
523 | && ! ia64_move_ok (operands[0], operands[1])) | |
524 | operands[1] = force_reg (TImode, operands[1]); | |
525 | }") | |
526 | ||
527 | (define_insn_and_split "*movti_internal" | |
528 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
529 | (match_operand:TI 1 "general_operand" "ri,m,r")) | |
530 | (clobber (match_scratch:DI 2 "=X,&r,&r"))] | |
531 | "ia64_move_ok (operands[0], operands[1])" | |
532 | "#" | |
533 | "reload_completed" | |
534 | [(const_int 0)] | |
535 | " | |
536 | { | |
703cf211 | 537 | rtx adj1, adj2, in[2], out[2], insn; |
3f622353 RH |
538 | int first; |
539 | ||
540 | adj1 = ia64_split_timode (in, operands[1], operands[2]); | |
541 | adj2 = ia64_split_timode (out, operands[0], operands[2]); | |
542 | ||
543 | first = 0; | |
544 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
545 | { | |
546 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
547 | abort (); | |
548 | first = 1; | |
549 | } | |
550 | ||
551 | if (adj1 && adj2) | |
552 | abort (); | |
553 | if (adj1) | |
554 | emit_insn (adj1); | |
555 | if (adj2) | |
556 | emit_insn (adj2); | |
703cf211 BS |
557 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); |
558 | if (GET_CODE (out[first]) == MEM | |
559 | && GET_CODE (XEXP (out[first], 0)) == POST_MODIFY) | |
560 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
561 | XEXP (XEXP (out[first], 0), 0), | |
562 | REG_NOTES (insn)); | |
563 | insn = emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
564 | if (GET_CODE (out[!first]) == MEM | |
565 | && GET_CODE (XEXP (out[!first], 0)) == POST_MODIFY) | |
566 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, | |
567 | XEXP (XEXP (out[!first], 0), 0), | |
568 | REG_NOTES (insn)); | |
3f622353 RH |
569 | DONE; |
570 | }" | |
52e12ad0 | 571 | [(set_attr "itanium_class" "unknown") |
3f622353 | 572 | (set_attr "predicable" "no")]) |
e314e331 | 573 | |
3f622353 RH |
574 | ;; ??? SSA creates these. Can't allow memories since we don't have |
575 | ;; the scratch register. Fortunately combine will know how to add | |
576 | ;; the clobber and scratch. | |
577 | (define_insn_and_split "*movti_internal_reg" | |
578 | [(set (match_operand:TI 0 "register_operand" "=r") | |
579 | (match_operand:TI 1 "nonmemory_operand" "ri"))] | |
580 | "" | |
e314e331 | 581 | "#" |
3f622353 RH |
582 | "reload_completed" |
583 | [(const_int 0)] | |
584 | " | |
585 | { | |
586 | rtx in[2], out[2]; | |
587 | int first; | |
588 | ||
589 | ia64_split_timode (in, operands[1], NULL_RTX); | |
590 | ia64_split_timode (out, operands[0], NULL_RTX); | |
591 | ||
592 | first = 0; | |
593 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
594 | { | |
595 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
596 | abort (); | |
597 | first = 1; | |
598 | } | |
599 | ||
600 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
601 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
602 | DONE; | |
603 | }" | |
52e12ad0 | 604 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
605 | (set_attr "predicable" "no")]) |
606 | ||
3f622353 RH |
607 | (define_expand "reload_inti" |
608 | [(parallel [(set (match_operand:TI 0 "register_operand" "=r") | |
609 | (match_operand:TI 1 "" "m")) | |
60a3c181 | 610 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
611 | "" |
612 | " | |
613 | { | |
60a3c181 RH |
614 | unsigned int s_regno = REGNO (operands[2]); |
615 | if (s_regno == REGNO (operands[0])) | |
616 | s_regno += 1; | |
617 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 RH |
618 | }") |
619 | ||
620 | (define_expand "reload_outti" | |
621 | [(parallel [(set (match_operand:TI 0 "" "=m") | |
622 | (match_operand:TI 1 "register_operand" "r")) | |
60a3c181 | 623 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
624 | "" |
625 | " | |
626 | { | |
60a3c181 RH |
627 | unsigned int s_regno = REGNO (operands[2]); |
628 | if (s_regno == REGNO (operands[1])) | |
629 | s_regno += 1; | |
630 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 | 631 | }") |
e314e331 | 632 | |
c65ebc55 JW |
633 | ;; Floating Point Moves |
634 | ;; | |
635 | ;; Note - Patterns for SF mode moves are compulsory, but | |
636 | ;; patterns for DF are optional, as GCC can synthesise them. | |
637 | ||
638 | (define_expand "movsf" | |
639 | [(set (match_operand:SF 0 "general_operand" "") | |
640 | (match_operand:SF 1 "general_operand" ""))] | |
641 | "" | |
642 | " | |
643 | { | |
644 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
645 | && ! ia64_move_ok (operands[0], operands[1])) |
646 | operands[1] = force_reg (SFmode, operands[1]); | |
c65ebc55 JW |
647 | }") |
648 | ||
c65ebc55 | 649 | (define_insn "*movsf_internal" |
4b983fdc RH |
650 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
651 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 652 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
653 | "@ |
654 | mov %0 = %F1 | |
655 | ldfs %0 = %1%P1 | |
656 | stfs %0 = %F1%P0 | |
657 | getf.s %0 = %F1 | |
658 | setf.s %0 = %1 | |
659 | mov %0 = %1 | |
13da91fd RH |
660 | ld4%O1 %0 = %1%P1 |
661 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 662 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
663 | |
664 | (define_expand "movdf" | |
665 | [(set (match_operand:DF 0 "general_operand" "") | |
666 | (match_operand:DF 1 "general_operand" ""))] | |
667 | "" | |
668 | " | |
669 | { | |
670 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
671 | && ! ia64_move_ok (operands[0], operands[1])) |
672 | operands[1] = force_reg (DFmode, operands[1]); | |
c65ebc55 JW |
673 | }") |
674 | ||
c65ebc55 | 675 | (define_insn "*movdf_internal" |
4b983fdc RH |
676 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
677 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 678 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
679 | "@ |
680 | mov %0 = %F1 | |
681 | ldfd %0 = %1%P1 | |
682 | stfd %0 = %F1%P0 | |
683 | getf.d %0 = %F1 | |
684 | setf.d %0 = %1 | |
13da91fd RH |
685 | mov %0 = %1 |
686 | ld8%O1 %0 = %1%P1 | |
687 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 688 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 689 | |
3f622353 RH |
690 | ;; With no offsettable memory references, we've got to have a scratch |
691 | ;; around to play with the second word if the variable winds up in GRs. | |
692 | (define_expand "movtf" | |
693 | [(set (match_operand:TF 0 "general_operand" "") | |
694 | (match_operand:TF 1 "general_operand" ""))] | |
23c108af | 695 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a RH |
696 | " |
697 | { | |
3f622353 RH |
698 | /* We must support TFmode loads into general registers for stdarg/vararg |
699 | and unprototyped calls. We split them into DImode loads for convenience. | |
700 | We don't need TFmode stores from general regs, because a stdarg/vararg | |
701 | routine does a block store to memory of unnamed arguments. */ | |
702 | if (GET_CODE (operands[0]) == REG | |
703 | && GR_REGNO_P (REGNO (operands[0]))) | |
704 | { | |
705 | /* We're hoping to transform everything that deals with TFmode | |
706 | quantities and GR registers early in the compiler. */ | |
707 | if (no_new_pseudos) | |
708 | abort (); | |
709 | ||
710 | /* Struct to register can just use TImode instead. */ | |
711 | if ((GET_CODE (operands[1]) == SUBREG | |
712 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
713 | || (GET_CODE (operands[1]) == REG | |
714 | && GR_REGNO_P (REGNO (operands[1])))) | |
715 | { | |
716 | emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), | |
717 | SUBREG_REG (operands[1])); | |
718 | DONE; | |
719 | } | |
720 | ||
721 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
722 | { | |
723 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), | |
2bf47a10 | 724 | operand_subword (operands[1], 0, 0, TFmode)); |
3f622353 | 725 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), |
2bf47a10 | 726 | operand_subword (operands[1], 1, 0, TFmode)); |
3f622353 RH |
727 | DONE; |
728 | } | |
729 | ||
730 | /* If the quantity is in a register not known to be GR, spill it. */ | |
731 | if (register_operand (operands[1], TFmode)) | |
732 | operands[1] = spill_tfmode_operand (operands[1], 1); | |
733 | ||
734 | if (GET_CODE (operands[1]) == MEM) | |
735 | { | |
736 | rtx out[2]; | |
737 | ||
738 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
739 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); | |
740 | ||
f4ef873c RK |
741 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
742 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
743 | DONE; |
744 | } | |
745 | ||
746 | abort (); | |
747 | } | |
748 | ||
749 | if (! reload_in_progress && ! reload_completed) | |
750 | { | |
751 | operands[0] = spill_tfmode_operand (operands[0], 0); | |
752 | operands[1] = spill_tfmode_operand (operands[1], 0); | |
753 | ||
754 | if (! ia64_move_ok (operands[0], operands[1])) | |
755 | operands[1] = force_reg (TFmode, operands[1]); | |
756 | } | |
e5bde68a RH |
757 | }") |
758 | ||
3b572406 | 759 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 760 | |
3f622353 RH |
761 | (define_insn "*movtf_internal" |
762 | [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m") | |
763 | (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] | |
23c108af | 764 | "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" |
e5bde68a RH |
765 | "@ |
766 | mov %0 = %F1 | |
46b1ac3f JW |
767 | ldfe %0 = %1%P1 |
768 | stfe %0 = %F1%P0" | |
52e12ad0 | 769 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
c65ebc55 JW |
770 | \f |
771 | ;; :::::::::::::::::::: | |
772 | ;; :: | |
773 | ;; :: Conversions | |
774 | ;; :: | |
775 | ;; :::::::::::::::::::: | |
776 | ||
777 | ;; Signed conversions from a smaller integer to a larger integer | |
778 | ||
779 | (define_insn "extendqidi2" | |
0551c32d RH |
780 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
781 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
782 | "" |
783 | "sxt1 %0 = %1" | |
52e12ad0 | 784 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
785 | |
786 | (define_insn "extendhidi2" | |
0551c32d RH |
787 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
788 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
789 | "" |
790 | "sxt2 %0 = %1" | |
52e12ad0 | 791 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
792 | |
793 | (define_insn "extendsidi2" | |
655f2eb9 RH |
794 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
795 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
796 | "" |
797 | "@ | |
798 | sxt4 %0 = %1 | |
aebf2462 | 799 | fsxt.r %0 = %1, %1" |
52e12ad0 | 800 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
801 | |
802 | ;; Unsigned conversions from a smaller integer to a larger integer | |
803 | ||
804 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
805 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
806 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
807 | "" |
808 | "@ | |
809 | zxt1 %0 = %1 | |
810 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 811 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
812 | |
813 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
814 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
815 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
816 | "" |
817 | "@ | |
818 | zxt2 %0 = %1 | |
819 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 820 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
821 | |
822 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 823 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 824 | (zero_extend:DI |
655f2eb9 | 825 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
826 | "" |
827 | "@ | |
828 | zxt4 %0 = %1 | |
829 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 830 | fmix.r %0 = f0, %1" |
52e12ad0 | 831 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
832 | |
833 | ;; Convert between floating point types of different sizes. | |
834 | ||
640cea5f JW |
835 | ;; At first glance, it would appear that emitting fnorm for an extending |
836 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
837 | ;; correctly only if the input is properly rounded for its type. In | |
838 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
839 | ;; denorm single. Since we don't know what the next instruction will be, we | |
840 | ;; have to emit an fnorm. | |
841 | ||
e8e20f18 RH |
842 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
843 | ;; when we can. Should probably use a scheme like has been proposed | |
844 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
845 | ;; would let combine merge the thing into adjacent insns. See also how the |
846 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
847 | ;; se_register_operand. | |
c65ebc55 | 848 | |
640cea5f JW |
849 | (define_insn "extendsfdf2" |
850 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
851 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 852 | "" |
640cea5f JW |
853 | "fnorm.d %0 = %1" |
854 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 855 | |
640cea5f JW |
856 | (define_insn "extendsftf2" |
857 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
858 | (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))] | |
23c108af | 859 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
860 | "fnorm %0 = %1" |
861 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 862 | |
640cea5f JW |
863 | (define_insn "extenddftf2" |
864 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
865 | (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))] | |
23c108af | 866 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
867 | "fnorm %0 = %1" |
868 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 869 | |
c65ebc55 | 870 | (define_insn "truncdfsf2" |
0551c32d RH |
871 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
872 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 873 | "" |
aebf2462 | 874 | "fnorm.s %0 = %1" |
52e12ad0 | 875 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 876 | |
3f622353 | 877 | (define_insn "trunctfsf2" |
0551c32d RH |
878 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
879 | (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 880 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 881 | "fnorm.s %0 = %1" |
52e12ad0 | 882 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 883 | |
3f622353 | 884 | (define_insn "trunctfdf2" |
0551c32d RH |
885 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
886 | (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 887 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 888 | "fnorm.d %0 = %1" |
52e12ad0 | 889 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
890 | |
891 | ;; Convert between signed integer types and floating point. | |
892 | ||
3f622353 | 893 | (define_insn "floatditf2" |
0551c32d RH |
894 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
895 | (float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 896 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 897 | "fcvt.xf %0 = %1" |
52e12ad0 | 898 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 899 | |
23c108af SE |
900 | ;; ??? Suboptimal. This should be split somehow. |
901 | (define_insn "floatdidf2" | |
902 | [(set (match_operand:DF 0 "register_operand" "=f") | |
903 | (float:DF (match_operand:DI 1 "register_operand" "f")))] | |
904 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
905 | "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0" | |
906 | [(set_attr "itanium_class" "fcvtfx")]) | |
907 | ||
908 | ;; ??? Suboptimal. This should be split somehow. | |
909 | (define_insn "floatdisf2" | |
910 | [(set (match_operand:SF 0 "register_operand" "=f") | |
911 | (float:SF (match_operand:DI 1 "register_operand" "f")))] | |
912 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
913 | "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0" | |
914 | [(set_attr "itanium_class" "fcvtfx")]) | |
915 | ||
c65ebc55 | 916 | (define_insn "fix_truncsfdi2" |
0551c32d RH |
917 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
918 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 919 | "" |
aebf2462 | 920 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 921 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
922 | |
923 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
924 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
925 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 926 | "" |
aebf2462 | 927 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 928 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 929 | |
3f622353 | 930 | (define_insn "fix_trunctfdi2" |
0551c32d RH |
931 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
932 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 933 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 934 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 935 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 936 | |
655f2eb9 RH |
937 | (define_insn "fix_trunctfdi2_alts" |
938 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
939 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
940 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 941 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 942 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 943 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 944 | |
c65ebc55 JW |
945 | ;; Convert between unsigned integer types and floating point. |
946 | ||
947 | (define_insn "floatunsdisf2" | |
0551c32d RH |
948 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
949 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 950 | "" |
aebf2462 | 951 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 952 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
953 | |
954 | (define_insn "floatunsdidf2" | |
0551c32d RH |
955 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
956 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 957 | "" |
aebf2462 | 958 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 959 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 960 | |
3f622353 | 961 | (define_insn "floatunsditf2" |
0551c32d RH |
962 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
963 | (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 964 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 965 | "fcvt.xuf %0 = %1" |
52e12ad0 | 966 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 967 | |
c65ebc55 | 968 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
969 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
970 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 971 | "" |
aebf2462 | 972 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 973 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
974 | |
975 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
976 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
977 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 978 | "" |
aebf2462 | 979 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 980 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 981 | |
3f622353 | 982 | (define_insn "fixuns_trunctfdi2" |
0551c32d RH |
983 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
984 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 985 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 986 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 987 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 RH |
988 | |
989 | (define_insn "fixuns_trunctfdi2_alts" | |
990 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
991 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
992 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 993 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 994 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 995 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
996 | \f |
997 | ;; :::::::::::::::::::: | |
998 | ;; :: | |
999 | ;; :: Bit field extraction | |
1000 | ;; :: | |
1001 | ;; :::::::::::::::::::: | |
1002 | ||
c65ebc55 | 1003 | (define_insn "extv" |
0551c32d RH |
1004 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1005 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1006 | (match_operand:DI 2 "const_int_operand" "n") |
1007 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1008 | "" | |
1009 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1010 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1011 | |
1012 | (define_insn "extzv" | |
0551c32d RH |
1013 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1014 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1015 | (match_operand:DI 2 "const_int_operand" "n") |
1016 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1017 | "" | |
1018 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1019 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1020 | |
1021 | ;; Insert a bit field. | |
1022 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1023 | ;; Source1 can be 0 or -1. | |
1024 | ;; Source2 can be 0. | |
1025 | ||
1026 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1027 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1028 | ;; where source2 != dest. | |
1029 | ||
1030 | (define_expand "insv" | |
0551c32d | 1031 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1032 | (match_operand:DI 1 "const_int_operand" "") |
1033 | (match_operand:DI 2 "const_int_operand" "")) | |
1034 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1035 | "" | |
1036 | " | |
1037 | { | |
1038 | int width = INTVAL (operands[1]); | |
1039 | int shift = INTVAL (operands[2]); | |
1040 | ||
1041 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1042 | pseudo. */ | |
1043 | if (! register_operand (operands[3], DImode) | |
1044 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1045 | operands[3] = force_reg (DImode, operands[3]); | |
1046 | ||
1047 | /* If this is a single dep instruction, we have nothing to do. */ | |
1048 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1049 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1050 | { | |
1051 | /* Check for cases that can be implemented with a mix instruction. */ | |
1052 | if (width == 32 && shift == 0) | |
1053 | { | |
1054 | /* Directly generating the mix4left instruction confuses | |
1055 | optimize_bit_field in function.c. Since this is performing | |
1056 | a useful optimization, we defer generation of the complicated | |
1057 | mix4left RTL to the first splitting phase. */ | |
1058 | rtx tmp = gen_reg_rtx (DImode); | |
1059 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1060 | DONE; | |
1061 | } | |
1062 | else if (width == 32 && shift == 32) | |
1063 | { | |
1064 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1065 | DONE; | |
1066 | } | |
1067 | ||
d2ba6dcf JW |
1068 | /* We could handle remaining cases by emitting multiple dep |
1069 | instructions. | |
1070 | ||
1071 | If we need more than two dep instructions then we lose. A 6 | |
1072 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1073 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1074 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1075 | only one function unit that can execute dep and shr immed. | |
1076 | ||
1077 | If we only need two dep instruction, then we still lose. | |
1078 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1079 | the unnecessary mov, this is still undesirable because it will be | |
1080 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1081 | function unit. */ | |
1082 | ||
c65ebc55 JW |
1083 | FAIL; |
1084 | ||
1085 | #if 0 | |
1086 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1087 | for now. */ | |
1088 | while (width > 16) | |
1089 | { | |
1090 | rtx tmp; | |
1091 | ||
1092 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1093 | operands[3])); | |
1094 | shift += 16; | |
1095 | width -= 16; | |
1096 | tmp = gen_reg_rtx (DImode); | |
1097 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1098 | operands[3] = tmp; | |
1099 | } | |
1100 | operands[1] = GEN_INT (width); | |
1101 | operands[2] = GEN_INT (shift); | |
1102 | #endif | |
1103 | } | |
1104 | }") | |
1105 | ||
1106 | (define_insn "*insv_internal" | |
0551c32d | 1107 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1108 | (match_operand:DI 1 "const_int_operand" "n") |
1109 | (match_operand:DI 2 "const_int_operand" "n")) | |
1110 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1111 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1112 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1113 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1114 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1115 | |
041f25e6 RH |
1116 | ;; Combine doesn't like to create bitfield insertions into zero. |
1117 | (define_insn "*depz_internal" | |
0551c32d RH |
1118 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1119 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1120 | (match_operand:DI 2 "const_int_operand" "n")) |
1121 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1122 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1123 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
1124 | "* | |
1125 | { | |
1126 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1127 | return \"%,dep.z %0 = %1, %2, %3\"; | |
1128 | }" | |
52e12ad0 | 1129 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1130 | |
c65ebc55 | 1131 | (define_insn "shift_mix4left" |
0551c32d | 1132 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1133 | (const_int 32) (const_int 0)) |
0551c32d RH |
1134 | (match_operand:DI 1 "gr_register_operand" "r")) |
1135 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1136 | "" |
1137 | "#" | |
52e12ad0 | 1138 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1139 | |
c65ebc55 JW |
1140 | (define_split |
1141 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1142 | (const_int 32) (const_int 0)) | |
1143 | (match_operand:DI 1 "register_operand" "")) | |
1144 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1145 | "reload_completed" | |
1146 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
c65ebc55 JW |
1147 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) |
1148 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1149 | "operands[3] = operands[2];") | |
1150 | ||
1151 | (define_split | |
1152 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1153 | (const_int 32) (const_int 0)) | |
1154 | (match_operand:DI 1 "register_operand" "")) | |
1155 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1156 | "! reload_completed" | |
1157 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
1158 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1159 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1160 | "operands[3] = operands[2];") | |
1161 | ||
1162 | (define_insn "*mix4left" | |
0551c32d | 1163 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1164 | (const_int 32) (const_int 0)) |
0551c32d | 1165 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1166 | (const_int 32)))] |
1167 | "" | |
1168 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1169 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1170 | |
1171 | (define_insn "mix4right" | |
0551c32d | 1172 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1173 | (const_int 32) (const_int 32)) |
0551c32d | 1174 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1175 | "" |
1176 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1177 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1178 | |
1179 | ;; This is used by the rotrsi3 pattern. | |
1180 | ||
1181 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1182 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1183 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1184 | (ashift:DI (zero_extend:DI | |
1185 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1186 | (const_int 32))))] |
1187 | "" | |
fa9a44e8 | 1188 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1189 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1190 | |
1191 | \f | |
1192 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1193 | ;; :: |
f2f90c63 RH |
1194 | ;; :: 1 bit Integer arithmetic |
1195 | ;; :: | |
1196 | ;; :::::::::::::::::::: | |
1197 | ||
1198 | (define_insn_and_split "andbi3" | |
1199 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1200 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1201 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1202 | "" | |
1203 | "@ | |
1204 | # | |
1205 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1206 | and %0 = %2, %1" | |
1207 | "reload_completed | |
1208 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1209 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1210 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1211 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1212 | (match_dup 0))))] | |
1213 | "" | |
52e12ad0 | 1214 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1215 | |
1216 | (define_insn_and_split "*andcmbi3" | |
1217 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1218 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1219 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1220 | "" | |
1221 | "@ | |
1222 | # | |
967603ef | 1223 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1224 | andcm %0 = %2, %1" |
1225 | "reload_completed | |
1226 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1227 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1228 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1229 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1230 | (match_dup 0))))] | |
1231 | "" | |
52e12ad0 | 1232 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1233 | |
1234 | (define_insn_and_split "iorbi3" | |
1235 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1236 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1237 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1238 | "" | |
1239 | "@ | |
1240 | # | |
1241 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1242 | or %0 = %2, %1" | |
1243 | "reload_completed | |
1244 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1245 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1246 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1247 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1248 | (match_dup 0))))] | |
1249 | "" | |
52e12ad0 | 1250 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1251 | |
1252 | (define_insn_and_split "*iorcmbi3" | |
1253 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1254 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1255 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1256 | "" | |
1257 | "@ | |
1258 | # | |
967603ef | 1259 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1260 | "reload_completed |
1261 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1262 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1263 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1264 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1265 | (match_dup 0))))] | |
1266 | "" | |
52e12ad0 | 1267 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1268 | |
1269 | (define_insn "one_cmplbi2" | |
1270 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1271 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1272 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1273 | "" | |
1274 | "@ | |
1275 | tbit.z %0, %I0 = %1, 0 | |
1276 | xor %0 = 1, %1 | |
1277 | # | |
1278 | #" | |
52e12ad0 | 1279 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1280 | |
1281 | (define_split | |
1282 | [(set (match_operand:BI 0 "register_operand" "") | |
1283 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1284 | (clobber (match_scratch:BI 2 ""))] | |
1285 | "reload_completed | |
1286 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1287 | && rtx_equal_p (operands[0], operands[1])" |
1288 | [(set (match_dup 4) (match_dup 3)) | |
1289 | (set (match_dup 0) (const_int 1)) | |
1290 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1291 | (set (match_dup 0) (const_int 0))) | |
1292 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1293 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
1294 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1295 | ||
1296 | (define_split | |
1297 | [(set (match_operand:BI 0 "register_operand" "") | |
1298 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1299 | (clobber (match_scratch:BI 2 ""))] | |
1300 | "reload_completed | |
1301 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1302 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1303 | && ! rtx_equal_p (operands[0], operands[1])" | |
1304 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1305 | (set (match_dup 0) (const_int 0))) | |
1306 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1307 | (set (match_dup 0) (const_int 1))) | |
1308 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1309 | "") | |
1310 | ||
1311 | (define_insn "*cmpsi_and_0" | |
1312 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1313 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1314 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1315 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1316 | (match_operand:BI 1 "register_operand" "0")))] | |
1317 | "" | |
1318 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1319 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1320 | |
1321 | (define_insn "*cmpsi_and_1" | |
1322 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1323 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1324 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1325 | (const_int 0)]) | |
1326 | (match_operand:BI 1 "register_operand" "0")))] | |
1327 | "" | |
1328 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1329 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1330 | |
1331 | (define_insn "*cmpsi_andnot_0" | |
1332 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1333 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1334 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1335 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1336 | (match_operand:BI 1 "register_operand" "0")))] | |
1337 | "" | |
1338 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1339 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1340 | |
1341 | (define_insn "*cmpsi_andnot_1" | |
1342 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1343 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1344 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1345 | (const_int 0)])) | |
1346 | (match_operand:BI 1 "register_operand" "0")))] | |
1347 | "" | |
1348 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1349 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1350 | |
1351 | (define_insn "*cmpdi_and_0" | |
1352 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1353 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1354 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1355 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1356 | (match_operand:BI 1 "register_operand" "0")))] | |
1357 | "" | |
1358 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1359 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1360 | |
1361 | (define_insn "*cmpdi_and_1" | |
1362 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1363 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1364 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1365 | (const_int 0)]) | |
1366 | (match_operand:BI 1 "register_operand" "0")))] | |
1367 | "" | |
1368 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1369 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1370 | |
1371 | (define_insn "*cmpdi_andnot_0" | |
1372 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1373 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1374 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1375 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1376 | (match_operand:BI 1 "register_operand" "0")))] | |
1377 | "" | |
1378 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1379 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1380 | |
1381 | (define_insn "*cmpdi_andnot_1" | |
1382 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1383 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1384 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1385 | (const_int 0)])) | |
1386 | (match_operand:BI 1 "register_operand" "0")))] | |
1387 | "" | |
1388 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1389 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1390 | |
1391 | (define_insn "*tbit_and_0" | |
1392 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1393 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1394 | (const_int 1)) | |
1395 | (const_int 0)) | |
c77e04ae | 1396 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1397 | "" |
1398 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1399 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1400 | |
1401 | (define_insn "*tbit_and_1" | |
1402 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1403 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1404 | (const_int 1)) | |
1405 | (const_int 0)) | |
c77e04ae | 1406 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1407 | "" |
1408 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1409 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1410 | |
1411 | (define_insn "*tbit_and_2" | |
1412 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1413 | (and:BI (ne:BI (zero_extract:DI | |
1414 | (match_operand:DI 1 "gr_register_operand" "r") | |
1415 | (const_int 1) | |
1416 | (match_operand:DI 2 "const_int_operand" "n")) | |
1417 | (const_int 0)) | |
1418 | (match_operand:BI 3 "register_operand" "0")))] | |
1419 | "" | |
1420 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1421 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1422 | |
1423 | (define_insn "*tbit_and_3" | |
1424 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1425 | (and:BI (eq:BI (zero_extract:DI | |
1426 | (match_operand:DI 1 "gr_register_operand" "r") | |
1427 | (const_int 1) | |
1428 | (match_operand:DI 2 "const_int_operand" "n")) | |
1429 | (const_int 0)) | |
1430 | (match_operand:BI 3 "register_operand" "0")))] | |
1431 | "" | |
1432 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1433 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1434 | |
1435 | (define_insn "*cmpsi_or_0" | |
1436 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1437 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1438 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1439 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1440 | (match_operand:BI 1 "register_operand" "0")))] | |
1441 | "" | |
1442 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1443 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1444 | |
1445 | (define_insn "*cmpsi_or_1" | |
1446 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1447 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1448 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1449 | (const_int 0)]) | |
1450 | (match_operand:BI 1 "register_operand" "0")))] | |
1451 | "" | |
1452 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1453 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1454 | |
1455 | (define_insn "*cmpsi_orcm_0" | |
1456 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1457 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1458 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1459 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1460 | (match_operand:BI 1 "register_operand" "0")))] | |
1461 | "" | |
1462 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1463 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1464 | |
1465 | (define_insn "*cmpsi_orcm_1" | |
1466 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1467 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1468 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1469 | (const_int 0)])) | |
1470 | (match_operand:BI 1 "register_operand" "0")))] | |
1471 | "" | |
1472 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1473 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1474 | |
1475 | (define_insn "*cmpdi_or_0" | |
1476 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1477 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1478 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1479 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1480 | (match_operand:BI 1 "register_operand" "0")))] | |
1481 | "" | |
1482 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1483 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1484 | |
1485 | (define_insn "*cmpdi_or_1" | |
1486 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1487 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1488 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1489 | (const_int 0)]) | |
1490 | (match_operand:BI 1 "register_operand" "0")))] | |
1491 | "" | |
1492 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1493 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1494 | |
1495 | (define_insn "*cmpdi_orcm_0" | |
1496 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1497 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1498 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1499 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1500 | (match_operand:BI 1 "register_operand" "0")))] | |
1501 | "" | |
1502 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1503 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1504 | |
1505 | (define_insn "*cmpdi_orcm_1" | |
1506 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1507 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1508 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1509 | (const_int 0)])) | |
1510 | (match_operand:BI 1 "register_operand" "0")))] | |
1511 | "" | |
1512 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1513 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1514 | |
1515 | (define_insn "*tbit_or_0" | |
1516 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1517 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1518 | (const_int 1)) | |
1519 | (const_int 0)) | |
c77e04ae | 1520 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1521 | "" |
1522 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1523 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1524 | |
1525 | (define_insn "*tbit_or_1" | |
1526 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1527 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1528 | (const_int 1)) | |
1529 | (const_int 0)) | |
c77e04ae | 1530 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1531 | "" |
1532 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1533 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1534 | |
1535 | (define_insn "*tbit_or_2" | |
1536 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1537 | (ior:BI (ne:BI (zero_extract:DI | |
1538 | (match_operand:DI 1 "gr_register_operand" "r") | |
1539 | (const_int 1) | |
1540 | (match_operand:DI 2 "const_int_operand" "n")) | |
1541 | (const_int 0)) | |
1542 | (match_operand:BI 3 "register_operand" "0")))] | |
1543 | "" | |
1544 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1545 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1546 | |
1547 | (define_insn "*tbit_or_3" | |
1548 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1549 | (ior:BI (eq:BI (zero_extract:DI | |
1550 | (match_operand:DI 1 "gr_register_operand" "r") | |
1551 | (const_int 1) | |
1552 | (match_operand:DI 2 "const_int_operand" "n")) | |
1553 | (const_int 0)) | |
1554 | (match_operand:BI 3 "register_operand" "0")))] | |
1555 | "" | |
1556 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1557 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1558 | |
1559 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1560 | ||
1561 | (define_split | |
1562 | [(set (match_operand:BI 0 "register_operand" "") | |
1563 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1564 | (const_int 0)) | |
1565 | (match_operand:DI 3 "register_operand" "")) | |
1566 | (const_int 0)))] | |
1567 | "" | |
1568 | [(set (match_dup 0) | |
1569 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1570 | (match_dup 2)))] | |
1571 | "") | |
1572 | ||
1573 | (define_split | |
1574 | [(set (match_operand:BI 0 "register_operand" "") | |
1575 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1576 | (const_int 0)) | |
1577 | (match_operand:DI 3 "register_operand" "")) | |
1578 | (const_int 0)))] | |
1579 | "" | |
1580 | [(set (match_dup 0) | |
1581 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1582 | (match_dup 2))) | |
1583 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1584 | (clobber (scratch))])] | |
1585 | "") | |
1586 | ||
1587 | (define_split | |
1588 | [(set (match_operand:BI 0 "register_operand" "") | |
1589 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1590 | (const_int 0)) | |
1591 | (match_operand:DI 3 "register_operand" "")) | |
1592 | (const_int 0)))] | |
1593 | "" | |
1594 | [(set (match_dup 0) | |
1595 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1596 | (match_dup 2)))] | |
1597 | "") | |
1598 | ||
1599 | (define_split | |
1600 | [(set (match_operand:BI 0 "register_operand" "") | |
1601 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1602 | (const_int 0)) | |
1603 | (match_operand:DI 3 "register_operand" "")) | |
1604 | (const_int 0)))] | |
1605 | "" | |
1606 | [(set (match_dup 0) | |
1607 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1608 | (match_dup 2))) | |
1609 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1610 | (clobber (scratch))])] | |
1611 | "") | |
1612 | ||
1613 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1614 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1615 | ;; nothing bad happens to the comparisons in the meantime. | |
1616 | ;; | |
1617 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1618 | ;; that we're doing height reduction. | |
1619 | ; | |
1620 | ;(define_insn_and_split "" | |
1621 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1622 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1623 | ; [(match_operand 2 "" "") | |
1624 | ; (match_operand 3 "" "")]) | |
1625 | ; (match_operator:BI 4 "comparison_operator" | |
1626 | ; [(match_operand 5 "" "") | |
1627 | ; (match_operand 6 "" "")])) | |
1628 | ; (match_dup 0)))] | |
1629 | ; "flag_schedule_insns" | |
1630 | ; "#" | |
1631 | ; "" | |
1632 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1633 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1634 | ; "") | |
1635 | ; | |
1636 | ;(define_insn_and_split "" | |
1637 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1638 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1639 | ; [(match_operand 2 "" "") | |
1640 | ; (match_operand 3 "" "")]) | |
1641 | ; (match_operator:BI 4 "comparison_operator" | |
1642 | ; [(match_operand 5 "" "") | |
1643 | ; (match_operand 6 "" "")])) | |
1644 | ; (match_dup 0)))] | |
1645 | ; "flag_schedule_insns" | |
1646 | ; "#" | |
1647 | ; "" | |
1648 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1649 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1650 | ; "") | |
1651 | ; | |
1652 | ;(define_split | |
1653 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1654 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1655 | ; [(match_operand 2 "" "") | |
1656 | ; (match_operand 3 "" "")]) | |
1657 | ; (match_operand:BI 7 "register_operand" "")) | |
1658 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1659 | ; [(match_operand 5 "" "") | |
1660 | ; (match_operand 6 "" "")]) | |
1661 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1662 | ; "" | |
1663 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1664 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1665 | ; (match_dup 0)))] | |
1666 | ; "") | |
1667 | ; | |
1668 | ;(define_split | |
1669 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1670 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1671 | ; [(match_operand 2 "" "") | |
1672 | ; (match_operand 3 "" "")]) | |
1673 | ; (match_operand:BI 7 "register_operand" "")) | |
1674 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1675 | ; [(match_operand 5 "" "") | |
1676 | ; (match_operand 6 "" "")]) | |
1677 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1678 | ; "" | |
1679 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1680 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1681 | ; (match_dup 0)))] | |
1682 | ; "") | |
1683 | ||
1684 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1685 | ;; Note that we'll have already split the predicate copy, which | |
1686 | ;; is kind of a pain, but oh well. | |
1687 | ||
1688 | (define_peephole2 | |
1689 | [(set (match_operand:BI 0 "register_operand" "") | |
1690 | (match_operand:BI 1 "comparison_operator" "")) | |
1691 | (set (match_operand:CCI 2 "register_operand" "") | |
1692 | (match_operand:CCI 3 "register_operand" "")) | |
1693 | (set (match_operand:CCI 4 "register_operand" "") | |
1694 | (match_operand:CCI 5 "register_operand" "")) | |
1695 | (set (match_operand:BI 6 "register_operand" "") | |
1696 | (unspec:BI [(match_dup 6)] 7))] | |
1697 | "REGNO (operands[3]) == REGNO (operands[0]) | |
1698 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1699 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1700 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1701 | [(set (match_dup 0) (match_dup 1)) | |
1702 | (set (match_dup 6) (match_dup 7))] | |
1703 | "operands[7] = copy_rtx (operands[1]);") | |
1704 | \f | |
1705 | ;; :::::::::::::::::::: | |
1706 | ;; :: | |
cf1f6ae3 RH |
1707 | ;; :: 16 bit Integer arithmetic |
1708 | ;; :: | |
1709 | ;; :::::::::::::::::::: | |
1710 | ||
1711 | (define_insn "mulhi3" | |
1712 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1713 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1714 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1715 | "" | |
2a7ffc85 | 1716 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1717 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1718 | |
1719 | \f | |
1720 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1721 | ;; :: |
1722 | ;; :: 32 bit Integer arithmetic | |
1723 | ;; :: | |
1724 | ;; :::::::::::::::::::: | |
1725 | ||
058557c4 | 1726 | (define_insn "addsi3" |
0551c32d RH |
1727 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1728 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1729 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1730 | "" |
1731 | "@ | |
1732 | add %0 = %1, %2 | |
1733 | adds %0 = %2, %1 | |
1734 | addl %0 = %2, %1" | |
52e12ad0 | 1735 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1736 | |
1737 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1738 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1739 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1740 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1741 | (const_int 1)))] |
1742 | "" | |
1743 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1744 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1745 | |
5527bf14 | 1746 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1747 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1748 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1749 | (const_int 2)) |
1750 | (const_int 1)))] | |
1751 | "" | |
1752 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1753 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1754 | |
058557c4 | 1755 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1756 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1757 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1758 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1759 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1760 | "" |
058557c4 | 1761 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1762 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1763 | |
058557c4 | 1764 | (define_insn "subsi3" |
0551c32d RH |
1765 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1766 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1767 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1768 | "" |
1769 | "sub %0 = %1, %2" | |
52e12ad0 | 1770 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1771 | |
1772 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1773 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1774 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1775 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1776 | "" |
1777 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1778 | [(set_attr "itanium_class" "ialu")]) |
1779 | ||
1780 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1781 | |
058557c4 | 1782 | (define_insn "mulsi3" |
0551c32d | 1783 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1784 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1785 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1786 | "" |
aebf2462 | 1787 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1788 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1789 | |
655f2eb9 | 1790 | (define_insn "maddsi4" |
11a13704 RH |
1791 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1792 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1793 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1794 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1795 | "" | |
aebf2462 | 1796 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1797 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1798 | |
058557c4 | 1799 | (define_insn "negsi2" |
0551c32d RH |
1800 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1801 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1802 | "" |
1803 | "sub %0 = r0, %1" | |
52e12ad0 | 1804 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1805 | |
1806 | (define_expand "abssi2" | |
1807 | [(set (match_dup 2) | |
f2f90c63 | 1808 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1809 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1810 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1811 | (neg:SI (match_dup 1)) |
1812 | (match_dup 1)))] | |
c65ebc55 JW |
1813 | "" |
1814 | " | |
1815 | { | |
f2f90c63 | 1816 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1817 | }") |
1818 | ||
1819 | (define_expand "sminsi3" | |
1820 | [(set (match_dup 3) | |
f2f90c63 | 1821 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1822 | (match_operand:SI 2 "gr_register_operand" ""))) |
1823 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1824 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1825 | (match_dup 2) (match_dup 1)))] |
1826 | "" | |
1827 | " | |
1828 | { | |
f2f90c63 | 1829 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1830 | }") |
1831 | ||
1832 | (define_expand "smaxsi3" | |
1833 | [(set (match_dup 3) | |
f2f90c63 | 1834 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1835 | (match_operand:SI 2 "gr_register_operand" ""))) |
1836 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1837 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1838 | (match_dup 1) (match_dup 2)))] |
1839 | "" | |
1840 | " | |
1841 | { | |
f2f90c63 | 1842 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1843 | }") |
1844 | ||
1845 | (define_expand "uminsi3" | |
1846 | [(set (match_dup 3) | |
f2f90c63 | 1847 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1848 | (match_operand:SI 2 "gr_register_operand" ""))) |
1849 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1850 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1851 | (match_dup 2) (match_dup 1)))] |
1852 | "" | |
1853 | " | |
1854 | { | |
f2f90c63 | 1855 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1856 | }") |
1857 | ||
1858 | (define_expand "umaxsi3" | |
1859 | [(set (match_dup 3) | |
f2f90c63 | 1860 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1861 | (match_operand:SI 2 "gr_register_operand" ""))) |
1862 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1863 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1864 | (match_dup 1) (match_dup 2)))] |
1865 | "" | |
1866 | " | |
1867 | { | |
f2f90c63 | 1868 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1869 | }") |
1870 | ||
655f2eb9 RH |
1871 | (define_expand "divsi3" |
1872 | [(set (match_operand:SI 0 "register_operand" "") | |
1873 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1874 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1875 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1876 | " |
1877 | { | |
1878 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1879 | ||
1880 | op0_tf = gen_reg_rtx (TFmode); | |
1881 | op0_di = gen_reg_rtx (DImode); | |
1882 | ||
1883 | if (CONSTANT_P (operands[1])) | |
1884 | operands[1] = force_reg (SImode, operands[1]); | |
1885 | op1_tf = gen_reg_rtx (TFmode); | |
1886 | expand_float (op1_tf, operands[1], 0); | |
1887 | ||
1888 | if (CONSTANT_P (operands[2])) | |
1889 | operands[2] = force_reg (SImode, operands[2]); | |
1890 | op2_tf = gen_reg_rtx (TFmode); | |
1891 | expand_float (op2_tf, operands[2], 0); | |
1892 | ||
1893 | /* 2^-34 */ | |
1894 | #if 0 | |
1895 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1896 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1897 | twon34 = force_reg (TFmode, twon34); | |
1898 | #else | |
1899 | twon34 = gen_reg_rtx (TFmode); | |
1900 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1901 | #endif | |
1902 | ||
1903 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1904 | ||
1905 | emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1906 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1907 | DONE; | |
1908 | }") | |
1909 | ||
1910 | (define_expand "modsi3" | |
1911 | [(set (match_operand:SI 0 "register_operand" "") | |
1912 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
1913 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1914 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1915 | " |
1916 | { | |
1917 | rtx op2_neg, op1_di, div; | |
1918 | ||
1919 | div = gen_reg_rtx (SImode); | |
1920 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
1921 | ||
1922 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1923 | ||
1924 | /* This is a trick to get us to reuse the value that we're sure to | |
1925 | have already copied to the FP regs. */ | |
1926 | op1_di = gen_reg_rtx (DImode); | |
1927 | convert_move (op1_di, operands[1], 0); | |
1928 | ||
1929 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1930 | gen_lowpart (SImode, op1_di))); | |
1931 | DONE; | |
1932 | }") | |
1933 | ||
1934 | (define_expand "udivsi3" | |
1935 | [(set (match_operand:SI 0 "register_operand" "") | |
1936 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
1937 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1938 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1939 | " |
1940 | { | |
1941 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1942 | ||
1943 | op0_tf = gen_reg_rtx (TFmode); | |
1944 | op0_di = gen_reg_rtx (DImode); | |
1945 | ||
1946 | if (CONSTANT_P (operands[1])) | |
1947 | operands[1] = force_reg (SImode, operands[1]); | |
1948 | op1_tf = gen_reg_rtx (TFmode); | |
1949 | expand_float (op1_tf, operands[1], 1); | |
1950 | ||
1951 | if (CONSTANT_P (operands[2])) | |
1952 | operands[2] = force_reg (SImode, operands[2]); | |
1953 | op2_tf = gen_reg_rtx (TFmode); | |
1954 | expand_float (op2_tf, operands[2], 1); | |
1955 | ||
1956 | /* 2^-34 */ | |
1957 | #if 0 | |
1958 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1959 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1960 | twon34 = force_reg (TFmode, twon34); | |
1961 | #else | |
1962 | twon34 = gen_reg_rtx (TFmode); | |
1963 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1964 | #endif | |
1965 | ||
1966 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1967 | ||
1968 | emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1969 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1970 | DONE; | |
1971 | }") | |
1972 | ||
1973 | (define_expand "umodsi3" | |
1974 | [(set (match_operand:SI 0 "register_operand" "") | |
1975 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
1976 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1977 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1978 | " |
1979 | { | |
1980 | rtx op2_neg, op1_di, div; | |
1981 | ||
1982 | div = gen_reg_rtx (SImode); | |
1983 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
1984 | ||
1985 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1986 | ||
1987 | /* This is a trick to get us to reuse the value that we're sure to | |
1988 | have already copied to the FP regs. */ | |
1989 | op1_di = gen_reg_rtx (DImode); | |
1990 | convert_move (op1_di, operands[1], 1); | |
1991 | ||
1992 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1993 | gen_lowpart (SImode, op1_di))); | |
1994 | DONE; | |
1995 | }") | |
1996 | ||
1997 | (define_insn_and_split "divsi3_internal" | |
1998 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
1999 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2000 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2001 | (clobber (match_scratch:TF 4 "=&f")) | |
2002 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2003 | (clobber (match_scratch:BI 6 "=c")) |
655f2eb9 | 2004 | (use (match_operand:TF 3 "fr_register_operand" "f"))] |
23c108af | 2005 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2006 | "#" |
2007 | "&& reload_completed" | |
2008 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2009 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2010 | (use (const_int 1))]) |
2011 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2012 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2013 | (use (const_int 1))])) | |
2014 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2015 | (parallel [(set (match_dup 5) | |
2016 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2017 | (match_dup 7))) | |
2018 | (use (const_int 1))])) | |
2019 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2020 | (parallel [(set (match_dup 4) | |
2021 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2022 | (match_dup 4))) | |
2023 | (use (const_int 1))])) | |
2024 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2025 | (parallel [(set (match_dup 5) | |
2026 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
2027 | (match_dup 3))) | |
2028 | (use (const_int 1))])) | |
2029 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2030 | (parallel [(set (match_dup 0) | |
2031 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2032 | (match_dup 4))) | |
2033 | (use (const_int 1))])) | |
2034 | ] | |
2035 | "operands[7] = CONST1_RTX (TFmode);" | |
2036 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2037 | \f |
2038 | ;; :::::::::::::::::::: | |
2039 | ;; :: | |
2040 | ;; :: 64 bit Integer arithmetic | |
2041 | ;; :: | |
2042 | ;; :::::::::::::::::::: | |
2043 | ||
2044 | (define_insn "adddi3" | |
0551c32d RH |
2045 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2046 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2047 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2048 | "" |
2049 | "@ | |
2050 | add %0 = %1, %2 | |
2051 | adds %0 = %2, %1 | |
2052 | addl %0 = %2, %1" | |
52e12ad0 | 2053 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2054 | |
2055 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2056 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2057 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2058 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2059 | (const_int 1)))] |
2060 | "" | |
2061 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2062 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2063 | |
5527bf14 RH |
2064 | ;; This has some of the same problems as shladd. We let the shladd |
2065 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2066 | ;; a register, but not more ugliness here. | |
2067 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2068 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2069 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2070 | (const_int 2)) |
2071 | (const_int 1)))] | |
2072 | "" | |
2073 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2074 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2075 | |
c65ebc55 | 2076 | (define_insn "subdi3" |
0551c32d RH |
2077 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2078 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2079 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2080 | "" |
2081 | "sub %0 = %1, %2" | |
52e12ad0 | 2082 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2083 | |
2084 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2085 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2086 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2087 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2088 | "" |
2089 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2090 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2091 | |
cee58bc0 RH |
2092 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2093 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2094 | (define_insn "muldi3" |
0551c32d | 2095 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2096 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2097 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2098 | "" |
aebf2462 | 2099 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2100 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2101 | |
2102 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2103 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2104 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2105 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2106 | ;; here so that it will be present just in case register elimination gives us | |
2107 | ;; the funny result. | |
2108 | ||
2109 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2110 | ||
2111 | ;; ??? Maybe we should change how adds are canonicalized. | |
2112 | ||
655f2eb9 | 2113 | (define_insn "madddi4" |
0551c32d | 2114 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2115 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2116 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2117 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2118 | (clobber (match_scratch:DI 4 "=X"))] |
2119 | "" | |
aebf2462 | 2120 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2121 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2122 | |
2123 | ;; This can be created by register elimination if operand3 of shladd is an | |
2124 | ;; eliminable register or has reg_equiv_constant set. | |
2125 | ||
2126 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2127 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2128 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2129 | ;; incorrectly. |
2130 | ||
655f2eb9 | 2131 | (define_insn "*madddi4_elim" |
c65ebc55 | 2132 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2133 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2134 | (match_operand:DI 2 "register_operand" "f")) | |
2135 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2136 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2137 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2138 | "reload_in_progress" |
2139 | "#" | |
52e12ad0 | 2140 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2141 | |
c65ebc55 JW |
2142 | (define_split |
2143 | [(set (match_operand:DI 0 "register_operand" "") | |
2144 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2145 | (match_operand:DI 2 "register_operand" "")) | |
2146 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2147 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2148 | (clobber (match_scratch:DI 5 ""))] |
2149 | "reload_completed" | |
2150 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2151 | (match_dup 3))) | |
2152 | (clobber (match_dup 0))]) | |
c65ebc55 | 2153 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2154 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2155 | "") | |
2156 | ||
2157 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2158 | ;; to generate them. | |
2159 | ||
2160 | (define_insn "smuldi3_highpart" | |
0551c32d | 2161 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2162 | (truncate:DI |
2163 | (lshiftrt:TI | |
0551c32d RH |
2164 | (mult:TI (sign_extend:TI |
2165 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2166 | (sign_extend:TI | |
2167 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2168 | (const_int 64))))] |
2169 | "" | |
aebf2462 | 2170 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2171 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2172 | |
2173 | (define_insn "umuldi3_highpart" | |
0551c32d | 2174 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2175 | (truncate:DI |
2176 | (lshiftrt:TI | |
0551c32d RH |
2177 | (mult:TI (zero_extend:TI |
2178 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2179 | (zero_extend:TI | |
2180 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2181 | (const_int 64))))] |
2182 | "" | |
aebf2462 | 2183 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2184 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2185 | |
2186 | (define_insn "negdi2" | |
0551c32d RH |
2187 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2188 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2189 | "" |
2190 | "sub %0 = r0, %1" | |
52e12ad0 | 2191 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2192 | |
2193 | (define_expand "absdi2" | |
2194 | [(set (match_dup 2) | |
f2f90c63 | 2195 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2196 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2197 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2198 | (neg:DI (match_dup 1)) |
2199 | (match_dup 1)))] | |
c65ebc55 JW |
2200 | "" |
2201 | " | |
2202 | { | |
f2f90c63 | 2203 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2204 | }") |
2205 | ||
2206 | (define_expand "smindi3" | |
2207 | [(set (match_dup 3) | |
f2f90c63 | 2208 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2209 | (match_operand:DI 2 "gr_register_operand" ""))) |
2210 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2211 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2212 | (match_dup 2) (match_dup 1)))] |
2213 | "" | |
2214 | " | |
2215 | { | |
f2f90c63 | 2216 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2217 | }") |
2218 | ||
2219 | (define_expand "smaxdi3" | |
2220 | [(set (match_dup 3) | |
f2f90c63 | 2221 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2222 | (match_operand:DI 2 "gr_register_operand" ""))) |
2223 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2224 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2225 | (match_dup 1) (match_dup 2)))] |
2226 | "" | |
2227 | " | |
2228 | { | |
f2f90c63 | 2229 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2230 | }") |
2231 | ||
2232 | (define_expand "umindi3" | |
2233 | [(set (match_dup 3) | |
f2f90c63 | 2234 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2235 | (match_operand:DI 2 "gr_register_operand" ""))) |
2236 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2237 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2238 | (match_dup 2) (match_dup 1)))] |
2239 | "" | |
2240 | " | |
2241 | { | |
f2f90c63 | 2242 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2243 | }") |
2244 | ||
2245 | (define_expand "umaxdi3" | |
2246 | [(set (match_dup 3) | |
f2f90c63 | 2247 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2248 | (match_operand:DI 2 "gr_register_operand" ""))) |
2249 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2250 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2251 | (match_dup 1) (match_dup 2)))] |
2252 | "" | |
2253 | " | |
2254 | { | |
f2f90c63 | 2255 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2256 | }") |
2257 | ||
2258 | (define_expand "ffsdi2" | |
2259 | [(set (match_dup 6) | |
f2f90c63 | 2260 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2261 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2262 | (set (match_dup 5) (const_int 0)) | |
2263 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
2264 | (set (match_dup 4) (unspec:DI [(match_dup 3)] 8)) | |
0551c32d | 2265 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2266 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2267 | (match_dup 5) (match_dup 4)))] |
2268 | "" | |
2269 | " | |
2270 | { | |
2271 | operands[2] = gen_reg_rtx (DImode); | |
2272 | operands[3] = gen_reg_rtx (DImode); | |
2273 | operands[4] = gen_reg_rtx (DImode); | |
2274 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2275 | operands[6] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2276 | }") |
2277 | ||
2278 | (define_insn "*popcnt" | |
0551c32d RH |
2279 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2280 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))] | |
c65ebc55 JW |
2281 | "" |
2282 | "popcnt %0 = %1" | |
52e12ad0 | 2283 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2284 | |
655f2eb9 RH |
2285 | (define_expand "divdi3" |
2286 | [(set (match_operand:DI 0 "register_operand" "") | |
2287 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2288 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2289 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2290 | " |
2291 | { | |
2292 | rtx op1_tf, op2_tf, op0_tf; | |
2293 | ||
2294 | op0_tf = gen_reg_rtx (TFmode); | |
2295 | ||
2296 | if (CONSTANT_P (operands[1])) | |
2297 | operands[1] = force_reg (DImode, operands[1]); | |
2298 | op1_tf = gen_reg_rtx (TFmode); | |
2299 | expand_float (op1_tf, operands[1], 0); | |
2300 | ||
2301 | if (CONSTANT_P (operands[2])) | |
2302 | operands[2] = force_reg (DImode, operands[2]); | |
2303 | op2_tf = gen_reg_rtx (TFmode); | |
2304 | expand_float (op2_tf, operands[2], 0); | |
2305 | ||
2306 | if (TARGET_INLINE_DIV_LAT) | |
2307 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2308 | else | |
2309 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2310 | ||
2311 | emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2312 | DONE; | |
2313 | }") | |
2314 | ||
2315 | (define_expand "moddi3" | |
2316 | [(set (match_operand:DI 0 "register_operand" "") | |
2317 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2318 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2319 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2320 | " |
2321 | { | |
2322 | rtx op2_neg, div; | |
2323 | ||
2324 | div = gen_reg_rtx (DImode); | |
2325 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2326 | ||
2327 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2328 | ||
2329 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2330 | DONE; | |
2331 | }") | |
2332 | ||
2333 | (define_expand "udivdi3" | |
2334 | [(set (match_operand:DI 0 "register_operand" "") | |
2335 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2336 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2337 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2338 | " |
2339 | { | |
2340 | rtx op1_tf, op2_tf, op0_tf; | |
2341 | ||
2342 | op0_tf = gen_reg_rtx (TFmode); | |
2343 | ||
2344 | if (CONSTANT_P (operands[1])) | |
2345 | operands[1] = force_reg (DImode, operands[1]); | |
2346 | op1_tf = gen_reg_rtx (TFmode); | |
2347 | expand_float (op1_tf, operands[1], 1); | |
2348 | ||
2349 | if (CONSTANT_P (operands[2])) | |
2350 | operands[2] = force_reg (DImode, operands[2]); | |
2351 | op2_tf = gen_reg_rtx (TFmode); | |
2352 | expand_float (op2_tf, operands[2], 1); | |
2353 | ||
2354 | if (TARGET_INLINE_DIV_LAT) | |
2355 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2356 | else | |
2357 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2358 | ||
2359 | emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2360 | DONE; | |
2361 | }") | |
2362 | ||
2363 | (define_expand "umoddi3" | |
2364 | [(set (match_operand:DI 0 "register_operand" "") | |
2365 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2366 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2367 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2368 | " |
2369 | { | |
2370 | rtx op2_neg, div; | |
2371 | ||
2372 | div = gen_reg_rtx (DImode); | |
2373 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2374 | ||
2375 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2376 | ||
2377 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2378 | DONE; | |
2379 | }") | |
2380 | ||
2381 | (define_insn_and_split "divdi3_internal_lat" | |
2382 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2383 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2384 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2385 | (clobber (match_scratch:TF 3 "=&f")) | |
2386 | (clobber (match_scratch:TF 4 "=&f")) | |
2387 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2388 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2389 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
655f2eb9 RH |
2390 | "#" |
2391 | "&& reload_completed" | |
2392 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2393 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2394 | (use (const_int 1))]) |
2395 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2396 | (parallel [(set (match_dup 3) | |
2397 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2398 | (match_dup 7))) | |
2399 | (use (const_int 1))])) | |
2400 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2401 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2402 | (use (const_int 1))])) | |
2403 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2404 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
2405 | (use (const_int 1))])) | |
2406 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2407 | (parallel [(set (match_dup 4) | |
2408 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
2409 | (match_dup 4))) | |
2410 | (use (const_int 1))])) | |
2411 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2412 | (parallel [(set (match_dup 0) | |
2413 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2414 | (match_dup 0))) | |
2415 | (use (const_int 1))])) | |
2416 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2417 | (parallel [(set (match_dup 3) | |
2418 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2419 | (match_dup 4))) | |
2420 | (use (const_int 1))])) | |
2421 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2422 | (parallel [(set (match_dup 0) | |
2423 | (plus:TF (mult:TF (match_dup 5) (match_dup 0)) | |
2424 | (match_dup 0))) | |
2425 | (use (const_int 1))])) | |
2426 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2427 | (parallel [(set (match_dup 4) | |
2428 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2429 | (match_dup 1))) | |
2430 | (use (const_int 1))])) | |
2431 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2432 | (parallel [(set (match_dup 0) | |
2433 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2434 | (match_dup 3))) | |
2435 | (use (const_int 1))])) | |
2436 | ] | |
2437 | "operands[7] = CONST1_RTX (TFmode);" | |
2438 | [(set_attr "predicable" "no")]) | |
2439 | ||
2440 | (define_insn_and_split "divdi3_internal_thr" | |
2441 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2442 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2443 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2444 | (clobber (match_scratch:TF 3 "=&f")) | |
2445 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2446 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2447 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
655f2eb9 RH |
2448 | "#" |
2449 | "&& reload_completed" | |
2450 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2451 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2452 | (use (const_int 1))]) |
2453 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2454 | (parallel [(set (match_dup 3) | |
2455 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2456 | (match_dup 6))) | |
2457 | (use (const_int 1))])) | |
2458 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2459 | (parallel [(set (match_dup 0) | |
2460 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2461 | (match_dup 0))) | |
2462 | (use (const_int 1))])) | |
2463 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2464 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
2465 | (use (const_int 1))])) | |
2466 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2467 | (parallel [(set (match_dup 0) | |
2468 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2469 | (match_dup 0))) | |
2470 | (use (const_int 1))])) | |
2471 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2472 | (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1))) | |
2473 | (use (const_int 1))])) | |
2474 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2475 | (parallel [(set (match_dup 4) | |
2476 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2477 | (match_dup 1))) | |
2478 | (use (const_int 1))])) | |
2479 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2480 | (parallel [(set (match_dup 0) | |
2481 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2482 | (match_dup 3))) | |
2483 | (use (const_int 1))])) | |
2484 | ] | |
2485 | "operands[6] = CONST1_RTX (TFmode);" | |
2486 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2487 | \f |
2488 | ;; :::::::::::::::::::: | |
2489 | ;; :: | |
2490 | ;; :: 32 bit floating point arithmetic | |
2491 | ;; :: | |
2492 | ;; :::::::::::::::::::: | |
2493 | ||
2494 | (define_insn "addsf3" | |
0551c32d RH |
2495 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2496 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2497 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2498 | "" |
aebf2462 | 2499 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2500 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2501 | |
2502 | (define_insn "subsf3" | |
0551c32d RH |
2503 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2504 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2505 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2506 | "" |
aebf2462 | 2507 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2508 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2509 | |
2510 | (define_insn "mulsf3" | |
0551c32d RH |
2511 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2512 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2513 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2514 | "" |
aebf2462 | 2515 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2516 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2517 | |
2518 | (define_insn "abssf2" | |
0551c32d RH |
2519 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2520 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2521 | "" |
aebf2462 | 2522 | "fabs %0 = %1" |
52e12ad0 | 2523 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2524 | |
2525 | (define_insn "negsf2" | |
0551c32d RH |
2526 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2527 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2528 | "" |
aebf2462 | 2529 | "fneg %0 = %1" |
52e12ad0 | 2530 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2531 | |
2532 | (define_insn "*nabssf2" | |
0551c32d RH |
2533 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2534 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2535 | "" |
aebf2462 | 2536 | "fnegabs %0 = %1" |
52e12ad0 | 2537 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2538 | |
2539 | (define_insn "minsf3" | |
0551c32d RH |
2540 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2541 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2542 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2543 | "" |
aebf2462 | 2544 | "fmin %0 = %1, %F2" |
52e12ad0 | 2545 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2546 | |
2547 | (define_insn "maxsf3" | |
0551c32d RH |
2548 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2549 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2550 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2551 | "" |
aebf2462 | 2552 | "fmax %0 = %1, %F2" |
52e12ad0 | 2553 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2554 | |
655f2eb9 | 2555 | (define_insn "*maddsf4" |
0551c32d RH |
2556 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2557 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2558 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2559 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2560 | "" |
aebf2462 | 2561 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2562 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2563 | |
655f2eb9 | 2564 | (define_insn "*msubsf4" |
0551c32d RH |
2565 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2566 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2567 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2568 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2569 | "" |
aebf2462 | 2570 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2571 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2572 | |
2573 | (define_insn "*nmulsf3" | |
0551c32d RH |
2574 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2575 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2576 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2577 | "" |
aebf2462 | 2578 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2579 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2580 | |
2581 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? | |
2582 | ||
655f2eb9 | 2583 | (define_insn "*nmaddsf4" |
0551c32d | 2584 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
26102535 RH |
2585 | (plus:SF (neg:SF (mult:SF |
2586 | (match_operand:SF 1 "fr_register_operand" "f") | |
2587 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
0551c32d | 2588 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2589 | "" |
aebf2462 | 2590 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2591 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2592 | |
26102535 RH |
2593 | (define_expand "divsf3" |
2594 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2595 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2596 | (match_operand:SF 2 "fr_register_operand" "")))] | |
23c108af | 2597 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2598 | " |
2599 | { | |
2600 | rtx insn; | |
2601 | if (TARGET_INLINE_DIV_LAT) | |
2602 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); | |
2603 | else | |
2604 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2605 | emit_insn (insn); | |
2606 | DONE; | |
2607 | }") | |
2608 | ||
2609 | (define_insn_and_split "divsf3_internal_lat" | |
2610 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2611 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2612 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2613 | (clobber (match_scratch:TF 3 "=&f")) | |
2614 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2615 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2616 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2617 | "#" |
2618 | "&& reload_completed" | |
2619 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2620 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2621 | (use (const_int 1))]) |
2622 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2623 | (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) | |
2624 | (use (const_int 1))])) | |
2625 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2626 | (parallel [(set (match_dup 4) | |
2627 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2628 | (match_dup 10))) | |
2629 | (use (const_int 1))])) | |
2630 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2631 | (parallel [(set (match_dup 3) | |
2632 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2633 | (match_dup 3))) | |
2634 | (use (const_int 1))])) | |
2635 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2636 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2637 | (use (const_int 1))])) | |
2638 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2639 | (parallel [(set (match_dup 3) | |
2640 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2641 | (match_dup 3))) | |
2642 | (use (const_int 1))])) | |
2643 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2644 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2645 | (use (const_int 1))])) | |
2646 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2647 | (parallel [(set (match_dup 9) | |
2648 | (float_truncate:DF | |
2649 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2650 | (match_dup 3)))) | |
2651 | (use (const_int 1))])) | |
2652 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2653 | (set (match_dup 0) | |
2654 | (float_truncate:SF (match_dup 6)))) | |
2655 | ] | |
2656 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2657 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2658 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2659 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); | |
2660 | operands[10] = CONST1_RTX (TFmode);" | |
2661 | [(set_attr "predicable" "no")]) | |
2662 | ||
2663 | (define_insn_and_split "divsf3_internal_thr" | |
2664 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2665 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2666 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2667 | (clobber (match_scratch:TF 3 "=&f")) | |
2668 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2669 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2670 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2671 | "#" |
2672 | "&& reload_completed" | |
2673 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2674 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2675 | (use (const_int 1))]) |
2676 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2677 | (parallel [(set (match_dup 3) | |
2678 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2679 | (match_dup 10))) | |
2680 | (use (const_int 1))])) | |
2681 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2682 | (parallel [(set (match_dup 3) | |
2683 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
2684 | (match_dup 3))) | |
2685 | (use (const_int 1))])) | |
2686 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2687 | (parallel [(set (match_dup 6) | |
2688 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
2689 | (match_dup 6))) | |
2690 | (use (const_int 1))])) | |
2691 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2692 | (parallel [(set (match_dup 9) | |
2693 | (float_truncate:SF | |
2694 | (mult:TF (match_dup 7) (match_dup 6)))) | |
2695 | (use (const_int 1))])) | |
2696 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2697 | (parallel [(set (match_dup 4) | |
2698 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3))) | |
2699 | (match_dup 7))) | |
2700 | (use (const_int 1))])) | |
2701 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2702 | (set (match_dup 0) | |
2703 | (float_truncate:SF | |
2704 | (plus:TF (mult:TF (match_dup 4) (match_dup 6)) | |
2705 | (match_dup 3))))) | |
2706 | ] | |
2707 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2708 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2709 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2710 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); | |
2711 | operands[10] = CONST1_RTX (TFmode);" | |
2712 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2713 | \f |
2714 | ;; :::::::::::::::::::: | |
2715 | ;; :: | |
2716 | ;; :: 64 bit floating point arithmetic | |
2717 | ;; :: | |
2718 | ;; :::::::::::::::::::: | |
2719 | ||
2720 | (define_insn "adddf3" | |
0551c32d RH |
2721 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2722 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2723 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2724 | "" |
aebf2462 | 2725 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2726 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2727 | |
26102535 RH |
2728 | (define_insn "*adddf3_trunc" |
2729 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2730 | (float_truncate:SF | |
2731 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2732 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2733 | "" | |
aebf2462 | 2734 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2735 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2736 | |
c65ebc55 | 2737 | (define_insn "subdf3" |
0551c32d RH |
2738 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2739 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2740 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2741 | "" |
aebf2462 | 2742 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2743 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2744 | |
26102535 RH |
2745 | (define_insn "*subdf3_trunc" |
2746 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2747 | (float_truncate:SF | |
2748 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2749 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2750 | "" | |
aebf2462 | 2751 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2752 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2753 | |
c65ebc55 | 2754 | (define_insn "muldf3" |
0551c32d RH |
2755 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2756 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2757 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2758 | "" |
aebf2462 | 2759 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2760 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2761 | |
26102535 RH |
2762 | (define_insn "*muldf3_trunc" |
2763 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2764 | (float_truncate:SF | |
2765 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2766 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2767 | "" | |
aebf2462 | 2768 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2769 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2770 | |
c65ebc55 | 2771 | (define_insn "absdf2" |
0551c32d RH |
2772 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2773 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2774 | "" |
aebf2462 | 2775 | "fabs %0 = %1" |
52e12ad0 | 2776 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2777 | |
2778 | (define_insn "negdf2" | |
0551c32d RH |
2779 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2780 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2781 | "" |
aebf2462 | 2782 | "fneg %0 = %1" |
52e12ad0 | 2783 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2784 | |
2785 | (define_insn "*nabsdf2" | |
0551c32d RH |
2786 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2787 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2788 | "" |
aebf2462 | 2789 | "fnegabs %0 = %1" |
52e12ad0 | 2790 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2791 | |
2792 | (define_insn "mindf3" | |
0551c32d RH |
2793 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2794 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2795 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2796 | "" |
aebf2462 | 2797 | "fmin %0 = %1, %F2" |
52e12ad0 | 2798 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2799 | |
2800 | (define_insn "maxdf3" | |
0551c32d RH |
2801 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2802 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2803 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2804 | "" |
aebf2462 | 2805 | "fmax %0 = %1, %F2" |
52e12ad0 | 2806 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2807 | |
655f2eb9 | 2808 | (define_insn "*madddf4" |
0551c32d RH |
2809 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2810 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2811 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2812 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2813 | "" |
aebf2462 | 2814 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 2815 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2816 | |
26102535 RH |
2817 | (define_insn "*madddf4_trunc" |
2818 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2819 | (float_truncate:SF | |
2820 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2821 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2822 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2823 | "" | |
aebf2462 | 2824 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2825 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2826 | |
655f2eb9 | 2827 | (define_insn "*msubdf4" |
0551c32d RH |
2828 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2829 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2830 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2831 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2832 | "" |
aebf2462 | 2833 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 2834 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2835 | |
26102535 RH |
2836 | (define_insn "*msubdf4_trunc" |
2837 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2838 | (float_truncate:SF | |
2839 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2840 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2841 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2842 | "" | |
aebf2462 | 2843 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2844 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2845 | |
c65ebc55 | 2846 | (define_insn "*nmuldf3" |
0551c32d RH |
2847 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2848 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2849 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2850 | "" |
aebf2462 | 2851 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 2852 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2853 | |
26102535 RH |
2854 | (define_insn "*nmuldf3_trunc" |
2855 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2856 | (float_truncate:SF | |
2857 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2858 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
2859 | "" | |
aebf2462 | 2860 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2861 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2862 | |
c65ebc55 JW |
2863 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
2864 | ||
655f2eb9 | 2865 | (define_insn "*nmadddf4" |
0551c32d | 2866 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
26102535 RH |
2867 | (plus:DF (neg:DF (mult:DF |
2868 | (match_operand:DF 1 "fr_register_operand" "f") | |
2869 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
0551c32d | 2870 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2871 | "" |
aebf2462 | 2872 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 2873 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2874 | |
2875 | (define_insn "*nmadddf4_alts" | |
2876 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2877 | (plus:DF (neg:DF (mult:DF | |
2878 | (match_operand:DF 1 "fr_register_operand" "f") | |
2879 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2880 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))) | |
2881 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2882 | "" | |
aebf2462 | 2883 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 2884 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2885 | |
2886 | (define_insn "*nmadddf4_trunc" | |
2887 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2888 | (float_truncate:SF | |
2889 | (plus:DF (neg:DF (mult:DF | |
2890 | (match_operand:DF 1 "fr_register_operand" "f") | |
2891 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2892 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2893 | "" | |
aebf2462 | 2894 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2895 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2896 | |
2897 | (define_expand "divdf3" | |
2898 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
2899 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
2900 | (match_operand:DF 2 "fr_register_operand" "")))] | |
23c108af | 2901 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2902 | " |
2903 | { | |
2904 | rtx insn; | |
2905 | if (TARGET_INLINE_DIV_LAT) | |
2906 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); | |
2907 | else | |
2908 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
2909 | emit_insn (insn); | |
2910 | DONE; | |
2911 | }") | |
2912 | ||
2913 | (define_insn_and_split "divdf3_internal_lat" | |
2914 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2915 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2916 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2917 | (clobber (match_scratch:TF 3 "=&f")) | |
2918 | (clobber (match_scratch:TF 4 "=&f")) | |
2919 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2920 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2921 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2922 | "#" |
2923 | "&& reload_completed" | |
2924 | [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) | |
f2f90c63 | 2925 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5)) |
26102535 RH |
2926 | (use (const_int 1))]) |
2927 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2928 | (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) | |
2929 | (use (const_int 1))])) | |
2930 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2931 | (parallel [(set (match_dup 4) | |
2932 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7))) | |
2933 | (match_dup 12))) | |
2934 | (use (const_int 1))])) | |
2935 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2936 | (parallel [(set (match_dup 3) | |
2937 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2938 | (match_dup 3))) | |
2939 | (use (const_int 1))])) | |
2940 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2941 | (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4))) | |
2942 | (use (const_int 1))])) | |
2943 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2944 | (parallel [(set (match_dup 7) | |
2945 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2946 | (match_dup 7))) | |
2947 | (use (const_int 1))])) | |
2948 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2949 | (parallel [(set (match_dup 3) | |
2950 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
2951 | (match_dup 3))) | |
2952 | (use (const_int 1))])) | |
2953 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2954 | (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5))) | |
2955 | (use (const_int 1))])) | |
2956 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2957 | (parallel [(set (match_dup 7) | |
2958 | (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2959 | (match_dup 7))) | |
2960 | (use (const_int 1))])) | |
2961 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2962 | (parallel [(set (match_dup 10) | |
2963 | (float_truncate:DF | |
2964 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2965 | (match_dup 3)))) | |
2966 | (use (const_int 1))])) | |
2967 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2968 | (parallel [(set (match_dup 7) | |
2969 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2970 | (match_dup 7))) | |
2971 | (use (const_int 1))])) | |
2972 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2973 | (parallel [(set (match_dup 11) | |
2974 | (float_truncate:DF | |
2975 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3))) | |
2976 | (match_dup 8)))) | |
2977 | (use (const_int 1))])) | |
2978 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2979 | (set (match_dup 0) | |
2980 | (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2981 | (match_dup 3))))) | |
2982 | ] | |
2983 | "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2984 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2985 | operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2986 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
2987 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
2988 | operands[12] = CONST1_RTX (TFmode);" | |
2989 | [(set_attr "predicable" "no")]) | |
2990 | ||
2991 | (define_insn_and_split "divdf3_internal_thr" | |
2992 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2993 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2994 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2995 | (clobber (match_scratch:TF 3 "=&f")) | |
2996 | (clobber (match_scratch:DF 4 "=f")) | |
f2f90c63 | 2997 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2998 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2999 | "#" |
3000 | "&& reload_completed" | |
3001 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 3002 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
3003 | (use (const_int 1))]) |
3004 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3005 | (parallel [(set (match_dup 3) | |
3006 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
3007 | (match_dup 10))) | |
3008 | (use (const_int 1))])) | |
3009 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3010 | (parallel [(set (match_dup 6) | |
3011 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3012 | (match_dup 6))) | |
3013 | (use (const_int 1))])) | |
3014 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3015 | (parallel [(set (match_dup 3) | |
3016 | (mult:TF (match_dup 3) (match_dup 3))) | |
3017 | (use (const_int 1))])) | |
3018 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3019 | (parallel [(set (match_dup 6) | |
3020 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3021 | (match_dup 6))) | |
3022 | (use (const_int 1))])) | |
3023 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3024 | (parallel [(set (match_dup 3) | |
3025 | (mult:TF (match_dup 3) (match_dup 3))) | |
3026 | (use (const_int 1))])) | |
3027 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3028 | (parallel [(set (match_dup 6) | |
3029 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3030 | (match_dup 6))) | |
3031 | (use (const_int 1))])) | |
3032 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3033 | (parallel [(set (match_dup 9) | |
3034 | (float_truncate:DF | |
3035 | (mult:TF (match_dup 7) (match_dup 3)))) | |
3036 | (use (const_int 1))])) | |
3037 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3038 | (parallel [(set (match_dup 4) | |
3039 | (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9))) | |
3040 | (match_dup 1))) | |
3041 | (use (const_int 1))])) | |
3042 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3043 | (set (match_dup 0) | |
3044 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3045 | (match_dup 9)))) | |
3046 | ] | |
3047 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3048 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3049 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3050 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3051 | operands[10] = CONST1_RTX (TFmode);" | |
3052 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3053 | \f |
3054 | ;; :::::::::::::::::::: | |
3055 | ;; :: | |
3056 | ;; :: 80 bit floating point arithmetic | |
3057 | ;; :: | |
3058 | ;; :::::::::::::::::::: | |
3059 | ||
3060 | (define_insn "addtf3" | |
0551c32d | 3061 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3062 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3063 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3064 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3065 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3066 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3067 | |
26102535 RH |
3068 | (define_insn "*addtf3_truncsf" |
3069 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3070 | (float_truncate:SF | |
3071 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3072 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3073 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3074 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3075 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3076 | |
3077 | (define_insn "*addtf3_truncdf" | |
3078 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3079 | (float_truncate:DF | |
3080 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3081 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3082 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3083 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3084 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3085 | |
3f622353 | 3086 | (define_insn "subtf3" |
0551c32d | 3087 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3088 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3089 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3090 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3091 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3092 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3093 | |
26102535 RH |
3094 | (define_insn "*subtf3_truncsf" |
3095 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3096 | (float_truncate:SF | |
3097 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3098 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3099 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3100 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3101 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3102 | |
3103 | (define_insn "*subtf3_truncdf" | |
3104 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3105 | (float_truncate:DF | |
3106 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3107 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3108 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3109 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3110 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3111 | |
3f622353 | 3112 | (define_insn "multf3" |
0551c32d | 3113 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3114 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3115 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3116 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3117 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3118 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3119 | |
26102535 RH |
3120 | (define_insn "*multf3_truncsf" |
3121 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3122 | (float_truncate:SF | |
3123 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3124 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3125 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3126 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3127 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3128 | |
3129 | (define_insn "*multf3_truncdf" | |
3130 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3131 | (float_truncate:DF | |
3132 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3133 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3134 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3135 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3136 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3137 | |
655f2eb9 RH |
3138 | (define_insn "*multf3_alts" |
3139 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3140 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3141 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3142 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3143 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3144 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3145 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3146 | |
26102535 RH |
3147 | (define_insn "*multf3_truncsf_alts" |
3148 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3149 | (float_truncate:SF | |
3150 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3151 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3152 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3153 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3154 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3155 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3156 | |
3157 | (define_insn "*multf3_truncdf_alts" | |
3158 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3159 | (float_truncate:DF | |
3160 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3161 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3162 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3163 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3164 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3165 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3166 | |
3f622353 | 3167 | (define_insn "abstf2" |
0551c32d | 3168 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3169 | (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3170 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3171 | "fabs %0 = %F1" |
52e12ad0 | 3172 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3173 | |
3174 | (define_insn "negtf2" | |
0551c32d | 3175 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3176 | (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3177 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3178 | "fneg %0 = %F1" |
52e12ad0 | 3179 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3180 | |
3181 | (define_insn "*nabstf2" | |
0551c32d | 3182 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3183 | (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))] |
23c108af | 3184 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3185 | "fnegabs %0 = %F1" |
52e12ad0 | 3186 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3187 | |
3188 | (define_insn "mintf3" | |
0551c32d | 3189 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3190 | (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3191 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3192 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3193 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3194 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3195 | |
3196 | (define_insn "maxtf3" | |
0551c32d | 3197 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3198 | (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3199 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3200 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3201 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3202 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3203 | |
655f2eb9 | 3204 | (define_insn "*maddtf4" |
0551c32d | 3205 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3206 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3207 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3208 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3209 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3210 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3211 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3212 | |
26102535 RH |
3213 | (define_insn "*maddtf4_truncsf" |
3214 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3215 | (float_truncate:SF | |
3216 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3217 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3218 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3219 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3220 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3221 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3222 | |
3223 | (define_insn "*maddtf4_truncdf" | |
3224 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3225 | (float_truncate:DF | |
3226 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3227 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3228 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3229 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3230 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3231 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3232 | |
655f2eb9 RH |
3233 | (define_insn "*maddtf4_alts" |
3234 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3235 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3236 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3237 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3238 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3239 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3240 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3241 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3242 | |
26102535 RH |
3243 | (define_insn "*maddtf4_alts_truncdf" |
3244 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3245 | (float_truncate:DF | |
3246 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3247 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3248 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3249 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3250 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3251 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3252 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3253 | |
655f2eb9 | 3254 | (define_insn "*msubtf4" |
0551c32d | 3255 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3256 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3257 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3258 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3259 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3260 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3261 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3262 | |
26102535 RH |
3263 | (define_insn "*msubtf4_truncsf" |
3264 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3265 | (float_truncate:SF | |
3266 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3267 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3268 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3269 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3270 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3271 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3272 | |
3273 | (define_insn "*msubtf4_truncdf" | |
3274 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3275 | (float_truncate:DF | |
3276 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3277 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3278 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3279 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3280 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3281 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3282 | |
3f622353 | 3283 | (define_insn "*nmultf3" |
0551c32d | 3284 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3285 | (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3286 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3287 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3288 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3289 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3290 | |
26102535 RH |
3291 | (define_insn "*nmultf3_truncsf" |
3292 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3293 | (float_truncate:SF | |
3294 | (neg:TF (mult:TF | |
3295 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3296 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3297 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3298 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3299 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3300 | |
3301 | (define_insn "*nmultf3_truncdf" | |
3302 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3303 | (float_truncate:DF | |
3304 | (neg:TF (mult:TF | |
3305 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3306 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3307 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3308 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3309 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3310 | |
3f622353 RH |
3311 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
3312 | ||
655f2eb9 | 3313 | (define_insn "*nmaddtf4" |
0551c32d | 3314 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3315 | (plus:TF (neg:TF (mult:TF |
3316 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3317 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3318 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3319 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3320 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3321 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3322 | |
26102535 RH |
3323 | (define_insn "*nmaddtf4_truncsf" |
3324 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3325 | (float_truncate:SF | |
3326 | (plus:TF (neg:TF (mult:TF | |
3327 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3328 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3329 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3330 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3331 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3332 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3333 | |
3334 | (define_insn "*nmaddtf4_truncdf" | |
3335 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3336 | (float_truncate:DF | |
3337 | (plus:TF (neg:TF (mult:TF | |
3338 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3339 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3340 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3341 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3342 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3343 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3344 | |
655f2eb9 RH |
3345 | (define_insn "*nmaddtf4_alts" |
3346 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3347 | (plus:TF (neg:TF (mult:TF | |
3348 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3349 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3350 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3351 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3352 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3353 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3354 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3355 | |
26102535 RH |
3356 | (define_insn "*nmaddtf4_truncdf_alts" |
3357 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3358 | (float_truncate:DF | |
3359 | (plus:TF (neg:TF | |
3360 | (mult:TF | |
3361 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3362 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3363 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3364 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3365 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3366 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3367 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3368 | |
3369 | (define_expand "divtf3" | |
3370 | [(set (match_operand:TF 0 "fr_register_operand" "") | |
3371 | (div:TF (match_operand:TF 1 "fr_register_operand" "") | |
3372 | (match_operand:TF 2 "fr_register_operand" "")))] | |
23c108af | 3373 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3374 | " |
3375 | { | |
3376 | rtx insn; | |
3377 | if (TARGET_INLINE_DIV_LAT) | |
3378 | insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]); | |
3379 | else | |
3380 | insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); | |
3381 | emit_insn (insn); | |
3382 | DONE; | |
3383 | }") | |
3384 | ||
3385 | (define_insn_and_split "divtf3_internal_lat" | |
3386 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3387 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3388 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3389 | (clobber (match_scratch:TF 3 "=&f")) | |
3390 | (clobber (match_scratch:TF 4 "=&f")) | |
3391 | (clobber (match_scratch:TF 5 "=&f")) | |
3392 | (clobber (match_scratch:TF 6 "=&f")) | |
f2f90c63 | 3393 | (clobber (match_scratch:BI 7 "=c"))] |
23c108af | 3394 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3395 | "#" |
3396 | "&& reload_completed" | |
3397 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3398 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3399 | (use (const_int 1))]) |
3400 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3401 | (parallel [(set (match_dup 3) | |
3402 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3403 | (match_dup 8))) | |
3404 | (use (const_int 1))])) | |
3405 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3406 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3407 | (use (const_int 1))])) | |
3408 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3409 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
3410 | (use (const_int 1))])) | |
3411 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3412 | (parallel [(set (match_dup 6) | |
3413 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
3414 | (match_dup 3))) | |
3415 | (use (const_int 1))])) | |
3416 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3417 | (parallel [(set (match_dup 3) | |
3418 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
3419 | (match_dup 3))) | |
3420 | (use (const_int 1))])) | |
3421 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3422 | (parallel [(set (match_dup 5) | |
3423 | (plus:TF (mult:TF (match_dup 6) (match_dup 0)) | |
3424 | (match_dup 0))) | |
3425 | (use (const_int 1))])) | |
3426 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3427 | (parallel [(set (match_dup 0) | |
3428 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3429 | (match_dup 0))) | |
3430 | (use (const_int 1))])) | |
3431 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3432 | (parallel [(set (match_dup 4) | |
3433 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3434 | (match_dup 1))) | |
3435 | (use (const_int 1))])) | |
3436 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3437 | (parallel [(set (match_dup 3) | |
3438 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3439 | (match_dup 4))) | |
3440 | (use (const_int 1))])) | |
3441 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3442 | (parallel [(set (match_dup 5) | |
3443 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3444 | (match_dup 8))) | |
3445 | (use (const_int 1))])) | |
3446 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3447 | (parallel [(set (match_dup 0) | |
3448 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3449 | (match_dup 0))) | |
3450 | (use (const_int 1))])) | |
3451 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3452 | (parallel [(set (match_dup 4) | |
3453 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3454 | (match_dup 1))) | |
3455 | (use (const_int 1))])) | |
3456 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3457 | (set (match_dup 0) | |
3458 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3459 | (match_dup 3)))) | |
3460 | ] | |
3461 | "operands[8] = CONST1_RTX (TFmode);" | |
3462 | [(set_attr "predicable" "no")]) | |
3463 | ||
3464 | (define_insn_and_split "divtf3_internal_thr" | |
3465 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3466 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3467 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3468 | (clobber (match_scratch:TF 3 "=&f")) | |
3469 | (clobber (match_scratch:TF 4 "=&f")) | |
f2f90c63 | 3470 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3471 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3472 | "#" |
3473 | "&& reload_completed" | |
3474 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3475 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3476 | (use (const_int 1))]) |
3477 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3478 | (parallel [(set (match_dup 3) | |
3479 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3480 | (match_dup 6))) | |
3481 | (use (const_int 1))])) | |
3482 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3483 | (parallel [(set (match_dup 4) | |
3484 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3485 | (match_dup 0))) | |
3486 | (use (const_int 1))])) | |
3487 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3488 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
3489 | (use (const_int 1))])) | |
3490 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3491 | (parallel [(set (match_dup 3) | |
3492 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
3493 | (match_dup 4))) | |
3494 | (use (const_int 1))])) | |
3495 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3496 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3497 | (use (const_int 1))])) | |
3498 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3499 | (parallel [(set (match_dup 0) | |
3500 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3501 | (match_dup 6))) | |
3502 | (use (const_int 1))])) | |
3503 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3504 | (parallel [(set (match_dup 0) | |
3505 | (plus:TF (mult:TF (match_dup 0) (match_dup 3)) | |
3506 | (match_dup 3))) | |
3507 | (use (const_int 1))])) | |
3508 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3509 | (parallel [(set (match_dup 3) | |
3510 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3511 | (match_dup 1))) | |
3512 | (use (const_int 1))])) | |
3513 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3514 | (parallel [(set (match_dup 3) | |
3515 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3516 | (match_dup 4))) | |
3517 | (use (const_int 1))])) | |
3518 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3519 | (parallel [(set (match_dup 4) | |
3520 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3521 | (match_dup 6))) | |
3522 | (use (const_int 1))])) | |
3523 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3524 | (parallel [(set (match_dup 0) | |
3525 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3526 | (match_dup 0))) | |
3527 | (use (const_int 1))])) | |
3528 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3529 | (parallel [(set (match_dup 4) | |
3530 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3531 | (match_dup 1))) | |
3532 | (use (const_int 1))])) | |
3533 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3534 | (set (match_dup 0) | |
3535 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3536 | (match_dup 3)))) | |
3537 | ] | |
3538 | "operands[6] = CONST1_RTX (TFmode);" | |
3539 | [(set_attr "predicable" "no")]) | |
3540 | ||
3541 | ;; ??? frcpa works like cmp.foo.unc. | |
3542 | ||
655f2eb9 RH |
3543 | (define_insn "*recip_approx" |
3544 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3545 | (div:TF (const_int 1) | |
3546 | (match_operand:TF 3 "fr_register_operand" "f"))) | |
f2f90c63 RH |
3547 | (set (match_operand:BI 1 "register_operand" "=c") |
3548 | (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") | |
655f2eb9 RH |
3549 | (match_dup 3)] 5)) |
3550 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3551 | "INTEL_EXTENDED_IEEE_FORMAT" |
655f2eb9 | 3552 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 3553 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3554 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3555 | \f |
3556 | ;; :::::::::::::::::::: | |
3557 | ;; :: | |
3558 | ;; :: 32 bit Integer Shifts and Rotates | |
3559 | ;; :: | |
3560 | ;; :::::::::::::::::::: | |
3561 | ||
9c668921 | 3562 | (define_expand "ashlsi3" |
0551c32d RH |
3563 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3564 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3565 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 RH |
3566 | "" |
3567 | " | |
3568 | { | |
3569 | if (GET_CODE (operands[2]) != CONST_INT) | |
3570 | { | |
3571 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3572 | we've got to get rid of stray bits outside the SImode register. */ | |
3573 | rtx subshift = gen_reg_rtx (DImode); | |
3574 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3575 | operands[2] = subshift; | |
3576 | } | |
3577 | }") | |
3578 | ||
3579 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3580 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3581 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3582 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3583 | "" |
041f25e6 RH |
3584 | "@ |
3585 | shladd %0 = %1, %2, r0 | |
3586 | dep.z %0 = %1, %2, %E2 | |
3587 | shl %0 = %1, %2" | |
52e12ad0 | 3588 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3589 | |
3590 | (define_expand "ashrsi3" | |
0551c32d RH |
3591 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3592 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3593 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3594 | "" |
3595 | " | |
3596 | { | |
041f25e6 RH |
3597 | rtx subtarget = gen_reg_rtx (DImode); |
3598 | if (GET_CODE (operands[2]) == CONST_INT) | |
3599 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3600 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3601 | else | |
3602 | { | |
9c668921 | 3603 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3604 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3605 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3606 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3607 | } |
3608 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3609 | DONE; | |
c65ebc55 JW |
3610 | }") |
3611 | ||
c65ebc55 | 3612 | (define_expand "lshrsi3" |
0551c32d RH |
3613 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3614 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3615 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3616 | "" |
3617 | " | |
3618 | { | |
041f25e6 RH |
3619 | rtx subtarget = gen_reg_rtx (DImode); |
3620 | if (GET_CODE (operands[2]) == CONST_INT) | |
3621 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3622 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3623 | else | |
3624 | { | |
9c668921 | 3625 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3626 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3627 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3628 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3629 | } |
3630 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3631 | DONE; | |
c65ebc55 JW |
3632 | }") |
3633 | ||
c65ebc55 | 3634 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3635 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3636 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3637 | |
3638 | (define_expand "rotrsi3" | |
66db6b45 RH |
3639 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3640 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3641 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3642 | "" | |
3643 | " | |
3644 | { | |
3645 | if (GET_MODE (operands[2]) != VOIDmode) | |
3646 | { | |
3647 | rtx tmp = gen_reg_rtx (DImode); | |
3648 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3649 | operands[2] = tmp; | |
3650 | } | |
3651 | }") | |
3652 | ||
3653 | (define_insn_and_split "*rotrsi3_internal" | |
3654 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3655 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3656 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3657 | "" | |
3658 | "#" | |
3659 | "reload_completed" | |
c65ebc55 | 3660 | [(set (match_dup 3) |
66db6b45 | 3661 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3662 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3663 | (set (match_dup 3) | |
66db6b45 RH |
3664 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3665 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3666 | ||
3667 | (define_expand "rotlsi3" | |
3668 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3669 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3670 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3671 | "" |
3672 | " | |
3673 | { | |
3674 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3675 | { |
3676 | rtx tmp = gen_reg_rtx (SImode); | |
3677 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3678 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3679 | DONE; | |
3680 | } | |
c65ebc55 | 3681 | }") |
66db6b45 RH |
3682 | |
3683 | (define_insn_and_split "*rotlsi3_internal" | |
3684 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3685 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3686 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3687 | "" | |
3688 | "#" | |
3689 | "reload_completed" | |
3690 | [(set (match_dup 3) | |
3691 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3692 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3693 | (set (match_dup 3) | |
3694 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
3695 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3696 | operands[2] = GEN_INT (32 - INTVAL (operands[2]));") | |
c65ebc55 JW |
3697 | \f |
3698 | ;; :::::::::::::::::::: | |
3699 | ;; :: | |
3700 | ;; :: 64 bit Integer Shifts and Rotates | |
3701 | ;; :: | |
3702 | ;; :::::::::::::::::::: | |
3703 | ||
3704 | (define_insn "ashldi3" | |
52e12ad0 BS |
3705 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3706 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3707 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3708 | "" |
041f25e6 RH |
3709 | "@ |
3710 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3711 | shl %0 = %1, %2 |
041f25e6 | 3712 | shl %0 = %1, %2" |
52e12ad0 | 3713 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3714 | |
3715 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3716 | ||
3717 | (define_insn "*shladd" | |
0551c32d RH |
3718 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3719 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3720 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3721 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3722 | "" |
3723 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3724 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3725 | |
3726 | ;; This can be created by register elimination if operand3 of shladd is an | |
3727 | ;; eliminable register or has reg_equiv_constant set. | |
3728 | ||
3729 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3730 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3731 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3732 | ;; incorrectly. | |
3733 | ||
5527bf14 | 3734 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3735 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3736 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3737 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3738 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3739 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3740 | "reload_in_progress" | |
5527bf14 | 3741 | "* abort ();" |
c65ebc55 JW |
3742 | "reload_completed" |
3743 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3744 | (match_dup 3))) | |
c65ebc55 | 3745 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3746 | "" |
52e12ad0 | 3747 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3748 | |
3749 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3750 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3751 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3752 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3753 | "" |
52e12ad0 BS |
3754 | "@ |
3755 | shr %0 = %1, %2 | |
3756 | shr %0 = %1, %2" | |
3757 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3758 | |
3759 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3760 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3761 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3762 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3763 | "" |
52e12ad0 BS |
3764 | "@ |
3765 | shr.u %0 = %1, %2 | |
3766 | shr.u %0 = %1, %2" | |
3767 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3768 | |
3769 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3770 | ;; will load the operand into a register and call the pattern if the predicate | |
3771 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3772 | ;; verify that we have an appropriate constant in the expander. | |
3773 | ||
3774 | (define_expand "rotrdi3" | |
0551c32d RH |
3775 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3776 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3777 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3778 | "" | |
3779 | " | |
3780 | { | |
3781 | if (! shift_count_operand (operands[2], DImode)) | |
3782 | FAIL; | |
3783 | }") | |
3784 | ||
3785 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3786 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3787 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3788 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3789 | "" | |
3790 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3791 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3792 | |
66db6b45 RH |
3793 | (define_expand "rotldi3" |
3794 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3795 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3796 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3797 | "" | |
3798 | " | |
3799 | { | |
3800 | if (! shift_count_operand (operands[2], DImode)) | |
3801 | FAIL; | |
3802 | }") | |
3803 | ||
3804 | (define_insn "*rotldi3_internal" | |
3805 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3806 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3807 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3808 | "" | |
3809 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3810 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
3811 | \f |
3812 | ;; :::::::::::::::::::: | |
3813 | ;; :: | |
058557c4 | 3814 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
3815 | ;; :: |
3816 | ;; :::::::::::::::::::: | |
3817 | ||
3818 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3819 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3820 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3821 | ;; This doesn't work for unary logical operations, because we don't call | |
3822 | ;; apply_distributive_law for them. | |
3823 | ||
3824 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3825 | ;; apply_distributive_law. We get inefficient code for | |
3826 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3827 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3828 | ;; (zero_extend (and (not A) B)) in combine. | |
3829 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3830 | ;; one_cmplsi2 pattern. | |
3831 | ||
058557c4 | 3832 | (define_insn "one_cmplsi2" |
0551c32d RH |
3833 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3834 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3835 | "" |
3836 | "andcm %0 = -1, %1" | |
52e12ad0 | 3837 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3838 | \f |
3839 | ;; :::::::::::::::::::: | |
3840 | ;; :: | |
058557c4 | 3841 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
3842 | ;; :: |
3843 | ;; :::::::::::::::::::: | |
3844 | ||
3845 | (define_insn "anddi3" | |
0551c32d RH |
3846 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3847 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3848 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3849 | "" |
3850 | "@ | |
3851 | and %0 = %2, %1 | |
aebf2462 | 3852 | fand %0 = %2, %1" |
52e12ad0 | 3853 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3854 | |
3855 | (define_insn "*andnot" | |
0551c32d RH |
3856 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3857 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3858 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3859 | "" |
3860 | "@ | |
3861 | andcm %0 = %2, %1 | |
aebf2462 | 3862 | fandcm %0 = %2, %1" |
52e12ad0 | 3863 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3864 | |
3865 | (define_insn "iordi3" | |
0551c32d RH |
3866 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3867 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3868 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3869 | "" |
3870 | "@ | |
3871 | or %0 = %2, %1 | |
aebf2462 | 3872 | for %0 = %2, %1" |
52e12ad0 | 3873 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3874 | |
3875 | (define_insn "xordi3" | |
0551c32d RH |
3876 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3877 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3878 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3879 | "" |
3880 | "@ | |
3881 | xor %0 = %2, %1 | |
aebf2462 | 3882 | fxor %0 = %2, %1" |
52e12ad0 | 3883 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3884 | |
3885 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3886 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3887 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3888 | "" |
3889 | "andcm %0 = -1, %1" | |
52e12ad0 | 3890 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3891 | \f |
3892 | ;; :::::::::::::::::::: | |
3893 | ;; :: | |
3894 | ;; :: Comparisons | |
3895 | ;; :: | |
3896 | ;; :::::::::::::::::::: | |
3897 | ||
f2f90c63 RH |
3898 | (define_expand "cmpbi" |
3899 | [(set (cc0) | |
3900 | (compare (match_operand:BI 0 "register_operand" "") | |
3901 | (match_operand:BI 1 "const_int_operand" "")))] | |
3902 | "" | |
3903 | " | |
3904 | { | |
3905 | ia64_compare_op0 = operands[0]; | |
3906 | ia64_compare_op1 = operands[1]; | |
3907 | DONE; | |
3908 | }") | |
3909 | ||
c65ebc55 JW |
3910 | (define_expand "cmpsi" |
3911 | [(set (cc0) | |
0551c32d RH |
3912 | (compare (match_operand:SI 0 "gr_register_operand" "") |
3913 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3914 | "" |
3915 | " | |
3916 | { | |
3917 | ia64_compare_op0 = operands[0]; | |
3918 | ia64_compare_op1 = operands[1]; | |
3919 | DONE; | |
3920 | }") | |
3921 | ||
3922 | (define_expand "cmpdi" | |
3923 | [(set (cc0) | |
0551c32d RH |
3924 | (compare (match_operand:DI 0 "gr_register_operand" "") |
3925 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3926 | "" |
3927 | " | |
3928 | { | |
3929 | ia64_compare_op0 = operands[0]; | |
3930 | ia64_compare_op1 = operands[1]; | |
3931 | DONE; | |
3932 | }") | |
3933 | ||
3934 | (define_expand "cmpsf" | |
3935 | [(set (cc0) | |
0551c32d RH |
3936 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
3937 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3938 | "" |
3939 | " | |
3940 | { | |
3941 | ia64_compare_op0 = operands[0]; | |
3942 | ia64_compare_op1 = operands[1]; | |
3943 | DONE; | |
3944 | }") | |
3945 | ||
3946 | (define_expand "cmpdf" | |
3947 | [(set (cc0) | |
0551c32d RH |
3948 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
3949 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3950 | "" |
3951 | " | |
3952 | { | |
3953 | ia64_compare_op0 = operands[0]; | |
3954 | ia64_compare_op1 = operands[1]; | |
3955 | DONE; | |
3956 | }") | |
3957 | ||
3f622353 | 3958 | (define_expand "cmptf" |
c65ebc55 | 3959 | [(set (cc0) |
3f622353 RH |
3960 | (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") |
3961 | (match_operand:TF 1 "tfreg_or_fp01_operand" "")))] | |
23c108af | 3962 | "INTEL_EXTENDED_IEEE_FORMAT" |
c65ebc55 JW |
3963 | " |
3964 | { | |
3965 | ia64_compare_op0 = operands[0]; | |
3966 | ia64_compare_op1 = operands[1]; | |
3967 | DONE; | |
3968 | }") | |
3969 | ||
3970 | (define_insn "*cmpsi_normal" | |
f2f90c63 RH |
3971 | [(set (match_operand:BI 0 "register_operand" "=c") |
3972 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
3973 | [(match_operand:SI 2 "gr_register_operand" "r") |
3974 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
3975 | "" |
3976 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 3977 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3978 | |
18a3c539 JW |
3979 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3980 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3981 | ||
c65ebc55 | 3982 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
3983 | [(set (match_operand:BI 0 "register_operand" "=c") |
3984 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3985 | [(match_operand:SI 2 "gr_register_operand" "r") |
3986 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3987 | "" |
18a3c539 | 3988 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3989 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3990 | |
3991 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
3992 | [(set (match_operand:BI 0 "register_operand" "=c") |
3993 | (match_operator:BI 1 "normal_comparison_operator" | |
3994 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 3995 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 3996 | "" |
f2f90c63 | 3997 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 3998 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3999 | |
18a3c539 JW |
4000 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4001 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4002 | ||
c65ebc55 | 4003 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4004 | [(set (match_operand:BI 0 "register_operand" "=c") |
4005 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4006 | [(match_operand:DI 2 "gr_register_operand" "r") |
4007 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4008 | "" |
18a3c539 | 4009 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4010 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4011 | |
4012 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4013 | [(set (match_operand:BI 0 "register_operand" "=c") |
4014 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4015 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4016 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4017 | "" |
4018 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4019 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4020 | |
4021 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4022 | [(set (match_operand:BI 0 "register_operand" "=c") |
4023 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4024 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4025 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4026 | "" |
4027 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4028 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4029 | |
3f622353 | 4030 | (define_insn "*cmptf_internal" |
f2f90c63 RH |
4031 | [(set (match_operand:BI 0 "register_operand" "=c") |
4032 | (match_operator:BI 1 "comparison_operator" | |
3f622353 RH |
4033 | [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG") |
4034 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))] | |
23c108af | 4035 | "INTEL_EXTENDED_IEEE_FORMAT" |
3f622353 | 4036 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4037 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4038 | |
c65ebc55 JW |
4039 | ;; ??? Can this pattern be generated? |
4040 | ||
4041 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4042 | [(set (match_operand:BI 0 "register_operand" "=c") |
4043 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4044 | (const_int 1) |
4045 | (match_operand:DI 2 "immediate_operand" "n")) | |
4046 | (const_int 0)))] | |
4047 | "" | |
4048 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4049 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4050 | |
4051 | (define_insn "*bit_one" | |
f2f90c63 RH |
4052 | [(set (match_operand:BI 0 "register_operand" "=c") |
4053 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4054 | (const_int 1) |
4055 | (match_operand:DI 2 "immediate_operand" "n")) | |
4056 | (const_int 0)))] | |
4057 | "" | |
4058 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4059 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4060 | \f |
4061 | ;; :::::::::::::::::::: | |
4062 | ;; :: | |
4063 | ;; :: Branches | |
4064 | ;; :: | |
4065 | ;; :::::::::::::::::::: | |
4066 | ||
4067 | (define_expand "beq" | |
f2f90c63 RH |
4068 | [(set (pc) |
4069 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4070 | (label_ref (match_operand 0 "" "")) |
4071 | (pc)))] | |
4072 | "" | |
f2f90c63 | 4073 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4074 | |
4075 | (define_expand "bne" | |
f2f90c63 RH |
4076 | [(set (pc) |
4077 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4078 | (label_ref (match_operand 0 "" "")) |
4079 | (pc)))] | |
4080 | "" | |
f2f90c63 | 4081 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4082 | |
4083 | (define_expand "blt" | |
f2f90c63 RH |
4084 | [(set (pc) |
4085 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4086 | (label_ref (match_operand 0 "" "")) |
4087 | (pc)))] | |
4088 | "" | |
f2f90c63 | 4089 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4090 | |
4091 | (define_expand "ble" | |
f2f90c63 RH |
4092 | [(set (pc) |
4093 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4094 | (label_ref (match_operand 0 "" "")) |
4095 | (pc)))] | |
4096 | "" | |
f2f90c63 | 4097 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4098 | |
4099 | (define_expand "bgt" | |
f2f90c63 RH |
4100 | [(set (pc) |
4101 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4102 | (label_ref (match_operand 0 "" "")) |
4103 | (pc)))] | |
4104 | "" | |
f2f90c63 | 4105 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4106 | |
4107 | (define_expand "bge" | |
f2f90c63 RH |
4108 | [(set (pc) |
4109 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4110 | (label_ref (match_operand 0 "" "")) |
4111 | (pc)))] | |
4112 | "" | |
f2f90c63 | 4113 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4114 | |
4115 | (define_expand "bltu" | |
f2f90c63 RH |
4116 | [(set (pc) |
4117 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4118 | (label_ref (match_operand 0 "" "")) |
4119 | (pc)))] | |
4120 | "" | |
f2f90c63 | 4121 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4122 | |
4123 | (define_expand "bleu" | |
f2f90c63 RH |
4124 | [(set (pc) |
4125 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4126 | (label_ref (match_operand 0 "" "")) |
4127 | (pc)))] | |
4128 | "" | |
f2f90c63 | 4129 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4130 | |
4131 | (define_expand "bgtu" | |
f2f90c63 RH |
4132 | [(set (pc) |
4133 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4134 | (label_ref (match_operand 0 "" "")) |
4135 | (pc)))] | |
4136 | "" | |
f2f90c63 | 4137 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4138 | |
4139 | (define_expand "bgeu" | |
f2f90c63 RH |
4140 | [(set (pc) |
4141 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4142 | (label_ref (match_operand 0 "" "")) |
4143 | (pc)))] | |
4144 | "" | |
f2f90c63 | 4145 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4146 | |
e57b9d65 | 4147 | (define_expand "bunordered" |
f2f90c63 RH |
4148 | [(set (pc) |
4149 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4150 | (label_ref (match_operand 0 "" "")) |
4151 | (pc)))] | |
4152 | "" | |
f2f90c63 | 4153 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4154 | |
4155 | (define_expand "bordered" | |
f2f90c63 RH |
4156 | [(set (pc) |
4157 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4158 | (label_ref (match_operand 0 "" "")) |
4159 | (pc)))] | |
4160 | "" | |
f2f90c63 | 4161 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4162 | |
6b6c1201 | 4163 | (define_insn "*br_true" |
c65ebc55 | 4164 | [(set (pc) |
6b6c1201 | 4165 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4166 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4167 | (const_int 0)]) |
4168 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4169 | (pc)))] |
4170 | "" | |
85548039 | 4171 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4172 | [(set_attr "itanium_class" "br") |
e5bde68a | 4173 | (set_attr "predicable" "no")]) |
c65ebc55 | 4174 | |
6b6c1201 | 4175 | (define_insn "*br_false" |
c65ebc55 | 4176 | [(set (pc) |
6b6c1201 | 4177 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4178 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4179 | (const_int 0)]) |
c65ebc55 | 4180 | (pc) |
6b6c1201 | 4181 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4182 | "" |
85548039 | 4183 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4184 | [(set_attr "itanium_class" "br") |
e5bde68a | 4185 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4186 | \f |
4187 | ;; :::::::::::::::::::: | |
4188 | ;; :: | |
5527bf14 RH |
4189 | ;; :: Counted loop operations |
4190 | ;; :: | |
4191 | ;; :::::::::::::::::::: | |
4192 | ||
4193 | (define_expand "doloop_end" | |
4194 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4195 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4196 | (use (match_operand 2 "" "")) ; max iterations | |
4197 | (use (match_operand 3 "" "")) ; loop level | |
4198 | (use (match_operand 4 "" ""))] ; label | |
4199 | "" | |
4200 | " | |
4201 | { | |
4202 | /* Only use cloop on innermost loops. */ | |
4203 | if (INTVAL (operands[3]) > 1) | |
4204 | FAIL; | |
4205 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4206 | operands[4])); | |
4207 | DONE; | |
4208 | }") | |
4209 | ||
4210 | (define_insn "doloop_end_internal" | |
4211 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4212 | (const_int 0)) | |
4213 | (label_ref (match_operand 1 "" "")) | |
4214 | (pc))) | |
4215 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
4216 | (match_dup 0) | |
4217 | (plus:DI (match_dup 0) (const_int -1))))] | |
4218 | "" | |
4219 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4220 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4221 | (set_attr "predicable" "no")]) |
4222 | \f | |
4223 | ;; :::::::::::::::::::: | |
4224 | ;; :: | |
c65ebc55 JW |
4225 | ;; :: Set flag operations |
4226 | ;; :: | |
4227 | ;; :::::::::::::::::::: | |
4228 | ||
4229 | (define_expand "seq" | |
f2f90c63 | 4230 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4231 | "" |
f2f90c63 | 4232 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4233 | |
4234 | (define_expand "sne" | |
f2f90c63 | 4235 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4236 | "" |
f2f90c63 | 4237 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4238 | |
4239 | (define_expand "slt" | |
f2f90c63 | 4240 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4241 | "" |
f2f90c63 | 4242 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4243 | |
4244 | (define_expand "sle" | |
f2f90c63 | 4245 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4246 | "" |
f2f90c63 | 4247 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4248 | |
4249 | (define_expand "sgt" | |
f2f90c63 | 4250 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4251 | "" |
f2f90c63 | 4252 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4253 | |
4254 | (define_expand "sge" | |
f2f90c63 | 4255 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4256 | "" |
f2f90c63 | 4257 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4258 | |
4259 | (define_expand "sltu" | |
f2f90c63 | 4260 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4261 | "" |
f2f90c63 | 4262 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4263 | |
4264 | (define_expand "sleu" | |
f2f90c63 | 4265 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4266 | "" |
f2f90c63 | 4267 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4268 | |
4269 | (define_expand "sgtu" | |
f2f90c63 | 4270 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4271 | "" |
f2f90c63 | 4272 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4273 | |
4274 | (define_expand "sgeu" | |
f2f90c63 | 4275 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4276 | "" |
f2f90c63 | 4277 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4278 | |
e57b9d65 | 4279 | (define_expand "sunordered" |
f2f90c63 | 4280 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4281 | "" |
f2f90c63 | 4282 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4283 | |
4284 | (define_expand "sordered" | |
f2f90c63 | 4285 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4286 | "" |
f2f90c63 | 4287 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4288 | |
c65ebc55 JW |
4289 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4290 | ;; efficient than mov/mov/cst/cst. | |
4291 | ||
0551c32d RH |
4292 | (define_insn_and_split "*sne_internal" |
4293 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4294 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4295 | (const_int 0)))] |
4296 | "" | |
4297 | "#" | |
c65ebc55 | 4298 | "reload_completed" |
f2f90c63 RH |
4299 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4300 | (set (match_dup 0) (const_int 1))) | |
4301 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4302 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4303 | "" |
52e12ad0 | 4304 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4305 | |
0551c32d RH |
4306 | (define_insn_and_split "*seq_internal" |
4307 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4308 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4309 | (const_int 0)))] |
4310 | "" | |
4311 | "#" | |
c65ebc55 | 4312 | "reload_completed" |
f2f90c63 RH |
4313 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4314 | (set (match_dup 0) (const_int 0))) | |
4315 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4316 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4317 | "" |
52e12ad0 | 4318 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4319 | \f |
4320 | ;; :::::::::::::::::::: | |
4321 | ;; :: | |
4322 | ;; :: Conditional move instructions. | |
4323 | ;; :: | |
4324 | ;; :::::::::::::::::::: | |
4325 | ||
4326 | ;; ??? Add movXXcc patterns? | |
4327 | ||
c65ebc55 JW |
4328 | ;; |
4329 | ;; DImode if_then_else patterns. | |
4330 | ;; | |
4331 | ||
75cdbeb8 | 4332 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4333 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4334 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4335 | (if_then_else:DI |
f2f90c63 RH |
4336 | (match_operator 4 "predicate_operator" |
4337 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4338 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4339 | (const_int 0)]) |
f2f90c63 | 4340 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4341 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4342 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4343 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4344 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4345 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 RH |
4346 | "* abort ();" |
4347 | [(set_attr "predicable" "no")]) | |
4348 | ||
4349 | (define_split | |
f2f90c63 | 4350 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4351 | (if_then_else |
f2f90c63 RH |
4352 | (match_operator 4 "predicate_operator" |
4353 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4354 | (const_int 0)]) |
f2f90c63 RH |
4355 | (match_operand 2 "move_operand" "") |
4356 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4357 | "reload_completed" |
4358 | [(const_int 0)] | |
e5bde68a RH |
4359 | " |
4360 | { | |
3b572406 RH |
4361 | rtx tmp; |
4362 | if (! rtx_equal_p (operands[0], operands[2])) | |
e5bde68a | 4363 | { |
3b572406 RH |
4364 | tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]); |
4365 | tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp); | |
4366 | emit_insn (tmp); | |
e5bde68a | 4367 | } |
3b572406 RH |
4368 | if (! rtx_equal_p (operands[0], operands[3])) |
4369 | { | |
4370 | tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4371 | VOIDmode, operands[1], const0_rtx); |
3b572406 RH |
4372 | tmp = gen_rtx_COND_EXEC (VOIDmode, tmp, |
4373 | gen_rtx_SET (VOIDmode, operands[0], | |
4374 | operands[3])); | |
4375 | emit_insn (tmp); | |
4376 | } | |
4377 | DONE; | |
75cdbeb8 | 4378 | }") |
c65ebc55 JW |
4379 | |
4380 | ;; Absolute value pattern. | |
4381 | ||
4382 | (define_insn "*absdi2_internal" | |
0551c32d | 4383 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4384 | (if_then_else:DI |
f2f90c63 RH |
4385 | (match_operator 4 "predicate_operator" |
4386 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4387 | (const_int 0)]) |
0551c32d RH |
4388 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4389 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4390 | "" |
e5bde68a | 4391 | "#" |
52e12ad0 | 4392 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4393 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4394 | |
4395 | (define_split | |
4396 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4397 | (if_then_else:DI |
f2f90c63 RH |
4398 | (match_operator 4 "predicate_operator" |
4399 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4400 | (const_int 0)]) |
0551c32d RH |
4401 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4402 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4403 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4404 | [(cond_exec | |
4405 | (match_dup 4) | |
4406 | (set (match_dup 0) | |
4407 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4408 | "") |
4409 | ||
e5bde68a RH |
4410 | (define_split |
4411 | [(set (match_operand:DI 0 "register_operand" "") | |
4412 | (if_then_else:DI | |
f2f90c63 RH |
4413 | (match_operator 4 "predicate_operator" |
4414 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4415 | (const_int 0)]) |
0551c32d RH |
4416 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4417 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4418 | "reload_completed" |
4419 | [(cond_exec | |
4420 | (match_dup 4) | |
4421 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4422 | (cond_exec | |
4423 | (match_dup 5) | |
4424 | (set (match_dup 0) (match_dup 3)))] | |
4425 | " | |
4426 | { | |
4427 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4428 | VOIDmode, operands[1], const0_rtx); |
e5bde68a | 4429 | }") |
c65ebc55 JW |
4430 | |
4431 | ;; | |
4432 | ;; SImode if_then_else patterns. | |
4433 | ;; | |
4434 | ||
75cdbeb8 | 4435 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4436 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4437 | (if_then_else:SI |
f2f90c63 RH |
4438 | (match_operator 4 "predicate_operator" |
4439 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4440 | (const_int 0)]) |
f2f90c63 | 4441 | (match_operand:SI 2 "move_operand" |
3b572406 | 4442 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4443 | (match_operand:SI 3 "move_operand" |
3b572406 | 4444 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4445 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4446 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 | 4447 | "* abort ();" |
3b572406 | 4448 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4449 | |
4450 | (define_insn "*abssi2_internal" | |
0551c32d | 4451 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4452 | (if_then_else:SI |
f2f90c63 RH |
4453 | (match_operator 4 "predicate_operator" |
4454 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4455 | (const_int 0)]) |
0551c32d RH |
4456 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4457 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4458 | "" |
e5bde68a | 4459 | "#" |
52e12ad0 | 4460 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4461 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4462 | |
4463 | (define_split | |
4464 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4465 | (if_then_else:SI |
f2f90c63 RH |
4466 | (match_operator 4 "predicate_operator" |
4467 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4468 | (const_int 0)]) |
0551c32d RH |
4469 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4470 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4471 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4472 | [(cond_exec | |
4473 | (match_dup 4) | |
4474 | (set (match_dup 0) | |
4475 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4476 | "") |
4477 | ||
e5bde68a RH |
4478 | (define_split |
4479 | [(set (match_operand:SI 0 "register_operand" "") | |
4480 | (if_then_else:SI | |
f2f90c63 RH |
4481 | (match_operator 4 "predicate_operator" |
4482 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4483 | (const_int 0)]) |
0551c32d RH |
4484 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4485 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4486 | "reload_completed" |
4487 | [(cond_exec | |
4488 | (match_dup 4) | |
4489 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4490 | (cond_exec | |
4491 | (match_dup 5) | |
4492 | (set (match_dup 0) (match_dup 3)))] | |
4493 | " | |
4494 | { | |
4495 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4496 | VOIDmode, operands[1], const0_rtx); |
e5bde68a RH |
4497 | }") |
4498 | ||
7dcc803e | 4499 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
4500 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4501 | (match_operator:SI 5 "condop_operator" | |
4502 | [(if_then_else:SI | |
4503 | (match_operator 6 "predicate_operator" | |
4504 | [(match_operand:BI 1 "register_operand" "c") | |
4505 | (const_int 0)]) | |
4506 | (match_operand:SI 2 "gr_register_operand" "r") | |
4507 | (match_operand:SI 3 "gr_register_operand" "r")) | |
4508 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
4509 | "" | |
4510 | "#" | |
acb0638d BS |
4511 | "reload_completed" |
4512 | [(cond_exec | |
4513 | (match_dup 6) | |
4514 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
4515 | (cond_exec | |
4516 | (match_dup 7) | |
4517 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
4518 | " | |
4519 | { | |
4520 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4521 | VOIDmode, operands[1], const0_rtx); | |
7dcc803e BS |
4522 | }" |
4523 | [(set_attr "itanium_class" "ialu") | |
4524 | (set_attr "predicable" "no")]) | |
4525 | ||
acb0638d | 4526 | |
7dcc803e | 4527 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
4528 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4529 | (match_operator:SI 5 "condop_operator" | |
4530 | [(match_operand:SI 4 "gr_register_operand" "r") | |
4531 | (if_then_else:SI | |
4532 | (match_operator 6 "predicate_operator" | |
4533 | [(match_operand:BI 1 "register_operand" "c") | |
4534 | (const_int 0)]) | |
4535 | (match_operand:SI 2 "gr_register_operand" "r") | |
4536 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
4537 | "" | |
4538 | "#" | |
acb0638d BS |
4539 | "reload_completed" |
4540 | [(cond_exec | |
4541 | (match_dup 6) | |
4542 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
4543 | (cond_exec | |
4544 | (match_dup 7) | |
4545 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
4546 | " | |
4547 | { | |
4548 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
4549 | VOIDmode, operands[1], const0_rtx); | |
7dcc803e BS |
4550 | }" |
4551 | [(set_attr "itanium_class" "ialu") | |
4552 | (set_attr "predicable" "no")]) | |
acb0638d | 4553 | |
c65ebc55 JW |
4554 | \f |
4555 | ;; :::::::::::::::::::: | |
4556 | ;; :: | |
4557 | ;; :: Call and branch instructions | |
4558 | ;; :: | |
4559 | ;; :::::::::::::::::::: | |
4560 | ||
4561 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4562 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4563 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4564 | ;; registers used as operands. | |
4565 | ||
4566 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4567 | ;; is supplied for the sake of some RISC machines which need to put this | |
4568 | ;; information into the assembler code; they can put it in the RTL instead of | |
4569 | ;; operand 1. | |
4570 | ||
4571 | (define_expand "call" | |
4572 | [(use (match_operand:DI 0 "" "")) | |
4573 | (use (match_operand 1 "" "")) | |
4574 | (use (match_operand 2 "" "")) | |
4575 | (use (match_operand 3 "" ""))] | |
4576 | "" | |
4577 | " | |
4578 | { | |
2ed4af6f | 4579 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); |
c65ebc55 JW |
4580 | DONE; |
4581 | }") | |
4582 | ||
2ed4af6f RH |
4583 | (define_expand "sibcall" |
4584 | [(use (match_operand:DI 0 "" "")) | |
4585 | (use (match_operand 1 "" "")) | |
4586 | (use (match_operand 2 "" "")) | |
4587 | (use (match_operand 3 "" ""))] | |
c65ebc55 JW |
4588 | "" |
4589 | " | |
4590 | { | |
2ed4af6f RH |
4591 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); |
4592 | DONE; | |
c65ebc55 JW |
4593 | }") |
4594 | ||
c65ebc55 | 4595 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4596 | ;; register in which the value is returned. There are three more operands, |
4597 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4598 | ;; increased by one). |
2ed4af6f | 4599 | ;; |
c65ebc55 JW |
4600 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4601 | ||
4602 | (define_expand "call_value" | |
4603 | [(use (match_operand 0 "" "")) | |
4604 | (use (match_operand:DI 1 "" "")) | |
4605 | (use (match_operand 2 "" "")) | |
4606 | (use (match_operand 3 "" "")) | |
4607 | (use (match_operand 4 "" ""))] | |
4608 | "" | |
4609 | " | |
4610 | { | |
2ed4af6f | 4611 | ia64_expand_call (operands[0], operands[1], operands[3], 0); |
c65ebc55 JW |
4612 | DONE; |
4613 | }") | |
4614 | ||
2ed4af6f RH |
4615 | (define_expand "sibcall_value" |
4616 | [(use (match_operand 0 "" "")) | |
4617 | (use (match_operand:DI 1 "" "")) | |
4618 | (use (match_operand 2 "" "")) | |
4619 | (use (match_operand 3 "" "")) | |
4620 | (use (match_operand 4 "" ""))] | |
c65ebc55 JW |
4621 | "" |
4622 | " | |
4623 | { | |
2ed4af6f RH |
4624 | ia64_expand_call (operands[0], operands[1], operands[3], 1); |
4625 | DONE; | |
c65ebc55 JW |
4626 | }") |
4627 | ||
c65ebc55 JW |
4628 | ;; Call subroutine returning any type. |
4629 | ||
4630 | (define_expand "untyped_call" | |
4631 | [(parallel [(call (match_operand 0 "" "") | |
4632 | (const_int 0)) | |
4633 | (match_operand 1 "" "") | |
4634 | (match_operand 2 "" "")])] | |
4635 | "" | |
4636 | " | |
4637 | { | |
4638 | int i; | |
4639 | ||
4640 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4641 | ||
4642 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4643 | { | |
4644 | rtx set = XVECEXP (operands[2], 0, i); | |
4645 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4646 | } | |
4647 | ||
4648 | /* The optimizer does not know that the call sets the function value | |
4649 | registers we stored in the result block. We avoid problems by | |
4650 | claiming that all hard registers are used and clobbered at this | |
4651 | point. */ | |
4652 | emit_insn (gen_blockage ()); | |
4653 | ||
4654 | DONE; | |
4655 | }") | |
4656 | ||
2ed4af6f | 4657 | (define_insn "call_nopic" |
52e12ad0 | 4658 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4659 | (match_operand 1 "" "")) |
52e12ad0 | 4660 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4661 | "" |
4662 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4663 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4664 | |
4665 | (define_insn "call_value_nopic" | |
4666 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4667 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4668 | (match_operand 2 "" ""))) |
52e12ad0 | 4669 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4670 | "" |
4671 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4672 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4673 | |
4674 | (define_insn "sibcall_nopic" | |
52e12ad0 | 4675 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4676 | (match_operand 1 "" "")) |
6ca3c22f RH |
4677 | (use (match_operand:DI 2 "register_operand" "=b,b")) |
4678 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4679 | "" |
4680 | "br%+.many %0" | |
52e12ad0 | 4681 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4682 | |
4683 | (define_insn "call_pic" | |
52e12ad0 | 4684 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f RH |
4685 | (match_operand 1 "" "")) |
4686 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4687 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4688 | "" |
4689 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4690 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4691 | |
4692 | (define_insn "call_value_pic" | |
4693 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4694 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f RH |
4695 | (match_operand 2 "" ""))) |
4696 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4697 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4698 | "" |
4699 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4700 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4701 | |
4702 | (define_insn "sibcall_pic" | |
4703 | [(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) | |
4704 | (match_operand 1 "" "")) | |
4705 | (use (unspec [(reg:DI 1)] 9)) | |
6ca3c22f RH |
4706 | (use (match_operand:DI 2 "register_operand" "=b")) |
4707 | (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))] | |
2ed4af6f RH |
4708 | "" |
4709 | "br%+.many %0" | |
52e12ad0 | 4710 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4711 | |
c65ebc55 JW |
4712 | (define_insn "return_internal" |
4713 | [(return) | |
4714 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4715 | "" | |
4716 | "br.ret.sptk.many %0" | |
52e12ad0 | 4717 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4718 | |
4719 | (define_insn "return" | |
4720 | [(return)] | |
4721 | "ia64_direct_return ()" | |
4722 | "br.ret.sptk.many rp" | |
52e12ad0 | 4723 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4724 | |
6b6c1201 | 4725 | (define_insn "*return_true" |
c65ebc55 | 4726 | [(set (pc) |
6b6c1201 | 4727 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4728 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4729 | (const_int 0)]) |
c65ebc55 JW |
4730 | (return) |
4731 | (pc)))] | |
4732 | "ia64_direct_return ()" | |
13da91fd | 4733 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4734 | [(set_attr "itanium_class" "br") |
e5bde68a | 4735 | (set_attr "predicable" "no")]) |
c65ebc55 | 4736 | |
6b6c1201 | 4737 | (define_insn "*return_false" |
c65ebc55 | 4738 | [(set (pc) |
6b6c1201 | 4739 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4740 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4741 | (const_int 0)]) |
c65ebc55 JW |
4742 | (pc) |
4743 | (return)))] | |
4744 | "ia64_direct_return ()" | |
13da91fd | 4745 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4746 | [(set_attr "itanium_class" "br") |
e5bde68a | 4747 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4748 | |
4749 | (define_insn "jump" | |
4750 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4751 | "" | |
4752 | "br %l0" | |
52e12ad0 | 4753 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4754 | |
4755 | (define_insn "indirect_jump" | |
4756 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4757 | "" | |
4758 | "br %0" | |
52e12ad0 | 4759 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4760 | |
4761 | (define_expand "tablejump" | |
340f7e7c RH |
4762 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
4763 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 4764 | "" |
c65ebc55 | 4765 | { |
340f7e7c RH |
4766 | rtx op0 = operands[0]; |
4767 | rtx addr; | |
4768 | ||
4769 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
4770 | element into a register without bothering to see whether that | |
4771 | is necessary given the operand predicate. Check for MEM just | |
4772 | in case someone fixes this. */ | |
4773 | if (GET_CODE (op0) == MEM) | |
4774 | addr = XEXP (op0, 0); | |
4775 | else | |
4776 | { | |
4777 | /* Otherwise, cheat and guess that the previous insn in the | |
4778 | stream was the memory load. Grab the address from that. | |
4779 | Note we have to momentarily pop out of the sequence started | |
4780 | by the insn-emit wrapper in order to grab the last insn. */ | |
4781 | rtx last, set; | |
4782 | ||
4783 | end_sequence (); | |
4784 | last = get_last_insn (); | |
4785 | start_sequence (); | |
4786 | set = single_set (last); | |
4787 | ||
4788 | if (! rtx_equal_p (SET_DEST (set), op0) | |
4789 | || GET_CODE (SET_SRC (set)) != MEM) | |
4790 | abort (); | |
4791 | addr = XEXP (SET_SRC (set), 0); | |
4792 | if (rtx_equal_p (addr, op0)) | |
4793 | abort (); | |
4794 | } | |
c65ebc55 | 4795 | |
340f7e7c RH |
4796 | /* Jump table elements are stored pc-relative. That is, a displacement |
4797 | from the entry to the label. Thus to convert to an absolute address | |
4798 | we add the address of the memory from which the value is loaded. */ | |
4799 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
4800 | NULL_RTX, 1, OPTAB_DIRECT); | |
4801 | }) | |
c65ebc55 | 4802 | |
340f7e7c | 4803 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
4804 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
4805 | (use (label_ref (match_operand 1 "" "")))] | |
4806 | "" | |
4807 | "br %0" | |
52e12ad0 | 4808 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4809 | |
4810 | \f | |
4811 | ;; :::::::::::::::::::: | |
4812 | ;; :: | |
4813 | ;; :: Prologue and Epilogue instructions | |
4814 | ;; :: | |
4815 | ;; :::::::::::::::::::: | |
4816 | ||
4817 | (define_expand "prologue" | |
4818 | [(const_int 1)] | |
4819 | "" | |
4820 | " | |
4821 | { | |
4822 | ia64_expand_prologue (); | |
4823 | DONE; | |
4824 | }") | |
4825 | ||
4826 | (define_expand "epilogue" | |
2ed4af6f RH |
4827 | [(return)] |
4828 | "" | |
4829 | " | |
4830 | { | |
4831 | ia64_expand_epilogue (0); | |
4832 | DONE; | |
4833 | }") | |
4834 | ||
4835 | (define_expand "sibcall_epilogue" | |
4836 | [(return)] | |
c65ebc55 JW |
4837 | "" |
4838 | " | |
4839 | { | |
2ed4af6f | 4840 | ia64_expand_epilogue (1); |
c65ebc55 JW |
4841 | DONE; |
4842 | }") | |
4843 | ||
4844 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4845 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4846 | ||
4847 | (define_insn "prologue_allocate_stack" | |
4848 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4849 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4850 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 4851 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
4852 | (match_dup 3))] |
4853 | "" | |
4854 | "@ | |
4855 | add %0 = %1, %2 | |
4856 | adds %0 = %2, %1 | |
4857 | addl %0 = %2, %1" | |
52e12ad0 | 4858 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4859 | |
4860 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4861 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4862 | ||
4863 | (define_insn "epilogue_deallocate_stack" | |
4864 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4865 | (match_operand:DI 1 "register_operand" "+r")) | |
4866 | (set (match_dup 1) (match_dup 1))] | |
4867 | "" | |
4868 | "mov %0 = %1" | |
52e12ad0 | 4869 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4870 | |
4871 | ;; Allocate a new register frame. | |
4872 | ||
4873 | (define_insn "alloc" | |
4874 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4875 | (unspec_volatile:DI [(const_int 0)] 0)) | |
4876 | (use (match_operand:DI 1 "const_int_operand" "i")) | |
4877 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4878 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4879 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4880 | "" | |
4881 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4882 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 4883 | (set_attr "predicable" "no")]) |
c65ebc55 | 4884 | |
97e242b0 RH |
4885 | ;; Modifies ar.unat |
4886 | (define_expand "gr_spill" | |
870f9ec0 RH |
4887 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4888 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
4889 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4890 | (clobber (match_dup 3))])] | |
97e242b0 | 4891 | "" |
870f9ec0 | 4892 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4893 | |
870f9ec0 | 4894 | (define_insn "gr_spill_internal" |
c65ebc55 | 4895 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 RH |
4896 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
4897 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4898 | (clobber (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4899 | "" |
2130b7fb BS |
4900 | "* |
4901 | { | |
4902 | return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\"; | |
4903 | }" | |
52e12ad0 | 4904 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4905 | |
97e242b0 RH |
4906 | ;; Reads ar.unat |
4907 | (define_expand "gr_restore" | |
870f9ec0 RH |
4908 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4909 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
4910 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4911 | (use (match_dup 3))])] | |
97e242b0 | 4912 | "" |
870f9ec0 | 4913 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4914 | |
870f9ec0 | 4915 | (define_insn "gr_restore_internal" |
c65ebc55 | 4916 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 RH |
4917 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
4918 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4919 | (use (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4920 | "" |
2130b7fb BS |
4921 | "* |
4922 | { | |
4923 | return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\"; | |
4924 | }" | |
52e12ad0 | 4925 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4926 | |
4927 | (define_insn "fr_spill" | |
3f622353 RH |
4928 | [(set (match_operand:TF 0 "memory_operand" "=m") |
4929 | (unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))] | |
c65ebc55 JW |
4930 | "" |
4931 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 4932 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
4933 | |
4934 | (define_insn "fr_restore" | |
3f622353 RH |
4935 | [(set (match_operand:TF 0 "register_operand" "=f") |
4936 | (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))] | |
c65ebc55 JW |
4937 | "" |
4938 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 4939 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 4940 | |
0024a804 JW |
4941 | ;; ??? The explicit stop is not ideal. It would be better if |
4942 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4943 | ;; fixed later. This avoids an RSE DV. | |
4944 | ||
0c96007e AM |
4945 | (define_insn "bsp_value" |
4946 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4947 | (unspec:DI [(const_int 0)] 20))] | |
4948 | "" | |
0024a804 | 4949 | ";;\;mov %0 = ar.bsp" |
52e12ad0 | 4950 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
4951 | |
4952 | (define_insn "set_bsp" | |
2ed4af6f | 4953 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)] |
0c96007e | 4954 | "" |
13da91fd | 4955 | "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19" |
52e12ad0 | 4956 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 4957 | (set_attr "predicable" "no")]) |
ce152ef8 | 4958 | |
0024a804 JW |
4959 | ;; ??? The explicit stops are not ideal. It would be better if |
4960 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4961 | ;; fixed later. This avoids an RSE DV. | |
4962 | ||
ce152ef8 AM |
4963 | (define_insn "flushrs" |
4964 | [(unspec [(const_int 0)] 21)] | |
4965 | "" | |
0024a804 | 4966 | ";;\;flushrs\;;;" |
52e12ad0 | 4967 | [(set_attr "itanium_class" "rse_m")]) |
c65ebc55 JW |
4968 | \f |
4969 | ;; :::::::::::::::::::: | |
4970 | ;; :: | |
4971 | ;; :: Miscellaneous instructions | |
4972 | ;; :: | |
4973 | ;; :::::::::::::::::::: | |
4974 | ||
4975 | ;; ??? Emiting a NOP instruction isn't very useful. This should probably | |
4976 | ;; be emitting ";;" to force a break in the instruction packing. | |
4977 | ||
4978 | ;; No operation, needed in case the user uses -g but not -O. | |
4979 | (define_insn "nop" | |
4980 | [(const_int 0)] | |
4981 | "" | |
4982 | "nop 0" | |
52e12ad0 | 4983 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4984 | |
2130b7fb BS |
4985 | (define_insn "nop_m" |
4986 | [(const_int 1)] | |
4987 | "" | |
4988 | "nop.m 0" | |
4989 | [(set_attr "itanium_class" "nop_m")]) | |
4990 | ||
4991 | (define_insn "nop_i" | |
4992 | [(const_int 2)] | |
4993 | "" | |
4994 | "nop.i 0" | |
4995 | [(set_attr "itanium_class" "nop_i")]) | |
4996 | ||
4997 | (define_insn "nop_f" | |
4998 | [(const_int 3)] | |
4999 | "" | |
5000 | "nop.f 0" | |
5001 | [(set_attr "itanium_class" "nop_f")]) | |
5002 | ||
5003 | (define_insn "nop_b" | |
5004 | [(const_int 4)] | |
5005 | "" | |
5006 | "nop.b 0" | |
5007 | [(set_attr "itanium_class" "nop_b")]) | |
5008 | ||
5009 | (define_insn "nop_x" | |
5010 | [(const_int 5)] | |
5011 | "" | |
5012 | "" | |
5013 | [(set_attr "itanium_class" "nop_x")]) | |
5014 | ||
8e8de254 | 5015 | (define_insn "cycle_display" |
2130b7fb BS |
5016 | [(unspec [(match_operand 0 "const_int_operand" "")] 23)] |
5017 | "" | |
5018 | "// cycle %0" | |
5019 | [(set_attr "itanium_class" "ignore") | |
5020 | (set_attr "predicable" "no")]) | |
5021 | ||
5022 | (define_insn "bundle_selector" | |
5023 | [(unspec [(match_operand 0 "const_int_operand" "")] 22)] | |
5024 | "" | |
5025 | "* | |
5026 | { | |
5027 | return get_bundle_name (INTVAL (operands[0])); | |
5028 | }" | |
5029 | [(set_attr "itanium_class" "ignore") | |
5030 | (set_attr "predicable" "no")]) | |
5031 | ||
c65ebc55 JW |
5032 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
5033 | ;; point. | |
5034 | (define_insn "blockage" | |
5035 | [(unspec_volatile [(const_int 0)] 1)] | |
5036 | "" | |
5037 | "" | |
52e12ad0 | 5038 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 5039 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5040 | |
5041 | (define_insn "insn_group_barrier" | |
2130b7fb | 5042 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)] |
c65ebc55 JW |
5043 | "" |
5044 | ";;" | |
52e12ad0 | 5045 | [(set_attr "itanium_class" "stop_bit") |
e5bde68a | 5046 | (set_attr "predicable" "no")]) |
c65ebc55 | 5047 | |
f12f25a7 RH |
5048 | (define_insn "break_f" |
5049 | [(unspec_volatile [(const_int 0)] 3)] | |
5050 | "" | |
5051 | "break.f 0" | |
5052 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
5053 | |
5054 | (define_insn "prefetch" | |
5055 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
5056 | (match_operand:DI 1 "const_int_operand" "n") | |
5057 | (match_operand:DI 2 "const_int_operand" "n"))] | |
5058 | "" | |
5059 | { | |
5060 | static const char * const alt[2][4] = { | |
b3656137 KG |
5061 | { |
5062 | "lfetch.nta [%0]", | |
5063 | "lfetch.nt1 [%0]", | |
5064 | "lfetch.nt2 [%0]", | |
5065 | "lfetch [%0]" | |
5066 | }, | |
5067 | { | |
5068 | "lfetch.excl.nta [%0]", | |
5069 | "lfetch.excl.nt1 [%0]", | |
5070 | "lfetch.excl.nt2 [%0]", | |
5071 | "lfetch.excl [%0]" | |
5072 | } | |
44eca121 JJ |
5073 | }; |
5074 | int i = (INTVAL (operands[1])); | |
5075 | int j = (INTVAL (operands[2])); | |
5076 | ||
5077 | if (i != 0 && i != 1) | |
5078 | abort (); | |
5079 | if (j < 0 || j > 3) | |
5080 | abort (); | |
5081 | return alt[i][j]; | |
5082 | } | |
5083 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
5084 | \f |
5085 | ;; Non-local goto support. | |
5086 | ||
5087 | (define_expand "save_stack_nonlocal" | |
5088 | [(use (match_operand:OI 0 "memory_operand" "")) | |
5089 | (use (match_operand:DI 1 "register_operand" ""))] | |
5090 | "" | |
5091 | " | |
5092 | { | |
5093 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5094 | \"__ia64_save_stack_nonlocal\"), | |
5095 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
5096 | operands[1], Pmode); | |
5097 | DONE; | |
5098 | }") | |
5099 | ||
5100 | (define_expand "nonlocal_goto" | |
5101 | [(use (match_operand 0 "general_operand" "")) | |
5102 | (use (match_operand 1 "general_operand" "")) | |
5103 | (use (match_operand 2 "general_operand" "")) | |
5104 | (use (match_operand 3 "general_operand" ""))] | |
5105 | "" | |
5106 | " | |
5107 | { | |
c65ebc55 | 5108 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 5109 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 5110 | operands[1], Pmode, |
c65ebc55 | 5111 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 5112 | operands[3], Pmode); |
c65ebc55 JW |
5113 | emit_barrier (); |
5114 | DONE; | |
5115 | }") | |
5116 | ||
97e242b0 RH |
5117 | ;; The rest of the setjmp processing happens with the nonlocal_goto expander. |
5118 | ;; ??? This is not tested. | |
5119 | (define_expand "builtin_setjmp_setup" | |
5120 | [(use (match_operand:DI 0 "" ""))] | |
c65ebc55 JW |
5121 | "" |
5122 | " | |
5123 | { | |
97e242b0 RH |
5124 | emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); |
5125 | DONE; | |
5126 | }") | |
5127 | ||
5128 | (define_expand "builtin_setjmp_receiver" | |
5129 | [(use (match_operand:DI 0 "" ""))] | |
5130 | "" | |
5131 | " | |
5132 | { | |
5133 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); | |
c65ebc55 JW |
5134 | DONE; |
5135 | }") | |
5136 | ||
0c96007e AM |
5137 | (define_expand "eh_epilogue" |
5138 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5139 | (use (match_operand:DI 1 "register_operand" "r")) | |
5140 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5141 | "" | |
5142 | " | |
5143 | { | |
5144 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5145 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5146 | ||
5147 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5148 | { | |
5149 | emit_move_insn (bsp, operands[0]); | |
5150 | operands[0] = bsp; | |
5151 | } | |
5152 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5153 | { | |
5154 | emit_move_insn (sp, operands[2]); | |
5155 | operands[2] = sp; | |
5156 | } | |
5157 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5158 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5159 | ||
5160 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5161 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
0c96007e | 5162 | }") |
9525c690 JW |
5163 | \f |
5164 | ;; Builtin apply support. | |
5165 | ||
5166 | (define_expand "restore_stack_nonlocal" | |
5167 | [(use (match_operand:DI 0 "register_operand" "")) | |
5168 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5169 | "" | |
5170 | " | |
5171 | { | |
5172 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5173 | \"__ia64_restore_stack_nonlocal\"), | |
5174 | 0, VOIDmode, 1, | |
5175 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5176 | DONE; | |
5177 | }") | |
5178 | ||
5179 | \f | |
5180 | ;;; Intrinsics support. | |
c65ebc55 | 5181 | |
0551c32d RH |
5182 | (define_expand "mf" |
5183 | [(set (mem:BLK (match_dup 0)) | |
5184 | (unspec:BLK [(mem:BLK (match_dup 0))] 12))] | |
5185 | "" | |
5186 | " | |
5187 | { | |
5188 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
5189 | MEM_VOLATILE_P (operands[0]) = 1; | |
5190 | }") | |
5191 | ||
5192 | (define_insn "*mf_internal" | |
5193 | [(set (match_operand:BLK 0 "" "") | |
5194 | (unspec:BLK [(match_operand:BLK 1 "" "")] 12))] | |
c65ebc55 JW |
5195 | "" |
5196 | "mf" | |
52e12ad0 | 5197 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
5198 | |
5199 | (define_insn "fetchadd_acq_si" | |
0551c32d RH |
5200 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5201 | (match_dup 1)) | |
5202 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5203 | (unspec:SI [(match_dup 1) | |
5204 | (match_operand:SI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5205 | "" |
5206 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 5207 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5208 | |
5209 | (define_insn "fetchadd_acq_di" | |
0551c32d RH |
5210 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5211 | (match_dup 1)) | |
5212 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5213 | (unspec:DI [(match_dup 1) | |
5214 | (match_operand:DI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5215 | "" |
5216 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 5217 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5218 | |
5219 | (define_insn "cmpxchg_acq_si" | |
0551c32d RH |
5220 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5221 | (match_dup 1)) | |
5222 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5223 | (unspec:SI [(match_dup 1) | |
5224 | (match_operand:SI 2 "gr_register_operand" "r") | |
97e242b0 | 5225 | (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))] |
c65ebc55 | 5226 | "" |
97e242b0 | 5227 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 5228 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5229 | |
5230 | (define_insn "cmpxchg_acq_di" | |
0551c32d RH |
5231 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5232 | (match_dup 1)) | |
5233 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5234 | (unspec:DI [(match_dup 1) | |
5235 | (match_operand:DI 2 "gr_register_operand" "r") | |
5236 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))] | |
c65ebc55 | 5237 | "" |
97e242b0 | 5238 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 5239 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 5240 | |
c65ebc55 | 5241 | (define_insn "xchgsi" |
0551c32d RH |
5242 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5243 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5244 | (set (match_dup 1) |
0551c32d | 5245 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5246 | "" |
5247 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 5248 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5249 | |
5250 | (define_insn "xchgdi" | |
0551c32d RH |
5251 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5252 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5253 | (set (match_dup 1) |
0551c32d | 5254 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5255 | "" |
5256 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 5257 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
5258 | \f |
5259 | ;; Predication. | |
5260 | ||
5261 | (define_cond_exec | |
5262 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5263 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5264 | (const_int 0)])] |
5265 | "" | |
5266 | "(%J0)") | |
3b572406 RH |
5267 | |
5268 | (define_insn "pred_rel_mutex" | |
f2f90c63 RH |
5269 | [(set (match_operand:BI 0 "register_operand" "+c") |
5270 | (unspec:BI [(match_dup 0)] 7))] | |
3b572406 | 5271 | "" |
054451ea | 5272 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5273 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5274 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5275 | |
5276 | (define_insn "safe_across_calls_all" | |
5277 | [(unspec_volatile [(const_int 0)] 8)] | |
5278 | "" | |
5279 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5280 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5281 | (set_attr "predicable" "no")]) |
5282 | ||
5283 | (define_insn "safe_across_calls_normal" | |
5284 | [(unspec_volatile [(const_int 0)] 9)] | |
5285 | "" | |
5286 | "* | |
5287 | { | |
5288 | emit_safe_across_calls (asm_out_file); | |
5289 | return \"\"; | |
5290 | }" | |
52e12ad0 | 5291 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5292 | (set_attr "predicable" "no")]) |
5293 | ||
6dd12198 SE |
5294 | ;; |
5295 | ;; | |
5296 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit | |
5297 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
5298 | ||
5299 | (define_insn "ptr_extend" | |
5300 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5301 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] 24))] | |
5302 | "" | |
5303 | "addp4 %0 = 0,%1" | |
5304 | [(set_attr "itanium_class" "ialu")]) | |
5305 | ||
e206a74f SE |
5306 | ;; |
5307 | ;; Optimizations for ptr_extend | |
5308 | ||
5309 | (define_insn "*ptr_extend_plus_1" | |
5310 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5311 | (unspec:DI | |
5312 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
5313 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
5314 | 24))] | |
5315 | "" | |
5316 | "addp4 %0 = %2, %1" | |
5317 | [(set_attr "itanium_class" "ialu")]) | |
5318 | ||
5319 | (define_insn "*ptr_extend_plus_2" | |
5320 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5321 | (unspec:DI | |
5322 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5323 | (match_operand:SI 2 "basereg_operand" "r"))] | |
5324 | 24))] | |
5325 | "" | |
5326 | "addp4 %0 = %1, %2" | |
5327 | [(set_attr "itanium_class" "ialu")]) | |
5328 | ||
d0e82870 JJ |
5329 | ;; |
5330 | ;; As USE insns aren't meaningful after reload, this is used instead | |
5331 | ;; to prevent deleting instructions setting registers for EH handling | |
5332 | (define_insn "prologue_use" | |
5333 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] 25)] | |
5334 | "" | |
5335 | "// %0 needed for EH" | |
5336 | [(set_attr "itanium_class" "ignore") | |
5337 | (set_attr "predicable" "no")]) |