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c65ebc55 | 1 | ;; IA-64 Machine description template |
283334f0 KH |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
3 | ;; Free Software Foundation, Inc. | |
c65ebc55 JW |
4 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
5 | ;; David Mosberger <davidm@hpl.hp.com>. | |
6 | ||
3bed2930 | 7 | ;; This file is part of GCC. |
c65ebc55 | 8 | |
3bed2930 | 9 | ;; GCC is free software; you can redistribute it and/or modify |
c65ebc55 JW |
10 | ;; it under the terms of the GNU General Public License as published by |
11 | ;; the Free Software Foundation; either version 2, or (at your option) | |
12 | ;; any later version. | |
13 | ||
3bed2930 | 14 | ;; GCC is distributed in the hope that it will be useful, |
c65ebc55 JW |
15 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | ;; GNU General Public License for more details. | |
18 | ||
19 | ;; You should have received a copy of the GNU General Public License | |
3bed2930 | 20 | ;; along with GCC; see the file COPYING. If not, write to |
c65ebc55 JW |
21 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
22 | ;; Boston, MA 02111-1307, USA. | |
23 | ||
24 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
25 | ||
c65ebc55 JW |
26 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
27 | ;; reload. This will be fixed once scheduling support is turned on. | |
28 | ||
29 | ;; ??? Optimize for post-increment addressing modes. | |
30 | ||
31 | ;; ??? fselect is not supported, because there is no integer register | |
32 | ;; equivalent. | |
33 | ||
34 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
35 | ||
36 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
37 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
38 | ||
39 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
40 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
41 | ||
42 | ;; ??? Go through list of documented named patterns and look for more to | |
43 | ;; implement. | |
44 | ||
45 | ;; ??? Go through instruction manual and look for more instructions that | |
46 | ;; can be emitted. | |
47 | ||
48 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
49 | ||
26102535 RH |
50 | ;; ??? Need a better way to describe alternate fp status registers. |
51 | ||
086c0f96 | 52 | (define_constants |
7b6e506e RH |
53 | [; Relocations |
54 | (UNSPEC_LTOFF_DTPMOD 0) | |
55 | (UNSPEC_LTOFF_DTPREL 1) | |
56 | (UNSPEC_DTPREL 2) | |
57 | (UNSPEC_LTOFF_TPREL 3) | |
58 | (UNSPEC_TPREL 4) | |
59 | ||
60 | (UNSPEC_LD_BASE 9) | |
61 | (UNSPEC_GR_SPILL 10) | |
62 | (UNSPEC_GR_RESTORE 11) | |
63 | (UNSPEC_FR_SPILL 12) | |
64 | (UNSPEC_FR_RESTORE 13) | |
65 | (UNSPEC_FR_RECIP_APPROX 14) | |
66 | (UNSPEC_PRED_REL_MUTEX 15) | |
c407570a | 67 | (UNSPEC_GETF_EXP 16) |
7b6e506e RH |
68 | (UNSPEC_PIC_CALL 17) |
69 | (UNSPEC_MF 18) | |
70 | (UNSPEC_CMPXCHG_ACQ 19) | |
71 | (UNSPEC_FETCHADD_ACQ 20) | |
72 | (UNSPEC_BSP_VALUE 21) | |
73 | (UNSPEC_FLUSHRS 22) | |
74 | (UNSPEC_BUNDLE_SELECTOR 23) | |
086c0f96 RH |
75 | (UNSPEC_ADDP4 24) |
76 | (UNSPEC_PROLOGUE_USE 25) | |
af1e5518 | 77 | (UNSPEC_RET_ADDR 26) |
b38ba463 ZW |
78 | (UNSPEC_SETF_EXP 27) |
79 | (UNSPEC_FR_SQRT_RECIP_APPROX 28) | |
f526a3c8 | 80 | (UNSPEC_SHRP 29) |
086c0f96 RH |
81 | ]) |
82 | ||
83 | (define_constants | |
84 | [(UNSPECV_ALLOC 0) | |
85 | (UNSPECV_BLOCKAGE 1) | |
86 | (UNSPECV_INSN_GROUP_BARRIER 2) | |
87 | (UNSPECV_BREAK 3) | |
7b6e506e RH |
88 | (UNSPECV_SET_BSP 4) |
89 | (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls | |
90 | (UNSPECV_PSAC_NORMAL 6) | |
b39eb2f9 | 91 | (UNSPECV_SETJMP_RECEIVER 7) |
086c0f96 | 92 | ]) |
e543e219 ZW |
93 | \f |
94 | ;; :::::::::::::::::::: | |
95 | ;; :: | |
96 | ;; :: Predicates | |
97 | ;; :: | |
98 | ;; :::::::::::::::::::: | |
99 | ||
100 | ;; True if OP is a valid operand for the MEM of a CALL insn. | |
101 | (define_predicate "call_operand" | |
102 | (ior (match_code "symbol_ref") | |
103 | (match_operand 0 "register_operand"))) | |
104 | ||
105 | ;; True if OP refers to any kind of symbol. | |
106 | ;; For roughly the same reasons that pmode_register_operand exists, this | |
107 | ;; predicate ignores its mode argument. | |
108 | (define_special_predicate "symbolic_operand" | |
109 | (match_code "symbol_ref,const,label_ref")) | |
110 | ||
111 | ;; True if OP is a SYMBOL_REF which refers to a function. | |
112 | (define_predicate "function_operand" | |
113 | (and (match_code "symbol_ref") | |
114 | (match_test "SYMBOL_REF_FUNCTION_P (op)"))) | |
115 | ||
116 | ;; True if OP refers to a symbol, and is appropriate for a GOT load. | |
117 | (define_predicate "got_symbolic_operand" | |
118 | (match_operand 0 "symbolic_operand" "") | |
119 | { | |
120 | switch (GET_CODE (op)) | |
121 | { | |
122 | case LABEL_REF: | |
123 | return true; | |
124 | ||
125 | case SYMBOL_REF: | |
126 | /* This sort of load should not be used for things in sdata. */ | |
127 | return !SYMBOL_REF_SMALL_ADDR_P (op); | |
128 | ||
129 | case CONST: | |
130 | /* Accept only (plus (symbol_ref) (const_int)). */ | |
131 | op = XEXP (op, 0); | |
132 | if (GET_CODE (op) != PLUS | |
133 | || GET_CODE (XEXP (op, 0)) != SYMBOL_REF | |
134 | || GET_CODE (XEXP (op, 1)) != CONST_INT) | |
135 | return false; | |
136 | ||
137 | /* Ok if we're not using GOT entries at all. */ | |
138 | if (TARGET_NO_PIC || TARGET_AUTO_PIC) | |
139 | return true; | |
140 | ||
141 | /* The low 14 bits of the constant have been forced to zero | |
142 | by ia64_expand_load_address, so that we do not use up so | |
143 | many GOT entries. Prevent cse from undoing this. */ | |
144 | op = XEXP (op, 1); | |
145 | return (INTVAL (op) & 0x3fff) == 0; | |
146 | ||
147 | default: | |
148 | abort (); | |
149 | } | |
150 | }) | |
151 | ||
152 | ;; True if OP refers to a symbol in the sdata section. | |
153 | (define_predicate "sdata_symbolic_operand" | |
154 | (match_code "symbol_ref,const") | |
155 | { | |
156 | switch (GET_CODE (op)) | |
157 | { | |
158 | case CONST: | |
159 | op = XEXP (op, 0); | |
160 | if (GET_CODE (op) != PLUS | |
161 | || GET_CODE (XEXP (op, 0)) != SYMBOL_REF) | |
162 | return false; | |
163 | op = XEXP (op, 0); | |
164 | /* FALLTHRU */ | |
165 | ||
166 | case SYMBOL_REF: | |
167 | if (CONSTANT_POOL_ADDRESS_P (op)) | |
168 | return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold; | |
169 | else | |
170 | return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op); | |
171 | ||
172 | default: | |
173 | abort (); | |
174 | } | |
175 | }) | |
176 | ||
177 | ;; Like nonimmediate_operand, but don't allow MEMs that try to use a | |
178 | ;; POST_MODIFY with a REG as displacement. | |
179 | (define_predicate "destination_operand" | |
180 | (and (match_operand 0 "nonimmediate_operand") | |
181 | (match_test "GET_CODE (op) != MEM | |
182 | || GET_CODE (XEXP (op, 0)) != POST_MODIFY | |
183 | || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG"))) | |
184 | ||
185 | ;; Like memory_operand, but don't allow post-increments. | |
186 | (define_predicate "not_postinc_memory_operand" | |
187 | (and (match_operand 0 "memory_operand") | |
188 | (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) | |
189 | ||
190 | ;; True if OP is a general operand, excluding tls symbolic operands. | |
191 | (define_predicate "move_operand" | |
192 | (and (match_operand 0 "general_operand") | |
193 | (not (match_test | |
194 | "GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (op)")))) | |
195 | ||
196 | ;; True if OP is a register operand that is (or could be) a GR reg. | |
197 | (define_predicate "gr_register_operand" | |
198 | (match_operand 0 "register_operand") | |
199 | { | |
200 | unsigned int regno; | |
201 | if (GET_CODE (op) == SUBREG) | |
202 | op = SUBREG_REG (op); | |
203 | ||
204 | regno = REGNO (op); | |
205 | return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); | |
206 | }) | |
207 | ||
208 | ;; True if OP is a register operand that is (or could be) an FR reg. | |
209 | (define_predicate "fr_register_operand" | |
210 | (match_operand 0 "register_operand") | |
211 | { | |
212 | unsigned int regno; | |
213 | if (GET_CODE (op) == SUBREG) | |
214 | op = SUBREG_REG (op); | |
215 | ||
216 | regno = REGNO (op); | |
217 | return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno)); | |
218 | }) | |
219 | ||
220 | ;; True if OP is a register operand that is (or could be) a GR/FR reg. | |
221 | (define_predicate "grfr_register_operand" | |
222 | (match_operand 0 "register_operand") | |
223 | { | |
224 | unsigned int regno; | |
225 | if (GET_CODE (op) == SUBREG) | |
226 | op = SUBREG_REG (op); | |
227 | ||
228 | regno = REGNO (op); | |
229 | return (regno >= FIRST_PSEUDO_REGISTER | |
230 | || GENERAL_REGNO_P (regno) | |
231 | || FR_REGNO_P (regno)); | |
232 | }) | |
233 | ||
234 | ;; True if OP is a nonimmediate operand that is (or could be) a GR reg. | |
235 | (define_predicate "gr_nonimmediate_operand" | |
236 | (match_operand 0 "nonimmediate_operand") | |
237 | { | |
238 | unsigned int regno; | |
239 | ||
240 | if (GET_CODE (op) == MEM) | |
241 | return true; | |
242 | if (GET_CODE (op) == SUBREG) | |
243 | op = SUBREG_REG (op); | |
244 | ||
245 | regno = REGNO (op); | |
246 | return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); | |
247 | }) | |
248 | ||
249 | ;; True if OP is a nonimmediate operand that is (or could be) a FR reg. | |
250 | (define_predicate "fr_nonimmediate_operand" | |
251 | (match_operand 0 "nonimmediate_operand") | |
252 | { | |
253 | unsigned int regno; | |
254 | ||
255 | if (GET_CODE (op) == MEM) | |
256 | return true; | |
257 | if (GET_CODE (op) == SUBREG) | |
258 | op = SUBREG_REG (op); | |
259 | ||
260 | regno = REGNO (op); | |
261 | return (regno >= FIRST_PSEUDO_REGISTER || FR_REGNO_P (regno)); | |
262 | }) | |
263 | ||
264 | ;; True if OP is a nonimmediate operand that is (or could be) a GR/FR reg. | |
265 | (define_predicate "grfr_nonimmediate_operand" | |
266 | (match_operand 0 "nonimmediate_operand") | |
267 | { | |
268 | unsigned int regno; | |
269 | ||
270 | if (GET_CODE (op) == MEM) | |
271 | return true; | |
272 | if (GET_CODE (op) == SUBREG) | |
273 | op = SUBREG_REG (op); | |
274 | ||
275 | regno = REGNO (op); | |
276 | return (regno >= FIRST_PSEUDO_REGISTER | |
277 | || GENERAL_REGNO_P (regno) | |
278 | || FR_REGNO_P (regno)); | |
279 | }) | |
280 | ||
281 | ;; True if OP is a GR register operand, or zero. | |
282 | (define_predicate "gr_reg_or_0_operand" | |
283 | (ior (match_operand 0 "gr_register_operand") | |
284 | (and (match_code "const_int") | |
285 | (match_test "op == const0_rtx")))) | |
286 | ||
287 | ;; True if OP is a GR register operand, or a 5 bit immediate operand. | |
288 | (define_predicate "gr_reg_or_5bit_operand" | |
289 | (ior (match_operand 0 "gr_register_operand") | |
290 | (and (match_code "const_int") | |
291 | (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32")))) | |
292 | ||
293 | ;; True if OP is a GR register operand, or a 6 bit immediate operand. | |
294 | (define_predicate "gr_reg_or_6bit_operand" | |
295 | (ior (match_operand 0 "gr_register_operand") | |
296 | (and (match_code "const_int") | |
297 | (match_test "CONST_OK_FOR_M (INTVAL (op))")))) | |
298 | ||
299 | ;; True if OP is a GR register operand, or an 8 bit immediate operand. | |
300 | (define_predicate "gr_reg_or_8bit_operand" | |
301 | (ior (match_operand 0 "gr_register_operand") | |
302 | (and (match_code "const_int") | |
303 | (match_test "CONST_OK_FOR_K (INTVAL (op))")))) | |
304 | ||
305 | ;; True if OP is a GR/FR register operand, or an 8 bit immediate operand. | |
306 | (define_predicate "grfr_reg_or_8bit_operand" | |
307 | (ior (match_operand 0 "grfr_register_operand") | |
308 | (and (match_code "const_int") | |
309 | (match_test "CONST_OK_FOR_K (INTVAL (op))")))) | |
310 | ||
311 | ;; True if OP is a register operand, or an 8 bit adjusted immediate operand. | |
312 | (define_predicate "gr_reg_or_8bit_adjusted_operand" | |
313 | (ior (match_operand 0 "gr_register_operand") | |
314 | (and (match_code "const_int") | |
315 | (match_test "CONST_OK_FOR_L (INTVAL (op))")))) | |
316 | ||
317 | ;; True if OP is a register operand, or is valid for both an 8 bit | |
318 | ;; immediate and an 8 bit adjusted immediate operand. This is necessary | |
319 | ;; because when we emit a compare, we don't know what the condition will be, | |
320 | ;; so we need the union of the immediates accepted by GT and LT. | |
321 | (define_predicate "gr_reg_or_8bit_and_adjusted_operand" | |
322 | (ior (match_operand 0 "gr_register_operand") | |
323 | (and (match_code "const_int") | |
324 | (match_test "CONST_OK_FOR_K (INTVAL (op)) | |
325 | && CONST_OK_FOR_L (INTVAL (op))")))) | |
326 | ||
327 | ;; True if OP is a register operand, or a 14 bit immediate operand. | |
328 | (define_predicate "gr_reg_or_14bit_operand" | |
329 | (ior (match_operand 0 "gr_register_operand") | |
330 | (and (match_code "const_int") | |
331 | (match_test "CONST_OK_FOR_I (INTVAL (op))")))) | |
332 | ||
333 | ;; True if OP is a register operand, or a 22 bit immediate operand. | |
334 | (define_predicate "gr_reg_or_22bit_operand" | |
335 | (ior (match_operand 0 "gr_register_operand") | |
336 | (and (match_code "const_int") | |
337 | (match_test "CONST_OK_FOR_J (INTVAL (op))")))) | |
338 | ||
f526a3c8 RH |
339 | ;; True if OP is a 7 bit immediate operand. |
340 | (define_predicate "dshift_count_operand" | |
341 | (and (match_code "const_int") | |
342 | (match_test "INTVAL (op) >= 0 && INTVAL (op) < 128"))) | |
343 | ||
e543e219 ZW |
344 | ;; True if OP is a 6 bit immediate operand. |
345 | (define_predicate "shift_count_operand" | |
346 | (and (match_code "const_int") | |
347 | (match_test "CONST_OK_FOR_M (INTVAL (op))"))) | |
348 | ||
349 | ;; True if OP is a 5 bit immediate operand. | |
350 | (define_predicate "shift_32bit_count_operand" | |
351 | (and (match_code "const_int") | |
352 | (match_test "INTVAL (op) >= 0 && INTVAL (op) < 32"))) | |
353 | ||
c112cf2b | 354 | ;; True if OP is one of the immediate values 2, 4, 8, or 16. |
e543e219 ZW |
355 | (define_predicate "shladd_operand" |
356 | (and (match_code "const_int") | |
357 | (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || | |
358 | INTVAL (op) == 8 || INTVAL (op) == 16"))) | |
359 | ||
360 | ;; True if OP is one of the immediate values -16, -8, -4, -1, 1, 4, 8, 16. | |
361 | (define_predicate "fetchadd_operand" | |
362 | (and (match_code "const_int") | |
363 | (match_test "INTVAL (op) == -16 || INTVAL (op) == -8 || | |
364 | INTVAL (op) == -4 || INTVAL (op) == -1 || | |
365 | INTVAL (op) == 1 || INTVAL (op) == 4 || | |
366 | INTVAL (op) == 8 || INTVAL (op) == 16"))) | |
367 | ||
368 | ||
369 | ;; True if OP is a floating-point constant zero, one, or a register. | |
370 | (define_predicate "fr_reg_or_fp01_operand" | |
371 | (ior (match_operand 0 "fr_register_operand") | |
372 | (and (match_code "const_double") | |
373 | (match_test "CONST_DOUBLE_OK_FOR_G (op)")))) | |
374 | ||
375 | ;; Like fr_reg_or_fp01_operand, but don't allow any SUBREGs. | |
376 | (define_predicate "xfreg_or_fp01_operand" | |
377 | (and (match_operand 0 "fr_reg_or_fp01_operand") | |
378 | (not (match_code "subreg")))) | |
379 | ||
380 | ;; True if this is a comparison operator, which accepts a normal 8-bit | |
381 | ;; signed immediate operand. | |
382 | (define_predicate "normal_comparison_operator" | |
383 | (match_code "eq,ne,gt,le,gtu,leu")) | |
384 | ||
385 | ;; True if this is a comparison operator, which accepts an adjusted 8-bit | |
386 | ;; signed immediate operand. | |
387 | (define_predicate "adjusted_comparison_operator" | |
388 | (match_code "lt,ge,ltu,geu")) | |
389 | ||
390 | ;; True if this is a signed inequality operator. | |
391 | (define_predicate "signed_inequality_operator" | |
392 | (match_code "ge,gt,le,lt")) | |
393 | ||
394 | ;; True if this operator is valid for predication. | |
395 | (define_predicate "predicate_operator" | |
396 | (match_code "eq,ne")) | |
397 | ||
398 | ;; True if this operator can be used in a conditional operation. | |
399 | (define_predicate "condop_operator" | |
400 | (match_code "plus,minus,ior,xor,and")) | |
401 | ||
402 | ;; These three are hardware registers that can only be addressed in | |
403 | ;; DImode. It's not strictly necessary to test mode == DImode here, | |
404 | ;; but it makes decent insurance against someone writing a | |
405 | ;; match_operand wrong. | |
406 | ||
407 | ;; True if this is the ar.lc register. | |
408 | (define_predicate "ar_lc_reg_operand" | |
409 | (and (match_code "reg") | |
410 | (match_test "mode == DImode && REGNO (op) == AR_LC_REGNUM"))) | |
411 | ||
412 | ;; True if this is the ar.ccv register. | |
413 | (define_predicate "ar_ccv_reg_operand" | |
414 | (and (match_code "reg") | |
415 | (match_test "mode == DImode && REGNO (op) == AR_CCV_REGNUM"))) | |
416 | ||
417 | ;; True if this is the ar.pfs register. | |
418 | (define_predicate "ar_pfs_reg_operand" | |
419 | (and (match_code "reg") | |
420 | (match_test "mode == DImode && REGNO (op) == AR_PFS_REGNUM"))) | |
421 | ||
422 | ;; True if OP is valid as a base register in a reg + offset address. | |
423 | ;; ??? Should I copy the flag_omit_frame_pointer and cse_not_expected | |
424 | ;; checks from pa.c basereg_operand as well? Seems to be OK without them | |
425 | ;; in test runs. | |
426 | (define_predicate "basereg_operand" | |
427 | (match_operand 0 "register_operand") | |
428 | { | |
429 | if (GET_CODE (op) == SUBREG) | |
430 | op = SUBREG_REG (op); | |
431 | return REG_POINTER (op); | |
432 | }) | |
433 | ||
c65ebc55 JW |
434 | \f |
435 | ;; :::::::::::::::::::: | |
436 | ;; :: | |
437 | ;; :: Attributes | |
438 | ;; :: | |
439 | ;; :::::::::::::::::::: | |
440 | ||
30028c85 VM |
441 | ;; Processor type. This attribute must exactly match the processor_type |
442 | ;; enumeration in ia64.h. | |
443 | (define_attr "cpu" "itanium,itanium2" (const (symbol_ref "ia64_tune"))) | |
444 | ||
c65ebc55 JW |
445 | ;; Instruction type. This primarily determines how instructions can be |
446 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
447 | ||
448 | ;; A alu, can go in I or M syllable of a bundle | |
449 | ;; I integer | |
450 | ;; M memory | |
451 | ;; F floating-point | |
452 | ;; B branch | |
453 | ;; L long immediate, takes two syllables | |
454 | ;; S stop bit | |
455 | ||
456 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
457 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
458 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
459 | ;; which emit instruction that can go in any slot (e.g. nop). | |
460 | ||
1d5d7a21 RH |
461 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld, |
462 | fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld, | |
463 | chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0, | |
30028c85 VM |
464 | syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,nop_b,nop_f, |
465 | nop_i,nop_m,nop_x,lfetch,pre_cycle" | |
1d5d7a21 | 466 | (const_string "unknown")) |
52e12ad0 | 467 | |
2130b7fb BS |
468 | ;; chk_s has an I and an M form; use type A for convenience. |
469 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
470 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
471 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
472 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
44eca121 | 473 | (eq_attr "itanium_class" "lfetch") (const_string "M") |
2130b7fb BS |
474 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
475 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
476 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
477 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
478 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
479 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
480 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 481 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 482 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
483 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
484 | (const_string "unknown"))) | |
c65ebc55 | 485 | |
2130b7fb BS |
486 | (define_attr "itanium_requires_unit0" "no,yes" |
487 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
488 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
489 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
490 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
491 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
492 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
493 | (const_string "no"))) | |
494 | ||
e5bde68a RH |
495 | ;; Predication. True iff this instruction can be predicated. |
496 | ||
497 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
498 | ||
fa978426 AS |
499 | ;; Empty. True iff this insn does not generate any code. |
500 | ||
501 | (define_attr "empty" "no,yes" (const_string "no")) | |
502 | ||
c65ebc55 | 503 | \f |
c65ebc55 | 504 | |
30028c85 VM |
505 | ;; DFA descriptions of ia64 processors used for insn scheduling and |
506 | ;; bundling. | |
507 | ||
508 | (automata_option "ndfa") | |
509 | ||
510 | ;; Uncomment the following line to output automata for debugging. | |
511 | ;; (automata_option "v") | |
512 | ||
513 | (automata_option "w") | |
514 | ||
515 | ;;(automata_option "no-minimization") | |
516 | ||
517 | ||
518 | (include "itanium1.md") | |
519 | (include "itanium2.md") | |
520 | ||
c65ebc55 JW |
521 | \f |
522 | ;; :::::::::::::::::::: | |
523 | ;; :: | |
524 | ;; :: Moves | |
525 | ;; :: | |
526 | ;; :::::::::::::::::::: | |
527 | ||
f2f90c63 RH |
528 | ;; Set of a single predicate register. This is only used to implement |
529 | ;; pr-to-pr move and complement. | |
530 | ||
531 | (define_insn "*movcci" | |
532 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
533 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
534 | "" | |
535 | "@ | |
536 | cmp.ne %0, p0 = r0, r0 | |
537 | cmp.eq %0, p0 = r0, r0 | |
538 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 539 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
540 | (set_attr "predicable" "no")]) |
541 | ||
542 | (define_insn "movbi" | |
cd5c4048 RH |
543 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
544 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
545 | "" |
546 | "@ | |
547 | cmp.ne %0, %I0 = r0, r0 | |
548 | cmp.eq %0, %I0 = r0, r0 | |
549 | # | |
550 | # | |
551 | tbit.nz %0, %I0 = %1, 0 | |
552 | adds %0 = %1, r0 | |
553 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
554 | st1%Q0 %0 = %1%P0 |
555 | mov %0 = %1" | |
52e12ad0 | 556 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
557 | |
558 | (define_split | |
559 | [(set (match_operand:BI 0 "register_operand" "") | |
560 | (match_operand:BI 1 "register_operand" ""))] | |
561 | "reload_completed | |
562 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
563 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
564 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
565 | (set (match_dup 0) (const_int 1))) | |
566 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
567 | (set (match_dup 0) (const_int 0)))] | |
568 | "") | |
569 | ||
570 | (define_split | |
571 | [(set (match_operand:BI 0 "register_operand" "") | |
572 | (match_operand:BI 1 "register_operand" ""))] | |
573 | "reload_completed | |
574 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
575 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
576 | [(set (match_dup 2) (match_dup 4)) | |
577 | (set (match_dup 3) (match_dup 5)) | |
086c0f96 | 578 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
579 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); |
580 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
581 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
582 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
583 | ||
c65ebc55 JW |
584 | (define_expand "movqi" |
585 | [(set (match_operand:QI 0 "general_operand" "") | |
586 | (match_operand:QI 1 "general_operand" ""))] | |
587 | "" | |
c65ebc55 | 588 | { |
7b6e506e RH |
589 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
590 | if (!op1) | |
591 | DONE; | |
592 | operands[1] = op1; | |
1d5d7a21 | 593 | }) |
c65ebc55 JW |
594 | |
595 | (define_insn "*movqi_internal" | |
4b983fdc RH |
596 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
597 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 598 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 599 | "@ |
13da91fd | 600 | mov %0 = %r1 |
c65ebc55 JW |
601 | addl %0 = %1, r0 |
602 | ld1%O1 %0 = %1%P1 | |
13da91fd | 603 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 604 | getf.sig %0 = %1 |
13da91fd RH |
605 | setf.sig %0 = %r1 |
606 | mov %0 = %1" | |
52e12ad0 | 607 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
608 | |
609 | (define_expand "movhi" | |
610 | [(set (match_operand:HI 0 "general_operand" "") | |
611 | (match_operand:HI 1 "general_operand" ""))] | |
612 | "" | |
c65ebc55 | 613 | { |
7b6e506e RH |
614 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
615 | if (!op1) | |
616 | DONE; | |
617 | operands[1] = op1; | |
1d5d7a21 | 618 | }) |
c65ebc55 JW |
619 | |
620 | (define_insn "*movhi_internal" | |
4b983fdc RH |
621 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
622 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 623 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 624 | "@ |
13da91fd | 625 | mov %0 = %r1 |
c65ebc55 JW |
626 | addl %0 = %1, r0 |
627 | ld2%O1 %0 = %1%P1 | |
13da91fd | 628 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 629 | getf.sig %0 = %1 |
13da91fd RH |
630 | setf.sig %0 = %r1 |
631 | mov %0 = %1" | |
52e12ad0 | 632 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
633 | |
634 | (define_expand "movsi" | |
635 | [(set (match_operand:SI 0 "general_operand" "") | |
636 | (match_operand:SI 1 "general_operand" ""))] | |
637 | "" | |
c65ebc55 | 638 | { |
7b6e506e RH |
639 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
640 | if (!op1) | |
641 | DONE; | |
642 | operands[1] = op1; | |
1d5d7a21 | 643 | }) |
c65ebc55 JW |
644 | |
645 | (define_insn "*movsi_internal" | |
97e242b0 | 646 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 647 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 648 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 649 | "@ |
13da91fd | 650 | mov %0 = %r1 |
c65ebc55 JW |
651 | addl %0 = %1, r0 |
652 | movl %0 = %1 | |
653 | ld4%O1 %0 = %1%P1 | |
13da91fd | 654 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 655 | getf.sig %0 = %1 |
13da91fd | 656 | setf.sig %0 = %r1 |
97e242b0 RH |
657 | mov %0 = %1 |
658 | mov %0 = %1 | |
659 | mov %0 = %r1" | |
1d5d7a21 | 660 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
52e12ad0 | 661 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) |
c65ebc55 JW |
662 | |
663 | (define_expand "movdi" | |
664 | [(set (match_operand:DI 0 "general_operand" "") | |
665 | (match_operand:DI 1 "general_operand" ""))] | |
666 | "" | |
c65ebc55 | 667 | { |
7b6e506e RH |
668 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
669 | if (!op1) | |
670 | DONE; | |
671 | operands[1] = op1; | |
1d5d7a21 | 672 | }) |
c65ebc55 | 673 | |
c65ebc55 | 674 | (define_insn "*movdi_internal" |
4b983fdc | 675 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 676 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 677 | (match_operand:DI 1 "move_operand" |
a32767e4 | 678 | "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 679 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
680 | { |
681 | static const char * const alt[] = { | |
1d5d7a21 RH |
682 | "%,mov %0 = %r1", |
683 | "%,addl %0 = %1, r0", | |
684 | "%,movl %0 = %1", | |
685 | "%,ld8%O1 %0 = %1%P1", | |
686 | "%,st8%Q0 %0 = %r1%P0", | |
687 | "%,getf.sig %0 = %1", | |
688 | "%,setf.sig %0 = %r1", | |
689 | "%,mov %0 = %1", | |
690 | "%,ldf8 %0 = %1%P1", | |
691 | "%,stf8 %0 = %1%P0", | |
692 | "%,mov %0 = %1", | |
693 | "%,mov %0 = %r1", | |
694 | "%,mov %0 = %1", | |
695 | "%,mov %0 = %1", | |
696 | "%,mov %0 = %1", | |
697 | "%,mov %0 = %1", | |
698 | "mov %0 = pr", | |
699 | "mov pr = %1, -1" | |
9b7bf67d RH |
700 | }; |
701 | ||
9b7bf67d RH |
702 | if (which_alternative == 2 && ! TARGET_NO_PIC |
703 | && symbolic_operand (operands[1], VOIDmode)) | |
704 | abort (); | |
705 | ||
706 | return alt[which_alternative]; | |
1d5d7a21 | 707 | } |
52e12ad0 | 708 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 709 | |
9b7bf67d | 710 | (define_split |
21515593 RH |
711 | [(set (match_operand 0 "register_operand" "") |
712 | (match_operand 1 "symbolic_operand" ""))] | |
9b7bf67d RH |
713 | "reload_completed && ! TARGET_NO_PIC" |
714 | [(const_int 0)] | |
9b7bf67d | 715 | { |
21515593 | 716 | ia64_expand_load_address (operands[0], operands[1]); |
9b7bf67d | 717 | DONE; |
1d5d7a21 | 718 | }) |
9b7bf67d | 719 | |
c65ebc55 JW |
720 | (define_expand "load_fptr" |
721 | [(set (match_dup 2) | |
5da4f548 | 722 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" ""))) |
ec039e3c | 723 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 | 724 | "" |
c65ebc55 | 725 | { |
ec039e3c | 726 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
542a8afa | 727 | operands[3] = gen_const_mem (DImode, operands[2]); |
1d5d7a21 | 728 | }) |
c65ebc55 JW |
729 | |
730 | (define_insn "*load_fptr_internal1" | |
731 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 732 | (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))] |
c65ebc55 JW |
733 | "" |
734 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 735 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
736 | |
737 | (define_insn "load_gprel" | |
738 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5da4f548 | 739 | (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))] |
c65ebc55 JW |
740 | "" |
741 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 742 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 743 | |
59da9a7d JW |
744 | (define_insn "gprel64_offset" |
745 | [(set (match_operand:DI 0 "register_operand" "=r") | |
746 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
747 | "" | |
748 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 749 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
750 | |
751 | (define_expand "load_gprel64" | |
752 | [(set (match_dup 2) | |
b5d37c6f | 753 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 754 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 755 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 756 | "" |
ec039e3c RH |
757 | { |
758 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 759 | operands[3] = pic_offset_table_rtx; |
1d5d7a21 | 760 | }) |
59da9a7d | 761 | |
af1e5518 RH |
762 | ;; This is used as a placeholder for the return address during early |
763 | ;; compilation. We won't know where we've placed this until during | |
764 | ;; reload, at which point it can wind up in b0, a general register, | |
765 | ;; or memory. The only safe destination under these conditions is a | |
766 | ;; general register. | |
767 | ||
768 | (define_insn_and_split "*movdi_ret_addr" | |
769 | [(set (match_operand:DI 0 "register_operand" "=r") | |
770 | (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))] | |
771 | "" | |
772 | "#" | |
773 | "reload_completed" | |
774 | [(const_int 0)] | |
775 | { | |
776 | ia64_split_return_addr_rtx (operands[0]); | |
777 | DONE; | |
778 | } | |
779 | [(set_attr "itanium_class" "ialu")]) | |
780 | ||
ef1ecf87 | 781 | (define_insn "*load_symptr_high" |
c65ebc55 | 782 | [(set (match_operand:DI 0 "register_operand" "=r") |
ef1ecf87 RH |
783 | (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s")) |
784 | (match_operand:DI 2 "register_operand" "a")))] | |
c65ebc55 | 785 | "" |
ef1ecf87 RH |
786 | { |
787 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
788 | return "%,addl %0 = @ltoffx(%1), %2"; | |
789 | else | |
790 | return "%,addl %0 = @ltoff(%1), %2"; | |
791 | } | |
52e12ad0 | 792 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 793 | |
ef1ecf87 RH |
794 | (define_insn "*load_symptr_low" |
795 | [(set (match_operand:DI 0 "register_operand" "=r") | |
796 | (lo_sum:DI (match_operand:DI 1 "register_operand" "r") | |
797 | (match_operand 2 "got_symbolic_operand" "s")))] | |
798 | "" | |
799 | { | |
800 | if (HAVE_AS_LTOFFX_LDXMOV_RELOCS) | |
801 | return "%,ld8.mov %0 = [%1], %2"; | |
802 | else | |
803 | return "%,ld8 %0 = [%1]"; | |
804 | } | |
805 | [(set_attr "itanium_class" "ld")]) | |
806 | ||
7b6e506e RH |
807 | (define_insn "load_ltoff_dtpmod" |
808 | [(set (match_operand:DI 0 "register_operand" "=r") | |
809 | (plus:DI (reg:DI 1) | |
810 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
811 | UNSPEC_LTOFF_DTPMOD)))] | |
812 | "" | |
813 | "addl %0 = @ltoff(@dtpmod(%1)), gp" | |
814 | [(set_attr "itanium_class" "ialu")]) | |
815 | ||
816 | (define_insn "load_ltoff_dtprel" | |
817 | [(set (match_operand:DI 0 "register_operand" "=r") | |
818 | (plus:DI (reg:DI 1) | |
819 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
820 | UNSPEC_LTOFF_DTPREL)))] | |
821 | "" | |
822 | "addl %0 = @ltoff(@dtprel(%1)), gp" | |
823 | [(set_attr "itanium_class" "ialu")]) | |
824 | ||
825 | (define_expand "load_dtprel" | |
826 | [(set (match_operand:DI 0 "register_operand" "") | |
827 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
828 | UNSPEC_DTPREL))] | |
829 | "" | |
830 | "") | |
831 | ||
832 | (define_insn "*load_dtprel64" | |
833 | [(set (match_operand:DI 0 "register_operand" "=r") | |
834 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
835 | UNSPEC_DTPREL))] | |
836 | "TARGET_TLS64" | |
837 | "movl %0 = @dtprel(%1)" | |
838 | [(set_attr "itanium_class" "long_i")]) | |
839 | ||
840 | (define_insn "*load_dtprel22" | |
841 | [(set (match_operand:DI 0 "register_operand" "=r") | |
842 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
843 | UNSPEC_DTPREL))] | |
844 | "" | |
845 | "addl %0 = @dtprel(%1), r0" | |
846 | [(set_attr "itanium_class" "ialu")]) | |
847 | ||
848 | (define_expand "add_dtprel" | |
849 | [(set (match_operand:DI 0 "register_operand" "") | |
850 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
851 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
852 | UNSPEC_DTPREL)))] | |
853 | "!TARGET_TLS64" | |
854 | "") | |
855 | ||
856 | (define_insn "*add_dtprel14" | |
857 | [(set (match_operand:DI 0 "register_operand" "=r") | |
858 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
859 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
860 | UNSPEC_DTPREL)))] | |
861 | "TARGET_TLS14" | |
862 | "adds %0 = @dtprel(%2), %1" | |
863 | [(set_attr "itanium_class" "ialu")]) | |
864 | ||
865 | (define_insn "*add_dtprel22" | |
866 | [(set (match_operand:DI 0 "register_operand" "=r") | |
867 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
868 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
869 | UNSPEC_DTPREL)))] | |
870 | "TARGET_TLS22" | |
871 | "addl %0 = @dtprel(%2), %1" | |
872 | [(set_attr "itanium_class" "ialu")]) | |
873 | ||
874 | (define_insn "load_ltoff_tprel" | |
875 | [(set (match_operand:DI 0 "register_operand" "=r") | |
876 | (plus:DI (reg:DI 1) | |
877 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
878 | UNSPEC_LTOFF_TPREL)))] | |
879 | "" | |
880 | "addl %0 = @ltoff(@tprel(%1)), gp" | |
881 | [(set_attr "itanium_class" "ialu")]) | |
882 | ||
883 | (define_expand "load_tprel" | |
884 | [(set (match_operand:DI 0 "register_operand" "") | |
885 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
886 | UNSPEC_TPREL))] | |
887 | "" | |
888 | "") | |
889 | ||
890 | (define_insn "*load_tprel64" | |
891 | [(set (match_operand:DI 0 "register_operand" "=r") | |
892 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
893 | UNSPEC_TPREL))] | |
894 | "TARGET_TLS64" | |
895 | "movl %0 = @tprel(%1)" | |
896 | [(set_attr "itanium_class" "long_i")]) | |
897 | ||
898 | (define_insn "*load_tprel22" | |
899 | [(set (match_operand:DI 0 "register_operand" "=r") | |
900 | (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] | |
901 | UNSPEC_TPREL))] | |
902 | "" | |
903 | "addl %0 = @tprel(%1), r0" | |
904 | [(set_attr "itanium_class" "ialu")]) | |
905 | ||
906 | (define_expand "add_tprel" | |
907 | [(set (match_operand:DI 0 "register_operand" "") | |
908 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
909 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
910 | UNSPEC_TPREL)))] | |
911 | "!TARGET_TLS64" | |
912 | "") | |
913 | ||
914 | (define_insn "*add_tprel14" | |
915 | [(set (match_operand:DI 0 "register_operand" "=r") | |
916 | (plus:DI (match_operand:DI 1 "register_operand" "r") | |
917 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
918 | UNSPEC_TPREL)))] | |
919 | "TARGET_TLS14" | |
920 | "adds %0 = @tprel(%2), %1" | |
921 | [(set_attr "itanium_class" "ialu")]) | |
922 | ||
923 | (define_insn "*add_tprel22" | |
924 | [(set (match_operand:DI 0 "register_operand" "=r") | |
925 | (plus:DI (match_operand:DI 1 "register_operand" "a") | |
926 | (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] | |
927 | UNSPEC_TPREL)))] | |
928 | "TARGET_TLS22" | |
929 | "addl %0 = @tprel(%2), %1" | |
930 | [(set_attr "itanium_class" "ialu")]) | |
931 | ||
3f622353 | 932 | ;; With no offsettable memory references, we've got to have a scratch |
2ffe0e02 ZW |
933 | ;; around to play with the second word. However, in order to avoid a |
934 | ;; reload nightmare we lie, claim we don't need one, and fix it up | |
935 | ;; in ia64_split_tmode_move. | |
3f622353 | 936 | (define_expand "movti" |
2ffe0e02 ZW |
937 | [(set (match_operand:TI 0 "general_operand" "") |
938 | (match_operand:TI 1 "general_operand" ""))] | |
3f622353 | 939 | "" |
3f622353 | 940 | { |
7b6e506e RH |
941 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
942 | if (!op1) | |
943 | DONE; | |
944 | operands[1] = op1; | |
1d5d7a21 | 945 | }) |
3f622353 RH |
946 | |
947 | (define_insn_and_split "*movti_internal" | |
948 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
2ffe0e02 | 949 | (match_operand:TI 1 "general_operand" "ri,m,r"))] |
3f622353 RH |
950 | "ia64_move_ok (operands[0], operands[1])" |
951 | "#" | |
952 | "reload_completed" | |
953 | [(const_int 0)] | |
3f622353 | 954 | { |
f57fc998 | 955 | ia64_split_tmode_move (operands); |
3f622353 | 956 | DONE; |
1d5d7a21 | 957 | } |
52e12ad0 | 958 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
959 | (set_attr "predicable" "no")]) |
960 | ||
c65ebc55 JW |
961 | ;; Floating Point Moves |
962 | ;; | |
963 | ;; Note - Patterns for SF mode moves are compulsory, but | |
05713b80 | 964 | ;; patterns for DF are optional, as GCC can synthesize them. |
c65ebc55 JW |
965 | |
966 | (define_expand "movsf" | |
967 | [(set (match_operand:SF 0 "general_operand" "") | |
968 | (match_operand:SF 1 "general_operand" ""))] | |
969 | "" | |
c65ebc55 | 970 | { |
7b6e506e RH |
971 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
972 | if (!op1) | |
973 | DONE; | |
974 | operands[1] = op1; | |
1d5d7a21 | 975 | }) |
c65ebc55 | 976 | |
c65ebc55 | 977 | (define_insn "*movsf_internal" |
4b983fdc RH |
978 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
979 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 980 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 981 | "@ |
1d5d7a21 RH |
982 | mov %0 = %F1 |
983 | ldfs %0 = %1%P1 | |
984 | stfs %0 = %F1%P0 | |
985 | getf.s %0 = %F1 | |
986 | setf.s %0 = %1 | |
987 | mov %0 = %1 | |
988 | ld4%O1 %0 = %1%P1 | |
989 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 990 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
991 | |
992 | (define_expand "movdf" | |
993 | [(set (match_operand:DF 0 "general_operand" "") | |
994 | (match_operand:DF 1 "general_operand" ""))] | |
995 | "" | |
c65ebc55 | 996 | { |
7b6e506e RH |
997 | rtx op1 = ia64_expand_move (operands[0], operands[1]); |
998 | if (!op1) | |
999 | DONE; | |
1000 | operands[1] = op1; | |
1d5d7a21 | 1001 | }) |
c65ebc55 | 1002 | |
c65ebc55 | 1003 | (define_insn "*movdf_internal" |
4b983fdc RH |
1004 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
1005 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 1006 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 1007 | "@ |
1d5d7a21 RH |
1008 | mov %0 = %F1 |
1009 | ldfd %0 = %1%P1 | |
1010 | stfd %0 = %F1%P0 | |
1011 | getf.d %0 = %F1 | |
1012 | setf.d %0 = %1 | |
1013 | mov %0 = %1 | |
1014 | ld8%O1 %0 = %1%P1 | |
1015 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 1016 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 1017 | |
3f622353 RH |
1018 | ;; With no offsettable memory references, we've got to have a scratch |
1019 | ;; around to play with the second word if the variable winds up in GRs. | |
02befdf4 ZW |
1020 | (define_expand "movxf" |
1021 | [(set (match_operand:XF 0 "general_operand" "") | |
1022 | (match_operand:XF 1 "general_operand" ""))] | |
1023 | "" | |
e5bde68a | 1024 | { |
6d7870d1 JW |
1025 | rtx op0 = operands[0]; |
1026 | ||
1027 | if (GET_CODE (op0) == SUBREG) | |
1028 | op0 = SUBREG_REG (op0); | |
1029 | ||
02befdf4 | 1030 | /* We must support XFmode loads into general registers for stdarg/vararg |
3f622353 | 1031 | and unprototyped calls. We split them into DImode loads for convenience. |
02befdf4 | 1032 | We don't need XFmode stores from general regs, because a stdarg/vararg |
3f622353 | 1033 | routine does a block store to memory of unnamed arguments. */ |
6d7870d1 JW |
1034 | |
1035 | if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0))) | |
3f622353 | 1036 | { |
02befdf4 | 1037 | /* We're hoping to transform everything that deals with XFmode |
3f622353 RH |
1038 | quantities and GR registers early in the compiler. */ |
1039 | if (no_new_pseudos) | |
1040 | abort (); | |
1041 | ||
1042 | /* Struct to register can just use TImode instead. */ | |
1043 | if ((GET_CODE (operands[1]) == SUBREG | |
1044 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
1045 | || (GET_CODE (operands[1]) == REG | |
1046 | && GR_REGNO_P (REGNO (operands[1])))) | |
1047 | { | |
6d7870d1 JW |
1048 | rtx op1 = operands[1]; |
1049 | ||
1050 | if (GET_CODE (op1) == SUBREG) | |
1051 | op1 = SUBREG_REG (op1); | |
1052 | else | |
1053 | /* ??? Maybe we should make a SUBREG here? */ | |
1054 | op1 = gen_rtx_REG (TImode, REGNO (op1)); | |
1055 | ||
1056 | emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1); | |
3f622353 RH |
1057 | DONE; |
1058 | } | |
1059 | ||
1060 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
1061 | { | |
6d7870d1 | 1062 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)), |
02befdf4 | 1063 | operand_subword (operands[1], 0, 0, XFmode)); |
6d7870d1 | 1064 | emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1), |
02befdf4 | 1065 | operand_subword (operands[1], 1, 0, XFmode)); |
3f622353 RH |
1066 | DONE; |
1067 | } | |
1068 | ||
1069 | /* If the quantity is in a register not known to be GR, spill it. */ | |
02befdf4 ZW |
1070 | if (register_operand (operands[1], XFmode)) |
1071 | operands[1] = spill_xfmode_operand (operands[1], 1); | |
3f622353 RH |
1072 | |
1073 | if (GET_CODE (operands[1]) == MEM) | |
1074 | { | |
1075 | rtx out[2]; | |
1076 | ||
6d7870d1 JW |
1077 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0)); |
1078 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1); | |
3f622353 | 1079 | |
f4ef873c RK |
1080 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
1081 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
1082 | DONE; |
1083 | } | |
1084 | ||
1085 | abort (); | |
1086 | } | |
1087 | ||
1088 | if (! reload_in_progress && ! reload_completed) | |
1089 | { | |
02befdf4 | 1090 | operands[1] = spill_xfmode_operand (operands[1], 0); |
3f622353 | 1091 | |
68d22aa5 RH |
1092 | if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG) |
1093 | { | |
1094 | rtx memt, memx, in = operands[1]; | |
1095 | if (CONSTANT_P (in)) | |
1096 | in = validize_mem (force_const_mem (XFmode, in)); | |
1097 | if (GET_CODE (in) == MEM) | |
1098 | memt = adjust_address (in, TImode, 0); | |
1099 | else | |
1100 | { | |
1101 | memt = assign_stack_temp (TImode, 16, 0); | |
1102 | memx = adjust_address (memt, XFmode, 0); | |
1103 | emit_move_insn (memx, in); | |
1104 | } | |
1105 | emit_move_insn (op0, memt); | |
1106 | DONE; | |
1107 | } | |
1108 | ||
3f622353 | 1109 | if (! ia64_move_ok (operands[0], operands[1])) |
02befdf4 | 1110 | operands[1] = force_reg (XFmode, operands[1]); |
3f622353 | 1111 | } |
1d5d7a21 | 1112 | }) |
e5bde68a | 1113 | |
3b572406 | 1114 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 1115 | |
02befdf4 | 1116 | (define_insn "*movxf_internal" |
78d8e0f9 ZW |
1117 | [(set (match_operand:XF 0 "destination_operand" "=f,f, m") |
1118 | (match_operand:XF 1 "general_operand" "fG,m,fG"))] | |
02befdf4 | 1119 | "ia64_move_ok (operands[0], operands[1])" |
e5bde68a | 1120 | "@ |
1d5d7a21 RH |
1121 | mov %0 = %F1 |
1122 | ldfe %0 = %1%P1 | |
1123 | stfe %0 = %F1%P0" | |
52e12ad0 | 1124 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
f57fc998 ZW |
1125 | |
1126 | ;; Better code generation via insns that deal with TFmode register pairs | |
2ffe0e02 | 1127 | ;; directly. Same concerns apply as for TImode. |
f57fc998 | 1128 | (define_expand "movtf" |
2ffe0e02 ZW |
1129 | [(set (match_operand:TF 0 "general_operand" "") |
1130 | (match_operand:TF 1 "general_operand" ""))] | |
f57fc998 ZW |
1131 | "" |
1132 | { | |
1133 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1134 | if (!op1) | |
1135 | DONE; | |
1136 | operands[1] = op1; | |
1137 | }) | |
1138 | ||
1139 | (define_insn_and_split "*movtf_internal" | |
1140 | [(set (match_operand:TF 0 "nonimmediate_operand" "=r,r,m") | |
2ffe0e02 | 1141 | (match_operand:TF 1 "general_operand" "ri,m,r"))] |
f57fc998 ZW |
1142 | "ia64_move_ok (operands[0], operands[1])" |
1143 | "#" | |
1144 | "reload_completed" | |
1145 | [(const_int 0)] | |
1146 | { | |
1147 | ia64_split_tmode_move (operands); | |
1148 | DONE; | |
1149 | } | |
1150 | [(set_attr "itanium_class" "unknown") | |
1151 | (set_attr "predicable" "no")]) | |
1152 | ||
c65ebc55 JW |
1153 | \f |
1154 | ;; :::::::::::::::::::: | |
1155 | ;; :: | |
1156 | ;; :: Conversions | |
1157 | ;; :: | |
1158 | ;; :::::::::::::::::::: | |
1159 | ||
1160 | ;; Signed conversions from a smaller integer to a larger integer | |
1161 | ||
1162 | (define_insn "extendqidi2" | |
0551c32d RH |
1163 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1164 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1165 | "" |
1166 | "sxt1 %0 = %1" | |
52e12ad0 | 1167 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1168 | |
1169 | (define_insn "extendhidi2" | |
0551c32d RH |
1170 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1171 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1172 | "" |
1173 | "sxt2 %0 = %1" | |
52e12ad0 | 1174 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
1175 | |
1176 | (define_insn "extendsidi2" | |
655f2eb9 RH |
1177 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
1178 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
1179 | "" |
1180 | "@ | |
1181 | sxt4 %0 = %1 | |
aebf2462 | 1182 | fsxt.r %0 = %1, %1" |
52e12ad0 | 1183 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
1184 | |
1185 | ;; Unsigned conversions from a smaller integer to a larger integer | |
1186 | ||
1187 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
1188 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1189 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1190 | "" |
1191 | "@ | |
1192 | zxt1 %0 = %1 | |
1193 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 1194 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1195 | |
1196 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
1197 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
1198 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
1199 | "" |
1200 | "@ | |
1201 | zxt2 %0 = %1 | |
1202 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 1203 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
1204 | |
1205 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 1206 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 1207 | (zero_extend:DI |
655f2eb9 | 1208 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
1209 | "" |
1210 | "@ | |
1211 | zxt4 %0 = %1 | |
1212 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 1213 | fmix.r %0 = f0, %1" |
52e12ad0 | 1214 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
1215 | |
1216 | ;; Convert between floating point types of different sizes. | |
1217 | ||
640cea5f JW |
1218 | ;; At first glance, it would appear that emitting fnorm for an extending |
1219 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
1220 | ;; correctly only if the input is properly rounded for its type. In | |
1221 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
1222 | ;; denorm single. Since we don't know what the next instruction will be, we | |
1223 | ;; have to emit an fnorm. | |
1224 | ||
e8e20f18 RH |
1225 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
1226 | ;; when we can. Should probably use a scheme like has been proposed | |
1227 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
1228 | ;; would let combine merge the thing into adjacent insns. See also how the |
1229 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
1230 | ;; se_register_operand. | |
c65ebc55 | 1231 | |
640cea5f JW |
1232 | (define_insn "extendsfdf2" |
1233 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
1234 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1235 | "" |
640cea5f JW |
1236 | "fnorm.d %0 = %1" |
1237 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 1238 | |
02befdf4 ZW |
1239 | (define_insn "extendsfxf2" |
1240 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1241 | (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))] | |
1242 | "" | |
640cea5f JW |
1243 | "fnorm %0 = %1" |
1244 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1245 | |
02befdf4 ZW |
1246 | (define_insn "extenddfxf2" |
1247 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1248 | (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))] | |
1249 | "" | |
640cea5f JW |
1250 | "fnorm %0 = %1" |
1251 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 1252 | |
c65ebc55 | 1253 | (define_insn "truncdfsf2" |
0551c32d RH |
1254 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1255 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1256 | "" |
aebf2462 | 1257 | "fnorm.s %0 = %1" |
52e12ad0 | 1258 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1259 | |
02befdf4 | 1260 | (define_insn "truncxfsf2" |
0551c32d | 1261 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1262 | (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))] |
1263 | "" | |
aebf2462 | 1264 | "fnorm.s %0 = %1" |
52e12ad0 | 1265 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 1266 | |
02befdf4 | 1267 | (define_insn "truncxfdf2" |
0551c32d | 1268 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1269 | (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))] |
1270 | "" | |
aebf2462 | 1271 | "fnorm.d %0 = %1" |
52e12ad0 | 1272 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
1273 | |
1274 | ;; Convert between signed integer types and floating point. | |
1275 | ||
02befdf4 ZW |
1276 | (define_insn "floatdixf2" |
1277 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1278 | (float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1279 | "" | |
e5bde68a | 1280 | "fcvt.xf %0 = %1" |
52e12ad0 | 1281 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1282 | |
1283 | (define_insn "fix_truncsfdi2" | |
0551c32d RH |
1284 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1285 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1286 | "" |
aebf2462 | 1287 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1288 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1289 | |
1290 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
1291 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1292 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1293 | "" |
aebf2462 | 1294 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1295 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1296 | |
02befdf4 | 1297 | (define_insn "fix_truncxfdi2" |
0551c32d | 1298 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1299 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1300 | "" | |
aebf2462 | 1301 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 1302 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1303 | |
02befdf4 | 1304 | (define_insn "fix_truncxfdi2_alts" |
655f2eb9 | 1305 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1306 | (fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1307 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1308 | "" |
aebf2462 | 1309 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 1310 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1311 | |
c65ebc55 JW |
1312 | ;; Convert between unsigned integer types and floating point. |
1313 | ||
1314 | (define_insn "floatunsdisf2" | |
0551c32d RH |
1315 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
1316 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1317 | "" |
aebf2462 | 1318 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 1319 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1320 | |
1321 | (define_insn "floatunsdidf2" | |
0551c32d RH |
1322 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
1323 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1324 | "" |
aebf2462 | 1325 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 1326 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1327 | |
02befdf4 ZW |
1328 | (define_insn "floatunsdixf2" |
1329 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
1330 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))] | |
1331 | "" | |
aebf2462 | 1332 | "fcvt.xuf %0 = %1" |
52e12ad0 | 1333 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 1334 | |
c65ebc55 | 1335 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
1336 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1337 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1338 | "" |
aebf2462 | 1339 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1340 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1341 | |
1342 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
1343 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
1344 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 1345 | "" |
aebf2462 | 1346 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1347 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 1348 | |
02befdf4 | 1349 | (define_insn "fixuns_truncxfdi2" |
0551c32d | 1350 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 ZW |
1351 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))] |
1352 | "" | |
aebf2462 | 1353 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 1354 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 1355 | |
02befdf4 | 1356 | (define_insn "fixuns_truncxfdi2_alts" |
655f2eb9 | 1357 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
02befdf4 | 1358 | (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f"))) |
655f2eb9 | 1359 | (use (match_operand:SI 2 "const_int_operand" ""))] |
02befdf4 | 1360 | "" |
aebf2462 | 1361 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 1362 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
1363 | \f |
1364 | ;; :::::::::::::::::::: | |
1365 | ;; :: | |
1366 | ;; :: Bit field extraction | |
1367 | ;; :: | |
1368 | ;; :::::::::::::::::::: | |
1369 | ||
c65ebc55 | 1370 | (define_insn "extv" |
0551c32d RH |
1371 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1372 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1373 | (match_operand:DI 2 "const_int_operand" "n") |
1374 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1375 | "" | |
1376 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 1377 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1378 | |
1379 | (define_insn "extzv" | |
0551c32d RH |
1380 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1381 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1382 | (match_operand:DI 2 "const_int_operand" "n") |
1383 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1384 | "" | |
1385 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1386 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1387 | |
1388 | ;; Insert a bit field. | |
1389 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1390 | ;; Source1 can be 0 or -1. | |
1391 | ;; Source2 can be 0. | |
1392 | ||
1393 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1394 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1395 | ;; where source2 != dest. | |
1396 | ||
1397 | (define_expand "insv" | |
0551c32d | 1398 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1399 | (match_operand:DI 1 "const_int_operand" "") |
1400 | (match_operand:DI 2 "const_int_operand" "")) | |
1401 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1402 | "" | |
c65ebc55 JW |
1403 | { |
1404 | int width = INTVAL (operands[1]); | |
1405 | int shift = INTVAL (operands[2]); | |
1406 | ||
1407 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1408 | pseudo. */ | |
1409 | if (! register_operand (operands[3], DImode) | |
1410 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1411 | operands[3] = force_reg (DImode, operands[3]); | |
1412 | ||
1413 | /* If this is a single dep instruction, we have nothing to do. */ | |
1414 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1415 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1416 | { | |
1417 | /* Check for cases that can be implemented with a mix instruction. */ | |
1418 | if (width == 32 && shift == 0) | |
1419 | { | |
1420 | /* Directly generating the mix4left instruction confuses | |
1421 | optimize_bit_field in function.c. Since this is performing | |
1422 | a useful optimization, we defer generation of the complicated | |
1423 | mix4left RTL to the first splitting phase. */ | |
1424 | rtx tmp = gen_reg_rtx (DImode); | |
1425 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1426 | DONE; | |
1427 | } | |
1428 | else if (width == 32 && shift == 32) | |
1429 | { | |
1430 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1431 | DONE; | |
1432 | } | |
1433 | ||
d2ba6dcf JW |
1434 | /* We could handle remaining cases by emitting multiple dep |
1435 | instructions. | |
1436 | ||
1437 | If we need more than two dep instructions then we lose. A 6 | |
1438 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1439 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1440 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1441 | only one function unit that can execute dep and shr immed. | |
1442 | ||
1443 | If we only need two dep instruction, then we still lose. | |
1444 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1445 | the unnecessary mov, this is still undesirable because it will be | |
1446 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1447 | function unit. */ | |
1448 | ||
c65ebc55 JW |
1449 | FAIL; |
1450 | ||
1451 | #if 0 | |
1452 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1453 | for now. */ | |
1454 | while (width > 16) | |
1455 | { | |
1456 | rtx tmp; | |
1457 | ||
1458 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1459 | operands[3])); | |
1460 | shift += 16; | |
1461 | width -= 16; | |
1462 | tmp = gen_reg_rtx (DImode); | |
1463 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1464 | operands[3] = tmp; | |
1465 | } | |
1466 | operands[1] = GEN_INT (width); | |
1467 | operands[2] = GEN_INT (shift); | |
1468 | #endif | |
1469 | } | |
1d5d7a21 | 1470 | }) |
c65ebc55 JW |
1471 | |
1472 | (define_insn "*insv_internal" | |
0551c32d | 1473 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1474 | (match_operand:DI 1 "const_int_operand" "n") |
1475 | (match_operand:DI 2 "const_int_operand" "n")) | |
1476 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1477 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1478 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1479 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1480 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1481 | |
43a88a8c | 1482 | ;; Combine doesn't like to create bit-field insertions into zero. |
041f25e6 | 1483 | (define_insn "*depz_internal" |
0551c32d RH |
1484 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1485 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1486 | (match_operand:DI 2 "const_int_operand" "n")) |
1487 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1488 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1489 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
041f25e6 RH |
1490 | { |
1491 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1d5d7a21 RH |
1492 | return "%,dep.z %0 = %1, %2, %3"; |
1493 | } | |
52e12ad0 | 1494 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1495 | |
c65ebc55 | 1496 | (define_insn "shift_mix4left" |
0551c32d | 1497 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1498 | (const_int 32) (const_int 0)) |
0551c32d RH |
1499 | (match_operand:DI 1 "gr_register_operand" "r")) |
1500 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1501 | "" |
1502 | "#" | |
52e12ad0 | 1503 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1504 | |
c65ebc55 JW |
1505 | (define_split |
1506 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1507 | (const_int 32) (const_int 0)) | |
1508 | (match_operand:DI 1 "register_operand" "")) | |
1509 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
06a419ff | 1510 | "" |
c65ebc55 JW |
1511 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) |
1512 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1513 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1514 | "operands[3] = operands[2];") | |
1515 | ||
1516 | (define_insn "*mix4left" | |
0551c32d | 1517 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1518 | (const_int 32) (const_int 0)) |
0551c32d | 1519 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1520 | (const_int 32)))] |
1521 | "" | |
1522 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1523 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1524 | |
1525 | (define_insn "mix4right" | |
0551c32d | 1526 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1527 | (const_int 32) (const_int 32)) |
0551c32d | 1528 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1529 | "" |
1530 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1531 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1532 | |
1533 | ;; This is used by the rotrsi3 pattern. | |
1534 | ||
1535 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1536 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1537 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1538 | (ashift:DI (zero_extend:DI | |
1539 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1540 | (const_int 32))))] |
1541 | "" | |
fa9a44e8 | 1542 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1543 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1544 | |
1545 | \f | |
1546 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1547 | ;; :: |
f2f90c63 RH |
1548 | ;; :: 1 bit Integer arithmetic |
1549 | ;; :: | |
1550 | ;; :::::::::::::::::::: | |
1551 | ||
1552 | (define_insn_and_split "andbi3" | |
1553 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1554 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1555 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1556 | "" | |
1557 | "@ | |
1558 | # | |
1559 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1560 | and %0 = %2, %1" | |
1561 | "reload_completed | |
1562 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1563 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1564 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1565 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1566 | (match_dup 0))))] | |
1567 | "" | |
52e12ad0 | 1568 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1569 | |
1570 | (define_insn_and_split "*andcmbi3" | |
1571 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1572 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1573 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1574 | "" | |
1575 | "@ | |
1576 | # | |
967603ef | 1577 | tbit.z.and.orcm %0, %I0 = %1, 0 |
f2f90c63 RH |
1578 | andcm %0 = %2, %1" |
1579 | "reload_completed | |
1580 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1581 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1582 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
1583 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1584 | (match_dup 0))))] | |
1585 | "" | |
52e12ad0 | 1586 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1587 | |
1588 | (define_insn_and_split "iorbi3" | |
1589 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1590 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1591 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1592 | "" | |
1593 | "@ | |
1594 | # | |
1595 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1596 | or %0 = %2, %1" | |
1597 | "reload_completed | |
1598 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1599 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1600 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1601 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1602 | (match_dup 0))))] | |
1603 | "" | |
52e12ad0 | 1604 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1605 | |
1606 | (define_insn_and_split "*iorcmbi3" | |
1607 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1608 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1609 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1610 | "" | |
1611 | "@ | |
1612 | # | |
967603ef | 1613 | tbit.z.or.andcm %0, %I0 = %1, 0" |
f2f90c63 RH |
1614 | "reload_completed |
1615 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
967603ef | 1616 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" |
f2f90c63 RH |
1617 | [(cond_exec (eq (match_dup 1) (const_int 0)) |
1618 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1619 | (match_dup 0))))] | |
1620 | "" | |
52e12ad0 | 1621 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1622 | |
1623 | (define_insn "one_cmplbi2" | |
1624 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1625 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1626 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1627 | "" | |
1628 | "@ | |
1629 | tbit.z %0, %I0 = %1, 0 | |
1630 | xor %0 = 1, %1 | |
1631 | # | |
1632 | #" | |
52e12ad0 | 1633 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1634 | |
1635 | (define_split | |
1636 | [(set (match_operand:BI 0 "register_operand" "") | |
1637 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1638 | (clobber (match_scratch:BI 2 ""))] | |
1639 | "reload_completed | |
1640 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
f2f90c63 RH |
1641 | && rtx_equal_p (operands[0], operands[1])" |
1642 | [(set (match_dup 4) (match_dup 3)) | |
1643 | (set (match_dup 0) (const_int 1)) | |
1644 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1645 | (set (match_dup 0) (const_int 0))) | |
086c0f96 | 1646 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1647 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); |
1648 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1649 | ||
1650 | (define_split | |
1651 | [(set (match_operand:BI 0 "register_operand" "") | |
1652 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1653 | (clobber (match_scratch:BI 2 ""))] | |
1654 | "reload_completed | |
1655 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1656 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1657 | && ! rtx_equal_p (operands[0], operands[1])" | |
1658 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1659 | (set (match_dup 0) (const_int 0))) | |
1660 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1661 | (set (match_dup 0) (const_int 1))) | |
086c0f96 | 1662 | (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
1663 | "") |
1664 | ||
1665 | (define_insn "*cmpsi_and_0" | |
1666 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1667 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1668 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1669 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1670 | (match_operand:BI 1 "register_operand" "0")))] | |
1671 | "" | |
1672 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1673 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1674 | |
1675 | (define_insn "*cmpsi_and_1" | |
1676 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1677 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1678 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1679 | (const_int 0)]) | |
1680 | (match_operand:BI 1 "register_operand" "0")))] | |
1681 | "" | |
1682 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1683 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1684 | |
1685 | (define_insn "*cmpsi_andnot_0" | |
1686 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1687 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1688 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1689 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1690 | (match_operand:BI 1 "register_operand" "0")))] | |
1691 | "" | |
1692 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1693 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1694 | |
1695 | (define_insn "*cmpsi_andnot_1" | |
1696 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1697 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1698 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1699 | (const_int 0)])) | |
1700 | (match_operand:BI 1 "register_operand" "0")))] | |
1701 | "" | |
1702 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1703 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1704 | |
1705 | (define_insn "*cmpdi_and_0" | |
1706 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1707 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1708 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1709 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1710 | (match_operand:BI 1 "register_operand" "0")))] | |
1711 | "" | |
1712 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1713 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1714 | |
1715 | (define_insn "*cmpdi_and_1" | |
1716 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1717 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1718 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1719 | (const_int 0)]) | |
1720 | (match_operand:BI 1 "register_operand" "0")))] | |
1721 | "" | |
1722 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1723 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1724 | |
1725 | (define_insn "*cmpdi_andnot_0" | |
1726 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1727 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1728 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1729 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1730 | (match_operand:BI 1 "register_operand" "0")))] | |
1731 | "" | |
1732 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1733 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1734 | |
1735 | (define_insn "*cmpdi_andnot_1" | |
1736 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1737 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1738 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1739 | (const_int 0)])) | |
1740 | (match_operand:BI 1 "register_operand" "0")))] | |
1741 | "" | |
1742 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1743 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1744 | |
1745 | (define_insn "*tbit_and_0" | |
1746 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1747 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1748 | (const_int 1)) | |
1749 | (const_int 0)) | |
c77e04ae | 1750 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1751 | "" |
1752 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1753 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1754 | |
1755 | (define_insn "*tbit_and_1" | |
1756 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1757 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1758 | (const_int 1)) | |
1759 | (const_int 0)) | |
c77e04ae | 1760 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1761 | "" |
1762 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1763 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1764 | |
1765 | (define_insn "*tbit_and_2" | |
1766 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1767 | (and:BI (ne:BI (zero_extract:DI | |
1768 | (match_operand:DI 1 "gr_register_operand" "r") | |
1769 | (const_int 1) | |
1770 | (match_operand:DI 2 "const_int_operand" "n")) | |
1771 | (const_int 0)) | |
1772 | (match_operand:BI 3 "register_operand" "0")))] | |
1773 | "" | |
1774 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1775 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1776 | |
1777 | (define_insn "*tbit_and_3" | |
1778 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1779 | (and:BI (eq:BI (zero_extract:DI | |
1780 | (match_operand:DI 1 "gr_register_operand" "r") | |
1781 | (const_int 1) | |
1782 | (match_operand:DI 2 "const_int_operand" "n")) | |
1783 | (const_int 0)) | |
1784 | (match_operand:BI 3 "register_operand" "0")))] | |
1785 | "" | |
1786 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1787 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1788 | |
1789 | (define_insn "*cmpsi_or_0" | |
1790 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1791 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1792 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1793 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1794 | (match_operand:BI 1 "register_operand" "0")))] | |
1795 | "" | |
1796 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1797 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1798 | |
1799 | (define_insn "*cmpsi_or_1" | |
1800 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1801 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1802 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1803 | (const_int 0)]) | |
1804 | (match_operand:BI 1 "register_operand" "0")))] | |
1805 | "" | |
1806 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1807 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1808 | |
1809 | (define_insn "*cmpsi_orcm_0" | |
1810 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1811 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1812 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1813 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1814 | (match_operand:BI 1 "register_operand" "0")))] | |
1815 | "" | |
1816 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1817 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1818 | |
1819 | (define_insn "*cmpsi_orcm_1" | |
1820 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1821 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1822 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1823 | (const_int 0)])) | |
1824 | (match_operand:BI 1 "register_operand" "0")))] | |
1825 | "" | |
1826 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1827 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1828 | |
1829 | (define_insn "*cmpdi_or_0" | |
1830 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1831 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1832 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1833 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1834 | (match_operand:BI 1 "register_operand" "0")))] | |
1835 | "" | |
1836 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1837 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1838 | |
1839 | (define_insn "*cmpdi_or_1" | |
1840 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1841 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1842 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1843 | (const_int 0)]) | |
1844 | (match_operand:BI 1 "register_operand" "0")))] | |
1845 | "" | |
1846 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1847 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1848 | |
1849 | (define_insn "*cmpdi_orcm_0" | |
1850 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1851 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1852 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1853 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1854 | (match_operand:BI 1 "register_operand" "0")))] | |
1855 | "" | |
1856 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1857 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1858 | |
1859 | (define_insn "*cmpdi_orcm_1" | |
1860 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1861 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1862 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1863 | (const_int 0)])) | |
1864 | (match_operand:BI 1 "register_operand" "0")))] | |
1865 | "" | |
1866 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1867 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1868 | |
1869 | (define_insn "*tbit_or_0" | |
1870 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1871 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1872 | (const_int 1)) | |
1873 | (const_int 0)) | |
c77e04ae | 1874 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1875 | "" |
1876 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1877 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1878 | |
1879 | (define_insn "*tbit_or_1" | |
1880 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1881 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1882 | (const_int 1)) | |
1883 | (const_int 0)) | |
c77e04ae | 1884 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1885 | "" |
1886 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1887 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1888 | |
1889 | (define_insn "*tbit_or_2" | |
1890 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1891 | (ior:BI (ne:BI (zero_extract:DI | |
1892 | (match_operand:DI 1 "gr_register_operand" "r") | |
1893 | (const_int 1) | |
1894 | (match_operand:DI 2 "const_int_operand" "n")) | |
1895 | (const_int 0)) | |
1896 | (match_operand:BI 3 "register_operand" "0")))] | |
1897 | "" | |
1898 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1899 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1900 | |
1901 | (define_insn "*tbit_or_3" | |
1902 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1903 | (ior:BI (eq:BI (zero_extract:DI | |
1904 | (match_operand:DI 1 "gr_register_operand" "r") | |
1905 | (const_int 1) | |
1906 | (match_operand:DI 2 "const_int_operand" "n")) | |
1907 | (const_int 0)) | |
1908 | (match_operand:BI 3 "register_operand" "0")))] | |
1909 | "" | |
1910 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1911 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1912 | |
1913 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1914 | ||
1915 | (define_split | |
1916 | [(set (match_operand:BI 0 "register_operand" "") | |
1917 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1918 | (const_int 0)) | |
1919 | (match_operand:DI 3 "register_operand" "")) | |
1920 | (const_int 0)))] | |
1921 | "" | |
1922 | [(set (match_dup 0) | |
1923 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1924 | (match_dup 2)))] | |
1925 | "") | |
1926 | ||
1927 | (define_split | |
1928 | [(set (match_operand:BI 0 "register_operand" "") | |
1929 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1930 | (const_int 0)) | |
1931 | (match_operand:DI 3 "register_operand" "")) | |
1932 | (const_int 0)))] | |
1933 | "" | |
1934 | [(set (match_dup 0) | |
1935 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1936 | (match_dup 2))) | |
1937 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1938 | (clobber (scratch))])] | |
1939 | "") | |
1940 | ||
1941 | (define_split | |
1942 | [(set (match_operand:BI 0 "register_operand" "") | |
1943 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1944 | (const_int 0)) | |
1945 | (match_operand:DI 3 "register_operand" "")) | |
1946 | (const_int 0)))] | |
1947 | "" | |
1948 | [(set (match_dup 0) | |
1949 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1950 | (match_dup 2)))] | |
1951 | "") | |
1952 | ||
1953 | (define_split | |
1954 | [(set (match_operand:BI 0 "register_operand" "") | |
1955 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1956 | (const_int 0)) | |
1957 | (match_operand:DI 3 "register_operand" "")) | |
1958 | (const_int 0)))] | |
1959 | "" | |
1960 | [(set (match_dup 0) | |
1961 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1962 | (match_dup 2))) | |
1963 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1964 | (clobber (scratch))])] | |
1965 | "") | |
1966 | ||
1967 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1968 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1969 | ;; nothing bad happens to the comparisons in the meantime. | |
1970 | ;; | |
1971 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1972 | ;; that we're doing height reduction. | |
1973 | ; | |
1974 | ;(define_insn_and_split "" | |
1975 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1976 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1977 | ; [(match_operand 2 "" "") | |
1978 | ; (match_operand 3 "" "")]) | |
1979 | ; (match_operator:BI 4 "comparison_operator" | |
1980 | ; [(match_operand 5 "" "") | |
1981 | ; (match_operand 6 "" "")])) | |
1982 | ; (match_dup 0)))] | |
1983 | ; "flag_schedule_insns" | |
1984 | ; "#" | |
1985 | ; "" | |
1986 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1987 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1988 | ; "") | |
1989 | ; | |
1990 | ;(define_insn_and_split "" | |
1991 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1992 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1993 | ; [(match_operand 2 "" "") | |
1994 | ; (match_operand 3 "" "")]) | |
1995 | ; (match_operator:BI 4 "comparison_operator" | |
1996 | ; [(match_operand 5 "" "") | |
1997 | ; (match_operand 6 "" "")])) | |
1998 | ; (match_dup 0)))] | |
1999 | ; "flag_schedule_insns" | |
2000 | ; "#" | |
2001 | ; "" | |
2002 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
2003 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
2004 | ; "") | |
2005 | ; | |
2006 | ;(define_split | |
2007 | ; [(set (match_operand:BI 0 "register_operand" "") | |
2008 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
2009 | ; [(match_operand 2 "" "") | |
2010 | ; (match_operand 3 "" "")]) | |
2011 | ; (match_operand:BI 7 "register_operand" "")) | |
2012 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
2013 | ; [(match_operand 5 "" "") | |
2014 | ; (match_operand 6 "" "")]) | |
2015 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2016 | ; "" | |
2017 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
2018 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
2019 | ; (match_dup 0)))] | |
2020 | ; "") | |
2021 | ; | |
2022 | ;(define_split | |
2023 | ; [(set (match_operand:BI 0 "register_operand" "") | |
2024 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
2025 | ; [(match_operand 2 "" "") | |
2026 | ; (match_operand 3 "" "")]) | |
2027 | ; (match_operand:BI 7 "register_operand" "")) | |
2028 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
2029 | ; [(match_operand 5 "" "") | |
2030 | ; (match_operand 6 "" "")]) | |
2031 | ; (match_operand:BI 8 "register_operand" ""))))] | |
2032 | ; "" | |
2033 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
2034 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
2035 | ; (match_dup 0)))] | |
2036 | ; "") | |
2037 | ||
2038 | ;; Try harder to avoid predicate copies by duplicating compares. | |
2039 | ;; Note that we'll have already split the predicate copy, which | |
2040 | ;; is kind of a pain, but oh well. | |
2041 | ||
2042 | (define_peephole2 | |
2043 | [(set (match_operand:BI 0 "register_operand" "") | |
2044 | (match_operand:BI 1 "comparison_operator" "")) | |
2045 | (set (match_operand:CCI 2 "register_operand" "") | |
2046 | (match_operand:CCI 3 "register_operand" "")) | |
2047 | (set (match_operand:CCI 4 "register_operand" "") | |
2048 | (match_operand:CCI 5 "register_operand" "")) | |
2049 | (set (match_operand:BI 6 "register_operand" "") | |
086c0f96 | 2050 | (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))] |
f2f90c63 RH |
2051 | "REGNO (operands[3]) == REGNO (operands[0]) |
2052 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
2053 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
2054 | && REGNO (operands[6]) == REGNO (operands[2])" | |
2055 | [(set (match_dup 0) (match_dup 1)) | |
2056 | (set (match_dup 6) (match_dup 7))] | |
2057 | "operands[7] = copy_rtx (operands[1]);") | |
2058 | \f | |
2059 | ;; :::::::::::::::::::: | |
2060 | ;; :: | |
cf1f6ae3 RH |
2061 | ;; :: 16 bit Integer arithmetic |
2062 | ;; :: | |
2063 | ;; :::::::::::::::::::: | |
2064 | ||
2065 | (define_insn "mulhi3" | |
2066 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
2067 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
2068 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
2069 | "" | |
2a7ffc85 | 2070 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 2071 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
2072 | |
2073 | \f | |
2074 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
2075 | ;; :: |
2076 | ;; :: 32 bit Integer arithmetic | |
2077 | ;; :: | |
2078 | ;; :::::::::::::::::::: | |
2079 | ||
058557c4 | 2080 | (define_insn "addsi3" |
0551c32d RH |
2081 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
2082 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
2083 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2084 | "" |
2085 | "@ | |
1d5d7a21 RH |
2086 | add %0 = %1, %2 |
2087 | adds %0 = %2, %1 | |
2088 | addl %0 = %2, %1" | |
52e12ad0 | 2089 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2090 | |
2091 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
2092 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2093 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
2094 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2095 | (const_int 1)))] |
2096 | "" | |
2097 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2098 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2099 | |
5527bf14 | 2100 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
2101 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2102 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2103 | (const_int 2)) |
2104 | (const_int 1)))] | |
2105 | "" | |
2106 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2107 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2108 | |
058557c4 | 2109 | (define_insn "*addsi3_shladd" |
0551c32d RH |
2110 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2111 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 2112 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 2113 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 2114 | "" |
058557c4 | 2115 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 2116 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2117 | |
058557c4 | 2118 | (define_insn "subsi3" |
0551c32d RH |
2119 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2120 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
2121 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2122 | "" |
2123 | "sub %0 = %1, %2" | |
52e12ad0 | 2124 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2125 | |
2126 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
2127 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2128 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
2129 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2130 | "" |
2131 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
2132 | [(set_attr "itanium_class" "ialu")]) |
2133 | ||
2134 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 2135 | |
058557c4 | 2136 | (define_insn "mulsi3" |
0551c32d | 2137 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
2138 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
2139 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2140 | "" |
aebf2462 | 2141 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2142 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 2143 | |
655f2eb9 | 2144 | (define_insn "maddsi4" |
11a13704 RH |
2145 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
2146 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
2147 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
2148 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
2149 | "" | |
aebf2462 | 2150 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2151 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 2152 | |
058557c4 | 2153 | (define_insn "negsi2" |
0551c32d RH |
2154 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
2155 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2156 | "" |
2157 | "sub %0 = r0, %1" | |
52e12ad0 | 2158 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2159 | |
2160 | (define_expand "abssi2" | |
2161 | [(set (match_dup 2) | |
f2f90c63 | 2162 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2163 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 2164 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2165 | (neg:SI (match_dup 1)) |
2166 | (match_dup 1)))] | |
c65ebc55 | 2167 | "" |
1d5d7a21 | 2168 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2169 | |
2170 | (define_expand "sminsi3" | |
2171 | [(set (match_dup 3) | |
f2f90c63 | 2172 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2173 | (match_operand:SI 2 "gr_register_operand" ""))) |
2174 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2175 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2176 | (match_dup 2) (match_dup 1)))] |
2177 | "" | |
1d5d7a21 | 2178 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2179 | |
2180 | (define_expand "smaxsi3" | |
2181 | [(set (match_dup 3) | |
f2f90c63 | 2182 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2183 | (match_operand:SI 2 "gr_register_operand" ""))) |
2184 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2185 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2186 | (match_dup 1) (match_dup 2)))] |
2187 | "" | |
1d5d7a21 | 2188 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2189 | |
2190 | (define_expand "uminsi3" | |
2191 | [(set (match_dup 3) | |
f2f90c63 | 2192 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2193 | (match_operand:SI 2 "gr_register_operand" ""))) |
2194 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2195 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2196 | (match_dup 2) (match_dup 1)))] |
2197 | "" | |
1d5d7a21 | 2198 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2199 | |
2200 | (define_expand "umaxsi3" | |
2201 | [(set (match_dup 3) | |
f2f90c63 | 2202 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
2203 | (match_operand:SI 2 "gr_register_operand" ""))) |
2204 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 2205 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2206 | (match_dup 1) (match_dup 2)))] |
2207 | "" | |
1d5d7a21 | 2208 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 | 2209 | |
655f2eb9 RH |
2210 | (define_expand "divsi3" |
2211 | [(set (match_operand:SI 0 "register_operand" "") | |
2212 | (div:SI (match_operand:SI 1 "general_operand" "") | |
2213 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2214 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2215 | { |
9aec7fb4 | 2216 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2217 | |
02befdf4 | 2218 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2219 | op0_di = gen_reg_rtx (DImode); |
2220 | ||
2221 | if (CONSTANT_P (operands[1])) | |
2222 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2223 | op1_xf = gen_reg_rtx (XFmode); |
2224 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2225 | |
2226 | if (CONSTANT_P (operands[2])) | |
2227 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2228 | op2_xf = gen_reg_rtx (XFmode); |
2229 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 RH |
2230 | |
2231 | /* 2^-34 */ | |
9aec7fb4 SE |
2232 | twon34_exp = gen_reg_rtx (DImode); |
2233 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2234 | twon34 = gen_reg_rtx (XFmode); | |
2235 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2236 | |
02befdf4 | 2237 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2238 | |
02befdf4 | 2239 | emit_insn (gen_fix_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2240 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2241 | DONE; | |
1d5d7a21 | 2242 | }) |
655f2eb9 RH |
2243 | |
2244 | (define_expand "modsi3" | |
2245 | [(set (match_operand:SI 0 "register_operand" "") | |
2246 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
2247 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2248 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2249 | { |
2250 | rtx op2_neg, op1_di, div; | |
2251 | ||
2252 | div = gen_reg_rtx (SImode); | |
2253 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
2254 | ||
2255 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2256 | ||
2257 | /* This is a trick to get us to reuse the value that we're sure to | |
2258 | have already copied to the FP regs. */ | |
2259 | op1_di = gen_reg_rtx (DImode); | |
2260 | convert_move (op1_di, operands[1], 0); | |
2261 | ||
2262 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2263 | gen_lowpart (SImode, op1_di))); | |
2264 | DONE; | |
1d5d7a21 | 2265 | }) |
655f2eb9 RH |
2266 | |
2267 | (define_expand "udivsi3" | |
2268 | [(set (match_operand:SI 0 "register_operand" "") | |
2269 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
2270 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2271 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2272 | { |
9aec7fb4 | 2273 | rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp; |
655f2eb9 | 2274 | |
02befdf4 | 2275 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2276 | op0_di = gen_reg_rtx (DImode); |
2277 | ||
2278 | if (CONSTANT_P (operands[1])) | |
2279 | operands[1] = force_reg (SImode, operands[1]); | |
02befdf4 ZW |
2280 | op1_xf = gen_reg_rtx (XFmode); |
2281 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2282 | |
2283 | if (CONSTANT_P (operands[2])) | |
2284 | operands[2] = force_reg (SImode, operands[2]); | |
02befdf4 ZW |
2285 | op2_xf = gen_reg_rtx (XFmode); |
2286 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 RH |
2287 | |
2288 | /* 2^-34 */ | |
9aec7fb4 SE |
2289 | twon34_exp = gen_reg_rtx (DImode); |
2290 | emit_move_insn (twon34_exp, GEN_INT (65501)); | |
2291 | twon34 = gen_reg_rtx (XFmode); | |
2292 | emit_insn (gen_setf_exp_xf (twon34, twon34_exp)); | |
655f2eb9 | 2293 | |
02befdf4 | 2294 | emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34)); |
655f2eb9 | 2295 | |
02befdf4 | 2296 | emit_insn (gen_fixuns_truncxfdi2_alts (op0_di, op0_xf, const1_rtx)); |
655f2eb9 RH |
2297 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); |
2298 | DONE; | |
1d5d7a21 | 2299 | }) |
655f2eb9 RH |
2300 | |
2301 | (define_expand "umodsi3" | |
2302 | [(set (match_operand:SI 0 "register_operand" "") | |
2303 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
2304 | (match_operand:SI 2 "general_operand" "")))] | |
02befdf4 | 2305 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2306 | { |
2307 | rtx op2_neg, op1_di, div; | |
2308 | ||
2309 | div = gen_reg_rtx (SImode); | |
2310 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
2311 | ||
2312 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
2313 | ||
2314 | /* This is a trick to get us to reuse the value that we're sure to | |
2315 | have already copied to the FP regs. */ | |
2316 | op1_di = gen_reg_rtx (DImode); | |
2317 | convert_move (op1_di, operands[1], 1); | |
2318 | ||
2319 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
2320 | gen_lowpart (SImode, op1_di))); | |
2321 | DONE; | |
1d5d7a21 | 2322 | }) |
655f2eb9 RH |
2323 | |
2324 | (define_insn_and_split "divsi3_internal" | |
02befdf4 ZW |
2325 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2326 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2327 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2328 | (clobber (match_scratch:XF 4 "=&f")) | |
2329 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2330 | (clobber (match_scratch:BI 6 "=c")) |
02befdf4 ZW |
2331 | (use (match_operand:XF 3 "fr_register_operand" "f"))] |
2332 | "TARGET_INLINE_INT_DIV" | |
655f2eb9 RH |
2333 | "#" |
2334 | "&& reload_completed" | |
02befdf4 | 2335 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2336 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2337 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2338 | (use (const_int 1))]) |
2339 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2340 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2341 | (use (const_int 1))])) |
2342 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2343 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
2344 | (minus:XF (match_dup 7) |
2345 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2346 | (use (const_int 1))])) |
2347 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2348 | (parallel [(set (match_dup 4) | |
02befdf4 | 2349 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2350 | (match_dup 4))) |
2351 | (use (const_int 1))])) | |
2352 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2353 | (parallel [(set (match_dup 5) | |
02befdf4 | 2354 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
655f2eb9 RH |
2355 | (match_dup 3))) |
2356 | (use (const_int 1))])) | |
2357 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2358 | (parallel [(set (match_dup 0) | |
02befdf4 | 2359 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2360 | (match_dup 4))) |
2361 | (use (const_int 1))])) | |
2362 | ] | |
02befdf4 | 2363 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 | 2364 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2365 | \f |
2366 | ;; :::::::::::::::::::: | |
2367 | ;; :: | |
2368 | ;; :: 64 bit Integer arithmetic | |
2369 | ;; :: | |
2370 | ;; :::::::::::::::::::: | |
2371 | ||
2372 | (define_insn "adddi3" | |
0551c32d RH |
2373 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2374 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2375 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2376 | "" |
2377 | "@ | |
1d5d7a21 RH |
2378 | add %0 = %1, %2 |
2379 | adds %0 = %2, %1 | |
2380 | addl %0 = %2, %1" | |
52e12ad0 | 2381 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2382 | |
2383 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2384 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2385 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2386 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2387 | (const_int 1)))] |
2388 | "" | |
2389 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2390 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2391 | |
5527bf14 RH |
2392 | ;; This has some of the same problems as shladd. We let the shladd |
2393 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2394 | ;; a register, but not more ugliness here. | |
2395 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2396 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2397 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2398 | (const_int 2)) |
2399 | (const_int 1)))] | |
2400 | "" | |
2401 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2402 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2403 | |
c65ebc55 | 2404 | (define_insn "subdi3" |
0551c32d RH |
2405 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2406 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2407 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2408 | "" |
2409 | "sub %0 = %1, %2" | |
52e12ad0 | 2410 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2411 | |
2412 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2413 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2414 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2415 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2416 | "" |
2417 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2418 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2419 | |
cee58bc0 RH |
2420 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2421 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2422 | (define_insn "muldi3" |
0551c32d | 2423 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2424 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2425 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2426 | "" |
aebf2462 | 2427 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2428 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2429 | |
2430 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2431 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2432 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2433 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2434 | ;; here so that it will be present just in case register elimination gives us | |
2435 | ;; the funny result. | |
2436 | ||
2437 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2438 | ||
2439 | ;; ??? Maybe we should change how adds are canonicalized. | |
2440 | ||
655f2eb9 | 2441 | (define_insn "madddi4" |
0551c32d | 2442 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2443 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2444 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2445 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2446 | (clobber (match_scratch:DI 4 "=X"))] |
2447 | "" | |
aebf2462 | 2448 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2449 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2450 | |
2451 | ;; This can be created by register elimination if operand3 of shladd is an | |
2452 | ;; eliminable register or has reg_equiv_constant set. | |
2453 | ||
2454 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2455 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2456 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2457 | ;; incorrectly. |
2458 | ||
655f2eb9 | 2459 | (define_insn "*madddi4_elim" |
c65ebc55 | 2460 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2461 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2462 | (match_operand:DI 2 "register_operand" "f")) | |
2463 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2464 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2465 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2466 | "reload_in_progress" |
2467 | "#" | |
52e12ad0 | 2468 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2469 | |
c65ebc55 JW |
2470 | (define_split |
2471 | [(set (match_operand:DI 0 "register_operand" "") | |
2472 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2473 | (match_operand:DI 2 "register_operand" "")) | |
2474 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2475 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2476 | (clobber (match_scratch:DI 5 ""))] |
2477 | "reload_completed" | |
2478 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2479 | (match_dup 3))) | |
2480 | (clobber (match_dup 0))]) | |
c65ebc55 | 2481 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2482 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2483 | "") | |
2484 | ||
2485 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2486 | ;; to generate them. | |
2487 | ||
2488 | (define_insn "smuldi3_highpart" | |
0551c32d | 2489 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2490 | (truncate:DI |
2491 | (lshiftrt:TI | |
0551c32d RH |
2492 | (mult:TI (sign_extend:TI |
2493 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2494 | (sign_extend:TI | |
2495 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2496 | (const_int 64))))] |
2497 | "" | |
aebf2462 | 2498 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2499 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2500 | |
2501 | (define_insn "umuldi3_highpart" | |
0551c32d | 2502 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2503 | (truncate:DI |
2504 | (lshiftrt:TI | |
0551c32d RH |
2505 | (mult:TI (zero_extend:TI |
2506 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2507 | (zero_extend:TI | |
2508 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2509 | (const_int 64))))] |
2510 | "" | |
aebf2462 | 2511 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2512 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2513 | |
2514 | (define_insn "negdi2" | |
0551c32d RH |
2515 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2516 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2517 | "" |
2518 | "sub %0 = r0, %1" | |
52e12ad0 | 2519 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2520 | |
2521 | (define_expand "absdi2" | |
2522 | [(set (match_dup 2) | |
f2f90c63 | 2523 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2524 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2525 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2526 | (neg:DI (match_dup 1)) |
2527 | (match_dup 1)))] | |
c65ebc55 | 2528 | "" |
1d5d7a21 | 2529 | { operands[2] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2530 | |
2531 | (define_expand "smindi3" | |
2532 | [(set (match_dup 3) | |
f2f90c63 | 2533 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2534 | (match_operand:DI 2 "gr_register_operand" ""))) |
2535 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2536 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2537 | (match_dup 2) (match_dup 1)))] |
2538 | "" | |
1d5d7a21 | 2539 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2540 | |
2541 | (define_expand "smaxdi3" | |
2542 | [(set (match_dup 3) | |
f2f90c63 | 2543 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2544 | (match_operand:DI 2 "gr_register_operand" ""))) |
2545 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2546 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2547 | (match_dup 1) (match_dup 2)))] |
2548 | "" | |
1d5d7a21 | 2549 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2550 | |
2551 | (define_expand "umindi3" | |
2552 | [(set (match_dup 3) | |
f2f90c63 | 2553 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2554 | (match_operand:DI 2 "gr_register_operand" ""))) |
2555 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2556 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2557 | (match_dup 2) (match_dup 1)))] |
2558 | "" | |
1d5d7a21 | 2559 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2560 | |
2561 | (define_expand "umaxdi3" | |
2562 | [(set (match_dup 3) | |
f2f90c63 | 2563 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2564 | (match_operand:DI 2 "gr_register_operand" ""))) |
2565 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2566 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2567 | (match_dup 1) (match_dup 2)))] |
2568 | "" | |
1d5d7a21 | 2569 | { operands[3] = gen_reg_rtx (BImode); }) |
c65ebc55 JW |
2570 | |
2571 | (define_expand "ffsdi2" | |
2572 | [(set (match_dup 6) | |
f2f90c63 | 2573 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2574 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2575 | (set (match_dup 5) (const_int 0)) | |
2576 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
c407570a | 2577 | (set (match_dup 4) (popcount:DI (match_dup 3))) |
0551c32d | 2578 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2579 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2580 | (match_dup 5) (match_dup 4)))] |
2581 | "" | |
c65ebc55 JW |
2582 | { |
2583 | operands[2] = gen_reg_rtx (DImode); | |
2584 | operands[3] = gen_reg_rtx (DImode); | |
2585 | operands[4] = gen_reg_rtx (DImode); | |
2586 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2587 | operands[6] = gen_reg_rtx (BImode); |
1d5d7a21 | 2588 | }) |
c65ebc55 | 2589 | |
c407570a RH |
2590 | (define_expand "ctzdi2" |
2591 | [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "") | |
2592 | (const_int -1))) | |
2593 | (set (match_dup 3) (not:DI (match_dup 1))) | |
2594 | (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3))) | |
2595 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2596 | (popcount:DI (match_dup 4)))] | |
2597 | "" | |
2598 | { | |
2599 | operands[2] = gen_reg_rtx (DImode); | |
2600 | operands[3] = gen_reg_rtx (DImode); | |
2601 | operands[4] = gen_reg_rtx (DImode); | |
2602 | }) | |
2603 | ||
c407570a RH |
2604 | ;; Note the computation here is op0 = 63 - (exp - 0xffff). |
2605 | (define_expand "clzdi2" | |
2606 | [(set (match_dup 2) | |
02befdf4 | 2607 | (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" ""))) |
c407570a RH |
2608 | (set (match_dup 3) |
2609 | (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP)) | |
2610 | (set (match_dup 4) (const_int 65598)) | |
2611 | (set (match_operand:DI 0 "gr_register_operand" "") | |
2612 | (minus:DI (match_dup 4) (match_dup 3)))] | |
02befdf4 | 2613 | "" |
c407570a | 2614 | { |
02befdf4 | 2615 | operands[2] = gen_reg_rtx (XFmode); |
c407570a RH |
2616 | operands[3] = gen_reg_rtx (DImode); |
2617 | operands[4] = gen_reg_rtx (DImode); | |
2618 | }) | |
2619 | ||
2620 | (define_insn "popcountdi2" | |
0551c32d | 2621 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
c407570a | 2622 | (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))] |
c65ebc55 JW |
2623 | "" |
2624 | "popcnt %0 = %1" | |
52e12ad0 | 2625 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2626 | |
02befdf4 | 2627 | (define_insn "*getf_exp_xf" |
c407570a | 2628 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
02befdf4 | 2629 | (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")] |
c407570a | 2630 | UNSPEC_GETF_EXP))] |
02befdf4 | 2631 | "" |
c407570a RH |
2632 | "getf.exp %0 = %1" |
2633 | [(set_attr "itanium_class" "frfr")]) | |
2634 | ||
655f2eb9 RH |
2635 | (define_expand "divdi3" |
2636 | [(set (match_operand:DI 0 "register_operand" "") | |
2637 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2638 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2639 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2640 | { |
02befdf4 | 2641 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2642 | |
02befdf4 | 2643 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2644 | |
2645 | if (CONSTANT_P (operands[1])) | |
2646 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2647 | op1_xf = gen_reg_rtx (XFmode); |
2648 | expand_float (op1_xf, operands[1], 0); | |
655f2eb9 RH |
2649 | |
2650 | if (CONSTANT_P (operands[2])) | |
2651 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2652 | op2_xf = gen_reg_rtx (XFmode); |
2653 | expand_float (op2_xf, operands[2], 0); | |
655f2eb9 | 2654 | |
dcffbade | 2655 | if (TARGET_INLINE_INT_DIV_LAT) |
02befdf4 | 2656 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2657 | else |
02befdf4 | 2658 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2659 | |
02befdf4 | 2660 | emit_insn (gen_fix_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2661 | DONE; |
1d5d7a21 | 2662 | }) |
655f2eb9 RH |
2663 | |
2664 | (define_expand "moddi3" | |
2665 | [(set (match_operand:DI 0 "register_operand" "") | |
2666 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2667 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2668 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2669 | { |
2670 | rtx op2_neg, div; | |
2671 | ||
2672 | div = gen_reg_rtx (DImode); | |
2673 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2674 | ||
2675 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2676 | ||
2677 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2678 | DONE; | |
1d5d7a21 | 2679 | }) |
655f2eb9 RH |
2680 | |
2681 | (define_expand "udivdi3" | |
2682 | [(set (match_operand:DI 0 "register_operand" "") | |
2683 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2684 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2685 | "TARGET_INLINE_INT_DIV" |
655f2eb9 | 2686 | { |
02befdf4 | 2687 | rtx op1_xf, op2_xf, op0_xf; |
655f2eb9 | 2688 | |
02befdf4 | 2689 | op0_xf = gen_reg_rtx (XFmode); |
655f2eb9 RH |
2690 | |
2691 | if (CONSTANT_P (operands[1])) | |
2692 | operands[1] = force_reg (DImode, operands[1]); | |
02befdf4 ZW |
2693 | op1_xf = gen_reg_rtx (XFmode); |
2694 | expand_float (op1_xf, operands[1], 1); | |
655f2eb9 RH |
2695 | |
2696 | if (CONSTANT_P (operands[2])) | |
2697 | operands[2] = force_reg (DImode, operands[2]); | |
02befdf4 ZW |
2698 | op2_xf = gen_reg_rtx (XFmode); |
2699 | expand_float (op2_xf, operands[2], 1); | |
655f2eb9 | 2700 | |
dcffbade | 2701 | if (TARGET_INLINE_INT_DIV_LAT) |
02befdf4 | 2702 | emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2703 | else |
02befdf4 | 2704 | emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf)); |
655f2eb9 | 2705 | |
02befdf4 | 2706 | emit_insn (gen_fixuns_truncxfdi2_alts (operands[0], op0_xf, const1_rtx)); |
655f2eb9 | 2707 | DONE; |
1d5d7a21 | 2708 | }) |
655f2eb9 RH |
2709 | |
2710 | (define_expand "umoddi3" | |
2711 | [(set (match_operand:DI 0 "register_operand" "") | |
2712 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2713 | (match_operand:DI 2 "general_operand" "")))] | |
02befdf4 | 2714 | "TARGET_INLINE_INT_DIV" |
655f2eb9 RH |
2715 | { |
2716 | rtx op2_neg, div; | |
2717 | ||
2718 | div = gen_reg_rtx (DImode); | |
2719 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2720 | ||
2721 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2722 | ||
2723 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2724 | DONE; | |
1d5d7a21 | 2725 | }) |
655f2eb9 RH |
2726 | |
2727 | (define_insn_and_split "divdi3_internal_lat" | |
02befdf4 ZW |
2728 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2729 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2730 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2731 | (clobber (match_scratch:XF 3 "=&f")) | |
2732 | (clobber (match_scratch:XF 4 "=&f")) | |
2733 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 2734 | (clobber (match_scratch:BI 6 "=c"))] |
02befdf4 | 2735 | "TARGET_INLINE_INT_DIV_LAT" |
655f2eb9 RH |
2736 | "#" |
2737 | "&& reload_completed" | |
02befdf4 | 2738 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2739 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] |
2740 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2741 | (use (const_int 1))]) |
2742 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2743 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2744 | (minus:XF (match_dup 7) |
2745 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2746 | (use (const_int 1))])) |
2747 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2748 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
655f2eb9 RH |
2749 | (use (const_int 1))])) |
2750 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 2751 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2752 | (use (const_int 1))])) |
2753 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2754 | (parallel [(set (match_dup 4) | |
02befdf4 | 2755 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
655f2eb9 RH |
2756 | (match_dup 4))) |
2757 | (use (const_int 1))])) | |
2758 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2759 | (parallel [(set (match_dup 0) | |
02befdf4 | 2760 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2761 | (match_dup 0))) |
2762 | (use (const_int 1))])) | |
2763 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2764 | (parallel [(set (match_dup 3) | |
02befdf4 | 2765 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) |
655f2eb9 RH |
2766 | (match_dup 4))) |
2767 | (use (const_int 1))])) | |
2768 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2769 | (parallel [(set (match_dup 0) | |
02befdf4 | 2770 | (plus:XF (mult:XF (match_dup 5) (match_dup 0)) |
655f2eb9 RH |
2771 | (match_dup 0))) |
2772 | (use (const_int 1))])) | |
2773 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2774 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2775 | (minus:XF (match_dup 1) |
2776 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2777 | (use (const_int 1))])) |
2778 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2779 | (parallel [(set (match_dup 0) | |
02befdf4 | 2780 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2781 | (match_dup 3))) |
2782 | (use (const_int 1))])) | |
2783 | ] | |
02befdf4 | 2784 | "operands[7] = CONST1_RTX (XFmode);" |
655f2eb9 RH |
2785 | [(set_attr "predicable" "no")]) |
2786 | ||
2787 | (define_insn_and_split "divdi3_internal_thr" | |
02befdf4 ZW |
2788 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") |
2789 | (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f") | |
2790 | (match_operand:XF 2 "fr_register_operand" "f")))) | |
2791 | (clobber (match_scratch:XF 3 "=&f")) | |
2792 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2793 | (clobber (match_scratch:BI 5 "=c"))] |
02befdf4 | 2794 | "TARGET_INLINE_INT_DIV_THR" |
655f2eb9 RH |
2795 | "#" |
2796 | "&& reload_completed" | |
02befdf4 | 2797 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
2798 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
2799 | UNSPEC_FR_RECIP_APPROX)) | |
655f2eb9 RH |
2800 | (use (const_int 1))]) |
2801 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2802 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
2803 | (minus:XF (match_dup 6) |
2804 | (mult:XF (match_dup 2) (match_dup 0)))) | |
655f2eb9 RH |
2805 | (use (const_int 1))])) |
2806 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2807 | (parallel [(set (match_dup 0) | |
02befdf4 | 2808 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2809 | (match_dup 0))) |
2810 | (use (const_int 1))])) | |
2811 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2812 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
655f2eb9 RH |
2813 | (use (const_int 1))])) |
2814 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2815 | (parallel [(set (match_dup 0) | |
02befdf4 | 2816 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
655f2eb9 RH |
2817 | (match_dup 0))) |
2818 | (use (const_int 1))])) | |
2819 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2820 | (parallel [(set (match_dup 3) (mult:XF (match_dup 0) (match_dup 1))) |
655f2eb9 RH |
2821 | (use (const_int 1))])) |
2822 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2823 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2824 | (minus:XF (match_dup 1) |
2825 | (mult:XF (match_dup 2) (match_dup 3)))) | |
655f2eb9 RH |
2826 | (use (const_int 1))])) |
2827 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2828 | (parallel [(set (match_dup 0) | |
02befdf4 | 2829 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
655f2eb9 RH |
2830 | (match_dup 3))) |
2831 | (use (const_int 1))])) | |
2832 | ] | |
02befdf4 | 2833 | "operands[6] = CONST1_RTX (XFmode);" |
655f2eb9 | 2834 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
2835 | \f |
2836 | ;; :::::::::::::::::::: | |
2837 | ;; :: | |
2838 | ;; :: 32 bit floating point arithmetic | |
2839 | ;; :: | |
2840 | ;; :::::::::::::::::::: | |
2841 | ||
2842 | (define_insn "addsf3" | |
0551c32d RH |
2843 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2844 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2845 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2846 | "" |
aebf2462 | 2847 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2848 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2849 | |
2850 | (define_insn "subsf3" | |
0551c32d RH |
2851 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2852 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2853 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2854 | "" |
aebf2462 | 2855 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2856 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2857 | |
2858 | (define_insn "mulsf3" | |
0551c32d RH |
2859 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2860 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2861 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2862 | "" |
aebf2462 | 2863 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2864 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2865 | |
2866 | (define_insn "abssf2" | |
0551c32d RH |
2867 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2868 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2869 | "" |
aebf2462 | 2870 | "fabs %0 = %1" |
52e12ad0 | 2871 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2872 | |
2873 | (define_insn "negsf2" | |
0551c32d RH |
2874 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2875 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2876 | "" |
aebf2462 | 2877 | "fneg %0 = %1" |
52e12ad0 | 2878 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2879 | |
2880 | (define_insn "*nabssf2" | |
0551c32d RH |
2881 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2882 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2883 | "" |
aebf2462 | 2884 | "fnegabs %0 = %1" |
52e12ad0 | 2885 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2886 | |
2887 | (define_insn "minsf3" | |
0551c32d RH |
2888 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2889 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2890 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2891 | "" |
aebf2462 | 2892 | "fmin %0 = %1, %F2" |
52e12ad0 | 2893 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2894 | |
2895 | (define_insn "maxsf3" | |
0551c32d RH |
2896 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2897 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2898 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2899 | "" |
aebf2462 | 2900 | "fmax %0 = %1, %F2" |
52e12ad0 | 2901 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2902 | |
655f2eb9 | 2903 | (define_insn "*maddsf4" |
0551c32d RH |
2904 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2905 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2906 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2907 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2908 | "" |
aebf2462 | 2909 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2910 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2911 | |
655f2eb9 | 2912 | (define_insn "*msubsf4" |
0551c32d RH |
2913 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2914 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2915 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2916 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2917 | "" |
aebf2462 | 2918 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2919 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2920 | |
2921 | (define_insn "*nmulsf3" | |
0551c32d RH |
2922 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2923 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2924 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2925 | "" |
aebf2462 | 2926 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2927 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2928 | |
655f2eb9 | 2929 | (define_insn "*nmaddsf4" |
0551c32d | 2930 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
2931 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") |
2932 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2933 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2934 | "" |
aebf2462 | 2935 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2936 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2937 | |
52ad4d7b ZW |
2938 | (define_insn "*nmaddsf4_alts" |
2939 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2940 | (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG") | |
2941 | (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2942 | (match_operand:SF 2 "fr_register_operand" "f")))) | |
2943 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2944 | "" | |
2945 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
2946 | [(set_attr "itanium_class" "fmac")]) | |
2947 | ||
26102535 RH |
2948 | (define_expand "divsf3" |
2949 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2950 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2951 | (match_operand:SF 2 "fr_register_operand" "")))] | |
02befdf4 | 2952 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
2953 | { |
2954 | rtx insn; | |
dcffbade | 2955 | if (TARGET_INLINE_FLOAT_DIV_LAT) |
26102535 RH |
2956 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); |
2957 | else | |
2958 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2959 | emit_insn (insn); | |
2960 | DONE; | |
1d5d7a21 | 2961 | }) |
26102535 RH |
2962 | |
2963 | (define_insn_and_split "divsf3_internal_lat" | |
2964 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2965 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2966 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
2967 | (clobber (match_scratch:XF 3 "=&f")) |
2968 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 2969 | (clobber (match_scratch:BI 5 "=c"))] |
02befdf4 | 2970 | "TARGET_INLINE_FLOAT_DIV_LAT" |
26102535 RH |
2971 | "#" |
2972 | "&& reload_completed" | |
02befdf4 | 2973 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
2974 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
2975 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
2976 | (use (const_int 1))]) |
2977 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2978 | (parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6))) |
26102535 RH |
2979 | (use (const_int 1))])) |
2980 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2981 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
2982 | (minus:XF (match_dup 10) |
2983 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
2984 | (use (const_int 1))])) |
2985 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2986 | (parallel [(set (match_dup 3) | |
02befdf4 | 2987 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2988 | (match_dup 3))) |
2989 | (use (const_int 1))])) | |
2990 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2991 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
2992 | (use (const_int 1))])) |
2993 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2994 | (parallel [(set (match_dup 3) | |
02befdf4 | 2995 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
2996 | (match_dup 3))) |
2997 | (use (const_int 1))])) | |
2998 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 2999 | (parallel [(set (match_dup 4) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3000 | (use (const_int 1))])) |
3001 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3002 | (parallel [(set (match_dup 9) | |
3003 | (float_truncate:DF | |
02befdf4 | 3004 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3005 | (match_dup 3)))) |
3006 | (use (const_int 1))])) | |
3007 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3008 | (set (match_dup 0) | |
3009 | (float_truncate:SF (match_dup 6)))) | |
3010 | ] | |
1d5d7a21 | 3011 | { |
02befdf4 ZW |
3012 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3013 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3014 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3015 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); |
02befdf4 | 3016 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3017 | } |
26102535 RH |
3018 | [(set_attr "predicable" "no")]) |
3019 | ||
3020 | (define_insn_and_split "divsf3_internal_thr" | |
3021 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3022 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
3023 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3024 | (clobber (match_scratch:XF 3 "=&f")) |
3025 | (clobber (match_scratch:XF 4 "=f")) | |
f2f90c63 | 3026 | (clobber (match_scratch:BI 5 "=c"))] |
02befdf4 | 3027 | "TARGET_INLINE_FLOAT_DIV_THR" |
26102535 RH |
3028 | "#" |
3029 | "&& reload_completed" | |
02befdf4 | 3030 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3031 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3032 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3033 | (use (const_int 1))]) |
3034 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3035 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3036 | (minus:XF (match_dup 10) |
3037 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3038 | (use (const_int 1))])) |
3039 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3040 | (parallel [(set (match_dup 3) | |
02befdf4 | 3041 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
3042 | (match_dup 3))) |
3043 | (use (const_int 1))])) | |
3044 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3045 | (parallel [(set (match_dup 6) | |
02befdf4 | 3046 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3047 | (match_dup 6))) |
3048 | (use (const_int 1))])) | |
3049 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3050 | (parallel [(set (match_dup 9) | |
3051 | (float_truncate:SF | |
02befdf4 | 3052 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3053 | (use (const_int 1))])) |
3054 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3055 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3056 | (minus:XF (match_dup 7) |
3057 | (mult:XF (match_dup 8) (match_dup 3)))) | |
26102535 RH |
3058 | (use (const_int 1))])) |
3059 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3060 | (set (match_dup 0) | |
3061 | (float_truncate:SF | |
02befdf4 | 3062 | (plus:XF (mult:XF (match_dup 4) (match_dup 6)) |
26102535 RH |
3063 | (match_dup 3))))) |
3064 | ] | |
1d5d7a21 | 3065 | { |
02befdf4 ZW |
3066 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3067 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3068 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3069 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); |
02befdf4 | 3070 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3071 | } |
26102535 | 3072 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3073 | |
3074 | ;; Inline square root. | |
3075 | ||
3076 | (define_insn "*sqrt_approx" | |
3077 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3078 | (div:XF (const_int 1) | |
3079 | (sqrt:XF (match_operand:XF 2 "fr_register_operand" "f")))) | |
3080 | (set (match_operand:BI 1 "register_operand" "=c") | |
3081 | (unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3082 | (use (match_operand:SI 3 "const_int_operand" "")) ] | |
3083 | "" | |
3084 | "frsqrta.s%3 %0, %1 = %2" | |
3085 | [(set_attr "itanium_class" "fmisc") | |
3086 | (set_attr "predicable" "no")]) | |
3087 | ||
9aec7fb4 | 3088 | (define_insn "setf_exp_xf" |
b38ba463 ZW |
3089 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
3090 | (unspec:XF [(match_operand:DI 1 "register_operand" "r")] | |
3091 | UNSPEC_SETF_EXP))] | |
3092 | "" | |
3093 | "setf.exp %0 = %1" | |
3094 | [(set_attr "itanium_class" "frfr")]) | |
3095 | ||
3096 | (define_expand "sqrtsf2" | |
3097 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3098 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
3099 | "TARGET_INLINE_SQRT" | |
3100 | { | |
3101 | rtx insn; | |
3102 | if (TARGET_INLINE_SQRT_LAT) | |
3103 | #if 0 | |
3104 | insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]); | |
3105 | #else | |
3106 | abort (); | |
3107 | #endif | |
3108 | else | |
3109 | insn = gen_sqrtsf2_internal_thr (operands[0], operands[1]); | |
3110 | emit_insn (insn); | |
3111 | DONE; | |
3112 | }) | |
3113 | ||
3114 | ;; Latency-optimized square root. | |
3115 | ;; FIXME: Implement. | |
3116 | ||
3117 | ;; Throughput-optimized square root. | |
3118 | ||
3119 | (define_insn_and_split "sqrtsf2_internal_thr" | |
3120 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
3121 | (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f"))) | |
3122 | ;; Register r2 in optimization guide. | |
3123 | (clobber (match_scratch:DI 2 "=r")) | |
3124 | ;; Register f8 in optimization guide | |
3125 | (clobber (match_scratch:XF 3 "=&f")) | |
3126 | ;; Register f9 in optimization guide | |
3127 | (clobber (match_scratch:XF 4 "=&f")) | |
3128 | ;; Register f10 in optimization guide | |
3129 | (clobber (match_scratch:XF 5 "=&f")) | |
3130 | ;; Register p6 in optimization guide. | |
3131 | (clobber (match_scratch:BI 6 "=c"))] | |
3132 | "TARGET_INLINE_SQRT_THR" | |
3133 | "#" | |
3134 | "&& reload_completed" | |
3135 | [ ;; exponent of +1/2 in r2 | |
3136 | (set (match_dup 2) (const_int 65534)) | |
3137 | ;; +1/2 in f8 | |
3138 | (set (match_dup 3) | |
3139 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3140 | ;; Step 1 | |
3141 | ;; y0 = 1/sqrt(a) in f7 | |
3142 | (parallel [(set (match_dup 7) | |
3143 | (div:XF (const_int 1) | |
3144 | (sqrt:XF (match_dup 8)))) | |
3145 | (set (match_dup 6) | |
3146 | (unspec:BI [(match_dup 8)] | |
3147 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3148 | (use (const_int 0))]) | |
3149 | ;; Step 2 | |
3150 | ;; H0 = 1/2 * y0 in f9 | |
3151 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3152 | (parallel [(set (match_dup 4) | |
3153 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3154 | (match_dup 9))) | |
3155 | (use (const_int 1))])) | |
3156 | ;; Step 3 | |
3157 | ;; S0 = a * y0 in f7 | |
3158 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3159 | (parallel [(set (match_dup 7) | |
3160 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3161 | (match_dup 9))) | |
3162 | (use (const_int 1))])) | |
3163 | ;; Step 4 | |
3164 | ;; d = 1/2 - S0 * H0 in f10 | |
3165 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3166 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
3167 | (minus:XF (match_dup 3) |
3168 | (mult:XF (match_dup 7) (match_dup 4)))) | |
b38ba463 ZW |
3169 | (use (const_int 1))])) |
3170 | ;; Step 5 | |
3171 | ;; d' = d + 1/2 * d in f8 | |
3172 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3173 | (parallel [(set (match_dup 3) | |
3174 | (plus:XF (mult:XF (match_dup 3) (match_dup 5)) | |
3175 | (match_dup 5))) | |
3176 | (use (const_int 1))])) | |
3177 | ;; Step 6 | |
3178 | ;; e = d + d * d' in f8 | |
3179 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3180 | (parallel [(set (match_dup 3) | |
3181 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) | |
3182 | (match_dup 5))) | |
3183 | (use (const_int 1))])) | |
3184 | ;; Step 7 | |
3185 | ;; S1 = S0 + e * S0 in f7 | |
3186 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3187 | (parallel [(set (match_dup 0) | |
3188 | (float_truncate:SF | |
3189 | (plus:XF (mult:XF (match_dup 3) (match_dup 7)) | |
3190 | (match_dup 7)))) | |
3191 | (use (const_int 1))])) | |
3192 | ;; Step 8 | |
3193 | ;; H1 = H0 + e * H0 in f8 | |
3194 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3195 | (parallel [(set (match_dup 3) | |
3196 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
3197 | (match_dup 4))) | |
3198 | (use (const_int 1))])) | |
3199 | ;; Step 9 | |
3200 | ;; d1 = a - S1 * S1 in f9 | |
3201 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3202 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3203 | (minus:XF (match_dup 8) |
3204 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3205 | (use (const_int 1))])) |
3206 | ;; Step 10 | |
3207 | ;; S = S1 + d1 * H1 in f7 | |
3208 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3209 | (parallel [(set (match_dup 0) | |
3210 | (float_truncate:SF | |
3211 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3212 | (match_dup 7)))) | |
3213 | (use (const_int 0))]))] | |
3214 | { | |
3215 | /* Generate 82-bit versions of the input and output operands. */ | |
3216 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3217 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3218 | /* Generate required floating-point constants. */ | |
3219 | operands[9] = CONST0_RTX (XFmode); | |
3220 | } | |
3221 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
3222 | \f |
3223 | ;; :::::::::::::::::::: | |
3224 | ;; :: | |
3225 | ;; :: 64 bit floating point arithmetic | |
3226 | ;; :: | |
3227 | ;; :::::::::::::::::::: | |
3228 | ||
3229 | (define_insn "adddf3" | |
0551c32d RH |
3230 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3231 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3232 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3233 | "" |
aebf2462 | 3234 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 3235 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3236 | |
26102535 RH |
3237 | (define_insn "*adddf3_trunc" |
3238 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3239 | (float_truncate:SF | |
3240 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
3241 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3242 | "" | |
aebf2462 | 3243 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 3244 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3245 | |
c65ebc55 | 3246 | (define_insn "subdf3" |
0551c32d RH |
3247 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3248 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3249 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3250 | "" |
aebf2462 | 3251 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3252 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3253 | |
26102535 RH |
3254 | (define_insn "*subdf3_trunc" |
3255 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3256 | (float_truncate:SF | |
3257 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
3258 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
3259 | "" | |
aebf2462 | 3260 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3261 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3262 | |
c65ebc55 | 3263 | (define_insn "muldf3" |
0551c32d RH |
3264 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3265 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3266 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 3267 | "" |
aebf2462 | 3268 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 3269 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3270 | |
26102535 RH |
3271 | (define_insn "*muldf3_trunc" |
3272 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3273 | (float_truncate:SF | |
3274 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3275 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
3276 | "" | |
aebf2462 | 3277 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 3278 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3279 | |
c65ebc55 | 3280 | (define_insn "absdf2" |
0551c32d RH |
3281 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3282 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3283 | "" |
aebf2462 | 3284 | "fabs %0 = %1" |
52e12ad0 | 3285 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3286 | |
3287 | (define_insn "negdf2" | |
0551c32d RH |
3288 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3289 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 3290 | "" |
aebf2462 | 3291 | "fneg %0 = %1" |
52e12ad0 | 3292 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3293 | |
3294 | (define_insn "*nabsdf2" | |
0551c32d RH |
3295 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3296 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 3297 | "" |
aebf2462 | 3298 | "fnegabs %0 = %1" |
52e12ad0 | 3299 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3300 | |
3301 | (define_insn "mindf3" | |
0551c32d RH |
3302 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3303 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3304 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3305 | "" |
aebf2462 | 3306 | "fmin %0 = %1, %F2" |
52e12ad0 | 3307 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
3308 | |
3309 | (define_insn "maxdf3" | |
0551c32d RH |
3310 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3311 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3312 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3313 | "" |
aebf2462 | 3314 | "fmax %0 = %1, %F2" |
52e12ad0 | 3315 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 3316 | |
655f2eb9 | 3317 | (define_insn "*madddf4" |
0551c32d RH |
3318 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3319 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3320 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3321 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3322 | "" |
aebf2462 | 3323 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 3324 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3325 | |
26102535 RH |
3326 | (define_insn "*madddf4_trunc" |
3327 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3328 | (float_truncate:SF | |
3329 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3330 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3331 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3332 | "" | |
aebf2462 | 3333 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 3334 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3335 | |
655f2eb9 | 3336 | (define_insn "*msubdf4" |
0551c32d RH |
3337 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3338 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3339 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3340 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 3341 | "" |
aebf2462 | 3342 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 3343 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3344 | |
26102535 RH |
3345 | (define_insn "*msubdf4_trunc" |
3346 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3347 | (float_truncate:SF | |
3348 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3349 | (match_operand:DF 2 "fr_register_operand" "f")) | |
3350 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
3351 | "" | |
aebf2462 | 3352 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 3353 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3354 | |
c65ebc55 | 3355 | (define_insn "*nmuldf3" |
0551c32d RH |
3356 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3357 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3358 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3359 | "" |
aebf2462 | 3360 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 3361 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3362 | |
26102535 RH |
3363 | (define_insn "*nmuldf3_trunc" |
3364 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3365 | (float_truncate:SF | |
3366 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3367 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
3368 | "" | |
aebf2462 | 3369 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 3370 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3371 | |
655f2eb9 | 3372 | (define_insn "*nmadddf4" |
0551c32d | 3373 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
52ad4d7b ZW |
3374 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3375 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3376 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 3377 | "" |
aebf2462 | 3378 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 3379 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3380 | |
3381 | (define_insn "*nmadddf4_alts" | |
3382 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3383 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3384 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3385 | (match_operand:DF 2 "fr_register_operand" "f")))) | |
26102535 RH |
3386 | (use (match_operand:SI 4 "const_int_operand" ""))] |
3387 | "" | |
aebf2462 | 3388 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 3389 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3390 | |
52ad4d7b | 3391 | (define_insn "*nmadddf4_truncsf" |
26102535 RH |
3392 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3393 | (float_truncate:SF | |
52ad4d7b ZW |
3394 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") |
3395 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3396 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
26102535 | 3397 | "" |
aebf2462 | 3398 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 3399 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3400 | |
52ad4d7b ZW |
3401 | (define_insn "*nmadddf4_truncsf_alts" |
3402 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3403 | (float_truncate:SF | |
3404 | (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG") | |
3405 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3406 | (match_operand:DF 2 "fr_register_operand" "f"))))) | |
3407 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3408 | "" | |
3409 | "fnma.s.s%4 %0 = %1, %2, %F3" | |
3410 | [(set_attr "itanium_class" "fmac")]) | |
3411 | ||
26102535 RH |
3412 | (define_expand "divdf3" |
3413 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
3414 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
3415 | (match_operand:DF 2 "fr_register_operand" "")))] | |
02befdf4 | 3416 | "TARGET_INLINE_FLOAT_DIV" |
26102535 RH |
3417 | { |
3418 | rtx insn; | |
dcffbade | 3419 | if (TARGET_INLINE_FLOAT_DIV_LAT) |
26102535 RH |
3420 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); |
3421 | else | |
3422 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
3423 | emit_insn (insn); | |
3424 | DONE; | |
1d5d7a21 | 3425 | }) |
26102535 RH |
3426 | |
3427 | (define_insn_and_split "divdf3_internal_lat" | |
3428 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3429 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3430 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 ZW |
3431 | (clobber (match_scratch:XF 3 "=&f")) |
3432 | (clobber (match_scratch:XF 4 "=&f")) | |
3433 | (clobber (match_scratch:XF 5 "=&f")) | |
f2f90c63 | 3434 | (clobber (match_scratch:BI 6 "=c"))] |
02befdf4 | 3435 | "TARGET_INLINE_FLOAT_DIV_LAT" |
26102535 RH |
3436 | "#" |
3437 | "&& reload_completed" | |
02befdf4 | 3438 | [(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9))) |
086c0f96 RH |
3439 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] |
3440 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3441 | (use (const_int 1))]) |
3442 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3443 | (parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7))) |
26102535 RH |
3444 | (use (const_int 1))])) |
3445 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3446 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3447 | (minus:XF (match_dup 12) |
3448 | (mult:XF (match_dup 9) (match_dup 7)))) | |
26102535 RH |
3449 | (use (const_int 1))])) |
3450 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3451 | (parallel [(set (match_dup 3) | |
02befdf4 | 3452 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3453 | (match_dup 3))) |
3454 | (use (const_int 1))])) | |
3455 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3456 | (parallel [(set (match_dup 5) (mult:XF (match_dup 4) (match_dup 4))) |
26102535 RH |
3457 | (use (const_int 1))])) |
3458 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3459 | (parallel [(set (match_dup 7) | |
02befdf4 | 3460 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3461 | (match_dup 7))) |
3462 | (use (const_int 1))])) | |
3463 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3464 | (parallel [(set (match_dup 3) | |
02befdf4 | 3465 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
3466 | (match_dup 3))) |
3467 | (use (const_int 1))])) | |
3468 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
02befdf4 | 3469 | (parallel [(set (match_dup 4) (mult:XF (match_dup 5) (match_dup 5))) |
26102535 RH |
3470 | (use (const_int 1))])) |
3471 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3472 | (parallel [(set (match_dup 7) | |
02befdf4 | 3473 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3474 | (match_dup 7))) |
3475 | (use (const_int 1))])) | |
3476 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3477 | (parallel [(set (match_dup 10) | |
3478 | (float_truncate:DF | |
02befdf4 | 3479 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) |
26102535 RH |
3480 | (match_dup 3)))) |
3481 | (use (const_int 1))])) | |
3482 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3483 | (parallel [(set (match_dup 7) | |
02befdf4 | 3484 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) |
26102535 RH |
3485 | (match_dup 7))) |
3486 | (use (const_int 1))])) | |
3487 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3488 | (parallel [(set (match_dup 11) | |
3489 | (float_truncate:DF | |
52ad4d7b ZW |
3490 | (minus:XF (match_dup 8) |
3491 | (mult:XF (match_dup 9) (match_dup 3))))) | |
26102535 RH |
3492 | (use (const_int 1))])) |
3493 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3494 | (set (match_dup 0) | |
02befdf4 | 3495 | (float_truncate:DF (plus:XF (mult:XF (match_dup 5) (match_dup 7)) |
26102535 RH |
3496 | (match_dup 3))))) |
3497 | ] | |
1d5d7a21 | 3498 | { |
02befdf4 ZW |
3499 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3500 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3501 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 RH |
3502 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
3503 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
02befdf4 | 3504 | operands[12] = CONST1_RTX (XFmode); |
1d5d7a21 | 3505 | } |
26102535 RH |
3506 | [(set_attr "predicable" "no")]) |
3507 | ||
3508 | (define_insn_and_split "divdf3_internal_thr" | |
3509 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3510 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
3511 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
02befdf4 | 3512 | (clobber (match_scratch:XF 3 "=&f")) |
26102535 | 3513 | (clobber (match_scratch:DF 4 "=f")) |
f2f90c63 | 3514 | (clobber (match_scratch:BI 5 "=c"))] |
02befdf4 | 3515 | "TARGET_INLINE_FLOAT_DIV_THR" |
26102535 RH |
3516 | "#" |
3517 | "&& reload_completed" | |
02befdf4 | 3518 | [(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8))) |
086c0f96 RH |
3519 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] |
3520 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
3521 | (use (const_int 1))]) |
3522 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3523 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
3524 | (minus:XF (match_dup 10) |
3525 | (mult:XF (match_dup 8) (match_dup 6)))) | |
26102535 RH |
3526 | (use (const_int 1))])) |
3527 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3528 | (parallel [(set (match_dup 6) | |
02befdf4 | 3529 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3530 | (match_dup 6))) |
3531 | (use (const_int 1))])) | |
3532 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3533 | (parallel [(set (match_dup 3) | |
02befdf4 | 3534 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3535 | (use (const_int 1))])) |
3536 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3537 | (parallel [(set (match_dup 6) | |
02befdf4 | 3538 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3539 | (match_dup 6))) |
3540 | (use (const_int 1))])) | |
3541 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3542 | (parallel [(set (match_dup 3) | |
02befdf4 | 3543 | (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
3544 | (use (const_int 1))])) |
3545 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3546 | (parallel [(set (match_dup 6) | |
02befdf4 | 3547 | (plus:XF (mult:XF (match_dup 3) (match_dup 6)) |
26102535 RH |
3548 | (match_dup 6))) |
3549 | (use (const_int 1))])) | |
3550 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3551 | (parallel [(set (match_dup 9) | |
3552 | (float_truncate:DF | |
aa42f99d | 3553 | (mult:XF (match_dup 7) (match_dup 6)))) |
26102535 RH |
3554 | (use (const_int 1))])) |
3555 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3556 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3557 | (minus:DF (match_dup 1) |
3558 | (mult:DF (match_dup 2) (match_dup 9)))) | |
26102535 RH |
3559 | (use (const_int 1))])) |
3560 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3561 | (set (match_dup 0) | |
3562 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3563 | (match_dup 9)))) | |
3564 | ] | |
1d5d7a21 | 3565 | { |
02befdf4 ZW |
3566 | operands[6] = gen_rtx_REG (XFmode, REGNO (operands[0])); |
3567 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3568 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[2])); | |
1d5d7a21 | 3569 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); |
02befdf4 | 3570 | operands[10] = CONST1_RTX (XFmode); |
1d5d7a21 | 3571 | } |
26102535 | 3572 | [(set_attr "predicable" "no")]) |
b38ba463 ZW |
3573 | |
3574 | ;; Inline square root. | |
3575 | ||
3576 | (define_expand "sqrtdf2" | |
3577 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3578 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
3579 | "TARGET_INLINE_SQRT" | |
3580 | { | |
3581 | rtx insn; | |
3582 | if (TARGET_INLINE_SQRT_LAT) | |
3583 | #if 0 | |
3584 | insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]); | |
3585 | #else | |
3586 | abort (); | |
3587 | #endif | |
3588 | else | |
3589 | insn = gen_sqrtdf2_internal_thr (operands[0], operands[1]); | |
3590 | emit_insn (insn); | |
3591 | DONE; | |
3592 | }) | |
3593 | ||
3594 | ;; Latency-optimized square root. | |
3595 | ;; FIXME: Implement. | |
3596 | ||
3597 | ;; Throughput-optimized square root. | |
3598 | ||
3599 | (define_insn_and_split "sqrtdf2_internal_thr" | |
3600 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
3601 | (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f"))) | |
3602 | ;; Register r2 in optimization guide. | |
3603 | (clobber (match_scratch:DI 2 "=r")) | |
3604 | ;; Register f8 in optimization guide | |
3605 | (clobber (match_scratch:XF 3 "=&f")) | |
3606 | ;; Register f9 in optimization guide | |
3607 | (clobber (match_scratch:XF 4 "=&f")) | |
3608 | ;; Register f10 in optimization guide | |
3609 | (clobber (match_scratch:XF 5 "=&f")) | |
3610 | ;; Register p6 in optimization guide. | |
3611 | (clobber (match_scratch:BI 6 "=c"))] | |
3612 | "TARGET_INLINE_SQRT_THR" | |
3613 | "#" | |
3614 | "&& reload_completed" | |
3615 | [ ;; exponent of +1/2 in r2 | |
3616 | (set (match_dup 2) (const_int 65534)) | |
3617 | ;; +1/2 in f10 | |
3618 | (set (match_dup 5) | |
3619 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
3620 | ;; Step 1 | |
3621 | ;; y0 = 1/sqrt(a) in f7 | |
3622 | (parallel [(set (match_dup 7) | |
3623 | (div:XF (const_int 1) | |
3624 | (sqrt:XF (match_dup 8)))) | |
3625 | (set (match_dup 6) | |
3626 | (unspec:BI [(match_dup 8)] | |
3627 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
3628 | (use (const_int 0))]) | |
3629 | ;; Step 2 | |
3630 | ;; H0 = 1/2 * y0 in f8 | |
3631 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3632 | (parallel [(set (match_dup 3) | |
3633 | (plus:XF (mult:XF (match_dup 5) (match_dup 7)) | |
3634 | (match_dup 9))) | |
3635 | (use (const_int 1))])) | |
3636 | ;; Step 3 | |
3637 | ;; G0 = a * y0 in f7 | |
3638 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3639 | (parallel [(set (match_dup 7) | |
3640 | (plus:XF (mult:XF (match_dup 8) (match_dup 7)) | |
3641 | (match_dup 9))) | |
3642 | (use (const_int 1))])) | |
3643 | ;; Step 4 | |
3644 | ;; r0 = 1/2 - G0 * H0 in f9 | |
3645 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3646 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3647 | (minus:XF (match_dup 5) |
3648 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3649 | (use (const_int 1))])) |
3650 | ;; Step 5 | |
3651 | ;; H1 = H0 + r0 * H0 in f8 | |
3652 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3653 | (parallel [(set (match_dup 3) | |
3654 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3655 | (match_dup 3))) | |
3656 | (use (const_int 1))])) | |
3657 | ;; Step 6 | |
3658 | ;; G1 = G0 + r0 * G0 in f7 | |
3659 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3660 | (parallel [(set (match_dup 7) | |
3661 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3662 | (match_dup 7))) | |
3663 | (use (const_int 1))])) | |
3664 | ;; Step 7 | |
3665 | ;; r1 = 1/2 - G1 * H1 in f9 | |
3666 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3667 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3668 | (minus:XF (match_dup 5) |
3669 | (mult:XF (match_dup 7) (match_dup 3)))) | |
b38ba463 ZW |
3670 | (use (const_int 1))])) |
3671 | ;; Step 8 | |
3672 | ;; H2 = H1 + r1 * H1 in f8 | |
3673 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3674 | (parallel [(set (match_dup 3) | |
3675 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3676 | (match_dup 3))) | |
3677 | (use (const_int 1))])) | |
3678 | ;; Step 9 | |
3679 | ;; G2 = G1 + r1 * G1 in f7 | |
3680 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3681 | (parallel [(set (match_dup 7) | |
3682 | (plus:XF (mult:XF (match_dup 4) (match_dup 7)) | |
3683 | (match_dup 7))) | |
3684 | (use (const_int 1))])) | |
3685 | ;; Step 10 | |
3686 | ;; d2 = a - G2 * G2 in f9 | |
3687 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3688 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3689 | (minus:XF (match_dup 8) |
3690 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3691 | (use (const_int 1))])) |
3692 | ;; Step 11 | |
3693 | ;; G3 = G2 + d2 * H2 in f7 | |
3694 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3695 | (parallel [(set (match_dup 7) | |
3696 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3697 | (match_dup 7))) | |
3698 | (use (const_int 1))])) | |
3699 | ;; Step 12 | |
3700 | ;; d3 = a - G3 * G3 in f9 | |
3701 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3702 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
3703 | (minus:XF (match_dup 8) |
3704 | (mult:XF (match_dup 7) (match_dup 7)))) | |
b38ba463 ZW |
3705 | (use (const_int 1))])) |
3706 | ;; Step 13 | |
3707 | ;; S = G3 + d3 * H2 in f7 | |
3708 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
3709 | (parallel [(set (match_dup 0) | |
3710 | (float_truncate:DF | |
3711 | (plus:XF (mult:XF (match_dup 4) (match_dup 3)) | |
3712 | (match_dup 7)))) | |
3713 | (use (const_int 0))]))] | |
3714 | { | |
3715 | /* Generate 82-bit versions of the input and output operands. */ | |
3716 | operands[7] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
3717 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
3718 | /* Generate required floating-point constants. */ | |
3719 | operands[9] = CONST0_RTX (XFmode); | |
3720 | } | |
3721 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3722 | \f |
3723 | ;; :::::::::::::::::::: | |
3724 | ;; :: | |
3725 | ;; :: 80 bit floating point arithmetic | |
3726 | ;; :: | |
3727 | ;; :::::::::::::::::::: | |
3728 | ||
02befdf4 ZW |
3729 | (define_insn "addxf3" |
3730 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3731 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3732 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3733 | "" | |
aebf2462 | 3734 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3735 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3736 | |
02befdf4 | 3737 | (define_insn "*addxf3_truncsf" |
26102535 RH |
3738 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3739 | (float_truncate:SF | |
02befdf4 ZW |
3740 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3741 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3742 | "" | |
aebf2462 | 3743 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3744 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3745 | |
02befdf4 | 3746 | (define_insn "*addxf3_truncdf" |
26102535 RH |
3747 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3748 | (float_truncate:DF | |
02befdf4 ZW |
3749 | (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3750 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3751 | "" | |
aebf2462 | 3752 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3753 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3754 | |
02befdf4 ZW |
3755 | (define_insn "subxf3" |
3756 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3757 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3758 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3759 | "" | |
aebf2462 | 3760 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3761 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3762 | |
02befdf4 | 3763 | (define_insn "*subxf3_truncsf" |
26102535 RH |
3764 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3765 | (float_truncate:SF | |
02befdf4 ZW |
3766 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3767 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3768 | "" | |
aebf2462 | 3769 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3770 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3771 | |
02befdf4 | 3772 | (define_insn "*subxf3_truncdf" |
26102535 RH |
3773 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3774 | (float_truncate:DF | |
02befdf4 ZW |
3775 | (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3776 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3777 | "" | |
aebf2462 | 3778 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3779 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3780 | |
02befdf4 ZW |
3781 | (define_insn "mulxf3" |
3782 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3783 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3784 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3785 | "" | |
aebf2462 | 3786 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3787 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3788 | |
02befdf4 | 3789 | (define_insn "*mulxf3_truncsf" |
26102535 RH |
3790 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3791 | (float_truncate:SF | |
02befdf4 ZW |
3792 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3793 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3794 | "" | |
aebf2462 | 3795 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3796 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3797 | |
02befdf4 | 3798 | (define_insn "*mulxf3_truncdf" |
26102535 RH |
3799 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3800 | (float_truncate:DF | |
02befdf4 ZW |
3801 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3802 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3803 | "" | |
aebf2462 | 3804 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3805 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3806 | |
02befdf4 ZW |
3807 | (define_insn "*mulxf3_alts" |
3808 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3809 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3810 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3811 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3812 | "" |
aebf2462 | 3813 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3814 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3815 | |
02befdf4 | 3816 | (define_insn "*mulxf3_truncsf_alts" |
26102535 RH |
3817 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3818 | (float_truncate:SF | |
02befdf4 ZW |
3819 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3820 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3821 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3822 | "" |
aebf2462 | 3823 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3824 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3825 | |
02befdf4 | 3826 | (define_insn "*mulxf3_truncdf_alts" |
26102535 RH |
3827 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3828 | (float_truncate:DF | |
02befdf4 ZW |
3829 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3830 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3831 | (use (match_operand:SI 3 "const_int_operand" ""))] |
02befdf4 | 3832 | "" |
aebf2462 | 3833 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3834 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3835 | |
02befdf4 ZW |
3836 | (define_insn "absxf2" |
3837 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3838 | (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3839 | "" | |
aebf2462 | 3840 | "fabs %0 = %F1" |
52e12ad0 | 3841 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3842 | |
02befdf4 ZW |
3843 | (define_insn "negxf2" |
3844 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3845 | (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))] | |
3846 | "" | |
aebf2462 | 3847 | "fneg %0 = %F1" |
52e12ad0 | 3848 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3849 | |
02befdf4 ZW |
3850 | (define_insn "*nabsxf2" |
3851 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3852 | (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))] | |
3853 | "" | |
aebf2462 | 3854 | "fnegabs %0 = %F1" |
52e12ad0 | 3855 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3856 | |
02befdf4 ZW |
3857 | (define_insn "minxf3" |
3858 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3859 | (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3860 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3861 | "" | |
aebf2462 | 3862 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3863 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3864 | |
02befdf4 ZW |
3865 | (define_insn "maxxf3" |
3866 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3867 | (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3868 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))] | |
3869 | "" | |
aebf2462 | 3870 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3871 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3872 | |
02befdf4 ZW |
3873 | (define_insn "*maddxf4" |
3874 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3875 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3876 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3877 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3878 | "" | |
aebf2462 | 3879 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3880 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3881 | |
02befdf4 | 3882 | (define_insn "*maddxf4_truncsf" |
26102535 RH |
3883 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3884 | (float_truncate:SF | |
02befdf4 ZW |
3885 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3886 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3887 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3888 | "" | |
aebf2462 | 3889 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3890 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3891 | |
02befdf4 | 3892 | (define_insn "*maddxf4_truncdf" |
26102535 RH |
3893 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3894 | (float_truncate:DF | |
02befdf4 ZW |
3895 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3896 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3897 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3898 | "" | |
aebf2462 | 3899 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3900 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3901 | |
02befdf4 ZW |
3902 | (define_insn "*maddxf4_alts" |
3903 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3904 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3905 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3906 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))) | |
655f2eb9 | 3907 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3908 | "" |
aebf2462 | 3909 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3910 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3911 | |
b38ba463 ZW |
3912 | (define_insn "*maddxf4_alts_truncsf" |
3913 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3914 | (float_truncate:SF | |
3915 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3916 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3917 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
3918 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
3919 | "" | |
3920 | "fma.s.s%4 %0 = %F1, %F2, %F3" | |
3921 | [(set_attr "itanium_class" "fmac")]) | |
3922 | ||
02befdf4 | 3923 | (define_insn "*maddxf4_alts_truncdf" |
26102535 RH |
3924 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3925 | (float_truncate:DF | |
02befdf4 ZW |
3926 | (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3927 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3928 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))) | |
26102535 | 3929 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 3930 | "" |
aebf2462 | 3931 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3932 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3933 | |
02befdf4 ZW |
3934 | (define_insn "*msubxf4" |
3935 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3936 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3937 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3938 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))] | |
3939 | "" | |
aebf2462 | 3940 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3941 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3942 | |
02befdf4 | 3943 | (define_insn "*msubxf4_truncsf" |
26102535 RH |
3944 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3945 | (float_truncate:SF | |
02befdf4 ZW |
3946 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3947 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3948 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3949 | "" | |
aebf2462 | 3950 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3951 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3952 | |
02befdf4 | 3953 | (define_insn "*msubxf4_truncdf" |
26102535 RH |
3954 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3955 | (float_truncate:DF | |
02befdf4 ZW |
3956 | (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |
3957 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")) | |
3958 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))] | |
3959 | "" | |
aebf2462 | 3960 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3961 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3962 | |
02befdf4 ZW |
3963 | (define_insn "*nmulxf3" |
3964 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
3965 | (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3966 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))] | |
3967 | "" | |
aebf2462 | 3968 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3969 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3970 | |
02befdf4 | 3971 | (define_insn "*nmulxf3_truncsf" |
26102535 RH |
3972 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
3973 | (float_truncate:SF | |
02befdf4 ZW |
3974 | (neg:XF (mult:XF |
3975 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3976 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3977 | "" | |
aebf2462 | 3978 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3979 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3980 | |
02befdf4 | 3981 | (define_insn "*nmulxf3_truncdf" |
26102535 RH |
3982 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
3983 | (float_truncate:DF | |
02befdf4 ZW |
3984 | (neg:XF (mult:XF |
3985 | (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3986 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))] | |
3987 | "" | |
aebf2462 | 3988 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3989 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3990 | |
02befdf4 ZW |
3991 | (define_insn "*nmaddxf4" |
3992 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
3993 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
3994 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
3995 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
3996 | )))] | |
02befdf4 | 3997 | "" |
aebf2462 | 3998 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3999 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4000 | |
02befdf4 | 4001 | (define_insn "*nmaddxf4_truncsf" |
26102535 RH |
4002 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
4003 | (float_truncate:SF | |
52ad4d7b ZW |
4004 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4005 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4006 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4007 | ))))] | |
02befdf4 | 4008 | "" |
aebf2462 | 4009 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 4010 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4011 | |
02befdf4 | 4012 | (define_insn "*nmaddxf4_truncdf" |
26102535 RH |
4013 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4014 | (float_truncate:DF | |
52ad4d7b ZW |
4015 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4016 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4017 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4018 | ))))] | |
02befdf4 | 4019 | "" |
aebf2462 | 4020 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 4021 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4022 | |
02befdf4 ZW |
4023 | (define_insn "*nmaddxf4_alts" |
4024 | [(set (match_operand:XF 0 "fr_register_operand" "=f") | |
52ad4d7b ZW |
4025 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4026 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4027 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4028 | ))) | |
655f2eb9 | 4029 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4030 | "" |
aebf2462 | 4031 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4032 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 4033 | |
52ad4d7b ZW |
4034 | (define_insn "*nmaddxf4_truncsf_alts" |
4035 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
4036 | (float_truncate:SF | |
4037 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") | |
4038 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4039 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4040 | )))) | |
4041 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
4042 | "" | |
4043 | "fnma.s.s%4 %0 = %F1, %F2, %F3" | |
4044 | [(set_attr "itanium_class" "fmac")]) | |
4045 | ||
02befdf4 | 4046 | (define_insn "*nmaddxf4_truncdf_alts" |
26102535 RH |
4047 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
4048 | (float_truncate:DF | |
52ad4d7b ZW |
4049 | (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG") |
4050 | (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") | |
4051 | (match_operand:XF 2 "xfreg_or_fp01_operand" "fG") | |
4052 | )))) | |
26102535 | 4053 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4054 | "" |
aebf2462 | 4055 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 4056 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 4057 | |
02befdf4 ZW |
4058 | (define_expand "divxf3" |
4059 | [(set (match_operand:XF 0 "fr_register_operand" "") | |
4060 | (div:XF (match_operand:XF 1 "fr_register_operand" "") | |
4061 | (match_operand:XF 2 "fr_register_operand" "")))] | |
4062 | "TARGET_INLINE_FLOAT_DIV" | |
26102535 RH |
4063 | { |
4064 | rtx insn; | |
dcffbade | 4065 | if (TARGET_INLINE_FLOAT_DIV_LAT) |
02befdf4 | 4066 | insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]); |
26102535 | 4067 | else |
02befdf4 | 4068 | insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]); |
26102535 RH |
4069 | emit_insn (insn); |
4070 | DONE; | |
1d5d7a21 | 4071 | }) |
26102535 | 4072 | |
02befdf4 ZW |
4073 | (define_insn_and_split "divxf3_internal_lat" |
4074 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4075 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4076 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4077 | (clobber (match_scratch:XF 3 "=&f")) | |
4078 | (clobber (match_scratch:XF 4 "=&f")) | |
4079 | (clobber (match_scratch:XF 5 "=&f")) | |
4080 | (clobber (match_scratch:XF 6 "=&f")) | |
f2f90c63 | 4081 | (clobber (match_scratch:BI 7 "=c"))] |
02befdf4 | 4082 | "TARGET_INLINE_FLOAT_DIV_LAT" |
26102535 RH |
4083 | "#" |
4084 | "&& reload_completed" | |
02befdf4 | 4085 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4086 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] |
4087 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
4088 | (use (const_int 1))]) |
4089 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4090 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4091 | (minus:XF (match_dup 8) |
4092 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4093 | (use (const_int 1))])) |
4094 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4095 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4096 | (use (const_int 1))])) |
4097 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
02befdf4 | 4098 | (parallel [(set (match_dup 5) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4099 | (use (const_int 1))])) |
4100 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4101 | (parallel [(set (match_dup 6) | |
02befdf4 | 4102 | (plus:XF (mult:XF (match_dup 3) (match_dup 3)) |
26102535 RH |
4103 | (match_dup 3))) |
4104 | (use (const_int 1))])) | |
4105 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4106 | (parallel [(set (match_dup 3) | |
02befdf4 | 4107 | (plus:XF (mult:XF (match_dup 5) (match_dup 5)) |
26102535 RH |
4108 | (match_dup 3))) |
4109 | (use (const_int 1))])) | |
4110 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4111 | (parallel [(set (match_dup 5) | |
02befdf4 | 4112 | (plus:XF (mult:XF (match_dup 6) (match_dup 0)) |
26102535 RH |
4113 | (match_dup 0))) |
4114 | (use (const_int 1))])) | |
4115 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4116 | (parallel [(set (match_dup 0) | |
02befdf4 | 4117 | (plus:XF (mult:XF (match_dup 5) (match_dup 3)) |
26102535 RH |
4118 | (match_dup 0))) |
4119 | (use (const_int 1))])) | |
4120 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4121 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4122 | (minus:XF (match_dup 1) |
4123 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4124 | (use (const_int 1))])) |
4125 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4126 | (parallel [(set (match_dup 3) | |
02befdf4 | 4127 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4128 | (match_dup 4))) |
4129 | (use (const_int 1))])) | |
4130 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4131 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4132 | (minus:XF (match_dup 8) |
4133 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4134 | (use (const_int 1))])) |
4135 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4136 | (parallel [(set (match_dup 0) | |
02befdf4 | 4137 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4138 | (match_dup 0))) |
4139 | (use (const_int 1))])) | |
4140 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4141 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4142 | (minus:XF (match_dup 1) |
4143 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4144 | (use (const_int 1))])) |
4145 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4146 | (set (match_dup 0) | |
02befdf4 | 4147 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4148 | (match_dup 3)))) |
4149 | ] | |
02befdf4 | 4150 | "operands[8] = CONST1_RTX (XFmode);" |
26102535 RH |
4151 | [(set_attr "predicable" "no")]) |
4152 | ||
02befdf4 ZW |
4153 | (define_insn_and_split "divxf3_internal_thr" |
4154 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4155 | (div:XF (match_operand:XF 1 "fr_register_operand" "f") | |
4156 | (match_operand:XF 2 "fr_register_operand" "f"))) | |
4157 | (clobber (match_scratch:XF 3 "=&f")) | |
4158 | (clobber (match_scratch:XF 4 "=&f")) | |
f2f90c63 | 4159 | (clobber (match_scratch:BI 5 "=c"))] |
02befdf4 | 4160 | "TARGET_INLINE_FLOAT_DIV_THR" |
26102535 RH |
4161 | "#" |
4162 | "&& reload_completed" | |
02befdf4 | 4163 | [(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2))) |
086c0f96 RH |
4164 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] |
4165 | UNSPEC_FR_RECIP_APPROX)) | |
26102535 RH |
4166 | (use (const_int 1))]) |
4167 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4168 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4169 | (minus:XF (match_dup 6) |
4170 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4171 | (use (const_int 1))])) |
4172 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4173 | (parallel [(set (match_dup 4) | |
02befdf4 | 4174 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4175 | (match_dup 0))) |
4176 | (use (const_int 1))])) | |
4177 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4178 | (parallel [(set (match_dup 3) (mult:XF (match_dup 3) (match_dup 3))) |
26102535 RH |
4179 | (use (const_int 1))])) |
4180 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4181 | (parallel [(set (match_dup 3) | |
02befdf4 | 4182 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) |
26102535 RH |
4183 | (match_dup 4))) |
4184 | (use (const_int 1))])) | |
4185 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
02befdf4 | 4186 | (parallel [(set (match_dup 4) (mult:XF (match_dup 1) (match_dup 0))) |
26102535 RH |
4187 | (use (const_int 1))])) |
4188 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4189 | (parallel [(set (match_dup 0) | |
52ad4d7b ZW |
4190 | (minus:XF (match_dup 6) |
4191 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4192 | (use (const_int 1))])) |
4193 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4194 | (parallel [(set (match_dup 0) | |
02befdf4 | 4195 | (plus:XF (mult:XF (match_dup 0) (match_dup 3)) |
26102535 RH |
4196 | (match_dup 3))) |
4197 | (use (const_int 1))])) | |
4198 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4199 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4200 | (minus:XF (match_dup 1) |
4201 | (mult:XF (match_dup 2) (match_dup 4)))) | |
26102535 RH |
4202 | (use (const_int 1))])) |
4203 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4204 | (parallel [(set (match_dup 3) | |
02befdf4 | 4205 | (plus:XF (mult:XF (match_dup 3) (match_dup 0)) |
26102535 RH |
4206 | (match_dup 4))) |
4207 | (use (const_int 1))])) | |
4208 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4209 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4210 | (minus:XF (match_dup 6) |
4211 | (mult:XF (match_dup 2) (match_dup 0)))) | |
26102535 RH |
4212 | (use (const_int 1))])) |
4213 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4214 | (parallel [(set (match_dup 0) | |
02befdf4 | 4215 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4216 | (match_dup 0))) |
4217 | (use (const_int 1))])) | |
4218 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4219 | (parallel [(set (match_dup 4) | |
52ad4d7b ZW |
4220 | (minus:XF (match_dup 1) |
4221 | (mult:XF (match_dup 2) (match_dup 3)))) | |
26102535 RH |
4222 | (use (const_int 1))])) |
4223 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
4224 | (set (match_dup 0) | |
02befdf4 | 4225 | (plus:XF (mult:XF (match_dup 4) (match_dup 0)) |
26102535 RH |
4226 | (match_dup 3)))) |
4227 | ] | |
02befdf4 | 4228 | "operands[6] = CONST1_RTX (XFmode);" |
26102535 RH |
4229 | [(set_attr "predicable" "no")]) |
4230 | ||
b38ba463 ZW |
4231 | ;; Inline square root. |
4232 | ||
4233 | (define_expand "sqrtxf2" | |
4234 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4235 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))] | |
4236 | "TARGET_INLINE_SQRT" | |
4237 | { | |
4238 | rtx insn; | |
4239 | if (TARGET_INLINE_SQRT_LAT) | |
4240 | #if 0 | |
4241 | insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]); | |
4242 | #else | |
4243 | abort (); | |
4244 | #endif | |
4245 | else | |
4246 | insn = gen_sqrtxf2_internal_thr (operands[0], operands[1]); | |
4247 | emit_insn (insn); | |
4248 | DONE; | |
4249 | }) | |
4250 | ||
4251 | ;; Latency-optimized square root. | |
4252 | ;; FIXME: Implement. | |
4253 | ||
4254 | ;; Throughput-optimized square root. | |
4255 | ||
4256 | (define_insn_and_split "sqrtxf2_internal_thr" | |
4257 | [(set (match_operand:XF 0 "fr_register_operand" "=&f") | |
4258 | (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f"))) | |
4259 | ;; Register r2 in optimization guide. | |
4260 | (clobber (match_scratch:DI 2 "=r")) | |
4261 | ;; Register f8 in optimization guide | |
4262 | (clobber (match_scratch:XF 3 "=&f")) | |
4263 | ;; Register f9 in optimization guide | |
4264 | (clobber (match_scratch:XF 4 "=&f")) | |
4265 | ;; Register f10 in optimization guide | |
4266 | (clobber (match_scratch:XF 5 "=&f")) | |
4267 | ;; Register f11 in optimization guide | |
4268 | (clobber (match_scratch:XF 6 "=&f")) | |
4269 | ;; Register p6 in optimization guide. | |
4270 | (clobber (match_scratch:BI 7 "=c"))] | |
4271 | "TARGET_INLINE_SQRT_THR" | |
4272 | "#" | |
4273 | "&& reload_completed" | |
4274 | [ ;; exponent of +1/2 in r2 | |
4275 | (set (match_dup 2) (const_int 65534)) | |
4276 | ;; +1/2 in f8. The Intel manual mistakenly specifies f10. | |
4277 | (set (match_dup 3) | |
4278 | (unspec:XF [(match_dup 2)] UNSPEC_SETF_EXP)) | |
4279 | ;; Step 1 | |
4280 | ;; y0 = 1/sqrt(a) in f7 | |
4281 | (parallel [(set (match_dup 8) | |
4282 | (div:XF (const_int 1) | |
4283 | (sqrt:XF (match_dup 9)))) | |
4284 | (set (match_dup 7) | |
4285 | (unspec:BI [(match_dup 9)] | |
4286 | UNSPEC_FR_SQRT_RECIP_APPROX)) | |
4287 | (use (const_int 0))]) | |
4288 | ;; Step 2 | |
4289 | ;; H0 = 1/2 * y0 in f9 | |
4290 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4291 | (parallel [(set (match_dup 4) | |
4292 | (plus:XF (mult:XF (match_dup 3) (match_dup 8)) | |
4293 | (match_dup 10))) | |
4294 | (use (const_int 1))])) | |
4295 | ;; Step 3 | |
4296 | ;; S0 = a * y0 in f7 | |
4297 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4298 | (parallel [(set (match_dup 8) | |
4299 | (plus:XF (mult:XF (match_dup 9) (match_dup 8)) | |
4300 | (match_dup 10))) | |
4301 | (use (const_int 1))])) | |
4302 | ;; Step 4 | |
4303 | ;; d0 = 1/2 - S0 * H0 in f10 | |
4304 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4305 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4306 | (minus:XF (match_dup 3) |
4307 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4308 | (use (const_int 1))])) |
4309 | ;; Step 5 | |
4310 | ;; H1 = H0 + d0 * H0 in f9 | |
4311 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4312 | (parallel [(set (match_dup 4) | |
4313 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4314 | (match_dup 4))) | |
4315 | (use (const_int 1))])) | |
4316 | ;; Step 6 | |
4317 | ;; S1 = S0 + d0 * S0 in f7 | |
4318 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4319 | (parallel [(set (match_dup 8) | |
4320 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4321 | (match_dup 8))) | |
4322 | (use (const_int 1))])) | |
4323 | ;; Step 7 | |
4324 | ;; d1 = 1/2 - S1 * H1 in f10 | |
4325 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4326 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4327 | (minus:XF (match_dup 3) |
4328 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4329 | (use (const_int 1))])) |
4330 | ;; Step 8 | |
4331 | ;; H2 = H1 + d1 * H1 in f9 | |
4332 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4333 | (parallel [(set (match_dup 4) | |
4334 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4335 | (match_dup 4))) | |
4336 | (use (const_int 1))])) | |
4337 | ;; Step 9 | |
4338 | ;; S2 = S1 + d1 * S1 in f7 | |
4339 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4340 | (parallel [(set (match_dup 8) | |
4341 | (plus:XF (mult:XF (match_dup 5) (match_dup 8)) | |
4342 | (match_dup 8))) | |
4343 | (use (const_int 1))])) | |
4344 | ;; Step 10 | |
4345 | ;; d2 = 1/2 - S2 * H2 in f10 | |
4346 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4347 | (parallel [(set (match_dup 5) | |
52ad4d7b ZW |
4348 | (minus:XF (match_dup 3) |
4349 | (mult:XF (match_dup 8) (match_dup 4)))) | |
b38ba463 ZW |
4350 | (use (const_int 1))])) |
4351 | ;; Step 11 | |
4352 | ;; e2 = a - S2 * S2 in f8 | |
4353 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4354 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4355 | (minus:XF (match_dup 9) |
4356 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4357 | (use (const_int 1))])) |
4358 | ;; Step 12 | |
4359 | ;; S3 = S2 + e2 * H2 in f7 | |
4360 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4361 | (parallel [(set (match_dup 8) | |
4362 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4363 | (match_dup 8))) | |
4364 | (use (const_int 1))])) | |
4365 | ;; Step 13 | |
4366 | ;; H3 = H2 + d2 * H2 in f9 | |
4367 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4368 | (parallel [(set (match_dup 4) | |
4369 | (plus:XF (mult:XF (match_dup 5) (match_dup 4)) | |
4370 | (match_dup 4))) | |
4371 | (use (const_int 1))])) | |
4372 | ;; Step 14 | |
4373 | ;; e3 = a - S3 * S3 in f8 | |
4374 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4375 | (parallel [(set (match_dup 3) | |
52ad4d7b ZW |
4376 | (minus:XF (match_dup 9) |
4377 | (mult:XF (match_dup 8) (match_dup 8)))) | |
b38ba463 ZW |
4378 | (use (const_int 1))])) |
4379 | ;; Step 15 | |
4380 | ;; S = S3 + e3 * H3 in f7 | |
4381 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
4382 | (parallel [(set (match_dup 0) | |
4383 | (plus:XF (mult:XF (match_dup 3) (match_dup 4)) | |
4384 | (match_dup 8))) | |
4385 | (use (const_int 0))]))] | |
4386 | { | |
4387 | /* Generate 82-bit versions of the input and output operands. */ | |
4388 | operands[8] = gen_rtx_REG (XFmode, REGNO (operands[0])); | |
4389 | operands[9] = gen_rtx_REG (XFmode, REGNO (operands[1])); | |
4390 | /* Generate required floating-point constants. */ | |
4391 | operands[10] = CONST0_RTX (XFmode); | |
4392 | } | |
4393 | [(set_attr "predicable" "no")]) | |
4394 | ||
26102535 RH |
4395 | ;; ??? frcpa works like cmp.foo.unc. |
4396 | ||
655f2eb9 | 4397 | (define_insn "*recip_approx" |
02befdf4 ZW |
4398 | [(set (match_operand:XF 0 "fr_register_operand" "=f") |
4399 | (div:XF (const_int 1) | |
4400 | (match_operand:XF 3 "fr_register_operand" "f"))) | |
f2f90c63 | 4401 | (set (match_operand:BI 1 "register_operand" "=c") |
02befdf4 | 4402 | (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f") |
086c0f96 | 4403 | (match_dup 3)] UNSPEC_FR_RECIP_APPROX)) |
655f2eb9 | 4404 | (use (match_operand:SI 4 "const_int_operand" ""))] |
02befdf4 | 4405 | "" |
655f2eb9 | 4406 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 4407 | [(set_attr "itanium_class" "fmisc") |
26102535 | 4408 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4409 | \f |
4410 | ;; :::::::::::::::::::: | |
4411 | ;; :: | |
4412 | ;; :: 32 bit Integer Shifts and Rotates | |
4413 | ;; :: | |
4414 | ;; :::::::::::::::::::: | |
4415 | ||
9c668921 | 4416 | (define_expand "ashlsi3" |
0551c32d RH |
4417 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4418 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
4419 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 | 4420 | "" |
9c668921 RH |
4421 | { |
4422 | if (GET_CODE (operands[2]) != CONST_INT) | |
4423 | { | |
4424 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
4425 | we've got to get rid of stray bits outside the SImode register. */ | |
4426 | rtx subshift = gen_reg_rtx (DImode); | |
4427 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
4428 | operands[2] = subshift; | |
4429 | } | |
1d5d7a21 | 4430 | }) |
9c668921 RH |
4431 | |
4432 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
4433 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
4434 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
4435 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 4436 | "" |
041f25e6 RH |
4437 | "@ |
4438 | shladd %0 = %1, %2, r0 | |
4439 | dep.z %0 = %1, %2, %E2 | |
4440 | shl %0 = %1, %2" | |
52e12ad0 | 4441 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
4442 | |
4443 | (define_expand "ashrsi3" | |
0551c32d RH |
4444 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4445 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4446 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4447 | "" |
c65ebc55 | 4448 | { |
041f25e6 RH |
4449 | rtx subtarget = gen_reg_rtx (DImode); |
4450 | if (GET_CODE (operands[2]) == CONST_INT) | |
4451 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
4452 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4453 | else | |
4454 | { | |
9c668921 | 4455 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4456 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4457 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4458 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4459 | } |
4460 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4461 | DONE; | |
1d5d7a21 | 4462 | }) |
c65ebc55 | 4463 | |
c65ebc55 | 4464 | (define_expand "lshrsi3" |
0551c32d RH |
4465 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4466 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
4467 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4468 | "" |
c65ebc55 | 4469 | { |
041f25e6 RH |
4470 | rtx subtarget = gen_reg_rtx (DImode); |
4471 | if (GET_CODE (operands[2]) == CONST_INT) | |
4472 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
4473 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
4474 | else | |
4475 | { | |
9c668921 | 4476 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 4477 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
4478 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
4479 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
4480 | } |
4481 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
4482 | DONE; | |
1d5d7a21 | 4483 | }) |
c65ebc55 | 4484 | |
c65ebc55 | 4485 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
4486 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
4487 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
4488 | |
4489 | (define_expand "rotrsi3" | |
66db6b45 RH |
4490 | [(set (match_operand:SI 0 "gr_register_operand" "") |
4491 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
4492 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
4493 | "" | |
66db6b45 RH |
4494 | { |
4495 | if (GET_MODE (operands[2]) != VOIDmode) | |
4496 | { | |
4497 | rtx tmp = gen_reg_rtx (DImode); | |
4498 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
4499 | operands[2] = tmp; | |
4500 | } | |
1d5d7a21 | 4501 | }) |
66db6b45 RH |
4502 | |
4503 | (define_insn_and_split "*rotrsi3_internal" | |
4504 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
4505 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4506 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
4507 | "" | |
4508 | "#" | |
4509 | "reload_completed" | |
c65ebc55 | 4510 | [(set (match_dup 3) |
66db6b45 | 4511 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
4512 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
4513 | (set (match_dup 3) | |
66db6b45 RH |
4514 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
4515 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
4516 | ||
4517 | (define_expand "rotlsi3" | |
4518 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
4519 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
4520 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 | 4521 | "" |
c65ebc55 JW |
4522 | { |
4523 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
4524 | { |
4525 | rtx tmp = gen_reg_rtx (SImode); | |
4526 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
4527 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
4528 | DONE; | |
4529 | } | |
1d5d7a21 | 4530 | }) |
66db6b45 RH |
4531 | |
4532 | (define_insn_and_split "*rotlsi3_internal" | |
4533 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
4534 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
4535 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
4536 | "" | |
4537 | "#" | |
4538 | "reload_completed" | |
4539 | [(set (match_dup 3) | |
4540 | (ior:DI (zero_extend:DI (match_dup 1)) | |
4541 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
4542 | (set (match_dup 3) | |
4543 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
1d5d7a21 RH |
4544 | { |
4545 | operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
4546 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
4547 | }) | |
c65ebc55 JW |
4548 | \f |
4549 | ;; :::::::::::::::::::: | |
4550 | ;; :: | |
4551 | ;; :: 64 bit Integer Shifts and Rotates | |
4552 | ;; :: | |
4553 | ;; :::::::::::::::::::: | |
4554 | ||
4555 | (define_insn "ashldi3" | |
52e12ad0 BS |
4556 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
4557 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
4558 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 4559 | "" |
041f25e6 RH |
4560 | "@ |
4561 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 4562 | shl %0 = %1, %2 |
041f25e6 | 4563 | shl %0 = %1, %2" |
52e12ad0 | 4564 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
4565 | |
4566 | ;; ??? Maybe combine this with the multiply and add instruction? | |
4567 | ||
4568 | (define_insn "*shladd" | |
0551c32d RH |
4569 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4570 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4571 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 4572 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
4573 | "" |
4574 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 4575 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4576 | |
4577 | ;; This can be created by register elimination if operand3 of shladd is an | |
4578 | ;; eliminable register or has reg_equiv_constant set. | |
4579 | ||
4580 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
4581 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
4582 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
4583 | ;; incorrectly. | |
4584 | ||
5527bf14 | 4585 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
4586 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
4587 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 4588 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 4589 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
4590 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
4591 | "reload_in_progress" | |
5527bf14 | 4592 | "* abort ();" |
c65ebc55 JW |
4593 | "reload_completed" |
4594 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
4595 | (match_dup 3))) | |
c65ebc55 | 4596 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 4597 | "" |
52e12ad0 | 4598 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4599 | |
4600 | (define_insn "ashrdi3" | |
52e12ad0 BS |
4601 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4602 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4603 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4604 | "" |
52e12ad0 BS |
4605 | "@ |
4606 | shr %0 = %1, %2 | |
4607 | shr %0 = %1, %2" | |
4608 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4609 | |
4610 | (define_insn "lshrdi3" | |
52e12ad0 BS |
4611 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
4612 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
4613 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 4614 | "" |
52e12ad0 BS |
4615 | "@ |
4616 | shr.u %0 = %1, %2 | |
4617 | shr.u %0 = %1, %2" | |
4618 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
4619 | |
4620 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
4621 | ;; will load the operand into a register and call the pattern if the predicate | |
4622 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
4623 | ;; verify that we have an appropriate constant in the expander. | |
4624 | ||
4625 | (define_expand "rotrdi3" | |
0551c32d RH |
4626 | [(set (match_operand:DI 0 "gr_register_operand" "") |
4627 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
4628 | (match_operand:DI 2 "nonmemory_operand" "")))] |
4629 | "" | |
c65ebc55 JW |
4630 | { |
4631 | if (! shift_count_operand (operands[2], DImode)) | |
4632 | FAIL; | |
1d5d7a21 | 4633 | }) |
c65ebc55 JW |
4634 | |
4635 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
4636 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4637 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4638 | (match_operand:DI 2 "shift_count_operand" "M")))] |
4639 | "" | |
4640 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 4641 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 4642 | |
66db6b45 RH |
4643 | (define_expand "rotldi3" |
4644 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
4645 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
4646 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4647 | "" | |
66db6b45 RH |
4648 | { |
4649 | if (! shift_count_operand (operands[2], DImode)) | |
4650 | FAIL; | |
1d5d7a21 | 4651 | }) |
66db6b45 RH |
4652 | |
4653 | (define_insn "*rotldi3_internal" | |
4654 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4655 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
4656 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
4657 | "" | |
4658 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 4659 | [(set_attr "itanium_class" "ishf")]) |
f526a3c8 RH |
4660 | \f |
4661 | ;; :::::::::::::::::::: | |
4662 | ;; :: | |
4663 | ;; :: 128 bit Integer Shifts and Rotates | |
4664 | ;; :: | |
4665 | ;; :::::::::::::::::::: | |
4666 | ||
4667 | (define_expand "ashrti3" | |
4668 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4669 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4670 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4671 | "" | |
4672 | { | |
4673 | if (!dshift_count_operand (operands[2], DImode)) | |
4674 | FAIL; | |
4675 | }) | |
4676 | ||
4677 | (define_insn_and_split "*ashrti3_internal" | |
4678 | [(set (match_operand:TI 0 "gr_register_operand" "=r") | |
4679 | (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4680 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4681 | "" | |
4682 | "#" | |
4683 | "reload_completed" | |
4684 | [(const_int 0)] | |
4685 | { | |
4686 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4687 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4688 | rtx hi = gen_highpart (DImode, operands[1]); | |
4689 | rtx shiftlo = GEN_INT (shift & 63); | |
4690 | ||
4691 | if (shift & 64) | |
4692 | { | |
4693 | emit_insn (gen_ashrdi3 (lo, hi, shiftlo)); | |
4694 | emit_insn (gen_ashrdi3 (hi, hi, GEN_INT (63))); | |
4695 | } | |
4696 | else | |
4697 | { | |
4698 | emit_insn (gen_shrp (lo, hi, lo, shiftlo)); | |
4699 | emit_insn (gen_ashrdi3 (hi, hi, shiftlo)); | |
4700 | } | |
4701 | DONE; | |
4702 | }) | |
4703 | ||
4704 | (define_expand "lshrti3" | |
4705 | [(set (match_operand:TI 0 "gr_register_operand" "") | |
4706 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "") | |
4707 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
4708 | "" | |
4709 | { | |
4710 | if (!dshift_count_operand (operands[2], DImode)) | |
4711 | FAIL; | |
4712 | }) | |
4713 | ||
4714 | (define_insn_and_split "*lshrti3_internal" | |
4715 | [(set (match_operand:TI 0 "gr_register_operand" "=r") | |
4716 | (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r") | |
4717 | (match_operand:DI 2 "dshift_count_operand" "n")))] | |
4718 | "" | |
4719 | "#" | |
4720 | "reload_completed" | |
4721 | [(const_int 0)] | |
4722 | { | |
4723 | HOST_WIDE_INT shift = INTVAL (operands[2]); | |
4724 | rtx lo = gen_lowpart (DImode, operands[1]); | |
4725 | rtx hi = gen_highpart (DImode, operands[1]); | |
4726 | rtx shiftlo = GEN_INT (shift & 63); | |
4727 | ||
4728 | if (shift & 64) | |
4729 | { | |
4730 | emit_insn (gen_lshrdi3 (lo, hi, shiftlo)); | |
4731 | emit_move_insn (hi, const0_rtx); | |
4732 | } | |
4733 | else | |
4734 | { | |
4735 | emit_insn (gen_shrp (lo, hi, lo, shiftlo)); | |
4736 | emit_insn (gen_lshrdi3 (hi, hi, shiftlo)); | |
4737 | } | |
4738 | DONE; | |
4739 | }) | |
4740 | ||
4741 | (define_insn "shrp" | |
4742 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
4743 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r") | |
4744 | (match_operand:DI 2 "gr_register_operand" "r") | |
4745 | (match_operand:DI 3 "shift_count_operand" "M")] | |
4746 | UNSPEC_SHRP))] | |
4747 | "" | |
4748 | "shrp %0 = %1, %2, %3" | |
4749 | [(set_attr "itanium_class" "ishf")]) | |
c65ebc55 JW |
4750 | \f |
4751 | ;; :::::::::::::::::::: | |
4752 | ;; :: | |
058557c4 | 4753 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
4754 | ;; :: |
4755 | ;; :::::::::::::::::::: | |
4756 | ||
4757 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
4758 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
4759 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
4760 | ;; This doesn't work for unary logical operations, because we don't call | |
4761 | ;; apply_distributive_law for them. | |
4762 | ||
4763 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
4764 | ;; apply_distributive_law. We get inefficient code for | |
4765 | ;; int sub4 (int i, int j) { return i & ~j; } | |
4766 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
4767 | ;; (zero_extend (and (not A) B)) in combine. | |
4768 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
4769 | ;; one_cmplsi2 pattern. | |
4770 | ||
058557c4 | 4771 | (define_insn "one_cmplsi2" |
0551c32d RH |
4772 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
4773 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4774 | "" |
4775 | "andcm %0 = -1, %1" | |
52e12ad0 | 4776 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4777 | \f |
4778 | ;; :::::::::::::::::::: | |
4779 | ;; :: | |
058557c4 | 4780 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
4781 | ;; :: |
4782 | ;; :::::::::::::::::::: | |
4783 | ||
4784 | (define_insn "anddi3" | |
0551c32d RH |
4785 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4786 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4787 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4788 | "" |
4789 | "@ | |
4790 | and %0 = %2, %1 | |
aebf2462 | 4791 | fand %0 = %2, %1" |
52e12ad0 | 4792 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4793 | |
4794 | (define_insn "*andnot" | |
0551c32d RH |
4795 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4796 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
4797 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4798 | "" |
4799 | "@ | |
4800 | andcm %0 = %2, %1 | |
aebf2462 | 4801 | fandcm %0 = %2, %1" |
52e12ad0 | 4802 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4803 | |
4804 | (define_insn "iordi3" | |
0551c32d RH |
4805 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4806 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4807 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4808 | "" |
4809 | "@ | |
4810 | or %0 = %2, %1 | |
aebf2462 | 4811 | for %0 = %2, %1" |
52e12ad0 | 4812 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4813 | |
4814 | (define_insn "xordi3" | |
0551c32d RH |
4815 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
4816 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
4817 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
4818 | "" |
4819 | "@ | |
4820 | xor %0 = %2, %1 | |
aebf2462 | 4821 | fxor %0 = %2, %1" |
52e12ad0 | 4822 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
4823 | |
4824 | (define_insn "one_cmpldi2" | |
0551c32d RH |
4825 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
4826 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
4827 | "" |
4828 | "andcm %0 = -1, %1" | |
52e12ad0 | 4829 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
4830 | \f |
4831 | ;; :::::::::::::::::::: | |
4832 | ;; :: | |
4833 | ;; :: Comparisons | |
4834 | ;; :: | |
4835 | ;; :::::::::::::::::::: | |
4836 | ||
f2f90c63 RH |
4837 | (define_expand "cmpbi" |
4838 | [(set (cc0) | |
4839 | (compare (match_operand:BI 0 "register_operand" "") | |
4840 | (match_operand:BI 1 "const_int_operand" "")))] | |
4841 | "" | |
f2f90c63 RH |
4842 | { |
4843 | ia64_compare_op0 = operands[0]; | |
4844 | ia64_compare_op1 = operands[1]; | |
4845 | DONE; | |
1d5d7a21 | 4846 | }) |
f2f90c63 | 4847 | |
c65ebc55 JW |
4848 | (define_expand "cmpsi" |
4849 | [(set (cc0) | |
0551c32d RH |
4850 | (compare (match_operand:SI 0 "gr_register_operand" "") |
4851 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4852 | "" |
c65ebc55 JW |
4853 | { |
4854 | ia64_compare_op0 = operands[0]; | |
4855 | ia64_compare_op1 = operands[1]; | |
4856 | DONE; | |
1d5d7a21 | 4857 | }) |
c65ebc55 JW |
4858 | |
4859 | (define_expand "cmpdi" | |
4860 | [(set (cc0) | |
0551c32d RH |
4861 | (compare (match_operand:DI 0 "gr_register_operand" "") |
4862 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 | 4863 | "" |
c65ebc55 JW |
4864 | { |
4865 | ia64_compare_op0 = operands[0]; | |
4866 | ia64_compare_op1 = operands[1]; | |
4867 | DONE; | |
1d5d7a21 | 4868 | }) |
c65ebc55 JW |
4869 | |
4870 | (define_expand "cmpsf" | |
4871 | [(set (cc0) | |
0551c32d RH |
4872 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
4873 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4874 | "" |
c65ebc55 JW |
4875 | { |
4876 | ia64_compare_op0 = operands[0]; | |
4877 | ia64_compare_op1 = operands[1]; | |
4878 | DONE; | |
1d5d7a21 | 4879 | }) |
c65ebc55 JW |
4880 | |
4881 | (define_expand "cmpdf" | |
4882 | [(set (cc0) | |
0551c32d RH |
4883 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
4884 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 | 4885 | "" |
c65ebc55 JW |
4886 | { |
4887 | ia64_compare_op0 = operands[0]; | |
4888 | ia64_compare_op1 = operands[1]; | |
4889 | DONE; | |
1d5d7a21 | 4890 | }) |
c65ebc55 | 4891 | |
02befdf4 | 4892 | (define_expand "cmpxf" |
c65ebc55 | 4893 | [(set (cc0) |
02befdf4 ZW |
4894 | (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "") |
4895 | (match_operand:XF 1 "xfreg_or_fp01_operand" "")))] | |
4896 | "" | |
c65ebc55 JW |
4897 | { |
4898 | ia64_compare_op0 = operands[0]; | |
4899 | ia64_compare_op1 = operands[1]; | |
4900 | DONE; | |
1d5d7a21 | 4901 | }) |
c65ebc55 | 4902 | |
24ea7948 ZW |
4903 | (define_expand "cmptf" |
4904 | [(set (cc0) | |
4905 | (compare (match_operand:TF 0 "gr_register_operand" "") | |
4906 | (match_operand:TF 1 "gr_register_operand" "")))] | |
4907 | "TARGET_HPUX" | |
4908 | { | |
4909 | ia64_compare_op0 = operands[0]; | |
4910 | ia64_compare_op1 = operands[1]; | |
4911 | DONE; | |
4912 | }) | |
4913 | ||
c65ebc55 | 4914 | (define_insn "*cmpsi_normal" |
f2f90c63 RH |
4915 | [(set (match_operand:BI 0 "register_operand" "=c") |
4916 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
4917 | [(match_operand:SI 2 "gr_register_operand" "r") |
4918 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
4919 | "" |
4920 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 4921 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4922 | |
18a3c539 JW |
4923 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4924 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4925 | ||
c65ebc55 | 4926 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
4927 | [(set (match_operand:BI 0 "register_operand" "=c") |
4928 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4929 | [(match_operand:SI 2 "gr_register_operand" "r") |
4930 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4931 | "" |
18a3c539 | 4932 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4933 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4934 | |
4935 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
4936 | [(set (match_operand:BI 0 "register_operand" "=c") |
4937 | (match_operator:BI 1 "normal_comparison_operator" | |
4938 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 4939 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 4940 | "" |
f2f90c63 | 4941 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 4942 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 4943 | |
18a3c539 JW |
4944 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
4945 | ;; unsigned comparisons don't accept immediate operands of zero. | |
4946 | ||
c65ebc55 | 4947 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
4948 | [(set (match_operand:BI 0 "register_operand" "=c") |
4949 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
4950 | [(match_operand:DI 2 "gr_register_operand" "r") |
4951 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 4952 | "" |
18a3c539 | 4953 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 4954 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4955 | |
4956 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4957 | [(set (match_operand:BI 0 "register_operand" "=c") |
4958 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4959 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4960 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4961 | "" |
4962 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4963 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4964 | |
4965 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4966 | [(set (match_operand:BI 0 "register_operand" "=c") |
4967 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4968 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4969 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4970 | "" |
4971 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4972 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4973 | |
02befdf4 | 4974 | (define_insn "*cmpxf_internal" |
f2f90c63 RH |
4975 | [(set (match_operand:BI 0 "register_operand" "=c") |
4976 | (match_operator:BI 1 "comparison_operator" | |
02befdf4 ZW |
4977 | [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG") |
4978 | (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))] | |
4979 | "" | |
3f622353 | 4980 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4981 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4982 | |
c65ebc55 JW |
4983 | ;; ??? Can this pattern be generated? |
4984 | ||
4985 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4986 | [(set (match_operand:BI 0 "register_operand" "=c") |
4987 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4988 | (const_int 1) |
4989 | (match_operand:DI 2 "immediate_operand" "n")) | |
4990 | (const_int 0)))] | |
4991 | "" | |
4992 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4993 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4994 | |
4995 | (define_insn "*bit_one" | |
f2f90c63 RH |
4996 | [(set (match_operand:BI 0 "register_operand" "=c") |
4997 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4998 | (const_int 1) |
4999 | (match_operand:DI 2 "immediate_operand" "n")) | |
5000 | (const_int 0)))] | |
5001 | "" | |
5002 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 5003 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
5004 | \f |
5005 | ;; :::::::::::::::::::: | |
5006 | ;; :: | |
5007 | ;; :: Branches | |
5008 | ;; :: | |
5009 | ;; :::::::::::::::::::: | |
5010 | ||
5011 | (define_expand "beq" | |
f2f90c63 RH |
5012 | [(set (pc) |
5013 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5014 | (label_ref (match_operand 0 "" "")) |
5015 | (pc)))] | |
5016 | "" | |
f2f90c63 | 5017 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
5018 | |
5019 | (define_expand "bne" | |
f2f90c63 RH |
5020 | [(set (pc) |
5021 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5022 | (label_ref (match_operand 0 "" "")) |
5023 | (pc)))] | |
5024 | "" | |
f2f90c63 | 5025 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
5026 | |
5027 | (define_expand "blt" | |
f2f90c63 RH |
5028 | [(set (pc) |
5029 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5030 | (label_ref (match_operand 0 "" "")) |
5031 | (pc)))] | |
5032 | "" | |
f2f90c63 | 5033 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
5034 | |
5035 | (define_expand "ble" | |
f2f90c63 RH |
5036 | [(set (pc) |
5037 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5038 | (label_ref (match_operand 0 "" "")) |
5039 | (pc)))] | |
5040 | "" | |
f2f90c63 | 5041 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
5042 | |
5043 | (define_expand "bgt" | |
f2f90c63 RH |
5044 | [(set (pc) |
5045 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5046 | (label_ref (match_operand 0 "" "")) |
5047 | (pc)))] | |
5048 | "" | |
f2f90c63 | 5049 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
5050 | |
5051 | (define_expand "bge" | |
f2f90c63 RH |
5052 | [(set (pc) |
5053 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5054 | (label_ref (match_operand 0 "" "")) |
5055 | (pc)))] | |
5056 | "" | |
f2f90c63 | 5057 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
5058 | |
5059 | (define_expand "bltu" | |
f2f90c63 RH |
5060 | [(set (pc) |
5061 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5062 | (label_ref (match_operand 0 "" "")) |
5063 | (pc)))] | |
5064 | "" | |
f2f90c63 | 5065 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
5066 | |
5067 | (define_expand "bleu" | |
f2f90c63 RH |
5068 | [(set (pc) |
5069 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5070 | (label_ref (match_operand 0 "" "")) |
5071 | (pc)))] | |
5072 | "" | |
f2f90c63 | 5073 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
5074 | |
5075 | (define_expand "bgtu" | |
f2f90c63 RH |
5076 | [(set (pc) |
5077 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5078 | (label_ref (match_operand 0 "" "")) |
5079 | (pc)))] | |
5080 | "" | |
f2f90c63 | 5081 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
5082 | |
5083 | (define_expand "bgeu" | |
f2f90c63 RH |
5084 | [(set (pc) |
5085 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
5086 | (label_ref (match_operand 0 "" "")) |
5087 | (pc)))] | |
5088 | "" | |
f2f90c63 | 5089 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 5090 | |
e57b9d65 | 5091 | (define_expand "bunordered" |
f2f90c63 RH |
5092 | [(set (pc) |
5093 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5094 | (label_ref (match_operand 0 "" "")) |
5095 | (pc)))] | |
5096 | "" | |
f2f90c63 | 5097 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
5098 | |
5099 | (define_expand "bordered" | |
f2f90c63 RH |
5100 | [(set (pc) |
5101 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
5102 | (label_ref (match_operand 0 "" "")) |
5103 | (pc)))] | |
5104 | "" | |
f2f90c63 | 5105 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 5106 | |
6b6c1201 | 5107 | (define_insn "*br_true" |
c65ebc55 | 5108 | [(set (pc) |
6b6c1201 | 5109 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5110 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
5111 | (const_int 0)]) |
5112 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
5113 | (pc)))] |
5114 | "" | |
85548039 | 5115 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 5116 | [(set_attr "itanium_class" "br") |
e5bde68a | 5117 | (set_attr "predicable" "no")]) |
c65ebc55 | 5118 | |
6b6c1201 | 5119 | (define_insn "*br_false" |
c65ebc55 | 5120 | [(set (pc) |
6b6c1201 | 5121 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5122 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5123 | (const_int 0)]) |
c65ebc55 | 5124 | (pc) |
6b6c1201 | 5125 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 5126 | "" |
85548039 | 5127 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 5128 | [(set_attr "itanium_class" "br") |
e5bde68a | 5129 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5130 | \f |
5131 | ;; :::::::::::::::::::: | |
5132 | ;; :: | |
5527bf14 RH |
5133 | ;; :: Counted loop operations |
5134 | ;; :: | |
5135 | ;; :::::::::::::::::::: | |
5136 | ||
5137 | (define_expand "doloop_end" | |
5138 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5139 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5140 | (use (match_operand 2 "" "")) ; max iterations | |
5141 | (use (match_operand 3 "" "")) ; loop level | |
5142 | (use (match_operand 4 "" ""))] ; label | |
5143 | "" | |
5527bf14 RH |
5144 | { |
5145 | /* Only use cloop on innermost loops. */ | |
5146 | if (INTVAL (operands[3]) > 1) | |
5147 | FAIL; | |
5148 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
5149 | operands[4])); | |
5150 | DONE; | |
1d5d7a21 | 5151 | }) |
5527bf14 RH |
5152 | |
5153 | (define_insn "doloop_end_internal" | |
5154 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
5155 | (const_int 0)) | |
5156 | (label_ref (match_operand 1 "" "")) | |
5157 | (pc))) | |
5158 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
147d5f6f AM |
5159 | (plus:DI (match_dup 0) (const_int -1)) |
5160 | (match_dup 0)))] | |
5527bf14 RH |
5161 | "" |
5162 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 5163 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
5164 | (set_attr "predicable" "no")]) |
5165 | \f | |
5166 | ;; :::::::::::::::::::: | |
5167 | ;; :: | |
c65ebc55 JW |
5168 | ;; :: Set flag operations |
5169 | ;; :: | |
5170 | ;; :::::::::::::::::::: | |
5171 | ||
5172 | (define_expand "seq" | |
f2f90c63 | 5173 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5174 | "" |
f2f90c63 | 5175 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
5176 | |
5177 | (define_expand "sne" | |
f2f90c63 | 5178 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5179 | "" |
f2f90c63 | 5180 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
5181 | |
5182 | (define_expand "slt" | |
f2f90c63 | 5183 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5184 | "" |
f2f90c63 | 5185 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
5186 | |
5187 | (define_expand "sle" | |
f2f90c63 | 5188 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5189 | "" |
f2f90c63 | 5190 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
5191 | |
5192 | (define_expand "sgt" | |
f2f90c63 | 5193 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5194 | "" |
f2f90c63 | 5195 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
5196 | |
5197 | (define_expand "sge" | |
f2f90c63 | 5198 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5199 | "" |
f2f90c63 | 5200 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
5201 | |
5202 | (define_expand "sltu" | |
f2f90c63 | 5203 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5204 | "" |
f2f90c63 | 5205 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
5206 | |
5207 | (define_expand "sleu" | |
f2f90c63 | 5208 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5209 | "" |
f2f90c63 | 5210 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
5211 | |
5212 | (define_expand "sgtu" | |
f2f90c63 | 5213 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5214 | "" |
f2f90c63 | 5215 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
5216 | |
5217 | (define_expand "sgeu" | |
f2f90c63 | 5218 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 5219 | "" |
f2f90c63 | 5220 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 5221 | |
e57b9d65 | 5222 | (define_expand "sunordered" |
f2f90c63 | 5223 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5224 | "" |
f2f90c63 | 5225 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
5226 | |
5227 | (define_expand "sordered" | |
f2f90c63 | 5228 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 5229 | "" |
f2f90c63 | 5230 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 5231 | |
c65ebc55 JW |
5232 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
5233 | ;; efficient than mov/mov/cst/cst. | |
5234 | ||
0551c32d RH |
5235 | (define_insn_and_split "*sne_internal" |
5236 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5237 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5238 | (const_int 0)))] |
5239 | "" | |
5240 | "#" | |
c65ebc55 | 5241 | "reload_completed" |
f2f90c63 RH |
5242 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5243 | (set (match_dup 0) (const_int 1))) | |
5244 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5245 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 5246 | "" |
52e12ad0 | 5247 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 5248 | |
0551c32d RH |
5249 | (define_insn_and_split "*seq_internal" |
5250 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 5251 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
5252 | (const_int 0)))] |
5253 | "" | |
5254 | "#" | |
c65ebc55 | 5255 | "reload_completed" |
f2f90c63 RH |
5256 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
5257 | (set (match_dup 0) (const_int 0))) | |
5258 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
5259 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 5260 | "" |
52e12ad0 | 5261 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
5262 | \f |
5263 | ;; :::::::::::::::::::: | |
5264 | ;; :: | |
5265 | ;; :: Conditional move instructions. | |
5266 | ;; :: | |
5267 | ;; :::::::::::::::::::: | |
5268 | ||
5269 | ;; ??? Add movXXcc patterns? | |
5270 | ||
c65ebc55 JW |
5271 | ;; |
5272 | ;; DImode if_then_else patterns. | |
5273 | ;; | |
5274 | ||
75cdbeb8 | 5275 | (define_insn "*cmovdi_internal" |
f2f90c63 | 5276 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 5277 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 5278 | (if_then_else:DI |
f2f90c63 RH |
5279 | (match_operator 4 "predicate_operator" |
5280 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 5281 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 5282 | (const_int 0)]) |
f2f90c63 | 5283 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 5284 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 5285 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 5286 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 5287 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5288 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 5289 | { abort (); } |
75cdbeb8 RH |
5290 | [(set_attr "predicable" "no")]) |
5291 | ||
5292 | (define_split | |
f2f90c63 | 5293 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 5294 | (if_then_else |
f2f90c63 RH |
5295 | (match_operator 4 "predicate_operator" |
5296 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 5297 | (const_int 0)]) |
f2f90c63 RH |
5298 | (match_operand 2 "move_operand" "") |
5299 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
5300 | "reload_completed" |
5301 | [(const_int 0)] | |
e5bde68a | 5302 | { |
21515593 RH |
5303 | bool emitted_something = false; |
5304 | rtx dest = operands[0]; | |
5305 | rtx srct = operands[2]; | |
5306 | rtx srcf = operands[3]; | |
5307 | rtx cond = operands[4]; | |
2f937369 | 5308 | |
21515593 | 5309 | if (! rtx_equal_p (dest, srct)) |
e5bde68a | 5310 | { |
21515593 RH |
5311 | ia64_emit_cond_move (dest, srct, cond); |
5312 | emitted_something = true; | |
e5bde68a | 5313 | } |
21515593 | 5314 | if (! rtx_equal_p (dest, srcf)) |
3b572406 | 5315 | { |
21515593 RH |
5316 | cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE, |
5317 | VOIDmode, operands[1], const0_rtx); | |
5318 | ia64_emit_cond_move (dest, srcf, cond); | |
5319 | emitted_something = true; | |
3b572406 | 5320 | } |
2f937369 | 5321 | if (! emitted_something) |
f9974026 | 5322 | emit_note (NOTE_INSN_DELETED); |
3b572406 | 5323 | DONE; |
1d5d7a21 | 5324 | }) |
c65ebc55 JW |
5325 | |
5326 | ;; Absolute value pattern. | |
5327 | ||
5328 | (define_insn "*absdi2_internal" | |
0551c32d | 5329 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5330 | (if_then_else:DI |
f2f90c63 RH |
5331 | (match_operator 4 "predicate_operator" |
5332 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5333 | (const_int 0)]) |
0551c32d RH |
5334 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
5335 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5336 | "" |
e5bde68a | 5337 | "#" |
52e12ad0 | 5338 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5339 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5340 | |
5341 | (define_split | |
5342 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 5343 | (if_then_else:DI |
f2f90c63 RH |
5344 | (match_operator 4 "predicate_operator" |
5345 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5346 | (const_int 0)]) |
0551c32d RH |
5347 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5348 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5349 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5350 | [(cond_exec | |
5351 | (match_dup 4) | |
5352 | (set (match_dup 0) | |
5353 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
5354 | "") |
5355 | ||
e5bde68a RH |
5356 | (define_split |
5357 | [(set (match_operand:DI 0 "register_operand" "") | |
5358 | (if_then_else:DI | |
f2f90c63 RH |
5359 | (match_operator 4 "predicate_operator" |
5360 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5361 | (const_int 0)]) |
0551c32d RH |
5362 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
5363 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5364 | "reload_completed" |
5365 | [(cond_exec | |
5366 | (match_dup 4) | |
5367 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
5368 | (cond_exec | |
5369 | (match_dup 5) | |
5370 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5371 | { |
5372 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5373 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5374 | }) |
c65ebc55 JW |
5375 | |
5376 | ;; | |
5377 | ;; SImode if_then_else patterns. | |
5378 | ;; | |
5379 | ||
75cdbeb8 | 5380 | (define_insn "*cmovsi_internal" |
f2f90c63 | 5381 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 5382 | (if_then_else:SI |
f2f90c63 RH |
5383 | (match_operator 4 "predicate_operator" |
5384 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 5385 | (const_int 0)]) |
f2f90c63 | 5386 | (match_operand:SI 2 "move_operand" |
3b572406 | 5387 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 5388 | (match_operand:SI 3 "move_operand" |
3b572406 | 5389 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 5390 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 5391 | && ia64_move_ok (operands[0], operands[3])" |
1d5d7a21 | 5392 | { abort (); } |
3b572406 | 5393 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
5394 | |
5395 | (define_insn "*abssi2_internal" | |
0551c32d | 5396 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 5397 | (if_then_else:SI |
f2f90c63 RH |
5398 | (match_operator 4 "predicate_operator" |
5399 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5400 | (const_int 0)]) |
0551c32d RH |
5401 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
5402 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 5403 | "" |
e5bde68a | 5404 | "#" |
52e12ad0 | 5405 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 5406 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5407 | |
5408 | (define_split | |
5409 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 5410 | (if_then_else:SI |
f2f90c63 RH |
5411 | (match_operator 4 "predicate_operator" |
5412 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5413 | (const_int 0)]) |
0551c32d RH |
5414 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5415 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5416 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
5417 | [(cond_exec | |
5418 | (match_dup 4) | |
5419 | (set (match_dup 0) | |
5420 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
5421 | "") |
5422 | ||
e5bde68a RH |
5423 | (define_split |
5424 | [(set (match_operand:SI 0 "register_operand" "") | |
5425 | (if_then_else:SI | |
f2f90c63 RH |
5426 | (match_operator 4 "predicate_operator" |
5427 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 5428 | (const_int 0)]) |
0551c32d RH |
5429 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
5430 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
5431 | "reload_completed" |
5432 | [(cond_exec | |
5433 | (match_dup 4) | |
5434 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
5435 | (cond_exec | |
5436 | (match_dup 5) | |
5437 | (set (match_dup 0) (match_dup 3)))] | |
e5bde68a RH |
5438 | { |
5439 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 5440 | VOIDmode, operands[1], const0_rtx); |
1d5d7a21 | 5441 | }) |
e5bde68a | 5442 | |
7dcc803e | 5443 | (define_insn_and_split "*cond_opsi2_internal" |
acb0638d BS |
5444 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5445 | (match_operator:SI 5 "condop_operator" | |
5446 | [(if_then_else:SI | |
5447 | (match_operator 6 "predicate_operator" | |
5448 | [(match_operand:BI 1 "register_operand" "c") | |
5449 | (const_int 0)]) | |
5450 | (match_operand:SI 2 "gr_register_operand" "r") | |
5451 | (match_operand:SI 3 "gr_register_operand" "r")) | |
5452 | (match_operand:SI 4 "gr_register_operand" "r")]))] | |
5453 | "" | |
5454 | "#" | |
acb0638d BS |
5455 | "reload_completed" |
5456 | [(cond_exec | |
5457 | (match_dup 6) | |
5458 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)]))) | |
5459 | (cond_exec | |
5460 | (match_dup 7) | |
5461 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))] | |
acb0638d BS |
5462 | { |
5463 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5464 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5465 | } |
7dcc803e BS |
5466 | [(set_attr "itanium_class" "ialu") |
5467 | (set_attr "predicable" "no")]) | |
5468 | ||
acb0638d | 5469 | |
7dcc803e | 5470 | (define_insn_and_split "*cond_opsi2_internal_b" |
acb0638d BS |
5471 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5472 | (match_operator:SI 5 "condop_operator" | |
5473 | [(match_operand:SI 4 "gr_register_operand" "r") | |
5474 | (if_then_else:SI | |
5475 | (match_operator 6 "predicate_operator" | |
5476 | [(match_operand:BI 1 "register_operand" "c") | |
5477 | (const_int 0)]) | |
5478 | (match_operand:SI 2 "gr_register_operand" "r") | |
5479 | (match_operand:SI 3 "gr_register_operand" "r"))]))] | |
5480 | "" | |
5481 | "#" | |
acb0638d BS |
5482 | "reload_completed" |
5483 | [(cond_exec | |
5484 | (match_dup 6) | |
5485 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)]))) | |
5486 | (cond_exec | |
5487 | (match_dup 7) | |
5488 | (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))] | |
acb0638d BS |
5489 | { |
5490 | operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE, | |
5491 | VOIDmode, operands[1], const0_rtx); | |
1d5d7a21 | 5492 | } |
7dcc803e BS |
5493 | [(set_attr "itanium_class" "ialu") |
5494 | (set_attr "predicable" "no")]) | |
acb0638d | 5495 | |
c65ebc55 JW |
5496 | \f |
5497 | ;; :::::::::::::::::::: | |
5498 | ;; :: | |
5499 | ;; :: Call and branch instructions | |
5500 | ;; :: | |
5501 | ;; :::::::::::::::::::: | |
5502 | ||
5503 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
5504 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
5505 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
5506 | ;; registers used as operands. | |
5507 | ||
5508 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
5509 | ;; is supplied for the sake of some RISC machines which need to put this | |
5510 | ;; information into the assembler code; they can put it in the RTL instead of | |
5511 | ;; operand 1. | |
5512 | ||
5513 | (define_expand "call" | |
5514 | [(use (match_operand:DI 0 "" "")) | |
5515 | (use (match_operand 1 "" "")) | |
5516 | (use (match_operand 2 "" "")) | |
5517 | (use (match_operand 3 "" ""))] | |
5518 | "" | |
c65ebc55 | 5519 | { |
599aedd9 | 5520 | ia64_expand_call (NULL_RTX, operands[0], operands[2], false); |
c65ebc55 | 5521 | DONE; |
1d5d7a21 | 5522 | }) |
c65ebc55 | 5523 | |
2ed4af6f RH |
5524 | (define_expand "sibcall" |
5525 | [(use (match_operand:DI 0 "" "")) | |
5526 | (use (match_operand 1 "" "")) | |
5527 | (use (match_operand 2 "" "")) | |
5528 | (use (match_operand 3 "" ""))] | |
c65ebc55 | 5529 | "" |
c65ebc55 | 5530 | { |
599aedd9 | 5531 | ia64_expand_call (NULL_RTX, operands[0], operands[2], true); |
2ed4af6f | 5532 | DONE; |
1d5d7a21 | 5533 | }) |
c65ebc55 | 5534 | |
c65ebc55 | 5535 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
5536 | ;; register in which the value is returned. There are three more operands, |
5537 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 5538 | ;; increased by one). |
2ed4af6f | 5539 | ;; |
c65ebc55 JW |
5540 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
5541 | ||
5542 | (define_expand "call_value" | |
5543 | [(use (match_operand 0 "" "")) | |
5544 | (use (match_operand:DI 1 "" "")) | |
5545 | (use (match_operand 2 "" "")) | |
5546 | (use (match_operand 3 "" "")) | |
5547 | (use (match_operand 4 "" ""))] | |
5548 | "" | |
c65ebc55 | 5549 | { |
599aedd9 | 5550 | ia64_expand_call (operands[0], operands[1], operands[3], false); |
c65ebc55 | 5551 | DONE; |
1d5d7a21 | 5552 | }) |
c65ebc55 | 5553 | |
2ed4af6f RH |
5554 | (define_expand "sibcall_value" |
5555 | [(use (match_operand 0 "" "")) | |
5556 | (use (match_operand:DI 1 "" "")) | |
5557 | (use (match_operand 2 "" "")) | |
5558 | (use (match_operand 3 "" "")) | |
5559 | (use (match_operand 4 "" ""))] | |
c65ebc55 | 5560 | "" |
c65ebc55 | 5561 | { |
599aedd9 | 5562 | ia64_expand_call (operands[0], operands[1], operands[3], true); |
2ed4af6f | 5563 | DONE; |
1d5d7a21 | 5564 | }) |
c65ebc55 | 5565 | |
c65ebc55 JW |
5566 | ;; Call subroutine returning any type. |
5567 | ||
5568 | (define_expand "untyped_call" | |
5569 | [(parallel [(call (match_operand 0 "" "") | |
5570 | (const_int 0)) | |
5571 | (match_operand 1 "" "") | |
5572 | (match_operand 2 "" "")])] | |
5573 | "" | |
c65ebc55 JW |
5574 | { |
5575 | int i; | |
5576 | ||
5577 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
5578 | ||
5579 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
5580 | { | |
5581 | rtx set = XVECEXP (operands[2], 0, i); | |
5582 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
5583 | } | |
5584 | ||
5585 | /* The optimizer does not know that the call sets the function value | |
5586 | registers we stored in the result block. We avoid problems by | |
5587 | claiming that all hard registers are used and clobbered at this | |
5588 | point. */ | |
5589 | emit_insn (gen_blockage ()); | |
5590 | ||
5591 | DONE; | |
1d5d7a21 | 5592 | }) |
c65ebc55 | 5593 | |
599aedd9 RH |
5594 | (define_insn "call_nogp" |
5595 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5596 | (const_int 0)) | |
5597 | (clobber (match_operand:DI 1 "register_operand" "=b,b"))] | |
2ed4af6f | 5598 | "" |
599aedd9 | 5599 | "br.call%+.many %1 = %0" |
52e12ad0 | 5600 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5601 | |
599aedd9 | 5602 | (define_insn "call_value_nogp" |
75293ad6 | 5603 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5604 | (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i")) |
5605 | (const_int 0))) | |
5606 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] | |
2ed4af6f | 5607 | "" |
599aedd9 | 5608 | "br.call%+.many %2 = %1" |
52e12ad0 | 5609 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5610 | |
599aedd9 RH |
5611 | (define_insn "sibcall_nogp" |
5612 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i")) | |
5613 | (const_int 0))] | |
2ed4af6f RH |
5614 | "" |
5615 | "br%+.many %0" | |
52e12ad0 | 5616 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5617 | |
599aedd9 | 5618 | (define_insn "call_gp" |
c8083186 | 5619 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) |
599aedd9 RH |
5620 | (const_int 1)) |
5621 | (clobber (match_operand:DI 1 "register_operand" "=b,b")) | |
5622 | (clobber (match_scratch:DI 2 "=&r,X")) | |
5623 | (clobber (match_scratch:DI 3 "=b,X"))] | |
2ed4af6f | 5624 | "" |
599aedd9 | 5625 | "#" |
52e12ad0 | 5626 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5627 | |
599aedd9 RH |
5628 | ;; Irritatingly, we don't have access to INSN within the split body. |
5629 | ;; See commentary in ia64_split_call as to why these aren't peep2. | |
5630 | (define_split | |
5631 | [(call (mem (match_operand 0 "call_operand" "")) | |
5632 | (const_int 1)) | |
5633 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5634 | (clobber (match_scratch:DI 2 "")) | |
5635 | (clobber (match_scratch:DI 3 ""))] | |
5636 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5637 | [(const_int 0)] | |
5638 | { | |
5639 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5640 | operands[3], true, false); | |
5641 | DONE; | |
5642 | }) | |
5643 | ||
5644 | (define_split | |
5645 | [(call (mem (match_operand 0 "call_operand" "")) | |
5646 | (const_int 1)) | |
5647 | (clobber (match_operand:DI 1 "register_operand" "")) | |
5648 | (clobber (match_scratch:DI 2 "")) | |
5649 | (clobber (match_scratch:DI 3 ""))] | |
5650 | "reload_completed" | |
5651 | [(const_int 0)] | |
5652 | { | |
5653 | ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2], | |
5654 | operands[3], false, false); | |
5655 | DONE; | |
5656 | }) | |
5657 | ||
5658 | (define_insn "call_value_gp" | |
75293ad6 | 5659 | [(set (match_operand 0 "" "=X,X") |
599aedd9 RH |
5660 | (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i")) |
5661 | (const_int 1))) | |
5662 | (clobber (match_operand:DI 2 "register_operand" "=b,b")) | |
5663 | (clobber (match_scratch:DI 3 "=&r,X")) | |
5664 | (clobber (match_scratch:DI 4 "=b,X"))] | |
2ed4af6f | 5665 | "" |
599aedd9 | 5666 | "#" |
52e12ad0 | 5667 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f | 5668 | |
599aedd9 RH |
5669 | (define_split |
5670 | [(set (match_operand 0 "" "") | |
5671 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5672 | (const_int 1))) | |
5673 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5674 | (clobber (match_scratch:DI 3 "")) | |
5675 | (clobber (match_scratch:DI 4 ""))] | |
5676 | "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)" | |
5677 | [(const_int 0)] | |
5678 | { | |
5679 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5680 | operands[4], true, false); | |
5681 | DONE; | |
5682 | }) | |
5683 | ||
5684 | (define_split | |
5685 | [(set (match_operand 0 "" "") | |
5686 | (call (mem:DI (match_operand:DI 1 "call_operand" "")) | |
5687 | (const_int 1))) | |
5688 | (clobber (match_operand:DI 2 "register_operand" "")) | |
5689 | (clobber (match_scratch:DI 3 "")) | |
5690 | (clobber (match_scratch:DI 4 ""))] | |
5691 | "reload_completed" | |
5692 | [(const_int 0)] | |
5693 | { | |
5694 | ia64_split_call (operands[0], operands[1], operands[2], operands[3], | |
5695 | operands[4], false, false); | |
5696 | DONE; | |
5697 | }) | |
5698 | ||
5699 | (define_insn_and_split "sibcall_gp" | |
5700 | [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i")) | |
5701 | (const_int 1)) | |
5702 | (clobber (match_scratch:DI 1 "=&r,X")) | |
5703 | (clobber (match_scratch:DI 2 "=b,X"))] | |
2ed4af6f | 5704 | "" |
599aedd9 RH |
5705 | "#" |
5706 | "reload_completed" | |
5707 | [(const_int 0)] | |
5708 | { | |
5709 | ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1], | |
5710 | operands[2], true, true); | |
5711 | DONE; | |
5712 | } | |
52e12ad0 | 5713 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 5714 | |
c65ebc55 JW |
5715 | (define_insn "return_internal" |
5716 | [(return) | |
5717 | (use (match_operand:DI 0 "register_operand" "b"))] | |
5718 | "" | |
5719 | "br.ret.sptk.many %0" | |
52e12ad0 | 5720 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5721 | |
5722 | (define_insn "return" | |
5723 | [(return)] | |
5724 | "ia64_direct_return ()" | |
5725 | "br.ret.sptk.many rp" | |
52e12ad0 | 5726 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 5727 | |
6b6c1201 | 5728 | (define_insn "*return_true" |
c65ebc55 | 5729 | [(set (pc) |
6b6c1201 | 5730 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5731 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5732 | (const_int 0)]) |
c65ebc55 JW |
5733 | (return) |
5734 | (pc)))] | |
5735 | "ia64_direct_return ()" | |
13da91fd | 5736 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 5737 | [(set_attr "itanium_class" "br") |
e5bde68a | 5738 | (set_attr "predicable" "no")]) |
c65ebc55 | 5739 | |
6b6c1201 | 5740 | (define_insn "*return_false" |
c65ebc55 | 5741 | [(set (pc) |
6b6c1201 | 5742 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 5743 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 5744 | (const_int 0)]) |
c65ebc55 JW |
5745 | (pc) |
5746 | (return)))] | |
5747 | "ia64_direct_return ()" | |
13da91fd | 5748 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 5749 | [(set_attr "itanium_class" "br") |
e5bde68a | 5750 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
5751 | |
5752 | (define_insn "jump" | |
5753 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
5754 | "" | |
5755 | "br %l0" | |
52e12ad0 | 5756 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5757 | |
5758 | (define_insn "indirect_jump" | |
5759 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
5760 | "" | |
5761 | "br %0" | |
52e12ad0 | 5762 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5763 | |
5764 | (define_expand "tablejump" | |
340f7e7c RH |
5765 | [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" "")) |
5766 | (use (label_ref (match_operand 1 "" "")))])] | |
c65ebc55 | 5767 | "" |
c65ebc55 | 5768 | { |
340f7e7c RH |
5769 | rtx op0 = operands[0]; |
5770 | rtx addr; | |
5771 | ||
5772 | /* ??? Bother -- do_tablejump is "helpful" and pulls the table | |
5773 | element into a register without bothering to see whether that | |
5774 | is necessary given the operand predicate. Check for MEM just | |
5775 | in case someone fixes this. */ | |
5776 | if (GET_CODE (op0) == MEM) | |
5777 | addr = XEXP (op0, 0); | |
5778 | else | |
5779 | { | |
5780 | /* Otherwise, cheat and guess that the previous insn in the | |
5781 | stream was the memory load. Grab the address from that. | |
5782 | Note we have to momentarily pop out of the sequence started | |
5783 | by the insn-emit wrapper in order to grab the last insn. */ | |
5784 | rtx last, set; | |
5785 | ||
5786 | end_sequence (); | |
5787 | last = get_last_insn (); | |
5788 | start_sequence (); | |
5789 | set = single_set (last); | |
5790 | ||
5791 | if (! rtx_equal_p (SET_DEST (set), op0) | |
5792 | || GET_CODE (SET_SRC (set)) != MEM) | |
5793 | abort (); | |
5794 | addr = XEXP (SET_SRC (set), 0); | |
5795 | if (rtx_equal_p (addr, op0)) | |
5796 | abort (); | |
5797 | } | |
c65ebc55 | 5798 | |
340f7e7c RH |
5799 | /* Jump table elements are stored pc-relative. That is, a displacement |
5800 | from the entry to the label. Thus to convert to an absolute address | |
5801 | we add the address of the memory from which the value is loaded. */ | |
5802 | operands[0] = expand_simple_binop (DImode, PLUS, op0, addr, | |
5803 | NULL_RTX, 1, OPTAB_DIRECT); | |
5804 | }) | |
c65ebc55 | 5805 | |
340f7e7c | 5806 | (define_insn "*tablejump_internal" |
c65ebc55 JW |
5807 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) |
5808 | (use (label_ref (match_operand 1 "" "")))] | |
5809 | "" | |
5810 | "br %0" | |
52e12ad0 | 5811 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
5812 | |
5813 | \f | |
5814 | ;; :::::::::::::::::::: | |
5815 | ;; :: | |
5816 | ;; :: Prologue and Epilogue instructions | |
5817 | ;; :: | |
5818 | ;; :::::::::::::::::::: | |
5819 | ||
5820 | (define_expand "prologue" | |
5821 | [(const_int 1)] | |
5822 | "" | |
c65ebc55 JW |
5823 | { |
5824 | ia64_expand_prologue (); | |
5825 | DONE; | |
1d5d7a21 | 5826 | }) |
c65ebc55 JW |
5827 | |
5828 | (define_expand "epilogue" | |
2ed4af6f RH |
5829 | [(return)] |
5830 | "" | |
2ed4af6f RH |
5831 | { |
5832 | ia64_expand_epilogue (0); | |
5833 | DONE; | |
1d5d7a21 | 5834 | }) |
2ed4af6f RH |
5835 | |
5836 | (define_expand "sibcall_epilogue" | |
5837 | [(return)] | |
c65ebc55 | 5838 | "" |
c65ebc55 | 5839 | { |
2ed4af6f | 5840 | ia64_expand_epilogue (1); |
c65ebc55 | 5841 | DONE; |
1d5d7a21 | 5842 | }) |
c65ebc55 JW |
5843 | |
5844 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
5845 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
5846 | ||
5847 | (define_insn "prologue_allocate_stack" | |
5848 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
5849 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 5850 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
bdbe5b8d | 5851 | (set (match_operand:DI 3 "register_operand" "+r,r,r") |
c65ebc55 JW |
5852 | (match_dup 3))] |
5853 | "" | |
5854 | "@ | |
1d5d7a21 RH |
5855 | add %0 = %1, %2 |
5856 | adds %0 = %2, %1 | |
5857 | addl %0 = %2, %1" | |
52e12ad0 | 5858 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
5859 | |
5860 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
5861 | ;; stack accesses. This is similar to movdi plus the extra set. | |
5862 | ||
5863 | (define_insn "epilogue_deallocate_stack" | |
5864 | [(set (match_operand:DI 0 "register_operand" "=r") | |
5865 | (match_operand:DI 1 "register_operand" "+r")) | |
5866 | (set (match_dup 1) (match_dup 1))] | |
5867 | "" | |
5868 | "mov %0 = %1" | |
52e12ad0 | 5869 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 5870 | |
1d5d7a21 RH |
5871 | ;; As USE insns aren't meaningful after reload, this is used instead |
5872 | ;; to prevent deleting instructions setting registers for EH handling | |
5873 | (define_insn "prologue_use" | |
5874 | [(unspec:DI [(match_operand:DI 0 "register_operand" "")] | |
5875 | UNSPEC_PROLOGUE_USE)] | |
5876 | "" | |
5877 | "" | |
5878 | [(set_attr "itanium_class" "ignore") | |
fa978426 AS |
5879 | (set_attr "predicable" "no") |
5880 | (set_attr "empty" "yes")]) | |
1d5d7a21 | 5881 | |
c65ebc55 JW |
5882 | ;; Allocate a new register frame. |
5883 | ||
5884 | (define_insn "alloc" | |
5885 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5886 | (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC)) |
c65ebc55 JW |
5887 | (use (match_operand:DI 1 "const_int_operand" "i")) |
5888 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
5889 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
5890 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
5891 | "" | |
5892 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 5893 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 5894 | (set_attr "predicable" "no")]) |
c65ebc55 | 5895 | |
97e242b0 RH |
5896 | ;; Modifies ar.unat |
5897 | (define_expand "gr_spill" | |
870f9ec0 RH |
5898 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
5899 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
086c0f96 RH |
5900 | (match_operand:DI 2 "const_int_operand" "")] |
5901 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5902 | (clobber (match_dup 3))])] |
97e242b0 | 5903 | "" |
870f9ec0 | 5904 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5905 | |
870f9ec0 | 5906 | (define_insn "gr_spill_internal" |
c65ebc55 | 5907 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 | 5908 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
086c0f96 RH |
5909 | (match_operand:DI 2 "const_int_operand" "")] |
5910 | UNSPEC_GR_SPILL)) | |
870f9ec0 | 5911 | (clobber (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5912 | "" |
2130b7fb | 5913 | { |
1d5d7a21 RH |
5914 | /* Note that we use a C output pattern here to avoid the predicate |
5915 | being automatically added before the .mem.offset directive. */ | |
5916 | return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0"; | |
5917 | } | |
52e12ad0 | 5918 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 5919 | |
97e242b0 RH |
5920 | ;; Reads ar.unat |
5921 | (define_expand "gr_restore" | |
870f9ec0 RH |
5922 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
5923 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
086c0f96 RH |
5924 | (match_operand:DI 2 "const_int_operand" "")] |
5925 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5926 | (use (match_dup 3))])] |
97e242b0 | 5927 | "" |
870f9ec0 | 5928 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 5929 | |
870f9ec0 | 5930 | (define_insn "gr_restore_internal" |
c65ebc55 | 5931 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 | 5932 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
086c0f96 RH |
5933 | (match_operand:DI 2 "const_int_operand" "")] |
5934 | UNSPEC_GR_RESTORE)) | |
870f9ec0 | 5935 | (use (match_operand:DI 3 "register_operand" ""))] |
c65ebc55 | 5936 | "" |
1d5d7a21 | 5937 | { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; } |
52e12ad0 | 5938 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
5939 | |
5940 | (define_insn "fr_spill" | |
02befdf4 ZW |
5941 | [(set (match_operand:XF 0 "memory_operand" "=m") |
5942 | (unspec:XF [(match_operand:XF 1 "register_operand" "f")] | |
086c0f96 | 5943 | UNSPEC_FR_SPILL))] |
c65ebc55 JW |
5944 | "" |
5945 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 5946 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
5947 | |
5948 | (define_insn "fr_restore" | |
02befdf4 ZW |
5949 | [(set (match_operand:XF 0 "register_operand" "=f") |
5950 | (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] | |
086c0f96 | 5951 | UNSPEC_FR_RESTORE))] |
c65ebc55 JW |
5952 | "" |
5953 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 5954 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 5955 | |
0024a804 JW |
5956 | ;; ??? The explicit stop is not ideal. It would be better if |
5957 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5958 | ;; fixed later. This avoids an RSE DV. | |
5959 | ||
0c96007e AM |
5960 | (define_insn "bsp_value" |
5961 | [(set (match_operand:DI 0 "register_operand" "=r") | |
086c0f96 | 5962 | (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))] |
0c96007e | 5963 | "" |
582d11e6 JW |
5964 | "* |
5965 | { | |
5966 | return \";;\;%,mov %0 = ar.bsp\"; | |
5967 | }" | |
52e12ad0 | 5968 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
5969 | |
5970 | (define_insn "set_bsp" | |
086c0f96 RH |
5971 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
5972 | UNSPECV_SET_BSP)] | |
0c96007e | 5973 | "" |
1d5d7a21 RH |
5974 | "flushrs |
5975 | mov r19=ar.rsc | |
5976 | ;; | |
5977 | and r19=0x1c,r19 | |
5978 | ;; | |
5979 | mov ar.rsc=r19 | |
5980 | ;; | |
5981 | mov ar.bspstore=%0 | |
5982 | ;; | |
5983 | or r19=0x3,r19 | |
5984 | ;; | |
5985 | loadrs | |
5986 | invala | |
5987 | ;; | |
5988 | mov ar.rsc=r19" | |
52e12ad0 | 5989 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 5990 | (set_attr "predicable" "no")]) |
ce152ef8 | 5991 | |
0024a804 JW |
5992 | ;; ??? The explicit stops are not ideal. It would be better if |
5993 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
5994 | ;; fixed later. This avoids an RSE DV. | |
5995 | ||
ce152ef8 | 5996 | (define_insn "flushrs" |
086c0f96 | 5997 | [(unspec [(const_int 0)] UNSPEC_FLUSHRS)] |
ce152ef8 | 5998 | "" |
0024a804 | 5999 | ";;\;flushrs\;;;" |
582d11e6 JW |
6000 | [(set_attr "itanium_class" "rse_m") |
6001 | (set_attr "predicable" "no")]) | |
c65ebc55 JW |
6002 | \f |
6003 | ;; :::::::::::::::::::: | |
6004 | ;; :: | |
6005 | ;; :: Miscellaneous instructions | |
6006 | ;; :: | |
6007 | ;; :::::::::::::::::::: | |
6008 | ||
839a4992 | 6009 | ;; ??? Emitting a NOP instruction isn't very useful. This should probably |
c65ebc55 JW |
6010 | ;; be emitting ";;" to force a break in the instruction packing. |
6011 | ||
6012 | ;; No operation, needed in case the user uses -g but not -O. | |
6013 | (define_insn "nop" | |
6014 | [(const_int 0)] | |
6015 | "" | |
6016 | "nop 0" | |
30028c85 | 6017 | [(set_attr "itanium_class" "nop")]) |
c65ebc55 | 6018 | |
2130b7fb BS |
6019 | (define_insn "nop_m" |
6020 | [(const_int 1)] | |
6021 | "" | |
6022 | "nop.m 0" | |
6023 | [(set_attr "itanium_class" "nop_m")]) | |
6024 | ||
6025 | (define_insn "nop_i" | |
6026 | [(const_int 2)] | |
6027 | "" | |
6028 | "nop.i 0" | |
6029 | [(set_attr "itanium_class" "nop_i")]) | |
6030 | ||
6031 | (define_insn "nop_f" | |
6032 | [(const_int 3)] | |
6033 | "" | |
6034 | "nop.f 0" | |
6035 | [(set_attr "itanium_class" "nop_f")]) | |
6036 | ||
6037 | (define_insn "nop_b" | |
6038 | [(const_int 4)] | |
6039 | "" | |
6040 | "nop.b 0" | |
6041 | [(set_attr "itanium_class" "nop_b")]) | |
6042 | ||
6043 | (define_insn "nop_x" | |
6044 | [(const_int 5)] | |
6045 | "" | |
6046 | "" | |
fa978426 AS |
6047 | [(set_attr "itanium_class" "nop_x") |
6048 | (set_attr "empty" "yes")]) | |
2130b7fb | 6049 | |
30028c85 VM |
6050 | ;; The following insn will be never generated. It is used only by |
6051 | ;; insn scheduler to change state before advancing cycle. | |
6052 | (define_insn "pre_cycle" | |
6053 | [(const_int 6)] | |
6054 | "" | |
6055 | "" | |
6056 | [(set_attr "itanium_class" "pre_cycle")]) | |
6057 | ||
2130b7fb | 6058 | (define_insn "bundle_selector" |
086c0f96 | 6059 | [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)] |
2130b7fb | 6060 | "" |
1d5d7a21 | 6061 | { return get_bundle_name (INTVAL (operands[0])); } |
2130b7fb BS |
6062 | [(set_attr "itanium_class" "ignore") |
6063 | (set_attr "predicable" "no")]) | |
6064 | ||
c65ebc55 JW |
6065 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
6066 | ;; point. | |
6067 | (define_insn "blockage" | |
086c0f96 | 6068 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
c65ebc55 JW |
6069 | "" |
6070 | "" | |
52e12ad0 | 6071 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 6072 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
6073 | |
6074 | (define_insn "insn_group_barrier" | |
086c0f96 RH |
6075 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] |
6076 | UNSPECV_INSN_GROUP_BARRIER)] | |
c65ebc55 JW |
6077 | "" |
6078 | ";;" | |
52e12ad0 | 6079 | [(set_attr "itanium_class" "stop_bit") |
fa978426 AS |
6080 | (set_attr "predicable" "no") |
6081 | (set_attr "empty" "yes")]) | |
c65ebc55 | 6082 | |
26406018 RH |
6083 | (define_expand "trap" |
6084 | [(trap_if (const_int 1) (const_int 0))] | |
6085 | "" | |
6086 | "") | |
6087 | ||
6088 | ;; ??? We don't have a match-any slot type. Setting the type to unknown | |
6089 | ;; produces worse code that setting the slot type to A. | |
6090 | ||
6091 | (define_insn "*trap" | |
6092 | [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))] | |
6093 | "" | |
6094 | "break %0" | |
6095 | [(set_attr "itanium_class" "chk_s")]) | |
6096 | ||
6097 | (define_expand "conditional_trap" | |
6098 | [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))] | |
6099 | "" | |
6100 | { | |
6101 | operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode); | |
6102 | }) | |
6103 | ||
6104 | (define_insn "*conditional_trap" | |
6105 | [(trap_if (match_operator 0 "predicate_operator" | |
6106 | [(match_operand:BI 1 "register_operand" "c") | |
6107 | (const_int 0)]) | |
6108 | (match_operand 2 "const_int_operand" ""))] | |
6109 | "" | |
5cf63e3f | 6110 | "(%J0) break %2" |
26406018 RH |
6111 | [(set_attr "itanium_class" "chk_s") |
6112 | (set_attr "predicable" "no")]) | |
6113 | ||
f12f25a7 | 6114 | (define_insn "break_f" |
086c0f96 | 6115 | [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)] |
f12f25a7 RH |
6116 | "" |
6117 | "break.f 0" | |
6118 | [(set_attr "itanium_class" "nop_f")]) | |
44eca121 JJ |
6119 | |
6120 | (define_insn "prefetch" | |
6121 | [(prefetch (match_operand:DI 0 "address_operand" "p") | |
6122 | (match_operand:DI 1 "const_int_operand" "n") | |
6123 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6124 | "" | |
6125 | { | |
6126 | static const char * const alt[2][4] = { | |
b3656137 | 6127 | { |
92cbea22 L |
6128 | "%,lfetch.nta [%0]", |
6129 | "%,lfetch.nt1 [%0]", | |
6130 | "%,lfetch.nt2 [%0]", | |
6131 | "%,lfetch [%0]" | |
b3656137 KG |
6132 | }, |
6133 | { | |
92cbea22 L |
6134 | "%,lfetch.excl.nta [%0]", |
6135 | "%,lfetch.excl.nt1 [%0]", | |
6136 | "%,lfetch.excl.nt2 [%0]", | |
6137 | "%,lfetch.excl [%0]" | |
b3656137 | 6138 | } |
44eca121 JJ |
6139 | }; |
6140 | int i = (INTVAL (operands[1])); | |
6141 | int j = (INTVAL (operands[2])); | |
6142 | ||
6143 | if (i != 0 && i != 1) | |
6144 | abort (); | |
6145 | if (j < 0 || j > 3) | |
6146 | abort (); | |
6147 | return alt[i][j]; | |
6148 | } | |
6149 | [(set_attr "itanium_class" "lfetch")]) | |
c65ebc55 JW |
6150 | \f |
6151 | ;; Non-local goto support. | |
6152 | ||
6153 | (define_expand "save_stack_nonlocal" | |
6154 | [(use (match_operand:OI 0 "memory_operand" "")) | |
6155 | (use (match_operand:DI 1 "register_operand" ""))] | |
6156 | "" | |
c65ebc55 JW |
6157 | { |
6158 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
6159 | \"__ia64_save_stack_nonlocal\"), | |
6160 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
6161 | operands[1], Pmode); | |
6162 | DONE; | |
1d5d7a21 | 6163 | }) |
c65ebc55 JW |
6164 | |
6165 | (define_expand "nonlocal_goto" | |
6166 | [(use (match_operand 0 "general_operand" "")) | |
6167 | (use (match_operand 1 "general_operand" "")) | |
6168 | (use (match_operand 2 "general_operand" "")) | |
6169 | (use (match_operand 3 "general_operand" ""))] | |
6170 | "" | |
c65ebc55 | 6171 | { |
c65ebc55 | 6172 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 | 6173 | LCT_NORETURN, VOIDmode, 3, |
7c2b017c | 6174 | operands[1], Pmode, |
c65ebc55 | 6175 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
7c2b017c | 6176 | operands[3], Pmode); |
c65ebc55 JW |
6177 | emit_barrier (); |
6178 | DONE; | |
1d5d7a21 | 6179 | }) |
c65ebc55 | 6180 | |
b39eb2f9 RH |
6181 | (define_insn_and_split "builtin_setjmp_receiver" |
6182 | [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)] | |
97e242b0 | 6183 | "" |
b39eb2f9 RH |
6184 | "#" |
6185 | "reload_completed" | |
6186 | [(const_int 0)] | |
97e242b0 | 6187 | { |
599aedd9 | 6188 | ia64_reload_gp (); |
c65ebc55 | 6189 | DONE; |
1d5d7a21 | 6190 | }) |
c65ebc55 | 6191 | |
0c96007e AM |
6192 | (define_expand "eh_epilogue" |
6193 | [(use (match_operand:DI 0 "register_operand" "r")) | |
6194 | (use (match_operand:DI 1 "register_operand" "r")) | |
6195 | (use (match_operand:DI 2 "register_operand" "r"))] | |
6196 | "" | |
0c96007e AM |
6197 | { |
6198 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
6199 | rtx sp = gen_rtx_REG (Pmode, 9); | |
6200 | ||
6201 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
6202 | { | |
6203 | emit_move_insn (bsp, operands[0]); | |
6204 | operands[0] = bsp; | |
6205 | } | |
6206 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
6207 | { | |
6208 | emit_move_insn (sp, operands[2]); | |
6209 | operands[2] = sp; | |
6210 | } | |
6211 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
6212 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
6213 | ||
6214 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
6215 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
1d5d7a21 | 6216 | }) |
9525c690 JW |
6217 | \f |
6218 | ;; Builtin apply support. | |
6219 | ||
6220 | (define_expand "restore_stack_nonlocal" | |
6221 | [(use (match_operand:DI 0 "register_operand" "")) | |
6222 | (use (match_operand:OI 1 "memory_operand" ""))] | |
6223 | "" | |
9525c690 JW |
6224 | { |
6225 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
1d5d7a21 | 6226 | "__ia64_restore_stack_nonlocal"), |
9525c690 JW |
6227 | 0, VOIDmode, 1, |
6228 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
6229 | DONE; | |
1d5d7a21 | 6230 | }) |
9525c690 JW |
6231 | |
6232 | \f | |
6233 | ;;; Intrinsics support. | |
c65ebc55 | 6234 | |
0551c32d RH |
6235 | (define_expand "mf" |
6236 | [(set (mem:BLK (match_dup 0)) | |
086c0f96 | 6237 | (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))] |
0551c32d | 6238 | "" |
0551c32d RH |
6239 | { |
6240 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
6241 | MEM_VOLATILE_P (operands[0]) = 1; | |
1d5d7a21 | 6242 | }) |
0551c32d RH |
6243 | |
6244 | (define_insn "*mf_internal" | |
6245 | [(set (match_operand:BLK 0 "" "") | |
086c0f96 | 6246 | (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))] |
c65ebc55 JW |
6247 | "" |
6248 | "mf" | |
52e12ad0 | 6249 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
6250 | |
6251 | (define_insn "fetchadd_acq_si" | |
0551c32d | 6252 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
e7f47f83 ZW |
6253 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) |
6254 | (set (match_dup 1) | |
0551c32d | 6255 | (unspec:SI [(match_dup 1) |
086c0f96 RH |
6256 | (match_operand:SI 2 "fetchadd_operand" "n")] |
6257 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
6258 | "" |
6259 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 6260 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
6261 | |
6262 | (define_insn "fetchadd_acq_di" | |
0551c32d | 6263 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
e7f47f83 ZW |
6264 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) |
6265 | (set (match_dup 1) | |
0551c32d | 6266 | (unspec:DI [(match_dup 1) |
086c0f96 RH |
6267 | (match_operand:DI 2 "fetchadd_operand" "n")] |
6268 | UNSPEC_FETCHADD_ACQ))] | |
c65ebc55 JW |
6269 | "" |
6270 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 6271 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
6272 | |
6273 | (define_insn "cmpxchg_acq_si" | |
0551c32d | 6274 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
e7f47f83 ZW |
6275 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) |
6276 | (set (match_dup 1) | |
0551c32d RH |
6277 | (unspec:SI [(match_dup 1) |
6278 | (match_operand:SI 2 "gr_register_operand" "r") | |
5634cf72 | 6279 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] |
086c0f96 | 6280 | UNSPEC_CMPXCHG_ACQ))] |
c65ebc55 | 6281 | "" |
97e242b0 | 6282 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 6283 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
6284 | |
6285 | (define_insn "cmpxchg_acq_di" | |
0551c32d | 6286 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
e7f47f83 ZW |
6287 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) |
6288 | (set (match_dup 1) | |
0551c32d RH |
6289 | (unspec:DI [(match_dup 1) |
6290 | (match_operand:DI 2 "gr_register_operand" "r") | |
086c0f96 RH |
6291 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] |
6292 | UNSPEC_CMPXCHG_ACQ))] | |
c65ebc55 | 6293 | "" |
97e242b0 | 6294 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 6295 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 6296 | |
c65ebc55 | 6297 | (define_insn "xchgsi" |
0551c32d RH |
6298 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
6299 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 6300 | (set (match_dup 1) |
0551c32d | 6301 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
6302 | "" |
6303 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 6304 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
6305 | |
6306 | (define_insn "xchgdi" | |
0551c32d RH |
6307 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6308 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 6309 | (set (match_dup 1) |
0551c32d | 6310 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
6311 | "" |
6312 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 6313 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
6314 | \f |
6315 | ;; Predication. | |
6316 | ||
6317 | (define_cond_exec | |
6318 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 6319 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
6320 | (const_int 0)])] |
6321 | "" | |
6322 | "(%J0)") | |
3b572406 RH |
6323 | |
6324 | (define_insn "pred_rel_mutex" | |
f2f90c63 | 6325 | [(set (match_operand:BI 0 "register_operand" "+c") |
086c0f96 | 6326 | (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))] |
3b572406 | 6327 | "" |
054451ea | 6328 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 6329 | [(set_attr "itanium_class" "ignore") |
3b572406 | 6330 | (set_attr "predicable" "no")]) |
ca3920ad JW |
6331 | |
6332 | (define_insn "safe_across_calls_all" | |
086c0f96 | 6333 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)] |
ca3920ad JW |
6334 | "" |
6335 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 6336 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6337 | (set_attr "predicable" "no")]) |
6338 | ||
6339 | (define_insn "safe_across_calls_normal" | |
086c0f96 | 6340 | [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)] |
ca3920ad | 6341 | "" |
ca3920ad | 6342 | { |
1bc7c5b6 | 6343 | emit_safe_across_calls (); |
1d5d7a21 RH |
6344 | return ""; |
6345 | } | |
52e12ad0 | 6346 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
6347 | (set_attr "predicable" "no")]) |
6348 | ||
6dd12198 SE |
6349 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit |
6350 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
6351 | ||
6352 | (define_insn "ptr_extend" | |
6353 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
086c0f96 RH |
6354 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] |
6355 | UNSPEC_ADDP4))] | |
6dd12198 SE |
6356 | "" |
6357 | "addp4 %0 = 0,%1" | |
6358 | [(set_attr "itanium_class" "ialu")]) | |
6359 | ||
e206a74f SE |
6360 | ;; |
6361 | ;; Optimizations for ptr_extend | |
6362 | ||
36c216e5 | 6363 | (define_insn "ptr_extend_plus_imm" |
e206a74f SE |
6364 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
6365 | (unspec:DI | |
6366 | [(plus:SI (match_operand:SI 1 "basereg_operand" "r") | |
6367 | (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))] | |
086c0f96 | 6368 | UNSPEC_ADDP4))] |
08744705 | 6369 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6370 | "addp4 %0 = %2, %1" |
6371 | [(set_attr "itanium_class" "ialu")]) | |
6372 | ||
6373 | (define_insn "*ptr_extend_plus_2" | |
6374 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
6375 | (unspec:DI | |
6376 | [(plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
6377 | (match_operand:SI 2 "basereg_operand" "r"))] | |
086c0f96 | 6378 | UNSPEC_ADDP4))] |
08744705 | 6379 | "addp4_optimize_ok (operands[1], operands[2])" |
e206a74f SE |
6380 | "addp4 %0 = %1, %2" |
6381 | [(set_attr "itanium_class" "ialu")]) |