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c65ebc55 | 1 | ;; IA-64 Machine description template |
f4ef873c | 2 | ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. |
c65ebc55 JW |
3 | ;; Contributed by James E. Wilson <wilson@cygnus.com> and |
4 | ;; David Mosberger <davidm@hpl.hp.com>. | |
5 | ||
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | ;; Boston, MA 02111-1307, USA. | |
22 | ||
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
24 | ||
c65ebc55 JW |
25 | ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later |
26 | ;; reload. This will be fixed once scheduling support is turned on. | |
27 | ||
28 | ;; ??? Optimize for post-increment addressing modes. | |
29 | ||
30 | ;; ??? fselect is not supported, because there is no integer register | |
31 | ;; equivalent. | |
32 | ||
33 | ;; ??? fp abs/min/max instructions may also work for integer values. | |
34 | ||
35 | ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy, | |
36 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
37 | ||
38 | ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy, | |
39 | ;; it assumes the operand is a register and takes REGNO of it without checking. | |
40 | ||
41 | ;; ??? Go through list of documented named patterns and look for more to | |
42 | ;; implement. | |
43 | ||
44 | ;; ??? Go through instruction manual and look for more instructions that | |
45 | ;; can be emitted. | |
46 | ||
47 | ;; ??? Add function unit scheduling info for Itanium (TM) processor. | |
48 | ||
26102535 RH |
49 | ;; ??? Need a better way to describe alternate fp status registers. |
50 | ||
e5bde68a RH |
51 | ;; Unspec usage: |
52 | ;; | |
53 | ;; unspec: | |
54 | ;; 1 gr_spill | |
55 | ;; 2 gr_restore | |
56 | ;; 3 fr_spill | |
57 | ;; 4 fr_restore | |
655f2eb9 | 58 | ;; 5 recip_approx |
f2f90c63 | 59 | ;; 7 pred_rel_mutex |
e5bde68a | 60 | ;; 8 popcnt |
2ed4af6f | 61 | ;; 9 pic call |
97e242b0 | 62 | ;; 12 mf |
e5bde68a | 63 | ;; 13 cmpxchg_acq |
e5bde68a RH |
64 | ;; 19 fetchadd_acq |
65 | ;; 20 bsp_value | |
ce152ef8 | 66 | ;; 21 flushrs |
2130b7fb BS |
67 | ;; 22 bundle selector |
68 | ;; 23 cycle display | |
6dd12198 | 69 | ;; 24 addp4 |
e5bde68a RH |
70 | ;; |
71 | ;; unspec_volatile: | |
72 | ;; 0 alloc | |
73 | ;; 1 blockage | |
74 | ;; 2 insn_group_barrier | |
f12f25a7 | 75 | ;; 3 break |
e5bde68a | 76 | ;; 5 set_bsp |
ca3920ad JW |
77 | ;; 8 pred.safe_across_calls all |
78 | ;; 9 pred.safe_across_calls normal | |
c65ebc55 JW |
79 | \f |
80 | ;; :::::::::::::::::::: | |
81 | ;; :: | |
82 | ;; :: Attributes | |
83 | ;; :: | |
84 | ;; :::::::::::::::::::: | |
85 | ||
86 | ;; Instruction type. This primarily determines how instructions can be | |
87 | ;; packed in bundles, and secondarily affects scheduling to function units. | |
88 | ||
89 | ;; A alu, can go in I or M syllable of a bundle | |
90 | ;; I integer | |
91 | ;; M memory | |
92 | ;; F floating-point | |
93 | ;; B branch | |
94 | ;; L long immediate, takes two syllables | |
95 | ;; S stop bit | |
96 | ||
97 | ;; ??? Should not have any pattern with type unknown. Perhaps add code to | |
98 | ;; check this in md_reorg? Currently use unknown for patterns which emit | |
99 | ;; multiple instructions, patterns which emit 0 instructions, and patterns | |
100 | ;; which emit instruction that can go in any slot (e.g. nop). | |
101 | ||
2130b7fb | 102 | (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x" |
52e12ad0 BS |
103 | (const_string "unknown")) |
104 | ||
2130b7fb BS |
105 | ;; chk_s has an I and an M form; use type A for convenience. |
106 | (define_attr "type" "unknown,A,I,M,F,B,L,X,S" | |
107 | (cond [(eq_attr "itanium_class" "ld,st,fld,stf,sem,nop_m") (const_string "M") | |
52e12ad0 BS |
108 | (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M") |
109 | (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M") | |
2130b7fb BS |
110 | (eq_attr "itanium_class" "chk_s,ialu,icmp,ilog") (const_string "A") |
111 | (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F") | |
112 | (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F") | |
52e12ad0 BS |
113 | (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I") |
114 | (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I") | |
2130b7fb BS |
115 | (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I") |
116 | (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B") | |
52e12ad0 | 117 | (eq_attr "itanium_class" "stop_bit") (const_string "S") |
2130b7fb | 118 | (eq_attr "itanium_class" "nop_x") (const_string "X") |
52e12ad0 BS |
119 | (eq_attr "itanium_class" "long_i") (const_string "L")] |
120 | (const_string "unknown"))) | |
c65ebc55 | 121 | |
2130b7fb BS |
122 | (define_attr "itanium_requires_unit0" "no,yes" |
123 | (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes") | |
124 | (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes") | |
125 | (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes") | |
126 | (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes") | |
127 | (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes") | |
128 | (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")] | |
129 | (const_string "no"))) | |
130 | ||
e5bde68a RH |
131 | ;; Predication. True iff this instruction can be predicated. |
132 | ||
133 | (define_attr "predicable" "no,yes" (const_string "yes")) | |
134 | ||
c65ebc55 JW |
135 | \f |
136 | ;; :::::::::::::::::::: | |
137 | ;; :: | |
138 | ;; :: Function Units | |
139 | ;; :: | |
140 | ;; :::::::::::::::::::: | |
141 | ||
2130b7fb BS |
142 | ;; We define 6 "dummy" functional units. All the real work to decide which |
143 | ;; insn uses which unit is done by our MD_SCHED_REORDER hooks. We only | |
144 | ;; have to ensure here that there are enough copies of the dummy unit so | |
145 | ;; that the scheduler doesn't get confused by MD_SCHED_REORDER. | |
146 | ;; Other than the 6 dummies for normal insns, we also add a single dummy unit | |
147 | ;; for stop bits. | |
148 | ||
149 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "br") 0 0) | |
150 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "scall") 0 0) | |
151 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcmp") 2 0) | |
152 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fcvtfx") 7 0) | |
153 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fld") 9 0) | |
154 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmac") 5 0) | |
155 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "fmisc") 5 0) | |
156 | ||
157 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
158 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_i") 13 0) | |
159 | ;; There is only ony insn `mov = ar.unat' for frar_m: | |
160 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frar_m") 6 0) | |
161 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frbr") 2 0) | |
162 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frfr") 2 0) | |
163 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "frpr") 2 0) | |
164 | ||
165 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ialu") 1 0) | |
166 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "icmp") 1 0) | |
167 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ilog") 1 0) | |
168 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ishf") 1 0) | |
169 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ld") 2 0) | |
170 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "long_i") 1 0) | |
171 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmmul") 2 0) | |
172 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshf") 2 0) | |
173 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "mmshfi") 2 0) | |
174 | ||
175 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
176 | ;; is the 1st syllable of the bundle after stop bit. | |
177 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "rse_m") 0 0) | |
178 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "sem") 11 0) | |
179 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "stf") 1 0) | |
180 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "st") 1 0) | |
181 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m0") 1 0) | |
182 | ;; Now we use only one insn `mf'. Therfore latency time is set up to 0. | |
183 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "syst_m") 0 0) | |
184 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tbit") 1 0) | |
185 | ||
186 | ;; There is only one insn `mov ar.pfs =' for toar_i therefore we use | |
187 | ;; latency time equal to 0: | |
188 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_i") 0 0) | |
189 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
190 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "toar_m") 5 0) | |
191 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tobr") 1 0) | |
192 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "tofr") 9 0) | |
193 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "topr") 1 0) | |
194 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xmpy") 7 0) | |
195 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "xtd") 1 0) | |
196 | ||
197 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_m") 0 0) | |
198 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_i") 0 0) | |
199 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_f") 0 0) | |
200 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_b") 0 0) | |
201 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "nop_x") 0 0) | |
202 | ||
203 | (define_function_unit "stop_bit" 1 1 (eq_attr "itanium_class" "stop_bit") 0 0) | |
204 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "ignore") 0 0) | |
205 | (define_function_unit "dummy" 6 1 (eq_attr "itanium_class" "unknown") 0 0) | |
c65ebc55 JW |
206 | \f |
207 | ;; :::::::::::::::::::: | |
208 | ;; :: | |
209 | ;; :: Moves | |
210 | ;; :: | |
211 | ;; :::::::::::::::::::: | |
212 | ||
f2f90c63 RH |
213 | ;; Set of a single predicate register. This is only used to implement |
214 | ;; pr-to-pr move and complement. | |
215 | ||
216 | (define_insn "*movcci" | |
217 | [(set (match_operand:CCI 0 "register_operand" "=c,c,c") | |
218 | (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))] | |
219 | "" | |
220 | "@ | |
221 | cmp.ne %0, p0 = r0, r0 | |
222 | cmp.eq %0, p0 = r0, r0 | |
223 | (%1) cmp.eq.unc %0, p0 = r0, r0" | |
52e12ad0 | 224 | [(set_attr "itanium_class" "icmp") |
f2f90c63 RH |
225 | (set_attr "predicable" "no")]) |
226 | ||
227 | (define_insn "movbi" | |
cd5c4048 RH |
228 | [(set (match_operand:BI 0 "nonimmediate_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r") |
229 | (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))] | |
f2f90c63 RH |
230 | "" |
231 | "@ | |
232 | cmp.ne %0, %I0 = r0, r0 | |
233 | cmp.eq %0, %I0 = r0, r0 | |
234 | # | |
235 | # | |
236 | tbit.nz %0, %I0 = %1, 0 | |
237 | adds %0 = %1, r0 | |
238 | ld1%O1 %0 = %1%P1 | |
cd5c4048 RH |
239 | st1%Q0 %0 = %1%P0 |
240 | mov %0 = %1" | |
52e12ad0 | 241 | [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")]) |
f2f90c63 RH |
242 | |
243 | (define_split | |
244 | [(set (match_operand:BI 0 "register_operand" "") | |
245 | (match_operand:BI 1 "register_operand" ""))] | |
246 | "reload_completed | |
247 | && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0])) | |
248 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
249 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
250 | (set (match_dup 0) (const_int 1))) | |
251 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
252 | (set (match_dup 0) (const_int 0)))] | |
253 | "") | |
254 | ||
255 | (define_split | |
256 | [(set (match_operand:BI 0 "register_operand" "") | |
257 | (match_operand:BI 1 "register_operand" ""))] | |
258 | "reload_completed | |
259 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
260 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))" | |
261 | [(set (match_dup 2) (match_dup 4)) | |
262 | (set (match_dup 3) (match_dup 5)) | |
263 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
264 | "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0])); | |
265 | operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1); | |
266 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
267 | operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);") | |
268 | ||
c65ebc55 JW |
269 | (define_expand "movqi" |
270 | [(set (match_operand:QI 0 "general_operand" "") | |
271 | (match_operand:QI 1 "general_operand" ""))] | |
272 | "" | |
273 | " | |
274 | { | |
275 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
276 | && ! ia64_move_ok (operands[0], operands[1])) |
277 | operands[1] = force_reg (QImode, operands[1]); | |
c65ebc55 JW |
278 | }") |
279 | ||
280 | (define_insn "*movqi_internal" | |
4b983fdc RH |
281 | [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
282 | (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 283 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 284 | "@ |
13da91fd | 285 | mov %0 = %r1 |
c65ebc55 JW |
286 | addl %0 = %1, r0 |
287 | ld1%O1 %0 = %1%P1 | |
13da91fd | 288 | st1%Q0 %0 = %r1%P0 |
c65ebc55 | 289 | getf.sig %0 = %1 |
13da91fd RH |
290 | setf.sig %0 = %r1 |
291 | mov %0 = %1" | |
52e12ad0 | 292 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
293 | |
294 | (define_expand "movhi" | |
295 | [(set (match_operand:HI 0 "general_operand" "") | |
296 | (match_operand:HI 1 "general_operand" ""))] | |
297 | "" | |
298 | " | |
299 | { | |
300 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
301 | && ! ia64_move_ok (operands[0], operands[1])) |
302 | operands[1] = force_reg (HImode, operands[1]); | |
c65ebc55 JW |
303 | }") |
304 | ||
305 | (define_insn "*movhi_internal" | |
4b983fdc RH |
306 | [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f") |
307 | (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))] | |
aebf2462 | 308 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 309 | "@ |
13da91fd | 310 | mov %0 = %r1 |
c65ebc55 JW |
311 | addl %0 = %1, r0 |
312 | ld2%O1 %0 = %1%P1 | |
13da91fd | 313 | st2%Q0 %0 = %r1%P0 |
c65ebc55 | 314 | getf.sig %0 = %1 |
13da91fd RH |
315 | setf.sig %0 = %r1 |
316 | mov %0 = %1" | |
52e12ad0 | 317 | [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")]) |
c65ebc55 JW |
318 | |
319 | (define_expand "movsi" | |
320 | [(set (match_operand:SI 0 "general_operand" "") | |
321 | (match_operand:SI 1 "general_operand" ""))] | |
322 | "" | |
323 | " | |
324 | { | |
325 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
326 | && ! ia64_move_ok (operands[0], operands[1])) |
327 | operands[1] = force_reg (SImode, operands[1]); | |
c65ebc55 JW |
328 | }") |
329 | ||
330 | (define_insn "*movsi_internal" | |
97e242b0 | 331 | [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d") |
514f96e6 | 332 | (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f,*d,rK"))] |
aebf2462 | 333 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 | 334 | "@ |
13da91fd | 335 | mov %0 = %r1 |
c65ebc55 JW |
336 | addl %0 = %1, r0 |
337 | movl %0 = %1 | |
338 | ld4%O1 %0 = %1%P1 | |
13da91fd | 339 | st4%Q0 %0 = %r1%P0 |
c65ebc55 | 340 | getf.sig %0 = %1 |
13da91fd | 341 | setf.sig %0 = %r1 |
97e242b0 RH |
342 | mov %0 = %1 |
343 | mov %0 = %1 | |
344 | mov %0 = %r1" | |
52e12ad0 BS |
345 | ;; frar_m, toar_m ??? why not frar_i and toar_i |
346 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")]) | |
c65ebc55 JW |
347 | |
348 | (define_expand "movdi" | |
349 | [(set (match_operand:DI 0 "general_operand" "") | |
350 | (match_operand:DI 1 "general_operand" ""))] | |
351 | "" | |
352 | " | |
353 | { | |
9a89adb8 RH |
354 | if (! reload_in_progress && ! reload_completed |
355 | && ! ia64_move_ok (operands[0], operands[1])) | |
356 | operands[1] = force_reg (DImode, operands[1]); | |
ec039e3c | 357 | if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode)) |
c65ebc55 | 358 | { |
9a89adb8 RH |
359 | /* Before optimization starts, delay committing to any particular |
360 | type of PIC address load. If this function gets deferred, we | |
361 | may acquire information that changes the value of the | |
362 | sdata_symbolic_operand predicate. */ | |
7c866fb5 JW |
363 | /* But don't delay for function pointers. Loading a function address |
364 | actually loads the address of the descriptor not the function. | |
365 | If we represent these as SYMBOL_REFs, then they get cse'd with | |
366 | calls, and we end up with calls to the descriptor address instead of | |
367 | calls to the function address. Functions are not candidates for | |
368 | sdata anyways. */ | |
369 | if (rtx_equal_function_value_matters | |
370 | && ! (GET_CODE (operands[1]) == SYMBOL_REF | |
371 | && SYMBOL_REF_FLAG (operands[1]))) | |
b5d37c6f | 372 | emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode))); |
9a89adb8 | 373 | else |
b5d37c6f | 374 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d | 375 | DONE; |
c65ebc55 | 376 | } |
c65ebc55 JW |
377 | }") |
378 | ||
9a89adb8 RH |
379 | ;; This is used during early compilation to delay the decision on |
380 | ;; how to refer to a variable as long as possible. This is especially | |
381 | ;; important between initial rtl generation and optimization for | |
382 | ;; deferred functions, since we may acquire additional information | |
383 | ;; on the variables used in the meantime. | |
384 | ||
ef375129 JW |
385 | ;; ??? This causes us to lose REG_LABEL notes, because the insn splitter |
386 | ;; does not attempt to preserve any REG_NOTES on the input instruction. | |
387 | ||
9a89adb8 RH |
388 | (define_insn_and_split "movdi_symbolic" |
389 | [(set (match_operand:DI 0 "register_operand" "=r") | |
390 | (match_operand:DI 1 "symbolic_operand" "s")) | |
b5d37c6f | 391 | (clobber (match_operand:DI 2 "register_operand" "+r")) |
9a89adb8 RH |
392 | (use (reg:DI 1))] |
393 | "" | |
394 | "* abort ();" | |
395 | "" | |
396 | [(const_int 0)] | |
b5d37c6f | 397 | "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;") |
9a89adb8 | 398 | |
c65ebc55 | 399 | (define_insn "*movdi_internal" |
4b983fdc | 400 | [(set (match_operand:DI 0 "destination_operand" |
52e12ad0 | 401 | "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c") |
4b983fdc | 402 | (match_operand:DI 1 "move_operand" |
52e12ad0 | 403 | "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))] |
aebf2462 | 404 | "ia64_move_ok (operands[0], operands[1])" |
9b7bf67d RH |
405 | "* |
406 | { | |
407 | static const char * const alt[] = { | |
6f8aa100 RH |
408 | \"%,mov %0 = %r1\", |
409 | \"%,addl %0 = %1, r0\", | |
410 | \"%,movl %0 = %1\", | |
411 | \"%,ld8%O1 %0 = %1%P1\", | |
412 | \"%,st8%Q0 %0 = %r1%P0\", | |
413 | \"%,getf.sig %0 = %1\", | |
414 | \"%,setf.sig %0 = %r1\", | |
415 | \"%,mov %0 = %1\", | |
416 | \"%,ldf8 %0 = %1%P1\", | |
417 | \"%,stf8 %0 = %1%P0\", | |
418 | \"%,mov %0 = %1\", | |
5527bf14 RH |
419 | \"%,mov %0 = %r1\", |
420 | \"%,mov %0 = %1\", | |
514f96e6 RH |
421 | \"%,mov %0 = %1\", |
422 | \"%,mov %0 = %1\", | |
52e12ad0 | 423 | \"%,mov %0 = %1\", |
97e242b0 RH |
424 | \"mov %0 = pr\", |
425 | \"mov pr = %1, -1\" | |
9b7bf67d RH |
426 | }; |
427 | ||
9b7bf67d RH |
428 | if (which_alternative == 2 && ! TARGET_NO_PIC |
429 | && symbolic_operand (operands[1], VOIDmode)) | |
430 | abort (); | |
431 | ||
432 | return alt[which_alternative]; | |
433 | }" | |
52e12ad0 | 434 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")]) |
c65ebc55 | 435 | |
9b7bf67d RH |
436 | (define_split |
437 | [(set (match_operand:DI 0 "register_operand" "") | |
438 | (match_operand:DI 1 "symbolic_operand" ""))] | |
439 | "reload_completed && ! TARGET_NO_PIC" | |
440 | [(const_int 0)] | |
441 | " | |
442 | { | |
b5d37c6f | 443 | ia64_expand_load_address (operands[0], operands[1], NULL_RTX); |
9b7bf67d RH |
444 | DONE; |
445 | }") | |
446 | ||
c65ebc55 JW |
447 | (define_expand "load_fptr" |
448 | [(set (match_dup 2) | |
449 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" ""))) | |
ec039e3c | 450 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
451 | "" |
452 | " | |
453 | { | |
ec039e3c RH |
454 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); |
455 | operands[3] = gen_rtx_MEM (DImode, operands[2]); | |
456 | RTX_UNCHANGING_P (operands[3]) = 1; | |
c65ebc55 JW |
457 | }") |
458 | ||
459 | (define_insn "*load_fptr_internal1" | |
460 | [(set (match_operand:DI 0 "register_operand" "=r") | |
461 | (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))] | |
462 | "" | |
463 | "addl %0 = @ltoff(@fptr(%1)), gp" | |
52e12ad0 | 464 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
465 | |
466 | (define_insn "load_gprel" | |
467 | [(set (match_operand:DI 0 "register_operand" "=r") | |
468 | (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))] | |
469 | "" | |
470 | "addl %0 = @gprel(%1), gp" | |
52e12ad0 | 471 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 472 | |
59da9a7d JW |
473 | (define_insn "gprel64_offset" |
474 | [(set (match_operand:DI 0 "register_operand" "=r") | |
475 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))] | |
476 | "" | |
477 | "movl %0 = @gprel(%1)" | |
52e12ad0 | 478 | [(set_attr "itanium_class" "long_i")]) |
59da9a7d JW |
479 | |
480 | (define_expand "load_gprel64" | |
481 | [(set (match_dup 2) | |
b5d37c6f | 482 | (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 3))) |
59da9a7d | 483 | (set (match_operand:DI 0 "register_operand" "") |
b5d37c6f | 484 | (plus:DI (match_dup 3) (match_dup 2)))] |
59da9a7d | 485 | "" |
ec039e3c RH |
486 | " |
487 | { | |
488 | operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode); | |
b5d37c6f | 489 | operands[3] = pic_offset_table_rtx; |
59da9a7d JW |
490 | }") |
491 | ||
c65ebc55 | 492 | (define_expand "load_symptr" |
b5d37c6f BS |
493 | [(set (match_operand:DI 2 "register_operand" "") |
494 | (plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" ""))) | |
dee4095a | 495 | (set (match_operand:DI 0 "register_operand" "") (match_dup 3))] |
c65ebc55 JW |
496 | "" |
497 | " | |
498 | { | |
dee4095a | 499 | operands[3] = gen_rtx_MEM (DImode, operands[2]); |
b5d37c6f | 500 | operands[4] = pic_offset_table_rtx; |
dee4095a | 501 | RTX_UNCHANGING_P (operands[3]) = 1; |
c65ebc55 JW |
502 | }") |
503 | ||
504 | (define_insn "*load_symptr_internal1" | |
505 | [(set (match_operand:DI 0 "register_operand" "=r") | |
ec039e3c | 506 | (plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))] |
c65ebc55 JW |
507 | "" |
508 | "addl %0 = @ltoff(%1), gp" | |
52e12ad0 | 509 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 510 | |
3f622353 RH |
511 | ;; With no offsettable memory references, we've got to have a scratch |
512 | ;; around to play with the second word. | |
513 | (define_expand "movti" | |
514 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
515 | (match_operand:TI 1 "general_operand" "")) | |
516 | (clobber (match_scratch:DI 2 ""))])] | |
517 | "" | |
518 | " | |
519 | { | |
520 | if (! reload_in_progress && ! reload_completed | |
521 | && ! ia64_move_ok (operands[0], operands[1])) | |
522 | operands[1] = force_reg (TImode, operands[1]); | |
523 | }") | |
524 | ||
525 | (define_insn_and_split "*movti_internal" | |
526 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") | |
527 | (match_operand:TI 1 "general_operand" "ri,m,r")) | |
528 | (clobber (match_scratch:DI 2 "=X,&r,&r"))] | |
529 | "ia64_move_ok (operands[0], operands[1])" | |
530 | "#" | |
531 | "reload_completed" | |
532 | [(const_int 0)] | |
533 | " | |
534 | { | |
535 | rtx adj1, adj2, in[2], out[2]; | |
536 | int first; | |
537 | ||
538 | adj1 = ia64_split_timode (in, operands[1], operands[2]); | |
539 | adj2 = ia64_split_timode (out, operands[0], operands[2]); | |
540 | ||
541 | first = 0; | |
542 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
543 | { | |
544 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
545 | abort (); | |
546 | first = 1; | |
547 | } | |
548 | ||
549 | if (adj1 && adj2) | |
550 | abort (); | |
551 | if (adj1) | |
552 | emit_insn (adj1); | |
553 | if (adj2) | |
554 | emit_insn (adj2); | |
555 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
556 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
557 | DONE; | |
558 | }" | |
52e12ad0 | 559 | [(set_attr "itanium_class" "unknown") |
3f622353 | 560 | (set_attr "predicable" "no")]) |
e314e331 | 561 | |
3f622353 RH |
562 | ;; ??? SSA creates these. Can't allow memories since we don't have |
563 | ;; the scratch register. Fortunately combine will know how to add | |
564 | ;; the clobber and scratch. | |
565 | (define_insn_and_split "*movti_internal_reg" | |
566 | [(set (match_operand:TI 0 "register_operand" "=r") | |
567 | (match_operand:TI 1 "nonmemory_operand" "ri"))] | |
568 | "" | |
e314e331 | 569 | "#" |
3f622353 RH |
570 | "reload_completed" |
571 | [(const_int 0)] | |
572 | " | |
573 | { | |
574 | rtx in[2], out[2]; | |
575 | int first; | |
576 | ||
577 | ia64_split_timode (in, operands[1], NULL_RTX); | |
578 | ia64_split_timode (out, operands[0], NULL_RTX); | |
579 | ||
580 | first = 0; | |
581 | if (reg_overlap_mentioned_p (out[0], in[1])) | |
582 | { | |
583 | if (reg_overlap_mentioned_p (out[1], in[0])) | |
584 | abort (); | |
585 | first = 1; | |
586 | } | |
587 | ||
588 | emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first])); | |
589 | emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first])); | |
590 | DONE; | |
591 | }" | |
52e12ad0 | 592 | [(set_attr "itanium_class" "unknown") |
e314e331 JW |
593 | (set_attr "predicable" "no")]) |
594 | ||
3f622353 RH |
595 | (define_expand "reload_inti" |
596 | [(parallel [(set (match_operand:TI 0 "register_operand" "=r") | |
597 | (match_operand:TI 1 "" "m")) | |
60a3c181 | 598 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
599 | "" |
600 | " | |
601 | { | |
60a3c181 RH |
602 | unsigned int s_regno = REGNO (operands[2]); |
603 | if (s_regno == REGNO (operands[0])) | |
604 | s_regno += 1; | |
605 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 RH |
606 | }") |
607 | ||
608 | (define_expand "reload_outti" | |
609 | [(parallel [(set (match_operand:TI 0 "" "=m") | |
610 | (match_operand:TI 1 "register_operand" "r")) | |
60a3c181 | 611 | (clobber (match_operand:TI 2 "register_operand" "=&r"))])] |
3f622353 RH |
612 | "" |
613 | " | |
614 | { | |
60a3c181 RH |
615 | unsigned int s_regno = REGNO (operands[2]); |
616 | if (s_regno == REGNO (operands[1])) | |
617 | s_regno += 1; | |
618 | operands[2] = gen_rtx_REG (DImode, s_regno); | |
3f622353 | 619 | }") |
e314e331 | 620 | |
c65ebc55 JW |
621 | ;; Floating Point Moves |
622 | ;; | |
623 | ;; Note - Patterns for SF mode moves are compulsory, but | |
624 | ;; patterns for DF are optional, as GCC can synthesise them. | |
625 | ||
626 | (define_expand "movsf" | |
627 | [(set (match_operand:SF 0 "general_operand" "") | |
628 | (match_operand:SF 1 "general_operand" ""))] | |
629 | "" | |
630 | " | |
631 | { | |
632 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
633 | && ! ia64_move_ok (operands[0], operands[1])) |
634 | operands[1] = force_reg (SFmode, operands[1]); | |
c65ebc55 JW |
635 | }") |
636 | ||
c65ebc55 | 637 | (define_insn "*movsf_internal" |
4b983fdc RH |
638 | [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
639 | (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 640 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
641 | "@ |
642 | mov %0 = %F1 | |
643 | ldfs %0 = %1%P1 | |
644 | stfs %0 = %F1%P0 | |
645 | getf.s %0 = %F1 | |
646 | setf.s %0 = %1 | |
647 | mov %0 = %1 | |
13da91fd RH |
648 | ld4%O1 %0 = %1%P1 |
649 | st4%Q0 %0 = %1%P0" | |
52e12ad0 | 650 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 JW |
651 | |
652 | (define_expand "movdf" | |
653 | [(set (match_operand:DF 0 "general_operand" "") | |
654 | (match_operand:DF 1 "general_operand" ""))] | |
655 | "" | |
656 | " | |
657 | { | |
658 | if (! reload_in_progress && ! reload_completed | |
557b9df5 RH |
659 | && ! ia64_move_ok (operands[0], operands[1])) |
660 | operands[1] = force_reg (DFmode, operands[1]); | |
c65ebc55 JW |
661 | }") |
662 | ||
c65ebc55 | 663 | (define_insn "*movdf_internal" |
4b983fdc RH |
664 | [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m") |
665 | (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r"))] | |
aebf2462 | 666 | "ia64_move_ok (operands[0], operands[1])" |
c65ebc55 JW |
667 | "@ |
668 | mov %0 = %F1 | |
669 | ldfd %0 = %1%P1 | |
670 | stfd %0 = %F1%P0 | |
671 | getf.d %0 = %F1 | |
672 | setf.d %0 = %1 | |
13da91fd RH |
673 | mov %0 = %1 |
674 | ld8%O1 %0 = %1%P1 | |
675 | st8%Q0 %0 = %1%P0" | |
52e12ad0 | 676 | [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")]) |
c65ebc55 | 677 | |
3f622353 RH |
678 | ;; With no offsettable memory references, we've got to have a scratch |
679 | ;; around to play with the second word if the variable winds up in GRs. | |
680 | (define_expand "movtf" | |
681 | [(set (match_operand:TF 0 "general_operand" "") | |
682 | (match_operand:TF 1 "general_operand" ""))] | |
23c108af | 683 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a RH |
684 | " |
685 | { | |
3f622353 RH |
686 | /* We must support TFmode loads into general registers for stdarg/vararg |
687 | and unprototyped calls. We split them into DImode loads for convenience. | |
688 | We don't need TFmode stores from general regs, because a stdarg/vararg | |
689 | routine does a block store to memory of unnamed arguments. */ | |
690 | if (GET_CODE (operands[0]) == REG | |
691 | && GR_REGNO_P (REGNO (operands[0]))) | |
692 | { | |
693 | /* We're hoping to transform everything that deals with TFmode | |
694 | quantities and GR registers early in the compiler. */ | |
695 | if (no_new_pseudos) | |
696 | abort (); | |
697 | ||
698 | /* Struct to register can just use TImode instead. */ | |
699 | if ((GET_CODE (operands[1]) == SUBREG | |
700 | && GET_MODE (SUBREG_REG (operands[1])) == TImode) | |
701 | || (GET_CODE (operands[1]) == REG | |
702 | && GR_REGNO_P (REGNO (operands[1])))) | |
703 | { | |
704 | emit_move_insn (gen_rtx_REG (TImode, REGNO (operands[0])), | |
705 | SUBREG_REG (operands[1])); | |
706 | DONE; | |
707 | } | |
708 | ||
709 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
710 | { | |
711 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0])), | |
2bf47a10 | 712 | operand_subword (operands[1], 0, 0, TFmode)); |
3f622353 | 713 | emit_move_insn (gen_rtx_REG (DImode, REGNO (operands[0]) + 1), |
2bf47a10 | 714 | operand_subword (operands[1], 1, 0, TFmode)); |
3f622353 RH |
715 | DONE; |
716 | } | |
717 | ||
718 | /* If the quantity is in a register not known to be GR, spill it. */ | |
719 | if (register_operand (operands[1], TFmode)) | |
720 | operands[1] = spill_tfmode_operand (operands[1], 1); | |
721 | ||
722 | if (GET_CODE (operands[1]) == MEM) | |
723 | { | |
724 | rtx out[2]; | |
725 | ||
726 | out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
727 | out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[0])+1); | |
728 | ||
f4ef873c RK |
729 | emit_move_insn (out[0], adjust_address (operands[1], DImode, 0)); |
730 | emit_move_insn (out[1], adjust_address (operands[1], DImode, 8)); | |
3f622353 RH |
731 | DONE; |
732 | } | |
733 | ||
734 | abort (); | |
735 | } | |
736 | ||
737 | if (! reload_in_progress && ! reload_completed) | |
738 | { | |
739 | operands[0] = spill_tfmode_operand (operands[0], 0); | |
740 | operands[1] = spill_tfmode_operand (operands[1], 0); | |
741 | ||
742 | if (! ia64_move_ok (operands[0], operands[1])) | |
743 | operands[1] = force_reg (TFmode, operands[1]); | |
744 | } | |
e5bde68a RH |
745 | }") |
746 | ||
3b572406 | 747 | ;; ??? There's no easy way to mind volatile acquire/release semantics. |
75cdbeb8 | 748 | |
3f622353 RH |
749 | (define_insn "*movtf_internal" |
750 | [(set (match_operand:TF 0 "destination_tfmode_operand" "=f,f, m") | |
751 | (match_operand:TF 1 "general_tfmode_operand" "fG,m,fG"))] | |
23c108af | 752 | "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])" |
e5bde68a RH |
753 | "@ |
754 | mov %0 = %F1 | |
46b1ac3f JW |
755 | ldfe %0 = %1%P1 |
756 | stfe %0 = %F1%P0" | |
52e12ad0 | 757 | [(set_attr "itanium_class" "fmisc,fld,stf")]) |
c65ebc55 JW |
758 | \f |
759 | ;; :::::::::::::::::::: | |
760 | ;; :: | |
761 | ;; :: Conversions | |
762 | ;; :: | |
763 | ;; :::::::::::::::::::: | |
764 | ||
765 | ;; Signed conversions from a smaller integer to a larger integer | |
766 | ||
767 | (define_insn "extendqidi2" | |
0551c32d RH |
768 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
769 | (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
770 | "" |
771 | "sxt1 %0 = %1" | |
52e12ad0 | 772 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
773 | |
774 | (define_insn "extendhidi2" | |
0551c32d RH |
775 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
776 | (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
777 | "" |
778 | "sxt2 %0 = %1" | |
52e12ad0 | 779 | [(set_attr "itanium_class" "xtd")]) |
c65ebc55 JW |
780 | |
781 | (define_insn "extendsidi2" | |
655f2eb9 RH |
782 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f") |
783 | (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))] | |
c65ebc55 JW |
784 | "" |
785 | "@ | |
786 | sxt4 %0 = %1 | |
aebf2462 | 787 | fsxt.r %0 = %1, %1" |
52e12ad0 | 788 | [(set_attr "itanium_class" "xtd,fmisc")]) |
c65ebc55 JW |
789 | |
790 | ;; Unsigned conversions from a smaller integer to a larger integer | |
791 | ||
792 | (define_insn "zero_extendqidi2" | |
0551c32d RH |
793 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
794 | (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
795 | "" |
796 | "@ | |
797 | zxt1 %0 = %1 | |
798 | ld1%O1 %0 = %1%P1" | |
52e12ad0 | 799 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
800 | |
801 | (define_insn "zero_extendhidi2" | |
0551c32d RH |
802 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
803 | (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))] | |
c65ebc55 JW |
804 | "" |
805 | "@ | |
806 | zxt2 %0 = %1 | |
807 | ld2%O1 %0 = %1%P1" | |
52e12ad0 | 808 | [(set_attr "itanium_class" "xtd,ld")]) |
c65ebc55 JW |
809 | |
810 | (define_insn "zero_extendsidi2" | |
655f2eb9 | 811 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f") |
0551c32d | 812 | (zero_extend:DI |
655f2eb9 | 813 | (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))] |
c65ebc55 JW |
814 | "" |
815 | "@ | |
816 | zxt4 %0 = %1 | |
817 | ld4%O1 %0 = %1%P1 | |
aebf2462 | 818 | fmix.r %0 = f0, %1" |
52e12ad0 | 819 | [(set_attr "itanium_class" "xtd,ld,fmisc")]) |
c65ebc55 JW |
820 | |
821 | ;; Convert between floating point types of different sizes. | |
822 | ||
640cea5f JW |
823 | ;; At first glance, it would appear that emitting fnorm for an extending |
824 | ;; conversion is unnecessary. However, the stf and getf instructions work | |
825 | ;; correctly only if the input is properly rounded for its type. In | |
826 | ;; particular, we get the wrong result for getf.d/stfd if the input is a | |
827 | ;; denorm single. Since we don't know what the next instruction will be, we | |
828 | ;; have to emit an fnorm. | |
829 | ||
e8e20f18 RH |
830 | ;; ??? Optimization opportunity here. Get rid of the insn altogether |
831 | ;; when we can. Should probably use a scheme like has been proposed | |
832 | ;; for ia32 in dealing with operands that match unary operators. This | |
640cea5f JW |
833 | ;; would let combine merge the thing into adjacent insns. See also how the |
834 | ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via | |
835 | ;; se_register_operand. | |
c65ebc55 | 836 | |
640cea5f JW |
837 | (define_insn "extendsfdf2" |
838 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
839 | (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 840 | "" |
640cea5f JW |
841 | "fnorm.d %0 = %1" |
842 | [(set_attr "itanium_class" "fmac")]) | |
c65ebc55 | 843 | |
640cea5f JW |
844 | (define_insn "extendsftf2" |
845 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
846 | (float_extend:TF (match_operand:SF 1 "fr_register_operand" "f")))] | |
23c108af | 847 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
848 | "fnorm %0 = %1" |
849 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 850 | |
640cea5f JW |
851 | (define_insn "extenddftf2" |
852 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
853 | (float_extend:TF (match_operand:DF 1 "fr_register_operand" "f")))] | |
23c108af | 854 | "INTEL_EXTENDED_IEEE_FORMAT" |
640cea5f JW |
855 | "fnorm %0 = %1" |
856 | [(set_attr "itanium_class" "fmac")]) | |
3f622353 | 857 | |
c65ebc55 | 858 | (define_insn "truncdfsf2" |
0551c32d RH |
859 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
860 | (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 861 | "" |
aebf2462 | 862 | "fnorm.s %0 = %1" |
52e12ad0 | 863 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 864 | |
3f622353 | 865 | (define_insn "trunctfsf2" |
0551c32d RH |
866 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
867 | (float_truncate:SF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 868 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 869 | "fnorm.s %0 = %1" |
52e12ad0 | 870 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 871 | |
3f622353 | 872 | (define_insn "trunctfdf2" |
0551c32d RH |
873 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
874 | (float_truncate:DF (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 875 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 876 | "fnorm.d %0 = %1" |
52e12ad0 | 877 | [(set_attr "itanium_class" "fmac")]) |
e5bde68a RH |
878 | |
879 | ;; Convert between signed integer types and floating point. | |
880 | ||
3f622353 | 881 | (define_insn "floatditf2" |
0551c32d RH |
882 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
883 | (float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 884 | "INTEL_EXTENDED_IEEE_FORMAT" |
e5bde68a | 885 | "fcvt.xf %0 = %1" |
52e12ad0 | 886 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 887 | |
23c108af SE |
888 | ;; ??? Suboptimal. This should be split somehow. |
889 | (define_insn "floatdidf2" | |
890 | [(set (match_operand:DF 0 "register_operand" "=f") | |
891 | (float:DF (match_operand:DI 1 "register_operand" "f")))] | |
892 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
893 | "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0" | |
894 | [(set_attr "itanium_class" "fcvtfx")]) | |
895 | ||
896 | ;; ??? Suboptimal. This should be split somehow. | |
897 | (define_insn "floatdisf2" | |
898 | [(set (match_operand:SF 0 "register_operand" "=f") | |
899 | (float:SF (match_operand:DI 1 "register_operand" "f")))] | |
900 | "!INTEL_EXTENDED_IEEE_FORMAT" | |
901 | "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0" | |
902 | [(set_attr "itanium_class" "fcvtfx")]) | |
903 | ||
c65ebc55 | 904 | (define_insn "fix_truncsfdi2" |
0551c32d RH |
905 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
906 | (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 907 | "" |
aebf2462 | 908 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 909 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
910 | |
911 | (define_insn "fix_truncdfdi2" | |
0551c32d RH |
912 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
913 | (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 914 | "" |
aebf2462 | 915 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 916 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 917 | |
3f622353 | 918 | (define_insn "fix_trunctfdi2" |
0551c32d RH |
919 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
920 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 921 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 922 | "fcvt.fx.trunc %0 = %1" |
52e12ad0 | 923 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 924 | |
655f2eb9 RH |
925 | (define_insn "fix_trunctfdi2_alts" |
926 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
927 | (fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
928 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 929 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 930 | "fcvt.fx.trunc.s%2 %0 = %1" |
52e12ad0 | 931 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 | 932 | |
c65ebc55 JW |
933 | ;; Convert between unsigned integer types and floating point. |
934 | ||
935 | (define_insn "floatunsdisf2" | |
0551c32d RH |
936 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
937 | (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 938 | "" |
aebf2462 | 939 | "fcvt.xuf.s %0 = %1" |
52e12ad0 | 940 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
941 | |
942 | (define_insn "floatunsdidf2" | |
0551c32d RH |
943 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
944 | (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))] | |
c65ebc55 | 945 | "" |
aebf2462 | 946 | "fcvt.xuf.d %0 = %1" |
52e12ad0 | 947 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 948 | |
3f622353 | 949 | (define_insn "floatunsditf2" |
0551c32d RH |
950 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
951 | (unsigned_float:TF (match_operand:DI 1 "fr_register_operand" "f")))] | |
23c108af | 952 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 953 | "fcvt.xuf %0 = %1" |
52e12ad0 | 954 | [(set_attr "itanium_class" "fcvtfx")]) |
3f622353 | 955 | |
c65ebc55 | 956 | (define_insn "fixuns_truncsfdi2" |
0551c32d RH |
957 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
958 | (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 959 | "" |
aebf2462 | 960 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 961 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
962 | |
963 | (define_insn "fixuns_truncdfdi2" | |
0551c32d RH |
964 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
965 | (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 966 | "" |
aebf2462 | 967 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 968 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 | 969 | |
3f622353 | 970 | (define_insn "fixuns_trunctfdi2" |
0551c32d RH |
971 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
972 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f")))] | |
23c108af | 973 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 974 | "fcvt.fxu.trunc %0 = %1" |
52e12ad0 | 975 | [(set_attr "itanium_class" "fcvtfx")]) |
655f2eb9 RH |
976 | |
977 | (define_insn "fixuns_trunctfdi2_alts" | |
978 | [(set (match_operand:DI 0 "fr_register_operand" "=f") | |
979 | (unsigned_fix:DI (match_operand:TF 1 "fr_register_operand" "f"))) | |
980 | (use (match_operand:SI 2 "const_int_operand" ""))] | |
23c108af | 981 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 982 | "fcvt.fxu.trunc.s%2 %0 = %1" |
52e12ad0 | 983 | [(set_attr "itanium_class" "fcvtfx")]) |
c65ebc55 JW |
984 | \f |
985 | ;; :::::::::::::::::::: | |
986 | ;; :: | |
987 | ;; :: Bit field extraction | |
988 | ;; :: | |
989 | ;; :::::::::::::::::::: | |
990 | ||
c65ebc55 | 991 | (define_insn "extv" |
0551c32d RH |
992 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
993 | (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
994 | (match_operand:DI 2 "const_int_operand" "n") |
995 | (match_operand:DI 3 "const_int_operand" "n")))] | |
996 | "" | |
997 | "extr %0 = %1, %3, %2" | |
52e12ad0 | 998 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
999 | |
1000 | (define_insn "extzv" | |
0551c32d RH |
1001 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1002 | (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
1003 | (match_operand:DI 2 "const_int_operand" "n") |
1004 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1005 | "" | |
1006 | "extr.u %0 = %1, %3, %2" | |
52e12ad0 | 1007 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
1008 | |
1009 | ;; Insert a bit field. | |
1010 | ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest. | |
1011 | ;; Source1 can be 0 or -1. | |
1012 | ;; Source2 can be 0. | |
1013 | ||
1014 | ;; ??? Actual dep instruction is more powerful than what these insv | |
1015 | ;; patterns support. Unfortunately, combine is unable to create patterns | |
1016 | ;; where source2 != dest. | |
1017 | ||
1018 | (define_expand "insv" | |
0551c32d | 1019 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "") |
c65ebc55 JW |
1020 | (match_operand:DI 1 "const_int_operand" "") |
1021 | (match_operand:DI 2 "const_int_operand" "")) | |
1022 | (match_operand:DI 3 "nonmemory_operand" ""))] | |
1023 | "" | |
1024 | " | |
1025 | { | |
1026 | int width = INTVAL (operands[1]); | |
1027 | int shift = INTVAL (operands[2]); | |
1028 | ||
1029 | /* If operand[3] is a constant, and isn't 0 or -1, then load it into a | |
1030 | pseudo. */ | |
1031 | if (! register_operand (operands[3], DImode) | |
1032 | && operands[3] != const0_rtx && operands[3] != constm1_rtx) | |
1033 | operands[3] = force_reg (DImode, operands[3]); | |
1034 | ||
1035 | /* If this is a single dep instruction, we have nothing to do. */ | |
1036 | if (! ((register_operand (operands[3], DImode) && width <= 16) | |
1037 | || operands[3] == const0_rtx || operands[3] == constm1_rtx)) | |
1038 | { | |
1039 | /* Check for cases that can be implemented with a mix instruction. */ | |
1040 | if (width == 32 && shift == 0) | |
1041 | { | |
1042 | /* Directly generating the mix4left instruction confuses | |
1043 | optimize_bit_field in function.c. Since this is performing | |
1044 | a useful optimization, we defer generation of the complicated | |
1045 | mix4left RTL to the first splitting phase. */ | |
1046 | rtx tmp = gen_reg_rtx (DImode); | |
1047 | emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp)); | |
1048 | DONE; | |
1049 | } | |
1050 | else if (width == 32 && shift == 32) | |
1051 | { | |
1052 | emit_insn (gen_mix4right (operands[0], operands[3])); | |
1053 | DONE; | |
1054 | } | |
1055 | ||
d2ba6dcf JW |
1056 | /* We could handle remaining cases by emitting multiple dep |
1057 | instructions. | |
1058 | ||
1059 | If we need more than two dep instructions then we lose. A 6 | |
1060 | insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than | |
1061 | mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles, | |
1062 | the latter is 6 cycles on an Itanium (TM) processor, because there is | |
1063 | only one function unit that can execute dep and shr immed. | |
1064 | ||
1065 | If we only need two dep instruction, then we still lose. | |
1066 | mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away | |
1067 | the unnecessary mov, this is still undesirable because it will be | |
1068 | hard to optimize, and it creates unnecessary pressure on the I0 | |
1069 | function unit. */ | |
1070 | ||
c65ebc55 JW |
1071 | FAIL; |
1072 | ||
1073 | #if 0 | |
1074 | /* This code may be useful for other IA-64 processors, so we leave it in | |
1075 | for now. */ | |
1076 | while (width > 16) | |
1077 | { | |
1078 | rtx tmp; | |
1079 | ||
1080 | emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift), | |
1081 | operands[3])); | |
1082 | shift += 16; | |
1083 | width -= 16; | |
1084 | tmp = gen_reg_rtx (DImode); | |
1085 | emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16))); | |
1086 | operands[3] = tmp; | |
1087 | } | |
1088 | operands[1] = GEN_INT (width); | |
1089 | operands[2] = GEN_INT (shift); | |
1090 | #endif | |
1091 | } | |
1092 | }") | |
1093 | ||
1094 | (define_insn "*insv_internal" | |
0551c32d | 1095 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 JW |
1096 | (match_operand:DI 1 "const_int_operand" "n") |
1097 | (match_operand:DI 2 "const_int_operand" "n")) | |
1098 | (match_operand:DI 3 "nonmemory_operand" "rP"))] | |
0551c32d | 1099 | "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16) |
c65ebc55 JW |
1100 | || operands[3] == const0_rtx || operands[3] == constm1_rtx" |
1101 | "dep %0 = %3, %0, %2, %1" | |
52e12ad0 | 1102 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 1103 | |
041f25e6 RH |
1104 | ;; Combine doesn't like to create bitfield insertions into zero. |
1105 | (define_insn "*depz_internal" | |
0551c32d RH |
1106 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1107 | (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r") | |
041f25e6 RH |
1108 | (match_operand:DI 2 "const_int_operand" "n")) |
1109 | (match_operand:DI 3 "const_int_operand" "n")))] | |
1110 | "CONST_OK_FOR_M (INTVAL (operands[2])) | |
1111 | && ia64_depz_field_mask (operands[3], operands[2]) > 0" | |
1112 | "* | |
1113 | { | |
1114 | operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2])); | |
1115 | return \"%,dep.z %0 = %1, %2, %3\"; | |
1116 | }" | |
52e12ad0 | 1117 | [(set_attr "itanium_class" "ishf")]) |
041f25e6 | 1118 | |
c65ebc55 | 1119 | (define_insn "shift_mix4left" |
0551c32d | 1120 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1121 | (const_int 32) (const_int 0)) |
0551c32d RH |
1122 | (match_operand:DI 1 "gr_register_operand" "r")) |
1123 | (clobber (match_operand:DI 2 "gr_register_operand" "=r"))] | |
c65ebc55 JW |
1124 | "" |
1125 | "#" | |
52e12ad0 | 1126 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 1127 | |
c65ebc55 JW |
1128 | (define_split |
1129 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1130 | (const_int 32) (const_int 0)) | |
1131 | (match_operand:DI 1 "register_operand" "")) | |
1132 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1133 | "reload_completed" | |
1134 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
c65ebc55 JW |
1135 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) |
1136 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1137 | "operands[3] = operands[2];") | |
1138 | ||
1139 | (define_split | |
1140 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "") | |
1141 | (const_int 32) (const_int 0)) | |
1142 | (match_operand:DI 1 "register_operand" "")) | |
1143 | (clobber (match_operand:DI 2 "register_operand" ""))] | |
1144 | "! reload_completed" | |
1145 | [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32))) | |
1146 | (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0)) | |
1147 | (lshiftrt:DI (match_dup 3) (const_int 32)))] | |
1148 | "operands[3] = operands[2];") | |
1149 | ||
1150 | (define_insn "*mix4left" | |
0551c32d | 1151 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1152 | (const_int 32) (const_int 0)) |
0551c32d | 1153 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r") |
c65ebc55 JW |
1154 | (const_int 32)))] |
1155 | "" | |
1156 | "mix4.l %0 = %0, %r1" | |
52e12ad0 | 1157 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1158 | |
1159 | (define_insn "mix4right" | |
0551c32d | 1160 | [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r") |
c65ebc55 | 1161 | (const_int 32) (const_int 32)) |
0551c32d | 1162 | (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))] |
c65ebc55 JW |
1163 | "" |
1164 | "mix4.r %0 = %r1, %0" | |
52e12ad0 | 1165 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1166 | |
1167 | ;; This is used by the rotrsi3 pattern. | |
1168 | ||
1169 | (define_insn "*mix4right_3op" | |
0551c32d RH |
1170 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
1171 | (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r")) | |
1172 | (ashift:DI (zero_extend:DI | |
1173 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1174 | (const_int 32))))] |
1175 | "" | |
fa9a44e8 | 1176 | "mix4.r %0 = %2, %1" |
52e12ad0 | 1177 | [(set_attr "itanium_class" "mmshf")]) |
c65ebc55 JW |
1178 | |
1179 | \f | |
1180 | ;; :::::::::::::::::::: | |
cf1f6ae3 | 1181 | ;; :: |
f2f90c63 RH |
1182 | ;; :: 1 bit Integer arithmetic |
1183 | ;; :: | |
1184 | ;; :::::::::::::::::::: | |
1185 | ||
1186 | (define_insn_and_split "andbi3" | |
1187 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1188 | (and:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1189 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1190 | "" | |
1191 | "@ | |
1192 | # | |
1193 | tbit.nz.and.orcm %0, %I0 = %2, 0 | |
1194 | and %0 = %2, %1" | |
1195 | "reload_completed | |
1196 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1197 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1198 | [(cond_exec (eq (match_dup 2) (const_int 0)) | |
1199 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1200 | (match_dup 0))))] | |
1201 | "" | |
52e12ad0 | 1202 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1203 | |
1204 | (define_insn_and_split "*andcmbi3" | |
1205 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1206 | (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r")) | |
1207 | (match_operand:BI 2 "register_operand" "0,0,r")))] | |
1208 | "" | |
1209 | "@ | |
1210 | # | |
1211 | tbit.z.and.orcm %0, %I0 = %2, 0 | |
1212 | andcm %0 = %2, %1" | |
1213 | "reload_completed | |
1214 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1215 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1216 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1217 | (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0)) | |
1218 | (match_dup 0))))] | |
1219 | "" | |
52e12ad0 | 1220 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1221 | |
1222 | (define_insn_and_split "iorbi3" | |
1223 | [(set (match_operand:BI 0 "register_operand" "=c,c,r") | |
1224 | (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r") | |
1225 | (match_operand:BI 2 "register_operand" "c,r,r")))] | |
1226 | "" | |
1227 | "@ | |
1228 | # | |
1229 | tbit.nz.or.andcm %0, %I0 = %2, 0 | |
1230 | or %0 = %2, %1" | |
1231 | "reload_completed | |
1232 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1233 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1234 | [(cond_exec (ne (match_dup 2) (const_int 0)) | |
1235 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1236 | (match_dup 0))))] | |
1237 | "" | |
52e12ad0 | 1238 | [(set_attr "itanium_class" "unknown,tbit,ilog")]) |
f2f90c63 RH |
1239 | |
1240 | (define_insn_and_split "*iorcmbi3" | |
1241 | [(set (match_operand:BI 0 "register_operand" "=c,c") | |
1242 | (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r")) | |
1243 | (match_operand:BI 2 "register_operand" "0,0")))] | |
1244 | "" | |
1245 | "@ | |
1246 | # | |
1247 | tbit.z.or.andcm %0, %I0 = %2, 0" | |
1248 | "reload_completed | |
1249 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1250 | && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))" | |
1251 | [(cond_exec (eq (match_dup 1) (const_int 0)) | |
1252 | (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0)) | |
1253 | (match_dup 0))))] | |
1254 | "" | |
52e12ad0 | 1255 | [(set_attr "itanium_class" "unknown,tbit")]) |
f2f90c63 RH |
1256 | |
1257 | (define_insn "one_cmplbi2" | |
1258 | [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c") | |
1259 | (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c"))) | |
1260 | (clobber (match_scratch:BI 2 "=X,X,c,X"))] | |
1261 | "" | |
1262 | "@ | |
1263 | tbit.z %0, %I0 = %1, 0 | |
1264 | xor %0 = 1, %1 | |
1265 | # | |
1266 | #" | |
52e12ad0 | 1267 | [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")]) |
f2f90c63 RH |
1268 | |
1269 | (define_split | |
1270 | [(set (match_operand:BI 0 "register_operand" "") | |
1271 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1272 | (clobber (match_scratch:BI 2 ""))] | |
1273 | "reload_completed | |
1274 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1275 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1276 | && rtx_equal_p (operands[0], operands[1])" | |
1277 | [(set (match_dup 4) (match_dup 3)) | |
1278 | (set (match_dup 0) (const_int 1)) | |
1279 | (cond_exec (ne (match_dup 2) (const_int 0)) | |
1280 | (set (match_dup 0) (const_int 0))) | |
1281 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1282 | "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1])); | |
1283 | operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));") | |
1284 | ||
1285 | (define_split | |
1286 | [(set (match_operand:BI 0 "register_operand" "") | |
1287 | (not:BI (match_operand:BI 1 "register_operand" ""))) | |
1288 | (clobber (match_scratch:BI 2 ""))] | |
1289 | "reload_completed | |
1290 | && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0])) | |
1291 | && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1])) | |
1292 | && ! rtx_equal_p (operands[0], operands[1])" | |
1293 | [(cond_exec (ne (match_dup 1) (const_int 0)) | |
1294 | (set (match_dup 0) (const_int 0))) | |
1295 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
1296 | (set (match_dup 0) (const_int 1))) | |
1297 | (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))] | |
1298 | "") | |
1299 | ||
1300 | (define_insn "*cmpsi_and_0" | |
1301 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1302 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1303 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1304 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1305 | (match_operand:BI 1 "register_operand" "0")))] | |
1306 | "" | |
1307 | "cmp4.%C4.and.orcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1308 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1309 | |
1310 | (define_insn "*cmpsi_and_1" | |
1311 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1312 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1313 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1314 | (const_int 0)]) | |
1315 | (match_operand:BI 1 "register_operand" "0")))] | |
1316 | "" | |
1317 | "cmp4.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1318 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1319 | |
1320 | (define_insn "*cmpsi_andnot_0" | |
1321 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1322 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1323 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1324 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1325 | (match_operand:BI 1 "register_operand" "0")))] | |
1326 | "" | |
1327 | "cmp4.%C4.or.andcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1328 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1329 | |
1330 | (define_insn "*cmpsi_andnot_1" | |
1331 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1332 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1333 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1334 | (const_int 0)])) | |
1335 | (match_operand:BI 1 "register_operand" "0")))] | |
1336 | "" | |
1337 | "cmp4.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1338 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1339 | |
1340 | (define_insn "*cmpdi_and_0" | |
1341 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1342 | (and:BI (match_operator:BI 4 "predicate_operator" | |
1343 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1344 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1345 | (match_operand:BI 1 "register_operand" "0")))] | |
1346 | "" | |
1347 | "cmp.%C4.and.orcm %0, %I0 = %3, %2" | |
52e12ad0 | 1348 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1349 | |
1350 | (define_insn "*cmpdi_and_1" | |
1351 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1352 | (and:BI (match_operator:BI 3 "signed_inequality_operator" | |
1353 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1354 | (const_int 0)]) | |
1355 | (match_operand:BI 1 "register_operand" "0")))] | |
1356 | "" | |
1357 | "cmp.%C3.and.orcm %0, %I0 = r0, %2" | |
52e12ad0 | 1358 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1359 | |
1360 | (define_insn "*cmpdi_andnot_0" | |
1361 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1362 | (and:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1363 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1364 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1365 | (match_operand:BI 1 "register_operand" "0")))] | |
1366 | "" | |
1367 | "cmp.%C4.or.andcm %I0, %0 = %3, %2" | |
52e12ad0 | 1368 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1369 | |
1370 | (define_insn "*cmpdi_andnot_1" | |
1371 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1372 | (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1373 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1374 | (const_int 0)])) | |
1375 | (match_operand:BI 1 "register_operand" "0")))] | |
1376 | "" | |
1377 | "cmp.%C3.or.andcm %I0, %0 = r0, %2" | |
52e12ad0 | 1378 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1379 | |
1380 | (define_insn "*tbit_and_0" | |
1381 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1382 | (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1383 | (const_int 1)) | |
1384 | (const_int 0)) | |
c77e04ae | 1385 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1386 | "" |
1387 | "tbit.nz.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1388 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1389 | |
1390 | (define_insn "*tbit_and_1" | |
1391 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1392 | (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1393 | (const_int 1)) | |
1394 | (const_int 0)) | |
c77e04ae | 1395 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1396 | "" |
1397 | "tbit.z.and.orcm %0, %I0 = %1, 0" | |
52e12ad0 | 1398 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1399 | |
1400 | (define_insn "*tbit_and_2" | |
1401 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1402 | (and:BI (ne:BI (zero_extract:DI | |
1403 | (match_operand:DI 1 "gr_register_operand" "r") | |
1404 | (const_int 1) | |
1405 | (match_operand:DI 2 "const_int_operand" "n")) | |
1406 | (const_int 0)) | |
1407 | (match_operand:BI 3 "register_operand" "0")))] | |
1408 | "" | |
1409 | "tbit.nz.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1410 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1411 | |
1412 | (define_insn "*tbit_and_3" | |
1413 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1414 | (and:BI (eq:BI (zero_extract:DI | |
1415 | (match_operand:DI 1 "gr_register_operand" "r") | |
1416 | (const_int 1) | |
1417 | (match_operand:DI 2 "const_int_operand" "n")) | |
1418 | (const_int 0)) | |
1419 | (match_operand:BI 3 "register_operand" "0")))] | |
1420 | "" | |
1421 | "tbit.z.and.orcm %0, %I0 = %1, %2" | |
52e12ad0 | 1422 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1423 | |
1424 | (define_insn "*cmpsi_or_0" | |
1425 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1426 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1427 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1428 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1429 | (match_operand:BI 1 "register_operand" "0")))] | |
1430 | "" | |
1431 | "cmp4.%C4.or.andcm %0, %I0 = %3, %r2" | |
52e12ad0 | 1432 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1433 | |
1434 | (define_insn "*cmpsi_or_1" | |
1435 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1436 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1437 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1438 | (const_int 0)]) | |
1439 | (match_operand:BI 1 "register_operand" "0")))] | |
1440 | "" | |
1441 | "cmp4.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1442 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1443 | |
1444 | (define_insn "*cmpsi_orcm_0" | |
1445 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1446 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1447 | [(match_operand:SI 2 "gr_reg_or_0_operand" "rO") | |
1448 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1449 | (match_operand:BI 1 "register_operand" "0")))] | |
1450 | "" | |
1451 | "cmp4.%C4.and.orcm %I0, %0 = %3, %r2" | |
52e12ad0 | 1452 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1453 | |
1454 | (define_insn "*cmpsi_orcm_1" | |
1455 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1456 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1457 | [(match_operand:SI 2 "gr_register_operand" "r") | |
1458 | (const_int 0)])) | |
1459 | (match_operand:BI 1 "register_operand" "0")))] | |
1460 | "" | |
1461 | "cmp4.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1462 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1463 | |
1464 | (define_insn "*cmpdi_or_0" | |
1465 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1466 | (ior:BI (match_operator:BI 4 "predicate_operator" | |
1467 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1468 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]) | |
1469 | (match_operand:BI 1 "register_operand" "0")))] | |
1470 | "" | |
1471 | "cmp.%C4.or.andcm %0, %I0 = %3, %2" | |
52e12ad0 | 1472 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1473 | |
1474 | (define_insn "*cmpdi_or_1" | |
1475 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1476 | (ior:BI (match_operator:BI 3 "signed_inequality_operator" | |
1477 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1478 | (const_int 0)]) | |
1479 | (match_operand:BI 1 "register_operand" "0")))] | |
1480 | "" | |
1481 | "cmp.%C3.or.andcm %0, %I0 = r0, %2" | |
52e12ad0 | 1482 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1483 | |
1484 | (define_insn "*cmpdi_orcm_0" | |
1485 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1486 | (ior:BI (not:BI (match_operator:BI 4 "predicate_operator" | |
1487 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1488 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])) | |
1489 | (match_operand:BI 1 "register_operand" "0")))] | |
1490 | "" | |
1491 | "cmp.%C4.and.orcm %I0, %0 = %3, %2" | |
52e12ad0 | 1492 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1493 | |
1494 | (define_insn "*cmpdi_orcm_1" | |
1495 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1496 | (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator" | |
1497 | [(match_operand:DI 2 "gr_register_operand" "r") | |
1498 | (const_int 0)])) | |
1499 | (match_operand:BI 1 "register_operand" "0")))] | |
1500 | "" | |
1501 | "cmp.%C3.and.orcm %I0, %0 = r0, %2" | |
52e12ad0 | 1502 | [(set_attr "itanium_class" "icmp")]) |
f2f90c63 RH |
1503 | |
1504 | (define_insn "*tbit_or_0" | |
1505 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1506 | (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1507 | (const_int 1)) | |
1508 | (const_int 0)) | |
c77e04ae | 1509 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1510 | "" |
1511 | "tbit.nz.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1512 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1513 | |
1514 | (define_insn "*tbit_or_1" | |
1515 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1516 | (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r") | |
1517 | (const_int 1)) | |
1518 | (const_int 0)) | |
c77e04ae | 1519 | (match_operand:BI 2 "register_operand" "0")))] |
f2f90c63 RH |
1520 | "" |
1521 | "tbit.z.or.andcm %0, %I0 = %1, 0" | |
52e12ad0 | 1522 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1523 | |
1524 | (define_insn "*tbit_or_2" | |
1525 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1526 | (ior:BI (ne:BI (zero_extract:DI | |
1527 | (match_operand:DI 1 "gr_register_operand" "r") | |
1528 | (const_int 1) | |
1529 | (match_operand:DI 2 "const_int_operand" "n")) | |
1530 | (const_int 0)) | |
1531 | (match_operand:BI 3 "register_operand" "0")))] | |
1532 | "" | |
1533 | "tbit.nz.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1534 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1535 | |
1536 | (define_insn "*tbit_or_3" | |
1537 | [(set (match_operand:BI 0 "register_operand" "=c") | |
1538 | (ior:BI (eq:BI (zero_extract:DI | |
1539 | (match_operand:DI 1 "gr_register_operand" "r") | |
1540 | (const_int 1) | |
1541 | (match_operand:DI 2 "const_int_operand" "n")) | |
1542 | (const_int 0)) | |
1543 | (match_operand:BI 3 "register_operand" "0")))] | |
1544 | "" | |
1545 | "tbit.z.or.andcm %0, %I0 = %1, %2" | |
52e12ad0 | 1546 | [(set_attr "itanium_class" "tbit")]) |
f2f90c63 RH |
1547 | |
1548 | ;; Transform test of and/or of setcc into parallel comparisons. | |
1549 | ||
1550 | (define_split | |
1551 | [(set (match_operand:BI 0 "register_operand" "") | |
1552 | (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1553 | (const_int 0)) | |
1554 | (match_operand:DI 3 "register_operand" "")) | |
1555 | (const_int 0)))] | |
1556 | "" | |
1557 | [(set (match_dup 0) | |
1558 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1559 | (match_dup 2)))] | |
1560 | "") | |
1561 | ||
1562 | (define_split | |
1563 | [(set (match_operand:BI 0 "register_operand" "") | |
1564 | (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1565 | (const_int 0)) | |
1566 | (match_operand:DI 3 "register_operand" "")) | |
1567 | (const_int 0)))] | |
1568 | "" | |
1569 | [(set (match_dup 0) | |
1570 | (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0)) | |
1571 | (match_dup 2))) | |
1572 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1573 | (clobber (scratch))])] | |
1574 | "") | |
1575 | ||
1576 | (define_split | |
1577 | [(set (match_operand:BI 0 "register_operand" "") | |
1578 | (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1579 | (const_int 0)) | |
1580 | (match_operand:DI 3 "register_operand" "")) | |
1581 | (const_int 0)))] | |
1582 | "" | |
1583 | [(set (match_dup 0) | |
1584 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1585 | (match_dup 2)))] | |
1586 | "") | |
1587 | ||
1588 | (define_split | |
1589 | [(set (match_operand:BI 0 "register_operand" "") | |
1590 | (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "") | |
1591 | (const_int 0)) | |
1592 | (match_operand:DI 3 "register_operand" "")) | |
1593 | (const_int 0)))] | |
1594 | "" | |
1595 | [(set (match_dup 0) | |
1596 | (ior:BI (ne:BI (match_dup 3) (const_int 0)) | |
1597 | (match_dup 2))) | |
1598 | (parallel [(set (match_dup 0) (not:BI (match_dup 0))) | |
1599 | (clobber (scratch))])] | |
1600 | "") | |
1601 | ||
1602 | ;; ??? Incredibly hackish. Either need four proper patterns with all | |
1603 | ;; the alternatives, or rely on sched1 to split the insn and hope that | |
1604 | ;; nothing bad happens to the comparisons in the meantime. | |
1605 | ;; | |
1606 | ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming | |
1607 | ;; that we're doing height reduction. | |
1608 | ; | |
1609 | ;(define_insn_and_split "" | |
1610 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1611 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1612 | ; [(match_operand 2 "" "") | |
1613 | ; (match_operand 3 "" "")]) | |
1614 | ; (match_operator:BI 4 "comparison_operator" | |
1615 | ; [(match_operand 5 "" "") | |
1616 | ; (match_operand 6 "" "")])) | |
1617 | ; (match_dup 0)))] | |
1618 | ; "flag_schedule_insns" | |
1619 | ; "#" | |
1620 | ; "" | |
1621 | ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0))) | |
1622 | ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))] | |
1623 | ; "") | |
1624 | ; | |
1625 | ;(define_insn_and_split "" | |
1626 | ; [(set (match_operand:BI 0 "register_operand" "=c") | |
1627 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1628 | ; [(match_operand 2 "" "") | |
1629 | ; (match_operand 3 "" "")]) | |
1630 | ; (match_operator:BI 4 "comparison_operator" | |
1631 | ; [(match_operand 5 "" "") | |
1632 | ; (match_operand 6 "" "")])) | |
1633 | ; (match_dup 0)))] | |
1634 | ; "flag_schedule_insns" | |
1635 | ; "#" | |
1636 | ; "" | |
1637 | ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0))) | |
1638 | ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))] | |
1639 | ; "") | |
1640 | ; | |
1641 | ;(define_split | |
1642 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1643 | ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator" | |
1644 | ; [(match_operand 2 "" "") | |
1645 | ; (match_operand 3 "" "")]) | |
1646 | ; (match_operand:BI 7 "register_operand" "")) | |
1647 | ; (and:BI (match_operator:BI 4 "comparison_operator" | |
1648 | ; [(match_operand 5 "" "") | |
1649 | ; (match_operand 6 "" "")]) | |
1650 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1651 | ; "" | |
1652 | ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8))) | |
1653 | ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4)) | |
1654 | ; (match_dup 0)))] | |
1655 | ; "") | |
1656 | ; | |
1657 | ;(define_split | |
1658 | ; [(set (match_operand:BI 0 "register_operand" "") | |
1659 | ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator" | |
1660 | ; [(match_operand 2 "" "") | |
1661 | ; (match_operand 3 "" "")]) | |
1662 | ; (match_operand:BI 7 "register_operand" "")) | |
1663 | ; (ior:BI (match_operator:BI 4 "comparison_operator" | |
1664 | ; [(match_operand 5 "" "") | |
1665 | ; (match_operand 6 "" "")]) | |
1666 | ; (match_operand:BI 8 "register_operand" ""))))] | |
1667 | ; "" | |
1668 | ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8))) | |
1669 | ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4)) | |
1670 | ; (match_dup 0)))] | |
1671 | ; "") | |
1672 | ||
1673 | ;; Try harder to avoid predicate copies by duplicating compares. | |
1674 | ;; Note that we'll have already split the predicate copy, which | |
1675 | ;; is kind of a pain, but oh well. | |
1676 | ||
1677 | (define_peephole2 | |
1678 | [(set (match_operand:BI 0 "register_operand" "") | |
1679 | (match_operand:BI 1 "comparison_operator" "")) | |
1680 | (set (match_operand:CCI 2 "register_operand" "") | |
1681 | (match_operand:CCI 3 "register_operand" "")) | |
1682 | (set (match_operand:CCI 4 "register_operand" "") | |
1683 | (match_operand:CCI 5 "register_operand" "")) | |
1684 | (set (match_operand:BI 6 "register_operand" "") | |
1685 | (unspec:BI [(match_dup 6)] 7))] | |
1686 | "REGNO (operands[3]) == REGNO (operands[0]) | |
1687 | && REGNO (operands[4]) == REGNO (operands[0]) + 1 | |
1688 | && REGNO (operands[4]) == REGNO (operands[2]) + 1 | |
1689 | && REGNO (operands[6]) == REGNO (operands[2])" | |
1690 | [(set (match_dup 0) (match_dup 1)) | |
1691 | (set (match_dup 6) (match_dup 7))] | |
1692 | "operands[7] = copy_rtx (operands[1]);") | |
1693 | \f | |
1694 | ;; :::::::::::::::::::: | |
1695 | ;; :: | |
cf1f6ae3 RH |
1696 | ;; :: 16 bit Integer arithmetic |
1697 | ;; :: | |
1698 | ;; :::::::::::::::::::: | |
1699 | ||
1700 | (define_insn "mulhi3" | |
1701 | [(set (match_operand:HI 0 "gr_register_operand" "=r") | |
1702 | (mult:HI (match_operand:HI 1 "gr_register_operand" "r") | |
1703 | (match_operand:HI 2 "gr_register_operand" "r")))] | |
1704 | "" | |
2a7ffc85 | 1705 | "pmpy2.r %0 = %1, %2" |
52e12ad0 | 1706 | [(set_attr "itanium_class" "mmmul")]) |
cf1f6ae3 RH |
1707 | |
1708 | \f | |
1709 | ;; :::::::::::::::::::: | |
c65ebc55 JW |
1710 | ;; :: |
1711 | ;; :: 32 bit Integer arithmetic | |
1712 | ;; :: | |
1713 | ;; :::::::::::::::::::: | |
1714 | ||
058557c4 | 1715 | (define_insn "addsi3" |
0551c32d RH |
1716 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
1717 | (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a") | |
1718 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
1719 | "" |
1720 | "@ | |
1721 | add %0 = %1, %2 | |
1722 | adds %0 = %2, %1 | |
1723 | addl %0 = %2, %1" | |
52e12ad0 | 1724 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1725 | |
1726 | (define_insn "*addsi3_plus1" | |
0551c32d RH |
1727 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1728 | (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r") | |
1729 | (match_operand:SI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
1730 | (const_int 1)))] |
1731 | "" | |
1732 | "add %0 = %1, %2, 1" | |
52e12ad0 | 1733 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1734 | |
5527bf14 | 1735 | (define_insn "*addsi3_plus1_alt" |
0551c32d RH |
1736 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1737 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
5527bf14 RH |
1738 | (const_int 2)) |
1739 | (const_int 1)))] | |
1740 | "" | |
1741 | "add %0 = %1, %1, 1" | |
52e12ad0 | 1742 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 1743 | |
058557c4 | 1744 | (define_insn "*addsi3_shladd" |
0551c32d RH |
1745 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1746 | (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r") | |
058557c4 | 1747 | (match_operand:SI 2 "shladd_operand" "n")) |
0551c32d | 1748 | (match_operand:SI 3 "gr_register_operand" "r")))] |
c65ebc55 | 1749 | "" |
058557c4 | 1750 | "shladd %0 = %1, %S2, %3" |
52e12ad0 | 1751 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 1752 | |
058557c4 | 1753 | (define_insn "subsi3" |
0551c32d RH |
1754 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1755 | (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK") | |
1756 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1757 | "" |
1758 | "sub %0 = %1, %2" | |
52e12ad0 | 1759 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1760 | |
1761 | (define_insn "*subsi3_minus1" | |
0551c32d RH |
1762 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1763 | (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r")) | |
1764 | (match_operand:SI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1765 | "" |
1766 | "sub %0 = %2, %1, 1" | |
52e12ad0 BS |
1767 | [(set_attr "itanium_class" "ialu")]) |
1768 | ||
1769 | ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns. | |
c65ebc55 | 1770 | |
058557c4 | 1771 | (define_insn "mulsi3" |
0551c32d | 1772 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
11a13704 RH |
1773 | (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") |
1774 | (match_operand:SI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 1775 | "" |
aebf2462 | 1776 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 1777 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 | 1778 | |
655f2eb9 | 1779 | (define_insn "maddsi4" |
11a13704 RH |
1780 | [(set (match_operand:SI 0 "fr_register_operand" "=f") |
1781 | (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f") | |
1782 | (match_operand:SI 2 "grfr_register_operand" "f")) | |
1783 | (match_operand:SI 3 "grfr_register_operand" "f")))] | |
1784 | "" | |
aebf2462 | 1785 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 1786 | [(set_attr "itanium_class" "xmpy")]) |
11a13704 | 1787 | |
058557c4 | 1788 | (define_insn "negsi2" |
0551c32d RH |
1789 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
1790 | (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
1791 | "" |
1792 | "sub %0 = r0, %1" | |
52e12ad0 | 1793 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
1794 | |
1795 | (define_expand "abssi2" | |
1796 | [(set (match_dup 2) | |
f2f90c63 | 1797 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 1798 | (set (match_operand:SI 0 "gr_register_operand" "") |
f2f90c63 | 1799 | (if_then_else:SI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
1800 | (neg:SI (match_dup 1)) |
1801 | (match_dup 1)))] | |
c65ebc55 JW |
1802 | "" |
1803 | " | |
1804 | { | |
f2f90c63 | 1805 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1806 | }") |
1807 | ||
1808 | (define_expand "sminsi3" | |
1809 | [(set (match_dup 3) | |
f2f90c63 | 1810 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1811 | (match_operand:SI 2 "gr_register_operand" ""))) |
1812 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1813 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1814 | (match_dup 2) (match_dup 1)))] |
1815 | "" | |
1816 | " | |
1817 | { | |
f2f90c63 | 1818 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1819 | }") |
1820 | ||
1821 | (define_expand "smaxsi3" | |
1822 | [(set (match_dup 3) | |
f2f90c63 | 1823 | (ge:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1824 | (match_operand:SI 2 "gr_register_operand" ""))) |
1825 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1826 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1827 | (match_dup 1) (match_dup 2)))] |
1828 | "" | |
1829 | " | |
1830 | { | |
f2f90c63 | 1831 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1832 | }") |
1833 | ||
1834 | (define_expand "uminsi3" | |
1835 | [(set (match_dup 3) | |
f2f90c63 | 1836 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1837 | (match_operand:SI 2 "gr_register_operand" ""))) |
1838 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1839 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1840 | (match_dup 2) (match_dup 1)))] |
1841 | "" | |
1842 | " | |
1843 | { | |
f2f90c63 | 1844 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1845 | }") |
1846 | ||
1847 | (define_expand "umaxsi3" | |
1848 | [(set (match_dup 3) | |
f2f90c63 | 1849 | (geu:BI (match_operand:SI 1 "gr_register_operand" "") |
0551c32d RH |
1850 | (match_operand:SI 2 "gr_register_operand" ""))) |
1851 | (set (match_operand:SI 0 "gr_register_operand" "") | |
f2f90c63 | 1852 | (if_then_else:SI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
1853 | (match_dup 1) (match_dup 2)))] |
1854 | "" | |
1855 | " | |
1856 | { | |
f2f90c63 | 1857 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
1858 | }") |
1859 | ||
655f2eb9 RH |
1860 | (define_expand "divsi3" |
1861 | [(set (match_operand:SI 0 "register_operand" "") | |
1862 | (div:SI (match_operand:SI 1 "general_operand" "") | |
1863 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1864 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1865 | " |
1866 | { | |
1867 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1868 | ||
1869 | op0_tf = gen_reg_rtx (TFmode); | |
1870 | op0_di = gen_reg_rtx (DImode); | |
1871 | ||
1872 | if (CONSTANT_P (operands[1])) | |
1873 | operands[1] = force_reg (SImode, operands[1]); | |
1874 | op1_tf = gen_reg_rtx (TFmode); | |
1875 | expand_float (op1_tf, operands[1], 0); | |
1876 | ||
1877 | if (CONSTANT_P (operands[2])) | |
1878 | operands[2] = force_reg (SImode, operands[2]); | |
1879 | op2_tf = gen_reg_rtx (TFmode); | |
1880 | expand_float (op2_tf, operands[2], 0); | |
1881 | ||
1882 | /* 2^-34 */ | |
1883 | #if 0 | |
1884 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1885 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1886 | twon34 = force_reg (TFmode, twon34); | |
1887 | #else | |
1888 | twon34 = gen_reg_rtx (TFmode); | |
1889 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1890 | #endif | |
1891 | ||
1892 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1893 | ||
1894 | emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1895 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1896 | DONE; | |
1897 | }") | |
1898 | ||
1899 | (define_expand "modsi3" | |
1900 | [(set (match_operand:SI 0 "register_operand" "") | |
1901 | (mod:SI (match_operand:SI 1 "general_operand" "") | |
1902 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1903 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1904 | " |
1905 | { | |
1906 | rtx op2_neg, op1_di, div; | |
1907 | ||
1908 | div = gen_reg_rtx (SImode); | |
1909 | emit_insn (gen_divsi3 (div, operands[1], operands[2])); | |
1910 | ||
1911 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1912 | ||
1913 | /* This is a trick to get us to reuse the value that we're sure to | |
1914 | have already copied to the FP regs. */ | |
1915 | op1_di = gen_reg_rtx (DImode); | |
1916 | convert_move (op1_di, operands[1], 0); | |
1917 | ||
1918 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1919 | gen_lowpart (SImode, op1_di))); | |
1920 | DONE; | |
1921 | }") | |
1922 | ||
1923 | (define_expand "udivsi3" | |
1924 | [(set (match_operand:SI 0 "register_operand" "") | |
1925 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
1926 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1927 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1928 | " |
1929 | { | |
1930 | rtx op1_tf, op2_tf, op0_tf, op0_di, twon34; | |
1931 | ||
1932 | op0_tf = gen_reg_rtx (TFmode); | |
1933 | op0_di = gen_reg_rtx (DImode); | |
1934 | ||
1935 | if (CONSTANT_P (operands[1])) | |
1936 | operands[1] = force_reg (SImode, operands[1]); | |
1937 | op1_tf = gen_reg_rtx (TFmode); | |
1938 | expand_float (op1_tf, operands[1], 1); | |
1939 | ||
1940 | if (CONSTANT_P (operands[2])) | |
1941 | operands[2] = force_reg (SImode, operands[2]); | |
1942 | op2_tf = gen_reg_rtx (TFmode); | |
1943 | expand_float (op2_tf, operands[2], 1); | |
1944 | ||
1945 | /* 2^-34 */ | |
1946 | #if 0 | |
1947 | twon34 = (CONST_DOUBLE_FROM_REAL_VALUE | |
1948 | (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode)); | |
1949 | twon34 = force_reg (TFmode, twon34); | |
1950 | #else | |
1951 | twon34 = gen_reg_rtx (TFmode); | |
1952 | convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0); | |
1953 | #endif | |
1954 | ||
1955 | emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34)); | |
1956 | ||
1957 | emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx)); | |
1958 | emit_move_insn (operands[0], gen_lowpart (SImode, op0_di)); | |
1959 | DONE; | |
1960 | }") | |
1961 | ||
1962 | (define_expand "umodsi3" | |
1963 | [(set (match_operand:SI 0 "register_operand" "") | |
1964 | (umod:SI (match_operand:SI 1 "general_operand" "") | |
1965 | (match_operand:SI 2 "general_operand" "")))] | |
23c108af | 1966 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1967 | " |
1968 | { | |
1969 | rtx op2_neg, op1_di, div; | |
1970 | ||
1971 | div = gen_reg_rtx (SImode); | |
1972 | emit_insn (gen_udivsi3 (div, operands[1], operands[2])); | |
1973 | ||
1974 | op2_neg = expand_unop (SImode, neg_optab, operands[2], NULL_RTX, 0); | |
1975 | ||
1976 | /* This is a trick to get us to reuse the value that we're sure to | |
1977 | have already copied to the FP regs. */ | |
1978 | op1_di = gen_reg_rtx (DImode); | |
1979 | convert_move (op1_di, operands[1], 1); | |
1980 | ||
1981 | emit_insn (gen_maddsi4 (operands[0], div, op2_neg, | |
1982 | gen_lowpart (SImode, op1_di))); | |
1983 | DONE; | |
1984 | }") | |
1985 | ||
1986 | (define_insn_and_split "divsi3_internal" | |
1987 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
1988 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
1989 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
1990 | (clobber (match_scratch:TF 4 "=&f")) | |
1991 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 1992 | (clobber (match_scratch:BI 6 "=c")) |
655f2eb9 | 1993 | (use (match_operand:TF 3 "fr_register_operand" "f"))] |
23c108af | 1994 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
1995 | "#" |
1996 | "&& reload_completed" | |
1997 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 1998 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
1999 | (use (const_int 1))]) |
2000 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2001 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2002 | (use (const_int 1))])) | |
2003 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2004 | (parallel [(set (match_dup 5) | |
2005 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2006 | (match_dup 7))) | |
2007 | (use (const_int 1))])) | |
2008 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2009 | (parallel [(set (match_dup 4) | |
2010 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2011 | (match_dup 4))) | |
2012 | (use (const_int 1))])) | |
2013 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2014 | (parallel [(set (match_dup 5) | |
2015 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
2016 | (match_dup 3))) | |
2017 | (use (const_int 1))])) | |
2018 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2019 | (parallel [(set (match_dup 0) | |
2020 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2021 | (match_dup 4))) | |
2022 | (use (const_int 1))])) | |
2023 | ] | |
2024 | "operands[7] = CONST1_RTX (TFmode);" | |
2025 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2026 | \f |
2027 | ;; :::::::::::::::::::: | |
2028 | ;; :: | |
2029 | ;; :: 64 bit Integer arithmetic | |
2030 | ;; :: | |
2031 | ;; :::::::::::::::::::: | |
2032 | ||
2033 | (define_insn "adddi3" | |
0551c32d RH |
2034 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
2035 | (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a") | |
2036 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))] | |
c65ebc55 JW |
2037 | "" |
2038 | "@ | |
2039 | add %0 = %1, %2 | |
2040 | adds %0 = %2, %1 | |
2041 | addl %0 = %2, %1" | |
52e12ad0 | 2042 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2043 | |
2044 | (define_insn "*adddi3_plus1" | |
0551c32d RH |
2045 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2046 | (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r") | |
2047 | (match_operand:DI 2 "gr_register_operand" "r")) | |
c65ebc55 JW |
2048 | (const_int 1)))] |
2049 | "" | |
2050 | "add %0 = %1, %2, 1" | |
52e12ad0 | 2051 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2052 | |
5527bf14 RH |
2053 | ;; This has some of the same problems as shladd. We let the shladd |
2054 | ;; eliminator hack handle it, which results in the 1 being forced into | |
2055 | ;; a register, but not more ugliness here. | |
2056 | (define_insn "*adddi3_plus1_alt" | |
0551c32d RH |
2057 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2058 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
5527bf14 RH |
2059 | (const_int 2)) |
2060 | (const_int 1)))] | |
2061 | "" | |
2062 | "add %0 = %1, %1, 1" | |
52e12ad0 | 2063 | [(set_attr "itanium_class" "ialu")]) |
5527bf14 | 2064 | |
c65ebc55 | 2065 | (define_insn "subdi3" |
0551c32d RH |
2066 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2067 | (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK") | |
2068 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2069 | "" |
2070 | "sub %0 = %1, %2" | |
52e12ad0 | 2071 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2072 | |
2073 | (define_insn "*subdi3_minus1" | |
0551c32d RH |
2074 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2075 | (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r")) | |
2076 | (match_operand:DI 2 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2077 | "" |
2078 | "sub %0 = %2, %1, 1" | |
52e12ad0 | 2079 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 | 2080 | |
cee58bc0 RH |
2081 | ;; ??? Use grfr instead of fr because of virtual register elimination |
2082 | ;; and silly test cases multiplying by the frame pointer. | |
c65ebc55 | 2083 | (define_insn "muldi3" |
0551c32d | 2084 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
cee58bc0 RH |
2085 | (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2086 | (match_operand:DI 2 "grfr_register_operand" "f")))] | |
c65ebc55 | 2087 | "" |
aebf2462 | 2088 | "xmpy.l %0 = %1, %2" |
52e12ad0 | 2089 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2090 | |
2091 | ;; ??? If operand 3 is an eliminable reg, then register elimination causes the | |
2092 | ;; same problem that we have with shladd below. Unfortunately, this case is | |
2093 | ;; much harder to fix because the multiply puts the result in an FP register, | |
2094 | ;; but the add needs inputs from a general register. We add a spurious clobber | |
2095 | ;; here so that it will be present just in case register elimination gives us | |
2096 | ;; the funny result. | |
2097 | ||
2098 | ;; ??? Maybe validate_changes should try adding match_scratch clobbers? | |
2099 | ||
2100 | ;; ??? Maybe we should change how adds are canonicalized. | |
2101 | ||
655f2eb9 | 2102 | (define_insn "madddi4" |
0551c32d | 2103 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
11a13704 RH |
2104 | (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f") |
2105 | (match_operand:DI 2 "grfr_register_operand" "f")) | |
2106 | (match_operand:DI 3 "grfr_register_operand" "f"))) | |
c65ebc55 JW |
2107 | (clobber (match_scratch:DI 4 "=X"))] |
2108 | "" | |
aebf2462 | 2109 | "xma.l %0 = %1, %2, %3" |
52e12ad0 | 2110 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2111 | |
2112 | ;; This can be created by register elimination if operand3 of shladd is an | |
2113 | ;; eliminable register or has reg_equiv_constant set. | |
2114 | ||
2115 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
2116 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
655f2eb9 | 2117 | ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded |
c65ebc55 JW |
2118 | ;; incorrectly. |
2119 | ||
655f2eb9 | 2120 | (define_insn "*madddi4_elim" |
c65ebc55 | 2121 | [(set (match_operand:DI 0 "register_operand" "=&r") |
13da91fd RH |
2122 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f") |
2123 | (match_operand:DI 2 "register_operand" "f")) | |
2124 | (match_operand:DI 3 "register_operand" "f")) | |
c65ebc55 | 2125 | (match_operand:DI 4 "nonmemory_operand" "rI"))) |
13da91fd | 2126 | (clobber (match_scratch:DI 5 "=f"))] |
c65ebc55 JW |
2127 | "reload_in_progress" |
2128 | "#" | |
52e12ad0 | 2129 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 2130 | |
c65ebc55 JW |
2131 | (define_split |
2132 | [(set (match_operand:DI 0 "register_operand" "") | |
2133 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "") | |
2134 | (match_operand:DI 2 "register_operand" "")) | |
2135 | (match_operand:DI 3 "register_operand" "")) | |
0551c32d | 2136 | (match_operand:DI 4 "gr_reg_or_14bit_operand" ""))) |
c65ebc55 JW |
2137 | (clobber (match_scratch:DI 5 ""))] |
2138 | "reload_completed" | |
2139 | [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
2140 | (match_dup 3))) | |
2141 | (clobber (match_dup 0))]) | |
c65ebc55 | 2142 | (set (match_dup 0) (match_dup 5)) |
c65ebc55 JW |
2143 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
2144 | "") | |
2145 | ||
2146 | ;; ??? There are highpart multiply and add instructions, but we have no way | |
2147 | ;; to generate them. | |
2148 | ||
2149 | (define_insn "smuldi3_highpart" | |
0551c32d | 2150 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2151 | (truncate:DI |
2152 | (lshiftrt:TI | |
0551c32d RH |
2153 | (mult:TI (sign_extend:TI |
2154 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2155 | (sign_extend:TI | |
2156 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2157 | (const_int 64))))] |
2158 | "" | |
aebf2462 | 2159 | "xmpy.h %0 = %1, %2" |
52e12ad0 | 2160 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2161 | |
2162 | (define_insn "umuldi3_highpart" | |
0551c32d | 2163 | [(set (match_operand:DI 0 "fr_register_operand" "=f") |
c65ebc55 JW |
2164 | (truncate:DI |
2165 | (lshiftrt:TI | |
0551c32d RH |
2166 | (mult:TI (zero_extend:TI |
2167 | (match_operand:DI 1 "fr_register_operand" "f")) | |
2168 | (zero_extend:TI | |
2169 | (match_operand:DI 2 "fr_register_operand" "f"))) | |
c65ebc55 JW |
2170 | (const_int 64))))] |
2171 | "" | |
aebf2462 | 2172 | "xmpy.hu %0 = %1, %2" |
52e12ad0 | 2173 | [(set_attr "itanium_class" "xmpy")]) |
c65ebc55 JW |
2174 | |
2175 | (define_insn "negdi2" | |
0551c32d RH |
2176 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2177 | (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
2178 | "" |
2179 | "sub %0 = r0, %1" | |
52e12ad0 | 2180 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
2181 | |
2182 | (define_expand "absdi2" | |
2183 | [(set (match_dup 2) | |
f2f90c63 | 2184 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
0551c32d | 2185 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2186 | (if_then_else:DI (eq (match_dup 2) (const_int 0)) |
e5bde68a RH |
2187 | (neg:DI (match_dup 1)) |
2188 | (match_dup 1)))] | |
c65ebc55 JW |
2189 | "" |
2190 | " | |
2191 | { | |
f2f90c63 | 2192 | operands[2] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2193 | }") |
2194 | ||
2195 | (define_expand "smindi3" | |
2196 | [(set (match_dup 3) | |
f2f90c63 | 2197 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2198 | (match_operand:DI 2 "gr_register_operand" ""))) |
2199 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2200 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2201 | (match_dup 2) (match_dup 1)))] |
2202 | "" | |
2203 | " | |
2204 | { | |
f2f90c63 | 2205 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2206 | }") |
2207 | ||
2208 | (define_expand "smaxdi3" | |
2209 | [(set (match_dup 3) | |
f2f90c63 | 2210 | (ge:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2211 | (match_operand:DI 2 "gr_register_operand" ""))) |
2212 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2213 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2214 | (match_dup 1) (match_dup 2)))] |
2215 | "" | |
2216 | " | |
2217 | { | |
f2f90c63 | 2218 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2219 | }") |
2220 | ||
2221 | (define_expand "umindi3" | |
2222 | [(set (match_dup 3) | |
f2f90c63 | 2223 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2224 | (match_operand:DI 2 "gr_register_operand" ""))) |
2225 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2226 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2227 | (match_dup 2) (match_dup 1)))] |
2228 | "" | |
2229 | " | |
2230 | { | |
f2f90c63 | 2231 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2232 | }") |
2233 | ||
2234 | (define_expand "umaxdi3" | |
2235 | [(set (match_dup 3) | |
f2f90c63 | 2236 | (geu:BI (match_operand:DI 1 "gr_register_operand" "") |
0551c32d RH |
2237 | (match_operand:DI 2 "gr_register_operand" ""))) |
2238 | (set (match_operand:DI 0 "gr_register_operand" "") | |
f2f90c63 | 2239 | (if_then_else:DI (ne (match_dup 3) (const_int 0)) |
c65ebc55 JW |
2240 | (match_dup 1) (match_dup 2)))] |
2241 | "" | |
2242 | " | |
2243 | { | |
f2f90c63 | 2244 | operands[3] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2245 | }") |
2246 | ||
2247 | (define_expand "ffsdi2" | |
2248 | [(set (match_dup 6) | |
f2f90c63 | 2249 | (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0))) |
c65ebc55 JW |
2250 | (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1))) |
2251 | (set (match_dup 5) (const_int 0)) | |
2252 | (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2))) | |
2253 | (set (match_dup 4) (unspec:DI [(match_dup 3)] 8)) | |
0551c32d | 2254 | (set (match_operand:DI 0 "gr_register_operand" "") |
f2f90c63 | 2255 | (if_then_else:DI (ne (match_dup 6) (const_int 0)) |
c65ebc55 JW |
2256 | (match_dup 5) (match_dup 4)))] |
2257 | "" | |
2258 | " | |
2259 | { | |
2260 | operands[2] = gen_reg_rtx (DImode); | |
2261 | operands[3] = gen_reg_rtx (DImode); | |
2262 | operands[4] = gen_reg_rtx (DImode); | |
2263 | operands[5] = gen_reg_rtx (DImode); | |
f2f90c63 | 2264 | operands[6] = gen_reg_rtx (BImode); |
c65ebc55 JW |
2265 | }") |
2266 | ||
2267 | (define_insn "*popcnt" | |
0551c32d RH |
2268 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
2269 | (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))] | |
c65ebc55 JW |
2270 | "" |
2271 | "popcnt %0 = %1" | |
52e12ad0 | 2272 | [(set_attr "itanium_class" "mmmul")]) |
c65ebc55 | 2273 | |
655f2eb9 RH |
2274 | (define_expand "divdi3" |
2275 | [(set (match_operand:DI 0 "register_operand" "") | |
2276 | (div:DI (match_operand:DI 1 "general_operand" "") | |
2277 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2278 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2279 | " |
2280 | { | |
2281 | rtx op1_tf, op2_tf, op0_tf; | |
2282 | ||
2283 | op0_tf = gen_reg_rtx (TFmode); | |
2284 | ||
2285 | if (CONSTANT_P (operands[1])) | |
2286 | operands[1] = force_reg (DImode, operands[1]); | |
2287 | op1_tf = gen_reg_rtx (TFmode); | |
2288 | expand_float (op1_tf, operands[1], 0); | |
2289 | ||
2290 | if (CONSTANT_P (operands[2])) | |
2291 | operands[2] = force_reg (DImode, operands[2]); | |
2292 | op2_tf = gen_reg_rtx (TFmode); | |
2293 | expand_float (op2_tf, operands[2], 0); | |
2294 | ||
2295 | if (TARGET_INLINE_DIV_LAT) | |
2296 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2297 | else | |
2298 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2299 | ||
2300 | emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2301 | DONE; | |
2302 | }") | |
2303 | ||
2304 | (define_expand "moddi3" | |
2305 | [(set (match_operand:DI 0 "register_operand" "") | |
2306 | (mod:SI (match_operand:DI 1 "general_operand" "") | |
2307 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2308 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2309 | " |
2310 | { | |
2311 | rtx op2_neg, div; | |
2312 | ||
2313 | div = gen_reg_rtx (DImode); | |
2314 | emit_insn (gen_divdi3 (div, operands[1], operands[2])); | |
2315 | ||
2316 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2317 | ||
2318 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2319 | DONE; | |
2320 | }") | |
2321 | ||
2322 | (define_expand "udivdi3" | |
2323 | [(set (match_operand:DI 0 "register_operand" "") | |
2324 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
2325 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2326 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2327 | " |
2328 | { | |
2329 | rtx op1_tf, op2_tf, op0_tf; | |
2330 | ||
2331 | op0_tf = gen_reg_rtx (TFmode); | |
2332 | ||
2333 | if (CONSTANT_P (operands[1])) | |
2334 | operands[1] = force_reg (DImode, operands[1]); | |
2335 | op1_tf = gen_reg_rtx (TFmode); | |
2336 | expand_float (op1_tf, operands[1], 1); | |
2337 | ||
2338 | if (CONSTANT_P (operands[2])) | |
2339 | operands[2] = force_reg (DImode, operands[2]); | |
2340 | op2_tf = gen_reg_rtx (TFmode); | |
2341 | expand_float (op2_tf, operands[2], 1); | |
2342 | ||
2343 | if (TARGET_INLINE_DIV_LAT) | |
2344 | emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf)); | |
2345 | else | |
2346 | emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf)); | |
2347 | ||
2348 | emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx)); | |
2349 | DONE; | |
2350 | }") | |
2351 | ||
2352 | (define_expand "umoddi3" | |
2353 | [(set (match_operand:DI 0 "register_operand" "") | |
2354 | (umod:DI (match_operand:DI 1 "general_operand" "") | |
2355 | (match_operand:DI 2 "general_operand" "")))] | |
23c108af | 2356 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
655f2eb9 RH |
2357 | " |
2358 | { | |
2359 | rtx op2_neg, div; | |
2360 | ||
2361 | div = gen_reg_rtx (DImode); | |
2362 | emit_insn (gen_udivdi3 (div, operands[1], operands[2])); | |
2363 | ||
2364 | op2_neg = expand_unop (DImode, neg_optab, operands[2], NULL_RTX, 0); | |
2365 | ||
2366 | emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1])); | |
2367 | DONE; | |
2368 | }") | |
2369 | ||
2370 | (define_insn_and_split "divdi3_internal_lat" | |
2371 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2372 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2373 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2374 | (clobber (match_scratch:TF 3 "=&f")) | |
2375 | (clobber (match_scratch:TF 4 "=&f")) | |
2376 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2377 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2378 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
655f2eb9 RH |
2379 | "#" |
2380 | "&& reload_completed" | |
2381 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2382 | (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2383 | (use (const_int 1))]) |
2384 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2385 | (parallel [(set (match_dup 3) | |
2386 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2387 | (match_dup 7))) | |
2388 | (use (const_int 1))])) | |
2389 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2390 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
2391 | (use (const_int 1))])) | |
2392 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2393 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
2394 | (use (const_int 1))])) | |
2395 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2396 | (parallel [(set (match_dup 4) | |
2397 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
2398 | (match_dup 4))) | |
2399 | (use (const_int 1))])) | |
2400 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2401 | (parallel [(set (match_dup 0) | |
2402 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2403 | (match_dup 0))) | |
2404 | (use (const_int 1))])) | |
2405 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2406 | (parallel [(set (match_dup 3) | |
2407 | (plus:TF (mult:TF (match_dup 5) (match_dup 4)) | |
2408 | (match_dup 4))) | |
2409 | (use (const_int 1))])) | |
2410 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2411 | (parallel [(set (match_dup 0) | |
2412 | (plus:TF (mult:TF (match_dup 5) (match_dup 0)) | |
2413 | (match_dup 0))) | |
2414 | (use (const_int 1))])) | |
2415 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2416 | (parallel [(set (match_dup 4) | |
2417 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2418 | (match_dup 1))) | |
2419 | (use (const_int 1))])) | |
2420 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2421 | (parallel [(set (match_dup 0) | |
2422 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2423 | (match_dup 3))) | |
2424 | (use (const_int 1))])) | |
2425 | ] | |
2426 | "operands[7] = CONST1_RTX (TFmode);" | |
2427 | [(set_attr "predicable" "no")]) | |
2428 | ||
2429 | (define_insn_and_split "divdi3_internal_thr" | |
2430 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
2431 | (float:TF (div:SI (match_operand:TF 1 "fr_register_operand" "f") | |
2432 | (match_operand:TF 2 "fr_register_operand" "f")))) | |
2433 | (clobber (match_scratch:TF 3 "=&f")) | |
2434 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2435 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2436 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
655f2eb9 RH |
2437 | "#" |
2438 | "&& reload_completed" | |
2439 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 2440 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
655f2eb9 RH |
2441 | (use (const_int 1))]) |
2442 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2443 | (parallel [(set (match_dup 3) | |
2444 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
2445 | (match_dup 6))) | |
2446 | (use (const_int 1))])) | |
2447 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2448 | (parallel [(set (match_dup 0) | |
2449 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2450 | (match_dup 0))) | |
2451 | (use (const_int 1))])) | |
2452 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2453 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
2454 | (use (const_int 1))])) | |
2455 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2456 | (parallel [(set (match_dup 0) | |
2457 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
2458 | (match_dup 0))) | |
2459 | (use (const_int 1))])) | |
2460 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2461 | (parallel [(set (match_dup 3) (mult:TF (match_dup 0) (match_dup 1))) | |
2462 | (use (const_int 1))])) | |
2463 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2464 | (parallel [(set (match_dup 4) | |
2465 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
2466 | (match_dup 1))) | |
2467 | (use (const_int 1))])) | |
2468 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2469 | (parallel [(set (match_dup 0) | |
2470 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
2471 | (match_dup 3))) | |
2472 | (use (const_int 1))])) | |
2473 | ] | |
2474 | "operands[6] = CONST1_RTX (TFmode);" | |
2475 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2476 | \f |
2477 | ;; :::::::::::::::::::: | |
2478 | ;; :: | |
2479 | ;; :: 32 bit floating point arithmetic | |
2480 | ;; :: | |
2481 | ;; :::::::::::::::::::: | |
2482 | ||
2483 | (define_insn "addsf3" | |
0551c32d RH |
2484 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2485 | (plus:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2486 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2487 | "" |
aebf2462 | 2488 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2489 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2490 | |
2491 | (define_insn "subsf3" | |
0551c32d RH |
2492 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2493 | (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
2494 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2495 | "" |
aebf2462 | 2496 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2497 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2498 | |
2499 | (define_insn "mulsf3" | |
0551c32d RH |
2500 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2501 | (mult:SF (match_operand:SF 1 "fr_register_operand" "%f") | |
2502 | (match_operand:SF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2503 | "" |
aebf2462 | 2504 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2505 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2506 | |
2507 | (define_insn "abssf2" | |
0551c32d RH |
2508 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2509 | (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2510 | "" |
aebf2462 | 2511 | "fabs %0 = %1" |
52e12ad0 | 2512 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2513 | |
2514 | (define_insn "negsf2" | |
0551c32d RH |
2515 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2516 | (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2517 | "" |
aebf2462 | 2518 | "fneg %0 = %1" |
52e12ad0 | 2519 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2520 | |
2521 | (define_insn "*nabssf2" | |
0551c32d RH |
2522 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2523 | (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2524 | "" |
aebf2462 | 2525 | "fnegabs %0 = %1" |
52e12ad0 | 2526 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2527 | |
2528 | (define_insn "minsf3" | |
0551c32d RH |
2529 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2530 | (smin:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2531 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2532 | "" |
aebf2462 | 2533 | "fmin %0 = %1, %F2" |
52e12ad0 | 2534 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2535 | |
2536 | (define_insn "maxsf3" | |
0551c32d RH |
2537 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2538 | (smax:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2539 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2540 | "" |
aebf2462 | 2541 | "fmax %0 = %1, %F2" |
52e12ad0 | 2542 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2543 | |
655f2eb9 | 2544 | (define_insn "*maddsf4" |
0551c32d RH |
2545 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2546 | (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2547 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2548 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2549 | "" |
aebf2462 | 2550 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2551 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2552 | |
655f2eb9 | 2553 | (define_insn "*msubsf4" |
0551c32d RH |
2554 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2555 | (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2556 | (match_operand:SF 2 "fr_register_operand" "f")) | |
2557 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2558 | "" |
aebf2462 | 2559 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2560 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2561 | |
2562 | (define_insn "*nmulsf3" | |
0551c32d RH |
2563 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
2564 | (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2565 | (match_operand:SF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2566 | "" |
aebf2462 | 2567 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2568 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 JW |
2569 | |
2570 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? | |
2571 | ||
655f2eb9 | 2572 | (define_insn "*nmaddsf4" |
0551c32d | 2573 | [(set (match_operand:SF 0 "fr_register_operand" "=f") |
26102535 RH |
2574 | (plus:SF (neg:SF (mult:SF |
2575 | (match_operand:SF 1 "fr_register_operand" "f") | |
2576 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
0551c32d | 2577 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2578 | "" |
aebf2462 | 2579 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2580 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2581 | |
26102535 RH |
2582 | (define_expand "divsf3" |
2583 | [(set (match_operand:SF 0 "fr_register_operand" "") | |
2584 | (div:SF (match_operand:SF 1 "fr_register_operand" "") | |
2585 | (match_operand:SF 2 "fr_register_operand" "")))] | |
23c108af | 2586 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2587 | " |
2588 | { | |
2589 | rtx insn; | |
2590 | if (TARGET_INLINE_DIV_LAT) | |
2591 | insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]); | |
2592 | else | |
2593 | insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]); | |
2594 | emit_insn (insn); | |
2595 | DONE; | |
2596 | }") | |
2597 | ||
2598 | (define_insn_and_split "divsf3_internal_lat" | |
2599 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2600 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2601 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2602 | (clobber (match_scratch:TF 3 "=&f")) | |
2603 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2604 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2605 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2606 | "#" |
2607 | "&& reload_completed" | |
2608 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2609 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2610 | (use (const_int 1))]) |
2611 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2612 | (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6))) | |
2613 | (use (const_int 1))])) | |
2614 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2615 | (parallel [(set (match_dup 4) | |
2616 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2617 | (match_dup 10))) | |
2618 | (use (const_int 1))])) | |
2619 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2620 | (parallel [(set (match_dup 3) | |
2621 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2622 | (match_dup 3))) | |
2623 | (use (const_int 1))])) | |
2624 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2625 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2626 | (use (const_int 1))])) | |
2627 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2628 | (parallel [(set (match_dup 3) | |
2629 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2630 | (match_dup 3))) | |
2631 | (use (const_int 1))])) | |
2632 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2633 | (parallel [(set (match_dup 4) (mult:TF (match_dup 4) (match_dup 4))) | |
2634 | (use (const_int 1))])) | |
2635 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2636 | (parallel [(set (match_dup 9) | |
2637 | (float_truncate:DF | |
2638 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2639 | (match_dup 3)))) | |
2640 | (use (const_int 1))])) | |
2641 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2642 | (set (match_dup 0) | |
2643 | (float_truncate:SF (match_dup 6)))) | |
2644 | ] | |
2645 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2646 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2647 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2648 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0])); | |
2649 | operands[10] = CONST1_RTX (TFmode);" | |
2650 | [(set_attr "predicable" "no")]) | |
2651 | ||
2652 | (define_insn_and_split "divsf3_internal_thr" | |
2653 | [(set (match_operand:SF 0 "fr_register_operand" "=&f") | |
2654 | (div:SF (match_operand:SF 1 "fr_register_operand" "f") | |
2655 | (match_operand:SF 2 "fr_register_operand" "f"))) | |
2656 | (clobber (match_scratch:TF 3 "=&f")) | |
2657 | (clobber (match_scratch:TF 4 "=f")) | |
f2f90c63 | 2658 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2659 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2660 | "#" |
2661 | "&& reload_completed" | |
2662 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2663 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2664 | (use (const_int 1))]) |
2665 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2666 | (parallel [(set (match_dup 3) | |
2667 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2668 | (match_dup 10))) | |
2669 | (use (const_int 1))])) | |
2670 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2671 | (parallel [(set (match_dup 3) | |
2672 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
2673 | (match_dup 3))) | |
2674 | (use (const_int 1))])) | |
2675 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2676 | (parallel [(set (match_dup 6) | |
2677 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
2678 | (match_dup 6))) | |
2679 | (use (const_int 1))])) | |
2680 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2681 | (parallel [(set (match_dup 9) | |
2682 | (float_truncate:SF | |
2683 | (mult:TF (match_dup 7) (match_dup 6)))) | |
2684 | (use (const_int 1))])) | |
2685 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2686 | (parallel [(set (match_dup 4) | |
2687 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 3))) | |
2688 | (match_dup 7))) | |
2689 | (use (const_int 1))])) | |
2690 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2691 | (set (match_dup 0) | |
2692 | (float_truncate:SF | |
2693 | (plus:TF (mult:TF (match_dup 4) (match_dup 6)) | |
2694 | (match_dup 3))))) | |
2695 | ] | |
2696 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2697 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2698 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2699 | operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3])); | |
2700 | operands[10] = CONST1_RTX (TFmode);" | |
2701 | [(set_attr "predicable" "no")]) | |
c65ebc55 JW |
2702 | \f |
2703 | ;; :::::::::::::::::::: | |
2704 | ;; :: | |
2705 | ;; :: 64 bit floating point arithmetic | |
2706 | ;; :: | |
2707 | ;; :::::::::::::::::::: | |
2708 | ||
2709 | (define_insn "adddf3" | |
0551c32d RH |
2710 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2711 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2712 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2713 | "" |
aebf2462 | 2714 | "fadd.d %0 = %1, %F2" |
52e12ad0 | 2715 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2716 | |
26102535 RH |
2717 | (define_insn "*adddf3_trunc" |
2718 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2719 | (float_truncate:SF | |
2720 | (plus:DF (match_operand:DF 1 "fr_register_operand" "%f") | |
2721 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2722 | "" | |
aebf2462 | 2723 | "fadd.s %0 = %1, %F2" |
52e12ad0 | 2724 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2725 | |
c65ebc55 | 2726 | (define_insn "subdf3" |
0551c32d RH |
2727 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2728 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2729 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2730 | "" |
aebf2462 | 2731 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 2732 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2733 | |
26102535 RH |
2734 | (define_insn "*subdf3_trunc" |
2735 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2736 | (float_truncate:SF | |
2737 | (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") | |
2738 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))] | |
2739 | "" | |
aebf2462 | 2740 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 2741 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2742 | |
c65ebc55 | 2743 | (define_insn "muldf3" |
0551c32d RH |
2744 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2745 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2746 | (match_operand:DF 2 "fr_register_operand" "f")))] | |
c65ebc55 | 2747 | "" |
aebf2462 | 2748 | "fmpy.d %0 = %1, %2" |
52e12ad0 | 2749 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2750 | |
26102535 RH |
2751 | (define_insn "*muldf3_trunc" |
2752 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2753 | (float_truncate:SF | |
2754 | (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2755 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
2756 | "" | |
aebf2462 | 2757 | "fmpy.s %0 = %1, %2" |
52e12ad0 | 2758 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2759 | |
c65ebc55 | 2760 | (define_insn "absdf2" |
0551c32d RH |
2761 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2762 | (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2763 | "" |
aebf2462 | 2764 | "fabs %0 = %1" |
52e12ad0 | 2765 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2766 | |
2767 | (define_insn "negdf2" | |
0551c32d RH |
2768 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2769 | (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))] | |
c65ebc55 | 2770 | "" |
aebf2462 | 2771 | "fneg %0 = %1" |
52e12ad0 | 2772 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2773 | |
2774 | (define_insn "*nabsdf2" | |
0551c32d RH |
2775 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2776 | (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))] | |
c65ebc55 | 2777 | "" |
aebf2462 | 2778 | "fnegabs %0 = %1" |
52e12ad0 | 2779 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2780 | |
2781 | (define_insn "mindf3" | |
0551c32d RH |
2782 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2783 | (smin:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2784 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2785 | "" |
aebf2462 | 2786 | "fmin %0 = %1, %F2" |
52e12ad0 | 2787 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 JW |
2788 | |
2789 | (define_insn "maxdf3" | |
0551c32d RH |
2790 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2791 | (smax:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2792 | (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2793 | "" |
aebf2462 | 2794 | "fmax %0 = %1, %F2" |
52e12ad0 | 2795 | [(set_attr "itanium_class" "fmisc")]) |
c65ebc55 | 2796 | |
655f2eb9 | 2797 | (define_insn "*madddf4" |
0551c32d RH |
2798 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2799 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2800 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2801 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2802 | "" |
aebf2462 | 2803 | "fma.d %0 = %1, %2, %F3" |
52e12ad0 | 2804 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2805 | |
26102535 RH |
2806 | (define_insn "*madddf4_trunc" |
2807 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2808 | (float_truncate:SF | |
2809 | (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2810 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2811 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2812 | "" | |
aebf2462 | 2813 | "fma.s %0 = %1, %2, %F3" |
52e12ad0 | 2814 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2815 | |
655f2eb9 | 2816 | (define_insn "*msubdf4" |
0551c32d RH |
2817 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2818 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2819 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2820 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] | |
c65ebc55 | 2821 | "" |
aebf2462 | 2822 | "fms.d %0 = %1, %2, %F3" |
52e12ad0 | 2823 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2824 | |
26102535 RH |
2825 | (define_insn "*msubdf4_trunc" |
2826 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2827 | (float_truncate:SF | |
2828 | (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2829 | (match_operand:DF 2 "fr_register_operand" "f")) | |
2830 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2831 | "" | |
aebf2462 | 2832 | "fms.s %0 = %1, %2, %F3" |
52e12ad0 | 2833 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2834 | |
c65ebc55 | 2835 | (define_insn "*nmuldf3" |
0551c32d RH |
2836 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
2837 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2838 | (match_operand:DF 2 "fr_register_operand" "f"))))] | |
c65ebc55 | 2839 | "" |
aebf2462 | 2840 | "fnmpy.d %0 = %1, %2" |
52e12ad0 | 2841 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 2842 | |
26102535 RH |
2843 | (define_insn "*nmuldf3_trunc" |
2844 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2845 | (float_truncate:SF | |
2846 | (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2847 | (match_operand:DF 2 "fr_register_operand" "f")))))] | |
2848 | "" | |
aebf2462 | 2849 | "fnmpy.s %0 = %1, %2" |
52e12ad0 | 2850 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 2851 | |
c65ebc55 JW |
2852 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
2853 | ||
655f2eb9 | 2854 | (define_insn "*nmadddf4" |
0551c32d | 2855 | [(set (match_operand:DF 0 "fr_register_operand" "=f") |
26102535 RH |
2856 | (plus:DF (neg:DF (mult:DF |
2857 | (match_operand:DF 1 "fr_register_operand" "f") | |
2858 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
0551c32d | 2859 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))] |
c65ebc55 | 2860 | "" |
aebf2462 | 2861 | "fnma.d %0 = %1, %2, %F3" |
52e12ad0 | 2862 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2863 | |
2864 | (define_insn "*nmadddf4_alts" | |
2865 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
2866 | (plus:DF (neg:DF (mult:DF | |
2867 | (match_operand:DF 1 "fr_register_operand" "f") | |
2868 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2869 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))) | |
2870 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
2871 | "" | |
aebf2462 | 2872 | "fnma.d.s%4 %0 = %1, %2, %F3" |
52e12ad0 | 2873 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2874 | |
2875 | (define_insn "*nmadddf4_trunc" | |
2876 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
2877 | (float_truncate:SF | |
2878 | (plus:DF (neg:DF (mult:DF | |
2879 | (match_operand:DF 1 "fr_register_operand" "f") | |
2880 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2881 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))] | |
2882 | "" | |
aebf2462 | 2883 | "fnma.s %0 = %1, %2, %F3" |
52e12ad0 | 2884 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
2885 | |
2886 | (define_expand "divdf3" | |
2887 | [(set (match_operand:DF 0 "fr_register_operand" "") | |
2888 | (div:DF (match_operand:DF 1 "fr_register_operand" "") | |
2889 | (match_operand:DF 2 "fr_register_operand" "")))] | |
23c108af | 2890 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
2891 | " |
2892 | { | |
2893 | rtx insn; | |
2894 | if (TARGET_INLINE_DIV_LAT) | |
2895 | insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]); | |
2896 | else | |
2897 | insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]); | |
2898 | emit_insn (insn); | |
2899 | DONE; | |
2900 | }") | |
2901 | ||
2902 | (define_insn_and_split "divdf3_internal_lat" | |
2903 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2904 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2905 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2906 | (clobber (match_scratch:TF 3 "=&f")) | |
2907 | (clobber (match_scratch:TF 4 "=&f")) | |
2908 | (clobber (match_scratch:TF 5 "=&f")) | |
f2f90c63 | 2909 | (clobber (match_scratch:BI 6 "=c"))] |
23c108af | 2910 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
2911 | "#" |
2912 | "&& reload_completed" | |
2913 | [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9))) | |
f2f90c63 | 2914 | (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5)) |
26102535 RH |
2915 | (use (const_int 1))]) |
2916 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2917 | (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7))) | |
2918 | (use (const_int 1))])) | |
2919 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2920 | (parallel [(set (match_dup 4) | |
2921 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 7))) | |
2922 | (match_dup 12))) | |
2923 | (use (const_int 1))])) | |
2924 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2925 | (parallel [(set (match_dup 3) | |
2926 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2927 | (match_dup 3))) | |
2928 | (use (const_int 1))])) | |
2929 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2930 | (parallel [(set (match_dup 5) (mult:TF (match_dup 4) (match_dup 4))) | |
2931 | (use (const_int 1))])) | |
2932 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2933 | (parallel [(set (match_dup 7) | |
2934 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2935 | (match_dup 7))) | |
2936 | (use (const_int 1))])) | |
2937 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2938 | (parallel [(set (match_dup 3) | |
2939 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
2940 | (match_dup 3))) | |
2941 | (use (const_int 1))])) | |
2942 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2943 | (parallel [(set (match_dup 4) (mult:TF (match_dup 5) (match_dup 5))) | |
2944 | (use (const_int 1))])) | |
2945 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2946 | (parallel [(set (match_dup 7) | |
2947 | (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2948 | (match_dup 7))) | |
2949 | (use (const_int 1))])) | |
2950 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2951 | (parallel [(set (match_dup 10) | |
2952 | (float_truncate:DF | |
2953 | (plus:TF (mult:TF (match_dup 4) (match_dup 3)) | |
2954 | (match_dup 3)))) | |
2955 | (use (const_int 1))])) | |
2956 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2957 | (parallel [(set (match_dup 7) | |
2958 | (plus:TF (mult:TF (match_dup 4) (match_dup 7)) | |
2959 | (match_dup 7))) | |
2960 | (use (const_int 1))])) | |
2961 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2962 | (parallel [(set (match_dup 11) | |
2963 | (float_truncate:DF | |
2964 | (plus:TF (neg:TF (mult:TF (match_dup 9) (match_dup 3))) | |
2965 | (match_dup 8)))) | |
2966 | (use (const_int 1))])) | |
2967 | (cond_exec (ne (match_dup 6) (const_int 0)) | |
2968 | (set (match_dup 0) | |
2969 | (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7)) | |
2970 | (match_dup 3))))) | |
2971 | ] | |
2972 | "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
2973 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
2974 | operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
2975 | operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
2976 | operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5])); | |
2977 | operands[12] = CONST1_RTX (TFmode);" | |
2978 | [(set_attr "predicable" "no")]) | |
2979 | ||
2980 | (define_insn_and_split "divdf3_internal_thr" | |
2981 | [(set (match_operand:DF 0 "fr_register_operand" "=&f") | |
2982 | (div:DF (match_operand:DF 1 "fr_register_operand" "f") | |
2983 | (match_operand:DF 2 "fr_register_operand" "f"))) | |
2984 | (clobber (match_scratch:TF 3 "=&f")) | |
2985 | (clobber (match_scratch:DF 4 "=f")) | |
f2f90c63 | 2986 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 2987 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
2988 | "#" |
2989 | "&& reload_completed" | |
2990 | [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8))) | |
f2f90c63 | 2991 | (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5)) |
26102535 RH |
2992 | (use (const_int 1))]) |
2993 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2994 | (parallel [(set (match_dup 3) | |
2995 | (plus:TF (neg:TF (mult:TF (match_dup 8) (match_dup 6))) | |
2996 | (match_dup 10))) | |
2997 | (use (const_int 1))])) | |
2998 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
2999 | (parallel [(set (match_dup 6) | |
3000 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3001 | (match_dup 6))) | |
3002 | (use (const_int 1))])) | |
3003 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3004 | (parallel [(set (match_dup 3) | |
3005 | (mult:TF (match_dup 3) (match_dup 3))) | |
3006 | (use (const_int 1))])) | |
3007 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3008 | (parallel [(set (match_dup 6) | |
3009 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3010 | (match_dup 6))) | |
3011 | (use (const_int 1))])) | |
3012 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3013 | (parallel [(set (match_dup 3) | |
3014 | (mult:TF (match_dup 3) (match_dup 3))) | |
3015 | (use (const_int 1))])) | |
3016 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3017 | (parallel [(set (match_dup 6) | |
3018 | (plus:TF (mult:TF (match_dup 3) (match_dup 6)) | |
3019 | (match_dup 6))) | |
3020 | (use (const_int 1))])) | |
3021 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3022 | (parallel [(set (match_dup 9) | |
3023 | (float_truncate:DF | |
3024 | (mult:TF (match_dup 7) (match_dup 3)))) | |
3025 | (use (const_int 1))])) | |
3026 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3027 | (parallel [(set (match_dup 4) | |
3028 | (plus:DF (neg:DF (mult:DF (match_dup 2) (match_dup 9))) | |
3029 | (match_dup 1))) | |
3030 | (use (const_int 1))])) | |
3031 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3032 | (set (match_dup 0) | |
3033 | (plus:DF (mult:DF (match_dup 4) (match_dup 0)) | |
3034 | (match_dup 9)))) | |
3035 | ] | |
3036 | "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0])); | |
3037 | operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1])); | |
3038 | operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2])); | |
3039 | operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3])); | |
3040 | operands[10] = CONST1_RTX (TFmode);" | |
3041 | [(set_attr "predicable" "no")]) | |
3f622353 RH |
3042 | \f |
3043 | ;; :::::::::::::::::::: | |
3044 | ;; :: | |
3045 | ;; :: 80 bit floating point arithmetic | |
3046 | ;; :: | |
3047 | ;; :::::::::::::::::::: | |
3048 | ||
3049 | (define_insn "addtf3" | |
0551c32d | 3050 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3051 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3052 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3053 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3054 | "fadd %0 = %F1, %F2" |
52e12ad0 | 3055 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3056 | |
26102535 RH |
3057 | (define_insn "*addtf3_truncsf" |
3058 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3059 | (float_truncate:SF | |
3060 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3061 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3062 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3063 | "fadd.s %0 = %F1, %F2" |
52e12ad0 | 3064 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3065 | |
3066 | (define_insn "*addtf3_truncdf" | |
3067 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3068 | (float_truncate:DF | |
3069 | (plus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3070 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3071 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3072 | "fadd.d %0 = %F1, %F2" |
52e12ad0 | 3073 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3074 | |
3f622353 | 3075 | (define_insn "subtf3" |
0551c32d | 3076 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3077 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3078 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3079 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3080 | "fsub %0 = %F1, %F2" |
52e12ad0 | 3081 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3082 | |
26102535 RH |
3083 | (define_insn "*subtf3_truncsf" |
3084 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3085 | (float_truncate:SF | |
3086 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3087 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3088 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3089 | "fsub.s %0 = %F1, %F2" |
52e12ad0 | 3090 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3091 | |
3092 | (define_insn "*subtf3_truncdf" | |
3093 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3094 | (float_truncate:DF | |
3095 | (minus:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3096 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3097 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3098 | "fsub.d %0 = %F1, %F2" |
52e12ad0 | 3099 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3100 | |
3f622353 | 3101 | (define_insn "multf3" |
0551c32d | 3102 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3103 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3104 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3105 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3106 | "fmpy %0 = %F1, %F2" |
52e12ad0 | 3107 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3108 | |
26102535 RH |
3109 | (define_insn "*multf3_truncsf" |
3110 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3111 | (float_truncate:SF | |
3112 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3113 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3114 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3115 | "fmpy.s %0 = %F1, %F2" |
52e12ad0 | 3116 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3117 | |
3118 | (define_insn "*multf3_truncdf" | |
3119 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3120 | (float_truncate:DF | |
3121 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3122 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3123 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3124 | "fmpy.d %0 = %F1, %F2" |
52e12ad0 | 3125 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3126 | |
655f2eb9 RH |
3127 | (define_insn "*multf3_alts" |
3128 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3129 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3130 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3131 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3132 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3133 | "fmpy.s%3 %0 = %F1, %F2" |
52e12ad0 | 3134 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3135 | |
26102535 RH |
3136 | (define_insn "*multf3_truncsf_alts" |
3137 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3138 | (float_truncate:SF | |
3139 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3140 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3141 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3142 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3143 | "fmpy.s.s%3 %0 = %F1, %F2" |
52e12ad0 | 3144 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3145 | |
3146 | (define_insn "*multf3_truncdf_alts" | |
3147 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3148 | (float_truncate:DF | |
3149 | (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3150 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))) | |
3151 | (use (match_operand:SI 3 "const_int_operand" ""))] | |
23c108af | 3152 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3153 | "fmpy.d.s%3 %0 = %F1, %F2" |
52e12ad0 | 3154 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3155 | |
3f622353 | 3156 | (define_insn "abstf2" |
0551c32d | 3157 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3158 | (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3159 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3160 | "fabs %0 = %F1" |
52e12ad0 | 3161 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3162 | |
3163 | (define_insn "negtf2" | |
0551c32d | 3164 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3165 | (neg:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG")))] |
23c108af | 3166 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3167 | "fneg %0 = %F1" |
52e12ad0 | 3168 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3169 | |
3170 | (define_insn "*nabstf2" | |
0551c32d | 3171 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 | 3172 | (neg:TF (abs:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG"))))] |
23c108af | 3173 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3174 | "fnegabs %0 = %F1" |
52e12ad0 | 3175 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3176 | |
3177 | (define_insn "mintf3" | |
0551c32d | 3178 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3179 | (smin:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3180 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3181 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3182 | "fmin %0 = %F1, %F2" |
52e12ad0 | 3183 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 RH |
3184 | |
3185 | (define_insn "maxtf3" | |
0551c32d | 3186 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3187 | (smax:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3188 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3189 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3190 | "fmax %0 = %F1, %F2" |
52e12ad0 | 3191 | [(set_attr "itanium_class" "fmisc")]) |
3f622353 | 3192 | |
655f2eb9 | 3193 | (define_insn "*maddtf4" |
0551c32d | 3194 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3195 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3196 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3197 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3198 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3199 | "fma %0 = %F1, %F2, %F3" |
52e12ad0 | 3200 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3201 | |
26102535 RH |
3202 | (define_insn "*maddtf4_truncsf" |
3203 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3204 | (float_truncate:SF | |
3205 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3206 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3207 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3208 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3209 | "fma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3210 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3211 | |
3212 | (define_insn "*maddtf4_truncdf" | |
3213 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3214 | (float_truncate:DF | |
3215 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3216 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3217 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3218 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3219 | "fma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3220 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3221 | |
655f2eb9 RH |
3222 | (define_insn "*maddtf4_alts" |
3223 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3224 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3225 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3226 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3227 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3228 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3229 | "fma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3230 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3231 | |
26102535 RH |
3232 | (define_insn "*maddtf4_alts_truncdf" |
3233 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3234 | (float_truncate:DF | |
3235 | (plus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3236 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3237 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3238 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3239 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3240 | "fma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3241 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3242 | |
655f2eb9 | 3243 | (define_insn "*msubtf4" |
0551c32d | 3244 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3245 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3246 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3247 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3248 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3249 | "fms %0 = %F1, %F2, %F3" |
52e12ad0 | 3250 | [(set_attr "itanium_class" "fmac")]) |
3f622353 | 3251 | |
26102535 RH |
3252 | (define_insn "*msubtf4_truncsf" |
3253 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3254 | (float_truncate:SF | |
3255 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3256 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3257 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3258 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3259 | "fms.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3260 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3261 | |
3262 | (define_insn "*msubtf4_truncdf" | |
3263 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3264 | (float_truncate:DF | |
3265 | (minus:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3266 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")) | |
3267 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3268 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3269 | "fms.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3270 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3271 | |
3f622353 | 3272 | (define_insn "*nmultf3" |
0551c32d | 3273 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3274 | (neg:TF (mult:TF (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") |
3275 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3276 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3277 | "fnmpy %0 = %F1, %F2" |
52e12ad0 | 3278 | [(set_attr "itanium_class" "fmac")]) |
c65ebc55 | 3279 | |
26102535 RH |
3280 | (define_insn "*nmultf3_truncsf" |
3281 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3282 | (float_truncate:SF | |
3283 | (neg:TF (mult:TF | |
3284 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3285 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3286 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3287 | "fnmpy.s %0 = %F1, %F2" |
52e12ad0 | 3288 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3289 | |
3290 | (define_insn "*nmultf3_truncdf" | |
3291 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3292 | (float_truncate:DF | |
3293 | (neg:TF (mult:TF | |
3294 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3295 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG")))))] | |
23c108af | 3296 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3297 | "fnmpy.d %0 = %F1, %F2" |
52e12ad0 | 3298 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3299 | |
3f622353 RH |
3300 | ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))? |
3301 | ||
655f2eb9 | 3302 | (define_insn "*nmaddtf4" |
0551c32d | 3303 | [(set (match_operand:TF 0 "fr_register_operand" "=f") |
3f622353 RH |
3304 | (plus:TF (neg:TF (mult:TF |
3305 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3306 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3307 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))] | |
23c108af | 3308 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3309 | "fnma %0 = %F1, %F2, %F3" |
52e12ad0 | 3310 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3311 | |
26102535 RH |
3312 | (define_insn "*nmaddtf4_truncsf" |
3313 | [(set (match_operand:SF 0 "fr_register_operand" "=f") | |
3314 | (float_truncate:SF | |
3315 | (plus:TF (neg:TF (mult:TF | |
3316 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3317 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3318 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3319 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3320 | "fnma.s %0 = %F1, %F2, %F3" |
52e12ad0 | 3321 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3322 | |
3323 | (define_insn "*nmaddtf4_truncdf" | |
3324 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3325 | (float_truncate:DF | |
3326 | (plus:TF (neg:TF (mult:TF | |
3327 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3328 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3329 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))))] | |
23c108af | 3330 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3331 | "fnma.d %0 = %F1, %F2, %F3" |
52e12ad0 | 3332 | [(set_attr "itanium_class" "fmac")]) |
26102535 | 3333 | |
655f2eb9 RH |
3334 | (define_insn "*nmaddtf4_alts" |
3335 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3336 | (plus:TF (neg:TF (mult:TF | |
3337 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3338 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3339 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG"))) | |
3340 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3341 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3342 | "fnma.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3343 | [(set_attr "itanium_class" "fmac")]) |
655f2eb9 | 3344 | |
26102535 RH |
3345 | (define_insn "*nmaddtf4_truncdf_alts" |
3346 | [(set (match_operand:DF 0 "fr_register_operand" "=f") | |
3347 | (float_truncate:DF | |
3348 | (plus:TF (neg:TF | |
3349 | (mult:TF | |
3350 | (match_operand:TF 1 "tfreg_or_fp01_operand" "fG") | |
3351 | (match_operand:TF 2 "tfreg_or_fp01_operand" "fG"))) | |
3352 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")))) | |
3353 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3354 | "INTEL_EXTENDED_IEEE_FORMAT" |
aebf2462 | 3355 | "fnma.d.s%4 %0 = %F1, %F2, %F3" |
52e12ad0 | 3356 | [(set_attr "itanium_class" "fmac")]) |
26102535 RH |
3357 | |
3358 | (define_expand "divtf3" | |
3359 | [(set (match_operand:TF 0 "fr_register_operand" "") | |
3360 | (div:TF (match_operand:TF 1 "fr_register_operand" "") | |
3361 | (match_operand:TF 2 "fr_register_operand" "")))] | |
23c108af | 3362 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV" |
26102535 RH |
3363 | " |
3364 | { | |
3365 | rtx insn; | |
3366 | if (TARGET_INLINE_DIV_LAT) | |
3367 | insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]); | |
3368 | else | |
3369 | insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]); | |
3370 | emit_insn (insn); | |
3371 | DONE; | |
3372 | }") | |
3373 | ||
3374 | (define_insn_and_split "divtf3_internal_lat" | |
3375 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3376 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3377 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3378 | (clobber (match_scratch:TF 3 "=&f")) | |
3379 | (clobber (match_scratch:TF 4 "=&f")) | |
3380 | (clobber (match_scratch:TF 5 "=&f")) | |
3381 | (clobber (match_scratch:TF 6 "=&f")) | |
f2f90c63 | 3382 | (clobber (match_scratch:BI 7 "=c"))] |
23c108af | 3383 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT" |
26102535 RH |
3384 | "#" |
3385 | "&& reload_completed" | |
3386 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3387 | (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3388 | (use (const_int 1))]) |
3389 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3390 | (parallel [(set (match_dup 3) | |
3391 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3392 | (match_dup 8))) | |
3393 | (use (const_int 1))])) | |
3394 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3395 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3396 | (use (const_int 1))])) | |
3397 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3398 | (parallel [(set (match_dup 5) (mult:TF (match_dup 3) (match_dup 3))) | |
3399 | (use (const_int 1))])) | |
3400 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3401 | (parallel [(set (match_dup 6) | |
3402 | (plus:TF (mult:TF (match_dup 3) (match_dup 3)) | |
3403 | (match_dup 3))) | |
3404 | (use (const_int 1))])) | |
3405 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3406 | (parallel [(set (match_dup 3) | |
3407 | (plus:TF (mult:TF (match_dup 5) (match_dup 5)) | |
3408 | (match_dup 3))) | |
3409 | (use (const_int 1))])) | |
3410 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3411 | (parallel [(set (match_dup 5) | |
3412 | (plus:TF (mult:TF (match_dup 6) (match_dup 0)) | |
3413 | (match_dup 0))) | |
3414 | (use (const_int 1))])) | |
3415 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3416 | (parallel [(set (match_dup 0) | |
3417 | (plus:TF (mult:TF (match_dup 5) (match_dup 3)) | |
3418 | (match_dup 0))) | |
3419 | (use (const_int 1))])) | |
3420 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3421 | (parallel [(set (match_dup 4) | |
3422 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3423 | (match_dup 1))) | |
3424 | (use (const_int 1))])) | |
3425 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3426 | (parallel [(set (match_dup 3) | |
3427 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3428 | (match_dup 4))) | |
3429 | (use (const_int 1))])) | |
3430 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3431 | (parallel [(set (match_dup 5) | |
3432 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3433 | (match_dup 8))) | |
3434 | (use (const_int 1))])) | |
3435 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3436 | (parallel [(set (match_dup 0) | |
3437 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3438 | (match_dup 0))) | |
3439 | (use (const_int 1))])) | |
3440 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3441 | (parallel [(set (match_dup 4) | |
3442 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3443 | (match_dup 1))) | |
3444 | (use (const_int 1))])) | |
3445 | (cond_exec (ne (match_dup 7) (const_int 0)) | |
3446 | (set (match_dup 0) | |
3447 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3448 | (match_dup 3)))) | |
3449 | ] | |
3450 | "operands[8] = CONST1_RTX (TFmode);" | |
3451 | [(set_attr "predicable" "no")]) | |
3452 | ||
3453 | (define_insn_and_split "divtf3_internal_thr" | |
3454 | [(set (match_operand:TF 0 "fr_register_operand" "=&f") | |
3455 | (div:TF (match_operand:TF 1 "fr_register_operand" "f") | |
3456 | (match_operand:TF 2 "fr_register_operand" "f"))) | |
3457 | (clobber (match_scratch:TF 3 "=&f")) | |
3458 | (clobber (match_scratch:TF 4 "=&f")) | |
f2f90c63 | 3459 | (clobber (match_scratch:BI 5 "=c"))] |
23c108af | 3460 | "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR" |
26102535 RH |
3461 | "#" |
3462 | "&& reload_completed" | |
3463 | [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2))) | |
f2f90c63 | 3464 | (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5)) |
26102535 RH |
3465 | (use (const_int 1))]) |
3466 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3467 | (parallel [(set (match_dup 3) | |
3468 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3469 | (match_dup 6))) | |
3470 | (use (const_int 1))])) | |
3471 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3472 | (parallel [(set (match_dup 4) | |
3473 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3474 | (match_dup 0))) | |
3475 | (use (const_int 1))])) | |
3476 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3477 | (parallel [(set (match_dup 3) (mult:TF (match_dup 3) (match_dup 3))) | |
3478 | (use (const_int 1))])) | |
3479 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3480 | (parallel [(set (match_dup 3) | |
3481 | (plus:TF (mult:TF (match_dup 3) (match_dup 4)) | |
3482 | (match_dup 4))) | |
3483 | (use (const_int 1))])) | |
3484 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3485 | (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0))) | |
3486 | (use (const_int 1))])) | |
3487 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3488 | (parallel [(set (match_dup 0) | |
3489 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3490 | (match_dup 6))) | |
3491 | (use (const_int 1))])) | |
3492 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3493 | (parallel [(set (match_dup 0) | |
3494 | (plus:TF (mult:TF (match_dup 0) (match_dup 3)) | |
3495 | (match_dup 3))) | |
3496 | (use (const_int 1))])) | |
3497 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3498 | (parallel [(set (match_dup 3) | |
3499 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 4))) | |
3500 | (match_dup 1))) | |
3501 | (use (const_int 1))])) | |
3502 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3503 | (parallel [(set (match_dup 3) | |
3504 | (plus:TF (mult:TF (match_dup 3) (match_dup 0)) | |
3505 | (match_dup 4))) | |
3506 | (use (const_int 1))])) | |
3507 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3508 | (parallel [(set (match_dup 4) | |
3509 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 0))) | |
3510 | (match_dup 6))) | |
3511 | (use (const_int 1))])) | |
3512 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3513 | (parallel [(set (match_dup 0) | |
3514 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3515 | (match_dup 0))) | |
3516 | (use (const_int 1))])) | |
3517 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3518 | (parallel [(set (match_dup 4) | |
3519 | (plus:TF (neg:TF (mult:TF (match_dup 2) (match_dup 3))) | |
3520 | (match_dup 1))) | |
3521 | (use (const_int 1))])) | |
3522 | (cond_exec (ne (match_dup 5) (const_int 0)) | |
3523 | (set (match_dup 0) | |
3524 | (plus:TF (mult:TF (match_dup 4) (match_dup 0)) | |
3525 | (match_dup 3)))) | |
3526 | ] | |
3527 | "operands[6] = CONST1_RTX (TFmode);" | |
3528 | [(set_attr "predicable" "no")]) | |
3529 | ||
3530 | ;; ??? frcpa works like cmp.foo.unc. | |
3531 | ||
655f2eb9 RH |
3532 | (define_insn "*recip_approx" |
3533 | [(set (match_operand:TF 0 "fr_register_operand" "=f") | |
3534 | (div:TF (const_int 1) | |
3535 | (match_operand:TF 3 "fr_register_operand" "f"))) | |
f2f90c63 RH |
3536 | (set (match_operand:BI 1 "register_operand" "=c") |
3537 | (unspec:BI [(match_operand:TF 2 "fr_register_operand" "f") | |
655f2eb9 RH |
3538 | (match_dup 3)] 5)) |
3539 | (use (match_operand:SI 4 "const_int_operand" ""))] | |
23c108af | 3540 | "INTEL_EXTENDED_IEEE_FORMAT" |
655f2eb9 | 3541 | "frcpa.s%4 %0, %1 = %2, %3" |
52e12ad0 | 3542 | [(set_attr "itanium_class" "fmisc") |
26102535 | 3543 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
3544 | \f |
3545 | ;; :::::::::::::::::::: | |
3546 | ;; :: | |
3547 | ;; :: 32 bit Integer Shifts and Rotates | |
3548 | ;; :: | |
3549 | ;; :::::::::::::::::::: | |
3550 | ||
9c668921 | 3551 | (define_expand "ashlsi3" |
0551c32d RH |
3552 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3553 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "") | |
3554 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
9c668921 RH |
3555 | "" |
3556 | " | |
3557 | { | |
3558 | if (GET_CODE (operands[2]) != CONST_INT) | |
3559 | { | |
3560 | /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now | |
3561 | we've got to get rid of stray bits outside the SImode register. */ | |
3562 | rtx subshift = gen_reg_rtx (DImode); | |
3563 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); | |
3564 | operands[2] = subshift; | |
3565 | } | |
3566 | }") | |
3567 | ||
3568 | (define_insn "*ashlsi3_internal" | |
0551c32d RH |
3569 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r") |
3570 | (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r") | |
3571 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))] | |
c65ebc55 | 3572 | "" |
041f25e6 RH |
3573 | "@ |
3574 | shladd %0 = %1, %2, r0 | |
3575 | dep.z %0 = %1, %2, %E2 | |
3576 | shl %0 = %1, %2" | |
52e12ad0 | 3577 | [(set_attr "itanium_class" "ialu,ishf,mmshf")]) |
c65ebc55 JW |
3578 | |
3579 | (define_expand "ashrsi3" | |
0551c32d RH |
3580 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3581 | (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3582 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3583 | "" |
3584 | " | |
3585 | { | |
041f25e6 RH |
3586 | rtx subtarget = gen_reg_rtx (DImode); |
3587 | if (GET_CODE (operands[2]) == CONST_INT) | |
3588 | emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]), | |
3589 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3590 | else | |
3591 | { | |
9c668921 | 3592 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3593 | emit_insn (gen_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3594 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3595 | emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3596 | } |
3597 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3598 | DONE; | |
c65ebc55 JW |
3599 | }") |
3600 | ||
c65ebc55 | 3601 | (define_expand "lshrsi3" |
0551c32d RH |
3602 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3603 | (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "") | |
3604 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3605 | "" |
3606 | " | |
3607 | { | |
041f25e6 RH |
3608 | rtx subtarget = gen_reg_rtx (DImode); |
3609 | if (GET_CODE (operands[2]) == CONST_INT) | |
3610 | emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]), | |
3611 | GEN_INT (32 - INTVAL (operands[2])), operands[2])); | |
3612 | else | |
3613 | { | |
9c668921 | 3614 | rtx subshift = gen_reg_rtx (DImode); |
041f25e6 | 3615 | emit_insn (gen_zero_extendsidi2 (subtarget, operands[1])); |
9c668921 RH |
3616 | emit_insn (gen_zero_extendsidi2 (subshift, operands[2])); |
3617 | emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift)); | |
041f25e6 RH |
3618 | } |
3619 | emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget); | |
3620 | DONE; | |
c65ebc55 JW |
3621 | }") |
3622 | ||
c65ebc55 | 3623 | ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result |
66db6b45 RH |
3624 | ;; here, instead of 64 like the patterns above. Keep the pattern together |
3625 | ;; until after combine; otherwise it won't get matched often. | |
c65ebc55 JW |
3626 | |
3627 | (define_expand "rotrsi3" | |
66db6b45 RH |
3628 | [(set (match_operand:SI 0 "gr_register_operand" "") |
3629 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "") | |
3630 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
3631 | "" | |
3632 | " | |
3633 | { | |
3634 | if (GET_MODE (operands[2]) != VOIDmode) | |
3635 | { | |
3636 | rtx tmp = gen_reg_rtx (DImode); | |
3637 | emit_insn (gen_zero_extendsidi2 (tmp, operands[2])); | |
3638 | operands[2] = tmp; | |
3639 | } | |
3640 | }") | |
3641 | ||
3642 | (define_insn_and_split "*rotrsi3_internal" | |
3643 | [(set (match_operand:SI 0 "gr_register_operand" "=&r") | |
3644 | (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3645 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))] | |
3646 | "" | |
3647 | "#" | |
3648 | "reload_completed" | |
c65ebc55 | 3649 | [(set (match_dup 3) |
66db6b45 | 3650 | (ior:DI (zero_extend:DI (match_dup 1)) |
c65ebc55 JW |
3651 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) |
3652 | (set (match_dup 3) | |
66db6b45 RH |
3653 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] |
3654 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") | |
3655 | ||
3656 | (define_expand "rotlsi3" | |
3657 | [(set (match_operand:SI 0 "gr_register_operand" "") | |
3658 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "") | |
3659 | (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))] | |
c65ebc55 JW |
3660 | "" |
3661 | " | |
3662 | { | |
3663 | if (! shift_32bit_count_operand (operands[2], SImode)) | |
66db6b45 RH |
3664 | { |
3665 | rtx tmp = gen_reg_rtx (SImode); | |
3666 | emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2])); | |
3667 | emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp)); | |
3668 | DONE; | |
3669 | } | |
c65ebc55 | 3670 | }") |
66db6b45 RH |
3671 | |
3672 | (define_insn_and_split "*rotlsi3_internal" | |
3673 | [(set (match_operand:SI 0 "gr_register_operand" "=r") | |
3674 | (rotate:SI (match_operand:SI 1 "gr_register_operand" "r") | |
3675 | (match_operand:SI 2 "shift_32bit_count_operand" "n")))] | |
3676 | "" | |
3677 | "#" | |
3678 | "reload_completed" | |
3679 | [(set (match_dup 3) | |
3680 | (ior:DI (zero_extend:DI (match_dup 1)) | |
3681 | (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) | |
3682 | (set (match_dup 3) | |
3683 | (lshiftrt:DI (match_dup 3) (match_dup 2)))] | |
3684 | "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
3685 | operands[2] = GEN_INT (32 - INTVAL (operands[2]));") | |
c65ebc55 JW |
3686 | \f |
3687 | ;; :::::::::::::::::::: | |
3688 | ;; :: | |
3689 | ;; :: 64 bit Integer Shifts and Rotates | |
3690 | ;; :: | |
3691 | ;; :::::::::::::::::::: | |
3692 | ||
3693 | (define_insn "ashldi3" | |
52e12ad0 BS |
3694 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r") |
3695 | (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r") | |
3696 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))] | |
c65ebc55 | 3697 | "" |
041f25e6 RH |
3698 | "@ |
3699 | shladd %0 = %1, %2, r0 | |
52e12ad0 | 3700 | shl %0 = %1, %2 |
041f25e6 | 3701 | shl %0 = %1, %2" |
52e12ad0 | 3702 | [(set_attr "itanium_class" "ialu,mmshf,mmshfi")]) |
c65ebc55 JW |
3703 | |
3704 | ;; ??? Maybe combine this with the multiply and add instruction? | |
3705 | ||
3706 | (define_insn "*shladd" | |
0551c32d RH |
3707 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3708 | (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3709 | (match_operand:DI 2 "shladd_operand" "n")) |
0551c32d | 3710 | (match_operand:DI 3 "gr_register_operand" "r")))] |
c65ebc55 JW |
3711 | "" |
3712 | "shladd %0 = %1, %S2, %3" | |
52e12ad0 | 3713 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
3714 | |
3715 | ;; This can be created by register elimination if operand3 of shladd is an | |
3716 | ;; eliminable register or has reg_equiv_constant set. | |
3717 | ||
3718 | ;; We have to use nonmemory_operand for operand 4, to ensure that the | |
3719 | ;; validate_changes call inside eliminate_regs will always succeed. If it | |
3720 | ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded | |
3721 | ;; incorrectly. | |
3722 | ||
5527bf14 | 3723 | (define_insn_and_split "*shladd_elim" |
0551c32d RH |
3724 | [(set (match_operand:DI 0 "gr_register_operand" "=&r") |
3725 | (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 | 3726 | (match_operand:DI 2 "shladd_operand" "n")) |
5527bf14 | 3727 | (match_operand:DI 3 "nonmemory_operand" "r")) |
c65ebc55 JW |
3728 | (match_operand:DI 4 "nonmemory_operand" "rI")))] |
3729 | "reload_in_progress" | |
5527bf14 | 3730 | "* abort ();" |
c65ebc55 JW |
3731 | "reload_completed" |
3732 | [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2)) | |
3733 | (match_dup 3))) | |
c65ebc55 | 3734 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] |
5527bf14 | 3735 | "" |
52e12ad0 | 3736 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
3737 | |
3738 | (define_insn "ashrdi3" | |
52e12ad0 BS |
3739 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3740 | (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3741 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3742 | "" |
52e12ad0 BS |
3743 | "@ |
3744 | shr %0 = %1, %2 | |
3745 | shr %0 = %1, %2" | |
3746 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3747 | |
3748 | (define_insn "lshrdi3" | |
52e12ad0 BS |
3749 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
3750 | (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r") | |
3751 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))] | |
c65ebc55 | 3752 | "" |
52e12ad0 BS |
3753 | "@ |
3754 | shr.u %0 = %1, %2 | |
3755 | shr.u %0 = %1, %2" | |
3756 | [(set_attr "itanium_class" "mmshf,mmshfi")]) | |
c65ebc55 JW |
3757 | |
3758 | ;; Using a predicate that accepts only constants doesn't work, because optabs | |
3759 | ;; will load the operand into a register and call the pattern if the predicate | |
3760 | ;; did not accept it on the first try. So we use nonmemory_operand and then | |
3761 | ;; verify that we have an appropriate constant in the expander. | |
3762 | ||
3763 | (define_expand "rotrdi3" | |
0551c32d RH |
3764 | [(set (match_operand:DI 0 "gr_register_operand" "") |
3765 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "") | |
c65ebc55 JW |
3766 | (match_operand:DI 2 "nonmemory_operand" "")))] |
3767 | "" | |
3768 | " | |
3769 | { | |
3770 | if (! shift_count_operand (operands[2], DImode)) | |
3771 | FAIL; | |
3772 | }") | |
3773 | ||
3774 | (define_insn "*rotrdi3_internal" | |
0551c32d RH |
3775 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3776 | (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
3777 | (match_operand:DI 2 "shift_count_operand" "M")))] |
3778 | "" | |
3779 | "shrp %0 = %1, %1, %2" | |
52e12ad0 | 3780 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 | 3781 | |
66db6b45 RH |
3782 | (define_expand "rotldi3" |
3783 | [(set (match_operand:DI 0 "gr_register_operand" "") | |
3784 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "") | |
3785 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
3786 | "" | |
3787 | " | |
3788 | { | |
3789 | if (! shift_count_operand (operands[2], DImode)) | |
3790 | FAIL; | |
3791 | }") | |
3792 | ||
3793 | (define_insn "*rotldi3_internal" | |
3794 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
3795 | (rotate:DI (match_operand:DI 1 "gr_register_operand" "r") | |
3796 | (match_operand:DI 2 "shift_count_operand" "M")))] | |
3797 | "" | |
3798 | "shrp %0 = %1, %1, %e2" | |
52e12ad0 | 3799 | [(set_attr "itanium_class" "ishf")]) |
c65ebc55 JW |
3800 | \f |
3801 | ;; :::::::::::::::::::: | |
3802 | ;; :: | |
058557c4 | 3803 | ;; :: 32 bit Integer Logical operations |
c65ebc55 JW |
3804 | ;; :: |
3805 | ;; :::::::::::::::::::: | |
3806 | ||
3807 | ;; We don't seem to need any other 32-bit logical operations, because gcc | |
3808 | ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to | |
3809 | ;; DImode-op;zero-extend, and then we can optimize away the zero-extend. | |
3810 | ;; This doesn't work for unary logical operations, because we don't call | |
3811 | ;; apply_distributive_law for them. | |
3812 | ||
3813 | ;; ??? Likewise, this doesn't work for andnot, which isn't handled by | |
3814 | ;; apply_distributive_law. We get inefficient code for | |
3815 | ;; int sub4 (int i, int j) { return i & ~j; } | |
3816 | ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to | |
3817 | ;; (zero_extend (and (not A) B)) in combine. | |
3818 | ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the | |
3819 | ;; one_cmplsi2 pattern. | |
3820 | ||
058557c4 | 3821 | (define_insn "one_cmplsi2" |
0551c32d RH |
3822 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
3823 | (not:SI (match_operand:SI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3824 | "" |
3825 | "andcm %0 = -1, %1" | |
52e12ad0 | 3826 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3827 | \f |
3828 | ;; :::::::::::::::::::: | |
3829 | ;; :: | |
058557c4 | 3830 | ;; :: 64 bit Integer Logical operations |
c65ebc55 JW |
3831 | ;; :: |
3832 | ;; :::::::::::::::::::: | |
3833 | ||
3834 | (define_insn "anddi3" | |
0551c32d RH |
3835 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3836 | (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3837 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3838 | "" |
3839 | "@ | |
3840 | and %0 = %2, %1 | |
aebf2462 | 3841 | fand %0 = %2, %1" |
52e12ad0 | 3842 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3843 | |
3844 | (define_insn "*andnot" | |
0551c32d RH |
3845 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3846 | (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f")) | |
3847 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3848 | "" |
3849 | "@ | |
3850 | andcm %0 = %2, %1 | |
aebf2462 | 3851 | fandcm %0 = %2, %1" |
52e12ad0 | 3852 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3853 | |
3854 | (define_insn "iordi3" | |
0551c32d RH |
3855 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3856 | (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3857 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3858 | "" |
3859 | "@ | |
3860 | or %0 = %2, %1 | |
aebf2462 | 3861 | for %0 = %2, %1" |
52e12ad0 | 3862 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3863 | |
3864 | (define_insn "xordi3" | |
0551c32d RH |
3865 | [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f") |
3866 | (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f") | |
3867 | (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))] | |
c65ebc55 JW |
3868 | "" |
3869 | "@ | |
3870 | xor %0 = %2, %1 | |
aebf2462 | 3871 | fxor %0 = %2, %1" |
52e12ad0 | 3872 | [(set_attr "itanium_class" "ilog,fmisc")]) |
c65ebc55 JW |
3873 | |
3874 | (define_insn "one_cmpldi2" | |
0551c32d RH |
3875 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
3876 | (not:DI (match_operand:DI 1 "gr_register_operand" "r")))] | |
c65ebc55 JW |
3877 | "" |
3878 | "andcm %0 = -1, %1" | |
52e12ad0 | 3879 | [(set_attr "itanium_class" "ilog")]) |
c65ebc55 JW |
3880 | \f |
3881 | ;; :::::::::::::::::::: | |
3882 | ;; :: | |
3883 | ;; :: Comparisons | |
3884 | ;; :: | |
3885 | ;; :::::::::::::::::::: | |
3886 | ||
f2f90c63 RH |
3887 | (define_expand "cmpbi" |
3888 | [(set (cc0) | |
3889 | (compare (match_operand:BI 0 "register_operand" "") | |
3890 | (match_operand:BI 1 "const_int_operand" "")))] | |
3891 | "" | |
3892 | " | |
3893 | { | |
3894 | ia64_compare_op0 = operands[0]; | |
3895 | ia64_compare_op1 = operands[1]; | |
3896 | DONE; | |
3897 | }") | |
3898 | ||
c65ebc55 JW |
3899 | (define_expand "cmpsi" |
3900 | [(set (cc0) | |
0551c32d RH |
3901 | (compare (match_operand:SI 0 "gr_register_operand" "") |
3902 | (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3903 | "" |
3904 | " | |
3905 | { | |
3906 | ia64_compare_op0 = operands[0]; | |
3907 | ia64_compare_op1 = operands[1]; | |
3908 | DONE; | |
3909 | }") | |
3910 | ||
3911 | (define_expand "cmpdi" | |
3912 | [(set (cc0) | |
0551c32d RH |
3913 | (compare (match_operand:DI 0 "gr_register_operand" "") |
3914 | (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))] | |
c65ebc55 JW |
3915 | "" |
3916 | " | |
3917 | { | |
3918 | ia64_compare_op0 = operands[0]; | |
3919 | ia64_compare_op1 = operands[1]; | |
3920 | DONE; | |
3921 | }") | |
3922 | ||
3923 | (define_expand "cmpsf" | |
3924 | [(set (cc0) | |
0551c32d RH |
3925 | (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "") |
3926 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3927 | "" |
3928 | " | |
3929 | { | |
3930 | ia64_compare_op0 = operands[0]; | |
3931 | ia64_compare_op1 = operands[1]; | |
3932 | DONE; | |
3933 | }") | |
3934 | ||
3935 | (define_expand "cmpdf" | |
3936 | [(set (cc0) | |
0551c32d RH |
3937 | (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "") |
3938 | (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))] | |
c65ebc55 JW |
3939 | "" |
3940 | " | |
3941 | { | |
3942 | ia64_compare_op0 = operands[0]; | |
3943 | ia64_compare_op1 = operands[1]; | |
3944 | DONE; | |
3945 | }") | |
3946 | ||
3f622353 | 3947 | (define_expand "cmptf" |
c65ebc55 | 3948 | [(set (cc0) |
3f622353 RH |
3949 | (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "") |
3950 | (match_operand:TF 1 "tfreg_or_fp01_operand" "")))] | |
23c108af | 3951 | "INTEL_EXTENDED_IEEE_FORMAT" |
c65ebc55 JW |
3952 | " |
3953 | { | |
3954 | ia64_compare_op0 = operands[0]; | |
3955 | ia64_compare_op1 = operands[1]; | |
3956 | DONE; | |
3957 | }") | |
3958 | ||
3959 | (define_insn "*cmpsi_normal" | |
f2f90c63 RH |
3960 | [(set (match_operand:BI 0 "register_operand" "=c") |
3961 | (match_operator:BI 1 "normal_comparison_operator" | |
0551c32d RH |
3962 | [(match_operand:SI 2 "gr_register_operand" "r") |
3963 | (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))] | |
c65ebc55 JW |
3964 | "" |
3965 | "cmp4.%C1 %0, %I0 = %3, %2" | |
52e12ad0 | 3966 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3967 | |
18a3c539 JW |
3968 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3969 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3970 | ||
c65ebc55 | 3971 | (define_insn "*cmpsi_adjusted" |
f2f90c63 RH |
3972 | [(set (match_operand:BI 0 "register_operand" "=c") |
3973 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3974 | [(match_operand:SI 2 "gr_register_operand" "r") |
3975 | (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3976 | "" |
18a3c539 | 3977 | "cmp4.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3978 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
3979 | |
3980 | (define_insn "*cmpdi_normal" | |
f2f90c63 RH |
3981 | [(set (match_operand:BI 0 "register_operand" "=c") |
3982 | (match_operator:BI 1 "normal_comparison_operator" | |
3983 | [(match_operand:DI 2 "gr_reg_or_0_operand" "rO") | |
0551c32d | 3984 | (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))] |
c65ebc55 | 3985 | "" |
f2f90c63 | 3986 | "cmp.%C1 %0, %I0 = %3, %r2" |
52e12ad0 | 3987 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 | 3988 | |
18a3c539 JW |
3989 | ;; We use %r3 because it is possible for us to match a 0, and two of the |
3990 | ;; unsigned comparisons don't accept immediate operands of zero. | |
3991 | ||
c65ebc55 | 3992 | (define_insn "*cmpdi_adjusted" |
f2f90c63 RH |
3993 | [(set (match_operand:BI 0 "register_operand" "=c") |
3994 | (match_operator:BI 1 "adjusted_comparison_operator" | |
0551c32d RH |
3995 | [(match_operand:DI 2 "gr_register_operand" "r") |
3996 | (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))] | |
c65ebc55 | 3997 | "" |
18a3c539 | 3998 | "cmp.%C1 %0, %I0 = %r3, %2" |
52e12ad0 | 3999 | [(set_attr "itanium_class" "icmp")]) |
c65ebc55 JW |
4000 | |
4001 | (define_insn "*cmpsf_internal" | |
f2f90c63 RH |
4002 | [(set (match_operand:BI 0 "register_operand" "=c") |
4003 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4004 | [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") |
4005 | (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4006 | "" |
4007 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4008 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 JW |
4009 | |
4010 | (define_insn "*cmpdf_internal" | |
f2f90c63 RH |
4011 | [(set (match_operand:BI 0 "register_operand" "=c") |
4012 | (match_operator:BI 1 "comparison_operator" | |
0551c32d RH |
4013 | [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") |
4014 | (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))] | |
c65ebc55 JW |
4015 | "" |
4016 | "fcmp.%D1 %0, %I0 = %F2, %F3" | |
52e12ad0 | 4017 | [(set_attr "itanium_class" "fcmp")]) |
c65ebc55 | 4018 | |
3f622353 | 4019 | (define_insn "*cmptf_internal" |
f2f90c63 RH |
4020 | [(set (match_operand:BI 0 "register_operand" "=c") |
4021 | (match_operator:BI 1 "comparison_operator" | |
3f622353 RH |
4022 | [(match_operand:TF 2 "tfreg_or_fp01_operand" "fG") |
4023 | (match_operand:TF 3 "tfreg_or_fp01_operand" "fG")]))] | |
23c108af | 4024 | "INTEL_EXTENDED_IEEE_FORMAT" |
3f622353 | 4025 | "fcmp.%D1 %0, %I0 = %F2, %F3" |
52e12ad0 | 4026 | [(set_attr "itanium_class" "fcmp")]) |
3f622353 | 4027 | |
c65ebc55 JW |
4028 | ;; ??? Can this pattern be generated? |
4029 | ||
4030 | (define_insn "*bit_zero" | |
f2f90c63 RH |
4031 | [(set (match_operand:BI 0 "register_operand" "=c") |
4032 | (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4033 | (const_int 1) |
4034 | (match_operand:DI 2 "immediate_operand" "n")) | |
4035 | (const_int 0)))] | |
4036 | "" | |
4037 | "tbit.z %0, %I0 = %1, %2" | |
52e12ad0 | 4038 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4039 | |
4040 | (define_insn "*bit_one" | |
f2f90c63 RH |
4041 | [(set (match_operand:BI 0 "register_operand" "=c") |
4042 | (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") | |
c65ebc55 JW |
4043 | (const_int 1) |
4044 | (match_operand:DI 2 "immediate_operand" "n")) | |
4045 | (const_int 0)))] | |
4046 | "" | |
4047 | "tbit.nz %0, %I0 = %1, %2" | |
52e12ad0 | 4048 | [(set_attr "itanium_class" "tbit")]) |
c65ebc55 JW |
4049 | \f |
4050 | ;; :::::::::::::::::::: | |
4051 | ;; :: | |
4052 | ;; :: Branches | |
4053 | ;; :: | |
4054 | ;; :::::::::::::::::::: | |
4055 | ||
4056 | (define_expand "beq" | |
f2f90c63 RH |
4057 | [(set (pc) |
4058 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4059 | (label_ref (match_operand 0 "" "")) |
4060 | (pc)))] | |
4061 | "" | |
f2f90c63 | 4062 | "operands[1] = ia64_expand_compare (EQ, VOIDmode);") |
c65ebc55 JW |
4063 | |
4064 | (define_expand "bne" | |
f2f90c63 RH |
4065 | [(set (pc) |
4066 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4067 | (label_ref (match_operand 0 "" "")) |
4068 | (pc)))] | |
4069 | "" | |
f2f90c63 | 4070 | "operands[1] = ia64_expand_compare (NE, VOIDmode);") |
c65ebc55 JW |
4071 | |
4072 | (define_expand "blt" | |
f2f90c63 RH |
4073 | [(set (pc) |
4074 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4075 | (label_ref (match_operand 0 "" "")) |
4076 | (pc)))] | |
4077 | "" | |
f2f90c63 | 4078 | "operands[1] = ia64_expand_compare (LT, VOIDmode);") |
c65ebc55 JW |
4079 | |
4080 | (define_expand "ble" | |
f2f90c63 RH |
4081 | [(set (pc) |
4082 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4083 | (label_ref (match_operand 0 "" "")) |
4084 | (pc)))] | |
4085 | "" | |
f2f90c63 | 4086 | "operands[1] = ia64_expand_compare (LE, VOIDmode);") |
c65ebc55 JW |
4087 | |
4088 | (define_expand "bgt" | |
f2f90c63 RH |
4089 | [(set (pc) |
4090 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4091 | (label_ref (match_operand 0 "" "")) |
4092 | (pc)))] | |
4093 | "" | |
f2f90c63 | 4094 | "operands[1] = ia64_expand_compare (GT, VOIDmode);") |
c65ebc55 JW |
4095 | |
4096 | (define_expand "bge" | |
f2f90c63 RH |
4097 | [(set (pc) |
4098 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4099 | (label_ref (match_operand 0 "" "")) |
4100 | (pc)))] | |
4101 | "" | |
f2f90c63 | 4102 | "operands[1] = ia64_expand_compare (GE, VOIDmode);") |
c65ebc55 JW |
4103 | |
4104 | (define_expand "bltu" | |
f2f90c63 RH |
4105 | [(set (pc) |
4106 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4107 | (label_ref (match_operand 0 "" "")) |
4108 | (pc)))] | |
4109 | "" | |
f2f90c63 | 4110 | "operands[1] = ia64_expand_compare (LTU, VOIDmode);") |
c65ebc55 JW |
4111 | |
4112 | (define_expand "bleu" | |
f2f90c63 RH |
4113 | [(set (pc) |
4114 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4115 | (label_ref (match_operand 0 "" "")) |
4116 | (pc)))] | |
4117 | "" | |
f2f90c63 | 4118 | "operands[1] = ia64_expand_compare (LEU, VOIDmode);") |
c65ebc55 JW |
4119 | |
4120 | (define_expand "bgtu" | |
f2f90c63 RH |
4121 | [(set (pc) |
4122 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4123 | (label_ref (match_operand 0 "" "")) |
4124 | (pc)))] | |
4125 | "" | |
f2f90c63 | 4126 | "operands[1] = ia64_expand_compare (GTU, VOIDmode);") |
c65ebc55 JW |
4127 | |
4128 | (define_expand "bgeu" | |
f2f90c63 RH |
4129 | [(set (pc) |
4130 | (if_then_else (match_dup 1) | |
c65ebc55 JW |
4131 | (label_ref (match_operand 0 "" "")) |
4132 | (pc)))] | |
4133 | "" | |
f2f90c63 | 4134 | "operands[1] = ia64_expand_compare (GEU, VOIDmode);") |
c65ebc55 | 4135 | |
e57b9d65 | 4136 | (define_expand "bunordered" |
f2f90c63 RH |
4137 | [(set (pc) |
4138 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4139 | (label_ref (match_operand 0 "" "")) |
4140 | (pc)))] | |
4141 | "" | |
f2f90c63 | 4142 | "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);") |
e57b9d65 RH |
4143 | |
4144 | (define_expand "bordered" | |
f2f90c63 RH |
4145 | [(set (pc) |
4146 | (if_then_else (match_dup 1) | |
e57b9d65 RH |
4147 | (label_ref (match_operand 0 "" "")) |
4148 | (pc)))] | |
4149 | "" | |
f2f90c63 | 4150 | "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);") |
e57b9d65 | 4151 | |
6b6c1201 | 4152 | (define_insn "*br_true" |
c65ebc55 | 4153 | [(set (pc) |
6b6c1201 | 4154 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4155 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 RH |
4156 | (const_int 0)]) |
4157 | (label_ref (match_operand 2 "" "")) | |
c65ebc55 JW |
4158 | (pc)))] |
4159 | "" | |
85548039 | 4160 | "(%J0) br.cond%+ %l2" |
52e12ad0 | 4161 | [(set_attr "itanium_class" "br") |
e5bde68a | 4162 | (set_attr "predicable" "no")]) |
c65ebc55 | 4163 | |
6b6c1201 | 4164 | (define_insn "*br_false" |
c65ebc55 | 4165 | [(set (pc) |
6b6c1201 | 4166 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4167 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4168 | (const_int 0)]) |
c65ebc55 | 4169 | (pc) |
6b6c1201 | 4170 | (label_ref (match_operand 2 "" ""))))] |
c65ebc55 | 4171 | "" |
85548039 | 4172 | "(%j0) br.cond%+ %l2" |
52e12ad0 | 4173 | [(set_attr "itanium_class" "br") |
e5bde68a | 4174 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4175 | \f |
4176 | ;; :::::::::::::::::::: | |
4177 | ;; :: | |
5527bf14 RH |
4178 | ;; :: Counted loop operations |
4179 | ;; :: | |
4180 | ;; :::::::::::::::::::: | |
4181 | ||
4182 | (define_expand "doloop_end" | |
4183 | [(use (match_operand 0 "" "")) ; loop pseudo | |
4184 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
4185 | (use (match_operand 2 "" "")) ; max iterations | |
4186 | (use (match_operand 3 "" "")) ; loop level | |
4187 | (use (match_operand 4 "" ""))] ; label | |
4188 | "" | |
4189 | " | |
4190 | { | |
4191 | /* Only use cloop on innermost loops. */ | |
4192 | if (INTVAL (operands[3]) > 1) | |
4193 | FAIL; | |
4194 | emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM), | |
4195 | operands[4])); | |
4196 | DONE; | |
4197 | }") | |
4198 | ||
4199 | (define_insn "doloop_end_internal" | |
4200 | [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "") | |
4201 | (const_int 0)) | |
4202 | (label_ref (match_operand 1 "" "")) | |
4203 | (pc))) | |
4204 | (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0)) | |
4205 | (match_dup 0) | |
4206 | (plus:DI (match_dup 0) (const_int -1))))] | |
4207 | "" | |
4208 | "br.cloop.sptk.few %l1" | |
52e12ad0 | 4209 | [(set_attr "itanium_class" "br") |
5527bf14 RH |
4210 | (set_attr "predicable" "no")]) |
4211 | \f | |
4212 | ;; :::::::::::::::::::: | |
4213 | ;; :: | |
c65ebc55 JW |
4214 | ;; :: Set flag operations |
4215 | ;; :: | |
4216 | ;; :::::::::::::::::::: | |
4217 | ||
4218 | (define_expand "seq" | |
f2f90c63 | 4219 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4220 | "" |
f2f90c63 | 4221 | "operands[1] = ia64_expand_compare (EQ, DImode);") |
c65ebc55 JW |
4222 | |
4223 | (define_expand "sne" | |
f2f90c63 | 4224 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4225 | "" |
f2f90c63 | 4226 | "operands[1] = ia64_expand_compare (NE, DImode);") |
c65ebc55 JW |
4227 | |
4228 | (define_expand "slt" | |
f2f90c63 | 4229 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4230 | "" |
f2f90c63 | 4231 | "operands[1] = ia64_expand_compare (LT, DImode);") |
c65ebc55 JW |
4232 | |
4233 | (define_expand "sle" | |
f2f90c63 | 4234 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4235 | "" |
f2f90c63 | 4236 | "operands[1] = ia64_expand_compare (LE, DImode);") |
c65ebc55 JW |
4237 | |
4238 | (define_expand "sgt" | |
f2f90c63 | 4239 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4240 | "" |
f2f90c63 | 4241 | "operands[1] = ia64_expand_compare (GT, DImode);") |
c65ebc55 JW |
4242 | |
4243 | (define_expand "sge" | |
f2f90c63 | 4244 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4245 | "" |
f2f90c63 | 4246 | "operands[1] = ia64_expand_compare (GE, DImode);") |
c65ebc55 JW |
4247 | |
4248 | (define_expand "sltu" | |
f2f90c63 | 4249 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4250 | "" |
f2f90c63 | 4251 | "operands[1] = ia64_expand_compare (LTU, DImode);") |
c65ebc55 JW |
4252 | |
4253 | (define_expand "sleu" | |
f2f90c63 | 4254 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4255 | "" |
f2f90c63 | 4256 | "operands[1] = ia64_expand_compare (LEU, DImode);") |
c65ebc55 JW |
4257 | |
4258 | (define_expand "sgtu" | |
f2f90c63 | 4259 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4260 | "" |
f2f90c63 | 4261 | "operands[1] = ia64_expand_compare (GTU, DImode);") |
c65ebc55 JW |
4262 | |
4263 | (define_expand "sgeu" | |
f2f90c63 | 4264 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
c65ebc55 | 4265 | "" |
f2f90c63 | 4266 | "operands[1] = ia64_expand_compare (GEU, DImode);") |
c65ebc55 | 4267 | |
e57b9d65 | 4268 | (define_expand "sunordered" |
f2f90c63 | 4269 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4270 | "" |
f2f90c63 | 4271 | "operands[1] = ia64_expand_compare (UNORDERED, DImode);") |
e57b9d65 RH |
4272 | |
4273 | (define_expand "sordered" | |
f2f90c63 | 4274 | [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))] |
e57b9d65 | 4275 | "" |
f2f90c63 | 4276 | "operands[1] = ia64_expand_compare (ORDERED, DImode);") |
e57b9d65 | 4277 | |
c65ebc55 JW |
4278 | ;; Don't allow memory as destination here, because cmov/cmov/st is more |
4279 | ;; efficient than mov/mov/cst/cst. | |
4280 | ||
0551c32d RH |
4281 | (define_insn_and_split "*sne_internal" |
4282 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4283 | (ne:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4284 | (const_int 0)))] |
4285 | "" | |
4286 | "#" | |
c65ebc55 | 4287 | "reload_completed" |
f2f90c63 RH |
4288 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4289 | (set (match_dup 0) (const_int 1))) | |
4290 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4291 | (set (match_dup 0) (const_int 0)))] | |
0551c32d | 4292 | "" |
52e12ad0 | 4293 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4294 | |
0551c32d RH |
4295 | (define_insn_and_split "*seq_internal" |
4296 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
f2f90c63 | 4297 | (eq:DI (match_operand:BI 1 "register_operand" "c") |
c65ebc55 JW |
4298 | (const_int 0)))] |
4299 | "" | |
4300 | "#" | |
c65ebc55 | 4301 | "reload_completed" |
f2f90c63 RH |
4302 | [(cond_exec (ne (match_dup 1) (const_int 0)) |
4303 | (set (match_dup 0) (const_int 0))) | |
4304 | (cond_exec (eq (match_dup 1) (const_int 0)) | |
4305 | (set (match_dup 0) (const_int 1)))] | |
0551c32d | 4306 | "" |
52e12ad0 | 4307 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 JW |
4308 | \f |
4309 | ;; :::::::::::::::::::: | |
4310 | ;; :: | |
4311 | ;; :: Conditional move instructions. | |
4312 | ;; :: | |
4313 | ;; :::::::::::::::::::: | |
4314 | ||
4315 | ;; ??? Add movXXcc patterns? | |
4316 | ||
c65ebc55 JW |
4317 | ;; |
4318 | ;; DImode if_then_else patterns. | |
4319 | ;; | |
4320 | ||
75cdbeb8 | 4321 | (define_insn "*cmovdi_internal" |
f2f90c63 | 4322 | [(set (match_operand:DI 0 "destination_operand" |
cd5c4048 | 4323 | "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e") |
e5bde68a | 4324 | (if_then_else:DI |
f2f90c63 RH |
4325 | (match_operator 4 "predicate_operator" |
4326 | [(match_operand:BI 1 "register_operand" | |
cd5c4048 | 4327 | "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c") |
e5bde68a | 4328 | (const_int 0)]) |
f2f90c63 | 4329 | (match_operand:DI 2 "move_operand" |
cd5c4048 | 4330 | "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK") |
f2f90c63 | 4331 | (match_operand:DI 3 "move_operand" |
cd5c4048 | 4332 | "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))] |
aebf2462 | 4333 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4334 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 RH |
4335 | "* abort ();" |
4336 | [(set_attr "predicable" "no")]) | |
4337 | ||
4338 | (define_split | |
f2f90c63 | 4339 | [(set (match_operand 0 "destination_operand" "") |
75cdbeb8 | 4340 | (if_then_else |
f2f90c63 RH |
4341 | (match_operator 4 "predicate_operator" |
4342 | [(match_operand:BI 1 "register_operand" "") | |
75cdbeb8 | 4343 | (const_int 0)]) |
f2f90c63 RH |
4344 | (match_operand 2 "move_operand" "") |
4345 | (match_operand 3 "move_operand" "")))] | |
3b572406 RH |
4346 | "reload_completed" |
4347 | [(const_int 0)] | |
e5bde68a RH |
4348 | " |
4349 | { | |
3b572406 RH |
4350 | rtx tmp; |
4351 | if (! rtx_equal_p (operands[0], operands[2])) | |
e5bde68a | 4352 | { |
3b572406 RH |
4353 | tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]); |
4354 | tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp); | |
4355 | emit_insn (tmp); | |
e5bde68a | 4356 | } |
3b572406 RH |
4357 | if (! rtx_equal_p (operands[0], operands[3])) |
4358 | { | |
4359 | tmp = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4360 | VOIDmode, operands[1], const0_rtx); |
3b572406 RH |
4361 | tmp = gen_rtx_COND_EXEC (VOIDmode, tmp, |
4362 | gen_rtx_SET (VOIDmode, operands[0], | |
4363 | operands[3])); | |
4364 | emit_insn (tmp); | |
4365 | } | |
4366 | DONE; | |
75cdbeb8 | 4367 | }") |
c65ebc55 JW |
4368 | |
4369 | ;; Absolute value pattern. | |
4370 | ||
4371 | (define_insn "*absdi2_internal" | |
0551c32d | 4372 | [(set (match_operand:DI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4373 | (if_then_else:DI |
f2f90c63 RH |
4374 | (match_operator 4 "predicate_operator" |
4375 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4376 | (const_int 0)]) |
0551c32d RH |
4377 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI")) |
4378 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4379 | "" |
e5bde68a | 4380 | "#" |
52e12ad0 | 4381 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4382 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4383 | |
4384 | (define_split | |
4385 | [(set (match_operand:DI 0 "register_operand" "") | |
e5bde68a | 4386 | (if_then_else:DI |
f2f90c63 RH |
4387 | (match_operator 4 "predicate_operator" |
4388 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4389 | (const_int 0)]) |
0551c32d RH |
4390 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4391 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4392 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4393 | [(cond_exec | |
4394 | (match_dup 4) | |
4395 | (set (match_dup 0) | |
4396 | (neg:DI (match_dup 2))))] | |
c65ebc55 JW |
4397 | "") |
4398 | ||
e5bde68a RH |
4399 | (define_split |
4400 | [(set (match_operand:DI 0 "register_operand" "") | |
4401 | (if_then_else:DI | |
f2f90c63 RH |
4402 | (match_operator 4 "predicate_operator" |
4403 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4404 | (const_int 0)]) |
0551c32d RH |
4405 | (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "")) |
4406 | (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4407 | "reload_completed" |
4408 | [(cond_exec | |
4409 | (match_dup 4) | |
4410 | (set (match_dup 0) (neg:DI (match_dup 2)))) | |
4411 | (cond_exec | |
4412 | (match_dup 5) | |
4413 | (set (match_dup 0) (match_dup 3)))] | |
4414 | " | |
4415 | { | |
4416 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4417 | VOIDmode, operands[1], const0_rtx); |
e5bde68a | 4418 | }") |
c65ebc55 JW |
4419 | |
4420 | ;; | |
4421 | ;; SImode if_then_else patterns. | |
4422 | ;; | |
4423 | ||
75cdbeb8 | 4424 | (define_insn "*cmovsi_internal" |
f2f90c63 | 4425 | [(set (match_operand:SI 0 "destination_operand" "=r,m,*f,r,m,*f,r,m,*f") |
e5bde68a | 4426 | (if_then_else:SI |
f2f90c63 RH |
4427 | (match_operator 4 "predicate_operator" |
4428 | [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c") | |
e5bde68a | 4429 | (const_int 0)]) |
f2f90c63 | 4430 | (match_operand:SI 2 "move_operand" |
3b572406 | 4431 | "0,0,0,rim*f,rO,rO,rim*f,rO,rO") |
f2f90c63 | 4432 | (match_operand:SI 3 "move_operand" |
3b572406 | 4433 | "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))] |
aebf2462 | 4434 | "ia64_move_ok (operands[0], operands[2]) |
f2f90c63 | 4435 | && ia64_move_ok (operands[0], operands[3])" |
75cdbeb8 | 4436 | "* abort ();" |
3b572406 | 4437 | [(set_attr "predicable" "no")]) |
c65ebc55 JW |
4438 | |
4439 | (define_insn "*abssi2_internal" | |
0551c32d | 4440 | [(set (match_operand:SI 0 "gr_register_operand" "=r,r") |
e5bde68a | 4441 | (if_then_else:SI |
f2f90c63 RH |
4442 | (match_operator 4 "predicate_operator" |
4443 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4444 | (const_int 0)]) |
0551c32d RH |
4445 | (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI")) |
4446 | (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))] | |
c65ebc55 | 4447 | "" |
e5bde68a | 4448 | "#" |
52e12ad0 | 4449 | [(set_attr "itanium_class" "ialu,unknown") |
3b572406 | 4450 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4451 | |
4452 | (define_split | |
4453 | [(set (match_operand:SI 0 "register_operand" "") | |
e5bde68a | 4454 | (if_then_else:SI |
f2f90c63 RH |
4455 | (match_operator 4 "predicate_operator" |
4456 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4457 | (const_int 0)]) |
0551c32d RH |
4458 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4459 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4460 | "reload_completed && rtx_equal_p (operands[0], operands[3])" |
4461 | [(cond_exec | |
4462 | (match_dup 4) | |
4463 | (set (match_dup 0) | |
4464 | (neg:SI (match_dup 2))))] | |
c65ebc55 JW |
4465 | "") |
4466 | ||
e5bde68a RH |
4467 | (define_split |
4468 | [(set (match_operand:SI 0 "register_operand" "") | |
4469 | (if_then_else:SI | |
f2f90c63 RH |
4470 | (match_operator 4 "predicate_operator" |
4471 | [(match_operand:BI 1 "register_operand" "c,c") | |
e5bde68a | 4472 | (const_int 0)]) |
0551c32d RH |
4473 | (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" "")) |
4474 | (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))] | |
e5bde68a RH |
4475 | "reload_completed" |
4476 | [(cond_exec | |
4477 | (match_dup 4) | |
4478 | (set (match_dup 0) (neg:SI (match_dup 2)))) | |
4479 | (cond_exec | |
4480 | (match_dup 5) | |
4481 | (set (match_dup 0) (match_dup 3)))] | |
4482 | " | |
4483 | { | |
4484 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE, | |
f2f90c63 | 4485 | VOIDmode, operands[1], const0_rtx); |
e5bde68a RH |
4486 | }") |
4487 | ||
c65ebc55 JW |
4488 | \f |
4489 | ;; :::::::::::::::::::: | |
4490 | ;; :: | |
4491 | ;; :: Call and branch instructions | |
4492 | ;; :: | |
4493 | ;; :::::::::::::::::::: | |
4494 | ||
4495 | ;; Subroutine call instruction returning no value. Operand 0 is the function | |
4496 | ;; to call; operand 1 is the number of bytes of arguments pushed (in mode | |
4497 | ;; `SImode', except it is normally a `const_int'); operand 2 is the number of | |
4498 | ;; registers used as operands. | |
4499 | ||
4500 | ;; On most machines, operand 2 is not actually stored into the RTL pattern. It | |
4501 | ;; is supplied for the sake of some RISC machines which need to put this | |
4502 | ;; information into the assembler code; they can put it in the RTL instead of | |
4503 | ;; operand 1. | |
4504 | ||
4505 | (define_expand "call" | |
4506 | [(use (match_operand:DI 0 "" "")) | |
4507 | (use (match_operand 1 "" "")) | |
4508 | (use (match_operand 2 "" "")) | |
4509 | (use (match_operand 3 "" ""))] | |
4510 | "" | |
4511 | " | |
4512 | { | |
2ed4af6f | 4513 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 0); |
c65ebc55 JW |
4514 | DONE; |
4515 | }") | |
4516 | ||
2ed4af6f RH |
4517 | (define_expand "sibcall" |
4518 | [(use (match_operand:DI 0 "" "")) | |
4519 | (use (match_operand 1 "" "")) | |
4520 | (use (match_operand 2 "" "")) | |
4521 | (use (match_operand 3 "" ""))] | |
c65ebc55 JW |
4522 | "" |
4523 | " | |
4524 | { | |
2ed4af6f RH |
4525 | ia64_expand_call (NULL_RTX, operands[0], operands[2], 1); |
4526 | DONE; | |
c65ebc55 JW |
4527 | }") |
4528 | ||
c65ebc55 | 4529 | ;; Subroutine call instruction returning a value. Operand 0 is the hard |
2ed4af6f RH |
4530 | ;; register in which the value is returned. There are three more operands, |
4531 | ;; the same as the three operands of the `call' instruction (but with numbers | |
c65ebc55 | 4532 | ;; increased by one). |
2ed4af6f | 4533 | ;; |
c65ebc55 JW |
4534 | ;; Subroutines that return `BLKmode' objects use the `call' insn. |
4535 | ||
4536 | (define_expand "call_value" | |
4537 | [(use (match_operand 0 "" "")) | |
4538 | (use (match_operand:DI 1 "" "")) | |
4539 | (use (match_operand 2 "" "")) | |
4540 | (use (match_operand 3 "" "")) | |
4541 | (use (match_operand 4 "" ""))] | |
4542 | "" | |
4543 | " | |
4544 | { | |
2ed4af6f | 4545 | ia64_expand_call (operands[0], operands[1], operands[3], 0); |
c65ebc55 JW |
4546 | DONE; |
4547 | }") | |
4548 | ||
2ed4af6f RH |
4549 | (define_expand "sibcall_value" |
4550 | [(use (match_operand 0 "" "")) | |
4551 | (use (match_operand:DI 1 "" "")) | |
4552 | (use (match_operand 2 "" "")) | |
4553 | (use (match_operand 3 "" "")) | |
4554 | (use (match_operand 4 "" ""))] | |
c65ebc55 JW |
4555 | "" |
4556 | " | |
4557 | { | |
2ed4af6f RH |
4558 | ia64_expand_call (operands[0], operands[1], operands[3], 1); |
4559 | DONE; | |
c65ebc55 JW |
4560 | }") |
4561 | ||
c65ebc55 JW |
4562 | ;; Call subroutine returning any type. |
4563 | ||
4564 | (define_expand "untyped_call" | |
4565 | [(parallel [(call (match_operand 0 "" "") | |
4566 | (const_int 0)) | |
4567 | (match_operand 1 "" "") | |
4568 | (match_operand 2 "" "")])] | |
4569 | "" | |
4570 | " | |
4571 | { | |
4572 | int i; | |
4573 | ||
4574 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); | |
4575 | ||
4576 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
4577 | { | |
4578 | rtx set = XVECEXP (operands[2], 0, i); | |
4579 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
4580 | } | |
4581 | ||
4582 | /* The optimizer does not know that the call sets the function value | |
4583 | registers we stored in the result block. We avoid problems by | |
4584 | claiming that all hard registers are used and clobbered at this | |
4585 | point. */ | |
4586 | emit_insn (gen_blockage ()); | |
4587 | ||
4588 | DONE; | |
4589 | }") | |
4590 | ||
2ed4af6f | 4591 | (define_insn "call_nopic" |
52e12ad0 | 4592 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4593 | (match_operand 1 "" "")) |
52e12ad0 | 4594 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4595 | "" |
4596 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4597 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4598 | |
4599 | (define_insn "call_value_nopic" | |
4600 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4601 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f | 4602 | (match_operand 2 "" ""))) |
52e12ad0 | 4603 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4604 | "" |
4605 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4606 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4607 | |
4608 | (define_insn "sibcall_nopic" | |
52e12ad0 | 4609 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f | 4610 | (match_operand 1 "" "")) |
52e12ad0 | 4611 | (use (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4612 | "" |
4613 | "br%+.many %0" | |
52e12ad0 | 4614 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4615 | |
4616 | (define_insn "call_pic" | |
52e12ad0 | 4617 | [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i")) |
2ed4af6f RH |
4618 | (match_operand 1 "" "")) |
4619 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4620 | (clobber (match_operand:DI 2 "register_operand" "=b,b"))] |
2ed4af6f RH |
4621 | "" |
4622 | "br.call%+.many %2 = %0" | |
52e12ad0 | 4623 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4624 | |
4625 | (define_insn "call_value_pic" | |
4626 | [(set (match_operand 0 "" "") | |
52e12ad0 | 4627 | (call (mem:DI (match_operand:DI 1 "call_operand" "b,i")) |
2ed4af6f RH |
4628 | (match_operand 2 "" ""))) |
4629 | (use (unspec [(reg:DI 1)] 9)) | |
52e12ad0 | 4630 | (clobber (match_operand:DI 3 "register_operand" "=b,b"))] |
2ed4af6f RH |
4631 | "" |
4632 | "br.call%+.many %3 = %1" | |
52e12ad0 | 4633 | [(set_attr "itanium_class" "br,scall")]) |
2ed4af6f RH |
4634 | |
4635 | (define_insn "sibcall_pic" | |
4636 | [(call (mem:DI (match_operand:DI 0 "call_operand" "bi")) | |
4637 | (match_operand 1 "" "")) | |
4638 | (use (unspec [(reg:DI 1)] 9)) | |
4639 | (use (match_operand:DI 2 "register_operand" "=b"))] | |
4640 | "" | |
4641 | "br%+.many %0" | |
52e12ad0 | 4642 | [(set_attr "itanium_class" "br")]) |
2ed4af6f | 4643 | |
c65ebc55 JW |
4644 | (define_insn "return_internal" |
4645 | [(return) | |
4646 | (use (match_operand:DI 0 "register_operand" "b"))] | |
4647 | "" | |
4648 | "br.ret.sptk.many %0" | |
52e12ad0 | 4649 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4650 | |
4651 | (define_insn "return" | |
4652 | [(return)] | |
4653 | "ia64_direct_return ()" | |
4654 | "br.ret.sptk.many rp" | |
52e12ad0 | 4655 | [(set_attr "itanium_class" "br")]) |
c65ebc55 | 4656 | |
6b6c1201 | 4657 | (define_insn "*return_true" |
c65ebc55 | 4658 | [(set (pc) |
6b6c1201 | 4659 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4660 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4661 | (const_int 0)]) |
c65ebc55 JW |
4662 | (return) |
4663 | (pc)))] | |
4664 | "ia64_direct_return ()" | |
13da91fd | 4665 | "(%J0) br.ret%+.many rp" |
52e12ad0 | 4666 | [(set_attr "itanium_class" "br") |
e5bde68a | 4667 | (set_attr "predicable" "no")]) |
c65ebc55 | 4668 | |
6b6c1201 | 4669 | (define_insn "*return_false" |
c65ebc55 | 4670 | [(set (pc) |
6b6c1201 | 4671 | (if_then_else (match_operator 0 "predicate_operator" |
f2f90c63 | 4672 | [(match_operand:BI 1 "register_operand" "c") |
6b6c1201 | 4673 | (const_int 0)]) |
c65ebc55 JW |
4674 | (pc) |
4675 | (return)))] | |
4676 | "ia64_direct_return ()" | |
13da91fd | 4677 | "(%j0) br.ret%+.many rp" |
52e12ad0 | 4678 | [(set_attr "itanium_class" "br") |
e5bde68a | 4679 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4680 | |
4681 | (define_insn "jump" | |
4682 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
4683 | "" | |
4684 | "br %l0" | |
52e12ad0 | 4685 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4686 | |
4687 | (define_insn "indirect_jump" | |
4688 | [(set (pc) (match_operand:DI 0 "register_operand" "b"))] | |
4689 | "" | |
4690 | "br %0" | |
52e12ad0 | 4691 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4692 | |
4693 | (define_expand "tablejump" | |
4694 | [(match_operand:DI 0 "register_operand" "") | |
4695 | (match_operand 1 "" "")] | |
4696 | "" | |
4697 | " | |
4698 | { | |
4699 | rtx tmp1 = gen_reg_rtx (DImode); | |
4700 | rtx tmp2 = gen_reg_rtx (DImode); | |
4701 | ||
4702 | emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[1])); | |
4703 | emit_insn (gen_adddi3 (tmp2, operands[0], tmp1)); | |
4704 | emit_jump_insn (gen_tablejump_internal (tmp2, operands[1])); | |
4705 | DONE; | |
4706 | }") | |
4707 | ||
4708 | (define_insn "tablejump_internal" | |
4709 | [(set (pc) (match_operand:DI 0 "register_operand" "b")) | |
4710 | (use (label_ref (match_operand 1 "" "")))] | |
4711 | "" | |
4712 | "br %0" | |
52e12ad0 | 4713 | [(set_attr "itanium_class" "br")]) |
c65ebc55 JW |
4714 | |
4715 | \f | |
4716 | ;; :::::::::::::::::::: | |
4717 | ;; :: | |
4718 | ;; :: Prologue and Epilogue instructions | |
4719 | ;; :: | |
4720 | ;; :::::::::::::::::::: | |
4721 | ||
4722 | (define_expand "prologue" | |
4723 | [(const_int 1)] | |
4724 | "" | |
4725 | " | |
4726 | { | |
4727 | ia64_expand_prologue (); | |
4728 | DONE; | |
4729 | }") | |
4730 | ||
4731 | (define_expand "epilogue" | |
2ed4af6f RH |
4732 | [(return)] |
4733 | "" | |
4734 | " | |
4735 | { | |
4736 | ia64_expand_epilogue (0); | |
4737 | DONE; | |
4738 | }") | |
4739 | ||
4740 | (define_expand "sibcall_epilogue" | |
4741 | [(return)] | |
c65ebc55 JW |
4742 | "" |
4743 | " | |
4744 | { | |
2ed4af6f | 4745 | ia64_expand_epilogue (1); |
c65ebc55 JW |
4746 | DONE; |
4747 | }") | |
4748 | ||
4749 | ;; This prevents the scheduler from moving the SP decrement past FP-relative | |
4750 | ;; stack accesses. This is the same as adddi3 plus the extra set. | |
4751 | ||
4752 | (define_insn "prologue_allocate_stack" | |
4753 | [(set (match_operand:DI 0 "register_operand" "=r,r,r") | |
4754 | (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a") | |
0551c32d | 4755 | (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J"))) |
c65ebc55 JW |
4756 | (set (match_operand:DI 3 "register_operand" "=r,r,r") |
4757 | (match_dup 3))] | |
4758 | "" | |
4759 | "@ | |
4760 | add %0 = %1, %2 | |
4761 | adds %0 = %2, %1 | |
4762 | addl %0 = %2, %1" | |
52e12ad0 | 4763 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4764 | |
4765 | ;; This prevents the scheduler from moving the SP restore past FP-relative | |
4766 | ;; stack accesses. This is similar to movdi plus the extra set. | |
4767 | ||
4768 | (define_insn "epilogue_deallocate_stack" | |
4769 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4770 | (match_operand:DI 1 "register_operand" "+r")) | |
4771 | (set (match_dup 1) (match_dup 1))] | |
4772 | "" | |
4773 | "mov %0 = %1" | |
52e12ad0 | 4774 | [(set_attr "itanium_class" "ialu")]) |
c65ebc55 JW |
4775 | |
4776 | ;; Allocate a new register frame. | |
4777 | ||
4778 | (define_insn "alloc" | |
4779 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4780 | (unspec_volatile:DI [(const_int 0)] 0)) | |
4781 | (use (match_operand:DI 1 "const_int_operand" "i")) | |
4782 | (use (match_operand:DI 2 "const_int_operand" "i")) | |
4783 | (use (match_operand:DI 3 "const_int_operand" "i")) | |
4784 | (use (match_operand:DI 4 "const_int_operand" "i"))] | |
4785 | "" | |
4786 | "alloc %0 = ar.pfs, %1, %2, %3, %4" | |
52e12ad0 | 4787 | [(set_attr "itanium_class" "syst_m0") |
e5bde68a | 4788 | (set_attr "predicable" "no")]) |
c65ebc55 | 4789 | |
97e242b0 RH |
4790 | ;; Modifies ar.unat |
4791 | (define_expand "gr_spill" | |
870f9ec0 RH |
4792 | [(parallel [(set (match_operand:DI 0 "memory_operand" "=m") |
4793 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") | |
4794 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4795 | (clobber (match_dup 3))])] | |
97e242b0 | 4796 | "" |
870f9ec0 | 4797 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4798 | |
870f9ec0 | 4799 | (define_insn "gr_spill_internal" |
c65ebc55 | 4800 | [(set (match_operand:DI 0 "memory_operand" "=m") |
870f9ec0 RH |
4801 | (unspec:DI [(match_operand:DI 1 "register_operand" "r") |
4802 | (match_operand:DI 2 "const_int_operand" "")] 1)) | |
4803 | (clobber (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4804 | "" |
2130b7fb BS |
4805 | "* |
4806 | { | |
4807 | return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\"; | |
4808 | }" | |
52e12ad0 | 4809 | [(set_attr "itanium_class" "st")]) |
c65ebc55 | 4810 | |
97e242b0 RH |
4811 | ;; Reads ar.unat |
4812 | (define_expand "gr_restore" | |
870f9ec0 RH |
4813 | [(parallel [(set (match_operand:DI 0 "register_operand" "=r") |
4814 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
4815 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4816 | (use (match_dup 3))])] | |
97e242b0 | 4817 | "" |
870f9ec0 | 4818 | "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);") |
97e242b0 | 4819 | |
870f9ec0 | 4820 | (define_insn "gr_restore_internal" |
c65ebc55 | 4821 | [(set (match_operand:DI 0 "register_operand" "=r") |
870f9ec0 RH |
4822 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") |
4823 | (match_operand:DI 2 "const_int_operand" "")] 2)) | |
4824 | (use (match_operand:DI 3 "register_operand" ""))] | |
c65ebc55 | 4825 | "" |
2130b7fb BS |
4826 | "* |
4827 | { | |
4828 | return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\"; | |
4829 | }" | |
52e12ad0 | 4830 | [(set_attr "itanium_class" "ld")]) |
c65ebc55 JW |
4831 | |
4832 | (define_insn "fr_spill" | |
3f622353 RH |
4833 | [(set (match_operand:TF 0 "memory_operand" "=m") |
4834 | (unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))] | |
c65ebc55 JW |
4835 | "" |
4836 | "stf.spill %0 = %1%P0" | |
52e12ad0 | 4837 | [(set_attr "itanium_class" "stf")]) |
c65ebc55 JW |
4838 | |
4839 | (define_insn "fr_restore" | |
3f622353 RH |
4840 | [(set (match_operand:TF 0 "register_operand" "=f") |
4841 | (unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))] | |
c65ebc55 JW |
4842 | "" |
4843 | "ldf.fill %0 = %1%P1" | |
52e12ad0 | 4844 | [(set_attr "itanium_class" "fld")]) |
c65ebc55 | 4845 | |
0024a804 JW |
4846 | ;; ??? The explicit stop is not ideal. It would be better if |
4847 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4848 | ;; fixed later. This avoids an RSE DV. | |
4849 | ||
0c96007e AM |
4850 | (define_insn "bsp_value" |
4851 | [(set (match_operand:DI 0 "register_operand" "=r") | |
4852 | (unspec:DI [(const_int 0)] 20))] | |
4853 | "" | |
0024a804 | 4854 | ";;\;mov %0 = ar.bsp" |
52e12ad0 | 4855 | [(set_attr "itanium_class" "frar_i")]) |
0c96007e AM |
4856 | |
4857 | (define_insn "set_bsp" | |
2ed4af6f | 4858 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)] |
0c96007e | 4859 | "" |
13da91fd | 4860 | "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19" |
52e12ad0 | 4861 | [(set_attr "itanium_class" "unknown") |
e5bde68a | 4862 | (set_attr "predicable" "no")]) |
ce152ef8 | 4863 | |
0024a804 JW |
4864 | ;; ??? The explicit stops are not ideal. It would be better if |
4865 | ;; rtx_needs_barrier took care of this, but this is something that can be | |
4866 | ;; fixed later. This avoids an RSE DV. | |
4867 | ||
ce152ef8 AM |
4868 | (define_insn "flushrs" |
4869 | [(unspec [(const_int 0)] 21)] | |
4870 | "" | |
0024a804 | 4871 | ";;\;flushrs\;;;" |
52e12ad0 | 4872 | [(set_attr "itanium_class" "rse_m")]) |
c65ebc55 JW |
4873 | \f |
4874 | ;; :::::::::::::::::::: | |
4875 | ;; :: | |
4876 | ;; :: Miscellaneous instructions | |
4877 | ;; :: | |
4878 | ;; :::::::::::::::::::: | |
4879 | ||
4880 | ;; ??? Emiting a NOP instruction isn't very useful. This should probably | |
4881 | ;; be emitting ";;" to force a break in the instruction packing. | |
4882 | ||
4883 | ;; No operation, needed in case the user uses -g but not -O. | |
4884 | (define_insn "nop" | |
4885 | [(const_int 0)] | |
4886 | "" | |
4887 | "nop 0" | |
52e12ad0 | 4888 | [(set_attr "itanium_class" "unknown")]) |
c65ebc55 | 4889 | |
2130b7fb BS |
4890 | (define_insn "nop_m" |
4891 | [(const_int 1)] | |
4892 | "" | |
4893 | "nop.m 0" | |
4894 | [(set_attr "itanium_class" "nop_m")]) | |
4895 | ||
4896 | (define_insn "nop_i" | |
4897 | [(const_int 2)] | |
4898 | "" | |
4899 | "nop.i 0" | |
4900 | [(set_attr "itanium_class" "nop_i")]) | |
4901 | ||
4902 | (define_insn "nop_f" | |
4903 | [(const_int 3)] | |
4904 | "" | |
4905 | "nop.f 0" | |
4906 | [(set_attr "itanium_class" "nop_f")]) | |
4907 | ||
4908 | (define_insn "nop_b" | |
4909 | [(const_int 4)] | |
4910 | "" | |
4911 | "nop.b 0" | |
4912 | [(set_attr "itanium_class" "nop_b")]) | |
4913 | ||
4914 | (define_insn "nop_x" | |
4915 | [(const_int 5)] | |
4916 | "" | |
4917 | "" | |
4918 | [(set_attr "itanium_class" "nop_x")]) | |
4919 | ||
4920 | (define_expand "cycle_display" | |
4921 | [(unspec [(match_operand 0 "const_int_operand" "")] 23)] | |
4922 | "ia64_final_schedule" | |
4923 | "") | |
4924 | ||
4925 | (define_insn "*cycle_display_1" | |
4926 | [(unspec [(match_operand 0 "const_int_operand" "")] 23)] | |
4927 | "" | |
4928 | "// cycle %0" | |
4929 | [(set_attr "itanium_class" "ignore") | |
4930 | (set_attr "predicable" "no")]) | |
4931 | ||
4932 | (define_insn "bundle_selector" | |
4933 | [(unspec [(match_operand 0 "const_int_operand" "")] 22)] | |
4934 | "" | |
4935 | "* | |
4936 | { | |
4937 | return get_bundle_name (INTVAL (operands[0])); | |
4938 | }" | |
4939 | [(set_attr "itanium_class" "ignore") | |
4940 | (set_attr "predicable" "no")]) | |
4941 | ||
c65ebc55 JW |
4942 | ;; Pseudo instruction that prevents the scheduler from moving code above this |
4943 | ;; point. | |
4944 | (define_insn "blockage" | |
4945 | [(unspec_volatile [(const_int 0)] 1)] | |
4946 | "" | |
4947 | "" | |
52e12ad0 | 4948 | [(set_attr "itanium_class" "ignore") |
e5bde68a | 4949 | (set_attr "predicable" "no")]) |
c65ebc55 JW |
4950 | |
4951 | (define_insn "insn_group_barrier" | |
2130b7fb | 4952 | [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)] |
c65ebc55 JW |
4953 | "" |
4954 | ";;" | |
52e12ad0 | 4955 | [(set_attr "itanium_class" "stop_bit") |
e5bde68a | 4956 | (set_attr "predicable" "no")]) |
c65ebc55 | 4957 | |
f12f25a7 RH |
4958 | (define_insn "break_f" |
4959 | [(unspec_volatile [(const_int 0)] 3)] | |
4960 | "" | |
4961 | "break.f 0" | |
4962 | [(set_attr "itanium_class" "nop_f")]) | |
c65ebc55 JW |
4963 | \f |
4964 | ;; Non-local goto support. | |
4965 | ||
4966 | (define_expand "save_stack_nonlocal" | |
4967 | [(use (match_operand:OI 0 "memory_operand" "")) | |
4968 | (use (match_operand:DI 1 "register_operand" ""))] | |
4969 | "" | |
4970 | " | |
4971 | { | |
4972 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
4973 | \"__ia64_save_stack_nonlocal\"), | |
4974 | 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode, | |
4975 | operands[1], Pmode); | |
4976 | DONE; | |
4977 | }") | |
4978 | ||
4979 | (define_expand "nonlocal_goto" | |
4980 | [(use (match_operand 0 "general_operand" "")) | |
4981 | (use (match_operand 1 "general_operand" "")) | |
4982 | (use (match_operand 2 "general_operand" "")) | |
4983 | (use (match_operand 3 "general_operand" ""))] | |
4984 | "" | |
4985 | " | |
4986 | { | |
c65ebc55 | 4987 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"), |
8206fc89 AM |
4988 | LCT_NORETURN, VOIDmode, 3, |
4989 | operands[3], Pmode, | |
c65ebc55 | 4990 | copy_to_reg (XEXP (operands[2], 0)), Pmode, |
8206fc89 | 4991 | operands[1], Pmode); |
c65ebc55 JW |
4992 | emit_barrier (); |
4993 | DONE; | |
4994 | }") | |
4995 | ||
97e242b0 RH |
4996 | ;; The rest of the setjmp processing happens with the nonlocal_goto expander. |
4997 | ;; ??? This is not tested. | |
4998 | (define_expand "builtin_setjmp_setup" | |
4999 | [(use (match_operand:DI 0 "" ""))] | |
c65ebc55 JW |
5000 | "" |
5001 | " | |
5002 | { | |
97e242b0 RH |
5003 | emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1))); |
5004 | DONE; | |
5005 | }") | |
5006 | ||
5007 | (define_expand "builtin_setjmp_receiver" | |
5008 | [(use (match_operand:DI 0 "" ""))] | |
5009 | "" | |
5010 | " | |
5011 | { | |
5012 | emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0)); | |
c65ebc55 JW |
5013 | DONE; |
5014 | }") | |
5015 | ||
0c96007e AM |
5016 | (define_expand "eh_epilogue" |
5017 | [(use (match_operand:DI 0 "register_operand" "r")) | |
5018 | (use (match_operand:DI 1 "register_operand" "r")) | |
5019 | (use (match_operand:DI 2 "register_operand" "r"))] | |
5020 | "" | |
5021 | " | |
5022 | { | |
5023 | rtx bsp = gen_rtx_REG (Pmode, 10); | |
5024 | rtx sp = gen_rtx_REG (Pmode, 9); | |
5025 | ||
5026 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10) | |
5027 | { | |
5028 | emit_move_insn (bsp, operands[0]); | |
5029 | operands[0] = bsp; | |
5030 | } | |
5031 | if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9) | |
5032 | { | |
5033 | emit_move_insn (sp, operands[2]); | |
5034 | operands[2] = sp; | |
5035 | } | |
5036 | emit_insn (gen_rtx_USE (VOIDmode, sp)); | |
5037 | emit_insn (gen_rtx_USE (VOIDmode, bsp)); | |
5038 | ||
5039 | cfun->machine->ia64_eh_epilogue_sp = sp; | |
5040 | cfun->machine->ia64_eh_epilogue_bsp = bsp; | |
0c96007e | 5041 | }") |
9525c690 JW |
5042 | \f |
5043 | ;; Builtin apply support. | |
5044 | ||
5045 | (define_expand "restore_stack_nonlocal" | |
5046 | [(use (match_operand:DI 0 "register_operand" "")) | |
5047 | (use (match_operand:OI 1 "memory_operand" ""))] | |
5048 | "" | |
5049 | " | |
5050 | { | |
5051 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, | |
5052 | \"__ia64_restore_stack_nonlocal\"), | |
5053 | 0, VOIDmode, 1, | |
5054 | copy_to_reg (XEXP (operands[1], 0)), Pmode); | |
5055 | DONE; | |
5056 | }") | |
5057 | ||
5058 | \f | |
5059 | ;;; Intrinsics support. | |
c65ebc55 | 5060 | |
0551c32d RH |
5061 | (define_expand "mf" |
5062 | [(set (mem:BLK (match_dup 0)) | |
5063 | (unspec:BLK [(mem:BLK (match_dup 0))] 12))] | |
5064 | "" | |
5065 | " | |
5066 | { | |
5067 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
5068 | MEM_VOLATILE_P (operands[0]) = 1; | |
5069 | }") | |
5070 | ||
5071 | (define_insn "*mf_internal" | |
5072 | [(set (match_operand:BLK 0 "" "") | |
5073 | (unspec:BLK [(match_operand:BLK 1 "" "")] 12))] | |
c65ebc55 JW |
5074 | "" |
5075 | "mf" | |
52e12ad0 | 5076 | [(set_attr "itanium_class" "syst_m")]) |
c65ebc55 JW |
5077 | |
5078 | (define_insn "fetchadd_acq_si" | |
0551c32d RH |
5079 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5080 | (match_dup 1)) | |
5081 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5082 | (unspec:SI [(match_dup 1) | |
5083 | (match_operand:SI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5084 | "" |
5085 | "fetchadd4.acq %0 = %1, %2" | |
52e12ad0 | 5086 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5087 | |
5088 | (define_insn "fetchadd_acq_di" | |
0551c32d RH |
5089 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5090 | (match_dup 1)) | |
5091 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5092 | (unspec:DI [(match_dup 1) | |
5093 | (match_operand:DI 2 "fetchadd_operand" "n")] 19))] | |
c65ebc55 JW |
5094 | "" |
5095 | "fetchadd8.acq %0 = %1, %2" | |
52e12ad0 | 5096 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5097 | |
5098 | (define_insn "cmpxchg_acq_si" | |
0551c32d RH |
5099 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5100 | (match_dup 1)) | |
5101 | (set (match_operand:SI 1 "not_postinc_memory_operand" "+S") | |
5102 | (unspec:SI [(match_dup 1) | |
5103 | (match_operand:SI 2 "gr_register_operand" "r") | |
97e242b0 | 5104 | (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))] |
c65ebc55 | 5105 | "" |
97e242b0 | 5106 | "cmpxchg4.acq %0 = %1, %2, %3" |
52e12ad0 | 5107 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5108 | |
5109 | (define_insn "cmpxchg_acq_di" | |
0551c32d RH |
5110 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5111 | (match_dup 1)) | |
5112 | (set (match_operand:DI 1 "not_postinc_memory_operand" "+S") | |
5113 | (unspec:DI [(match_dup 1) | |
5114 | (match_operand:DI 2 "gr_register_operand" "r") | |
5115 | (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))] | |
c65ebc55 | 5116 | "" |
97e242b0 | 5117 | "cmpxchg8.acq %0 = %1, %2, %3" |
52e12ad0 | 5118 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 | 5119 | |
c65ebc55 | 5120 | (define_insn "xchgsi" |
0551c32d RH |
5121 | [(set (match_operand:SI 0 "gr_register_operand" "=r") |
5122 | (match_operand:SI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5123 | (set (match_dup 1) |
0551c32d | 5124 | (match_operand:SI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5125 | "" |
5126 | "xchg4 %0 = %1, %2" | |
52e12ad0 | 5127 | [(set_attr "itanium_class" "sem")]) |
c65ebc55 JW |
5128 | |
5129 | (define_insn "xchgdi" | |
0551c32d RH |
5130 | [(set (match_operand:DI 0 "gr_register_operand" "=r") |
5131 | (match_operand:DI 1 "not_postinc_memory_operand" "+S")) | |
c65ebc55 | 5132 | (set (match_dup 1) |
0551c32d | 5133 | (match_operand:DI 2 "gr_register_operand" "r"))] |
c65ebc55 JW |
5134 | "" |
5135 | "xchg8 %0 = %1, %2" | |
52e12ad0 | 5136 | [(set_attr "itanium_class" "sem")]) |
e5bde68a RH |
5137 | \f |
5138 | ;; Predication. | |
5139 | ||
5140 | (define_cond_exec | |
5141 | [(match_operator 0 "predicate_operator" | |
f2f90c63 | 5142 | [(match_operand:BI 1 "register_operand" "c") |
e5bde68a RH |
5143 | (const_int 0)])] |
5144 | "" | |
5145 | "(%J0)") | |
3b572406 RH |
5146 | |
5147 | (define_insn "pred_rel_mutex" | |
f2f90c63 RH |
5148 | [(set (match_operand:BI 0 "register_operand" "+c") |
5149 | (unspec:BI [(match_dup 0)] 7))] | |
3b572406 | 5150 | "" |
054451ea | 5151 | ".pred.rel.mutex %0, %I0" |
52e12ad0 | 5152 | [(set_attr "itanium_class" "ignore") |
3b572406 | 5153 | (set_attr "predicable" "no")]) |
ca3920ad JW |
5154 | |
5155 | (define_insn "safe_across_calls_all" | |
5156 | [(unspec_volatile [(const_int 0)] 8)] | |
5157 | "" | |
5158 | ".pred.safe_across_calls p1-p63" | |
52e12ad0 | 5159 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5160 | (set_attr "predicable" "no")]) |
5161 | ||
5162 | (define_insn "safe_across_calls_normal" | |
5163 | [(unspec_volatile [(const_int 0)] 9)] | |
5164 | "" | |
5165 | "* | |
5166 | { | |
5167 | emit_safe_across_calls (asm_out_file); | |
5168 | return \"\"; | |
5169 | }" | |
52e12ad0 | 5170 | [(set_attr "itanium_class" "ignore") |
ca3920ad JW |
5171 | (set_attr "predicable" "no")]) |
5172 | ||
6dd12198 SE |
5173 | ;; |
5174 | ;; | |
5175 | ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit | |
5176 | ;; pointer. This is used by the HP-UX 32 bit mode. | |
5177 | ||
5178 | (define_insn "ptr_extend" | |
5179 | [(set (match_operand:DI 0 "gr_register_operand" "=r") | |
5180 | (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] 24))] | |
5181 | "" | |
5182 | "addp4 %0 = 0,%1" | |
5183 | [(set_attr "itanium_class" "ialu")]) | |
5184 |