]>
Commit | Line | Data |
---|---|---|
58ada791 | 1 | ;; Itanium2 DFA descriptions for insn scheduling and bundling. |
71e45bc2 | 2 | ;; Copyright (C) 2002, 2004, 2005, 2007, 2008, 2011 |
3 | ;; Free Software Foundation, Inc. | |
58ada791 | 4 | ;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
5 | ;; | |
73f45a5c | 6 | ;; This file is part of GCC. |
58ada791 | 7 | ;; |
73f45a5c | 8 | ;; GCC is free software; you can redistribute it and/or modify |
58ada791 | 9 | ;; it under the terms of the GNU General Public License as published by |
038d1e19 | 10 | ;; the Free Software Foundation; either version 3, or (at your option) |
58ada791 | 11 | ;; any later version. |
12 | ;; | |
73f45a5c | 13 | ;; GCC is distributed in the hope that it will be useful, |
58ada791 | 14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | ;; along with GCC; see the file COPYING3. If not see |
20 | ;; <http://www.gnu.org/licenses/>. */ | |
58ada791 | 21 | ;; |
22 | ||
23 | /* This is description of pipeline hazards based on DFA. The | |
24 | following constructions can be used for this: | |
25 | ||
26 | o define_cpu_unit string [string]) describes a cpu functional unit | |
27 | (separated by comma). | |
28 | ||
29 | 1st operand: Names of cpu function units. | |
30 | 2nd operand: Name of automaton (see comments for | |
31 | DEFINE_AUTOMATON). | |
32 | ||
33 | All define_reservations and define_cpu_units should have unique | |
33f88b1c | 34 | names which cannot be "nothing". |
58ada791 | 35 | |
36 | o (exclusion_set string string) means that each CPU function unit | |
33f88b1c | 37 | in the first string cannot be reserved simultaneously with each |
58ada791 | 38 | unit whose name is in the second string and vise versa. CPU |
39 | units in the string are separated by commas. For example, it is | |
40 | useful for description CPU with fully pipelined floating point | |
41 | functional unit which can execute simultaneously only single | |
42 | floating point insns or only double floating point insns. | |
43 | ||
44 | o (presence_set string string) means that each CPU function unit in | |
33f88b1c | 45 | the first string cannot be reserved unless at least one of |
58ada791 | 46 | pattern of units whose names are in the second string is |
47 | reserved. This is an asymmetric relation. CPU units or unit | |
48 | patterns in the strings are separated by commas. Pattern is one | |
49 | unit name or unit names separated by white-spaces. | |
50 | ||
51 | For example, it is useful for description that slot1 is reserved | |
52 | after slot0 reservation for a VLIW processor. We could describe | |
53 | it by the following construction | |
54 | ||
55 | (presence_set "slot1" "slot0") | |
56 | ||
57 | Or slot1 is reserved only after slot0 and unit b0 reservation. | |
58 | In this case we could write | |
59 | ||
60 | (presence_set "slot1" "slot0 b0") | |
61 | ||
62 | All CPU functional units in a set should belong to the same | |
63 | automaton. | |
64 | ||
65 | o (final_presence_set string string) is analogous to | |
66 | `presence_set'. The difference between them is when checking is | |
67 | done. When an instruction is issued in given automaton state | |
68 | reflecting all current and planned unit reservations, the | |
69 | automaton state is changed. The first state is a source state, | |
70 | the second one is a result state. Checking for `presence_set' is | |
71 | done on the source state reservation, checking for | |
72 | `final_presence_set' is done on the result reservation. This | |
73 | construction is useful to describe a reservation which is | |
74 | actually two subsequent reservations. For example, if we use | |
75 | ||
76 | (presence_set "slot1" "slot0") | |
77 | ||
78 | the following insn will be never issued (because slot1 requires | |
79 | slot0 which is absent in the source state). | |
80 | ||
81 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
82 | ||
83 | but it can be issued if we use analogous `final_presence_set'. | |
84 | ||
85 | o (absence_set string string) means that each CPU function unit in | |
86 | the first string can be reserved only if each pattern of units | |
87 | whose names are in the second string is not reserved. This is an | |
88 | asymmetric relation (actually exclusion set is analogous to this | |
89 | one but it is symmetric). CPU units or unit patterns in the | |
90 | string are separated by commas. Pattern is one unit name or unit | |
91 | names separated by white-spaces. | |
92 | ||
33f88b1c | 93 | For example, it is useful for description that slot0 cannot be |
58ada791 | 94 | reserved after slot1 or slot2 reservation for a VLIW processor. |
95 | We could describe it by the following construction | |
96 | ||
97 | (absence_set "slot2" "slot0, slot1") | |
98 | ||
33f88b1c | 99 | Or slot2 cannot be reserved if slot0 and unit b0 are reserved or |
58ada791 | 100 | slot1 and unit b1 are reserved . In this case we could write |
101 | ||
102 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
103 | ||
104 | All CPU functional units in a set should to belong the same | |
105 | automaton. | |
106 | ||
107 | o (final_absence_set string string) is analogous to `absence_set' but | |
108 | checking is done on the result (state) reservation. See comments | |
109 | for final_presence_set. | |
110 | ||
111 | o (define_bypass number out_insn_names in_insn_names) names bypass with | |
112 | given latency (the first number) from insns given by the first | |
113 | string (see define_insn_reservation) into insns given by the | |
114 | second string. Insn names in the strings are separated by | |
115 | commas. | |
116 | ||
117 | o (define_automaton string) describes names of an automaton | |
118 | generated and used for pipeline hazards recognition. The names | |
119 | are separated by comma. Actually it is possibly to generate the | |
120 | single automaton but unfortunately it can be very large. If we | |
121 | use more one automata, the summary size of the automata usually | |
122 | is less than the single one. The automaton name is used in | |
123 | define_cpu_unit. All automata should have unique names. | |
124 | ||
125 | o (automata_option string) describes option for generation of | |
126 | automata. Currently there are the following options: | |
127 | ||
128 | o "no-minimization" which makes no minimization of automata. | |
129 | This is only worth to do when we are debugging the description | |
130 | and need to look more accurately at reservations of states. | |
131 | ||
26ac986e | 132 | o "ndfa" which makes automata with nondeterministic reservation |
58ada791 | 133 | by insns. |
134 | ||
135 | o (define_reservation string string) names reservation (the first | |
136 | string) of cpu functional units (the 2nd string). Sometimes unit | |
137 | reservations for different insns contain common parts. In such | |
138 | case, you describe common part and use one its name (the 1st | |
139 | parameter) in regular expression in define_insn_reservation. All | |
140 | define_reservations, define results and define_cpu_units should | |
33f88b1c | 141 | have unique names which cannot be "nothing". |
58ada791 | 142 | |
143 | o (define_insn_reservation name default_latency condition regexpr) | |
144 | describes reservation of cpu functional units (the 3nd operand) | |
145 | for instruction which is selected by the condition (the 2nd | |
146 | parameter). The first parameter is used for output of debugging | |
147 | information. The reservations are described by a regular | |
148 | expression according the following syntax: | |
149 | ||
150 | regexp = regexp "," oneof | |
151 | | oneof | |
152 | ||
153 | oneof = oneof "|" allof | |
154 | | allof | |
155 | ||
156 | allof = allof "+" repeat | |
157 | | repeat | |
158 | ||
159 | repeat = element "*" number | |
160 | | element | |
161 | ||
162 | element = cpu_function_name | |
163 | | reservation_name | |
164 | | result_name | |
165 | | "nothing" | |
166 | | "(" regexp ")" | |
167 | ||
168 | 1. "," is used for describing start of the next cycle in | |
169 | reservation. | |
170 | ||
171 | 2. "|" is used for describing the reservation described by the | |
172 | first regular expression *or* the reservation described by | |
173 | the second regular expression *or* etc. | |
174 | ||
175 | 3. "+" is used for describing the reservation described by the | |
176 | first regular expression *and* the reservation described by | |
177 | the second regular expression *and* etc. | |
178 | ||
3c364971 | 179 | 4. "*" is used for convenience and simply means sequence in |
58ada791 | 180 | which the regular expression are repeated NUMBER times with |
181 | cycle advancing (see ","). | |
182 | ||
183 | 5. cpu function unit name which means reservation. | |
184 | ||
185 | 6. reservation name -- see define_reservation. | |
186 | ||
187 | 7. string "nothing" means no units reservation. | |
188 | ||
189 | */ | |
190 | ||
191 | (define_automaton "two") | |
192 | ||
193 | ;; All possible combinations of bundles/syllables | |
194 | (define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
195 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two") | |
196 | (define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
197 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two") | |
198 | (define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
199 | 2_0mib., 2_0mmb., 2_0mfb." "two") | |
200 | ||
201 | (define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
202 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two") | |
203 | (define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
204 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two") | |
205 | (define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
206 | 2_1mib., 2_1mmb., 2_1mfb." "two") | |
207 | ||
208 | ;; Slot 1 | |
209 | (exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
210 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
211 | (exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\ | |
212 | 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
213 | (exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\ | |
214 | 2_0m.fb, 2_0m.lx") | |
215 | (exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\ | |
216 | 2_0m.lx") | |
217 | (exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
218 | (exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
219 | (exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx") | |
220 | (exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx") | |
221 | (exclusion_set "2_0m.fb" "2_0m.lx") | |
222 | ||
223 | ;; Slot 2 | |
224 | (exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
225 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
226 | (exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
227 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
228 | (exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\ | |
229 | 2_0mf.b, 2_0mlx.") | |
230 | (exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\ | |
231 | 2_0mlx.") | |
232 | (exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
233 | (exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
234 | (exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.") | |
235 | (exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.") | |
236 | (exclusion_set "2_0mf.b" "2_0mlx.") | |
237 | ||
238 | ;; Slot 3 | |
239 | (exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
240 | 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
241 | (exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
242 | 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
243 | (exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\ | |
244 | 2_0mfb., 2_0mlx.") | |
245 | (exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\ | |
246 | 2_0mlx.") | |
247 | (exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
248 | (exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
249 | (exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.") | |
250 | (exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.") | |
251 | (exclusion_set "2_0mfb." "2_0mlx.") | |
252 | ||
253 | ;; Slot 4 | |
254 | (exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
255 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
256 | (exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\ | |
257 | 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
258 | (exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\ | |
259 | 2_1m.fb, 2_1m.lx") | |
260 | (exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\ | |
261 | 2_1m.lx") | |
262 | (exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
263 | (exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
264 | (exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx") | |
265 | (exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx") | |
266 | (exclusion_set "2_1m.fb" "2_1m.lx") | |
267 | ||
268 | ;; Slot 5 | |
269 | (exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
270 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
271 | (exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
272 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
273 | (exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\ | |
274 | 2_1mf.b, 2_1mlx.") | |
275 | (exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\ | |
276 | 2_1mlx.") | |
277 | (exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
278 | (exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
279 | (exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.") | |
280 | (exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.") | |
281 | (exclusion_set "2_1mf.b" "2_1mlx.") | |
282 | ||
283 | ;; Slot 6 | |
284 | (exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
285 | 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
286 | (exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
287 | 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
288 | (exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\ | |
289 | 2_1mfb., 2_1mlx.") | |
290 | (exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\ | |
291 | 2_1mlx.") | |
292 | (exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
293 | (exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
294 | (exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.") | |
295 | (exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.") | |
296 | (exclusion_set "2_1mfb." "2_1mlx.") | |
297 | ||
298 | (final_presence_set "2_0mi.i" "2_0m.ii") | |
299 | (final_presence_set "2_0mii." "2_0mi.i") | |
300 | (final_presence_set "2_1mi.i" "2_1m.ii") | |
301 | (final_presence_set "2_1mii." "2_1mi.i") | |
302 | ||
303 | (final_presence_set "2_0mm.i" "2_0m.mi") | |
304 | (final_presence_set "2_0mmi." "2_0mm.i") | |
305 | (final_presence_set "2_1mm.i" "2_1m.mi") | |
306 | (final_presence_set "2_1mmi." "2_1mm.i") | |
307 | ||
308 | (final_presence_set "2_0mf.i" "2_0m.fi") | |
309 | (final_presence_set "2_0mfi." "2_0mf.i") | |
310 | (final_presence_set "2_1mf.i" "2_1m.fi") | |
311 | (final_presence_set "2_1mfi." "2_1mf.i") | |
312 | ||
313 | (final_presence_set "2_0mm.f" "2_0m.mf") | |
314 | (final_presence_set "2_0mmf." "2_0mm.f") | |
315 | (final_presence_set "2_1mm.f" "2_1m.mf") | |
316 | (final_presence_set "2_1mmf." "2_1mm.f") | |
317 | ||
318 | (final_presence_set "2_0bb.b" "2_0b.bb") | |
319 | (final_presence_set "2_0bbb." "2_0bb.b") | |
320 | (final_presence_set "2_1bb.b" "2_1b.bb") | |
321 | (final_presence_set "2_1bbb." "2_1bb.b") | |
322 | ||
323 | (final_presence_set "2_0mb.b" "2_0m.bb") | |
324 | (final_presence_set "2_0mbb." "2_0mb.b") | |
325 | (final_presence_set "2_1mb.b" "2_1m.bb") | |
326 | (final_presence_set "2_1mbb." "2_1mb.b") | |
327 | ||
328 | (final_presence_set "2_0mi.b" "2_0m.ib") | |
329 | (final_presence_set "2_0mib." "2_0mi.b") | |
330 | (final_presence_set "2_1mi.b" "2_1m.ib") | |
331 | (final_presence_set "2_1mib." "2_1mi.b") | |
332 | ||
333 | (final_presence_set "2_0mm.b" "2_0m.mb") | |
334 | (final_presence_set "2_0mmb." "2_0mm.b") | |
335 | (final_presence_set "2_1mm.b" "2_1m.mb") | |
336 | (final_presence_set "2_1mmb." "2_1mm.b") | |
337 | ||
338 | (final_presence_set "2_0mf.b" "2_0m.fb") | |
339 | (final_presence_set "2_0mfb." "2_0mf.b") | |
340 | (final_presence_set "2_1mf.b" "2_1m.fb") | |
341 | (final_presence_set "2_1mfb." "2_1mf.b") | |
342 | ||
343 | (final_presence_set "2_0mlx." "2_0m.lx") | |
344 | (final_presence_set "2_1mlx." "2_1m.lx") | |
345 | ||
346 | ;; The following reflects the dual issue bundle types table. | |
347 | ;; We could place all possible combinations here because impossible | |
348 | ;; combinations would go away by the subsequent constrains. | |
349 | (final_presence_set | |
350 | "2_1m.lx" | |
351 | "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") | |
352 | (final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.") | |
353 | (final_presence_set | |
354 | "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb" | |
355 | "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") | |
356 | ||
357 | ;; Ports/units (nb means nop.b insn issued into given port): | |
358 | (define_cpu_unit | |
359 | "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\ | |
360 | 2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two") | |
361 | ||
362 | (exclusion_set "2_ub0" "2_unb0") | |
363 | (exclusion_set "2_ub1" "2_unb1") | |
364 | (exclusion_set "2_ub2" "2_unb2") | |
365 | ||
366 | ;; The following rules are used to decrease number of alternatives. | |
367 | ;; They are consequences of Itanium2 microarchitecture. They also | |
368 | ;; describe the following rules mentioned in Itanium2 | |
369 | ;; microarchitecture: rules mentioned in Itanium2 microarchitecture: | |
370 | ;; o "BBB/MBB: Always splits issue after either of these bundles". | |
371 | ;; o "MIB BBB: Split issue after the first bundle in this pair". | |
372 | (exclusion_set | |
373 | "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb." | |
374 | "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\ | |
375 | 2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx") | |
376 | (exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb") | |
377 | ||
378 | ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the | |
379 | ;;; B-slot contains a nop.b or a brp instruction". | |
380 | ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or | |
381 | ;;; nop.b, otherwise it disperses to B2". | |
382 | (final_absence_set | |
383 | "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
384 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" | |
385 | "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2") | |
386 | ||
387 | ;; This is necessary to start new processor cycle when we meet stop bit. | |
388 | (define_cpu_unit "2_stop" "two") | |
389 | (final_absence_set | |
390 | "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ | |
391 | 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ | |
392 | 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ | |
393 | 2_0m.lx,2_0mlx., \ | |
394 | 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ | |
395 | 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ | |
396 | 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ | |
397 | 2_1m.lx,2_1mlx." | |
398 | "2_stop") | |
399 | ||
400 | ;; The issue logic can reorder M slot insns between different subtypes | |
33f88b1c | 401 | ;; but cannot reorder insn within the same subtypes. The following |
58ada791 | 402 | ;; constraint is enough to describe this. |
403 | (final_presence_set "2_um1" "2_um0") | |
404 | (final_presence_set "2_um3" "2_um2") | |
405 | ||
406 | ;; The insn in the 1st I slot of the two bundle issue group will issue | |
407 | ;; to I0. The second I slot insn will issue to I1. | |
408 | (final_presence_set "2_ui1" "2_ui0") | |
409 | ||
410 | ;; For exceptions of I insns: | |
411 | (define_cpu_unit "2_only_ui0" "two") | |
412 | (final_absence_set "2_only_ui0" "2_ui1") | |
413 | ||
414 | ;; Insns | |
415 | ||
416 | (define_reservation "2_M0" | |
417 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
418 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
419 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
420 | +(2_um0|2_um1|2_um2|2_um3)") | |
421 | ||
422 | (define_reservation "2_M1" | |
423 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
424 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
425 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
426 | +(2_um0|2_um1|2_um2|2_um3)") | |
427 | ||
428 | (define_reservation "2_M" "2_M0|2_M1") | |
429 | ||
430 | (define_reservation "2_M0_only_um0" | |
431 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
432 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
433 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
434 | +2_um0") | |
435 | ||
436 | (define_reservation "2_M1_only_um0" | |
437 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
438 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
439 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
440 | +2_um0") | |
441 | ||
442 | (define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0") | |
443 | ||
444 | (define_reservation "2_M0_only_um2" | |
445 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
446 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
447 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
448 | +2_um2") | |
449 | ||
450 | (define_reservation "2_M1_only_um2" | |
451 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
452 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
453 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
454 | +2_um2") | |
455 | ||
456 | (define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2") | |
457 | ||
458 | (define_reservation "2_M0_only_um23" | |
459 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
460 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
461 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
462 | +(2_um2|2_um3)") | |
463 | ||
464 | (define_reservation "2_M1_only_um23" | |
465 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
466 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
467 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
468 | +(2_um2|2_um3)") | |
469 | ||
470 | (define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23") | |
471 | ||
472 | (define_reservation "2_M0_only_um01" | |
473 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
474 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
475 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
476 | +(2_um0|2_um1)") | |
477 | ||
478 | (define_reservation "2_M1_only_um01" | |
479 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
480 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
481 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
482 | +(2_um0|2_um1)") | |
483 | ||
484 | (define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01") | |
485 | ||
486 | ;; I instruction is dispersed to the lowest numbered I unit | |
7bd28bba | 487 | ;; not already in use. Remember about possible splitting. |
58ada791 | 488 | (define_reservation "2_I0" |
489 | "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\ | |
490 | |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\ | |
491 | |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)") | |
492 | ||
493 | (define_reservation "2_I1" | |
494 | "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\ | |
495 | |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\ | |
496 | |2_0mf.i+2_uf0+2_0mfi.+2_ui0\ | |
497 | |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\ | |
498 | |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\ | |
499 | |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\ | |
500 | |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)") | |
501 | ||
502 | (define_reservation "2_I" "2_I0|2_I1") | |
503 | ||
504 | ;; "An F slot in the 1st bundle disperses to F0". | |
505 | ;; "An F slot in the 2st bundle disperses to F1". | |
506 | (define_reservation "2_F0" | |
507 | "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\ | |
508 | |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1") | |
509 | ||
510 | (define_reservation "2_F1" | |
511 | "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\ | |
512 | +(2_um0|2_um1|2_um2|2_um3)+2_uf0\ | |
513 | |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\ | |
514 | +(2_um0|2_um1|2_um2|2_um3)+2_uf1") | |
515 | ||
516 | (define_reservation "2_F2" | |
517 | "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\ | |
518 | +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\ | |
519 | |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\ | |
520 | |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\ | |
521 | |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\ | |
522 | +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1") | |
523 | ||
524 | (define_reservation "2_F" "2_F0|2_F1|2_F2") | |
525 | ||
526 | ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B | |
3c364971 | 527 | ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the |
58ada791 | 528 | ;;; 2nd position it is dispersed to B2". |
529 | (define_reservation "2_NB" | |
530 | "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\ | |
531 | |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\ | |
532 | |2_0mmb.+2_unb0|2_0mfb.+2_unb0\ | |
533 | |2_1b.bb+2_unb0|2_1bb.b+2_unb1 | |
534 | |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\ | |
535 | |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0") | |
536 | ||
537 | (define_reservation "2_B0" | |
538 | "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\ | |
539 | |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\ | |
540 | |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\ | |
541 | |2_1bbb.+2_ub2|2_1mb.b+2_ub1\ | |
542 | |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2") | |
543 | ||
544 | (define_reservation "2_B1" | |
545 | "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\ | |
546 | |2_0mi.b+2_ui0+2_0mib.+2_ub2\ | |
547 | |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\ | |
548 | |2_0mf.b+2_uf0+2_0mfb.+2_ub2\ | |
549 | |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\ | |
550 | +2_1b.bb+2_ub0\ | |
551 | |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\ | |
552 | |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\ | |
553 | |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\ | |
554 | |2_1mf.b+2_uf1+2_1mfb.+2_ub2") | |
555 | ||
556 | (define_reservation "2_B" "2_B0|2_B1") | |
557 | ||
558 | ;; MLX bunlde uses ports equivalent to MFI bundles. | |
559 | ||
560 | ;; For the MLI template, the I slot insn is always assigned to port I0 | |
561 | ;; if it is in the first bundle or it is assigned to port I1 if it is in | |
562 | ;; the second bundle. | |
563 | (define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1") | |
564 | ||
565 | (define_reservation "2_L1" | |
566 | "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\ | |
567 | |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") | |
568 | ||
569 | (define_reservation "2_L2" | |
570 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
571 | |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0) | |
572 | +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") | |
573 | ||
574 | (define_reservation "2_L" "2_L0|2_L1|2_L2") | |
575 | ||
576 | ;; Should we describe that A insn in I slot can be issued into M | |
577 | ;; ports? I think it is not necessary because of multipass | |
578 | ;; scheduling. For example, the multipass scheduling could use | |
579 | ;; MMI-MMI instead of MII-MII where the two last I slots contain A | |
580 | ;; insns (even if the case is complicated by use-def conflicts). | |
581 | ;; | |
582 | ;; In any case we could describe it as | |
583 | ;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two") | |
584 | ;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" | |
585 | ;; "2_ui1") | |
586 | ;; (define_reservation "b_A" | |
587 | ;; "b_M|b_I\ | |
588 | ;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\ | |
589 | ;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)") | |
590 | ||
591 | (define_reservation "2_A" "2_M|2_I") | |
592 | ||
593 | ;; We assume that there is no insn issued on the same cycle as the | |
594 | ;; unknown insn. | |
595 | (define_cpu_unit "2_empty" "two") | |
596 | (exclusion_set "2_empty" | |
597 | "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\ | |
598 | 2_0m.lx") | |
599 | ||
600 | (define_cpu_unit | |
601 | "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs" | |
602 | "two") | |
603 | (define_cpu_unit | |
604 | "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" | |
605 | "two") | |
606 | ||
607 | (define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\ | |
608 | 2_b_cont, 2_bb_cont" "two") | |
609 | ||
610 | ;; For stop in the middle of the bundles. | |
611 | (define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two") | |
612 | (define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two") | |
613 | ||
614 | (final_presence_set "2_0m_bs" | |
615 | "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\ | |
616 | 2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx") | |
617 | (final_presence_set "2_1m_bs" | |
618 | "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\ | |
619 | 2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx") | |
620 | (final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i") | |
621 | (final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i") | |
622 | (final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b") | |
623 | (final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b") | |
624 | (final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b") | |
625 | (final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b") | |
626 | (final_presence_set "2_0b_bs" "2_0b.bb") | |
627 | (final_presence_set "2_1b_bs" "2_1b.bb") | |
628 | (final_presence_set "2_0bb_bs" "2_0bb.b") | |
629 | (final_presence_set "2_1bb_bs" "2_1bb.b") | |
630 | (final_presence_set "2_0mb_bs" "2_0mb.b") | |
631 | (final_presence_set "2_1mb_bs" "2_1mb.b") | |
632 | ||
633 | (exclusion_set "2_0m_bs" | |
634 | "2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\ | |
635 | 2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop") | |
636 | (exclusion_set "2_1m_bs" | |
637 | "2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\ | |
638 | 2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop") | |
639 | (exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop") | |
640 | (exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop") | |
641 | (exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.") | |
642 | (exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.") | |
643 | (exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.") | |
644 | (exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.") | |
645 | (exclusion_set "2_0b_bs" "2_0bb.b") | |
646 | (exclusion_set "2_1b_bs" "2_1bb.b") | |
647 | (exclusion_set "2_0bb_bs" "2_0bbb.") | |
648 | (exclusion_set "2_1bb_bs" "2_1bbb.") | |
649 | (exclusion_set "2_0mb_bs" "2_0mbb.") | |
650 | (exclusion_set "2_1mb_bs" "2_1mbb.") | |
651 | ||
652 | (exclusion_set | |
653 | "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs, | |
654 | 2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" | |
655 | "2_stop") | |
656 | ||
657 | (final_presence_set | |
658 | "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ | |
659 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." | |
660 | "2_m_cont") | |
661 | (final_presence_set "2_0mii., 2_0mib." "2_mi_cont") | |
662 | (final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont") | |
663 | (final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont") | |
664 | (final_presence_set "2_0bb.b" "2_b_cont") | |
665 | (final_presence_set "2_0bbb." "2_bb_cont") | |
666 | (final_presence_set "2_0mbb." "2_mb_cont") | |
667 | ||
668 | (exclusion_set | |
669 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
670 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" | |
671 | "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\ | |
672 | 2_mb_cont, 2_b_cont, 2_bb_cont") | |
673 | ||
674 | (exclusion_set "2_empty" | |
675 | "2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\ | |
676 | 2_mb_cont,2_b_cont,2_bb_cont") | |
677 | ||
678 | ;; For m;mi bundle | |
679 | (final_presence_set "2_m0_stop" "2_0m.mi") | |
680 | (final_presence_set "2_0mm.i" "2_0mmi_cont") | |
681 | (exclusion_set "2_0mmi_cont" | |
682 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
683 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
684 | (exclusion_set "2_m0_stop" "2_0mm.i") | |
685 | (final_presence_set "2_m1_stop" "2_1m.mi") | |
686 | (exclusion_set "2_m1_stop" "2_1mm.i") | |
687 | (final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop") | |
688 | ||
689 | ;; For mi;i bundle | |
690 | (final_presence_set "2_mi0_stop" "2_0mi.i") | |
691 | (final_presence_set "2_0mii." "2_0mii_cont") | |
692 | (exclusion_set "2_0mii_cont" | |
693 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
694 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
695 | (exclusion_set "2_mi0_stop" "2_0mii.") | |
696 | (final_presence_set "2_mi1_stop" "2_1mi.i") | |
697 | (exclusion_set "2_mi1_stop" "2_1mii.") | |
698 | (final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop") | |
699 | ||
700 | (final_absence_set | |
701 | "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ | |
702 | 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ | |
703 | 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ | |
704 | 2_0m.lx,2_0mlx., \ | |
705 | 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ | |
706 | 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ | |
707 | 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ | |
708 | 2_1m.lx,2_1mlx." | |
709 | "2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop") | |
710 | ||
711 | (define_insn_reservation "2_stop_bit" 0 | |
712 | (and (and (eq_attr "cpu" "itanium2") | |
713 | (eq_attr "itanium_class" "stop_bit")) | |
f4d8a59e | 714 | (not (match_test "bundling_p"))) |
58ada791 | 715 | "2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop") |
716 | ||
717 | (define_insn_reservation "2_br" 0 | |
718 | (and (and (eq_attr "cpu" "itanium2") | |
719 | (eq_attr "itanium_class" "br")) | |
f4d8a59e | 720 | (not (match_test "bundling_p"))) "2_B") |
58ada791 | 721 | (define_insn_reservation "2_scall" 0 |
722 | (and (and (eq_attr "cpu" "itanium2") | |
723 | (eq_attr "itanium_class" "scall")) | |
f4d8a59e | 724 | (not (match_test "bundling_p"))) "2_B") |
58ada791 | 725 | (define_insn_reservation "2_fcmp" 2 |
726 | (and (and (eq_attr "cpu" "itanium2") | |
727 | (eq_attr "itanium_class" "fcmp")) | |
f4d8a59e | 728 | (not (match_test "bundling_p"))) "2_F") |
58ada791 | 729 | (define_insn_reservation "2_fcvtfx" 4 |
730 | (and (and (eq_attr "cpu" "itanium2") | |
731 | (eq_attr "itanium_class" "fcvtfx")) | |
f4d8a59e | 732 | (not (match_test "bundling_p"))) "2_F") |
58ada791 | 733 | (define_insn_reservation "2_fld" 6 |
ea13ae4c | 734 | (and (and (and (and (eq_attr "cpu" "itanium2") |
735 | (eq_attr "itanium_class" "fld")) | |
736 | (eq_attr "data_speculative" "no")) | |
737 | (eq_attr "check_load" "no")) | |
f4d8a59e | 738 | (not (match_test "bundling_p"))) |
ea13ae4c | 739 | "2_M") |
740 | (define_insn_reservation "2_flda" 6 | |
741 | (and (and (and (eq_attr "cpu" "itanium2") | |
742 | (eq_attr "itanium_class" "fld")) | |
743 | (eq_attr "data_speculative" "yes")) | |
f4d8a59e | 744 | (not (match_test "bundling_p"))) |
ea13ae4c | 745 | "2_M_only_um01") |
746 | (define_insn_reservation "2_fldc" 0 | |
747 | (and (and (and (eq_attr "cpu" "itanium2") | |
748 | (eq_attr "itanium_class" "fld")) | |
749 | (eq_attr "check_load" "yes")) | |
f4d8a59e | 750 | (not (match_test "bundling_p"))) |
ea13ae4c | 751 | "2_M_only_um01") |
752 | ||
4d053aca | 753 | (define_insn_reservation "2_fldp" 6 |
ea13ae4c | 754 | (and (and (and (eq_attr "cpu" "itanium2") |
755 | (eq_attr "itanium_class" "fldp")) | |
756 | (eq_attr "check_load" "no")) | |
f4d8a59e | 757 | (not (match_test "bundling_p"))) |
ea13ae4c | 758 | "2_M_only_um01") |
759 | (define_insn_reservation "2_fldpc" 0 | |
760 | (and (and (and (eq_attr "cpu" "itanium2") | |
761 | (eq_attr "itanium_class" "fldp")) | |
762 | (eq_attr "check_load" "yes")) | |
f4d8a59e | 763 | (not (match_test "bundling_p"))) |
4d053aca | 764 | "2_M_only_um01") |
ea13ae4c | 765 | |
58ada791 | 766 | (define_insn_reservation "2_fmac" 4 |
767 | (and (and (eq_attr "cpu" "itanium2") | |
768 | (eq_attr "itanium_class" "fmac")) | |
f4d8a59e | 769 | (not (match_test "bundling_p"))) "2_F") |
58ada791 | 770 | (define_insn_reservation "2_fmisc" 4 |
771 | (and (and (eq_attr "cpu" "itanium2") | |
772 | (eq_attr "itanium_class" "fmisc")) | |
f4d8a59e | 773 | (not (match_test "bundling_p"))) "2_F") |
58ada791 | 774 | |
775 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
776 | ;; Latency time ??? | |
777 | (define_insn_reservation "2_frar_i" 13 | |
778 | (and (and (eq_attr "cpu" "itanium2") | |
779 | (eq_attr "itanium_class" "frar_i")) | |
f4d8a59e | 780 | (not (match_test "bundling_p"))) |
58ada791 | 781 | "2_I+2_only_ui0") |
782 | ;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: | |
783 | ;; Latency time ??? | |
784 | (define_insn_reservation "2_frar_m" 6 | |
785 | (and (and (eq_attr "cpu" "itanium2") | |
786 | (eq_attr "itanium_class" "frar_m")) | |
f4d8a59e | 787 | (not (match_test "bundling_p"))) |
58ada791 | 788 | "2_M_only_um2") |
789 | (define_insn_reservation "2_frbr" 2 | |
790 | (and (and (eq_attr "cpu" "itanium2") | |
791 | (eq_attr "itanium_class" "frbr")) | |
f4d8a59e | 792 | (not (match_test "bundling_p"))) |
58ada791 | 793 | "2_I+2_only_ui0") |
794 | (define_insn_reservation "2_frfr" 5 | |
795 | (and (and (eq_attr "cpu" "itanium2") | |
796 | (eq_attr "itanium_class" "frfr")) | |
f4d8a59e | 797 | (not (match_test "bundling_p"))) |
58ada791 | 798 | "2_M_only_um2") |
799 | (define_insn_reservation "2_frpr" 2 | |
800 | (and (and (eq_attr "cpu" "itanium2") | |
801 | (eq_attr "itanium_class" "frpr")) | |
f4d8a59e | 802 | (not (match_test "bundling_p"))) |
58ada791 | 803 | "2_I+2_only_ui0") |
804 | ||
805 | (define_insn_reservation "2_ialu" 1 | |
806 | (and (and (eq_attr "cpu" "itanium2") | |
807 | (eq_attr "itanium_class" "ialu")) | |
f4d8a59e | 808 | (not (match_test "bundling_p"))) |
58ada791 | 809 | "2_A") |
810 | (define_insn_reservation "2_icmp" 1 | |
811 | (and (and (eq_attr "cpu" "itanium2") | |
812 | (eq_attr "itanium_class" "icmp")) | |
f4d8a59e | 813 | (not (match_test "bundling_p"))) "2_A") |
58ada791 | 814 | (define_insn_reservation "2_ilog" 1 |
815 | (and (and (eq_attr "cpu" "itanium2") | |
816 | (eq_attr "itanium_class" "ilog")) | |
f4d8a59e | 817 | (not (match_test "bundling_p"))) "2_A") |
a5c5f9d3 | 818 | (define_insn_reservation "2_mmalua" 2 |
819 | (and (and (eq_attr "cpu" "itanium2") | |
820 | (eq_attr "itanium_class" "mmalua")) | |
f4d8a59e | 821 | (not (match_test "bundling_p"))) "2_A") |
58ada791 | 822 | ;; Latency time ??? |
823 | (define_insn_reservation "2_ishf" 1 | |
824 | (and (and (eq_attr "cpu" "itanium2") | |
825 | (eq_attr "itanium_class" "ishf")) | |
f4d8a59e | 826 | (not (match_test "bundling_p"))) |
58ada791 | 827 | "2_I+2_only_ui0") |
ea13ae4c | 828 | |
58ada791 | 829 | (define_insn_reservation "2_ld" 1 |
ea13ae4c | 830 | (and (and (and (eq_attr "cpu" "itanium2") |
831 | (eq_attr "itanium_class" "ld")) | |
832 | (eq_attr "check_load" "no")) | |
f4d8a59e | 833 | (not (match_test "bundling_p"))) |
ea13ae4c | 834 | "2_M_only_um01") |
835 | (define_insn_reservation "2_ldc" 0 | |
58ada791 | 836 | (and (and (eq_attr "cpu" "itanium2") |
ea13ae4c | 837 | (eq_attr "check_load" "yes")) |
f4d8a59e | 838 | (not (match_test "bundling_p"))) |
58ada791 | 839 | "2_M_only_um01") |
ea13ae4c | 840 | |
58ada791 | 841 | (define_insn_reservation "2_long_i" 1 |
842 | (and (and (eq_attr "cpu" "itanium2") | |
843 | (eq_attr "itanium_class" "long_i")) | |
f4d8a59e | 844 | (not (match_test "bundling_p"))) "2_L") |
58ada791 | 845 | |
846 | (define_insn_reservation "2_mmmul" 2 | |
847 | (and (and (eq_attr "cpu" "itanium2") | |
848 | (eq_attr "itanium_class" "mmmul")) | |
f4d8a59e | 849 | (not (match_test "bundling_p"))) |
58ada791 | 850 | "2_I+2_only_ui0") |
851 | ;; Latency time ??? | |
852 | (define_insn_reservation "2_mmshf" 2 | |
853 | (and (and (eq_attr "cpu" "itanium2") | |
854 | (eq_attr "itanium_class" "mmshf")) | |
f4d8a59e | 855 | (not (match_test "bundling_p"))) "2_I") |
58ada791 | 856 | ;; Latency time ??? |
857 | (define_insn_reservation "2_mmshfi" 1 | |
858 | (and (and (eq_attr "cpu" "itanium2") | |
859 | (eq_attr "itanium_class" "mmshfi")) | |
f4d8a59e | 860 | (not (match_test "bundling_p"))) "2_I") |
58ada791 | 861 | |
862 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
863 | ;; is the 1st syllable of the bundle after stop bit. | |
864 | (define_insn_reservation "2_rse_m" 0 | |
865 | (and (and (eq_attr "cpu" "itanium2") | |
866 | (eq_attr "itanium_class" "rse_m")) | |
f4d8a59e | 867 | (not (match_test "bundling_p"))) |
58ada791 | 868 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\ |
869 | |2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0") | |
870 | (define_insn_reservation "2_sem" 0 | |
871 | (and (and (eq_attr "cpu" "itanium2") | |
872 | (eq_attr "itanium_class" "sem")) | |
f4d8a59e | 873 | (not (match_test "bundling_p"))) |
58ada791 | 874 | "2_M_only_um23") |
875 | ||
876 | (define_insn_reservation "2_stf" 1 | |
877 | (and (and (eq_attr "cpu" "itanium2") | |
878 | (eq_attr "itanium_class" "stf")) | |
f4d8a59e | 879 | (not (match_test "bundling_p"))) |
58ada791 | 880 | "2_M_only_um23") |
881 | (define_insn_reservation "2_st" 1 | |
882 | (and (and (eq_attr "cpu" "itanium2") | |
883 | (eq_attr "itanium_class" "st")) | |
f4d8a59e | 884 | (not (match_test "bundling_p"))) |
58ada791 | 885 | "2_M_only_um23") |
886 | (define_insn_reservation "2_syst_m0" 0 | |
887 | (and (and (eq_attr "cpu" "itanium2") | |
888 | (eq_attr "itanium_class" "syst_m0")) | |
f4d8a59e | 889 | (not (match_test "bundling_p"))) |
58ada791 | 890 | "2_M_only_um2") |
891 | (define_insn_reservation "2_syst_m" 0 | |
892 | (and (and (eq_attr "cpu" "itanium2") | |
893 | (eq_attr "itanium_class" "syst_m")) | |
f4d8a59e | 894 | (not (match_test "bundling_p"))) |
58ada791 | 895 | "2_M_only_um0") |
896 | ;; Reservation??? | |
897 | (define_insn_reservation "2_tbit" 1 | |
898 | (and (and (eq_attr "cpu" "itanium2") | |
899 | (eq_attr "itanium_class" "tbit")) | |
f4d8a59e | 900 | (not (match_test "bundling_p"))) |
58ada791 | 901 | "2_I+2_only_ui0") |
902 | ||
903 | ;; There is only ony insn `mov ar.pfs =' for toar_i: | |
904 | (define_insn_reservation "2_toar_i" 0 | |
905 | (and (and (eq_attr "cpu" "itanium2") | |
906 | (eq_attr "itanium_class" "toar_i")) | |
f4d8a59e | 907 | (not (match_test "bundling_p"))) |
58ada791 | 908 | "2_I+2_only_ui0") |
909 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
910 | ;; Latency time ??? | |
911 | (define_insn_reservation "2_toar_m" 5 | |
912 | (and (and (eq_attr "cpu" "itanium2") | |
913 | (eq_attr "itanium_class" "toar_m")) | |
f4d8a59e | 914 | (not (match_test "bundling_p"))) |
58ada791 | 915 | "2_M_only_um2") |
916 | ;; Latency time ??? | |
917 | (define_insn_reservation "2_tobr" 1 | |
918 | (and (and (eq_attr "cpu" "itanium2") | |
919 | (eq_attr "itanium_class" "tobr")) | |
f4d8a59e | 920 | (not (match_test "bundling_p"))) |
58ada791 | 921 | "2_I+2_only_ui0") |
922 | (define_insn_reservation "2_tofr" 5 | |
923 | (and (and (eq_attr "cpu" "itanium2") | |
924 | (eq_attr "itanium_class" "tofr")) | |
f4d8a59e | 925 | (not (match_test "bundling_p"))) |
58ada791 | 926 | "2_M_only_um23") |
927 | ;; Latency time ??? | |
928 | (define_insn_reservation "2_topr" 1 | |
929 | (and (and (eq_attr "cpu" "itanium2") | |
930 | (eq_attr "itanium_class" "topr")) | |
f4d8a59e | 931 | (not (match_test "bundling_p"))) |
58ada791 | 932 | "2_I+2_only_ui0") |
933 | ||
934 | (define_insn_reservation "2_xmpy" 4 | |
935 | (and (and (eq_attr "cpu" "itanium2") | |
936 | (eq_attr "itanium_class" "xmpy")) | |
f4d8a59e | 937 | (not (match_test "bundling_p"))) "2_F") |
58ada791 | 938 | ;; Latency time ??? |
939 | (define_insn_reservation "2_xtd" 1 | |
940 | (and (and (eq_attr "cpu" "itanium2") | |
941 | (eq_attr "itanium_class" "xtd")) | |
f4d8a59e | 942 | (not (match_test "bundling_p"))) "2_I") |
58ada791 | 943 | |
ea13ae4c | 944 | (define_insn_reservation "2_chk_s_i" 0 |
58ada791 | 945 | (and (and (eq_attr "cpu" "itanium2") |
ea13ae4c | 946 | (eq_attr "itanium_class" "chk_s_i")) |
f4d8a59e | 947 | (not (match_test "bundling_p"))) |
58ada791 | 948 | "2_I|2_M_only_um23") |
ea13ae4c | 949 | (define_insn_reservation "2_chk_s_f" 0 |
950 | (and (and (eq_attr "cpu" "itanium2") | |
951 | (eq_attr "itanium_class" "chk_s_f")) | |
f4d8a59e | 952 | (not (match_test "bundling_p"))) |
ea13ae4c | 953 | "2_M_only_um23") |
954 | (define_insn_reservation "2_chk_a" 0 | |
955 | (and (and (eq_attr "cpu" "itanium2") | |
956 | (eq_attr "itanium_class" "chk_a")) | |
f4d8a59e | 957 | (not (match_test "bundling_p"))) |
ea13ae4c | 958 | "2_M_only_um01") |
959 | ||
58ada791 | 960 | (define_insn_reservation "2_lfetch" 0 |
961 | (and (and (eq_attr "cpu" "itanium2") | |
962 | (eq_attr "itanium_class" "lfetch")) | |
f4d8a59e | 963 | (not (match_test "bundling_p"))) |
58ada791 | 964 | "2_M_only_um01") |
965 | ||
966 | (define_insn_reservation "2_nop_m" 0 | |
967 | (and (and (eq_attr "cpu" "itanium2") | |
968 | (eq_attr "itanium_class" "nop_m")) | |
f4d8a59e | 969 | (not (match_test "bundling_p"))) "2_M0") |
58ada791 | 970 | (define_insn_reservation "2_nop_b" 0 |
971 | (and (and (eq_attr "cpu" "itanium2") | |
972 | (eq_attr "itanium_class" "nop_b")) | |
f4d8a59e | 973 | (not (match_test "bundling_p"))) "2_NB") |
58ada791 | 974 | (define_insn_reservation "2_nop_i" 0 |
975 | (and (and (eq_attr "cpu" "itanium2") | |
976 | (eq_attr "itanium_class" "nop_i")) | |
f4d8a59e | 977 | (not (match_test "bundling_p"))) "2_I0") |
58ada791 | 978 | (define_insn_reservation "2_nop_f" 0 |
979 | (and (and (eq_attr "cpu" "itanium2") | |
980 | (eq_attr "itanium_class" "nop_f")) | |
f4d8a59e | 981 | (not (match_test "bundling_p"))) "2_F0") |
58ada791 | 982 | (define_insn_reservation "2_nop_x" 0 |
983 | (and (and (eq_attr "cpu" "itanium2") | |
984 | (eq_attr "itanium_class" "nop_x")) | |
f4d8a59e | 985 | (not (match_test "bundling_p"))) "2_L0") |
58ada791 | 986 | |
987 | (define_insn_reservation "2_unknown" 1 | |
988 | (and (and (eq_attr "cpu" "itanium2") | |
989 | (eq_attr "itanium_class" "unknown")) | |
f4d8a59e | 990 | (not (match_test "bundling_p"))) "2_empty") |
58ada791 | 991 | |
992 | (define_insn_reservation "2_nop" 0 | |
993 | (and (and (eq_attr "cpu" "itanium2") | |
994 | (eq_attr "itanium_class" "nop")) | |
f4d8a59e | 995 | (not (match_test "bundling_p"))) |
58ada791 | 996 | "2_M0|2_NB|2_I0|2_F0") |
997 | ||
998 | (define_insn_reservation "2_ignore" 0 | |
999 | (and (and (eq_attr "cpu" "itanium2") | |
1000 | (eq_attr "itanium_class" "ignore")) | |
f4d8a59e | 1001 | (not (match_test "bundling_p"))) "nothing") |
58ada791 | 1002 | |
1003 | (define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two") | |
1004 | (define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two") | |
1005 | (define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two") | |
1006 | ||
1007 | (final_presence_set "2_m_cont_only" "2_m_cont") | |
1008 | (exclusion_set "2_m_cont_only" | |
1009 | "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ | |
1010 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
1011 | ||
1012 | (final_presence_set "2_b_cont_only" "2_b_cont") | |
1013 | (exclusion_set "2_b_cont_only" "2_0bb.b") | |
1014 | ||
1015 | (final_presence_set "2_mi_cont_only" "2_mi_cont") | |
1016 | (exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.") | |
1017 | ||
1018 | (final_presence_set "2_mm_cont_only" "2_mm_cont") | |
1019 | (exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.") | |
1020 | ||
1021 | (final_presence_set "2_mf_cont_only" "2_mf_cont") | |
1022 | (exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.") | |
1023 | ||
1024 | (final_presence_set "2_mb_cont_only" "2_mb_cont") | |
1025 | (exclusion_set "2_mb_cont_only" "2_0mbb.") | |
1026 | ||
1027 | (final_presence_set "2_bb_cont_only" "2_bb_cont") | |
1028 | (exclusion_set "2_bb_cont_only" "2_0bbb.") | |
1029 | ||
1030 | (define_insn_reservation "2_pre_cycle" 0 | |
1031 | (and (and (eq_attr "cpu" "itanium2") | |
1032 | (eq_attr "itanium_class" "pre_cycle")) | |
f4d8a59e | 1033 | (not (match_test "bundling_p"))) |
58ada791 | 1034 | "nothing") |
1035 | ||
1036 | ;;(define_insn_reservation "2_pre_cycle" 0 | |
1037 | ;; (and (and (eq_attr "cpu" "itanium2") | |
1038 | ;; (eq_attr "itanium_class" "pre_cycle")) | |
f4d8a59e | 1039 | ;; (not (match_test "bundling_p"))) |
58ada791 | 1040 | ;; "(2_0m_bs, 2_m_cont) \ |
1041 | ;; | (2_0mi_bs, (2_mi_cont|nothing)) \ | |
1042 | ;; | (2_0mm_bs, 2_mm_cont) \ | |
1043 | ;; | (2_0mf_bs, (2_mf_cont|nothing)) \ | |
1044 | ;; | (2_0b_bs, (2_b_cont|nothing)) \ | |
1045 | ;; | (2_0bb_bs, (2_bb_cont|nothing)) \ | |
1046 | ;; | (2_0mb_bs, (2_mb_cont|nothing)) \ | |
1047 | ;; | (2_1m_bs, 2_m_cont) \ | |
1048 | ;; | (2_1mi_bs, (2_mi_cont|nothing)) \ | |
1049 | ;; | (2_1mm_bs, 2_mm_cont) \ | |
1050 | ;; | (2_1mf_bs, (2_mf_cont|nothing)) \ | |
1051 | ;; | (2_1b_bs, (2_b_cont|nothing)) \ | |
1052 | ;; | (2_1bb_bs, (2_bb_cont|nothing)) \ | |
1053 | ;; | (2_1mb_bs, (2_mb_cont|nothing)) \ | |
1054 | ;; | (2_m_cont_only, (2_m_cont|nothing)) \ | |
1055 | ;; | (2_b_cont_only, (2_b_cont|nothing)) \ | |
1056 | ;; | (2_mi_cont_only, (2_mi_cont|nothing)) \ | |
1057 | ;; | (2_mm_cont_only, (2_mm_cont|nothing)) \ | |
1058 | ;; | (2_mf_cont_only, (2_mf_cont|nothing)) \ | |
1059 | ;; | (2_mb_cont_only, (2_mb_cont|nothing)) \ | |
1060 | ;; | (2_bb_cont_only, (2_bb_cont|nothing)) \ | |
1061 | ;; | (2_m_stop, (2_0mmi_cont|nothing)) \ | |
1062 | ;; | (2_mi_stop, (2_0mii_cont|nothing))") | |
1063 | ||
1064 | ;; Bypasses: | |
1065 | ||
1066 | (define_bypass 1 "2_fcmp" "2_br,2_scall") | |
1067 | (define_bypass 0 "2_icmp" "2_br,2_scall") | |
1068 | (define_bypass 0 "2_tbit" "2_br,2_scall") | |
1069 | (define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") | |
1070 | (define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") | |
ea13ae4c | 1071 | (define_bypass 2 "2_ld,2_ldc" "2_mmalua,2_mmmul,2_mmshf") |
a5c5f9d3 | 1072 | (define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf") |
1073 | (define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf") | |
ea13ae4c | 1074 | (define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc") |
58ada791 | 1075 | (define_bypass 6 "2_tofr" "2_frfr,2_stf") |
58ada791 | 1076 | |
1077 | ;; We don't use here fcmp because scall may be predicated. | |
ea13ae4c | 1078 | (define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ |
1079 | 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\ | |
cf7898a6 | 1080 | 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tobr,2_tofr,\ |
a5c5f9d3 | 1081 | 2_xmpy,2_xtd" |
cf7898a6 | 1082 | "2_br,2_scall") |
58ada791 | 1083 | |
ea13ae4c | 1084 | (define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\ |
58ada791 | 1085 | 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ |
ea13ae4c | 1086 | 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_ldc,2_chk_s_i,2_chk_s_f,2_chk_a,2_long_i,\ |
a5c5f9d3 | 1087 | 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ |
58ada791 | 1088 | 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ |
1089 | 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ | |
1090 | 2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore") | |
1091 | ||
1092 | ||
1093 | \f | |
1094 | ;; Bundling | |
1095 | ||
1096 | (define_automaton "twob") | |
1097 | ||
1098 | ;; Pseudo units for quicker searching for position in two packet window. */ | |
1099 | (define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob") | |
1100 | ||
1101 | ;; All possible combinations of bundles/syllables | |
1102 | (define_cpu_unit | |
1103 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
1104 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob") | |
1105 | (define_cpu_unit | |
1106 | "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
1107 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob") | |
1108 | (define_query_cpu_unit | |
1109 | "2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
1110 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob") | |
1111 | ||
1112 | (define_cpu_unit | |
1113 | "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
1114 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob") | |
1115 | (define_cpu_unit | |
1116 | "2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
1117 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob") | |
1118 | (define_query_cpu_unit | |
1119 | "2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
1120 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob") | |
1121 | ||
1122 | ;; Slot 1 | |
1123 | (exclusion_set "2b_0m.ii" | |
1124 | "2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
1125 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1126 | (exclusion_set "2b_0m.mi" | |
1127 | "2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\ | |
1128 | 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1129 | (exclusion_set "2b_0m.fi" | |
1130 | "2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1131 | (exclusion_set "2b_0m.mf" | |
1132 | "2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1133 | (exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1134 | (exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1135 | (exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1136 | (exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx") | |
1137 | (exclusion_set "2b_0m.fb" "2b_0m.lx") | |
1138 | ||
1139 | ;; Slot 2 | |
1140 | (exclusion_set "2b_0mi.i" | |
1141 | "2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
1142 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1143 | (exclusion_set "2b_0mm.i" | |
1144 | "2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
1145 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1146 | (exclusion_set "2b_0mf.i" | |
1147 | "2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1148 | (exclusion_set "2b_0mm.f" | |
1149 | "2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1150 | (exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1151 | (exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1152 | (exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
1153 | (exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.") | |
1154 | (exclusion_set "2b_0mf.b" "2b_0mlx.") | |
1155 | ||
1156 | ;; Slot 3 | |
1157 | (exclusion_set "2b_0mii." | |
1158 | "2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
1159 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1160 | (exclusion_set "2b_0mmi." | |
1161 | "2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
1162 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1163 | (exclusion_set "2b_0mfi." | |
1164 | "2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1165 | (exclusion_set "2b_0mmf." | |
1166 | "2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1167 | (exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1168 | (exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1169 | (exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
1170 | (exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.") | |
1171 | (exclusion_set "2b_0mfb." "2b_0mlx.") | |
1172 | ||
1173 | ;; Slot 4 | |
1174 | (exclusion_set "2b_1m.ii" | |
1175 | "2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
1176 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1177 | (exclusion_set "2b_1m.mi" | |
1178 | "2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\ | |
1179 | 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1180 | (exclusion_set "2b_1m.fi" | |
1181 | "2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1182 | (exclusion_set "2b_1m.mf" | |
1183 | "2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1184 | (exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1185 | (exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1186 | (exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
1187 | (exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx") | |
1188 | (exclusion_set "2b_1m.fb" "2b_1m.lx") | |
1189 | ||
1190 | ;; Slot 5 | |
1191 | (exclusion_set "2b_1mi.i" | |
1192 | "2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
1193 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1194 | (exclusion_set "2b_1mm.i" | |
1195 | "2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
1196 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1197 | (exclusion_set "2b_1mf.i" | |
1198 | "2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1199 | (exclusion_set "2b_1mm.f" | |
1200 | "2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1201 | (exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1202 | (exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1203 | (exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
1204 | (exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.") | |
1205 | (exclusion_set "2b_1mf.b" "2b_1mlx.") | |
1206 | ||
1207 | ;; Slot 6 | |
1208 | (exclusion_set "2b_1mii." | |
1209 | "2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
1210 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1211 | (exclusion_set "2b_1mmi." | |
1212 | "2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
1213 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1214 | (exclusion_set "2b_1mfi." | |
1215 | "2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1216 | (exclusion_set "2b_1mmf." | |
1217 | "2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1218 | (exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1219 | (exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1220 | (exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
1221 | (exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.") | |
1222 | (exclusion_set "2b_1mfb." "2b_1mlx.") | |
1223 | ||
1224 | (final_presence_set "2b_0mi.i" "2b_0m.ii") | |
1225 | (final_presence_set "2b_0mii." "2b_0mi.i") | |
1226 | (final_presence_set "2b_1mi.i" "2b_1m.ii") | |
1227 | (final_presence_set "2b_1mii." "2b_1mi.i") | |
1228 | ||
1229 | (final_presence_set "2b_0mm.i" "2b_0m.mi") | |
1230 | (final_presence_set "2b_0mmi." "2b_0mm.i") | |
1231 | (final_presence_set "2b_1mm.i" "2b_1m.mi") | |
1232 | (final_presence_set "2b_1mmi." "2b_1mm.i") | |
1233 | ||
1234 | (final_presence_set "2b_0mf.i" "2b_0m.fi") | |
1235 | (final_presence_set "2b_0mfi." "2b_0mf.i") | |
1236 | (final_presence_set "2b_1mf.i" "2b_1m.fi") | |
1237 | (final_presence_set "2b_1mfi." "2b_1mf.i") | |
1238 | ||
1239 | (final_presence_set "2b_0mm.f" "2b_0m.mf") | |
1240 | (final_presence_set "2b_0mmf." "2b_0mm.f") | |
1241 | (final_presence_set "2b_1mm.f" "2b_1m.mf") | |
1242 | (final_presence_set "2b_1mmf." "2b_1mm.f") | |
1243 | ||
1244 | (final_presence_set "2b_0bb.b" "2b_0b.bb") | |
1245 | (final_presence_set "2b_0bbb." "2b_0bb.b") | |
1246 | (final_presence_set "2b_1bb.b" "2b_1b.bb") | |
1247 | (final_presence_set "2b_1bbb." "2b_1bb.b") | |
1248 | ||
1249 | (final_presence_set "2b_0mb.b" "2b_0m.bb") | |
1250 | (final_presence_set "2b_0mbb." "2b_0mb.b") | |
1251 | (final_presence_set "2b_1mb.b" "2b_1m.bb") | |
1252 | (final_presence_set "2b_1mbb." "2b_1mb.b") | |
1253 | ||
1254 | (final_presence_set "2b_0mi.b" "2b_0m.ib") | |
1255 | (final_presence_set "2b_0mib." "2b_0mi.b") | |
1256 | (final_presence_set "2b_1mi.b" "2b_1m.ib") | |
1257 | (final_presence_set "2b_1mib." "2b_1mi.b") | |
1258 | ||
1259 | (final_presence_set "2b_0mm.b" "2b_0m.mb") | |
1260 | (final_presence_set "2b_0mmb." "2b_0mm.b") | |
1261 | (final_presence_set "2b_1mm.b" "2b_1m.mb") | |
1262 | (final_presence_set "2b_1mmb." "2b_1mm.b") | |
1263 | ||
1264 | (final_presence_set "2b_0mf.b" "2b_0m.fb") | |
1265 | (final_presence_set "2b_0mfb." "2b_0mf.b") | |
1266 | (final_presence_set "2b_1mf.b" "2b_1m.fb") | |
1267 | (final_presence_set "2b_1mfb." "2b_1mf.b") | |
1268 | ||
1269 | (final_presence_set "2b_0mlx." "2b_0m.lx") | |
1270 | (final_presence_set "2b_1mlx." "2b_1m.lx") | |
1271 | ||
1272 | ;; See the corresponding comment in non-bundling section above. | |
1273 | (final_presence_set | |
1274 | "2b_1m.lx" | |
1275 | "2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") | |
1276 | (final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.") | |
1277 | (final_presence_set | |
1278 | "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb" | |
1279 | "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") | |
1280 | ||
1281 | ;; Ports/units (nb means nop.b insn issued into given port): | |
1282 | (define_cpu_unit | |
1283 | "2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\ | |
1284 | 2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob") | |
1285 | ||
1286 | (exclusion_set "2b_ub0" "2b_unb0") | |
1287 | (exclusion_set "2b_ub1" "2b_unb1") | |
1288 | (exclusion_set "2b_ub2" "2b_unb2") | |
1289 | ||
1290 | ;; The following rules are used to decrease number of alternatives. | |
1291 | ;; They are consequences of Itanium2 microarchitecture. They also | |
1292 | ;; describe the following rules mentioned in Itanium2 | |
1293 | ;; microarchitecture: rules mentioned in Itanium2 microarchitecture: | |
1294 | ;; o "BBB/MBB: Always splits issue after either of these bundles". | |
1295 | ;; o "MIB BBB: Split issue after the first bundle in this pair". | |
1296 | (exclusion_set | |
1297 | "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb." | |
1298 | "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\ | |
1299 | 2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx") | |
1300 | (exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb") | |
1301 | ||
1302 | ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the | |
1303 | ;;; B-slot contains a nop.b or a brp instruction". | |
1304 | ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or | |
1305 | ;;; nop.b, otherwise it disperses to B2". | |
1306 | (final_absence_set | |
1307 | "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
1308 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" | |
1309 | "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2") | |
1310 | ||
1311 | ;; This is necessary to start new processor cycle when we meet stop bit. | |
1312 | (define_cpu_unit "2b_stop" "twob") | |
1313 | (final_absence_set | |
1314 | "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ | |
1315 | 2b_0m.fi,2b_0mf.i,2b_0mfi.,\ | |
1316 | 2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\ | |
1317 | 2b_0m.bb,2b_0mb.b,2b_0mbb.,\ | |
1318 | 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ | |
1319 | 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ | |
1320 | 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ | |
1321 | 2b_1m.fi,2b_1mf.i,2b_1mfi.,\ | |
1322 | 2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\ | |
1323 | 2b_1m.bb,2b_1mb.b,2b_1mbb.,\ | |
1324 | 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ | |
1325 | 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." | |
1326 | "2b_stop") | |
1327 | ||
1328 | ;; The issue logic can reorder M slot insns between different subtypes | |
33f88b1c | 1329 | ;; but cannot reorder insn within the same subtypes. The following |
58ada791 | 1330 | ;; constraint is enough to describe this. |
1331 | (final_presence_set "2b_um1" "2b_um0") | |
1332 | (final_presence_set "2b_um3" "2b_um2") | |
1333 | ||
1334 | ;; The insn in the 1st I slot of the two bundle issue group will issue | |
1335 | ;; to I0. The second I slot insn will issue to I1. | |
1336 | (final_presence_set "2b_ui1" "2b_ui0") | |
1337 | ||
1338 | ;; For exceptions of I insns: | |
1339 | (define_cpu_unit "2b_only_ui0" "twob") | |
1340 | (final_absence_set "2b_only_ui0" "2b_ui1") | |
1341 | ||
1342 | ;; Insns | |
1343 | ||
1344 | (define_reservation "2b_M" | |
1345 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
1346 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
1347 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
1348 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
1349 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
1350 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
1351 | +(2b_um0|2b_um1|2b_um2|2b_um3)") | |
1352 | ||
1353 | (define_reservation "2b_M_only_um0" | |
1354 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
1355 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
1356 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
1357 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
1358 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
1359 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
1360 | +2b_um0") | |
1361 | ||
1362 | (define_reservation "2b_M_only_um2" | |
1363 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
1364 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
1365 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
1366 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
1367 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
1368 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
1369 | +2b_um2") | |
1370 | ||
1371 | (define_reservation "2b_M_only_um01" | |
1372 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
1373 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
1374 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
1375 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
1376 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
1377 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
1378 | +(2b_um0|2b_um1)") | |
1379 | ||
1380 | (define_reservation "2b_M_only_um23" | |
1381 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
1382 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
1383 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
1384 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
1385 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
1386 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
1387 | +(2b_um2|2b_um3)") | |
1388 | ||
1389 | ;; I instruction is dispersed to the lowest numbered I unit | |
7bd28bba | 1390 | ;; not already in use. Remember about possible splitting. |
58ada791 | 1391 | (define_reservation "2b_I" |
1392 | "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\ | |
1393 | |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\ | |
1394 | |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\ | |
1395 | |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)") | |
1396 | ||
1397 | ;; "An F slot in the 1st bundle disperses to F0". | |
1398 | ;; "An F slot in the 2st bundle disperses to F1". | |
1399 | (define_reservation "2b_F" | |
1400 | "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\ | |
1401 | |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1") | |
1402 | ||
1403 | ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B | |
3c364971 | 1404 | ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the |
58ada791 | 1405 | ;;; 2nd position it is dispersed to B2". |
1406 | (define_reservation "2b_NB" | |
1407 | "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\ | |
1408 | |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\ | |
1409 | |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\ | |
1410 | |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\ | |
1411 | |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\ | |
1412 | |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0") | |
1413 | ||
1414 | (define_reservation "2b_B" | |
1415 | "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\ | |
1416 | |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\ | |
1417 | |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\ | |
1418 | |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\ | |
1419 | |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2") | |
1420 | ||
1421 | ;; For the MLI template, the I slot insn is always assigned to port I0 | |
1422 | ;; if it is in the first bundle or it is assigned to port I1 if it is in | |
1423 | ;; the second bundle. | |
1424 | (define_reservation "2b_L" | |
1425 | "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1") | |
1426 | ||
1427 | ;; Should we describe that A insn in I slot can be issued into M | |
1428 | ;; ports? I think it is not necessary because of multipass | |
1429 | ;; scheduling. For example, the multipass scheduling could use | |
1430 | ;; MMI-MMI instead of MII-MII where the two last I slots contain A | |
1431 | ;; insns (even if the case is complicated by use-def conflicts). | |
1432 | ;; | |
1433 | ;; In any case we could describe it as | |
1434 | ;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" | |
1435 | ;; "twob") | |
1436 | ;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" | |
1437 | ;; "2b_ui1") | |
1438 | ;; (define_reservation "b_A" | |
1439 | ;; "b_M|b_I\ | |
1440 | ;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\ | |
1441 | ;; +(2b_um0|2b_um1|2b_um2|2b_um3)\ | |
1442 | ;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)") | |
1443 | ||
1444 | (define_reservation "2b_A" "2b_M|2b_I") | |
1445 | ||
1446 | ;; We assume that there is no insn issued on the same cycle as the | |
1447 | ;; unknown insn. | |
1448 | (define_cpu_unit "2b_empty" "twob") | |
1449 | (exclusion_set "2b_empty" | |
1450 | "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\ | |
1451 | 2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i") | |
1452 | ||
1453 | (define_cpu_unit | |
1454 | "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs" | |
1455 | "twob") | |
1456 | (define_cpu_unit | |
1457 | "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" | |
1458 | "twob") | |
1459 | ||
1460 | (define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\ | |
1461 | 2b_b_cont, 2b_bb_cont" "twob") | |
1462 | ||
1463 | ;; For stop in the middle of the bundles. | |
1464 | (define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob") | |
1465 | (define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob") | |
1466 | ||
1467 | (final_presence_set "2b_0m_bs" | |
1468 | "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\ | |
1469 | 2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx") | |
1470 | (final_presence_set "2b_1m_bs" | |
1471 | "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\ | |
1472 | 2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx") | |
1473 | (final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i") | |
1474 | (final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i") | |
1475 | (final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b") | |
1476 | (final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b") | |
1477 | (final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b") | |
1478 | (final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b") | |
1479 | (final_presence_set "2b_0b_bs" "2b_0b.bb") | |
1480 | (final_presence_set "2b_1b_bs" "2b_1b.bb") | |
1481 | (final_presence_set "2b_0bb_bs" "2b_0bb.b") | |
1482 | (final_presence_set "2b_1bb_bs" "2b_1bb.b") | |
1483 | (final_presence_set "2b_0mb_bs" "2b_0mb.b") | |
1484 | (final_presence_set "2b_1mb_bs" "2b_1mb.b") | |
1485 | ||
1486 | (exclusion_set "2b_0m_bs" | |
1487 | "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\ | |
1488 | 2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop") | |
1489 | (exclusion_set "2b_1m_bs" | |
1490 | "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\ | |
1491 | 2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop") | |
1492 | (exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop") | |
1493 | (exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop") | |
1494 | (exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.") | |
1495 | (exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.") | |
1496 | (exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.") | |
1497 | (exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.") | |
1498 | (exclusion_set "2b_0b_bs" "2b_0bb.b") | |
1499 | (exclusion_set "2b_1b_bs" "2b_1bb.b") | |
1500 | (exclusion_set "2b_0bb_bs" "2b_0bbb.") | |
1501 | (exclusion_set "2b_1bb_bs" "2b_1bbb.") | |
1502 | (exclusion_set "2b_0mb_bs" "2b_0mbb.") | |
1503 | (exclusion_set "2b_1mb_bs" "2b_1mbb.") | |
1504 | ||
1505 | (exclusion_set | |
1506 | "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs, | |
1507 | 2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" | |
1508 | "2b_stop") | |
1509 | ||
1510 | (final_presence_set | |
1511 | "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\ | |
1512 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx." | |
1513 | "2b_m_cont") | |
1514 | (final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont") | |
1515 | (final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont") | |
1516 | (final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont") | |
1517 | (final_presence_set "2b_0bb.b" "2b_b_cont") | |
1518 | (final_presence_set "2b_0bbb." "2b_bb_cont") | |
1519 | (final_presence_set "2b_0mbb." "2b_mb_cont") | |
1520 | ||
1521 | (exclusion_set | |
1522 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
1523 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" | |
1524 | "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\ | |
1525 | 2b_mb_cont, 2b_b_cont, 2b_bb_cont") | |
1526 | ||
1527 | (exclusion_set "2b_empty" | |
1528 | "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\ | |
1529 | 2b_mb_cont,2b_b_cont,2b_bb_cont") | |
1530 | ||
1531 | ;; For m;mi bundle | |
1532 | (final_presence_set "2b_m0_stop" "2b_0m.mi") | |
1533 | (final_presence_set "2b_0mm.i" "2b_0mmi_cont") | |
1534 | (exclusion_set "2b_0mmi_cont" | |
1535 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
1536 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1537 | (exclusion_set "2b_m0_stop" "2b_0mm.i") | |
1538 | (final_presence_set "2b_m1_stop" "2b_1m.mi") | |
1539 | (exclusion_set "2b_m1_stop" "2b_1mm.i") | |
1540 | (final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop") | |
1541 | ||
1542 | ;; For mi;i bundle | |
1543 | (final_presence_set "2b_mi0_stop" "2b_0mi.i") | |
1544 | (final_presence_set "2b_0mii." "2b_0mii_cont") | |
1545 | (exclusion_set "2b_0mii_cont" | |
1546 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
1547 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
1548 | (exclusion_set "2b_mi0_stop" "2b_0mii.") | |
1549 | (final_presence_set "2b_mi1_stop" "2b_1mi.i") | |
1550 | (exclusion_set "2b_mi1_stop" "2b_1mii.") | |
1551 | (final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop") | |
1552 | ||
1553 | (final_absence_set | |
1554 | "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ | |
1555 | 2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\ | |
1556 | 2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\ | |
1557 | 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ | |
1558 | 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ | |
1559 | 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ | |
1560 | 2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\ | |
1561 | 2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\ | |
1562 | 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ | |
1563 | 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." | |
1564 | "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop") | |
1565 | ||
1566 | (define_insn_reservation "2b_stop_bit" 0 | |
1567 | (and (and (eq_attr "cpu" "itanium2") | |
1568 | (eq_attr "itanium_class" "stop_bit")) | |
f4d8a59e | 1569 | (match_test "bundling_p")) |
58ada791 | 1570 | "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop") |
1571 | (define_insn_reservation "2b_br" 0 | |
1572 | (and (and (eq_attr "cpu" "itanium2") | |
1573 | (eq_attr "itanium_class" "br")) | |
f4d8a59e | 1574 | (match_test "bundling_p")) "2b_B") |
58ada791 | 1575 | (define_insn_reservation "2b_scall" 0 |
1576 | (and (and (eq_attr "cpu" "itanium2") | |
1577 | (eq_attr "itanium_class" "scall")) | |
f4d8a59e | 1578 | (match_test "bundling_p")) "2b_B") |
58ada791 | 1579 | (define_insn_reservation "2b_fcmp" 2 |
1580 | (and (and (eq_attr "cpu" "itanium2") | |
1581 | (eq_attr "itanium_class" "fcmp")) | |
f4d8a59e | 1582 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1583 | (define_insn_reservation "2b_fcvtfx" 4 |
1584 | (and (and (eq_attr "cpu" "itanium2") | |
1585 | (eq_attr "itanium_class" "fcvtfx")) | |
f4d8a59e | 1586 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1587 | (define_insn_reservation "2b_fld" 6 |
ea13ae4c | 1588 | (and (and (and (and (eq_attr "cpu" "itanium2") |
1589 | (eq_attr "itanium_class" "fld")) | |
1590 | (eq_attr "data_speculative" "no")) | |
1591 | (eq_attr "check_load" "no")) | |
f4d8a59e | 1592 | (match_test "bundling_p")) |
ea13ae4c | 1593 | "2b_M") |
1594 | (define_insn_reservation "2b_flda" 6 | |
1595 | (and (and (and (eq_attr "cpu" "itanium2") | |
1596 | (eq_attr "itanium_class" "fld")) | |
1597 | (eq_attr "data_speculative" "yes")) | |
f4d8a59e | 1598 | (match_test "bundling_p")) |
ea13ae4c | 1599 | "2b_M_only_um01") |
1600 | (define_insn_reservation "2b_fldc" 0 | |
1601 | (and (and (and (eq_attr "cpu" "itanium2") | |
1602 | (eq_attr "itanium_class" "fld")) | |
1603 | (eq_attr "check_load" "yes")) | |
f4d8a59e | 1604 | (match_test "bundling_p")) |
ea13ae4c | 1605 | "2b_M_only_um01") |
1606 | ||
4d053aca | 1607 | (define_insn_reservation "2b_fldp" 6 |
ea13ae4c | 1608 | (and (and (and (eq_attr "cpu" "itanium2") |
1609 | (eq_attr "itanium_class" "fldp")) | |
1610 | (eq_attr "check_load" "no")) | |
f4d8a59e | 1611 | (match_test "bundling_p")) |
ea13ae4c | 1612 | "2b_M_only_um01") |
1613 | (define_insn_reservation "2b_fldpc" 0 | |
1614 | (and (and (and (eq_attr "cpu" "itanium2") | |
1615 | (eq_attr "itanium_class" "fldp")) | |
1616 | (eq_attr "check_load" "yes")) | |
f4d8a59e | 1617 | (match_test "bundling_p")) |
4d053aca | 1618 | "2b_M_only_um01") |
ea13ae4c | 1619 | |
58ada791 | 1620 | (define_insn_reservation "2b_fmac" 4 |
1621 | (and (and (eq_attr "cpu" "itanium2") | |
1622 | (eq_attr "itanium_class" "fmac")) | |
f4d8a59e | 1623 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1624 | (define_insn_reservation "2b_fmisc" 4 |
1625 | (and (and (eq_attr "cpu" "itanium2") | |
1626 | (eq_attr "itanium_class" "fmisc")) | |
f4d8a59e | 1627 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1628 | |
1629 | ;; Latency time ??? | |
1630 | (define_insn_reservation "2b_frar_i" 13 | |
1631 | (and (and (eq_attr "cpu" "itanium2") | |
1632 | (eq_attr "itanium_class" "frar_i")) | |
f4d8a59e | 1633 | (match_test "bundling_p")) |
58ada791 | 1634 | "2b_I+2b_only_ui0") |
1635 | ;; Latency time ??? | |
1636 | (define_insn_reservation "2b_frar_m" 6 | |
1637 | (and (and (eq_attr "cpu" "itanium2") | |
1638 | (eq_attr "itanium_class" "frar_m")) | |
f4d8a59e | 1639 | (match_test "bundling_p")) |
58ada791 | 1640 | "2b_M_only_um2") |
1641 | (define_insn_reservation "2b_frbr" 2 | |
1642 | (and (and (eq_attr "cpu" "itanium2") | |
1643 | (eq_attr "itanium_class" "frbr")) | |
f4d8a59e | 1644 | (match_test "bundling_p")) |
58ada791 | 1645 | "2b_I+2b_only_ui0") |
1646 | (define_insn_reservation "2b_frfr" 5 | |
1647 | (and (and (eq_attr "cpu" "itanium2") | |
1648 | (eq_attr "itanium_class" "frfr")) | |
f4d8a59e | 1649 | (match_test "bundling_p")) |
58ada791 | 1650 | "2b_M_only_um2") |
1651 | (define_insn_reservation "2b_frpr" 2 | |
1652 | (and (and (eq_attr "cpu" "itanium2") | |
1653 | (eq_attr "itanium_class" "frpr")) | |
f4d8a59e | 1654 | (match_test "bundling_p")) |
58ada791 | 1655 | "2b_I+2b_only_ui0") |
1656 | ||
1657 | (define_insn_reservation "2b_ialu" 1 | |
1658 | (and (and (eq_attr "cpu" "itanium2") | |
1659 | (eq_attr "itanium_class" "ialu")) | |
f4d8a59e | 1660 | (match_test "bundling_p")) |
58ada791 | 1661 | "2b_A") |
1662 | (define_insn_reservation "2b_icmp" 1 | |
1663 | (and (and (eq_attr "cpu" "itanium2") | |
1664 | (eq_attr "itanium_class" "icmp")) | |
f4d8a59e | 1665 | (match_test "bundling_p")) "2b_A") |
58ada791 | 1666 | (define_insn_reservation "2b_ilog" 1 |
1667 | (and (and (eq_attr "cpu" "itanium2") | |
1668 | (eq_attr "itanium_class" "ilog")) | |
f4d8a59e | 1669 | (match_test "bundling_p")) "2b_A") |
a5c5f9d3 | 1670 | (define_insn_reservation "2b_mmalua" 2 |
1671 | (and (and (eq_attr "cpu" "itanium2") | |
1672 | (eq_attr "itanium_class" "mmalua")) | |
f4d8a59e | 1673 | (match_test "bundling_p")) "2b_A") |
58ada791 | 1674 | ;; Latency time ??? |
1675 | (define_insn_reservation "2b_ishf" 1 | |
1676 | (and (and (eq_attr "cpu" "itanium2") | |
1677 | (eq_attr "itanium_class" "ishf")) | |
f4d8a59e | 1678 | (match_test "bundling_p")) |
58ada791 | 1679 | "2b_I+2b_only_ui0") |
ea13ae4c | 1680 | |
58ada791 | 1681 | (define_insn_reservation "2b_ld" 1 |
ea13ae4c | 1682 | (and (and (and (eq_attr "cpu" "itanium2") |
1683 | (eq_attr "itanium_class" "ld")) | |
1684 | (eq_attr "check_load" "no")) | |
f4d8a59e | 1685 | (match_test "bundling_p")) |
58ada791 | 1686 | "2b_M_only_um01") |
ea13ae4c | 1687 | (define_insn_reservation "2b_ldc" 0 |
1688 | (and (and (and (eq_attr "cpu" "itanium2") | |
1689 | (eq_attr "itanium_class" "ld")) | |
1690 | (eq_attr "check_load" "yes")) | |
f4d8a59e | 1691 | (match_test "bundling_p")) |
ea13ae4c | 1692 | "2b_M_only_um01") |
1693 | ||
58ada791 | 1694 | (define_insn_reservation "2b_long_i" 1 |
1695 | (and (and (eq_attr "cpu" "itanium2") | |
1696 | (eq_attr "itanium_class" "long_i")) | |
f4d8a59e | 1697 | (match_test "bundling_p")) "2b_L") |
58ada791 | 1698 | |
1699 | ;; Latency time ??? | |
1700 | (define_insn_reservation "2b_mmmul" 2 | |
1701 | (and (and (eq_attr "cpu" "itanium2") | |
1702 | (eq_attr "itanium_class" "mmmul")) | |
f4d8a59e | 1703 | (match_test "bundling_p")) |
58ada791 | 1704 | "2b_I+2b_only_ui0") |
1705 | ;; Latency time ??? | |
1706 | (define_insn_reservation "2b_mmshf" 2 | |
1707 | (and (and (eq_attr "cpu" "itanium2") | |
1708 | (eq_attr "itanium_class" "mmshf")) | |
f4d8a59e | 1709 | (match_test "bundling_p")) "2b_I") |
58ada791 | 1710 | ;; Latency time ??? |
1711 | (define_insn_reservation "2b_mmshfi" 1 | |
1712 | (and (and (eq_attr "cpu" "itanium2") | |
1713 | (eq_attr "itanium_class" "mmshfi")) | |
f4d8a59e | 1714 | (match_test "bundling_p")) "2b_I") |
58ada791 | 1715 | |
1716 | (define_insn_reservation "2b_rse_m" 0 | |
1717 | (and (and (eq_attr "cpu" "itanium2") | |
1718 | (eq_attr "itanium_class" "rse_m")) | |
f4d8a59e | 1719 | (match_test "bundling_p")) |
58ada791 | 1720 | "(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ |
1721 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0") | |
1722 | (define_insn_reservation "2b_sem" 0 | |
1723 | (and (and (eq_attr "cpu" "itanium2") | |
1724 | (eq_attr "itanium_class" "sem")) | |
f4d8a59e | 1725 | (match_test "bundling_p")) |
58ada791 | 1726 | "2b_M_only_um23") |
1727 | ||
1728 | (define_insn_reservation "2b_stf" 1 | |
1729 | (and (and (eq_attr "cpu" "itanium2") | |
1730 | (eq_attr "itanium_class" "stf")) | |
f4d8a59e | 1731 | (match_test "bundling_p")) |
58ada791 | 1732 | "2b_M_only_um23") |
1733 | (define_insn_reservation "2b_st" 1 | |
1734 | (and (and (eq_attr "cpu" "itanium2") | |
1735 | (eq_attr "itanium_class" "st")) | |
f4d8a59e | 1736 | (match_test "bundling_p")) |
58ada791 | 1737 | "2b_M_only_um23") |
1738 | (define_insn_reservation "2b_syst_m0" 0 | |
1739 | (and (and (eq_attr "cpu" "itanium2") | |
1740 | (eq_attr "itanium_class" "syst_m0")) | |
f4d8a59e | 1741 | (match_test "bundling_p")) |
58ada791 | 1742 | "2b_M_only_um2") |
1743 | (define_insn_reservation "2b_syst_m" 0 | |
1744 | (and (and (eq_attr "cpu" "itanium2") | |
1745 | (eq_attr "itanium_class" "syst_m")) | |
f4d8a59e | 1746 | (match_test "bundling_p")) |
58ada791 | 1747 | "2b_M_only_um0") |
1748 | ;; Reservation??? | |
1749 | (define_insn_reservation "2b_tbit" 1 | |
1750 | (and (and (eq_attr "cpu" "itanium2") | |
1751 | (eq_attr "itanium_class" "tbit")) | |
f4d8a59e | 1752 | (match_test "bundling_p")) |
58ada791 | 1753 | "2b_I+2b_only_ui0") |
1754 | (define_insn_reservation "2b_toar_i" 0 | |
1755 | (and (and (eq_attr "cpu" "itanium2") | |
1756 | (eq_attr "itanium_class" "toar_i")) | |
f4d8a59e | 1757 | (match_test "bundling_p")) |
58ada791 | 1758 | "2b_I+2b_only_ui0") |
1759 | ;; Latency time ??? | |
1760 | (define_insn_reservation "2b_toar_m" 5 | |
1761 | (and (and (eq_attr "cpu" "itanium2") | |
1762 | (eq_attr "itanium_class" "toar_m")) | |
f4d8a59e | 1763 | (match_test "bundling_p")) |
58ada791 | 1764 | "2b_M_only_um2") |
1765 | ;; Latency time ??? | |
1766 | (define_insn_reservation "2b_tobr" 1 | |
1767 | (and (and (eq_attr "cpu" "itanium2") | |
1768 | (eq_attr "itanium_class" "tobr")) | |
f4d8a59e | 1769 | (match_test "bundling_p")) |
58ada791 | 1770 | "2b_I+2b_only_ui0") |
1771 | (define_insn_reservation "2b_tofr" 5 | |
1772 | (and (and (eq_attr "cpu" "itanium2") | |
1773 | (eq_attr "itanium_class" "tofr")) | |
f4d8a59e | 1774 | (match_test "bundling_p")) |
58ada791 | 1775 | "2b_M_only_um23") |
1776 | ;; Latency time ??? | |
1777 | (define_insn_reservation "2b_topr" 1 | |
1778 | (and (and (eq_attr "cpu" "itanium2") | |
1779 | (eq_attr "itanium_class" "topr")) | |
f4d8a59e | 1780 | (match_test "bundling_p")) |
58ada791 | 1781 | "2b_I+2b_only_ui0") |
1782 | ||
1783 | (define_insn_reservation "2b_xmpy" 4 | |
1784 | (and (and (eq_attr "cpu" "itanium2") | |
1785 | (eq_attr "itanium_class" "xmpy")) | |
f4d8a59e | 1786 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1787 | ;; Latency time ??? |
1788 | (define_insn_reservation "2b_xtd" 1 | |
1789 | (and (and (eq_attr "cpu" "itanium2") | |
1790 | (eq_attr "itanium_class" "xtd")) | |
f4d8a59e | 1791 | (match_test "bundling_p")) "2b_I") |
ea13ae4c | 1792 | |
1793 | (define_insn_reservation "2b_chk_s_i" 0 | |
58ada791 | 1794 | (and (and (eq_attr "cpu" "itanium2") |
ea13ae4c | 1795 | (eq_attr "itanium_class" "chk_s_i")) |
f4d8a59e | 1796 | (match_test "bundling_p")) |
58ada791 | 1797 | "2b_I|2b_M_only_um23") |
ea13ae4c | 1798 | (define_insn_reservation "2b_chk_s_f" 0 |
1799 | (and (and (eq_attr "cpu" "itanium2") | |
1800 | (eq_attr "itanium_class" "chk_s_f")) | |
f4d8a59e | 1801 | (match_test "bundling_p")) |
ea13ae4c | 1802 | "2b_M_only_um23") |
1803 | (define_insn_reservation "2b_chk_a" 0 | |
1804 | (and (and (eq_attr "cpu" "itanium2") | |
1805 | (eq_attr "itanium_class" "chk_a")) | |
f4d8a59e | 1806 | (match_test "bundling_p")) |
ea13ae4c | 1807 | "2b_M_only_um01") |
1808 | ||
58ada791 | 1809 | (define_insn_reservation "2b_lfetch" 0 |
1810 | (and (and (eq_attr "cpu" "itanium2") | |
1811 | (eq_attr "itanium_class" "lfetch")) | |
f4d8a59e | 1812 | (match_test "bundling_p")) |
58ada791 | 1813 | "2b_M_only_um01") |
1814 | (define_insn_reservation "2b_nop_m" 0 | |
1815 | (and (and (eq_attr "cpu" "itanium2") | |
1816 | (eq_attr "itanium_class" "nop_m")) | |
f4d8a59e | 1817 | (match_test "bundling_p")) "2b_M") |
58ada791 | 1818 | (define_insn_reservation "2b_nop_b" 0 |
1819 | (and (and (eq_attr "cpu" "itanium2") | |
1820 | (eq_attr "itanium_class" "nop_b")) | |
f4d8a59e | 1821 | (match_test "bundling_p")) "2b_NB") |
58ada791 | 1822 | (define_insn_reservation "2b_nop_i" 0 |
1823 | (and (and (eq_attr "cpu" "itanium2") | |
1824 | (eq_attr "itanium_class" "nop_i")) | |
f4d8a59e | 1825 | (match_test "bundling_p")) "2b_I") |
58ada791 | 1826 | (define_insn_reservation "2b_nop_f" 0 |
1827 | (and (and (eq_attr "cpu" "itanium2") | |
1828 | (eq_attr "itanium_class" "nop_f")) | |
f4d8a59e | 1829 | (match_test "bundling_p")) "2b_F") |
58ada791 | 1830 | (define_insn_reservation "2b_nop_x" 0 |
1831 | (and (and (eq_attr "cpu" "itanium2") | |
1832 | (eq_attr "itanium_class" "nop_x")) | |
f4d8a59e | 1833 | (match_test "bundling_p")) "2b_L") |
58ada791 | 1834 | (define_insn_reservation "2b_unknown" 1 |
1835 | (and (and (eq_attr "cpu" "itanium2") | |
1836 | (eq_attr "itanium_class" "unknown")) | |
f4d8a59e | 1837 | (match_test "bundling_p")) "2b_empty") |
58ada791 | 1838 | (define_insn_reservation "2b_nop" 0 |
1839 | (and (and (eq_attr "cpu" "itanium2") | |
1840 | (eq_attr "itanium_class" "nop")) | |
f4d8a59e | 1841 | (match_test "bundling_p")) |
58ada791 | 1842 | "2b_M|2b_NB|2b_I|2b_F") |
1843 | (define_insn_reservation "2b_ignore" 0 | |
1844 | (and (and (eq_attr "cpu" "itanium2") | |
1845 | (eq_attr "itanium_class" "ignore")) | |
f4d8a59e | 1846 | (match_test "bundling_p")) "nothing") |
58ada791 | 1847 | |
1848 | (define_insn_reservation "2b_pre_cycle" 0 | |
1849 | (and (and (eq_attr "cpu" "itanium2") | |
1850 | (eq_attr "itanium_class" "pre_cycle")) | |
f4d8a59e | 1851 | (match_test "bundling_p")) |
58ada791 | 1852 | "(2b_0m_bs, 2b_m_cont) \ |
1853 | | (2b_0mi_bs, 2b_mi_cont) \ | |
1854 | | (2b_0mm_bs, 2b_mm_cont) \ | |
1855 | | (2b_0mf_bs, 2b_mf_cont) \ | |
1856 | | (2b_0b_bs, 2b_b_cont) \ | |
1857 | | (2b_0bb_bs, 2b_bb_cont) \ | |
1858 | | (2b_0mb_bs, 2b_mb_cont) \ | |
1859 | | (2b_1m_bs, 2b_m_cont) \ | |
1860 | | (2b_1mi_bs, 2b_mi_cont) \ | |
1861 | | (2b_1mm_bs, 2b_mm_cont) \ | |
1862 | | (2b_1mf_bs, 2b_mf_cont) \ | |
1863 | | (2b_1b_bs, 2b_b_cont) \ | |
1864 | | (2b_1bb_bs, 2b_bb_cont) \ | |
1865 | | (2b_1mb_bs, 2b_mb_cont) \ | |
1866 | | (2b_m_stop, 2b_0mmi_cont) \ | |
1867 | | (2b_mi_stop, 2b_0mii_cont)") | |
1868 |