projects / thirdparty / gcc.git / blame
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| 30028c85 | 1 | ;; Itanium2 DFA descriptions for insn scheduling and bundling. |
| 5b86a469 | 2 | ;; Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc. |
| 30028c85 VM |
3 | ;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
| 4 | ;; | |
| 3bed2930 | 5 | ;; This file is part of GCC. |
| 30028c85 | 6 | ;; |
| 3bed2930 | 7 | ;; GCC is free software; you can redistribute it and/or modify |
| 30028c85 VM |
8 | ;; it under the terms of the GNU General Public License as published by |
| 9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
| 10 | ;; any later version. | |
| 11 | ;; | |
| 3bed2930 | 12 | ;; GCC is distributed in the hope that it will be useful, |
| 30028c85 VM |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | ;; GNU General Public License for more details. | |
| 16 | ;; | |
| 17 | ;; You should have received a copy of the GNU General Public License | |
| 3bed2930 | 18 | ;; along with GCC; see the file COPYING. If not, write to |
| 39d14dda KC |
19 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
| 20 | ;; Boston, MA 02110-1301, USA. */ | |
| 30028c85 VM |
21 | ;; |
| 22 | ||
| 23 | /* This is description of pipeline hazards based on DFA. The | |
| 24 | following constructions can be used for this: | |
| 25 | ||
| 26 | o define_cpu_unit string [string]) describes a cpu functional unit | |
| 27 | (separated by comma). | |
| 28 | ||
| 29 | 1st operand: Names of cpu function units. | |
| 30 | 2nd operand: Name of automaton (see comments for | |
| 31 | DEFINE_AUTOMATON). | |
| 32 | ||
| 33 | All define_reservations and define_cpu_units should have unique | |
| 1e5f1716 | 34 | names which cannot be "nothing". |
| 30028c85 VM |
35 | |
| 36 | o (exclusion_set string string) means that each CPU function unit | |
| 1e5f1716 | 37 | in the first string cannot be reserved simultaneously with each |
| 30028c85 VM |
38 | unit whose name is in the second string and vise versa. CPU |
| 39 | units in the string are separated by commas. For example, it is | |
| 40 | useful for description CPU with fully pipelined floating point | |
| 41 | functional unit which can execute simultaneously only single | |
| 42 | floating point insns or only double floating point insns. | |
| 43 | ||
| 44 | o (presence_set string string) means that each CPU function unit in | |
| 1e5f1716 | 45 | the first string cannot be reserved unless at least one of |
| 30028c85 VM |
46 | pattern of units whose names are in the second string is |
| 47 | reserved. This is an asymmetric relation. CPU units or unit | |
| 48 | patterns in the strings are separated by commas. Pattern is one | |
| 49 | unit name or unit names separated by white-spaces. | |
| 50 | ||
| 51 | For example, it is useful for description that slot1 is reserved | |
| 52 | after slot0 reservation for a VLIW processor. We could describe | |
| 53 | it by the following construction | |
| 54 | ||
| 55 | (presence_set "slot1" "slot0") | |
| 56 | ||
| 57 | Or slot1 is reserved only after slot0 and unit b0 reservation. | |
| 58 | In this case we could write | |
| 59 | ||
| 60 | (presence_set "slot1" "slot0 b0") | |
| 61 | ||
| 62 | All CPU functional units in a set should belong to the same | |
| 63 | automaton. | |
| 64 | ||
| 65 | o (final_presence_set string string) is analogous to | |
| 66 | `presence_set'. The difference between them is when checking is | |
| 67 | done. When an instruction is issued in given automaton state | |
| 68 | reflecting all current and planned unit reservations, the | |
| 69 | automaton state is changed. The first state is a source state, | |
| 70 | the second one is a result state. Checking for `presence_set' is | |
| 71 | done on the source state reservation, checking for | |
| 72 | `final_presence_set' is done on the result reservation. This | |
| 73 | construction is useful to describe a reservation which is | |
| 74 | actually two subsequent reservations. For example, if we use | |
| 75 | ||
| 76 | (presence_set "slot1" "slot0") | |
| 77 | ||
| 78 | the following insn will be never issued (because slot1 requires | |
| 79 | slot0 which is absent in the source state). | |
| 80 | ||
| 81 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
| 82 | ||
| 83 | but it can be issued if we use analogous `final_presence_set'. | |
| 84 | ||
| 85 | o (absence_set string string) means that each CPU function unit in | |
| 86 | the first string can be reserved only if each pattern of units | |
| 87 | whose names are in the second string is not reserved. This is an | |
| 88 | asymmetric relation (actually exclusion set is analogous to this | |
| 89 | one but it is symmetric). CPU units or unit patterns in the | |
| 90 | string are separated by commas. Pattern is one unit name or unit | |
| 91 | names separated by white-spaces. | |
| 92 | ||
| 1e5f1716 | 93 | For example, it is useful for description that slot0 cannot be |
| 30028c85 VM |
94 | reserved after slot1 or slot2 reservation for a VLIW processor. |
| 95 | We could describe it by the following construction | |
| 96 | ||
| 97 | (absence_set "slot2" "slot0, slot1") | |
| 98 | ||
| 1e5f1716 | 99 | Or slot2 cannot be reserved if slot0 and unit b0 are reserved or |
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100 | slot1 and unit b1 are reserved . In this case we could write |
| 101 | ||
| 102 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
| 103 | ||
| 104 | All CPU functional units in a set should to belong the same | |
| 105 | automaton. | |
| 106 | ||
| 107 | o (final_absence_set string string) is analogous to `absence_set' but | |
| 108 | checking is done on the result (state) reservation. See comments | |
| 109 | for final_presence_set. | |
| 110 | ||
| 111 | o (define_bypass number out_insn_names in_insn_names) names bypass with | |
| 112 | given latency (the first number) from insns given by the first | |
| 113 | string (see define_insn_reservation) into insns given by the | |
| 114 | second string. Insn names in the strings are separated by | |
| 115 | commas. | |
| 116 | ||
| 117 | o (define_automaton string) describes names of an automaton | |
| 118 | generated and used for pipeline hazards recognition. The names | |
| 119 | are separated by comma. Actually it is possibly to generate the | |
| 120 | single automaton but unfortunately it can be very large. If we | |
| 121 | use more one automata, the summary size of the automata usually | |
| 122 | is less than the single one. The automaton name is used in | |
| 123 | define_cpu_unit. All automata should have unique names. | |
| 124 | ||
| 125 | o (automata_option string) describes option for generation of | |
| 126 | automata. Currently there are the following options: | |
| 127 | ||
| 128 | o "no-minimization" which makes no minimization of automata. | |
| 129 | This is only worth to do when we are debugging the description | |
| 130 | and need to look more accurately at reservations of states. | |
| 131 | ||
| 132 | o "ndfa" which makes automata with nondetermenistic reservation | |
| 133 | by insns. | |
| 134 | ||
| 135 | o (define_reservation string string) names reservation (the first | |
| 136 | string) of cpu functional units (the 2nd string). Sometimes unit | |
| 137 | reservations for different insns contain common parts. In such | |
| 138 | case, you describe common part and use one its name (the 1st | |
| 139 | parameter) in regular expression in define_insn_reservation. All | |
| 140 | define_reservations, define results and define_cpu_units should | |
| 1e5f1716 | 141 | have unique names which cannot be "nothing". |
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142 | |
| 143 | o (define_insn_reservation name default_latency condition regexpr) | |
| 144 | describes reservation of cpu functional units (the 3nd operand) | |
| 145 | for instruction which is selected by the condition (the 2nd | |
| 146 | parameter). The first parameter is used for output of debugging | |
| 147 | information. The reservations are described by a regular | |
| 148 | expression according the following syntax: | |
| 149 | ||
| 150 | regexp = regexp "," oneof | |
| 151 | | oneof | |
| 152 | ||
| 153 | oneof = oneof "|" allof | |
| 154 | | allof | |
| 155 | ||
| 156 | allof = allof "+" repeat | |
| 157 | | repeat | |
| 158 | ||
| 159 | repeat = element "*" number | |
| 160 | | element | |
| 161 | ||
| 162 | element = cpu_function_name | |
| 163 | | reservation_name | |
| 164 | | result_name | |
| 165 | | "nothing" | |
| 166 | | "(" regexp ")" | |
| 167 | ||
| 168 | 1. "," is used for describing start of the next cycle in | |
| 169 | reservation. | |
| 170 | ||
| 171 | 2. "|" is used for describing the reservation described by the | |
| 172 | first regular expression *or* the reservation described by | |
| 173 | the second regular expression *or* etc. | |
| 174 | ||
| 175 | 3. "+" is used for describing the reservation described by the | |
| 176 | first regular expression *and* the reservation described by | |
| 177 | the second regular expression *and* etc. | |
| 178 | ||
| 2a43945f | 179 | 4. "*" is used for convenience and simply means sequence in |
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180 | which the regular expression are repeated NUMBER times with |
| 181 | cycle advancing (see ","). | |
| 182 | ||
| 183 | 5. cpu function unit name which means reservation. | |
| 184 | ||
| 185 | 6. reservation name -- see define_reservation. | |
| 186 | ||
| 187 | 7. string "nothing" means no units reservation. | |
| 188 | ||
| 189 | */ | |
| 190 | ||
| 191 | (define_automaton "two") | |
| 192 | ||
| 193 | ;; All possible combinations of bundles/syllables | |
| 194 | (define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
| 195 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two") | |
| 196 | (define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
| 197 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two") | |
| 198 | (define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
| 199 | 2_0mib., 2_0mmb., 2_0mfb." "two") | |
| 200 | ||
| 201 | (define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
| 202 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two") | |
| 203 | (define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
| 204 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two") | |
| 205 | (define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
| 206 | 2_1mib., 2_1mmb., 2_1mfb." "two") | |
| 207 | ||
| 208 | ;; Slot 1 | |
| 209 | (exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
| 210 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 211 | (exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\ | |
| 212 | 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 213 | (exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\ | |
| 214 | 2_0m.fb, 2_0m.lx") | |
| 215 | (exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\ | |
| 216 | 2_0m.lx") | |
| 217 | (exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 218 | (exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 219 | (exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 220 | (exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx") | |
| 221 | (exclusion_set "2_0m.fb" "2_0m.lx") | |
| 222 | ||
| 223 | ;; Slot 2 | |
| 224 | (exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
| 225 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 226 | (exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ | |
| 227 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 228 | (exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\ | |
| 229 | 2_0mf.b, 2_0mlx.") | |
| 230 | (exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\ | |
| 231 | 2_0mlx.") | |
| 232 | (exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 233 | (exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 234 | (exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 235 | (exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.") | |
| 236 | (exclusion_set "2_0mf.b" "2_0mlx.") | |
| 237 | ||
| 238 | ;; Slot 3 | |
| 239 | (exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
| 240 | 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
| 241 | (exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ | |
| 242 | 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
| 243 | (exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\ | |
| 244 | 2_0mfb., 2_0mlx.") | |
| 245 | (exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\ | |
| 246 | 2_0mlx.") | |
| 247 | (exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
| 248 | (exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") | |
| 249 | (exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.") | |
| 250 | (exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.") | |
| 251 | (exclusion_set "2_0mfb." "2_0mlx.") | |
| 252 | ||
| 253 | ;; Slot 4 | |
| 254 | (exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
| 255 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
| 256 | (exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\ | |
| 257 | 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
| 258 | (exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\ | |
| 259 | 2_1m.fb, 2_1m.lx") | |
| 260 | (exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\ | |
| 261 | 2_1m.lx") | |
| 262 | (exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
| 263 | (exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") | |
| 264 | (exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx") | |
| 265 | (exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx") | |
| 266 | (exclusion_set "2_1m.fb" "2_1m.lx") | |
| 267 | ||
| 268 | ;; Slot 5 | |
| 269 | (exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
| 270 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
| 271 | (exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ | |
| 272 | 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
| 273 | (exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\ | |
| 274 | 2_1mf.b, 2_1mlx.") | |
| 275 | (exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\ | |
| 276 | 2_1mlx.") | |
| 277 | (exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
| 278 | (exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") | |
| 279 | (exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.") | |
| 280 | (exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.") | |
| 281 | (exclusion_set "2_1mf.b" "2_1mlx.") | |
| 282 | ||
| 283 | ;; Slot 6 | |
| 284 | (exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
| 285 | 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
| 286 | (exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ | |
| 287 | 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
| 288 | (exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\ | |
| 289 | 2_1mfb., 2_1mlx.") | |
| 290 | (exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\ | |
| 291 | 2_1mlx.") | |
| 292 | (exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
| 293 | (exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") | |
| 294 | (exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.") | |
| 295 | (exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.") | |
| 296 | (exclusion_set "2_1mfb." "2_1mlx.") | |
| 297 | ||
| 298 | (final_presence_set "2_0mi.i" "2_0m.ii") | |
| 299 | (final_presence_set "2_0mii." "2_0mi.i") | |
| 300 | (final_presence_set "2_1mi.i" "2_1m.ii") | |
| 301 | (final_presence_set "2_1mii." "2_1mi.i") | |
| 302 | ||
| 303 | (final_presence_set "2_0mm.i" "2_0m.mi") | |
| 304 | (final_presence_set "2_0mmi." "2_0mm.i") | |
| 305 | (final_presence_set "2_1mm.i" "2_1m.mi") | |
| 306 | (final_presence_set "2_1mmi." "2_1mm.i") | |
| 307 | ||
| 308 | (final_presence_set "2_0mf.i" "2_0m.fi") | |
| 309 | (final_presence_set "2_0mfi." "2_0mf.i") | |
| 310 | (final_presence_set "2_1mf.i" "2_1m.fi") | |
| 311 | (final_presence_set "2_1mfi." "2_1mf.i") | |
| 312 | ||
| 313 | (final_presence_set "2_0mm.f" "2_0m.mf") | |
| 314 | (final_presence_set "2_0mmf." "2_0mm.f") | |
| 315 | (final_presence_set "2_1mm.f" "2_1m.mf") | |
| 316 | (final_presence_set "2_1mmf." "2_1mm.f") | |
| 317 | ||
| 318 | (final_presence_set "2_0bb.b" "2_0b.bb") | |
| 319 | (final_presence_set "2_0bbb." "2_0bb.b") | |
| 320 | (final_presence_set "2_1bb.b" "2_1b.bb") | |
| 321 | (final_presence_set "2_1bbb." "2_1bb.b") | |
| 322 | ||
| 323 | (final_presence_set "2_0mb.b" "2_0m.bb") | |
| 324 | (final_presence_set "2_0mbb." "2_0mb.b") | |
| 325 | (final_presence_set "2_1mb.b" "2_1m.bb") | |
| 326 | (final_presence_set "2_1mbb." "2_1mb.b") | |
| 327 | ||
| 328 | (final_presence_set "2_0mi.b" "2_0m.ib") | |
| 329 | (final_presence_set "2_0mib." "2_0mi.b") | |
| 330 | (final_presence_set "2_1mi.b" "2_1m.ib") | |
| 331 | (final_presence_set "2_1mib." "2_1mi.b") | |
| 332 | ||
| 333 | (final_presence_set "2_0mm.b" "2_0m.mb") | |
| 334 | (final_presence_set "2_0mmb." "2_0mm.b") | |
| 335 | (final_presence_set "2_1mm.b" "2_1m.mb") | |
| 336 | (final_presence_set "2_1mmb." "2_1mm.b") | |
| 337 | ||
| 338 | (final_presence_set "2_0mf.b" "2_0m.fb") | |
| 339 | (final_presence_set "2_0mfb." "2_0mf.b") | |
| 340 | (final_presence_set "2_1mf.b" "2_1m.fb") | |
| 341 | (final_presence_set "2_1mfb." "2_1mf.b") | |
| 342 | ||
| 343 | (final_presence_set "2_0mlx." "2_0m.lx") | |
| 344 | (final_presence_set "2_1mlx." "2_1m.lx") | |
| 345 | ||
| 346 | ;; The following reflects the dual issue bundle types table. | |
| 347 | ;; We could place all possible combinations here because impossible | |
| 348 | ;; combinations would go away by the subsequent constrains. | |
| 349 | (final_presence_set | |
| 350 | "2_1m.lx" | |
| 351 | "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") | |
| 352 | (final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.") | |
| 353 | (final_presence_set | |
| 354 | "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb" | |
| 355 | "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") | |
| 356 | ||
| 357 | ;; Ports/units (nb means nop.b insn issued into given port): | |
| 358 | (define_cpu_unit | |
| 359 | "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\ | |
| 360 | 2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two") | |
| 361 | ||
| 362 | (exclusion_set "2_ub0" "2_unb0") | |
| 363 | (exclusion_set "2_ub1" "2_unb1") | |
| 364 | (exclusion_set "2_ub2" "2_unb2") | |
| 365 | ||
| 366 | ;; The following rules are used to decrease number of alternatives. | |
| 367 | ;; They are consequences of Itanium2 microarchitecture. They also | |
| 368 | ;; describe the following rules mentioned in Itanium2 | |
| 369 | ;; microarchitecture: rules mentioned in Itanium2 microarchitecture: | |
| 370 | ;; o "BBB/MBB: Always splits issue after either of these bundles". | |
| 371 | ;; o "MIB BBB: Split issue after the first bundle in this pair". | |
| 372 | (exclusion_set | |
| 373 | "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb." | |
| 374 | "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\ | |
| 375 | 2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx") | |
| 376 | (exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb") | |
| 377 | ||
| 378 | ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the | |
| 379 | ;;; B-slot contains a nop.b or a brp instruction". | |
| 380 | ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or | |
| 381 | ;;; nop.b, otherwise it disperses to B2". | |
| 382 | (final_absence_set | |
| 383 | "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ | |
| 384 | 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" | |
| 385 | "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2") | |
| 386 | ||
| 387 | ;; This is necessary to start new processor cycle when we meet stop bit. | |
| 388 | (define_cpu_unit "2_stop" "two") | |
| 389 | (final_absence_set | |
| 390 | "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ | |
| 391 | 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ | |
| 392 | 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ | |
| 393 | 2_0m.lx,2_0mlx., \ | |
| 394 | 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ | |
| 395 | 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ | |
| 396 | 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ | |
| 397 | 2_1m.lx,2_1mlx." | |
| 398 | "2_stop") | |
| 399 | ||
| 400 | ;; The issue logic can reorder M slot insns between different subtypes | |
| 1e5f1716 | 401 | ;; but cannot reorder insn within the same subtypes. The following |
| 30028c85 VM |
402 | ;; constraint is enough to describe this. |
| 403 | (final_presence_set "2_um1" "2_um0") | |
| 404 | (final_presence_set "2_um3" "2_um2") | |
| 405 | ||
| 406 | ;; The insn in the 1st I slot of the two bundle issue group will issue | |
| 407 | ;; to I0. The second I slot insn will issue to I1. | |
| 408 | (final_presence_set "2_ui1" "2_ui0") | |
| 409 | ||
| 410 | ;; For exceptions of I insns: | |
| 411 | (define_cpu_unit "2_only_ui0" "two") | |
| 412 | (final_absence_set "2_only_ui0" "2_ui1") | |
| 413 | ||
| 414 | ;; Insns | |
| 415 | ||
| 416 | (define_reservation "2_M0" | |
| 417 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
| 418 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
| 419 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
| 420 | +(2_um0|2_um1|2_um2|2_um3)") | |
| 421 | ||
| 422 | (define_reservation "2_M1" | |
| 423 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 424 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
| 425 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
| 426 | +(2_um0|2_um1|2_um2|2_um3)") | |
| 427 | ||
| 428 | (define_reservation "2_M" "2_M0|2_M1") | |
| 429 | ||
| 430 | (define_reservation "2_M0_only_um0" | |
| 431 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
| 432 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
| 433 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
| 434 | +2_um0") | |
| 435 | ||
| 436 | (define_reservation "2_M1_only_um0" | |
| 437 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 438 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
| 439 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
| 440 | +2_um0") | |
| 441 | ||
| 442 | (define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0") | |
| 443 | ||
| 444 | (define_reservation "2_M0_only_um2" | |
| 445 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
| 446 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
| 447 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
| 448 | +2_um2") | |
| 449 | ||
| 450 | (define_reservation "2_M1_only_um2" | |
| 451 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 452 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
| 453 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
| 454 | +2_um2") | |
| 455 | ||
| 456 | (define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2") | |
| 457 | ||
| 458 | (define_reservation "2_M0_only_um23" | |
| 459 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
| 460 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
| 461 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
| 462 | +(2_um2|2_um3)") | |
| 463 | ||
| 464 | (define_reservation "2_M1_only_um23" | |
| 465 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 466 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
| 467 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
| 468 | +(2_um2|2_um3)") | |
| 469 | ||
| 470 | (define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23") | |
| 471 | ||
| 472 | (define_reservation "2_M0_only_um01" | |
| 473 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ | |
| 474 | |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ | |
| 475 | |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ | |
| 476 | +(2_um0|2_um1)") | |
| 477 | ||
| 478 | (define_reservation "2_M1_only_um01" | |
| 479 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 480 | |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ | |
| 481 | +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ | |
| 482 | +(2_um0|2_um1)") | |
| 483 | ||
| 484 | (define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01") | |
| 485 | ||
| 486 | ;; I instruction is dispersed to the lowest numbered I unit | |
| 1ae58c30 | 487 | ;; not already in use. Remember about possible splitting. |
| 30028c85 VM |
488 | (define_reservation "2_I0" |
| 489 | "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\ | |
| 490 | |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\ | |
| 491 | |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)") | |
| 492 | ||
| 493 | (define_reservation "2_I1" | |
| 494 | "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\ | |
| 495 | |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\ | |
| 496 | |2_0mf.i+2_uf0+2_0mfi.+2_ui0\ | |
| 497 | |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\ | |
| 498 | |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\ | |
| 499 | |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\ | |
| 500 | |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)") | |
| 501 | ||
| 502 | (define_reservation "2_I" "2_I0|2_I1") | |
| 503 | ||
| 504 | ;; "An F slot in the 1st bundle disperses to F0". | |
| 505 | ;; "An F slot in the 2st bundle disperses to F1". | |
| 506 | (define_reservation "2_F0" | |
| 507 | "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\ | |
| 508 | |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1") | |
| 509 | ||
| 510 | (define_reservation "2_F1" | |
| 511 | "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\ | |
| 512 | +(2_um0|2_um1|2_um2|2_um3)+2_uf0\ | |
| 513 | |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\ | |
| 514 | +(2_um0|2_um1|2_um2|2_um3)+2_uf1") | |
| 515 | ||
| 516 | (define_reservation "2_F2" | |
| 517 | "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\ | |
| 518 | +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\ | |
| 519 | |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\ | |
| 520 | |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\ | |
| 521 | |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\ | |
| 522 | +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1") | |
| 523 | ||
| 524 | (define_reservation "2_F" "2_F0|2_F1|2_F2") | |
| 525 | ||
| 526 | ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B | |
| 2a43945f | 527 | ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the |
| 30028c85 VM |
528 | ;;; 2nd position it is dispersed to B2". |
| 529 | (define_reservation "2_NB" | |
| 530 | "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\ | |
| 531 | |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\ | |
| 532 | |2_0mmb.+2_unb0|2_0mfb.+2_unb0\ | |
| 533 | |2_1b.bb+2_unb0|2_1bb.b+2_unb1 | |
| 534 | |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\ | |
| 535 | |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0") | |
| 536 | ||
| 537 | (define_reservation "2_B0" | |
| 538 | "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\ | |
| 539 | |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\ | |
| 540 | |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\ | |
| 541 | |2_1bbb.+2_ub2|2_1mb.b+2_ub1\ | |
| 542 | |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2") | |
| 543 | ||
| 544 | (define_reservation "2_B1" | |
| 545 | "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\ | |
| 546 | |2_0mi.b+2_ui0+2_0mib.+2_ub2\ | |
| 547 | |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\ | |
| 548 | |2_0mf.b+2_uf0+2_0mfb.+2_ub2\ | |
| 549 | |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\ | |
| 550 | +2_1b.bb+2_ub0\ | |
| 551 | |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\ | |
| 552 | |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\ | |
| 553 | |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\ | |
| 554 | |2_1mf.b+2_uf1+2_1mfb.+2_ub2") | |
| 555 | ||
| 556 | (define_reservation "2_B" "2_B0|2_B1") | |
| 557 | ||
| 558 | ;; MLX bunlde uses ports equivalent to MFI bundles. | |
| 559 | ||
| 560 | ;; For the MLI template, the I slot insn is always assigned to port I0 | |
| 561 | ;; if it is in the first bundle or it is assigned to port I1 if it is in | |
| 562 | ;; the second bundle. | |
| 563 | (define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1") | |
| 564 | ||
| 565 | (define_reservation "2_L1" | |
| 566 | "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\ | |
| 567 | |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") | |
| 568 | ||
| 569 | (define_reservation "2_L2" | |
| 570 | "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ | |
| 571 | |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0) | |
| 572 | +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") | |
| 573 | ||
| 574 | (define_reservation "2_L" "2_L0|2_L1|2_L2") | |
| 575 | ||
| 576 | ;; Should we describe that A insn in I slot can be issued into M | |
| 577 | ;; ports? I think it is not necessary because of multipass | |
| 578 | ;; scheduling. For example, the multipass scheduling could use | |
| 579 | ;; MMI-MMI instead of MII-MII where the two last I slots contain A | |
| 580 | ;; insns (even if the case is complicated by use-def conflicts). | |
| 581 | ;; | |
| 582 | ;; In any case we could describe it as | |
| 583 | ;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two") | |
| 584 | ;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" | |
| 585 | ;; "2_ui1") | |
| 586 | ;; (define_reservation "b_A" | |
| 587 | ;; "b_M|b_I\ | |
| 588 | ;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\ | |
| 589 | ;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)") | |
| 590 | ||
| 591 | (define_reservation "2_A" "2_M|2_I") | |
| 592 | ||
| 593 | ;; We assume that there is no insn issued on the same cycle as the | |
| 594 | ;; unknown insn. | |
| 595 | (define_cpu_unit "2_empty" "two") | |
| 596 | (exclusion_set "2_empty" | |
| 597 | "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\ | |
| 598 | 2_0m.lx") | |
| 599 | ||
| 600 | (define_cpu_unit | |
| 601 | "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs" | |
| 602 | "two") | |
| 603 | (define_cpu_unit | |
| 604 | "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" | |
| 605 | "two") | |
| 606 | ||
| 607 | (define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\ | |
| 608 | 2_b_cont, 2_bb_cont" "two") | |
| 609 | ||
| 610 | ;; For stop in the middle of the bundles. | |
| 611 | (define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two") | |
| 612 | (define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two") | |
| 613 | ||
| 614 | (final_presence_set "2_0m_bs" | |
| 615 | "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\ | |
| 616 | 2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx") | |
| 617 | (final_presence_set "2_1m_bs" | |
| 618 | "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\ | |
| 619 | 2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx") | |
| 620 | (final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i") | |
| 621 | (final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i") | |
| 622 | (final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b") | |
| 623 | (final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b") | |
| 624 | (final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b") | |
| 625 | (final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b") | |
| 626 | (final_presence_set "2_0b_bs" "2_0b.bb") | |
| 627 | (final_presence_set "2_1b_bs" "2_1b.bb") | |
| 628 | (final_presence_set "2_0bb_bs" "2_0bb.b") | |
| 629 | (final_presence_set "2_1bb_bs" "2_1bb.b") | |
| 630 | (final_presence_set "2_0mb_bs" "2_0mb.b") | |
| 631 | (final_presence_set "2_1mb_bs" "2_1mb.b") | |
| 632 | ||
| 633 | (exclusion_set "2_0m_bs" | |
| 634 | "2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\ | |
| 635 | 2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop") | |
| 636 | (exclusion_set "2_1m_bs" | |
| 637 | "2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\ | |
| 638 | 2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop") | |
| 639 | (exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop") | |
| 640 | (exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop") | |
| 641 | (exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.") | |
| 642 | (exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.") | |
| 643 | (exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.") | |
| 644 | (exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.") | |
| 645 | (exclusion_set "2_0b_bs" "2_0bb.b") | |
| 646 | (exclusion_set "2_1b_bs" "2_1bb.b") | |
| 647 | (exclusion_set "2_0bb_bs" "2_0bbb.") | |
| 648 | (exclusion_set "2_1bb_bs" "2_1bbb.") | |
| 649 | (exclusion_set "2_0mb_bs" "2_0mbb.") | |
| 650 | (exclusion_set "2_1mb_bs" "2_1mbb.") | |
| 651 | ||
| 652 | (exclusion_set | |
| 653 | "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs, | |
| 654 | 2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" | |
| 655 | "2_stop") | |
| 656 | ||
| 657 | (final_presence_set | |
| 658 | "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ | |
| 659 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." | |
| 660 | "2_m_cont") | |
| 661 | (final_presence_set "2_0mii., 2_0mib." "2_mi_cont") | |
| 662 | (final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont") | |
| 663 | (final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont") | |
| 664 | (final_presence_set "2_0bb.b" "2_b_cont") | |
| 665 | (final_presence_set "2_0bbb." "2_bb_cont") | |
| 666 | (final_presence_set "2_0mbb." "2_mb_cont") | |
| 667 | ||
| 668 | (exclusion_set | |
| 669 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
| 670 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" | |
| 671 | "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\ | |
| 672 | 2_mb_cont, 2_b_cont, 2_bb_cont") | |
| 673 | ||
| 674 | (exclusion_set "2_empty" | |
| 675 | "2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\ | |
| 676 | 2_mb_cont,2_b_cont,2_bb_cont") | |
| 677 | ||
| 678 | ;; For m;mi bundle | |
| 679 | (final_presence_set "2_m0_stop" "2_0m.mi") | |
| 680 | (final_presence_set "2_0mm.i" "2_0mmi_cont") | |
| 681 | (exclusion_set "2_0mmi_cont" | |
| 682 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
| 683 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 684 | (exclusion_set "2_m0_stop" "2_0mm.i") | |
| 685 | (final_presence_set "2_m1_stop" "2_1m.mi") | |
| 686 | (exclusion_set "2_m1_stop" "2_1mm.i") | |
| 687 | (final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop") | |
| 688 | ||
| 689 | ;; For mi;i bundle | |
| 690 | (final_presence_set "2_mi0_stop" "2_0mi.i") | |
| 691 | (final_presence_set "2_0mii." "2_0mii_cont") | |
| 692 | (exclusion_set "2_0mii_cont" | |
| 693 | "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ | |
| 694 | 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") | |
| 695 | (exclusion_set "2_mi0_stop" "2_0mii.") | |
| 696 | (final_presence_set "2_mi1_stop" "2_1mi.i") | |
| 697 | (exclusion_set "2_mi1_stop" "2_1mii.") | |
| 698 | (final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop") | |
| 699 | ||
| 700 | (final_absence_set | |
| 701 | "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ | |
| 702 | 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ | |
| 703 | 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ | |
| 704 | 2_0m.lx,2_0mlx., \ | |
| 705 | 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ | |
| 706 | 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ | |
| 707 | 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ | |
| 708 | 2_1m.lx,2_1mlx." | |
| 709 | "2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop") | |
| 710 | ||
| 711 | (define_insn_reservation "2_stop_bit" 0 | |
| 712 | (and (and (eq_attr "cpu" "itanium2") | |
| 713 | (eq_attr "itanium_class" "stop_bit")) | |
| 714 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 715 | "2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop") | |
| 716 | ||
| 717 | (define_insn_reservation "2_br" 0 | |
| 718 | (and (and (eq_attr "cpu" "itanium2") | |
| 719 | (eq_attr "itanium_class" "br")) | |
| 720 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_B") | |
| 721 | (define_insn_reservation "2_scall" 0 | |
| 722 | (and (and (eq_attr "cpu" "itanium2") | |
| 723 | (eq_attr "itanium_class" "scall")) | |
| 724 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_B") | |
| 725 | (define_insn_reservation "2_fcmp" 2 | |
| 726 | (and (and (eq_attr "cpu" "itanium2") | |
| 727 | (eq_attr "itanium_class" "fcmp")) | |
| 728 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") | |
| 729 | (define_insn_reservation "2_fcvtfx" 4 | |
| 730 | (and (and (eq_attr "cpu" "itanium2") | |
| 731 | (eq_attr "itanium_class" "fcvtfx")) | |
| 732 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") | |
| 733 | (define_insn_reservation "2_fld" 6 | |
| 734 | (and (and (eq_attr "cpu" "itanium2") | |
| 735 | (eq_attr "itanium_class" "fld")) | |
| 736 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_M") | |
| 737 | (define_insn_reservation "2_fmac" 4 | |
| 738 | (and (and (eq_attr "cpu" "itanium2") | |
| 739 | (eq_attr "itanium_class" "fmac")) | |
| 740 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") | |
| 741 | (define_insn_reservation "2_fmisc" 4 | |
| 742 | (and (and (eq_attr "cpu" "itanium2") | |
| 743 | (eq_attr "itanium_class" "fmisc")) | |
| 744 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") | |
| 745 | ||
| 746 | ;; There is only one insn `mov = ar.bsp' for frar_i: | |
| 747 | ;; Latency time ??? | |
| 748 | (define_insn_reservation "2_frar_i" 13 | |
| 749 | (and (and (eq_attr "cpu" "itanium2") | |
| 750 | (eq_attr "itanium_class" "frar_i")) | |
| 751 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 752 | "2_I+2_only_ui0") | |
| 753 | ;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: | |
| 754 | ;; Latency time ??? | |
| 755 | (define_insn_reservation "2_frar_m" 6 | |
| 756 | (and (and (eq_attr "cpu" "itanium2") | |
| 757 | (eq_attr "itanium_class" "frar_m")) | |
| 758 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 759 | "2_M_only_um2") | |
| 760 | (define_insn_reservation "2_frbr" 2 | |
| 761 | (and (and (eq_attr "cpu" "itanium2") | |
| 762 | (eq_attr "itanium_class" "frbr")) | |
| 763 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 764 | "2_I+2_only_ui0") | |
| 765 | (define_insn_reservation "2_frfr" 5 | |
| 766 | (and (and (eq_attr "cpu" "itanium2") | |
| 767 | (eq_attr "itanium_class" "frfr")) | |
| 768 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 769 | "2_M_only_um2") | |
| 770 | (define_insn_reservation "2_frpr" 2 | |
| 771 | (and (and (eq_attr "cpu" "itanium2") | |
| 772 | (eq_attr "itanium_class" "frpr")) | |
| 773 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 774 | "2_I+2_only_ui0") | |
| 775 | ||
| 776 | (define_insn_reservation "2_ialu" 1 | |
| 777 | (and (and (eq_attr "cpu" "itanium2") | |
| 778 | (eq_attr "itanium_class" "ialu")) | |
| 779 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 780 | "2_A") | |
| 781 | (define_insn_reservation "2_icmp" 1 | |
| 782 | (and (and (eq_attr "cpu" "itanium2") | |
| 783 | (eq_attr "itanium_class" "icmp")) | |
| 784 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_A") | |
| 785 | (define_insn_reservation "2_ilog" 1 | |
| 786 | (and (and (eq_attr "cpu" "itanium2") | |
| 787 | (eq_attr "itanium_class" "ilog")) | |
| 788 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_A") | |
| f61134e8 RH |
789 | (define_insn_reservation "2_mmalua" 2 |
| 790 | (and (and (eq_attr "cpu" "itanium2") | |
| 791 | (eq_attr "itanium_class" "mmalua")) | |
| 792 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_A") | |
| 30028c85 VM |
793 | ;; Latency time ??? |
| 794 | (define_insn_reservation "2_ishf" 1 | |
| 795 | (and (and (eq_attr "cpu" "itanium2") | |
| 796 | (eq_attr "itanium_class" "ishf")) | |
| 797 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 798 | "2_I+2_only_ui0") | |
| 799 | (define_insn_reservation "2_ld" 1 | |
| 800 | (and (and (eq_attr "cpu" "itanium2") | |
| 801 | (eq_attr "itanium_class" "ld")) | |
| 802 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 803 | "2_M_only_um01") | |
| 804 | (define_insn_reservation "2_long_i" 1 | |
| 805 | (and (and (eq_attr "cpu" "itanium2") | |
| 806 | (eq_attr "itanium_class" "long_i")) | |
| 807 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_L") | |
| 808 | ||
| 809 | (define_insn_reservation "2_mmmul" 2 | |
| 810 | (and (and (eq_attr "cpu" "itanium2") | |
| 811 | (eq_attr "itanium_class" "mmmul")) | |
| 812 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 813 | "2_I+2_only_ui0") | |
| 814 | ;; Latency time ??? | |
| 815 | (define_insn_reservation "2_mmshf" 2 | |
| 816 | (and (and (eq_attr "cpu" "itanium2") | |
| 817 | (eq_attr "itanium_class" "mmshf")) | |
| 818 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") | |
| 819 | ;; Latency time ??? | |
| 820 | (define_insn_reservation "2_mmshfi" 1 | |
| 821 | (and (and (eq_attr "cpu" "itanium2") | |
| 822 | (eq_attr "itanium_class" "mmshfi")) | |
| 823 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") | |
| 824 | ||
| 825 | ;; Now we have only one insn (flushrs) of such class. We assume that flushrs | |
| 826 | ;; is the 1st syllable of the bundle after stop bit. | |
| 827 | (define_insn_reservation "2_rse_m" 0 | |
| 828 | (and (and (eq_attr "cpu" "itanium2") | |
| 829 | (eq_attr "itanium_class" "rse_m")) | |
| 830 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 831 | "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\ | |
| 832 | |2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0") | |
| 833 | (define_insn_reservation "2_sem" 0 | |
| 834 | (and (and (eq_attr "cpu" "itanium2") | |
| 835 | (eq_attr "itanium_class" "sem")) | |
| 836 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 837 | "2_M_only_um23") | |
| 838 | ||
| 839 | (define_insn_reservation "2_stf" 1 | |
| 840 | (and (and (eq_attr "cpu" "itanium2") | |
| 841 | (eq_attr "itanium_class" "stf")) | |
| 842 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 843 | "2_M_only_um23") | |
| 844 | (define_insn_reservation "2_st" 1 | |
| 845 | (and (and (eq_attr "cpu" "itanium2") | |
| 846 | (eq_attr "itanium_class" "st")) | |
| 847 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 848 | "2_M_only_um23") | |
| 849 | (define_insn_reservation "2_syst_m0" 0 | |
| 850 | (and (and (eq_attr "cpu" "itanium2") | |
| 851 | (eq_attr "itanium_class" "syst_m0")) | |
| 852 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 853 | "2_M_only_um2") | |
| 854 | (define_insn_reservation "2_syst_m" 0 | |
| 855 | (and (and (eq_attr "cpu" "itanium2") | |
| 856 | (eq_attr "itanium_class" "syst_m")) | |
| 857 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 858 | "2_M_only_um0") | |
| 859 | ;; Reservation??? | |
| 860 | (define_insn_reservation "2_tbit" 1 | |
| 861 | (and (and (eq_attr "cpu" "itanium2") | |
| 862 | (eq_attr "itanium_class" "tbit")) | |
| 863 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 864 | "2_I+2_only_ui0") | |
| 865 | ||
| 866 | ;; There is only ony insn `mov ar.pfs =' for toar_i: | |
| 867 | (define_insn_reservation "2_toar_i" 0 | |
| 868 | (and (and (eq_attr "cpu" "itanium2") | |
| 869 | (eq_attr "itanium_class" "toar_i")) | |
| 870 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 871 | "2_I+2_only_ui0") | |
| 872 | ;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: | |
| 873 | ;; Latency time ??? | |
| 874 | (define_insn_reservation "2_toar_m" 5 | |
| 875 | (and (and (eq_attr "cpu" "itanium2") | |
| 876 | (eq_attr "itanium_class" "toar_m")) | |
| 877 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 878 | "2_M_only_um2") | |
| 879 | ;; Latency time ??? | |
| 880 | (define_insn_reservation "2_tobr" 1 | |
| 881 | (and (and (eq_attr "cpu" "itanium2") | |
| 882 | (eq_attr "itanium_class" "tobr")) | |
| 883 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 884 | "2_I+2_only_ui0") | |
| 885 | (define_insn_reservation "2_tofr" 5 | |
| 886 | (and (and (eq_attr "cpu" "itanium2") | |
| 887 | (eq_attr "itanium_class" "tofr")) | |
| 888 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 889 | "2_M_only_um23") | |
| 890 | ;; Latency time ??? | |
| 891 | (define_insn_reservation "2_topr" 1 | |
| 892 | (and (and (eq_attr "cpu" "itanium2") | |
| 893 | (eq_attr "itanium_class" "topr")) | |
| 894 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 895 | "2_I+2_only_ui0") | |
| 896 | ||
| 897 | (define_insn_reservation "2_xmpy" 4 | |
| 898 | (and (and (eq_attr "cpu" "itanium2") | |
| 899 | (eq_attr "itanium_class" "xmpy")) | |
| 900 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F") | |
| 901 | ;; Latency time ??? | |
| 902 | (define_insn_reservation "2_xtd" 1 | |
| 903 | (and (and (eq_attr "cpu" "itanium2") | |
| 904 | (eq_attr "itanium_class" "xtd")) | |
| 905 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_I") | |
| 906 | ||
| 907 | (define_insn_reservation "2_chk_s" 0 | |
| 908 | (and (and (eq_attr "cpu" "itanium2") | |
| 909 | (eq_attr "itanium_class" "chk_s")) | |
| 910 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 911 | "2_I|2_M_only_um23") | |
| 912 | (define_insn_reservation "2_lfetch" 0 | |
| 913 | (and (and (eq_attr "cpu" "itanium2") | |
| 914 | (eq_attr "itanium_class" "lfetch")) | |
| 915 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 916 | "2_M_only_um01") | |
| 917 | ||
| 918 | (define_insn_reservation "2_nop_m" 0 | |
| 919 | (and (and (eq_attr "cpu" "itanium2") | |
| 920 | (eq_attr "itanium_class" "nop_m")) | |
| 921 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_M0") | |
| 922 | (define_insn_reservation "2_nop_b" 0 | |
| 923 | (and (and (eq_attr "cpu" "itanium2") | |
| 924 | (eq_attr "itanium_class" "nop_b")) | |
| 925 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_NB") | |
| 926 | (define_insn_reservation "2_nop_i" 0 | |
| 927 | (and (and (eq_attr "cpu" "itanium2") | |
| 928 | (eq_attr "itanium_class" "nop_i")) | |
| 929 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_I0") | |
| 930 | (define_insn_reservation "2_nop_f" 0 | |
| 931 | (and (and (eq_attr "cpu" "itanium2") | |
| 932 | (eq_attr "itanium_class" "nop_f")) | |
| 933 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_F0") | |
| 934 | (define_insn_reservation "2_nop_x" 0 | |
| 935 | (and (and (eq_attr "cpu" "itanium2") | |
| 936 | (eq_attr "itanium_class" "nop_x")) | |
| 937 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_L0") | |
| 938 | ||
| 939 | (define_insn_reservation "2_unknown" 1 | |
| 940 | (and (and (eq_attr "cpu" "itanium2") | |
| 941 | (eq_attr "itanium_class" "unknown")) | |
| 942 | (eq (symbol_ref "bundling_p") (const_int 0))) "2_empty") | |
| 943 | ||
| 944 | (define_insn_reservation "2_nop" 0 | |
| 945 | (and (and (eq_attr "cpu" "itanium2") | |
| 946 | (eq_attr "itanium_class" "nop")) | |
| 947 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 948 | "2_M0|2_NB|2_I0|2_F0") | |
| 949 | ||
| 950 | (define_insn_reservation "2_ignore" 0 | |
| 951 | (and (and (eq_attr "cpu" "itanium2") | |
| 952 | (eq_attr "itanium_class" "ignore")) | |
| 953 | (eq (symbol_ref "bundling_p") (const_int 0))) "nothing") | |
| 954 | ||
| 955 | (define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two") | |
| 956 | (define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two") | |
| 957 | (define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two") | |
| 958 | ||
| 959 | (final_presence_set "2_m_cont_only" "2_m_cont") | |
| 960 | (exclusion_set "2_m_cont_only" | |
| 961 | "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ | |
| 962 | 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") | |
| 963 | ||
| 964 | (final_presence_set "2_b_cont_only" "2_b_cont") | |
| 965 | (exclusion_set "2_b_cont_only" "2_0bb.b") | |
| 966 | ||
| 967 | (final_presence_set "2_mi_cont_only" "2_mi_cont") | |
| 968 | (exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.") | |
| 969 | ||
| 970 | (final_presence_set "2_mm_cont_only" "2_mm_cont") | |
| 971 | (exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.") | |
| 972 | ||
| 973 | (final_presence_set "2_mf_cont_only" "2_mf_cont") | |
| 974 | (exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.") | |
| 975 | ||
| 976 | (final_presence_set "2_mb_cont_only" "2_mb_cont") | |
| 977 | (exclusion_set "2_mb_cont_only" "2_0mbb.") | |
| 978 | ||
| 979 | (final_presence_set "2_bb_cont_only" "2_bb_cont") | |
| 980 | (exclusion_set "2_bb_cont_only" "2_0bbb.") | |
| 981 | ||
| 982 | (define_insn_reservation "2_pre_cycle" 0 | |
| 983 | (and (and (eq_attr "cpu" "itanium2") | |
| 984 | (eq_attr "itanium_class" "pre_cycle")) | |
| 985 | (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 986 | "nothing") | |
| 987 | ||
| 988 | ;;(define_insn_reservation "2_pre_cycle" 0 | |
| 989 | ;; (and (and (eq_attr "cpu" "itanium2") | |
| 990 | ;; (eq_attr "itanium_class" "pre_cycle")) | |
| 991 | ;; (eq (symbol_ref "bundling_p") (const_int 0))) | |
| 992 | ;; "(2_0m_bs, 2_m_cont) \ | |
| 993 | ;; | (2_0mi_bs, (2_mi_cont|nothing)) \ | |
| 994 | ;; | (2_0mm_bs, 2_mm_cont) \ | |
| 995 | ;; | (2_0mf_bs, (2_mf_cont|nothing)) \ | |
| 996 | ;; | (2_0b_bs, (2_b_cont|nothing)) \ | |
| 997 | ;; | (2_0bb_bs, (2_bb_cont|nothing)) \ | |
| 998 | ;; | (2_0mb_bs, (2_mb_cont|nothing)) \ | |
| 999 | ;; | (2_1m_bs, 2_m_cont) \ | |
| 1000 | ;; | (2_1mi_bs, (2_mi_cont|nothing)) \ | |
| 1001 | ;; | (2_1mm_bs, 2_mm_cont) \ | |
| 1002 | ;; | (2_1mf_bs, (2_mf_cont|nothing)) \ | |
| 1003 | ;; | (2_1b_bs, (2_b_cont|nothing)) \ | |
| 1004 | ;; | (2_1bb_bs, (2_bb_cont|nothing)) \ | |
| 1005 | ;; | (2_1mb_bs, (2_mb_cont|nothing)) \ | |
| 1006 | ;; | (2_m_cont_only, (2_m_cont|nothing)) \ | |
| 1007 | ;; | (2_b_cont_only, (2_b_cont|nothing)) \ | |
| 1008 | ;; | (2_mi_cont_only, (2_mi_cont|nothing)) \ | |
| 1009 | ;; | (2_mm_cont_only, (2_mm_cont|nothing)) \ | |
| 1010 | ;; | (2_mf_cont_only, (2_mf_cont|nothing)) \ | |
| 1011 | ;; | (2_mb_cont_only, (2_mb_cont|nothing)) \ | |
| 1012 | ;; | (2_bb_cont_only, (2_bb_cont|nothing)) \ | |
| 1013 | ;; | (2_m_stop, (2_0mmi_cont|nothing)) \ | |
| 1014 | ;; | (2_mi_stop, (2_0mii_cont|nothing))") | |
| 1015 | ||
| 1016 | ;; Bypasses: | |
| 1017 | ||
| 1018 | (define_bypass 1 "2_fcmp" "2_br,2_scall") | |
| 1019 | (define_bypass 0 "2_icmp" "2_br,2_scall") | |
| 1020 | (define_bypass 0 "2_tbit" "2_br,2_scall") | |
| 1021 | (define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") | |
| 1022 | (define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") | |
| f61134e8 RH |
1023 | (define_bypass 2 "2_ld" "2_mmalua,2_mmmul,2_mmshf") |
| 1024 | (define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf") | |
| 1025 | (define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf") | |
| 1026 | (define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld") | |
| 30028c85 VM |
1027 | (define_bypass 6 "2_tofr" "2_frfr,2_stf") |
| 1028 | (define_bypass 7 "2_fmac" "2_frfr,2_stf") | |
| 1029 | ||
| 1030 | ;; We don't use here fcmp because scall may be predicated. | |
| 1031 | (define_bypass 0 "2_fcvtfx,2_fld,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ | |
| 1032 | 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_long_i,\ | |
| f61134e8 RH |
1033 | 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tofr,\ |
| 1034 | 2_xmpy,2_xtd" | |
| 30028c85 VM |
1035 | "2_scall") |
| 1036 | ||
| 1037 | (define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,\ | |
| 1038 | 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ | |
| f61134e8 RH |
1039 | 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_chk_s,2_long_i,\ |
| 1040 | 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ | |
| 30028c85 VM |
1041 | 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ |
| 1042 | 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ | |
| 1043 | 2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore") | |
| 1044 | ||
| 1045 | ||
| 1046 | \f | |
| 1047 | ;; Bundling | |
| 1048 | ||
| 1049 | (define_automaton "twob") | |
| 1050 | ||
| 1051 | ;; Pseudo units for quicker searching for position in two packet window. */ | |
| 1052 | (define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob") | |
| 1053 | ||
| 1054 | ;; All possible combinations of bundles/syllables | |
| 1055 | (define_cpu_unit | |
| 1056 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
| 1057 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob") | |
| 1058 | (define_cpu_unit | |
| 1059 | "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
| 1060 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob") | |
| 1061 | (define_query_cpu_unit | |
| 1062 | "2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
| 1063 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob") | |
| 1064 | ||
| 1065 | (define_cpu_unit | |
| 1066 | "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
| 1067 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob") | |
| 1068 | (define_cpu_unit | |
| 1069 | "2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
| 1070 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob") | |
| 1071 | (define_query_cpu_unit | |
| 1072 | "2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
| 1073 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob") | |
| 1074 | ||
| 1075 | ;; Slot 1 | |
| 1076 | (exclusion_set "2b_0m.ii" | |
| 1077 | "2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
| 1078 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1079 | (exclusion_set "2b_0m.mi" | |
| 1080 | "2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\ | |
| 1081 | 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1082 | (exclusion_set "2b_0m.fi" | |
| 1083 | "2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1084 | (exclusion_set "2b_0m.mf" | |
| 1085 | "2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1086 | (exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1087 | (exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1088 | (exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1089 | (exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx") | |
| 1090 | (exclusion_set "2b_0m.fb" "2b_0m.lx") | |
| 1091 | ||
| 1092 | ;; Slot 2 | |
| 1093 | (exclusion_set "2b_0mi.i" | |
| 1094 | "2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
| 1095 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1096 | (exclusion_set "2b_0mm.i" | |
| 1097 | "2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ | |
| 1098 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1099 | (exclusion_set "2b_0mf.i" | |
| 1100 | "2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1101 | (exclusion_set "2b_0mm.f" | |
| 1102 | "2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1103 | (exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1104 | (exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1105 | (exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.") | |
| 1106 | (exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.") | |
| 1107 | (exclusion_set "2b_0mf.b" "2b_0mlx.") | |
| 1108 | ||
| 1109 | ;; Slot 3 | |
| 1110 | (exclusion_set "2b_0mii." | |
| 1111 | "2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
| 1112 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1113 | (exclusion_set "2b_0mmi." | |
| 1114 | "2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ | |
| 1115 | 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1116 | (exclusion_set "2b_0mfi." | |
| 1117 | "2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1118 | (exclusion_set "2b_0mmf." | |
| 1119 | "2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1120 | (exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1121 | (exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1122 | (exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.") | |
| 1123 | (exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.") | |
| 1124 | (exclusion_set "2b_0mfb." "2b_0mlx.") | |
| 1125 | ||
| 1126 | ;; Slot 4 | |
| 1127 | (exclusion_set "2b_1m.ii" | |
| 1128 | "2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
| 1129 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1130 | (exclusion_set "2b_1m.mi" | |
| 1131 | "2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\ | |
| 1132 | 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1133 | (exclusion_set "2b_1m.fi" | |
| 1134 | "2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1135 | (exclusion_set "2b_1m.mf" | |
| 1136 | "2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1137 | (exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1138 | (exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1139 | (exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx") | |
| 1140 | (exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx") | |
| 1141 | (exclusion_set "2b_1m.fb" "2b_1m.lx") | |
| 1142 | ||
| 1143 | ;; Slot 5 | |
| 1144 | (exclusion_set "2b_1mi.i" | |
| 1145 | "2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
| 1146 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1147 | (exclusion_set "2b_1mm.i" | |
| 1148 | "2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ | |
| 1149 | 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1150 | (exclusion_set "2b_1mf.i" | |
| 1151 | "2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1152 | (exclusion_set "2b_1mm.f" | |
| 1153 | "2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1154 | (exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1155 | (exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1156 | (exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.") | |
| 1157 | (exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.") | |
| 1158 | (exclusion_set "2b_1mf.b" "2b_1mlx.") | |
| 1159 | ||
| 1160 | ;; Slot 6 | |
| 1161 | (exclusion_set "2b_1mii." | |
| 1162 | "2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
| 1163 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1164 | (exclusion_set "2b_1mmi." | |
| 1165 | "2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ | |
| 1166 | 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1167 | (exclusion_set "2b_1mfi." | |
| 1168 | "2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1169 | (exclusion_set "2b_1mmf." | |
| 1170 | "2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1171 | (exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1172 | (exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1173 | (exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.") | |
| 1174 | (exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.") | |
| 1175 | (exclusion_set "2b_1mfb." "2b_1mlx.") | |
| 1176 | ||
| 1177 | (final_presence_set "2b_0mi.i" "2b_0m.ii") | |
| 1178 | (final_presence_set "2b_0mii." "2b_0mi.i") | |
| 1179 | (final_presence_set "2b_1mi.i" "2b_1m.ii") | |
| 1180 | (final_presence_set "2b_1mii." "2b_1mi.i") | |
| 1181 | ||
| 1182 | (final_presence_set "2b_0mm.i" "2b_0m.mi") | |
| 1183 | (final_presence_set "2b_0mmi." "2b_0mm.i") | |
| 1184 | (final_presence_set "2b_1mm.i" "2b_1m.mi") | |
| 1185 | (final_presence_set "2b_1mmi." "2b_1mm.i") | |
| 1186 | ||
| 1187 | (final_presence_set "2b_0mf.i" "2b_0m.fi") | |
| 1188 | (final_presence_set "2b_0mfi." "2b_0mf.i") | |
| 1189 | (final_presence_set "2b_1mf.i" "2b_1m.fi") | |
| 1190 | (final_presence_set "2b_1mfi." "2b_1mf.i") | |
| 1191 | ||
| 1192 | (final_presence_set "2b_0mm.f" "2b_0m.mf") | |
| 1193 | (final_presence_set "2b_0mmf." "2b_0mm.f") | |
| 1194 | (final_presence_set "2b_1mm.f" "2b_1m.mf") | |
| 1195 | (final_presence_set "2b_1mmf." "2b_1mm.f") | |
| 1196 | ||
| 1197 | (final_presence_set "2b_0bb.b" "2b_0b.bb") | |
| 1198 | (final_presence_set "2b_0bbb." "2b_0bb.b") | |
| 1199 | (final_presence_set "2b_1bb.b" "2b_1b.bb") | |
| 1200 | (final_presence_set "2b_1bbb." "2b_1bb.b") | |
| 1201 | ||
| 1202 | (final_presence_set "2b_0mb.b" "2b_0m.bb") | |
| 1203 | (final_presence_set "2b_0mbb." "2b_0mb.b") | |
| 1204 | (final_presence_set "2b_1mb.b" "2b_1m.bb") | |
| 1205 | (final_presence_set "2b_1mbb." "2b_1mb.b") | |
| 1206 | ||
| 1207 | (final_presence_set "2b_0mi.b" "2b_0m.ib") | |
| 1208 | (final_presence_set "2b_0mib." "2b_0mi.b") | |
| 1209 | (final_presence_set "2b_1mi.b" "2b_1m.ib") | |
| 1210 | (final_presence_set "2b_1mib." "2b_1mi.b") | |
| 1211 | ||
| 1212 | (final_presence_set "2b_0mm.b" "2b_0m.mb") | |
| 1213 | (final_presence_set "2b_0mmb." "2b_0mm.b") | |
| 1214 | (final_presence_set "2b_1mm.b" "2b_1m.mb") | |
| 1215 | (final_presence_set "2b_1mmb." "2b_1mm.b") | |
| 1216 | ||
| 1217 | (final_presence_set "2b_0mf.b" "2b_0m.fb") | |
| 1218 | (final_presence_set "2b_0mfb." "2b_0mf.b") | |
| 1219 | (final_presence_set "2b_1mf.b" "2b_1m.fb") | |
| 1220 | (final_presence_set "2b_1mfb." "2b_1mf.b") | |
| 1221 | ||
| 1222 | (final_presence_set "2b_0mlx." "2b_0m.lx") | |
| 1223 | (final_presence_set "2b_1mlx." "2b_1m.lx") | |
| 1224 | ||
| 1225 | ;; See the corresponding comment in non-bundling section above. | |
| 1226 | (final_presence_set | |
| 1227 | "2b_1m.lx" | |
| 1228 | "2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") | |
| 1229 | (final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.") | |
| 1230 | (final_presence_set | |
| 1231 | "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb" | |
| 1232 | "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") | |
| 1233 | ||
| 1234 | ;; Ports/units (nb means nop.b insn issued into given port): | |
| 1235 | (define_cpu_unit | |
| 1236 | "2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\ | |
| 1237 | 2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob") | |
| 1238 | ||
| 1239 | (exclusion_set "2b_ub0" "2b_unb0") | |
| 1240 | (exclusion_set "2b_ub1" "2b_unb1") | |
| 1241 | (exclusion_set "2b_ub2" "2b_unb2") | |
| 1242 | ||
| 1243 | ;; The following rules are used to decrease number of alternatives. | |
| 1244 | ;; They are consequences of Itanium2 microarchitecture. They also | |
| 1245 | ;; describe the following rules mentioned in Itanium2 | |
| 1246 | ;; microarchitecture: rules mentioned in Itanium2 microarchitecture: | |
| 1247 | ;; o "BBB/MBB: Always splits issue after either of these bundles". | |
| 1248 | ;; o "MIB BBB: Split issue after the first bundle in this pair". | |
| 1249 | (exclusion_set | |
| 1250 | "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb." | |
| 1251 | "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\ | |
| 1252 | 2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx") | |
| 1253 | (exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb") | |
| 1254 | ||
| 1255 | ;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the | |
| 1256 | ;;; B-slot contains a nop.b or a brp instruction". | |
| 1257 | ;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or | |
| 1258 | ;;; nop.b, otherwise it disperses to B2". | |
| 1259 | (final_absence_set | |
| 1260 | "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ | |
| 1261 | 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" | |
| 1262 | "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2") | |
| 1263 | ||
| 1264 | ;; This is necessary to start new processor cycle when we meet stop bit. | |
| 1265 | (define_cpu_unit "2b_stop" "twob") | |
| 1266 | (final_absence_set | |
| 1267 | "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ | |
| 1268 | 2b_0m.fi,2b_0mf.i,2b_0mfi.,\ | |
| 1269 | 2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\ | |
| 1270 | 2b_0m.bb,2b_0mb.b,2b_0mbb.,\ | |
| 1271 | 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ | |
| 1272 | 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ | |
| 1273 | 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ | |
| 1274 | 2b_1m.fi,2b_1mf.i,2b_1mfi.,\ | |
| 1275 | 2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\ | |
| 1276 | 2b_1m.bb,2b_1mb.b,2b_1mbb.,\ | |
| 1277 | 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ | |
| 1278 | 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." | |
| 1279 | "2b_stop") | |
| 1280 | ||
| 1281 | ;; The issue logic can reorder M slot insns between different subtypes | |
| 1e5f1716 | 1282 | ;; but cannot reorder insn within the same subtypes. The following |
| 30028c85 VM |
1283 | ;; constraint is enough to describe this. |
| 1284 | (final_presence_set "2b_um1" "2b_um0") | |
| 1285 | (final_presence_set "2b_um3" "2b_um2") | |
| 1286 | ||
| 1287 | ;; The insn in the 1st I slot of the two bundle issue group will issue | |
| 1288 | ;; to I0. The second I slot insn will issue to I1. | |
| 1289 | (final_presence_set "2b_ui1" "2b_ui0") | |
| 1290 | ||
| 1291 | ;; For exceptions of I insns: | |
| 1292 | (define_cpu_unit "2b_only_ui0" "twob") | |
| 1293 | (final_absence_set "2b_only_ui0" "2b_ui1") | |
| 1294 | ||
| 1295 | ;; Insns | |
| 1296 | ||
| 1297 | (define_reservation "2b_M" | |
| 1298 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1299 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
| 1300 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
| 1301 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
| 1302 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
| 1303 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
| 1304 | +(2b_um0|2b_um1|2b_um2|2b_um3)") | |
| 1305 | ||
| 1306 | (define_reservation "2b_M_only_um0" | |
| 1307 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1308 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
| 1309 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
| 1310 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
| 1311 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
| 1312 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
| 1313 | +2b_um0") | |
| 1314 | ||
| 1315 | (define_reservation "2b_M_only_um2" | |
| 1316 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1317 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
| 1318 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
| 1319 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
| 1320 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
| 1321 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
| 1322 | +2b_um2") | |
| 1323 | ||
| 1324 | (define_reservation "2b_M_only_um01" | |
| 1325 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1326 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
| 1327 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
| 1328 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
| 1329 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
| 1330 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
| 1331 | +(2b_um0|2b_um1)") | |
| 1332 | ||
| 1333 | (define_reservation "2b_M_only_um23" | |
| 1334 | "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1335 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ | |
| 1336 | |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ | |
| 1337 | |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ | |
| 1338 | |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ | |
| 1339 | |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ | |
| 1340 | +(2b_um2|2b_um3)") | |
| 1341 | ||
| 1342 | ;; I instruction is dispersed to the lowest numbered I unit | |
| 1ae58c30 | 1343 | ;; not already in use. Remember about possible splitting. |
| 30028c85 VM |
1344 | (define_reservation "2b_I" |
| 1345 | "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\ | |
| 1346 | |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\ | |
| 1347 | |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\ | |
| 1348 | |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)") | |
| 1349 | ||
| 1350 | ;; "An F slot in the 1st bundle disperses to F0". | |
| 1351 | ;; "An F slot in the 2st bundle disperses to F1". | |
| 1352 | (define_reservation "2b_F" | |
| 1353 | "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\ | |
| 1354 | |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1") | |
| 1355 | ||
| 1356 | ;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B | |
| 2a43945f | 1357 | ;;; unit. That is, a B slot in 1st position is dispersed to B0. In the |
| 30028c85 VM |
1358 | ;;; 2nd position it is dispersed to B2". |
| 1359 | (define_reservation "2b_NB" | |
| 1360 | "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\ | |
| 1361 | |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\ | |
| 1362 | |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\ | |
| 1363 | |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\ | |
| 1364 | |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\ | |
| 1365 | |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0") | |
| 1366 | ||
| 1367 | (define_reservation "2b_B" | |
| 1368 | "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\ | |
| 1369 | |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\ | |
| 1370 | |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\ | |
| 1371 | |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\ | |
| 1372 | |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2") | |
| 1373 | ||
| 1374 | ;; For the MLI template, the I slot insn is always assigned to port I0 | |
| 1375 | ;; if it is in the first bundle or it is assigned to port I1 if it is in | |
| 1376 | ;; the second bundle. | |
| 1377 | (define_reservation "2b_L" | |
| 1378 | "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1") | |
| 1379 | ||
| 1380 | ;; Should we describe that A insn in I slot can be issued into M | |
| 1381 | ;; ports? I think it is not necessary because of multipass | |
| 1382 | ;; scheduling. For example, the multipass scheduling could use | |
| 1383 | ;; MMI-MMI instead of MII-MII where the two last I slots contain A | |
| 1384 | ;; insns (even if the case is complicated by use-def conflicts). | |
| 1385 | ;; | |
| 1386 | ;; In any case we could describe it as | |
| 1387 | ;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" | |
| 1388 | ;; "twob") | |
| 1389 | ;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" | |
| 1390 | ;; "2b_ui1") | |
| 1391 | ;; (define_reservation "b_A" | |
| 1392 | ;; "b_M|b_I\ | |
| 1393 | ;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\ | |
| 1394 | ;; +(2b_um0|2b_um1|2b_um2|2b_um3)\ | |
| 1395 | ;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)") | |
| 1396 | ||
| 1397 | (define_reservation "2b_A" "2b_M|2b_I") | |
| 1398 | ||
| 1399 | ;; We assume that there is no insn issued on the same cycle as the | |
| 1400 | ;; unknown insn. | |
| 1401 | (define_cpu_unit "2b_empty" "twob") | |
| 1402 | (exclusion_set "2b_empty" | |
| 1403 | "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\ | |
| 1404 | 2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i") | |
| 1405 | ||
| 1406 | (define_cpu_unit | |
| 1407 | "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs" | |
| 1408 | "twob") | |
| 1409 | (define_cpu_unit | |
| 1410 | "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" | |
| 1411 | "twob") | |
| 1412 | ||
| 1413 | (define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\ | |
| 1414 | 2b_b_cont, 2b_bb_cont" "twob") | |
| 1415 | ||
| 1416 | ;; For stop in the middle of the bundles. | |
| 1417 | (define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob") | |
| 1418 | (define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob") | |
| 1419 | ||
| 1420 | (final_presence_set "2b_0m_bs" | |
| 1421 | "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\ | |
| 1422 | 2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx") | |
| 1423 | (final_presence_set "2b_1m_bs" | |
| 1424 | "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\ | |
| 1425 | 2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx") | |
| 1426 | (final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i") | |
| 1427 | (final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i") | |
| 1428 | (final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b") | |
| 1429 | (final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b") | |
| 1430 | (final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b") | |
| 1431 | (final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b") | |
| 1432 | (final_presence_set "2b_0b_bs" "2b_0b.bb") | |
| 1433 | (final_presence_set "2b_1b_bs" "2b_1b.bb") | |
| 1434 | (final_presence_set "2b_0bb_bs" "2b_0bb.b") | |
| 1435 | (final_presence_set "2b_1bb_bs" "2b_1bb.b") | |
| 1436 | (final_presence_set "2b_0mb_bs" "2b_0mb.b") | |
| 1437 | (final_presence_set "2b_1mb_bs" "2b_1mb.b") | |
| 1438 | ||
| 1439 | (exclusion_set "2b_0m_bs" | |
| 1440 | "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\ | |
| 1441 | 2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop") | |
| 1442 | (exclusion_set "2b_1m_bs" | |
| 1443 | "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\ | |
| 1444 | 2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop") | |
| 1445 | (exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop") | |
| 1446 | (exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop") | |
| 1447 | (exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.") | |
| 1448 | (exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.") | |
| 1449 | (exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.") | |
| 1450 | (exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.") | |
| 1451 | (exclusion_set "2b_0b_bs" "2b_0bb.b") | |
| 1452 | (exclusion_set "2b_1b_bs" "2b_1bb.b") | |
| 1453 | (exclusion_set "2b_0bb_bs" "2b_0bbb.") | |
| 1454 | (exclusion_set "2b_1bb_bs" "2b_1bbb.") | |
| 1455 | (exclusion_set "2b_0mb_bs" "2b_0mbb.") | |
| 1456 | (exclusion_set "2b_1mb_bs" "2b_1mbb.") | |
| 1457 | ||
| 1458 | (exclusion_set | |
| 1459 | "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs, | |
| 1460 | 2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" | |
| 1461 | "2b_stop") | |
| 1462 | ||
| 1463 | (final_presence_set | |
| 1464 | "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\ | |
| 1465 | 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx." | |
| 1466 | "2b_m_cont") | |
| 1467 | (final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont") | |
| 1468 | (final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont") | |
| 1469 | (final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont") | |
| 1470 | (final_presence_set "2b_0bb.b" "2b_b_cont") | |
| 1471 | (final_presence_set "2b_0bbb." "2b_bb_cont") | |
| 1472 | (final_presence_set "2b_0mbb." "2b_mb_cont") | |
| 1473 | ||
| 1474 | (exclusion_set | |
| 1475 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
| 1476 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" | |
| 1477 | "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\ | |
| 1478 | 2b_mb_cont, 2b_b_cont, 2b_bb_cont") | |
| 1479 | ||
| 1480 | (exclusion_set "2b_empty" | |
| 1481 | "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\ | |
| 1482 | 2b_mb_cont,2b_b_cont,2b_bb_cont") | |
| 1483 | ||
| 1484 | ;; For m;mi bundle | |
| 1485 | (final_presence_set "2b_m0_stop" "2b_0m.mi") | |
| 1486 | (final_presence_set "2b_0mm.i" "2b_0mmi_cont") | |
| 1487 | (exclusion_set "2b_0mmi_cont" | |
| 1488 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
| 1489 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1490 | (exclusion_set "2b_m0_stop" "2b_0mm.i") | |
| 1491 | (final_presence_set "2b_m1_stop" "2b_1m.mi") | |
| 1492 | (exclusion_set "2b_m1_stop" "2b_1mm.i") | |
| 1493 | (final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop") | |
| 1494 | ||
| 1495 | ;; For mi;i bundle | |
| 1496 | (final_presence_set "2b_mi0_stop" "2b_0mi.i") | |
| 1497 | (final_presence_set "2b_0mii." "2b_0mii_cont") | |
| 1498 | (exclusion_set "2b_0mii_cont" | |
| 1499 | "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ | |
| 1500 | 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") | |
| 1501 | (exclusion_set "2b_mi0_stop" "2b_0mii.") | |
| 1502 | (final_presence_set "2b_mi1_stop" "2b_1mi.i") | |
| 1503 | (exclusion_set "2b_mi1_stop" "2b_1mii.") | |
| 1504 | (final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop") | |
| 1505 | ||
| 1506 | (final_absence_set | |
| 1507 | "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ | |
| 1508 | 2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\ | |
| 1509 | 2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\ | |
| 1510 | 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ | |
| 1511 | 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ | |
| 1512 | 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ | |
| 1513 | 2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\ | |
| 1514 | 2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\ | |
| 1515 | 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ | |
| 1516 | 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." | |
| 1517 | "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop") | |
| 1518 | ||
| 1519 | (define_insn_reservation "2b_stop_bit" 0 | |
| 1520 | (and (and (eq_attr "cpu" "itanium2") | |
| 1521 | (eq_attr "itanium_class" "stop_bit")) | |
| 1522 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1523 | "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop") | |
| 1524 | (define_insn_reservation "2b_br" 0 | |
| 1525 | (and (and (eq_attr "cpu" "itanium2") | |
| 1526 | (eq_attr "itanium_class" "br")) | |
| 1527 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B") | |
| 1528 | (define_insn_reservation "2b_scall" 0 | |
| 1529 | (and (and (eq_attr "cpu" "itanium2") | |
| 1530 | (eq_attr "itanium_class" "scall")) | |
| 1531 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_B") | |
| 1532 | (define_insn_reservation "2b_fcmp" 2 | |
| 1533 | (and (and (eq_attr "cpu" "itanium2") | |
| 1534 | (eq_attr "itanium_class" "fcmp")) | |
| 1535 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1536 | (define_insn_reservation "2b_fcvtfx" 4 | |
| 1537 | (and (and (eq_attr "cpu" "itanium2") | |
| 1538 | (eq_attr "itanium_class" "fcvtfx")) | |
| 1539 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1540 | (define_insn_reservation "2b_fld" 6 | |
| 1541 | (and (and (eq_attr "cpu" "itanium2") | |
| 1542 | (eq_attr "itanium_class" "fld")) | |
| 1543 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") | |
| 1544 | (define_insn_reservation "2b_fmac" 4 | |
| 1545 | (and (and (eq_attr "cpu" "itanium2") | |
| 1546 | (eq_attr "itanium_class" "fmac")) | |
| 1547 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1548 | (define_insn_reservation "2b_fmisc" 4 | |
| 1549 | (and (and (eq_attr "cpu" "itanium2") | |
| 1550 | (eq_attr "itanium_class" "fmisc")) | |
| 1551 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1552 | ||
| 1553 | ;; Latency time ??? | |
| 1554 | (define_insn_reservation "2b_frar_i" 13 | |
| 1555 | (and (and (eq_attr "cpu" "itanium2") | |
| 1556 | (eq_attr "itanium_class" "frar_i")) | |
| 1557 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1558 | "2b_I+2b_only_ui0") | |
| 1559 | ;; Latency time ??? | |
| 1560 | (define_insn_reservation "2b_frar_m" 6 | |
| 1561 | (and (and (eq_attr "cpu" "itanium2") | |
| 1562 | (eq_attr "itanium_class" "frar_m")) | |
| 1563 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1564 | "2b_M_only_um2") | |
| 1565 | (define_insn_reservation "2b_frbr" 2 | |
| 1566 | (and (and (eq_attr "cpu" "itanium2") | |
| 1567 | (eq_attr "itanium_class" "frbr")) | |
| 1568 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1569 | "2b_I+2b_only_ui0") | |
| 1570 | (define_insn_reservation "2b_frfr" 5 | |
| 1571 | (and (and (eq_attr "cpu" "itanium2") | |
| 1572 | (eq_attr "itanium_class" "frfr")) | |
| 1573 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1574 | "2b_M_only_um2") | |
| 1575 | (define_insn_reservation "2b_frpr" 2 | |
| 1576 | (and (and (eq_attr "cpu" "itanium2") | |
| 1577 | (eq_attr "itanium_class" "frpr")) | |
| 1578 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1579 | "2b_I+2b_only_ui0") | |
| 1580 | ||
| 1581 | (define_insn_reservation "2b_ialu" 1 | |
| 1582 | (and (and (eq_attr "cpu" "itanium2") | |
| 1583 | (eq_attr "itanium_class" "ialu")) | |
| 1584 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1585 | "2b_A") | |
| 1586 | (define_insn_reservation "2b_icmp" 1 | |
| 1587 | (and (and (eq_attr "cpu" "itanium2") | |
| 1588 | (eq_attr "itanium_class" "icmp")) | |
| 1589 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A") | |
| 1590 | (define_insn_reservation "2b_ilog" 1 | |
| 1591 | (and (and (eq_attr "cpu" "itanium2") | |
| 1592 | (eq_attr "itanium_class" "ilog")) | |
| 1593 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A") | |
| f61134e8 RH |
1594 | (define_insn_reservation "2b_mmalua" 2 |
| 1595 | (and (and (eq_attr "cpu" "itanium2") | |
| 1596 | (eq_attr "itanium_class" "mmalua")) | |
| 1597 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_A") | |
| 30028c85 VM |
1598 | ;; Latency time ??? |
| 1599 | (define_insn_reservation "2b_ishf" 1 | |
| 1600 | (and (and (eq_attr "cpu" "itanium2") | |
| 1601 | (eq_attr "itanium_class" "ishf")) | |
| 1602 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1603 | "2b_I+2b_only_ui0") | |
| 1604 | (define_insn_reservation "2b_ld" 1 | |
| 1605 | (and (and (eq_attr "cpu" "itanium2") | |
| 1606 | (eq_attr "itanium_class" "ld")) | |
| 1607 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1608 | "2b_M_only_um01") | |
| 1609 | (define_insn_reservation "2b_long_i" 1 | |
| 1610 | (and (and (eq_attr "cpu" "itanium2") | |
| 1611 | (eq_attr "itanium_class" "long_i")) | |
| 1612 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L") | |
| 1613 | ||
| 1614 | ;; Latency time ??? | |
| 1615 | (define_insn_reservation "2b_mmmul" 2 | |
| 1616 | (and (and (eq_attr "cpu" "itanium2") | |
| 1617 | (eq_attr "itanium_class" "mmmul")) | |
| 1618 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1619 | "2b_I+2b_only_ui0") | |
| 1620 | ;; Latency time ??? | |
| 1621 | (define_insn_reservation "2b_mmshf" 2 | |
| 1622 | (and (and (eq_attr "cpu" "itanium2") | |
| 1623 | (eq_attr "itanium_class" "mmshf")) | |
| 1624 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") | |
| 1625 | ;; Latency time ??? | |
| 1626 | (define_insn_reservation "2b_mmshfi" 1 | |
| 1627 | (and (and (eq_attr "cpu" "itanium2") | |
| 1628 | (eq_attr "itanium_class" "mmshfi")) | |
| 1629 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") | |
| 1630 | ||
| 1631 | (define_insn_reservation "2b_rse_m" 0 | |
| 1632 | (and (and (eq_attr "cpu" "itanium2") | |
| 1633 | (eq_attr "itanium_class" "rse_m")) | |
| 1634 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1635 | "(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ | |
| 1636 | |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0") | |
| 1637 | (define_insn_reservation "2b_sem" 0 | |
| 1638 | (and (and (eq_attr "cpu" "itanium2") | |
| 1639 | (eq_attr "itanium_class" "sem")) | |
| 1640 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1641 | "2b_M_only_um23") | |
| 1642 | ||
| 1643 | (define_insn_reservation "2b_stf" 1 | |
| 1644 | (and (and (eq_attr "cpu" "itanium2") | |
| 1645 | (eq_attr "itanium_class" "stf")) | |
| 1646 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1647 | "2b_M_only_um23") | |
| 1648 | (define_insn_reservation "2b_st" 1 | |
| 1649 | (and (and (eq_attr "cpu" "itanium2") | |
| 1650 | (eq_attr "itanium_class" "st")) | |
| 1651 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1652 | "2b_M_only_um23") | |
| 1653 | (define_insn_reservation "2b_syst_m0" 0 | |
| 1654 | (and (and (eq_attr "cpu" "itanium2") | |
| 1655 | (eq_attr "itanium_class" "syst_m0")) | |
| 1656 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1657 | "2b_M_only_um2") | |
| 1658 | (define_insn_reservation "2b_syst_m" 0 | |
| 1659 | (and (and (eq_attr "cpu" "itanium2") | |
| 1660 | (eq_attr "itanium_class" "syst_m")) | |
| 1661 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1662 | "2b_M_only_um0") | |
| 1663 | ;; Reservation??? | |
| 1664 | (define_insn_reservation "2b_tbit" 1 | |
| 1665 | (and (and (eq_attr "cpu" "itanium2") | |
| 1666 | (eq_attr "itanium_class" "tbit")) | |
| 1667 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1668 | "2b_I+2b_only_ui0") | |
| 1669 | (define_insn_reservation "2b_toar_i" 0 | |
| 1670 | (and (and (eq_attr "cpu" "itanium2") | |
| 1671 | (eq_attr "itanium_class" "toar_i")) | |
| 1672 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1673 | "2b_I+2b_only_ui0") | |
| 1674 | ;; Latency time ??? | |
| 1675 | (define_insn_reservation "2b_toar_m" 5 | |
| 1676 | (and (and (eq_attr "cpu" "itanium2") | |
| 1677 | (eq_attr "itanium_class" "toar_m")) | |
| 1678 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1679 | "2b_M_only_um2") | |
| 1680 | ;; Latency time ??? | |
| 1681 | (define_insn_reservation "2b_tobr" 1 | |
| 1682 | (and (and (eq_attr "cpu" "itanium2") | |
| 1683 | (eq_attr "itanium_class" "tobr")) | |
| 1684 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1685 | "2b_I+2b_only_ui0") | |
| 1686 | (define_insn_reservation "2b_tofr" 5 | |
| 1687 | (and (and (eq_attr "cpu" "itanium2") | |
| 1688 | (eq_attr "itanium_class" "tofr")) | |
| 1689 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1690 | "2b_M_only_um23") | |
| 1691 | ;; Latency time ??? | |
| 1692 | (define_insn_reservation "2b_topr" 1 | |
| 1693 | (and (and (eq_attr "cpu" "itanium2") | |
| 1694 | (eq_attr "itanium_class" "topr")) | |
| 1695 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1696 | "2b_I+2b_only_ui0") | |
| 1697 | ||
| 1698 | (define_insn_reservation "2b_xmpy" 4 | |
| 1699 | (and (and (eq_attr "cpu" "itanium2") | |
| 1700 | (eq_attr "itanium_class" "xmpy")) | |
| 1701 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1702 | ;; Latency time ??? | |
| 1703 | (define_insn_reservation "2b_xtd" 1 | |
| 1704 | (and (and (eq_attr "cpu" "itanium2") | |
| 1705 | (eq_attr "itanium_class" "xtd")) | |
| 1706 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") | |
| 1707 | (define_insn_reservation "2b_chk_s" 0 | |
| 1708 | (and (and (eq_attr "cpu" "itanium2") | |
| 1709 | (eq_attr "itanium_class" "chk_s")) | |
| 1710 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1711 | "2b_I|2b_M_only_um23") | |
| 1712 | (define_insn_reservation "2b_lfetch" 0 | |
| 1713 | (and (and (eq_attr "cpu" "itanium2") | |
| 1714 | (eq_attr "itanium_class" "lfetch")) | |
| 1715 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1716 | "2b_M_only_um01") | |
| 1717 | (define_insn_reservation "2b_nop_m" 0 | |
| 1718 | (and (and (eq_attr "cpu" "itanium2") | |
| 1719 | (eq_attr "itanium_class" "nop_m")) | |
| 1720 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_M") | |
| 1721 | (define_insn_reservation "2b_nop_b" 0 | |
| 1722 | (and (and (eq_attr "cpu" "itanium2") | |
| 1723 | (eq_attr "itanium_class" "nop_b")) | |
| 1724 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_NB") | |
| 1725 | (define_insn_reservation "2b_nop_i" 0 | |
| 1726 | (and (and (eq_attr "cpu" "itanium2") | |
| 1727 | (eq_attr "itanium_class" "nop_i")) | |
| 1728 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_I") | |
| 1729 | (define_insn_reservation "2b_nop_f" 0 | |
| 1730 | (and (and (eq_attr "cpu" "itanium2") | |
| 1731 | (eq_attr "itanium_class" "nop_f")) | |
| 1732 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_F") | |
| 1733 | (define_insn_reservation "2b_nop_x" 0 | |
| 1734 | (and (and (eq_attr "cpu" "itanium2") | |
| 1735 | (eq_attr "itanium_class" "nop_x")) | |
| 1736 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_L") | |
| 1737 | (define_insn_reservation "2b_unknown" 1 | |
| 1738 | (and (and (eq_attr "cpu" "itanium2") | |
| 1739 | (eq_attr "itanium_class" "unknown")) | |
| 1740 | (ne (symbol_ref "bundling_p") (const_int 0))) "2b_empty") | |
| 1741 | (define_insn_reservation "2b_nop" 0 | |
| 1742 | (and (and (eq_attr "cpu" "itanium2") | |
| 1743 | (eq_attr "itanium_class" "nop")) | |
| 1744 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1745 | "2b_M|2b_NB|2b_I|2b_F") | |
| 1746 | (define_insn_reservation "2b_ignore" 0 | |
| 1747 | (and (and (eq_attr "cpu" "itanium2") | |
| 1748 | (eq_attr "itanium_class" "ignore")) | |
| 1749 | (ne (symbol_ref "bundling_p") (const_int 0))) "nothing") | |
| 1750 | ||
| 1751 | (define_insn_reservation "2b_pre_cycle" 0 | |
| 1752 | (and (and (eq_attr "cpu" "itanium2") | |
| 1753 | (eq_attr "itanium_class" "pre_cycle")) | |
| 1754 | (ne (symbol_ref "bundling_p") (const_int 0))) | |
| 1755 | "(2b_0m_bs, 2b_m_cont) \ | |
| 1756 | | (2b_0mi_bs, 2b_mi_cont) \ | |
| 1757 | | (2b_0mm_bs, 2b_mm_cont) \ | |
| 1758 | | (2b_0mf_bs, 2b_mf_cont) \ | |
| 1759 | | (2b_0b_bs, 2b_b_cont) \ | |
| 1760 | | (2b_0bb_bs, 2b_bb_cont) \ | |
| 1761 | | (2b_0mb_bs, 2b_mb_cont) \ | |
| 1762 | | (2b_1m_bs, 2b_m_cont) \ | |
| 1763 | | (2b_1mi_bs, 2b_mi_cont) \ | |
| 1764 | | (2b_1mm_bs, 2b_mm_cont) \ | |
| 1765 | | (2b_1mf_bs, 2b_mf_cont) \ | |
| 1766 | | (2b_1b_bs, 2b_b_cont) \ | |
| 1767 | | (2b_1bb_bs, 2b_bb_cont) \ | |
| 1768 | | (2b_1mb_bs, 2b_mb_cont) \ | |
| 1769 | | (2b_m_stop, 2b_0mmi_cont) \ | |
| 1770 | | (2b_mi_stop, 2b_0mii_cont)") | |
| 1771 |