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f61134e8 | 1 | ;; IA-64 machine description for vector operations. |
23a5b65a | 2 | ;; Copyright (C) 2004-2014 Free Software Foundation, Inc. |
f61134e8 RH |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
f61134e8 RH |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
f61134e8 RH |
19 | |
20 | ||
21 | ;; Integer vector operations | |
22 | ||
e6431744 | 23 | (define_mode_iterator VEC [V8QI V4HI V2SI V2SF]) |
3abcb3a7 HPN |
24 | (define_mode_iterator VECINT [V8QI V4HI V2SI]) |
25 | (define_mode_iterator VECINT12 [V8QI V4HI]) | |
26 | (define_mode_iterator VECINT24 [V4HI V2SI]) | |
f61134e8 | 27 | (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")]) |
604e3ff3 | 28 | (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")]) |
e6431744 RH |
29 | (define_mode_attr vecint |
30 | [(V8QI "V8QI") (V4HI "V4HI") (V2SI "V2SI") (V2SF "V2SI")]) | |
f61134e8 RH |
31 | |
32 | (define_expand "mov<mode>" | |
33 | [(set (match_operand:VECINT 0 "general_operand" "") | |
34 | (match_operand:VECINT 1 "general_operand" ""))] | |
35 | "" | |
36 | { | |
37 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
38 | if (!op1) | |
39 | DONE; | |
40 | operands[1] = op1; | |
41 | }) | |
42 | ||
43 | (define_insn "*mov<mode>_internal" | |
44 | [(set (match_operand:VECINT 0 "destination_operand" | |
45 | "=r,r,r,r,m ,*f ,*f,Q ,r ,*f") | |
46 | (match_operand:VECINT 1 "move_operand" | |
47 | "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))] | |
48 | "ia64_move_ok (operands[0], operands[1])" | |
49 | "@ | |
50 | mov %0 = %r1 | |
51 | addl %0 = %v1, r0 | |
52 | movl %0 = %v1 | |
53 | ld8%O1 %0 = %1%P1 | |
54 | st8%Q0 %0 = %r1%P0 | |
55 | mov %0 = %F1 | |
56 | ldf8 %0 = %1%P1 | |
57 | stf8 %0 = %1%P0 | |
58 | getf.sig %0 = %1 | |
59 | setf.sig %0 = %1" | |
60 | [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")]) | |
61 | ||
62 | (define_insn "one_cmpl<mode>2" | |
63 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
64 | (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] | |
65 | "" | |
66 | "andcm %0 = -1, %1" | |
67 | [(set_attr "itanium_class" "ilog")]) | |
68 | ||
69 | (define_insn "and<mode>3" | |
70 | [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
71 | (and:VECINT | |
72 | (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
73 | (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
74 | "" | |
75 | "@ | |
76 | and %0 = %2, %1 | |
77 | fand %0 = %2, %1" | |
78 | [(set_attr "itanium_class" "ilog,fmisc")]) | |
79 | ||
80 | (define_insn "*andnot<mode>" | |
81 | [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
82 | (and:VECINT | |
83 | (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f")) | |
84 | (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
85 | "" | |
86 | "@ | |
87 | andcm %0 = %2, %1 | |
88 | fandcm %0 = %2, %1" | |
89 | [(set_attr "itanium_class" "ilog,fmisc")]) | |
90 | ||
91 | (define_insn "ior<mode>3" | |
92 | [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
93 | (ior:VECINT | |
94 | (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
95 | (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
96 | "" | |
97 | "@ | |
98 | or %0 = %2, %1 | |
99 | for %0 = %2, %1" | |
100 | [(set_attr "itanium_class" "ilog,fmisc")]) | |
101 | ||
102 | (define_insn "xor<mode>3" | |
103 | [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
104 | (xor:VECINT | |
105 | (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
106 | (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
107 | "" | |
108 | "@ | |
109 | xor %0 = %2, %1 | |
110 | fxor %0 = %2, %1" | |
111 | [(set_attr "itanium_class" "ilog,fmisc")]) | |
112 | ||
113 | (define_insn "neg<mode>2" | |
114 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
115 | (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] | |
116 | "" | |
117 | "psub<vecsize> %0 = r0, %1" | |
118 | [(set_attr "itanium_class" "mmalua")]) | |
119 | ||
120 | (define_insn "add<mode>3" | |
121 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
122 | (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") | |
123 | (match_operand:VECINT 2 "gr_register_operand" "r")))] | |
124 | "" | |
125 | "padd<vecsize> %0 = %1, %2" | |
126 | [(set_attr "itanium_class" "mmalua")]) | |
127 | ||
128 | (define_insn "*ssadd<mode>3" | |
129 | [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
130 | (ss_plus:VECINT12 | |
131 | (match_operand:VECINT12 1 "gr_register_operand" "r") | |
132 | (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
133 | "" | |
134 | "padd<vecsize>.sss %0 = %1, %2" | |
135 | [(set_attr "itanium_class" "mmalua")]) | |
136 | ||
137 | (define_insn "*usadd<mode>3" | |
138 | [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
139 | (us_plus:VECINT12 | |
140 | (match_operand:VECINT12 1 "gr_register_operand" "r") | |
141 | (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
142 | "" | |
143 | "padd<vecsize>.uuu %0 = %1, %2" | |
144 | [(set_attr "itanium_class" "mmalua")]) | |
145 | ||
146 | (define_insn "sub<mode>3" | |
147 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
148 | (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") | |
149 | (match_operand:VECINT 2 "gr_register_operand" "r")))] | |
150 | "" | |
151 | "psub<vecsize> %0 = %1, %2" | |
152 | [(set_attr "itanium_class" "mmalua")]) | |
153 | ||
154 | (define_insn "*sssub<mode>3" | |
155 | [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
156 | (ss_minus:VECINT12 | |
157 | (match_operand:VECINT12 1 "gr_register_operand" "r") | |
158 | (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
159 | "" | |
160 | "psub<vecsize>.sss %0 = %1, %2" | |
161 | [(set_attr "itanium_class" "mmalua")]) | |
162 | ||
163 | (define_insn "*ussub<mode>3" | |
164 | [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
165 | (us_minus:VECINT12 | |
166 | (match_operand:VECINT12 1 "gr_register_operand" "r") | |
167 | (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
168 | "" | |
169 | "psub<vecsize>.uuu %0 = %1, %2" | |
170 | [(set_attr "itanium_class" "mmalua")]) | |
171 | ||
172 | (define_expand "mulv8qi3" | |
173 | [(set (match_operand:V8QI 0 "gr_register_operand" "") | |
174 | (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
175 | (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
176 | "" | |
177 | { | |
55eaaa5b RH |
178 | rtx l = gen_reg_rtx (V4HImode); |
179 | rtx h = gen_reg_rtx (V4HImode); | |
180 | emit_insn (gen_vec_widen_umult_lo_v8qi (l, operands[1], operands[2])); | |
181 | emit_insn (gen_vec_widen_umult_hi_v8qi (h, operands[1], operands[2])); | |
182 | if (TARGET_BIG_ENDIAN) | |
183 | emit_insn (gen_vec_pack_trunc_v4hi (operands[0], h, l)); | |
184 | else | |
185 | emit_insn (gen_vec_pack_trunc_v4hi (operands[0], l, h)); | |
f61134e8 RH |
186 | DONE; |
187 | }) | |
188 | ||
604e3ff3 RH |
189 | (define_expand "vec_widen_umult_lo_v8qi" |
190 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
191 | (match_operand:V8QI 1 "gr_register_operand" "") | |
192 | (match_operand:V8QI 2 "gr_register_operand" "")] | |
193 | "" | |
194 | { | |
195 | rtx op1 = gen_reg_rtx (V4HImode); | |
196 | rtx op2 = gen_reg_rtx (V4HImode); | |
197 | emit_insn (gen_vec_unpacku_lo_v8qi (op1, operands[1])); | |
198 | emit_insn (gen_vec_unpacku_lo_v8qi (op2, operands[2])); | |
199 | emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); | |
200 | DONE; | |
201 | }); | |
202 | ||
203 | (define_expand "vec_widen_umult_hi_v8qi" | |
204 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
205 | (match_operand:V8QI 1 "gr_register_operand" "") | |
206 | (match_operand:V8QI 2 "gr_register_operand" "")] | |
207 | "" | |
208 | { | |
209 | rtx op1 = gen_reg_rtx (V4HImode); | |
210 | rtx op2 = gen_reg_rtx (V4HImode); | |
211 | emit_insn (gen_vec_unpacku_hi_v8qi (op1, operands[1])); | |
212 | emit_insn (gen_vec_unpacku_hi_v8qi (op2, operands[2])); | |
213 | emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); | |
214 | DONE; | |
215 | }); | |
216 | ||
217 | (define_expand "vec_widen_smult_lo_v8qi" | |
218 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
219 | (match_operand:V8QI 1 "gr_register_operand" "") | |
220 | (match_operand:V8QI 2 "gr_register_operand" "")] | |
221 | "" | |
222 | { | |
223 | rtx op1 = gen_reg_rtx (V4HImode); | |
224 | rtx op2 = gen_reg_rtx (V4HImode); | |
225 | emit_insn (gen_vec_unpacks_lo_v8qi (op1, operands[1])); | |
226 | emit_insn (gen_vec_unpacks_lo_v8qi (op2, operands[2])); | |
227 | emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); | |
228 | DONE; | |
229 | }); | |
230 | ||
231 | (define_expand "vec_widen_smult_hi_v8qi" | |
232 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
233 | (match_operand:V8QI 1 "gr_register_operand" "") | |
234 | (match_operand:V8QI 2 "gr_register_operand" "")] | |
235 | "" | |
236 | { | |
237 | rtx op1 = gen_reg_rtx (V4HImode); | |
238 | rtx op2 = gen_reg_rtx (V4HImode); | |
239 | emit_insn (gen_vec_unpacks_hi_v8qi (op1, operands[1])); | |
240 | emit_insn (gen_vec_unpacks_hi_v8qi (op2, operands[2])); | |
241 | emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); | |
242 | DONE; | |
243 | }); | |
244 | ||
f61134e8 RH |
245 | (define_insn "mulv4hi3" |
246 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
247 | (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r") | |
248 | (match_operand:V4HI 2 "gr_register_operand" "r")))] | |
249 | "" | |
250 | "pmpyshr2 %0 = %1, %2, 0" | |
051d8245 | 251 | [(set_attr "itanium_class" "mmmul")]) |
f61134e8 | 252 | |
604e3ff3 RH |
253 | (define_insn "pmpyshr2" |
254 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
255 | (truncate:V4HI | |
256 | (ashiftrt:V4SI | |
257 | (mult:V4SI | |
258 | (sign_extend:V4SI | |
259 | (match_operand:V4HI 1 "gr_register_operand" "r")) | |
260 | (sign_extend:V4SI | |
261 | (match_operand:V4HI 2 "gr_register_operand" "r"))) | |
262 | (match_operand:SI 3 "pmpyshr_operand" "n"))))] | |
263 | "" | |
264 | "pmpyshr2 %0 = %1, %2, %3" | |
265 | [(set_attr "itanium_class" "mmmul")]) | |
266 | ||
267 | (define_insn "pmpyshr2_u" | |
268 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
269 | (truncate:V4HI | |
270 | (lshiftrt:V4SI | |
271 | (mult:V4SI | |
272 | (zero_extend:V4SI | |
273 | (match_operand:V4HI 1 "gr_register_operand" "r")) | |
274 | (zero_extend:V4SI | |
275 | (match_operand:V4HI 2 "gr_register_operand" "r"))) | |
276 | (match_operand:SI 3 "pmpyshr_operand" "n"))))] | |
277 | "" | |
278 | "pmpyshr2.u %0 = %1, %2, %3" | |
279 | [(set_attr "itanium_class" "mmmul")]) | |
280 | ||
1312c276 RH |
281 | (define_expand "smulv4hi3_highpart" |
282 | [(match_operand:V4HI 0 "gr_register_operand") | |
283 | (match_operand:V4HI 1 "gr_register_operand") | |
284 | (match_operand:V4HI 2 "gr_register_operand")] | |
285 | "" | |
286 | { | |
287 | emit_insn (gen_pmpyshr2 (operands[0], operands[1], | |
288 | operands[2], GEN_INT (16))); | |
289 | DONE; | |
290 | }) | |
291 | ||
292 | (define_expand "umulv4hi3_highpart" | |
293 | [(match_operand:V4HI 0 "gr_register_operand") | |
294 | (match_operand:V4HI 1 "gr_register_operand") | |
295 | (match_operand:V4HI 2 "gr_register_operand")] | |
296 | "" | |
297 | { | |
298 | emit_insn (gen_pmpyshr2_u (operands[0], operands[1], | |
299 | operands[2], GEN_INT (16))); | |
300 | DONE; | |
301 | }) | |
302 | ||
303 | (define_insn "vec_widen_smult_even_v4hi" | |
e898620c RH |
304 | [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
305 | (mult:V2SI | |
306 | (vec_select:V2SI | |
307 | (sign_extend:V4SI | |
308 | (match_operand:V4HI 1 "gr_register_operand" "r")) | |
309 | (parallel [(const_int 0) (const_int 2)])) | |
310 | (vec_select:V2SI | |
311 | (sign_extend:V4SI | |
312 | (match_operand:V4HI 2 "gr_register_operand" "r")) | |
313 | (parallel [(const_int 0) (const_int 2)]))))] | |
314 | "" | |
55eaaa5b RH |
315 | { |
316 | /* Recall that vector elements are numbered in memory order. */ | |
317 | if (TARGET_BIG_ENDIAN) | |
318 | return "%,pmpy2.l %0 = %1, %2"; | |
319 | else | |
320 | return "%,pmpy2.r %0 = %1, %2"; | |
321 | } | |
e898620c RH |
322 | [(set_attr "itanium_class" "mmshf")]) |
323 | ||
1312c276 | 324 | (define_insn "vec_widen_smult_odd_v4hi" |
e898620c RH |
325 | [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
326 | (mult:V2SI | |
327 | (vec_select:V2SI | |
328 | (sign_extend:V4SI | |
329 | (match_operand:V4HI 1 "gr_register_operand" "r")) | |
330 | (parallel [(const_int 1) (const_int 3)])) | |
331 | (vec_select:V2SI | |
332 | (sign_extend:V4SI | |
333 | (match_operand:V4HI 2 "gr_register_operand" "r")) | |
334 | (parallel [(const_int 1) (const_int 3)]))))] | |
335 | "" | |
55eaaa5b RH |
336 | { |
337 | /* Recall that vector elements are numbered in memory order. */ | |
338 | if (TARGET_BIG_ENDIAN) | |
339 | return "%,pmpy2.r %0 = %1, %2"; | |
340 | else | |
341 | return "%,pmpy2.l %0 = %1, %2"; | |
342 | } | |
e898620c RH |
343 | [(set_attr "itanium_class" "mmshf")]) |
344 | ||
604e3ff3 RH |
345 | (define_expand "vec_widen_smult_lo_v4hi" |
346 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
347 | (match_operand:V4HI 1 "gr_register_operand" "") | |
348 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
349 | "" | |
350 | { | |
55eaaa5b RH |
351 | rtx l = gen_reg_rtx (V4HImode); |
352 | rtx h = gen_reg_rtx (V4HImode); | |
353 | emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); | |
354 | emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16))); | |
355 | ia64_unpack_assemble (operands[0], l, h, false); | |
604e3ff3 RH |
356 | DONE; |
357 | }) | |
358 | ||
359 | (define_expand "vec_widen_smult_hi_v4hi" | |
360 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
361 | (match_operand:V4HI 1 "gr_register_operand" "") | |
362 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
363 | "" | |
364 | { | |
55eaaa5b RH |
365 | rtx l = gen_reg_rtx (V4HImode); |
366 | rtx h = gen_reg_rtx (V4HImode); | |
367 | emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); | |
368 | emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16))); | |
369 | ia64_unpack_assemble (operands[0], l, h, true); | |
604e3ff3 RH |
370 | DONE; |
371 | }) | |
372 | ||
373 | (define_expand "vec_widen_umult_lo_v4hi" | |
374 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
375 | (match_operand:V4HI 1 "gr_register_operand" "") | |
376 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
377 | "" | |
378 | { | |
55eaaa5b RH |
379 | rtx l = gen_reg_rtx (V4HImode); |
380 | rtx h = gen_reg_rtx (V4HImode); | |
381 | emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); | |
382 | emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16))); | |
383 | ia64_unpack_assemble (operands[0], l, h, false); | |
604e3ff3 RH |
384 | DONE; |
385 | }) | |
386 | ||
387 | (define_expand "vec_widen_umult_hi_v4hi" | |
388 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
389 | (match_operand:V4HI 1 "gr_register_operand" "") | |
390 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
391 | "" | |
392 | { | |
55eaaa5b RH |
393 | rtx l = gen_reg_rtx (V4HImode); |
394 | rtx h = gen_reg_rtx (V4HImode); | |
395 | emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); | |
396 | emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16))); | |
397 | ia64_unpack_assemble (operands[0], l, h, true); | |
604e3ff3 RH |
398 | DONE; |
399 | }) | |
400 | ||
401 | (define_expand "mulv2si3" | |
402 | [(set (match_operand:V2SI 0 "gr_register_operand" "") | |
403 | (mult:V2SI (match_operand:V2SI 1 "gr_register_operand" "r") | |
404 | (match_operand:V2SI 2 "gr_register_operand" "r")))] | |
e435f098 | 405 | "" |
604e3ff3 RH |
406 | { |
407 | rtx t0, t1, t2, t3, t4, t5, t6, t7, x; | |
408 | rtx op1h = gen_lowpart (V4HImode, operands[1]); | |
409 | rtx op2h = gen_lowpart (V4HImode, operands[2]); | |
410 | ||
411 | t0 = gen_reg_rtx (V4HImode); | |
412 | t1 = gen_reg_rtx (V4HImode); | |
413 | t2 = gen_reg_rtx (V4HImode); | |
414 | t3 = gen_reg_rtx (V4HImode); | |
415 | t4 = gen_reg_rtx (V2SImode); | |
416 | t5 = gen_reg_rtx (V2SImode); | |
417 | t6 = gen_reg_rtx (V2SImode); | |
418 | t7 = gen_reg_rtx (V2SImode); | |
419 | ||
420 | /* Consider the HImode components of op1 = DCBA, op2 = ZYXW. | |
421 | Consider .l and .h suffixes below the low and high 16 bits | |
422 | of the full 32-bit product. */ | |
423 | ||
424 | /* T0 = CDBA. */ | |
55eaaa5b RH |
425 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx, |
426 | GEN_INT (3), const2_rtx)); | |
604e3ff3 RH |
427 | x = gen_rtx_VEC_SELECT (V4HImode, op1h, x); |
428 | emit_insn (gen_rtx_SET (VOIDmode, t0, x)); | |
429 | ||
430 | /* T1 = DZ.l, CY.l, BX.l, AW.l. */ | |
431 | emit_insn (gen_mulv4hi3 (t1, op1h, op2h)); | |
432 | ||
433 | /* T2 = DZ.h, CY.h, BX.h, AW.h. */ | |
434 | emit_insn (gen_pmpyshr2_u (t2, op1h, op2h, GEN_INT (16))); | |
435 | ||
436 | /* T3 = CZ.l, DY.l, AX.l, BW.l. */ | |
437 | emit_insn (gen_mulv4hi3 (t3, t0, op2h)); | |
438 | ||
439 | /* T4 = CY.h, CY.l, AW.h, AW.l = CY, AW. */ | |
55eaaa5b RH |
440 | x = gen_lowpart (V4HImode, t4); |
441 | if (TARGET_BIG_ENDIAN) | |
442 | x = gen_mix2_odd (x, t2, t1); | |
443 | else | |
444 | x = gen_mix2_even (x, t1, t2); | |
445 | emit_insn (x); | |
604e3ff3 RH |
446 | |
447 | /* T5 = CZ.l, 0, AX.l, 0 = CZ << 16, AX << 16. */ | |
55eaaa5b RH |
448 | x = gen_lowpart (V4HImode, t5); |
449 | if (TARGET_BIG_ENDIAN) | |
450 | x = gen_mix2_even (x, t3, CONST0_RTX (V4HImode)); | |
451 | else | |
452 | x = gen_mix2_odd (x, CONST0_RTX (V4HImode), t3); | |
453 | emit_insn (x); | |
604e3ff3 RH |
454 | |
455 | /* T6 = DY.l, 0, BW.l, 0 = DY << 16, BW << 16. */ | |
55eaaa5b RH |
456 | x = gen_lowpart (V4HImode, t6); |
457 | if (TARGET_BIG_ENDIAN) | |
458 | x = gen_mix2_odd (x, t3, CONST0_RTX (V4HImode)); | |
459 | else | |
460 | x = gen_mix2_even (x, CONST0_RTX (V4HImode), t3); | |
461 | emit_insn (x); | |
604e3ff3 RH |
462 | |
463 | emit_insn (gen_addv2si3 (t7, t4, t5)); | |
464 | emit_insn (gen_addv2si3 (operands[0], t6, t7)); | |
465 | DONE; | |
466 | }) | |
467 | ||
f61134e8 RH |
468 | (define_expand "umax<mode>3" |
469 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
cabddb23 | 470 | (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "") |
f61134e8 RH |
471 | (match_operand:VECINT 2 "gr_register_operand" "")))] |
472 | "" | |
473 | { | |
474 | if (ia64_expand_vecint_minmax (UMAX, <MODE>mode, operands)) | |
475 | DONE; | |
476 | }) | |
477 | ||
478 | (define_expand "smax<mode>3" | |
479 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
480 | (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
481 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
482 | "" | |
483 | { | |
484 | if (ia64_expand_vecint_minmax (SMAX, <MODE>mode, operands)) | |
485 | DONE; | |
486 | }) | |
487 | ||
488 | (define_expand "umin<mode>3" | |
489 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
490 | (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "") | |
491 | (match_operand:VECINT 2 "gr_register_operand" "")))] | |
492 | "" | |
493 | { | |
494 | if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands)) | |
495 | DONE; | |
496 | }) | |
497 | ||
498 | (define_expand "smin<mode>3" | |
499 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
500 | (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
501 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
502 | "" | |
503 | { | |
504 | if (ia64_expand_vecint_minmax (SMIN, <MODE>mode, operands)) | |
505 | DONE; | |
506 | }) | |
507 | ||
508 | (define_insn "*umaxv8qi3" | |
509 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
510 | (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
511 | (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
512 | "" | |
513 | "pmax1.u %0 = %1, %2" | |
514 | [(set_attr "itanium_class" "mmshf")]) | |
515 | ||
516 | (define_insn "*smaxv4hi3" | |
517 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
518 | (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
519 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] | |
520 | "" | |
521 | "pmax2 %0 = %r1, %r2" | |
522 | [(set_attr "itanium_class" "mmshf")]) | |
523 | ||
524 | (define_insn "*uminv8qi3" | |
525 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
526 | (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
527 | (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
528 | "" | |
529 | "pmin1.u %0 = %1, %2" | |
530 | [(set_attr "itanium_class" "mmshf")]) | |
531 | ||
532 | (define_insn "*sminv4hi3" | |
533 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
534 | (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
535 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] | |
536 | "" | |
537 | "pmin2 %0 = %r1, %r2" | |
538 | [(set_attr "itanium_class" "mmshf")]) | |
539 | ||
540 | (define_insn "ashl<mode>3" | |
541 | [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
542 | (ashift:VECINT24 | |
543 | (match_operand:VECINT24 1 "gr_register_operand" "r") | |
3dbb4dce | 544 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] |
f61134e8 RH |
545 | "" |
546 | "pshl<vecsize> %0 = %1, %2" | |
547 | [(set_attr "itanium_class" "mmshf")]) | |
548 | ||
549 | (define_insn "ashr<mode>3" | |
550 | [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
551 | (ashiftrt:VECINT24 | |
552 | (match_operand:VECINT24 1 "gr_register_operand" "r") | |
3dbb4dce | 553 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] |
f61134e8 RH |
554 | "" |
555 | "pshr<vecsize> %0 = %1, %2" | |
556 | [(set_attr "itanium_class" "mmshf")]) | |
557 | ||
558 | (define_insn "lshr<mode>3" | |
559 | [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
560 | (lshiftrt:VECINT24 | |
561 | (match_operand:VECINT24 1 "gr_register_operand" "r") | |
3dbb4dce | 562 | (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] |
f61134e8 RH |
563 | "" |
564 | "pshr<vecsize>.u %0 = %1, %2" | |
565 | [(set_attr "itanium_class" "mmshf")]) | |
566 | ||
cabddb23 RH |
567 | (define_expand "vec_shl_<mode>" |
568 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
569 | (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "") | |
570 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] | |
571 | "" | |
572 | { | |
573 | operands[0] = gen_lowpart (DImode, operands[0]); | |
574 | operands[1] = gen_lowpart (DImode, operands[1]); | |
575 | }) | |
576 | ||
577 | (define_expand "vec_shr_<mode>" | |
578 | [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
579 | (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "") | |
580 | (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] | |
581 | "" | |
582 | { | |
583 | operands[0] = gen_lowpart (DImode, operands[0]); | |
584 | operands[1] = gen_lowpart (DImode, operands[1]); | |
585 | }) | |
586 | ||
e898620c RH |
587 | (define_expand "widen_usumv8qi3" |
588 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
589 | (match_operand:V8QI 1 "gr_register_operand" "") | |
590 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
591 | "" | |
592 | { | |
593 | ia64_expand_widen_sum (operands, true); | |
594 | DONE; | |
595 | }) | |
596 | ||
597 | (define_expand "widen_usumv4hi3" | |
598 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
599 | (match_operand:V4HI 1 "gr_register_operand" "") | |
600 | (match_operand:V2SI 2 "gr_register_operand" "")] | |
601 | "" | |
602 | { | |
603 | ia64_expand_widen_sum (operands, true); | |
604 | DONE; | |
605 | }) | |
606 | ||
607 | (define_expand "widen_ssumv8qi3" | |
608 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
609 | (match_operand:V8QI 1 "gr_register_operand" "") | |
610 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
611 | "" | |
612 | { | |
613 | ia64_expand_widen_sum (operands, false); | |
614 | DONE; | |
615 | }) | |
616 | ||
617 | (define_expand "widen_ssumv4hi3" | |
618 | [(match_operand:V2SI 0 "gr_register_operand" "") | |
619 | (match_operand:V4HI 1 "gr_register_operand" "") | |
620 | (match_operand:V2SI 2 "gr_register_operand" "")] | |
621 | "" | |
622 | { | |
623 | ia64_expand_widen_sum (operands, false); | |
624 | DONE; | |
625 | }) | |
626 | ||
e9e1d143 | 627 | (define_expand "vcond<mode><mode>" |
f61134e8 RH |
628 | [(set (match_operand:VECINT 0 "gr_register_operand" "") |
629 | (if_then_else:VECINT | |
630 | (match_operator 3 "" | |
631 | [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") | |
632 | (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) | |
633 | (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
634 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
635 | "" | |
636 | { | |
637 | ia64_expand_vecint_cmov (operands); | |
638 | DONE; | |
639 | }) | |
640 | ||
e9e1d143 | 641 | (define_expand "vcondu<mode><mode>" |
f61134e8 RH |
642 | [(set (match_operand:VECINT 0 "gr_register_operand" "") |
643 | (if_then_else:VECINT | |
644 | (match_operator 3 "" | |
645 | [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") | |
646 | (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) | |
647 | (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
648 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
649 | "" | |
650 | { | |
651 | ia64_expand_vecint_cmov (operands); | |
652 | DONE; | |
653 | }) | |
654 | ||
655 | (define_insn "*cmpeq_<mode>" | |
656 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
657 | (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") | |
658 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] | |
659 | "" | |
660 | "pcmp<vecsize>.eq %0 = %r1, %r2" | |
661 | [(set_attr "itanium_class" "mmalua")]) | |
662 | ||
663 | (define_insn "*cmpgt_<mode>" | |
664 | [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
665 | (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") | |
666 | (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] | |
667 | "" | |
668 | "pcmp<vecsize>.gt %0 = %r1, %r2" | |
669 | [(set_attr "itanium_class" "mmalua")]) | |
670 | ||
604e3ff3 | 671 | (define_insn "vec_pack_ssat_v4hi" |
f61134e8 RH |
672 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
673 | (vec_concat:V8QI | |
674 | (ss_truncate:V4QI | |
675 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) | |
676 | (ss_truncate:V4QI | |
677 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] | |
678 | "" | |
55eaaa5b RH |
679 | { |
680 | /* Recall that vector elements are numbered in memory order. */ | |
681 | if (TARGET_BIG_ENDIAN) | |
682 | return "%,pack2.sss %0 = %r2, %r1"; | |
683 | else | |
684 | return "%,pack2.sss %0 = %r1, %r2"; | |
685 | } | |
f61134e8 RH |
686 | [(set_attr "itanium_class" "mmshf")]) |
687 | ||
604e3ff3 | 688 | (define_insn "vec_pack_usat_v4hi" |
f61134e8 RH |
689 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
690 | (vec_concat:V8QI | |
691 | (us_truncate:V4QI | |
692 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) | |
693 | (us_truncate:V4QI | |
694 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] | |
695 | "" | |
55eaaa5b RH |
696 | { |
697 | /* Recall that vector elements are numbered in memory order. */ | |
698 | if (TARGET_BIG_ENDIAN) | |
699 | return "%,pack2.uss %0 = %r2, %r1"; | |
700 | else | |
701 | return "%,pack2.uss %0 = %r1, %r2"; | |
702 | } | |
f61134e8 RH |
703 | [(set_attr "itanium_class" "mmshf")]) |
704 | ||
604e3ff3 | 705 | (define_insn "vec_pack_ssat_v2si" |
f61134e8 RH |
706 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
707 | (vec_concat:V4HI | |
708 | (ss_truncate:V2HI | |
709 | (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")) | |
710 | (ss_truncate:V2HI | |
711 | (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))] | |
712 | "" | |
55eaaa5b RH |
713 | { |
714 | /* Recall that vector elements are numbered in memory order. */ | |
715 | if (TARGET_BIG_ENDIAN) | |
716 | return "%,pack4.sss %0 = %r2, %r1"; | |
717 | else | |
718 | return "%,pack4.sss %0 = %r1, %r2"; | |
719 | } | |
f61134e8 RH |
720 | [(set_attr "itanium_class" "mmshf")]) |
721 | ||
e6431744 | 722 | (define_insn "*vec_interleave_lowv8qi" |
f61134e8 RH |
723 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
724 | (vec_select:V8QI | |
725 | (vec_concat:V16QI | |
726 | (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
727 | (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
604e3ff3 RH |
728 | (parallel [(const_int 0) (const_int 8) |
729 | (const_int 1) (const_int 9) | |
730 | (const_int 2) (const_int 10) | |
731 | (const_int 3) (const_int 11)])))] | |
f61134e8 | 732 | "" |
d2cd871f SE |
733 | { |
734 | /* Recall that vector elements are numbered in memory order. */ | |
735 | if (TARGET_BIG_ENDIAN) | |
736 | return "%,unpack1.l %0 = %r1, %r2"; | |
737 | else | |
738 | return "%,unpack1.l %0 = %r2, %r1"; | |
739 | } | |
f61134e8 RH |
740 | [(set_attr "itanium_class" "mmshf")]) |
741 | ||
e6431744 | 742 | (define_insn "*vec_interleave_highv8qi" |
f61134e8 RH |
743 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
744 | (vec_select:V8QI | |
745 | (vec_concat:V16QI | |
746 | (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
747 | (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
604e3ff3 RH |
748 | (parallel [(const_int 4) (const_int 12) |
749 | (const_int 5) (const_int 13) | |
750 | (const_int 6) (const_int 14) | |
751 | (const_int 7) (const_int 15)])))] | |
f61134e8 | 752 | "" |
d2cd871f SE |
753 | { |
754 | /* Recall that vector elements are numbered in memory order. */ | |
755 | if (TARGET_BIG_ENDIAN) | |
756 | return "%,unpack1.h %0 = %r1, %r2"; | |
757 | else | |
758 | return "%,unpack1.h %0 = %r2, %r1"; | |
759 | } | |
f61134e8 RH |
760 | [(set_attr "itanium_class" "mmshf")]) |
761 | ||
e6431744 | 762 | (define_insn "*mix1_even" |
f61134e8 RH |
763 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
764 | (vec_select:V8QI | |
765 | (vec_concat:V16QI | |
766 | (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
767 | (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
768 | (parallel [(const_int 0) (const_int 8) |
769 | (const_int 2) (const_int 10) | |
770 | (const_int 4) (const_int 12) | |
771 | (const_int 6) (const_int 14)])))] | |
772 | "" | |
773 | { | |
774 | /* Recall that vector elements are numbered in memory order. */ | |
775 | if (TARGET_BIG_ENDIAN) | |
776 | return "%,mix1.l %0 = %r1, %r2"; | |
777 | else | |
778 | return "%,mix1.r %0 = %r2, %r1"; | |
779 | } | |
f61134e8 RH |
780 | [(set_attr "itanium_class" "mmshf")]) |
781 | ||
e6431744 | 782 | (define_insn "*mix1_odd" |
f61134e8 RH |
783 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
784 | (vec_select:V8QI | |
785 | (vec_concat:V16QI | |
786 | (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
787 | (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
788 | (parallel [(const_int 1) (const_int 9) |
789 | (const_int 3) (const_int 11) | |
790 | (const_int 5) (const_int 13) | |
791 | (const_int 7) (const_int 15)])))] | |
792 | "" | |
793 | { | |
794 | /* Recall that vector elements are numbered in memory order. */ | |
795 | if (TARGET_BIG_ENDIAN) | |
796 | return "%,mix1.r %0 = %r1, %r2"; | |
797 | else | |
798 | return "%,mix1.l %0 = %r2, %r1"; | |
799 | } | |
f61134e8 RH |
800 | [(set_attr "itanium_class" "mmshf")]) |
801 | ||
802 | (define_insn "*mux1_rev" | |
803 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
804 | (vec_select:V8QI | |
805 | (match_operand:V8QI 1 "gr_register_operand" "r") | |
55eaaa5b RH |
806 | (parallel [(const_int 7) (const_int 6) |
807 | (const_int 5) (const_int 4) | |
808 | (const_int 3) (const_int 2) | |
809 | (const_int 1) (const_int 0)])))] | |
f61134e8 RH |
810 | "" |
811 | "mux1 %0 = %1, @rev" | |
812 | [(set_attr "itanium_class" "mmshf")]) | |
813 | ||
814 | (define_insn "*mux1_mix" | |
815 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
816 | (vec_select:V8QI | |
817 | (match_operand:V8QI 1 "gr_register_operand" "r") | |
55eaaa5b RH |
818 | (parallel [(const_int 0) (const_int 4) |
819 | (const_int 2) (const_int 6) | |
820 | (const_int 1) (const_int 5) | |
821 | (const_int 3) (const_int 7)])))] | |
f61134e8 RH |
822 | "" |
823 | "mux1 %0 = %1, @mix" | |
824 | [(set_attr "itanium_class" "mmshf")]) | |
825 | ||
826 | (define_insn "*mux1_shuf" | |
827 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
828 | (vec_select:V8QI | |
829 | (match_operand:V8QI 1 "gr_register_operand" "r") | |
55eaaa5b RH |
830 | (parallel [(const_int 0) (const_int 4) |
831 | (const_int 1) (const_int 5) | |
832 | (const_int 2) (const_int 6) | |
833 | (const_int 3) (const_int 7)])))] | |
f61134e8 RH |
834 | "" |
835 | "mux1 %0 = %1, @shuf" | |
836 | [(set_attr "itanium_class" "mmshf")]) | |
837 | ||
e6431744 | 838 | (define_insn "*mux1_alt" |
f61134e8 RH |
839 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
840 | (vec_select:V8QI | |
841 | (match_operand:V8QI 1 "gr_register_operand" "r") | |
55eaaa5b RH |
842 | (parallel [(const_int 0) (const_int 2) |
843 | (const_int 4) (const_int 6) | |
844 | (const_int 1) (const_int 3) | |
845 | (const_int 5) (const_int 7)])))] | |
f61134e8 RH |
846 | "" |
847 | "mux1 %0 = %1, @alt" | |
848 | [(set_attr "itanium_class" "mmshf")]) | |
849 | ||
850 | (define_insn "*mux1_brcst_v8qi" | |
851 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
852 | (vec_select:V8QI | |
853 | (match_operand:V8QI 1 "gr_register_operand" "r") | |
55eaaa5b RH |
854 | (parallel [(match_operand 2 "mux1_brcst_element" "") |
855 | (match_dup 2) | |
856 | (match_dup 2) | |
857 | (match_dup 2) | |
858 | (match_dup 2) | |
859 | (match_dup 2) | |
860 | (match_dup 2) | |
861 | (match_dup 2)])))] | |
f61134e8 RH |
862 | "" |
863 | "mux1 %0 = %1, @brcst" | |
864 | [(set_attr "itanium_class" "mmshf")]) | |
865 | ||
e6431744 | 866 | (define_insn "mux1_brcst_qi" |
f61134e8 RH |
867 | [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
868 | (vec_duplicate:V8QI | |
869 | (match_operand:QI 1 "gr_register_operand" "r")))] | |
870 | "" | |
871 | "mux1 %0 = %1, @brcst" | |
872 | [(set_attr "itanium_class" "mmshf")]) | |
873 | ||
e6431744 | 874 | (define_insn "*vec_interleave_lowv4hi" |
f61134e8 RH |
875 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
876 | (vec_select:V4HI | |
877 | (vec_concat:V8HI | |
878 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
879 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
880 | (parallel [(const_int 0) (const_int 4) |
881 | (const_int 1) (const_int 5)])))] | |
f61134e8 | 882 | "" |
d2cd871f SE |
883 | { |
884 | /* Recall that vector elements are numbered in memory order. */ | |
885 | if (TARGET_BIG_ENDIAN) | |
886 | return "%,unpack2.l %0 = %r1, %r2"; | |
887 | else | |
888 | return "%,unpack2.l %0 = %r2, %r1"; | |
889 | } | |
f61134e8 RH |
890 | [(set_attr "itanium_class" "mmshf")]) |
891 | ||
e6431744 | 892 | (define_insn "*vec_interleave_highv4hi" |
f61134e8 RH |
893 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
894 | (vec_select:V4HI | |
895 | (vec_concat:V8HI | |
896 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
897 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
898 | (parallel [(const_int 2) (const_int 6) |
899 | (const_int 3) (const_int 7)])))] | |
f61134e8 | 900 | "" |
d2cd871f SE |
901 | { |
902 | /* Recall that vector elements are numbered in memory order. */ | |
903 | if (TARGET_BIG_ENDIAN) | |
904 | return "%,unpack2.h %0 = %r1, %r2"; | |
905 | else | |
906 | return "%,unpack2.h %0 = %r2, %r1"; | |
907 | } | |
f61134e8 RH |
908 | [(set_attr "itanium_class" "mmshf")]) |
909 | ||
55eaaa5b | 910 | (define_insn "mix2_even" |
f61134e8 RH |
911 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
912 | (vec_select:V4HI | |
913 | (vec_concat:V8HI | |
914 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
915 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
916 | (parallel [(const_int 0) (const_int 4) |
917 | (const_int 2) (const_int 6)])))] | |
f61134e8 | 918 | "" |
55eaaa5b RH |
919 | { |
920 | /* Recall that vector elements are numbered in memory order. */ | |
921 | if (TARGET_BIG_ENDIAN) | |
922 | return "%,mix2.l %0 = %r1, %r2"; | |
923 | else | |
924 | return "%,mix2.r %0 = %r2, %r1"; | |
925 | } | |
f61134e8 RH |
926 | [(set_attr "itanium_class" "mmshf")]) |
927 | ||
55eaaa5b | 928 | (define_insn "mix2_odd" |
f61134e8 RH |
929 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
930 | (vec_select:V4HI | |
931 | (vec_concat:V8HI | |
932 | (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
933 | (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b RH |
934 | (parallel [(const_int 1) (const_int 5) |
935 | (const_int 3) (const_int 7)])))] | |
f61134e8 | 936 | "" |
55eaaa5b RH |
937 | { |
938 | /* Recall that vector elements are numbered in memory order. */ | |
939 | if (TARGET_BIG_ENDIAN) | |
940 | return "%,mix2.r %0 = %r1, %r2"; | |
941 | else | |
942 | return "%,mix2.l %0 = %r2, %r1"; | |
943 | } | |
f61134e8 RH |
944 | [(set_attr "itanium_class" "mmshf")]) |
945 | ||
946 | (define_insn "*mux2" | |
947 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
948 | (vec_select:V4HI | |
949 | (match_operand:V4HI 1 "gr_register_operand" "r") | |
950 | (parallel [(match_operand 2 "const_int_2bit_operand" "") | |
951 | (match_operand 3 "const_int_2bit_operand" "") | |
952 | (match_operand 4 "const_int_2bit_operand" "") | |
953 | (match_operand 5 "const_int_2bit_operand" "")])))] | |
954 | "" | |
955 | { | |
55eaaa5b | 956 | int mask = 0; |
e435f098 SE |
957 | if (TARGET_BIG_ENDIAN) |
958 | { | |
55eaaa5b RH |
959 | mask |= (3 - INTVAL (operands[2])) << 6; |
960 | mask |= (3 - INTVAL (operands[3])) << 4; | |
961 | mask |= (3 - INTVAL (operands[4])) << 2; | |
962 | mask |= 3 - INTVAL (operands[5]); | |
e435f098 SE |
963 | } |
964 | else | |
965 | { | |
55eaaa5b | 966 | mask |= INTVAL (operands[2]); |
e435f098 SE |
967 | mask |= INTVAL (operands[3]) << 2; |
968 | mask |= INTVAL (operands[4]) << 4; | |
969 | mask |= INTVAL (operands[5]) << 6; | |
970 | } | |
f61134e8 RH |
971 | operands[2] = GEN_INT (mask); |
972 | return "%,mux2 %0 = %1, %2"; | |
973 | } | |
974 | [(set_attr "itanium_class" "mmshf")]) | |
975 | ||
976 | (define_insn "*mux2_brcst_hi" | |
977 | [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
978 | (vec_duplicate:V4HI | |
979 | (match_operand:HI 1 "gr_register_operand" "r")))] | |
980 | "" | |
981 | "mux2 %0 = %1, 0" | |
982 | [(set_attr "itanium_class" "mmshf")]) | |
983 | ||
e6431744 | 984 | (define_insn "*vec_interleave_lowv2si" |
f61134e8 RH |
985 | [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
986 | (vec_select:V2SI | |
987 | (vec_concat:V4SI | |
988 | (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") | |
989 | (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b | 990 | (parallel [(const_int 0) (const_int 2)])))] |
f61134e8 | 991 | "" |
d2cd871f SE |
992 | { |
993 | /* Recall that vector elements are numbered in memory order. */ | |
994 | if (TARGET_BIG_ENDIAN) | |
e435f098 | 995 | return "%,unpack4.l %0 = %r1, %r2"; |
d2cd871f SE |
996 | else |
997 | return "%,unpack4.l %0 = %r2, %r1"; | |
998 | } | |
f61134e8 RH |
999 | [(set_attr "itanium_class" "mmshf")]) |
1000 | ||
e6431744 | 1001 | (define_insn "*vec_interleave_highv2si" |
f61134e8 RH |
1002 | [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
1003 | (vec_select:V2SI | |
1004 | (vec_concat:V4SI | |
1005 | (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") | |
1006 | (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) | |
55eaaa5b | 1007 | (parallel [(const_int 1) (const_int 3)])))] |
f61134e8 | 1008 | "" |
d2cd871f SE |
1009 | { |
1010 | /* Recall that vector elements are numbered in memory order. */ | |
1011 | if (TARGET_BIG_ENDIAN) | |
e435f098 | 1012 | return "%,unpack4.h %0 = %r1, %r2"; |
d2cd871f SE |
1013 | else |
1014 | return "%,unpack4.h %0 = %r2, %r1"; | |
1015 | } | |
f61134e8 RH |
1016 | [(set_attr "itanium_class" "mmshf")]) |
1017 | ||
1018 | (define_expand "vec_initv2si" | |
10dc6e8c | 1019 | [(match_operand:V2SI 0 "gr_register_operand" "") |
f61134e8 RH |
1020 | (match_operand 1 "" "")] |
1021 | "" | |
1022 | { | |
1023 | rtx op1 = XVECEXP (operands[1], 0, 0); | |
1024 | rtx op2 = XVECEXP (operands[1], 0, 1); | |
1025 | rtx x; | |
1026 | ||
1027 | if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT) | |
1028 | { | |
e3d693e9 | 1029 | x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0)); |
f61134e8 RH |
1030 | emit_move_insn (operands[0], x); |
1031 | DONE; | |
1032 | } | |
1033 | ||
1034 | if (!gr_reg_or_0_operand (op1, SImode)) | |
1035 | op1 = force_reg (SImode, op1); | |
1036 | if (!gr_reg_or_0_operand (op2, SImode)) | |
1037 | op2 = force_reg (SImode, op2); | |
1038 | ||
55eaaa5b | 1039 | x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2); |
f61134e8 RH |
1040 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); |
1041 | DONE; | |
1042 | }) | |
1043 | ||
1044 | (define_insn "*vecinit_v2si" | |
1045 | [(set (match_operand:V2SI 0 "gr_register_operand" "=r") | |
1046 | (vec_concat:V2SI | |
1047 | (match_operand:SI 1 "gr_reg_or_0_operand" "rO") | |
1048 | (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))] | |
1049 | "" | |
55eaaa5b RH |
1050 | { |
1051 | /* Recall that vector elements are numbered in memory order. */ | |
1052 | if (TARGET_BIG_ENDIAN) | |
1053 | return "%,unpack4.l %0 = %r1, %r2"; | |
1054 | else | |
1055 | return "%,unpack4.l %0 = %r2, %r1"; | |
1056 | } | |
f61134e8 RH |
1057 | [(set_attr "itanium_class" "mmshf")]) |
1058 | ||
1059 | ;; Missing operations | |
1060 | ;; padd.uus | |
1061 | ;; pavg | |
1062 | ;; pavgsub | |
f61134e8 RH |
1063 | ;; psad |
1064 | ;; pshladd | |
1065 | ;; pshradd | |
1066 | ;; psub.uus | |
f61134e8 RH |
1067 | \f |
1068 | ;; Floating point vector operations | |
1069 | ||
1070 | (define_expand "movv2sf" | |
1071 | [(set (match_operand:V2SF 0 "general_operand" "") | |
1072 | (match_operand:V2SF 1 "general_operand" ""))] | |
1073 | "" | |
1074 | { | |
1075 | rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1076 | if (!op1) | |
1077 | DONE; | |
1078 | operands[1] = op1; | |
1079 | }) | |
1080 | ||
1081 | (define_insn "*movv2sf_internal" | |
1082 | [(set (match_operand:V2SF 0 "destination_operand" | |
1083 | "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r") | |
1084 | (match_operand:V2SF 1 "move_operand" | |
1085 | "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))] | |
1086 | "ia64_move_ok (operands[0], operands[1])" | |
1087 | { | |
1088 | static const char * const alt[] = { | |
1089 | "%,mov %0 = %F1", | |
1090 | "%,fpack %0 = %F2, %F1", | |
1091 | "%,ldf8 %0 = %1%P1", | |
1092 | "%,stf8 %0 = %1%P0", | |
1093 | "%,mov %0 = %r1", | |
1094 | "%,addl %0 = %v1, r0", | |
1095 | "%,movl %0 = %v1", | |
1096 | "%,ld8%O1 %0 = %1%P1", | |
1097 | "%,st8%Q0 %0 = %r1%P0", | |
1098 | "%,setf.sig %0 = %1", | |
1099 | "%,getf.sig %0 = %1" | |
1100 | }; | |
1101 | ||
1102 | if (which_alternative == 1) | |
1103 | { | |
19d892fd SE |
1104 | operands[2] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 0 : 1); |
1105 | operands[1] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 1 : 0); | |
f61134e8 RH |
1106 | } |
1107 | ||
1108 | return alt[which_alternative]; | |
1109 | } | |
1110 | [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")]) | |
1111 | ||
1112 | (define_insn "absv2sf2" | |
1113 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1114 | (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] | |
1115 | "" | |
1116 | "fpabs %0 = %1" | |
1117 | [(set_attr "itanium_class" "fmisc")]) | |
1118 | ||
1119 | (define_insn "negv2sf2" | |
1120 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1121 | (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] | |
1122 | "" | |
1123 | "fpneg %0 = %1" | |
1124 | [(set_attr "itanium_class" "fmisc")]) | |
1125 | ||
1126 | (define_insn "*negabsv2sf2" | |
1127 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1128 | (neg:V2SF | |
1129 | (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))] | |
1130 | "" | |
1131 | "fpnegabs %0 = %1" | |
1132 | [(set_attr "itanium_class" "fmisc")]) | |
1133 | ||
1134 | (define_expand "addv2sf3" | |
f19f1e5e RH |
1135 | [(set (match_operand:V2SF 0 "fr_register_operand" "") |
1136 | (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "") | |
1137 | (match_dup 3) | |
1138 | (match_operand:V2SF 2 "fr_register_operand" "")))] | |
f61134e8 RH |
1139 | "" |
1140 | { | |
1141 | rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); | |
1142 | operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); | |
1143 | }) | |
1144 | ||
1145 | (define_expand "subv2sf3" | |
f19f1e5e RH |
1146 | [(set (match_operand:V2SF 0 "fr_register_operand" "") |
1147 | (fma:V2SF | |
1148 | (match_operand:V2SF 1 "fr_register_operand" "") | |
1149 | (match_dup 3) | |
1150 | (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))] | |
f61134e8 RH |
1151 | "" |
1152 | { | |
1153 | rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode)); | |
1154 | operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v)); | |
1155 | }) | |
1156 | ||
1157 | (define_insn "mulv2sf3" | |
1158 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1159 | (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1160 | (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1161 | "" | |
1162 | "fpmpy %0 = %1, %2" | |
1163 | [(set_attr "itanium_class" "fmac")]) | |
1164 | ||
f19f1e5e | 1165 | (define_insn "fmav2sf4" |
f61134e8 | 1166 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
f19f1e5e RH |
1167 | (fma:V2SF |
1168 | (match_operand:V2SF 1 "fr_register_operand" "f") | |
1169 | (match_operand:V2SF 2 "fr_register_operand" "f") | |
f61134e8 RH |
1170 | (match_operand:V2SF 3 "fr_register_operand" "f")))] |
1171 | "" | |
1172 | "fpma %0 = %1, %2, %3" | |
1173 | [(set_attr "itanium_class" "fmac")]) | |
1174 | ||
f19f1e5e | 1175 | (define_insn "fmsv2sf4" |
f61134e8 | 1176 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
f19f1e5e RH |
1177 | (fma:V2SF |
1178 | (match_operand:V2SF 1 "fr_register_operand" "f") | |
1179 | (match_operand:V2SF 2 "fr_register_operand" "f") | |
1180 | (neg:V2SF (match_operand:V2SF 3 "fr_register_operand" "f"))))] | |
f61134e8 RH |
1181 | "" |
1182 | "fpms %0 = %1, %2, %3" | |
1183 | [(set_attr "itanium_class" "fmac")]) | |
1184 | ||
1185 | (define_insn "*fpnmpy" | |
1186 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1187 | (neg:V2SF | |
1188 | (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1189 | (match_operand:V2SF 2 "fr_register_operand" "f"))))] | |
1190 | "" | |
1191 | "fpnmpy %0 = %1, %2" | |
1192 | [(set_attr "itanium_class" "fmac")]) | |
1193 | ||
f19f1e5e | 1194 | (define_insn "fnmav2sf4" |
f61134e8 | 1195 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
f19f1e5e RH |
1196 | (fma:V2SF |
1197 | (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")) | |
1198 | (match_operand:V2SF 2 "fr_register_operand" "f") | |
f61134e8 RH |
1199 | (match_operand:V2SF 3 "fr_register_operand" "f")))] |
1200 | "" | |
1201 | "fpnma %0 = %1, %2, %3" | |
1202 | [(set_attr "itanium_class" "fmac")]) | |
1203 | ||
b4e3537b | 1204 | (define_insn "smaxv2sf3" |
f61134e8 RH |
1205 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1206 | (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1207 | (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1208 | "" | |
1209 | "fpmax %0 = %1, %2" | |
1210 | [(set_attr "itanium_class" "fmisc")]) | |
1211 | ||
b4e3537b | 1212 | (define_insn "sminv2sf3" |
f61134e8 RH |
1213 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1214 | (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1215 | (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1216 | "" | |
1217 | "fpmin %0 = %1, %2" | |
1218 | [(set_attr "itanium_class" "fmisc")]) | |
1219 | ||
e898620c | 1220 | (define_expand "reduc_splus_v2sf" |
b4e3537b RH |
1221 | [(match_operand:V2SF 0 "fr_register_operand" "") |
1222 | (match_operand:V2SF 1 "fr_register_operand" "")] | |
1223 | "" | |
1224 | { | |
1225 | rtx tmp = gen_reg_rtx (V2SFmode); | |
55eaaa5b RH |
1226 | if (TARGET_BIG_ENDIAN) |
1227 | emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); | |
1228 | else | |
1229 | emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); | |
b4e3537b RH |
1230 | emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp)); |
1231 | DONE; | |
1232 | }) | |
1233 | ||
1234 | (define_expand "reduc_smax_v2sf" | |
1235 | [(match_operand:V2SF 0 "fr_register_operand" "") | |
1236 | (match_operand:V2SF 1 "fr_register_operand" "")] | |
1237 | "" | |
1238 | { | |
1239 | rtx tmp = gen_reg_rtx (V2SFmode); | |
55eaaa5b RH |
1240 | if (TARGET_BIG_ENDIAN) |
1241 | emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); | |
1242 | else | |
1243 | emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); | |
b4e3537b RH |
1244 | emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp)); |
1245 | DONE; | |
1246 | }) | |
1247 | ||
1248 | (define_expand "reduc_smin_v2sf" | |
1249 | [(match_operand:V2SF 0 "fr_register_operand" "") | |
1250 | (match_operand:V2SF 1 "fr_register_operand" "")] | |
1251 | "" | |
1252 | { | |
1253 | rtx tmp = gen_reg_rtx (V2SFmode); | |
55eaaa5b RH |
1254 | if (TARGET_BIG_ENDIAN) |
1255 | emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); | |
1256 | else | |
1257 | emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); | |
b4e3537b RH |
1258 | emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp)); |
1259 | DONE; | |
1260 | }) | |
1261 | ||
e9e1d143 | 1262 | (define_expand "vcondv2sfv2sf" |
f61134e8 RH |
1263 | [(set (match_operand:V2SF 0 "fr_register_operand" "") |
1264 | (if_then_else:V2SF | |
1265 | (match_operator 3 "" | |
1266 | [(match_operand:V2SF 4 "fr_reg_or_0_operand" "") | |
1267 | (match_operand:V2SF 5 "fr_reg_or_0_operand" "")]) | |
1268 | (match_operand:V2SF 1 "fr_reg_or_0_operand" "") | |
1269 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))] | |
1270 | "" | |
1271 | { | |
1272 | rtx x, cmp; | |
1273 | ||
f61134e8 | 1274 | cmp = gen_reg_rtx (V2SFmode); |
c8d3810f | 1275 | PUT_MODE (operands[3], V2SFmode); |
f61134e8 RH |
1276 | emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3])); |
1277 | ||
1278 | x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]); | |
1279 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); | |
1280 | DONE; | |
1281 | }) | |
1282 | ||
1283 | (define_insn "*fpcmp" | |
c8d3810f RH |
1284 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1285 | (match_operator:V2SF 3 "comparison_operator" | |
1286 | [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1287 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))] | |
1288 | "" | |
1289 | "fpcmp.%D3 %0 = %F1, %F2" | |
1290 | [(set_attr "itanium_class" "fmisc")]) | |
1291 | ||
1292 | (define_insn "*fselect" | |
f61134e8 RH |
1293 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1294 | (if_then_else:V2SF | |
1295 | (match_operand:V2SF 1 "fr_register_operand" "f") | |
1296 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU") | |
1297 | (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))] | |
1298 | "" | |
c8d3810f | 1299 | "fselect %0 = %F2, %F3, %1" |
f61134e8 RH |
1300 | [(set_attr "itanium_class" "fmisc")]) |
1301 | ||
1302 | (define_expand "vec_initv2sf" | |
1303 | [(match_operand:V2SF 0 "fr_register_operand" "") | |
1304 | (match_operand 1 "" "")] | |
1305 | "" | |
1306 | { | |
1307 | rtx op1 = XVECEXP (operands[1], 0, 0); | |
1308 | rtx op2 = XVECEXP (operands[1], 0, 1); | |
1309 | rtx x; | |
1310 | ||
1311 | if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE) | |
1312 | { | |
1313 | x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0)); | |
1314 | emit_move_insn (operands[0], x); | |
1315 | DONE; | |
1316 | } | |
1317 | ||
1318 | if (!fr_reg_or_fp01_operand (op1, SFmode)) | |
1319 | op1 = force_reg (SFmode, op1); | |
1320 | if (!fr_reg_or_fp01_operand (op2, SFmode)) | |
1321 | op2 = force_reg (SFmode, op2); | |
1322 | ||
55eaaa5b | 1323 | emit_insn (gen_fpack (operands[0], op1, op2)); |
f61134e8 RH |
1324 | DONE; |
1325 | }) | |
1326 | ||
b4e3537b | 1327 | (define_insn "fpack" |
f61134e8 RH |
1328 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1329 | (vec_concat:V2SF | |
1330 | (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
1331 | (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
1332 | "" | |
55eaaa5b RH |
1333 | { |
1334 | /* Recall that vector elements are numbered in memory order. */ | |
1335 | if (TARGET_BIG_ENDIAN) | |
1336 | return "%,fpack %0 = %F1, %F2"; | |
1337 | else | |
1338 | return "%,fpack %0 = %F2, %F1"; | |
1339 | } | |
f61134e8 RH |
1340 | [(set_attr "itanium_class" "fmisc")]) |
1341 | ||
b4e3537b RH |
1342 | (define_insn "fswap" |
1343 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1344 | (vec_select:V2SF | |
1345 | (vec_concat:V4SF | |
1346 | (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1347 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1348 | (parallel [(const_int 1) (const_int 2)])))] | |
1349 | "" | |
55eaaa5b RH |
1350 | { |
1351 | /* Recall that vector elements are numbered in memory order. */ | |
1352 | if (TARGET_BIG_ENDIAN) | |
1353 | return "%,fswap %0 = %F2, %F1"; | |
1354 | else | |
1355 | return "%,fswap %0 = %F1, %F2"; | |
1356 | } | |
b4e3537b RH |
1357 | [(set_attr "itanium_class" "fmisc")]) |
1358 | ||
e6431744 | 1359 | (define_insn "*vec_interleave_highv2sf" |
b4e3537b RH |
1360 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1361 | (vec_select:V2SF | |
1362 | (vec_concat:V4SF | |
1363 | (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1364 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1365 | (parallel [(const_int 1) (const_int 3)])))] | |
1366 | "" | |
55eaaa5b RH |
1367 | { |
1368 | /* Recall that vector elements are numbered in memory order. */ | |
1369 | if (TARGET_BIG_ENDIAN) | |
821014aa | 1370 | return "%,fmix.l %0 = %F1, %F2"; |
55eaaa5b RH |
1371 | else |
1372 | return "%,fmix.l %0 = %F2, %F1"; | |
1373 | } | |
b4e3537b RH |
1374 | [(set_attr "itanium_class" "fmisc")]) |
1375 | ||
e6431744 | 1376 | (define_insn "*vec_interleave_lowv2sf" |
b4e3537b RH |
1377 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1378 | (vec_select:V2SF | |
1379 | (vec_concat:V4SF | |
1380 | (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1381 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1382 | (parallel [(const_int 0) (const_int 2)])))] | |
1383 | "" | |
55eaaa5b RH |
1384 | { |
1385 | /* Recall that vector elements are numbered in memory order. */ | |
1386 | if (TARGET_BIG_ENDIAN) | |
821014aa | 1387 | return "%,fmix.r %0 = %F1, %F2"; |
55eaaa5b RH |
1388 | else |
1389 | return "%,fmix.r %0 = %F2, %F1"; | |
1390 | } | |
b4e3537b RH |
1391 | [(set_attr "itanium_class" "fmisc")]) |
1392 | ||
1393 | (define_insn "fmix_lr" | |
1394 | [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1395 | (vec_select:V2SF | |
1396 | (vec_concat:V4SF | |
1397 | (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1398 | (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1399 | (parallel [(const_int 0) (const_int 3)])))] | |
1400 | "" | |
55eaaa5b RH |
1401 | { |
1402 | /* Recall that vector elements are numbered in memory order. */ | |
1403 | if (TARGET_BIG_ENDIAN) | |
1404 | return "%,fmix.lr %0 = %F1, %F2"; | |
1405 | else | |
1406 | return "%,fmix.lr %0 = %F2, %F1"; | |
1407 | } | |
b4e3537b RH |
1408 | [(set_attr "itanium_class" "fmisc")]) |
1409 | ||
1410 | (define_expand "vec_setv2sf" | |
1411 | [(match_operand:V2SF 0 "fr_register_operand" "") | |
1412 | (match_operand:SF 1 "fr_register_operand" "") | |
1413 | (match_operand 2 "const_int_operand" "")] | |
1414 | "" | |
1415 | { | |
e6431744 | 1416 | ia64_expand_vec_setv2sf (operands); |
b4e3537b RH |
1417 | DONE; |
1418 | }) | |
1419 | ||
1420 | (define_insn_and_split "*vec_extractv2sf_0_le" | |
1421 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m") | |
1422 | (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r") | |
1423 | (const_int 0)] | |
1424 | UNSPEC_VECT_EXTR))] | |
1425 | "!TARGET_BIG_ENDIAN" | |
1426 | "#" | |
1427 | "reload_completed" | |
1428 | [(set (match_dup 0) (match_dup 1))] | |
1429 | { | |
1430 | if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1]))) | |
1431 | operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0])); | |
1432 | else if (MEM_P (operands[1])) | |
1433 | operands[1] = adjust_address (operands[1], SFmode, 0); | |
1434 | else | |
1435 | operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); | |
1436 | }) | |
1437 | ||
1438 | (define_insn_and_split "*vec_extractv2sf_0_be" | |
55eaaa5b RH |
1439 | [(set (match_operand:SF 0 "register_operand" "=rf,r") |
1440 | (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "m,r") | |
b4e3537b RH |
1441 | (const_int 0)] |
1442 | UNSPEC_VECT_EXTR))] | |
1443 | "TARGET_BIG_ENDIAN" | |
1444 | "#" | |
1445 | "reload_completed" | |
1446 | [(set (match_dup 0) (match_dup 1))] | |
1447 | { | |
55eaaa5b RH |
1448 | if (MEM_P (operands[1])) |
1449 | operands[1] = adjust_address (operands[1], SFmode, 0); | |
b4e3537b | 1450 | else |
55eaaa5b RH |
1451 | { |
1452 | emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); | |
1453 | DONE; | |
1454 | } | |
b4e3537b RH |
1455 | }) |
1456 | ||
55eaaa5b | 1457 | (define_insn_and_split "*vec_extractv2sf_1_le" |
e364ab3a | 1458 | [(set (match_operand:SF 0 "register_operand" "=r") |
b4e3537b RH |
1459 | (unspec:SF [(match_operand:V2SF 1 "register_operand" "r") |
1460 | (const_int 1)] | |
1461 | UNSPEC_VECT_EXTR))] | |
55eaaa5b | 1462 | "!TARGET_BIG_ENDIAN" |
b4e3537b | 1463 | "#" |
55eaaa5b | 1464 | "&& reload_completed" |
b4e3537b RH |
1465 | [(const_int 0)] |
1466 | { | |
e364ab3a RH |
1467 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); |
1468 | operands[1] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
55eaaa5b | 1469 | emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); |
b4e3537b RH |
1470 | DONE; |
1471 | }) | |
1472 | ||
55eaaa5b RH |
1473 | (define_insn_and_split "*vec_extractv2sf_1_be" |
1474 | [(set (match_operand:SF 0 "register_operand" "=rf") | |
1475 | (unspec:SF [(match_operand:V2SF 1 "register_operand" "r") | |
1476 | (const_int 1)] | |
1477 | UNSPEC_VECT_EXTR))] | |
1478 | "TARGET_BIG_ENDIAN" | |
1479 | "#" | |
1480 | "&& reload_completed" | |
1481 | [(set (match_dup 0) (match_dup 1))] | |
1482 | { | |
1483 | operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); | |
1484 | }) | |
1485 | ||
b4e3537b RH |
1486 | (define_expand "vec_extractv2sf" |
1487 | [(set (match_operand:SF 0 "register_operand" "") | |
1488 | (unspec:SF [(match_operand:V2SF 1 "register_operand" "") | |
1489 | (match_operand:DI 2 "const_int_operand" "")] | |
1490 | UNSPEC_VECT_EXTR))] | |
1491 | "" | |
1492 | "") | |
1493 | ||
604e3ff3 RH |
1494 | (define_expand "vec_unpacku_lo_<mode>" |
1495 | [(match_operand:<vecwider> 0 "register_operand" "") | |
1496 | (match_operand:VECINT12 1 "register_operand" "")] | |
1497 | "" | |
1498 | { | |
1499 | ia64_expand_unpack (operands, true, false); | |
1500 | DONE; | |
1501 | }) | |
1502 | ||
1503 | (define_expand "vec_unpacku_hi_<mode>" | |
1504 | [(match_operand:<vecwider> 0 "register_operand" "") | |
1505 | (match_operand:VECINT12 1 "register_operand" "")] | |
1506 | "" | |
1507 | { | |
1508 | ia64_expand_unpack (operands, true, true); | |
1509 | DONE; | |
1510 | }) | |
1511 | ||
1512 | (define_expand "vec_unpacks_lo_<mode>" | |
1513 | [(match_operand:<vecwider> 0 "register_operand" "") | |
1514 | (match_operand:VECINT12 1 "register_operand" "")] | |
1515 | "" | |
1516 | { | |
1517 | ia64_expand_unpack (operands, false, false); | |
1518 | DONE; | |
1519 | }) | |
1520 | ||
1521 | (define_expand "vec_unpacks_hi_<mode>" | |
1522 | [(match_operand:<vecwider> 0 "register_operand" "") | |
1523 | (match_operand:VECINT12 1 "register_operand" "")] | |
1524 | "" | |
1525 | { | |
1526 | ia64_expand_unpack (operands, false, true); | |
1527 | DONE; | |
1528 | }) | |
1529 | ||
1530 | (define_expand "vec_pack_trunc_v4hi" | |
1531 | [(match_operand:V8QI 0 "gr_register_operand" "") | |
1532 | (match_operand:V4HI 1 "gr_register_operand" "") | |
1533 | (match_operand:V4HI 2 "gr_register_operand" "")] | |
55eaaa5b | 1534 | "" |
604e3ff3 | 1535 | { |
55eaaa5b RH |
1536 | rtx op1 = gen_lowpart (V8QImode, operands[1]); |
1537 | rtx op2 = gen_lowpart (V8QImode, operands[2]); | |
e6431744 | 1538 | ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); |
604e3ff3 RH |
1539 | DONE; |
1540 | }) | |
1541 | ||
1542 | (define_expand "vec_pack_trunc_v2si" | |
1543 | [(match_operand:V4HI 0 "gr_register_operand" "") | |
1544 | (match_operand:V2SI 1 "gr_register_operand" "") | |
1545 | (match_operand:V2SI 2 "gr_register_operand" "")] | |
e435f098 | 1546 | "" |
604e3ff3 | 1547 | { |
55eaaa5b RH |
1548 | rtx op1 = gen_lowpart (V4HImode, operands[1]); |
1549 | rtx op2 = gen_lowpart (V4HImode, operands[2]); | |
e6431744 | 1550 | ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); |
604e3ff3 RH |
1551 | DONE; |
1552 | }) | |
1553 | ||
e6431744 RH |
1554 | (define_expand "vec_perm_const<mode>" |
1555 | [(match_operand:VEC 0 "register_operand" "") | |
1556 | (match_operand:VEC 1 "register_operand" "") | |
1557 | (match_operand:VEC 2 "register_operand" "") | |
1558 | (match_operand:<vecint> 3 "" "")] | |
1559 | "" | |
1560 | { | |
1561 | if (ia64_expand_vec_perm_const (operands)) | |
1562 | DONE; | |
1563 | else | |
1564 | FAIL; | |
1565 | }) | |
1566 | ||
f61134e8 RH |
1567 | ;; Missing operations |
1568 | ;; fprcpa | |
1569 | ;; fpsqrta |