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6b3d1e47 SC |
1 | /* Definitions of target machine for GNU compiler. |
2 | Vitesse IQ2000 processors | |
cbe34bb5 | 3 | Copyright (C) 2003-2017 Free Software Foundation, Inc. |
6b3d1e47 SC |
4 | |
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
6b3d1e47 SC |
10 | option) any later version. |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
18 | along with GCC; see the file COPYING3. If not see |
19 | <http://www.gnu.org/licenses/>. */ | |
6b3d1e47 | 20 | |
6b3d1e47 SC |
21 | /* Driver configuration. */ |
22 | ||
57809813 | 23 | /* A generic LIB_SPEC with -leval and --*group tacked on. */ |
6b3d1e47 SC |
24 | #undef LIB_SPEC |
25 | #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}" | |
26 | ||
27 | #undef STARTFILE_SPEC | |
28 | #undef ENDFILE_SPEC | |
29 | ||
248a9e94 JM |
30 | #undef LINK_SPEC |
31 | #define LINK_SPEC "%{h*} %{v:-V} \ | |
32 | %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" | |
33 | ||
6b3d1e47 SC |
34 | \f |
35 | /* Run-time target specifications. */ | |
36 | ||
37 | #define TARGET_CPU_CPP_BUILTINS() \ | |
38 | do \ | |
39 | { \ | |
b5144086 SC |
40 | builtin_define ("__iq2000__"); \ |
41 | builtin_assert ("cpu=iq2000"); \ | |
42 | builtin_assert ("machine=iq2000"); \ | |
6b3d1e47 SC |
43 | } \ |
44 | while (0) | |
45 | ||
6b3d1e47 SC |
46 | /* Macros used in the machine description to test the flags. */ |
47 | ||
48 | #define TARGET_STATS 0 | |
49 | ||
9e1db42d RS |
50 | #define TARGET_DEBUG_MODE 0 |
51 | #define TARGET_DEBUG_A_MODE 0 | |
52 | #define TARGET_DEBUG_B_MODE 0 | |
53 | #define TARGET_DEBUG_C_MODE 0 | |
54 | #define TARGET_DEBUG_D_MODE 0 | |
6b3d1e47 SC |
55 | |
56 | #ifndef IQ2000_ISA_DEFAULT | |
57 | #define IQ2000_ISA_DEFAULT 1 | |
58 | #endif | |
6b3d1e47 SC |
59 | \f |
60 | /* Storage Layout. */ | |
61 | ||
b5144086 SC |
62 | #define BITS_BIG_ENDIAN 0 |
63 | #define BYTES_BIG_ENDIAN 1 | |
64 | #define WORDS_BIG_ENDIAN 1 | |
b5144086 SC |
65 | #define BITS_PER_WORD 32 |
66 | #define MAX_BITS_PER_WORD 64 | |
67 | #define UNITS_PER_WORD 4 | |
68 | #define MIN_UNITS_PER_WORD 4 | |
69 | #define POINTER_SIZE 32 | |
6b3d1e47 SC |
70 | |
71 | /* Define this macro if it is advisable to hold scalars in registers | |
72 | in a wider mode than that declared by the program. In such cases, | |
73 | the value is constrained to be within the bounds of the declared | |
74 | type, but kept valid in the wider mode. The signedness of the | |
75 | extension may differ from that of the type. | |
76 | ||
77 | We promote any value smaller than SImode up to SImode. */ | |
78 | ||
79 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
80 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
81 | && GET_MODE_SIZE (MODE) < 4) \ | |
82 | (MODE) = SImode; | |
83 | ||
6b3d1e47 SC |
84 | #define PARM_BOUNDARY 32 |
85 | ||
86 | #define STACK_BOUNDARY 64 | |
87 | ||
88 | #define FUNCTION_BOUNDARY 32 | |
89 | ||
90 | #define BIGGEST_ALIGNMENT 64 | |
91 | ||
b5144086 | 92 | #undef DATA_ALIGNMENT |
6b3d1e47 SC |
93 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ |
94 | ((((ALIGN) < BITS_PER_WORD) \ | |
95 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
96 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
97 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
98 | ||
99 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
100 | ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ | |
101 | && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) | |
102 | ||
103 | #define EMPTY_FIELD_BOUNDARY 32 | |
104 | ||
105 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
106 | ||
107 | #define STRICT_ALIGNMENT 1 | |
108 | ||
109 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
110 | ||
6b3d1e47 SC |
111 | \f |
112 | /* Layout of Source Language Data Types. */ | |
113 | ||
b5144086 SC |
114 | #define INT_TYPE_SIZE 32 |
115 | #define SHORT_TYPE_SIZE 16 | |
116 | #define LONG_TYPE_SIZE 32 | |
117 | #define LONG_LONG_TYPE_SIZE 64 | |
118 | #define CHAR_TYPE_SIZE BITS_PER_UNIT | |
119 | #define FLOAT_TYPE_SIZE 32 | |
120 | #define DOUBLE_TYPE_SIZE 64 | |
121 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
122 | #define DEFAULT_SIGNED_CHAR 1 | |
6b3d1e47 | 123 | |
248a9e94 JM |
124 | #undef SIZE_TYPE |
125 | #define SIZE_TYPE "unsigned int" | |
126 | ||
127 | #undef PTRDIFF_TYPE | |
128 | #define PTRDIFF_TYPE "int" | |
129 | ||
130 | #undef WCHAR_TYPE | |
131 | #define WCHAR_TYPE "long int" | |
132 | ||
133 | #undef WCHAR_TYPE_SIZE | |
134 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
135 | ||
6b3d1e47 SC |
136 | \f |
137 | /* Register Basics. */ | |
138 | ||
139 | /* On the IQ2000, we have 32 integer registers. */ | |
140 | #define FIRST_PSEUDO_REGISTER 33 | |
141 | ||
142 | #define FIXED_REGISTERS \ | |
143 | { \ | |
144 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
145 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1 \ | |
146 | } | |
147 | ||
148 | #define CALL_USED_REGISTERS \ | |
149 | { \ | |
150 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
151 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1 \ | |
152 | } | |
153 | ||
154 | \f | |
155 | /* Order of allocation of registers. */ | |
156 | ||
157 | #define REG_ALLOC_ORDER \ | |
158 | { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
159 | 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 \ | |
160 | } | |
161 | ||
162 | \f | |
6b3d1e47 | 163 | |
6b3d1e47 SC |
164 | #define AVOID_CCMODE_COPIES |
165 | ||
166 | \f | |
167 | /* Register Classes. */ | |
168 | ||
169 | enum reg_class | |
170 | { | |
b5144086 SC |
171 | NO_REGS, /* No registers in set. */ |
172 | GR_REGS, /* Integer registers. */ | |
173 | ALL_REGS, /* All registers. */ | |
174 | LIM_REG_CLASSES /* Max value + 1. */ | |
6b3d1e47 SC |
175 | }; |
176 | ||
177 | #define GENERAL_REGS GR_REGS | |
178 | ||
179 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
180 | ||
b5144086 SC |
181 | #define REG_CLASS_NAMES \ |
182 | { \ | |
183 | "NO_REGS", \ | |
184 | "GR_REGS", \ | |
185 | "ALL_REGS" \ | |
6b3d1e47 SC |
186 | } |
187 | ||
b5144086 SC |
188 | #define REG_CLASS_CONTENTS \ |
189 | { \ | |
190 | { 0x00000000, 0x00000000 }, /* No registers, */ \ | |
191 | { 0xffffffff, 0x00000000 }, /* Integer registers. */ \ | |
192 | { 0xffffffff, 0x00000001 } /* All registers. */ \ | |
6b3d1e47 SC |
193 | } |
194 | ||
195 | #define REGNO_REG_CLASS(REGNO) \ | |
196 | ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS) | |
197 | ||
198 | #define BASE_REG_CLASS (GR_REGS) | |
199 | ||
200 | #define INDEX_REG_CLASS NO_REGS | |
201 | ||
6b3d1e47 SC |
202 | #define REGNO_OK_FOR_INDEX_P(regno) 0 |
203 | ||
b5144086 SC |
204 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
205 | ((CLASS) != ALL_REGS \ | |
206 | ? (CLASS) \ | |
207 | : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ | |
208 | || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ | |
209 | ? (GR_REGS) \ | |
210 | : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ | |
211 | || GET_MODE (X) == VOIDmode) \ | |
212 | ? (GR_REGS) \ | |
6b3d1e47 SC |
213 | : (CLASS)))) |
214 | ||
6b3d1e47 SC |
215 | \f |
216 | /* Basic Stack Layout. */ | |
217 | ||
62f9f30b | 218 | #define STACK_GROWS_DOWNWARD 1 |
6b3d1e47 | 219 | |
f62c8a5c | 220 | #define FRAME_GROWS_DOWNWARD 0 |
6b3d1e47 SC |
221 | |
222 | #define STARTING_FRAME_OFFSET \ | |
38173d38 | 223 | (crtl->outgoing_args_size) |
6b3d1e47 SC |
224 | |
225 | /* Use the default value zero. */ | |
226 | /* #define STACK_POINTER_OFFSET 0 */ | |
227 | ||
228 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
229 | ||
230 | /* The return address for the current frame is in r31 if this is a leaf | |
231 | function. Otherwise, it is on the stack. It is at a variable offset | |
232 | from sp/fp/ap, so we define a fake hard register rap which is a | |
233 | pointer to the return address on the stack. This always gets eliminated | |
234 | during reload to be either the frame pointer or the stack pointer plus | |
235 | an offset. */ | |
236 | ||
237 | #define RETURN_ADDR_RTX(count, frame) \ | |
238 | (((count) == 0) \ | |
239 | ? (leaf_function_p () \ | |
240 | ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \ | |
241 | : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \ | |
242 | RETURN_ADDRESS_POINTER_REGNUM))) \ | |
243 | : (rtx) 0) | |
244 | ||
245 | /* Before the prologue, RA lives in r31. */ | |
240930c4 | 246 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 31) |
6b3d1e47 SC |
247 | |
248 | \f | |
249 | /* Register That Address the Stack Frame. */ | |
250 | ||
b5144086 SC |
251 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) |
252 | #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1) | |
253 | #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 27) | |
254 | #define ARG_POINTER_REGNUM GP_REG_FIRST | |
255 | #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM | |
256 | #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2) | |
6b3d1e47 SC |
257 | |
258 | \f | |
259 | /* Eliminating the Frame Pointer and the Arg Pointer. */ | |
260 | ||
6b3d1e47 SC |
261 | #define ELIMINABLE_REGS \ |
262 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
263 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
264 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
265 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
266 | { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \ | |
267 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
268 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
269 | ||
6b3d1e47 SC |
270 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
271 | (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO)) | |
272 | \f | |
273 | /* Passing Function Arguments on the Stack. */ | |
274 | ||
6b3d1e47 SC |
275 | /* #define PUSH_ROUNDING(BYTES) 0 */ |
276 | ||
277 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
278 | ||
279 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
280 | ||
81464b2c | 281 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
6b3d1e47 | 282 | |
6b3d1e47 SC |
283 | \f |
284 | /* Function Arguments in Registers. */ | |
285 | ||
6b3d1e47 SC |
286 | #define MAX_ARGS_IN_REGISTERS 8 |
287 | ||
b5144086 SC |
288 | typedef struct iq2000_args |
289 | { | |
290 | int gp_reg_found; /* Whether a gp register was found yet. */ | |
291 | unsigned int arg_number; /* Argument number. */ | |
292 | unsigned int arg_words; /* # total words the arguments take. */ | |
293 | unsigned int fp_arg_words; /* # words for FP args (IQ2000_EABI only). */ | |
294 | int last_arg_fp; /* Nonzero if last arg was FP (EABI only). */ | |
295 | int fp_code; /* Mode of FP arguments. */ | |
296 | unsigned int num_adjusts; /* Number of adjustments made. */ | |
6b3d1e47 | 297 | /* Adjustments made to args pass in regs. */ |
984514ac | 298 | rtx adjust[MAX_ARGS_IN_REGISTERS * 2]; |
6b3d1e47 SC |
299 | } CUMULATIVE_ARGS; |
300 | ||
301 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
302 | for a call to a function whose data type is FNTYPE. | |
303 | For a library call, FNTYPE is 0. */ | |
0f6937fe | 304 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
b5144086 | 305 | init_cumulative_args (& CUM, FNTYPE, LIBNAME) \ |
6b3d1e47 | 306 | |
6b3d1e47 SC |
307 | #define FUNCTION_ARG_REGNO_P(N) \ |
308 | (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) | |
309 | ||
310 | \f | |
6b3d1e47 SC |
311 | /* On the IQ2000, R2 and R3 are the only register thus used. */ |
312 | ||
7ae62237 | 313 | #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N) |
6b3d1e47 SC |
314 | |
315 | \f | |
316 | /* How Large Values are Returned. */ | |
317 | ||
6b3d1e47 | 318 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
6b3d1e47 SC |
319 | \f |
320 | /* Function Entry and Exit. */ | |
321 | ||
322 | #define EXIT_IGNORE_STACK 1 | |
323 | ||
324 | \f | |
325 | /* Generating Code for Profiling. */ | |
326 | ||
327 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
328 | { \ | |
329 | fprintf (FILE, "\t.set\tnoreorder\n"); \ | |
330 | fprintf (FILE, "\t.set\tnoat\n"); \ | |
331 | fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \ | |
332 | reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \ | |
333 | fprintf (FILE, "\tjal\t_mcount\n"); \ | |
334 | fprintf (FILE, \ | |
335 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \ | |
336 | "subu", \ | |
337 | reg_names[STACK_POINTER_REGNUM], \ | |
338 | reg_names[STACK_POINTER_REGNUM], \ | |
339 | Pmode == DImode ? 16 : 8); \ | |
340 | fprintf (FILE, "\t.set\treorder\n"); \ | |
341 | fprintf (FILE, "\t.set\tat\n"); \ | |
342 | } | |
343 | ||
6b3d1e47 SC |
344 | \f |
345 | /* Trampolines for Nested Functions. */ | |
346 | ||
f4a33d37 RH |
347 | #define TRAMPOLINE_CODE_SIZE (8*4) |
348 | #define TRAMPOLINE_SIZE (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode)) | |
349 | #define TRAMPOLINE_ALIGNMENT GET_MODE_ALIGNMENT (Pmode) | |
6b3d1e47 | 350 | |
6b3d1e47 SC |
351 | \f |
352 | /* Addressing Modes. */ | |
353 | ||
354 | #define CONSTANT_ADDRESS_P(X) \ | |
b5144086 | 355 | ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ |
6b3d1e47 SC |
356 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ |
357 | || (GET_CODE (X) == CONST))) | |
358 | ||
359 | #define MAX_REGS_PER_ADDRESS 1 | |
360 | ||
6b3d1e47 SC |
361 | #define REG_OK_FOR_INDEX_P(X) 0 |
362 | ||
6b3d1e47 SC |
363 | \f |
364 | /* Describing Relative Costs of Operations. */ | |
365 | ||
6b3d1e47 SC |
366 | #define REGISTER_MOVE_COST(MODE, FROM, TO) 2 |
367 | ||
368 | #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ | |
369 | (TO_P ? 2 : 16) | |
370 | ||
3a4fd356 | 371 | #define BRANCH_COST(speed_p, predictable_p) 2 |
6b3d1e47 SC |
372 | |
373 | #define SLOW_BYTE_ACCESS 1 | |
374 | ||
375 | #define NO_FUNCTION_CSE 1 | |
376 | ||
6b3d1e47 SC |
377 | #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ |
378 | if (REG_NOTE_KIND (LINK) != 0) \ | |
379 | (COST) = 0; /* Anti or output dependence. */ | |
380 | ||
381 | \f | |
382 | /* Dividing the output into sections. */ | |
383 | ||
b5144086 | 384 | #define TEXT_SECTION_ASM_OP "\t.text" /* Instructions. */ |
6b3d1e47 | 385 | |
b5144086 | 386 | #define DATA_SECTION_ASM_OP "\t.data" /* Large data. */ |
6b3d1e47 SC |
387 | |
388 | \f | |
389 | /* The Overall Framework of an Assembler File. */ | |
390 | ||
391 | #define ASM_COMMENT_START " #" | |
392 | ||
393 | #define ASM_APP_ON "#APP\n" | |
394 | ||
395 | #define ASM_APP_OFF "#NO_APP\n" | |
396 | ||
397 | \f | |
398 | /* Output and Generation of Labels. */ | |
399 | ||
6b3d1e47 SC |
400 | #undef ASM_GENERATE_INTERNAL_LABEL |
401 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
b5144086 | 402 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM)) |
6b3d1e47 SC |
403 | |
404 | #define GLOBAL_ASM_OP "\t.globl\t" | |
405 | ||
406 | \f | |
407 | /* Output of Assembler Instructions. */ | |
408 | ||
409 | #define REGISTER_NAMES \ | |
410 | { \ | |
411 | "%0", "%1", "%2", "%3", "%4", "%5", "%6", "%7", \ | |
412 | "%8", "%9", "%10", "%11", "%12", "%13", "%14", "%15", \ | |
413 | "%16", "%17", "%18", "%19", "%20", "%21", "%22", "%23", \ | |
414 | "%24", "%25", "%26", "%27", "%28", "%29", "%30", "%31", "%rap" \ | |
954c7446 | 415 | } |
6b3d1e47 SC |
416 | |
417 | #define ADDITIONAL_REGISTER_NAMES \ | |
418 | { \ | |
419 | { "%0", 0 + GP_REG_FIRST }, \ | |
420 | { "%1", 1 + GP_REG_FIRST }, \ | |
421 | { "%2", 2 + GP_REG_FIRST }, \ | |
422 | { "%3", 3 + GP_REG_FIRST }, \ | |
423 | { "%4", 4 + GP_REG_FIRST }, \ | |
424 | { "%5", 5 + GP_REG_FIRST }, \ | |
425 | { "%6", 6 + GP_REG_FIRST }, \ | |
426 | { "%7", 7 + GP_REG_FIRST }, \ | |
427 | { "%8", 8 + GP_REG_FIRST }, \ | |
428 | { "%9", 9 + GP_REG_FIRST }, \ | |
429 | { "%10", 10 + GP_REG_FIRST }, \ | |
430 | { "%11", 11 + GP_REG_FIRST }, \ | |
431 | { "%12", 12 + GP_REG_FIRST }, \ | |
432 | { "%13", 13 + GP_REG_FIRST }, \ | |
433 | { "%14", 14 + GP_REG_FIRST }, \ | |
434 | { "%15", 15 + GP_REG_FIRST }, \ | |
435 | { "%16", 16 + GP_REG_FIRST }, \ | |
436 | { "%17", 17 + GP_REG_FIRST }, \ | |
437 | { "%18", 18 + GP_REG_FIRST }, \ | |
438 | { "%19", 19 + GP_REG_FIRST }, \ | |
439 | { "%20", 20 + GP_REG_FIRST }, \ | |
440 | { "%21", 21 + GP_REG_FIRST }, \ | |
441 | { "%22", 22 + GP_REG_FIRST }, \ | |
442 | { "%23", 23 + GP_REG_FIRST }, \ | |
443 | { "%24", 24 + GP_REG_FIRST }, \ | |
444 | { "%25", 25 + GP_REG_FIRST }, \ | |
445 | { "%26", 26 + GP_REG_FIRST }, \ | |
446 | { "%27", 27 + GP_REG_FIRST }, \ | |
447 | { "%28", 28 + GP_REG_FIRST }, \ | |
448 | { "%29", 29 + GP_REG_FIRST }, \ | |
449 | { "%30", 27 + GP_REG_FIRST }, \ | |
450 | { "%31", 31 + GP_REG_FIRST }, \ | |
451 | { "%rap", 32 + GP_REG_FIRST }, \ | |
452 | } | |
453 | ||
454 | /* Check if the current insn needs a nop in front of it | |
455 | because of load delays, and also update the delay slot statistics. */ | |
456 | ||
457 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
458 | final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
459 | ||
6b3d1e47 SC |
460 | #define DBR_OUTPUT_SEQEND(STREAM) \ |
461 | do \ | |
462 | { \ | |
6b3d1e47 SC |
463 | fputs ("\n", STREAM); \ |
464 | } \ | |
465 | while (0) | |
466 | ||
467 | #define LOCAL_LABEL_PREFIX "$" | |
468 | ||
469 | #define USER_LABEL_PREFIX "" | |
470 | ||
471 | \f | |
472 | /* Output of dispatch tables. */ | |
473 | ||
474 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
b5144086 SC |
475 | do \ |
476 | { \ | |
477 | fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
478 | Pmode == DImode ? ".dword" : ".word", \ | |
479 | LOCAL_LABEL_PREFIX, VALUE); \ | |
480 | } \ | |
481 | while (0) | |
6b3d1e47 SC |
482 | |
483 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
484 | fprintf (STREAM, "\t%s\t%sL%d\n", \ | |
485 | Pmode == DImode ? ".dword" : ".word", \ | |
486 | LOCAL_LABEL_PREFIX, \ | |
487 | VALUE) | |
488 | ||
489 | \f | |
490 | /* Assembler Commands for Alignment. */ | |
491 | ||
492 | #undef ASM_OUTPUT_SKIP | |
493 | #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ | |
586de218 KG |
494 | fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", \ |
495 | (unsigned HOST_WIDE_INT)(SIZE)) | |
6b3d1e47 SC |
496 | |
497 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
498 | if ((LOG) != 0) \ | |
499 | fprintf (STREAM, "\t.balign %d\n", 1<<(LOG)) | |
500 | ||
501 | \f | |
502 | /* Macros Affecting all Debug Formats. */ | |
503 | ||
504 | #define DEBUGGER_AUTO_OFFSET(X) \ | |
505 | iq2000_debugger_offset (X, (HOST_WIDE_INT) 0) | |
506 | ||
507 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ | |
508 | iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET) | |
509 | ||
510 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
511 | ||
512 | #define DWARF2_DEBUGGING_INFO 1 | |
513 | ||
514 | \f | |
515 | /* Miscellaneous Parameters. */ | |
516 | ||
6b3d1e47 SC |
517 | #define CASE_VECTOR_MODE SImode |
518 | ||
9e11bfef | 519 | #define WORD_REGISTER_OPERATIONS 1 |
6b3d1e47 SC |
520 | |
521 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
522 | ||
523 | #define MOVE_MAX 4 | |
524 | ||
525 | #define MAX_MOVE_MAX 8 | |
526 | ||
527 | #define SHIFT_COUNT_TRUNCATED 1 | |
528 | ||
6b3d1e47 SC |
529 | #define STORE_FLAG_VALUE 1 |
530 | ||
531 | #define Pmode SImode | |
532 | ||
533 | #define FUNCTION_MODE SImode | |
534 | ||
6b3d1e47 SC |
535 | /* IQ2000 external variables defined in iq2000.c. */ |
536 | ||
537 | /* Comparison type. */ | |
538 | enum cmp_type | |
539 | { | |
b5144086 SC |
540 | CMP_SI, /* Compare four byte integers. */ |
541 | CMP_DI, /* Compare eight byte integers. */ | |
542 | CMP_SF, /* Compare single precision floats. */ | |
543 | CMP_DF, /* Compare double precision floats. */ | |
544 | CMP_MAX /* Max comparison type. */ | |
6b3d1e47 SC |
545 | }; |
546 | ||
547 | /* Types of delay slot. */ | |
548 | enum delay_type | |
549 | { | |
b5144086 SC |
550 | DELAY_NONE, /* No delay slot. */ |
551 | DELAY_LOAD, /* Load from memory delay. */ | |
552 | DELAY_FCMP /* Delay after doing c.<xx>.{d,s}. */ | |
6b3d1e47 SC |
553 | }; |
554 | ||
6b3d1e47 | 555 | /* Recast the cpu class to be the cpu attribute. */ |
b5144086 | 556 | #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune) |
6b3d1e47 | 557 | |
b5144086 SC |
558 | #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16) /* 0xffff0000 */ |
559 | #define BITMASK_LOWER16 ((unsigned long) 0xffff) /* 0x0000ffff */ | |
6b3d1e47 SC |
560 | |
561 | \f | |
562 | #define GENERATE_BRANCHLIKELY (ISA_HAS_BRANCHLIKELY) | |
563 | ||
564 | /* Macros to decide whether certain features are available or not, | |
565 | depending on the instruction set architecture level. */ | |
566 | ||
567 | #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY | |
568 | ||
569 | /* ISA has branch likely instructions. */ | |
570 | #define ISA_HAS_BRANCHLIKELY (iq2000_isa == 1) | |
571 | ||
572 | \f | |
573 | #undef ASM_SPEC | |
6b3d1e47 SC |
574 | |
575 | \f | |
10e70392 SC |
576 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ |
577 | #define DWARF_FRAME_REGNUM(REG) (REG) | |
6b3d1e47 SC |
578 | |
579 | /* The DWARF 2 CFA column which tracks the return address. */ | |
10e70392 | 580 | #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31) |
6b3d1e47 SC |
581 | |
582 | /* Describe how we implement __builtin_eh_return. */ | |
583 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
584 | ||
585 | /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the | |
586 | location used to store the amount to adjust the stack. This is | |
587 | usually a register that is available from end of the function's body | |
588 | to the end of the epilogue. Thus, this cannot be a register used as a | |
589 | temporary by the epilogue. | |
590 | ||
591 | This must be an integer register. */ | |
592 | #define EH_RETURN_STACKADJ_REGNO 3 | |
593 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) | |
594 | ||
595 | /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the | |
596 | location used to store the address the processor should jump to | |
597 | catch exception. This is usually a registers that is available from | |
598 | end of the function's body to the end of the epilogue. Thus, this | |
599 | cannot be a register used as a temporary by the epilogue. | |
600 | ||
601 | This must be an address register. */ | |
602 | #define EH_RETURN_HANDLER_REGNO 26 | |
603 | #define EH_RETURN_HANDLER_RTX \ | |
604 | gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO) | |
605 | ||
606 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
607 | #define DWARF_CIE_DATA_ALIGNMENT 4 | |
608 | ||
609 | /* For IQ2000, width of a floating point register. */ | |
610 | #define UNITS_PER_FPREG 4 | |
611 | ||
612 | /* Force right-alignment for small varargs in 32 bit little_endian mode */ | |
613 | ||
614 | #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN | |
615 | ||
616 | /* Internal macros to classify a register number as to whether it's a | |
617 | general purpose register, a floating point register, a | |
618 | multiply/divide register, or a status register. */ | |
619 | ||
620 | #define GP_REG_FIRST 0 | |
621 | #define GP_REG_LAST 31 | |
622 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
623 | ||
624 | #define RAP_REG_NUM 32 | |
625 | #define AT_REGNUM (GP_REG_FIRST + 1) | |
626 | ||
627 | #define GP_REG_P(REGNO) \ | |
628 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
629 | ||
630 | /* IQ2000 registers used in prologue/epilogue code when the stack frame | |
631 | is larger than 32K bytes. These registers must come from the | |
632 | scratch register set, and not used for passing and returning | |
633 | arguments and any other information used in the calling sequence. */ | |
634 | ||
635 | #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12) | |
636 | #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13) | |
637 | ||
638 | /* This macro is used later on in the file. */ | |
639 | #define GR_REG_CLASS_P(CLASS) \ | |
640 | ((CLASS) == GR_REGS) | |
641 | ||
642 | #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
643 | #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000) | |
644 | ||
645 | /* Certain machines have the property that some registers cannot be | |
646 | copied to some other registers without using memory. Define this | |
4375e090 | 647 | macro on those machines to be a C expression that is nonzero if |
6b3d1e47 SC |
648 | objects of mode MODE in registers of CLASS1 can only be copied to |
649 | registers of class CLASS2 by storing a register of CLASS1 into | |
650 | memory and loading that memory location into a register of CLASS2. | |
651 | ||
652 | Do not define this macro if its value would always be zero. */ | |
653 | ||
654 | /* Return the maximum number of consecutive registers | |
655 | needed to represent mode MODE in a register of class CLASS. */ | |
656 | ||
657 | #define CLASS_UNITS(mode, size) \ | |
658 | ((GET_MODE_SIZE (mode) + (size) - 1) / (size)) | |
659 | ||
660 | /* If defined, gives a class of registers that cannot be used as the | |
661 | operand of a SUBREG that changes the mode of the object illegally. */ | |
662 | ||
663 | #define CLASS_CANNOT_CHANGE_MODE 0 | |
664 | ||
665 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
666 | ||
667 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
668 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
669 | ||
670 | /* Make sure 4 words are always allocated on the stack. */ | |
671 | ||
672 | #ifndef STACK_ARGS_ADJUST | |
673 | #define STACK_ARGS_ADJUST(SIZE) \ | |
b5144086 SC |
674 | { \ |
675 | if (SIZE.constant < 4 * UNITS_PER_WORD) \ | |
676 | SIZE.constant = 4 * UNITS_PER_WORD; \ | |
677 | } | |
6b3d1e47 SC |
678 | #endif |
679 | ||
680 | \f | |
681 | /* Symbolic macros for the registers used to return integer and floating | |
682 | point values. */ | |
683 | ||
684 | #define GP_RETURN (GP_REG_FIRST + 2) | |
685 | ||
686 | /* Symbolic macros for the first/last argument registers. */ | |
687 | ||
688 | #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
689 | #define GP_ARG_LAST (GP_REG_FIRST + 11) | |
690 | ||
691 | #define MAX_ARGS_IN_REGISTERS 8 | |
692 | ||
693 | \f | |
694 | /* Tell prologue and epilogue if register REGNO should be saved / restored. */ | |
695 | ||
696 | #define MUST_SAVE_REGISTER(regno) \ | |
6fb5fa3c | 697 | ((df_regs_ever_live_p (regno) && !call_used_regs[regno]) \ |
6b3d1e47 | 698 | || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \ |
6fb5fa3c | 699 | || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31))) |
6b3d1e47 SC |
700 | |
701 | /* ALIGN FRAMES on double word boundaries */ | |
702 | #ifndef IQ2000_STACK_ALIGN | |
703 | #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7) | |
704 | #endif | |
705 | ||
706 | \f | |
707 | /* These assume that REGNO is a hard or pseudo reg number. | |
708 | They give nonzero only if REGNO is a hard reg of the suitable class | |
709 | or a pseudo reg currently allocated to a suitable hard reg. | |
710 | These definitions are NOT overridden anywhere. */ | |
711 | ||
712 | #define BASE_REG_P(regno, mode) \ | |
713 | (GP_REG_P (regno)) | |
714 | ||
715 | #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \ | |
716 | BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \ | |
717 | (mode)) | |
718 | ||
719 | #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \ | |
720 | (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode)))) | |
721 | ||
722 | #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \ | |
954c7446 | 723 | GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode)) |
6b3d1e47 SC |
724 | |
725 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
726 | and check its validity for a certain class. | |
727 | We have two alternate definitions for each of them. | |
728 | The usual definition accepts all pseudo regs; the other rejects them all. | |
729 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
730 | ||
731 | Most source files want to accept pseudo regs in the hope that | |
732 | they will get allocated to the class that the insn wants them to be in. | |
733 | Some source files that are used after register allocation | |
734 | need to be strict. */ | |
735 | ||
736 | #ifndef REG_OK_STRICT | |
737 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
738 | iq2000_reg_mode_ok_for_base_p (X, MODE, 0) | |
739 | #else | |
740 | #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ | |
741 | iq2000_reg_mode_ok_for_base_p (X, MODE, 1) | |
742 | #endif | |
743 | ||
744 | #if 1 | |
b5144086 SC |
745 | #define GO_PRINTF(x) fprintf (stderr, (x)) |
746 | #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y)) | |
747 | #define GO_DEBUG_RTX(x) debug_rtx (x) | |
6b3d1e47 SC |
748 | |
749 | #else | |
750 | #define GO_PRINTF(x) | |
751 | #define GO_PRINTF2(x,y) | |
752 | #define GO_DEBUG_RTX(x) | |
753 | #endif | |
754 | ||
6b3d1e47 SC |
755 | /* If defined, modifies the length assigned to instruction INSN as a |
756 | function of the context in which it is used. LENGTH is an lvalue | |
757 | that contains the initially computed length of the insn and should | |
758 | be updated with the correct length of the insn. */ | |
759 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
760 | ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH))) | |
761 | ||
762 | \f | |
6b3d1e47 SC |
763 | |
764 | ||
765 | /* How to tell the debugger about changes of source files. */ | |
766 | ||
767 | #ifndef SET_FILE_NUMBER | |
b5144086 | 768 | #define SET_FILE_NUMBER() ++ num_source_filenames |
6b3d1e47 SC |
769 | #endif |
770 | ||
771 | /* This is how to output a note the debugger telling it the line number | |
772 | to which the following sequence of instructions corresponds. */ | |
773 | ||
774 | #ifndef LABEL_AFTER_LOC | |
775 | #define LABEL_AFTER_LOC(STREAM) | |
776 | #endif | |
777 | ||
6b3d1e47 SC |
778 | \f |
779 | /* Default to -G 8 */ | |
780 | #ifndef IQ2000_DEFAULT_GVALUE | |
781 | #define IQ2000_DEFAULT_GVALUE 8 | |
782 | #endif | |
783 | ||
b5144086 | 784 | #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small data. */ |
6b3d1e47 | 785 | |
6b3d1e47 | 786 | \f |
b5144086 SC |
787 | /* Which instruction set architecture to use. */ |
788 | extern int iq2000_isa; | |
789 | ||
6b3d1e47 SC |
790 | enum iq2000_builtins |
791 | { | |
792 | IQ2000_BUILTIN_ADO16, | |
793 | IQ2000_BUILTIN_CFC0, | |
794 | IQ2000_BUILTIN_CFC1, | |
795 | IQ2000_BUILTIN_CFC2, | |
796 | IQ2000_BUILTIN_CFC3, | |
797 | IQ2000_BUILTIN_CHKHDR, | |
798 | IQ2000_BUILTIN_CTC0, | |
799 | IQ2000_BUILTIN_CTC1, | |
800 | IQ2000_BUILTIN_CTC2, | |
801 | IQ2000_BUILTIN_CTC3, | |
802 | IQ2000_BUILTIN_LU, | |
803 | IQ2000_BUILTIN_LUC32L, | |
804 | IQ2000_BUILTIN_LUC64, | |
805 | IQ2000_BUILTIN_LUC64L, | |
806 | IQ2000_BUILTIN_LUK, | |
807 | IQ2000_BUILTIN_LULCK, | |
808 | IQ2000_BUILTIN_LUM32, | |
809 | IQ2000_BUILTIN_LUM32L, | |
810 | IQ2000_BUILTIN_LUM64, | |
811 | IQ2000_BUILTIN_LUM64L, | |
812 | IQ2000_BUILTIN_LUR, | |
813 | IQ2000_BUILTIN_LURL, | |
814 | IQ2000_BUILTIN_MFC0, | |
815 | IQ2000_BUILTIN_MFC1, | |
816 | IQ2000_BUILTIN_MFC2, | |
817 | IQ2000_BUILTIN_MFC3, | |
818 | IQ2000_BUILTIN_MRGB, | |
819 | IQ2000_BUILTIN_MTC0, | |
820 | IQ2000_BUILTIN_MTC1, | |
821 | IQ2000_BUILTIN_MTC2, | |
822 | IQ2000_BUILTIN_MTC3, | |
823 | IQ2000_BUILTIN_PKRL, | |
824 | IQ2000_BUILTIN_RAM, | |
825 | IQ2000_BUILTIN_RB, | |
826 | IQ2000_BUILTIN_RX, | |
827 | IQ2000_BUILTIN_SRRD, | |
828 | IQ2000_BUILTIN_SRRDL, | |
829 | IQ2000_BUILTIN_SRULC, | |
830 | IQ2000_BUILTIN_SRULCK, | |
831 | IQ2000_BUILTIN_SRWR, | |
832 | IQ2000_BUILTIN_SRWRU, | |
833 | IQ2000_BUILTIN_TRAPQF, | |
834 | IQ2000_BUILTIN_TRAPQFL, | |
835 | IQ2000_BUILTIN_TRAPQN, | |
836 | IQ2000_BUILTIN_TRAPQNE, | |
837 | IQ2000_BUILTIN_TRAPRE, | |
838 | IQ2000_BUILTIN_TRAPREL, | |
839 | IQ2000_BUILTIN_WB, | |
840 | IQ2000_BUILTIN_WBR, | |
841 | IQ2000_BUILTIN_WBU, | |
842 | IQ2000_BUILTIN_WX, | |
843 | IQ2000_BUILTIN_SYSCALL | |
844 | }; |