projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 6b3d1e47 | 1 | ;; iq2000.md Machine Description for Vitesse IQ2000 processors |
| 83ffe9cd | 2 | ;; Copyright (C) 2003-2023 Free Software Foundation, Inc. |
| 6b3d1e47 | 3 | |
| b7849684 | 4 | ;; This file is part of GCC. |
| 6b3d1e47 | 5 | |
| b7849684 | 6 | ;; GCC is free software; you can redistribute it and/or modify |
| 6b3d1e47 | 7 | ;; it under the terms of the GNU General Public License as published by |
| 2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
| 6b3d1e47 SC |
9 | ;; any later version. |
| 10 | ||
| b7849684 | 11 | ;; GCC is distributed in the hope that it will be useful, |
| 6b3d1e47 SC |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 | ;; GNU General Public License for more details. | |
| 15 | ||
| 16 | ;; You should have received a copy of the GNU General Public License | |
| 2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
| 18 | ;; <http://www.gnu.org/licenses/>. | |
| 6b3d1e47 | 19 | |
| 6b3d1e47 SC |
20 | (define_constants |
| 21 | [(UNSPEC_ADO16 0) | |
| 22 | (UNSPEC_RAM 1) | |
| 23 | (UNSPEC_CHKHDR 2) | |
| 24 | (UNSPEC_PKRL 3) | |
| 25 | (UNSPEC_CFC0 4) | |
| 26 | (UNSPEC_CFC1 5) | |
| 27 | (UNSPEC_CFC2 6) | |
| 28 | (UNSPEC_CFC3 7) | |
| 29 | (UNSPEC_CTC0 8) | |
| 30 | (UNSPEC_CTC1 9) | |
| 31 | (UNSPEC_CTC2 10) | |
| 32 | (UNSPEC_CTC3 11) | |
| 33 | (UNSPEC_MFC0 12) | |
| 34 | (UNSPEC_MFC1 13) | |
| 35 | (UNSPEC_MFC2 14) | |
| 36 | (UNSPEC_MFC3 15) | |
| 37 | (UNSPEC_MTC0 16) | |
| 38 | (UNSPEC_MTC1 17) | |
| 39 | (UNSPEC_MTC2 18) | |
| 40 | (UNSPEC_MTC3 19) | |
| 41 | (UNSPEC_LUR 20) | |
| 42 | (UNSPEC_RB 21) | |
| 43 | (UNSPEC_RX 22) | |
| 44 | (UNSPEC_SRRD 23) | |
| 45 | (UNSPEC_SRWR 24) | |
| 46 | (UNSPEC_WB 25) | |
| 47 | (UNSPEC_WX 26) | |
| 48 | (UNSPEC_LUC32 49) | |
| 49 | (UNSPEC_LUC32L 27) | |
| 50 | (UNSPEC_LUC64 28) | |
| 51 | (UNSPEC_LUC64L 29) | |
| 52 | (UNSPEC_LUK 30) | |
| 53 | (UNSPEC_LULCK 31) | |
| 54 | (UNSPEC_LUM32 32) | |
| 55 | (UNSPEC_LUM32L 33) | |
| 56 | (UNSPEC_LUM64 34) | |
| 57 | (UNSPEC_LUM64L 35) | |
| 58 | (UNSPEC_LURL 36) | |
| 59 | (UNSPEC_MRGB 37) | |
| 60 | (UNSPEC_SRRDL 38) | |
| 61 | (UNSPEC_SRULCK 39) | |
| 62 | (UNSPEC_SRWRU 40) | |
| 63 | (UNSPEC_TRAPQFL 41) | |
| 64 | (UNSPEC_TRAPQNE 42) | |
| 65 | (UNSPEC_TRAPREL 43) | |
| 66 | (UNSPEC_WBU 44) | |
| 67 | (UNSPEC_SYSCALL 45)] | |
| 68 | ) | |
| 69 | ;; UNSPEC values used in iq2000.md | |
| 70 | ;; Number USE | |
| 71 | ;; 0 movsi_ul | |
| 72 | ;; 1 movsi_us, get_fnaddr | |
| 73 | ;; 3 eh_set_return | |
| 74 | ;; 20 builtin_setjmp_setup | |
| 75 | ;; | |
| 76 | ;; UNSPEC_VOLATILE values | |
| 77 | ;; 0 blockage | |
| 78 | ;; 2 loadgp | |
| 79 | ;; 3 builtin_longjmp | |
| 80 | ;; 4 exception_receiver | |
| 81 | ;; 10 consttable_qi | |
| 82 | ;; 11 consttable_hi | |
| 83 | ;; 12 consttable_si | |
| 84 | ;; 13 consttable_di | |
| 85 | ;; 14 consttable_sf | |
| 86 | ;; 15 consttable_df | |
| 87 | ;; 16 align_2 | |
| 88 | ;; 17 align_4 | |
| 89 | ;; 18 align_8 | |
| 90 | \f | |
| 91 | ||
| 92 | ;; .................... | |
| 93 | ;; | |
| 94 | ;; Attributes | |
| 95 | ;; | |
| 96 | ;; .................... | |
| 97 | ||
| 98 | ;; Classification of each insn. | |
| 99 | ;; branch conditional branch | |
| 100 | ;; jump unconditional jump | |
| 101 | ;; call unconditional call | |
| 102 | ;; load load instruction(s) | |
| 103 | ;; store store instruction(s) | |
| 104 | ;; move data movement within same register set | |
| 105 | ;; xfer transfer to/from coprocessor | |
| 106 | ;; arith integer arithmetic instruction | |
| 107 | ;; darith double precision integer arithmetic instructions | |
| 108 | ;; imul integer multiply | |
| 109 | ;; idiv integer divide | |
| 110 | ;; icmp integer compare | |
| 111 | ;; fadd floating point add/subtract | |
| 112 | ;; fmul floating point multiply | |
| 113 | ;; fmadd floating point multiply-add | |
| 114 | ;; fdiv floating point divide | |
| 115 | ;; fabs floating point absolute value | |
| 116 | ;; fneg floating point negation | |
| 117 | ;; fcmp floating point compare | |
| 118 | ;; fcvt floating point convert | |
| 119 | ;; fsqrt floating point square root | |
| 120 | ;; multi multiword sequence (or user asm statements) | |
| 121 | ;; nop no operation | |
| 122 | ||
| 123 | (define_attr "type" | |
| 124 | "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop" | |
| 125 | (const_string "unknown")) | |
| 126 | ||
| 127 | ;; Main data type used by the insn | |
| 128 | (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown")) | |
| 129 | ||
| 130 | ;; Length (in # of bytes). A conditional branch is allowed only to a | |
| 131 | ;; location within a signed 18-bit offset of the delay slot. If that | |
| 132 | ;; provides too small a range, we use the `j' instruction. This | |
| 133 | ;; instruction takes a 28-bit value, but that value is not an offset. | |
| 134 | ;; Instead, it's bitwise-ored with the high-order four bits of the | |
| 135 | ;; instruction in the delay slot, which means it cannot be used to | |
| 026c3cfd | 136 | ;; cross a 256MB boundary. We could fall back on the jr |
| 6b3d1e47 SC |
137 | ;; instruction which allows full access to the entire address space, |
| 138 | ;; but we do not do so at present. | |
| 139 | ||
| 140 | (define_attr "length" "" | |
| 141 | (cond [(eq_attr "type" "branch") | |
| 142 | (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4)))) | |
| 143 | (const_int 131072)) | |
| 144 | (const_int 4)] | |
| 145 | (const_int 12))] | |
| 146 | (const_int 4))) | |
| 147 | ||
| 148 | (define_attr "cpu" | |
| 149 | "default,iq2000" | |
| 150 | (const (symbol_ref "iq2000_cpu_attr"))) | |
| 151 | ||
| 152 | ;; Does the instruction have a mandatory delay slot? has_dslot | |
| 153 | ;; Can the instruction be in a delay slot? ok_in_dslot | |
| 154 | ;; Can the instruction not be in a delay slot? not_in_dslot | |
| 155 | (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot" | |
| 156 | (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp") | |
| 157 | (const_string "has_dslot") | |
| 158 | (const_string "ok_in_dslot"))) | |
| 159 | ||
| 160 | ;; Attribute defining whether or not we can use the branch-likely instructions | |
| 161 | ||
| 162 | (define_attr "branch_likely" "no,yes" | |
| 163 | (const | |
| b4d58803 | 164 | (if_then_else (match_test "GENERATE_BRANCHLIKELY") |
| 6b3d1e47 SC |
165 | (const_string "yes") |
| 166 | (const_string "no")))) | |
| 167 | ||
| 0364465e JL |
168 | ;; Is this a bbi instruction or not |
| 169 | (define_attr "bbi" "no,yes" (const_string "no")) | |
| 6b3d1e47 SC |
170 | |
| 171 | ;; Describe a user's asm statement. | |
| 172 | (define_asm_attributes | |
| 173 | [(set_attr "type" "multi")]) | |
| 174 | ||
| 175 | \f | |
| 176 | ||
| 177 | ;; ......................... | |
| 178 | ;; | |
| 179 | ;; Delay slots, can't describe load/fcmp/xfer delay slots here | |
| 180 | ;; | |
| 181 | ;; ......................... | |
| 182 | ||
| 183 | (define_delay (eq_attr "type" "jump") | |
| 184 | [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 185 | (nil) | |
| 186 | (nil)]) | |
| 187 | ||
| 0364465e JL |
188 | ;; GAS refuses to assemble bbi[n]l. So for bbi instructions, do not |
| 189 | ;; allow them to annul-false. | |
| 190 | (define_delay (and (eq_attr "type" "branch") (eq_attr "bbi" "no")) | |
| 6b3d1e47 SC |
191 | [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) |
| 192 | (nil) | |
| 193 | (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))]) | |
| 194 | ||
| 0364465e JL |
195 | (define_delay (and (eq_attr "type" "branch") (eq_attr "bbi" "yes")) |
| 196 | [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 197 | (nil) | |
| 198 | (nil)]) | |
| 199 | ||
| 6b3d1e47 SC |
200 | (define_delay (eq_attr "type" "call") |
| 201 | [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 202 | (nil) | |
| 203 | (nil)]) | |
| 204 | ||
| 80ad92e9 | 205 | (include "predicates.md") |
| 679e8183 | 206 | (include "constraints.md") |
| 6b3d1e47 SC |
207 | \f |
| 208 | ||
| 209 | ;; ......................... | |
| 210 | ;; | |
| 78c21202 | 211 | ;; Pipeline model |
| 6b3d1e47 SC |
212 | ;; |
| 213 | ;; ......................... | |
| 214 | ||
| 78c21202 SB |
215 | (define_automaton "iq2000") |
| 216 | (define_cpu_unit "core,memory" "iq2000") | |
| 6b3d1e47 | 217 | |
| 78c21202 SB |
218 | (define_insn_reservation "nonmemory" 1 |
| 219 | (eq_attr "type" "!load,move,store,xfer") | |
| 220 | "core") | |
| 6b3d1e47 | 221 | |
| 78c21202 SB |
222 | (define_insn_reservation "iq2000_load_move" 3 |
| 223 | (and (eq_attr "type" "load,move") | |
| 6b3d1e47 | 224 | (eq_attr "cpu" "iq2000")) |
| 78c21202 | 225 | "memory") |
| 6b3d1e47 | 226 | |
| 78c21202 SB |
227 | (define_insn_reservation "other_load_move" 1 |
| 228 | (and (eq_attr "type" "load,move") | |
| 229 | (eq_attr "cpu" "!iq2000")) | |
| 230 | "memory") | |
| 6b3d1e47 | 231 | |
| 78c21202 SB |
232 | (define_insn_reservation "store" 1 |
| 233 | (eq_attr "type" "store") | |
| 234 | "memory") | |
| 6b3d1e47 | 235 | |
| 78c21202 SB |
236 | (define_insn_reservation "xfer" 2 |
| 237 | (eq_attr "type" "xfer") | |
| 238 | "memory") | |
| 6b3d1e47 SC |
239 | \f |
| 240 | ;; | |
| 241 | ;; .................... | |
| 242 | ;; | |
| 243 | ;; CONDITIONAL TRAPS | |
| 244 | ;; | |
| 245 | ;; .................... | |
| 246 | ;; | |
| 247 | ||
| 248 | (define_insn "trap" | |
| 249 | [(trap_if (const_int 1) (const_int 0))] | |
| 250 | "" | |
| 251 | "* | |
| 252 | { | |
| 253 | return \"break\"; | |
| 254 | }") | |
| 255 | \f | |
| 256 | ;; | |
| 257 | ;; .................... | |
| 258 | ;; | |
| 259 | ;; ADDITION | |
| 260 | ;; | |
| 261 | ;; .................... | |
| 262 | ;; | |
| 263 | ||
| 264 | (define_expand "addsi3" | |
| 265 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 266 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 267 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 268 | "" | |
| 269 | "") | |
| 270 | ||
| 271 | (define_insn "addsi3_internal" | |
| 73f793e3 | 272 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 6b3d1e47 SC |
273 | (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") |
| 274 | (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 275 | "" | |
| 276 | "@ | |
| 277 | addu\\t%0,%z1,%2 | |
| 278 | addiu\\t%0,%z1,%2" | |
| 279 | [(set_attr "type" "arith") | |
| 280 | (set_attr "mode" "SI")]) | |
| 281 | \f | |
| 282 | ;; | |
| 283 | ;; .................... | |
| 284 | ;; | |
| 285 | ;; SUBTRACTION | |
| 286 | ;; | |
| 287 | ;; .................... | |
| 288 | ;; | |
| 289 | ||
| 290 | (define_expand "subsi3" | |
| 291 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 292 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 293 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 294 | "" | |
| 295 | "") | |
| 296 | ||
| 297 | (define_insn "subsi3_internal" | |
| 73f793e3 | 298 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 6b3d1e47 SC |
299 | (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") |
| 300 | (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 301 | "" | |
| 302 | "@ | |
| 303 | subu\\t%0,%z1,%2 | |
| 304 | addiu\\t%0,%z1,%n2" | |
| 305 | [(set_attr "type" "arith") | |
| 306 | (set_attr "mode" "SI")]) | |
| 307 | \f | |
| 308 | ;; | |
| 309 | ;; .................... | |
| 310 | ;; | |
| 311 | ;; NEGATION and ONE'S COMPLEMENT | |
| 312 | ;; | |
| 313 | ;; .................... | |
| 314 | ||
| 315 | (define_insn "negsi2" | |
| 316 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 317 | (neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 318 | "" | |
| 319 | "* | |
| 320 | { | |
| 321 | operands[2] = const0_rtx; | |
| 322 | return \"subu\\t%0,%z2,%1\"; | |
| 323 | }" | |
| 324 | [(set_attr "type" "arith") | |
| 325 | (set_attr "mode" "SI")]) | |
| 326 | ||
| 327 | (define_insn "one_cmplsi2" | |
| 328 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 329 | (not:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 330 | "" | |
| 331 | "* | |
| 332 | { | |
| 333 | operands[2] = const0_rtx; | |
| 334 | return \"nor\\t%0,%z2,%1\"; | |
| 335 | }" | |
| 336 | [(set_attr "type" "arith") | |
| 337 | (set_attr "mode" "SI")]) | |
| 338 | \f | |
| 339 | ;; | |
| 340 | ;; .................... | |
| 341 | ;; | |
| 342 | ;; LOGICAL | |
| 343 | ;; | |
| 344 | ;; .................... | |
| 345 | ;; | |
| 346 | ||
| 347 | (define_expand "andsi3" | |
| 348 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 349 | (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 350 | (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 351 | "" | |
| 352 | "") | |
| 353 | ||
| 354 | (define_insn "" | |
| 355 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 356 | (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 357 | (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 358 | "" | |
| 359 | "* | |
| 360 | { | |
| 361 | if (which_alternative == 0) | |
| 362 | return \"and\\t%0,%1,%2\"; | |
| 363 | else if (which_alternative == 1) | |
| 364 | return \"andi\\t%0,%1,%x2\"; | |
| 365 | else if (which_alternative == 2) | |
| 366 | { | |
| 367 | if ((INTVAL (operands[2]) & 0xffff) == 0xffff) | |
| 368 | { | |
| 369 | operands[2] = GEN_INT (INTVAL (operands[2]) >> 16); | |
| 370 | return \"andoui\\t%0,%1,%x2\"; | |
| 371 | } | |
| 372 | else | |
| 373 | { | |
| 374 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
| 375 | return \"andoi\\t%0,%1,%x2\"; | |
| 376 | } | |
| 377 | } | |
| 954c7446 JR |
378 | else |
| 379 | gcc_unreachable (); | |
| 6b3d1e47 SC |
380 | }" |
| 381 | [(set_attr "type" "arith") | |
| 382 | (set_attr "mode" "SI")]) | |
| 383 | ||
| 384 | (define_expand "iorsi3" | |
| 385 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 386 | (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 387 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 388 | "" | |
| 389 | "") | |
| 390 | ||
| 391 | (define_insn "" | |
| 392 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 393 | (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 394 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 395 | "" | |
| 396 | "@ | |
| 397 | or\\t%0,%1,%2 | |
| 398 | ori\\t%0,%1,%x2" | |
| 399 | [(set_attr "type" "arith") | |
| 400 | (set_attr "mode" "SI")]) | |
| 401 | ||
| 402 | (define_expand "xorsi3" | |
| 403 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 404 | (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 405 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 406 | "" | |
| 407 | "") | |
| 408 | ||
| 409 | (define_insn "" | |
| 410 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 411 | (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 412 | (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 413 | "" | |
| 414 | "@ | |
| 415 | xor\\t%0,%1,%2 | |
| 416 | xori\\t%0,%1,%x2" | |
| 417 | [(set_attr "type" "arith") | |
| 418 | (set_attr "mode" "SI")]) | |
| 419 | ||
| 420 | (define_insn "*norsi3" | |
| 421 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 422 | (and:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
| 423 | (not:SI (match_operand:SI 2 "register_operand" "d"))))] | |
| 424 | "" | |
| 425 | "nor\\t%0,%z1,%z2" | |
| 426 | [(set_attr "type" "arith") | |
| 427 | (set_attr "mode" "SI")]) | |
| 428 | \f | |
| 429 | ;; | |
| 430 | ;; .................... | |
| 431 | ;; | |
| 432 | ;; ZERO EXTENSION | |
| 433 | ;; | |
| 434 | ;; .................... | |
| 435 | ||
| 436 | ;; Extension insns. | |
| 437 | ;; Those for integer source operand are ordered widest source type first. | |
| 438 | ||
| 439 | (define_expand "zero_extendhisi2" | |
| 440 | [(set (match_operand:SI 0 "register_operand" "") | |
| 441 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 442 | "" | |
| 443 | "") | |
| 444 | ||
| 445 | (define_insn "" | |
| 446 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 447 | (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] | |
| 448 | "" | |
| 449 | "* | |
| 450 | { | |
| 451 | if (which_alternative == 0) | |
| 452 | return \"andi\\t%0,%1,0xffff\"; | |
| 453 | else | |
| 454 | return iq2000_move_1word (operands, insn, TRUE); | |
| 455 | }" | |
| 456 | [(set_attr "type" "arith,load,load") | |
| 457 | (set_attr "mode" "SI") | |
| 458 | (set_attr "length" "4,4,8")]) | |
| 459 | ||
| 460 | (define_expand "zero_extendqihi2" | |
| 461 | [(set (match_operand:HI 0 "register_operand" "") | |
| 462 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 463 | "" | |
| 464 | "") | |
| 465 | ||
| 466 | (define_insn "" | |
| 467 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
| 468 | (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 469 | "" | |
| 470 | "* | |
| 471 | { | |
| 472 | if (which_alternative == 0) | |
| 473 | return \"andi\\t%0,%1,0x00ff\"; | |
| 474 | else | |
| 475 | return iq2000_move_1word (operands, insn, TRUE); | |
| 476 | }" | |
| 477 | [(set_attr "type" "arith,load,load") | |
| 478 | (set_attr "mode" "HI") | |
| 479 | (set_attr "length" "4,4,8")]) | |
| 480 | ||
| 481 | (define_expand "zero_extendqisi2" | |
| 482 | [(set (match_operand:SI 0 "register_operand" "") | |
| 483 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 484 | "" | |
| 485 | "") | |
| 486 | ||
| 487 | (define_insn "" | |
| 488 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 489 | (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 490 | "" | |
| 491 | "* | |
| 492 | { | |
| 493 | if (which_alternative == 0) | |
| 494 | return \"andi\\t%0,%1,0x00ff\"; | |
| 495 | else | |
| 496 | return iq2000_move_1word (operands, insn, TRUE); | |
| 497 | }" | |
| 498 | [(set_attr "type" "arith,load,load") | |
| 499 | (set_attr "mode" "SI") | |
| 500 | (set_attr "length" "4,4,8")]) | |
| 501 | ||
| 502 | ;; | |
| 503 | ;; .................... | |
| 504 | ;; | |
| 505 | ;; SIGN EXTENSION | |
| 506 | ;; | |
| 507 | ;; .................... | |
| 508 | ||
| 509 | ;; Extension insns. | |
| 510 | ;; Those for integer source operand are ordered widest source type first. | |
| 511 | ||
| 512 | ;; These patterns originally accepted general_operands, however, slightly | |
| 513 | ;; better code is generated by only accepting register_operands, and then | |
| 514 | ;; letting combine generate the lh and lb insns. | |
| 515 | ||
| 516 | (define_expand "extendhisi2" | |
| 517 | [(set (match_operand:SI 0 "register_operand" "") | |
| 518 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 519 | "" | |
| 520 | " | |
| 521 | { | |
| 522 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 523 | operands[1] = force_not_mem (operands[1]); | |
| 524 | ||
| 525 | if (GET_CODE (operands[1]) != MEM) | |
| 526 | { | |
| 527 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 528 | rtx temp = gen_reg_rtx (SImode); | |
| 529 | rtx shift = GEN_INT (16); | |
| 530 | ||
| 531 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 532 | emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 533 | DONE; | |
| 534 | } | |
| 535 | }") | |
| 536 | ||
| 537 | (define_insn "extendhisi2_internal" | |
| 538 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 539 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] | |
| 540 | "" | |
| 541 | "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 542 | [(set_attr "type" "load") | |
| 543 | (set_attr "mode" "SI") | |
| 544 | (set_attr "length" "4,8")]) | |
| 545 | ||
| 546 | (define_expand "extendqihi2" | |
| 547 | [(set (match_operand:HI 0 "register_operand" "") | |
| 548 | (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 549 | "" | |
| 550 | " | |
| 551 | { | |
| 552 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 553 | operands[1] = force_not_mem (operands[1]); | |
| 554 | ||
| 555 | if (GET_CODE (operands[1]) != MEM) | |
| 556 | { | |
| 557 | rtx op0 = gen_lowpart (SImode, operands[0]); | |
| 558 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 559 | rtx temp = gen_reg_rtx (SImode); | |
| 560 | rtx shift = GEN_INT (24); | |
| 561 | ||
| 562 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 563 | emit_insn (gen_ashrsi3 (op0, temp, shift)); | |
| 564 | DONE; | |
| 565 | } | |
| 566 | }") | |
| 567 | ||
| 568 | (define_insn "extendqihi2_internal" | |
| 569 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 570 | (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 571 | "" | |
| 572 | "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 573 | [(set_attr "type" "load") | |
| 574 | (set_attr "mode" "SI") | |
| 575 | (set_attr "length" "4,8")]) | |
| 576 | ||
| 577 | ||
| 578 | (define_expand "extendqisi2" | |
| 579 | [(set (match_operand:SI 0 "register_operand" "") | |
| 580 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 581 | "" | |
| 582 | " | |
| 583 | { | |
| 584 | if (optimize && GET_CODE (operands[1]) == MEM) | |
| 585 | operands[1] = force_not_mem (operands[1]); | |
| 586 | ||
| 587 | if (GET_CODE (operands[1]) != MEM) | |
| 588 | { | |
| 589 | rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 590 | rtx temp = gen_reg_rtx (SImode); | |
| 591 | rtx shift = GEN_INT (24); | |
| 592 | ||
| 593 | emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 594 | emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 595 | DONE; | |
| 596 | } | |
| 597 | }") | |
| 598 | ||
| 599 | (define_insn "extendqisi2_insn" | |
| 600 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 601 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 602 | "" | |
| 603 | "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 604 | [(set_attr "type" "load") | |
| 605 | (set_attr "mode" "SI") | |
| 606 | (set_attr "length" "4,8")]) | |
| 607 | \f | |
| 608 | ;; | |
| 609 | ;; ........................ | |
| 610 | ;; | |
| 611 | ;; BIT FIELD EXTRACTION | |
| 612 | ;; | |
| 613 | ;; ........................ | |
| 614 | ||
| 615 | (define_insn "extzv" | |
| 616 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 617 | (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | |
| 618 | (match_operand:SI 2 "const_int_operand" "O") | |
| 619 | (match_operand:SI 3 "const_int_operand" "O")))] | |
| 620 | "" | |
| 621 | "* | |
| 622 | { | |
| 623 | int value[4]; | |
| 624 | value[2] = INTVAL (operands[2]); | |
| 625 | value[3] = INTVAL (operands[3]); | |
| 626 | operands[2] = GEN_INT ((value[3])); | |
| 627 | operands[3] = GEN_INT ((32 - value[2])); | |
| 628 | return \"ram\\t%0,%1,%2,%3,0x0\"; | |
| 629 | }" | |
| 630 | [(set_attr "type" "arith")]) | |
| 631 | \f | |
| 632 | ;; | |
| 633 | ;; .................... | |
| 634 | ;; | |
| 635 | ;; DATA MOVEMENT | |
| 636 | ;; | |
| 637 | ;; .................... | |
| 638 | ||
| 639 | /* Take care of constants that don't fit in single instruction */ | |
| 640 | (define_split | |
| 641 | [(set (match_operand:SI 0 "register_operand" "") | |
| 642 | (match_operand:SI 1 "general_operand" ""))] | |
| 643 | "(reload_in_progress || reload_completed) | |
| 644 | && large_int (operands[1], SImode)" | |
| 645 | ||
| 646 | [(set (match_dup 0 ) | |
| 647 | (high:SI (match_dup 1))) | |
| 648 | (set (match_dup 0 ) | |
| 649 | (lo_sum:SI (match_dup 0) | |
| 650 | (match_dup 1)))] | |
| 651 | ) | |
| 652 | ||
| 653 | ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be | |
| 654 | ;; unnecessary. | |
| 655 | ||
| 656 | (define_insn "high" | |
| 657 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 658 | (high:SI (match_operand:SI 1 "immediate_operand" "")))] | |
| 659 | "" | |
| 660 | "lui\\t%0,%%hi(%1) # high" | |
| 661 | [(set_attr "type" "move")]) | |
| 662 | ||
| 663 | (define_insn "low" | |
| 664 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 665 | (lo_sum:SI (match_operand:SI 1 "register_operand" "r") | |
| 666 | (match_operand:SI 2 "immediate_operand" "")))] | |
| 667 | "" | |
| 668 | "addiu\\t%0,%1,%%lo(%2) # low" | |
| 669 | [(set_attr "type" "arith") | |
| 670 | (set_attr "mode" "SI")]) | |
| 671 | ||
| 672 | ;; 32-bit Integer moves | |
| 673 | ||
| 674 | (define_split | |
| 675 | [(set (match_operand:SI 0 "register_operand" "") | |
| 676 | (match_operand:SI 1 "large_int" ""))] | |
| 677 | "reload_in_progress | reload_completed" | |
| 678 | [(set (match_dup 0) | |
| 679 | (match_dup 2)) | |
| 680 | (set (match_dup 0) | |
| 681 | (ior:SI (match_dup 0) | |
| 682 | (match_dup 3)))] | |
| 683 | " | |
| 684 | { | |
| 685 | operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]) | |
| 686 | & BITMASK_UPPER16, | |
| 687 | SImode)); | |
| 688 | operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16); | |
| 689 | }") | |
| 690 | ||
| 691 | ;; Unlike most other insns, the move insns can't be split with | |
| 692 | ;; different predicates, because register spilling and other parts of | |
| 693 | ;; the compiler, have memoized the insn number already. | |
| 694 | ||
| 695 | (define_expand "movsi" | |
| 696 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 697 | (match_operand:SI 1 "general_operand" ""))] | |
| 698 | "" | |
| 699 | " | |
| 700 | { | |
| 701 | if (iq2000_check_split (operands[1], SImode)) | |
| 702 | { | |
| ef4bddc2 | 703 | machine_mode mode = GET_MODE (operands[0]); |
| 6b3d1e47 SC |
704 | rtx tem = ((reload_in_progress | reload_completed) |
| 705 | ? operands[0] : gen_reg_rtx (mode)); | |
| 706 | ||
| f7df4a84 | 707 | emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (mode, operands[1]))); |
| 6b3d1e47 SC |
708 | |
| 709 | operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]); | |
| 710 | } | |
| 711 | ||
| 712 | if ((reload_in_progress | reload_completed) == 0 | |
| 713 | && !register_operand (operands[0], SImode) | |
| 714 | && !register_operand (operands[1], SImode) | |
| 715 | && (GET_CODE (operands[1]) != CONST_INT | |
| 716 | || INTVAL (operands[1]) != 0)) | |
| 717 | { | |
| 718 | rtx temp = force_reg (SImode, operands[1]); | |
| 719 | emit_move_insn (operands[0], temp); | |
| 720 | DONE; | |
| 721 | } | |
| 722 | ||
| 723 | /* Take care of constants that don't fit in single instruction */ | |
| 724 | if ((reload_in_progress || reload_completed) | |
| 725 | && CONSTANT_P (operands[1]) | |
| 726 | && GET_CODE (operands[1]) != HIGH | |
| 727 | && GET_CODE (operands[1]) != LO_SUM | |
| 728 | && ! SMALL_INT_UNSIGNED (operands[1])) | |
| 729 | { | |
| 730 | rtx tem = ((reload_in_progress | reload_completed) | |
| 731 | ? operands[0] : gen_reg_rtx (SImode)); | |
| 732 | ||
| f7df4a84 | 733 | emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (SImode, operands[1]))); |
| 6b3d1e47 SC |
734 | operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]); |
| 735 | } | |
| 736 | }") | |
| 737 | ||
| 738 | ;; The difference between these two is whether or not ints are allowed | |
| 739 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 740 | ||
| 741 | (define_insn "movsi_internal2" | |
| 679e8183 NF |
742 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m") |
| 743 | (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))] | |
| 6b3d1e47 SC |
744 | "(register_operand (operands[0], SImode) |
| 745 | || register_operand (operands[1], SImode) | |
| 746 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 747 | "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 679e8183 | 748 | [(set_attr "type" "move,arith,arith,load,load,store,store") |
| 6b3d1e47 | 749 | (set_attr "mode" "SI") |
| 679e8183 | 750 | (set_attr "length" "4,4,8,8,8,4,8")]) |
| 6b3d1e47 SC |
751 | |
| 752 | ;; 16-bit Integer moves | |
| 753 | ||
| 754 | ;; Unlike most other insns, the move insns can't be split with | |
| 755 | ;; different predicates, because register spilling and other parts of | |
| 756 | ;; the compiler, have memoized the insn number already. | |
| 757 | ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 758 | ||
| 759 | (define_expand "movhi" | |
| 760 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 761 | (match_operand:HI 1 "general_operand" ""))] | |
| 762 | "" | |
| 763 | " | |
| 764 | { | |
| 765 | if ((reload_in_progress | reload_completed) == 0 | |
| 766 | && !register_operand (operands[0], HImode) | |
| 767 | && !register_operand (operands[1], HImode) | |
| 768 | && ((GET_CODE (operands[1]) != CONST_INT | |
| 769 | || INTVAL (operands[1]) != 0))) | |
| 770 | { | |
| 771 | rtx temp = force_reg (HImode, operands[1]); | |
| 772 | emit_move_insn (operands[0], temp); | |
| 773 | DONE; | |
| 774 | } | |
| 775 | }") | |
| 776 | ||
| 777 | ;; The difference between these two is whether or not ints are allowed | |
| 778 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 779 | ||
| 780 | (define_insn "movhi_internal2" | |
| 679e8183 NF |
781 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m") |
| 782 | (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))] | |
| 6b3d1e47 SC |
783 | "(register_operand (operands[0], HImode) |
| 784 | || register_operand (operands[1], HImode) | |
| 785 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 786 | "* return iq2000_move_1word (operands, insn, TRUE);" | |
| 679e8183 | 787 | [(set_attr "type" "move,arith,load,load,store,store") |
| 6b3d1e47 | 788 | (set_attr "mode" "HI") |
| 679e8183 | 789 | (set_attr "length" "4,4,4,8,4,8")]) |
| 6b3d1e47 SC |
790 | |
| 791 | ;; 8-bit Integer moves | |
| 792 | ||
| 793 | ;; Unlike most other insns, the move insns can't be split with | |
| 794 | ;; different predicates, because register spilling and other parts of | |
| 795 | ;; the compiler, have memoized the insn number already. | |
| 796 | ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 797 | ||
| 798 | (define_expand "movqi" | |
| 799 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 800 | (match_operand:QI 1 "general_operand" ""))] | |
| 801 | "" | |
| 802 | " | |
| 803 | { | |
| 804 | if ((reload_in_progress | reload_completed) == 0 | |
| 805 | && !register_operand (operands[0], QImode) | |
| 806 | && !register_operand (operands[1], QImode) | |
| 807 | && (GET_CODE (operands[1]) != CONST_INT | |
| 808 | || INTVAL (operands[1]) != 0)) | |
| 809 | { | |
| 810 | rtx temp = force_reg (QImode, operands[1]); | |
| 811 | emit_move_insn (operands[0], temp); | |
| 812 | DONE; | |
| 813 | } | |
| 814 | }") | |
| 815 | ||
| 816 | ;; The difference between these two is whether or not ints are allowed | |
| 817 | ;; in FP registers (off by default, use -mdebugh to enable). | |
| 818 | ||
| 819 | (define_insn "movqi_internal2" | |
| 679e8183 NF |
820 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m") |
| 821 | (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))] | |
| 6b3d1e47 SC |
822 | "(register_operand (operands[0], QImode) |
| 823 | || register_operand (operands[1], QImode) | |
| 824 | || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 825 | "* return iq2000_move_1word (operands, insn, TRUE);" | |
| 679e8183 | 826 | [(set_attr "type" "move,arith,load,load,store,store") |
| 6b3d1e47 | 827 | (set_attr "mode" "QI") |
| 679e8183 | 828 | (set_attr "length" "4,4,4,8,4,8")]) |
| 6b3d1e47 SC |
829 | |
| 830 | ;; 32-bit floating point moves | |
| 831 | ||
| 832 | (define_expand "movsf" | |
| 833 | [(set (match_operand:SF 0 "general_operand" "") | |
| 834 | (match_operand:SF 1 "general_operand" ""))] | |
| 835 | "" | |
| 836 | " | |
| 837 | { | |
| 838 | if (!reload_in_progress | |
| 839 | && !reload_completed | |
| 840 | && GET_CODE (operands[0]) == MEM | |
| 841 | && (GET_CODE (operands[1]) == MEM | |
| 842 | || GET_CODE (operands[1]) == CONST_DOUBLE)) | |
| 843 | operands[1] = copy_to_mode_reg (SFmode, operands[1]); | |
| 844 | ||
| 845 | /* Take care of reg <- SF constant */ | |
| 846 | if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) ) | |
| 847 | { | |
| 848 | emit_insn (gen_movsf_high (operands[0], operands[1])); | |
| 849 | emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1])); | |
| 850 | DONE; | |
| 851 | } | |
| 852 | }") | |
| 853 | ||
| 854 | (define_insn "movsf_lo_sum" | |
| 855 | [(set (match_operand:SF 0 "register_operand" "=r") | |
| 856 | (lo_sum:SF (match_operand:SF 1 "register_operand" "r") | |
| 857 | (match_operand:SF 2 "const_double_operand" "")))] | |
| 858 | "" | |
| 859 | "* | |
| 860 | { | |
| 6b3d1e47 SC |
861 | long i; |
| 862 | ||
| 34a72c33 | 863 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[2]), i); |
| 6b3d1e47 SC |
864 | operands[2] = GEN_INT (i); |
| 865 | return \"addiu\\t%0,%1,%%lo(%2) # low\"; | |
| 866 | }" | |
| 867 | [(set_attr "length" "4") | |
| 868 | (set_attr "type" "arith")]) | |
| 869 | ||
| 870 | (define_insn "movsf_high" | |
| 871 | [(set (match_operand:SF 0 "register_operand" "=r") | |
| 872 | (high:SF (match_operand:SF 1 "const_double_operand" "")))] | |
| 873 | "" | |
| 874 | "* | |
| 875 | { | |
| 6b3d1e47 SC |
876 | long i; |
| 877 | ||
| 34a72c33 | 878 | REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), i); |
| 6b3d1e47 SC |
879 | operands[1] = GEN_INT (i); |
| 880 | return \"lui\\t%0,%%hi(%1) # high\"; | |
| 881 | }" | |
| 882 | [(set_attr "length" "4") | |
| 883 | (set_attr "type" "arith")]) | |
| 884 | ||
| 885 | (define_insn "*movsf_internal" | |
| 886 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") | |
| 887 | (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))] | |
| 888 | "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)" | |
| 889 | "* | |
| 890 | { | |
| 891 | iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn); | |
| 892 | if (which_alternative == 0) | |
| 893 | return \"or\\t%0,%1,%1\"; | |
| 894 | else if (which_alternative == 1) | |
| 895 | return \"lw\\t%0,%1\"; | |
| 896 | else if (which_alternative == 2) | |
| 897 | return \"sw\\t%1,%0\"; | |
| 954c7446 JR |
898 | else |
| 899 | gcc_unreachable (); | |
| 6b3d1e47 SC |
900 | }" |
| 901 | [(set_attr "length" "4,4,4") | |
| 902 | (set_attr "type" "arith,load,store")] | |
| 903 | ) | |
| 904 | \f | |
| 905 | ;; | |
| 906 | ;; .................... | |
| 907 | ;; | |
| 908 | ;; SHIFTS | |
| 909 | ;; | |
| 910 | ;; .................... | |
| 911 | ||
| 912 | (define_expand "ashlsi3" | |
| 913 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 914 | (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 915 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 916 | "" | |
| 917 | "") | |
| 918 | ||
| 919 | (define_insn "ashlsi3_internal1" | |
| 920 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 921 | (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 922 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 923 | "" | |
| 924 | "* | |
| 925 | { | |
| 926 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 927 | { | |
| 928 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 929 | return \"sll\\t%0,%1,%2\"; | |
| 930 | } | |
| 931 | else | |
| 932 | return \"sllv\\t%0,%1,%2\"; | |
| 933 | }" | |
| 934 | [(set_attr "type" "arith") | |
| 935 | (set_attr "mode" "SI")]) | |
| 936 | ||
| 937 | (define_expand "ashrsi3" | |
| 938 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 939 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 940 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 941 | "" | |
| 942 | "") | |
| 943 | ||
| 944 | (define_insn "ashrsi3_internal1" | |
| 945 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 946 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 947 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 948 | "" | |
| 949 | "* | |
| 950 | { | |
| 951 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 952 | { | |
| 953 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 954 | return \"sra\\t%0,%1,%2\"; | |
| 955 | } | |
| 956 | else | |
| 957 | return \"srav\\t%0,%1,%2\"; | |
| 958 | }" | |
| 959 | [(set_attr "type" "arith") | |
| 960 | (set_attr "mode" "SI")]) | |
| 961 | ||
| 962 | (define_expand "lshrsi3" | |
| 963 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 964 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 965 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 966 | "" | |
| 967 | "") | |
| 968 | ||
| 969 | (define_insn "lshrsi3_internal1" | |
| 970 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 971 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 972 | (match_operand:SI 2 "arith_operand" "dI")))] | |
| 973 | "" | |
| 974 | "* | |
| 975 | { | |
| 976 | if (GET_CODE (operands[2]) == CONST_INT) | |
| 977 | { | |
| 978 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 979 | return \"srl\\t%0,%1,%2\"; | |
| 980 | } | |
| 981 | else | |
| 982 | return \"srlv\\t%0,%1,%2\"; | |
| 983 | }" | |
| 984 | [(set_attr "type" "arith") | |
| 985 | (set_attr "mode" "SI")]) | |
| 986 | ||
| 987 | ;; Rotate Right | |
| 988 | (define_insn "rotrsi3" | |
| 989 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 990 | (rotatert:SI (match_operand:SI 1 "register_operand" "r") | |
| 991 | (match_operand:SI 2 "uns_arith_operand" "O")))] | |
| 992 | "" | |
| 993 | "ram %0,%1,%2,0x0,0x0" | |
| 994 | [(set_attr "type" "arith")]) | |
| 995 | ||
| 996 | \f | |
| 997 | ;; | |
| 998 | ;; .................... | |
| 999 | ;; | |
| f90b7a5a | 1000 | ;; CONDITIONAL BRANCHES |
| 6b3d1e47 SC |
1001 | ;; |
| 1002 | ;; .................... | |
| 1003 | ||
| f90b7a5a PB |
1004 | (define_expand "cbranchsi4" |
| 1005 | [(set (pc) | |
| 1006 | (if_then_else | |
| 335db8e6 NC |
1007 | (match_operator 0 "ordered_comparison_operator" |
| 1008 | [(match_operand:SI 1 "register_operand") | |
| 1009 | (match_operand:SI 2 "reg_or_const_operand")]) | |
| 1010 | (label_ref (match_operand 3 "")) | |
| f90b7a5a | 1011 | (pc)))] |
| 6b3d1e47 SC |
1012 | "" |
| 1013 | " | |
| 1014 | { | |
| f90b7a5a PB |
1015 | gen_conditional_branch (operands, SImode); |
| 1016 | DONE; | |
| 6b3d1e47 SC |
1017 | }") |
| 1018 | ||
| 6b3d1e47 SC |
1019 | |
| 1020 | ;; Conditional branches on comparisons with zero. | |
| 1021 | ||
| 1022 | (define_insn "branch_zero" | |
| 1023 | [(set (pc) | |
| 1024 | (if_then_else | |
| 335db8e6 NC |
1025 | (match_operator 0 "cmp_op" |
| 1026 | [(match_operand:SI 2 "register_operand" "d") | |
| 1027 | (const_int 0)]) | |
| 6b3d1e47 SC |
1028 | (label_ref (match_operand 1 "" "")) |
| 1029 | (pc)))] | |
| 1030 | "" | |
| 1031 | "* | |
| 1032 | { | |
| 1033 | return iq2000_output_conditional_branch (insn, | |
| 1034 | operands, | |
| 1035 | /*two_operands_p=*/0, | |
| 1036 | /*float_p=*/0, | |
| 1037 | /*inverted_p=*/0, | |
| 1038 | get_attr_length (insn)); | |
| 1039 | }" | |
| 1040 | [(set_attr "type" "branch") | |
| 1041 | (set_attr "mode" "none")]) | |
| 1042 | ||
| 1043 | (define_insn "branch_zero_inverted" | |
| 1044 | [(set (pc) | |
| 1045 | (if_then_else | |
| 335db8e6 NC |
1046 | (match_operator 0 "cmp_op" |
| 1047 | [(match_operand:SI 2 "register_operand" "d") | |
| 1048 | (const_int 0)]) | |
| 6b3d1e47 SC |
1049 | (pc) |
| 1050 | (label_ref (match_operand 1 "" ""))))] | |
| 1051 | "" | |
| 1052 | "* | |
| 1053 | { | |
| 1054 | return iq2000_output_conditional_branch (insn, | |
| 1055 | operands, | |
| 1056 | /*two_operands_p=*/0, | |
| 1057 | /*float_p=*/0, | |
| 1058 | /*inverted_p=*/1, | |
| 1059 | get_attr_length (insn)); | |
| 1060 | }" | |
| 1061 | [(set_attr "type" "branch") | |
| 1062 | (set_attr "mode" "none")]) | |
| 1063 | ||
| 2cac216b | 1064 | ;; Conditional branch on equality comparison. |
| 6b3d1e47 SC |
1065 | |
| 1066 | (define_insn "branch_equality" | |
| 1067 | [(set (pc) | |
| 1068 | (if_then_else | |
| 335db8e6 NC |
1069 | (match_operator 0 "equality_op" |
| 1070 | [(match_operand:SI 2 "register_operand" "d") | |
| 1071 | (match_operand:SI 3 "register_operand" "d")]) | |
| 6b3d1e47 SC |
1072 | (label_ref (match_operand 1 "" "")) |
| 1073 | (pc)))] | |
| 1074 | "" | |
| 1075 | "* | |
| 1076 | { | |
| 1077 | return iq2000_output_conditional_branch (insn, | |
| 1078 | operands, | |
| 1079 | /*two_operands_p=*/1, | |
| 1080 | /*float_p=*/0, | |
| 1081 | /*inverted_p=*/0, | |
| 1082 | get_attr_length (insn)); | |
| 1083 | }" | |
| 1084 | [(set_attr "type" "branch") | |
| 1085 | (set_attr "mode" "none")]) | |
| 1086 | ||
| 1087 | (define_insn "branch_equality_inverted" | |
| 1088 | [(set (pc) | |
| 1089 | (if_then_else | |
| 335db8e6 NC |
1090 | (match_operator 0 "equality_op" |
| 1091 | [(match_operand:SI 2 "register_operand" "d") | |
| 1092 | (match_operand:SI 3 "register_operand" "d")]) | |
| 6b3d1e47 SC |
1093 | (pc) |
| 1094 | (label_ref (match_operand 1 "" ""))))] | |
| 1095 | "" | |
| 1096 | "* | |
| 1097 | { | |
| 1098 | return iq2000_output_conditional_branch (insn, | |
| 1099 | operands, | |
| 1100 | /*two_operands_p=*/1, | |
| 1101 | /*float_p=*/0, | |
| 1102 | /*inverted_p=*/1, | |
| 1103 | get_attr_length (insn)); | |
| 1104 | }" | |
| 1105 | [(set_attr "type" "branch") | |
| 1106 | (set_attr "mode" "none")]) | |
| 1107 | ||
| 6b3d1e47 SC |
1108 | |
| 1109 | ;; Recognize bbi and bbin instructions. These use two unusual template | |
| 1110 | ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF | |
| 1111 | ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC | |
| 1112 | ;; and outputs the operand if `x' is a LABEL_REF. | |
| 1113 | ||
| 1114 | (define_insn "" | |
| 1115 | [(set (pc) | |
| 1116 | (if_then_else | |
| 1117 | (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1118 | (const_int 1) | |
| 1119 | (match_operand:SI 1 "arith_operand" "I")) | |
| 1120 | (const_int 0)) | |
| 1121 | (match_operand 2 "pc_or_label_operand" "") | |
| 1122 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 1123 | "" | |
| 1124 | "bb%A2\\t%0(31-%1),%P2%P3" | |
| 1125 | [(set_attr "length" "4") | |
| 0364465e JL |
1126 | (set_attr "type" "branch") |
| 1127 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1128 | |
| 1129 | (define_insn "" | |
| 1130 | [(set (pc) | |
| 1131 | (if_then_else | |
| 1132 | (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1133 | (const_int 1) | |
| 1134 | (match_operand:SI 1 "arith_operand" "I")) | |
| 1135 | (const_int 0)) | |
| 1136 | (match_operand 2 "pc_or_label_operand" "") | |
| 1137 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 1138 | "" | |
| 1139 | "bb%A3\\t%0(31-%1),%P2%P3" | |
| 1140 | [(set_attr "length" "4") | |
| 0364465e JL |
1141 | (set_attr "type" "branch") |
| 1142 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1143 | |
| 1144 | (define_insn "" | |
| 1145 | [(set (pc) | |
| 1146 | (if_then_else | |
| 1147 | (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1148 | (const_int 1) | |
| 1149 | (match_operand:SI 1 "arith_operand" "I")) | |
| 1150 | (const_int 0)) | |
| 1151 | (match_operand 2 "pc_or_label_operand" "") | |
| 1152 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 335db8e6 | 1153 | "0" |
| 6b3d1e47 SC |
1154 | "bb%A2\\t%0(31-%1),%P2%P3" |
| 1155 | [(set_attr "length" "4") | |
| 0364465e JL |
1156 | (set_attr "type" "branch") |
| 1157 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1158 | |
| 1159 | (define_insn "" | |
| 1160 | [(set (pc) | |
| 1161 | (if_then_else | |
| 1162 | (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1163 | (const_int 1) | |
| 1164 | (match_operand:SI 1 "arith_operand" "I")) | |
| 1165 | (const_int 0)) | |
| 1166 | (match_operand 2 "pc_or_label_operand" "") | |
| 1167 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 335db8e6 | 1168 | "0" |
| 6b3d1e47 SC |
1169 | "bb%A3\\t%0(31-%1),%P2%P3" |
| 1170 | [(set_attr "length" "4") | |
| 0364465e JL |
1171 | (set_attr "type" "branch") |
| 1172 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1173 | |
| 1174 | (define_insn "" | |
| 1175 | [(set (pc) | |
| 1176 | (if_then_else | |
| 1177 | (eq (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1178 | (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1179 | (const_int 0)) | |
| 1180 | (match_operand 2 "pc_or_label_operand" "") | |
| 1181 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 1182 | "" | |
| 1183 | "bb%A3\\t%0(%p1),%P2%P3" | |
| 1184 | [(set_attr "length" "4") | |
| 0364465e JL |
1185 | (set_attr "type" "branch") |
| 1186 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1187 | |
| 1188 | (define_insn "" | |
| 1189 | [(set (pc) | |
| 1190 | (if_then_else | |
| 1191 | (ne (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1192 | (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1193 | (const_int 0)) | |
| 1194 | (match_operand 2 "pc_or_label_operand" "") | |
| 1195 | (match_operand 3 "pc_or_label_operand" "")))] | |
| 1196 | "" | |
| 1197 | "bb%A2\\t%0(%p1),%P2%P3" | |
| 1198 | [(set_attr "length" "4") | |
| 0364465e JL |
1199 | (set_attr "type" "branch") |
| 1200 | (set_attr "bbi" "yes")]) | |
| 6b3d1e47 SC |
1201 | \f |
| 1202 | ;; | |
| 1203 | ;; .................... | |
| 1204 | ;; | |
| 1205 | ;; SETTING A REGISTER FROM A COMPARISON | |
| 1206 | ;; | |
| 1207 | ;; .................... | |
| 1208 | ||
| f90b7a5a | 1209 | (define_expand "cstoresi4" |
| 6b3d1e47 | 1210 | [(set (match_operand:SI 0 "register_operand" "=d") |
| f90b7a5a PB |
1211 | (match_operator:SI 1 "ordered_comparison_operator" |
| 1212 | [(match_operand:SI 2 "register_operand") | |
| 1213 | (match_operand:SI 3 "reg_or_const_operand")]))] | |
| 6b3d1e47 SC |
1214 | "" |
| 1215 | " | |
| 1216 | { | |
| f90b7a5a PB |
1217 | gen_int_relational (GET_CODE (operands[1]), operands[0], |
| 1218 | operands[2], operands[3], (int *)0); | |
| 6b3d1e47 SC |
1219 | DONE; |
| 1220 | }") | |
| 1221 | ||
| 6b3d1e47 SC |
1222 | (define_insn "seq_si_zero" |
| 1223 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1224 | (eq:SI (match_operand:SI 1 "register_operand" "d") | |
| 1225 | (const_int 0)))] | |
| 1226 | "" | |
| 1227 | "sltiu\\t%0,%1,1" | |
| 1228 | [(set_attr "type" "arith") | |
| 1229 | (set_attr "mode" "SI")]) | |
| 1230 | ||
| 6b3d1e47 SC |
1231 | (define_insn "sne_si_zero" |
| 1232 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1233 | (ne:SI (match_operand:SI 1 "register_operand" "d") | |
| 1234 | (const_int 0)))] | |
| 1235 | "" | |
| 1236 | "sltu\\t%0,%.,%1" | |
| 1237 | [(set_attr "type" "arith") | |
| 1238 | (set_attr "mode" "SI")]) | |
| 1239 | ||
| 6b3d1e47 | 1240 | (define_insn "sgt_si" |
| 73f793e3 | 1241 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 6b3d1e47 SC |
1242 | (gt:SI (match_operand:SI 1 "register_operand" "d,d") |
| 1243 | (match_operand:SI 2 "reg_or_0_operand" "d,J")))] | |
| 1244 | "" | |
| 1245 | "@ | |
| 1246 | slt\\t%0,%z2,%1 | |
| 1247 | slt\\t%0,%z2,%1" | |
| 1248 | [(set_attr "type" "arith,arith") | |
| 1249 | (set_attr "mode" "SI,SI")]) | |
| 1250 | ||
| 6b3d1e47 | 1251 | (define_insn "slt_si" |
| 73f793e3 | 1252 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 6b3d1e47 SC |
1253 | (lt:SI (match_operand:SI 1 "register_operand" "d,d") |
| 1254 | (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1255 | "" | |
| 1256 | "@ | |
| 1257 | slt\\t%0,%1,%2 | |
| 1258 | slti\\t%0,%1,%2" | |
| 1259 | [(set_attr "type" "arith,arith") | |
| 1260 | (set_attr "mode" "SI,SI")]) | |
| 1261 | ||
| 6b3d1e47 SC |
1262 | (define_insn "sle_si_const" |
| 1263 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1264 | (le:SI (match_operand:SI 1 "register_operand" "d") | |
| 1265 | (match_operand:SI 2 "small_int" "I")))] | |
| 1266 | "INTVAL (operands[2]) < 32767" | |
| 1267 | "* | |
| 1268 | { | |
| 1269 | operands[2] = GEN_INT (INTVAL (operands[2])+1); | |
| 1270 | return \"slti\\t%0,%1,%2\"; | |
| 1271 | }" | |
| 1272 | [(set_attr "type" "arith") | |
| 1273 | (set_attr "mode" "SI")]) | |
| 1274 | ||
| 6b3d1e47 SC |
1275 | (define_insn "sgtu_si" |
| 1276 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1277 | (gtu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1278 | (match_operand:SI 2 "reg_or_0_operand" "dJ")))] | |
| 1279 | "" | |
| 1280 | "sltu\\t%0,%z2,%1" | |
| 1281 | [(set_attr "type" "arith") | |
| 1282 | (set_attr "mode" "SI")]) | |
| 1283 | ||
| 6b3d1e47 | 1284 | (define_insn "sltu_si" |
| 73f793e3 | 1285 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 6b3d1e47 SC |
1286 | (ltu:SI (match_operand:SI 1 "register_operand" "d,d") |
| 1287 | (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1288 | "" | |
| 1289 | "@ | |
| 1290 | sltu\\t%0,%1,%2 | |
| 1291 | sltiu\\t%0,%1,%2" | |
| 1292 | [(set_attr "type" "arith,arith") | |
| 1293 | (set_attr "mode" "SI,SI")]) | |
| 1294 | ||
| 6b3d1e47 SC |
1295 | (define_insn "sleu_si_const" |
| 1296 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1297 | (leu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1298 | (match_operand:SI 2 "small_int" "I")))] | |
| 1299 | "INTVAL (operands[2]) < 32767" | |
| 1300 | "* | |
| 1301 | { | |
| 1302 | operands[2] = GEN_INT (INTVAL (operands[2]) + 1); | |
| 1303 | return \"sltiu\\t%0,%1,%2\"; | |
| 1304 | }" | |
| 1305 | [(set_attr "type" "arith") | |
| 1306 | (set_attr "mode" "SI")]) | |
| 1307 | ||
| 1308 | \f | |
| 1309 | ;; | |
| 1310 | ;; .................... | |
| 1311 | ;; | |
| 1312 | ;; UNCONDITIONAL BRANCHES | |
| 1313 | ;; | |
| 1314 | ;; .................... | |
| 1315 | ||
| 1316 | ;; Unconditional branches. | |
| 1317 | ||
| 1318 | (define_insn "jump" | |
| 1319 | [(set (pc) | |
| 1320 | (label_ref (match_operand 0 "" "")))] | |
| 1321 | "" | |
| 1322 | "* | |
| 1323 | { | |
| 1324 | if (GET_CODE (operands[0]) == REG) | |
| 1325 | return \"j\\t%0\"; | |
| 1326 | return \"j\\t%l0\"; | |
| 1327 | /* return \"b\\t%l0\";*/ | |
| 1328 | }" | |
| 1329 | [(set_attr "type" "jump") | |
| 1330 | (set_attr "mode" "none")]) | |
| 1331 | ||
| 1332 | (define_expand "indirect_jump" | |
| 1333 | [(set (pc) (match_operand 0 "register_operand" "d"))] | |
| 1334 | "" | |
| 1335 | " | |
| 1336 | { | |
| 1337 | rtx dest; | |
| 1338 | ||
| 1339 | if (operands[0]) /* eliminate unused code warnings */ | |
| 1340 | { | |
| 1341 | dest = operands[0]; | |
| 1342 | if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) | |
| 1343 | operands[0] = copy_to_mode_reg (Pmode, dest); | |
| 1344 | ||
| 1345 | if (!(Pmode == DImode)) | |
| 1346 | emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); | |
| 1347 | else | |
| 954c7446 | 1348 | internal_error (\"unimplemented functionality\"); |
| 6b3d1e47 SC |
1349 | |
| 1350 | DONE; | |
| 1351 | } | |
| 1352 | }") | |
| 1353 | ||
| 1354 | (define_insn "indirect_jump_internal1" | |
| 1355 | [(set (pc) (match_operand:SI 0 "register_operand" "d"))] | |
| 1356 | "!(Pmode == DImode)" | |
| 1357 | "j\\t%0" | |
| 1358 | [(set_attr "type" "jump") | |
| 1359 | (set_attr "mode" "none")]) | |
| 1360 | ||
| 1361 | (define_expand "tablejump" | |
| 1362 | [(set (pc) | |
| 1363 | (match_operand 0 "register_operand" "d")) | |
| 1364 | (use (label_ref (match_operand 1 "" "")))] | |
| 1365 | "" | |
| 1366 | " | |
| 1367 | { | |
| 1368 | if (operands[0]) /* eliminate unused code warnings */ | |
| 1369 | { | |
| 292c8018 | 1370 | gcc_assert (GET_MODE (operands[0]) == Pmode); |
| 6b3d1e47 SC |
1371 | |
| 1372 | if (!(Pmode == DImode)) | |
| 1373 | emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | |
| 1374 | else | |
| 954c7446 | 1375 | internal_error (\"unimplemented functionality\"); |
| 6b3d1e47 SC |
1376 | |
| 1377 | DONE; | |
| 1378 | } | |
| 1379 | }") | |
| 1380 | ||
| 1381 | (define_insn "tablejump_internal1" | |
| 1382 | [(set (pc) | |
| 1383 | (match_operand:SI 0 "register_operand" "d")) | |
| 1384 | (use (label_ref (match_operand 1 "" "")))] | |
| 1385 | "!(Pmode == DImode)" | |
| 1386 | "j\\t%0" | |
| 1387 | [(set_attr "type" "jump") | |
| 1388 | (set_attr "mode" "none")]) | |
| 1389 | ||
| 1390 | (define_expand "tablejump_internal3" | |
| 1391 | [(parallel [(set (pc) | |
| 1392 | (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1393 | (label_ref:SI (match_operand 1 "" "")))) | |
| 1394 | (use (label_ref:SI (match_dup 1)))])] | |
| 1395 | "" | |
| 1396 | "") | |
| 1397 | ||
| 1398 | ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise | |
| 1399 | ;;; it is not valid. ??? With the USE, the condition tests may not be required | |
| 1400 | ;;; any longer. | |
| 1401 | ||
| 1402 | ;;; ??? The length depends on the ABI. It is two for o32, and one for n32. | |
| 1403 | ;;; We just use the conservative number here. | |
| 1404 | ||
| 1405 | (define_insn "" | |
| 1406 | [(set (pc) | |
| 1407 | (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1408 | (label_ref:SI (match_operand 1 "" "")))) | |
| 1409 | (use (label_ref:SI (match_dup 1)))] | |
| b32d5189 DM |
1410 | "!(Pmode == DImode) && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0 |
| 1411 | && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC" | |
| 6b3d1e47 SC |
1412 | "* |
| 1413 | { | |
| 1414 | return \"j\\t%0\"; | |
| 1415 | }" | |
| 1416 | [(set_attr "type" "jump") | |
| 1417 | (set_attr "mode" "none") | |
| 1418 | (set_attr "length" "8")]) | |
| 1419 | \f | |
| 1420 | ;; | |
| 1421 | ;; .................... | |
| 1422 | ;; | |
| 1423 | ;; Function prologue/epilogue | |
| 1424 | ;; | |
| 1425 | ;; .................... | |
| 1426 | ;; | |
| 1427 | ||
| 1428 | (define_expand "prologue" | |
| 1429 | [(const_int 1)] | |
| 1430 | "" | |
| 1431 | " | |
| 1432 | { | |
| 1433 | if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1434 | { | |
| 1435 | iq2000_expand_prologue (); | |
| 1436 | DONE; | |
| 1437 | } | |
| 1438 | }") | |
| 1439 | ||
| 1440 | ;; Block any insns from being moved before this point, since the | |
| 1441 | ;; profiling call to mcount can use various registers that aren't | |
| 1442 | ;; saved or used to pass arguments. | |
| 1443 | ||
| 1444 | (define_insn "blockage" | |
| 1445 | [(unspec_volatile [(const_int 0)] 0)] | |
| 1446 | "" | |
| 1447 | "" | |
| 1448 | [(set_attr "type" "unknown") | |
| 1449 | (set_attr "mode" "none") | |
| 1450 | (set_attr "length" "0")]) | |
| 1451 | ||
| 1452 | (define_expand "epilogue" | |
| 1453 | [(const_int 2)] | |
| 1454 | "" | |
| 1455 | " | |
| 1456 | { | |
| 1457 | if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1458 | { | |
| 1459 | iq2000_expand_epilogue (); | |
| 1460 | DONE; | |
| 1461 | } | |
| 1462 | }") | |
| 1463 | ||
| 1464 | ;; Trivial return. Make it look like a normal return insn as that | |
| 1465 | ;; allows jump optimizations to work better . | |
| 1466 | (define_insn "return" | |
| 1467 | [(return)] | |
| 1468 | "iq2000_can_use_return_insn ()" | |
| 1469 | "j\\t%%31" | |
| 1470 | [(set_attr "type" "jump") | |
| 1471 | (set_attr "mode" "none")]) | |
| 1472 | ||
| 1473 | ;; Normal return. | |
| 1474 | ||
| 1475 | (define_insn "return_internal" | |
| 1476 | [(use (match_operand 0 "pmode_register_operand" "")) | |
| 1477 | (return)] | |
| 1478 | "" | |
| 1479 | "* | |
| 1480 | { | |
| 1481 | return \"j\\t%0\"; | |
| 1482 | }" | |
| 1483 | [(set_attr "type" "jump") | |
| 1484 | (set_attr "mode" "none")]) | |
| 1485 | ||
| 1486 | (define_insn "eh_return_internal" | |
| 1487 | [(const_int 4) | |
| 1488 | (return) | |
| 1489 | (use (reg:SI 26)) | |
| 1490 | (use (reg:SI 31))] | |
| 1491 | "" | |
| 1492 | "j\\t%%26" | |
| 1493 | [(set_attr "type" "jump") | |
| 1494 | (set_attr "mode" "none")]) | |
| 1495 | ||
| 1496 | (define_expand "eh_return" | |
| 1497 | [(use (match_operand:SI 0 "register_operand" "r"))] | |
| 1498 | "" | |
| 1499 | " | |
| 1500 | { | |
| 1501 | iq2000_expand_eh_return (operands[0]); | |
| 1502 | DONE; | |
| 1503 | }") | |
| 1504 | ||
| 1505 | \f | |
| 1506 | ;; | |
| 1507 | ;; .................... | |
| 1508 | ;; | |
| 1509 | ;; FUNCTION CALLS | |
| 1510 | ;; | |
| 1511 | ;; .................... | |
| 1512 | ||
| e53b6e56 | 1513 | ;; calls.cc now passes a third argument, make saber happy |
| 6b3d1e47 SC |
1514 | |
| 1515 | (define_expand "call" | |
| 1516 | [(parallel [(call (match_operand 0 "memory_operand" "m") | |
| 1517 | (match_operand 1 "" "i")) | |
| 1518 | (clobber (reg:SI 31)) | |
| 1519 | (use (match_operand 2 "" "")) ;; next_arg_reg | |
| 1520 | (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx | |
| 1521 | "" | |
| 1522 | " | |
| 1523 | { | |
| 1524 | rtx addr; | |
| 1525 | ||
| 1526 | if (operands[0]) /* eliminate unused code warnings */ | |
| 1527 | { | |
| 1528 | addr = XEXP (operands[0], 0); | |
| 1529 | if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1530 | || ! call_insn_operand (addr, VOIDmode)) | |
| 1531 | XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1532 | ||
| 1533 | /* In order to pass small structures by value in registers | |
| 1534 | compatibly with the IQ2000 compiler, we need to shift the value | |
| 1535 | into the high part of the register. Function_arg has encoded | |
| 1536 | a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1537 | as the next_arg_reg variable, so we split up the insns, | |
| 1538 | and emit them separately. */ | |
| 1539 | ||
| 1540 | if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL) | |
| 1541 | { | |
| 1542 | rtvec adjust = XVEC (operands[2], 0); | |
| 1543 | int num = GET_NUM_ELEM (adjust); | |
| 1544 | int i; | |
| 1545 | ||
| 1546 | for (i = 0; i < num; i++) | |
| 1547 | emit_insn (RTVEC_ELT (adjust, i)); | |
| 1548 | } | |
| 1549 | ||
| 1550 | emit_call_insn (gen_call_internal0 (operands[0], operands[1], | |
| 1551 | gen_rtx_REG (SImode, | |
| 1552 | GP_REG_FIRST + 31))); | |
| 1553 | DONE; | |
| 1554 | } | |
| 1555 | }") | |
| 1556 | ||
| 1557 | (define_expand "call_internal0" | |
| 1558 | [(parallel [(call (match_operand 0 "" "") | |
| 1559 | (match_operand 1 "" "")) | |
| 1560 | (clobber (match_operand:SI 2 "" ""))])] | |
| 1561 | "" | |
| 1562 | "") | |
| 1563 | ||
| 1564 | (define_insn "call_internal1" | |
| 1565 | [(call (mem (match_operand 0 "call_insn_operand" "ri")) | |
| 1566 | (match_operand 1 "" "i")) | |
| 1567 | (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 1568 | "" | |
| 1569 | "* | |
| 1570 | { | |
| 76898cec | 1571 | rtx target = operands[0]; |
| 6b3d1e47 SC |
1572 | |
| 1573 | if (GET_CODE (target) == CONST_INT) | |
| 1574 | return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\"; | |
| 1575 | else if (CONSTANT_ADDRESS_P (target)) | |
| 1576 | return \"jal\\t%0\"; | |
| 1577 | else | |
| 1578 | return \"jalr\\t%2,%0\"; | |
| 1579 | }" | |
| 1580 | [(set_attr "type" "call") | |
| 1581 | (set_attr "mode" "none")]) | |
| 1582 | ||
| e53b6e56 | 1583 | ;; calls.cc now passes a fourth argument, make saber happy |
| 6b3d1e47 SC |
1584 | |
| 1585 | (define_expand "call_value" | |
| 679e8183 | 1586 | [(parallel [(set (match_operand 0 "register_operand" "=d") |
| 6b3d1e47 SC |
1587 | (call (match_operand 1 "memory_operand" "m") |
| 1588 | (match_operand 2 "" "i"))) | |
| 1589 | (clobber (reg:SI 31)) | |
| 1590 | (use (match_operand 3 "" ""))])] ;; next_arg_reg | |
| 1591 | "" | |
| 1592 | " | |
| 1593 | { | |
| 1594 | rtx addr; | |
| 1595 | ||
| 1596 | if (operands[0]) /* eliminate unused code warning */ | |
| 1597 | { | |
| 1598 | addr = XEXP (operands[1], 0); | |
| 1599 | if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1600 | || ! call_insn_operand (addr, VOIDmode)) | |
| 1601 | XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1602 | ||
| 1603 | /* In order to pass small structures by value in registers | |
| 1604 | compatibly with the IQ2000 compiler, we need to shift the value | |
| 1605 | into the high part of the register. Function_arg has encoded | |
| 1606 | a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1607 | as the next_arg_reg variable, so we split up the insns, | |
| 1608 | and emit them separately. */ | |
| 1609 | ||
| 1610 | if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL) | |
| 1611 | { | |
| 1612 | rtvec adjust = XVEC (operands[3], 0); | |
| 1613 | int num = GET_NUM_ELEM (adjust); | |
| 1614 | int i; | |
| 1615 | ||
| 1616 | for (i = 0; i < num; i++) | |
| 1617 | emit_insn (RTVEC_ELT (adjust, i)); | |
| 1618 | } | |
| 1619 | ||
| 1620 | if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1) | |
| 1621 | { | |
| 1622 | emit_call_insn (gen_call_value_multiple_internal0 | |
| 1623 | (XEXP (XVECEXP (operands[0], 0, 0), 0), | |
| 1624 | operands[1], operands[2], | |
| 1625 | XEXP (XVECEXP (operands[0], 0, 1), 0), | |
| 1626 | gen_rtx_REG (SImode, GP_REG_FIRST + 31))); | |
| 1627 | DONE; | |
| 1628 | } | |
| 1629 | ||
| 1630 | /* We have a call returning a DImode structure in an FP reg. | |
| 1631 | Strip off the now unnecessary PARALLEL. */ | |
| 1632 | if (GET_CODE (operands[0]) == PARALLEL) | |
| 1633 | operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0); | |
| 1634 | ||
| 1635 | emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2], | |
| 1636 | gen_rtx_REG (SImode, | |
| 1637 | GP_REG_FIRST + 31))); | |
| 1638 | ||
| 1639 | DONE; | |
| 1640 | } | |
| 1641 | }") | |
| 1642 | ||
| 1643 | (define_expand "call_value_internal0" | |
| 1644 | [(parallel [(set (match_operand 0 "" "") | |
| 1645 | (call (match_operand 1 "" "") | |
| 1646 | (match_operand 2 "" ""))) | |
| 1647 | (clobber (match_operand:SI 3 "" ""))])] | |
| 1648 | "" | |
| 1649 | "") | |
| 1650 | ||
| 1651 | (define_insn "call_value_internal1" | |
| 679e8183 NF |
1652 | [(set (match_operand 0 "register_operand" "=d") |
| 1653 | (call (mem (match_operand 1 "call_insn_operand" "r")) | |
| 6b3d1e47 SC |
1654 | (match_operand 2 "" "i"))) |
| 1655 | (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 1656 | "" | |
| 1657 | "* | |
| 1658 | { | |
| 76898cec | 1659 | rtx target = operands[1]; |
| 6b3d1e47 SC |
1660 | |
| 1661 | if (GET_CODE (target) == CONST_INT) | |
| 1662 | return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\"; | |
| 1663 | else if (CONSTANT_ADDRESS_P (target)) | |
| 1664 | return \"jal\\t%1\"; | |
| 1665 | else | |
| 1666 | return \"jalr\\t%3,%1\"; | |
| 1667 | }" | |
| 1668 | [(set_attr "type" "call") | |
| 1669 | (set_attr "mode" "none")]) | |
| 1670 | ||
| 1671 | (define_expand "call_value_multiple_internal0" | |
| 1672 | [(parallel [(set (match_operand 0 "" "") | |
| 1673 | (call (match_operand 1 "" "") | |
| 1674 | (match_operand 2 "" ""))) | |
| 1675 | (set (match_operand 3 "" "") | |
| 1676 | (call (match_dup 1) | |
| 1677 | (match_dup 2))) | |
| 1678 | (clobber (match_operand:SI 4 "" ""))])] | |
| 1679 | "" | |
| 1680 | "") | |
| 1681 | ||
| 1682 | ;; ??? May eventually need all 6 versions of the call patterns with multiple | |
| 1683 | ;; return values. | |
| 1684 | ||
| 1685 | (define_insn "call_value_multiple_internal1" | |
| 679e8183 NF |
1686 | [(set (match_operand 0 "register_operand" "=d") |
| 1687 | (call (mem (match_operand 1 "call_insn_operand" "r")) | |
| 6b3d1e47 | 1688 | (match_operand 2 "" "i"))) |
| 679e8183 | 1689 | (set (match_operand 3 "register_operand" "=d") |
| 6b3d1e47 SC |
1690 | (call (mem (match_dup 1)) |
| 1691 | (match_dup 2))) | |
| 1692 | (clobber (match_operand:SI 4 "register_operand" "=d"))] | |
| 1693 | "" | |
| 1694 | "* | |
| 1695 | { | |
| 76898cec | 1696 | rtx target = operands[1]; |
| 6b3d1e47 SC |
1697 | |
| 1698 | if (GET_CODE (target) == CONST_INT) | |
| 1699 | return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\"; | |
| 1700 | else if (CONSTANT_ADDRESS_P (target)) | |
| 1701 | return \"jal\\t%1\"; | |
| 1702 | else | |
| 1703 | return \"jalr\\t%4,%1\"; | |
| 1704 | }" | |
| 1705 | [(set_attr "type" "call") | |
| 1706 | (set_attr "mode" "none")]) | |
| 1707 | ||
| 1708 | ;; Call subroutine returning any type. | |
| 1709 | ||
| 1710 | (define_expand "untyped_call" | |
| 1711 | [(parallel [(call (match_operand 0 "" "") | |
| 1712 | (const_int 0)) | |
| 1713 | (match_operand 1 "" "") | |
| 1714 | (match_operand 2 "" "")])] | |
| 1715 | "" | |
| 1716 | " | |
| 1717 | { | |
| 1718 | if (operands[0]) /* silence statement not reached warnings */ | |
| 1719 | { | |
| 1720 | int i; | |
| 1721 | ||
| 58d745ec | 1722 | emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); |
| 6b3d1e47 SC |
1723 | |
| 1724 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
| 1725 | { | |
| 1726 | rtx set = XVECEXP (operands[2], 0, i); | |
| 1727 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 1728 | } | |
| 1729 | ||
| 1730 | emit_insn (gen_blockage ()); | |
| 1731 | DONE; | |
| 1732 | } | |
| 1733 | }") | |
| 1734 | \f | |
| 1735 | ;; | |
| 1736 | ;; .................... | |
| 1737 | ;; | |
| 1738 | ;; MISC. | |
| 1739 | ;; | |
| 1740 | ;; .................... | |
| 1741 | ;; | |
| 1742 | ||
| 1743 | (define_insn "nop" | |
| 1744 | [(const_int 0)] | |
| 1745 | "" | |
| 1746 | "nop" | |
| 1747 | [(set_attr "type" "nop") | |
| 1748 | (set_attr "mode" "none")]) | |
| 1749 | ||
| 1750 | \f | |
| 1751 | ;; For the rare case where we need to load an address into a register | |
| 1e5f1716 | 1752 | ;; that cannot be recognized by the normal movsi/addsi instructions. |
| 6b3d1e47 SC |
1753 | ;; I have no idea how many insns this can actually generate. It should |
| 1754 | ;; be rare, so over-estimating as 10 instructions should not have any | |
| 1755 | ;; real performance impact. | |
| 1756 | (define_insn "leasi" | |
| 1757 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1758 | (match_operand:SI 1 "address_operand" "p"))] | |
| 1759 | "Pmode == SImode" | |
| 1760 | "* | |
| 1761 | { | |
| 1762 | rtx xoperands [3]; | |
| 1763 | ||
| 1764 | xoperands[0] = operands[0]; | |
| 1765 | xoperands[1] = XEXP (operands[1], 0); | |
| 1766 | xoperands[2] = XEXP (operands[1], 1); | |
| 1767 | output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands); | |
| 1768 | return \"\"; | |
| 1769 | }" | |
| 1770 | [(set_attr "type" "arith") | |
| 1771 | (set_attr "mode" "SI") | |
| 1772 | (set_attr "length" "40")]) | |
| 1773 | ||
| 1774 | (define_insn "ado16" | |
| 1775 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1776 | (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1777 | (match_operand:SI 2 "register_operand" "r")] | |
| 1778 | UNSPEC_ADO16))] | |
| 1779 | "" | |
| 1780 | "ado16\\t%0, %1, %2" | |
| 1781 | ) | |
| 1782 | ||
| 1783 | (define_insn "ram" | |
| 1784 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1785 | (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1786 | (match_operand:SI 2 "const_int_operand" "I") | |
| 1787 | (match_operand:SI 3 "const_int_operand" "I") | |
| 1788 | (match_operand:SI 4 "const_int_operand" "I")] | |
| 1789 | UNSPEC_RAM))] | |
| 1790 | "" | |
| 1791 | "ram\\t%0, %1, %2, %3, %4" | |
| 1792 | ) | |
| 1793 | ||
| 1794 | (define_insn "chkhdr" | |
| 1795 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r") | |
| 1796 | (match_operand:SI 1 "register_operand" "r")] | |
| 1797 | UNSPEC_CHKHDR)] | |
| 1798 | "" | |
| 1799 | "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);" | |
| 1800 | [(set_attr "dslot" "not_in_dslot")] | |
| 1801 | ) | |
| 1802 | ||
| 1803 | (define_insn "pkrl" | |
| 1804 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1805 | (match_operand:SI 1 "register_operand" "r")] | |
| 1806 | UNSPEC_PKRL)] | |
| 1807 | "" | |
| 1808 | "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1809 | [(set_attr "dslot" "not_in_dslot")] | |
| 1810 | ) | |
| 1811 | ||
| 1812 | (define_insn "cfc0" | |
| 1813 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1814 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1815 | UNSPEC_CFC0))] | |
| 1816 | "" | |
| 1817 | "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1818 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1819 | ) | |
| 1820 | ||
| 1821 | (define_insn "cfc1" | |
| 1822 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1823 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1824 | UNSPEC_CFC1))] | |
| 1825 | "" | |
| 1826 | "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1827 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1828 | ) | |
| 1829 | ||
| 1830 | (define_insn "cfc2" | |
| 1831 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1832 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1833 | UNSPEC_CFC2))] | |
| 1834 | "" | |
| 1835 | "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1836 | [(set_attr "dslot" "not_in_dslot")] | |
| 1837 | ) | |
| 1838 | ||
| 1839 | (define_insn "cfc3" | |
| 1840 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1841 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1842 | UNSPEC_CFC3))] | |
| 1843 | "" | |
| 1844 | "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1845 | [(set_attr "dslot" "not_in_dslot")] | |
| 1846 | ) | |
| 1847 | ||
| 1848 | (define_insn "ctc0" | |
| 1849 | [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1850 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1851 | UNSPEC_CTC0)] | |
| 1852 | "" | |
| 1853 | "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1854 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1855 | ) | |
| 1856 | ||
| 1857 | (define_insn "ctc1" | |
| 1858 | [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1859 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1860 | UNSPEC_CTC1)] | |
| 1861 | "" | |
| 1862 | "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1863 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1864 | ) | |
| 1865 | ||
| 1866 | (define_insn "ctc2" | |
| 1867 | [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1868 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1869 | UNSPEC_CTC2)] | |
| 1870 | "" | |
| 1871 | "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1872 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1873 | ) | |
| 1874 | ||
| 1875 | (define_insn "ctc3" | |
| 1876 | [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1877 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1878 | UNSPEC_CTC3)] | |
| 1879 | "" | |
| 1880 | "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1881 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1882 | ) | |
| 1883 | ||
| 1884 | (define_insn "mfc0" | |
| 1885 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1886 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1887 | UNSPEC_MFC0))] | |
| 1888 | "" | |
| 1889 | "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1890 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1891 | ) | |
| 1892 | ||
| 1893 | (define_insn "mfc1" | |
| 1894 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1895 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1896 | UNSPEC_MFC1))] | |
| 1897 | "" | |
| 1898 | "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1899 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1900 | ) | |
| 1901 | ||
| 1902 | (define_insn "mfc2" | |
| 1903 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1904 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1905 | UNSPEC_MFC2))] | |
| 1906 | "" | |
| 1907 | "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1908 | [(set_attr "dslot" "not_in_dslot")] | |
| 1909 | ) | |
| 1910 | ||
| 1911 | (define_insn "mfc3" | |
| 1912 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1913 | (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1914 | UNSPEC_MFC3))] | |
| 1915 | "" | |
| 1916 | "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1917 | [(set_attr "dslot" "not_in_dslot")] | |
| 1918 | ) | |
| 1919 | ||
| 1920 | (define_insn "mtc0" | |
| 1921 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1922 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1923 | UNSPEC_MTC0)] | |
| 1924 | "" | |
| 1925 | "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1926 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1927 | ) | |
| 1928 | ||
| 1929 | (define_insn "mtc1" | |
| 1930 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1931 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1932 | UNSPEC_MTC1)] | |
| 1933 | "" | |
| 1934 | "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1935 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1936 | ) | |
| 1937 | ||
| 1938 | (define_insn "mtc2" | |
| 1939 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1940 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1941 | UNSPEC_MTC2)] | |
| 1942 | "" | |
| 1943 | "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1944 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1945 | ) | |
| 1946 | ||
| 1947 | (define_insn "mtc3" | |
| 1948 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1949 | (match_operand:SI 1 "const_int_operand" "I")] | |
| 1950 | UNSPEC_MTC3)] | |
| 1951 | "" | |
| 1952 | "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1953 | [(set_attr "dslot" "ok_in_dslot")] | |
| 1954 | ) | |
| 1955 | ||
| 1956 | (define_insn "lur" | |
| 1957 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1958 | (match_operand:SI 1 "register_operand" "r")] | |
| 1959 | UNSPEC_LUR)] | |
| 1960 | "" | |
| 1961 | "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1962 | [(set_attr "dslot" "not_in_dslot")] | |
| 1963 | ) | |
| 1964 | ||
| 1965 | (define_insn "rb" | |
| 1966 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1967 | (match_operand:SI 1 "register_operand" "r")] | |
| 1968 | UNSPEC_RB)] | |
| 1969 | "" | |
| 1970 | "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1971 | [(set_attr "dslot" "not_in_dslot")] | |
| 1972 | ) | |
| 1973 | ||
| 1974 | (define_insn "rx" | |
| 1975 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1976 | (match_operand:SI 1 "register_operand" "r")] | |
| 1977 | UNSPEC_RX)] | |
| 1978 | "" | |
| 1979 | "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1980 | [(set_attr "dslot" "not_in_dslot")] | |
| 1981 | ) | |
| 1982 | ||
| 1983 | (define_insn "srrd" | |
| 1984 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 1985 | UNSPEC_SRRD)] | |
| 1986 | "" | |
| 1987 | "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);" | |
| 1988 | [(set_attr "dslot" "not_in_dslot")] | |
| 1989 | ) | |
| 1990 | ||
| 1991 | (define_insn "srwr" | |
| 1992 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1993 | (match_operand:SI 1 "register_operand" "r")] | |
| 1994 | UNSPEC_SRWR)] | |
| 1995 | "" | |
| 1996 | "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1997 | [(set_attr "dslot" "not_in_dslot")] | |
| 1998 | ) | |
| 1999 | ||
| 2000 | (define_insn "wb" | |
| 2001 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2002 | (match_operand:SI 1 "register_operand" "r")] | |
| 2003 | UNSPEC_WB)] | |
| 2004 | "" | |
| 2005 | "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2006 | [(set_attr "dslot" "not_in_dslot")] | |
| 2007 | ) | |
| 2008 | ||
| 2009 | (define_insn "wx" | |
| 2010 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2011 | (match_operand:SI 1 "register_operand" "r")] | |
| 2012 | UNSPEC_WX)] | |
| 2013 | "" | |
| 2014 | "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2015 | [(set_attr "dslot" "not_in_dslot")] | |
| 2016 | ) | |
| 2017 | ||
| 2018 | (define_insn "luc32" | |
| 2019 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2020 | (match_operand:SI 1 "register_operand" "r")] | |
| 2021 | UNSPEC_LUC32)] | |
| 2022 | "" | |
| 2023 | "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2024 | [(set_attr "dslot" "not_in_dslot")] | |
| 2025 | ) | |
| 2026 | ||
| 2027 | (define_insn "luc32l" | |
| 2028 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2029 | (match_operand:SI 1 "register_operand" "r")] | |
| 2030 | UNSPEC_LUC32L)] | |
| 2031 | "" | |
| 2032 | "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2033 | [(set_attr "dslot" "not_in_dslot")] | |
| 2034 | ) | |
| 2035 | ||
| 2036 | (define_insn "luc64" | |
| 2037 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2038 | (match_operand:SI 1 "register_operand" "r")] | |
| 2039 | UNSPEC_LUC64)] | |
| 2040 | "" | |
| 2041 | "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2042 | [(set_attr "dslot" "not_in_dslot")] | |
| 2043 | ) | |
| 2044 | ||
| 2045 | (define_insn "luc64l" | |
| 2046 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2047 | (match_operand:SI 1 "register_operand" "r")] | |
| 2048 | UNSPEC_LUC64L)] | |
| 2049 | "" | |
| 2050 | "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2051 | [(set_attr "dslot" "not_in_dslot")] | |
| 2052 | ) | |
| 2053 | ||
| 2054 | (define_insn "luk" | |
| 2055 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2056 | (match_operand:SI 1 "register_operand" "r")] | |
| 2057 | UNSPEC_LUK)] | |
| 2058 | "" | |
| 2059 | "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2060 | [(set_attr "dslot" "ok_in_dslot")] | |
| 2061 | ) | |
| 2062 | ||
| 2063 | (define_insn "lulck" | |
| 2064 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2065 | UNSPEC_LULCK)] | |
| 2066 | "" | |
| 2067 | "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2068 | [(set_attr "dslot" "not_in_dslot")] | |
| 2069 | ) | |
| 2070 | ||
| 2071 | (define_insn "lum32" | |
| 2072 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2073 | (match_operand:SI 1 "register_operand" "r")] | |
| 2074 | UNSPEC_LUM32)] | |
| 2075 | "" | |
| 2076 | "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2077 | [(set_attr "dslot" "not_in_dslot")] | |
| 2078 | ) | |
| 2079 | ||
| 2080 | (define_insn "lum32l" | |
| 2081 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2082 | (match_operand:SI 1 "register_operand" "r")] | |
| 2083 | UNSPEC_LUM32L)] | |
| 2084 | "" | |
| 2085 | "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2086 | [(set_attr "dslot" "not_in_dslot")] | |
| 2087 | ) | |
| 2088 | ||
| 2089 | (define_insn "lum64" | |
| 2090 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2091 | (match_operand:SI 1 "register_operand" "r")] | |
| 2092 | UNSPEC_LUM64)] | |
| 2093 | "" | |
| 2094 | "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2095 | [(set_attr "dslot" "not_in_dslot")] | |
| 2096 | ) | |
| 2097 | ||
| 2098 | (define_insn "lum64l" | |
| 2099 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2100 | (match_operand:SI 1 "register_operand" "r")] | |
| 2101 | UNSPEC_LUM64L)] | |
| 2102 | "" | |
| 2103 | "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2104 | [(set_attr "dslot" "not_in_dslot")] | |
| 2105 | ) | |
| 2106 | ||
| 2107 | (define_insn "lurl" | |
| 2108 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2109 | (match_operand:SI 1 "register_operand" "r")] | |
| 2110 | UNSPEC_LURL)] | |
| 2111 | "" | |
| 2112 | "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2113 | [(set_attr "dslot" "not_in_dslot")] | |
| 2114 | ) | |
| 2115 | ||
| 2116 | (define_insn "mrgb" | |
| 2117 | [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2118 | (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") | |
| 2119 | (match_operand:SI 2 "register_operand" "r") | |
| 2120 | (match_operand:SI 3 "const_int_operand" "I")] | |
| 2121 | UNSPEC_MRGB))] | |
| 2122 | "" | |
| 2123 | "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);" | |
| 2124 | [(set_attr "dslot" "ok_in_dslot")] | |
| 2125 | ) | |
| 2126 | ||
| 2127 | (define_insn "srrdl" | |
| 2128 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2129 | UNSPEC_SRRDL)] | |
| 2130 | "" | |
| 2131 | "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);" | |
| 2132 | [(set_attr "dslot" "not_in_dslot")] | |
| 2133 | ) | |
| 2134 | ||
| 2135 | (define_insn "srulck" | |
| 2136 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2137 | UNSPEC_SRULCK)] | |
| 2138 | "" | |
| 2139 | "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2140 | [(set_attr "dslot" "not_in_dslot")] | |
| 2141 | ) | |
| 2142 | ||
| 2143 | (define_insn "srwru" | |
| 2144 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2145 | (match_operand:SI 1 "register_operand" "r")] | |
| 2146 | UNSPEC_SRWRU)] | |
| 2147 | "" | |
| 2148 | "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2149 | [(set_attr "dslot" "not_in_dslot")] | |
| 2150 | ) | |
| 2151 | ||
| 2152 | (define_insn "trapqfl" | |
| 2153 | [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)] | |
| 2154 | "" | |
| 2155 | "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);" | |
| 2156 | [(set_attr "dslot" "not_in_dslot")] | |
| 2157 | ) | |
| 2158 | ||
| 2159 | (define_insn "trapqne" | |
| 2160 | [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)] | |
| 2161 | "" | |
| 2162 | "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);" | |
| 2163 | [(set_attr "dslot" "not_in_dslot")] | |
| 2164 | ) | |
| 2165 | ||
| 2166 | (define_insn "traprel" | |
| 2167 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2168 | UNSPEC_TRAPREL)] | |
| 2169 | "" | |
| 2170 | "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);" | |
| 2171 | [(set_attr "dslot" "not_in_dslot")] | |
| 2172 | ) | |
| 2173 | ||
| 2174 | (define_insn "wbu" | |
| 2175 | [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2176 | (match_operand:SI 1 "register_operand" "r")] | |
| 2177 | UNSPEC_WBU)] | |
| 2178 | "" | |
| 2179 | "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2180 | [(set_attr "dslot" "not_in_dslot")] | |
| 2181 | ) | |
| 2182 | ||
| 2183 | (define_insn "syscall" | |
| 2184 | [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)] | |
| 2185 | "" | |
| 2186 | "syscall" | |
| 2187 | [(set_attr "dslot" "not_in_dslot")] | |
| 2188 | ) |