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54f12d76 1;; iq2000.md Machine Description for Vitesse IQ2000 processors
fbd26352 2;; Copyright (C) 2003-2019 Free Software Foundation, Inc.
54f12d76 3
5c1d8983 4;; This file is part of GCC.
54f12d76 5
5c1d8983 6;; GCC is free software; you can redistribute it and/or modify
54f12d76 7;; it under the terms of the GNU General Public License as published by
038d1e19 8;; the Free Software Foundation; either version 3, or (at your option)
54f12d76 9;; any later version.
10
5c1d8983 11;; GCC is distributed in the hope that it will be useful,
54f12d76 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14;; GNU General Public License for more details.
15
16;; You should have received a copy of the GNU General Public License
038d1e19 17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
54f12d76 19
54f12d76 20(define_constants
21 [(UNSPEC_ADO16 0)
22 (UNSPEC_RAM 1)
23 (UNSPEC_CHKHDR 2)
24 (UNSPEC_PKRL 3)
25 (UNSPEC_CFC0 4)
26 (UNSPEC_CFC1 5)
27 (UNSPEC_CFC2 6)
28 (UNSPEC_CFC3 7)
29 (UNSPEC_CTC0 8)
30 (UNSPEC_CTC1 9)
31 (UNSPEC_CTC2 10)
32 (UNSPEC_CTC3 11)
33 (UNSPEC_MFC0 12)
34 (UNSPEC_MFC1 13)
35 (UNSPEC_MFC2 14)
36 (UNSPEC_MFC3 15)
37 (UNSPEC_MTC0 16)
38 (UNSPEC_MTC1 17)
39 (UNSPEC_MTC2 18)
40 (UNSPEC_MTC3 19)
41 (UNSPEC_LUR 20)
42 (UNSPEC_RB 21)
43 (UNSPEC_RX 22)
44 (UNSPEC_SRRD 23)
45 (UNSPEC_SRWR 24)
46 (UNSPEC_WB 25)
47 (UNSPEC_WX 26)
48 (UNSPEC_LUC32 49)
49 (UNSPEC_LUC32L 27)
50 (UNSPEC_LUC64 28)
51 (UNSPEC_LUC64L 29)
52 (UNSPEC_LUK 30)
53 (UNSPEC_LULCK 31)
54 (UNSPEC_LUM32 32)
55 (UNSPEC_LUM32L 33)
56 (UNSPEC_LUM64 34)
57 (UNSPEC_LUM64L 35)
58 (UNSPEC_LURL 36)
59 (UNSPEC_MRGB 37)
60 (UNSPEC_SRRDL 38)
61 (UNSPEC_SRULCK 39)
62 (UNSPEC_SRWRU 40)
63 (UNSPEC_TRAPQFL 41)
64 (UNSPEC_TRAPQNE 42)
65 (UNSPEC_TRAPREL 43)
66 (UNSPEC_WBU 44)
67 (UNSPEC_SYSCALL 45)]
68)
69;; UNSPEC values used in iq2000.md
70;; Number USE
71;; 0 movsi_ul
72;; 1 movsi_us, get_fnaddr
73;; 3 eh_set_return
74;; 20 builtin_setjmp_setup
75;;
76;; UNSPEC_VOLATILE values
77;; 0 blockage
78;; 2 loadgp
79;; 3 builtin_longjmp
80;; 4 exception_receiver
81;; 10 consttable_qi
82;; 11 consttable_hi
83;; 12 consttable_si
84;; 13 consttable_di
85;; 14 consttable_sf
86;; 15 consttable_df
87;; 16 align_2
88;; 17 align_4
89;; 18 align_8
90\f
91
92;; ....................
93;;
94;; Attributes
95;;
96;; ....................
97
98;; Classification of each insn.
99;; branch conditional branch
100;; jump unconditional jump
101;; call unconditional call
102;; load load instruction(s)
103;; store store instruction(s)
104;; move data movement within same register set
105;; xfer transfer to/from coprocessor
106;; arith integer arithmetic instruction
107;; darith double precision integer arithmetic instructions
108;; imul integer multiply
109;; idiv integer divide
110;; icmp integer compare
111;; fadd floating point add/subtract
112;; fmul floating point multiply
113;; fmadd floating point multiply-add
114;; fdiv floating point divide
115;; fabs floating point absolute value
116;; fneg floating point negation
117;; fcmp floating point compare
118;; fcvt floating point convert
119;; fsqrt floating point square root
120;; multi multiword sequence (or user asm statements)
121;; nop no operation
122
123(define_attr "type"
124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
125 (const_string "unknown"))
126
127;; Main data type used by the insn
128(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
129
130;; Length (in # of bytes). A conditional branch is allowed only to a
131;; location within a signed 18-bit offset of the delay slot. If that
132;; provides too small a range, we use the `j' instruction. This
133;; instruction takes a 28-bit value, but that value is not an offset.
134;; Instead, it's bitwise-ored with the high-order four bits of the
135;; instruction in the delay slot, which means it cannot be used to
47ae02b7 136;; cross a 256MB boundary. We could fall back on the jr
54f12d76 137;; instruction which allows full access to the entire address space,
138;; but we do not do so at present.
139
140(define_attr "length" ""
141 (cond [(eq_attr "type" "branch")
142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
143 (const_int 131072))
144 (const_int 4)]
145 (const_int 12))]
146 (const_int 4)))
147
148(define_attr "cpu"
149 "default,iq2000"
150 (const (symbol_ref "iq2000_cpu_attr")))
151
152;; Does the instruction have a mandatory delay slot? has_dslot
153;; Can the instruction be in a delay slot? ok_in_dslot
154;; Can the instruction not be in a delay slot? not_in_dslot
155(define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
157 (const_string "has_dslot")
158 (const_string "ok_in_dslot")))
159
160;; Attribute defining whether or not we can use the branch-likely instructions
161
162(define_attr "branch_likely" "no,yes"
163 (const
a7299290 164 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
54f12d76 165 (const_string "yes")
166 (const_string "no"))))
167
168
169;; Describe a user's asm statement.
170(define_asm_attributes
171 [(set_attr "type" "multi")])
172
173\f
174
175;; .........................
176;;
177;; Delay slots, can't describe load/fcmp/xfer delay slots here
178;;
179;; .........................
180
181(define_delay (eq_attr "type" "jump")
182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
183 (nil)
184 (nil)])
185
186(define_delay (eq_attr "type" "branch")
187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
188 (nil)
189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
190
191(define_delay (eq_attr "type" "call")
192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
193 (nil)
194 (nil)])
195
94c41a53 196(include "predicates.md")
8ba7ed0c 197(include "constraints.md")
54f12d76 198\f
199
200;; .........................
201;;
49321da4 202;; Pipeline model
54f12d76 203;;
204;; .........................
205
49321da4 206(define_automaton "iq2000")
207(define_cpu_unit "core,memory" "iq2000")
54f12d76 208
49321da4 209(define_insn_reservation "nonmemory" 1
210 (eq_attr "type" "!load,move,store,xfer")
211 "core")
54f12d76 212
49321da4 213(define_insn_reservation "iq2000_load_move" 3
214 (and (eq_attr "type" "load,move")
54f12d76 215 (eq_attr "cpu" "iq2000"))
49321da4 216 "memory")
54f12d76 217
49321da4 218(define_insn_reservation "other_load_move" 1
219 (and (eq_attr "type" "load,move")
220 (eq_attr "cpu" "!iq2000"))
221 "memory")
54f12d76 222
49321da4 223(define_insn_reservation "store" 1
224 (eq_attr "type" "store")
225 "memory")
54f12d76 226
49321da4 227(define_insn_reservation "xfer" 2
228 (eq_attr "type" "xfer")
229 "memory")
54f12d76 230\f
231;;
232;; ....................
233;;
234;; CONDITIONAL TRAPS
235;;
236;; ....................
237;;
238
239(define_insn "trap"
240 [(trap_if (const_int 1) (const_int 0))]
241 ""
242 "*
243{
244 return \"break\";
245}")
246\f
247;;
248;; ....................
249;;
250;; ADDITION
251;;
252;; ....................
253;;
254
255(define_expand "addsi3"
256 [(set (match_operand:SI 0 "register_operand" "=d")
257 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
258 (match_operand:SI 2 "arith_operand" "dI")))]
259 ""
260 "")
261
262(define_insn "addsi3_internal"
205c3b0a 263 [(set (match_operand:SI 0 "register_operand" "=d,d")
54f12d76 264 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
265 (match_operand:SI 2 "arith_operand" "d,I")))]
266 ""
267 "@
268 addu\\t%0,%z1,%2
269 addiu\\t%0,%z1,%2"
270 [(set_attr "type" "arith")
271 (set_attr "mode" "SI")])
272\f
273;;
274;; ....................
275;;
276;; SUBTRACTION
277;;
278;; ....................
279;;
280
281(define_expand "subsi3"
282 [(set (match_operand:SI 0 "register_operand" "=d")
283 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
284 (match_operand:SI 2 "arith_operand" "dI")))]
285 ""
286 "")
287
288(define_insn "subsi3_internal"
205c3b0a 289 [(set (match_operand:SI 0 "register_operand" "=d,d")
54f12d76 290 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
291 (match_operand:SI 2 "arith_operand" "d,I")))]
292 ""
293 "@
294 subu\\t%0,%z1,%2
295 addiu\\t%0,%z1,%n2"
296 [(set_attr "type" "arith")
297 (set_attr "mode" "SI")])
298\f
299;;
300;; ....................
301;;
302;; NEGATION and ONE'S COMPLEMENT
303;;
304;; ....................
305
306(define_insn "negsi2"
307 [(set (match_operand:SI 0 "register_operand" "=d")
308 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
309 ""
310 "*
311{
312 operands[2] = const0_rtx;
313 return \"subu\\t%0,%z2,%1\";
314}"
315 [(set_attr "type" "arith")
316 (set_attr "mode" "SI")])
317
318(define_insn "one_cmplsi2"
319 [(set (match_operand:SI 0 "register_operand" "=d")
320 (not:SI (match_operand:SI 1 "register_operand" "d")))]
321 ""
322 "*
323{
324 operands[2] = const0_rtx;
325 return \"nor\\t%0,%z2,%1\";
326}"
327 [(set_attr "type" "arith")
328 (set_attr "mode" "SI")])
329\f
330;;
331;; ....................
332;;
333;; LOGICAL
334;;
335;; ....................
336;;
337
338(define_expand "andsi3"
339 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
340 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
341 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
342 ""
343 "")
344
345(define_insn ""
346 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
347 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
348 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
349 ""
350 "*
351{
352 if (which_alternative == 0)
353 return \"and\\t%0,%1,%2\";
354 else if (which_alternative == 1)
355 return \"andi\\t%0,%1,%x2\";
356 else if (which_alternative == 2)
357 {
358 if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
359 {
360 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
361 return \"andoui\\t%0,%1,%x2\";
362 }
363 else
364 {
365 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
366 return \"andoi\\t%0,%1,%x2\";
367 }
368 }
cfa41c37 369 else
370 gcc_unreachable ();
54f12d76 371}"
372 [(set_attr "type" "arith")
373 (set_attr "mode" "SI")])
374
375(define_expand "iorsi3"
376 [(set (match_operand:SI 0 "register_operand" "=d,d")
377 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
378 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
379 ""
380 "")
381
382(define_insn ""
383 [(set (match_operand:SI 0 "register_operand" "=d,d")
384 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
385 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
386 ""
387 "@
388 or\\t%0,%1,%2
389 ori\\t%0,%1,%x2"
390 [(set_attr "type" "arith")
391 (set_attr "mode" "SI")])
392
393(define_expand "xorsi3"
394 [(set (match_operand:SI 0 "register_operand" "=d,d")
395 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
396 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
397 ""
398 "")
399
400(define_insn ""
401 [(set (match_operand:SI 0 "register_operand" "=d,d")
402 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
403 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
404 ""
405 "@
406 xor\\t%0,%1,%2
407 xori\\t%0,%1,%x2"
408 [(set_attr "type" "arith")
409 (set_attr "mode" "SI")])
410
411(define_insn "*norsi3"
412 [(set (match_operand:SI 0 "register_operand" "=d")
413 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
414 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
415 ""
416 "nor\\t%0,%z1,%z2"
417 [(set_attr "type" "arith")
418 (set_attr "mode" "SI")])
419\f
420;;
421;; ....................
422;;
423;; ZERO EXTENSION
424;;
425;; ....................
426
427;; Extension insns.
428;; Those for integer source operand are ordered widest source type first.
429
430(define_expand "zero_extendhisi2"
431 [(set (match_operand:SI 0 "register_operand" "")
432 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
433 ""
434 "")
435
436(define_insn ""
437 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
438 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
439 ""
440 "*
441{
442 if (which_alternative == 0)
443 return \"andi\\t%0,%1,0xffff\";
444 else
445 return iq2000_move_1word (operands, insn, TRUE);
446}"
447 [(set_attr "type" "arith,load,load")
448 (set_attr "mode" "SI")
449 (set_attr "length" "4,4,8")])
450
451(define_expand "zero_extendqihi2"
452 [(set (match_operand:HI 0 "register_operand" "")
453 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
454 ""
455 "")
456
457(define_insn ""
458 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
459 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
460 ""
461 "*
462{
463 if (which_alternative == 0)
464 return \"andi\\t%0,%1,0x00ff\";
465 else
466 return iq2000_move_1word (operands, insn, TRUE);
467}"
468 [(set_attr "type" "arith,load,load")
469 (set_attr "mode" "HI")
470 (set_attr "length" "4,4,8")])
471
472(define_expand "zero_extendqisi2"
473 [(set (match_operand:SI 0 "register_operand" "")
474 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
475 ""
476 "")
477
478(define_insn ""
479 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
480 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
481 ""
482 "*
483{
484 if (which_alternative == 0)
485 return \"andi\\t%0,%1,0x00ff\";
486 else
487 return iq2000_move_1word (operands, insn, TRUE);
488}"
489 [(set_attr "type" "arith,load,load")
490 (set_attr "mode" "SI")
491 (set_attr "length" "4,4,8")])
492
493;;
494;; ....................
495;;
496;; SIGN EXTENSION
497;;
498;; ....................
499
500;; Extension insns.
501;; Those for integer source operand are ordered widest source type first.
502
503;; These patterns originally accepted general_operands, however, slightly
504;; better code is generated by only accepting register_operands, and then
505;; letting combine generate the lh and lb insns.
506
507(define_expand "extendhisi2"
508 [(set (match_operand:SI 0 "register_operand" "")
509 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
510 ""
511 "
512{
513 if (optimize && GET_CODE (operands[1]) == MEM)
514 operands[1] = force_not_mem (operands[1]);
515
516 if (GET_CODE (operands[1]) != MEM)
517 {
518 rtx op1 = gen_lowpart (SImode, operands[1]);
519 rtx temp = gen_reg_rtx (SImode);
520 rtx shift = GEN_INT (16);
521
522 emit_insn (gen_ashlsi3 (temp, op1, shift));
523 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
524 DONE;
525 }
526}")
527
528(define_insn "extendhisi2_internal"
529 [(set (match_operand:SI 0 "register_operand" "=d,d")
530 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
531 ""
532 "* return iq2000_move_1word (operands, insn, FALSE);"
533 [(set_attr "type" "load")
534 (set_attr "mode" "SI")
535 (set_attr "length" "4,8")])
536
537(define_expand "extendqihi2"
538 [(set (match_operand:HI 0 "register_operand" "")
539 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
540 ""
541 "
542{
543 if (optimize && GET_CODE (operands[1]) == MEM)
544 operands[1] = force_not_mem (operands[1]);
545
546 if (GET_CODE (operands[1]) != MEM)
547 {
548 rtx op0 = gen_lowpart (SImode, operands[0]);
549 rtx op1 = gen_lowpart (SImode, operands[1]);
550 rtx temp = gen_reg_rtx (SImode);
551 rtx shift = GEN_INT (24);
552
553 emit_insn (gen_ashlsi3 (temp, op1, shift));
554 emit_insn (gen_ashrsi3 (op0, temp, shift));
555 DONE;
556 }
557}")
558
559(define_insn "extendqihi2_internal"
560 [(set (match_operand:HI 0 "register_operand" "=d,d")
561 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
562 ""
563 "* return iq2000_move_1word (operands, insn, FALSE);"
564 [(set_attr "type" "load")
565 (set_attr "mode" "SI")
566 (set_attr "length" "4,8")])
567
568
569(define_expand "extendqisi2"
570 [(set (match_operand:SI 0 "register_operand" "")
571 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
572 ""
573 "
574{
575 if (optimize && GET_CODE (operands[1]) == MEM)
576 operands[1] = force_not_mem (operands[1]);
577
578 if (GET_CODE (operands[1]) != MEM)
579 {
580 rtx op1 = gen_lowpart (SImode, operands[1]);
581 rtx temp = gen_reg_rtx (SImode);
582 rtx shift = GEN_INT (24);
583
584 emit_insn (gen_ashlsi3 (temp, op1, shift));
585 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
586 DONE;
587 }
588}")
589
590(define_insn "extendqisi2_insn"
591 [(set (match_operand:SI 0 "register_operand" "=d,d")
592 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
593 ""
594 "* return iq2000_move_1word (operands, insn, FALSE);"
595 [(set_attr "type" "load")
596 (set_attr "mode" "SI")
597 (set_attr "length" "4,8")])
598\f
599;;
600;; ........................
601;;
602;; BIT FIELD EXTRACTION
603;;
604;; ........................
605
606(define_insn "extzv"
607 [(set (match_operand:SI 0 "register_operand" "=r")
608 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
609 (match_operand:SI 2 "const_int_operand" "O")
610 (match_operand:SI 3 "const_int_operand" "O")))]
611 ""
612 "*
613{
614 int value[4];
615 value[2] = INTVAL (operands[2]);
616 value[3] = INTVAL (operands[3]);
617 operands[2] = GEN_INT ((value[3]));
618 operands[3] = GEN_INT ((32 - value[2]));
619 return \"ram\\t%0,%1,%2,%3,0x0\";
620}"
621 [(set_attr "type" "arith")])
622\f
623;;
624;; ....................
625;;
626;; DATA MOVEMENT
627;;
628;; ....................
629
630/* Take care of constants that don't fit in single instruction */
631(define_split
632 [(set (match_operand:SI 0 "register_operand" "")
633 (match_operand:SI 1 "general_operand" ""))]
634 "(reload_in_progress || reload_completed)
635 && large_int (operands[1], SImode)"
636
637 [(set (match_dup 0 )
638 (high:SI (match_dup 1)))
639 (set (match_dup 0 )
640 (lo_sum:SI (match_dup 0)
641 (match_dup 1)))]
642)
643
644;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
645;; unnecessary.
646
647(define_insn "high"
648 [(set (match_operand:SI 0 "register_operand" "=r")
649 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
650 ""
651 "lui\\t%0,%%hi(%1) # high"
652 [(set_attr "type" "move")])
653
654(define_insn "low"
655 [(set (match_operand:SI 0 "register_operand" "=r")
656 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
657 (match_operand:SI 2 "immediate_operand" "")))]
658 ""
659 "addiu\\t%0,%1,%%lo(%2) # low"
660 [(set_attr "type" "arith")
661 (set_attr "mode" "SI")])
662
663;; 32-bit Integer moves
664
665(define_split
666 [(set (match_operand:SI 0 "register_operand" "")
667 (match_operand:SI 1 "large_int" ""))]
668 "reload_in_progress | reload_completed"
669 [(set (match_dup 0)
670 (match_dup 2))
671 (set (match_dup 0)
672 (ior:SI (match_dup 0)
673 (match_dup 3)))]
674 "
675{
676 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
677 & BITMASK_UPPER16,
678 SImode));
679 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
680}")
681
682;; Unlike most other insns, the move insns can't be split with
683;; different predicates, because register spilling and other parts of
684;; the compiler, have memoized the insn number already.
685
686(define_expand "movsi"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
688 (match_operand:SI 1 "general_operand" ""))]
689 ""
690 "
691{
692 if (iq2000_check_split (operands[1], SImode))
693 {
3754d046 694 machine_mode mode = GET_MODE (operands[0]);
54f12d76 695 rtx tem = ((reload_in_progress | reload_completed)
696 ? operands[0] : gen_reg_rtx (mode));
697
d1f9b275 698 emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (mode, operands[1])));
54f12d76 699
700 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
701 }
702
703 if ((reload_in_progress | reload_completed) == 0
704 && !register_operand (operands[0], SImode)
705 && !register_operand (operands[1], SImode)
706 && (GET_CODE (operands[1]) != CONST_INT
707 || INTVAL (operands[1]) != 0))
708 {
709 rtx temp = force_reg (SImode, operands[1]);
710 emit_move_insn (operands[0], temp);
711 DONE;
712 }
713
714 /* Take care of constants that don't fit in single instruction */
715 if ((reload_in_progress || reload_completed)
716 && CONSTANT_P (operands[1])
717 && GET_CODE (operands[1]) != HIGH
718 && GET_CODE (operands[1]) != LO_SUM
719 && ! SMALL_INT_UNSIGNED (operands[1]))
720 {
721 rtx tem = ((reload_in_progress | reload_completed)
722 ? operands[0] : gen_reg_rtx (SImode));
723
d1f9b275 724 emit_insn (gen_rtx_SET (tem, gen_rtx_HIGH (SImode, operands[1])));
54f12d76 725 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
726 }
727}")
728
729;; The difference between these two is whether or not ints are allowed
730;; in FP registers (off by default, use -mdebugh to enable).
731
732(define_insn "movsi_internal2"
8ba7ed0c 733 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m")
734 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
54f12d76 735 "(register_operand (operands[0], SImode)
736 || register_operand (operands[1], SImode)
737 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
738 "* return iq2000_move_1word (operands, insn, FALSE);"
8ba7ed0c 739 [(set_attr "type" "move,arith,arith,load,load,store,store")
54f12d76 740 (set_attr "mode" "SI")
8ba7ed0c 741 (set_attr "length" "4,4,8,8,8,4,8")])
54f12d76 742
743;; 16-bit Integer moves
744
745;; Unlike most other insns, the move insns can't be split with
746;; different predicates, because register spilling and other parts of
747;; the compiler, have memoized the insn number already.
748;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
749
750(define_expand "movhi"
751 [(set (match_operand:HI 0 "nonimmediate_operand" "")
752 (match_operand:HI 1 "general_operand" ""))]
753 ""
754 "
755{
756 if ((reload_in_progress | reload_completed) == 0
757 && !register_operand (operands[0], HImode)
758 && !register_operand (operands[1], HImode)
759 && ((GET_CODE (operands[1]) != CONST_INT
760 || INTVAL (operands[1]) != 0)))
761 {
762 rtx temp = force_reg (HImode, operands[1]);
763 emit_move_insn (operands[0], temp);
764 DONE;
765 }
766}")
767
768;; The difference between these two is whether or not ints are allowed
769;; in FP registers (off by default, use -mdebugh to enable).
770
771(define_insn "movhi_internal2"
8ba7ed0c 772 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
773 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
54f12d76 774 "(register_operand (operands[0], HImode)
775 || register_operand (operands[1], HImode)
776 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
777 "* return iq2000_move_1word (operands, insn, TRUE);"
8ba7ed0c 778 [(set_attr "type" "move,arith,load,load,store,store")
54f12d76 779 (set_attr "mode" "HI")
8ba7ed0c 780 (set_attr "length" "4,4,4,8,4,8")])
54f12d76 781
782;; 8-bit Integer moves
783
784;; Unlike most other insns, the move insns can't be split with
785;; different predicates, because register spilling and other parts of
786;; the compiler, have memoized the insn number already.
787;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
788
789(define_expand "movqi"
790 [(set (match_operand:QI 0 "nonimmediate_operand" "")
791 (match_operand:QI 1 "general_operand" ""))]
792 ""
793 "
794{
795 if ((reload_in_progress | reload_completed) == 0
796 && !register_operand (operands[0], QImode)
797 && !register_operand (operands[1], QImode)
798 && (GET_CODE (operands[1]) != CONST_INT
799 || INTVAL (operands[1]) != 0))
800 {
801 rtx temp = force_reg (QImode, operands[1]);
802 emit_move_insn (operands[0], temp);
803 DONE;
804 }
805}")
806
807;; The difference between these two is whether or not ints are allowed
808;; in FP registers (off by default, use -mdebugh to enable).
809
810(define_insn "movqi_internal2"
8ba7ed0c 811 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
812 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
54f12d76 813 "(register_operand (operands[0], QImode)
814 || register_operand (operands[1], QImode)
815 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
816 "* return iq2000_move_1word (operands, insn, TRUE);"
8ba7ed0c 817 [(set_attr "type" "move,arith,load,load,store,store")
54f12d76 818 (set_attr "mode" "QI")
8ba7ed0c 819 (set_attr "length" "4,4,4,8,4,8")])
54f12d76 820
821;; 32-bit floating point moves
822
823(define_expand "movsf"
824 [(set (match_operand:SF 0 "general_operand" "")
825 (match_operand:SF 1 "general_operand" ""))]
826 ""
827 "
828{
829 if (!reload_in_progress
830 && !reload_completed
831 && GET_CODE (operands[0]) == MEM
832 && (GET_CODE (operands[1]) == MEM
833 || GET_CODE (operands[1]) == CONST_DOUBLE))
834 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
835
836 /* Take care of reg <- SF constant */
837 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
838 {
839 emit_insn (gen_movsf_high (operands[0], operands[1]));
840 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
841 DONE;
842 }
843}")
844
845(define_insn "movsf_lo_sum"
846 [(set (match_operand:SF 0 "register_operand" "=r")
847 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
848 (match_operand:SF 2 "const_double_operand" "")))]
849 ""
850 "*
851{
54f12d76 852 long i;
853
945f7b03 854 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[2]), i);
54f12d76 855 operands[2] = GEN_INT (i);
856 return \"addiu\\t%0,%1,%%lo(%2) # low\";
857}"
858 [(set_attr "length" "4")
859 (set_attr "type" "arith")])
860
861(define_insn "movsf_high"
862 [(set (match_operand:SF 0 "register_operand" "=r")
863 (high:SF (match_operand:SF 1 "const_double_operand" "")))]
864 ""
865 "*
866{
54f12d76 867 long i;
868
945f7b03 869 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), i);
54f12d76 870 operands[1] = GEN_INT (i);
871 return \"lui\\t%0,%%hi(%1) # high\";
872}"
873 [(set_attr "length" "4")
874 (set_attr "type" "arith")])
875
876(define_insn "*movsf_internal"
877 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
878 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
879 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
880 "*
881{
882 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
883 if (which_alternative == 0)
884 return \"or\\t%0,%1,%1\";
885 else if (which_alternative == 1)
886 return \"lw\\t%0,%1\";
887 else if (which_alternative == 2)
888 return \"sw\\t%1,%0\";
cfa41c37 889 else
890 gcc_unreachable ();
54f12d76 891}"
892 [(set_attr "length" "4,4,4")
893 (set_attr "type" "arith,load,store")]
894)
895\f
896;;
897;; ....................
898;;
899;; SHIFTS
900;;
901;; ....................
902
903(define_expand "ashlsi3"
904 [(set (match_operand:SI 0 "register_operand" "=d")
905 (ashift:SI (match_operand:SI 1 "register_operand" "d")
906 (match_operand:SI 2 "arith_operand" "dI")))]
907 ""
908 "")
909
910(define_insn "ashlsi3_internal1"
911 [(set (match_operand:SI 0 "register_operand" "=d")
912 (ashift:SI (match_operand:SI 1 "register_operand" "d")
913 (match_operand:SI 2 "arith_operand" "dI")))]
914 ""
915 "*
916{
917 if (GET_CODE (operands[2]) == CONST_INT)
918 {
919 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
920 return \"sll\\t%0,%1,%2\";
921 }
922 else
923 return \"sllv\\t%0,%1,%2\";
924}"
925 [(set_attr "type" "arith")
926 (set_attr "mode" "SI")])
927
928(define_expand "ashrsi3"
929 [(set (match_operand:SI 0 "register_operand" "=d")
930 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
931 (match_operand:SI 2 "arith_operand" "dI")))]
932 ""
933 "")
934
935(define_insn "ashrsi3_internal1"
936 [(set (match_operand:SI 0 "register_operand" "=d")
937 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
938 (match_operand:SI 2 "arith_operand" "dI")))]
939 ""
940 "*
941{
942 if (GET_CODE (operands[2]) == CONST_INT)
943 {
944 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
945 return \"sra\\t%0,%1,%2\";
946 }
947 else
948 return \"srav\\t%0,%1,%2\";
949}"
950 [(set_attr "type" "arith")
951 (set_attr "mode" "SI")])
952
953(define_expand "lshrsi3"
954 [(set (match_operand:SI 0 "register_operand" "=d")
955 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
956 (match_operand:SI 2 "arith_operand" "dI")))]
957 ""
958 "")
959
960(define_insn "lshrsi3_internal1"
961 [(set (match_operand:SI 0 "register_operand" "=d")
962 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
963 (match_operand:SI 2 "arith_operand" "dI")))]
964 ""
965 "*
966{
967 if (GET_CODE (operands[2]) == CONST_INT)
968 {
969 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
970 return \"srl\\t%0,%1,%2\";
971 }
972 else
973 return \"srlv\\t%0,%1,%2\";
974}"
975 [(set_attr "type" "arith")
976 (set_attr "mode" "SI")])
977
978;; Rotate Right
979(define_insn "rotrsi3"
980 [(set (match_operand:SI 0 "register_operand" "=r")
981 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
982 (match_operand:SI 2 "uns_arith_operand" "O")))]
983 ""
984 "ram %0,%1,%2,0x0,0x0"
985 [(set_attr "type" "arith")])
986
987\f
988;;
989;; ....................
990;;
74f4459c 991;; CONDITIONAL BRANCHES
54f12d76 992;;
993;; ....................
994
74f4459c 995(define_expand "cbranchsi4"
996 [(set (pc)
997 (if_then_else
91651d9b 998 (match_operator 0 "ordered_comparison_operator"
999 [(match_operand:SI 1 "register_operand")
1000 (match_operand:SI 2 "reg_or_const_operand")])
1001 (label_ref (match_operand 3 ""))
74f4459c 1002 (pc)))]
54f12d76 1003 ""
1004 "
1005{
74f4459c 1006 gen_conditional_branch (operands, SImode);
1007 DONE;
54f12d76 1008}")
1009
54f12d76 1010
1011;; Conditional branches on comparisons with zero.
1012
1013(define_insn "branch_zero"
1014 [(set (pc)
1015 (if_then_else
91651d9b 1016 (match_operator 0 "cmp_op"
1017 [(match_operand:SI 2 "register_operand" "d")
1018 (const_int 0)])
54f12d76 1019 (label_ref (match_operand 1 "" ""))
1020 (pc)))]
1021 ""
1022 "*
1023{
1024 return iq2000_output_conditional_branch (insn,
1025 operands,
1026 /*two_operands_p=*/0,
1027 /*float_p=*/0,
1028 /*inverted_p=*/0,
1029 get_attr_length (insn));
1030}"
1031 [(set_attr "type" "branch")
1032 (set_attr "mode" "none")])
1033
1034(define_insn "branch_zero_inverted"
1035 [(set (pc)
1036 (if_then_else
91651d9b 1037 (match_operator 0 "cmp_op"
1038 [(match_operand:SI 2 "register_operand" "d")
1039 (const_int 0)])
54f12d76 1040 (pc)
1041 (label_ref (match_operand 1 "" ""))))]
1042 ""
1043 "*
1044{
1045 return iq2000_output_conditional_branch (insn,
1046 operands,
1047 /*two_operands_p=*/0,
1048 /*float_p=*/0,
1049 /*inverted_p=*/1,
1050 get_attr_length (insn));
1051}"
1052 [(set_attr "type" "branch")
1053 (set_attr "mode" "none")])
1054
5b2a6a38 1055;; Conditional branch on equality comparison.
54f12d76 1056
1057(define_insn "branch_equality"
1058 [(set (pc)
1059 (if_then_else
91651d9b 1060 (match_operator 0 "equality_op"
1061 [(match_operand:SI 2 "register_operand" "d")
1062 (match_operand:SI 3 "register_operand" "d")])
54f12d76 1063 (label_ref (match_operand 1 "" ""))
1064 (pc)))]
1065 ""
1066 "*
1067{
1068 return iq2000_output_conditional_branch (insn,
1069 operands,
1070 /*two_operands_p=*/1,
1071 /*float_p=*/0,
1072 /*inverted_p=*/0,
1073 get_attr_length (insn));
1074}"
1075 [(set_attr "type" "branch")
1076 (set_attr "mode" "none")])
1077
1078(define_insn "branch_equality_inverted"
1079 [(set (pc)
1080 (if_then_else
91651d9b 1081 (match_operator 0 "equality_op"
1082 [(match_operand:SI 2 "register_operand" "d")
1083 (match_operand:SI 3 "register_operand" "d")])
54f12d76 1084 (pc)
1085 (label_ref (match_operand 1 "" ""))))]
1086 ""
1087 "*
1088{
1089 return iq2000_output_conditional_branch (insn,
1090 operands,
1091 /*two_operands_p=*/1,
1092 /*float_p=*/0,
1093 /*inverted_p=*/1,
1094 get_attr_length (insn));
1095}"
1096 [(set_attr "type" "branch")
1097 (set_attr "mode" "none")])
1098
54f12d76 1099
1100;; Recognize bbi and bbin instructions. These use two unusual template
1101;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF
1102;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC
1103;; and outputs the operand if `x' is a LABEL_REF.
1104
1105(define_insn ""
1106 [(set (pc)
1107 (if_then_else
1108 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1109 (const_int 1)
1110 (match_operand:SI 1 "arith_operand" "I"))
1111 (const_int 0))
1112 (match_operand 2 "pc_or_label_operand" "")
1113 (match_operand 3 "pc_or_label_operand" "")))]
1114 ""
1115 "bb%A2\\t%0(31-%1),%P2%P3"
1116 [(set_attr "length" "4")
1117 (set_attr "type" "branch")])
1118
1119(define_insn ""
1120 [(set (pc)
1121 (if_then_else
1122 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1123 (const_int 1)
1124 (match_operand:SI 1 "arith_operand" "I"))
1125 (const_int 0))
1126 (match_operand 2 "pc_or_label_operand" "")
1127 (match_operand 3 "pc_or_label_operand" "")))]
1128 ""
1129 "bb%A3\\t%0(31-%1),%P2%P3"
1130 [(set_attr "length" "4")
1131 (set_attr "type" "branch")])
1132
1133(define_insn ""
1134 [(set (pc)
1135 (if_then_else
1136 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1137 (const_int 1)
1138 (match_operand:SI 1 "arith_operand" "I"))
1139 (const_int 0))
1140 (match_operand 2 "pc_or_label_operand" "")
1141 (match_operand 3 "pc_or_label_operand" "")))]
91651d9b 1142 "0"
54f12d76 1143 "bb%A2\\t%0(31-%1),%P2%P3"
1144 [(set_attr "length" "4")
1145 (set_attr "type" "branch")])
1146
1147(define_insn ""
1148 [(set (pc)
1149 (if_then_else
1150 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1151 (const_int 1)
1152 (match_operand:SI 1 "arith_operand" "I"))
1153 (const_int 0))
1154 (match_operand 2 "pc_or_label_operand" "")
1155 (match_operand 3 "pc_or_label_operand" "")))]
91651d9b 1156 "0"
54f12d76 1157 "bb%A3\\t%0(31-%1),%P2%P3"
1158 [(set_attr "length" "4")
1159 (set_attr "type" "branch")])
1160
1161(define_insn ""
1162 [(set (pc)
1163 (if_then_else
1164 (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1165 (match_operand:SI 1 "power_of_2_operand" "I"))
1166 (const_int 0))
1167 (match_operand 2 "pc_or_label_operand" "")
1168 (match_operand 3 "pc_or_label_operand" "")))]
1169 ""
1170 "bb%A3\\t%0(%p1),%P2%P3"
1171 [(set_attr "length" "4")
1172 (set_attr "type" "branch")])
1173
1174(define_insn ""
1175 [(set (pc)
1176 (if_then_else
1177 (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1178 (match_operand:SI 1 "power_of_2_operand" "I"))
1179 (const_int 0))
1180 (match_operand 2 "pc_or_label_operand" "")
1181 (match_operand 3 "pc_or_label_operand" "")))]
1182 ""
1183 "bb%A2\\t%0(%p1),%P2%P3"
1184 [(set_attr "length" "4")
1185 (set_attr "type" "branch")])
1186\f
1187;;
1188;; ....................
1189;;
1190;; SETTING A REGISTER FROM A COMPARISON
1191;;
1192;; ....................
1193
74f4459c 1194(define_expand "cstoresi4"
54f12d76 1195 [(set (match_operand:SI 0 "register_operand" "=d")
74f4459c 1196 (match_operator:SI 1 "ordered_comparison_operator"
1197 [(match_operand:SI 2 "register_operand")
1198 (match_operand:SI 3 "reg_or_const_operand")]))]
54f12d76 1199 ""
1200 "
1201{
74f4459c 1202 gen_int_relational (GET_CODE (operands[1]), operands[0],
1203 operands[2], operands[3], (int *)0);
54f12d76 1204 DONE;
1205}")
1206
54f12d76 1207(define_insn "seq_si_zero"
1208 [(set (match_operand:SI 0 "register_operand" "=d")
1209 (eq:SI (match_operand:SI 1 "register_operand" "d")
1210 (const_int 0)))]
1211 ""
1212 "sltiu\\t%0,%1,1"
1213 [(set_attr "type" "arith")
1214 (set_attr "mode" "SI")])
1215
54f12d76 1216(define_insn "sne_si_zero"
1217 [(set (match_operand:SI 0 "register_operand" "=d")
1218 (ne:SI (match_operand:SI 1 "register_operand" "d")
1219 (const_int 0)))]
1220 ""
1221 "sltu\\t%0,%.,%1"
1222 [(set_attr "type" "arith")
1223 (set_attr "mode" "SI")])
1224
54f12d76 1225(define_insn "sgt_si"
205c3b0a 1226 [(set (match_operand:SI 0 "register_operand" "=d,d")
54f12d76 1227 (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1228 (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1229 ""
1230 "@
1231 slt\\t%0,%z2,%1
1232 slt\\t%0,%z2,%1"
1233 [(set_attr "type" "arith,arith")
1234 (set_attr "mode" "SI,SI")])
1235
54f12d76 1236(define_insn "slt_si"
205c3b0a 1237 [(set (match_operand:SI 0 "register_operand" "=d,d")
54f12d76 1238 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1239 (match_operand:SI 2 "arith_operand" "d,I")))]
1240 ""
1241 "@
1242 slt\\t%0,%1,%2
1243 slti\\t%0,%1,%2"
1244 [(set_attr "type" "arith,arith")
1245 (set_attr "mode" "SI,SI")])
1246
54f12d76 1247(define_insn "sle_si_const"
1248 [(set (match_operand:SI 0 "register_operand" "=d")
1249 (le:SI (match_operand:SI 1 "register_operand" "d")
1250 (match_operand:SI 2 "small_int" "I")))]
1251 "INTVAL (operands[2]) < 32767"
1252 "*
1253{
1254 operands[2] = GEN_INT (INTVAL (operands[2])+1);
1255 return \"slti\\t%0,%1,%2\";
1256}"
1257 [(set_attr "type" "arith")
1258 (set_attr "mode" "SI")])
1259
54f12d76 1260(define_insn "sgtu_si"
1261 [(set (match_operand:SI 0 "register_operand" "=d")
1262 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1263 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1264 ""
1265 "sltu\\t%0,%z2,%1"
1266 [(set_attr "type" "arith")
1267 (set_attr "mode" "SI")])
1268
54f12d76 1269(define_insn "sltu_si"
205c3b0a 1270 [(set (match_operand:SI 0 "register_operand" "=d,d")
54f12d76 1271 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1272 (match_operand:SI 2 "arith_operand" "d,I")))]
1273 ""
1274 "@
1275 sltu\\t%0,%1,%2
1276 sltiu\\t%0,%1,%2"
1277 [(set_attr "type" "arith,arith")
1278 (set_attr "mode" "SI,SI")])
1279
54f12d76 1280(define_insn "sleu_si_const"
1281 [(set (match_operand:SI 0 "register_operand" "=d")
1282 (leu:SI (match_operand:SI 1 "register_operand" "d")
1283 (match_operand:SI 2 "small_int" "I")))]
1284 "INTVAL (operands[2]) < 32767"
1285 "*
1286{
1287 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1288 return \"sltiu\\t%0,%1,%2\";
1289}"
1290 [(set_attr "type" "arith")
1291 (set_attr "mode" "SI")])
1292
1293\f
1294;;
1295;; ....................
1296;;
1297;; UNCONDITIONAL BRANCHES
1298;;
1299;; ....................
1300
1301;; Unconditional branches.
1302
1303(define_insn "jump"
1304 [(set (pc)
1305 (label_ref (match_operand 0 "" "")))]
1306 ""
1307 "*
1308{
1309 if (GET_CODE (operands[0]) == REG)
1310 return \"j\\t%0\";
1311 return \"j\\t%l0\";
1312 /* return \"b\\t%l0\";*/
1313}"
1314 [(set_attr "type" "jump")
1315 (set_attr "mode" "none")])
1316
1317(define_expand "indirect_jump"
1318 [(set (pc) (match_operand 0 "register_operand" "d"))]
1319 ""
1320 "
1321{
1322 rtx dest;
1323
1324 if (operands[0]) /* eliminate unused code warnings */
1325 {
1326 dest = operands[0];
1327 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1328 operands[0] = copy_to_mode_reg (Pmode, dest);
1329
1330 if (!(Pmode == DImode))
1331 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1332 else
cfa41c37 1333 internal_error (\"unimplemented functionality\");
54f12d76 1334
1335 DONE;
1336 }
1337}")
1338
1339(define_insn "indirect_jump_internal1"
1340 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1341 "!(Pmode == DImode)"
1342 "j\\t%0"
1343 [(set_attr "type" "jump")
1344 (set_attr "mode" "none")])
1345
1346(define_expand "tablejump"
1347 [(set (pc)
1348 (match_operand 0 "register_operand" "d"))
1349 (use (label_ref (match_operand 1 "" "")))]
1350 ""
1351 "
1352{
1353 if (operands[0]) /* eliminate unused code warnings */
1354 {
797d223e 1355 gcc_assert (GET_MODE (operands[0]) == Pmode);
54f12d76 1356
1357 if (!(Pmode == DImode))
1358 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1359 else
cfa41c37 1360 internal_error (\"unimplemented functionality\");
54f12d76 1361
1362 DONE;
1363 }
1364}")
1365
1366(define_insn "tablejump_internal1"
1367 [(set (pc)
1368 (match_operand:SI 0 "register_operand" "d"))
1369 (use (label_ref (match_operand 1 "" "")))]
1370 "!(Pmode == DImode)"
1371 "j\\t%0"
1372 [(set_attr "type" "jump")
1373 (set_attr "mode" "none")])
1374
1375(define_expand "tablejump_internal3"
1376 [(parallel [(set (pc)
1377 (plus:SI (match_operand:SI 0 "register_operand" "d")
1378 (label_ref:SI (match_operand 1 "" ""))))
1379 (use (label_ref:SI (match_dup 1)))])]
1380 ""
1381 "")
1382
1383;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
1384;;; it is not valid. ??? With the USE, the condition tests may not be required
1385;;; any longer.
1386
1387;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
1388;;; We just use the conservative number here.
1389
1390(define_insn ""
1391 [(set (pc)
1392 (plus:SI (match_operand:SI 0 "register_operand" "d")
1393 (label_ref:SI (match_operand 1 "" ""))))
1394 (use (label_ref:SI (match_dup 1)))]
91a55c11 1395 "!(Pmode == DImode) && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
1396 && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC"
54f12d76 1397 "*
1398{
1399 return \"j\\t%0\";
1400}"
1401 [(set_attr "type" "jump")
1402 (set_attr "mode" "none")
1403 (set_attr "length" "8")])
1404\f
1405;;
1406;; ....................
1407;;
1408;; Function prologue/epilogue
1409;;
1410;; ....................
1411;;
1412
1413(define_expand "prologue"
1414 [(const_int 1)]
1415 ""
1416 "
1417{
1418 if (iq2000_isa >= 0) /* avoid unused code warnings */
1419 {
1420 iq2000_expand_prologue ();
1421 DONE;
1422 }
1423}")
1424
1425;; Block any insns from being moved before this point, since the
1426;; profiling call to mcount can use various registers that aren't
1427;; saved or used to pass arguments.
1428
1429(define_insn "blockage"
1430 [(unspec_volatile [(const_int 0)] 0)]
1431 ""
1432 ""
1433 [(set_attr "type" "unknown")
1434 (set_attr "mode" "none")
1435 (set_attr "length" "0")])
1436
1437(define_expand "epilogue"
1438 [(const_int 2)]
1439 ""
1440 "
1441{
1442 if (iq2000_isa >= 0) /* avoid unused code warnings */
1443 {
1444 iq2000_expand_epilogue ();
1445 DONE;
1446 }
1447}")
1448
1449;; Trivial return. Make it look like a normal return insn as that
1450;; allows jump optimizations to work better .
1451(define_insn "return"
1452 [(return)]
1453 "iq2000_can_use_return_insn ()"
1454 "j\\t%%31"
1455 [(set_attr "type" "jump")
1456 (set_attr "mode" "none")])
1457
1458;; Normal return.
1459
1460(define_insn "return_internal"
1461 [(use (match_operand 0 "pmode_register_operand" ""))
1462 (return)]
1463 ""
1464 "*
1465{
1466 return \"j\\t%0\";
1467}"
1468 [(set_attr "type" "jump")
1469 (set_attr "mode" "none")])
1470
1471(define_insn "eh_return_internal"
1472 [(const_int 4)
1473 (return)
1474 (use (reg:SI 26))
1475 (use (reg:SI 31))]
1476 ""
1477 "j\\t%%26"
1478 [(set_attr "type" "jump")
1479 (set_attr "mode" "none")])
1480
1481(define_expand "eh_return"
1482 [(use (match_operand:SI 0 "register_operand" "r"))]
1483 ""
1484 "
1485{
1486 iq2000_expand_eh_return (operands[0]);
1487 DONE;
1488}")
1489
1490\f
1491;;
1492;; ....................
1493;;
1494;; FUNCTION CALLS
1495;;
1496;; ....................
1497
1498;; calls.c now passes a third argument, make saber happy
1499
1500(define_expand "call"
1501 [(parallel [(call (match_operand 0 "memory_operand" "m")
1502 (match_operand 1 "" "i"))
1503 (clobber (reg:SI 31))
1504 (use (match_operand 2 "" "")) ;; next_arg_reg
1505 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
1506 ""
1507 "
1508{
1509 rtx addr;
1510
1511 if (operands[0]) /* eliminate unused code warnings */
1512 {
1513 addr = XEXP (operands[0], 0);
1514 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1515 || ! call_insn_operand (addr, VOIDmode))
1516 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1517
1518 /* In order to pass small structures by value in registers
1519 compatibly with the IQ2000 compiler, we need to shift the value
1520 into the high part of the register. Function_arg has encoded
1521 a PARALLEL rtx, holding a vector of adjustments to be made
1522 as the next_arg_reg variable, so we split up the insns,
1523 and emit them separately. */
1524
1525 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1526 {
1527 rtvec adjust = XVEC (operands[2], 0);
1528 int num = GET_NUM_ELEM (adjust);
1529 int i;
1530
1531 for (i = 0; i < num; i++)
1532 emit_insn (RTVEC_ELT (adjust, i));
1533 }
1534
1535 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1536 gen_rtx_REG (SImode,
1537 GP_REG_FIRST + 31)));
1538 DONE;
1539 }
1540}")
1541
1542(define_expand "call_internal0"
1543 [(parallel [(call (match_operand 0 "" "")
1544 (match_operand 1 "" ""))
1545 (clobber (match_operand:SI 2 "" ""))])]
1546 ""
1547 "")
1548
1549(define_insn "call_internal1"
1550 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1551 (match_operand 1 "" "i"))
1552 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1553 ""
1554 "*
1555{
1556 register rtx target = operands[0];
1557
1558 if (GET_CODE (target) == CONST_INT)
1559 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1560 else if (CONSTANT_ADDRESS_P (target))
1561 return \"jal\\t%0\";
1562 else
1563 return \"jalr\\t%2,%0\";
1564}"
1565 [(set_attr "type" "call")
1566 (set_attr "mode" "none")])
1567
1568;; calls.c now passes a fourth argument, make saber happy
1569
1570(define_expand "call_value"
8ba7ed0c 1571 [(parallel [(set (match_operand 0 "register_operand" "=d")
54f12d76 1572 (call (match_operand 1 "memory_operand" "m")
1573 (match_operand 2 "" "i")))
1574 (clobber (reg:SI 31))
1575 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1576 ""
1577 "
1578{
1579 rtx addr;
1580
1581 if (operands[0]) /* eliminate unused code warning */
1582 {
1583 addr = XEXP (operands[1], 0);
1584 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1585 || ! call_insn_operand (addr, VOIDmode))
1586 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1587
1588 /* In order to pass small structures by value in registers
1589 compatibly with the IQ2000 compiler, we need to shift the value
1590 into the high part of the register. Function_arg has encoded
1591 a PARALLEL rtx, holding a vector of adjustments to be made
1592 as the next_arg_reg variable, so we split up the insns,
1593 and emit them separately. */
1594
1595 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1596 {
1597 rtvec adjust = XVEC (operands[3], 0);
1598 int num = GET_NUM_ELEM (adjust);
1599 int i;
1600
1601 for (i = 0; i < num; i++)
1602 emit_insn (RTVEC_ELT (adjust, i));
1603 }
1604
1605 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1606 {
1607 emit_call_insn (gen_call_value_multiple_internal0
1608 (XEXP (XVECEXP (operands[0], 0, 0), 0),
1609 operands[1], operands[2],
1610 XEXP (XVECEXP (operands[0], 0, 1), 0),
1611 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1612 DONE;
1613 }
1614
1615 /* We have a call returning a DImode structure in an FP reg.
1616 Strip off the now unnecessary PARALLEL. */
1617 if (GET_CODE (operands[0]) == PARALLEL)
1618 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1619
1620 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1621 gen_rtx_REG (SImode,
1622 GP_REG_FIRST + 31)));
1623
1624 DONE;
1625 }
1626}")
1627
1628(define_expand "call_value_internal0"
1629 [(parallel [(set (match_operand 0 "" "")
1630 (call (match_operand 1 "" "")
1631 (match_operand 2 "" "")))
1632 (clobber (match_operand:SI 3 "" ""))])]
1633 ""
1634 "")
1635
1636(define_insn "call_value_internal1"
8ba7ed0c 1637 [(set (match_operand 0 "register_operand" "=d")
1638 (call (mem (match_operand 1 "call_insn_operand" "r"))
54f12d76 1639 (match_operand 2 "" "i")))
1640 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1641 ""
1642 "*
1643{
1644 register rtx target = operands[1];
1645
1646 if (GET_CODE (target) == CONST_INT)
1647 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
1648 else if (CONSTANT_ADDRESS_P (target))
1649 return \"jal\\t%1\";
1650 else
1651 return \"jalr\\t%3,%1\";
1652}"
1653 [(set_attr "type" "call")
1654 (set_attr "mode" "none")])
1655
1656(define_expand "call_value_multiple_internal0"
1657 [(parallel [(set (match_operand 0 "" "")
1658 (call (match_operand 1 "" "")
1659 (match_operand 2 "" "")))
1660 (set (match_operand 3 "" "")
1661 (call (match_dup 1)
1662 (match_dup 2)))
1663 (clobber (match_operand:SI 4 "" ""))])]
1664 ""
1665 "")
1666
1667;; ??? May eventually need all 6 versions of the call patterns with multiple
1668;; return values.
1669
1670(define_insn "call_value_multiple_internal1"
8ba7ed0c 1671 [(set (match_operand 0 "register_operand" "=d")
1672 (call (mem (match_operand 1 "call_insn_operand" "r"))
54f12d76 1673 (match_operand 2 "" "i")))
8ba7ed0c 1674 (set (match_operand 3 "register_operand" "=d")
54f12d76 1675 (call (mem (match_dup 1))
1676 (match_dup 2)))
1677 (clobber (match_operand:SI 4 "register_operand" "=d"))]
1678 ""
1679 "*
1680{
1681 register rtx target = operands[1];
1682
1683 if (GET_CODE (target) == CONST_INT)
1684 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
1685 else if (CONSTANT_ADDRESS_P (target))
1686 return \"jal\\t%1\";
1687 else
1688 return \"jalr\\t%4,%1\";
1689}"
1690 [(set_attr "type" "call")
1691 (set_attr "mode" "none")])
1692
1693;; Call subroutine returning any type.
1694
1695(define_expand "untyped_call"
1696 [(parallel [(call (match_operand 0 "" "")
1697 (const_int 0))
1698 (match_operand 1 "" "")
1699 (match_operand 2 "" "")])]
1700 ""
1701 "
1702{
1703 if (operands[0]) /* silence statement not reached warnings */
1704 {
1705 int i;
1706
7f265a08 1707 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
54f12d76 1708
1709 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1710 {
1711 rtx set = XVECEXP (operands[2], 0, i);
1712 emit_move_insn (SET_DEST (set), SET_SRC (set));
1713 }
1714
1715 emit_insn (gen_blockage ());
1716 DONE;
1717 }
1718}")
1719\f
1720;;
1721;; ....................
1722;;
1723;; MISC.
1724;;
1725;; ....................
1726;;
1727
1728(define_insn "nop"
1729 [(const_int 0)]
1730 ""
1731 "nop"
1732 [(set_attr "type" "nop")
1733 (set_attr "mode" "none")])
1734
1735\f
1736;; For the rare case where we need to load an address into a register
33f88b1c 1737;; that cannot be recognized by the normal movsi/addsi instructions.
54f12d76 1738;; I have no idea how many insns this can actually generate. It should
1739;; be rare, so over-estimating as 10 instructions should not have any
1740;; real performance impact.
1741(define_insn "leasi"
1742 [(set (match_operand:SI 0 "register_operand" "=d")
1743 (match_operand:SI 1 "address_operand" "p"))]
1744 "Pmode == SImode"
1745 "*
1746{
1747 rtx xoperands [3];
1748
1749 xoperands[0] = operands[0];
1750 xoperands[1] = XEXP (operands[1], 0);
1751 xoperands[2] = XEXP (operands[1], 1);
1752 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
1753 return \"\";
1754}"
1755 [(set_attr "type" "arith")
1756 (set_attr "mode" "SI")
1757 (set_attr "length" "40")])
1758
1759(define_insn "ado16"
1760 [(set (match_operand:SI 0 "register_operand" "=r")
1761 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1762 (match_operand:SI 2 "register_operand" "r")]
1763 UNSPEC_ADO16))]
1764 ""
1765 "ado16\\t%0, %1, %2"
1766)
1767
1768(define_insn "ram"
1769 [(set (match_operand:SI 0 "register_operand" "=r")
1770 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1771 (match_operand:SI 2 "const_int_operand" "I")
1772 (match_operand:SI 3 "const_int_operand" "I")
1773 (match_operand:SI 4 "const_int_operand" "I")]
1774 UNSPEC_RAM))]
1775 ""
1776 "ram\\t%0, %1, %2, %3, %4"
1777)
1778
1779(define_insn "chkhdr"
1780 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
1781 (match_operand:SI 1 "register_operand" "r")]
1782 UNSPEC_CHKHDR)]
1783 ""
1784 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
1785 [(set_attr "dslot" "not_in_dslot")]
1786)
1787
1788(define_insn "pkrl"
1789 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1790 (match_operand:SI 1 "register_operand" "r")]
1791 UNSPEC_PKRL)]
1792 ""
1793 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
1794 [(set_attr "dslot" "not_in_dslot")]
1795)
1796
1797(define_insn "cfc0"
1798 [(set (match_operand:SI 0 "register_operand" "=r")
1799 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1800 UNSPEC_CFC0))]
1801 ""
1802 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1803 [(set_attr "dslot" "ok_in_dslot")]
1804)
1805
1806(define_insn "cfc1"
1807 [(set (match_operand:SI 0 "register_operand" "=r")
1808 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1809 UNSPEC_CFC1))]
1810 ""
1811 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1812 [(set_attr "dslot" "ok_in_dslot")]
1813)
1814
1815(define_insn "cfc2"
1816 [(set (match_operand:SI 0 "register_operand" "=r")
1817 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1818 UNSPEC_CFC2))]
1819 ""
1820 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1821 [(set_attr "dslot" "not_in_dslot")]
1822)
1823
1824(define_insn "cfc3"
1825 [(set (match_operand:SI 0 "register_operand" "=r")
1826 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1827 UNSPEC_CFC3))]
1828 ""
1829 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1830 [(set_attr "dslot" "not_in_dslot")]
1831)
1832
1833(define_insn "ctc0"
1834 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1835 (match_operand:SI 1 "const_int_operand" "I")]
1836 UNSPEC_CTC0)]
1837 ""
1838 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1839 [(set_attr "dslot" "ok_in_dslot")]
1840)
1841
1842(define_insn "ctc1"
1843 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1844 (match_operand:SI 1 "const_int_operand" "I")]
1845 UNSPEC_CTC1)]
1846 ""
1847 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1848 [(set_attr "dslot" "ok_in_dslot")]
1849)
1850
1851(define_insn "ctc2"
1852 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1853 (match_operand:SI 1 "const_int_operand" "I")]
1854 UNSPEC_CTC2)]
1855 ""
1856 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1857 [(set_attr "dslot" "ok_in_dslot")]
1858)
1859
1860(define_insn "ctc3"
1861 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1862 (match_operand:SI 1 "const_int_operand" "I")]
1863 UNSPEC_CTC3)]
1864 ""
1865 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1866 [(set_attr "dslot" "ok_in_dslot")]
1867)
1868
1869(define_insn "mfc0"
1870 [(set (match_operand:SI 0 "register_operand" "=r")
1871 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1872 UNSPEC_MFC0))]
1873 ""
1874 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1875 [(set_attr "dslot" "ok_in_dslot")]
1876)
1877
1878(define_insn "mfc1"
1879 [(set (match_operand:SI 0 "register_operand" "=r")
1880 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1881 UNSPEC_MFC1))]
1882 ""
1883 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1884 [(set_attr "dslot" "ok_in_dslot")]
1885)
1886
1887(define_insn "mfc2"
1888 [(set (match_operand:SI 0 "register_operand" "=r")
1889 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1890 UNSPEC_MFC2))]
1891 ""
1892 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1893 [(set_attr "dslot" "not_in_dslot")]
1894)
1895
1896(define_insn "mfc3"
1897 [(set (match_operand:SI 0 "register_operand" "=r")
1898 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1899 UNSPEC_MFC3))]
1900 ""
1901 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1902 [(set_attr "dslot" "not_in_dslot")]
1903)
1904
1905(define_insn "mtc0"
1906 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1907 (match_operand:SI 1 "const_int_operand" "I")]
1908 UNSPEC_MTC0)]
1909 ""
1910 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1911 [(set_attr "dslot" "ok_in_dslot")]
1912)
1913
1914(define_insn "mtc1"
1915 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1916 (match_operand:SI 1 "const_int_operand" "I")]
1917 UNSPEC_MTC1)]
1918 ""
1919 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1920 [(set_attr "dslot" "ok_in_dslot")]
1921)
1922
1923(define_insn "mtc2"
1924 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1925 (match_operand:SI 1 "const_int_operand" "I")]
1926 UNSPEC_MTC2)]
1927 ""
1928 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1929 [(set_attr "dslot" "ok_in_dslot")]
1930)
1931
1932(define_insn "mtc3"
1933 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1934 (match_operand:SI 1 "const_int_operand" "I")]
1935 UNSPEC_MTC3)]
1936 ""
1937 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1938 [(set_attr "dslot" "ok_in_dslot")]
1939)
1940
1941(define_insn "lur"
1942 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1943 (match_operand:SI 1 "register_operand" "r")]
1944 UNSPEC_LUR)]
1945 ""
1946 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
1947 [(set_attr "dslot" "not_in_dslot")]
1948)
1949
1950(define_insn "rb"
1951 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1952 (match_operand:SI 1 "register_operand" "r")]
1953 UNSPEC_RB)]
1954 ""
1955 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
1956 [(set_attr "dslot" "not_in_dslot")]
1957)
1958
1959(define_insn "rx"
1960 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1961 (match_operand:SI 1 "register_operand" "r")]
1962 UNSPEC_RX)]
1963 ""
1964 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
1965 [(set_attr "dslot" "not_in_dslot")]
1966)
1967
1968(define_insn "srrd"
1969 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1970 UNSPEC_SRRD)]
1971 ""
1972 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
1973 [(set_attr "dslot" "not_in_dslot")]
1974)
1975
1976(define_insn "srwr"
1977 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1978 (match_operand:SI 1 "register_operand" "r")]
1979 UNSPEC_SRWR)]
1980 ""
1981 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
1982 [(set_attr "dslot" "not_in_dslot")]
1983)
1984
1985(define_insn "wb"
1986 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1987 (match_operand:SI 1 "register_operand" "r")]
1988 UNSPEC_WB)]
1989 ""
1990 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
1991 [(set_attr "dslot" "not_in_dslot")]
1992)
1993
1994(define_insn "wx"
1995 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1996 (match_operand:SI 1 "register_operand" "r")]
1997 UNSPEC_WX)]
1998 ""
1999 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2000 [(set_attr "dslot" "not_in_dslot")]
2001)
2002
2003(define_insn "luc32"
2004 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2005 (match_operand:SI 1 "register_operand" "r")]
2006 UNSPEC_LUC32)]
2007 ""
2008 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2009 [(set_attr "dslot" "not_in_dslot")]
2010)
2011
2012(define_insn "luc32l"
2013 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2014 (match_operand:SI 1 "register_operand" "r")]
2015 UNSPEC_LUC32L)]
2016 ""
2017 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2018 [(set_attr "dslot" "not_in_dslot")]
2019)
2020
2021(define_insn "luc64"
2022 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2023 (match_operand:SI 1 "register_operand" "r")]
2024 UNSPEC_LUC64)]
2025 ""
2026 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2027 [(set_attr "dslot" "not_in_dslot")]
2028)
2029
2030(define_insn "luc64l"
2031 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2032 (match_operand:SI 1 "register_operand" "r")]
2033 UNSPEC_LUC64L)]
2034 ""
2035 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2036 [(set_attr "dslot" "not_in_dslot")]
2037)
2038
2039(define_insn "luk"
2040 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2041 (match_operand:SI 1 "register_operand" "r")]
2042 UNSPEC_LUK)]
2043 ""
2044 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2045 [(set_attr "dslot" "ok_in_dslot")]
2046)
2047
2048(define_insn "lulck"
2049 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2050 UNSPEC_LULCK)]
2051 ""
2052 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2053 [(set_attr "dslot" "not_in_dslot")]
2054)
2055
2056(define_insn "lum32"
2057 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2058 (match_operand:SI 1 "register_operand" "r")]
2059 UNSPEC_LUM32)]
2060 ""
2061 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2062 [(set_attr "dslot" "not_in_dslot")]
2063)
2064
2065(define_insn "lum32l"
2066 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2067 (match_operand:SI 1 "register_operand" "r")]
2068 UNSPEC_LUM32L)]
2069 ""
2070 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2071 [(set_attr "dslot" "not_in_dslot")]
2072)
2073
2074(define_insn "lum64"
2075 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2076 (match_operand:SI 1 "register_operand" "r")]
2077 UNSPEC_LUM64)]
2078 ""
2079 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2080 [(set_attr "dslot" "not_in_dslot")]
2081)
2082
2083(define_insn "lum64l"
2084 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2085 (match_operand:SI 1 "register_operand" "r")]
2086 UNSPEC_LUM64L)]
2087 ""
2088 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2089 [(set_attr "dslot" "not_in_dslot")]
2090)
2091
2092(define_insn "lurl"
2093 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2094 (match_operand:SI 1 "register_operand" "r")]
2095 UNSPEC_LURL)]
2096 ""
2097 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2098 [(set_attr "dslot" "not_in_dslot")]
2099)
2100
2101(define_insn "mrgb"
2102 [(set (match_operand:SI 0 "register_operand" "=r")
2103 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2104 (match_operand:SI 2 "register_operand" "r")
2105 (match_operand:SI 3 "const_int_operand" "I")]
2106 UNSPEC_MRGB))]
2107 ""
2108 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2109 [(set_attr "dslot" "ok_in_dslot")]
2110)
2111
2112(define_insn "srrdl"
2113 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2114 UNSPEC_SRRDL)]
2115 ""
2116 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2117 [(set_attr "dslot" "not_in_dslot")]
2118)
2119
2120(define_insn "srulck"
2121 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2122 UNSPEC_SRULCK)]
2123 ""
2124 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2125 [(set_attr "dslot" "not_in_dslot")]
2126)
2127
2128(define_insn "srwru"
2129 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2130 (match_operand:SI 1 "register_operand" "r")]
2131 UNSPEC_SRWRU)]
2132 ""
2133 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2134 [(set_attr "dslot" "not_in_dslot")]
2135)
2136
2137(define_insn "trapqfl"
2138 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2139 ""
2140 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2141 [(set_attr "dslot" "not_in_dslot")]
2142)
2143
2144(define_insn "trapqne"
2145 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2146 ""
2147 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2148 [(set_attr "dslot" "not_in_dslot")]
2149)
2150
2151(define_insn "traprel"
2152 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2153 UNSPEC_TRAPREL)]
2154 ""
2155 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2156 [(set_attr "dslot" "not_in_dslot")]
2157)
2158
2159(define_insn "wbu"
2160 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2161 (match_operand:SI 1 "register_operand" "r")]
2162 UNSPEC_WBU)]
2163 ""
2164 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2165 [(set_attr "dslot" "not_in_dslot")]
2166)
2167
2168(define_insn "syscall"
2169 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2170 ""
2171 "syscall"
2172 [(set_attr "dslot" "not_in_dslot")]
2173)
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