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Makefile.in (PLUGIN_HEADERS): Add output.h and IPA_UTILS_H.
[thirdparty/gcc.git] / gcc / config / m32c / m32c.c
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38b2d076 1/* Target Code for R8C/M16C/M32C
29d08eba 2 Copyright (C) 2005, 2006, 2007, 2008, 2009
38b2d076
DD		 3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
2f83c7d6 10 by the Free Software Foundation; either version 3, or (at your
38b2d076
DD		 11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
38b2d076
DD		 21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
26#include "rtl.h"
27#include "regs.h"
28#include "hard-reg-set.h"
29#include "real.h"
30#include "insn-config.h"
31#include "conditions.h"
32#include "insn-flags.h"
33#include "output.h"
34#include "insn-attr.h"
35#include "flags.h"
36#include "recog.h"
37#include "reload.h"
38#include "toplev.h"
39#include "obstack.h"
40#include "tree.h"
41#include "expr.h"
42#include "optabs.h"
43#include "except.h"
44#include "function.h"
45#include "ggc.h"
46#include "target.h"
47#include "target-def.h"
48#include "tm_p.h"
49#include "langhooks.h"
726a989a 50#include "gimple.h"
fa9fd28a 51#include "df.h"
38b2d076
DD		 52
53/* Prototypes */
54
55/* Used by m32c_pushm_popm. */
56typedef enum
57{
58 PP_pushm,
59 PP_popm,
60 PP_justcount
61} Push_Pop_Type;
62
65655f79 63static bool m32c_function_needs_enter (void);
38b2d076 64static tree interrupt_handler (tree *, tree, tree, int, bool *);
5abd2125 65static tree function_vector_handler (tree *, tree, tree, int, bool *);
38b2d076 66static int interrupt_p (tree node);
65655f79
DD		 67static int bank_switch_p (tree node);
68static int fast_interrupt_p (tree node);
69static int interrupt_p (tree node);
38b2d076 70static bool m32c_asm_integer (rtx, unsigned int, int);
3101faab 71static int m32c_comp_type_attributes (const_tree, const_tree);
38b2d076
DD		 72static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
73static struct machine_function *m32c_init_machine_status (void);
74static void m32c_insert_attributes (tree, tree *);
c6c3dba9 75static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
38b2d076 76static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
586de218
KG		 77 const_tree, bool);
78static bool m32c_promote_prototypes (const_tree);
38b2d076
DD		 79static int m32c_pushm_popm (Push_Pop_Type);
80static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
81static rtx m32c_struct_value_rtx (tree, int);
82static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
83static int need_to_save (int);
5abd2125
JS		 84int current_function_special_page_vector (rtx);
85
86#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
38b2d076
DD		 87
88#define streq(a,b) (strcmp ((a), (b)) == 0)
89
90/* Internal support routines */
91
92/* Debugging statements are tagged with DEBUG0 only so that they can
93 be easily enabled individually, by replacing the '0' with '1' as
94 needed. */
95#define DEBUG0 0
96#define DEBUG1 1
97
98#if DEBUG0
99/* This is needed by some of the commented-out debug statements
100 below. */
101static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
102#endif
103static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
104
105/* These are all to support encode_pattern(). */
106static char pattern[30], *patternp;
107static GTY(()) rtx patternr[30];
108#define RTX_IS(x) (streq (pattern, x))
109
110/* Some macros to simplify the logic throughout this file. */
111#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
112#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
113
114#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
115#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
116
117/* We do most RTX matching by converting the RTX into a string, and
118 using string compares. This vastly simplifies the logic in many of
119 the functions in this file.
120
121 On exit, pattern[] has the encoded string (use RTX_IS("...") to
122 compare it) and patternr[] has pointers to the nodes in the RTX
123 corresponding to each character in the encoded string. The latter
124 is mostly used by print_operand().
125
126 Unrecognized patterns have '?' in them; this shows up when the
127 assembler complains about syntax errors.
128*/
129
130static void
131encode_pattern_1 (rtx x)
132{
133 int i;
134
135 if (patternp == pattern + sizeof (pattern) - 2)
136 {
137 patternp[-1] = '?';
138 return;
139 }
140
141 patternr[patternp - pattern] = x;
142
143 switch (GET_CODE (x))
144 {
145 case REG:
146 *patternp++ = 'r';
147 break;
148 case SUBREG:
149 if (GET_MODE_SIZE (GET_MODE (x)) !=
150 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
151 *patternp++ = 'S';
152 encode_pattern_1 (XEXP (x, 0));
153 break;
154 case MEM:
155 *patternp++ = 'm';
156 case CONST:
157 encode_pattern_1 (XEXP (x, 0));
158 break;
159 case PLUS:
160 *patternp++ = '+';
161 encode_pattern_1 (XEXP (x, 0));
162 encode_pattern_1 (XEXP (x, 1));
163 break;
164 case PRE_DEC:
165 *patternp++ = '>';
166 encode_pattern_1 (XEXP (x, 0));
167 break;
168 case POST_INC:
169 *patternp++ = '<';
170 encode_pattern_1 (XEXP (x, 0));
171 break;
172 case LO_SUM:
173 *patternp++ = 'L';
174 encode_pattern_1 (XEXP (x, 0));
175 encode_pattern_1 (XEXP (x, 1));
176 break;
177 case HIGH:
178 *patternp++ = 'H';
179 encode_pattern_1 (XEXP (x, 0));
180 break;
181 case SYMBOL_REF:
182 *patternp++ = 's';
183 break;
184 case LABEL_REF:
185 *patternp++ = 'l';
186 break;
187 case CODE_LABEL:
188 *patternp++ = 'c';
189 break;
190 case CONST_INT:
191 case CONST_DOUBLE:
192 *patternp++ = 'i';
193 break;
194 case UNSPEC:
195 *patternp++ = 'u';
196 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
197 for (i = 0; i < XVECLEN (x, 0); i++)
198 encode_pattern_1 (XVECEXP (x, 0, i));
199 break;
200 case USE:
201 *patternp++ = 'U';
202 break;
203 case PARALLEL:
204 *patternp++ = '|';
205 for (i = 0; i < XVECLEN (x, 0); i++)
206 encode_pattern_1 (XVECEXP (x, 0, i));
207 break;
208 case EXPR_LIST:
209 *patternp++ = 'E';
210 encode_pattern_1 (XEXP (x, 0));
211 if (XEXP (x, 1))
212 encode_pattern_1 (XEXP (x, 1));
213 break;
214 default:
215 *patternp++ = '?';
216#if DEBUG0
217 fprintf (stderr, "can't encode pattern %s\n",
218 GET_RTX_NAME (GET_CODE (x)));
219 debug_rtx (x);
220 gcc_unreachable ();
221#endif
222 break;
223 }
224}
225
226static void
227encode_pattern (rtx x)
228{
229 patternp = pattern;
230 encode_pattern_1 (x);
231 *patternp = 0;
232}
233
234/* Since register names indicate the mode they're used in, we need a
235 way to determine which name to refer to the register with. Called
236 by print_operand(). */
237
238static const char *
239reg_name_with_mode (int regno, enum machine_mode mode)
240{
241 int mlen = GET_MODE_SIZE (mode);
242 if (regno == R0_REGNO && mlen == 1)
243 return "r0l";
244 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
245 return "r2r0";
246 if (regno == R0_REGNO && mlen == 6)
247 return "r2r1r0";
248 if (regno == R0_REGNO && mlen == 8)
249 return "r3r1r2r0";
250 if (regno == R1_REGNO && mlen == 1)
251 return "r1l";
252 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
253 return "r3r1";
254 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
255 return "a1a0";
256 return reg_names[regno];
257}
258
259/* How many bytes a register uses on stack when it's pushed. We need
260 to know this because the push opcode needs to explicitly indicate
261 the size of the register, even though the name of the register
262 already tells it that. Used by m32c_output_reg_{push,pop}, which
263 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
264
265static int
266reg_push_size (int regno)
267{
268 switch (regno)
269 {
270 case R0_REGNO:
271 case R1_REGNO:
272 return 2;
273 case R2_REGNO:
274 case R3_REGNO:
275 case FLG_REGNO:
276 return 2;
277 case A0_REGNO:
278 case A1_REGNO:
279 case SB_REGNO:
280 case FB_REGNO:
281 case SP_REGNO:
282 if (TARGET_A16)
283 return 2;
284 else
285 return 3;
286 default:
287 gcc_unreachable ();
288 }
289}
290
291static int *class_sizes = 0;
292
293/* Given two register classes, find the largest intersection between
294 them. If there is no intersection, return RETURNED_IF_EMPTY
295 instead. */
296static int
297reduce_class (int original_class, int limiting_class, int returned_if_empty)
298{
299 int cc = class_contents[original_class][0];
300 int i, best = NO_REGS;
301 int best_size = 0;
302
303 if (original_class == limiting_class)
304 return original_class;
305
306 if (!class_sizes)
307 {
308 int r;
309 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
310 for (i = 0; i < LIM_REG_CLASSES; i++)
311 {
312 class_sizes[i] = 0;
313 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
314 if (class_contents[i][0] & (1 << r))
315 class_sizes[i]++;
316 }
317 }
318
319 cc &= class_contents[limiting_class][0];
320 for (i = 0; i < LIM_REG_CLASSES; i++)
321 {
322 int ic = class_contents[i][0];
323
324 if ((~cc & ic) == 0)
325 if (best_size < class_sizes[i])
326 {
327 best = i;
328 best_size = class_sizes[i];
329 }
330
331 }
332 if (best == NO_REGS)
333 return returned_if_empty;
334 return best;
335}
336
337/* Returns TRUE If there are any registers that exist in both register
338 classes. */
339static int
340classes_intersect (int class1, int class2)
341{
342 return class_contents[class1][0] & class_contents[class2][0];
343}
344
345/* Used by m32c_register_move_cost to determine if a move is
346 impossibly expensive. */
347static int
0a2aaacc 348class_can_hold_mode (int rclass, enum machine_mode mode)
38b2d076
DD		 349{
350 /* Cache the results: 0=untested 1=no 2=yes */
351 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
0a2aaacc 352 if (results[rclass][mode] == 0)
38b2d076
DD		 353 {
354 int r, n, i;
0a2aaacc 355 results[rclass][mode] = 1;
38b2d076 356 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
0a2aaacc 357 if (class_contents[rclass][0] & (1 << r)
38b2d076
DD		 358 && HARD_REGNO_MODE_OK (r, mode))
359 {
360 int ok = 1;
361 n = HARD_REGNO_NREGS (r, mode);
362 for (i = 1; i < n; i++)
0a2aaacc 363 if (!(class_contents[rclass][0] & (1 << (r + i))))
38b2d076
DD		 364 ok = 0;
365 if (ok)
366 {
0a2aaacc 367 results[rclass][mode] = 2;
38b2d076
DD		 368 break;
369 }
370 }
371 }
372#if DEBUG0
373 fprintf (stderr, "class %s can hold %s? %s\n",
0a2aaacc
KG		 374 class_names[rclass], mode_name[mode],
375 (results[rclass][mode] == 2) ? "yes" : "no");
38b2d076 376#endif
0a2aaacc 377 return results[rclass][mode] == 2;
38b2d076
DD		 378}
379
380/* Run-time Target Specification. */
381
382/* Memregs are memory locations that gcc treats like general
383 registers, as there are a limited number of true registers and the
384 m32c families can use memory in most places that registers can be
385 used.
386
387 However, since memory accesses are more expensive than registers,
388 we allow the user to limit the number of memregs available, in
389 order to try to persuade gcc to try harder to use real registers.
390
391 Memregs are provided by m32c-lib1.S.
392*/
393
394int target_memregs = 16;
395static bool target_memregs_set = FALSE;
396int ok_to_change_target_memregs = TRUE;
397
398#undef TARGET_HANDLE_OPTION
399#define TARGET_HANDLE_OPTION m32c_handle_option
400static bool
401m32c_handle_option (size_t code,
402 const char *arg ATTRIBUTE_UNUSED,
403 int value ATTRIBUTE_UNUSED)
404{
405 if (code == OPT_memregs_)
406 {
407 target_memregs_set = TRUE;
408 target_memregs = atoi (arg);
409 }
410 return TRUE;
411}
412
413/* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
414 provide a default. */
415void
416m32c_override_options (void)
417{
418 if (target_memregs_set)
419 {
420 if (target_memregs < 0 || target_memregs > 16)
421 error ("invalid target memregs value '%d'", target_memregs);
422 }
423 else
07127a0a 424 target_memregs = 16;
18b80268
DD		 425
426 if (TARGET_A24)
427 flag_ivopts = 0;
38b2d076
DD		 428}
429
430/* Defining data structures for per-function information */
431
432/* The usual; we set up our machine_function data. */
433static struct machine_function *
434m32c_init_machine_status (void)
435{
436 struct machine_function *machine;
437 machine =
438 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
439
440 return machine;
441}
442
443/* Implements INIT_EXPANDERS. We just set up to call the above
444 function. */
445void
446m32c_init_expanders (void)
447{
448 init_machine_status = m32c_init_machine_status;
449}
450
451/* Storage Layout */
452
38b2d076
DD		 453/* Register Basics */
454
455/* Basic Characteristics of Registers */
456
457/* Whether a mode fits in a register is complex enough to warrant a
458 table. */
459static struct
460{
461 char qi_regs;
462 char hi_regs;
463 char pi_regs;
464 char si_regs;
465 char di_regs;
466} nregs_table[FIRST_PSEUDO_REGISTER] =
467{
468 { 1, 1, 2, 2, 4 }, /* r0 */
469 { 0, 1, 0, 0, 0 }, /* r2 */
470 { 1, 1, 2, 2, 0 }, /* r1 */
471 { 0, 1, 0, 0, 0 }, /* r3 */
472 { 0, 1, 1, 0, 0 }, /* a0 */
473 { 0, 1, 1, 0, 0 }, /* a1 */
474 { 0, 1, 1, 0, 0 }, /* sb */
475 { 0, 1, 1, 0, 0 }, /* fb */
476 { 0, 1, 1, 0, 0 }, /* sp */
477 { 1, 1, 1, 0, 0 }, /* pc */
478 { 0, 0, 0, 0, 0 }, /* fl */
479 { 1, 1, 1, 0, 0 }, /* ap */
480 { 1, 1, 2, 2, 4 }, /* mem0 */
481 { 1, 1, 2, 2, 4 }, /* mem1 */
482 { 1, 1, 2, 2, 4 }, /* mem2 */
483 { 1, 1, 2, 2, 4 }, /* mem3 */
484 { 1, 1, 2, 2, 4 }, /* mem4 */
485 { 1, 1, 2, 2, 0 }, /* mem5 */
486 { 1, 1, 2, 2, 0 }, /* mem6 */
487 { 1, 1, 0, 0, 0 }, /* mem7 */
488};
489
490/* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
491 available memregs, and select which registers need to be preserved
492 across calls based on the chip family. */
493
494void
495m32c_conditional_register_usage (void)
496{
38b2d076
DD		 497 int i;
498
499 if (0 <= target_memregs && target_memregs <= 16)
500 {
501 /* The command line option is bytes, but our "registers" are
502 16-bit words. */
65655f79 503 for (i = (target_memregs+1)/2; i < 8; i++)
38b2d076
DD		 504 {
505 fixed_regs[MEM0_REGNO + i] = 1;
506 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
507 }
508 }
509
510 /* M32CM and M32C preserve more registers across function calls. */
511 if (TARGET_A24)
512 {
513 call_used_regs[R1_REGNO] = 0;
514 call_used_regs[R2_REGNO] = 0;
515 call_used_regs[R3_REGNO] = 0;
516 call_used_regs[A0_REGNO] = 0;
517 call_used_regs[A1_REGNO] = 0;
518 }
519}
520
521/* How Values Fit in Registers */
522
523/* Implements HARD_REGNO_NREGS. This is complicated by the fact that
524 different registers are different sizes from each other, *and* may
525 be different sizes in different chip families. */
b8a669d0
DD		 526static int
527m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
38b2d076
DD		 528{
529 if (regno == FLG_REGNO && mode == CCmode)
530 return 1;
531 if (regno >= FIRST_PSEUDO_REGISTER)
532 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
533
534 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
535 return (GET_MODE_SIZE (mode) + 1) / 2;
536
537 if (GET_MODE_SIZE (mode) <= 1)
538 return nregs_table[regno].qi_regs;
539 if (GET_MODE_SIZE (mode) <= 2)
540 return nregs_table[regno].hi_regs;
541 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
542 return 2;
543 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
544 return nregs_table[regno].pi_regs;
545 if (GET_MODE_SIZE (mode) <= 4)
546 return nregs_table[regno].si_regs;
547 if (GET_MODE_SIZE (mode) <= 8)
548 return nregs_table[regno].di_regs;
549 return 0;
550}
551
b8a669d0
DD		 552int
553m32c_hard_regno_nregs (int regno, enum machine_mode mode)
554{
555 int rv = m32c_hard_regno_nregs_1 (regno, mode);
556 return rv ? rv : 1;
557}
558
38b2d076
DD		 559/* Implements HARD_REGNO_MODE_OK. The above function does the work
560 already; just test its return value. */
561int
562m32c_hard_regno_ok (int regno, enum machine_mode mode)
563{
b8a669d0 564 return m32c_hard_regno_nregs_1 (regno, mode) != 0;
38b2d076
DD		 565}
566
567/* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
568 registers are all different sizes. However, since most modes are
569 bigger than our registers anyway, it's easier to implement this
570 function that way, leaving QImode as the only unique case. */
571int
572m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
573{
574 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
575 return 1;
576
07127a0a 577#if 0
38b2d076
DD		 578 if (m1 == QImode || m2 == QImode)
579 return 0;
07127a0a 580#endif
38b2d076
DD		 581
582 return 1;
583}
584
585/* Register Classes */
586
587/* Implements REGNO_REG_CLASS. */
588enum machine_mode
589m32c_regno_reg_class (int regno)
590{
591 switch (regno)
592 {
593 case R0_REGNO:
594 return R0_REGS;
595 case R1_REGNO:
596 return R1_REGS;
597 case R2_REGNO:
598 return R2_REGS;
599 case R3_REGNO:
600 return R3_REGS;
601 case A0_REGNO:
602 case A1_REGNO:
603 return A_REGS;
604 case SB_REGNO:
605 return SB_REGS;
606 case FB_REGNO:
607 return FB_REGS;
608 case SP_REGNO:
609 return SP_REGS;
610 case FLG_REGNO:
611 return FLG_REGS;
612 default:
613 if (IS_MEM_REGNO (regno))
614 return MEM_REGS;
615 return ALL_REGS;
616 }
617}
618
619/* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
620 for certain chip families. */
621int
622m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
623{
624 if (memcmp (s, "Rsp", 3) == 0)
625 return SP_REGS;
626 if (memcmp (s, "Rfb", 3) == 0)
627 return FB_REGS;
628 if (memcmp (s, "Rsb", 3) == 0)
629 return SB_REGS;
07127a0a
DD		 630 if (memcmp (s, "Rcr", 3) == 0)
631 return TARGET_A16 ? CR_REGS : NO_REGS;
632 if (memcmp (s, "Rcl", 3) == 0)
633 return TARGET_A24 ? CR_REGS : NO_REGS;
38b2d076
DD		 634 if (memcmp (s, "R0w", 3) == 0)
635 return R0_REGS;
636 if (memcmp (s, "R1w", 3) == 0)
637 return R1_REGS;
638 if (memcmp (s, "R2w", 3) == 0)
639 return R2_REGS;
640 if (memcmp (s, "R3w", 3) == 0)
641 return R3_REGS;
642 if (memcmp (s, "R02", 3) == 0)
643 return R02_REGS;
18b80268
DD		 644 if (memcmp (s, "R13", 3) == 0)
645 return R13_REGS;
38b2d076
DD		 646 if (memcmp (s, "R03", 3) == 0)
647 return R03_REGS;
648 if (memcmp (s, "Rdi", 3) == 0)
649 return DI_REGS;
650 if (memcmp (s, "Rhl", 3) == 0)
651 return HL_REGS;
652 if (memcmp (s, "R23", 3) == 0)
653 return R23_REGS;
07127a0a
DD		 654 if (memcmp (s, "Ra0", 3) == 0)
655 return A0_REGS;
656 if (memcmp (s, "Ra1", 3) == 0)
657 return A1_REGS;
38b2d076
DD		 658 if (memcmp (s, "Raa", 3) == 0)
659 return A_REGS;
07127a0a
DD		 660 if (memcmp (s, "Raw", 3) == 0)
661 return TARGET_A16 ? A_REGS : NO_REGS;
662 if (memcmp (s, "Ral", 3) == 0)
663 return TARGET_A24 ? A_REGS : NO_REGS;
38b2d076
DD		 664 if (memcmp (s, "Rqi", 3) == 0)
665 return QI_REGS;
666 if (memcmp (s, "Rad", 3) == 0)
667 return AD_REGS;
668 if (memcmp (s, "Rsi", 3) == 0)
669 return SI_REGS;
670 if (memcmp (s, "Rhi", 3) == 0)
671 return HI_REGS;
672 if (memcmp (s, "Rhc", 3) == 0)
673 return HC_REGS;
674 if (memcmp (s, "Rra", 3) == 0)
675 return RA_REGS;
676 if (memcmp (s, "Rfl", 3) == 0)
677 return FLG_REGS;
678 if (memcmp (s, "Rmm", 3) == 0)
679 {
680 if (fixed_regs[MEM0_REGNO])
681 return NO_REGS;
682 return MEM_REGS;
683 }
684
685 /* PSImode registers - i.e. whatever can hold a pointer. */
686 if (memcmp (s, "Rpi", 3) == 0)
687 {
688 if (TARGET_A16)
689 return HI_REGS;
690 else
691 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
692 }
693
694 /* We handle this one as an EXTRA_CONSTRAINT. */
695 if (memcmp (s, "Rpa", 3) == 0)
696 return NO_REGS;
697
07127a0a
DD		 698 if (*s == 'R')
699 {
700 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
701 gcc_unreachable();
702 }
703
38b2d076
DD		 704 return NO_REGS;
705}
706
707/* Implements REGNO_OK_FOR_BASE_P. */
708int
709m32c_regno_ok_for_base_p (int regno)
710{
711 if (regno == A0_REGNO
712 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
713 return 1;
714 return 0;
715}
716
717#define DEBUG_RELOAD 0
718
719/* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
720 registers of the appropriate size. */
721int
722m32c_preferred_reload_class (rtx x, int rclass)
723{
724 int newclass = rclass;
725
726#if DEBUG_RELOAD
727 fprintf (stderr, "\npreferred_reload_class for %s is ",
728 class_names[rclass]);
729#endif
730 if (rclass == NO_REGS)
731 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
732
733 if (classes_intersect (rclass, CR_REGS))
734 {
735 switch (GET_MODE (x))
736 {
737 case QImode:
738 newclass = HL_REGS;
739 break;
740 default:
741 /* newclass = HI_REGS; */
742 break;
743 }
744 }
745
746 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
747 newclass = SI_REGS;
748 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
749 && ~class_contents[rclass][0] & 0x000f)
750 newclass = DI_REGS;
751
752 rclass = reduce_class (rclass, newclass, rclass);
753
754 if (GET_MODE (x) == QImode)
755 rclass = reduce_class (rclass, HL_REGS, rclass);
756
757#if DEBUG_RELOAD
758 fprintf (stderr, "%s\n", class_names[rclass]);
759 debug_rtx (x);
760
761 if (GET_CODE (x) == MEM
762 && GET_CODE (XEXP (x, 0)) == PLUS
763 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
764 fprintf (stderr, "Glorm!\n");
765#endif
766 return rclass;
767}
768
769/* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
770int
771m32c_preferred_output_reload_class (rtx x, int rclass)
772{
773 return m32c_preferred_reload_class (x, rclass);
774}
775
776/* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
777 address registers for reloads since they're needed for address
778 reloads. */
779int
780m32c_limit_reload_class (enum machine_mode mode, int rclass)
781{
782#if DEBUG_RELOAD
783 fprintf (stderr, "limit_reload_class for %s: %s ->",
784 mode_name[mode], class_names[rclass]);
785#endif
786
787 if (mode == QImode)
788 rclass = reduce_class (rclass, HL_REGS, rclass);
789 else if (mode == HImode)
790 rclass = reduce_class (rclass, HI_REGS, rclass);
791 else if (mode == SImode)
792 rclass = reduce_class (rclass, SI_REGS, rclass);
793
794 if (rclass != A_REGS)
795 rclass = reduce_class (rclass, DI_REGS, rclass);
796
797#if DEBUG_RELOAD
798 fprintf (stderr, " %s\n", class_names[rclass]);
799#endif
800 return rclass;
801}
802
803/* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
804 r0 or r1, as those are the only real QImode registers. CR regs get
805 reloaded through appropriately sized general or address
806 registers. */
807int
808m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
809{
810 int cc = class_contents[rclass][0];
811#if DEBUG0
812 fprintf (stderr, "\nsecondary reload class %s %s\n",
813 class_names[rclass], mode_name[mode]);
814 debug_rtx (x);
815#endif
816 if (mode == QImode
817 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
818 return QI_REGS;
819 if (classes_intersect (rclass, CR_REGS)
820 && GET_CODE (x) == REG
821 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
822 return TARGET_A16 ? HI_REGS : A_REGS;
823 return NO_REGS;
824}
825
826/* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
827 reloads. */
828int
829m32c_class_likely_spilled_p (int regclass)
830{
831 if (regclass == A_REGS)
832 return 1;
833 return reg_class_size[regclass] == 1;
834}
835
836/* Implements CLASS_MAX_NREGS. We calculate this according to its
837 documented meaning, to avoid potential inconsistencies with actual
838 class definitions. */
839int
840m32c_class_max_nregs (int regclass, enum machine_mode mode)
841{
842 int rn, max = 0;
843
844 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
845 if (class_contents[regclass][0] & (1 << rn))
846 {
847 int n = m32c_hard_regno_nregs (rn, mode);
848 if (max < n)
849 max = n;
850 }
851 return max;
852}
853
854/* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
855 QI (r0l, r1l) because the chip doesn't support QI ops on other
856 registers (well, it does on a0/a1 but if we let gcc do that, reload
857 suffers). Otherwise, we allow changes to larger modes. */
858int
859m32c_cannot_change_mode_class (enum machine_mode from,
860 enum machine_mode to, int rclass)
861{
db9c8397 862 int rn;
38b2d076
DD		 863#if DEBUG0
864 fprintf (stderr, "cannot change from %s to %s in %s\n",
865 mode_name[from], mode_name[to], class_names[rclass]);
866#endif
867
db9c8397
DD		 868 /* If the larger mode isn't allowed in any of these registers, we
869 can't allow the change. */
870 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
871 if (class_contents[rclass][0] & (1 << rn))
872 if (! m32c_hard_regno_ok (rn, to))
873 return 1;
874
38b2d076
DD		 875 if (to == QImode)
876 return (class_contents[rclass][0] & 0x1ffa);
877
878 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
879 && GET_MODE_SIZE (from) > 1)
880 return 0;
881 if (GET_MODE_SIZE (from) > 2) /* all other regs */
882 return 0;
883
884 return 1;
885}
886
887/* Helpers for the rest of the file. */
888/* TRUE if the rtx is a REG rtx for the given register. */
889#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
890 && REGNO (rtx) == regno)
891/* TRUE if the rtx is a pseudo - specifically, one we can use as a
892 base register in address calculations (hence the "strict"
893 argument). */
894#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
895 && (REGNO (rtx) == AP_REGNO \
896 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
897
898/* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
899 constraints start with 'I', with the next two characters indicating
900 the type and size of the range allowed. */
901int
902m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
903 char c ATTRIBUTE_UNUSED, const char *str)
904{
905 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
906 [sun] bits [SUN] bytes, p=pointer size
907 I[-0-9][0-9] matches that number */
908 if (memcmp (str, "Is3", 3) == 0)
909 {
910 return (-8 <= value && value <= 7);
911 }
912 if (memcmp (str, "IS1", 3) == 0)
913 {
914 return (-128 <= value && value <= 127);
915 }
916 if (memcmp (str, "IS2", 3) == 0)
917 {
918 return (-32768 <= value && value <= 32767);
919 }
920 if (memcmp (str, "IU2", 3) == 0)
921 {
922 return (0 <= value && value <= 65535);
923 }
924 if (memcmp (str, "IU3", 3) == 0)
925 {
926 return (0 <= value && value <= 0x00ffffff);
927 }
928 if (memcmp (str, "In4", 3) == 0)
929 {
930 return (-8 <= value && value && value <= 8);
931 }
932 if (memcmp (str, "In5", 3) == 0)
933 {
934 return (-16 <= value && value && value <= 16);
935 }
23fed240
DD		 936 if (memcmp (str, "In6", 3) == 0)
937 {
938 return (-32 <= value && value && value <= 32);
939 }
38b2d076
DD		 940 if (memcmp (str, "IM2", 3) == 0)
941 {
942 return (-65536 <= value && value && value <= -1);
943 }
944 if (memcmp (str, "Ilb", 3) == 0)
945 {
946 int b = exact_log2 (value);
8e4edce7 947 return (b >= 0 && b <= 7);
38b2d076 948 }
07127a0a
DD		 949 if (memcmp (str, "Imb", 3) == 0)
950 {
951 int b = exact_log2 ((value ^ 0xff) & 0xff);
8e4edce7 952 return (b >= 0 && b <= 7);
07127a0a 953 }
600e668e
DD		 954 if (memcmp (str, "ImB", 3) == 0)
955 {
956 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
957 return (b >= 0 && b <= 7);
958 }
38b2d076
DD		 959 if (memcmp (str, "Ilw", 3) == 0)
960 {
961 int b = exact_log2 (value);
8e4edce7 962 return (b >= 0 && b <= 15);
38b2d076 963 }
07127a0a
DD		 964 if (memcmp (str, "Imw", 3) == 0)
965 {
966 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
8e4edce7 967 return (b >= 0 && b <= 15);
07127a0a
DD		 968 }
969 if (memcmp (str, "I00", 3) == 0)
970 {
971 return (value == 0);
972 }
38b2d076
DD		 973 return 0;
974}
975
976/* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
977 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
978 call return values. */
979int
980m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
981{
982 encode_pattern (value);
983 if (memcmp (str, "Sd", 2) == 0)
984 {
985 /* This is the common "src/dest" address */
986 rtx r;
987 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
988 return 1;
989 if (RTX_IS ("ms") || RTX_IS ("m+si"))
990 return 1;
07127a0a
DD		 991 if (RTX_IS ("m++rii"))
992 {
993 if (REGNO (patternr[3]) == FB_REGNO
994 && INTVAL (patternr[4]) == 0)
995 return 1;
996 }
38b2d076
DD		 997 if (RTX_IS ("mr"))
998 r = patternr[1];
999 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
1000 r = patternr[2];
1001 else
1002 return 0;
1003 if (REGNO (r) == SP_REGNO)
1004 return 0;
1005 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
1006 }
1007 else if (memcmp (str, "Sa", 2) == 0)
1008 {
1009 rtx r;
1010 if (RTX_IS ("mr"))
1011 r = patternr[1];
1012 else if (RTX_IS ("m+ri"))
1013 r = patternr[2];
1014 else
1015 return 0;
1016 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1017 }
1018 else if (memcmp (str, "Si", 2) == 0)
1019 {
1020 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1021 }
1022 else if (memcmp (str, "Ss", 2) == 0)
1023 {
1024 return ((RTX_IS ("mr")
1025 && (IS_REG (patternr[1], SP_REGNO)))
1026 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1027 }
1028 else if (memcmp (str, "Sf", 2) == 0)
1029 {
1030 return ((RTX_IS ("mr")
1031 && (IS_REG (patternr[1], FB_REGNO)))
1032 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1033 }
1034 else if (memcmp (str, "Sb", 2) == 0)
1035 {
1036 return ((RTX_IS ("mr")
1037 && (IS_REG (patternr[1], SB_REGNO)))
1038 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1039 }
07127a0a
DD		 1040 else if (memcmp (str, "Sp", 2) == 0)
1041 {
1042 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1043 return (RTX_IS ("mi")
1044 && !(INTVAL (patternr[1]) & ~0x1fff));
1045 }
38b2d076
DD		 1046 else if (memcmp (str, "S1", 2) == 0)
1047 {
1048 return r1h_operand (value, QImode);
1049 }
1050
1051 gcc_assert (str[0] != 'S');
1052
1053 if (memcmp (str, "Rpa", 2) == 0)
1054 return GET_CODE (value) == PARALLEL;
1055
1056 return 0;
1057}
1058
1059/* This is for when we're debugging the above. */
1060int
1061m32c_extra_constraint_p (rtx value, char c, const char *str)
1062{
1063 int rv = m32c_extra_constraint_p2 (value, c, str);
1064#if DEBUG0
1065 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1066 rv);
1067 debug_rtx (value);
1068#endif
1069 return rv;
1070}
1071
1072/* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1073 starting with 'S'. */
1074int
1075m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1076{
1077 return c == 'S';
1078}
1079
1080/* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1081 but don't currently define any. */
1082int
1083m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1084{
1085 return c == 'A';
1086}
1087
1088/* STACK AND CALLING */
1089
1090/* Frame Layout */
1091
1092/* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1093 (yes, THREE bytes) onto the stack for the return address, but we
1094 don't support pointers bigger than 16 bits on those chips. This
1095 will likely wreak havoc with exception unwinding. FIXME. */
1096rtx
1097m32c_return_addr_rtx (int count)
1098{
1099 enum machine_mode mode;
1100 int offset;
1101 rtx ra_mem;
1102
1103 if (count)
1104 return NULL_RTX;
1105 /* we want 2[$fb] */
1106
1107 if (TARGET_A24)
1108 {
80b093df
DD		 1109 /* It's four bytes */
1110 mode = PSImode;
38b2d076
DD		 1111 offset = 4;
1112 }
1113 else
1114 {
1115 /* FIXME: it's really 3 bytes */
1116 mode = HImode;
1117 offset = 2;
1118 }
1119
1120 ra_mem =
1121 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1122 return copy_to_mode_reg (mode, ra_mem);
1123}
1124
1125/* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1126rtx
1127m32c_incoming_return_addr_rtx (void)
1128{
1129 /* we want [sp] */
1130 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1131}
1132
1133/* Exception Handling Support */
1134
1135/* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1136 pointers. */
1137int
1138m32c_eh_return_data_regno (int n)
1139{
1140 switch (n)
1141 {
1142 case 0:
1143 return A0_REGNO;
1144 case 1:
c6004917
RIL		 1145 if (TARGET_A16)
1146 return R3_REGNO;
1147 else
1148 return R1_REGNO;
38b2d076
DD		 1149 default:
1150 return INVALID_REGNUM;
1151 }
1152}
1153
1154/* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1155 m32c_emit_eh_epilogue. */
1156rtx
1157m32c_eh_return_stackadj_rtx (void)
1158{
1159 if (!cfun->machine->eh_stack_adjust)
1160 {
1161 rtx sa;
1162
99920b6f 1163 sa = gen_rtx_REG (Pmode, R0_REGNO);
38b2d076
DD		 1164 cfun->machine->eh_stack_adjust = sa;
1165 }
1166 return cfun->machine->eh_stack_adjust;
1167}
1168
1169/* Registers That Address the Stack Frame */
1170
1171/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1172 the original spec called for dwarf numbers to vary with register
1173 width as well, for example, r0l, r0, and r2r0 would each have
1174 different dwarf numbers. GCC doesn't support this, and we don't do
1175 it, and gdb seems to like it this way anyway. */
1176unsigned int
1177m32c_dwarf_frame_regnum (int n)
1178{
1179 switch (n)
1180 {
1181 case R0_REGNO:
1182 return 5;
1183 case R1_REGNO:
1184 return 6;
1185 case R2_REGNO:
1186 return 7;
1187 case R3_REGNO:
1188 return 8;
1189 case A0_REGNO:
1190 return 9;
1191 case A1_REGNO:
1192 return 10;
1193 case FB_REGNO:
1194 return 11;
1195 case SB_REGNO:
1196 return 19;
1197
1198 case SP_REGNO:
1199 return 12;
1200 case PC_REGNO:
1201 return 13;
1202 default:
1203 return DWARF_FRAME_REGISTERS + 1;
1204 }
1205}
1206
1207/* The frame looks like this:
1208
1209 ap -> +------------------------------
1210 | Return address (3 or 4 bytes)
1211 | Saved FB (2 or 4 bytes)
1212 fb -> +------------------------------
1213 | local vars
1214 | register saves fb
1215 | through r0 as needed
1216 sp -> +------------------------------
1217*/
1218
1219/* We use this to wrap all emitted insns in the prologue. */
1220static rtx
1221F (rtx x)
1222{
1223 RTX_FRAME_RELATED_P (x) = 1;
1224 return x;
1225}
1226
1227/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1228 how much the stack pointer moves for each, for each cpu family. */
1229static struct
1230{
1231 int reg1;
1232 int bit;
1233 int a16_bytes;
1234 int a24_bytes;
1235} pushm_info[] =
1236{
9d746d5e
DD		 1237 /* These are in reverse push (nearest-to-sp) order. */
1238 { R0_REGNO, 0x80, 2, 2 },
38b2d076 1239 { R1_REGNO, 0x40, 2, 2 },
9d746d5e
DD		 1240 { R2_REGNO, 0x20, 2, 2 },
1241 { R3_REGNO, 0x10, 2, 2 },
1242 { A0_REGNO, 0x08, 2, 4 },
1243 { A1_REGNO, 0x04, 2, 4 },
1244 { SB_REGNO, 0x02, 2, 4 },
1245 { FB_REGNO, 0x01, 2, 4 }
38b2d076
DD		 1246};
1247
1248#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1249
1250/* Returns TRUE if we need to save/restore the given register. We
1251 save everything for exception handlers, so that any register can be
1252 unwound. For interrupt handlers, we save everything if the handler
1253 calls something else (because we don't know what *that* function
1254 might do), but try to be a bit smarter if the handler is a leaf
1255 function. We always save $a0, though, because we use that in the
85f65093 1256 epilogue to copy $fb to $sp. */
38b2d076
DD		 1257static int
1258need_to_save (int regno)
1259{
1260 if (fixed_regs[regno])
1261 return 0;
ad516a74 1262 if (crtl->calls_eh_return)
38b2d076
DD		 1263 return 1;
1264 if (regno == FP_REGNO)
1265 return 0;
1266 if (cfun->machine->is_interrupt
65655f79
DD		 1267 && (!cfun->machine->is_leaf
1268 || (regno == A0_REGNO
1269 && m32c_function_needs_enter ())
1270 ))
38b2d076 1271 return 1;
6fb5fa3c 1272 if (df_regs_ever_live_p (regno)
38b2d076
DD		 1273 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1274 return 1;
1275 return 0;
1276}
1277
1278/* This function contains all the intelligence about saving and
1279 restoring registers. It always figures out the register save set.
1280 When called with PP_justcount, it merely returns the size of the
1281 save set (for eliminating the frame pointer, for example). When
1282 called with PP_pushm or PP_popm, it emits the appropriate
1283 instructions for saving (pushm) or restoring (popm) the
1284 registers. */
1285static int
1286m32c_pushm_popm (Push_Pop_Type ppt)
1287{
1288 int reg_mask = 0;
1289 int byte_count = 0, bytes;
1290 int i;
1291 rtx dwarf_set[PUSHM_N];
1292 int n_dwarfs = 0;
1293 int nosave_mask = 0;
1294
305da3ec
JH		 1295 if (crtl->return_rtx
1296 && GET_CODE (crtl->return_rtx) == PARALLEL
ad516a74 1297 && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
38b2d076 1298 {
305da3ec 1299 rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
38b2d076
DD		 1300 rtx rv = XEXP (exp, 0);
1301 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1302
1303 if (rv_bytes > 2)
1304 nosave_mask |= 0x20; /* PSI, SI */
1305 else
1306 nosave_mask |= 0xf0; /* DF */
1307 if (rv_bytes > 4)
1308 nosave_mask |= 0x50; /* DI */
1309 }
1310
1311 for (i = 0; i < (int) PUSHM_N; i++)
1312 {
1313 /* Skip if neither register needs saving. */
1314 if (!need_to_save (pushm_info[i].reg1))
1315 continue;
1316
1317 if (pushm_info[i].bit & nosave_mask)
1318 continue;
1319
1320 reg_mask |= pushm_info[i].bit;
1321 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1322
1323 if (ppt == PP_pushm)
1324 {
1325 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1326 rtx addr;
1327
1328 /* Always use stack_pointer_rtx instead of calling
1329 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1330 that there is a single rtx representing the stack pointer,
1331 namely stack_pointer_rtx, and uses == to recognize it. */
1332 addr = stack_pointer_rtx;
1333
1334 if (byte_count != 0)
1335 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1336
1337 dwarf_set[n_dwarfs++] =
1338 gen_rtx_SET (VOIDmode,
1339 gen_rtx_MEM (mode, addr),
1340 gen_rtx_REG (mode, pushm_info[i].reg1));
1341 F (dwarf_set[n_dwarfs - 1]);
1342
1343 }
1344 byte_count += bytes;
1345 }
1346
1347 if (cfun->machine->is_interrupt)
1348 {
1349 cfun->machine->intr_pushm = reg_mask & 0xfe;
1350 reg_mask = 0;
1351 byte_count = 0;
1352 }
1353
1354 if (cfun->machine->is_interrupt)
1355 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1356 if (need_to_save (i))
1357 {
1358 byte_count += 2;
1359 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1360 }
1361
1362 if (ppt == PP_pushm && byte_count)
1363 {
1364 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1365 rtx pushm;
1366
1367 if (reg_mask)
1368 {
1369 XVECEXP (note, 0, 0)
1370 = gen_rtx_SET (VOIDmode,
1371 stack_pointer_rtx,
1372 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1373 stack_pointer_rtx,
1374 GEN_INT (-byte_count)));
1375 F (XVECEXP (note, 0, 0));
1376
1377 for (i = 0; i < n_dwarfs; i++)
1378 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1379
1380 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1381
1382 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1383 REG_NOTES (pushm));
1384 }
1385
1386 if (cfun->machine->is_interrupt)
1387 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1388 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1389 {
1390 if (TARGET_A16)
1391 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1392 else
1393 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1394 F (pushm);
1395 }
1396 }
1397 if (ppt == PP_popm && byte_count)
1398 {
38b2d076
DD		 1399 if (cfun->machine->is_interrupt)
1400 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1401 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1402 {
1403 if (TARGET_A16)
b3fdec9e 1404 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
38b2d076 1405 else
b3fdec9e 1406 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
38b2d076
DD		 1407 }
1408 if (reg_mask)
1409 emit_insn (gen_popm (GEN_INT (reg_mask)));
1410 }
1411
1412 return byte_count;
1413}
1414
1415/* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1416 diagrams our call frame. */
1417int
1418m32c_initial_elimination_offset (int from, int to)
1419{
1420 int ofs = 0;
1421
1422 if (from == AP_REGNO)
1423 {
1424 if (TARGET_A16)
1425 ofs += 5;
1426 else
1427 ofs += 8;
1428 }
1429
1430 if (to == SP_REGNO)
1431 {
1432 ofs += m32c_pushm_popm (PP_justcount);
1433 ofs += get_frame_size ();
1434 }
1435
1436 /* Account for push rounding. */
1437 if (TARGET_A24)
1438 ofs = (ofs + 1) & ~1;
1439#if DEBUG0
1440 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1441 to, ofs);
1442#endif
1443 return ofs;
1444}
1445
1446/* Passing Function Arguments on the Stack */
1447
38b2d076
DD		 1448/* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1449 M32C has word stacks. */
1450int
1451m32c_push_rounding (int n)
1452{
1453 if (TARGET_R8C || TARGET_M16C)
1454 return n;
1455 return (n + 1) & ~1;
1456}
1457
1458/* Passing Arguments in Registers */
1459
1460/* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1461 partly on stack. If our function returns a struct, a pointer to a
1462 buffer for it is at the top of the stack (last thing pushed). The
1463 first few real arguments may be in registers as follows:
1464
1465 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1466 arg2 in r2 if it's HI (else pushed on stack)
1467 rest on stack
1468 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1469 rest on stack
1470
1471 Structs are not passed in registers, even if they fit. Only
1472 integer and pointer types are passed in registers.
1473
1474 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1475 r2 if it fits. */
1476rtx
1477m32c_function_arg (CUMULATIVE_ARGS * ca,
1478 enum machine_mode mode, tree type, int named)
1479{
1480 /* Can return a reg, parallel, or 0 for stack */
1481 rtx rv = NULL_RTX;
1482#if DEBUG0
1483 fprintf (stderr, "func_arg %d (%s, %d)\n",
1484 ca->parm_num, mode_name[mode], named);
1485 debug_tree (type);
1486#endif
1487
1488 if (mode == VOIDmode)
1489 return GEN_INT (0);
1490
1491 if (ca->force_mem || !named)
1492 {
1493#if DEBUG0
1494 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1495 named);
1496#endif
1497 return NULL_RTX;
1498 }
1499
1500 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1501 return NULL_RTX;
1502
9d746d5e
DD		 1503 if (type && AGGREGATE_TYPE_P (type))
1504 return NULL_RTX;
1505
38b2d076
DD		 1506 switch (ca->parm_num)
1507 {
1508 case 1:
1509 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1510 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1511 break;
1512
1513 case 2:
1514 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1515 rv = gen_rtx_REG (mode, R2_REGNO);
1516 break;
1517 }
1518
1519#if DEBUG0
1520 debug_rtx (rv);
1521#endif
1522 return rv;
1523}
1524
1525#undef TARGET_PASS_BY_REFERENCE
1526#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1527static bool
1528m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1529 enum machine_mode mode ATTRIBUTE_UNUSED,
586de218 1530 const_tree type ATTRIBUTE_UNUSED,
38b2d076
DD		 1531 bool named ATTRIBUTE_UNUSED)
1532{
1533 return 0;
1534}
1535
1536/* Implements INIT_CUMULATIVE_ARGS. */
1537void
1538m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
9d746d5e 1539 tree fntype,
38b2d076 1540 rtx libname ATTRIBUTE_UNUSED,
9d746d5e 1541 tree fndecl,
38b2d076
DD		 1542 int n_named_args ATTRIBUTE_UNUSED)
1543{
9d746d5e
DD		 1544 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1545 ca->force_mem = 1;
1546 else
1547 ca->force_mem = 0;
38b2d076
DD		 1548 ca->parm_num = 1;
1549}
1550
1551/* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1552 returning structures, so we always reset that. Otherwise, we only
1553 need to know the sequence number of the argument to know what to do
1554 with it. */
1555void
1556m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1557 enum machine_mode mode ATTRIBUTE_UNUSED,
1558 tree type ATTRIBUTE_UNUSED,
1559 int named ATTRIBUTE_UNUSED)
1560{
1561 if (ca->force_mem)
1562 ca->force_mem = 0;
9d746d5e
DD		 1563 else
1564 ca->parm_num++;
38b2d076
DD		 1565}
1566
1567/* Implements FUNCTION_ARG_REGNO_P. */
1568int
1569m32c_function_arg_regno_p (int r)
1570{
1571 if (TARGET_A24)
1572 return (r == R0_REGNO);
1573 return (r == R1_REGNO || r == R2_REGNO);
1574}
1575
e9555b13 1576/* HImode and PSImode are the two "native" modes as far as GCC is
85f65093 1577 concerned, but the chips also support a 32-bit mode which is used
e9555b13
DD		 1578 for some opcodes in R8C/M16C and for reset vectors and such. */
1579#undef TARGET_VALID_POINTER_MODE
1580#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
23fed240 1581static bool
e9555b13
DD		 1582m32c_valid_pointer_mode (enum machine_mode mode)
1583{
e9555b13
DD		 1584 if (mode == HImode
1585 || mode == PSImode
1586 || mode == SImode
1587 )
1588 return 1;
1589 return 0;
1590}
1591
38b2d076
DD		 1592/* How Scalar Function Values Are Returned */
1593
1594/* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1595 combination of registers starting there (r2r0 for longs, r3r1r2r0
1596 for long long, r3r2r1r0 for doubles), except that that ABI
1597 currently doesn't work because it ends up using all available
1598 general registers and gcc often can't compile it. So, instead, we
1599 return anything bigger than 16 bits in "mem0" (effectively, a
1600 memory location). */
1601rtx
1602m32c_libcall_value (enum machine_mode mode)
1603{
1604 /* return reg or parallel */
1605#if 0
1606 /* FIXME: GCC has difficulty returning large values in registers,
1607 because that ties up most of the general registers and gives the
1608 register allocator little to work with. Until we can resolve
1609 this, large values are returned in memory. */
1610 if (mode == DFmode)
1611 {
1612 rtx rv;
1613
1614 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1615 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1616 gen_rtx_REG (HImode,
1617 R0_REGNO),
1618 GEN_INT (0));
1619 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1620 gen_rtx_REG (HImode,
1621 R1_REGNO),
1622 GEN_INT (2));
1623 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1624 gen_rtx_REG (HImode,
1625 R2_REGNO),
1626 GEN_INT (4));
1627 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1628 gen_rtx_REG (HImode,
1629 R3_REGNO),
1630 GEN_INT (6));
1631 return rv;
1632 }
1633
1634 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1635 {
1636 rtx rv;
1637
1638 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1639 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1640 gen_rtx_REG (mode,
1641 R0_REGNO),
1642 GEN_INT (0));
1643 return rv;
1644 }
1645#endif
1646
1647 if (GET_MODE_SIZE (mode) > 2)
1648 return gen_rtx_REG (mode, MEM0_REGNO);
1649 return gen_rtx_REG (mode, R0_REGNO);
1650}
1651
1652/* Implements FUNCTION_VALUE. Functions and libcalls have the same
1653 conventions. */
1654rtx
586de218 1655m32c_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
38b2d076
DD		 1656{
1657 /* return reg or parallel */
586de218 1658 const enum machine_mode mode = TYPE_MODE (valtype);
38b2d076
DD		 1659 return m32c_libcall_value (mode);
1660}
1661
1662/* How Large Values Are Returned */
1663
1664/* We return structures by pushing the address on the stack, even if
1665 we use registers for the first few "real" arguments. */
1666#undef TARGET_STRUCT_VALUE_RTX
1667#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1668static rtx
1669m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1670 int incoming ATTRIBUTE_UNUSED)
1671{
1672 return 0;
1673}
1674
1675/* Function Entry and Exit */
1676
1677/* Implements EPILOGUE_USES. Interrupts restore all registers. */
1678int
1679m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1680{
1681 if (cfun->machine->is_interrupt)
1682 return 1;
1683 return 0;
1684}
1685
1686/* Implementing the Varargs Macros */
1687
1688#undef TARGET_STRICT_ARGUMENT_NAMING
1689#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1690static bool
1691m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1692{
1693 return 1;
1694}
1695
1696/* Trampolines for Nested Functions */
1697
1698/*
1699 m16c:
1700 1 0000 75C43412 mov.w #0x1234,a0
1701 2 0004 FC000000 jmp.a label
1702
1703 m32c:
1704 1 0000 BC563412 mov.l:s #0x123456,a0
1705 2 0004 CC000000 jmp.a label
1706*/
1707
1708/* Implements TRAMPOLINE_SIZE. */
1709int
1710m32c_trampoline_size (void)
1711{
1712 /* Allocate extra space so we can avoid the messy shifts when we
1713 initialize the trampoline; we just write past the end of the
1714 opcode. */
1715 return TARGET_A16 ? 8 : 10;
1716}
1717
1718/* Implements TRAMPOLINE_ALIGNMENT. */
1719int
1720m32c_trampoline_alignment (void)
1721{
1722 return 2;
1723}
1724
229fbccb
RH		 1725/* Implements TARGET_TRAMPOLINE_INIT. */
1726
1727#undef TARGET_TRAMPOLINE_INIT
1728#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1729static void
1730m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
38b2d076 1731{
229fbccb
RH		 1732 rtx function = XEXP (DECL_RTL (fndecl), 0);
1733
1734#define A0(m,i) adjust_address (m_tramp, m, i)
38b2d076
DD		 1735 if (TARGET_A16)
1736 {
1737 /* Note: we subtract a "word" because the moves want signed
1738 constants, not unsigned constants. */
1739 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1740 emit_move_insn (A0 (HImode, 2), chainval);
1741 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
85f65093
KH		 1742 /* We use 16-bit addresses here, but store the zero to turn it
1743 into a 24-bit offset. */
38b2d076
DD		 1744 emit_move_insn (A0 (HImode, 5), function);
1745 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1746 }
1747 else
1748 {
1749 /* Note that the PSI moves actually write 4 bytes. Make sure we
1750 write stuff out in the right order, and leave room for the
1751 extra byte at the end. */
1752 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1753 emit_move_insn (A0 (PSImode, 1), chainval);
1754 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1755 emit_move_insn (A0 (PSImode, 5), function);
1756 }
1757#undef A0
1758}
1759
07127a0a
DD		 1760/* Implicit Calls to Library Routines */
1761
1762#undef TARGET_INIT_LIBFUNCS
1763#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1764static void
1765m32c_init_libfuncs (void)
1766{
f90b7a5a
PB		 1767 /* We do this because the M32C has an HImode operand, but the
1768 M16C has an 8-bit operand. Since gcc looks at the match data
1769 and not the expanded rtl, we have to reset the optab so that
1770 the right modes are found. */
07127a0a
DD		 1771 if (TARGET_A24)
1772 {
f90b7a5a
PB		 1773 optab_handler (cstore_optab, QImode)->insn_code = CODE_FOR_cstoreqi4_24;
1774 optab_handler (cstore_optab, HImode)->insn_code = CODE_FOR_cstorehi4_24;
1775 optab_handler (cstore_optab, PSImode)->insn_code = CODE_FOR_cstorepsi4_24;
07127a0a
DD		 1776 }
1777}
1778
38b2d076
DD		 1779/* Addressing Modes */
1780
c6c3dba9
PB		 1781/* The r8c/m32c family supports a wide range of non-orthogonal
1782 addressing modes, including the ability to double-indirect on *some*
1783 of them. Not all insns support all modes, either, but we rely on
1784 predicates and constraints to deal with that. */
1785#undef TARGET_LEGITIMATE_ADDRESS_P
1786#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1787bool
1788m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
38b2d076
DD		 1789{
1790 int mode_adjust;
1791 if (CONSTANT_P (x))
1792 return 1;
1793
1794 /* Wide references to memory will be split after reload, so we must
1795 ensure that all parts of such splits remain legitimate
1796 addresses. */
1797 mode_adjust = GET_MODE_SIZE (mode) - 1;
1798
1799 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1800 if (GET_CODE (x) == PRE_DEC
1801 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1802 {
1803 return (GET_CODE (XEXP (x, 0)) == REG
1804 && REGNO (XEXP (x, 0)) == SP_REGNO);
1805 }
1806
1807#if 0
1808 /* This is the double indirection detection, but it currently
1809 doesn't work as cleanly as this code implies, so until we've had
1810 a chance to debug it, leave it disabled. */
1811 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1812 {
1813#if DEBUG_DOUBLE
1814 fprintf (stderr, "double indirect\n");
1815#endif
1816 x = XEXP (x, 0);
1817 }
1818#endif
1819
1820 encode_pattern (x);
1821 if (RTX_IS ("r"))
1822 {
1823 /* Most indexable registers can be used without displacements,
1824 although some of them will be emitted with an explicit zero
1825 to please the assembler. */
1826 switch (REGNO (patternr[0]))
1827 {
1828 case A0_REGNO:
1829 case A1_REGNO:
1830 case SB_REGNO:
1831 case FB_REGNO:
1832 case SP_REGNO:
1833 return 1;
1834
1835 default:
1836 if (IS_PSEUDO (patternr[0], strict))
1837 return 1;
1838 return 0;
1839 }
1840 }
1841 if (RTX_IS ("+ri"))
1842 {
1843 /* This is more interesting, because different base registers
1844 allow for different displacements - both range and signedness
1845 - and it differs from chip series to chip series too. */
1846 int rn = REGNO (patternr[1]);
1847 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1848 switch (rn)
1849 {
1850 case A0_REGNO:
1851 case A1_REGNO:
1852 case SB_REGNO:
1853 /* The syntax only allows positive offsets, but when the
1854 offsets span the entire memory range, we can simulate
1855 negative offsets by wrapping. */
1856 if (TARGET_A16)
1857 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1858 if (rn == SB_REGNO)
1859 return (offs >= 0 && offs <= 65535 - mode_adjust);
1860 /* A0 or A1 */
1861 return (offs >= -16777216 && offs <= 16777215);
1862
1863 case FB_REGNO:
1864 if (TARGET_A16)
1865 return (offs >= -128 && offs <= 127 - mode_adjust);
1866 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1867
1868 case SP_REGNO:
1869 return (offs >= -128 && offs <= 127 - mode_adjust);
1870
1871 default:
1872 if (IS_PSEUDO (patternr[1], strict))
1873 return 1;
1874 return 0;
1875 }
1876 }
1877 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1878 {
1879 rtx reg = patternr[1];
1880
1881 /* We don't know where the symbol is, so only allow base
1882 registers which support displacements spanning the whole
1883 address range. */
1884 switch (REGNO (reg))
1885 {
1886 case A0_REGNO:
1887 case A1_REGNO:
1888 /* $sb needs a secondary reload, but since it's involved in
1889 memory address reloads too, we don't deal with it very
1890 well. */
1891 /* case SB_REGNO: */
1892 return 1;
1893 default:
1894 if (IS_PSEUDO (reg, strict))
1895 return 1;
1896 return 0;
1897 }
1898 }
1899 return 0;
1900}
1901
1902/* Implements REG_OK_FOR_BASE_P. */
1903int
1904m32c_reg_ok_for_base_p (rtx x, int strict)
1905{
1906 if (GET_CODE (x) != REG)
1907 return 0;
1908 switch (REGNO (x))
1909 {
1910 case A0_REGNO:
1911 case A1_REGNO:
1912 case SB_REGNO:
1913 case FB_REGNO:
1914 case SP_REGNO:
1915 return 1;
1916 default:
1917 if (IS_PSEUDO (x, strict))
1918 return 1;
1919 return 0;
1920 }
1921}
1922
04aff2c0 1923/* We have three choices for choosing fb->aN offsets. If we choose -128,
85f65093 1924 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
04aff2c0
DD		 1925 like this:
1926 EB 4B FF mova -128[$fb],$a0
1927 D8 0C FF FF mov.w:Q #0,-1[$a0]
1928
85f65093 1929 Alternately, we subtract the frame size, and hopefully use 8-bit aN
04aff2c0
DD		 1930 displacements:
1931 7B F4 stc $fb,$a0
1932 77 54 00 01 sub #256,$a0
1933 D8 08 01 mov.w:Q #0,1[$a0]
1934
1935 If we don't offset (i.e. offset by zero), we end up with:
1936 7B F4 stc $fb,$a0
1937 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1938
1939 We have to subtract *something* so that we have a PLUS rtx to mark
1940 that we've done this reload. The -128 offset will never result in
85f65093 1941 an 8-bit aN offset, and the payoff for the second case is five
04aff2c0
DD		 1942 loads *if* those loads are within 256 bytes of the other end of the
1943 frame, so the third case seems best. Note that we subtract the
1944 zero, but detect that in the addhi3 pattern. */
1945
ea471af0
JM		 1946#define BIG_FB_ADJ 0
1947
38b2d076
DD		 1948/* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1949 worry about is frame base offsets, as $fb has a limited
1950 displacement range. We deal with this by attempting to reload $fb
1951 itself into an address register; that seems to result in the best
1952 code. */
506d7b68
PB		 1953#undef TARGET_LEGITIMIZE_ADDRESS
1954#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
1955static rtx
1956m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1957 enum machine_mode mode)
38b2d076
DD		 1958{
1959#if DEBUG0
1960 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
506d7b68 1961 debug_rtx (x);
38b2d076
DD		 1962 fprintf (stderr, "\n");
1963#endif
1964
506d7b68
PB		 1965 if (GET_CODE (x) == PLUS
1966 && GET_CODE (XEXP (x, 0)) == REG
1967 && REGNO (XEXP (x, 0)) == FB_REGNO
1968 && GET_CODE (XEXP (x, 1)) == CONST_INT
1969 && (INTVAL (XEXP (x, 1)) < -128
1970 || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
38b2d076
DD		 1971 {
1972 /* reload FB to A_REGS */
38b2d076 1973 rtx temp = gen_reg_rtx (Pmode);
506d7b68
PB		 1974 x = copy_rtx (x);
1975 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
1976 XEXP (x, 0) = temp;
38b2d076
DD		 1977 }
1978
506d7b68 1979 return x;
38b2d076
DD		 1980}
1981
1982/* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1983int
1984m32c_legitimize_reload_address (rtx * x,
1985 enum machine_mode mode,
1986 int opnum,
1987 int type, int ind_levels ATTRIBUTE_UNUSED)
1988{
1989#if DEBUG0
1990 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1991 mode_name[mode]);
1992 debug_rtx (*x);
1993#endif
1994
1995 /* At one point, this function tried to get $fb copied to an address
1996 register, which in theory would maximize sharing, but gcc was
1997 *also* still trying to reload the whole address, and we'd run out
1998 of address registers. So we let gcc do the naive (but safe)
1999 reload instead, when the above function doesn't handle it for
04aff2c0
DD		 2000 us.
2001
2002 The code below is a second attempt at the above. */
2003
2004 if (GET_CODE (*x) == PLUS
2005 && GET_CODE (XEXP (*x, 0)) == REG
2006 && REGNO (XEXP (*x, 0)) == FB_REGNO
2007 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2008 && (INTVAL (XEXP (*x, 1)) < -128
2009 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2010 {
2011 rtx sum;
2012 int offset = INTVAL (XEXP (*x, 1));
2013 int adjustment = -BIG_FB_ADJ;
2014
2015 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2016 GEN_INT (adjustment));
2017 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2018 if (type == RELOAD_OTHER)
2019 type = RELOAD_FOR_OTHER_ADDRESS;
2020 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2021 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2022 type);
2023 return 1;
2024 }
2025
2026 if (GET_CODE (*x) == PLUS
2027 && GET_CODE (XEXP (*x, 0)) == PLUS
2028 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2029 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2030 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2031 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2032 )
2033 {
2034 if (type == RELOAD_OTHER)
2035 type = RELOAD_FOR_OTHER_ADDRESS;
2036 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2037 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2038 type);
2039 return 1;
2040 }
38b2d076
DD		 2041
2042 return 0;
2043}
2044
38b2d076
DD		 2045/* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2046 so we can allow anything. */
2047int
2048m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2049{
2050 return 1;
2051}
2052
2053
2054/* Condition Code Status */
2055
2056#undef TARGET_FIXED_CONDITION_CODE_REGS
2057#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2058static bool
2059m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2060{
2061 *p1 = FLG_REGNO;
2062 *p2 = INVALID_REGNUM;
2063 return true;
2064}
2065
2066/* Describing Relative Costs of Operations */
2067
2068/* Implements REGISTER_MOVE_COST. We make impossible moves
2069 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2070 no opcodes to do that). We also discourage use of mem* registers
2071 since they're really memory. */
2072int
2073m32c_register_move_cost (enum machine_mode mode, int from, int to)
2074{
2075 int cost = COSTS_N_INSNS (3);
2076 int cc = class_contents[from][0] | class_contents[to][0];
2077 /* FIXME: pick real values, but not 2 for now. */
2078 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
2079 {
2080 if (!(cc & ~class_contents[R23_REGS][0]))
2081 cost = COSTS_N_INSNS (1000);
2082 else
2083 cost = COSTS_N_INSNS (80);
2084 }
2085
2086 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2087 cost = COSTS_N_INSNS (1000);
2088
2089 if (classes_intersect (from, CR_REGS))
2090 cost += COSTS_N_INSNS (5);
2091
2092 if (classes_intersect (to, CR_REGS))
2093 cost += COSTS_N_INSNS (5);
2094
2095 if (from == MEM_REGS || to == MEM_REGS)
2096 cost += COSTS_N_INSNS (50);
2097 else if (classes_intersect (from, MEM_REGS)
2098 || classes_intersect (to, MEM_REGS))
2099 cost += COSTS_N_INSNS (10);
2100
2101#if DEBUG0
2102 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
2103 mode_name[mode], class_names[from], class_names[to], cost);
2104#endif
2105 return cost;
2106}
2107
2108/* Implements MEMORY_MOVE_COST. */
2109int
2110m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2111 int reg_class ATTRIBUTE_UNUSED,
2112 int in ATTRIBUTE_UNUSED)
2113{
2114 /* FIXME: pick real values. */
2115 return COSTS_N_INSNS (10);
2116}
2117
07127a0a
DD		 2118/* Here we try to describe when we use multiple opcodes for one RTX so
2119 that gcc knows when to use them. */
2120#undef TARGET_RTX_COSTS
2121#define TARGET_RTX_COSTS m32c_rtx_costs
2122static bool
f40751dd
JH		 2123m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
2124 bool speed ATTRIBUTE_UNUSED)
07127a0a
DD		 2125{
2126 switch (code)
2127 {
2128 case REG:
2129 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2130 *total += COSTS_N_INSNS (500);
2131 else
2132 *total += COSTS_N_INSNS (1);
2133 return true;
2134
2135 case ASHIFT:
2136 case LSHIFTRT:
2137 case ASHIFTRT:
2138 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2139 {
2140 /* mov.b r1l, r1h */
2141 *total += COSTS_N_INSNS (1);
2142 return true;
2143 }
2144 if (INTVAL (XEXP (x, 1)) > 8
2145 || INTVAL (XEXP (x, 1)) < -8)
2146 {
2147 /* mov.b #N, r1l */
2148 /* mov.b r1l, r1h */
2149 *total += COSTS_N_INSNS (2);
2150 return true;
2151 }
2152 return true;
2153
2154 case LE:
2155 case LEU:
2156 case LT:
2157 case LTU:
2158 case GT:
2159 case GTU:
2160 case GE:
2161 case GEU:
2162 case NE:
2163 case EQ:
2164 if (outer_code == SET)
2165 {
2166 *total += COSTS_N_INSNS (2);
2167 return true;
2168 }
2169 break;
2170
2171 case ZERO_EXTRACT:
2172 {
2173 rtx dest = XEXP (x, 0);
2174 rtx addr = XEXP (dest, 0);
2175 switch (GET_CODE (addr))
2176 {
2177 case CONST_INT:
2178 *total += COSTS_N_INSNS (1);
2179 break;
2180 case SYMBOL_REF:
2181 *total += COSTS_N_INSNS (3);
2182 break;
2183 default:
2184 *total += COSTS_N_INSNS (2);
2185 break;
2186 }
2187 return true;
2188 }
2189 break;
2190
2191 default:
2192 /* Reasonable default. */
2193 if (TARGET_A16 && GET_MODE(x) == SImode)
2194 *total += COSTS_N_INSNS (2);
2195 break;
2196 }
2197 return false;
2198}
2199
2200#undef TARGET_ADDRESS_COST
2201#define TARGET_ADDRESS_COST m32c_address_cost
2202static int
f40751dd 2203m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
07127a0a 2204{
80b093df 2205 int i;
07127a0a
DD		 2206 /* fprintf(stderr, "\naddress_cost\n");
2207 debug_rtx(addr);*/
2208 switch (GET_CODE (addr))
2209 {
2210 case CONST_INT:
80b093df
DD		 2211 i = INTVAL (addr);
2212 if (i == 0)
2213 return COSTS_N_INSNS(1);
2214 if (0 < i && i <= 255)
2215 return COSTS_N_INSNS(2);
2216 if (0 < i && i <= 65535)
2217 return COSTS_N_INSNS(3);
2218 return COSTS_N_INSNS(4);
07127a0a 2219 case SYMBOL_REF:
80b093df 2220 return COSTS_N_INSNS(4);
07127a0a 2221 case REG:
80b093df
DD		 2222 return COSTS_N_INSNS(1);
2223 case PLUS:
2224 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2225 {
2226 i = INTVAL (XEXP (addr, 1));
2227 if (i == 0)
2228 return COSTS_N_INSNS(1);
2229 if (0 < i && i <= 255)
2230 return COSTS_N_INSNS(2);
2231 if (0 < i && i <= 65535)
2232 return COSTS_N_INSNS(3);
2233 }
2234 return COSTS_N_INSNS(4);
07127a0a
DD		 2235 default:
2236 return 0;
2237 }
2238}
2239
38b2d076
DD		 2240/* Defining the Output Assembler Language */
2241
2242/* The Overall Framework of an Assembler File */
2243
2244#undef TARGET_HAVE_NAMED_SECTIONS
2245#define TARGET_HAVE_NAMED_SECTIONS true
2246
2247/* Output of Data */
2248
2249/* We may have 24 bit sizes, which is the native address size.
2250 Currently unused, but provided for completeness. */
2251#undef TARGET_ASM_INTEGER
2252#define TARGET_ASM_INTEGER m32c_asm_integer
2253static bool
2254m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2255{
2256 switch (size)
2257 {
2258 case 3:
2259 fprintf (asm_out_file, "\t.3byte\t");
2260 output_addr_const (asm_out_file, x);
2261 fputc ('\n', asm_out_file);
2262 return true;
e9555b13
DD		 2263 case 4:
2264 if (GET_CODE (x) == SYMBOL_REF)
2265 {
2266 fprintf (asm_out_file, "\t.long\t");
2267 output_addr_const (asm_out_file, x);
2268 fputc ('\n', asm_out_file);
2269 return true;
2270 }
2271 break;
38b2d076
DD		 2272 }
2273 return default_assemble_integer (x, size, aligned_p);
2274}
2275
2276/* Output of Assembler Instructions */
2277
a4174ebf 2278/* We use a lookup table because the addressing modes are non-orthogonal. */
38b2d076
DD		 2279
2280static struct
2281{
2282 char code;
2283 char const *pattern;
2284 char const *format;
2285}
2286const conversions[] = {
2287 { 0, "r", "0" },
2288
2289 { 0, "mr", "z[1]" },
2290 { 0, "m+ri", "3[2]" },
2291 { 0, "m+rs", "3[2]" },
2292 { 0, "m+r+si", "4+5[2]" },
2293 { 0, "ms", "1" },
2294 { 0, "mi", "1" },
2295 { 0, "m+si", "2+3" },
2296
2297 { 0, "mmr", "[z[2]]" },
2298 { 0, "mm+ri", "[4[3]]" },
2299 { 0, "mm+rs", "[4[3]]" },
2300 { 0, "mm+r+si", "[5+6[3]]" },
2301 { 0, "mms", "[[2]]" },
2302 { 0, "mmi", "[[2]]" },
2303 { 0, "mm+si", "[4[3]]" },
2304
2305 { 0, "i", "#0" },
2306 { 0, "s", "#0" },
2307 { 0, "+si", "#1+2" },
2308 { 0, "l", "#0" },
2309
2310 { 'l', "l", "0" },
2311 { 'd', "i", "0" },
2312 { 'd', "s", "0" },
2313 { 'd', "+si", "1+2" },
2314 { 'D', "i", "0" },
2315 { 'D', "s", "0" },
2316 { 'D', "+si", "1+2" },
2317 { 'x', "i", "#0" },
2318 { 'X', "i", "#0" },
2319 { 'm', "i", "#0" },
2320 { 'b', "i", "#0" },
07127a0a 2321 { 'B', "i", "0" },
38b2d076
DD		 2322 { 'p', "i", "0" },
2323
2324 { 0, 0, 0 }
2325};
2326
2327/* This is in order according to the bitfield that pushm/popm use. */
2328static char const *pushm_regs[] = {
2329 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2330};
2331
2332/* Implements PRINT_OPERAND. */
2333void
2334m32c_print_operand (FILE * file, rtx x, int code)
2335{
2336 int i, j, b;
2337 const char *comma;
2338 HOST_WIDE_INT ival;
2339 int unsigned_const = 0;
ff485e71 2340 int force_sign;
38b2d076
DD		 2341
2342 /* Multiplies; constants are converted to sign-extended format but
2343 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2344 need. */
2345 if (code == 'u')
2346 {
2347 unsigned_const = 2;
2348 code = 0;
2349 }
2350 if (code == 'U')
2351 {
2352 unsigned_const = 1;
2353 code = 0;
2354 }
2355 /* This one is only for debugging; you can put it in a pattern to
2356 force this error. */
2357 if (code == '!')
2358 {
2359 fprintf (stderr, "dj: unreviewed pattern:");
2360 if (current_output_insn)
2361 debug_rtx (current_output_insn);
2362 gcc_unreachable ();
2363 }
2364 /* PSImode operations are either .w or .l depending on the target. */
2365 if (code == '&')
2366 {
2367 if (TARGET_A16)
2368 fprintf (file, "w");
2369 else
2370 fprintf (file, "l");
2371 return;
2372 }
2373 /* Inverted conditionals. */
2374 if (code == 'C')
2375 {
2376 switch (GET_CODE (x))
2377 {
2378 case LE:
2379 fputs ("gt", file);
2380 break;
2381 case LEU:
2382 fputs ("gtu", file);
2383 break;
2384 case LT:
2385 fputs ("ge", file);
2386 break;
2387 case LTU:
2388 fputs ("geu", file);
2389 break;
2390 case GT:
2391 fputs ("le", file);
2392 break;
2393 case GTU:
2394 fputs ("leu", file);
2395 break;
2396 case GE:
2397 fputs ("lt", file);
2398 break;
2399 case GEU:
2400 fputs ("ltu", file);
2401 break;
2402 case NE:
2403 fputs ("eq", file);
2404 break;
2405 case EQ:
2406 fputs ("ne", file);
2407 break;
2408 default:
2409 gcc_unreachable ();
2410 }
2411 return;
2412 }
2413 /* Regular conditionals. */
2414 if (code == 'c')
2415 {
2416 switch (GET_CODE (x))
2417 {
2418 case LE:
2419 fputs ("le", file);
2420 break;
2421 case LEU:
2422 fputs ("leu", file);
2423 break;
2424 case LT:
2425 fputs ("lt", file);
2426 break;
2427 case LTU:
2428 fputs ("ltu", file);
2429 break;
2430 case GT:
2431 fputs ("gt", file);
2432 break;
2433 case GTU:
2434 fputs ("gtu", file);
2435 break;
2436 case GE:
2437 fputs ("ge", file);
2438 break;
2439 case GEU:
2440 fputs ("geu", file);
2441 break;
2442 case NE:
2443 fputs ("ne", file);
2444 break;
2445 case EQ:
2446 fputs ("eq", file);
2447 break;
2448 default:
2449 gcc_unreachable ();
2450 }
2451 return;
2452 }
2453 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2454 operand. */
2455 if (code == 'h' && GET_MODE (x) == SImode)
2456 {
2457 x = m32c_subreg (HImode, x, SImode, 0);
2458 code = 0;
2459 }
2460 if (code == 'H' && GET_MODE (x) == SImode)
2461 {
2462 x = m32c_subreg (HImode, x, SImode, 2);
2463 code = 0;
2464 }
07127a0a
DD		 2465 if (code == 'h' && GET_MODE (x) == HImode)
2466 {
2467 x = m32c_subreg (QImode, x, HImode, 0);
2468 code = 0;
2469 }
2470 if (code == 'H' && GET_MODE (x) == HImode)
2471 {
2472 /* We can't actually represent this as an rtx. Do it here. */
2473 if (GET_CODE (x) == REG)
2474 {
2475 switch (REGNO (x))
2476 {
2477 case R0_REGNO:
2478 fputs ("r0h", file);
2479 return;
2480 case R1_REGNO:
2481 fputs ("r1h", file);
2482 return;
2483 default:
2484 gcc_unreachable();
2485 }
2486 }
2487 /* This should be a MEM. */
2488 x = m32c_subreg (QImode, x, HImode, 1);
2489 code = 0;
2490 }
2491 /* This is for BMcond, which always wants word register names. */
2492 if (code == 'h' && GET_MODE (x) == QImode)
2493 {
2494 if (GET_CODE (x) == REG)
2495 x = gen_rtx_REG (HImode, REGNO (x));
2496 code = 0;
2497 }
38b2d076
DD		 2498 /* 'x' and 'X' need to be ignored for non-immediates. */
2499 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2500 code = 0;
2501
2502 encode_pattern (x);
ff485e71 2503 force_sign = 0;
38b2d076
DD		 2504 for (i = 0; conversions[i].pattern; i++)
2505 if (conversions[i].code == code
2506 && streq (conversions[i].pattern, pattern))
2507 {
2508 for (j = 0; conversions[i].format[j]; j++)
2509 /* backslash quotes the next character in the output pattern. */
2510 if (conversions[i].format[j] == '\\')
2511 {
2512 fputc (conversions[i].format[j + 1], file);
2513 j++;
2514 }
2515 /* Digits in the output pattern indicate that the
2516 corresponding RTX is to be output at that point. */
2517 else if (ISDIGIT (conversions[i].format[j]))
2518 {
2519 rtx r = patternr[conversions[i].format[j] - '0'];
2520 switch (GET_CODE (r))
2521 {
2522 case REG:
2523 fprintf (file, "%s",
2524 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2525 break;
2526 case CONST_INT:
2527 switch (code)
2528 {
2529 case 'b':
07127a0a
DD		 2530 case 'B':
2531 {
2532 int v = INTVAL (r);
2533 int i = (int) exact_log2 (v);
2534 if (i == -1)
2535 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2536 if (i == -1)
2537 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2538 /* Bit position. */
2539 fprintf (file, "%d", i);
2540 }
38b2d076
DD		 2541 break;
2542 case 'x':
2543 /* Unsigned byte. */
2544 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2545 INTVAL (r) & 0xff);
2546 break;
2547 case 'X':
2548 /* Unsigned word. */
2549 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2550 INTVAL (r) & 0xffff);
2551 break;
2552 case 'p':
2553 /* pushm and popm encode a register set into a single byte. */
2554 comma = "";
2555 for (b = 7; b >= 0; b--)
2556 if (INTVAL (r) & (1 << b))
2557 {
2558 fprintf (file, "%s%s", comma, pushm_regs[b]);
2559 comma = ",";
2560 }
2561 break;
2562 case 'm':
2563 /* "Minus". Output -X */
2564 ival = (-INTVAL (r) & 0xffff);
2565 if (ival & 0x8000)
2566 ival = ival - 0x10000;
2567 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2568 break;
2569 default:
2570 ival = INTVAL (r);
2571 if (conversions[i].format[j + 1] == '[' && ival < 0)
2572 {
2573 /* We can simulate negative displacements by
2574 taking advantage of address space
2575 wrapping when the offset can span the
2576 entire address range. */
2577 rtx base =
2578 patternr[conversions[i].format[j + 2] - '0'];
2579 if (GET_CODE (base) == REG)
2580 switch (REGNO (base))
2581 {
2582 case A0_REGNO:
2583 case A1_REGNO:
2584 if (TARGET_A24)
2585 ival = 0x1000000 + ival;
2586 else
2587 ival = 0x10000 + ival;
2588 break;
2589 case SB_REGNO:
2590 if (TARGET_A16)
2591 ival = 0x10000 + ival;
2592 break;
2593 }
2594 }
2595 else if (code == 'd' && ival < 0 && j == 0)
2596 /* The "mova" opcode is used to do addition by
2597 computing displacements, but again, we need
2598 displacements to be unsigned *if* they're
2599 the only component of the displacement
2600 (i.e. no "symbol-4" type displacement). */
2601 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2602
2603 if (conversions[i].format[j] == '0')
2604 {
2605 /* More conversions to unsigned. */
2606 if (unsigned_const == 2)
2607 ival &= 0xffff;
2608 if (unsigned_const == 1)
2609 ival &= 0xff;
2610 }
2611 if (streq (conversions[i].pattern, "mi")
2612 || streq (conversions[i].pattern, "mmi"))
2613 {
2614 /* Integers used as addresses are unsigned. */
2615 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2616 }
ff485e71
DD		 2617 if (force_sign && ival >= 0)
2618 fputc ('+', file);
38b2d076
DD		 2619 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2620 break;
2621 }
2622 break;
2623 case CONST_DOUBLE:
2624 /* We don't have const_double constants. If it
2625 happens, make it obvious. */
2626 fprintf (file, "[const_double 0x%lx]",
2627 (unsigned long) CONST_DOUBLE_HIGH (r));
2628 break;
2629 case SYMBOL_REF:
2630 assemble_name (file, XSTR (r, 0));
2631 break;
2632 case LABEL_REF:
2633 output_asm_label (r);
2634 break;
2635 default:
2636 fprintf (stderr, "don't know how to print this operand:");
2637 debug_rtx (r);
2638 gcc_unreachable ();
2639 }
2640 }
2641 else
2642 {
2643 if (conversions[i].format[j] == 'z')
2644 {
2645 /* Some addressing modes *must* have a displacement,
2646 so insert a zero here if needed. */
2647 int k;
2648 for (k = j + 1; conversions[i].format[k]; k++)
2649 if (ISDIGIT (conversions[i].format[k]))
2650 {
2651 rtx reg = patternr[conversions[i].format[k] - '0'];
2652 if (GET_CODE (reg) == REG
2653 && (REGNO (reg) == SB_REGNO
2654 || REGNO (reg) == FB_REGNO
2655 || REGNO (reg) == SP_REGNO))
2656 fputc ('0', file);
2657 }
2658 continue;
2659 }
2660 /* Signed displacements off symbols need to have signs
2661 blended cleanly. */
2662 if (conversions[i].format[j] == '+'
ff485e71 2663 && (!code || code == 'D' || code == 'd')
38b2d076 2664 && ISDIGIT (conversions[i].format[j + 1])
ff485e71
DD		 2665 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2666 == CONST_INT))
2667 {
2668 force_sign = 1;
2669 continue;
2670 }
38b2d076
DD		 2671 fputc (conversions[i].format[j], file);
2672 }
2673 break;
2674 }
2675 if (!conversions[i].pattern)
2676 {
2677 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2678 pattern);
2679 debug_rtx (x);
2680 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2681 }
2682
2683 return;
2684}
2685
2686/* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2687 above for descriptions of what these do. */
2688int
2689m32c_print_operand_punct_valid_p (int c)
2690{
2691 if (c == '&' || c == '!')
2692 return 1;
2693 return 0;
2694}
2695
2696/* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2697void
2698m32c_print_operand_address (FILE * stream, rtx address)
2699{
235e1fe8
NC		 2700 if (GET_CODE (address) == MEM)
2701 address = XEXP (address, 0);
2702 else
2703 /* cf: gcc.dg/asm-4.c. */
2704 gcc_assert (GET_CODE (address) == REG);
2705
2706 m32c_print_operand (stream, address, 0);
38b2d076
DD		 2707}
2708
2709/* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2710 differently than general registers. */
2711void
2712m32c_output_reg_push (FILE * s, int regno)
2713{
2714 if (regno == FLG_REGNO)
2715 fprintf (s, "\tpushc\tflg\n");
2716 else
04aff2c0 2717 fprintf (s, "\tpush.%c\t%s\n",
38b2d076
DD		 2718 " bwll"[reg_push_size (regno)], reg_names[regno]);
2719}
2720
2721/* Likewise for ASM_OUTPUT_REG_POP. */
2722void
2723m32c_output_reg_pop (FILE * s, int regno)
2724{
2725 if (regno == FLG_REGNO)
2726 fprintf (s, "\tpopc\tflg\n");
2727 else
04aff2c0 2728 fprintf (s, "\tpop.%c\t%s\n",
38b2d076
DD		 2729 " bwll"[reg_push_size (regno)], reg_names[regno]);
2730}
2731
2732/* Defining target-specific uses of `__attribute__' */
2733
2734/* Used to simplify the logic below. Find the attributes wherever
2735 they may be. */
2736#define M32C_ATTRIBUTES(decl) \
2737 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2738 : DECL_ATTRIBUTES (decl) \
2739 ? (DECL_ATTRIBUTES (decl)) \
2740 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2741
2742/* Returns TRUE if the given tree has the "interrupt" attribute. */
2743static int
2744interrupt_p (tree node ATTRIBUTE_UNUSED)
2745{
2746 tree list = M32C_ATTRIBUTES (node);
2747 while (list)
2748 {
2749 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2750 return 1;
2751 list = TREE_CHAIN (list);
2752 }
65655f79
DD		 2753 return fast_interrupt_p (node);
2754}
2755
2756/* Returns TRUE if the given tree has the "bank_switch" attribute. */
2757static int
2758bank_switch_p (tree node ATTRIBUTE_UNUSED)
2759{
2760 tree list = M32C_ATTRIBUTES (node);
2761 while (list)
2762 {
2763 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
2764 return 1;
2765 list = TREE_CHAIN (list);
2766 }
2767 return 0;
2768}
2769
2770/* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
2771static int
2772fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
2773{
2774 tree list = M32C_ATTRIBUTES (node);
2775 while (list)
2776 {
2777 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
2778 return 1;
2779 list = TREE_CHAIN (list);
2780 }
38b2d076
DD		 2781 return 0;
2782}
2783
2784static tree
2785interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2786 tree name ATTRIBUTE_UNUSED,
2787 tree args ATTRIBUTE_UNUSED,
2788 int flags ATTRIBUTE_UNUSED,
2789 bool * no_add_attrs ATTRIBUTE_UNUSED)
2790{
2791 return NULL_TREE;
2792}
2793
5abd2125
JS		 2794/* Returns TRUE if given tree has the "function_vector" attribute. */
2795int
2796m32c_special_page_vector_p (tree func)
2797{
653e2568
DD		 2798 tree list;
2799
5abd2125
JS		 2800 if (TREE_CODE (func) != FUNCTION_DECL)
2801 return 0;
2802
653e2568 2803 list = M32C_ATTRIBUTES (func);
5abd2125
JS		 2804 while (list)
2805 {
2806 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2807 return 1;
2808 list = TREE_CHAIN (list);
2809 }
2810 return 0;
2811}
2812
2813static tree
2814function_vector_handler (tree * node ATTRIBUTE_UNUSED,
2815 tree name ATTRIBUTE_UNUSED,
2816 tree args ATTRIBUTE_UNUSED,
2817 int flags ATTRIBUTE_UNUSED,
2818 bool * no_add_attrs ATTRIBUTE_UNUSED)
2819{
2820 if (TARGET_R8C)
2821 {
2822 /* The attribute is not supported for R8C target. */
2823 warning (OPT_Wattributes,
29d08eba
JM		 2824 "%qE attribute is not supported for R8C target",
2825 name);
5abd2125
JS		 2826 *no_add_attrs = true;
2827 }
2828 else if (TREE_CODE (*node) != FUNCTION_DECL)
2829 {
2830 /* The attribute must be applied to functions only. */
2831 warning (OPT_Wattributes,
29d08eba
JM		 2832 "%qE attribute applies only to functions",
2833 name);
5abd2125
JS		 2834 *no_add_attrs = true;
2835 }
2836 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2837 {
2838 /* The argument must be a constant integer. */
2839 warning (OPT_Wattributes,
29d08eba
JM		 2840 "%qE attribute argument not an integer constant",
2841 name);
5abd2125
JS		 2842 *no_add_attrs = true;
2843 }
2844 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
2845 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
2846 {
2847 /* The argument value must be between 18 to 255. */
2848 warning (OPT_Wattributes,
29d08eba
JM		 2849 "%qE attribute argument should be between 18 to 255",
2850 name);
5abd2125
JS		 2851 *no_add_attrs = true;
2852 }
2853 return NULL_TREE;
2854}
2855
2856/* If the function is assigned the attribute 'function_vector', it
2857 returns the function vector number, otherwise returns zero. */
2858int
2859current_function_special_page_vector (rtx x)
2860{
2861 int num;
2862
2863 if ((GET_CODE(x) == SYMBOL_REF)
2864 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2865 {
653e2568 2866 tree list;
5abd2125
JS		 2867 tree t = SYMBOL_REF_DECL (x);
2868
2869 if (TREE_CODE (t) != FUNCTION_DECL)
2870 return 0;
2871
653e2568 2872 list = M32C_ATTRIBUTES (t);
5abd2125
JS		 2873 while (list)
2874 {
2875 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2876 {
2877 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
2878 return num;
2879 }
2880
2881 list = TREE_CHAIN (list);
2882 }
2883
2884 return 0;
2885 }
2886 else
2887 return 0;
2888}
2889
38b2d076
DD		 2890#undef TARGET_ATTRIBUTE_TABLE
2891#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2892static const struct attribute_spec m32c_attribute_table[] = {
2893 {"interrupt", 0, 0, false, false, false, interrupt_handler},
65655f79
DD		 2894 {"bank_switch", 0, 0, false, false, false, interrupt_handler},
2895 {"fast_interrupt", 0, 0, false, false, false, interrupt_handler},
5abd2125 2896 {"function_vector", 1, 1, true, false, false, function_vector_handler},
38b2d076
DD		 2897 {0, 0, 0, 0, 0, 0, 0}
2898};
2899
2900#undef TARGET_COMP_TYPE_ATTRIBUTES
2901#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2902static int
3101faab
KG		 2903m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
2904 const_tree type2 ATTRIBUTE_UNUSED)
38b2d076
DD		 2905{
2906 /* 0=incompatible 1=compatible 2=warning */
2907 return 1;
2908}
2909
2910#undef TARGET_INSERT_ATTRIBUTES
2911#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2912static void
2913m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2914 tree * attr_ptr ATTRIBUTE_UNUSED)
2915{
2916 /* Nothing to do here. */
2917}
2918
2919/* Predicates */
2920
f9b89438 2921/* This is a list of legal subregs of hard regs. */
67fc44cb
DD		 2922static const struct {
2923 unsigned char outer_mode_size;
2924 unsigned char inner_mode_size;
2925 unsigned char byte_mask;
2926 unsigned char legal_when;
f9b89438 2927 unsigned int regno;
f9b89438 2928} legal_subregs[] = {
67fc44cb
DD		 2929 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
2930 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
2931 {1, 2, 0x01, 1, A0_REGNO},
2932 {1, 2, 0x01, 1, A1_REGNO},
f9b89438 2933
67fc44cb
DD		 2934 {1, 4, 0x01, 1, A0_REGNO},
2935 {1, 4, 0x01, 1, A1_REGNO},
f9b89438 2936
67fc44cb
DD		 2937 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
2938 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
2939 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
2940 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
2941 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
f9b89438 2942
67fc44cb 2943 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
f9b89438
DD		 2944};
2945
2946/* Returns TRUE if OP is a subreg of a hard reg which we don't
2947 support. */
2948bool
2949m32c_illegal_subreg_p (rtx op)
2950{
f9b89438
DD		 2951 int offset;
2952 unsigned int i;
2953 int src_mode, dest_mode;
2954
2955 if (GET_CODE (op) != SUBREG)
2956 return false;
2957
2958 dest_mode = GET_MODE (op);
2959 offset = SUBREG_BYTE (op);
2960 op = SUBREG_REG (op);
2961 src_mode = GET_MODE (op);
2962
2963 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
2964 return false;
2965 if (GET_CODE (op) != REG)
2966 return false;
2967 if (REGNO (op) >= MEM0_REGNO)
2968 return false;
2969
2970 offset = (1 << offset);
2971
67fc44cb 2972 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
f9b89438
DD		 2973 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
2974 && legal_subregs[i].regno == REGNO (op)
2975 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
2976 && legal_subregs[i].byte_mask & offset)
2977 {
2978 switch (legal_subregs[i].legal_when)
2979 {
2980 case 1:
2981 return false;
2982 case 16:
2983 if (TARGET_A16)
2984 return false;
2985 break;
2986 case 24:
2987 if (TARGET_A24)
2988 return false;
2989 break;
2990 }
2991 }
2992 return true;
2993}
2994
38b2d076
DD		 2995/* Returns TRUE if we support a move between the first two operands.
2996 At the moment, we just want to discourage mem to mem moves until
2997 after reload, because reload has a hard time with our limited
2998 number of address registers, and we can get into a situation where
2999 we need three of them when we only have two. */
3000bool
3001m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
3002{
3003 rtx op0 = operands[0];
3004 rtx op1 = operands[1];
3005
3006 if (TARGET_A24)
3007 return true;
3008
3009#define DEBUG_MOV_OK 0
3010#if DEBUG_MOV_OK
3011 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
3012 debug_rtx (op0);
3013 debug_rtx (op1);
3014#endif
3015
3016 if (GET_CODE (op0) == SUBREG)
3017 op0 = XEXP (op0, 0);
3018 if (GET_CODE (op1) == SUBREG)
3019 op1 = XEXP (op1, 0);
3020
3021 if (GET_CODE (op0) == MEM
3022 && GET_CODE (op1) == MEM
3023 && ! reload_completed)
3024 {
3025#if DEBUG_MOV_OK
3026 fprintf (stderr, " - no, mem to mem\n");
3027#endif
3028 return false;
3029 }
3030
3031#if DEBUG_MOV_OK
3032 fprintf (stderr, " - ok\n");
3033#endif
3034 return true;
3035}
3036
ff485e71
DD		 3037/* Returns TRUE if two consecutive HImode mov instructions, generated
3038 for moving an immediate double data to a double data type variable
3039 location, can be combined into single SImode mov instruction. */
3040bool
3041m32c_immd_dbl_mov (rtx * operands,
3042 enum machine_mode mode ATTRIBUTE_UNUSED)
3043{
3044 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
3045 const char *str1;
3046 const char *str2;
3047
3048 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3049 && MEM_SCALAR_P (operands[0])
3050 && !MEM_IN_STRUCT_P (operands[0])
3051 && GET_CODE (XEXP (operands[2], 0)) == CONST
3052 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3053 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3054 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
3055 && MEM_SCALAR_P (operands[2])
3056 && !MEM_IN_STRUCT_P (operands[2]))
3057 flag = 1;
3058
3059 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
3060 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
3061 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
3062 && MEM_SCALAR_P (operands[0])
3063 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3064 && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
ff485e71
DD		 3065 && GET_CODE (XEXP (operands[2], 0)) == CONST
3066 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3067 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3068 && MEM_SCALAR_P (operands[2])
3069 && !MEM_IN_STRUCT_P (operands[2]))
3070 flag = 2;
3071
3072 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3073 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3074 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3075 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3076 && MEM_SCALAR_P (operands[0])
3077 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3078 && !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
ff485e71
DD		 3079 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3080 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3081 && MEM_SCALAR_P (operands[2])
3082 && !MEM_IN_STRUCT_P (operands[2]))
3083 flag = 3;
3084
3085 else
3086 return false;
3087
3088 switch (flag)
3089 {
3090 case 1:
3091 str1 = XSTR (XEXP (operands[0], 0), 0);
3092 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3093 if (strcmp (str1, str2) == 0)
3094 okflag = 1;
3095 else
3096 okflag = 0;
3097 break;
3098 case 2:
3099 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3100 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3101 if (strcmp(str1,str2) == 0)
3102 okflag = 1;
3103 else
3104 okflag = 0;
3105 break;
3106 case 3:
f9f3567e
DD		 3107 offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
3108 offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
ff485e71
DD		 3109 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3110 if (((offset2-offset1) == 2) && offsetsign != 0)
3111 okflag = 1;
3112 else
3113 okflag = 0;
3114 break;
3115 default:
3116 okflag = 0;
3117 }
3118
3119 if (okflag == 1)
3120 {
3121 HOST_WIDE_INT val;
3122 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3123
f9f3567e 3124 val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
ff485e71
DD		 3125 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3126
3127 return true;
3128 }
3129
3130 return false;
3131}
3132
38b2d076
DD		 3133/* Expanders */
3134
3135/* Subregs are non-orthogonal for us, because our registers are all
3136 different sizes. */
3137static rtx
3138m32c_subreg (enum machine_mode outer,
3139 rtx x, enum machine_mode inner, int byte)
3140{
3141 int r, nr = -1;
3142
3143 /* Converting MEMs to different types that are the same size, we
3144 just rewrite them. */
3145 if (GET_CODE (x) == SUBREG
3146 && SUBREG_BYTE (x) == 0
3147 && GET_CODE (SUBREG_REG (x)) == MEM
3148 && (GET_MODE_SIZE (GET_MODE (x))
3149 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3150 {
3151 rtx oldx = x;
3152 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3153 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3154 }
3155
3156 /* Push/pop get done as smaller push/pops. */
3157 if (GET_CODE (x) == MEM
3158 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3159 || GET_CODE (XEXP (x, 0)) == POST_INC))
3160 return gen_rtx_MEM (outer, XEXP (x, 0));
3161 if (GET_CODE (x) == SUBREG
3162 && GET_CODE (XEXP (x, 0)) == MEM
3163 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3164 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3165 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3166
3167 if (GET_CODE (x) != REG)
3168 return simplify_gen_subreg (outer, x, inner, byte);
3169
3170 r = REGNO (x);
3171 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3172 return simplify_gen_subreg (outer, x, inner, byte);
3173
3174 if (IS_MEM_REGNO (r))
3175 return simplify_gen_subreg (outer, x, inner, byte);
3176
3177 /* This is where the complexities of our register layout are
3178 described. */
3179 if (byte == 0)
3180 nr = r;
3181 else if (outer == HImode)
3182 {
3183 if (r == R0_REGNO && byte == 2)
3184 nr = R2_REGNO;
3185 else if (r == R0_REGNO && byte == 4)
3186 nr = R1_REGNO;
3187 else if (r == R0_REGNO && byte == 6)
3188 nr = R3_REGNO;
3189 else if (r == R1_REGNO && byte == 2)
3190 nr = R3_REGNO;
3191 else if (r == A0_REGNO && byte == 2)
3192 nr = A1_REGNO;
3193 }
3194 else if (outer == SImode)
3195 {
3196 if (r == R0_REGNO && byte == 0)
3197 nr = R0_REGNO;
3198 else if (r == R0_REGNO && byte == 4)
3199 nr = R1_REGNO;
3200 }
3201 if (nr == -1)
3202 {
3203 fprintf (stderr, "m32c_subreg %s %s %d\n",
3204 mode_name[outer], mode_name[inner], byte);
3205 debug_rtx (x);
3206 gcc_unreachable ();
3207 }
3208 return gen_rtx_REG (outer, nr);
3209}
3210
3211/* Used to emit move instructions. We split some moves,
3212 and avoid mem-mem moves. */
3213int
3214m32c_prepare_move (rtx * operands, enum machine_mode mode)
3215{
3216 if (TARGET_A16 && mode == PSImode)
3217 return m32c_split_move (operands, mode, 1);
3218 if ((GET_CODE (operands[0]) == MEM)
3219 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3220 {
3221 rtx pmv = XEXP (operands[0], 0);
3222 rtx dest_reg = XEXP (pmv, 0);
3223 rtx dest_mod = XEXP (pmv, 1);
3224
3225 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3226 operands[0] = gen_rtx_MEM (mode, dest_reg);
3227 }
b3a13419 3228 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3229 operands[1] = copy_to_mode_reg (mode, operands[1]);
3230 return 0;
3231}
3232
3233#define DEBUG_SPLIT 0
3234
3235/* Returns TRUE if the given PSImode move should be split. We split
3236 for all r8c/m16c moves, since it doesn't support them, and for
3237 POP.L as we can only *push* SImode. */
3238int
3239m32c_split_psi_p (rtx * operands)
3240{
3241#if DEBUG_SPLIT
3242 fprintf (stderr, "\nm32c_split_psi_p\n");
3243 debug_rtx (operands[0]);
3244 debug_rtx (operands[1]);
3245#endif
3246 if (TARGET_A16)
3247 {
3248#if DEBUG_SPLIT
3249 fprintf (stderr, "yes, A16\n");
3250#endif
3251 return 1;
3252 }
3253 if (GET_CODE (operands[1]) == MEM
3254 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3255 {
3256#if DEBUG_SPLIT
3257 fprintf (stderr, "yes, pop.l\n");
3258#endif
3259 return 1;
3260 }
3261#if DEBUG_SPLIT
3262 fprintf (stderr, "no, default\n");
3263#endif
3264 return 0;
3265}
3266
3267/* Split the given move. SPLIT_ALL is 0 if splitting is optional
3268 (define_expand), 1 if it is not optional (define_insn_and_split),
3269 and 3 for define_split (alternate api). */
3270int
3271m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3272{
3273 rtx s[4], d[4];
3274 int parts, si, di, rev = 0;
3275 int rv = 0, opi = 2;
3276 enum machine_mode submode = HImode;
3277 rtx *ops, local_ops[10];
3278
3279 /* define_split modifies the existing operands, but the other two
3280 emit new insns. OPS is where we store the operand pairs, which
3281 we emit later. */
3282 if (split_all == 3)
3283 ops = operands;
3284 else
3285 ops = local_ops;
3286
3287 /* Else HImode. */
3288 if (mode == DImode)
3289 submode = SImode;
3290
3291 /* Before splitting mem-mem moves, force one operand into a
3292 register. */
b3a13419 3293 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3294 {
3295#if DEBUG0
3296 fprintf (stderr, "force_reg...\n");
3297 debug_rtx (operands[1]);
3298#endif
3299 operands[1] = force_reg (mode, operands[1]);
3300#if DEBUG0
3301 debug_rtx (operands[1]);
3302#endif
3303 }
3304
3305 parts = 2;
3306
3307#if DEBUG_SPLIT
b3a13419
ILT		 3308 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3309 split_all);
38b2d076
DD		 3310 debug_rtx (operands[0]);
3311 debug_rtx (operands[1]);
3312#endif
3313
eb5f0c07
DD		 3314 /* Note that split_all is not used to select the api after this
3315 point, so it's safe to set it to 3 even with define_insn. */
3316 /* None of the chips can move SI operands to sp-relative addresses,
3317 so we always split those. */
3318 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3319 split_all = 3;
3320
38b2d076
DD		 3321 /* We don't need to split these. */
3322 if (TARGET_A24
3323 && split_all != 3
3324 && (mode == SImode || mode == PSImode)
3325 && !(GET_CODE (operands[1]) == MEM
3326 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3327 return 0;
3328
3329 /* First, enumerate the subregs we'll be dealing with. */
3330 for (si = 0; si < parts; si++)
3331 {
3332 d[si] =
3333 m32c_subreg (submode, operands[0], mode,
3334 si * GET_MODE_SIZE (submode));
3335 s[si] =
3336 m32c_subreg (submode, operands[1], mode,
3337 si * GET_MODE_SIZE (submode));
3338 }
3339
3340 /* Split pushes by emitting a sequence of smaller pushes. */
3341 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3342 {
3343 for (si = parts - 1; si >= 0; si--)
3344 {
3345 ops[opi++] = gen_rtx_MEM (submode,
3346 gen_rtx_PRE_DEC (Pmode,
3347 gen_rtx_REG (Pmode,
3348 SP_REGNO)));
3349 ops[opi++] = s[si];
3350 }
3351
3352 rv = 1;
3353 }
3354 /* Likewise for pops. */
3355 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3356 {
3357 for (di = 0; di < parts; di++)
3358 {
3359 ops[opi++] = d[di];
3360 ops[opi++] = gen_rtx_MEM (submode,
3361 gen_rtx_POST_INC (Pmode,
3362 gen_rtx_REG (Pmode,
3363 SP_REGNO)));
3364 }
3365 rv = 1;
3366 }
3367 else if (split_all)
3368 {
3369 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3370 for (di = 0; di < parts - 1; di++)
3371 for (si = di + 1; si < parts; si++)
3372 if (reg_mentioned_p (d[di], s[si]))
3373 rev = 1;
3374
3375 if (rev)
3376 for (si = 0; si < parts; si++)
3377 {
3378 ops[opi++] = d[si];
3379 ops[opi++] = s[si];
3380 }
3381 else
3382 for (si = parts - 1; si >= 0; si--)
3383 {
3384 ops[opi++] = d[si];
3385 ops[opi++] = s[si];
3386 }
3387 rv = 1;
3388 }
3389 /* Now emit any moves we may have accumulated. */
3390 if (rv && split_all != 3)
3391 {
3392 int i;
3393 for (i = 2; i < opi; i += 2)
3394 emit_move_insn (ops[i], ops[i + 1]);
3395 }
3396 return rv;
3397}
3398
07127a0a
DD		 3399/* The m32c has a number of opcodes that act like memcpy, strcmp, and
3400 the like. For the R8C they expect one of the addresses to be in
3401 R1L:An so we need to arrange for that. Otherwise, it's just a
3402 matter of picking out the operands we want and emitting the right
3403 pattern for them. All these expanders, which correspond to
3404 patterns in blkmov.md, must return nonzero if they expand the insn,
3405 or zero if they should FAIL. */
3406
3407/* This is a memset() opcode. All operands are implied, so we need to
3408 arrange for them to be in the right registers. The opcode wants
3409 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3410 the count (HI), and $2 the value (QI). */
3411int
3412m32c_expand_setmemhi(rtx *operands)
3413{
3414 rtx desta, count, val;
3415 rtx desto, counto;
3416
3417 desta = XEXP (operands[0], 0);
3418 count = operands[1];
3419 val = operands[2];
3420
3421 desto = gen_reg_rtx (Pmode);
3422 counto = gen_reg_rtx (HImode);
3423
3424 if (GET_CODE (desta) != REG
3425 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3426 desta = copy_to_mode_reg (Pmode, desta);
3427
3428 /* This looks like an arbitrary restriction, but this is by far the
3429 most common case. For counts 8..14 this actually results in
3430 smaller code with no speed penalty because the half-sized
3431 constant can be loaded with a shorter opcode. */
3432 if (GET_CODE (count) == CONST_INT
3433 && GET_CODE (val) == CONST_INT
3434 && ! (INTVAL (count) & 1)
3435 && (INTVAL (count) > 1)
3436 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3437 {
3438 unsigned v = INTVAL (val) & 0xff;
3439 v = v | (v << 8);
3440 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3441 val = copy_to_mode_reg (HImode, GEN_INT (v));
3442 if (TARGET_A16)
3443 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3444 else
3445 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3446 return 1;
3447 }
3448
3449 /* This is the generalized memset() case. */
3450 if (GET_CODE (val) != REG
3451 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3452 val = copy_to_mode_reg (QImode, val);
3453
3454 if (GET_CODE (count) != REG
3455 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3456 count = copy_to_mode_reg (HImode, count);
3457
3458 if (TARGET_A16)
3459 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3460 else
3461 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3462
3463 return 1;
3464}
3465
3466/* This is a memcpy() opcode. All operands are implied, so we need to
3467 arrange for them to be in the right registers. The opcode wants
3468 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3469 is the source (MEM:BLK), and $2 the count (HI). */
3470int
3471m32c_expand_movmemhi(rtx *operands)
3472{
3473 rtx desta, srca, count;
3474 rtx desto, srco, counto;
3475
3476 desta = XEXP (operands[0], 0);
3477 srca = XEXP (operands[1], 0);
3478 count = operands[2];
3479
3480 desto = gen_reg_rtx (Pmode);
3481 srco = gen_reg_rtx (Pmode);
3482 counto = gen_reg_rtx (HImode);
3483
3484 if (GET_CODE (desta) != REG
3485 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3486 desta = copy_to_mode_reg (Pmode, desta);
3487
3488 if (GET_CODE (srca) != REG
3489 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3490 srca = copy_to_mode_reg (Pmode, srca);
3491
3492 /* Similar to setmem, but we don't need to check the value. */
3493 if (GET_CODE (count) == CONST_INT
3494 && ! (INTVAL (count) & 1)
3495 && (INTVAL (count) > 1))
3496 {
3497 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3498 if (TARGET_A16)
3499 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3500 else
3501 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3502 return 1;
3503 }
3504
3505 /* This is the generalized memset() case. */
3506 if (GET_CODE (count) != REG
3507 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3508 count = copy_to_mode_reg (HImode, count);
3509
3510 if (TARGET_A16)
3511 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3512 else
3513 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3514
3515 return 1;
3516}
3517
3518/* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3519 the copy, which should point to the NUL at the end of the string,
3520 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3521 Since our opcode leaves the destination pointing *after* the NUL,
3522 we must emit an adjustment. */
3523int
3524m32c_expand_movstr(rtx *operands)
3525{
3526 rtx desta, srca;
3527 rtx desto, srco;
3528
3529 desta = XEXP (operands[1], 0);
3530 srca = XEXP (operands[2], 0);
3531
3532 desto = gen_reg_rtx (Pmode);
3533 srco = gen_reg_rtx (Pmode);
3534
3535 if (GET_CODE (desta) != REG
3536 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3537 desta = copy_to_mode_reg (Pmode, desta);
3538
3539 if (GET_CODE (srca) != REG
3540 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3541 srca = copy_to_mode_reg (Pmode, srca);
3542
3543 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3544 /* desto ends up being a1, which allows this type of add through MOVA. */
3545 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3546
3547 return 1;
3548}
3549
3550/* This is a strcmp() opcode. $0 is the destination (HI) which holds
3551 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3552 $2 is the other (MEM:BLK). We must do the comparison, and then
3553 convert the flags to a signed integer result. */
3554int
3555m32c_expand_cmpstr(rtx *operands)
3556{
3557 rtx src1a, src2a;
3558
3559 src1a = XEXP (operands[1], 0);
3560 src2a = XEXP (operands[2], 0);
3561
3562 if (GET_CODE (src1a) != REG
3563 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
3564 src1a = copy_to_mode_reg (Pmode, src1a);
3565
3566 if (GET_CODE (src2a) != REG
3567 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
3568 src2a = copy_to_mode_reg (Pmode, src2a);
3569
3570 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
3571 emit_insn (gen_cond_to_int (operands[0]));
3572
3573 return 1;
3574}
3575
3576
23fed240
DD		 3577typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
3578
3579static shift_gen_func
3580shift_gen_func_for (int mode, int code)
3581{
3582#define GFF(m,c,f) if (mode == m && code == c) return f
3583 GFF(QImode, ASHIFT, gen_ashlqi3_i);
3584 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
3585 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
3586 GFF(HImode, ASHIFT, gen_ashlhi3_i);
3587 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
3588 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
3589 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
3590 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
3591 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
3592 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
3593 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
3594 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
3595#undef GFF
07127a0a 3596 gcc_unreachable ();
23fed240
DD		 3597}
3598
38b2d076
DD		 3599/* The m32c only has one shift, but it takes a signed count. GCC
3600 doesn't want this, so we fake it by negating any shift count when
07127a0a
DD		 3601 we're pretending to shift the other way. Also, the shift count is
3602 limited to -8..8. It's slightly better to use two shifts for 9..15
3603 than to load the count into r1h, so we do that too. */
38b2d076 3604int
23fed240 3605m32c_prepare_shift (rtx * operands, int scale, int shift_code)
38b2d076 3606{
23fed240
DD		 3607 enum machine_mode mode = GET_MODE (operands[0]);
3608 shift_gen_func func = shift_gen_func_for (mode, shift_code);
38b2d076 3609 rtx temp;
23fed240
DD		 3610
3611 if (GET_CODE (operands[2]) == CONST_INT)
38b2d076 3612 {
23fed240
DD		 3613 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
3614 int count = INTVAL (operands[2]) * scale;
3615
3616 while (count > maxc)
3617 {
3618 temp = gen_reg_rtx (mode);
3619 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
3620 operands[1] = temp;
3621 count -= maxc;
3622 }
3623 while (count < -maxc)
3624 {
3625 temp = gen_reg_rtx (mode);
3626 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
3627 operands[1] = temp;
3628 count += maxc;
3629 }
3630 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
3631 return 1;
38b2d076 3632 }
2e160056
DD		 3633
3634 temp = gen_reg_rtx (QImode);
38b2d076 3635 if (scale < 0)
2e160056
DD		 3636 /* The pattern has a NEG that corresponds to this. */
3637 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
3638 else if (TARGET_A16 && mode == SImode)
3639 /* We do this because the code below may modify this, we don't
3640 want to modify the origin of this value. */
3641 emit_move_insn (temp, operands[2]);
38b2d076 3642 else
2e160056 3643 /* We'll only use it for the shift, no point emitting a move. */
38b2d076 3644 temp = operands[2];
2e160056 3645
16659fcf 3646 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
2e160056
DD		 3647 {
3648 /* The m16c has a limit of -16..16 for SI shifts, even when the
3649 shift count is in a register. Since there are so many targets
3650 of these shifts, it's better to expand the RTL here than to
3651 call a helper function.
3652
3653 The resulting code looks something like this:
3654
3655 cmp.b r1h,-16
3656 jge.b 1f
3657 shl.l -16,dest
3658 add.b r1h,16
3659 1f: cmp.b r1h,16
3660 jle.b 1f
3661 shl.l 16,dest
3662 sub.b r1h,16
3663 1f: shl.l r1h,dest
3664
3665 We take advantage of the fact that "negative" shifts are
3666 undefined to skip one of the comparisons. */
3667
3668 rtx count;
833bf445 3669 rtx label, lref, insn, tempvar;
2e160056 3670
16659fcf
DD		 3671 emit_move_insn (operands[0], operands[1]);
3672
2e160056
DD		 3673 count = temp;
3674 label = gen_label_rtx ();
3675 lref = gen_rtx_LABEL_REF (VOIDmode, label);
3676 LABEL_NUSES (label) ++;
3677
833bf445
DD		 3678 tempvar = gen_reg_rtx (mode);
3679
2e160056
DD		 3680 if (shift_code == ASHIFT)
3681 {
3682 /* This is a left shift. We only need check positive counts. */
3683 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
3684 count, GEN_INT (16), label));
833bf445
DD		 3685 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
3686 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
2e160056
DD		 3687 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
3688 emit_label_after (label, insn);
3689 }
3690 else
3691 {
3692 /* This is a right shift. We only need check negative counts. */
3693 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
3694 count, GEN_INT (-16), label));
833bf445
DD		 3695 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
3696 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
2e160056
DD		 3697 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
3698 emit_label_after (label, insn);
3699 }
16659fcf
DD		 3700 operands[1] = operands[0];
3701 emit_insn (func (operands[0], operands[0], count));
3702 return 1;
2e160056
DD		 3703 }
3704
38b2d076
DD		 3705 operands[2] = temp;
3706 return 0;
3707}
3708
12ea2512
DD		 3709/* The m32c has a limited range of operations that work on PSImode
3710 values; we have to expand to SI, do the math, and truncate back to
3711 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3712 those cases. */
3713void
3714m32c_expand_neg_mulpsi3 (rtx * operands)
3715{
3716 /* operands: a = b * i */
3717 rtx temp1; /* b as SI */
07127a0a
DD		 3718 rtx scale /* i as SI */;
3719 rtx temp2; /* a*b as SI */
12ea2512
DD		 3720
3721 temp1 = gen_reg_rtx (SImode);
3722 temp2 = gen_reg_rtx (SImode);
07127a0a
DD		 3723 if (GET_CODE (operands[2]) != CONST_INT)
3724 {
3725 scale = gen_reg_rtx (SImode);
3726 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
3727 }
3728 else
3729 scale = copy_to_mode_reg (SImode, operands[2]);
12ea2512
DD		 3730
3731 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
07127a0a
DD		 3732 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
3733 emit_insn (gen_truncsipsi2 (operands[0], temp2));
12ea2512
DD		 3734}
3735
38b2d076
DD		 3736/* Pattern Output Functions */
3737
07127a0a
DD		 3738int
3739m32c_expand_movcc (rtx *operands)
3740{
3741 rtx rel = operands[1];
0166ff05
DD		 3742 rtx cmp;
3743
07127a0a
DD		 3744 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
3745 return 1;
3746 if (GET_CODE (operands[2]) != CONST_INT
3747 || GET_CODE (operands[3]) != CONST_INT)
3748 return 1;
07127a0a
DD		 3749 if (GET_CODE (rel) == NE)
3750 {
3751 rtx tmp = operands[2];
3752 operands[2] = operands[3];
3753 operands[3] = tmp;
f90b7a5a 3754 rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
07127a0a 3755 }
0166ff05 3756
0166ff05
DD		 3757 emit_move_insn (operands[0],
3758 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
f90b7a5a 3759 rel,
0166ff05
DD		 3760 operands[2],
3761 operands[3]));
07127a0a
DD		 3762 return 0;
3763}
3764
3765/* Used for the "insv" pattern. Return nonzero to fail, else done. */
3766int
3767m32c_expand_insv (rtx *operands)
3768{
3769 rtx op0, src0, p;
3770 int mask;
3771
3772 if (INTVAL (operands[1]) != 1)
3773 return 1;
3774
9cb96754
N		 3775 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3776 if (GET_CODE (operands[3]) != CONST_INT)
3777 return 1;
3778 if (INTVAL (operands[3]) != 0
3779 && INTVAL (operands[3]) != 1
3780 && INTVAL (operands[3]) != -1)
3781 return 1;
3782
07127a0a
DD		 3783 mask = 1 << INTVAL (operands[2]);
3784
3785 op0 = operands[0];
3786 if (GET_CODE (op0) == SUBREG
3787 && SUBREG_BYTE (op0) == 0)
3788 {
3789 rtx sub = SUBREG_REG (op0);
3790 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
3791 op0 = sub;
3792 }
3793
b3a13419 3794 if (!can_create_pseudo_p ()
07127a0a
DD		 3795 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
3796 src0 = op0;
3797 else
3798 {
3799 src0 = gen_reg_rtx (GET_MODE (op0));
3800 emit_move_insn (src0, op0);
3801 }
3802
3803 if (GET_MODE (op0) == HImode
3804 && INTVAL (operands[2]) >= 8
3805 && GET_MODE (op0) == MEM)
3806 {
3807 /* We are little endian. */
3808 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
3809 MEM_COPY_ATTRIBUTES (new_mem, op0);
3810 mask >>= 8;
3811 }
3812
8e4edce7
DD		 3813 /* First, we generate a mask with the correct polarity. If we are
3814 storing a zero, we want an AND mask, so invert it. */
3815 if (INTVAL (operands[3]) == 0)
07127a0a 3816 {
16659fcf 3817 /* Storing a zero, use an AND mask */
07127a0a
DD		 3818 if (GET_MODE (op0) == HImode)
3819 mask ^= 0xffff;
3820 else
3821 mask ^= 0xff;
3822 }
8e4edce7
DD		 3823 /* Now we need to properly sign-extend the mask in case we need to
3824 fall back to an AND or OR opcode. */
07127a0a
DD		 3825 if (GET_MODE (op0) == HImode)
3826 {
3827 if (mask & 0x8000)
3828 mask -= 0x10000;
3829 }
3830 else
3831 {
3832 if (mask & 0x80)
3833 mask -= 0x100;
3834 }
3835
3836 switch ( (INTVAL (operands[3]) ? 4 : 0)
3837 + ((GET_MODE (op0) == HImode) ? 2 : 0)
3838 + (TARGET_A24 ? 1 : 0))
3839 {
3840 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
3841 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
3842 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
3843 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
3844 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
3845 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
3846 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
3847 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
653e2568 3848 default: p = NULL_RTX; break; /* Not reached, but silences a warning. */
07127a0a
DD		 3849 }
3850
3851 emit_insn (p);
3852 return 0;
3853}
3854
3855const char *
3856m32c_scc_pattern(rtx *operands, RTX_CODE code)
3857{
3858 static char buf[30];
3859 if (GET_CODE (operands[0]) == REG
3860 && REGNO (operands[0]) == R0_REGNO)
3861 {
3862 if (code == EQ)
3863 return "stzx\t#1,#0,r0l";
3864 if (code == NE)
3865 return "stzx\t#0,#1,r0l";
3866 }
3867 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
3868 return buf;
3869}
3870
5abd2125
JS		 3871/* Encode symbol attributes of a SYMBOL_REF into its
3872 SYMBOL_REF_FLAGS. */
3873static void
3874m32c_encode_section_info (tree decl, rtx rtl, int first)
3875{
3876 int extra_flags = 0;
3877
3878 default_encode_section_info (decl, rtl, first);
3879 if (TREE_CODE (decl) == FUNCTION_DECL
3880 && m32c_special_page_vector_p (decl))
3881
3882 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
3883
3884 if (extra_flags)
3885 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
3886}
3887
38b2d076
DD		 3888/* Returns TRUE if the current function is a leaf, and thus we can
3889 determine which registers an interrupt function really needs to
3890 save. The logic below is mostly about finding the insn sequence
3891 that's the function, versus any sequence that might be open for the
3892 current insn. */
3893static int
3894m32c_leaf_function_p (void)
3895{
3896 rtx saved_first, saved_last;
3897 struct sequence_stack *seq;
3898 int rv;
3899
3e029763
JH		 3900 saved_first = crtl->emit.x_first_insn;
3901 saved_last = crtl->emit.x_last_insn;
3902 for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
38b2d076
DD		 3903 ;
3904 if (seq)
3905 {
3e029763
JH		 3906 crtl->emit.x_first_insn = seq->first;
3907 crtl->emit.x_last_insn = seq->last;
38b2d076
DD		 3908 }
3909
3910 rv = leaf_function_p ();
3911
3e029763
JH		 3912 crtl->emit.x_first_insn = saved_first;
3913 crtl->emit.x_last_insn = saved_last;
38b2d076
DD		 3914 return rv;
3915}
3916
3917/* Returns TRUE if the current function needs to use the ENTER/EXIT
3918 opcodes. If the function doesn't need the frame base or stack
3919 pointer, it can use the simpler RTS opcode. */
3920static bool
3921m32c_function_needs_enter (void)
3922{
3923 rtx insn;
3924 struct sequence_stack *seq;
3925 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
3926 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
3927
3928 insn = get_insns ();
3e029763 3929 for (seq = crtl->emit.sequence_stack;
38b2d076
DD		 3930 seq;
3931 insn = seq->first, seq = seq->next);
3932
3933 while (insn)
3934 {
3935 if (reg_mentioned_p (sp, insn))
3936 return true;
3937 if (reg_mentioned_p (fb, insn))
3938 return true;
3939 insn = NEXT_INSN (insn);
3940 }
3941 return false;
3942}
3943
3944/* Mark all the subexpressions of the PARALLEL rtx PAR as
3945 frame-related. Return PAR.
3946
3947 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3948 PARALLEL rtx other than the first if they do not have the
3949 FRAME_RELATED flag set on them. So this function is handy for
3950 marking up 'enter' instructions. */
3951static rtx
3952m32c_all_frame_related (rtx par)
3953{
3954 int len = XVECLEN (par, 0);
3955 int i;
3956
3957 for (i = 0; i < len; i++)
3958 F (XVECEXP (par, 0, i));
3959
3960 return par;
3961}
3962
3963/* Emits the prologue. See the frame layout comment earlier in this
3964 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3965 that we manually update sp. */
3966void
3967m32c_emit_prologue (void)
3968{
3969 int frame_size, extra_frame_size = 0, reg_save_size;
3970 int complex_prologue = 0;
3971
3972 cfun->machine->is_leaf = m32c_leaf_function_p ();
3973 if (interrupt_p (cfun->decl))
3974 {
3975 cfun->machine->is_interrupt = 1;
3976 complex_prologue = 1;
3977 }
65655f79
DD		 3978 else if (bank_switch_p (cfun->decl))
3979 warning (OPT_Wattributes,
3980 "%<bank_switch%> has no effect on non-interrupt functions");
38b2d076
DD		 3981
3982 reg_save_size = m32c_pushm_popm (PP_justcount);
3983
3984 if (interrupt_p (cfun->decl))
65655f79
DD		 3985 {
3986 if (bank_switch_p (cfun->decl))
3987 emit_insn (gen_fset_b ());
3988 else if (cfun->machine->intr_pushm)
3989 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
3990 }
38b2d076
DD		 3991
3992 frame_size =
3993 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
3994 if (frame_size == 0
38b2d076
DD		 3995 && !m32c_function_needs_enter ())
3996 cfun->machine->use_rts = 1;
3997
3998 if (frame_size > 254)
3999 {
4000 extra_frame_size = frame_size - 254;
4001 frame_size = 254;
4002 }
4003 if (cfun->machine->use_rts == 0)
4004 F (emit_insn (m32c_all_frame_related
4005 (TARGET_A16
fa9fd28a
RIL		 4006 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
4007 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
38b2d076
DD		 4008
4009 if (extra_frame_size)
4010 {
4011 complex_prologue = 1;
4012 if (TARGET_A16)
4013 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
4014 gen_rtx_REG (HImode, SP_REGNO),
4015 GEN_INT (-extra_frame_size))));
4016 else
4017 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
4018 gen_rtx_REG (PSImode, SP_REGNO),
4019 GEN_INT (-extra_frame_size))));
4020 }
4021
4022 complex_prologue += m32c_pushm_popm (PP_pushm);
4023
4024 /* This just emits a comment into the .s file for debugging. */
4025 if (complex_prologue)
4026 emit_insn (gen_prologue_end ());
4027}
4028
4029/* Likewise, for the epilogue. The only exception is that, for
4030 interrupts, we must manually unwind the frame as the REIT opcode
4031 doesn't do that. */
4032void
4033m32c_emit_epilogue (void)
4034{
4035 /* This just emits a comment into the .s file for debugging. */
4036 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4037 emit_insn (gen_epilogue_start ());
4038
4039 m32c_pushm_popm (PP_popm);
4040
4041 if (cfun->machine->is_interrupt)
4042 {
4043 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4044
65655f79
DD		 4045 /* REIT clears B flag and restores $fp for us, but we still
4046 have to fix up the stack. USE_RTS just means we didn't
4047 emit ENTER. */
4048 if (!cfun->machine->use_rts)
4049 {
4050 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4051 gen_rtx_REG (spmode, FP_REGNO));
4052 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4053 gen_rtx_REG (spmode, A0_REGNO));
4054 /* We can't just add this to the POPM because it would be in
4055 the wrong order, and wouldn't fix the stack if we're bank
4056 switching. */
4057 if (TARGET_A16)
4058 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4059 else
4060 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4061 }
4062 if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
4063 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4064
402f2db8
DD		 4065 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4066 generated only for M32C/M32CM targets (generate the REIT
4067 instruction otherwise). */
65655f79 4068 if (fast_interrupt_p (cfun->decl))
402f2db8
DD		 4069 {
4070 /* Check if fast_attribute is set for M32C or M32CM. */
4071 if (TARGET_A24)
4072 {
4073 emit_jump_insn (gen_epilogue_freit ());
4074 }
4075 /* If fast_interrupt attribute is set for an R8C or M16C
4076 target ignore this attribute and generated REIT
4077 instruction. */
4078 else
4079 {
4080 warning (OPT_Wattributes,
4081 "%<fast_interrupt%> attribute directive ignored");
4082 emit_jump_insn (gen_epilogue_reit_16 ());
4083 }
4084 }
65655f79 4085 else if (TARGET_A16)
0e0642aa
RIL		 4086 emit_jump_insn (gen_epilogue_reit_16 ());
4087 else
4088 emit_jump_insn (gen_epilogue_reit_24 ());
38b2d076
DD		 4089 }
4090 else if (cfun->machine->use_rts)
4091 emit_jump_insn (gen_epilogue_rts ());
0e0642aa
RIL		 4092 else if (TARGET_A16)
4093 emit_jump_insn (gen_epilogue_exitd_16 ());
38b2d076 4094 else
0e0642aa 4095 emit_jump_insn (gen_epilogue_exitd_24 ());
38b2d076
DD		 4096 emit_barrier ();
4097}
4098
4099void
4100m32c_emit_eh_epilogue (rtx ret_addr)
4101{
4102 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4103 return to. We have to fudge the stack, pop everything, pop SP
4104 (fudged), and return (fudged). This is actually easier to do in
4105 assembler, so punt to libgcc. */
4106 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
c41c1387 4107 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
38b2d076
DD		 4108 emit_barrier ();
4109}
4110
16659fcf
DD		 4111/* Indicate which flags must be properly set for a given conditional. */
4112static int
4113flags_needed_for_conditional (rtx cond)
4114{
4115 switch (GET_CODE (cond))
4116 {
4117 case LE:
4118 case GT:
4119 return FLAGS_OSZ;
4120 case LEU:
4121 case GTU:
4122 return FLAGS_ZC;
4123 case LT:
4124 case GE:
4125 return FLAGS_OS;
4126 case LTU:
4127 case GEU:
4128 return FLAGS_C;
4129 case EQ:
4130 case NE:
4131 return FLAGS_Z;
4132 default:
4133 return FLAGS_N;
4134 }
4135}
4136
4137#define DEBUG_CMP 0
4138
4139/* Returns true if a compare insn is redundant because it would only
4140 set flags that are already set correctly. */
4141static bool
4142m32c_compare_redundant (rtx cmp, rtx *operands)
4143{
4144 int flags_needed;
4145 int pflags;
4146 rtx prev, pp, next;
4147 rtx op0, op1, op2;
4148#if DEBUG_CMP
4149 int prev_icode, i;
4150#endif
4151
4152 op0 = operands[0];
4153 op1 = operands[1];
4154 op2 = operands[2];
4155
4156#if DEBUG_CMP
4157 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4158 debug_rtx(cmp);
4159 for (i=0; i<2; i++)
4160 {
4161 fprintf(stderr, "operands[%d] = ", i);
4162 debug_rtx(operands[i]);
4163 }
4164#endif
4165
4166 next = next_nonnote_insn (cmp);
4167 if (!next || !INSN_P (next))
4168 {
4169#if DEBUG_CMP
4170 fprintf(stderr, "compare not followed by insn\n");
4171 debug_rtx(next);
4172#endif
4173 return false;
4174 }
4175 if (GET_CODE (PATTERN (next)) == SET
4176 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4177 {
4178 next = XEXP (XEXP (PATTERN (next), 1), 0);
4179 }
4180 else if (GET_CODE (PATTERN (next)) == SET)
4181 {
4182 /* If this is a conditional, flags_needed will be something
4183 other than FLAGS_N, which we test below. */
4184 next = XEXP (PATTERN (next), 1);
4185 }
4186 else
4187 {
4188#if DEBUG_CMP
4189 fprintf(stderr, "compare not followed by conditional\n");
4190 debug_rtx(next);
4191#endif
4192 return false;
4193 }
4194#if DEBUG_CMP
4195 fprintf(stderr, "conditional is: ");
4196 debug_rtx(next);
4197#endif
4198
4199 flags_needed = flags_needed_for_conditional (next);
4200 if (flags_needed == FLAGS_N)
4201 {
4202#if DEBUG_CMP
4203 fprintf(stderr, "compare not followed by conditional\n");
4204 debug_rtx(next);
4205#endif
4206 return false;
4207 }
4208
4209 /* Compare doesn't set overflow and carry the same way that
4210 arithmetic instructions do, so we can't replace those. */
4211 if (flags_needed & FLAGS_OC)
4212 return false;
4213
4214 prev = cmp;
4215 do {
4216 prev = prev_nonnote_insn (prev);
4217 if (!prev)
4218 {
4219#if DEBUG_CMP
4220 fprintf(stderr, "No previous insn.\n");
4221#endif
4222 return false;
4223 }
4224 if (!INSN_P (prev))
4225 {
4226#if DEBUG_CMP
4227 fprintf(stderr, "Previous insn is a non-insn.\n");
4228#endif
4229 return false;
4230 }
4231 pp = PATTERN (prev);
4232 if (GET_CODE (pp) != SET)
4233 {
4234#if DEBUG_CMP
4235 fprintf(stderr, "Previous insn is not a SET.\n");
4236#endif
4237 return false;
4238 }
4239 pflags = get_attr_flags (prev);
4240
4241 /* Looking up attributes of previous insns corrupted the recog
4242 tables. */
4243 INSN_UID (cmp) = -1;
4244 recog (PATTERN (cmp), cmp, 0);
4245
4246 if (pflags == FLAGS_N
4247 && reg_mentioned_p (op0, pp))
4248 {
4249#if DEBUG_CMP
4250 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4251 debug_rtx(prev);
4252#endif
4253 return false;
4254 }
b3c5a409
DD		 4255
4256 /* Check for comparisons against memory - between volatiles and
4257 aliases, we just can't risk this one. */
4258 if (GET_CODE (operands[0]) == MEM
4259 || GET_CODE (operands[0]) == MEM)
4260 {
4261#if DEBUG_CMP
4262 fprintf(stderr, "comparisons with memory:\n");
4263 debug_rtx(prev);
4264#endif
4265 return false;
4266 }
4267
4268 /* Check for PREV changing a register that's used to compute a
4269 value in CMP, even if it doesn't otherwise change flags. */
4270 if (GET_CODE (operands[0]) == REG
4271 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
4272 {
4273#if DEBUG_CMP
4274 fprintf(stderr, "sub-value affected, op0:\n");
4275 debug_rtx(prev);
4276#endif
4277 return false;
4278 }
4279 if (GET_CODE (operands[1]) == REG
4280 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
4281 {
4282#if DEBUG_CMP
4283 fprintf(stderr, "sub-value affected, op1:\n");
4284 debug_rtx(prev);
4285#endif
4286 return false;
4287 }
4288
16659fcf
DD		 4289 } while (pflags == FLAGS_N);
4290#if DEBUG_CMP
4291 fprintf(stderr, "previous flag-setting insn:\n");
4292 debug_rtx(prev);
4293 debug_rtx(pp);
4294#endif
4295
4296 if (GET_CODE (pp) == SET
4297 && GET_CODE (XEXP (pp, 0)) == REG
4298 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4299 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4300 {
4301 /* Adjacent cbranches must have the same operands to be
4302 redundant. */
4303 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4304 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4305#if DEBUG_CMP
4306 fprintf(stderr, "adjacent cbranches\n");
4307 debug_rtx(pop0);
4308 debug_rtx(pop1);
4309#endif
4310 if (rtx_equal_p (op0, pop0)
4311 && rtx_equal_p (op1, pop1))
4312 return true;
4313#if DEBUG_CMP
4314 fprintf(stderr, "prev cmp not same\n");
4315#endif
4316 return false;
4317 }
4318
4319 /* Else the previous insn must be a SET, with either the source or
4320 dest equal to operands[0], and operands[1] must be zero. */
4321
4322 if (!rtx_equal_p (op1, const0_rtx))
4323 {
4324#if DEBUG_CMP
4325 fprintf(stderr, "operands[1] not const0_rtx\n");
4326#endif
4327 return false;
4328 }
4329 if (GET_CODE (pp) != SET)
4330 {
4331#if DEBUG_CMP
4332 fprintf (stderr, "pp not set\n");
4333#endif
4334 return false;
4335 }
4336 if (!rtx_equal_p (op0, SET_SRC (pp))
4337 && !rtx_equal_p (op0, SET_DEST (pp)))
4338 {
4339#if DEBUG_CMP
4340 fprintf(stderr, "operands[0] not found in set\n");
4341#endif
4342 return false;
4343 }
4344
4345#if DEBUG_CMP
4346 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4347#endif
4348 if ((pflags & flags_needed) == flags_needed)
4349 return true;
4350
4351 return false;
4352}
4353
4354/* Return the pattern for a compare. This will be commented out if
4355 the compare is redundant, else a normal pattern is returned. Thus,
4356 the assembler output says where the compare would have been. */
4357char *
4358m32c_output_compare (rtx insn, rtx *operands)
4359{
0a2aaacc 4360 static char templ[] = ";cmp.b\t%1,%0";
16659fcf
DD		 4361 /* ^ 5 */
4362
0a2aaacc 4363 templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
16659fcf
DD		 4364 if (m32c_compare_redundant (insn, operands))
4365 {
4366#if DEBUG_CMP
4367 fprintf(stderr, "cbranch: cmp not needed\n");
4368#endif
0a2aaacc 4369 return templ;
16659fcf
DD		 4370 }
4371
4372#if DEBUG_CMP
b3c5a409 4373 fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
16659fcf 4374#endif
0a2aaacc 4375 return templ + 1;
16659fcf
DD		 4376}
4377
5abd2125
JS		 4378#undef TARGET_ENCODE_SECTION_INFO
4379#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4380
b52b1749
AS		 4381/* If the frame pointer isn't used, we detect it manually. But the
4382 stack pointer doesn't have as flexible addressing as the frame
4383 pointer, so we always assume we have it. */
4384
4385#undef TARGET_FRAME_POINTER_REQUIRED
4386#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4387
38b2d076
DD		 4388/* The Global `targetm' Variable. */
4389
4390struct gcc_target targetm = TARGET_INITIALIZER;
4391
4392#include "gt-m32c.h"
Mirror of https://gcc.gnu.org/git/gcc.git