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[thirdparty/gcc.git] / gcc / config / m32c / m32c.c
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38b2d076 1/* Target Code for R8C/M16C/M32C
96e45421 2 Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
38b2d076
DD		 3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
2f83c7d6 10 by the Free Software Foundation; either version 3, or (at your
38b2d076
DD		 11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
38b2d076
DD		 21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
26#include "rtl.h"
27#include "regs.h"
28#include "hard-reg-set.h"
38b2d076
DD		 29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
36#include "reload.h"
718f9c0f 37#include "diagnostic-core.h"
38b2d076
DD		 38#include "obstack.h"
39#include "tree.h"
40#include "expr.h"
41#include "optabs.h"
42#include "except.h"
43#include "function.h"
44#include "ggc.h"
45#include "target.h"
46#include "target-def.h"
47#include "tm_p.h"
48#include "langhooks.h"
726a989a 49#include "gimple.h"
fa9fd28a 50#include "df.h"
38b2d076
DD		 51
52/* Prototypes */
53
54/* Used by m32c_pushm_popm. */
55typedef enum
56{
57 PP_pushm,
58 PP_popm,
59 PP_justcount
60} Push_Pop_Type;
61
65655f79 62static bool m32c_function_needs_enter (void);
38b2d076 63static tree interrupt_handler (tree *, tree, tree, int, bool *);
5abd2125 64static tree function_vector_handler (tree *, tree, tree, int, bool *);
38b2d076 65static int interrupt_p (tree node);
65655f79
DD		 66static int bank_switch_p (tree node);
67static int fast_interrupt_p (tree node);
68static int interrupt_p (tree node);
38b2d076 69static bool m32c_asm_integer (rtx, unsigned int, int);
3101faab 70static int m32c_comp_type_attributes (const_tree, const_tree);
38b2d076
DD		 71static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
72static struct machine_function *m32c_init_machine_status (void);
73static void m32c_insert_attributes (tree, tree *);
c6c3dba9 74static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
5fd5d713 75static bool m32c_addr_space_legitimate_address_p (enum machine_mode, rtx, bool, addr_space_t);
444d6efe
JR		 76static rtx m32c_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
77 const_tree, bool);
38b2d076 78static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
586de218 79 const_tree, bool);
cd34bbe8
NF		 80static void m32c_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
81 const_tree, bool);
c2ed6cf8 82static unsigned int m32c_function_arg_boundary (enum machine_mode, const_tree);
38b2d076
DD		 83static int m32c_pushm_popm (Push_Pop_Type);
84static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
85static rtx m32c_struct_value_rtx (tree, int);
86static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
87static int need_to_save (int);
2a31793e
AS		 88static rtx m32c_function_value (const_tree, const_tree, bool);
89static rtx m32c_libcall_value (enum machine_mode, const_rtx);
90
f6052f86
DD		 91/* Returns true if an address is specified, else false. */
92static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
93
5abd2125 94#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
38b2d076
DD		 95
96#define streq(a,b) (strcmp ((a), (b)) == 0)
97
98/* Internal support routines */
99
100/* Debugging statements are tagged with DEBUG0 only so that they can
101 be easily enabled individually, by replacing the '0' with '1' as
102 needed. */
103#define DEBUG0 0
104#define DEBUG1 1
105
106#if DEBUG0
107/* This is needed by some of the commented-out debug statements
108 below. */
109static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
110#endif
111static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
112
113/* These are all to support encode_pattern(). */
114static char pattern[30], *patternp;
115static GTY(()) rtx patternr[30];
116#define RTX_IS(x) (streq (pattern, x))
117
118/* Some macros to simplify the logic throughout this file. */
119#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
120#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
121
122#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
123#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
124
5fd5d713
DD		 125static int
126far_addr_space_p (rtx x)
127{
128 if (GET_CODE (x) != MEM)
129 return 0;
130#if DEBUG0
131 fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
132 fprintf(stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
133#endif
134 return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;
135}
136
38b2d076
DD		 137/* We do most RTX matching by converting the RTX into a string, and
138 using string compares. This vastly simplifies the logic in many of
139 the functions in this file.
140
141 On exit, pattern[] has the encoded string (use RTX_IS("...") to
142 compare it) and patternr[] has pointers to the nodes in the RTX
143 corresponding to each character in the encoded string. The latter
144 is mostly used by print_operand().
145
146 Unrecognized patterns have '?' in them; this shows up when the
147 assembler complains about syntax errors.
148*/
149
150static void
151encode_pattern_1 (rtx x)
152{
153 int i;
154
155 if (patternp == pattern + sizeof (pattern) - 2)
156 {
157 patternp[-1] = '?';
158 return;
159 }
160
161 patternr[patternp - pattern] = x;
162
163 switch (GET_CODE (x))
164 {
165 case REG:
166 *patternp++ = 'r';
167 break;
168 case SUBREG:
169 if (GET_MODE_SIZE (GET_MODE (x)) !=
170 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
171 *patternp++ = 'S';
172 encode_pattern_1 (XEXP (x, 0));
173 break;
174 case MEM:
175 *patternp++ = 'm';
176 case CONST:
177 encode_pattern_1 (XEXP (x, 0));
178 break;
5fd5d713
DD		 179 case SIGN_EXTEND:
180 *patternp++ = '^';
181 *patternp++ = 'S';
182 encode_pattern_1 (XEXP (x, 0));
183 break;
184 case ZERO_EXTEND:
185 *patternp++ = '^';
186 *patternp++ = 'Z';
187 encode_pattern_1 (XEXP (x, 0));
188 break;
38b2d076
DD		 189 case PLUS:
190 *patternp++ = '+';
191 encode_pattern_1 (XEXP (x, 0));
192 encode_pattern_1 (XEXP (x, 1));
193 break;
194 case PRE_DEC:
195 *patternp++ = '>';
196 encode_pattern_1 (XEXP (x, 0));
197 break;
198 case POST_INC:
199 *patternp++ = '<';
200 encode_pattern_1 (XEXP (x, 0));
201 break;
202 case LO_SUM:
203 *patternp++ = 'L';
204 encode_pattern_1 (XEXP (x, 0));
205 encode_pattern_1 (XEXP (x, 1));
206 break;
207 case HIGH:
208 *patternp++ = 'H';
209 encode_pattern_1 (XEXP (x, 0));
210 break;
211 case SYMBOL_REF:
212 *patternp++ = 's';
213 break;
214 case LABEL_REF:
215 *patternp++ = 'l';
216 break;
217 case CODE_LABEL:
218 *patternp++ = 'c';
219 break;
220 case CONST_INT:
221 case CONST_DOUBLE:
222 *patternp++ = 'i';
223 break;
224 case UNSPEC:
225 *patternp++ = 'u';
226 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
227 for (i = 0; i < XVECLEN (x, 0); i++)
228 encode_pattern_1 (XVECEXP (x, 0, i));
229 break;
230 case USE:
231 *patternp++ = 'U';
232 break;
233 case PARALLEL:
234 *patternp++ = '|';
235 for (i = 0; i < XVECLEN (x, 0); i++)
236 encode_pattern_1 (XVECEXP (x, 0, i));
237 break;
238 case EXPR_LIST:
239 *patternp++ = 'E';
240 encode_pattern_1 (XEXP (x, 0));
241 if (XEXP (x, 1))
242 encode_pattern_1 (XEXP (x, 1));
243 break;
244 default:
245 *patternp++ = '?';
246#if DEBUG0
247 fprintf (stderr, "can't encode pattern %s\n",
248 GET_RTX_NAME (GET_CODE (x)));
249 debug_rtx (x);
250 gcc_unreachable ();
251#endif
252 break;
253 }
254}
255
256static void
257encode_pattern (rtx x)
258{
259 patternp = pattern;
260 encode_pattern_1 (x);
261 *patternp = 0;
262}
263
264/* Since register names indicate the mode they're used in, we need a
265 way to determine which name to refer to the register with. Called
266 by print_operand(). */
267
268static const char *
269reg_name_with_mode (int regno, enum machine_mode mode)
270{
271 int mlen = GET_MODE_SIZE (mode);
272 if (regno == R0_REGNO && mlen == 1)
273 return "r0l";
274 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
275 return "r2r0";
276 if (regno == R0_REGNO && mlen == 6)
277 return "r2r1r0";
278 if (regno == R0_REGNO && mlen == 8)
279 return "r3r1r2r0";
280 if (regno == R1_REGNO && mlen == 1)
281 return "r1l";
282 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
283 return "r3r1";
284 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
285 return "a1a0";
286 return reg_names[regno];
287}
288
289/* How many bytes a register uses on stack when it's pushed. We need
290 to know this because the push opcode needs to explicitly indicate
291 the size of the register, even though the name of the register
292 already tells it that. Used by m32c_output_reg_{push,pop}, which
293 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
294
295static int
296reg_push_size (int regno)
297{
298 switch (regno)
299 {
300 case R0_REGNO:
301 case R1_REGNO:
302 return 2;
303 case R2_REGNO:
304 case R3_REGNO:
305 case FLG_REGNO:
306 return 2;
307 case A0_REGNO:
308 case A1_REGNO:
309 case SB_REGNO:
310 case FB_REGNO:
311 case SP_REGNO:
312 if (TARGET_A16)
313 return 2;
314 else
315 return 3;
316 default:
317 gcc_unreachable ();
318 }
319}
320
321static int *class_sizes = 0;
322
323/* Given two register classes, find the largest intersection between
324 them. If there is no intersection, return RETURNED_IF_EMPTY
325 instead. */
326static int
327reduce_class (int original_class, int limiting_class, int returned_if_empty)
328{
329 int cc = class_contents[original_class][0];
330 int i, best = NO_REGS;
331 int best_size = 0;
332
333 if (original_class == limiting_class)
334 return original_class;
335
336 if (!class_sizes)
337 {
338 int r;
339 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
340 for (i = 0; i < LIM_REG_CLASSES; i++)
341 {
342 class_sizes[i] = 0;
343 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
344 if (class_contents[i][0] & (1 << r))
345 class_sizes[i]++;
346 }
347 }
348
349 cc &= class_contents[limiting_class][0];
350 for (i = 0; i < LIM_REG_CLASSES; i++)
351 {
352 int ic = class_contents[i][0];
353
354 if ((~cc & ic) == 0)
355 if (best_size < class_sizes[i])
356 {
357 best = i;
358 best_size = class_sizes[i];
359 }
360
361 }
362 if (best == NO_REGS)
363 return returned_if_empty;
364 return best;
365}
366
38b2d076
DD		 367/* Used by m32c_register_move_cost to determine if a move is
368 impossibly expensive. */
0e607518
AS		 369static bool
370class_can_hold_mode (reg_class_t rclass, enum machine_mode mode)
38b2d076
DD		 371{
372 /* Cache the results: 0=untested 1=no 2=yes */
373 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
0e607518
AS		 374
375 if (results[(int) rclass][mode] == 0)
38b2d076 376 {
0e607518 377 int r;
0a2aaacc 378 results[rclass][mode] = 1;
38b2d076 379 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
0e607518 380 if (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)
38b2d076
DD		 381 && HARD_REGNO_MODE_OK (r, mode))
382 {
0e607518
AS		 383 results[rclass][mode] = 2;
384 break;
38b2d076
DD		 385 }
386 }
0e607518 387
38b2d076
DD		 388#if DEBUG0
389 fprintf (stderr, "class %s can hold %s? %s\n",
0e607518 390 class_names[(int) rclass], mode_name[mode],
0a2aaacc 391 (results[rclass][mode] == 2) ? "yes" : "no");
38b2d076 392#endif
0e607518 393 return results[(int) rclass][mode] == 2;
38b2d076
DD		 394}
395
396/* Run-time Target Specification. */
397
398/* Memregs are memory locations that gcc treats like general
399 registers, as there are a limited number of true registers and the
400 m32c families can use memory in most places that registers can be
401 used.
402
403 However, since memory accesses are more expensive than registers,
404 we allow the user to limit the number of memregs available, in
405 order to try to persuade gcc to try harder to use real registers.
406
407 Memregs are provided by m32c-lib1.S.
408*/
409
38b2d076
DD		 410int ok_to_change_target_memregs = TRUE;
411
f28f2337
AS		 412/* Implements TARGET_OPTION_OVERRIDE. */
413
414#undef TARGET_OPTION_OVERRIDE
415#define TARGET_OPTION_OVERRIDE m32c_option_override
416
417static void
418m32c_option_override (void)
38b2d076 419{
f28f2337 420 /* We limit memregs to 0..16, and provide a default. */
bbfc9a8c 421 if (global_options_set.x_target_memregs)
38b2d076
DD		 422 {
423 if (target_memregs < 0 || target_memregs > 16)
424 error ("invalid target memregs value '%d'", target_memregs);
425 }
426 else
07127a0a 427 target_memregs = 16;
18b80268
DD		 428
429 if (TARGET_A24)
430 flag_ivopts = 0;
0685e770
DD		 431
432 /* This target defaults to strict volatile bitfields. */
433 if (flag_strict_volatile_bitfields < 0)
434 flag_strict_volatile_bitfields = 1;
d123bf41
DD		 435
436 /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
437 This is always worse than an absolute call. */
438 if (TARGET_A16)
439 flag_no_function_cse = 1;
a4403164
DD		 440
441 /* This wants to put insns between compares and their jumps. */
442 /* FIXME: The right solution is to properly trace the flags register
443 values, but that is too much work for stage 4. */
444 flag_combine_stack_adjustments = 0;
d123bf41
DD		 445}
446
447#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
448#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
449
450static void
451m32c_override_options_after_change (void)
452{
453 if (TARGET_A16)
454 flag_no_function_cse = 1;
38b2d076
DD		 455}
456
457/* Defining data structures for per-function information */
458
459/* The usual; we set up our machine_function data. */
460static struct machine_function *
461m32c_init_machine_status (void)
462{
a9429e29 463 return ggc_alloc_cleared_machine_function ();
38b2d076
DD		 464}
465
466/* Implements INIT_EXPANDERS. We just set up to call the above
467 function. */
468void
469m32c_init_expanders (void)
470{
471 init_machine_status = m32c_init_machine_status;
472}
473
474/* Storage Layout */
475
38b2d076
DD		 476/* Register Basics */
477
478/* Basic Characteristics of Registers */
479
480/* Whether a mode fits in a register is complex enough to warrant a
481 table. */
482static struct
483{
484 char qi_regs;
485 char hi_regs;
486 char pi_regs;
487 char si_regs;
488 char di_regs;
489} nregs_table[FIRST_PSEUDO_REGISTER] =
490{
491 { 1, 1, 2, 2, 4 }, /* r0 */
492 { 0, 1, 0, 0, 0 }, /* r2 */
493 { 1, 1, 2, 2, 0 }, /* r1 */
494 { 0, 1, 0, 0, 0 }, /* r3 */
495 { 0, 1, 1, 0, 0 }, /* a0 */
496 { 0, 1, 1, 0, 0 }, /* a1 */
497 { 0, 1, 1, 0, 0 }, /* sb */
498 { 0, 1, 1, 0, 0 }, /* fb */
499 { 0, 1, 1, 0, 0 }, /* sp */
500 { 1, 1, 1, 0, 0 }, /* pc */
501 { 0, 0, 0, 0, 0 }, /* fl */
502 { 1, 1, 1, 0, 0 }, /* ap */
503 { 1, 1, 2, 2, 4 }, /* mem0 */
504 { 1, 1, 2, 2, 4 }, /* mem1 */
505 { 1, 1, 2, 2, 4 }, /* mem2 */
506 { 1, 1, 2, 2, 4 }, /* mem3 */
507 { 1, 1, 2, 2, 4 }, /* mem4 */
508 { 1, 1, 2, 2, 0 }, /* mem5 */
509 { 1, 1, 2, 2, 0 }, /* mem6 */
510 { 1, 1, 0, 0, 0 }, /* mem7 */
511};
512
5efd84c5
NF		 513/* Implements TARGET_CONDITIONAL_REGISTER_USAGE. We adjust the number
514 of available memregs, and select which registers need to be preserved
38b2d076
DD		 515 across calls based on the chip family. */
516
5efd84c5
NF		 517#undef TARGET_CONDITIONAL_REGISTER_USAGE
518#define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
d6d17ae7 519void
38b2d076
DD		 520m32c_conditional_register_usage (void)
521{
38b2d076
DD		 522 int i;
523
524 if (0 <= target_memregs && target_memregs <= 16)
525 {
526 /* The command line option is bytes, but our "registers" are
527 16-bit words. */
65655f79 528 for (i = (target_memregs+1)/2; i < 8; i++)
38b2d076
DD		 529 {
530 fixed_regs[MEM0_REGNO + i] = 1;
531 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
532 }
533 }
534
535 /* M32CM and M32C preserve more registers across function calls. */
536 if (TARGET_A24)
537 {
538 call_used_regs[R1_REGNO] = 0;
539 call_used_regs[R2_REGNO] = 0;
540 call_used_regs[R3_REGNO] = 0;
541 call_used_regs[A0_REGNO] = 0;
542 call_used_regs[A1_REGNO] = 0;
543 }
544}
545
546/* How Values Fit in Registers */
547
548/* Implements HARD_REGNO_NREGS. This is complicated by the fact that
549 different registers are different sizes from each other, *and* may
550 be different sizes in different chip families. */
b8a669d0
DD		 551static int
552m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
38b2d076
DD		 553{
554 if (regno == FLG_REGNO && mode == CCmode)
555 return 1;
556 if (regno >= FIRST_PSEUDO_REGISTER)
557 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
558
559 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
560 return (GET_MODE_SIZE (mode) + 1) / 2;
561
562 if (GET_MODE_SIZE (mode) <= 1)
563 return nregs_table[regno].qi_regs;
564 if (GET_MODE_SIZE (mode) <= 2)
565 return nregs_table[regno].hi_regs;
5fd5d713 566 if (regno == A0_REGNO && mode == SImode && TARGET_A16)
38b2d076
DD		 567 return 2;
568 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
569 return nregs_table[regno].pi_regs;
570 if (GET_MODE_SIZE (mode) <= 4)
571 return nregs_table[regno].si_regs;
572 if (GET_MODE_SIZE (mode) <= 8)
573 return nregs_table[regno].di_regs;
574 return 0;
575}
576
b8a669d0
DD		 577int
578m32c_hard_regno_nregs (int regno, enum machine_mode mode)
579{
580 int rv = m32c_hard_regno_nregs_1 (regno, mode);
581 return rv ? rv : 1;
582}
583
38b2d076
DD		 584/* Implements HARD_REGNO_MODE_OK. The above function does the work
585 already; just test its return value. */
586int
587m32c_hard_regno_ok (int regno, enum machine_mode mode)
588{
b8a669d0 589 return m32c_hard_regno_nregs_1 (regno, mode) != 0;
38b2d076
DD		 590}
591
592/* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
593 registers are all different sizes. However, since most modes are
594 bigger than our registers anyway, it's easier to implement this
595 function that way, leaving QImode as the only unique case. */
596int
597m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
598{
599 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
600 return 1;
601
07127a0a 602#if 0
38b2d076
DD		 603 if (m1 == QImode || m2 == QImode)
604 return 0;
07127a0a 605#endif
38b2d076
DD		 606
607 return 1;
608}
609
610/* Register Classes */
611
612/* Implements REGNO_REG_CLASS. */
444d6efe 613enum reg_class
38b2d076
DD		 614m32c_regno_reg_class (int regno)
615{
616 switch (regno)
617 {
618 case R0_REGNO:
619 return R0_REGS;
620 case R1_REGNO:
621 return R1_REGS;
622 case R2_REGNO:
623 return R2_REGS;
624 case R3_REGNO:
625 return R3_REGS;
626 case A0_REGNO:
22843acd 627 return A0_REGS;
38b2d076 628 case A1_REGNO:
22843acd 629 return A1_REGS;
38b2d076
DD		 630 case SB_REGNO:
631 return SB_REGS;
632 case FB_REGNO:
633 return FB_REGS;
634 case SP_REGNO:
635 return SP_REGS;
636 case FLG_REGNO:
637 return FLG_REGS;
638 default:
639 if (IS_MEM_REGNO (regno))
640 return MEM_REGS;
641 return ALL_REGS;
642 }
643}
644
645/* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
646 for certain chip families. */
647int
648m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
649{
650 if (memcmp (s, "Rsp", 3) == 0)
651 return SP_REGS;
652 if (memcmp (s, "Rfb", 3) == 0)
653 return FB_REGS;
654 if (memcmp (s, "Rsb", 3) == 0)
655 return SB_REGS;
07127a0a
DD		 656 if (memcmp (s, "Rcr", 3) == 0)
657 return TARGET_A16 ? CR_REGS : NO_REGS;
658 if (memcmp (s, "Rcl", 3) == 0)
659 return TARGET_A24 ? CR_REGS : NO_REGS;
38b2d076
DD		 660 if (memcmp (s, "R0w", 3) == 0)
661 return R0_REGS;
662 if (memcmp (s, "R1w", 3) == 0)
663 return R1_REGS;
664 if (memcmp (s, "R2w", 3) == 0)
665 return R2_REGS;
666 if (memcmp (s, "R3w", 3) == 0)
667 return R3_REGS;
668 if (memcmp (s, "R02", 3) == 0)
669 return R02_REGS;
18b80268
DD		 670 if (memcmp (s, "R13", 3) == 0)
671 return R13_REGS;
38b2d076
DD		 672 if (memcmp (s, "R03", 3) == 0)
673 return R03_REGS;
674 if (memcmp (s, "Rdi", 3) == 0)
675 return DI_REGS;
676 if (memcmp (s, "Rhl", 3) == 0)
677 return HL_REGS;
678 if (memcmp (s, "R23", 3) == 0)
679 return R23_REGS;
07127a0a
DD		 680 if (memcmp (s, "Ra0", 3) == 0)
681 return A0_REGS;
682 if (memcmp (s, "Ra1", 3) == 0)
683 return A1_REGS;
38b2d076
DD		 684 if (memcmp (s, "Raa", 3) == 0)
685 return A_REGS;
07127a0a
DD		 686 if (memcmp (s, "Raw", 3) == 0)
687 return TARGET_A16 ? A_REGS : NO_REGS;
688 if (memcmp (s, "Ral", 3) == 0)
689 return TARGET_A24 ? A_REGS : NO_REGS;
38b2d076
DD		 690 if (memcmp (s, "Rqi", 3) == 0)
691 return QI_REGS;
692 if (memcmp (s, "Rad", 3) == 0)
693 return AD_REGS;
694 if (memcmp (s, "Rsi", 3) == 0)
695 return SI_REGS;
696 if (memcmp (s, "Rhi", 3) == 0)
697 return HI_REGS;
698 if (memcmp (s, "Rhc", 3) == 0)
699 return HC_REGS;
700 if (memcmp (s, "Rra", 3) == 0)
701 return RA_REGS;
702 if (memcmp (s, "Rfl", 3) == 0)
703 return FLG_REGS;
704 if (memcmp (s, "Rmm", 3) == 0)
705 {
706 if (fixed_regs[MEM0_REGNO])
707 return NO_REGS;
708 return MEM_REGS;
709 }
710
711 /* PSImode registers - i.e. whatever can hold a pointer. */
712 if (memcmp (s, "Rpi", 3) == 0)
713 {
714 if (TARGET_A16)
715 return HI_REGS;
716 else
717 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
718 }
719
720 /* We handle this one as an EXTRA_CONSTRAINT. */
721 if (memcmp (s, "Rpa", 3) == 0)
722 return NO_REGS;
723
07127a0a
DD		 724 if (*s == 'R')
725 {
726 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
727 gcc_unreachable();
728 }
729
38b2d076
DD		 730 return NO_REGS;
731}
732
733/* Implements REGNO_OK_FOR_BASE_P. */
734int
735m32c_regno_ok_for_base_p (int regno)
736{
737 if (regno == A0_REGNO
738 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
739 return 1;
740 return 0;
741}
742
743#define DEBUG_RELOAD 0
744
745/* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
746 registers of the appropriate size. */
747int
748m32c_preferred_reload_class (rtx x, int rclass)
749{
750 int newclass = rclass;
751
752#if DEBUG_RELOAD
753 fprintf (stderr, "\npreferred_reload_class for %s is ",
754 class_names[rclass]);
755#endif
756 if (rclass == NO_REGS)
757 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
758
0e607518 759 if (reg_classes_intersect_p (rclass, CR_REGS))
38b2d076
DD		 760 {
761 switch (GET_MODE (x))
762 {
763 case QImode:
764 newclass = HL_REGS;
765 break;
766 default:
767 /* newclass = HI_REGS; */
768 break;
769 }
770 }
771
772 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
773 newclass = SI_REGS;
774 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
775 && ~class_contents[rclass][0] & 0x000f)
776 newclass = DI_REGS;
777
778 rclass = reduce_class (rclass, newclass, rclass);
779
780 if (GET_MODE (x) == QImode)
781 rclass = reduce_class (rclass, HL_REGS, rclass);
782
783#if DEBUG_RELOAD
784 fprintf (stderr, "%s\n", class_names[rclass]);
785 debug_rtx (x);
786
787 if (GET_CODE (x) == MEM
788 && GET_CODE (XEXP (x, 0)) == PLUS
789 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
790 fprintf (stderr, "Glorm!\n");
791#endif
792 return rclass;
793}
794
795/* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
796int
797m32c_preferred_output_reload_class (rtx x, int rclass)
798{
799 return m32c_preferred_reload_class (x, rclass);
800}
801
802/* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
803 address registers for reloads since they're needed for address
804 reloads. */
805int
806m32c_limit_reload_class (enum machine_mode mode, int rclass)
807{
808#if DEBUG_RELOAD
809 fprintf (stderr, "limit_reload_class for %s: %s ->",
810 mode_name[mode], class_names[rclass]);
811#endif
812
813 if (mode == QImode)
814 rclass = reduce_class (rclass, HL_REGS, rclass);
815 else if (mode == HImode)
816 rclass = reduce_class (rclass, HI_REGS, rclass);
817 else if (mode == SImode)
818 rclass = reduce_class (rclass, SI_REGS, rclass);
819
820 if (rclass != A_REGS)
821 rclass = reduce_class (rclass, DI_REGS, rclass);
822
823#if DEBUG_RELOAD
824 fprintf (stderr, " %s\n", class_names[rclass]);
825#endif
826 return rclass;
827}
828
829/* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
830 r0 or r1, as those are the only real QImode registers. CR regs get
831 reloaded through appropriately sized general or address
832 registers. */
833int
834m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
835{
836 int cc = class_contents[rclass][0];
837#if DEBUG0
838 fprintf (stderr, "\nsecondary reload class %s %s\n",
839 class_names[rclass], mode_name[mode]);
840 debug_rtx (x);
841#endif
842 if (mode == QImode
843 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
844 return QI_REGS;
0e607518 845 if (reg_classes_intersect_p (rclass, CR_REGS)
38b2d076
DD		 846 && GET_CODE (x) == REG
847 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
848 return TARGET_A16 ? HI_REGS : A_REGS;
849 return NO_REGS;
850}
851
184866c5 852/* Implements TARGET_CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
38b2d076 853 reloads. */
184866c5
AS		 854
855#undef TARGET_CLASS_LIKELY_SPILLED_P
856#define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
857
858static bool
859m32c_class_likely_spilled_p (reg_class_t regclass)
38b2d076
DD		 860{
861 if (regclass == A_REGS)
184866c5
AS		 862 return true;
863
864 return (reg_class_size[(int) regclass] == 1);
38b2d076
DD		 865}
866
867/* Implements CLASS_MAX_NREGS. We calculate this according to its
868 documented meaning, to avoid potential inconsistencies with actual
869 class definitions. */
870int
871m32c_class_max_nregs (int regclass, enum machine_mode mode)
872{
873 int rn, max = 0;
874
875 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
876 if (class_contents[regclass][0] & (1 << rn))
877 {
878 int n = m32c_hard_regno_nregs (rn, mode);
879 if (max < n)
880 max = n;
881 }
882 return max;
883}
884
885/* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
886 QI (r0l, r1l) because the chip doesn't support QI ops on other
887 registers (well, it does on a0/a1 but if we let gcc do that, reload
888 suffers). Otherwise, we allow changes to larger modes. */
889int
890m32c_cannot_change_mode_class (enum machine_mode from,
891 enum machine_mode to, int rclass)
892{
db9c8397 893 int rn;
38b2d076
DD		 894#if DEBUG0
895 fprintf (stderr, "cannot change from %s to %s in %s\n",
896 mode_name[from], mode_name[to], class_names[rclass]);
897#endif
898
db9c8397
DD		 899 /* If the larger mode isn't allowed in any of these registers, we
900 can't allow the change. */
901 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
902 if (class_contents[rclass][0] & (1 << rn))
903 if (! m32c_hard_regno_ok (rn, to))
904 return 1;
905
38b2d076
DD		 906 if (to == QImode)
907 return (class_contents[rclass][0] & 0x1ffa);
908
909 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
910 && GET_MODE_SIZE (from) > 1)
911 return 0;
912 if (GET_MODE_SIZE (from) > 2) /* all other regs */
913 return 0;
914
915 return 1;
916}
917
918/* Helpers for the rest of the file. */
919/* TRUE if the rtx is a REG rtx for the given register. */
920#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
921 && REGNO (rtx) == regno)
922/* TRUE if the rtx is a pseudo - specifically, one we can use as a
923 base register in address calculations (hence the "strict"
924 argument). */
925#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
926 && (REGNO (rtx) == AP_REGNO \
927 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
928
929/* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
930 constraints start with 'I', with the next two characters indicating
931 the type and size of the range allowed. */
932int
933m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
934 char c ATTRIBUTE_UNUSED, const char *str)
935{
936 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
937 [sun] bits [SUN] bytes, p=pointer size
938 I[-0-9][0-9] matches that number */
939 if (memcmp (str, "Is3", 3) == 0)
940 {
941 return (-8 <= value && value <= 7);
942 }
943 if (memcmp (str, "IS1", 3) == 0)
944 {
945 return (-128 <= value && value <= 127);
946 }
947 if (memcmp (str, "IS2", 3) == 0)
948 {
949 return (-32768 <= value && value <= 32767);
950 }
951 if (memcmp (str, "IU2", 3) == 0)
952 {
953 return (0 <= value && value <= 65535);
954 }
955 if (memcmp (str, "IU3", 3) == 0)
956 {
957 return (0 <= value && value <= 0x00ffffff);
958 }
959 if (memcmp (str, "In4", 3) == 0)
960 {
961 return (-8 <= value && value && value <= 8);
962 }
963 if (memcmp (str, "In5", 3) == 0)
964 {
965 return (-16 <= value && value && value <= 16);
966 }
23fed240
DD		 967 if (memcmp (str, "In6", 3) == 0)
968 {
969 return (-32 <= value && value && value <= 32);
970 }
38b2d076
DD		 971 if (memcmp (str, "IM2", 3) == 0)
972 {
973 return (-65536 <= value && value && value <= -1);
974 }
975 if (memcmp (str, "Ilb", 3) == 0)
976 {
977 int b = exact_log2 (value);
8e4edce7 978 return (b >= 0 && b <= 7);
38b2d076 979 }
07127a0a
DD		 980 if (memcmp (str, "Imb", 3) == 0)
981 {
982 int b = exact_log2 ((value ^ 0xff) & 0xff);
8e4edce7 983 return (b >= 0 && b <= 7);
07127a0a 984 }
600e668e
DD		 985 if (memcmp (str, "ImB", 3) == 0)
986 {
987 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
988 return (b >= 0 && b <= 7);
989 }
38b2d076
DD		 990 if (memcmp (str, "Ilw", 3) == 0)
991 {
992 int b = exact_log2 (value);
8e4edce7 993 return (b >= 0 && b <= 15);
38b2d076 994 }
07127a0a
DD		 995 if (memcmp (str, "Imw", 3) == 0)
996 {
997 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
8e4edce7 998 return (b >= 0 && b <= 15);
07127a0a
DD		 999 }
1000 if (memcmp (str, "I00", 3) == 0)
1001 {
1002 return (value == 0);
1003 }
38b2d076
DD		 1004 return 0;
1005}
1006
5fd5d713
DD		 1007#define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
1008
38b2d076
DD		 1009/* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
1010 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
1011 call return values. */
1012int
1013m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
1014{
1015 encode_pattern (value);
5fd5d713
DD		 1016
1017 if (far_addr_space_p (value))
1018 {
1019 if (memcmp (str, "SF", 2) == 0)
1020 {
1021 return ( (RTX_IS ("mr")
1022 && A0_OR_PSEUDO (patternr[1])
1023 && GET_MODE (patternr[1]) == SImode)
1024 || (RTX_IS ("m+^Sri")
1025 && A0_OR_PSEUDO (patternr[4])
1026 && GET_MODE (patternr[4]) == HImode)
1027 || (RTX_IS ("m+^Srs")
1028 && A0_OR_PSEUDO (patternr[4])
1029 && GET_MODE (patternr[4]) == HImode)
1030 || (RTX_IS ("m+^S+ris")
1031 && A0_OR_PSEUDO (patternr[5])
1032 && GET_MODE (patternr[5]) == HImode)
1033 || RTX_IS ("ms")
1034 );
1035 }
1036 return 0;
1037 }
1038
38b2d076
DD		 1039 if (memcmp (str, "Sd", 2) == 0)
1040 {
1041 /* This is the common "src/dest" address */
1042 rtx r;
1043 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
1044 return 1;
1045 if (RTX_IS ("ms") || RTX_IS ("m+si"))
1046 return 1;
07127a0a
DD		 1047 if (RTX_IS ("m++rii"))
1048 {
1049 if (REGNO (patternr[3]) == FB_REGNO
1050 && INTVAL (patternr[4]) == 0)
1051 return 1;
1052 }
38b2d076
DD		 1053 if (RTX_IS ("mr"))
1054 r = patternr[1];
1055 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
1056 r = patternr[2];
1057 else
1058 return 0;
1059 if (REGNO (r) == SP_REGNO)
1060 return 0;
1061 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
1062 }
1063 else if (memcmp (str, "Sa", 2) == 0)
1064 {
1065 rtx r;
1066 if (RTX_IS ("mr"))
1067 r = patternr[1];
1068 else if (RTX_IS ("m+ri"))
1069 r = patternr[2];
1070 else
1071 return 0;
1072 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1073 }
1074 else if (memcmp (str, "Si", 2) == 0)
1075 {
1076 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1077 }
1078 else if (memcmp (str, "Ss", 2) == 0)
1079 {
1080 return ((RTX_IS ("mr")
1081 && (IS_REG (patternr[1], SP_REGNO)))
1082 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1083 }
1084 else if (memcmp (str, "Sf", 2) == 0)
1085 {
1086 return ((RTX_IS ("mr")
1087 && (IS_REG (patternr[1], FB_REGNO)))
1088 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1089 }
1090 else if (memcmp (str, "Sb", 2) == 0)
1091 {
1092 return ((RTX_IS ("mr")
1093 && (IS_REG (patternr[1], SB_REGNO)))
1094 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1095 }
07127a0a
DD		 1096 else if (memcmp (str, "Sp", 2) == 0)
1097 {
1098 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1099 return (RTX_IS ("mi")
1100 && !(INTVAL (patternr[1]) & ~0x1fff));
1101 }
38b2d076
DD		 1102 else if (memcmp (str, "S1", 2) == 0)
1103 {
1104 return r1h_operand (value, QImode);
1105 }
5fd5d713
DD		 1106 else if (memcmp (str, "SF", 2) == 0)
1107 {
1108 return 0;
1109 }
38b2d076
DD		 1110
1111 gcc_assert (str[0] != 'S');
1112
1113 if (memcmp (str, "Rpa", 2) == 0)
1114 return GET_CODE (value) == PARALLEL;
1115
1116 return 0;
1117}
1118
1119/* This is for when we're debugging the above. */
1120int
1121m32c_extra_constraint_p (rtx value, char c, const char *str)
1122{
1123 int rv = m32c_extra_constraint_p2 (value, c, str);
1124#if DEBUG0
1125 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1126 rv);
1127 debug_rtx (value);
1128#endif
1129 return rv;
1130}
1131
1132/* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1133 starting with 'S'. */
1134int
1135m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1136{
1137 return c == 'S';
1138}
1139
1140/* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1141 but don't currently define any. */
1142int
1143m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1144{
1145 return c == 'A';
1146}
1147
1148/* STACK AND CALLING */
1149
1150/* Frame Layout */
1151
1152/* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1153 (yes, THREE bytes) onto the stack for the return address, but we
1154 don't support pointers bigger than 16 bits on those chips. This
1155 will likely wreak havoc with exception unwinding. FIXME. */
1156rtx
1157m32c_return_addr_rtx (int count)
1158{
1159 enum machine_mode mode;
1160 int offset;
1161 rtx ra_mem;
1162
1163 if (count)
1164 return NULL_RTX;
1165 /* we want 2[$fb] */
1166
1167 if (TARGET_A24)
1168 {
80b093df
DD		 1169 /* It's four bytes */
1170 mode = PSImode;
38b2d076
DD		 1171 offset = 4;
1172 }
1173 else
1174 {
1175 /* FIXME: it's really 3 bytes */
1176 mode = HImode;
1177 offset = 2;
1178 }
1179
1180 ra_mem =
1181 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1182 return copy_to_mode_reg (mode, ra_mem);
1183}
1184
1185/* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1186rtx
1187m32c_incoming_return_addr_rtx (void)
1188{
1189 /* we want [sp] */
1190 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1191}
1192
1193/* Exception Handling Support */
1194
1195/* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1196 pointers. */
1197int
1198m32c_eh_return_data_regno (int n)
1199{
1200 switch (n)
1201 {
1202 case 0:
1203 return A0_REGNO;
1204 case 1:
c6004917
RIL		 1205 if (TARGET_A16)
1206 return R3_REGNO;
1207 else
1208 return R1_REGNO;
38b2d076
DD		 1209 default:
1210 return INVALID_REGNUM;
1211 }
1212}
1213
1214/* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1215 m32c_emit_eh_epilogue. */
1216rtx
1217m32c_eh_return_stackadj_rtx (void)
1218{
1219 if (!cfun->machine->eh_stack_adjust)
1220 {
1221 rtx sa;
1222
99920b6f 1223 sa = gen_rtx_REG (Pmode, R0_REGNO);
38b2d076
DD		 1224 cfun->machine->eh_stack_adjust = sa;
1225 }
1226 return cfun->machine->eh_stack_adjust;
1227}
1228
1229/* Registers That Address the Stack Frame */
1230
1231/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1232 the original spec called for dwarf numbers to vary with register
1233 width as well, for example, r0l, r0, and r2r0 would each have
1234 different dwarf numbers. GCC doesn't support this, and we don't do
1235 it, and gdb seems to like it this way anyway. */
1236unsigned int
1237m32c_dwarf_frame_regnum (int n)
1238{
1239 switch (n)
1240 {
1241 case R0_REGNO:
1242 return 5;
1243 case R1_REGNO:
1244 return 6;
1245 case R2_REGNO:
1246 return 7;
1247 case R3_REGNO:
1248 return 8;
1249 case A0_REGNO:
1250 return 9;
1251 case A1_REGNO:
1252 return 10;
1253 case FB_REGNO:
1254 return 11;
1255 case SB_REGNO:
1256 return 19;
1257
1258 case SP_REGNO:
1259 return 12;
1260 case PC_REGNO:
1261 return 13;
1262 default:
1263 return DWARF_FRAME_REGISTERS + 1;
1264 }
1265}
1266
1267/* The frame looks like this:
1268
1269 ap -> +------------------------------
1270 | Return address (3 or 4 bytes)
1271 | Saved FB (2 or 4 bytes)
1272 fb -> +------------------------------
1273 | local vars
1274 | register saves fb
1275 | through r0 as needed
1276 sp -> +------------------------------
1277*/
1278
1279/* We use this to wrap all emitted insns in the prologue. */
1280static rtx
1281F (rtx x)
1282{
1283 RTX_FRAME_RELATED_P (x) = 1;
1284 return x;
1285}
1286
1287/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1288 how much the stack pointer moves for each, for each cpu family. */
1289static struct
1290{
1291 int reg1;
1292 int bit;
1293 int a16_bytes;
1294 int a24_bytes;
1295} pushm_info[] =
1296{
9d746d5e
DD		 1297 /* These are in reverse push (nearest-to-sp) order. */
1298 { R0_REGNO, 0x80, 2, 2 },
38b2d076 1299 { R1_REGNO, 0x40, 2, 2 },
9d746d5e
DD		 1300 { R2_REGNO, 0x20, 2, 2 },
1301 { R3_REGNO, 0x10, 2, 2 },
1302 { A0_REGNO, 0x08, 2, 4 },
1303 { A1_REGNO, 0x04, 2, 4 },
1304 { SB_REGNO, 0x02, 2, 4 },
1305 { FB_REGNO, 0x01, 2, 4 }
38b2d076
DD		 1306};
1307
1308#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1309
1310/* Returns TRUE if we need to save/restore the given register. We
1311 save everything for exception handlers, so that any register can be
1312 unwound. For interrupt handlers, we save everything if the handler
1313 calls something else (because we don't know what *that* function
1314 might do), but try to be a bit smarter if the handler is a leaf
1315 function. We always save $a0, though, because we use that in the
85f65093 1316 epilogue to copy $fb to $sp. */
38b2d076
DD		 1317static int
1318need_to_save (int regno)
1319{
1320 if (fixed_regs[regno])
1321 return 0;
ad516a74 1322 if (crtl->calls_eh_return)
38b2d076
DD		 1323 return 1;
1324 if (regno == FP_REGNO)
1325 return 0;
1326 if (cfun->machine->is_interrupt
65655f79
DD		 1327 && (!cfun->machine->is_leaf
1328 || (regno == A0_REGNO
1329 && m32c_function_needs_enter ())
1330 ))
38b2d076 1331 return 1;
6fb5fa3c 1332 if (df_regs_ever_live_p (regno)
38b2d076
DD		 1333 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1334 return 1;
1335 return 0;
1336}
1337
1338/* This function contains all the intelligence about saving and
1339 restoring registers. It always figures out the register save set.
1340 When called with PP_justcount, it merely returns the size of the
1341 save set (for eliminating the frame pointer, for example). When
1342 called with PP_pushm or PP_popm, it emits the appropriate
1343 instructions for saving (pushm) or restoring (popm) the
1344 registers. */
1345static int
1346m32c_pushm_popm (Push_Pop_Type ppt)
1347{
1348 int reg_mask = 0;
1349 int byte_count = 0, bytes;
1350 int i;
1351 rtx dwarf_set[PUSHM_N];
1352 int n_dwarfs = 0;
1353 int nosave_mask = 0;
1354
305da3ec
JH		 1355 if (crtl->return_rtx
1356 && GET_CODE (crtl->return_rtx) == PARALLEL
ad516a74 1357 && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
38b2d076 1358 {
305da3ec 1359 rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
38b2d076
DD		 1360 rtx rv = XEXP (exp, 0);
1361 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1362
1363 if (rv_bytes > 2)
1364 nosave_mask |= 0x20; /* PSI, SI */
1365 else
1366 nosave_mask |= 0xf0; /* DF */
1367 if (rv_bytes > 4)
1368 nosave_mask |= 0x50; /* DI */
1369 }
1370
1371 for (i = 0; i < (int) PUSHM_N; i++)
1372 {
1373 /* Skip if neither register needs saving. */
1374 if (!need_to_save (pushm_info[i].reg1))
1375 continue;
1376
1377 if (pushm_info[i].bit & nosave_mask)
1378 continue;
1379
1380 reg_mask |= pushm_info[i].bit;
1381 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1382
1383 if (ppt == PP_pushm)
1384 {
1385 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1386 rtx addr;
1387
1388 /* Always use stack_pointer_rtx instead of calling
1389 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1390 that there is a single rtx representing the stack pointer,
1391 namely stack_pointer_rtx, and uses == to recognize it. */
1392 addr = stack_pointer_rtx;
1393
1394 if (byte_count != 0)
1395 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1396
1397 dwarf_set[n_dwarfs++] =
1398 gen_rtx_SET (VOIDmode,
1399 gen_rtx_MEM (mode, addr),
1400 gen_rtx_REG (mode, pushm_info[i].reg1));
1401 F (dwarf_set[n_dwarfs - 1]);
1402
1403 }
1404 byte_count += bytes;
1405 }
1406
1407 if (cfun->machine->is_interrupt)
1408 {
1409 cfun->machine->intr_pushm = reg_mask & 0xfe;
1410 reg_mask = 0;
1411 byte_count = 0;
1412 }
1413
1414 if (cfun->machine->is_interrupt)
1415 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1416 if (need_to_save (i))
1417 {
1418 byte_count += 2;
1419 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1420 }
1421
1422 if (ppt == PP_pushm && byte_count)
1423 {
1424 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1425 rtx pushm;
1426
1427 if (reg_mask)
1428 {
1429 XVECEXP (note, 0, 0)
1430 = gen_rtx_SET (VOIDmode,
1431 stack_pointer_rtx,
1432 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1433 stack_pointer_rtx,
1434 GEN_INT (-byte_count)));
1435 F (XVECEXP (note, 0, 0));
1436
1437 for (i = 0; i < n_dwarfs; i++)
1438 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1439
1440 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1441
444d6efe 1442 add_reg_note (pushm, REG_FRAME_RELATED_EXPR, note);
38b2d076
DD		 1443 }
1444
1445 if (cfun->machine->is_interrupt)
1446 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1447 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1448 {
1449 if (TARGET_A16)
1450 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1451 else
1452 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1453 F (pushm);
1454 }
1455 }
1456 if (ppt == PP_popm && byte_count)
1457 {
38b2d076
DD		 1458 if (cfun->machine->is_interrupt)
1459 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1460 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1461 {
1462 if (TARGET_A16)
b3fdec9e 1463 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
38b2d076 1464 else
b3fdec9e 1465 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
38b2d076
DD		 1466 }
1467 if (reg_mask)
1468 emit_insn (gen_popm (GEN_INT (reg_mask)));
1469 }
1470
1471 return byte_count;
1472}
1473
1474/* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1475 diagrams our call frame. */
1476int
1477m32c_initial_elimination_offset (int from, int to)
1478{
1479 int ofs = 0;
1480
1481 if (from == AP_REGNO)
1482 {
1483 if (TARGET_A16)
1484 ofs += 5;
1485 else
1486 ofs += 8;
1487 }
1488
1489 if (to == SP_REGNO)
1490 {
1491 ofs += m32c_pushm_popm (PP_justcount);
1492 ofs += get_frame_size ();
1493 }
1494
1495 /* Account for push rounding. */
1496 if (TARGET_A24)
1497 ofs = (ofs + 1) & ~1;
1498#if DEBUG0
1499 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1500 to, ofs);
1501#endif
1502 return ofs;
1503}
1504
1505/* Passing Function Arguments on the Stack */
1506
38b2d076
DD		 1507/* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1508 M32C has word stacks. */
444d6efe 1509unsigned int
38b2d076
DD		 1510m32c_push_rounding (int n)
1511{
1512 if (TARGET_R8C || TARGET_M16C)
1513 return n;
1514 return (n + 1) & ~1;
1515}
1516
1517/* Passing Arguments in Registers */
1518
cd34bbe8
NF		 1519/* Implements TARGET_FUNCTION_ARG. Arguments are passed partly in
1520 registers, partly on stack. If our function returns a struct, a
1521 pointer to a buffer for it is at the top of the stack (last thing
1522 pushed). The first few real arguments may be in registers as
1523 follows:
38b2d076
DD		 1524
1525 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1526 arg2 in r2 if it's HI (else pushed on stack)
1527 rest on stack
1528 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1529 rest on stack
1530
1531 Structs are not passed in registers, even if they fit. Only
1532 integer and pointer types are passed in registers.
1533
1534 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1535 r2 if it fits. */
cd34bbe8
NF		 1536#undef TARGET_FUNCTION_ARG
1537#define TARGET_FUNCTION_ARG m32c_function_arg
1538static rtx
38b2d076 1539m32c_function_arg (CUMULATIVE_ARGS * ca,
cd34bbe8 1540 enum machine_mode mode, const_tree type, bool named)
38b2d076
DD		 1541{
1542 /* Can return a reg, parallel, or 0 for stack */
1543 rtx rv = NULL_RTX;
1544#if DEBUG0
1545 fprintf (stderr, "func_arg %d (%s, %d)\n",
1546 ca->parm_num, mode_name[mode], named);
1547 debug_tree (type);
1548#endif
1549
1550 if (mode == VOIDmode)
1551 return GEN_INT (0);
1552
1553 if (ca->force_mem || !named)
1554 {
1555#if DEBUG0
1556 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1557 named);
1558#endif
1559 return NULL_RTX;
1560 }
1561
1562 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1563 return NULL_RTX;
1564
9d746d5e
DD		 1565 if (type && AGGREGATE_TYPE_P (type))
1566 return NULL_RTX;
1567
38b2d076
DD		 1568 switch (ca->parm_num)
1569 {
1570 case 1:
1571 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1572 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1573 break;
1574
1575 case 2:
1576 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1577 rv = gen_rtx_REG (mode, R2_REGNO);
1578 break;
1579 }
1580
1581#if DEBUG0
1582 debug_rtx (rv);
1583#endif
1584 return rv;
1585}
1586
1587#undef TARGET_PASS_BY_REFERENCE
1588#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1589static bool
1590m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1591 enum machine_mode mode ATTRIBUTE_UNUSED,
586de218 1592 const_tree type ATTRIBUTE_UNUSED,
38b2d076
DD		 1593 bool named ATTRIBUTE_UNUSED)
1594{
1595 return 0;
1596}
1597
1598/* Implements INIT_CUMULATIVE_ARGS. */
1599void
1600m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
9d746d5e 1601 tree fntype,
38b2d076 1602 rtx libname ATTRIBUTE_UNUSED,
9d746d5e 1603 tree fndecl,
38b2d076
DD		 1604 int n_named_args ATTRIBUTE_UNUSED)
1605{
9d746d5e
DD		 1606 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1607 ca->force_mem = 1;
1608 else
1609 ca->force_mem = 0;
38b2d076
DD		 1610 ca->parm_num = 1;
1611}
1612
cd34bbe8
NF		 1613/* Implements TARGET_FUNCTION_ARG_ADVANCE. force_mem is set for
1614 functions returning structures, so we always reset that. Otherwise,
1615 we only need to know the sequence number of the argument to know what
1616 to do with it. */
1617#undef TARGET_FUNCTION_ARG_ADVANCE
1618#define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
1619static void
38b2d076
DD		 1620m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1621 enum machine_mode mode ATTRIBUTE_UNUSED,
cd34bbe8
NF		 1622 const_tree type ATTRIBUTE_UNUSED,
1623 bool named ATTRIBUTE_UNUSED)
38b2d076
DD		 1624{
1625 if (ca->force_mem)
1626 ca->force_mem = 0;
9d746d5e
DD		 1627 else
1628 ca->parm_num++;
38b2d076
DD		 1629}
1630
c2ed6cf8
NF		 1631/* Implements TARGET_FUNCTION_ARG_BOUNDARY. */
1632#undef TARGET_FUNCTION_ARG_BOUNDARY
1633#define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
1634static unsigned int
1635m32c_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
1636 const_tree type ATTRIBUTE_UNUSED)
1637{
1638 return (TARGET_A16 ? 8 : 16);
1639}
1640
38b2d076
DD		 1641/* Implements FUNCTION_ARG_REGNO_P. */
1642int
1643m32c_function_arg_regno_p (int r)
1644{
1645 if (TARGET_A24)
1646 return (r == R0_REGNO);
1647 return (r == R1_REGNO || r == R2_REGNO);
1648}
1649
e9555b13 1650/* HImode and PSImode are the two "native" modes as far as GCC is
85f65093 1651 concerned, but the chips also support a 32-bit mode which is used
e9555b13
DD		 1652 for some opcodes in R8C/M16C and for reset vectors and such. */
1653#undef TARGET_VALID_POINTER_MODE
1654#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
23fed240 1655static bool
e9555b13
DD		 1656m32c_valid_pointer_mode (enum machine_mode mode)
1657{
e9555b13
DD		 1658 if (mode == HImode
1659 || mode == PSImode
1660 || mode == SImode
1661 )
1662 return 1;
1663 return 0;
1664}
1665
38b2d076
DD		 1666/* How Scalar Function Values Are Returned */
1667
2a31793e 1668/* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some
38b2d076
DD		 1669 combination of registers starting there (r2r0 for longs, r3r1r2r0
1670 for long long, r3r2r1r0 for doubles), except that that ABI
1671 currently doesn't work because it ends up using all available
1672 general registers and gcc often can't compile it. So, instead, we
1673 return anything bigger than 16 bits in "mem0" (effectively, a
1674 memory location). */
2a31793e
AS		 1675
1676#undef TARGET_LIBCALL_VALUE
1677#define TARGET_LIBCALL_VALUE m32c_libcall_value
1678
1679static rtx
1680m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
38b2d076
DD		 1681{
1682 /* return reg or parallel */
1683#if 0
1684 /* FIXME: GCC has difficulty returning large values in registers,
1685 because that ties up most of the general registers and gives the
1686 register allocator little to work with. Until we can resolve
1687 this, large values are returned in memory. */
1688 if (mode == DFmode)
1689 {
1690 rtx rv;
1691
1692 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1693 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1694 gen_rtx_REG (HImode,
1695 R0_REGNO),
1696 GEN_INT (0));
1697 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1698 gen_rtx_REG (HImode,
1699 R1_REGNO),
1700 GEN_INT (2));
1701 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1702 gen_rtx_REG (HImode,
1703 R2_REGNO),
1704 GEN_INT (4));
1705 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1706 gen_rtx_REG (HImode,
1707 R3_REGNO),
1708 GEN_INT (6));
1709 return rv;
1710 }
1711
1712 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1713 {
1714 rtx rv;
1715
1716 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1717 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1718 gen_rtx_REG (mode,
1719 R0_REGNO),
1720 GEN_INT (0));
1721 return rv;
1722 }
1723#endif
1724
1725 if (GET_MODE_SIZE (mode) > 2)
1726 return gen_rtx_REG (mode, MEM0_REGNO);
1727 return gen_rtx_REG (mode, R0_REGNO);
1728}
1729
2a31793e 1730/* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same
38b2d076 1731 conventions. */
2a31793e
AS		 1732
1733#undef TARGET_FUNCTION_VALUE
1734#define TARGET_FUNCTION_VALUE m32c_function_value
1735
1736static rtx
1737m32c_function_value (const_tree valtype,
1738 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1739 bool outgoing ATTRIBUTE_UNUSED)
38b2d076
DD		 1740{
1741 /* return reg or parallel */
586de218 1742 const enum machine_mode mode = TYPE_MODE (valtype);
2a31793e
AS		 1743 return m32c_libcall_value (mode, NULL_RTX);
1744}
1745
f28f2337
AS		 1746/* Implements TARGET_FUNCTION_VALUE_REGNO_P. */
1747
1748#undef TARGET_FUNCTION_VALUE_REGNO_P
1749#define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
2a31793e 1750
f28f2337 1751static bool
2a31793e
AS		 1752m32c_function_value_regno_p (const unsigned int regno)
1753{
1754 return (regno == R0_REGNO || regno == MEM0_REGNO);
38b2d076
DD		 1755}
1756
1757/* How Large Values Are Returned */
1758
1759/* We return structures by pushing the address on the stack, even if
1760 we use registers for the first few "real" arguments. */
1761#undef TARGET_STRUCT_VALUE_RTX
1762#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1763static rtx
1764m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1765 int incoming ATTRIBUTE_UNUSED)
1766{
1767 return 0;
1768}
1769
1770/* Function Entry and Exit */
1771
1772/* Implements EPILOGUE_USES. Interrupts restore all registers. */
1773int
1774m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1775{
1776 if (cfun->machine->is_interrupt)
1777 return 1;
1778 return 0;
1779}
1780
1781/* Implementing the Varargs Macros */
1782
1783#undef TARGET_STRICT_ARGUMENT_NAMING
1784#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1785static bool
1786m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1787{
1788 return 1;
1789}
1790
1791/* Trampolines for Nested Functions */
1792
1793/*
1794 m16c:
1795 1 0000 75C43412 mov.w #0x1234,a0
1796 2 0004 FC000000 jmp.a label
1797
1798 m32c:
1799 1 0000 BC563412 mov.l:s #0x123456,a0
1800 2 0004 CC000000 jmp.a label
1801*/
1802
1803/* Implements TRAMPOLINE_SIZE. */
1804int
1805m32c_trampoline_size (void)
1806{
1807 /* Allocate extra space so we can avoid the messy shifts when we
1808 initialize the trampoline; we just write past the end of the
1809 opcode. */
1810 return TARGET_A16 ? 8 : 10;
1811}
1812
1813/* Implements TRAMPOLINE_ALIGNMENT. */
1814int
1815m32c_trampoline_alignment (void)
1816{
1817 return 2;
1818}
1819
229fbccb
RH		 1820/* Implements TARGET_TRAMPOLINE_INIT. */
1821
1822#undef TARGET_TRAMPOLINE_INIT
1823#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1824static void
1825m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
38b2d076 1826{
229fbccb
RH		 1827 rtx function = XEXP (DECL_RTL (fndecl), 0);
1828
1829#define A0(m,i) adjust_address (m_tramp, m, i)
38b2d076
DD		 1830 if (TARGET_A16)
1831 {
1832 /* Note: we subtract a "word" because the moves want signed
1833 constants, not unsigned constants. */
1834 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1835 emit_move_insn (A0 (HImode, 2), chainval);
1836 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
85f65093
KH		 1837 /* We use 16-bit addresses here, but store the zero to turn it
1838 into a 24-bit offset. */
38b2d076
DD		 1839 emit_move_insn (A0 (HImode, 5), function);
1840 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1841 }
1842 else
1843 {
1844 /* Note that the PSI moves actually write 4 bytes. Make sure we
1845 write stuff out in the right order, and leave room for the
1846 extra byte at the end. */
1847 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1848 emit_move_insn (A0 (PSImode, 1), chainval);
1849 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1850 emit_move_insn (A0 (PSImode, 5), function);
1851 }
1852#undef A0
1853}
1854
07127a0a
DD		 1855/* Implicit Calls to Library Routines */
1856
1857#undef TARGET_INIT_LIBFUNCS
1858#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1859static void
1860m32c_init_libfuncs (void)
1861{
f90b7a5a
PB		 1862 /* We do this because the M32C has an HImode operand, but the
1863 M16C has an 8-bit operand. Since gcc looks at the match data
1864 and not the expanded rtl, we have to reset the optab so that
1865 the right modes are found. */
07127a0a
DD		 1866 if (TARGET_A24)
1867 {
947131ba
RS		 1868 set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
1869 set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
1870 set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstorepsi4_24);
07127a0a
DD		 1871 }
1872}
1873
38b2d076
DD		 1874/* Addressing Modes */
1875
c6c3dba9
PB		 1876/* The r8c/m32c family supports a wide range of non-orthogonal
1877 addressing modes, including the ability to double-indirect on *some*
1878 of them. Not all insns support all modes, either, but we rely on
1879 predicates and constraints to deal with that. */
1880#undef TARGET_LEGITIMATE_ADDRESS_P
1881#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1882bool
1883m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
38b2d076
DD		 1884{
1885 int mode_adjust;
1886 if (CONSTANT_P (x))
1887 return 1;
1888
5fd5d713
DD		 1889 if (TARGET_A16 && GET_MODE (x) != HImode && GET_MODE (x) != SImode)
1890 return 0;
1891 if (TARGET_A24 && GET_MODE (x) != PSImode)
1892 return 0;
1893
38b2d076
DD		 1894 /* Wide references to memory will be split after reload, so we must
1895 ensure that all parts of such splits remain legitimate
1896 addresses. */
1897 mode_adjust = GET_MODE_SIZE (mode) - 1;
1898
1899 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1900 if (GET_CODE (x) == PRE_DEC
1901 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1902 {
1903 return (GET_CODE (XEXP (x, 0)) == REG
1904 && REGNO (XEXP (x, 0)) == SP_REGNO);
1905 }
1906
1907#if 0
1908 /* This is the double indirection detection, but it currently
1909 doesn't work as cleanly as this code implies, so until we've had
1910 a chance to debug it, leave it disabled. */
1911 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1912 {
1913#if DEBUG_DOUBLE
1914 fprintf (stderr, "double indirect\n");
1915#endif
1916 x = XEXP (x, 0);
1917 }
1918#endif
1919
1920 encode_pattern (x);
1921 if (RTX_IS ("r"))
1922 {
1923 /* Most indexable registers can be used without displacements,
1924 although some of them will be emitted with an explicit zero
1925 to please the assembler. */
1926 switch (REGNO (patternr[0]))
1927 {
38b2d076
DD		 1928 case A1_REGNO:
1929 case SB_REGNO:
1930 case FB_REGNO:
1931 case SP_REGNO:
5fd5d713
DD		 1932 if (TARGET_A16 && GET_MODE (x) == SImode)
1933 return 0;
1934 case A0_REGNO:
38b2d076
DD		 1935 return 1;
1936
1937 default:
1938 if (IS_PSEUDO (patternr[0], strict))
1939 return 1;
1940 return 0;
1941 }
1942 }
5fd5d713
DD		 1943
1944 if (TARGET_A16 && GET_MODE (x) == SImode)
1945 return 0;
1946
38b2d076
DD		 1947 if (RTX_IS ("+ri"))
1948 {
1949 /* This is more interesting, because different base registers
1950 allow for different displacements - both range and signedness
1951 - and it differs from chip series to chip series too. */
1952 int rn = REGNO (patternr[1]);
1953 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1954 switch (rn)
1955 {
1956 case A0_REGNO:
1957 case A1_REGNO:
1958 case SB_REGNO:
1959 /* The syntax only allows positive offsets, but when the
1960 offsets span the entire memory range, we can simulate
1961 negative offsets by wrapping. */
1962 if (TARGET_A16)
1963 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1964 if (rn == SB_REGNO)
1965 return (offs >= 0 && offs <= 65535 - mode_adjust);
1966 /* A0 or A1 */
1967 return (offs >= -16777216 && offs <= 16777215);
1968
1969 case FB_REGNO:
1970 if (TARGET_A16)
1971 return (offs >= -128 && offs <= 127 - mode_adjust);
1972 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1973
1974 case SP_REGNO:
1975 return (offs >= -128 && offs <= 127 - mode_adjust);
1976
1977 default:
1978 if (IS_PSEUDO (patternr[1], strict))
1979 return 1;
1980 return 0;
1981 }
1982 }
1983 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1984 {
1985 rtx reg = patternr[1];
1986
1987 /* We don't know where the symbol is, so only allow base
1988 registers which support displacements spanning the whole
1989 address range. */
1990 switch (REGNO (reg))
1991 {
1992 case A0_REGNO:
1993 case A1_REGNO:
1994 /* $sb needs a secondary reload, but since it's involved in
1995 memory address reloads too, we don't deal with it very
1996 well. */
1997 /* case SB_REGNO: */
1998 return 1;
1999 default:
2000 if (IS_PSEUDO (reg, strict))
2001 return 1;
2002 return 0;
2003 }
2004 }
2005 return 0;
2006}
2007
2008/* Implements REG_OK_FOR_BASE_P. */
2009int
2010m32c_reg_ok_for_base_p (rtx x, int strict)
2011{
2012 if (GET_CODE (x) != REG)
2013 return 0;
2014 switch (REGNO (x))
2015 {
2016 case A0_REGNO:
2017 case A1_REGNO:
2018 case SB_REGNO:
2019 case FB_REGNO:
2020 case SP_REGNO:
2021 return 1;
2022 default:
2023 if (IS_PSEUDO (x, strict))
2024 return 1;
2025 return 0;
2026 }
2027}
2028
04aff2c0 2029/* We have three choices for choosing fb->aN offsets. If we choose -128,
85f65093 2030 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
04aff2c0
DD		 2031 like this:
2032 EB 4B FF mova -128[$fb],$a0
2033 D8 0C FF FF mov.w:Q #0,-1[$a0]
2034
85f65093 2035 Alternately, we subtract the frame size, and hopefully use 8-bit aN
04aff2c0
DD		 2036 displacements:
2037 7B F4 stc $fb,$a0
2038 77 54 00 01 sub #256,$a0
2039 D8 08 01 mov.w:Q #0,1[$a0]
2040
2041 If we don't offset (i.e. offset by zero), we end up with:
2042 7B F4 stc $fb,$a0
2043 D8 0C 00 FF mov.w:Q #0,-256[$a0]
2044
2045 We have to subtract *something* so that we have a PLUS rtx to mark
2046 that we've done this reload. The -128 offset will never result in
85f65093 2047 an 8-bit aN offset, and the payoff for the second case is five
04aff2c0
DD		 2048 loads *if* those loads are within 256 bytes of the other end of the
2049 frame, so the third case seems best. Note that we subtract the
2050 zero, but detect that in the addhi3 pattern. */
2051
ea471af0
JM		 2052#define BIG_FB_ADJ 0
2053
38b2d076
DD		 2054/* Implements LEGITIMIZE_ADDRESS. The only address we really have to
2055 worry about is frame base offsets, as $fb has a limited
2056 displacement range. We deal with this by attempting to reload $fb
2057 itself into an address register; that seems to result in the best
2058 code. */
506d7b68
PB		 2059#undef TARGET_LEGITIMIZE_ADDRESS
2060#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
2061static rtx
2062m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2063 enum machine_mode mode)
38b2d076
DD		 2064{
2065#if DEBUG0
2066 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
506d7b68 2067 debug_rtx (x);
38b2d076
DD		 2068 fprintf (stderr, "\n");
2069#endif
2070
506d7b68
PB		 2071 if (GET_CODE (x) == PLUS
2072 && GET_CODE (XEXP (x, 0)) == REG
2073 && REGNO (XEXP (x, 0)) == FB_REGNO
2074 && GET_CODE (XEXP (x, 1)) == CONST_INT
2075 && (INTVAL (XEXP (x, 1)) < -128
2076 || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
38b2d076
DD		 2077 {
2078 /* reload FB to A_REGS */
38b2d076 2079 rtx temp = gen_reg_rtx (Pmode);
506d7b68
PB		 2080 x = copy_rtx (x);
2081 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
2082 XEXP (x, 0) = temp;
38b2d076
DD		 2083 }
2084
506d7b68 2085 return x;
38b2d076
DD		 2086}
2087
2088/* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
2089int
2090m32c_legitimize_reload_address (rtx * x,
2091 enum machine_mode mode,
2092 int opnum,
2093 int type, int ind_levels ATTRIBUTE_UNUSED)
2094{
2095#if DEBUG0
2096 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
2097 mode_name[mode]);
2098 debug_rtx (*x);
2099#endif
2100
2101 /* At one point, this function tried to get $fb copied to an address
2102 register, which in theory would maximize sharing, but gcc was
2103 *also* still trying to reload the whole address, and we'd run out
2104 of address registers. So we let gcc do the naive (but safe)
2105 reload instead, when the above function doesn't handle it for
04aff2c0
DD		 2106 us.
2107
2108 The code below is a second attempt at the above. */
2109
2110 if (GET_CODE (*x) == PLUS
2111 && GET_CODE (XEXP (*x, 0)) == REG
2112 && REGNO (XEXP (*x, 0)) == FB_REGNO
2113 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2114 && (INTVAL (XEXP (*x, 1)) < -128
2115 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2116 {
2117 rtx sum;
2118 int offset = INTVAL (XEXP (*x, 1));
2119 int adjustment = -BIG_FB_ADJ;
2120
2121 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2122 GEN_INT (adjustment));
2123 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2124 if (type == RELOAD_OTHER)
2125 type = RELOAD_FOR_OTHER_ADDRESS;
2126 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2127 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
444d6efe 2128 (enum reload_type) type);
04aff2c0
DD		 2129 return 1;
2130 }
2131
2132 if (GET_CODE (*x) == PLUS
2133 && GET_CODE (XEXP (*x, 0)) == PLUS
2134 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2135 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2136 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2137 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2138 )
2139 {
2140 if (type == RELOAD_OTHER)
2141 type = RELOAD_FOR_OTHER_ADDRESS;
2142 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2143 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
444d6efe 2144 (enum reload_type) type);
04aff2c0
DD		 2145 return 1;
2146 }
38b2d076
DD		 2147
2148 return 0;
2149}
2150
5fd5d713
DD		 2151/* Return the appropriate mode for a named address pointer. */
2152#undef TARGET_ADDR_SPACE_POINTER_MODE
2153#define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
2154static enum machine_mode
2155m32c_addr_space_pointer_mode (addr_space_t addrspace)
2156{
2157 switch (addrspace)
2158 {
2159 case ADDR_SPACE_GENERIC:
2160 return TARGET_A24 ? PSImode : HImode;
2161 case ADDR_SPACE_FAR:
2162 return SImode;
2163 default:
2164 gcc_unreachable ();
2165 }
2166}
2167
2168/* Return the appropriate mode for a named address address. */
2169#undef TARGET_ADDR_SPACE_ADDRESS_MODE
2170#define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
2171static enum machine_mode
2172m32c_addr_space_address_mode (addr_space_t addrspace)
2173{
2174 switch (addrspace)
2175 {
2176 case ADDR_SPACE_GENERIC:
2177 return TARGET_A24 ? PSImode : HImode;
2178 case ADDR_SPACE_FAR:
2179 return SImode;
2180 default:
2181 gcc_unreachable ();
2182 }
2183}
2184
2185/* Like m32c_legitimate_address_p, except with named addresses. */
2186#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
2187#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
2188 m32c_addr_space_legitimate_address_p
2189static bool
2190m32c_addr_space_legitimate_address_p (enum machine_mode mode, rtx x,
2191 bool strict, addr_space_t as)
2192{
2193 if (as == ADDR_SPACE_FAR)
2194 {
2195 if (TARGET_A24)
2196 return 0;
2197 encode_pattern (x);
2198 if (RTX_IS ("r"))
2199 {
2200 if (GET_MODE (x) != SImode)
2201 return 0;
2202 switch (REGNO (patternr[0]))
2203 {
2204 case A0_REGNO:
2205 return 1;
2206
2207 default:
2208 if (IS_PSEUDO (patternr[0], strict))
2209 return 1;
2210 return 0;
2211 }
2212 }
2213 if (RTX_IS ("+^Sri"))
2214 {
2215 int rn = REGNO (patternr[3]);
2216 HOST_WIDE_INT offs = INTVAL (patternr[4]);
2217 if (GET_MODE (patternr[3]) != HImode)
2218 return 0;
2219 switch (rn)
2220 {
2221 case A0_REGNO:
2222 return (offs >= 0 && offs <= 0xfffff);
2223
2224 default:
2225 if (IS_PSEUDO (patternr[3], strict))
2226 return 1;
2227 return 0;
2228 }
2229 }
2230 if (RTX_IS ("+^Srs"))
2231 {
2232 int rn = REGNO (patternr[3]);
2233 if (GET_MODE (patternr[3]) != HImode)
2234 return 0;
2235 switch (rn)
2236 {
2237 case A0_REGNO:
2238 return 1;
2239
2240 default:
2241 if (IS_PSEUDO (patternr[3], strict))
2242 return 1;
2243 return 0;
2244 }
2245 }
2246 if (RTX_IS ("+^S+ris"))
2247 {
2248 int rn = REGNO (patternr[4]);
2249 if (GET_MODE (patternr[4]) != HImode)
2250 return 0;
2251 switch (rn)
2252 {
2253 case A0_REGNO:
2254 return 1;
2255
2256 default:
2257 if (IS_PSEUDO (patternr[4], strict))
2258 return 1;
2259 return 0;
2260 }
2261 }
2262 if (RTX_IS ("s"))
2263 {
2264 return 1;
2265 }
2266 return 0;
2267 }
2268
2269 else if (as != ADDR_SPACE_GENERIC)
2270 gcc_unreachable ();
2271
2272 return m32c_legitimate_address_p (mode, x, strict);
2273}
2274
2275/* Like m32c_legitimate_address, except with named address support. */
2276#undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
2277#define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
2278static rtx
2279m32c_addr_space_legitimize_address (rtx x, rtx oldx, enum machine_mode mode,
2280 addr_space_t as)
2281{
2282 if (as != ADDR_SPACE_GENERIC)
2283 {
2284#if DEBUG0
2285 fprintf (stderr, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name[mode]);
2286 debug_rtx (x);
2287 fprintf (stderr, "\n");
2288#endif
2289
2290 if (GET_CODE (x) != REG)
2291 {
2292 x = force_reg (SImode, x);
2293 }
2294 return x;
2295 }
2296
2297 return m32c_legitimize_address (x, oldx, mode);
2298}
2299
2300/* Determine if one named address space is a subset of another. */
2301#undef TARGET_ADDR_SPACE_SUBSET_P
2302#define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
2303static bool
2304m32c_addr_space_subset_p (addr_space_t subset, addr_space_t superset)
2305{
2306 gcc_assert (subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_FAR);
2307 gcc_assert (superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_FAR);
2308
2309 if (subset == superset)
2310 return true;
2311
2312 else
2313 return (subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_FAR);
2314}
2315
2316#undef TARGET_ADDR_SPACE_CONVERT
2317#define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
2318/* Convert from one address space to another. */
2319static rtx
2320m32c_addr_space_convert (rtx op, tree from_type, tree to_type)
2321{
2322 addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));
2323 addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));
2324 rtx result;
2325
2326 gcc_assert (from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR);
2327 gcc_assert (to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR);
2328
2329 if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR)
2330 {
2331 /* This is unpredictable, as we're truncating off usable address
2332 bits. */
2333
2334 result = gen_reg_rtx (HImode);
2335 emit_move_insn (result, simplify_subreg (HImode, op, SImode, 0));
2336 return result;
2337 }
2338 else if (to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC)
2339 {
2340 /* This always works. */
2341 result = gen_reg_rtx (SImode);
2342 emit_insn (gen_zero_extendhisi2 (result, op));
2343 return result;
2344 }
2345 else
2346 gcc_unreachable ();
2347}
2348
38b2d076
DD		 2349/* Condition Code Status */
2350
2351#undef TARGET_FIXED_CONDITION_CODE_REGS
2352#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2353static bool
2354m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2355{
2356 *p1 = FLG_REGNO;
2357 *p2 = INVALID_REGNUM;
2358 return true;
2359}
2360
2361/* Describing Relative Costs of Operations */
2362
0e607518 2363/* Implements TARGET_REGISTER_MOVE_COST. We make impossible moves
38b2d076
DD		 2364 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2365 no opcodes to do that). We also discourage use of mem* registers
2366 since they're really memory. */
0e607518
AS		 2367
2368#undef TARGET_REGISTER_MOVE_COST
2369#define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
2370
2371static int
2372m32c_register_move_cost (enum machine_mode mode, reg_class_t from,
2373 reg_class_t to)
38b2d076
DD		 2374{
2375 int cost = COSTS_N_INSNS (3);
0e607518
AS		 2376 HARD_REG_SET cc;
2377
2378/* FIXME: pick real values, but not 2 for now. */
2379 COPY_HARD_REG_SET (cc, reg_class_contents[(int) from]);
2380 IOR_HARD_REG_SET (cc, reg_class_contents[(int) to]);
2381
2382 if (mode == QImode
2383 && hard_reg_set_intersect_p (cc, reg_class_contents[R23_REGS]))
38b2d076 2384 {
0e607518 2385 if (hard_reg_set_subset_p (cc, reg_class_contents[R23_REGS]))
38b2d076
DD		 2386 cost = COSTS_N_INSNS (1000);
2387 else
2388 cost = COSTS_N_INSNS (80);
2389 }
2390
2391 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2392 cost = COSTS_N_INSNS (1000);
2393
0e607518 2394 if (reg_classes_intersect_p (from, CR_REGS))
38b2d076
DD		 2395 cost += COSTS_N_INSNS (5);
2396
0e607518 2397 if (reg_classes_intersect_p (to, CR_REGS))
38b2d076
DD		 2398 cost += COSTS_N_INSNS (5);
2399
2400 if (from == MEM_REGS || to == MEM_REGS)
2401 cost += COSTS_N_INSNS (50);
0e607518
AS		 2402 else if (reg_classes_intersect_p (from, MEM_REGS)
2403 || reg_classes_intersect_p (to, MEM_REGS))
38b2d076
DD		 2404 cost += COSTS_N_INSNS (10);
2405
2406#if DEBUG0
2407 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
0e607518
AS		 2408 mode_name[mode], class_names[(int) from], class_names[(int) to],
2409 cost);
38b2d076
DD		 2410#endif
2411 return cost;
2412}
2413
0e607518
AS		 2414/* Implements TARGET_MEMORY_MOVE_COST. */
2415
2416#undef TARGET_MEMORY_MOVE_COST
2417#define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
2418
2419static int
38b2d076 2420m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
0e607518
AS		 2421 reg_class_t rclass ATTRIBUTE_UNUSED,
2422 bool in ATTRIBUTE_UNUSED)
38b2d076
DD		 2423{
2424 /* FIXME: pick real values. */
2425 return COSTS_N_INSNS (10);
2426}
2427
07127a0a
DD		 2428/* Here we try to describe when we use multiple opcodes for one RTX so
2429 that gcc knows when to use them. */
2430#undef TARGET_RTX_COSTS
2431#define TARGET_RTX_COSTS m32c_rtx_costs
2432static bool
f40751dd
JH		 2433m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
2434 bool speed ATTRIBUTE_UNUSED)
07127a0a
DD		 2435{
2436 switch (code)
2437 {
2438 case REG:
2439 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2440 *total += COSTS_N_INSNS (500);
2441 else
2442 *total += COSTS_N_INSNS (1);
2443 return true;
2444
2445 case ASHIFT:
2446 case LSHIFTRT:
2447 case ASHIFTRT:
2448 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2449 {
2450 /* mov.b r1l, r1h */
2451 *total += COSTS_N_INSNS (1);
2452 return true;
2453 }
2454 if (INTVAL (XEXP (x, 1)) > 8
2455 || INTVAL (XEXP (x, 1)) < -8)
2456 {
2457 /* mov.b #N, r1l */
2458 /* mov.b r1l, r1h */
2459 *total += COSTS_N_INSNS (2);
2460 return true;
2461 }
2462 return true;
2463
2464 case LE:
2465 case LEU:
2466 case LT:
2467 case LTU:
2468 case GT:
2469 case GTU:
2470 case GE:
2471 case GEU:
2472 case NE:
2473 case EQ:
2474 if (outer_code == SET)
2475 {
2476 *total += COSTS_N_INSNS (2);
2477 return true;
2478 }
2479 break;
2480
2481 case ZERO_EXTRACT:
2482 {
2483 rtx dest = XEXP (x, 0);
2484 rtx addr = XEXP (dest, 0);
2485 switch (GET_CODE (addr))
2486 {
2487 case CONST_INT:
2488 *total += COSTS_N_INSNS (1);
2489 break;
2490 case SYMBOL_REF:
2491 *total += COSTS_N_INSNS (3);
2492 break;
2493 default:
2494 *total += COSTS_N_INSNS (2);
2495 break;
2496 }
2497 return true;
2498 }
2499 break;
2500
2501 default:
2502 /* Reasonable default. */
2503 if (TARGET_A16 && GET_MODE(x) == SImode)
2504 *total += COSTS_N_INSNS (2);
2505 break;
2506 }
2507 return false;
2508}
2509
2510#undef TARGET_ADDRESS_COST
2511#define TARGET_ADDRESS_COST m32c_address_cost
2512static int
f40751dd 2513m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
07127a0a 2514{
80b093df 2515 int i;
07127a0a
DD		 2516 /* fprintf(stderr, "\naddress_cost\n");
2517 debug_rtx(addr);*/
2518 switch (GET_CODE (addr))
2519 {
2520 case CONST_INT:
80b093df
DD		 2521 i = INTVAL (addr);
2522 if (i == 0)
2523 return COSTS_N_INSNS(1);
2524 if (0 < i && i <= 255)
2525 return COSTS_N_INSNS(2);
2526 if (0 < i && i <= 65535)
2527 return COSTS_N_INSNS(3);
2528 return COSTS_N_INSNS(4);
07127a0a 2529 case SYMBOL_REF:
80b093df 2530 return COSTS_N_INSNS(4);
07127a0a 2531 case REG:
80b093df
DD		 2532 return COSTS_N_INSNS(1);
2533 case PLUS:
2534 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2535 {
2536 i = INTVAL (XEXP (addr, 1));
2537 if (i == 0)
2538 return COSTS_N_INSNS(1);
2539 if (0 < i && i <= 255)
2540 return COSTS_N_INSNS(2);
2541 if (0 < i && i <= 65535)
2542 return COSTS_N_INSNS(3);
2543 }
2544 return COSTS_N_INSNS(4);
07127a0a
DD		 2545 default:
2546 return 0;
2547 }
2548}
2549
38b2d076
DD		 2550/* Defining the Output Assembler Language */
2551
38b2d076
DD		 2552/* Output of Data */
2553
2554/* We may have 24 bit sizes, which is the native address size.
2555 Currently unused, but provided for completeness. */
2556#undef TARGET_ASM_INTEGER
2557#define TARGET_ASM_INTEGER m32c_asm_integer
2558static bool
2559m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2560{
2561 switch (size)
2562 {
2563 case 3:
2564 fprintf (asm_out_file, "\t.3byte\t");
2565 output_addr_const (asm_out_file, x);
2566 fputc ('\n', asm_out_file);
2567 return true;
e9555b13
DD		 2568 case 4:
2569 if (GET_CODE (x) == SYMBOL_REF)
2570 {
2571 fprintf (asm_out_file, "\t.long\t");
2572 output_addr_const (asm_out_file, x);
2573 fputc ('\n', asm_out_file);
2574 return true;
2575 }
2576 break;
38b2d076
DD		 2577 }
2578 return default_assemble_integer (x, size, aligned_p);
2579}
2580
2581/* Output of Assembler Instructions */
2582
a4174ebf 2583/* We use a lookup table because the addressing modes are non-orthogonal. */
38b2d076
DD		 2584
2585static struct
2586{
2587 char code;
2588 char const *pattern;
2589 char const *format;
2590}
2591const conversions[] = {
2592 { 0, "r", "0" },
2593
2594 { 0, "mr", "z[1]" },
2595 { 0, "m+ri", "3[2]" },
2596 { 0, "m+rs", "3[2]" },
5fd5d713
DD		 2597 { 0, "m+^Zrs", "5[4]" },
2598 { 0, "m+^Zri", "5[4]" },
2599 { 0, "m+^Z+ris", "7+6[5]" },
2600 { 0, "m+^Srs", "5[4]" },
2601 { 0, "m+^Sri", "5[4]" },
2602 { 0, "m+^S+ris", "7+6[5]" },
38b2d076
DD		 2603 { 0, "m+r+si", "4+5[2]" },
2604 { 0, "ms", "1" },
2605 { 0, "mi", "1" },
2606 { 0, "m+si", "2+3" },
2607
2608 { 0, "mmr", "[z[2]]" },
2609 { 0, "mm+ri", "[4[3]]" },
2610 { 0, "mm+rs", "[4[3]]" },
2611 { 0, "mm+r+si", "[5+6[3]]" },
2612 { 0, "mms", "[[2]]" },
2613 { 0, "mmi", "[[2]]" },
2614 { 0, "mm+si", "[4[3]]" },
2615
2616 { 0, "i", "#0" },
2617 { 0, "s", "#0" },
2618 { 0, "+si", "#1+2" },
2619 { 0, "l", "#0" },
2620
2621 { 'l', "l", "0" },
2622 { 'd', "i", "0" },
2623 { 'd', "s", "0" },
2624 { 'd', "+si", "1+2" },
2625 { 'D', "i", "0" },
2626 { 'D', "s", "0" },
2627 { 'D', "+si", "1+2" },
2628 { 'x', "i", "#0" },
2629 { 'X', "i", "#0" },
2630 { 'm', "i", "#0" },
2631 { 'b', "i", "#0" },
07127a0a 2632 { 'B', "i", "0" },
38b2d076
DD		 2633 { 'p', "i", "0" },
2634
2635 { 0, 0, 0 }
2636};
2637
2638/* This is in order according to the bitfield that pushm/popm use. */
2639static char const *pushm_regs[] = {
2640 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2641};
2642
2643/* Implements PRINT_OPERAND. */
2644void
2645m32c_print_operand (FILE * file, rtx x, int code)
2646{
2647 int i, j, b;
2648 const char *comma;
2649 HOST_WIDE_INT ival;
2650 int unsigned_const = 0;
ff485e71 2651 int force_sign;
38b2d076
DD		 2652
2653 /* Multiplies; constants are converted to sign-extended format but
2654 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2655 need. */
2656 if (code == 'u')
2657 {
2658 unsigned_const = 2;
2659 code = 0;
2660 }
2661 if (code == 'U')
2662 {
2663 unsigned_const = 1;
2664 code = 0;
2665 }
2666 /* This one is only for debugging; you can put it in a pattern to
2667 force this error. */
2668 if (code == '!')
2669 {
2670 fprintf (stderr, "dj: unreviewed pattern:");
2671 if (current_output_insn)
2672 debug_rtx (current_output_insn);
2673 gcc_unreachable ();
2674 }
2675 /* PSImode operations are either .w or .l depending on the target. */
2676 if (code == '&')
2677 {
2678 if (TARGET_A16)
2679 fprintf (file, "w");
2680 else
2681 fprintf (file, "l");
2682 return;
2683 }
2684 /* Inverted conditionals. */
2685 if (code == 'C')
2686 {
2687 switch (GET_CODE (x))
2688 {
2689 case LE:
2690 fputs ("gt", file);
2691 break;
2692 case LEU:
2693 fputs ("gtu", file);
2694 break;
2695 case LT:
2696 fputs ("ge", file);
2697 break;
2698 case LTU:
2699 fputs ("geu", file);
2700 break;
2701 case GT:
2702 fputs ("le", file);
2703 break;
2704 case GTU:
2705 fputs ("leu", file);
2706 break;
2707 case GE:
2708 fputs ("lt", file);
2709 break;
2710 case GEU:
2711 fputs ("ltu", file);
2712 break;
2713 case NE:
2714 fputs ("eq", file);
2715 break;
2716 case EQ:
2717 fputs ("ne", file);
2718 break;
2719 default:
2720 gcc_unreachable ();
2721 }
2722 return;
2723 }
2724 /* Regular conditionals. */
2725 if (code == 'c')
2726 {
2727 switch (GET_CODE (x))
2728 {
2729 case LE:
2730 fputs ("le", file);
2731 break;
2732 case LEU:
2733 fputs ("leu", file);
2734 break;
2735 case LT:
2736 fputs ("lt", file);
2737 break;
2738 case LTU:
2739 fputs ("ltu", file);
2740 break;
2741 case GT:
2742 fputs ("gt", file);
2743 break;
2744 case GTU:
2745 fputs ("gtu", file);
2746 break;
2747 case GE:
2748 fputs ("ge", file);
2749 break;
2750 case GEU:
2751 fputs ("geu", file);
2752 break;
2753 case NE:
2754 fputs ("ne", file);
2755 break;
2756 case EQ:
2757 fputs ("eq", file);
2758 break;
2759 default:
2760 gcc_unreachable ();
2761 }
2762 return;
2763 }
2764 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2765 operand. */
2766 if (code == 'h' && GET_MODE (x) == SImode)
2767 {
2768 x = m32c_subreg (HImode, x, SImode, 0);
2769 code = 0;
2770 }
2771 if (code == 'H' && GET_MODE (x) == SImode)
2772 {
2773 x = m32c_subreg (HImode, x, SImode, 2);
2774 code = 0;
2775 }
07127a0a
DD		 2776 if (code == 'h' && GET_MODE (x) == HImode)
2777 {
2778 x = m32c_subreg (QImode, x, HImode, 0);
2779 code = 0;
2780 }
2781 if (code == 'H' && GET_MODE (x) == HImode)
2782 {
2783 /* We can't actually represent this as an rtx. Do it here. */
2784 if (GET_CODE (x) == REG)
2785 {
2786 switch (REGNO (x))
2787 {
2788 case R0_REGNO:
2789 fputs ("r0h", file);
2790 return;
2791 case R1_REGNO:
2792 fputs ("r1h", file);
2793 return;
2794 default:
2795 gcc_unreachable();
2796 }
2797 }
2798 /* This should be a MEM. */
2799 x = m32c_subreg (QImode, x, HImode, 1);
2800 code = 0;
2801 }
2802 /* This is for BMcond, which always wants word register names. */
2803 if (code == 'h' && GET_MODE (x) == QImode)
2804 {
2805 if (GET_CODE (x) == REG)
2806 x = gen_rtx_REG (HImode, REGNO (x));
2807 code = 0;
2808 }
38b2d076
DD		 2809 /* 'x' and 'X' need to be ignored for non-immediates. */
2810 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2811 code = 0;
2812
2813 encode_pattern (x);
ff485e71 2814 force_sign = 0;
38b2d076
DD		 2815 for (i = 0; conversions[i].pattern; i++)
2816 if (conversions[i].code == code
2817 && streq (conversions[i].pattern, pattern))
2818 {
2819 for (j = 0; conversions[i].format[j]; j++)
2820 /* backslash quotes the next character in the output pattern. */
2821 if (conversions[i].format[j] == '\\')
2822 {
2823 fputc (conversions[i].format[j + 1], file);
2824 j++;
2825 }
2826 /* Digits in the output pattern indicate that the
2827 corresponding RTX is to be output at that point. */
2828 else if (ISDIGIT (conversions[i].format[j]))
2829 {
2830 rtx r = patternr[conversions[i].format[j] - '0'];
2831 switch (GET_CODE (r))
2832 {
2833 case REG:
2834 fprintf (file, "%s",
2835 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2836 break;
2837 case CONST_INT:
2838 switch (code)
2839 {
2840 case 'b':
07127a0a
DD		 2841 case 'B':
2842 {
2843 int v = INTVAL (r);
2844 int i = (int) exact_log2 (v);
2845 if (i == -1)
2846 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2847 if (i == -1)
2848 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2849 /* Bit position. */
2850 fprintf (file, "%d", i);
2851 }
38b2d076
DD		 2852 break;
2853 case 'x':
2854 /* Unsigned byte. */
2855 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2856 INTVAL (r) & 0xff);
2857 break;
2858 case 'X':
2859 /* Unsigned word. */
2860 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2861 INTVAL (r) & 0xffff);
2862 break;
2863 case 'p':
2864 /* pushm and popm encode a register set into a single byte. */
2865 comma = "";
2866 for (b = 7; b >= 0; b--)
2867 if (INTVAL (r) & (1 << b))
2868 {
2869 fprintf (file, "%s%s", comma, pushm_regs[b]);
2870 comma = ",";
2871 }
2872 break;
2873 case 'm':
2874 /* "Minus". Output -X */
2875 ival = (-INTVAL (r) & 0xffff);
2876 if (ival & 0x8000)
2877 ival = ival - 0x10000;
2878 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2879 break;
2880 default:
2881 ival = INTVAL (r);
2882 if (conversions[i].format[j + 1] == '[' && ival < 0)
2883 {
2884 /* We can simulate negative displacements by
2885 taking advantage of address space
2886 wrapping when the offset can span the
2887 entire address range. */
2888 rtx base =
2889 patternr[conversions[i].format[j + 2] - '0'];
2890 if (GET_CODE (base) == REG)
2891 switch (REGNO (base))
2892 {
2893 case A0_REGNO:
2894 case A1_REGNO:
2895 if (TARGET_A24)
2896 ival = 0x1000000 + ival;
2897 else
2898 ival = 0x10000 + ival;
2899 break;
2900 case SB_REGNO:
2901 if (TARGET_A16)
2902 ival = 0x10000 + ival;
2903 break;
2904 }
2905 }
2906 else if (code == 'd' && ival < 0 && j == 0)
2907 /* The "mova" opcode is used to do addition by
2908 computing displacements, but again, we need
2909 displacements to be unsigned *if* they're
2910 the only component of the displacement
2911 (i.e. no "symbol-4" type displacement). */
2912 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2913
2914 if (conversions[i].format[j] == '0')
2915 {
2916 /* More conversions to unsigned. */
2917 if (unsigned_const == 2)
2918 ival &= 0xffff;
2919 if (unsigned_const == 1)
2920 ival &= 0xff;
2921 }
2922 if (streq (conversions[i].pattern, "mi")
2923 || streq (conversions[i].pattern, "mmi"))
2924 {
2925 /* Integers used as addresses are unsigned. */
2926 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2927 }
ff485e71
DD		 2928 if (force_sign && ival >= 0)
2929 fputc ('+', file);
38b2d076
DD		 2930 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2931 break;
2932 }
2933 break;
2934 case CONST_DOUBLE:
2935 /* We don't have const_double constants. If it
2936 happens, make it obvious. */
2937 fprintf (file, "[const_double 0x%lx]",
2938 (unsigned long) CONST_DOUBLE_HIGH (r));
2939 break;
2940 case SYMBOL_REF:
2941 assemble_name (file, XSTR (r, 0));
2942 break;
2943 case LABEL_REF:
2944 output_asm_label (r);
2945 break;
2946 default:
2947 fprintf (stderr, "don't know how to print this operand:");
2948 debug_rtx (r);
2949 gcc_unreachable ();
2950 }
2951 }
2952 else
2953 {
2954 if (conversions[i].format[j] == 'z')
2955 {
2956 /* Some addressing modes *must* have a displacement,
2957 so insert a zero here if needed. */
2958 int k;
2959 for (k = j + 1; conversions[i].format[k]; k++)
2960 if (ISDIGIT (conversions[i].format[k]))
2961 {
2962 rtx reg = patternr[conversions[i].format[k] - '0'];
2963 if (GET_CODE (reg) == REG
2964 && (REGNO (reg) == SB_REGNO
2965 || REGNO (reg) == FB_REGNO
2966 || REGNO (reg) == SP_REGNO))
2967 fputc ('0', file);
2968 }
2969 continue;
2970 }
2971 /* Signed displacements off symbols need to have signs
2972 blended cleanly. */
2973 if (conversions[i].format[j] == '+'
ff485e71 2974 && (!code || code == 'D' || code == 'd')
38b2d076 2975 && ISDIGIT (conversions[i].format[j + 1])
ff485e71
DD		 2976 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2977 == CONST_INT))
2978 {
2979 force_sign = 1;
2980 continue;
2981 }
38b2d076
DD		 2982 fputc (conversions[i].format[j], file);
2983 }
2984 break;
2985 }
2986 if (!conversions[i].pattern)
2987 {
2988 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2989 pattern);
2990 debug_rtx (x);
2991 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2992 }
2993
2994 return;
2995}
2996
2997/* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2998 above for descriptions of what these do. */
2999int
3000m32c_print_operand_punct_valid_p (int c)
3001{
3002 if (c == '&' || c == '!')
3003 return 1;
3004 return 0;
3005}
3006
3007/* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
3008void
3009m32c_print_operand_address (FILE * stream, rtx address)
3010{
235e1fe8
NC		 3011 if (GET_CODE (address) == MEM)
3012 address = XEXP (address, 0);
3013 else
3014 /* cf: gcc.dg/asm-4.c. */
3015 gcc_assert (GET_CODE (address) == REG);
3016
3017 m32c_print_operand (stream, address, 0);
38b2d076
DD		 3018}
3019
3020/* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
3021 differently than general registers. */
3022void
3023m32c_output_reg_push (FILE * s, int regno)
3024{
3025 if (regno == FLG_REGNO)
3026 fprintf (s, "\tpushc\tflg\n");
3027 else
04aff2c0 3028 fprintf (s, "\tpush.%c\t%s\n",
38b2d076
DD		 3029 " bwll"[reg_push_size (regno)], reg_names[regno]);
3030}
3031
3032/* Likewise for ASM_OUTPUT_REG_POP. */
3033void
3034m32c_output_reg_pop (FILE * s, int regno)
3035{
3036 if (regno == FLG_REGNO)
3037 fprintf (s, "\tpopc\tflg\n");
3038 else
04aff2c0 3039 fprintf (s, "\tpop.%c\t%s\n",
38b2d076
DD		 3040 " bwll"[reg_push_size (regno)], reg_names[regno]);
3041}
3042
3043/* Defining target-specific uses of `__attribute__' */
3044
3045/* Used to simplify the logic below. Find the attributes wherever
3046 they may be. */
3047#define M32C_ATTRIBUTES(decl) \
3048 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
3049 : DECL_ATTRIBUTES (decl) \
3050 ? (DECL_ATTRIBUTES (decl)) \
3051 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
3052
3053/* Returns TRUE if the given tree has the "interrupt" attribute. */
3054static int
3055interrupt_p (tree node ATTRIBUTE_UNUSED)
3056{
3057 tree list = M32C_ATTRIBUTES (node);
3058 while (list)
3059 {
3060 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
3061 return 1;
3062 list = TREE_CHAIN (list);
3063 }
65655f79
DD		 3064 return fast_interrupt_p (node);
3065}
3066
3067/* Returns TRUE if the given tree has the "bank_switch" attribute. */
3068static int
3069bank_switch_p (tree node ATTRIBUTE_UNUSED)
3070{
3071 tree list = M32C_ATTRIBUTES (node);
3072 while (list)
3073 {
3074 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
3075 return 1;
3076 list = TREE_CHAIN (list);
3077 }
3078 return 0;
3079}
3080
3081/* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
3082static int
3083fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
3084{
3085 tree list = M32C_ATTRIBUTES (node);
3086 while (list)
3087 {
3088 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
3089 return 1;
3090 list = TREE_CHAIN (list);
3091 }
38b2d076
DD		 3092 return 0;
3093}
3094
3095static tree
3096interrupt_handler (tree * node ATTRIBUTE_UNUSED,
3097 tree name ATTRIBUTE_UNUSED,
3098 tree args ATTRIBUTE_UNUSED,
3099 int flags ATTRIBUTE_UNUSED,
3100 bool * no_add_attrs ATTRIBUTE_UNUSED)
3101{
3102 return NULL_TREE;
3103}
3104
5abd2125
JS		 3105/* Returns TRUE if given tree has the "function_vector" attribute. */
3106int
3107m32c_special_page_vector_p (tree func)
3108{
653e2568
DD		 3109 tree list;
3110
5abd2125
JS		 3111 if (TREE_CODE (func) != FUNCTION_DECL)
3112 return 0;
3113
653e2568 3114 list = M32C_ATTRIBUTES (func);
5abd2125
JS		 3115 while (list)
3116 {
3117 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
3118 return 1;
3119 list = TREE_CHAIN (list);
3120 }
3121 return 0;
3122}
3123
3124static tree
3125function_vector_handler (tree * node ATTRIBUTE_UNUSED,
3126 tree name ATTRIBUTE_UNUSED,
3127 tree args ATTRIBUTE_UNUSED,
3128 int flags ATTRIBUTE_UNUSED,
3129 bool * no_add_attrs ATTRIBUTE_UNUSED)
3130{
3131 if (TARGET_R8C)
3132 {
3133 /* The attribute is not supported for R8C target. */
3134 warning (OPT_Wattributes,
29d08eba
JM		 3135 "%qE attribute is not supported for R8C target",
3136 name);
5abd2125
JS		 3137 *no_add_attrs = true;
3138 }
3139 else if (TREE_CODE (*node) != FUNCTION_DECL)
3140 {
3141 /* The attribute must be applied to functions only. */
3142 warning (OPT_Wattributes,
29d08eba
JM		 3143 "%qE attribute applies only to functions",
3144 name);
5abd2125
JS		 3145 *no_add_attrs = true;
3146 }
3147 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
3148 {
3149 /* The argument must be a constant integer. */
3150 warning (OPT_Wattributes,
29d08eba
JM		 3151 "%qE attribute argument not an integer constant",
3152 name);
5abd2125
JS		 3153 *no_add_attrs = true;
3154 }
3155 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
3156 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
3157 {
3158 /* The argument value must be between 18 to 255. */
3159 warning (OPT_Wattributes,
29d08eba
JM		 3160 "%qE attribute argument should be between 18 to 255",
3161 name);
5abd2125
JS		 3162 *no_add_attrs = true;
3163 }
3164 return NULL_TREE;
3165}
3166
3167/* If the function is assigned the attribute 'function_vector', it
3168 returns the function vector number, otherwise returns zero. */
3169int
3170current_function_special_page_vector (rtx x)
3171{
3172 int num;
3173
3174 if ((GET_CODE(x) == SYMBOL_REF)
3175 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
3176 {
653e2568 3177 tree list;
5abd2125
JS		 3178 tree t = SYMBOL_REF_DECL (x);
3179
3180 if (TREE_CODE (t) != FUNCTION_DECL)
3181 return 0;
3182
653e2568 3183 list = M32C_ATTRIBUTES (t);
5abd2125
JS		 3184 while (list)
3185 {
3186 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
3187 {
3188 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
3189 return num;
3190 }
3191
3192 list = TREE_CHAIN (list);
3193 }
3194
3195 return 0;
3196 }
3197 else
3198 return 0;
3199}
3200
38b2d076
DD		 3201#undef TARGET_ATTRIBUTE_TABLE
3202#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
3203static const struct attribute_spec m32c_attribute_table[] = {
62d784f7
KT		 3204 {"interrupt", 0, 0, false, false, false, interrupt_handler, false},
3205 {"bank_switch", 0, 0, false, false, false, interrupt_handler, false},
3206 {"fast_interrupt", 0, 0, false, false, false, interrupt_handler, false},
3207 {"function_vector", 1, 1, true, false, false, function_vector_handler,
3208 false},
3209 {0, 0, 0, 0, 0, 0, 0, false}
38b2d076
DD		 3210};
3211
3212#undef TARGET_COMP_TYPE_ATTRIBUTES
3213#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
3214static int
3101faab
KG		 3215m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
3216 const_tree type2 ATTRIBUTE_UNUSED)
38b2d076
DD		 3217{
3218 /* 0=incompatible 1=compatible 2=warning */
3219 return 1;
3220}
3221
3222#undef TARGET_INSERT_ATTRIBUTES
3223#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
3224static void
3225m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
3226 tree * attr_ptr ATTRIBUTE_UNUSED)
3227{
f6052f86
DD		 3228 unsigned addr;
3229 /* See if we need to make #pragma address variables volatile. */
3230
3231 if (TREE_CODE (node) == VAR_DECL)
3232 {
444d6efe 3233 const char *name = IDENTIFIER_POINTER (DECL_NAME (node));
f6052f86
DD		 3234 if (m32c_get_pragma_address (name, &addr))
3235 {
3236 TREE_THIS_VOLATILE (node) = true;
3237 }
3238 }
3239}
3240
3241
3242struct GTY(()) pragma_entry {
3243 const char *varname;
3244 unsigned address;
3245};
3246typedef struct pragma_entry pragma_entry;
3247
3248/* Hash table of pragma info. */
3249static GTY((param_is (pragma_entry))) htab_t pragma_htab;
3250
3251static int
3252pragma_entry_eq (const void *p1, const void *p2)
3253{
3254 const pragma_entry *old = (const pragma_entry *) p1;
3255 const char *new_name = (const char *) p2;
3256
3257 return strcmp (old->varname, new_name) == 0;
3258}
3259
3260static hashval_t
3261pragma_entry_hash (const void *p)
3262{
3263 const pragma_entry *old = (const pragma_entry *) p;
3264 return htab_hash_string (old->varname);
3265}
3266
3267void
3268m32c_note_pragma_address (const char *varname, unsigned address)
3269{
3270 pragma_entry **slot;
3271
3272 if (!pragma_htab)
3273 pragma_htab = htab_create_ggc (31, pragma_entry_hash,
3274 pragma_entry_eq, NULL);
3275
3276 slot = (pragma_entry **)
3277 htab_find_slot_with_hash (pragma_htab, varname,
3278 htab_hash_string (varname), INSERT);
3279
3280 if (!*slot)
3281 {
3282 *slot = ggc_alloc_pragma_entry ();
3283 (*slot)->varname = ggc_strdup (varname);
3284 }
3285 (*slot)->address = address;
3286}
3287
3288static bool
3289m32c_get_pragma_address (const char *varname, unsigned *address)
3290{
3291 pragma_entry **slot;
3292
3293 if (!pragma_htab)
3294 return false;
3295
3296 slot = (pragma_entry **)
3297 htab_find_slot_with_hash (pragma_htab, varname,
3298 htab_hash_string (varname), NO_INSERT);
3299 if (slot && *slot)
3300 {
3301 *address = (*slot)->address;
3302 return true;
3303 }
3304 return false;
3305}
3306
3307void
444d6efe
JR		 3308m32c_output_aligned_common (FILE *stream, tree decl ATTRIBUTE_UNUSED,
3309 const char *name,
f6052f86
DD		 3310 int size, int align, int global)
3311{
3312 unsigned address;
3313
3314 if (m32c_get_pragma_address (name, &address))
3315 {
3316 /* We never output these as global. */
3317 assemble_name (stream, name);
3318 fprintf (stream, " = 0x%04x\n", address);
3319 return;
3320 }
3321 if (!global)
3322 {
3323 fprintf (stream, "\t.local\t");
3324 assemble_name (stream, name);
3325 fprintf (stream, "\n");
3326 }
3327 fprintf (stream, "\t.comm\t");
3328 assemble_name (stream, name);
3329 fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT);
38b2d076
DD		 3330}
3331
3332/* Predicates */
3333
f9b89438 3334/* This is a list of legal subregs of hard regs. */
67fc44cb
DD		 3335static const struct {
3336 unsigned char outer_mode_size;
3337 unsigned char inner_mode_size;
3338 unsigned char byte_mask;
3339 unsigned char legal_when;
f9b89438 3340 unsigned int regno;
f9b89438 3341} legal_subregs[] = {
67fc44cb
DD		 3342 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
3343 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
3344 {1, 2, 0x01, 1, A0_REGNO},
3345 {1, 2, 0x01, 1, A1_REGNO},
f9b89438 3346
67fc44cb
DD		 3347 {1, 4, 0x01, 1, A0_REGNO},
3348 {1, 4, 0x01, 1, A1_REGNO},
f9b89438 3349
67fc44cb
DD		 3350 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
3351 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
3352 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
3353 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
3354 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
f9b89438 3355
67fc44cb 3356 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
f9b89438
DD		 3357};
3358
3359/* Returns TRUE if OP is a subreg of a hard reg which we don't
f6052f86 3360 support. We also bail on MEMs with illegal addresses. */
f9b89438
DD		 3361bool
3362m32c_illegal_subreg_p (rtx op)
3363{
f9b89438
DD		 3364 int offset;
3365 unsigned int i;
3366 int src_mode, dest_mode;
3367
f6052f86
DD		 3368 if (GET_CODE (op) == MEM
3369 && ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))
3370 {
3371 return true;
3372 }
3373
f9b89438
DD		 3374 if (GET_CODE (op) != SUBREG)
3375 return false;
3376
3377 dest_mode = GET_MODE (op);
3378 offset = SUBREG_BYTE (op);
3379 op = SUBREG_REG (op);
3380 src_mode = GET_MODE (op);
3381
3382 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
3383 return false;
3384 if (GET_CODE (op) != REG)
3385 return false;
3386 if (REGNO (op) >= MEM0_REGNO)
3387 return false;
3388
3389 offset = (1 << offset);
3390
67fc44cb 3391 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
f9b89438
DD		 3392 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
3393 && legal_subregs[i].regno == REGNO (op)
3394 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
3395 && legal_subregs[i].byte_mask & offset)
3396 {
3397 switch (legal_subregs[i].legal_when)
3398 {
3399 case 1:
3400 return false;
3401 case 16:
3402 if (TARGET_A16)
3403 return false;
3404 break;
3405 case 24:
3406 if (TARGET_A24)
3407 return false;
3408 break;
3409 }
3410 }
3411 return true;
3412}
3413
38b2d076
DD		 3414/* Returns TRUE if we support a move between the first two operands.
3415 At the moment, we just want to discourage mem to mem moves until
3416 after reload, because reload has a hard time with our limited
3417 number of address registers, and we can get into a situation where
3418 we need three of them when we only have two. */
3419bool
3420m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
3421{
3422 rtx op0 = operands[0];
3423 rtx op1 = operands[1];
3424
3425 if (TARGET_A24)
3426 return true;
3427
3428#define DEBUG_MOV_OK 0
3429#if DEBUG_MOV_OK
3430 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
3431 debug_rtx (op0);
3432 debug_rtx (op1);
3433#endif
3434
3435 if (GET_CODE (op0) == SUBREG)
3436 op0 = XEXP (op0, 0);
3437 if (GET_CODE (op1) == SUBREG)
3438 op1 = XEXP (op1, 0);
3439
3440 if (GET_CODE (op0) == MEM
3441 && GET_CODE (op1) == MEM
3442 && ! reload_completed)
3443 {
3444#if DEBUG_MOV_OK
3445 fprintf (stderr, " - no, mem to mem\n");
3446#endif
3447 return false;
3448 }
3449
3450#if DEBUG_MOV_OK
3451 fprintf (stderr, " - ok\n");
3452#endif
3453 return true;
3454}
3455
ff485e71
DD		 3456/* Returns TRUE if two consecutive HImode mov instructions, generated
3457 for moving an immediate double data to a double data type variable
3458 location, can be combined into single SImode mov instruction. */
3459bool
3460m32c_immd_dbl_mov (rtx * operands,
3461 enum machine_mode mode ATTRIBUTE_UNUSED)
3462{
3463 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
3464 const char *str1;
3465 const char *str2;
3466
3467 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3468 && MEM_SCALAR_P (operands[0])
3469 && !MEM_IN_STRUCT_P (operands[0])
3470 && GET_CODE (XEXP (operands[2], 0)) == CONST
3471 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3472 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3473 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
3474 && MEM_SCALAR_P (operands[2])
3475 && !MEM_IN_STRUCT_P (operands[2]))
3476 flag = 1;
3477
3478 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
3479 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
3480 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
3481 && MEM_SCALAR_P (operands[0])
3482 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3483 && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
ff485e71
DD		 3484 && GET_CODE (XEXP (operands[2], 0)) == CONST
3485 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3486 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3487 && MEM_SCALAR_P (operands[2])
3488 && !MEM_IN_STRUCT_P (operands[2]))
3489 flag = 2;
3490
3491 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3492 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3493 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3494 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3495 && MEM_SCALAR_P (operands[0])
3496 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3497 && !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
ff485e71
DD		 3498 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3499 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3500 && MEM_SCALAR_P (operands[2])
3501 && !MEM_IN_STRUCT_P (operands[2]))
3502 flag = 3;
3503
3504 else
3505 return false;
3506
3507 switch (flag)
3508 {
3509 case 1:
3510 str1 = XSTR (XEXP (operands[0], 0), 0);
3511 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3512 if (strcmp (str1, str2) == 0)
3513 okflag = 1;
3514 else
3515 okflag = 0;
3516 break;
3517 case 2:
3518 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3519 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3520 if (strcmp(str1,str2) == 0)
3521 okflag = 1;
3522 else
3523 okflag = 0;
3524 break;
3525 case 3:
f9f3567e
DD		 3526 offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
3527 offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
ff485e71
DD		 3528 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3529 if (((offset2-offset1) == 2) && offsetsign != 0)
3530 okflag = 1;
3531 else
3532 okflag = 0;
3533 break;
3534 default:
3535 okflag = 0;
3536 }
3537
3538 if (okflag == 1)
3539 {
3540 HOST_WIDE_INT val;
3541 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3542
f9f3567e 3543 val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
ff485e71
DD		 3544 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3545
3546 return true;
3547 }
3548
3549 return false;
3550}
3551
38b2d076
DD		 3552/* Expanders */
3553
3554/* Subregs are non-orthogonal for us, because our registers are all
3555 different sizes. */
3556static rtx
3557m32c_subreg (enum machine_mode outer,
3558 rtx x, enum machine_mode inner, int byte)
3559{
3560 int r, nr = -1;
3561
3562 /* Converting MEMs to different types that are the same size, we
3563 just rewrite them. */
3564 if (GET_CODE (x) == SUBREG
3565 && SUBREG_BYTE (x) == 0
3566 && GET_CODE (SUBREG_REG (x)) == MEM
3567 && (GET_MODE_SIZE (GET_MODE (x))
3568 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3569 {
3570 rtx oldx = x;
3571 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3572 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3573 }
3574
3575 /* Push/pop get done as smaller push/pops. */
3576 if (GET_CODE (x) == MEM
3577 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3578 || GET_CODE (XEXP (x, 0)) == POST_INC))
3579 return gen_rtx_MEM (outer, XEXP (x, 0));
3580 if (GET_CODE (x) == SUBREG
3581 && GET_CODE (XEXP (x, 0)) == MEM
3582 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3583 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3584 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3585
3586 if (GET_CODE (x) != REG)
146456c1
DD		 3587 {
3588 rtx r = simplify_gen_subreg (outer, x, inner, byte);
3589 if (GET_CODE (r) == SUBREG
3590 && GET_CODE (x) == MEM
3591 && MEM_VOLATILE_P (x))
3592 {
3593 /* Volatile MEMs don't get simplified, but we need them to
3594 be. We are little endian, so the subreg byte is the
3595 offset. */
91140cd3 3596 r = adjust_address_nv (x, outer, byte);
146456c1
DD		 3597 }
3598 return r;
3599 }
38b2d076
DD		 3600
3601 r = REGNO (x);
3602 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3603 return simplify_gen_subreg (outer, x, inner, byte);
3604
3605 if (IS_MEM_REGNO (r))
3606 return simplify_gen_subreg (outer, x, inner, byte);
3607
3608 /* This is where the complexities of our register layout are
3609 described. */
3610 if (byte == 0)
3611 nr = r;
3612 else if (outer == HImode)
3613 {
3614 if (r == R0_REGNO && byte == 2)
3615 nr = R2_REGNO;
3616 else if (r == R0_REGNO && byte == 4)
3617 nr = R1_REGNO;
3618 else if (r == R0_REGNO && byte == 6)
3619 nr = R3_REGNO;
3620 else if (r == R1_REGNO && byte == 2)
3621 nr = R3_REGNO;
3622 else if (r == A0_REGNO && byte == 2)
3623 nr = A1_REGNO;
3624 }
3625 else if (outer == SImode)
3626 {
3627 if (r == R0_REGNO && byte == 0)
3628 nr = R0_REGNO;
3629 else if (r == R0_REGNO && byte == 4)
3630 nr = R1_REGNO;
3631 }
3632 if (nr == -1)
3633 {
3634 fprintf (stderr, "m32c_subreg %s %s %d\n",
3635 mode_name[outer], mode_name[inner], byte);
3636 debug_rtx (x);
3637 gcc_unreachable ();
3638 }
3639 return gen_rtx_REG (outer, nr);
3640}
3641
3642/* Used to emit move instructions. We split some moves,
3643 and avoid mem-mem moves. */
3644int
3645m32c_prepare_move (rtx * operands, enum machine_mode mode)
3646{
5fd5d713
DD		 3647 if (far_addr_space_p (operands[0])
3648 && CONSTANT_P (operands[1]))
3649 {
3650 operands[1] = force_reg (GET_MODE (operands[0]), operands[1]);
3651 }
38b2d076
DD		 3652 if (TARGET_A16 && mode == PSImode)
3653 return m32c_split_move (operands, mode, 1);
3654 if ((GET_CODE (operands[0]) == MEM)
3655 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3656 {
3657 rtx pmv = XEXP (operands[0], 0);
3658 rtx dest_reg = XEXP (pmv, 0);
3659 rtx dest_mod = XEXP (pmv, 1);
3660
3661 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3662 operands[0] = gen_rtx_MEM (mode, dest_reg);
3663 }
b3a13419 3664 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3665 operands[1] = copy_to_mode_reg (mode, operands[1]);
3666 return 0;
3667}
3668
3669#define DEBUG_SPLIT 0
3670
3671/* Returns TRUE if the given PSImode move should be split. We split
3672 for all r8c/m16c moves, since it doesn't support them, and for
3673 POP.L as we can only *push* SImode. */
3674int
3675m32c_split_psi_p (rtx * operands)
3676{
3677#if DEBUG_SPLIT
3678 fprintf (stderr, "\nm32c_split_psi_p\n");
3679 debug_rtx (operands[0]);
3680 debug_rtx (operands[1]);
3681#endif
3682 if (TARGET_A16)
3683 {
3684#if DEBUG_SPLIT
3685 fprintf (stderr, "yes, A16\n");
3686#endif
3687 return 1;
3688 }
3689 if (GET_CODE (operands[1]) == MEM
3690 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3691 {
3692#if DEBUG_SPLIT
3693 fprintf (stderr, "yes, pop.l\n");
3694#endif
3695 return 1;
3696 }
3697#if DEBUG_SPLIT
3698 fprintf (stderr, "no, default\n");
3699#endif
3700 return 0;
3701}
3702
3703/* Split the given move. SPLIT_ALL is 0 if splitting is optional
3704 (define_expand), 1 if it is not optional (define_insn_and_split),
3705 and 3 for define_split (alternate api). */
3706int
3707m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3708{
3709 rtx s[4], d[4];
3710 int parts, si, di, rev = 0;
3711 int rv = 0, opi = 2;
3712 enum machine_mode submode = HImode;
3713 rtx *ops, local_ops[10];
3714
3715 /* define_split modifies the existing operands, but the other two
3716 emit new insns. OPS is where we store the operand pairs, which
3717 we emit later. */
3718 if (split_all == 3)
3719 ops = operands;
3720 else
3721 ops = local_ops;
3722
3723 /* Else HImode. */
3724 if (mode == DImode)
3725 submode = SImode;
3726
3727 /* Before splitting mem-mem moves, force one operand into a
3728 register. */
b3a13419 3729 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3730 {
3731#if DEBUG0
3732 fprintf (stderr, "force_reg...\n");
3733 debug_rtx (operands[1]);
3734#endif
3735 operands[1] = force_reg (mode, operands[1]);
3736#if DEBUG0
3737 debug_rtx (operands[1]);
3738#endif
3739 }
3740
3741 parts = 2;
3742
3743#if DEBUG_SPLIT
b3a13419
ILT		 3744 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3745 split_all);
38b2d076
DD		 3746 debug_rtx (operands[0]);
3747 debug_rtx (operands[1]);
3748#endif
3749
eb5f0c07
DD		 3750 /* Note that split_all is not used to select the api after this
3751 point, so it's safe to set it to 3 even with define_insn. */
3752 /* None of the chips can move SI operands to sp-relative addresses,
3753 so we always split those. */
3754 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3755 split_all = 3;
3756
5fd5d713
DD		 3757 if (TARGET_A16
3758 && (far_addr_space_p (operands[0])
3759 || far_addr_space_p (operands[1])))
3760 split_all |= 1;
3761
38b2d076
DD		 3762 /* We don't need to split these. */
3763 if (TARGET_A24
3764 && split_all != 3
3765 && (mode == SImode || mode == PSImode)
3766 && !(GET_CODE (operands[1]) == MEM
3767 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3768 return 0;
3769
3770 /* First, enumerate the subregs we'll be dealing with. */
3771 for (si = 0; si < parts; si++)
3772 {
3773 d[si] =
3774 m32c_subreg (submode, operands[0], mode,
3775 si * GET_MODE_SIZE (submode));
3776 s[si] =
3777 m32c_subreg (submode, operands[1], mode,
3778 si * GET_MODE_SIZE (submode));
3779 }
3780
3781 /* Split pushes by emitting a sequence of smaller pushes. */
3782 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3783 {
3784 for (si = parts - 1; si >= 0; si--)
3785 {
3786 ops[opi++] = gen_rtx_MEM (submode,
3787 gen_rtx_PRE_DEC (Pmode,
3788 gen_rtx_REG (Pmode,
3789 SP_REGNO)));
3790 ops[opi++] = s[si];
3791 }
3792
3793 rv = 1;
3794 }
3795 /* Likewise for pops. */
3796 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3797 {
3798 for (di = 0; di < parts; di++)
3799 {
3800 ops[opi++] = d[di];
3801 ops[opi++] = gen_rtx_MEM (submode,
3802 gen_rtx_POST_INC (Pmode,
3803 gen_rtx_REG (Pmode,
3804 SP_REGNO)));
3805 }
3806 rv = 1;
3807 }
3808 else if (split_all)
3809 {
3810 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3811 for (di = 0; di < parts - 1; di++)
3812 for (si = di + 1; si < parts; si++)
3813 if (reg_mentioned_p (d[di], s[si]))
3814 rev = 1;
3815
3816 if (rev)
3817 for (si = 0; si < parts; si++)
3818 {
3819 ops[opi++] = d[si];
3820 ops[opi++] = s[si];
3821 }
3822 else
3823 for (si = parts - 1; si >= 0; si--)
3824 {
3825 ops[opi++] = d[si];
3826 ops[opi++] = s[si];
3827 }
3828 rv = 1;
3829 }
3830 /* Now emit any moves we may have accumulated. */
3831 if (rv && split_all != 3)
3832 {
3833 int i;
3834 for (i = 2; i < opi; i += 2)
3835 emit_move_insn (ops[i], ops[i + 1]);
3836 }
3837 return rv;
3838}
3839
07127a0a
DD		 3840/* The m32c has a number of opcodes that act like memcpy, strcmp, and
3841 the like. For the R8C they expect one of the addresses to be in
3842 R1L:An so we need to arrange for that. Otherwise, it's just a
3843 matter of picking out the operands we want and emitting the right
3844 pattern for them. All these expanders, which correspond to
3845 patterns in blkmov.md, must return nonzero if they expand the insn,
3846 or zero if they should FAIL. */
3847
3848/* This is a memset() opcode. All operands are implied, so we need to
3849 arrange for them to be in the right registers. The opcode wants
3850 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3851 the count (HI), and $2 the value (QI). */
3852int
3853m32c_expand_setmemhi(rtx *operands)
3854{
3855 rtx desta, count, val;
3856 rtx desto, counto;
3857
3858 desta = XEXP (operands[0], 0);
3859 count = operands[1];
3860 val = operands[2];
3861
3862 desto = gen_reg_rtx (Pmode);
3863 counto = gen_reg_rtx (HImode);
3864
3865 if (GET_CODE (desta) != REG
3866 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3867 desta = copy_to_mode_reg (Pmode, desta);
3868
3869 /* This looks like an arbitrary restriction, but this is by far the
3870 most common case. For counts 8..14 this actually results in
3871 smaller code with no speed penalty because the half-sized
3872 constant can be loaded with a shorter opcode. */
3873 if (GET_CODE (count) == CONST_INT
3874 && GET_CODE (val) == CONST_INT
3875 && ! (INTVAL (count) & 1)
3876 && (INTVAL (count) > 1)
3877 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3878 {
3879 unsigned v = INTVAL (val) & 0xff;
3880 v = v | (v << 8);
3881 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3882 val = copy_to_mode_reg (HImode, GEN_INT (v));
3883 if (TARGET_A16)
3884 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3885 else
3886 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3887 return 1;
3888 }
3889
3890 /* This is the generalized memset() case. */
3891 if (GET_CODE (val) != REG
3892 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3893 val = copy_to_mode_reg (QImode, val);
3894
3895 if (GET_CODE (count) != REG
3896 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3897 count = copy_to_mode_reg (HImode, count);
3898
3899 if (TARGET_A16)
3900 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3901 else
3902 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3903
3904 return 1;
3905}
3906
3907/* This is a memcpy() opcode. All operands are implied, so we need to
3908 arrange for them to be in the right registers. The opcode wants
3909 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3910 is the source (MEM:BLK), and $2 the count (HI). */
3911int
3912m32c_expand_movmemhi(rtx *operands)
3913{
3914 rtx desta, srca, count;
3915 rtx desto, srco, counto;
3916
3917 desta = XEXP (operands[0], 0);
3918 srca = XEXP (operands[1], 0);
3919 count = operands[2];
3920
3921 desto = gen_reg_rtx (Pmode);
3922 srco = gen_reg_rtx (Pmode);
3923 counto = gen_reg_rtx (HImode);
3924
3925 if (GET_CODE (desta) != REG
3926 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3927 desta = copy_to_mode_reg (Pmode, desta);
3928
3929 if (GET_CODE (srca) != REG
3930 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3931 srca = copy_to_mode_reg (Pmode, srca);
3932
3933 /* Similar to setmem, but we don't need to check the value. */
3934 if (GET_CODE (count) == CONST_INT
3935 && ! (INTVAL (count) & 1)
3936 && (INTVAL (count) > 1))
3937 {
3938 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3939 if (TARGET_A16)
3940 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3941 else
3942 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3943 return 1;
3944 }
3945
3946 /* This is the generalized memset() case. */
3947 if (GET_CODE (count) != REG
3948 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3949 count = copy_to_mode_reg (HImode, count);
3950
3951 if (TARGET_A16)
3952 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3953 else
3954 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3955
3956 return 1;
3957}
3958
3959/* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3960 the copy, which should point to the NUL at the end of the string,
3961 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3962 Since our opcode leaves the destination pointing *after* the NUL,
3963 we must emit an adjustment. */
3964int
3965m32c_expand_movstr(rtx *operands)
3966{
3967 rtx desta, srca;
3968 rtx desto, srco;
3969
3970 desta = XEXP (operands[1], 0);
3971 srca = XEXP (operands[2], 0);
3972
3973 desto = gen_reg_rtx (Pmode);
3974 srco = gen_reg_rtx (Pmode);
3975
3976 if (GET_CODE (desta) != REG
3977 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3978 desta = copy_to_mode_reg (Pmode, desta);
3979
3980 if (GET_CODE (srca) != REG
3981 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3982 srca = copy_to_mode_reg (Pmode, srca);
3983
3984 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3985 /* desto ends up being a1, which allows this type of add through MOVA. */
3986 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3987
3988 return 1;
3989}
3990
3991/* This is a strcmp() opcode. $0 is the destination (HI) which holds
3992 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3993 $2 is the other (MEM:BLK). We must do the comparison, and then
3994 convert the flags to a signed integer result. */
3995int
3996m32c_expand_cmpstr(rtx *operands)
3997{
3998 rtx src1a, src2a;
3999
4000 src1a = XEXP (operands[1], 0);
4001 src2a = XEXP (operands[2], 0);
4002
4003 if (GET_CODE (src1a) != REG
4004 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
4005 src1a = copy_to_mode_reg (Pmode, src1a);
4006
4007 if (GET_CODE (src2a) != REG
4008 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
4009 src2a = copy_to_mode_reg (Pmode, src2a);
4010
4011 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
4012 emit_insn (gen_cond_to_int (operands[0]));
4013
4014 return 1;
4015}
4016
4017
23fed240
DD		 4018typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
4019
4020static shift_gen_func
4021shift_gen_func_for (int mode, int code)
4022{
4023#define GFF(m,c,f) if (mode == m && code == c) return f
4024 GFF(QImode, ASHIFT, gen_ashlqi3_i);
4025 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
4026 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
4027 GFF(HImode, ASHIFT, gen_ashlhi3_i);
4028 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
4029 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
4030 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
4031 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
4032 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
4033 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
4034 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
4035 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
4036#undef GFF
07127a0a 4037 gcc_unreachable ();
23fed240
DD		 4038}
4039
38b2d076
DD		 4040/* The m32c only has one shift, but it takes a signed count. GCC
4041 doesn't want this, so we fake it by negating any shift count when
07127a0a
DD		 4042 we're pretending to shift the other way. Also, the shift count is
4043 limited to -8..8. It's slightly better to use two shifts for 9..15
4044 than to load the count into r1h, so we do that too. */
38b2d076 4045int
23fed240 4046m32c_prepare_shift (rtx * operands, int scale, int shift_code)
38b2d076 4047{
23fed240
DD		 4048 enum machine_mode mode = GET_MODE (operands[0]);
4049 shift_gen_func func = shift_gen_func_for (mode, shift_code);
38b2d076 4050 rtx temp;
23fed240
DD		 4051
4052 if (GET_CODE (operands[2]) == CONST_INT)
38b2d076 4053 {
23fed240
DD		 4054 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
4055 int count = INTVAL (operands[2]) * scale;
4056
4057 while (count > maxc)
4058 {
4059 temp = gen_reg_rtx (mode);
4060 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
4061 operands[1] = temp;
4062 count -= maxc;
4063 }
4064 while (count < -maxc)
4065 {
4066 temp = gen_reg_rtx (mode);
4067 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
4068 operands[1] = temp;
4069 count += maxc;
4070 }
4071 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
4072 return 1;
38b2d076 4073 }
2e160056
DD		 4074
4075 temp = gen_reg_rtx (QImode);
38b2d076 4076 if (scale < 0)
2e160056
DD		 4077 /* The pattern has a NEG that corresponds to this. */
4078 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
4079 else if (TARGET_A16 && mode == SImode)
4080 /* We do this because the code below may modify this, we don't
4081 want to modify the origin of this value. */
4082 emit_move_insn (temp, operands[2]);
38b2d076 4083 else
2e160056 4084 /* We'll only use it for the shift, no point emitting a move. */
38b2d076 4085 temp = operands[2];
2e160056 4086
16659fcf 4087 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
2e160056
DD		 4088 {
4089 /* The m16c has a limit of -16..16 for SI shifts, even when the
4090 shift count is in a register. Since there are so many targets
4091 of these shifts, it's better to expand the RTL here than to
4092 call a helper function.
4093
4094 The resulting code looks something like this:
4095
4096 cmp.b r1h,-16
4097 jge.b 1f
4098 shl.l -16,dest
4099 add.b r1h,16
4100 1f: cmp.b r1h,16
4101 jle.b 1f
4102 shl.l 16,dest
4103 sub.b r1h,16
4104 1f: shl.l r1h,dest
4105
4106 We take advantage of the fact that "negative" shifts are
4107 undefined to skip one of the comparisons. */
4108
4109 rtx count;
444d6efe 4110 rtx label, insn, tempvar;
2e160056 4111
16659fcf
DD		 4112 emit_move_insn (operands[0], operands[1]);
4113
2e160056
DD		 4114 count = temp;
4115 label = gen_label_rtx ();
2e160056
DD		 4116 LABEL_NUSES (label) ++;
4117
833bf445
DD		 4118 tempvar = gen_reg_rtx (mode);
4119
2e160056
DD		 4120 if (shift_code == ASHIFT)
4121 {
4122 /* This is a left shift. We only need check positive counts. */
4123 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
4124 count, GEN_INT (16), label));
833bf445
DD		 4125 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
4126 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
2e160056
DD		 4127 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
4128 emit_label_after (label, insn);
4129 }
4130 else
4131 {
4132 /* This is a right shift. We only need check negative counts. */
4133 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
4134 count, GEN_INT (-16), label));
833bf445
DD		 4135 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
4136 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
2e160056
DD		 4137 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
4138 emit_label_after (label, insn);
4139 }
16659fcf
DD		 4140 operands[1] = operands[0];
4141 emit_insn (func (operands[0], operands[0], count));
4142 return 1;
2e160056
DD		 4143 }
4144
38b2d076
DD		 4145 operands[2] = temp;
4146 return 0;
4147}
4148
12ea2512
DD		 4149/* The m32c has a limited range of operations that work on PSImode
4150 values; we have to expand to SI, do the math, and truncate back to
4151 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
4152 those cases. */
4153void
4154m32c_expand_neg_mulpsi3 (rtx * operands)
4155{
4156 /* operands: a = b * i */
4157 rtx temp1; /* b as SI */
07127a0a
DD		 4158 rtx scale /* i as SI */;
4159 rtx temp2; /* a*b as SI */
12ea2512
DD		 4160
4161 temp1 = gen_reg_rtx (SImode);
4162 temp2 = gen_reg_rtx (SImode);
07127a0a
DD		 4163 if (GET_CODE (operands[2]) != CONST_INT)
4164 {
4165 scale = gen_reg_rtx (SImode);
4166 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
4167 }
4168 else
4169 scale = copy_to_mode_reg (SImode, operands[2]);
12ea2512
DD		 4170
4171 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
07127a0a
DD		 4172 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
4173 emit_insn (gen_truncsipsi2 (operands[0], temp2));
12ea2512
DD		 4174}
4175
38b2d076
DD		 4176/* Pattern Output Functions */
4177
07127a0a
DD		 4178int
4179m32c_expand_movcc (rtx *operands)
4180{
4181 rtx rel = operands[1];
0166ff05 4182
07127a0a
DD		 4183 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
4184 return 1;
4185 if (GET_CODE (operands[2]) != CONST_INT
4186 || GET_CODE (operands[3]) != CONST_INT)
4187 return 1;
07127a0a
DD		 4188 if (GET_CODE (rel) == NE)
4189 {
4190 rtx tmp = operands[2];
4191 operands[2] = operands[3];
4192 operands[3] = tmp;
f90b7a5a 4193 rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
07127a0a 4194 }
0166ff05 4195
0166ff05
DD		 4196 emit_move_insn (operands[0],
4197 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
f90b7a5a 4198 rel,
0166ff05
DD		 4199 operands[2],
4200 operands[3]));
07127a0a
DD		 4201 return 0;
4202}
4203
4204/* Used for the "insv" pattern. Return nonzero to fail, else done. */
4205int
4206m32c_expand_insv (rtx *operands)
4207{
4208 rtx op0, src0, p;
4209 int mask;
4210
4211 if (INTVAL (operands[1]) != 1)
4212 return 1;
4213
9cb96754
N		 4214 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
4215 if (GET_CODE (operands[3]) != CONST_INT)
4216 return 1;
4217 if (INTVAL (operands[3]) != 0
4218 && INTVAL (operands[3]) != 1
4219 && INTVAL (operands[3]) != -1)
4220 return 1;
4221
07127a0a
DD		 4222 mask = 1 << INTVAL (operands[2]);
4223
4224 op0 = operands[0];
4225 if (GET_CODE (op0) == SUBREG
4226 && SUBREG_BYTE (op0) == 0)
4227 {
4228 rtx sub = SUBREG_REG (op0);
4229 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
4230 op0 = sub;
4231 }
4232
b3a13419 4233 if (!can_create_pseudo_p ()
07127a0a
DD		 4234 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
4235 src0 = op0;
4236 else
4237 {
4238 src0 = gen_reg_rtx (GET_MODE (op0));
4239 emit_move_insn (src0, op0);
4240 }
4241
4242 if (GET_MODE (op0) == HImode
4243 && INTVAL (operands[2]) >= 8
444d6efe 4244 && GET_CODE (op0) == MEM)
07127a0a
DD		 4245 {
4246 /* We are little endian. */
4247 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
4248 MEM_COPY_ATTRIBUTES (new_mem, op0);
4249 mask >>= 8;
4250 }
4251
8e4edce7
DD		 4252 /* First, we generate a mask with the correct polarity. If we are
4253 storing a zero, we want an AND mask, so invert it. */
4254 if (INTVAL (operands[3]) == 0)
07127a0a 4255 {
16659fcf 4256 /* Storing a zero, use an AND mask */
07127a0a
DD		 4257 if (GET_MODE (op0) == HImode)
4258 mask ^= 0xffff;
4259 else
4260 mask ^= 0xff;
4261 }
8e4edce7
DD		 4262 /* Now we need to properly sign-extend the mask in case we need to
4263 fall back to an AND or OR opcode. */
07127a0a
DD		 4264 if (GET_MODE (op0) == HImode)
4265 {
4266 if (mask & 0x8000)
4267 mask -= 0x10000;
4268 }
4269 else
4270 {
4271 if (mask & 0x80)
4272 mask -= 0x100;
4273 }
4274
4275 switch ( (INTVAL (operands[3]) ? 4 : 0)
4276 + ((GET_MODE (op0) == HImode) ? 2 : 0)
4277 + (TARGET_A24 ? 1 : 0))
4278 {
4279 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
4280 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
4281 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
4282 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
4283 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
4284 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
4285 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
4286 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
653e2568 4287 default: p = NULL_RTX; break; /* Not reached, but silences a warning. */
07127a0a
DD		 4288 }
4289
4290 emit_insn (p);
4291 return 0;
4292}
4293
4294const char *
4295m32c_scc_pattern(rtx *operands, RTX_CODE code)
4296{
4297 static char buf[30];
4298 if (GET_CODE (operands[0]) == REG
4299 && REGNO (operands[0]) == R0_REGNO)
4300 {
4301 if (code == EQ)
4302 return "stzx\t#1,#0,r0l";
4303 if (code == NE)
4304 return "stzx\t#0,#1,r0l";
4305 }
4306 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
4307 return buf;
4308}
4309
5abd2125
JS		 4310/* Encode symbol attributes of a SYMBOL_REF into its
4311 SYMBOL_REF_FLAGS. */
4312static void
4313m32c_encode_section_info (tree decl, rtx rtl, int first)
4314{
4315 int extra_flags = 0;
4316
4317 default_encode_section_info (decl, rtl, first);
4318 if (TREE_CODE (decl) == FUNCTION_DECL
4319 && m32c_special_page_vector_p (decl))
4320
4321 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4322
4323 if (extra_flags)
4324 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4325}
4326
38b2d076
DD		 4327/* Returns TRUE if the current function is a leaf, and thus we can
4328 determine which registers an interrupt function really needs to
4329 save. The logic below is mostly about finding the insn sequence
4330 that's the function, versus any sequence that might be open for the
4331 current insn. */
4332static int
4333m32c_leaf_function_p (void)
4334{
4335 rtx saved_first, saved_last;
4336 struct sequence_stack *seq;
4337 int rv;
4338
3e029763
JH		 4339 saved_first = crtl->emit.x_first_insn;
4340 saved_last = crtl->emit.x_last_insn;
4341 for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
38b2d076
DD		 4342 ;
4343 if (seq)
4344 {
3e029763
JH		 4345 crtl->emit.x_first_insn = seq->first;
4346 crtl->emit.x_last_insn = seq->last;
38b2d076
DD		 4347 }
4348
4349 rv = leaf_function_p ();
4350
3e029763
JH		 4351 crtl->emit.x_first_insn = saved_first;
4352 crtl->emit.x_last_insn = saved_last;
38b2d076
DD		 4353 return rv;
4354}
4355
4356/* Returns TRUE if the current function needs to use the ENTER/EXIT
4357 opcodes. If the function doesn't need the frame base or stack
4358 pointer, it can use the simpler RTS opcode. */
4359static bool
4360m32c_function_needs_enter (void)
4361{
4362 rtx insn;
4363 struct sequence_stack *seq;
4364 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
4365 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
4366
4367 insn = get_insns ();
3e029763 4368 for (seq = crtl->emit.sequence_stack;
38b2d076
DD		 4369 seq;
4370 insn = seq->first, seq = seq->next);
4371
4372 while (insn)
4373 {
4374 if (reg_mentioned_p (sp, insn))
4375 return true;
4376 if (reg_mentioned_p (fb, insn))
4377 return true;
4378 insn = NEXT_INSN (insn);
4379 }
4380 return false;
4381}
4382
4383/* Mark all the subexpressions of the PARALLEL rtx PAR as
4384 frame-related. Return PAR.
4385
4386 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
4387 PARALLEL rtx other than the first if they do not have the
4388 FRAME_RELATED flag set on them. So this function is handy for
4389 marking up 'enter' instructions. */
4390static rtx
4391m32c_all_frame_related (rtx par)
4392{
4393 int len = XVECLEN (par, 0);
4394 int i;
4395
4396 for (i = 0; i < len; i++)
4397 F (XVECEXP (par, 0, i));
4398
4399 return par;
4400}
4401
4402/* Emits the prologue. See the frame layout comment earlier in this
4403 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
4404 that we manually update sp. */
4405void
4406m32c_emit_prologue (void)
4407{
4408 int frame_size, extra_frame_size = 0, reg_save_size;
4409 int complex_prologue = 0;
4410
4411 cfun->machine->is_leaf = m32c_leaf_function_p ();
4412 if (interrupt_p (cfun->decl))
4413 {
4414 cfun->machine->is_interrupt = 1;
4415 complex_prologue = 1;
4416 }
65655f79
DD		 4417 else if (bank_switch_p (cfun->decl))
4418 warning (OPT_Wattributes,
4419 "%<bank_switch%> has no effect on non-interrupt functions");
38b2d076
DD		 4420
4421 reg_save_size = m32c_pushm_popm (PP_justcount);
4422
4423 if (interrupt_p (cfun->decl))
65655f79
DD		 4424 {
4425 if (bank_switch_p (cfun->decl))
4426 emit_insn (gen_fset_b ());
4427 else if (cfun->machine->intr_pushm)
4428 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
4429 }
38b2d076
DD		 4430
4431 frame_size =
4432 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
4433 if (frame_size == 0
38b2d076
DD		 4434 && !m32c_function_needs_enter ())
4435 cfun->machine->use_rts = 1;
4436
4437 if (frame_size > 254)
4438 {
4439 extra_frame_size = frame_size - 254;
4440 frame_size = 254;
4441 }
4442 if (cfun->machine->use_rts == 0)
4443 F (emit_insn (m32c_all_frame_related
4444 (TARGET_A16
fa9fd28a
RIL		 4445 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
4446 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
38b2d076
DD		 4447
4448 if (extra_frame_size)
4449 {
4450 complex_prologue = 1;
4451 if (TARGET_A16)
4452 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
4453 gen_rtx_REG (HImode, SP_REGNO),
4454 GEN_INT (-extra_frame_size))));
4455 else
4456 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
4457 gen_rtx_REG (PSImode, SP_REGNO),
4458 GEN_INT (-extra_frame_size))));
4459 }
4460
4461 complex_prologue += m32c_pushm_popm (PP_pushm);
4462
4463 /* This just emits a comment into the .s file for debugging. */
4464 if (complex_prologue)
4465 emit_insn (gen_prologue_end ());
4466}
4467
4468/* Likewise, for the epilogue. The only exception is that, for
4469 interrupts, we must manually unwind the frame as the REIT opcode
4470 doesn't do that. */
4471void
4472m32c_emit_epilogue (void)
4473{
f0679612
DD		 4474 int popm_count = m32c_pushm_popm (PP_justcount);
4475
38b2d076 4476 /* This just emits a comment into the .s file for debugging. */
f0679612 4477 if (popm_count > 0 || cfun->machine->is_interrupt)
38b2d076
DD		 4478 emit_insn (gen_epilogue_start ());
4479
f0679612
DD		 4480 if (popm_count > 0)
4481 m32c_pushm_popm (PP_popm);
38b2d076
DD		 4482
4483 if (cfun->machine->is_interrupt)
4484 {
4485 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4486
65655f79
DD		 4487 /* REIT clears B flag and restores $fp for us, but we still
4488 have to fix up the stack. USE_RTS just means we didn't
4489 emit ENTER. */
4490 if (!cfun->machine->use_rts)
4491 {
4492 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4493 gen_rtx_REG (spmode, FP_REGNO));
4494 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4495 gen_rtx_REG (spmode, A0_REGNO));
4496 /* We can't just add this to the POPM because it would be in
4497 the wrong order, and wouldn't fix the stack if we're bank
4498 switching. */
4499 if (TARGET_A16)
4500 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4501 else
4502 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4503 }
4504 if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
4505 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4506
402f2db8
DD		 4507 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4508 generated only for M32C/M32CM targets (generate the REIT
4509 instruction otherwise). */
65655f79 4510 if (fast_interrupt_p (cfun->decl))
402f2db8
DD		 4511 {
4512 /* Check if fast_attribute is set for M32C or M32CM. */
4513 if (TARGET_A24)
4514 {
4515 emit_jump_insn (gen_epilogue_freit ());
4516 }
4517 /* If fast_interrupt attribute is set for an R8C or M16C
4518 target ignore this attribute and generated REIT
4519 instruction. */
4520 else
4521 {
4522 warning (OPT_Wattributes,
4523 "%<fast_interrupt%> attribute directive ignored");
4524 emit_jump_insn (gen_epilogue_reit_16 ());
4525 }
4526 }
65655f79 4527 else if (TARGET_A16)
0e0642aa
RIL		 4528 emit_jump_insn (gen_epilogue_reit_16 ());
4529 else
4530 emit_jump_insn (gen_epilogue_reit_24 ());
38b2d076
DD		 4531 }
4532 else if (cfun->machine->use_rts)
4533 emit_jump_insn (gen_epilogue_rts ());
0e0642aa
RIL		 4534 else if (TARGET_A16)
4535 emit_jump_insn (gen_epilogue_exitd_16 ());
38b2d076 4536 else
0e0642aa 4537 emit_jump_insn (gen_epilogue_exitd_24 ());
38b2d076
DD		 4538}
4539
4540void
4541m32c_emit_eh_epilogue (rtx ret_addr)
4542{
4543 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4544 return to. We have to fudge the stack, pop everything, pop SP
4545 (fudged), and return (fudged). This is actually easier to do in
4546 assembler, so punt to libgcc. */
4547 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
c41c1387 4548 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
38b2d076
DD		 4549}
4550
16659fcf
DD		 4551/* Indicate which flags must be properly set for a given conditional. */
4552static int
4553flags_needed_for_conditional (rtx cond)
4554{
4555 switch (GET_CODE (cond))
4556 {
4557 case LE:
4558 case GT:
4559 return FLAGS_OSZ;
4560 case LEU:
4561 case GTU:
4562 return FLAGS_ZC;
4563 case LT:
4564 case GE:
4565 return FLAGS_OS;
4566 case LTU:
4567 case GEU:
4568 return FLAGS_C;
4569 case EQ:
4570 case NE:
4571 return FLAGS_Z;
4572 default:
4573 return FLAGS_N;
4574 }
4575}
4576
4577#define DEBUG_CMP 0
4578
4579/* Returns true if a compare insn is redundant because it would only
4580 set flags that are already set correctly. */
4581static bool
4582m32c_compare_redundant (rtx cmp, rtx *operands)
4583{
4584 int flags_needed;
4585 int pflags;
4586 rtx prev, pp, next;
444d6efe 4587 rtx op0, op1;
16659fcf
DD		 4588#if DEBUG_CMP
4589 int prev_icode, i;
4590#endif
4591
4592 op0 = operands[0];
4593 op1 = operands[1];
16659fcf
DD		 4594
4595#if DEBUG_CMP
4596 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4597 debug_rtx(cmp);
4598 for (i=0; i<2; i++)
4599 {
4600 fprintf(stderr, "operands[%d] = ", i);
4601 debug_rtx(operands[i]);
4602 }
4603#endif
4604
4605 next = next_nonnote_insn (cmp);
4606 if (!next || !INSN_P (next))
4607 {
4608#if DEBUG_CMP
4609 fprintf(stderr, "compare not followed by insn\n");
4610 debug_rtx(next);
4611#endif
4612 return false;
4613 }
4614 if (GET_CODE (PATTERN (next)) == SET
4615 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4616 {
4617 next = XEXP (XEXP (PATTERN (next), 1), 0);
4618 }
4619 else if (GET_CODE (PATTERN (next)) == SET)
4620 {
4621 /* If this is a conditional, flags_needed will be something
4622 other than FLAGS_N, which we test below. */
4623 next = XEXP (PATTERN (next), 1);
4624 }
4625 else
4626 {
4627#if DEBUG_CMP
4628 fprintf(stderr, "compare not followed by conditional\n");
4629 debug_rtx(next);
4630#endif
4631 return false;
4632 }
4633#if DEBUG_CMP
4634 fprintf(stderr, "conditional is: ");
4635 debug_rtx(next);
4636#endif
4637
4638 flags_needed = flags_needed_for_conditional (next);
4639 if (flags_needed == FLAGS_N)
4640 {
4641#if DEBUG_CMP
4642 fprintf(stderr, "compare not followed by conditional\n");
4643 debug_rtx(next);
4644#endif
4645 return false;
4646 }
4647
4648 /* Compare doesn't set overflow and carry the same way that
4649 arithmetic instructions do, so we can't replace those. */
4650 if (flags_needed & FLAGS_OC)
4651 return false;
4652
4653 prev = cmp;
4654 do {
4655 prev = prev_nonnote_insn (prev);
4656 if (!prev)
4657 {
4658#if DEBUG_CMP
4659 fprintf(stderr, "No previous insn.\n");
4660#endif
4661 return false;
4662 }
4663 if (!INSN_P (prev))
4664 {
4665#if DEBUG_CMP
4666 fprintf(stderr, "Previous insn is a non-insn.\n");
4667#endif
4668 return false;
4669 }
4670 pp = PATTERN (prev);
4671 if (GET_CODE (pp) != SET)
4672 {
4673#if DEBUG_CMP
4674 fprintf(stderr, "Previous insn is not a SET.\n");
4675#endif
4676 return false;
4677 }
4678 pflags = get_attr_flags (prev);
4679
4680 /* Looking up attributes of previous insns corrupted the recog
4681 tables. */
4682 INSN_UID (cmp) = -1;
4683 recog (PATTERN (cmp), cmp, 0);
4684
4685 if (pflags == FLAGS_N
4686 && reg_mentioned_p (op0, pp))
4687 {
4688#if DEBUG_CMP
4689 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4690 debug_rtx(prev);
4691#endif
4692 return false;
4693 }
b3c5a409
DD		 4694
4695 /* Check for comparisons against memory - between volatiles and
4696 aliases, we just can't risk this one. */
4697 if (GET_CODE (operands[0]) == MEM
4698 || GET_CODE (operands[0]) == MEM)
4699 {
4700#if DEBUG_CMP
4701 fprintf(stderr, "comparisons with memory:\n");
4702 debug_rtx(prev);
4703#endif
4704 return false;
4705 }
4706
4707 /* Check for PREV changing a register that's used to compute a
4708 value in CMP, even if it doesn't otherwise change flags. */
4709 if (GET_CODE (operands[0]) == REG
4710 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
4711 {
4712#if DEBUG_CMP
4713 fprintf(stderr, "sub-value affected, op0:\n");
4714 debug_rtx(prev);
4715#endif
4716 return false;
4717 }
4718 if (GET_CODE (operands[1]) == REG
4719 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
4720 {
4721#if DEBUG_CMP
4722 fprintf(stderr, "sub-value affected, op1:\n");
4723 debug_rtx(prev);
4724#endif
4725 return false;
4726 }
4727
16659fcf
DD		 4728 } while (pflags == FLAGS_N);
4729#if DEBUG_CMP
4730 fprintf(stderr, "previous flag-setting insn:\n");
4731 debug_rtx(prev);
4732 debug_rtx(pp);
4733#endif
4734
4735 if (GET_CODE (pp) == SET
4736 && GET_CODE (XEXP (pp, 0)) == REG
4737 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4738 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4739 {
4740 /* Adjacent cbranches must have the same operands to be
4741 redundant. */
4742 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4743 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4744#if DEBUG_CMP
4745 fprintf(stderr, "adjacent cbranches\n");
4746 debug_rtx(pop0);
4747 debug_rtx(pop1);
4748#endif
4749 if (rtx_equal_p (op0, pop0)
4750 && rtx_equal_p (op1, pop1))
4751 return true;
4752#if DEBUG_CMP
4753 fprintf(stderr, "prev cmp not same\n");
4754#endif
4755 return false;
4756 }
4757
4758 /* Else the previous insn must be a SET, with either the source or
4759 dest equal to operands[0], and operands[1] must be zero. */
4760
4761 if (!rtx_equal_p (op1, const0_rtx))
4762 {
4763#if DEBUG_CMP
4764 fprintf(stderr, "operands[1] not const0_rtx\n");
4765#endif
4766 return false;
4767 }
4768 if (GET_CODE (pp) != SET)
4769 {
4770#if DEBUG_CMP
4771 fprintf (stderr, "pp not set\n");
4772#endif
4773 return false;
4774 }
4775 if (!rtx_equal_p (op0, SET_SRC (pp))
4776 && !rtx_equal_p (op0, SET_DEST (pp)))
4777 {
4778#if DEBUG_CMP
4779 fprintf(stderr, "operands[0] not found in set\n");
4780#endif
4781 return false;
4782 }
4783
4784#if DEBUG_CMP
4785 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4786#endif
4787 if ((pflags & flags_needed) == flags_needed)
4788 return true;
4789
4790 return false;
4791}
4792
4793/* Return the pattern for a compare. This will be commented out if
4794 the compare is redundant, else a normal pattern is returned. Thus,
4795 the assembler output says where the compare would have been. */
4796char *
4797m32c_output_compare (rtx insn, rtx *operands)
4798{
0a2aaacc 4799 static char templ[] = ";cmp.b\t%1,%0";
16659fcf
DD		 4800 /* ^ 5 */
4801
0a2aaacc 4802 templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
16659fcf
DD		 4803 if (m32c_compare_redundant (insn, operands))
4804 {
4805#if DEBUG_CMP
4806 fprintf(stderr, "cbranch: cmp not needed\n");
4807#endif
0a2aaacc 4808 return templ;
16659fcf
DD		 4809 }
4810
4811#if DEBUG_CMP
b3c5a409 4812 fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
16659fcf 4813#endif
0a2aaacc 4814 return templ + 1;
16659fcf
DD		 4815}
4816
5abd2125
JS		 4817#undef TARGET_ENCODE_SECTION_INFO
4818#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4819
b52b1749
AS		 4820/* If the frame pointer isn't used, we detect it manually. But the
4821 stack pointer doesn't have as flexible addressing as the frame
4822 pointer, so we always assume we have it. */
4823
4824#undef TARGET_FRAME_POINTER_REQUIRED
4825#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4826
38b2d076
DD		 4827/* The Global `targetm' Variable. */
4828
4829struct gcc_target targetm = TARGET_INITIALIZER;
4830
4831#include "gt-m32c.h"
Mirror of https://gcc.gnu.org/git/gcc.git