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38b2d076 1/* Target Code for R8C/M16C/M32C
96e45421 2 Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010, 2011
38b2d076
DD		 3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
2f83c7d6 10 by the Free Software Foundation; either version 3, or (at your
38b2d076
DD		 11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
38b2d076
DD		 21
22#include "config.h"
23#include "system.h"
24#include "coretypes.h"
25#include "tm.h"
26#include "rtl.h"
27#include "regs.h"
28#include "hard-reg-set.h"
38b2d076
DD		 29#include "insn-config.h"
30#include "conditions.h"
31#include "insn-flags.h"
32#include "output.h"
33#include "insn-attr.h"
34#include "flags.h"
35#include "recog.h"
36#include "reload.h"
718f9c0f 37#include "diagnostic-core.h"
38b2d076
DD		 38#include "obstack.h"
39#include "tree.h"
40#include "expr.h"
41#include "optabs.h"
42#include "except.h"
43#include "function.h"
44#include "ggc.h"
45#include "target.h"
46#include "target-def.h"
47#include "tm_p.h"
48#include "langhooks.h"
726a989a 49#include "gimple.h"
fa9fd28a 50#include "df.h"
96e45421 51#include "opts.h"
38b2d076
DD		 52
53/* Prototypes */
54
55/* Used by m32c_pushm_popm. */
56typedef enum
57{
58 PP_pushm,
59 PP_popm,
60 PP_justcount
61} Push_Pop_Type;
62
65655f79 63static bool m32c_function_needs_enter (void);
38b2d076 64static tree interrupt_handler (tree *, tree, tree, int, bool *);
5abd2125 65static tree function_vector_handler (tree *, tree, tree, int, bool *);
38b2d076 66static int interrupt_p (tree node);
65655f79
DD		 67static int bank_switch_p (tree node);
68static int fast_interrupt_p (tree node);
69static int interrupt_p (tree node);
38b2d076 70static bool m32c_asm_integer (rtx, unsigned int, int);
3101faab 71static int m32c_comp_type_attributes (const_tree, const_tree);
38b2d076
DD		 72static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
73static struct machine_function *m32c_init_machine_status (void);
74static void m32c_insert_attributes (tree, tree *);
c6c3dba9 75static bool m32c_legitimate_address_p (enum machine_mode, rtx, bool);
5fd5d713 76static bool m32c_addr_space_legitimate_address_p (enum machine_mode, rtx, bool, addr_space_t);
444d6efe
JR		 77static rtx m32c_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
78 const_tree, bool);
38b2d076 79static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
586de218 80 const_tree, bool);
cd34bbe8
NF		 81static void m32c_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
82 const_tree, bool);
c2ed6cf8 83static unsigned int m32c_function_arg_boundary (enum machine_mode, const_tree);
38b2d076
DD		 84static int m32c_pushm_popm (Push_Pop_Type);
85static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
86static rtx m32c_struct_value_rtx (tree, int);
87static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
88static int need_to_save (int);
2a31793e
AS		 89static rtx m32c_function_value (const_tree, const_tree, bool);
90static rtx m32c_libcall_value (enum machine_mode, const_rtx);
91
f6052f86
DD		 92/* Returns true if an address is specified, else false. */
93static bool m32c_get_pragma_address (const char *varname, unsigned *addr);
94
5abd2125 95#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
38b2d076
DD		 96
97#define streq(a,b) (strcmp ((a), (b)) == 0)
98
99/* Internal support routines */
100
101/* Debugging statements are tagged with DEBUG0 only so that they can
102 be easily enabled individually, by replacing the '0' with '1' as
103 needed. */
104#define DEBUG0 0
105#define DEBUG1 1
106
107#if DEBUG0
108/* This is needed by some of the commented-out debug statements
109 below. */
110static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
111#endif
112static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
113
114/* These are all to support encode_pattern(). */
115static char pattern[30], *patternp;
116static GTY(()) rtx patternr[30];
117#define RTX_IS(x) (streq (pattern, x))
118
119/* Some macros to simplify the logic throughout this file. */
120#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
121#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
122
123#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
124#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
125
5fd5d713
DD		 126static int
127far_addr_space_p (rtx x)
128{
129 if (GET_CODE (x) != MEM)
130 return 0;
131#if DEBUG0
132 fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
133 fprintf(stderr, " = %d\033[0m\n", MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR);
134#endif
135 return MEM_ADDR_SPACE (x) == ADDR_SPACE_FAR;
136}
137
38b2d076
DD		 138/* We do most RTX matching by converting the RTX into a string, and
139 using string compares. This vastly simplifies the logic in many of
140 the functions in this file.
141
142 On exit, pattern[] has the encoded string (use RTX_IS("...") to
143 compare it) and patternr[] has pointers to the nodes in the RTX
144 corresponding to each character in the encoded string. The latter
145 is mostly used by print_operand().
146
147 Unrecognized patterns have '?' in them; this shows up when the
148 assembler complains about syntax errors.
149*/
150
151static void
152encode_pattern_1 (rtx x)
153{
154 int i;
155
156 if (patternp == pattern + sizeof (pattern) - 2)
157 {
158 patternp[-1] = '?';
159 return;
160 }
161
162 patternr[patternp - pattern] = x;
163
164 switch (GET_CODE (x))
165 {
166 case REG:
167 *patternp++ = 'r';
168 break;
169 case SUBREG:
170 if (GET_MODE_SIZE (GET_MODE (x)) !=
171 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
172 *patternp++ = 'S';
173 encode_pattern_1 (XEXP (x, 0));
174 break;
175 case MEM:
176 *patternp++ = 'm';
177 case CONST:
178 encode_pattern_1 (XEXP (x, 0));
179 break;
5fd5d713
DD		 180 case SIGN_EXTEND:
181 *patternp++ = '^';
182 *patternp++ = 'S';
183 encode_pattern_1 (XEXP (x, 0));
184 break;
185 case ZERO_EXTEND:
186 *patternp++ = '^';
187 *patternp++ = 'Z';
188 encode_pattern_1 (XEXP (x, 0));
189 break;
38b2d076
DD		 190 case PLUS:
191 *patternp++ = '+';
192 encode_pattern_1 (XEXP (x, 0));
193 encode_pattern_1 (XEXP (x, 1));
194 break;
195 case PRE_DEC:
196 *patternp++ = '>';
197 encode_pattern_1 (XEXP (x, 0));
198 break;
199 case POST_INC:
200 *patternp++ = '<';
201 encode_pattern_1 (XEXP (x, 0));
202 break;
203 case LO_SUM:
204 *patternp++ = 'L';
205 encode_pattern_1 (XEXP (x, 0));
206 encode_pattern_1 (XEXP (x, 1));
207 break;
208 case HIGH:
209 *patternp++ = 'H';
210 encode_pattern_1 (XEXP (x, 0));
211 break;
212 case SYMBOL_REF:
213 *patternp++ = 's';
214 break;
215 case LABEL_REF:
216 *patternp++ = 'l';
217 break;
218 case CODE_LABEL:
219 *patternp++ = 'c';
220 break;
221 case CONST_INT:
222 case CONST_DOUBLE:
223 *patternp++ = 'i';
224 break;
225 case UNSPEC:
226 *patternp++ = 'u';
227 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
228 for (i = 0; i < XVECLEN (x, 0); i++)
229 encode_pattern_1 (XVECEXP (x, 0, i));
230 break;
231 case USE:
232 *patternp++ = 'U';
233 break;
234 case PARALLEL:
235 *patternp++ = '|';
236 for (i = 0; i < XVECLEN (x, 0); i++)
237 encode_pattern_1 (XVECEXP (x, 0, i));
238 break;
239 case EXPR_LIST:
240 *patternp++ = 'E';
241 encode_pattern_1 (XEXP (x, 0));
242 if (XEXP (x, 1))
243 encode_pattern_1 (XEXP (x, 1));
244 break;
245 default:
246 *patternp++ = '?';
247#if DEBUG0
248 fprintf (stderr, "can't encode pattern %s\n",
249 GET_RTX_NAME (GET_CODE (x)));
250 debug_rtx (x);
251 gcc_unreachable ();
252#endif
253 break;
254 }
255}
256
257static void
258encode_pattern (rtx x)
259{
260 patternp = pattern;
261 encode_pattern_1 (x);
262 *patternp = 0;
263}
264
265/* Since register names indicate the mode they're used in, we need a
266 way to determine which name to refer to the register with. Called
267 by print_operand(). */
268
269static const char *
270reg_name_with_mode (int regno, enum machine_mode mode)
271{
272 int mlen = GET_MODE_SIZE (mode);
273 if (regno == R0_REGNO && mlen == 1)
274 return "r0l";
275 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
276 return "r2r0";
277 if (regno == R0_REGNO && mlen == 6)
278 return "r2r1r0";
279 if (regno == R0_REGNO && mlen == 8)
280 return "r3r1r2r0";
281 if (regno == R1_REGNO && mlen == 1)
282 return "r1l";
283 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
284 return "r3r1";
285 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
286 return "a1a0";
287 return reg_names[regno];
288}
289
290/* How many bytes a register uses on stack when it's pushed. We need
291 to know this because the push opcode needs to explicitly indicate
292 the size of the register, even though the name of the register
293 already tells it that. Used by m32c_output_reg_{push,pop}, which
294 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
295
296static int
297reg_push_size (int regno)
298{
299 switch (regno)
300 {
301 case R0_REGNO:
302 case R1_REGNO:
303 return 2;
304 case R2_REGNO:
305 case R3_REGNO:
306 case FLG_REGNO:
307 return 2;
308 case A0_REGNO:
309 case A1_REGNO:
310 case SB_REGNO:
311 case FB_REGNO:
312 case SP_REGNO:
313 if (TARGET_A16)
314 return 2;
315 else
316 return 3;
317 default:
318 gcc_unreachable ();
319 }
320}
321
322static int *class_sizes = 0;
323
324/* Given two register classes, find the largest intersection between
325 them. If there is no intersection, return RETURNED_IF_EMPTY
326 instead. */
327static int
328reduce_class (int original_class, int limiting_class, int returned_if_empty)
329{
330 int cc = class_contents[original_class][0];
331 int i, best = NO_REGS;
332 int best_size = 0;
333
334 if (original_class == limiting_class)
335 return original_class;
336
337 if (!class_sizes)
338 {
339 int r;
340 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
341 for (i = 0; i < LIM_REG_CLASSES; i++)
342 {
343 class_sizes[i] = 0;
344 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
345 if (class_contents[i][0] & (1 << r))
346 class_sizes[i]++;
347 }
348 }
349
350 cc &= class_contents[limiting_class][0];
351 for (i = 0; i < LIM_REG_CLASSES; i++)
352 {
353 int ic = class_contents[i][0];
354
355 if ((~cc & ic) == 0)
356 if (best_size < class_sizes[i])
357 {
358 best = i;
359 best_size = class_sizes[i];
360 }
361
362 }
363 if (best == NO_REGS)
364 return returned_if_empty;
365 return best;
366}
367
38b2d076
DD		 368/* Used by m32c_register_move_cost to determine if a move is
369 impossibly expensive. */
0e607518
AS		 370static bool
371class_can_hold_mode (reg_class_t rclass, enum machine_mode mode)
38b2d076
DD		 372{
373 /* Cache the results: 0=untested 1=no 2=yes */
374 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
0e607518
AS		 375
376 if (results[(int) rclass][mode] == 0)
38b2d076 377 {
0e607518 378 int r;
0a2aaacc 379 results[rclass][mode] = 1;
38b2d076 380 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
0e607518 381 if (in_hard_reg_set_p (reg_class_contents[(int) rclass], mode, r)
38b2d076
DD		 382 && HARD_REGNO_MODE_OK (r, mode))
383 {
0e607518
AS		 384 results[rclass][mode] = 2;
385 break;
38b2d076
DD		 386 }
387 }
0e607518 388
38b2d076
DD		 389#if DEBUG0
390 fprintf (stderr, "class %s can hold %s? %s\n",
0e607518 391 class_names[(int) rclass], mode_name[mode],
0a2aaacc 392 (results[rclass][mode] == 2) ? "yes" : "no");
38b2d076 393#endif
0e607518 394 return results[(int) rclass][mode] == 2;
38b2d076
DD		 395}
396
397/* Run-time Target Specification. */
398
399/* Memregs are memory locations that gcc treats like general
400 registers, as there are a limited number of true registers and the
401 m32c families can use memory in most places that registers can be
402 used.
403
404 However, since memory accesses are more expensive than registers,
405 we allow the user to limit the number of memregs available, in
406 order to try to persuade gcc to try harder to use real registers.
407
408 Memregs are provided by m32c-lib1.S.
409*/
410
411int target_memregs = 16;
412static bool target_memregs_set = FALSE;
413int ok_to_change_target_memregs = TRUE;
414
415#undef TARGET_HANDLE_OPTION
416#define TARGET_HANDLE_OPTION m32c_handle_option
417static bool
96e45421
JM		 418m32c_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
419 const struct cl_decoded_option *decoded,
420 location_t loc ATTRIBUTE_UNUSED)
38b2d076 421{
96e45421
JM		 422 size_t code = decoded->opt_index;
423 const char *arg = decoded->arg;
424
425 gcc_assert (opts == &global_options);
426 gcc_assert (opts_set == &global_options_set);
427
38b2d076
DD		 428 if (code == OPT_memregs_)
429 {
430 target_memregs_set = TRUE;
431 target_memregs = atoi (arg);
432 }
433 return TRUE;
434}
435
f28f2337
AS		 436/* Implements TARGET_OPTION_OVERRIDE. */
437
438#undef TARGET_OPTION_OVERRIDE
439#define TARGET_OPTION_OVERRIDE m32c_option_override
440
441static void
442m32c_option_override (void)
38b2d076 443{
f28f2337 444 /* We limit memregs to 0..16, and provide a default. */
38b2d076
DD		 445 if (target_memregs_set)
446 {
447 if (target_memregs < 0 || target_memregs > 16)
448 error ("invalid target memregs value '%d'", target_memregs);
449 }
450 else
07127a0a 451 target_memregs = 16;
18b80268
DD		 452
453 if (TARGET_A24)
454 flag_ivopts = 0;
0685e770
DD		 455
456 /* This target defaults to strict volatile bitfields. */
457 if (flag_strict_volatile_bitfields < 0)
458 flag_strict_volatile_bitfields = 1;
d123bf41
DD		 459
460 /* r8c/m16c have no 16-bit indirect call, so thunks are involved.
461 This is always worse than an absolute call. */
462 if (TARGET_A16)
463 flag_no_function_cse = 1;
a4403164
DD		 464
465 /* This wants to put insns between compares and their jumps. */
466 /* FIXME: The right solution is to properly trace the flags register
467 values, but that is too much work for stage 4. */
468 flag_combine_stack_adjustments = 0;
d123bf41
DD		 469}
470
471#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
472#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change
473
474static void
475m32c_override_options_after_change (void)
476{
477 if (TARGET_A16)
478 flag_no_function_cse = 1;
38b2d076
DD		 479}
480
481/* Defining data structures for per-function information */
482
483/* The usual; we set up our machine_function data. */
484static struct machine_function *
485m32c_init_machine_status (void)
486{
a9429e29 487 return ggc_alloc_cleared_machine_function ();
38b2d076
DD		 488}
489
490/* Implements INIT_EXPANDERS. We just set up to call the above
491 function. */
492void
493m32c_init_expanders (void)
494{
495 init_machine_status = m32c_init_machine_status;
496}
497
498/* Storage Layout */
499
38b2d076
DD		 500/* Register Basics */
501
502/* Basic Characteristics of Registers */
503
504/* Whether a mode fits in a register is complex enough to warrant a
505 table. */
506static struct
507{
508 char qi_regs;
509 char hi_regs;
510 char pi_regs;
511 char si_regs;
512 char di_regs;
513} nregs_table[FIRST_PSEUDO_REGISTER] =
514{
515 { 1, 1, 2, 2, 4 }, /* r0 */
516 { 0, 1, 0, 0, 0 }, /* r2 */
517 { 1, 1, 2, 2, 0 }, /* r1 */
518 { 0, 1, 0, 0, 0 }, /* r3 */
519 { 0, 1, 1, 0, 0 }, /* a0 */
520 { 0, 1, 1, 0, 0 }, /* a1 */
521 { 0, 1, 1, 0, 0 }, /* sb */
522 { 0, 1, 1, 0, 0 }, /* fb */
523 { 0, 1, 1, 0, 0 }, /* sp */
524 { 1, 1, 1, 0, 0 }, /* pc */
525 { 0, 0, 0, 0, 0 }, /* fl */
526 { 1, 1, 1, 0, 0 }, /* ap */
527 { 1, 1, 2, 2, 4 }, /* mem0 */
528 { 1, 1, 2, 2, 4 }, /* mem1 */
529 { 1, 1, 2, 2, 4 }, /* mem2 */
530 { 1, 1, 2, 2, 4 }, /* mem3 */
531 { 1, 1, 2, 2, 4 }, /* mem4 */
532 { 1, 1, 2, 2, 0 }, /* mem5 */
533 { 1, 1, 2, 2, 0 }, /* mem6 */
534 { 1, 1, 0, 0, 0 }, /* mem7 */
535};
536
5efd84c5
NF		 537/* Implements TARGET_CONDITIONAL_REGISTER_USAGE. We adjust the number
538 of available memregs, and select which registers need to be preserved
38b2d076
DD		 539 across calls based on the chip family. */
540
5efd84c5
NF		 541#undef TARGET_CONDITIONAL_REGISTER_USAGE
542#define TARGET_CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage
d6d17ae7 543void
38b2d076
DD		 544m32c_conditional_register_usage (void)
545{
38b2d076
DD		 546 int i;
547
548 if (0 <= target_memregs && target_memregs <= 16)
549 {
550 /* The command line option is bytes, but our "registers" are
551 16-bit words. */
65655f79 552 for (i = (target_memregs+1)/2; i < 8; i++)
38b2d076
DD		 553 {
554 fixed_regs[MEM0_REGNO + i] = 1;
555 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
556 }
557 }
558
559 /* M32CM and M32C preserve more registers across function calls. */
560 if (TARGET_A24)
561 {
562 call_used_regs[R1_REGNO] = 0;
563 call_used_regs[R2_REGNO] = 0;
564 call_used_regs[R3_REGNO] = 0;
565 call_used_regs[A0_REGNO] = 0;
566 call_used_regs[A1_REGNO] = 0;
567 }
568}
569
570/* How Values Fit in Registers */
571
572/* Implements HARD_REGNO_NREGS. This is complicated by the fact that
573 different registers are different sizes from each other, *and* may
574 be different sizes in different chip families. */
b8a669d0
DD		 575static int
576m32c_hard_regno_nregs_1 (int regno, enum machine_mode mode)
38b2d076
DD		 577{
578 if (regno == FLG_REGNO && mode == CCmode)
579 return 1;
580 if (regno >= FIRST_PSEUDO_REGISTER)
581 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
582
583 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
584 return (GET_MODE_SIZE (mode) + 1) / 2;
585
586 if (GET_MODE_SIZE (mode) <= 1)
587 return nregs_table[regno].qi_regs;
588 if (GET_MODE_SIZE (mode) <= 2)
589 return nregs_table[regno].hi_regs;
5fd5d713 590 if (regno == A0_REGNO && mode == SImode && TARGET_A16)
38b2d076
DD		 591 return 2;
592 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
593 return nregs_table[regno].pi_regs;
594 if (GET_MODE_SIZE (mode) <= 4)
595 return nregs_table[regno].si_regs;
596 if (GET_MODE_SIZE (mode) <= 8)
597 return nregs_table[regno].di_regs;
598 return 0;
599}
600
b8a669d0
DD		 601int
602m32c_hard_regno_nregs (int regno, enum machine_mode mode)
603{
604 int rv = m32c_hard_regno_nregs_1 (regno, mode);
605 return rv ? rv : 1;
606}
607
38b2d076
DD		 608/* Implements HARD_REGNO_MODE_OK. The above function does the work
609 already; just test its return value. */
610int
611m32c_hard_regno_ok (int regno, enum machine_mode mode)
612{
b8a669d0 613 return m32c_hard_regno_nregs_1 (regno, mode) != 0;
38b2d076
DD		 614}
615
616/* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
617 registers are all different sizes. However, since most modes are
618 bigger than our registers anyway, it's easier to implement this
619 function that way, leaving QImode as the only unique case. */
620int
621m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
622{
623 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
624 return 1;
625
07127a0a 626#if 0
38b2d076
DD		 627 if (m1 == QImode || m2 == QImode)
628 return 0;
07127a0a 629#endif
38b2d076
DD		 630
631 return 1;
632}
633
634/* Register Classes */
635
636/* Implements REGNO_REG_CLASS. */
444d6efe 637enum reg_class
38b2d076
DD		 638m32c_regno_reg_class (int regno)
639{
640 switch (regno)
641 {
642 case R0_REGNO:
643 return R0_REGS;
644 case R1_REGNO:
645 return R1_REGS;
646 case R2_REGNO:
647 return R2_REGS;
648 case R3_REGNO:
649 return R3_REGS;
650 case A0_REGNO:
22843acd 651 return A0_REGS;
38b2d076 652 case A1_REGNO:
22843acd 653 return A1_REGS;
38b2d076
DD		 654 case SB_REGNO:
655 return SB_REGS;
656 case FB_REGNO:
657 return FB_REGS;
658 case SP_REGNO:
659 return SP_REGS;
660 case FLG_REGNO:
661 return FLG_REGS;
662 default:
663 if (IS_MEM_REGNO (regno))
664 return MEM_REGS;
665 return ALL_REGS;
666 }
667}
668
669/* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
670 for certain chip families. */
671int
672m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
673{
674 if (memcmp (s, "Rsp", 3) == 0)
675 return SP_REGS;
676 if (memcmp (s, "Rfb", 3) == 0)
677 return FB_REGS;
678 if (memcmp (s, "Rsb", 3) == 0)
679 return SB_REGS;
07127a0a
DD		 680 if (memcmp (s, "Rcr", 3) == 0)
681 return TARGET_A16 ? CR_REGS : NO_REGS;
682 if (memcmp (s, "Rcl", 3) == 0)
683 return TARGET_A24 ? CR_REGS : NO_REGS;
38b2d076
DD		 684 if (memcmp (s, "R0w", 3) == 0)
685 return R0_REGS;
686 if (memcmp (s, "R1w", 3) == 0)
687 return R1_REGS;
688 if (memcmp (s, "R2w", 3) == 0)
689 return R2_REGS;
690 if (memcmp (s, "R3w", 3) == 0)
691 return R3_REGS;
692 if (memcmp (s, "R02", 3) == 0)
693 return R02_REGS;
18b80268
DD		 694 if (memcmp (s, "R13", 3) == 0)
695 return R13_REGS;
38b2d076
DD		 696 if (memcmp (s, "R03", 3) == 0)
697 return R03_REGS;
698 if (memcmp (s, "Rdi", 3) == 0)
699 return DI_REGS;
700 if (memcmp (s, "Rhl", 3) == 0)
701 return HL_REGS;
702 if (memcmp (s, "R23", 3) == 0)
703 return R23_REGS;
07127a0a
DD		 704 if (memcmp (s, "Ra0", 3) == 0)
705 return A0_REGS;
706 if (memcmp (s, "Ra1", 3) == 0)
707 return A1_REGS;
38b2d076
DD		 708 if (memcmp (s, "Raa", 3) == 0)
709 return A_REGS;
07127a0a
DD		 710 if (memcmp (s, "Raw", 3) == 0)
711 return TARGET_A16 ? A_REGS : NO_REGS;
712 if (memcmp (s, "Ral", 3) == 0)
713 return TARGET_A24 ? A_REGS : NO_REGS;
38b2d076
DD		 714 if (memcmp (s, "Rqi", 3) == 0)
715 return QI_REGS;
716 if (memcmp (s, "Rad", 3) == 0)
717 return AD_REGS;
718 if (memcmp (s, "Rsi", 3) == 0)
719 return SI_REGS;
720 if (memcmp (s, "Rhi", 3) == 0)
721 return HI_REGS;
722 if (memcmp (s, "Rhc", 3) == 0)
723 return HC_REGS;
724 if (memcmp (s, "Rra", 3) == 0)
725 return RA_REGS;
726 if (memcmp (s, "Rfl", 3) == 0)
727 return FLG_REGS;
728 if (memcmp (s, "Rmm", 3) == 0)
729 {
730 if (fixed_regs[MEM0_REGNO])
731 return NO_REGS;
732 return MEM_REGS;
733 }
734
735 /* PSImode registers - i.e. whatever can hold a pointer. */
736 if (memcmp (s, "Rpi", 3) == 0)
737 {
738 if (TARGET_A16)
739 return HI_REGS;
740 else
741 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
742 }
743
744 /* We handle this one as an EXTRA_CONSTRAINT. */
745 if (memcmp (s, "Rpa", 3) == 0)
746 return NO_REGS;
747
07127a0a
DD		 748 if (*s == 'R')
749 {
750 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
751 gcc_unreachable();
752 }
753
38b2d076
DD		 754 return NO_REGS;
755}
756
757/* Implements REGNO_OK_FOR_BASE_P. */
758int
759m32c_regno_ok_for_base_p (int regno)
760{
761 if (regno == A0_REGNO
762 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
763 return 1;
764 return 0;
765}
766
767#define DEBUG_RELOAD 0
768
769/* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
770 registers of the appropriate size. */
771int
772m32c_preferred_reload_class (rtx x, int rclass)
773{
774 int newclass = rclass;
775
776#if DEBUG_RELOAD
777 fprintf (stderr, "\npreferred_reload_class for %s is ",
778 class_names[rclass]);
779#endif
780 if (rclass == NO_REGS)
781 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
782
0e607518 783 if (reg_classes_intersect_p (rclass, CR_REGS))
38b2d076
DD		 784 {
785 switch (GET_MODE (x))
786 {
787 case QImode:
788 newclass = HL_REGS;
789 break;
790 default:
791 /* newclass = HI_REGS; */
792 break;
793 }
794 }
795
796 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
797 newclass = SI_REGS;
798 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
799 && ~class_contents[rclass][0] & 0x000f)
800 newclass = DI_REGS;
801
802 rclass = reduce_class (rclass, newclass, rclass);
803
804 if (GET_MODE (x) == QImode)
805 rclass = reduce_class (rclass, HL_REGS, rclass);
806
807#if DEBUG_RELOAD
808 fprintf (stderr, "%s\n", class_names[rclass]);
809 debug_rtx (x);
810
811 if (GET_CODE (x) == MEM
812 && GET_CODE (XEXP (x, 0)) == PLUS
813 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
814 fprintf (stderr, "Glorm!\n");
815#endif
816 return rclass;
817}
818
819/* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
820int
821m32c_preferred_output_reload_class (rtx x, int rclass)
822{
823 return m32c_preferred_reload_class (x, rclass);
824}
825
826/* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
827 address registers for reloads since they're needed for address
828 reloads. */
829int
830m32c_limit_reload_class (enum machine_mode mode, int rclass)
831{
832#if DEBUG_RELOAD
833 fprintf (stderr, "limit_reload_class for %s: %s ->",
834 mode_name[mode], class_names[rclass]);
835#endif
836
837 if (mode == QImode)
838 rclass = reduce_class (rclass, HL_REGS, rclass);
839 else if (mode == HImode)
840 rclass = reduce_class (rclass, HI_REGS, rclass);
841 else if (mode == SImode)
842 rclass = reduce_class (rclass, SI_REGS, rclass);
843
844 if (rclass != A_REGS)
845 rclass = reduce_class (rclass, DI_REGS, rclass);
846
847#if DEBUG_RELOAD
848 fprintf (stderr, " %s\n", class_names[rclass]);
849#endif
850 return rclass;
851}
852
853/* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
854 r0 or r1, as those are the only real QImode registers. CR regs get
855 reloaded through appropriately sized general or address
856 registers. */
857int
858m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
859{
860 int cc = class_contents[rclass][0];
861#if DEBUG0
862 fprintf (stderr, "\nsecondary reload class %s %s\n",
863 class_names[rclass], mode_name[mode]);
864 debug_rtx (x);
865#endif
866 if (mode == QImode
867 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
868 return QI_REGS;
0e607518 869 if (reg_classes_intersect_p (rclass, CR_REGS)
38b2d076
DD		 870 && GET_CODE (x) == REG
871 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
872 return TARGET_A16 ? HI_REGS : A_REGS;
873 return NO_REGS;
874}
875
184866c5 876/* Implements TARGET_CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
38b2d076 877 reloads. */
184866c5
AS		 878
879#undef TARGET_CLASS_LIKELY_SPILLED_P
880#define TARGET_CLASS_LIKELY_SPILLED_P m32c_class_likely_spilled_p
881
882static bool
883m32c_class_likely_spilled_p (reg_class_t regclass)
38b2d076
DD		 884{
885 if (regclass == A_REGS)
184866c5
AS		 886 return true;
887
888 return (reg_class_size[(int) regclass] == 1);
38b2d076
DD		 889}
890
891/* Implements CLASS_MAX_NREGS. We calculate this according to its
892 documented meaning, to avoid potential inconsistencies with actual
893 class definitions. */
894int
895m32c_class_max_nregs (int regclass, enum machine_mode mode)
896{
897 int rn, max = 0;
898
899 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
900 if (class_contents[regclass][0] & (1 << rn))
901 {
902 int n = m32c_hard_regno_nregs (rn, mode);
903 if (max < n)
904 max = n;
905 }
906 return max;
907}
908
909/* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
910 QI (r0l, r1l) because the chip doesn't support QI ops on other
911 registers (well, it does on a0/a1 but if we let gcc do that, reload
912 suffers). Otherwise, we allow changes to larger modes. */
913int
914m32c_cannot_change_mode_class (enum machine_mode from,
915 enum machine_mode to, int rclass)
916{
db9c8397 917 int rn;
38b2d076
DD		 918#if DEBUG0
919 fprintf (stderr, "cannot change from %s to %s in %s\n",
920 mode_name[from], mode_name[to], class_names[rclass]);
921#endif
922
db9c8397
DD		 923 /* If the larger mode isn't allowed in any of these registers, we
924 can't allow the change. */
925 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
926 if (class_contents[rclass][0] & (1 << rn))
927 if (! m32c_hard_regno_ok (rn, to))
928 return 1;
929
38b2d076
DD		 930 if (to == QImode)
931 return (class_contents[rclass][0] & 0x1ffa);
932
933 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
934 && GET_MODE_SIZE (from) > 1)
935 return 0;
936 if (GET_MODE_SIZE (from) > 2) /* all other regs */
937 return 0;
938
939 return 1;
940}
941
942/* Helpers for the rest of the file. */
943/* TRUE if the rtx is a REG rtx for the given register. */
944#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
945 && REGNO (rtx) == regno)
946/* TRUE if the rtx is a pseudo - specifically, one we can use as a
947 base register in address calculations (hence the "strict"
948 argument). */
949#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
950 && (REGNO (rtx) == AP_REGNO \
951 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
952
953/* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
954 constraints start with 'I', with the next two characters indicating
955 the type and size of the range allowed. */
956int
957m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
958 char c ATTRIBUTE_UNUSED, const char *str)
959{
960 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
961 [sun] bits [SUN] bytes, p=pointer size
962 I[-0-9][0-9] matches that number */
963 if (memcmp (str, "Is3", 3) == 0)
964 {
965 return (-8 <= value && value <= 7);
966 }
967 if (memcmp (str, "IS1", 3) == 0)
968 {
969 return (-128 <= value && value <= 127);
970 }
971 if (memcmp (str, "IS2", 3) == 0)
972 {
973 return (-32768 <= value && value <= 32767);
974 }
975 if (memcmp (str, "IU2", 3) == 0)
976 {
977 return (0 <= value && value <= 65535);
978 }
979 if (memcmp (str, "IU3", 3) == 0)
980 {
981 return (0 <= value && value <= 0x00ffffff);
982 }
983 if (memcmp (str, "In4", 3) == 0)
984 {
985 return (-8 <= value && value && value <= 8);
986 }
987 if (memcmp (str, "In5", 3) == 0)
988 {
989 return (-16 <= value && value && value <= 16);
990 }
23fed240
DD		 991 if (memcmp (str, "In6", 3) == 0)
992 {
993 return (-32 <= value && value && value <= 32);
994 }
38b2d076
DD		 995 if (memcmp (str, "IM2", 3) == 0)
996 {
997 return (-65536 <= value && value && value <= -1);
998 }
999 if (memcmp (str, "Ilb", 3) == 0)
1000 {
1001 int b = exact_log2 (value);
8e4edce7 1002 return (b >= 0 && b <= 7);
38b2d076 1003 }
07127a0a
DD		 1004 if (memcmp (str, "Imb", 3) == 0)
1005 {
1006 int b = exact_log2 ((value ^ 0xff) & 0xff);
8e4edce7 1007 return (b >= 0 && b <= 7);
07127a0a 1008 }
600e668e
DD		 1009 if (memcmp (str, "ImB", 3) == 0)
1010 {
1011 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
1012 return (b >= 0 && b <= 7);
1013 }
38b2d076
DD		 1014 if (memcmp (str, "Ilw", 3) == 0)
1015 {
1016 int b = exact_log2 (value);
8e4edce7 1017 return (b >= 0 && b <= 15);
38b2d076 1018 }
07127a0a
DD		 1019 if (memcmp (str, "Imw", 3) == 0)
1020 {
1021 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
8e4edce7 1022 return (b >= 0 && b <= 15);
07127a0a
DD		 1023 }
1024 if (memcmp (str, "I00", 3) == 0)
1025 {
1026 return (value == 0);
1027 }
38b2d076
DD		 1028 return 0;
1029}
1030
5fd5d713
DD		 1031#define A0_OR_PSEUDO(x) (IS_REG(x, A0_REGNO) || REGNO (x) >= FIRST_PSEUDO_REGISTER)
1032
38b2d076
DD		 1033/* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
1034 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
1035 call return values. */
1036int
1037m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
1038{
1039 encode_pattern (value);
5fd5d713
DD		 1040
1041 if (far_addr_space_p (value))
1042 {
1043 if (memcmp (str, "SF", 2) == 0)
1044 {
1045 return ( (RTX_IS ("mr")
1046 && A0_OR_PSEUDO (patternr[1])
1047 && GET_MODE (patternr[1]) == SImode)
1048 || (RTX_IS ("m+^Sri")
1049 && A0_OR_PSEUDO (patternr[4])
1050 && GET_MODE (patternr[4]) == HImode)
1051 || (RTX_IS ("m+^Srs")
1052 && A0_OR_PSEUDO (patternr[4])
1053 && GET_MODE (patternr[4]) == HImode)
1054 || (RTX_IS ("m+^S+ris")
1055 && A0_OR_PSEUDO (patternr[5])
1056 && GET_MODE (patternr[5]) == HImode)
1057 || RTX_IS ("ms")
1058 );
1059 }
1060 return 0;
1061 }
1062
38b2d076
DD		 1063 if (memcmp (str, "Sd", 2) == 0)
1064 {
1065 /* This is the common "src/dest" address */
1066 rtx r;
1067 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
1068 return 1;
1069 if (RTX_IS ("ms") || RTX_IS ("m+si"))
1070 return 1;
07127a0a
DD		 1071 if (RTX_IS ("m++rii"))
1072 {
1073 if (REGNO (patternr[3]) == FB_REGNO
1074 && INTVAL (patternr[4]) == 0)
1075 return 1;
1076 }
38b2d076
DD		 1077 if (RTX_IS ("mr"))
1078 r = patternr[1];
1079 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
1080 r = patternr[2];
1081 else
1082 return 0;
1083 if (REGNO (r) == SP_REGNO)
1084 return 0;
1085 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
1086 }
1087 else if (memcmp (str, "Sa", 2) == 0)
1088 {
1089 rtx r;
1090 if (RTX_IS ("mr"))
1091 r = patternr[1];
1092 else if (RTX_IS ("m+ri"))
1093 r = patternr[2];
1094 else
1095 return 0;
1096 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1097 }
1098 else if (memcmp (str, "Si", 2) == 0)
1099 {
1100 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1101 }
1102 else if (memcmp (str, "Ss", 2) == 0)
1103 {
1104 return ((RTX_IS ("mr")
1105 && (IS_REG (patternr[1], SP_REGNO)))
1106 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1107 }
1108 else if (memcmp (str, "Sf", 2) == 0)
1109 {
1110 return ((RTX_IS ("mr")
1111 && (IS_REG (patternr[1], FB_REGNO)))
1112 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1113 }
1114 else if (memcmp (str, "Sb", 2) == 0)
1115 {
1116 return ((RTX_IS ("mr")
1117 && (IS_REG (patternr[1], SB_REGNO)))
1118 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1119 }
07127a0a
DD		 1120 else if (memcmp (str, "Sp", 2) == 0)
1121 {
1122 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1123 return (RTX_IS ("mi")
1124 && !(INTVAL (patternr[1]) & ~0x1fff));
1125 }
38b2d076
DD		 1126 else if (memcmp (str, "S1", 2) == 0)
1127 {
1128 return r1h_operand (value, QImode);
1129 }
5fd5d713
DD		 1130 else if (memcmp (str, "SF", 2) == 0)
1131 {
1132 return 0;
1133 }
38b2d076
DD		 1134
1135 gcc_assert (str[0] != 'S');
1136
1137 if (memcmp (str, "Rpa", 2) == 0)
1138 return GET_CODE (value) == PARALLEL;
1139
1140 return 0;
1141}
1142
1143/* This is for when we're debugging the above. */
1144int
1145m32c_extra_constraint_p (rtx value, char c, const char *str)
1146{
1147 int rv = m32c_extra_constraint_p2 (value, c, str);
1148#if DEBUG0
1149 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1150 rv);
1151 debug_rtx (value);
1152#endif
1153 return rv;
1154}
1155
1156/* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1157 starting with 'S'. */
1158int
1159m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1160{
1161 return c == 'S';
1162}
1163
1164/* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1165 but don't currently define any. */
1166int
1167m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1168{
1169 return c == 'A';
1170}
1171
1172/* STACK AND CALLING */
1173
1174/* Frame Layout */
1175
1176/* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1177 (yes, THREE bytes) onto the stack for the return address, but we
1178 don't support pointers bigger than 16 bits on those chips. This
1179 will likely wreak havoc with exception unwinding. FIXME. */
1180rtx
1181m32c_return_addr_rtx (int count)
1182{
1183 enum machine_mode mode;
1184 int offset;
1185 rtx ra_mem;
1186
1187 if (count)
1188 return NULL_RTX;
1189 /* we want 2[$fb] */
1190
1191 if (TARGET_A24)
1192 {
80b093df
DD		 1193 /* It's four bytes */
1194 mode = PSImode;
38b2d076
DD		 1195 offset = 4;
1196 }
1197 else
1198 {
1199 /* FIXME: it's really 3 bytes */
1200 mode = HImode;
1201 offset = 2;
1202 }
1203
1204 ra_mem =
1205 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1206 return copy_to_mode_reg (mode, ra_mem);
1207}
1208
1209/* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1210rtx
1211m32c_incoming_return_addr_rtx (void)
1212{
1213 /* we want [sp] */
1214 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1215}
1216
1217/* Exception Handling Support */
1218
1219/* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1220 pointers. */
1221int
1222m32c_eh_return_data_regno (int n)
1223{
1224 switch (n)
1225 {
1226 case 0:
1227 return A0_REGNO;
1228 case 1:
c6004917
RIL		 1229 if (TARGET_A16)
1230 return R3_REGNO;
1231 else
1232 return R1_REGNO;
38b2d076
DD		 1233 default:
1234 return INVALID_REGNUM;
1235 }
1236}
1237
1238/* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1239 m32c_emit_eh_epilogue. */
1240rtx
1241m32c_eh_return_stackadj_rtx (void)
1242{
1243 if (!cfun->machine->eh_stack_adjust)
1244 {
1245 rtx sa;
1246
99920b6f 1247 sa = gen_rtx_REG (Pmode, R0_REGNO);
38b2d076
DD		 1248 cfun->machine->eh_stack_adjust = sa;
1249 }
1250 return cfun->machine->eh_stack_adjust;
1251}
1252
1253/* Registers That Address the Stack Frame */
1254
1255/* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1256 the original spec called for dwarf numbers to vary with register
1257 width as well, for example, r0l, r0, and r2r0 would each have
1258 different dwarf numbers. GCC doesn't support this, and we don't do
1259 it, and gdb seems to like it this way anyway. */
1260unsigned int
1261m32c_dwarf_frame_regnum (int n)
1262{
1263 switch (n)
1264 {
1265 case R0_REGNO:
1266 return 5;
1267 case R1_REGNO:
1268 return 6;
1269 case R2_REGNO:
1270 return 7;
1271 case R3_REGNO:
1272 return 8;
1273 case A0_REGNO:
1274 return 9;
1275 case A1_REGNO:
1276 return 10;
1277 case FB_REGNO:
1278 return 11;
1279 case SB_REGNO:
1280 return 19;
1281
1282 case SP_REGNO:
1283 return 12;
1284 case PC_REGNO:
1285 return 13;
1286 default:
1287 return DWARF_FRAME_REGISTERS + 1;
1288 }
1289}
1290
1291/* The frame looks like this:
1292
1293 ap -> +------------------------------
1294 | Return address (3 or 4 bytes)
1295 | Saved FB (2 or 4 bytes)
1296 fb -> +------------------------------
1297 | local vars
1298 | register saves fb
1299 | through r0 as needed
1300 sp -> +------------------------------
1301*/
1302
1303/* We use this to wrap all emitted insns in the prologue. */
1304static rtx
1305F (rtx x)
1306{
1307 RTX_FRAME_RELATED_P (x) = 1;
1308 return x;
1309}
1310
1311/* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1312 how much the stack pointer moves for each, for each cpu family. */
1313static struct
1314{
1315 int reg1;
1316 int bit;
1317 int a16_bytes;
1318 int a24_bytes;
1319} pushm_info[] =
1320{
9d746d5e
DD		 1321 /* These are in reverse push (nearest-to-sp) order. */
1322 { R0_REGNO, 0x80, 2, 2 },
38b2d076 1323 { R1_REGNO, 0x40, 2, 2 },
9d746d5e
DD		 1324 { R2_REGNO, 0x20, 2, 2 },
1325 { R3_REGNO, 0x10, 2, 2 },
1326 { A0_REGNO, 0x08, 2, 4 },
1327 { A1_REGNO, 0x04, 2, 4 },
1328 { SB_REGNO, 0x02, 2, 4 },
1329 { FB_REGNO, 0x01, 2, 4 }
38b2d076
DD		 1330};
1331
1332#define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1333
1334/* Returns TRUE if we need to save/restore the given register. We
1335 save everything for exception handlers, so that any register can be
1336 unwound. For interrupt handlers, we save everything if the handler
1337 calls something else (because we don't know what *that* function
1338 might do), but try to be a bit smarter if the handler is a leaf
1339 function. We always save $a0, though, because we use that in the
85f65093 1340 epilogue to copy $fb to $sp. */
38b2d076
DD		 1341static int
1342need_to_save (int regno)
1343{
1344 if (fixed_regs[regno])
1345 return 0;
ad516a74 1346 if (crtl->calls_eh_return)
38b2d076
DD		 1347 return 1;
1348 if (regno == FP_REGNO)
1349 return 0;
1350 if (cfun->machine->is_interrupt
65655f79
DD		 1351 && (!cfun->machine->is_leaf
1352 || (regno == A0_REGNO
1353 && m32c_function_needs_enter ())
1354 ))
38b2d076 1355 return 1;
6fb5fa3c 1356 if (df_regs_ever_live_p (regno)
38b2d076
DD		 1357 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1358 return 1;
1359 return 0;
1360}
1361
1362/* This function contains all the intelligence about saving and
1363 restoring registers. It always figures out the register save set.
1364 When called with PP_justcount, it merely returns the size of the
1365 save set (for eliminating the frame pointer, for example). When
1366 called with PP_pushm or PP_popm, it emits the appropriate
1367 instructions for saving (pushm) or restoring (popm) the
1368 registers. */
1369static int
1370m32c_pushm_popm (Push_Pop_Type ppt)
1371{
1372 int reg_mask = 0;
1373 int byte_count = 0, bytes;
1374 int i;
1375 rtx dwarf_set[PUSHM_N];
1376 int n_dwarfs = 0;
1377 int nosave_mask = 0;
1378
305da3ec
JH		 1379 if (crtl->return_rtx
1380 && GET_CODE (crtl->return_rtx) == PARALLEL
ad516a74 1381 && !(crtl->calls_eh_return || cfun->machine->is_interrupt))
38b2d076 1382 {
305da3ec 1383 rtx exp = XVECEXP (crtl->return_rtx, 0, 0);
38b2d076
DD		 1384 rtx rv = XEXP (exp, 0);
1385 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1386
1387 if (rv_bytes > 2)
1388 nosave_mask |= 0x20; /* PSI, SI */
1389 else
1390 nosave_mask |= 0xf0; /* DF */
1391 if (rv_bytes > 4)
1392 nosave_mask |= 0x50; /* DI */
1393 }
1394
1395 for (i = 0; i < (int) PUSHM_N; i++)
1396 {
1397 /* Skip if neither register needs saving. */
1398 if (!need_to_save (pushm_info[i].reg1))
1399 continue;
1400
1401 if (pushm_info[i].bit & nosave_mask)
1402 continue;
1403
1404 reg_mask |= pushm_info[i].bit;
1405 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1406
1407 if (ppt == PP_pushm)
1408 {
1409 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1410 rtx addr;
1411
1412 /* Always use stack_pointer_rtx instead of calling
1413 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1414 that there is a single rtx representing the stack pointer,
1415 namely stack_pointer_rtx, and uses == to recognize it. */
1416 addr = stack_pointer_rtx;
1417
1418 if (byte_count != 0)
1419 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1420
1421 dwarf_set[n_dwarfs++] =
1422 gen_rtx_SET (VOIDmode,
1423 gen_rtx_MEM (mode, addr),
1424 gen_rtx_REG (mode, pushm_info[i].reg1));
1425 F (dwarf_set[n_dwarfs - 1]);
1426
1427 }
1428 byte_count += bytes;
1429 }
1430
1431 if (cfun->machine->is_interrupt)
1432 {
1433 cfun->machine->intr_pushm = reg_mask & 0xfe;
1434 reg_mask = 0;
1435 byte_count = 0;
1436 }
1437
1438 if (cfun->machine->is_interrupt)
1439 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1440 if (need_to_save (i))
1441 {
1442 byte_count += 2;
1443 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1444 }
1445
1446 if (ppt == PP_pushm && byte_count)
1447 {
1448 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1449 rtx pushm;
1450
1451 if (reg_mask)
1452 {
1453 XVECEXP (note, 0, 0)
1454 = gen_rtx_SET (VOIDmode,
1455 stack_pointer_rtx,
1456 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1457 stack_pointer_rtx,
1458 GEN_INT (-byte_count)));
1459 F (XVECEXP (note, 0, 0));
1460
1461 for (i = 0; i < n_dwarfs; i++)
1462 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1463
1464 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1465
444d6efe 1466 add_reg_note (pushm, REG_FRAME_RELATED_EXPR, note);
38b2d076
DD		 1467 }
1468
1469 if (cfun->machine->is_interrupt)
1470 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1471 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1472 {
1473 if (TARGET_A16)
1474 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1475 else
1476 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1477 F (pushm);
1478 }
1479 }
1480 if (ppt == PP_popm && byte_count)
1481 {
38b2d076
DD		 1482 if (cfun->machine->is_interrupt)
1483 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1484 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1485 {
1486 if (TARGET_A16)
b3fdec9e 1487 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
38b2d076 1488 else
b3fdec9e 1489 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
38b2d076
DD		 1490 }
1491 if (reg_mask)
1492 emit_insn (gen_popm (GEN_INT (reg_mask)));
1493 }
1494
1495 return byte_count;
1496}
1497
1498/* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1499 diagrams our call frame. */
1500int
1501m32c_initial_elimination_offset (int from, int to)
1502{
1503 int ofs = 0;
1504
1505 if (from == AP_REGNO)
1506 {
1507 if (TARGET_A16)
1508 ofs += 5;
1509 else
1510 ofs += 8;
1511 }
1512
1513 if (to == SP_REGNO)
1514 {
1515 ofs += m32c_pushm_popm (PP_justcount);
1516 ofs += get_frame_size ();
1517 }
1518
1519 /* Account for push rounding. */
1520 if (TARGET_A24)
1521 ofs = (ofs + 1) & ~1;
1522#if DEBUG0
1523 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1524 to, ofs);
1525#endif
1526 return ofs;
1527}
1528
1529/* Passing Function Arguments on the Stack */
1530
38b2d076
DD		 1531/* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1532 M32C has word stacks. */
444d6efe 1533unsigned int
38b2d076
DD		 1534m32c_push_rounding (int n)
1535{
1536 if (TARGET_R8C || TARGET_M16C)
1537 return n;
1538 return (n + 1) & ~1;
1539}
1540
1541/* Passing Arguments in Registers */
1542
cd34bbe8
NF		 1543/* Implements TARGET_FUNCTION_ARG. Arguments are passed partly in
1544 registers, partly on stack. If our function returns a struct, a
1545 pointer to a buffer for it is at the top of the stack (last thing
1546 pushed). The first few real arguments may be in registers as
1547 follows:
38b2d076
DD		 1548
1549 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1550 arg2 in r2 if it's HI (else pushed on stack)
1551 rest on stack
1552 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1553 rest on stack
1554
1555 Structs are not passed in registers, even if they fit. Only
1556 integer and pointer types are passed in registers.
1557
1558 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1559 r2 if it fits. */
cd34bbe8
NF		 1560#undef TARGET_FUNCTION_ARG
1561#define TARGET_FUNCTION_ARG m32c_function_arg
1562static rtx
38b2d076 1563m32c_function_arg (CUMULATIVE_ARGS * ca,
cd34bbe8 1564 enum machine_mode mode, const_tree type, bool named)
38b2d076
DD		 1565{
1566 /* Can return a reg, parallel, or 0 for stack */
1567 rtx rv = NULL_RTX;
1568#if DEBUG0
1569 fprintf (stderr, "func_arg %d (%s, %d)\n",
1570 ca->parm_num, mode_name[mode], named);
1571 debug_tree (type);
1572#endif
1573
1574 if (mode == VOIDmode)
1575 return GEN_INT (0);
1576
1577 if (ca->force_mem || !named)
1578 {
1579#if DEBUG0
1580 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1581 named);
1582#endif
1583 return NULL_RTX;
1584 }
1585
1586 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1587 return NULL_RTX;
1588
9d746d5e
DD		 1589 if (type && AGGREGATE_TYPE_P (type))
1590 return NULL_RTX;
1591
38b2d076
DD		 1592 switch (ca->parm_num)
1593 {
1594 case 1:
1595 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1596 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1597 break;
1598
1599 case 2:
1600 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1601 rv = gen_rtx_REG (mode, R2_REGNO);
1602 break;
1603 }
1604
1605#if DEBUG0
1606 debug_rtx (rv);
1607#endif
1608 return rv;
1609}
1610
1611#undef TARGET_PASS_BY_REFERENCE
1612#define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1613static bool
1614m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1615 enum machine_mode mode ATTRIBUTE_UNUSED,
586de218 1616 const_tree type ATTRIBUTE_UNUSED,
38b2d076
DD		 1617 bool named ATTRIBUTE_UNUSED)
1618{
1619 return 0;
1620}
1621
1622/* Implements INIT_CUMULATIVE_ARGS. */
1623void
1624m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
9d746d5e 1625 tree fntype,
38b2d076 1626 rtx libname ATTRIBUTE_UNUSED,
9d746d5e 1627 tree fndecl,
38b2d076
DD		 1628 int n_named_args ATTRIBUTE_UNUSED)
1629{
9d746d5e
DD		 1630 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1631 ca->force_mem = 1;
1632 else
1633 ca->force_mem = 0;
38b2d076
DD		 1634 ca->parm_num = 1;
1635}
1636
cd34bbe8
NF		 1637/* Implements TARGET_FUNCTION_ARG_ADVANCE. force_mem is set for
1638 functions returning structures, so we always reset that. Otherwise,
1639 we only need to know the sequence number of the argument to know what
1640 to do with it. */
1641#undef TARGET_FUNCTION_ARG_ADVANCE
1642#define TARGET_FUNCTION_ARG_ADVANCE m32c_function_arg_advance
1643static void
38b2d076
DD		 1644m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1645 enum machine_mode mode ATTRIBUTE_UNUSED,
cd34bbe8
NF		 1646 const_tree type ATTRIBUTE_UNUSED,
1647 bool named ATTRIBUTE_UNUSED)
38b2d076
DD		 1648{
1649 if (ca->force_mem)
1650 ca->force_mem = 0;
9d746d5e
DD		 1651 else
1652 ca->parm_num++;
38b2d076
DD		 1653}
1654
c2ed6cf8
NF		 1655/* Implements TARGET_FUNCTION_ARG_BOUNDARY. */
1656#undef TARGET_FUNCTION_ARG_BOUNDARY
1657#define TARGET_FUNCTION_ARG_BOUNDARY m32c_function_arg_boundary
1658static unsigned int
1659m32c_function_arg_boundary (enum machine_mode mode ATTRIBUTE_UNUSED,
1660 const_tree type ATTRIBUTE_UNUSED)
1661{
1662 return (TARGET_A16 ? 8 : 16);
1663}
1664
38b2d076
DD		 1665/* Implements FUNCTION_ARG_REGNO_P. */
1666int
1667m32c_function_arg_regno_p (int r)
1668{
1669 if (TARGET_A24)
1670 return (r == R0_REGNO);
1671 return (r == R1_REGNO || r == R2_REGNO);
1672}
1673
e9555b13 1674/* HImode and PSImode are the two "native" modes as far as GCC is
85f65093 1675 concerned, but the chips also support a 32-bit mode which is used
e9555b13
DD		 1676 for some opcodes in R8C/M16C and for reset vectors and such. */
1677#undef TARGET_VALID_POINTER_MODE
1678#define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
23fed240 1679static bool
e9555b13
DD		 1680m32c_valid_pointer_mode (enum machine_mode mode)
1681{
e9555b13
DD		 1682 if (mode == HImode
1683 || mode == PSImode
1684 || mode == SImode
1685 )
1686 return 1;
1687 return 0;
1688}
1689
38b2d076
DD		 1690/* How Scalar Function Values Are Returned */
1691
2a31793e 1692/* Implements TARGET_LIBCALL_VALUE. Most values are returned in $r0, or some
38b2d076
DD		 1693 combination of registers starting there (r2r0 for longs, r3r1r2r0
1694 for long long, r3r2r1r0 for doubles), except that that ABI
1695 currently doesn't work because it ends up using all available
1696 general registers and gcc often can't compile it. So, instead, we
1697 return anything bigger than 16 bits in "mem0" (effectively, a
1698 memory location). */
2a31793e
AS		 1699
1700#undef TARGET_LIBCALL_VALUE
1701#define TARGET_LIBCALL_VALUE m32c_libcall_value
1702
1703static rtx
1704m32c_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
38b2d076
DD		 1705{
1706 /* return reg or parallel */
1707#if 0
1708 /* FIXME: GCC has difficulty returning large values in registers,
1709 because that ties up most of the general registers and gives the
1710 register allocator little to work with. Until we can resolve
1711 this, large values are returned in memory. */
1712 if (mode == DFmode)
1713 {
1714 rtx rv;
1715
1716 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1717 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1718 gen_rtx_REG (HImode,
1719 R0_REGNO),
1720 GEN_INT (0));
1721 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1722 gen_rtx_REG (HImode,
1723 R1_REGNO),
1724 GEN_INT (2));
1725 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1726 gen_rtx_REG (HImode,
1727 R2_REGNO),
1728 GEN_INT (4));
1729 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1730 gen_rtx_REG (HImode,
1731 R3_REGNO),
1732 GEN_INT (6));
1733 return rv;
1734 }
1735
1736 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1737 {
1738 rtx rv;
1739
1740 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1741 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1742 gen_rtx_REG (mode,
1743 R0_REGNO),
1744 GEN_INT (0));
1745 return rv;
1746 }
1747#endif
1748
1749 if (GET_MODE_SIZE (mode) > 2)
1750 return gen_rtx_REG (mode, MEM0_REGNO);
1751 return gen_rtx_REG (mode, R0_REGNO);
1752}
1753
2a31793e 1754/* Implements TARGET_FUNCTION_VALUE. Functions and libcalls have the same
38b2d076 1755 conventions. */
2a31793e
AS		 1756
1757#undef TARGET_FUNCTION_VALUE
1758#define TARGET_FUNCTION_VALUE m32c_function_value
1759
1760static rtx
1761m32c_function_value (const_tree valtype,
1762 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1763 bool outgoing ATTRIBUTE_UNUSED)
38b2d076
DD		 1764{
1765 /* return reg or parallel */
586de218 1766 const enum machine_mode mode = TYPE_MODE (valtype);
2a31793e
AS		 1767 return m32c_libcall_value (mode, NULL_RTX);
1768}
1769
f28f2337
AS		 1770/* Implements TARGET_FUNCTION_VALUE_REGNO_P. */
1771
1772#undef TARGET_FUNCTION_VALUE_REGNO_P
1773#define TARGET_FUNCTION_VALUE_REGNO_P m32c_function_value_regno_p
2a31793e 1774
f28f2337 1775static bool
2a31793e
AS		 1776m32c_function_value_regno_p (const unsigned int regno)
1777{
1778 return (regno == R0_REGNO || regno == MEM0_REGNO);
38b2d076
DD		 1779}
1780
1781/* How Large Values Are Returned */
1782
1783/* We return structures by pushing the address on the stack, even if
1784 we use registers for the first few "real" arguments. */
1785#undef TARGET_STRUCT_VALUE_RTX
1786#define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1787static rtx
1788m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1789 int incoming ATTRIBUTE_UNUSED)
1790{
1791 return 0;
1792}
1793
1794/* Function Entry and Exit */
1795
1796/* Implements EPILOGUE_USES. Interrupts restore all registers. */
1797int
1798m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1799{
1800 if (cfun->machine->is_interrupt)
1801 return 1;
1802 return 0;
1803}
1804
1805/* Implementing the Varargs Macros */
1806
1807#undef TARGET_STRICT_ARGUMENT_NAMING
1808#define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1809static bool
1810m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1811{
1812 return 1;
1813}
1814
1815/* Trampolines for Nested Functions */
1816
1817/*
1818 m16c:
1819 1 0000 75C43412 mov.w #0x1234,a0
1820 2 0004 FC000000 jmp.a label
1821
1822 m32c:
1823 1 0000 BC563412 mov.l:s #0x123456,a0
1824 2 0004 CC000000 jmp.a label
1825*/
1826
1827/* Implements TRAMPOLINE_SIZE. */
1828int
1829m32c_trampoline_size (void)
1830{
1831 /* Allocate extra space so we can avoid the messy shifts when we
1832 initialize the trampoline; we just write past the end of the
1833 opcode. */
1834 return TARGET_A16 ? 8 : 10;
1835}
1836
1837/* Implements TRAMPOLINE_ALIGNMENT. */
1838int
1839m32c_trampoline_alignment (void)
1840{
1841 return 2;
1842}
1843
229fbccb
RH		 1844/* Implements TARGET_TRAMPOLINE_INIT. */
1845
1846#undef TARGET_TRAMPOLINE_INIT
1847#define TARGET_TRAMPOLINE_INIT m32c_trampoline_init
1848static void
1849m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
38b2d076 1850{
229fbccb
RH		 1851 rtx function = XEXP (DECL_RTL (fndecl), 0);
1852
1853#define A0(m,i) adjust_address (m_tramp, m, i)
38b2d076
DD		 1854 if (TARGET_A16)
1855 {
1856 /* Note: we subtract a "word" because the moves want signed
1857 constants, not unsigned constants. */
1858 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1859 emit_move_insn (A0 (HImode, 2), chainval);
1860 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
85f65093
KH		 1861 /* We use 16-bit addresses here, but store the zero to turn it
1862 into a 24-bit offset. */
38b2d076
DD		 1863 emit_move_insn (A0 (HImode, 5), function);
1864 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1865 }
1866 else
1867 {
1868 /* Note that the PSI moves actually write 4 bytes. Make sure we
1869 write stuff out in the right order, and leave room for the
1870 extra byte at the end. */
1871 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1872 emit_move_insn (A0 (PSImode, 1), chainval);
1873 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1874 emit_move_insn (A0 (PSImode, 5), function);
1875 }
1876#undef A0
1877}
1878
07127a0a
DD		 1879/* Implicit Calls to Library Routines */
1880
1881#undef TARGET_INIT_LIBFUNCS
1882#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1883static void
1884m32c_init_libfuncs (void)
1885{
f90b7a5a
PB		 1886 /* We do this because the M32C has an HImode operand, but the
1887 M16C has an 8-bit operand. Since gcc looks at the match data
1888 and not the expanded rtl, we have to reset the optab so that
1889 the right modes are found. */
07127a0a
DD		 1890 if (TARGET_A24)
1891 {
947131ba
RS		 1892 set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
1893 set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
1894 set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstorepsi4_24);
07127a0a
DD		 1895 }
1896}
1897
38b2d076
DD		 1898/* Addressing Modes */
1899
c6c3dba9
PB		 1900/* The r8c/m32c family supports a wide range of non-orthogonal
1901 addressing modes, including the ability to double-indirect on *some*
1902 of them. Not all insns support all modes, either, but we rely on
1903 predicates and constraints to deal with that. */
1904#undef TARGET_LEGITIMATE_ADDRESS_P
1905#define TARGET_LEGITIMATE_ADDRESS_P m32c_legitimate_address_p
1906bool
1907m32c_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
38b2d076
DD		 1908{
1909 int mode_adjust;
1910 if (CONSTANT_P (x))
1911 return 1;
1912
5fd5d713
DD		 1913 if (TARGET_A16 && GET_MODE (x) != HImode && GET_MODE (x) != SImode)
1914 return 0;
1915 if (TARGET_A24 && GET_MODE (x) != PSImode)
1916 return 0;
1917
38b2d076
DD		 1918 /* Wide references to memory will be split after reload, so we must
1919 ensure that all parts of such splits remain legitimate
1920 addresses. */
1921 mode_adjust = GET_MODE_SIZE (mode) - 1;
1922
1923 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1924 if (GET_CODE (x) == PRE_DEC
1925 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1926 {
1927 return (GET_CODE (XEXP (x, 0)) == REG
1928 && REGNO (XEXP (x, 0)) == SP_REGNO);
1929 }
1930
1931#if 0
1932 /* This is the double indirection detection, but it currently
1933 doesn't work as cleanly as this code implies, so until we've had
1934 a chance to debug it, leave it disabled. */
1935 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1936 {
1937#if DEBUG_DOUBLE
1938 fprintf (stderr, "double indirect\n");
1939#endif
1940 x = XEXP (x, 0);
1941 }
1942#endif
1943
1944 encode_pattern (x);
1945 if (RTX_IS ("r"))
1946 {
1947 /* Most indexable registers can be used without displacements,
1948 although some of them will be emitted with an explicit zero
1949 to please the assembler. */
1950 switch (REGNO (patternr[0]))
1951 {
38b2d076
DD		 1952 case A1_REGNO:
1953 case SB_REGNO:
1954 case FB_REGNO:
1955 case SP_REGNO:
5fd5d713
DD		 1956 if (TARGET_A16 && GET_MODE (x) == SImode)
1957 return 0;
1958 case A0_REGNO:
38b2d076
DD		 1959 return 1;
1960
1961 default:
1962 if (IS_PSEUDO (patternr[0], strict))
1963 return 1;
1964 return 0;
1965 }
1966 }
5fd5d713
DD		 1967
1968 if (TARGET_A16 && GET_MODE (x) == SImode)
1969 return 0;
1970
38b2d076
DD		 1971 if (RTX_IS ("+ri"))
1972 {
1973 /* This is more interesting, because different base registers
1974 allow for different displacements - both range and signedness
1975 - and it differs from chip series to chip series too. */
1976 int rn = REGNO (patternr[1]);
1977 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1978 switch (rn)
1979 {
1980 case A0_REGNO:
1981 case A1_REGNO:
1982 case SB_REGNO:
1983 /* The syntax only allows positive offsets, but when the
1984 offsets span the entire memory range, we can simulate
1985 negative offsets by wrapping. */
1986 if (TARGET_A16)
1987 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1988 if (rn == SB_REGNO)
1989 return (offs >= 0 && offs <= 65535 - mode_adjust);
1990 /* A0 or A1 */
1991 return (offs >= -16777216 && offs <= 16777215);
1992
1993 case FB_REGNO:
1994 if (TARGET_A16)
1995 return (offs >= -128 && offs <= 127 - mode_adjust);
1996 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1997
1998 case SP_REGNO:
1999 return (offs >= -128 && offs <= 127 - mode_adjust);
2000
2001 default:
2002 if (IS_PSEUDO (patternr[1], strict))
2003 return 1;
2004 return 0;
2005 }
2006 }
2007 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
2008 {
2009 rtx reg = patternr[1];
2010
2011 /* We don't know where the symbol is, so only allow base
2012 registers which support displacements spanning the whole
2013 address range. */
2014 switch (REGNO (reg))
2015 {
2016 case A0_REGNO:
2017 case A1_REGNO:
2018 /* $sb needs a secondary reload, but since it's involved in
2019 memory address reloads too, we don't deal with it very
2020 well. */
2021 /* case SB_REGNO: */
2022 return 1;
2023 default:
2024 if (IS_PSEUDO (reg, strict))
2025 return 1;
2026 return 0;
2027 }
2028 }
2029 return 0;
2030}
2031
2032/* Implements REG_OK_FOR_BASE_P. */
2033int
2034m32c_reg_ok_for_base_p (rtx x, int strict)
2035{
2036 if (GET_CODE (x) != REG)
2037 return 0;
2038 switch (REGNO (x))
2039 {
2040 case A0_REGNO:
2041 case A1_REGNO:
2042 case SB_REGNO:
2043 case FB_REGNO:
2044 case SP_REGNO:
2045 return 1;
2046 default:
2047 if (IS_PSEUDO (x, strict))
2048 return 1;
2049 return 0;
2050 }
2051}
2052
04aff2c0 2053/* We have three choices for choosing fb->aN offsets. If we choose -128,
85f65093 2054 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
04aff2c0
DD		 2055 like this:
2056 EB 4B FF mova -128[$fb],$a0
2057 D8 0C FF FF mov.w:Q #0,-1[$a0]
2058
85f65093 2059 Alternately, we subtract the frame size, and hopefully use 8-bit aN
04aff2c0
DD		 2060 displacements:
2061 7B F4 stc $fb,$a0
2062 77 54 00 01 sub #256,$a0
2063 D8 08 01 mov.w:Q #0,1[$a0]
2064
2065 If we don't offset (i.e. offset by zero), we end up with:
2066 7B F4 stc $fb,$a0
2067 D8 0C 00 FF mov.w:Q #0,-256[$a0]
2068
2069 We have to subtract *something* so that we have a PLUS rtx to mark
2070 that we've done this reload. The -128 offset will never result in
85f65093 2071 an 8-bit aN offset, and the payoff for the second case is five
04aff2c0
DD		 2072 loads *if* those loads are within 256 bytes of the other end of the
2073 frame, so the third case seems best. Note that we subtract the
2074 zero, but detect that in the addhi3 pattern. */
2075
ea471af0
JM		 2076#define BIG_FB_ADJ 0
2077
38b2d076
DD		 2078/* Implements LEGITIMIZE_ADDRESS. The only address we really have to
2079 worry about is frame base offsets, as $fb has a limited
2080 displacement range. We deal with this by attempting to reload $fb
2081 itself into an address register; that seems to result in the best
2082 code. */
506d7b68
PB		 2083#undef TARGET_LEGITIMIZE_ADDRESS
2084#define TARGET_LEGITIMIZE_ADDRESS m32c_legitimize_address
2085static rtx
2086m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2087 enum machine_mode mode)
38b2d076
DD		 2088{
2089#if DEBUG0
2090 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
506d7b68 2091 debug_rtx (x);
38b2d076
DD		 2092 fprintf (stderr, "\n");
2093#endif
2094
506d7b68
PB		 2095 if (GET_CODE (x) == PLUS
2096 && GET_CODE (XEXP (x, 0)) == REG
2097 && REGNO (XEXP (x, 0)) == FB_REGNO
2098 && GET_CODE (XEXP (x, 1)) == CONST_INT
2099 && (INTVAL (XEXP (x, 1)) < -128
2100 || INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
38b2d076
DD		 2101 {
2102 /* reload FB to A_REGS */
38b2d076 2103 rtx temp = gen_reg_rtx (Pmode);
506d7b68
PB		 2104 x = copy_rtx (x);
2105 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (x, 0)));
2106 XEXP (x, 0) = temp;
38b2d076
DD		 2107 }
2108
506d7b68 2109 return x;
38b2d076
DD		 2110}
2111
2112/* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
2113int
2114m32c_legitimize_reload_address (rtx * x,
2115 enum machine_mode mode,
2116 int opnum,
2117 int type, int ind_levels ATTRIBUTE_UNUSED)
2118{
2119#if DEBUG0
2120 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
2121 mode_name[mode]);
2122 debug_rtx (*x);
2123#endif
2124
2125 /* At one point, this function tried to get $fb copied to an address
2126 register, which in theory would maximize sharing, but gcc was
2127 *also* still trying to reload the whole address, and we'd run out
2128 of address registers. So we let gcc do the naive (but safe)
2129 reload instead, when the above function doesn't handle it for
04aff2c0
DD		 2130 us.
2131
2132 The code below is a second attempt at the above. */
2133
2134 if (GET_CODE (*x) == PLUS
2135 && GET_CODE (XEXP (*x, 0)) == REG
2136 && REGNO (XEXP (*x, 0)) == FB_REGNO
2137 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2138 && (INTVAL (XEXP (*x, 1)) < -128
2139 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2140 {
2141 rtx sum;
2142 int offset = INTVAL (XEXP (*x, 1));
2143 int adjustment = -BIG_FB_ADJ;
2144
2145 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2146 GEN_INT (adjustment));
2147 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2148 if (type == RELOAD_OTHER)
2149 type = RELOAD_FOR_OTHER_ADDRESS;
2150 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2151 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
444d6efe 2152 (enum reload_type) type);
04aff2c0
DD		 2153 return 1;
2154 }
2155
2156 if (GET_CODE (*x) == PLUS
2157 && GET_CODE (XEXP (*x, 0)) == PLUS
2158 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2159 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2160 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2161 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2162 )
2163 {
2164 if (type == RELOAD_OTHER)
2165 type = RELOAD_FOR_OTHER_ADDRESS;
2166 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2167 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
444d6efe 2168 (enum reload_type) type);
04aff2c0
DD		 2169 return 1;
2170 }
38b2d076
DD		 2171
2172 return 0;
2173}
2174
38b2d076
DD		 2175/* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2176 so we can allow anything. */
2177int
2178m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2179{
2180 return 1;
2181}
2182
2183
5fd5d713
DD		 2184/* Return the appropriate mode for a named address pointer. */
2185#undef TARGET_ADDR_SPACE_POINTER_MODE
2186#define TARGET_ADDR_SPACE_POINTER_MODE m32c_addr_space_pointer_mode
2187static enum machine_mode
2188m32c_addr_space_pointer_mode (addr_space_t addrspace)
2189{
2190 switch (addrspace)
2191 {
2192 case ADDR_SPACE_GENERIC:
2193 return TARGET_A24 ? PSImode : HImode;
2194 case ADDR_SPACE_FAR:
2195 return SImode;
2196 default:
2197 gcc_unreachable ();
2198 }
2199}
2200
2201/* Return the appropriate mode for a named address address. */
2202#undef TARGET_ADDR_SPACE_ADDRESS_MODE
2203#define TARGET_ADDR_SPACE_ADDRESS_MODE m32c_addr_space_address_mode
2204static enum machine_mode
2205m32c_addr_space_address_mode (addr_space_t addrspace)
2206{
2207 switch (addrspace)
2208 {
2209 case ADDR_SPACE_GENERIC:
2210 return TARGET_A24 ? PSImode : HImode;
2211 case ADDR_SPACE_FAR:
2212 return SImode;
2213 default:
2214 gcc_unreachable ();
2215 }
2216}
2217
2218/* Like m32c_legitimate_address_p, except with named addresses. */
2219#undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
2220#define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P \
2221 m32c_addr_space_legitimate_address_p
2222static bool
2223m32c_addr_space_legitimate_address_p (enum machine_mode mode, rtx x,
2224 bool strict, addr_space_t as)
2225{
2226 if (as == ADDR_SPACE_FAR)
2227 {
2228 if (TARGET_A24)
2229 return 0;
2230 encode_pattern (x);
2231 if (RTX_IS ("r"))
2232 {
2233 if (GET_MODE (x) != SImode)
2234 return 0;
2235 switch (REGNO (patternr[0]))
2236 {
2237 case A0_REGNO:
2238 return 1;
2239
2240 default:
2241 if (IS_PSEUDO (patternr[0], strict))
2242 return 1;
2243 return 0;
2244 }
2245 }
2246 if (RTX_IS ("+^Sri"))
2247 {
2248 int rn = REGNO (patternr[3]);
2249 HOST_WIDE_INT offs = INTVAL (patternr[4]);
2250 if (GET_MODE (patternr[3]) != HImode)
2251 return 0;
2252 switch (rn)
2253 {
2254 case A0_REGNO:
2255 return (offs >= 0 && offs <= 0xfffff);
2256
2257 default:
2258 if (IS_PSEUDO (patternr[3], strict))
2259 return 1;
2260 return 0;
2261 }
2262 }
2263 if (RTX_IS ("+^Srs"))
2264 {
2265 int rn = REGNO (patternr[3]);
2266 if (GET_MODE (patternr[3]) != HImode)
2267 return 0;
2268 switch (rn)
2269 {
2270 case A0_REGNO:
2271 return 1;
2272
2273 default:
2274 if (IS_PSEUDO (patternr[3], strict))
2275 return 1;
2276 return 0;
2277 }
2278 }
2279 if (RTX_IS ("+^S+ris"))
2280 {
2281 int rn = REGNO (patternr[4]);
2282 if (GET_MODE (patternr[4]) != HImode)
2283 return 0;
2284 switch (rn)
2285 {
2286 case A0_REGNO:
2287 return 1;
2288
2289 default:
2290 if (IS_PSEUDO (patternr[4], strict))
2291 return 1;
2292 return 0;
2293 }
2294 }
2295 if (RTX_IS ("s"))
2296 {
2297 return 1;
2298 }
2299 return 0;
2300 }
2301
2302 else if (as != ADDR_SPACE_GENERIC)
2303 gcc_unreachable ();
2304
2305 return m32c_legitimate_address_p (mode, x, strict);
2306}
2307
2308/* Like m32c_legitimate_address, except with named address support. */
2309#undef TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS
2310#define TARGET_ADDR_SPACE_LEGITIMIZE_ADDRESS m32c_addr_space_legitimize_address
2311static rtx
2312m32c_addr_space_legitimize_address (rtx x, rtx oldx, enum machine_mode mode,
2313 addr_space_t as)
2314{
2315 if (as != ADDR_SPACE_GENERIC)
2316 {
2317#if DEBUG0
2318 fprintf (stderr, "\033[36mm32c_addr_space_legitimize_address for mode %s\033[0m\n", mode_name[mode]);
2319 debug_rtx (x);
2320 fprintf (stderr, "\n");
2321#endif
2322
2323 if (GET_CODE (x) != REG)
2324 {
2325 x = force_reg (SImode, x);
2326 }
2327 return x;
2328 }
2329
2330 return m32c_legitimize_address (x, oldx, mode);
2331}
2332
2333/* Determine if one named address space is a subset of another. */
2334#undef TARGET_ADDR_SPACE_SUBSET_P
2335#define TARGET_ADDR_SPACE_SUBSET_P m32c_addr_space_subset_p
2336static bool
2337m32c_addr_space_subset_p (addr_space_t subset, addr_space_t superset)
2338{
2339 gcc_assert (subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_FAR);
2340 gcc_assert (superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_FAR);
2341
2342 if (subset == superset)
2343 return true;
2344
2345 else
2346 return (subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_FAR);
2347}
2348
2349#undef TARGET_ADDR_SPACE_CONVERT
2350#define TARGET_ADDR_SPACE_CONVERT m32c_addr_space_convert
2351/* Convert from one address space to another. */
2352static rtx
2353m32c_addr_space_convert (rtx op, tree from_type, tree to_type)
2354{
2355 addr_space_t from_as = TYPE_ADDR_SPACE (TREE_TYPE (from_type));
2356 addr_space_t to_as = TYPE_ADDR_SPACE (TREE_TYPE (to_type));
2357 rtx result;
2358
2359 gcc_assert (from_as == ADDR_SPACE_GENERIC || from_as == ADDR_SPACE_FAR);
2360 gcc_assert (to_as == ADDR_SPACE_GENERIC || to_as == ADDR_SPACE_FAR);
2361
2362 if (to_as == ADDR_SPACE_GENERIC && from_as == ADDR_SPACE_FAR)
2363 {
2364 /* This is unpredictable, as we're truncating off usable address
2365 bits. */
2366
2367 result = gen_reg_rtx (HImode);
2368 emit_move_insn (result, simplify_subreg (HImode, op, SImode, 0));
2369 return result;
2370 }
2371 else if (to_as == ADDR_SPACE_FAR && from_as == ADDR_SPACE_GENERIC)
2372 {
2373 /* This always works. */
2374 result = gen_reg_rtx (SImode);
2375 emit_insn (gen_zero_extendhisi2 (result, op));
2376 return result;
2377 }
2378 else
2379 gcc_unreachable ();
2380}
2381
38b2d076
DD		 2382/* Condition Code Status */
2383
2384#undef TARGET_FIXED_CONDITION_CODE_REGS
2385#define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2386static bool
2387m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2388{
2389 *p1 = FLG_REGNO;
2390 *p2 = INVALID_REGNUM;
2391 return true;
2392}
2393
2394/* Describing Relative Costs of Operations */
2395
0e607518 2396/* Implements TARGET_REGISTER_MOVE_COST. We make impossible moves
38b2d076
DD		 2397 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2398 no opcodes to do that). We also discourage use of mem* registers
2399 since they're really memory. */
0e607518
AS		 2400
2401#undef TARGET_REGISTER_MOVE_COST
2402#define TARGET_REGISTER_MOVE_COST m32c_register_move_cost
2403
2404static int
2405m32c_register_move_cost (enum machine_mode mode, reg_class_t from,
2406 reg_class_t to)
38b2d076
DD		 2407{
2408 int cost = COSTS_N_INSNS (3);
0e607518
AS		 2409 HARD_REG_SET cc;
2410
2411/* FIXME: pick real values, but not 2 for now. */
2412 COPY_HARD_REG_SET (cc, reg_class_contents[(int) from]);
2413 IOR_HARD_REG_SET (cc, reg_class_contents[(int) to]);
2414
2415 if (mode == QImode
2416 && hard_reg_set_intersect_p (cc, reg_class_contents[R23_REGS]))
38b2d076 2417 {
0e607518 2418 if (hard_reg_set_subset_p (cc, reg_class_contents[R23_REGS]))
38b2d076
DD		 2419 cost = COSTS_N_INSNS (1000);
2420 else
2421 cost = COSTS_N_INSNS (80);
2422 }
2423
2424 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2425 cost = COSTS_N_INSNS (1000);
2426
0e607518 2427 if (reg_classes_intersect_p (from, CR_REGS))
38b2d076
DD		 2428 cost += COSTS_N_INSNS (5);
2429
0e607518 2430 if (reg_classes_intersect_p (to, CR_REGS))
38b2d076
DD		 2431 cost += COSTS_N_INSNS (5);
2432
2433 if (from == MEM_REGS || to == MEM_REGS)
2434 cost += COSTS_N_INSNS (50);
0e607518
AS		 2435 else if (reg_classes_intersect_p (from, MEM_REGS)
2436 || reg_classes_intersect_p (to, MEM_REGS))
38b2d076
DD		 2437 cost += COSTS_N_INSNS (10);
2438
2439#if DEBUG0
2440 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
0e607518
AS		 2441 mode_name[mode], class_names[(int) from], class_names[(int) to],
2442 cost);
38b2d076
DD		 2443#endif
2444 return cost;
2445}
2446
0e607518
AS		 2447/* Implements TARGET_MEMORY_MOVE_COST. */
2448
2449#undef TARGET_MEMORY_MOVE_COST
2450#define TARGET_MEMORY_MOVE_COST m32c_memory_move_cost
2451
2452static int
38b2d076 2453m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
0e607518
AS		 2454 reg_class_t rclass ATTRIBUTE_UNUSED,
2455 bool in ATTRIBUTE_UNUSED)
38b2d076
DD		 2456{
2457 /* FIXME: pick real values. */
2458 return COSTS_N_INSNS (10);
2459}
2460
07127a0a
DD		 2461/* Here we try to describe when we use multiple opcodes for one RTX so
2462 that gcc knows when to use them. */
2463#undef TARGET_RTX_COSTS
2464#define TARGET_RTX_COSTS m32c_rtx_costs
2465static bool
f40751dd
JH		 2466m32c_rtx_costs (rtx x, int code, int outer_code, int *total,
2467 bool speed ATTRIBUTE_UNUSED)
07127a0a
DD		 2468{
2469 switch (code)
2470 {
2471 case REG:
2472 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2473 *total += COSTS_N_INSNS (500);
2474 else
2475 *total += COSTS_N_INSNS (1);
2476 return true;
2477
2478 case ASHIFT:
2479 case LSHIFTRT:
2480 case ASHIFTRT:
2481 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2482 {
2483 /* mov.b r1l, r1h */
2484 *total += COSTS_N_INSNS (1);
2485 return true;
2486 }
2487 if (INTVAL (XEXP (x, 1)) > 8
2488 || INTVAL (XEXP (x, 1)) < -8)
2489 {
2490 /* mov.b #N, r1l */
2491 /* mov.b r1l, r1h */
2492 *total += COSTS_N_INSNS (2);
2493 return true;
2494 }
2495 return true;
2496
2497 case LE:
2498 case LEU:
2499 case LT:
2500 case LTU:
2501 case GT:
2502 case GTU:
2503 case GE:
2504 case GEU:
2505 case NE:
2506 case EQ:
2507 if (outer_code == SET)
2508 {
2509 *total += COSTS_N_INSNS (2);
2510 return true;
2511 }
2512 break;
2513
2514 case ZERO_EXTRACT:
2515 {
2516 rtx dest = XEXP (x, 0);
2517 rtx addr = XEXP (dest, 0);
2518 switch (GET_CODE (addr))
2519 {
2520 case CONST_INT:
2521 *total += COSTS_N_INSNS (1);
2522 break;
2523 case SYMBOL_REF:
2524 *total += COSTS_N_INSNS (3);
2525 break;
2526 default:
2527 *total += COSTS_N_INSNS (2);
2528 break;
2529 }
2530 return true;
2531 }
2532 break;
2533
2534 default:
2535 /* Reasonable default. */
2536 if (TARGET_A16 && GET_MODE(x) == SImode)
2537 *total += COSTS_N_INSNS (2);
2538 break;
2539 }
2540 return false;
2541}
2542
2543#undef TARGET_ADDRESS_COST
2544#define TARGET_ADDRESS_COST m32c_address_cost
2545static int
f40751dd 2546m32c_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
07127a0a 2547{
80b093df 2548 int i;
07127a0a
DD		 2549 /* fprintf(stderr, "\naddress_cost\n");
2550 debug_rtx(addr);*/
2551 switch (GET_CODE (addr))
2552 {
2553 case CONST_INT:
80b093df
DD		 2554 i = INTVAL (addr);
2555 if (i == 0)
2556 return COSTS_N_INSNS(1);
2557 if (0 < i && i <= 255)
2558 return COSTS_N_INSNS(2);
2559 if (0 < i && i <= 65535)
2560 return COSTS_N_INSNS(3);
2561 return COSTS_N_INSNS(4);
07127a0a 2562 case SYMBOL_REF:
80b093df 2563 return COSTS_N_INSNS(4);
07127a0a 2564 case REG:
80b093df
DD		 2565 return COSTS_N_INSNS(1);
2566 case PLUS:
2567 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2568 {
2569 i = INTVAL (XEXP (addr, 1));
2570 if (i == 0)
2571 return COSTS_N_INSNS(1);
2572 if (0 < i && i <= 255)
2573 return COSTS_N_INSNS(2);
2574 if (0 < i && i <= 65535)
2575 return COSTS_N_INSNS(3);
2576 }
2577 return COSTS_N_INSNS(4);
07127a0a
DD		 2578 default:
2579 return 0;
2580 }
2581}
2582
38b2d076
DD		 2583/* Defining the Output Assembler Language */
2584
2585/* The Overall Framework of an Assembler File */
2586
2587#undef TARGET_HAVE_NAMED_SECTIONS
2588#define TARGET_HAVE_NAMED_SECTIONS true
2589
2590/* Output of Data */
2591
2592/* We may have 24 bit sizes, which is the native address size.
2593 Currently unused, but provided for completeness. */
2594#undef TARGET_ASM_INTEGER
2595#define TARGET_ASM_INTEGER m32c_asm_integer
2596static bool
2597m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2598{
2599 switch (size)
2600 {
2601 case 3:
2602 fprintf (asm_out_file, "\t.3byte\t");
2603 output_addr_const (asm_out_file, x);
2604 fputc ('\n', asm_out_file);
2605 return true;
e9555b13
DD		 2606 case 4:
2607 if (GET_CODE (x) == SYMBOL_REF)
2608 {
2609 fprintf (asm_out_file, "\t.long\t");
2610 output_addr_const (asm_out_file, x);
2611 fputc ('\n', asm_out_file);
2612 return true;
2613 }
2614 break;
38b2d076
DD		 2615 }
2616 return default_assemble_integer (x, size, aligned_p);
2617}
2618
2619/* Output of Assembler Instructions */
2620
a4174ebf 2621/* We use a lookup table because the addressing modes are non-orthogonal. */
38b2d076
DD		 2622
2623static struct
2624{
2625 char code;
2626 char const *pattern;
2627 char const *format;
2628}
2629const conversions[] = {
2630 { 0, "r", "0" },
2631
2632 { 0, "mr", "z[1]" },
2633 { 0, "m+ri", "3[2]" },
2634 { 0, "m+rs", "3[2]" },
5fd5d713
DD		 2635 { 0, "m+^Zrs", "5[4]" },
2636 { 0, "m+^Zri", "5[4]" },
2637 { 0, "m+^Z+ris", "7+6[5]" },
2638 { 0, "m+^Srs", "5[4]" },
2639 { 0, "m+^Sri", "5[4]" },
2640 { 0, "m+^S+ris", "7+6[5]" },
38b2d076
DD		 2641 { 0, "m+r+si", "4+5[2]" },
2642 { 0, "ms", "1" },
2643 { 0, "mi", "1" },
2644 { 0, "m+si", "2+3" },
2645
2646 { 0, "mmr", "[z[2]]" },
2647 { 0, "mm+ri", "[4[3]]" },
2648 { 0, "mm+rs", "[4[3]]" },
2649 { 0, "mm+r+si", "[5+6[3]]" },
2650 { 0, "mms", "[[2]]" },
2651 { 0, "mmi", "[[2]]" },
2652 { 0, "mm+si", "[4[3]]" },
2653
2654 { 0, "i", "#0" },
2655 { 0, "s", "#0" },
2656 { 0, "+si", "#1+2" },
2657 { 0, "l", "#0" },
2658
2659 { 'l', "l", "0" },
2660 { 'd', "i", "0" },
2661 { 'd', "s", "0" },
2662 { 'd', "+si", "1+2" },
2663 { 'D', "i", "0" },
2664 { 'D', "s", "0" },
2665 { 'D', "+si", "1+2" },
2666 { 'x', "i", "#0" },
2667 { 'X', "i", "#0" },
2668 { 'm', "i", "#0" },
2669 { 'b', "i", "#0" },
07127a0a 2670 { 'B', "i", "0" },
38b2d076
DD		 2671 { 'p', "i", "0" },
2672
2673 { 0, 0, 0 }
2674};
2675
2676/* This is in order according to the bitfield that pushm/popm use. */
2677static char const *pushm_regs[] = {
2678 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2679};
2680
2681/* Implements PRINT_OPERAND. */
2682void
2683m32c_print_operand (FILE * file, rtx x, int code)
2684{
2685 int i, j, b;
2686 const char *comma;
2687 HOST_WIDE_INT ival;
2688 int unsigned_const = 0;
ff485e71 2689 int force_sign;
38b2d076
DD		 2690
2691 /* Multiplies; constants are converted to sign-extended format but
2692 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2693 need. */
2694 if (code == 'u')
2695 {
2696 unsigned_const = 2;
2697 code = 0;
2698 }
2699 if (code == 'U')
2700 {
2701 unsigned_const = 1;
2702 code = 0;
2703 }
2704 /* This one is only for debugging; you can put it in a pattern to
2705 force this error. */
2706 if (code == '!')
2707 {
2708 fprintf (stderr, "dj: unreviewed pattern:");
2709 if (current_output_insn)
2710 debug_rtx (current_output_insn);
2711 gcc_unreachable ();
2712 }
2713 /* PSImode operations are either .w or .l depending on the target. */
2714 if (code == '&')
2715 {
2716 if (TARGET_A16)
2717 fprintf (file, "w");
2718 else
2719 fprintf (file, "l");
2720 return;
2721 }
2722 /* Inverted conditionals. */
2723 if (code == 'C')
2724 {
2725 switch (GET_CODE (x))
2726 {
2727 case LE:
2728 fputs ("gt", file);
2729 break;
2730 case LEU:
2731 fputs ("gtu", file);
2732 break;
2733 case LT:
2734 fputs ("ge", file);
2735 break;
2736 case LTU:
2737 fputs ("geu", file);
2738 break;
2739 case GT:
2740 fputs ("le", file);
2741 break;
2742 case GTU:
2743 fputs ("leu", file);
2744 break;
2745 case GE:
2746 fputs ("lt", file);
2747 break;
2748 case GEU:
2749 fputs ("ltu", file);
2750 break;
2751 case NE:
2752 fputs ("eq", file);
2753 break;
2754 case EQ:
2755 fputs ("ne", file);
2756 break;
2757 default:
2758 gcc_unreachable ();
2759 }
2760 return;
2761 }
2762 /* Regular conditionals. */
2763 if (code == 'c')
2764 {
2765 switch (GET_CODE (x))
2766 {
2767 case LE:
2768 fputs ("le", file);
2769 break;
2770 case LEU:
2771 fputs ("leu", file);
2772 break;
2773 case LT:
2774 fputs ("lt", file);
2775 break;
2776 case LTU:
2777 fputs ("ltu", file);
2778 break;
2779 case GT:
2780 fputs ("gt", file);
2781 break;
2782 case GTU:
2783 fputs ("gtu", file);
2784 break;
2785 case GE:
2786 fputs ("ge", file);
2787 break;
2788 case GEU:
2789 fputs ("geu", file);
2790 break;
2791 case NE:
2792 fputs ("ne", file);
2793 break;
2794 case EQ:
2795 fputs ("eq", file);
2796 break;
2797 default:
2798 gcc_unreachable ();
2799 }
2800 return;
2801 }
2802 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2803 operand. */
2804 if (code == 'h' && GET_MODE (x) == SImode)
2805 {
2806 x = m32c_subreg (HImode, x, SImode, 0);
2807 code = 0;
2808 }
2809 if (code == 'H' && GET_MODE (x) == SImode)
2810 {
2811 x = m32c_subreg (HImode, x, SImode, 2);
2812 code = 0;
2813 }
07127a0a
DD		 2814 if (code == 'h' && GET_MODE (x) == HImode)
2815 {
2816 x = m32c_subreg (QImode, x, HImode, 0);
2817 code = 0;
2818 }
2819 if (code == 'H' && GET_MODE (x) == HImode)
2820 {
2821 /* We can't actually represent this as an rtx. Do it here. */
2822 if (GET_CODE (x) == REG)
2823 {
2824 switch (REGNO (x))
2825 {
2826 case R0_REGNO:
2827 fputs ("r0h", file);
2828 return;
2829 case R1_REGNO:
2830 fputs ("r1h", file);
2831 return;
2832 default:
2833 gcc_unreachable();
2834 }
2835 }
2836 /* This should be a MEM. */
2837 x = m32c_subreg (QImode, x, HImode, 1);
2838 code = 0;
2839 }
2840 /* This is for BMcond, which always wants word register names. */
2841 if (code == 'h' && GET_MODE (x) == QImode)
2842 {
2843 if (GET_CODE (x) == REG)
2844 x = gen_rtx_REG (HImode, REGNO (x));
2845 code = 0;
2846 }
38b2d076
DD		 2847 /* 'x' and 'X' need to be ignored for non-immediates. */
2848 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2849 code = 0;
2850
2851 encode_pattern (x);
ff485e71 2852 force_sign = 0;
38b2d076
DD		 2853 for (i = 0; conversions[i].pattern; i++)
2854 if (conversions[i].code == code
2855 && streq (conversions[i].pattern, pattern))
2856 {
2857 for (j = 0; conversions[i].format[j]; j++)
2858 /* backslash quotes the next character in the output pattern. */
2859 if (conversions[i].format[j] == '\\')
2860 {
2861 fputc (conversions[i].format[j + 1], file);
2862 j++;
2863 }
2864 /* Digits in the output pattern indicate that the
2865 corresponding RTX is to be output at that point. */
2866 else if (ISDIGIT (conversions[i].format[j]))
2867 {
2868 rtx r = patternr[conversions[i].format[j] - '0'];
2869 switch (GET_CODE (r))
2870 {
2871 case REG:
2872 fprintf (file, "%s",
2873 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2874 break;
2875 case CONST_INT:
2876 switch (code)
2877 {
2878 case 'b':
07127a0a
DD		 2879 case 'B':
2880 {
2881 int v = INTVAL (r);
2882 int i = (int) exact_log2 (v);
2883 if (i == -1)
2884 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2885 if (i == -1)
2886 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2887 /* Bit position. */
2888 fprintf (file, "%d", i);
2889 }
38b2d076
DD		 2890 break;
2891 case 'x':
2892 /* Unsigned byte. */
2893 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2894 INTVAL (r) & 0xff);
2895 break;
2896 case 'X':
2897 /* Unsigned word. */
2898 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2899 INTVAL (r) & 0xffff);
2900 break;
2901 case 'p':
2902 /* pushm and popm encode a register set into a single byte. */
2903 comma = "";
2904 for (b = 7; b >= 0; b--)
2905 if (INTVAL (r) & (1 << b))
2906 {
2907 fprintf (file, "%s%s", comma, pushm_regs[b]);
2908 comma = ",";
2909 }
2910 break;
2911 case 'm':
2912 /* "Minus". Output -X */
2913 ival = (-INTVAL (r) & 0xffff);
2914 if (ival & 0x8000)
2915 ival = ival - 0x10000;
2916 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2917 break;
2918 default:
2919 ival = INTVAL (r);
2920 if (conversions[i].format[j + 1] == '[' && ival < 0)
2921 {
2922 /* We can simulate negative displacements by
2923 taking advantage of address space
2924 wrapping when the offset can span the
2925 entire address range. */
2926 rtx base =
2927 patternr[conversions[i].format[j + 2] - '0'];
2928 if (GET_CODE (base) == REG)
2929 switch (REGNO (base))
2930 {
2931 case A0_REGNO:
2932 case A1_REGNO:
2933 if (TARGET_A24)
2934 ival = 0x1000000 + ival;
2935 else
2936 ival = 0x10000 + ival;
2937 break;
2938 case SB_REGNO:
2939 if (TARGET_A16)
2940 ival = 0x10000 + ival;
2941 break;
2942 }
2943 }
2944 else if (code == 'd' && ival < 0 && j == 0)
2945 /* The "mova" opcode is used to do addition by
2946 computing displacements, but again, we need
2947 displacements to be unsigned *if* they're
2948 the only component of the displacement
2949 (i.e. no "symbol-4" type displacement). */
2950 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2951
2952 if (conversions[i].format[j] == '0')
2953 {
2954 /* More conversions to unsigned. */
2955 if (unsigned_const == 2)
2956 ival &= 0xffff;
2957 if (unsigned_const == 1)
2958 ival &= 0xff;
2959 }
2960 if (streq (conversions[i].pattern, "mi")
2961 || streq (conversions[i].pattern, "mmi"))
2962 {
2963 /* Integers used as addresses are unsigned. */
2964 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2965 }
ff485e71
DD		 2966 if (force_sign && ival >= 0)
2967 fputc ('+', file);
38b2d076
DD		 2968 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2969 break;
2970 }
2971 break;
2972 case CONST_DOUBLE:
2973 /* We don't have const_double constants. If it
2974 happens, make it obvious. */
2975 fprintf (file, "[const_double 0x%lx]",
2976 (unsigned long) CONST_DOUBLE_HIGH (r));
2977 break;
2978 case SYMBOL_REF:
2979 assemble_name (file, XSTR (r, 0));
2980 break;
2981 case LABEL_REF:
2982 output_asm_label (r);
2983 break;
2984 default:
2985 fprintf (stderr, "don't know how to print this operand:");
2986 debug_rtx (r);
2987 gcc_unreachable ();
2988 }
2989 }
2990 else
2991 {
2992 if (conversions[i].format[j] == 'z')
2993 {
2994 /* Some addressing modes *must* have a displacement,
2995 so insert a zero here if needed. */
2996 int k;
2997 for (k = j + 1; conversions[i].format[k]; k++)
2998 if (ISDIGIT (conversions[i].format[k]))
2999 {
3000 rtx reg = patternr[conversions[i].format[k] - '0'];
3001 if (GET_CODE (reg) == REG
3002 && (REGNO (reg) == SB_REGNO
3003 || REGNO (reg) == FB_REGNO
3004 || REGNO (reg) == SP_REGNO))
3005 fputc ('0', file);
3006 }
3007 continue;
3008 }
3009 /* Signed displacements off symbols need to have signs
3010 blended cleanly. */
3011 if (conversions[i].format[j] == '+'
ff485e71 3012 && (!code || code == 'D' || code == 'd')
38b2d076 3013 && ISDIGIT (conversions[i].format[j + 1])
ff485e71
DD		 3014 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
3015 == CONST_INT))
3016 {
3017 force_sign = 1;
3018 continue;
3019 }
38b2d076
DD		 3020 fputc (conversions[i].format[j], file);
3021 }
3022 break;
3023 }
3024 if (!conversions[i].pattern)
3025 {
3026 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
3027 pattern);
3028 debug_rtx (x);
3029 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
3030 }
3031
3032 return;
3033}
3034
3035/* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
3036 above for descriptions of what these do. */
3037int
3038m32c_print_operand_punct_valid_p (int c)
3039{
3040 if (c == '&' || c == '!')
3041 return 1;
3042 return 0;
3043}
3044
3045/* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
3046void
3047m32c_print_operand_address (FILE * stream, rtx address)
3048{
235e1fe8
NC		 3049 if (GET_CODE (address) == MEM)
3050 address = XEXP (address, 0);
3051 else
3052 /* cf: gcc.dg/asm-4.c. */
3053 gcc_assert (GET_CODE (address) == REG);
3054
3055 m32c_print_operand (stream, address, 0);
38b2d076
DD		 3056}
3057
3058/* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
3059 differently than general registers. */
3060void
3061m32c_output_reg_push (FILE * s, int regno)
3062{
3063 if (regno == FLG_REGNO)
3064 fprintf (s, "\tpushc\tflg\n");
3065 else
04aff2c0 3066 fprintf (s, "\tpush.%c\t%s\n",
38b2d076
DD		 3067 " bwll"[reg_push_size (regno)], reg_names[regno]);
3068}
3069
3070/* Likewise for ASM_OUTPUT_REG_POP. */
3071void
3072m32c_output_reg_pop (FILE * s, int regno)
3073{
3074 if (regno == FLG_REGNO)
3075 fprintf (s, "\tpopc\tflg\n");
3076 else
04aff2c0 3077 fprintf (s, "\tpop.%c\t%s\n",
38b2d076
DD		 3078 " bwll"[reg_push_size (regno)], reg_names[regno]);
3079}
3080
3081/* Defining target-specific uses of `__attribute__' */
3082
3083/* Used to simplify the logic below. Find the attributes wherever
3084 they may be. */
3085#define M32C_ATTRIBUTES(decl) \
3086 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
3087 : DECL_ATTRIBUTES (decl) \
3088 ? (DECL_ATTRIBUTES (decl)) \
3089 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
3090
3091/* Returns TRUE if the given tree has the "interrupt" attribute. */
3092static int
3093interrupt_p (tree node ATTRIBUTE_UNUSED)
3094{
3095 tree list = M32C_ATTRIBUTES (node);
3096 while (list)
3097 {
3098 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
3099 return 1;
3100 list = TREE_CHAIN (list);
3101 }
65655f79
DD		 3102 return fast_interrupt_p (node);
3103}
3104
3105/* Returns TRUE if the given tree has the "bank_switch" attribute. */
3106static int
3107bank_switch_p (tree node ATTRIBUTE_UNUSED)
3108{
3109 tree list = M32C_ATTRIBUTES (node);
3110 while (list)
3111 {
3112 if (is_attribute_p ("bank_switch", TREE_PURPOSE (list)))
3113 return 1;
3114 list = TREE_CHAIN (list);
3115 }
3116 return 0;
3117}
3118
3119/* Returns TRUE if the given tree has the "fast_interrupt" attribute. */
3120static int
3121fast_interrupt_p (tree node ATTRIBUTE_UNUSED)
3122{
3123 tree list = M32C_ATTRIBUTES (node);
3124 while (list)
3125 {
3126 if (is_attribute_p ("fast_interrupt", TREE_PURPOSE (list)))
3127 return 1;
3128 list = TREE_CHAIN (list);
3129 }
38b2d076
DD		 3130 return 0;
3131}
3132
3133static tree
3134interrupt_handler (tree * node ATTRIBUTE_UNUSED,
3135 tree name ATTRIBUTE_UNUSED,
3136 tree args ATTRIBUTE_UNUSED,
3137 int flags ATTRIBUTE_UNUSED,
3138 bool * no_add_attrs ATTRIBUTE_UNUSED)
3139{
3140 return NULL_TREE;
3141}
3142
5abd2125
JS		 3143/* Returns TRUE if given tree has the "function_vector" attribute. */
3144int
3145m32c_special_page_vector_p (tree func)
3146{
653e2568
DD		 3147 tree list;
3148
5abd2125
JS		 3149 if (TREE_CODE (func) != FUNCTION_DECL)
3150 return 0;
3151
653e2568 3152 list = M32C_ATTRIBUTES (func);
5abd2125
JS		 3153 while (list)
3154 {
3155 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
3156 return 1;
3157 list = TREE_CHAIN (list);
3158 }
3159 return 0;
3160}
3161
3162static tree
3163function_vector_handler (tree * node ATTRIBUTE_UNUSED,
3164 tree name ATTRIBUTE_UNUSED,
3165 tree args ATTRIBUTE_UNUSED,
3166 int flags ATTRIBUTE_UNUSED,
3167 bool * no_add_attrs ATTRIBUTE_UNUSED)
3168{
3169 if (TARGET_R8C)
3170 {
3171 /* The attribute is not supported for R8C target. */
3172 warning (OPT_Wattributes,
29d08eba
JM		 3173 "%qE attribute is not supported for R8C target",
3174 name);
5abd2125
JS		 3175 *no_add_attrs = true;
3176 }
3177 else if (TREE_CODE (*node) != FUNCTION_DECL)
3178 {
3179 /* The attribute must be applied to functions only. */
3180 warning (OPT_Wattributes,
29d08eba
JM		 3181 "%qE attribute applies only to functions",
3182 name);
5abd2125
JS		 3183 *no_add_attrs = true;
3184 }
3185 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
3186 {
3187 /* The argument must be a constant integer. */
3188 warning (OPT_Wattributes,
29d08eba
JM		 3189 "%qE attribute argument not an integer constant",
3190 name);
5abd2125
JS		 3191 *no_add_attrs = true;
3192 }
3193 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
3194 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
3195 {
3196 /* The argument value must be between 18 to 255. */
3197 warning (OPT_Wattributes,
29d08eba
JM		 3198 "%qE attribute argument should be between 18 to 255",
3199 name);
5abd2125
JS		 3200 *no_add_attrs = true;
3201 }
3202 return NULL_TREE;
3203}
3204
3205/* If the function is assigned the attribute 'function_vector', it
3206 returns the function vector number, otherwise returns zero. */
3207int
3208current_function_special_page_vector (rtx x)
3209{
3210 int num;
3211
3212 if ((GET_CODE(x) == SYMBOL_REF)
3213 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
3214 {
653e2568 3215 tree list;
5abd2125
JS		 3216 tree t = SYMBOL_REF_DECL (x);
3217
3218 if (TREE_CODE (t) != FUNCTION_DECL)
3219 return 0;
3220
653e2568 3221 list = M32C_ATTRIBUTES (t);
5abd2125
JS		 3222 while (list)
3223 {
3224 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
3225 {
3226 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
3227 return num;
3228 }
3229
3230 list = TREE_CHAIN (list);
3231 }
3232
3233 return 0;
3234 }
3235 else
3236 return 0;
3237}
3238
38b2d076
DD		 3239#undef TARGET_ATTRIBUTE_TABLE
3240#define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
3241static const struct attribute_spec m32c_attribute_table[] = {
62d784f7
KT		 3242 {"interrupt", 0, 0, false, false, false, interrupt_handler, false},
3243 {"bank_switch", 0, 0, false, false, false, interrupt_handler, false},
3244 {"fast_interrupt", 0, 0, false, false, false, interrupt_handler, false},
3245 {"function_vector", 1, 1, true, false, false, function_vector_handler,
3246 false},
3247 {0, 0, 0, 0, 0, 0, 0, false}
38b2d076
DD		 3248};
3249
3250#undef TARGET_COMP_TYPE_ATTRIBUTES
3251#define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
3252static int
3101faab
KG		 3253m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
3254 const_tree type2 ATTRIBUTE_UNUSED)
38b2d076
DD		 3255{
3256 /* 0=incompatible 1=compatible 2=warning */
3257 return 1;
3258}
3259
3260#undef TARGET_INSERT_ATTRIBUTES
3261#define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
3262static void
3263m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
3264 tree * attr_ptr ATTRIBUTE_UNUSED)
3265{
f6052f86
DD		 3266 unsigned addr;
3267 /* See if we need to make #pragma address variables volatile. */
3268
3269 if (TREE_CODE (node) == VAR_DECL)
3270 {
444d6efe 3271 const char *name = IDENTIFIER_POINTER (DECL_NAME (node));
f6052f86
DD		 3272 if (m32c_get_pragma_address (name, &addr))
3273 {
3274 TREE_THIS_VOLATILE (node) = true;
3275 }
3276 }
3277}
3278
3279
3280struct GTY(()) pragma_entry {
3281 const char *varname;
3282 unsigned address;
3283};
3284typedef struct pragma_entry pragma_entry;
3285
3286/* Hash table of pragma info. */
3287static GTY((param_is (pragma_entry))) htab_t pragma_htab;
3288
3289static int
3290pragma_entry_eq (const void *p1, const void *p2)
3291{
3292 const pragma_entry *old = (const pragma_entry *) p1;
3293 const char *new_name = (const char *) p2;
3294
3295 return strcmp (old->varname, new_name) == 0;
3296}
3297
3298static hashval_t
3299pragma_entry_hash (const void *p)
3300{
3301 const pragma_entry *old = (const pragma_entry *) p;
3302 return htab_hash_string (old->varname);
3303}
3304
3305void
3306m32c_note_pragma_address (const char *varname, unsigned address)
3307{
3308 pragma_entry **slot;
3309
3310 if (!pragma_htab)
3311 pragma_htab = htab_create_ggc (31, pragma_entry_hash,
3312 pragma_entry_eq, NULL);
3313
3314 slot = (pragma_entry **)
3315 htab_find_slot_with_hash (pragma_htab, varname,
3316 htab_hash_string (varname), INSERT);
3317
3318 if (!*slot)
3319 {
3320 *slot = ggc_alloc_pragma_entry ();
3321 (*slot)->varname = ggc_strdup (varname);
3322 }
3323 (*slot)->address = address;
3324}
3325
3326static bool
3327m32c_get_pragma_address (const char *varname, unsigned *address)
3328{
3329 pragma_entry **slot;
3330
3331 if (!pragma_htab)
3332 return false;
3333
3334 slot = (pragma_entry **)
3335 htab_find_slot_with_hash (pragma_htab, varname,
3336 htab_hash_string (varname), NO_INSERT);
3337 if (slot && *slot)
3338 {
3339 *address = (*slot)->address;
3340 return true;
3341 }
3342 return false;
3343}
3344
3345void
444d6efe
JR		 3346m32c_output_aligned_common (FILE *stream, tree decl ATTRIBUTE_UNUSED,
3347 const char *name,
f6052f86
DD		 3348 int size, int align, int global)
3349{
3350 unsigned address;
3351
3352 if (m32c_get_pragma_address (name, &address))
3353 {
3354 /* We never output these as global. */
3355 assemble_name (stream, name);
3356 fprintf (stream, " = 0x%04x\n", address);
3357 return;
3358 }
3359 if (!global)
3360 {
3361 fprintf (stream, "\t.local\t");
3362 assemble_name (stream, name);
3363 fprintf (stream, "\n");
3364 }
3365 fprintf (stream, "\t.comm\t");
3366 assemble_name (stream, name);
3367 fprintf (stream, ",%u,%u\n", size, align / BITS_PER_UNIT);
38b2d076
DD		 3368}
3369
3370/* Predicates */
3371
f9b89438 3372/* This is a list of legal subregs of hard regs. */
67fc44cb
DD		 3373static const struct {
3374 unsigned char outer_mode_size;
3375 unsigned char inner_mode_size;
3376 unsigned char byte_mask;
3377 unsigned char legal_when;
f9b89438 3378 unsigned int regno;
f9b89438 3379} legal_subregs[] = {
67fc44cb
DD		 3380 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
3381 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
3382 {1, 2, 0x01, 1, A0_REGNO},
3383 {1, 2, 0x01, 1, A1_REGNO},
f9b89438 3384
67fc44cb
DD		 3385 {1, 4, 0x01, 1, A0_REGNO},
3386 {1, 4, 0x01, 1, A1_REGNO},
f9b89438 3387
67fc44cb
DD		 3388 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
3389 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
3390 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
3391 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
3392 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
f9b89438 3393
67fc44cb 3394 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
f9b89438
DD		 3395};
3396
3397/* Returns TRUE if OP is a subreg of a hard reg which we don't
f6052f86 3398 support. We also bail on MEMs with illegal addresses. */
f9b89438
DD		 3399bool
3400m32c_illegal_subreg_p (rtx op)
3401{
f9b89438
DD		 3402 int offset;
3403 unsigned int i;
3404 int src_mode, dest_mode;
3405
f6052f86
DD		 3406 if (GET_CODE (op) == MEM
3407 && ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))
3408 {
3409 return true;
3410 }
3411
f9b89438
DD		 3412 if (GET_CODE (op) != SUBREG)
3413 return false;
3414
3415 dest_mode = GET_MODE (op);
3416 offset = SUBREG_BYTE (op);
3417 op = SUBREG_REG (op);
3418 src_mode = GET_MODE (op);
3419
3420 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
3421 return false;
3422 if (GET_CODE (op) != REG)
3423 return false;
3424 if (REGNO (op) >= MEM0_REGNO)
3425 return false;
3426
3427 offset = (1 << offset);
3428
67fc44cb 3429 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
f9b89438
DD		 3430 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
3431 && legal_subregs[i].regno == REGNO (op)
3432 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
3433 && legal_subregs[i].byte_mask & offset)
3434 {
3435 switch (legal_subregs[i].legal_when)
3436 {
3437 case 1:
3438 return false;
3439 case 16:
3440 if (TARGET_A16)
3441 return false;
3442 break;
3443 case 24:
3444 if (TARGET_A24)
3445 return false;
3446 break;
3447 }
3448 }
3449 return true;
3450}
3451
38b2d076
DD		 3452/* Returns TRUE if we support a move between the first two operands.
3453 At the moment, we just want to discourage mem to mem moves until
3454 after reload, because reload has a hard time with our limited
3455 number of address registers, and we can get into a situation where
3456 we need three of them when we only have two. */
3457bool
3458m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
3459{
3460 rtx op0 = operands[0];
3461 rtx op1 = operands[1];
3462
3463 if (TARGET_A24)
3464 return true;
3465
3466#define DEBUG_MOV_OK 0
3467#if DEBUG_MOV_OK
3468 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
3469 debug_rtx (op0);
3470 debug_rtx (op1);
3471#endif
3472
3473 if (GET_CODE (op0) == SUBREG)
3474 op0 = XEXP (op0, 0);
3475 if (GET_CODE (op1) == SUBREG)
3476 op1 = XEXP (op1, 0);
3477
3478 if (GET_CODE (op0) == MEM
3479 && GET_CODE (op1) == MEM
3480 && ! reload_completed)
3481 {
3482#if DEBUG_MOV_OK
3483 fprintf (stderr, " - no, mem to mem\n");
3484#endif
3485 return false;
3486 }
3487
3488#if DEBUG_MOV_OK
3489 fprintf (stderr, " - ok\n");
3490#endif
3491 return true;
3492}
3493
ff485e71
DD		 3494/* Returns TRUE if two consecutive HImode mov instructions, generated
3495 for moving an immediate double data to a double data type variable
3496 location, can be combined into single SImode mov instruction. */
3497bool
3498m32c_immd_dbl_mov (rtx * operands,
3499 enum machine_mode mode ATTRIBUTE_UNUSED)
3500{
3501 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
3502 const char *str1;
3503 const char *str2;
3504
3505 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
3506 && MEM_SCALAR_P (operands[0])
3507 && !MEM_IN_STRUCT_P (operands[0])
3508 && GET_CODE (XEXP (operands[2], 0)) == CONST
3509 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3510 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3511 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
3512 && MEM_SCALAR_P (operands[2])
3513 && !MEM_IN_STRUCT_P (operands[2]))
3514 flag = 1;
3515
3516 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
3517 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
3518 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
3519 && MEM_SCALAR_P (operands[0])
3520 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3521 && !(INTVAL (XEXP (XEXP (XEXP (operands[0], 0), 0), 1)) %4)
ff485e71
DD		 3522 && GET_CODE (XEXP (operands[2], 0)) == CONST
3523 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
3524 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3525 && MEM_SCALAR_P (operands[2])
3526 && !MEM_IN_STRUCT_P (operands[2]))
3527 flag = 2;
3528
3529 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3530 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3531 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3532 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3533 && MEM_SCALAR_P (operands[0])
3534 && !MEM_IN_STRUCT_P (operands[0])
f9f3567e 3535 && !(INTVAL (XEXP (XEXP (operands[0], 0), 1)) %4)
ff485e71
DD		 3536 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3537 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3538 && MEM_SCALAR_P (operands[2])
3539 && !MEM_IN_STRUCT_P (operands[2]))
3540 flag = 3;
3541
3542 else
3543 return false;
3544
3545 switch (flag)
3546 {
3547 case 1:
3548 str1 = XSTR (XEXP (operands[0], 0), 0);
3549 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3550 if (strcmp (str1, str2) == 0)
3551 okflag = 1;
3552 else
3553 okflag = 0;
3554 break;
3555 case 2:
3556 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3557 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3558 if (strcmp(str1,str2) == 0)
3559 okflag = 1;
3560 else
3561 okflag = 0;
3562 break;
3563 case 3:
f9f3567e
DD		 3564 offset1 = INTVAL (XEXP (XEXP (operands[0], 0), 1));
3565 offset2 = INTVAL (XEXP (XEXP (operands[2], 0), 1));
ff485e71
DD		 3566 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3567 if (((offset2-offset1) == 2) && offsetsign != 0)
3568 okflag = 1;
3569 else
3570 okflag = 0;
3571 break;
3572 default:
3573 okflag = 0;
3574 }
3575
3576 if (okflag == 1)
3577 {
3578 HOST_WIDE_INT val;
3579 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3580
f9f3567e 3581 val = (INTVAL (operands[3]) << 16) + (INTVAL (operands[1]) & 0xFFFF);
ff485e71
DD		 3582 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3583
3584 return true;
3585 }
3586
3587 return false;
3588}
3589
38b2d076
DD		 3590/* Expanders */
3591
3592/* Subregs are non-orthogonal for us, because our registers are all
3593 different sizes. */
3594static rtx
3595m32c_subreg (enum machine_mode outer,
3596 rtx x, enum machine_mode inner, int byte)
3597{
3598 int r, nr = -1;
3599
3600 /* Converting MEMs to different types that are the same size, we
3601 just rewrite them. */
3602 if (GET_CODE (x) == SUBREG
3603 && SUBREG_BYTE (x) == 0
3604 && GET_CODE (SUBREG_REG (x)) == MEM
3605 && (GET_MODE_SIZE (GET_MODE (x))
3606 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3607 {
3608 rtx oldx = x;
3609 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3610 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3611 }
3612
3613 /* Push/pop get done as smaller push/pops. */
3614 if (GET_CODE (x) == MEM
3615 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3616 || GET_CODE (XEXP (x, 0)) == POST_INC))
3617 return gen_rtx_MEM (outer, XEXP (x, 0));
3618 if (GET_CODE (x) == SUBREG
3619 && GET_CODE (XEXP (x, 0)) == MEM
3620 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3621 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3622 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3623
3624 if (GET_CODE (x) != REG)
146456c1
DD		 3625 {
3626 rtx r = simplify_gen_subreg (outer, x, inner, byte);
3627 if (GET_CODE (r) == SUBREG
3628 && GET_CODE (x) == MEM
3629 && MEM_VOLATILE_P (x))
3630 {
3631 /* Volatile MEMs don't get simplified, but we need them to
3632 be. We are little endian, so the subreg byte is the
3633 offset. */
91140cd3 3634 r = adjust_address_nv (x, outer, byte);
146456c1
DD		 3635 }
3636 return r;
3637 }
38b2d076
DD		 3638
3639 r = REGNO (x);
3640 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3641 return simplify_gen_subreg (outer, x, inner, byte);
3642
3643 if (IS_MEM_REGNO (r))
3644 return simplify_gen_subreg (outer, x, inner, byte);
3645
3646 /* This is where the complexities of our register layout are
3647 described. */
3648 if (byte == 0)
3649 nr = r;
3650 else if (outer == HImode)
3651 {
3652 if (r == R0_REGNO && byte == 2)
3653 nr = R2_REGNO;
3654 else if (r == R0_REGNO && byte == 4)
3655 nr = R1_REGNO;
3656 else if (r == R0_REGNO && byte == 6)
3657 nr = R3_REGNO;
3658 else if (r == R1_REGNO && byte == 2)
3659 nr = R3_REGNO;
3660 else if (r == A0_REGNO && byte == 2)
3661 nr = A1_REGNO;
3662 }
3663 else if (outer == SImode)
3664 {
3665 if (r == R0_REGNO && byte == 0)
3666 nr = R0_REGNO;
3667 else if (r == R0_REGNO && byte == 4)
3668 nr = R1_REGNO;
3669 }
3670 if (nr == -1)
3671 {
3672 fprintf (stderr, "m32c_subreg %s %s %d\n",
3673 mode_name[outer], mode_name[inner], byte);
3674 debug_rtx (x);
3675 gcc_unreachable ();
3676 }
3677 return gen_rtx_REG (outer, nr);
3678}
3679
3680/* Used to emit move instructions. We split some moves,
3681 and avoid mem-mem moves. */
3682int
3683m32c_prepare_move (rtx * operands, enum machine_mode mode)
3684{
5fd5d713
DD		 3685 if (far_addr_space_p (operands[0])
3686 && CONSTANT_P (operands[1]))
3687 {
3688 operands[1] = force_reg (GET_MODE (operands[0]), operands[1]);
3689 }
38b2d076
DD		 3690 if (TARGET_A16 && mode == PSImode)
3691 return m32c_split_move (operands, mode, 1);
3692 if ((GET_CODE (operands[0]) == MEM)
3693 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3694 {
3695 rtx pmv = XEXP (operands[0], 0);
3696 rtx dest_reg = XEXP (pmv, 0);
3697 rtx dest_mod = XEXP (pmv, 1);
3698
3699 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3700 operands[0] = gen_rtx_MEM (mode, dest_reg);
3701 }
b3a13419 3702 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3703 operands[1] = copy_to_mode_reg (mode, operands[1]);
3704 return 0;
3705}
3706
3707#define DEBUG_SPLIT 0
3708
3709/* Returns TRUE if the given PSImode move should be split. We split
3710 for all r8c/m16c moves, since it doesn't support them, and for
3711 POP.L as we can only *push* SImode. */
3712int
3713m32c_split_psi_p (rtx * operands)
3714{
3715#if DEBUG_SPLIT
3716 fprintf (stderr, "\nm32c_split_psi_p\n");
3717 debug_rtx (operands[0]);
3718 debug_rtx (operands[1]);
3719#endif
3720 if (TARGET_A16)
3721 {
3722#if DEBUG_SPLIT
3723 fprintf (stderr, "yes, A16\n");
3724#endif
3725 return 1;
3726 }
3727 if (GET_CODE (operands[1]) == MEM
3728 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3729 {
3730#if DEBUG_SPLIT
3731 fprintf (stderr, "yes, pop.l\n");
3732#endif
3733 return 1;
3734 }
3735#if DEBUG_SPLIT
3736 fprintf (stderr, "no, default\n");
3737#endif
3738 return 0;
3739}
3740
3741/* Split the given move. SPLIT_ALL is 0 if splitting is optional
3742 (define_expand), 1 if it is not optional (define_insn_and_split),
3743 and 3 for define_split (alternate api). */
3744int
3745m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3746{
3747 rtx s[4], d[4];
3748 int parts, si, di, rev = 0;
3749 int rv = 0, opi = 2;
3750 enum machine_mode submode = HImode;
3751 rtx *ops, local_ops[10];
3752
3753 /* define_split modifies the existing operands, but the other two
3754 emit new insns. OPS is where we store the operand pairs, which
3755 we emit later. */
3756 if (split_all == 3)
3757 ops = operands;
3758 else
3759 ops = local_ops;
3760
3761 /* Else HImode. */
3762 if (mode == DImode)
3763 submode = SImode;
3764
3765 /* Before splitting mem-mem moves, force one operand into a
3766 register. */
b3a13419 3767 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
38b2d076
DD		 3768 {
3769#if DEBUG0
3770 fprintf (stderr, "force_reg...\n");
3771 debug_rtx (operands[1]);
3772#endif
3773 operands[1] = force_reg (mode, operands[1]);
3774#if DEBUG0
3775 debug_rtx (operands[1]);
3776#endif
3777 }
3778
3779 parts = 2;
3780
3781#if DEBUG_SPLIT
b3a13419
ILT		 3782 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3783 split_all);
38b2d076
DD		 3784 debug_rtx (operands[0]);
3785 debug_rtx (operands[1]);
3786#endif
3787
eb5f0c07
DD		 3788 /* Note that split_all is not used to select the api after this
3789 point, so it's safe to set it to 3 even with define_insn. */
3790 /* None of the chips can move SI operands to sp-relative addresses,
3791 so we always split those. */
3792 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3793 split_all = 3;
3794
5fd5d713
DD		 3795 if (TARGET_A16
3796 && (far_addr_space_p (operands[0])
3797 || far_addr_space_p (operands[1])))
3798 split_all |= 1;
3799
38b2d076
DD		 3800 /* We don't need to split these. */
3801 if (TARGET_A24
3802 && split_all != 3
3803 && (mode == SImode || mode == PSImode)
3804 && !(GET_CODE (operands[1]) == MEM
3805 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3806 return 0;
3807
3808 /* First, enumerate the subregs we'll be dealing with. */
3809 for (si = 0; si < parts; si++)
3810 {
3811 d[si] =
3812 m32c_subreg (submode, operands[0], mode,
3813 si * GET_MODE_SIZE (submode));
3814 s[si] =
3815 m32c_subreg (submode, operands[1], mode,
3816 si * GET_MODE_SIZE (submode));
3817 }
3818
3819 /* Split pushes by emitting a sequence of smaller pushes. */
3820 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3821 {
3822 for (si = parts - 1; si >= 0; si--)
3823 {
3824 ops[opi++] = gen_rtx_MEM (submode,
3825 gen_rtx_PRE_DEC (Pmode,
3826 gen_rtx_REG (Pmode,
3827 SP_REGNO)));
3828 ops[opi++] = s[si];
3829 }
3830
3831 rv = 1;
3832 }
3833 /* Likewise for pops. */
3834 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3835 {
3836 for (di = 0; di < parts; di++)
3837 {
3838 ops[opi++] = d[di];
3839 ops[opi++] = gen_rtx_MEM (submode,
3840 gen_rtx_POST_INC (Pmode,
3841 gen_rtx_REG (Pmode,
3842 SP_REGNO)));
3843 }
3844 rv = 1;
3845 }
3846 else if (split_all)
3847 {
3848 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3849 for (di = 0; di < parts - 1; di++)
3850 for (si = di + 1; si < parts; si++)
3851 if (reg_mentioned_p (d[di], s[si]))
3852 rev = 1;
3853
3854 if (rev)
3855 for (si = 0; si < parts; si++)
3856 {
3857 ops[opi++] = d[si];
3858 ops[opi++] = s[si];
3859 }
3860 else
3861 for (si = parts - 1; si >= 0; si--)
3862 {
3863 ops[opi++] = d[si];
3864 ops[opi++] = s[si];
3865 }
3866 rv = 1;
3867 }
3868 /* Now emit any moves we may have accumulated. */
3869 if (rv && split_all != 3)
3870 {
3871 int i;
3872 for (i = 2; i < opi; i += 2)
3873 emit_move_insn (ops[i], ops[i + 1]);
3874 }
3875 return rv;
3876}
3877
07127a0a
DD		 3878/* The m32c has a number of opcodes that act like memcpy, strcmp, and
3879 the like. For the R8C they expect one of the addresses to be in
3880 R1L:An so we need to arrange for that. Otherwise, it's just a
3881 matter of picking out the operands we want and emitting the right
3882 pattern for them. All these expanders, which correspond to
3883 patterns in blkmov.md, must return nonzero if they expand the insn,
3884 or zero if they should FAIL. */
3885
3886/* This is a memset() opcode. All operands are implied, so we need to
3887 arrange for them to be in the right registers. The opcode wants
3888 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3889 the count (HI), and $2 the value (QI). */
3890int
3891m32c_expand_setmemhi(rtx *operands)
3892{
3893 rtx desta, count, val;
3894 rtx desto, counto;
3895
3896 desta = XEXP (operands[0], 0);
3897 count = operands[1];
3898 val = operands[2];
3899
3900 desto = gen_reg_rtx (Pmode);
3901 counto = gen_reg_rtx (HImode);
3902
3903 if (GET_CODE (desta) != REG
3904 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3905 desta = copy_to_mode_reg (Pmode, desta);
3906
3907 /* This looks like an arbitrary restriction, but this is by far the
3908 most common case. For counts 8..14 this actually results in
3909 smaller code with no speed penalty because the half-sized
3910 constant can be loaded with a shorter opcode. */
3911 if (GET_CODE (count) == CONST_INT
3912 && GET_CODE (val) == CONST_INT
3913 && ! (INTVAL (count) & 1)
3914 && (INTVAL (count) > 1)
3915 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3916 {
3917 unsigned v = INTVAL (val) & 0xff;
3918 v = v | (v << 8);
3919 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3920 val = copy_to_mode_reg (HImode, GEN_INT (v));
3921 if (TARGET_A16)
3922 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3923 else
3924 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3925 return 1;
3926 }
3927
3928 /* This is the generalized memset() case. */
3929 if (GET_CODE (val) != REG
3930 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3931 val = copy_to_mode_reg (QImode, val);
3932
3933 if (GET_CODE (count) != REG
3934 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3935 count = copy_to_mode_reg (HImode, count);
3936
3937 if (TARGET_A16)
3938 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3939 else
3940 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3941
3942 return 1;
3943}
3944
3945/* This is a memcpy() opcode. All operands are implied, so we need to
3946 arrange for them to be in the right registers. The opcode wants
3947 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3948 is the source (MEM:BLK), and $2 the count (HI). */
3949int
3950m32c_expand_movmemhi(rtx *operands)
3951{
3952 rtx desta, srca, count;
3953 rtx desto, srco, counto;
3954
3955 desta = XEXP (operands[0], 0);
3956 srca = XEXP (operands[1], 0);
3957 count = operands[2];
3958
3959 desto = gen_reg_rtx (Pmode);
3960 srco = gen_reg_rtx (Pmode);
3961 counto = gen_reg_rtx (HImode);
3962
3963 if (GET_CODE (desta) != REG
3964 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3965 desta = copy_to_mode_reg (Pmode, desta);
3966
3967 if (GET_CODE (srca) != REG
3968 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3969 srca = copy_to_mode_reg (Pmode, srca);
3970
3971 /* Similar to setmem, but we don't need to check the value. */
3972 if (GET_CODE (count) == CONST_INT
3973 && ! (INTVAL (count) & 1)
3974 && (INTVAL (count) > 1))
3975 {
3976 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3977 if (TARGET_A16)
3978 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3979 else
3980 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3981 return 1;
3982 }
3983
3984 /* This is the generalized memset() case. */
3985 if (GET_CODE (count) != REG
3986 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3987 count = copy_to_mode_reg (HImode, count);
3988
3989 if (TARGET_A16)
3990 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3991 else
3992 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3993
3994 return 1;
3995}
3996
3997/* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3998 the copy, which should point to the NUL at the end of the string,
3999 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
4000 Since our opcode leaves the destination pointing *after* the NUL,
4001 we must emit an adjustment. */
4002int
4003m32c_expand_movstr(rtx *operands)
4004{
4005 rtx desta, srca;
4006 rtx desto, srco;
4007
4008 desta = XEXP (operands[1], 0);
4009 srca = XEXP (operands[2], 0);
4010
4011 desto = gen_reg_rtx (Pmode);
4012 srco = gen_reg_rtx (Pmode);
4013
4014 if (GET_CODE (desta) != REG
4015 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
4016 desta = copy_to_mode_reg (Pmode, desta);
4017
4018 if (GET_CODE (srca) != REG
4019 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
4020 srca = copy_to_mode_reg (Pmode, srca);
4021
4022 emit_insn (gen_movstr_op (desto, srco, desta, srca));
4023 /* desto ends up being a1, which allows this type of add through MOVA. */
4024 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
4025
4026 return 1;
4027}
4028
4029/* This is a strcmp() opcode. $0 is the destination (HI) which holds
4030 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
4031 $2 is the other (MEM:BLK). We must do the comparison, and then
4032 convert the flags to a signed integer result. */
4033int
4034m32c_expand_cmpstr(rtx *operands)
4035{
4036 rtx src1a, src2a;
4037
4038 src1a = XEXP (operands[1], 0);
4039 src2a = XEXP (operands[2], 0);
4040
4041 if (GET_CODE (src1a) != REG
4042 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
4043 src1a = copy_to_mode_reg (Pmode, src1a);
4044
4045 if (GET_CODE (src2a) != REG
4046 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
4047 src2a = copy_to_mode_reg (Pmode, src2a);
4048
4049 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
4050 emit_insn (gen_cond_to_int (operands[0]));
4051
4052 return 1;
4053}
4054
4055
23fed240
DD		 4056typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
4057
4058static shift_gen_func
4059shift_gen_func_for (int mode, int code)
4060{
4061#define GFF(m,c,f) if (mode == m && code == c) return f
4062 GFF(QImode, ASHIFT, gen_ashlqi3_i);
4063 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
4064 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
4065 GFF(HImode, ASHIFT, gen_ashlhi3_i);
4066 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
4067 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
4068 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
4069 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
4070 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
4071 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
4072 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
4073 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
4074#undef GFF
07127a0a 4075 gcc_unreachable ();
23fed240
DD		 4076}
4077
38b2d076
DD		 4078/* The m32c only has one shift, but it takes a signed count. GCC
4079 doesn't want this, so we fake it by negating any shift count when
07127a0a
DD		 4080 we're pretending to shift the other way. Also, the shift count is
4081 limited to -8..8. It's slightly better to use two shifts for 9..15
4082 than to load the count into r1h, so we do that too. */
38b2d076 4083int
23fed240 4084m32c_prepare_shift (rtx * operands, int scale, int shift_code)
38b2d076 4085{
23fed240
DD		 4086 enum machine_mode mode = GET_MODE (operands[0]);
4087 shift_gen_func func = shift_gen_func_for (mode, shift_code);
38b2d076 4088 rtx temp;
23fed240
DD		 4089
4090 if (GET_CODE (operands[2]) == CONST_INT)
38b2d076 4091 {
23fed240
DD		 4092 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
4093 int count = INTVAL (operands[2]) * scale;
4094
4095 while (count > maxc)
4096 {
4097 temp = gen_reg_rtx (mode);
4098 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
4099 operands[1] = temp;
4100 count -= maxc;
4101 }
4102 while (count < -maxc)
4103 {
4104 temp = gen_reg_rtx (mode);
4105 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
4106 operands[1] = temp;
4107 count += maxc;
4108 }
4109 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
4110 return 1;
38b2d076 4111 }
2e160056
DD		 4112
4113 temp = gen_reg_rtx (QImode);
38b2d076 4114 if (scale < 0)
2e160056
DD		 4115 /* The pattern has a NEG that corresponds to this. */
4116 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
4117 else if (TARGET_A16 && mode == SImode)
4118 /* We do this because the code below may modify this, we don't
4119 want to modify the origin of this value. */
4120 emit_move_insn (temp, operands[2]);
38b2d076 4121 else
2e160056 4122 /* We'll only use it for the shift, no point emitting a move. */
38b2d076 4123 temp = operands[2];
2e160056 4124
16659fcf 4125 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
2e160056
DD		 4126 {
4127 /* The m16c has a limit of -16..16 for SI shifts, even when the
4128 shift count is in a register. Since there are so many targets
4129 of these shifts, it's better to expand the RTL here than to
4130 call a helper function.
4131
4132 The resulting code looks something like this:
4133
4134 cmp.b r1h,-16
4135 jge.b 1f
4136 shl.l -16,dest
4137 add.b r1h,16
4138 1f: cmp.b r1h,16
4139 jle.b 1f
4140 shl.l 16,dest
4141 sub.b r1h,16
4142 1f: shl.l r1h,dest
4143
4144 We take advantage of the fact that "negative" shifts are
4145 undefined to skip one of the comparisons. */
4146
4147 rtx count;
444d6efe 4148 rtx label, insn, tempvar;
2e160056 4149
16659fcf
DD		 4150 emit_move_insn (operands[0], operands[1]);
4151
2e160056
DD		 4152 count = temp;
4153 label = gen_label_rtx ();
2e160056
DD		 4154 LABEL_NUSES (label) ++;
4155
833bf445
DD		 4156 tempvar = gen_reg_rtx (mode);
4157
2e160056
DD		 4158 if (shift_code == ASHIFT)
4159 {
4160 /* This is a left shift. We only need check positive counts. */
4161 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
4162 count, GEN_INT (16), label));
833bf445
DD		 4163 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
4164 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
2e160056
DD		 4165 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
4166 emit_label_after (label, insn);
4167 }
4168 else
4169 {
4170 /* This is a right shift. We only need check negative counts. */
4171 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
4172 count, GEN_INT (-16), label));
833bf445
DD		 4173 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
4174 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
2e160056
DD		 4175 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
4176 emit_label_after (label, insn);
4177 }
16659fcf
DD		 4178 operands[1] = operands[0];
4179 emit_insn (func (operands[0], operands[0], count));
4180 return 1;
2e160056
DD		 4181 }
4182
38b2d076
DD		 4183 operands[2] = temp;
4184 return 0;
4185}
4186
12ea2512
DD		 4187/* The m32c has a limited range of operations that work on PSImode
4188 values; we have to expand to SI, do the math, and truncate back to
4189 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
4190 those cases. */
4191void
4192m32c_expand_neg_mulpsi3 (rtx * operands)
4193{
4194 /* operands: a = b * i */
4195 rtx temp1; /* b as SI */
07127a0a
DD		 4196 rtx scale /* i as SI */;
4197 rtx temp2; /* a*b as SI */
12ea2512
DD		 4198
4199 temp1 = gen_reg_rtx (SImode);
4200 temp2 = gen_reg_rtx (SImode);
07127a0a
DD		 4201 if (GET_CODE (operands[2]) != CONST_INT)
4202 {
4203 scale = gen_reg_rtx (SImode);
4204 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
4205 }
4206 else
4207 scale = copy_to_mode_reg (SImode, operands[2]);
12ea2512
DD		 4208
4209 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
07127a0a
DD		 4210 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
4211 emit_insn (gen_truncsipsi2 (operands[0], temp2));
12ea2512
DD		 4212}
4213
38b2d076
DD		 4214/* Pattern Output Functions */
4215
07127a0a
DD		 4216int
4217m32c_expand_movcc (rtx *operands)
4218{
4219 rtx rel = operands[1];
0166ff05 4220
07127a0a
DD		 4221 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
4222 return 1;
4223 if (GET_CODE (operands[2]) != CONST_INT
4224 || GET_CODE (operands[3]) != CONST_INT)
4225 return 1;
07127a0a
DD		 4226 if (GET_CODE (rel) == NE)
4227 {
4228 rtx tmp = operands[2];
4229 operands[2] = operands[3];
4230 operands[3] = tmp;
f90b7a5a 4231 rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
07127a0a 4232 }
0166ff05 4233
0166ff05
DD		 4234 emit_move_insn (operands[0],
4235 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
f90b7a5a 4236 rel,
0166ff05
DD		 4237 operands[2],
4238 operands[3]));
07127a0a
DD		 4239 return 0;
4240}
4241
4242/* Used for the "insv" pattern. Return nonzero to fail, else done. */
4243int
4244m32c_expand_insv (rtx *operands)
4245{
4246 rtx op0, src0, p;
4247 int mask;
4248
4249 if (INTVAL (operands[1]) != 1)
4250 return 1;
4251
9cb96754
N		 4252 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
4253 if (GET_CODE (operands[3]) != CONST_INT)
4254 return 1;
4255 if (INTVAL (operands[3]) != 0
4256 && INTVAL (operands[3]) != 1
4257 && INTVAL (operands[3]) != -1)
4258 return 1;
4259
07127a0a
DD		 4260 mask = 1 << INTVAL (operands[2]);
4261
4262 op0 = operands[0];
4263 if (GET_CODE (op0) == SUBREG
4264 && SUBREG_BYTE (op0) == 0)
4265 {
4266 rtx sub = SUBREG_REG (op0);
4267 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
4268 op0 = sub;
4269 }
4270
b3a13419 4271 if (!can_create_pseudo_p ()
07127a0a
DD		 4272 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
4273 src0 = op0;
4274 else
4275 {
4276 src0 = gen_reg_rtx (GET_MODE (op0));
4277 emit_move_insn (src0, op0);
4278 }
4279
4280 if (GET_MODE (op0) == HImode
4281 && INTVAL (operands[2]) >= 8
444d6efe 4282 && GET_CODE (op0) == MEM)
07127a0a
DD		 4283 {
4284 /* We are little endian. */
4285 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
4286 MEM_COPY_ATTRIBUTES (new_mem, op0);
4287 mask >>= 8;
4288 }
4289
8e4edce7
DD		 4290 /* First, we generate a mask with the correct polarity. If we are
4291 storing a zero, we want an AND mask, so invert it. */
4292 if (INTVAL (operands[3]) == 0)
07127a0a 4293 {
16659fcf 4294 /* Storing a zero, use an AND mask */
07127a0a
DD		 4295 if (GET_MODE (op0) == HImode)
4296 mask ^= 0xffff;
4297 else
4298 mask ^= 0xff;
4299 }
8e4edce7
DD		 4300 /* Now we need to properly sign-extend the mask in case we need to
4301 fall back to an AND or OR opcode. */
07127a0a
DD		 4302 if (GET_MODE (op0) == HImode)
4303 {
4304 if (mask & 0x8000)
4305 mask -= 0x10000;
4306 }
4307 else
4308 {
4309 if (mask & 0x80)
4310 mask -= 0x100;
4311 }
4312
4313 switch ( (INTVAL (operands[3]) ? 4 : 0)
4314 + ((GET_MODE (op0) == HImode) ? 2 : 0)
4315 + (TARGET_A24 ? 1 : 0))
4316 {
4317 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
4318 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
4319 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
4320 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
4321 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
4322 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
4323 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
4324 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
653e2568 4325 default: p = NULL_RTX; break; /* Not reached, but silences a warning. */
07127a0a
DD		 4326 }
4327
4328 emit_insn (p);
4329 return 0;
4330}
4331
4332const char *
4333m32c_scc_pattern(rtx *operands, RTX_CODE code)
4334{
4335 static char buf[30];
4336 if (GET_CODE (operands[0]) == REG
4337 && REGNO (operands[0]) == R0_REGNO)
4338 {
4339 if (code == EQ)
4340 return "stzx\t#1,#0,r0l";
4341 if (code == NE)
4342 return "stzx\t#0,#1,r0l";
4343 }
4344 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
4345 return buf;
4346}
4347
5abd2125
JS		 4348/* Encode symbol attributes of a SYMBOL_REF into its
4349 SYMBOL_REF_FLAGS. */
4350static void
4351m32c_encode_section_info (tree decl, rtx rtl, int first)
4352{
4353 int extra_flags = 0;
4354
4355 default_encode_section_info (decl, rtl, first);
4356 if (TREE_CODE (decl) == FUNCTION_DECL
4357 && m32c_special_page_vector_p (decl))
4358
4359 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
4360
4361 if (extra_flags)
4362 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
4363}
4364
38b2d076
DD		 4365/* Returns TRUE if the current function is a leaf, and thus we can
4366 determine which registers an interrupt function really needs to
4367 save. The logic below is mostly about finding the insn sequence
4368 that's the function, versus any sequence that might be open for the
4369 current insn. */
4370static int
4371m32c_leaf_function_p (void)
4372{
4373 rtx saved_first, saved_last;
4374 struct sequence_stack *seq;
4375 int rv;
4376
3e029763
JH		 4377 saved_first = crtl->emit.x_first_insn;
4378 saved_last = crtl->emit.x_last_insn;
4379 for (seq = crtl->emit.sequence_stack; seq && seq->next; seq = seq->next)
38b2d076
DD		 4380 ;
4381 if (seq)
4382 {
3e029763
JH		 4383 crtl->emit.x_first_insn = seq->first;
4384 crtl->emit.x_last_insn = seq->last;
38b2d076
DD		 4385 }
4386
4387 rv = leaf_function_p ();
4388
3e029763
JH		 4389 crtl->emit.x_first_insn = saved_first;
4390 crtl->emit.x_last_insn = saved_last;
38b2d076
DD		 4391 return rv;
4392}
4393
4394/* Returns TRUE if the current function needs to use the ENTER/EXIT
4395 opcodes. If the function doesn't need the frame base or stack
4396 pointer, it can use the simpler RTS opcode. */
4397static bool
4398m32c_function_needs_enter (void)
4399{
4400 rtx insn;
4401 struct sequence_stack *seq;
4402 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
4403 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
4404
4405 insn = get_insns ();
3e029763 4406 for (seq = crtl->emit.sequence_stack;
38b2d076
DD		 4407 seq;
4408 insn = seq->first, seq = seq->next);
4409
4410 while (insn)
4411 {
4412 if (reg_mentioned_p (sp, insn))
4413 return true;
4414 if (reg_mentioned_p (fb, insn))
4415 return true;
4416 insn = NEXT_INSN (insn);
4417 }
4418 return false;
4419}
4420
4421/* Mark all the subexpressions of the PARALLEL rtx PAR as
4422 frame-related. Return PAR.
4423
4424 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
4425 PARALLEL rtx other than the first if they do not have the
4426 FRAME_RELATED flag set on them. So this function is handy for
4427 marking up 'enter' instructions. */
4428static rtx
4429m32c_all_frame_related (rtx par)
4430{
4431 int len = XVECLEN (par, 0);
4432 int i;
4433
4434 for (i = 0; i < len; i++)
4435 F (XVECEXP (par, 0, i));
4436
4437 return par;
4438}
4439
4440/* Emits the prologue. See the frame layout comment earlier in this
4441 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
4442 that we manually update sp. */
4443void
4444m32c_emit_prologue (void)
4445{
4446 int frame_size, extra_frame_size = 0, reg_save_size;
4447 int complex_prologue = 0;
4448
4449 cfun->machine->is_leaf = m32c_leaf_function_p ();
4450 if (interrupt_p (cfun->decl))
4451 {
4452 cfun->machine->is_interrupt = 1;
4453 complex_prologue = 1;
4454 }
65655f79
DD		 4455 else if (bank_switch_p (cfun->decl))
4456 warning (OPT_Wattributes,
4457 "%<bank_switch%> has no effect on non-interrupt functions");
38b2d076
DD		 4458
4459 reg_save_size = m32c_pushm_popm (PP_justcount);
4460
4461 if (interrupt_p (cfun->decl))
65655f79
DD		 4462 {
4463 if (bank_switch_p (cfun->decl))
4464 emit_insn (gen_fset_b ());
4465 else if (cfun->machine->intr_pushm)
4466 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
4467 }
38b2d076
DD		 4468
4469 frame_size =
4470 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
4471 if (frame_size == 0
38b2d076
DD		 4472 && !m32c_function_needs_enter ())
4473 cfun->machine->use_rts = 1;
4474
4475 if (frame_size > 254)
4476 {
4477 extra_frame_size = frame_size - 254;
4478 frame_size = 254;
4479 }
4480 if (cfun->machine->use_rts == 0)
4481 F (emit_insn (m32c_all_frame_related
4482 (TARGET_A16
fa9fd28a
RIL		 4483 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
4484 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
38b2d076
DD		 4485
4486 if (extra_frame_size)
4487 {
4488 complex_prologue = 1;
4489 if (TARGET_A16)
4490 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
4491 gen_rtx_REG (HImode, SP_REGNO),
4492 GEN_INT (-extra_frame_size))));
4493 else
4494 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
4495 gen_rtx_REG (PSImode, SP_REGNO),
4496 GEN_INT (-extra_frame_size))));
4497 }
4498
4499 complex_prologue += m32c_pushm_popm (PP_pushm);
4500
4501 /* This just emits a comment into the .s file for debugging. */
4502 if (complex_prologue)
4503 emit_insn (gen_prologue_end ());
4504}
4505
4506/* Likewise, for the epilogue. The only exception is that, for
4507 interrupts, we must manually unwind the frame as the REIT opcode
4508 doesn't do that. */
4509void
4510m32c_emit_epilogue (void)
4511{
4512 /* This just emits a comment into the .s file for debugging. */
4513 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4514 emit_insn (gen_epilogue_start ());
4515
4516 m32c_pushm_popm (PP_popm);
4517
4518 if (cfun->machine->is_interrupt)
4519 {
4520 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4521
65655f79
DD		 4522 /* REIT clears B flag and restores $fp for us, but we still
4523 have to fix up the stack. USE_RTS just means we didn't
4524 emit ENTER. */
4525 if (!cfun->machine->use_rts)
4526 {
4527 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4528 gen_rtx_REG (spmode, FP_REGNO));
4529 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4530 gen_rtx_REG (spmode, A0_REGNO));
4531 /* We can't just add this to the POPM because it would be in
4532 the wrong order, and wouldn't fix the stack if we're bank
4533 switching. */
4534 if (TARGET_A16)
4535 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4536 else
4537 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4538 }
4539 if (!bank_switch_p (cfun->decl) && cfun->machine->intr_pushm)
4540 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4541
402f2db8
DD		 4542 /* The FREIT (Fast REturn from InTerrupt) instruction should be
4543 generated only for M32C/M32CM targets (generate the REIT
4544 instruction otherwise). */
65655f79 4545 if (fast_interrupt_p (cfun->decl))
402f2db8
DD		 4546 {
4547 /* Check if fast_attribute is set for M32C or M32CM. */
4548 if (TARGET_A24)
4549 {
4550 emit_jump_insn (gen_epilogue_freit ());
4551 }
4552 /* If fast_interrupt attribute is set for an R8C or M16C
4553 target ignore this attribute and generated REIT
4554 instruction. */
4555 else
4556 {
4557 warning (OPT_Wattributes,
4558 "%<fast_interrupt%> attribute directive ignored");
4559 emit_jump_insn (gen_epilogue_reit_16 ());
4560 }
4561 }
65655f79 4562 else if (TARGET_A16)
0e0642aa
RIL		 4563 emit_jump_insn (gen_epilogue_reit_16 ());
4564 else
4565 emit_jump_insn (gen_epilogue_reit_24 ());
38b2d076
DD		 4566 }
4567 else if (cfun->machine->use_rts)
4568 emit_jump_insn (gen_epilogue_rts ());
0e0642aa
RIL		 4569 else if (TARGET_A16)
4570 emit_jump_insn (gen_epilogue_exitd_16 ());
38b2d076 4571 else
0e0642aa 4572 emit_jump_insn (gen_epilogue_exitd_24 ());
38b2d076
DD		 4573 emit_barrier ();
4574}
4575
4576void
4577m32c_emit_eh_epilogue (rtx ret_addr)
4578{
4579 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4580 return to. We have to fudge the stack, pop everything, pop SP
4581 (fudged), and return (fudged). This is actually easier to do in
4582 assembler, so punt to libgcc. */
4583 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
c41c1387 4584 /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */
38b2d076
DD		 4585 emit_barrier ();
4586}
4587
16659fcf
DD		 4588/* Indicate which flags must be properly set for a given conditional. */
4589static int
4590flags_needed_for_conditional (rtx cond)
4591{
4592 switch (GET_CODE (cond))
4593 {
4594 case LE:
4595 case GT:
4596 return FLAGS_OSZ;
4597 case LEU:
4598 case GTU:
4599 return FLAGS_ZC;
4600 case LT:
4601 case GE:
4602 return FLAGS_OS;
4603 case LTU:
4604 case GEU:
4605 return FLAGS_C;
4606 case EQ:
4607 case NE:
4608 return FLAGS_Z;
4609 default:
4610 return FLAGS_N;
4611 }
4612}
4613
4614#define DEBUG_CMP 0
4615
4616/* Returns true if a compare insn is redundant because it would only
4617 set flags that are already set correctly. */
4618static bool
4619m32c_compare_redundant (rtx cmp, rtx *operands)
4620{
4621 int flags_needed;
4622 int pflags;
4623 rtx prev, pp, next;
444d6efe 4624 rtx op0, op1;
16659fcf
DD		 4625#if DEBUG_CMP
4626 int prev_icode, i;
4627#endif
4628
4629 op0 = operands[0];
4630 op1 = operands[1];
16659fcf
DD		 4631
4632#if DEBUG_CMP
4633 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4634 debug_rtx(cmp);
4635 for (i=0; i<2; i++)
4636 {
4637 fprintf(stderr, "operands[%d] = ", i);
4638 debug_rtx(operands[i]);
4639 }
4640#endif
4641
4642 next = next_nonnote_insn (cmp);
4643 if (!next || !INSN_P (next))
4644 {
4645#if DEBUG_CMP
4646 fprintf(stderr, "compare not followed by insn\n");
4647 debug_rtx(next);
4648#endif
4649 return false;
4650 }
4651 if (GET_CODE (PATTERN (next)) == SET
4652 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4653 {
4654 next = XEXP (XEXP (PATTERN (next), 1), 0);
4655 }
4656 else if (GET_CODE (PATTERN (next)) == SET)
4657 {
4658 /* If this is a conditional, flags_needed will be something
4659 other than FLAGS_N, which we test below. */
4660 next = XEXP (PATTERN (next), 1);
4661 }
4662 else
4663 {
4664#if DEBUG_CMP
4665 fprintf(stderr, "compare not followed by conditional\n");
4666 debug_rtx(next);
4667#endif
4668 return false;
4669 }
4670#if DEBUG_CMP
4671 fprintf(stderr, "conditional is: ");
4672 debug_rtx(next);
4673#endif
4674
4675 flags_needed = flags_needed_for_conditional (next);
4676 if (flags_needed == FLAGS_N)
4677 {
4678#if DEBUG_CMP
4679 fprintf(stderr, "compare not followed by conditional\n");
4680 debug_rtx(next);
4681#endif
4682 return false;
4683 }
4684
4685 /* Compare doesn't set overflow and carry the same way that
4686 arithmetic instructions do, so we can't replace those. */
4687 if (flags_needed & FLAGS_OC)
4688 return false;
4689
4690 prev = cmp;
4691 do {
4692 prev = prev_nonnote_insn (prev);
4693 if (!prev)
4694 {
4695#if DEBUG_CMP
4696 fprintf(stderr, "No previous insn.\n");
4697#endif
4698 return false;
4699 }
4700 if (!INSN_P (prev))
4701 {
4702#if DEBUG_CMP
4703 fprintf(stderr, "Previous insn is a non-insn.\n");
4704#endif
4705 return false;
4706 }
4707 pp = PATTERN (prev);
4708 if (GET_CODE (pp) != SET)
4709 {
4710#if DEBUG_CMP
4711 fprintf(stderr, "Previous insn is not a SET.\n");
4712#endif
4713 return false;
4714 }
4715 pflags = get_attr_flags (prev);
4716
4717 /* Looking up attributes of previous insns corrupted the recog
4718 tables. */
4719 INSN_UID (cmp) = -1;
4720 recog (PATTERN (cmp), cmp, 0);
4721
4722 if (pflags == FLAGS_N
4723 && reg_mentioned_p (op0, pp))
4724 {
4725#if DEBUG_CMP
4726 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4727 debug_rtx(prev);
4728#endif
4729 return false;
4730 }
b3c5a409
DD		 4731
4732 /* Check for comparisons against memory - between volatiles and
4733 aliases, we just can't risk this one. */
4734 if (GET_CODE (operands[0]) == MEM
4735 || GET_CODE (operands[0]) == MEM)
4736 {
4737#if DEBUG_CMP
4738 fprintf(stderr, "comparisons with memory:\n");
4739 debug_rtx(prev);
4740#endif
4741 return false;
4742 }
4743
4744 /* Check for PREV changing a register that's used to compute a
4745 value in CMP, even if it doesn't otherwise change flags. */
4746 if (GET_CODE (operands[0]) == REG
4747 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
4748 {
4749#if DEBUG_CMP
4750 fprintf(stderr, "sub-value affected, op0:\n");
4751 debug_rtx(prev);
4752#endif
4753 return false;
4754 }
4755 if (GET_CODE (operands[1]) == REG
4756 && rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
4757 {
4758#if DEBUG_CMP
4759 fprintf(stderr, "sub-value affected, op1:\n");
4760 debug_rtx(prev);
4761#endif
4762 return false;
4763 }
4764
16659fcf
DD		 4765 } while (pflags == FLAGS_N);
4766#if DEBUG_CMP
4767 fprintf(stderr, "previous flag-setting insn:\n");
4768 debug_rtx(prev);
4769 debug_rtx(pp);
4770#endif
4771
4772 if (GET_CODE (pp) == SET
4773 && GET_CODE (XEXP (pp, 0)) == REG
4774 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4775 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4776 {
4777 /* Adjacent cbranches must have the same operands to be
4778 redundant. */
4779 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4780 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4781#if DEBUG_CMP
4782 fprintf(stderr, "adjacent cbranches\n");
4783 debug_rtx(pop0);
4784 debug_rtx(pop1);
4785#endif
4786 if (rtx_equal_p (op0, pop0)
4787 && rtx_equal_p (op1, pop1))
4788 return true;
4789#if DEBUG_CMP
4790 fprintf(stderr, "prev cmp not same\n");
4791#endif
4792 return false;
4793 }
4794
4795 /* Else the previous insn must be a SET, with either the source or
4796 dest equal to operands[0], and operands[1] must be zero. */
4797
4798 if (!rtx_equal_p (op1, const0_rtx))
4799 {
4800#if DEBUG_CMP
4801 fprintf(stderr, "operands[1] not const0_rtx\n");
4802#endif
4803 return false;
4804 }
4805 if (GET_CODE (pp) != SET)
4806 {
4807#if DEBUG_CMP
4808 fprintf (stderr, "pp not set\n");
4809#endif
4810 return false;
4811 }
4812 if (!rtx_equal_p (op0, SET_SRC (pp))
4813 && !rtx_equal_p (op0, SET_DEST (pp)))
4814 {
4815#if DEBUG_CMP
4816 fprintf(stderr, "operands[0] not found in set\n");
4817#endif
4818 return false;
4819 }
4820
4821#if DEBUG_CMP
4822 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4823#endif
4824 if ((pflags & flags_needed) == flags_needed)
4825 return true;
4826
4827 return false;
4828}
4829
4830/* Return the pattern for a compare. This will be commented out if
4831 the compare is redundant, else a normal pattern is returned. Thus,
4832 the assembler output says where the compare would have been. */
4833char *
4834m32c_output_compare (rtx insn, rtx *operands)
4835{
0a2aaacc 4836 static char templ[] = ";cmp.b\t%1,%0";
16659fcf
DD		 4837 /* ^ 5 */
4838
0a2aaacc 4839 templ[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
16659fcf
DD		 4840 if (m32c_compare_redundant (insn, operands))
4841 {
4842#if DEBUG_CMP
4843 fprintf(stderr, "cbranch: cmp not needed\n");
4844#endif
0a2aaacc 4845 return templ;
16659fcf
DD		 4846 }
4847
4848#if DEBUG_CMP
b3c5a409 4849 fprintf(stderr, "cbranch: cmp needed: `%s'\n", templ + 1);
16659fcf 4850#endif
0a2aaacc 4851 return templ + 1;
16659fcf
DD		 4852}
4853
5abd2125
JS		 4854#undef TARGET_ENCODE_SECTION_INFO
4855#define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4856
b52b1749
AS		 4857/* If the frame pointer isn't used, we detect it manually. But the
4858 stack pointer doesn't have as flexible addressing as the frame
4859 pointer, so we always assume we have it. */
4860
4861#undef TARGET_FRAME_POINTER_REQUIRED
4862#define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
4863
38b2d076
DD		 4864/* The Global `targetm' Variable. */
4865
4866struct gcc_target targetm = TARGET_INITIALIZER;
4867
4868#include "gt-m32c.h"
Mirror of https://gcc.gnu.org/git/gcc.git